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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_util.h"
29 #include "tgsi/tgsi_dump.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_llvm_util.h"
34 #include "si_shader_internal.h"
35 #include "si_pipe.h"
36 #include "sid.h"
37
38 #include "compiler/nir/nir.h"
39
40 static const char *scratch_rsrc_dword0_symbol =
41 "SCRATCH_RSRC_DWORD0";
42
43 static const char *scratch_rsrc_dword1_symbol =
44 "SCRATCH_RSRC_DWORD1";
45
46 struct si_shader_output_values
47 {
48 LLVMValueRef values[4];
49 unsigned semantic_name;
50 unsigned semantic_index;
51 ubyte vertex_stream[4];
52 };
53
54 /**
55 * Used to collect types and other info about arguments of the LLVM function
56 * before the function is created.
57 */
58 struct si_function_info {
59 LLVMTypeRef types[100];
60 LLVMValueRef *assign[100];
61 unsigned num_sgpr_params;
62 unsigned num_params;
63 };
64
65 enum si_arg_regfile {
66 ARG_SGPR,
67 ARG_VGPR
68 };
69
70 static void si_init_shader_ctx(struct si_shader_context *ctx,
71 struct si_screen *sscreen,
72 struct ac_llvm_compiler *compiler);
73
74 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
75 struct lp_build_tgsi_context *bld_base,
76 struct lp_build_emit_data *emit_data);
77
78 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
79 FILE *f);
80
81 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89 static void si_fix_resource_usage(struct si_screen *sscreen,
90 struct si_shader *shader);
91
92 /* Ideally pass the sample mask input to the PS epilog as v14, which
93 * is its usual location, so that the shader doesn't have to add v_mov.
94 */
95 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
96
97 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
98 LLVMTypeRef type)
99 {
100 if (type == ctx->ac.i64 || type == ctx->ac.f64)
101 return true;
102
103 return false;
104 }
105
106 static bool is_merged_shader(struct si_shader_context *ctx)
107 {
108 if (ctx->screen->info.chip_class <= VI)
109 return false;
110
111 return ctx->shader->key.as_ls ||
112 ctx->shader->key.as_es ||
113 ctx->type == PIPE_SHADER_TESS_CTRL ||
114 ctx->type == PIPE_SHADER_GEOMETRY;
115 }
116
117 static void si_init_function_info(struct si_function_info *fninfo)
118 {
119 fninfo->num_params = 0;
120 fninfo->num_sgpr_params = 0;
121 }
122
123 static unsigned add_arg_assign(struct si_function_info *fninfo,
124 enum si_arg_regfile regfile, LLVMTypeRef type,
125 LLVMValueRef *assign)
126 {
127 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
128
129 unsigned idx = fninfo->num_params++;
130 assert(idx < ARRAY_SIZE(fninfo->types));
131
132 if (regfile == ARG_SGPR)
133 fninfo->num_sgpr_params = fninfo->num_params;
134
135 fninfo->types[idx] = type;
136 fninfo->assign[idx] = assign;
137 return idx;
138 }
139
140 static unsigned add_arg(struct si_function_info *fninfo,
141 enum si_arg_regfile regfile, LLVMTypeRef type)
142 {
143 return add_arg_assign(fninfo, regfile, type, NULL);
144 }
145
146 static void add_arg_assign_checked(struct si_function_info *fninfo,
147 enum si_arg_regfile regfile, LLVMTypeRef type,
148 LLVMValueRef *assign, unsigned idx)
149 {
150 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
151 assert(actual == idx);
152 }
153
154 static void add_arg_checked(struct si_function_info *fninfo,
155 enum si_arg_regfile regfile, LLVMTypeRef type,
156 unsigned idx)
157 {
158 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
189 unsigned is_varying)
190 {
191 switch (semantic_name) {
192 case TGSI_SEMANTIC_POSITION:
193 return 0;
194 case TGSI_SEMANTIC_GENERIC:
195 /* Since some shader stages use the the highest used IO index
196 * to determine the size to allocate for inputs/outputs
197 * (in LDS, tess and GS rings). GENERIC should be placed right
198 * after POSITION to make that size as small as possible.
199 */
200 if (index < SI_MAX_IO_GENERIC)
201 return 1 + index;
202
203 assert(!"invalid generic index");
204 return 0;
205 case TGSI_SEMANTIC_PSIZE:
206 return SI_MAX_IO_GENERIC + 1;
207 case TGSI_SEMANTIC_CLIPDIST:
208 assert(index <= 1);
209 return SI_MAX_IO_GENERIC + 2 + index;
210 case TGSI_SEMANTIC_FOG:
211 return SI_MAX_IO_GENERIC + 4;
212 case TGSI_SEMANTIC_LAYER:
213 return SI_MAX_IO_GENERIC + 5;
214 case TGSI_SEMANTIC_VIEWPORT_INDEX:
215 return SI_MAX_IO_GENERIC + 6;
216 case TGSI_SEMANTIC_PRIMID:
217 return SI_MAX_IO_GENERIC + 7;
218 case TGSI_SEMANTIC_COLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_BCOLOR:
222 assert(index < 2);
223 /* If it's a varying, COLOR and BCOLOR alias. */
224 if (is_varying)
225 return SI_MAX_IO_GENERIC + 8 + index;
226 else
227 return SI_MAX_IO_GENERIC + 10 + index;
228 case TGSI_SEMANTIC_TEXCOORD:
229 assert(index < 8);
230 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
231 return SI_MAX_IO_GENERIC + 12 + index;
232 case TGSI_SEMANTIC_CLIPVERTEX:
233 return 63;
234 default:
235 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
236 assert(!"invalid semantic name");
237 return 0;
238 }
239 }
240
241 /**
242 * Get the value of a shader input parameter and extract a bitfield.
243 */
244 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
245 LLVMValueRef value, unsigned rshift,
246 unsigned bitwidth)
247 {
248 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
249 value = ac_to_integer(&ctx->ac, value);
250
251 if (rshift)
252 value = LLVMBuildLShr(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, rshift, 0), "");
254
255 if (rshift + bitwidth < 32) {
256 unsigned mask = (1 << bitwidth) - 1;
257 value = LLVMBuildAnd(ctx->ac.builder, value,
258 LLVMConstInt(ctx->i32, mask, 0), "");
259 }
260
261 return value;
262 }
263
264 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
265 unsigned param, unsigned rshift,
266 unsigned bitwidth)
267 {
268 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
269
270 return unpack_llvm_param(ctx, value, rshift, bitwidth);
271 }
272
273 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
274 {
275 switch (ctx->type) {
276 case PIPE_SHADER_TESS_CTRL:
277 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
278
279 case PIPE_SHADER_TESS_EVAL:
280 return LLVMGetParam(ctx->main_fn,
281 ctx->param_tes_rel_patch_id);
282
283 default:
284 assert(0);
285 return NULL;
286 }
287 }
288
289 /* Tessellation shaders pass outputs to the next shader using LDS.
290 *
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
293 *
294 * The LDS layout is:
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
298 * - ...
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * - ...
306 *
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
308 */
309
310 static LLVMValueRef
311 get_tcs_in_patch_stride(struct si_shader_context *ctx)
312 {
313 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
314 }
315
316 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
317 {
318 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
319
320 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
321 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
322
323 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
324 }
325
326 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
327 {
328 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
329
330 return LLVMConstInt(ctx->i32, stride, 0);
331 }
332
333 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
334 {
335 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
336 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
337
338 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
339 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
340 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
341 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
342 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
343 num_patch_outputs * 4;
344 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
349 {
350 return LLVMBuildMul(ctx->ac.builder,
351 si_unpack_param(ctx,
352 ctx->param_tcs_out_lds_offsets,
353 0, 16),
354 LLVMConstInt(ctx->i32, 4, 0), "");
355 }
356
357 static LLVMValueRef
358 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
359 {
360 return LLVMBuildMul(ctx->ac.builder,
361 si_unpack_param(ctx,
362 ctx->param_tcs_out_lds_offsets,
363 16, 16),
364 LLVMConstInt(ctx->i32, 4, 0), "");
365 }
366
367 static LLVMValueRef
368 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
369 {
370 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
371 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
372
373 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
374 }
375
376 static LLVMValueRef
377 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
378 {
379 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
380 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
381 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
382
383 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
388 {
389 LLVMValueRef patch0_patch_data_offset =
390 get_tcs_out_patch0_patch_data_offset(ctx);
391 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
392 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
393
394 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
395 }
396
397 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
398 {
399 unsigned tcs_out_vertices =
400 ctx->shader->selector ?
401 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
402
403 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
404 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
405 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
406
407 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
408 }
409
410 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
411 {
412 unsigned stride;
413
414 switch (ctx->type) {
415 case PIPE_SHADER_VERTEX:
416 stride = ctx->shader->selector->lshs_vertex_stride / 4;
417 return LLVMConstInt(ctx->i32, stride, 0);
418
419 case PIPE_SHADER_TESS_CTRL:
420 if (ctx->screen->info.chip_class >= GFX9 &&
421 ctx->shader->is_monolithic) {
422 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
423 return LLVMConstInt(ctx->i32, stride, 0);
424 }
425 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
426
427 default:
428 assert(0);
429 return NULL;
430 }
431 }
432
433 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
434 * to float. */
435 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
436 LLVMValueRef vec4,
437 unsigned double_index)
438 {
439 LLVMBuilderRef builder = ctx->ac.builder;
440 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
441 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
442 LLVMVectorType(f64, 2), "");
443 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
444 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
445 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
446 }
447
448 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
449 LLVMValueRef i32, unsigned index)
450 {
451 assert(index <= 1);
452
453 if (index == 1)
454 return LLVMBuildAShr(ctx->ac.builder, i32,
455 LLVMConstInt(ctx->i32, 16, 0), "");
456
457 return LLVMBuildSExt(ctx->ac.builder,
458 LLVMBuildTrunc(ctx->ac.builder, i32,
459 ctx->ac.i16, ""),
460 ctx->i32, "");
461 }
462
463 void si_llvm_load_input_vs(
464 struct si_shader_context *ctx,
465 unsigned input_index,
466 LLVMValueRef out[4])
467 {
468 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
469 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
470
471 if (vs_blit_property) {
472 LLVMValueRef vertex_id = ctx->abi.vertex_id;
473 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
474 LLVMIntULE, vertex_id,
475 ctx->i32_1, "");
476 /* Use LLVMIntNE, because we have 3 vertices and only
477 * the middle one should use y2.
478 */
479 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
480 LLVMIntNE, vertex_id,
481 ctx->i32_1, "");
482
483 if (input_index == 0) {
484 /* Position: */
485 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_blit_inputs);
487 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
488 ctx->param_vs_blit_inputs + 1);
489
490 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
491 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
492 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
493 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
494
495 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
496 x1, x2, "");
497 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
498 y1, y2, "");
499
500 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
501 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
502 out[2] = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 2);
504 out[3] = ctx->ac.f32_1;
505 return;
506 }
507
508 /* Color or texture coordinates: */
509 assert(input_index == 1);
510
511 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
512 for (int i = 0; i < 4; i++) {
513 out[i] = LLVMGetParam(ctx->main_fn,
514 ctx->param_vs_blit_inputs + 3 + i);
515 }
516 } else {
517 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
518 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
519 ctx->param_vs_blit_inputs + 3);
520 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
521 ctx->param_vs_blit_inputs + 4);
522 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 5);
524 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
525 ctx->param_vs_blit_inputs + 6);
526
527 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
528 x1, x2, "");
529 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
530 y1, y2, "");
531 out[2] = LLVMGetParam(ctx->main_fn,
532 ctx->param_vs_blit_inputs + 7);
533 out[3] = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 8);
535 }
536 return;
537 }
538
539 unsigned chan;
540 unsigned fix_fetch;
541 unsigned num_fetches;
542 unsigned fetch_stride;
543 unsigned num_channels;
544
545 LLVMValueRef t_list_ptr;
546 LLVMValueRef t_offset;
547 LLVMValueRef t_list;
548 LLVMValueRef vertex_index;
549 LLVMValueRef input[3];
550
551 /* Load the T list */
552 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
553
554 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
555
556 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
557
558 vertex_index = LLVMGetParam(ctx->main_fn,
559 ctx->param_vertex_index0 +
560 input_index);
561
562 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
563
564 /* Do multiple loads for special formats. */
565 switch (fix_fetch) {
566 case SI_FIX_FETCH_RG_64_FLOAT:
567 num_fetches = 1; /* 1 2-dword or 4-dword load */
568 fetch_stride = 0;
569 if (util_last_bit(info->input_usage_mask[input_index]) >= 2)
570 num_channels = 4; /* 2 doubles in 4 dwords */
571 else
572 num_channels = 2; /* 1 double in 2 dwords */
573 break;
574 case SI_FIX_FETCH_RGB_64_FLOAT:
575 num_fetches = 3; /* 3 2-dword loads */
576 fetch_stride = 8;
577 num_channels = 2;
578 break;
579 case SI_FIX_FETCH_RGBA_64_FLOAT:
580 num_fetches = 2; /* 2 4-dword loads */
581 fetch_stride = 16;
582 num_channels = 4;
583 break;
584 case SI_FIX_FETCH_RGB_8:
585 case SI_FIX_FETCH_RGB_8_INT:
586 num_fetches = 3;
587 fetch_stride = 1;
588 num_channels = 1;
589 break;
590 case SI_FIX_FETCH_RGB_16:
591 case SI_FIX_FETCH_RGB_16_INT:
592 num_fetches = 3;
593 fetch_stride = 2;
594 num_channels = 1;
595 break;
596 default:
597 num_fetches = 1;
598 fetch_stride = 0;
599 num_channels = util_last_bit(info->input_usage_mask[input_index]);
600 }
601
602 for (unsigned i = 0; i < num_fetches; i++) {
603 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
604
605 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
606 vertex_index, voffset,
607 num_channels, false, true);
608 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
609 }
610
611 /* Break up the vec4 into individual components */
612 for (chan = 0; chan < 4; chan++) {
613 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
614 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
615 input[0], llvm_chan, "");
616 }
617
618 switch (fix_fetch) {
619 case SI_FIX_FETCH_A2_SNORM:
620 case SI_FIX_FETCH_A2_SSCALED:
621 case SI_FIX_FETCH_A2_SINT: {
622 /* The hardware returns an unsigned value; convert it to a
623 * signed one.
624 */
625 LLVMValueRef tmp = out[3];
626 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
627
628 /* First, recover the sign-extended signed integer value. */
629 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
630 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
631 else
632 tmp = ac_to_integer(&ctx->ac, tmp);
633
634 /* For the integer-like cases, do a natural sign extension.
635 *
636 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
637 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
638 * exponent.
639 */
640 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
641 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
642 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
643 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
644
645 /* Convert back to the right type. */
646 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
647 LLVMValueRef clamp;
648 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
649 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
650 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
651 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
652 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
653 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
654 }
655
656 out[3] = tmp;
657 break;
658 }
659 case SI_FIX_FETCH_RGBA_32_UNORM:
660 case SI_FIX_FETCH_RGBX_32_UNORM:
661 for (chan = 0; chan < 4; chan++) {
662 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
663 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
664 out[chan], ctx->f32, "");
665 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
666 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
667 }
668 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
669 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
670 out[3] = LLVMConstReal(ctx->f32, 1);
671 break;
672 case SI_FIX_FETCH_RGBA_32_SNORM:
673 case SI_FIX_FETCH_RGBX_32_SNORM:
674 case SI_FIX_FETCH_RGBA_32_FIXED:
675 case SI_FIX_FETCH_RGBX_32_FIXED: {
676 double scale;
677 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
678 scale = 1.0 / 0x10000;
679 else
680 scale = 1.0 / INT_MAX;
681
682 for (chan = 0; chan < 4; chan++) {
683 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
684 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
685 out[chan], ctx->f32, "");
686 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
687 LLVMConstReal(ctx->f32, scale), "");
688 }
689 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
690 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
691 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
692 out[3] = LLVMConstReal(ctx->f32, 1);
693 break;
694 }
695 case SI_FIX_FETCH_RGBA_32_USCALED:
696 for (chan = 0; chan < 4; chan++) {
697 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
698 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
699 out[chan], ctx->f32, "");
700 }
701 break;
702 case SI_FIX_FETCH_RGBA_32_SSCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RG_64_FLOAT:
710 for (chan = 0; chan < 2; chan++)
711 out[chan] = extract_double_to_float(ctx, input[0], chan);
712
713 out[2] = LLVMConstReal(ctx->f32, 0);
714 out[3] = LLVMConstReal(ctx->f32, 1);
715 break;
716 case SI_FIX_FETCH_RGB_64_FLOAT:
717 for (chan = 0; chan < 3; chan++)
718 out[chan] = extract_double_to_float(ctx, input[chan], 0);
719
720 out[3] = LLVMConstReal(ctx->f32, 1);
721 break;
722 case SI_FIX_FETCH_RGBA_64_FLOAT:
723 for (chan = 0; chan < 4; chan++) {
724 out[chan] = extract_double_to_float(ctx, input[chan / 2],
725 chan % 2);
726 }
727 break;
728 case SI_FIX_FETCH_RGB_8:
729 case SI_FIX_FETCH_RGB_8_INT:
730 case SI_FIX_FETCH_RGB_16:
731 case SI_FIX_FETCH_RGB_16_INT:
732 for (chan = 0; chan < 3; chan++) {
733 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
734 input[chan],
735 ctx->i32_0, "");
736 }
737 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
738 fix_fetch == SI_FIX_FETCH_RGB_16) {
739 out[3] = LLVMConstReal(ctx->f32, 1);
740 } else {
741 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
742 }
743 break;
744 }
745 }
746
747 static void declare_input_vs(
748 struct si_shader_context *ctx,
749 unsigned input_index,
750 const struct tgsi_full_declaration *decl,
751 LLVMValueRef out[4])
752 {
753 si_llvm_load_input_vs(ctx, input_index, out);
754 }
755
756 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
757 unsigned swizzle)
758 {
759 if (swizzle > 0)
760 return ctx->i32_0;
761
762 switch (ctx->type) {
763 case PIPE_SHADER_VERTEX:
764 return LLVMGetParam(ctx->main_fn,
765 ctx->param_vs_prim_id);
766 case PIPE_SHADER_TESS_CTRL:
767 return ctx->abi.tcs_patch_id;
768 case PIPE_SHADER_TESS_EVAL:
769 return ctx->abi.tes_patch_id;
770 case PIPE_SHADER_GEOMETRY:
771 return ctx->abi.gs_prim_id;
772 default:
773 assert(0);
774 return ctx->i32_0;
775 }
776 }
777
778 /**
779 * Return the value of tgsi_ind_register for indexing.
780 * This is the indirect index with the constant offset added to it.
781 */
782 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
783 const struct tgsi_ind_register *ind,
784 unsigned addr_mul,
785 int rel_index)
786 {
787 LLVMValueRef result;
788
789 if (ind->File == TGSI_FILE_ADDRESS) {
790 result = ctx->addrs[ind->Index][ind->Swizzle];
791 result = LLVMBuildLoad(ctx->ac.builder, result, "");
792 } else {
793 struct tgsi_full_src_register src = {};
794
795 src.Register.File = ind->File;
796 src.Register.Index = ind->Index;
797
798 /* Set the second index to 0 for constants. */
799 if (ind->File == TGSI_FILE_CONSTANT)
800 src.Register.Dimension = 1;
801
802 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
803 TGSI_TYPE_SIGNED,
804 ind->Swizzle);
805 result = ac_to_integer(&ctx->ac, result);
806 }
807
808 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
809 LLVMConstInt(ctx->i32, rel_index, 0));
810 }
811
812 /**
813 * Like si_get_indirect_index, but restricts the return value to a (possibly
814 * undefined) value inside [0..num).
815 */
816 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
817 const struct tgsi_ind_register *ind,
818 int rel_index, unsigned num)
819 {
820 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
821
822 return si_llvm_bound_index(ctx, result, num);
823 }
824
825 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
826 LLVMValueRef vertex_dw_stride,
827 LLVMValueRef base_addr,
828 LLVMValueRef vertex_index,
829 LLVMValueRef param_index,
830 unsigned input_index,
831 ubyte *name,
832 ubyte *index,
833 bool is_patch)
834 {
835 if (vertex_dw_stride) {
836 base_addr = ac_build_imad(&ctx->ac, vertex_index,
837 vertex_dw_stride, base_addr);
838 }
839
840 if (param_index) {
841 base_addr = ac_build_imad(&ctx->ac, param_index,
842 LLVMConstInt(ctx->i32, 4, 0), base_addr);
843 }
844
845 int param = is_patch ?
846 si_shader_io_get_unique_index_patch(name[input_index],
847 index[input_index]) :
848 si_shader_io_get_unique_index(name[input_index],
849 index[input_index], false);
850
851 /* Add the base address of the element. */
852 return LLVMBuildAdd(ctx->ac.builder, base_addr,
853 LLVMConstInt(ctx->i32, param * 4, 0), "");
854 }
855
856 /**
857 * Calculate a dword address given an input or output register and a stride.
858 */
859 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
860 const struct tgsi_full_dst_register *dst,
861 const struct tgsi_full_src_register *src,
862 LLVMValueRef vertex_dw_stride,
863 LLVMValueRef base_addr)
864 {
865 struct tgsi_shader_info *info = &ctx->shader->selector->info;
866 ubyte *name, *index, *array_first;
867 int input_index;
868 struct tgsi_full_dst_register reg;
869 LLVMValueRef vertex_index = NULL;
870 LLVMValueRef ind_index = NULL;
871
872 /* Set the register description. The address computation is the same
873 * for sources and destinations. */
874 if (src) {
875 reg.Register.File = src->Register.File;
876 reg.Register.Index = src->Register.Index;
877 reg.Register.Indirect = src->Register.Indirect;
878 reg.Register.Dimension = src->Register.Dimension;
879 reg.Indirect = src->Indirect;
880 reg.Dimension = src->Dimension;
881 reg.DimIndirect = src->DimIndirect;
882 } else
883 reg = *dst;
884
885 /* If the register is 2-dimensional (e.g. an array of vertices
886 * in a primitive), calculate the base address of the vertex. */
887 if (reg.Register.Dimension) {
888 if (reg.Dimension.Indirect)
889 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
890 1, reg.Dimension.Index);
891 else
892 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
893 }
894
895 /* Get information about the register. */
896 if (reg.Register.File == TGSI_FILE_INPUT) {
897 name = info->input_semantic_name;
898 index = info->input_semantic_index;
899 array_first = info->input_array_first;
900 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
901 name = info->output_semantic_name;
902 index = info->output_semantic_index;
903 array_first = info->output_array_first;
904 } else {
905 assert(0);
906 return NULL;
907 }
908
909 if (reg.Register.Indirect) {
910 /* Add the relative address of the element. */
911 if (reg.Indirect.ArrayID)
912 input_index = array_first[reg.Indirect.ArrayID];
913 else
914 input_index = reg.Register.Index;
915
916 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
917 1, reg.Register.Index - input_index);
918 } else {
919 input_index = reg.Register.Index;
920 }
921
922 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
923 base_addr, vertex_index,
924 ind_index, input_index,
925 name, index,
926 !reg.Register.Dimension);
927 }
928
929 /* The offchip buffer layout for TCS->TES is
930 *
931 * - attribute 0 of patch 0 vertex 0
932 * - attribute 0 of patch 0 vertex 1
933 * - attribute 0 of patch 0 vertex 2
934 * ...
935 * - attribute 0 of patch 1 vertex 0
936 * - attribute 0 of patch 1 vertex 1
937 * ...
938 * - attribute 1 of patch 0 vertex 0
939 * - attribute 1 of patch 0 vertex 1
940 * ...
941 * - per patch attribute 0 of patch 0
942 * - per patch attribute 0 of patch 1
943 * ...
944 *
945 * Note that every attribute has 4 components.
946 */
947 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
948 LLVMValueRef rel_patch_id,
949 LLVMValueRef vertex_index,
950 LLVMValueRef param_index)
951 {
952 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
953 LLVMValueRef param_stride, constant16;
954
955 vertices_per_patch = get_num_tcs_out_vertices(ctx);
956 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
957 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
958 num_patches, "");
959
960 constant16 = LLVMConstInt(ctx->i32, 16, 0);
961 if (vertex_index) {
962 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
963 vertices_per_patch, vertex_index);
964 param_stride = total_vertices;
965 } else {
966 base_addr = rel_patch_id;
967 param_stride = num_patches;
968 }
969
970 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
971 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
972
973 if (!vertex_index) {
974 LLVMValueRef patch_data_offset =
975 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
976
977 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
978 patch_data_offset, "");
979 }
980 return base_addr;
981 }
982
983 /* This is a generic helper that can be shared by the NIR and TGSI backends */
984 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
985 struct si_shader_context *ctx,
986 LLVMValueRef vertex_index,
987 LLVMValueRef param_index,
988 unsigned param_base,
989 ubyte *name,
990 ubyte *index,
991 bool is_patch)
992 {
993 unsigned param_index_base;
994
995 param_index_base = is_patch ?
996 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
997 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
998
999 if (param_index) {
1000 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1001 LLVMConstInt(ctx->i32, param_index_base, 0),
1002 "");
1003 } else {
1004 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1005 }
1006
1007 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1008 vertex_index, param_index);
1009 }
1010
1011 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1012 struct si_shader_context *ctx,
1013 const struct tgsi_full_dst_register *dst,
1014 const struct tgsi_full_src_register *src)
1015 {
1016 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1017 ubyte *name, *index, *array_first;
1018 struct tgsi_full_src_register reg;
1019 LLVMValueRef vertex_index = NULL;
1020 LLVMValueRef param_index = NULL;
1021 unsigned param_base;
1022
1023 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1024
1025 if (reg.Register.Dimension) {
1026
1027 if (reg.Dimension.Indirect)
1028 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1029 1, reg.Dimension.Index);
1030 else
1031 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1032 }
1033
1034 /* Get information about the register. */
1035 if (reg.Register.File == TGSI_FILE_INPUT) {
1036 name = info->input_semantic_name;
1037 index = info->input_semantic_index;
1038 array_first = info->input_array_first;
1039 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1040 name = info->output_semantic_name;
1041 index = info->output_semantic_index;
1042 array_first = info->output_array_first;
1043 } else {
1044 assert(0);
1045 return NULL;
1046 }
1047
1048 if (reg.Register.Indirect) {
1049 if (reg.Indirect.ArrayID)
1050 param_base = array_first[reg.Indirect.ArrayID];
1051 else
1052 param_base = reg.Register.Index;
1053
1054 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1055 1, reg.Register.Index - param_base);
1056
1057 } else {
1058 param_base = reg.Register.Index;
1059 }
1060
1061 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1062 param_index, param_base,
1063 name, index, !reg.Register.Dimension);
1064 }
1065
1066 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1067 LLVMTypeRef type, unsigned swizzle,
1068 LLVMValueRef buffer, LLVMValueRef offset,
1069 LLVMValueRef base, bool can_speculate)
1070 {
1071 struct si_shader_context *ctx = si_shader_context(bld_base);
1072 LLVMValueRef value, value2;
1073 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1074
1075 if (swizzle == ~0) {
1076 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1077 0, 1, 0, can_speculate, false);
1078
1079 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1080 }
1081
1082 if (!llvm_type_is_64bit(ctx, type)) {
1083 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1084 0, 1, 0, can_speculate, false);
1085
1086 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1087 return LLVMBuildExtractElement(ctx->ac.builder, value,
1088 LLVMConstInt(ctx->i32, swizzle, 0), "");
1089 }
1090
1091 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1092 swizzle * 4, 1, 0, can_speculate, false);
1093
1094 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1095 swizzle * 4 + 4, 1, 0, can_speculate, false);
1096
1097 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1098 }
1099
1100 /**
1101 * Load from LDS.
1102 *
1103 * \param type output value type
1104 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1105 * \param dw_addr address in dwords
1106 */
1107 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1108 LLVMTypeRef type, unsigned swizzle,
1109 LLVMValueRef dw_addr)
1110 {
1111 struct si_shader_context *ctx = si_shader_context(bld_base);
1112 LLVMValueRef value;
1113
1114 if (swizzle == ~0) {
1115 LLVMValueRef values[TGSI_NUM_CHANNELS];
1116
1117 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1118 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1119
1120 return ac_build_gather_values(&ctx->ac, values,
1121 TGSI_NUM_CHANNELS);
1122 }
1123
1124 /* Split 64-bit loads. */
1125 if (llvm_type_is_64bit(ctx, type)) {
1126 LLVMValueRef lo, hi;
1127
1128 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1129 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1130 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1131 }
1132
1133 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1134 LLVMConstInt(ctx->i32, swizzle, 0), "");
1135
1136 value = ac_lds_load(&ctx->ac, dw_addr);
1137
1138 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1139 }
1140
1141 /**
1142 * Store to LDS.
1143 *
1144 * \param swizzle offset (typically 0..3)
1145 * \param dw_addr address in dwords
1146 * \param value value to store
1147 */
1148 static void lds_store(struct si_shader_context *ctx,
1149 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1150 LLVMValueRef value)
1151 {
1152 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1153 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1154
1155 ac_lds_store(&ctx->ac, dw_addr, value);
1156 }
1157
1158 enum si_tess_ring {
1159 TCS_FACTOR_RING,
1160 TESS_OFFCHIP_RING_TCS,
1161 TESS_OFFCHIP_RING_TES,
1162 };
1163
1164 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1165 enum si_tess_ring ring)
1166 {
1167 LLVMBuilderRef builder = ctx->ac.builder;
1168 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1169 ctx->param_tcs_out_lds_layout;
1170 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1171
1172 /* TCS only receives high 13 bits of the address. */
1173 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1174 addr = LLVMBuildAnd(builder, addr,
1175 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1176 }
1177
1178 if (ring == TCS_FACTOR_RING) {
1179 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1180 addr = LLVMBuildAdd(builder, addr,
1181 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1182 }
1183
1184 LLVMValueRef desc[4];
1185 desc[0] = addr;
1186 desc[1] = LLVMConstInt(ctx->i32,
1187 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1188 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1189 desc[3] = LLVMConstInt(ctx->i32,
1190 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1191 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1192 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1193 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1194 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1196
1197 return ac_build_gather_values(&ctx->ac, desc, 4);
1198 }
1199
1200 static LLVMValueRef fetch_input_tcs(
1201 struct lp_build_tgsi_context *bld_base,
1202 const struct tgsi_full_src_register *reg,
1203 enum tgsi_opcode_type type, unsigned swizzle_in)
1204 {
1205 struct si_shader_context *ctx = si_shader_context(bld_base);
1206 LLVMValueRef dw_addr, stride;
1207 unsigned swizzle = swizzle_in & 0xffff;
1208 stride = get_tcs_in_vertex_dw_stride(ctx);
1209 dw_addr = get_tcs_in_current_patch_offset(ctx);
1210 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1211
1212 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1213 }
1214
1215 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1216 LLVMTypeRef type,
1217 LLVMValueRef vertex_index,
1218 LLVMValueRef param_index,
1219 unsigned const_index,
1220 unsigned location,
1221 unsigned driver_location,
1222 unsigned component,
1223 unsigned num_components,
1224 bool is_patch,
1225 bool is_compact,
1226 bool load_input)
1227 {
1228 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1229 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1230 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1231 LLVMValueRef dw_addr, stride;
1232
1233 driver_location = driver_location / 4;
1234
1235 if (load_input) {
1236 stride = get_tcs_in_vertex_dw_stride(ctx);
1237 dw_addr = get_tcs_in_current_patch_offset(ctx);
1238 } else {
1239 if (is_patch) {
1240 stride = NULL;
1241 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1242 } else {
1243 stride = get_tcs_out_vertex_dw_stride(ctx);
1244 dw_addr = get_tcs_out_current_patch_offset(ctx);
1245 }
1246 }
1247
1248 if (param_index) {
1249 /* Add the constant index to the indirect index */
1250 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1251 LLVMConstInt(ctx->i32, const_index, 0), "");
1252 } else {
1253 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1254 }
1255
1256 ubyte *names;
1257 ubyte *indices;
1258 if (load_input) {
1259 names = info->input_semantic_name;
1260 indices = info->input_semantic_index;
1261 } else {
1262 names = info->output_semantic_name;
1263 indices = info->output_semantic_index;
1264 }
1265
1266 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1267 vertex_index, param_index,
1268 driver_location,
1269 names, indices,
1270 is_patch);
1271
1272 LLVMValueRef value[4];
1273 for (unsigned i = 0; i < num_components; i++) {
1274 unsigned offset = i;
1275 if (llvm_type_is_64bit(ctx, type))
1276 offset *= 2;
1277
1278 offset += component;
1279 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1280 }
1281
1282 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1283 }
1284
1285 static LLVMValueRef fetch_output_tcs(
1286 struct lp_build_tgsi_context *bld_base,
1287 const struct tgsi_full_src_register *reg,
1288 enum tgsi_opcode_type type, unsigned swizzle_in)
1289 {
1290 struct si_shader_context *ctx = si_shader_context(bld_base);
1291 LLVMValueRef dw_addr, stride;
1292 unsigned swizzle = (swizzle_in & 0xffff);
1293
1294 if (reg->Register.Dimension) {
1295 stride = get_tcs_out_vertex_dw_stride(ctx);
1296 dw_addr = get_tcs_out_current_patch_offset(ctx);
1297 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1298 } else {
1299 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1300 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1301 }
1302
1303 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1304 }
1305
1306 static LLVMValueRef fetch_input_tes(
1307 struct lp_build_tgsi_context *bld_base,
1308 const struct tgsi_full_src_register *reg,
1309 enum tgsi_opcode_type type, unsigned swizzle_in)
1310 {
1311 struct si_shader_context *ctx = si_shader_context(bld_base);
1312 LLVMValueRef base, addr;
1313 unsigned swizzle = (swizzle_in & 0xffff);
1314
1315 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1316 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1317
1318 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1319 ctx->tess_offchip_ring, base, addr, true);
1320 }
1321
1322 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1323 LLVMTypeRef type,
1324 LLVMValueRef vertex_index,
1325 LLVMValueRef param_index,
1326 unsigned const_index,
1327 unsigned location,
1328 unsigned driver_location,
1329 unsigned component,
1330 unsigned num_components,
1331 bool is_patch,
1332 bool is_compact,
1333 bool load_input)
1334 {
1335 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1336 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1337 LLVMValueRef base, addr;
1338
1339 driver_location = driver_location / 4;
1340
1341 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1342
1343 if (param_index) {
1344 /* Add the constant index to the indirect index */
1345 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1346 LLVMConstInt(ctx->i32, const_index, 0), "");
1347 } else {
1348 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1349 }
1350
1351 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1352 param_index, driver_location,
1353 info->input_semantic_name,
1354 info->input_semantic_index,
1355 is_patch);
1356
1357 /* TODO: This will generate rather ordinary llvm code, although it
1358 * should be easy for the optimiser to fix up. In future we might want
1359 * to refactor buffer_load(), but for now this maximises code sharing
1360 * between the NIR and TGSI backends.
1361 */
1362 LLVMValueRef value[4];
1363 for (unsigned i = 0; i < num_components; i++) {
1364 unsigned offset = i;
1365 if (llvm_type_is_64bit(ctx, type))
1366 offset *= 2;
1367
1368 offset += component;
1369 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1370 ctx->tess_offchip_ring, base, addr, true);
1371 }
1372
1373 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1374 }
1375
1376 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1377 const struct tgsi_full_instruction *inst,
1378 const struct tgsi_opcode_info *info,
1379 unsigned index,
1380 LLVMValueRef dst[4])
1381 {
1382 struct si_shader_context *ctx = si_shader_context(bld_base);
1383 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1384 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1385 unsigned chan_index;
1386 LLVMValueRef dw_addr, stride;
1387 LLVMValueRef buffer, base, buf_addr;
1388 LLVMValueRef values[4];
1389 bool skip_lds_store;
1390 bool is_tess_factor = false, is_tess_inner = false;
1391
1392 /* Only handle per-patch and per-vertex outputs here.
1393 * Vectors will be lowered to scalars and this function will be called again.
1394 */
1395 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1396 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1397 si_llvm_emit_store(bld_base, inst, info, index, dst);
1398 return;
1399 }
1400
1401 if (reg->Register.Dimension) {
1402 stride = get_tcs_out_vertex_dw_stride(ctx);
1403 dw_addr = get_tcs_out_current_patch_offset(ctx);
1404 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1405 skip_lds_store = !sh_info->reads_pervertex_outputs;
1406 } else {
1407 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1408 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1409 skip_lds_store = !sh_info->reads_perpatch_outputs;
1410
1411 if (!reg->Register.Indirect) {
1412 int name = sh_info->output_semantic_name[reg->Register.Index];
1413
1414 /* Always write tess factors into LDS for the TCS epilog. */
1415 if (name == TGSI_SEMANTIC_TESSINNER ||
1416 name == TGSI_SEMANTIC_TESSOUTER) {
1417 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1418 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1419 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1420 is_tess_factor = true;
1421 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1422 }
1423 }
1424 }
1425
1426 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1427
1428 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1429 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1430
1431 uint32_t writemask = reg->Register.WriteMask;
1432 while (writemask) {
1433 chan_index = u_bit_scan(&writemask);
1434 LLVMValueRef value = dst[chan_index];
1435
1436 if (inst->Instruction.Saturate)
1437 value = ac_build_clamp(&ctx->ac, value);
1438
1439 /* Skip LDS stores if there is no LDS read of this output. */
1440 if (!skip_lds_store)
1441 lds_store(ctx, chan_index, dw_addr, value);
1442
1443 value = ac_to_integer(&ctx->ac, value);
1444 values[chan_index] = value;
1445
1446 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1447 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1448 buf_addr, base,
1449 4 * chan_index, 1, 0, true, false);
1450 }
1451
1452 /* Write tess factors into VGPRs for the epilog. */
1453 if (is_tess_factor &&
1454 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1455 if (!is_tess_inner) {
1456 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1457 ctx->invoc0_tess_factors[chan_index]);
1458 } else if (chan_index < 2) {
1459 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1460 ctx->invoc0_tess_factors[4 + chan_index]);
1461 }
1462 }
1463 }
1464
1465 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1466 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1467 values, 4);
1468 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1469 base, 0, 1, 0, true, false);
1470 }
1471 }
1472
1473 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1474 const struct nir_variable *var,
1475 LLVMValueRef vertex_index,
1476 LLVMValueRef param_index,
1477 unsigned const_index,
1478 LLVMValueRef src,
1479 unsigned writemask)
1480 {
1481 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1482 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1483 const unsigned component = var->data.location_frac;
1484 const bool is_patch = var->data.patch;
1485 unsigned driver_location = var->data.driver_location;
1486 LLVMValueRef dw_addr, stride;
1487 LLVMValueRef buffer, base, addr;
1488 LLVMValueRef values[4];
1489 bool skip_lds_store;
1490 bool is_tess_factor = false, is_tess_inner = false;
1491
1492 driver_location = driver_location / 4;
1493
1494 if (param_index) {
1495 /* Add the constant index to the indirect index */
1496 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1497 LLVMConstInt(ctx->i32, const_index, 0), "");
1498 } else {
1499 if (const_index != 0)
1500 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1501 }
1502
1503 if (!is_patch) {
1504 stride = get_tcs_out_vertex_dw_stride(ctx);
1505 dw_addr = get_tcs_out_current_patch_offset(ctx);
1506 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1507 vertex_index, param_index,
1508 driver_location,
1509 info->output_semantic_name,
1510 info->output_semantic_index,
1511 is_patch);
1512
1513 skip_lds_store = !info->reads_pervertex_outputs;
1514 } else {
1515 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1516 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1517 vertex_index, param_index,
1518 driver_location,
1519 info->output_semantic_name,
1520 info->output_semantic_index,
1521 is_patch);
1522
1523 skip_lds_store = !info->reads_perpatch_outputs;
1524
1525 if (!param_index) {
1526 int name = info->output_semantic_name[driver_location];
1527
1528 /* Always write tess factors into LDS for the TCS epilog. */
1529 if (name == TGSI_SEMANTIC_TESSINNER ||
1530 name == TGSI_SEMANTIC_TESSOUTER) {
1531 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1532 skip_lds_store = !info->reads_tessfactor_outputs &&
1533 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1534 is_tess_factor = true;
1535 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1536 }
1537 }
1538 }
1539
1540 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1541
1542 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1543
1544 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1545 param_index, driver_location,
1546 info->output_semantic_name,
1547 info->output_semantic_index,
1548 is_patch);
1549
1550 for (unsigned chan = 0; chan < 4; chan++) {
1551 if (!(writemask & (1 << chan)))
1552 continue;
1553 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1554
1555 /* Skip LDS stores if there is no LDS read of this output. */
1556 if (!skip_lds_store)
1557 lds_store(ctx, chan, dw_addr, value);
1558
1559 value = ac_to_integer(&ctx->ac, value);
1560 values[chan] = value;
1561
1562 if (writemask != 0xF && !is_tess_factor) {
1563 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1564 addr, base,
1565 4 * chan, 1, 0, true, false);
1566 }
1567
1568 /* Write tess factors into VGPRs for the epilog. */
1569 if (is_tess_factor &&
1570 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1571 if (!is_tess_inner) {
1572 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1573 ctx->invoc0_tess_factors[chan]);
1574 } else if (chan < 2) {
1575 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1576 ctx->invoc0_tess_factors[4 + chan]);
1577 }
1578 }
1579 }
1580
1581 if (writemask == 0xF && !is_tess_factor) {
1582 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1583 values, 4);
1584 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1585 base, 0, 1, 0, true, false);
1586 }
1587 }
1588
1589 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1590 unsigned input_index,
1591 unsigned vtx_offset_param,
1592 LLVMTypeRef type,
1593 unsigned swizzle)
1594 {
1595 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1596 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1597 struct si_shader *shader = ctx->shader;
1598 LLVMValueRef vtx_offset, soffset;
1599 struct tgsi_shader_info *info = &shader->selector->info;
1600 unsigned semantic_name = info->input_semantic_name[input_index];
1601 unsigned semantic_index = info->input_semantic_index[input_index];
1602 unsigned param;
1603 LLVMValueRef value;
1604
1605 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1606
1607 /* GFX9 has the ESGS ring in LDS. */
1608 if (ctx->screen->info.chip_class >= GFX9) {
1609 unsigned index = vtx_offset_param;
1610
1611 switch (index / 2) {
1612 case 0:
1613 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1614 index % 2 ? 16 : 0, 16);
1615 break;
1616 case 1:
1617 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1618 index % 2 ? 16 : 0, 16);
1619 break;
1620 case 2:
1621 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1622 index % 2 ? 16 : 0, 16);
1623 break;
1624 default:
1625 assert(0);
1626 return NULL;
1627 }
1628
1629 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1630 LLVMConstInt(ctx->i32, param * 4, 0), "");
1631 return lds_load(bld_base, type, swizzle, vtx_offset);
1632 }
1633
1634 /* GFX6: input load from the ESGS ring in memory. */
1635 if (swizzle == ~0) {
1636 LLVMValueRef values[TGSI_NUM_CHANNELS];
1637 unsigned chan;
1638 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1639 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1640 type, chan);
1641 }
1642 return ac_build_gather_values(&ctx->ac, values,
1643 TGSI_NUM_CHANNELS);
1644 }
1645
1646 /* Get the vertex offset parameter on GFX6. */
1647 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1648
1649 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1650 LLVMConstInt(ctx->i32, 4, 0), "");
1651
1652 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1653
1654 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1655 vtx_offset, soffset, 0, 1, 0, true, false);
1656 if (llvm_type_is_64bit(ctx, type)) {
1657 LLVMValueRef value2;
1658 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1659
1660 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1661 ctx->i32_0, vtx_offset, soffset,
1662 0, 1, 0, true, false);
1663 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1664 }
1665 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1666 }
1667
1668 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1669 unsigned location,
1670 unsigned driver_location,
1671 unsigned component,
1672 unsigned num_components,
1673 unsigned vertex_index,
1674 unsigned const_index,
1675 LLVMTypeRef type)
1676 {
1677 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1678
1679 LLVMValueRef value[4];
1680 for (unsigned i = 0; i < num_components; i++) {
1681 unsigned offset = i;
1682 if (llvm_type_is_64bit(ctx, type))
1683 offset *= 2;
1684
1685 offset += component;
1686 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1687 vertex_index, type, offset);
1688 }
1689
1690 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1691 }
1692
1693 static LLVMValueRef fetch_input_gs(
1694 struct lp_build_tgsi_context *bld_base,
1695 const struct tgsi_full_src_register *reg,
1696 enum tgsi_opcode_type type,
1697 unsigned swizzle_in)
1698 {
1699 struct si_shader_context *ctx = si_shader_context(bld_base);
1700 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1701 unsigned swizzle = swizzle_in & 0xffff;
1702
1703 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1704 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1705 return get_primitive_id(ctx, swizzle);
1706
1707 if (!reg->Register.Dimension)
1708 return NULL;
1709
1710 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1711 reg->Dimension.Index,
1712 tgsi2llvmtype(bld_base, type),
1713 swizzle);
1714 }
1715
1716 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1717 {
1718 switch (interpolate) {
1719 case TGSI_INTERPOLATE_CONSTANT:
1720 return 0;
1721
1722 case TGSI_INTERPOLATE_LINEAR:
1723 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1724 return SI_PARAM_LINEAR_SAMPLE;
1725 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1726 return SI_PARAM_LINEAR_CENTROID;
1727 else
1728 return SI_PARAM_LINEAR_CENTER;
1729 break;
1730 case TGSI_INTERPOLATE_COLOR:
1731 case TGSI_INTERPOLATE_PERSPECTIVE:
1732 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1733 return SI_PARAM_PERSP_SAMPLE;
1734 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1735 return SI_PARAM_PERSP_CENTROID;
1736 else
1737 return SI_PARAM_PERSP_CENTER;
1738 break;
1739 default:
1740 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1741 return -1;
1742 }
1743 }
1744
1745 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1746 unsigned attr_index, unsigned chan,
1747 LLVMValueRef prim_mask,
1748 LLVMValueRef i, LLVMValueRef j)
1749 {
1750 if (i || j) {
1751 return ac_build_fs_interp(&ctx->ac,
1752 LLVMConstInt(ctx->i32, chan, 0),
1753 LLVMConstInt(ctx->i32, attr_index, 0),
1754 prim_mask, i, j);
1755 }
1756 return ac_build_fs_interp_mov(&ctx->ac,
1757 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1758 LLVMConstInt(ctx->i32, chan, 0),
1759 LLVMConstInt(ctx->i32, attr_index, 0),
1760 prim_mask);
1761 }
1762
1763 /**
1764 * Interpolate a fragment shader input.
1765 *
1766 * @param ctx context
1767 * @param input_index index of the input in hardware
1768 * @param semantic_name TGSI_SEMANTIC_*
1769 * @param semantic_index semantic index
1770 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1771 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1772 * @param interp_param interpolation weights (i,j)
1773 * @param prim_mask SI_PARAM_PRIM_MASK
1774 * @param face SI_PARAM_FRONT_FACE
1775 * @param result the return value (4 components)
1776 */
1777 static void interp_fs_input(struct si_shader_context *ctx,
1778 unsigned input_index,
1779 unsigned semantic_name,
1780 unsigned semantic_index,
1781 unsigned num_interp_inputs,
1782 unsigned colors_read_mask,
1783 LLVMValueRef interp_param,
1784 LLVMValueRef prim_mask,
1785 LLVMValueRef face,
1786 LLVMValueRef result[4])
1787 {
1788 LLVMValueRef i = NULL, j = NULL;
1789 unsigned chan;
1790
1791 /* fs.constant returns the param from the middle vertex, so it's not
1792 * really useful for flat shading. It's meant to be used for custom
1793 * interpolation (but the intrinsic can't fetch from the other two
1794 * vertices).
1795 *
1796 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1797 * to do the right thing. The only reason we use fs.constant is that
1798 * fs.interp cannot be used on integers, because they can be equal
1799 * to NaN.
1800 *
1801 * When interp is false we will use fs.constant or for newer llvm,
1802 * amdgcn.interp.mov.
1803 */
1804 bool interp = interp_param != NULL;
1805
1806 if (interp) {
1807 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1808 LLVMVectorType(ctx->f32, 2), "");
1809
1810 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1811 ctx->i32_0, "");
1812 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1813 ctx->i32_1, "");
1814 }
1815
1816 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1817 ctx->shader->key.part.ps.prolog.color_two_side) {
1818 LLVMValueRef is_face_positive;
1819
1820 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1821 * otherwise it's at offset "num_inputs".
1822 */
1823 unsigned back_attr_offset = num_interp_inputs;
1824 if (semantic_index == 1 && colors_read_mask & 0xf)
1825 back_attr_offset += 1;
1826
1827 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1828 face, ctx->i32_0, "");
1829
1830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1831 LLVMValueRef front, back;
1832
1833 front = si_build_fs_interp(ctx,
1834 input_index, chan,
1835 prim_mask, i, j);
1836 back = si_build_fs_interp(ctx,
1837 back_attr_offset, chan,
1838 prim_mask, i, j);
1839
1840 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1841 is_face_positive,
1842 front,
1843 back,
1844 "");
1845 }
1846 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1847 result[0] = si_build_fs_interp(ctx, input_index,
1848 0, prim_mask, i, j);
1849 result[1] =
1850 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1851 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1852 } else {
1853 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1854 result[chan] = si_build_fs_interp(ctx,
1855 input_index, chan,
1856 prim_mask, i, j);
1857 }
1858 }
1859 }
1860
1861 void si_llvm_load_input_fs(
1862 struct si_shader_context *ctx,
1863 unsigned input_index,
1864 LLVMValueRef out[4])
1865 {
1866 struct si_shader *shader = ctx->shader;
1867 struct tgsi_shader_info *info = &shader->selector->info;
1868 LLVMValueRef main_fn = ctx->main_fn;
1869 LLVMValueRef interp_param = NULL;
1870 int interp_param_idx;
1871 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1872 unsigned semantic_index = info->input_semantic_index[input_index];
1873 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1874 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1875
1876 /* Get colors from input VGPRs (set by the prolog). */
1877 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1878 unsigned colors_read = shader->selector->info.colors_read;
1879 unsigned mask = colors_read >> (semantic_index * 4);
1880 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1881 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1882 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1883
1884 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1885 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1886 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1887 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1888 return;
1889 }
1890
1891 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1892 if (interp_param_idx == -1)
1893 return;
1894 else if (interp_param_idx) {
1895 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1896 }
1897
1898 interp_fs_input(ctx, input_index, semantic_name,
1899 semantic_index, 0, /* this param is unused */
1900 shader->selector->info.colors_read, interp_param,
1901 ctx->abi.prim_mask,
1902 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1903 &out[0]);
1904 }
1905
1906 static void declare_input_fs(
1907 struct si_shader_context *ctx,
1908 unsigned input_index,
1909 const struct tgsi_full_declaration *decl,
1910 LLVMValueRef out[4])
1911 {
1912 si_llvm_load_input_fs(ctx, input_index, out);
1913 }
1914
1915 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1916 {
1917 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1918 }
1919
1920 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1921 {
1922 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1923
1924 /* For non-indexed draws, the base vertex set by the driver
1925 * (for direct draws) or the CP (for indirect draws) is the
1926 * first vertex ID, but GLSL expects 0 to be returned.
1927 */
1928 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1929 ctx->param_vs_state_bits);
1930 LLVMValueRef indexed;
1931
1932 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1933 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1934
1935 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1936 ctx->i32_0, "");
1937 }
1938
1939 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1940 {
1941 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1942
1943 LLVMValueRef values[3];
1944 LLVMValueRef result;
1945 unsigned i;
1946 unsigned *properties = ctx->shader->selector->info.properties;
1947
1948 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1949 unsigned sizes[3] = {
1950 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1951 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1952 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1953 };
1954
1955 for (i = 0; i < 3; ++i)
1956 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1957
1958 result = ac_build_gather_values(&ctx->ac, values, 3);
1959 } else {
1960 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1961 }
1962
1963 return result;
1964 }
1965
1966 /**
1967 * Load a dword from a constant buffer.
1968 */
1969 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1970 LLVMValueRef resource,
1971 LLVMValueRef offset)
1972 {
1973 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1974 0, 0, 0, true, true);
1975 }
1976
1977 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1978 {
1979 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1980 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1981 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1982 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1983
1984 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1985 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1986 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1987
1988 LLVMValueRef pos[4] = {
1989 buffer_load_const(ctx, resource, offset0),
1990 buffer_load_const(ctx, resource, offset1),
1991 LLVMConstReal(ctx->f32, 0),
1992 LLVMConstReal(ctx->f32, 0)
1993 };
1994
1995 return ac_build_gather_values(&ctx->ac, pos, 4);
1996 }
1997
1998 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1999 {
2000 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2001 return ac_to_integer(&ctx->ac, abi->sample_coverage);
2002 }
2003
2004 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2005 {
2006 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2007 LLVMValueRef coord[4] = {
2008 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2009 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2010 ctx->ac.f32_0,
2011 ctx->ac.f32_0
2012 };
2013
2014 /* For triangles, the vector should be (u, v, 1-u-v). */
2015 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2016 PIPE_PRIM_TRIANGLES) {
2017 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
2018 LLVMBuildFAdd(ctx->ac.builder,
2019 coord[0], coord[1], ""), "");
2020 }
2021 return ac_build_gather_values(&ctx->ac, coord, 4);
2022 }
2023
2024 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2025 unsigned semantic_name)
2026 {
2027 LLVMValueRef base, addr;
2028
2029 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2030
2031 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2032 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2033 LLVMConstInt(ctx->i32, param, 0));
2034
2035 return buffer_load(&ctx->bld_base, ctx->f32,
2036 ~0, ctx->tess_offchip_ring, base, addr, true);
2037
2038 }
2039
2040 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2041 unsigned varying_id)
2042 {
2043 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2044 unsigned semantic_name;
2045
2046 switch (varying_id) {
2047 case VARYING_SLOT_TESS_LEVEL_INNER:
2048 semantic_name = TGSI_SEMANTIC_TESSINNER;
2049 break;
2050 case VARYING_SLOT_TESS_LEVEL_OUTER:
2051 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2052 break;
2053 default:
2054 unreachable("unknown tess level");
2055 }
2056
2057 return load_tess_level(ctx, semantic_name);
2058
2059 }
2060
2061 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2062 {
2063 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2064 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2065 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2066 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2067 return get_num_tcs_out_vertices(ctx);
2068 else
2069 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2070 }
2071
2072 void si_load_system_value(struct si_shader_context *ctx,
2073 unsigned index,
2074 const struct tgsi_full_declaration *decl)
2075 {
2076 LLVMValueRef value = 0;
2077
2078 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2079
2080 switch (decl->Semantic.Name) {
2081 case TGSI_SEMANTIC_INSTANCEID:
2082 value = ctx->abi.instance_id;
2083 break;
2084
2085 case TGSI_SEMANTIC_VERTEXID:
2086 value = LLVMBuildAdd(ctx->ac.builder,
2087 ctx->abi.vertex_id,
2088 ctx->abi.base_vertex, "");
2089 break;
2090
2091 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2092 /* Unused. Clarify the meaning in indexed vs. non-indexed
2093 * draws if this is ever used again. */
2094 assert(false);
2095 break;
2096
2097 case TGSI_SEMANTIC_BASEVERTEX:
2098 value = get_base_vertex(&ctx->abi);
2099 break;
2100
2101 case TGSI_SEMANTIC_BASEINSTANCE:
2102 value = ctx->abi.start_instance;
2103 break;
2104
2105 case TGSI_SEMANTIC_DRAWID:
2106 value = ctx->abi.draw_id;
2107 break;
2108
2109 case TGSI_SEMANTIC_INVOCATIONID:
2110 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2111 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2112 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2113 value = ctx->abi.gs_invocation_id;
2114 else
2115 assert(!"INVOCATIONID not implemented");
2116 break;
2117
2118 case TGSI_SEMANTIC_POSITION:
2119 {
2120 LLVMValueRef pos[4] = {
2121 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2122 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2123 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2124 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2125 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2126 };
2127 value = ac_build_gather_values(&ctx->ac, pos, 4);
2128 break;
2129 }
2130
2131 case TGSI_SEMANTIC_FACE:
2132 value = ctx->abi.front_face;
2133 break;
2134
2135 case TGSI_SEMANTIC_SAMPLEID:
2136 value = si_get_sample_id(ctx);
2137 break;
2138
2139 case TGSI_SEMANTIC_SAMPLEPOS: {
2140 LLVMValueRef pos[4] = {
2141 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2142 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2143 LLVMConstReal(ctx->f32, 0),
2144 LLVMConstReal(ctx->f32, 0)
2145 };
2146 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2147 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2148 value = ac_build_gather_values(&ctx->ac, pos, 4);
2149 break;
2150 }
2151
2152 case TGSI_SEMANTIC_SAMPLEMASK:
2153 /* This can only occur with the OpenGL Core profile, which
2154 * doesn't support smoothing.
2155 */
2156 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2157 break;
2158
2159 case TGSI_SEMANTIC_TESSCOORD:
2160 value = si_load_tess_coord(&ctx->abi);
2161 break;
2162
2163 case TGSI_SEMANTIC_VERTICESIN:
2164 value = si_load_patch_vertices_in(&ctx->abi);
2165 break;
2166
2167 case TGSI_SEMANTIC_TESSINNER:
2168 case TGSI_SEMANTIC_TESSOUTER:
2169 value = load_tess_level(ctx, decl->Semantic.Name);
2170 break;
2171
2172 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2173 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2174 {
2175 LLVMValueRef buf, slot, val[4];
2176 int i, offset;
2177
2178 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2179 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2180 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2181 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2182
2183 for (i = 0; i < 4; i++)
2184 val[i] = buffer_load_const(ctx, buf,
2185 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2186 value = ac_build_gather_values(&ctx->ac, val, 4);
2187 break;
2188 }
2189
2190 case TGSI_SEMANTIC_PRIMID:
2191 value = get_primitive_id(ctx, 0);
2192 break;
2193
2194 case TGSI_SEMANTIC_GRID_SIZE:
2195 value = ctx->abi.num_work_groups;
2196 break;
2197
2198 case TGSI_SEMANTIC_BLOCK_SIZE:
2199 value = get_block_size(&ctx->abi);
2200 break;
2201
2202 case TGSI_SEMANTIC_BLOCK_ID:
2203 {
2204 LLVMValueRef values[3];
2205
2206 for (int i = 0; i < 3; i++) {
2207 values[i] = ctx->i32_0;
2208 if (ctx->abi.workgroup_ids[i]) {
2209 values[i] = ctx->abi.workgroup_ids[i];
2210 }
2211 }
2212 value = ac_build_gather_values(&ctx->ac, values, 3);
2213 break;
2214 }
2215
2216 case TGSI_SEMANTIC_THREAD_ID:
2217 value = ctx->abi.local_invocation_ids;
2218 break;
2219
2220 case TGSI_SEMANTIC_HELPER_INVOCATION:
2221 value = ac_build_intrinsic(&ctx->ac,
2222 "llvm.amdgcn.ps.live",
2223 ctx->i1, NULL, 0,
2224 AC_FUNC_ATTR_READNONE);
2225 value = LLVMBuildNot(ctx->ac.builder, value, "");
2226 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2227 break;
2228
2229 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2230 value = LLVMConstInt(ctx->i32, 64, 0);
2231 break;
2232
2233 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2234 value = ac_get_thread_id(&ctx->ac);
2235 break;
2236
2237 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2238 {
2239 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2240 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2241 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2242 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2243 break;
2244 }
2245
2246 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2247 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2248 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2249 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2250 {
2251 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2252 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2253 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2254 /* All bits set except LSB */
2255 value = LLVMConstInt(ctx->i64, -2, 0);
2256 } else {
2257 /* All bits set */
2258 value = LLVMConstInt(ctx->i64, -1, 0);
2259 }
2260 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2261 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2262 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2263 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2264 value = LLVMBuildNot(ctx->ac.builder, value, "");
2265 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2266 break;
2267 }
2268
2269 case TGSI_SEMANTIC_CS_USER_DATA:
2270 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2271 break;
2272
2273 default:
2274 assert(!"unknown system value");
2275 return;
2276 }
2277
2278 ctx->system_values[index] = value;
2279 }
2280
2281 void si_declare_compute_memory(struct si_shader_context *ctx)
2282 {
2283 struct si_shader_selector *sel = ctx->shader->selector;
2284 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2285
2286 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2287 LLVMValueRef var;
2288
2289 assert(!ctx->ac.lds);
2290
2291 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2292 LLVMArrayType(ctx->i8, lds_size),
2293 "compute_lds",
2294 AC_ADDR_SPACE_LDS);
2295 LLVMSetAlignment(var, 4);
2296
2297 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2298 }
2299
2300 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2301 const struct tgsi_full_declaration *decl)
2302 {
2303 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2304 assert(decl->Range.First == decl->Range.Last);
2305
2306 si_declare_compute_memory(ctx);
2307 }
2308
2309 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2310 {
2311 LLVMValueRef ptr =
2312 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2313 struct si_shader_selector *sel = ctx->shader->selector;
2314
2315 /* Do the bounds checking with a descriptor, because
2316 * doing computation and manual bounds checking of 64-bit
2317 * addresses generates horrible VALU code with very high
2318 * VGPR usage and very low SIMD occupancy.
2319 */
2320 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2321
2322 LLVMValueRef desc0, desc1;
2323 desc0 = ptr;
2324 desc1 = LLVMConstInt(ctx->i32,
2325 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2326
2327 LLVMValueRef desc_elems[] = {
2328 desc0,
2329 desc1,
2330 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2331 LLVMConstInt(ctx->i32,
2332 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2333 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2334 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2335 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2336 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2337 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2338 };
2339
2340 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2341 }
2342
2343 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2344 {
2345 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2346 ctx->param_const_and_shader_buffers);
2347
2348 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2349 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2350 }
2351
2352 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2353 {
2354 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2355 struct si_shader_selector *sel = ctx->shader->selector;
2356
2357 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2358
2359 if (sel->info.const_buffers_declared == 1 &&
2360 sel->info.shader_buffers_declared == 0) {
2361 return load_const_buffer_desc_fast_path(ctx);
2362 }
2363
2364 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2365 index = LLVMBuildAdd(ctx->ac.builder, index,
2366 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2367
2368 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2369 }
2370
2371 static LLVMValueRef
2372 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2373 {
2374 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2375 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2376 ctx->param_const_and_shader_buffers);
2377
2378 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2379 index = LLVMBuildSub(ctx->ac.builder,
2380 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2381 index, "");
2382
2383 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2384 }
2385
2386 static LLVMValueRef fetch_constant(
2387 struct lp_build_tgsi_context *bld_base,
2388 const struct tgsi_full_src_register *reg,
2389 enum tgsi_opcode_type type,
2390 unsigned swizzle_in)
2391 {
2392 struct si_shader_context *ctx = si_shader_context(bld_base);
2393 struct si_shader_selector *sel = ctx->shader->selector;
2394 const struct tgsi_ind_register *ireg = &reg->Indirect;
2395 unsigned buf, idx;
2396 unsigned swizzle = swizzle_in & 0xffff;
2397
2398 LLVMValueRef addr, bufp;
2399
2400 if (swizzle_in == LP_CHAN_ALL) {
2401 unsigned chan;
2402 LLVMValueRef values[4];
2403 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2404 values[chan] = fetch_constant(bld_base, reg, type, chan);
2405
2406 return ac_build_gather_values(&ctx->ac, values, 4);
2407 }
2408
2409 /* Split 64-bit loads. */
2410 if (tgsi_type_is_64bit(type)) {
2411 LLVMValueRef lo, hi;
2412
2413 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2414 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2415 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2416 lo, hi);
2417 }
2418
2419 idx = reg->Register.Index * 4 + swizzle;
2420 if (reg->Register.Indirect) {
2421 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2422 } else {
2423 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2424 }
2425
2426 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2427 if (sel->info.const_buffers_declared == 1 &&
2428 sel->info.shader_buffers_declared == 0) {
2429 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2430 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2431 return bitcast(bld_base, type, result);
2432 }
2433
2434 assert(reg->Register.Dimension);
2435 buf = reg->Dimension.Index;
2436
2437 if (reg->Dimension.Indirect) {
2438 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2439 LLVMValueRef index;
2440 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2441 reg->Dimension.Index,
2442 ctx->num_const_buffers);
2443 index = LLVMBuildAdd(ctx->ac.builder, index,
2444 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2445 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2446 } else
2447 bufp = load_const_buffer_desc(ctx, buf);
2448
2449 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2450 }
2451
2452 /* Initialize arguments for the shader export intrinsic */
2453 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2454 LLVMValueRef *values,
2455 unsigned target,
2456 struct ac_export_args *args)
2457 {
2458 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2459 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2460 unsigned chan;
2461 bool is_int8, is_int10;
2462
2463 /* Default is 0xf. Adjusted below depending on the format. */
2464 args->enabled_channels = 0xf; /* writemask */
2465
2466 /* Specify whether the EXEC mask represents the valid mask */
2467 args->valid_mask = 0;
2468
2469 /* Specify whether this is the last export */
2470 args->done = 0;
2471
2472 /* Specify the target we are exporting */
2473 args->target = target;
2474
2475 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2476 const struct si_shader_key *key = &ctx->shader->key;
2477 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2478 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2479
2480 assert(cbuf >= 0 && cbuf < 8);
2481 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2482 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2483 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2484 }
2485
2486 args->compr = false;
2487 args->out[0] = f32undef;
2488 args->out[1] = f32undef;
2489 args->out[2] = f32undef;
2490 args->out[3] = f32undef;
2491
2492 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2493 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2494 unsigned bits, bool hi) = NULL;
2495
2496 switch (spi_shader_col_format) {
2497 case V_028714_SPI_SHADER_ZERO:
2498 args->enabled_channels = 0; /* writemask */
2499 args->target = V_008DFC_SQ_EXP_NULL;
2500 break;
2501
2502 case V_028714_SPI_SHADER_32_R:
2503 args->enabled_channels = 1; /* writemask */
2504 args->out[0] = values[0];
2505 break;
2506
2507 case V_028714_SPI_SHADER_32_GR:
2508 args->enabled_channels = 0x3; /* writemask */
2509 args->out[0] = values[0];
2510 args->out[1] = values[1];
2511 break;
2512
2513 case V_028714_SPI_SHADER_32_AR:
2514 args->enabled_channels = 0x9; /* writemask */
2515 args->out[0] = values[0];
2516 args->out[3] = values[3];
2517 break;
2518
2519 case V_028714_SPI_SHADER_FP16_ABGR:
2520 packf = ac_build_cvt_pkrtz_f16;
2521 break;
2522
2523 case V_028714_SPI_SHADER_UNORM16_ABGR:
2524 packf = ac_build_cvt_pknorm_u16;
2525 break;
2526
2527 case V_028714_SPI_SHADER_SNORM16_ABGR:
2528 packf = ac_build_cvt_pknorm_i16;
2529 break;
2530
2531 case V_028714_SPI_SHADER_UINT16_ABGR:
2532 packi = ac_build_cvt_pk_u16;
2533 break;
2534
2535 case V_028714_SPI_SHADER_SINT16_ABGR:
2536 packi = ac_build_cvt_pk_i16;
2537 break;
2538
2539 case V_028714_SPI_SHADER_32_ABGR:
2540 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2541 break;
2542 }
2543
2544 /* Pack f16 or norm_i16/u16. */
2545 if (packf) {
2546 for (chan = 0; chan < 2; chan++) {
2547 LLVMValueRef pack_args[2] = {
2548 values[2 * chan],
2549 values[2 * chan + 1]
2550 };
2551 LLVMValueRef packed;
2552
2553 packed = packf(&ctx->ac, pack_args);
2554 args->out[chan] = ac_to_float(&ctx->ac, packed);
2555 }
2556 args->compr = 1; /* COMPR flag */
2557 }
2558 /* Pack i16/u16. */
2559 if (packi) {
2560 for (chan = 0; chan < 2; chan++) {
2561 LLVMValueRef pack_args[2] = {
2562 ac_to_integer(&ctx->ac, values[2 * chan]),
2563 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2564 };
2565 LLVMValueRef packed;
2566
2567 packed = packi(&ctx->ac, pack_args,
2568 is_int8 ? 8 : is_int10 ? 10 : 16,
2569 chan == 1);
2570 args->out[chan] = ac_to_float(&ctx->ac, packed);
2571 }
2572 args->compr = 1; /* COMPR flag */
2573 }
2574 }
2575
2576 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2577 LLVMValueRef alpha)
2578 {
2579 struct si_shader_context *ctx = si_shader_context(bld_base);
2580
2581 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2582 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2583 [PIPE_FUNC_LESS] = LLVMRealOLT,
2584 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2585 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2586 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2587 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2588 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2589 };
2590 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2591 assert(cond);
2592
2593 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2594 SI_PARAM_ALPHA_REF);
2595 LLVMValueRef alpha_pass =
2596 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2597 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2598 } else {
2599 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2600 }
2601 }
2602
2603 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2604 LLVMValueRef alpha,
2605 unsigned samplemask_param)
2606 {
2607 struct si_shader_context *ctx = si_shader_context(bld_base);
2608 LLVMValueRef coverage;
2609
2610 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2611 coverage = LLVMGetParam(ctx->main_fn,
2612 samplemask_param);
2613 coverage = ac_to_integer(&ctx->ac, coverage);
2614
2615 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2616 ctx->i32,
2617 &coverage, 1, AC_FUNC_ATTR_READNONE);
2618
2619 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2620 ctx->f32, "");
2621
2622 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2623 LLVMConstReal(ctx->f32,
2624 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2625
2626 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2627 }
2628
2629 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2630 struct ac_export_args *pos, LLVMValueRef *out_elts)
2631 {
2632 unsigned reg_index;
2633 unsigned chan;
2634 unsigned const_chan;
2635 LLVMValueRef base_elt;
2636 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2637 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2638 SI_VS_CONST_CLIP_PLANES, 0);
2639 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2640
2641 for (reg_index = 0; reg_index < 2; reg_index ++) {
2642 struct ac_export_args *args = &pos[2 + reg_index];
2643
2644 args->out[0] =
2645 args->out[1] =
2646 args->out[2] =
2647 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2648
2649 /* Compute dot products of position and user clip plane vectors */
2650 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2651 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2652 LLVMValueRef addr =
2653 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2654 const_chan) * 4, 0);
2655 base_elt = buffer_load_const(ctx, const_resource,
2656 addr);
2657 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2658 out_elts[const_chan], args->out[chan]);
2659 }
2660 }
2661
2662 args->enabled_channels = 0xf;
2663 args->valid_mask = 0;
2664 args->done = 0;
2665 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2666 args->compr = 0;
2667 }
2668 }
2669
2670 static void si_dump_streamout(struct pipe_stream_output_info *so)
2671 {
2672 unsigned i;
2673
2674 if (so->num_outputs)
2675 fprintf(stderr, "STREAMOUT\n");
2676
2677 for (i = 0; i < so->num_outputs; i++) {
2678 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2679 so->output[i].start_component;
2680 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2681 i, so->output[i].output_buffer,
2682 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2683 so->output[i].register_index,
2684 mask & 1 ? "x" : "",
2685 mask & 2 ? "y" : "",
2686 mask & 4 ? "z" : "",
2687 mask & 8 ? "w" : "");
2688 }
2689 }
2690
2691 static void emit_streamout_output(struct si_shader_context *ctx,
2692 LLVMValueRef const *so_buffers,
2693 LLVMValueRef const *so_write_offsets,
2694 struct pipe_stream_output *stream_out,
2695 struct si_shader_output_values *shader_out)
2696 {
2697 unsigned buf_idx = stream_out->output_buffer;
2698 unsigned start = stream_out->start_component;
2699 unsigned num_comps = stream_out->num_components;
2700 LLVMValueRef out[4];
2701
2702 assert(num_comps && num_comps <= 4);
2703 if (!num_comps || num_comps > 4)
2704 return;
2705
2706 /* Load the output as int. */
2707 for (int j = 0; j < num_comps; j++) {
2708 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2709
2710 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2711 }
2712
2713 /* Pack the output. */
2714 LLVMValueRef vdata = NULL;
2715
2716 switch (num_comps) {
2717 case 1: /* as i32 */
2718 vdata = out[0];
2719 break;
2720 case 2: /* as v2i32 */
2721 case 3: /* as v4i32 (aligned to 4) */
2722 out[3] = LLVMGetUndef(ctx->i32);
2723 /* fall through */
2724 case 4: /* as v4i32 */
2725 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2726 break;
2727 }
2728
2729 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2730 vdata, num_comps,
2731 so_write_offsets[buf_idx],
2732 ctx->i32_0,
2733 stream_out->dst_offset * 4, 1, 1, true, false);
2734 }
2735
2736 /**
2737 * Write streamout data to buffers for vertex stream @p stream (different
2738 * vertex streams can occur for GS copy shaders).
2739 */
2740 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2741 struct si_shader_output_values *outputs,
2742 unsigned noutput, unsigned stream)
2743 {
2744 struct si_shader_selector *sel = ctx->shader->selector;
2745 struct pipe_stream_output_info *so = &sel->so;
2746 LLVMBuilderRef builder = ctx->ac.builder;
2747 int i;
2748 struct lp_build_if_state if_ctx;
2749
2750 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2751 LLVMValueRef so_vtx_count =
2752 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2753
2754 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2755
2756 /* can_emit = tid < so_vtx_count; */
2757 LLVMValueRef can_emit =
2758 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2759
2760 /* Emit the streamout code conditionally. This actually avoids
2761 * out-of-bounds buffer access. The hw tells us via the SGPR
2762 * (so_vtx_count) which threads are allowed to emit streamout data. */
2763 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2764 {
2765 /* The buffer offset is computed as follows:
2766 * ByteOffset = streamout_offset[buffer_id]*4 +
2767 * (streamout_write_index + thread_id)*stride[buffer_id] +
2768 * attrib_offset
2769 */
2770
2771 LLVMValueRef so_write_index =
2772 LLVMGetParam(ctx->main_fn,
2773 ctx->param_streamout_write_index);
2774
2775 /* Compute (streamout_write_index + thread_id). */
2776 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2777
2778 /* Load the descriptor and compute the write offset for each
2779 * enabled buffer. */
2780 LLVMValueRef so_write_offset[4] = {};
2781 LLVMValueRef so_buffers[4];
2782 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2783 ctx->param_rw_buffers);
2784
2785 for (i = 0; i < 4; i++) {
2786 if (!so->stride[i])
2787 continue;
2788
2789 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2790 SI_VS_STREAMOUT_BUF0 + i, 0);
2791
2792 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2793
2794 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2795 ctx->param_streamout_offset[i]);
2796 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2797
2798 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2799 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2800 so_offset);
2801 }
2802
2803 /* Write streamout data. */
2804 for (i = 0; i < so->num_outputs; i++) {
2805 unsigned reg = so->output[i].register_index;
2806
2807 if (reg >= noutput)
2808 continue;
2809
2810 if (stream != so->output[i].stream)
2811 continue;
2812
2813 emit_streamout_output(ctx, so_buffers, so_write_offset,
2814 &so->output[i], &outputs[reg]);
2815 }
2816 }
2817 lp_build_endif(&if_ctx);
2818 }
2819
2820 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2821 LLVMValueRef *values)
2822 {
2823 struct ac_export_args args;
2824
2825 si_llvm_init_export_args(ctx, values,
2826 V_008DFC_SQ_EXP_PARAM + index, &args);
2827 ac_build_export(&ctx->ac, &args);
2828 }
2829
2830 static void si_build_param_exports(struct si_shader_context *ctx,
2831 struct si_shader_output_values *outputs,
2832 unsigned noutput)
2833 {
2834 struct si_shader *shader = ctx->shader;
2835 unsigned param_count = 0;
2836
2837 for (unsigned i = 0; i < noutput; i++) {
2838 unsigned semantic_name = outputs[i].semantic_name;
2839 unsigned semantic_index = outputs[i].semantic_index;
2840
2841 if (outputs[i].vertex_stream[0] != 0 &&
2842 outputs[i].vertex_stream[1] != 0 &&
2843 outputs[i].vertex_stream[2] != 0 &&
2844 outputs[i].vertex_stream[3] != 0)
2845 continue;
2846
2847 switch (semantic_name) {
2848 case TGSI_SEMANTIC_LAYER:
2849 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2850 case TGSI_SEMANTIC_CLIPDIST:
2851 case TGSI_SEMANTIC_COLOR:
2852 case TGSI_SEMANTIC_BCOLOR:
2853 case TGSI_SEMANTIC_PRIMID:
2854 case TGSI_SEMANTIC_FOG:
2855 case TGSI_SEMANTIC_TEXCOORD:
2856 case TGSI_SEMANTIC_GENERIC:
2857 break;
2858 default:
2859 continue;
2860 }
2861
2862 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2863 semantic_index < SI_MAX_IO_GENERIC) &&
2864 shader->key.opt.kill_outputs &
2865 (1ull << si_shader_io_get_unique_index(semantic_name,
2866 semantic_index, true)))
2867 continue;
2868
2869 si_export_param(ctx, param_count, outputs[i].values);
2870
2871 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2872 shader->info.vs_output_param_offset[i] = param_count++;
2873 }
2874
2875 shader->info.nr_param_exports = param_count;
2876 }
2877
2878 /* Generate export instructions for hardware VS shader stage */
2879 static void si_llvm_export_vs(struct si_shader_context *ctx,
2880 struct si_shader_output_values *outputs,
2881 unsigned noutput)
2882 {
2883 struct si_shader *shader = ctx->shader;
2884 struct ac_export_args pos_args[4] = {};
2885 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2886 unsigned pos_idx;
2887 int i;
2888
2889 /* Build position exports. */
2890 for (i = 0; i < noutput; i++) {
2891 switch (outputs[i].semantic_name) {
2892 case TGSI_SEMANTIC_POSITION:
2893 si_llvm_init_export_args(ctx, outputs[i].values,
2894 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2895 break;
2896 case TGSI_SEMANTIC_PSIZE:
2897 psize_value = outputs[i].values[0];
2898 break;
2899 case TGSI_SEMANTIC_LAYER:
2900 layer_value = outputs[i].values[0];
2901 break;
2902 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2903 viewport_index_value = outputs[i].values[0];
2904 break;
2905 case TGSI_SEMANTIC_EDGEFLAG:
2906 edgeflag_value = outputs[i].values[0];
2907 break;
2908 case TGSI_SEMANTIC_CLIPDIST:
2909 if (!shader->key.opt.clip_disable) {
2910 unsigned index = 2 + outputs[i].semantic_index;
2911 si_llvm_init_export_args(ctx, outputs[i].values,
2912 V_008DFC_SQ_EXP_POS + index,
2913 &pos_args[index]);
2914 }
2915 break;
2916 case TGSI_SEMANTIC_CLIPVERTEX:
2917 if (!shader->key.opt.clip_disable) {
2918 si_llvm_emit_clipvertex(ctx, pos_args,
2919 outputs[i].values);
2920 }
2921 break;
2922 }
2923 }
2924
2925 /* We need to add the position output manually if it's missing. */
2926 if (!pos_args[0].out[0]) {
2927 pos_args[0].enabled_channels = 0xf; /* writemask */
2928 pos_args[0].valid_mask = 0; /* EXEC mask */
2929 pos_args[0].done = 0; /* last export? */
2930 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2931 pos_args[0].compr = 0; /* COMPR flag */
2932 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2933 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2934 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2935 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2936 }
2937
2938 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2939 if (shader->selector->info.writes_psize ||
2940 shader->selector->info.writes_edgeflag ||
2941 shader->selector->info.writes_viewport_index ||
2942 shader->selector->info.writes_layer) {
2943 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2944 (shader->selector->info.writes_edgeflag << 1) |
2945 (shader->selector->info.writes_layer << 2);
2946
2947 pos_args[1].valid_mask = 0; /* EXEC mask */
2948 pos_args[1].done = 0; /* last export? */
2949 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2950 pos_args[1].compr = 0; /* COMPR flag */
2951 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2952 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2953 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2954 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2955
2956 if (shader->selector->info.writes_psize)
2957 pos_args[1].out[0] = psize_value;
2958
2959 if (shader->selector->info.writes_edgeflag) {
2960 /* The output is a float, but the hw expects an integer
2961 * with the first bit containing the edge flag. */
2962 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2963 edgeflag_value,
2964 ctx->i32, "");
2965 edgeflag_value = ac_build_umin(&ctx->ac,
2966 edgeflag_value,
2967 ctx->i32_1);
2968
2969 /* The LLVM intrinsic expects a float. */
2970 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2971 }
2972
2973 if (ctx->screen->info.chip_class >= GFX9) {
2974 /* GFX9 has the layer in out.z[10:0] and the viewport
2975 * index in out.z[19:16].
2976 */
2977 if (shader->selector->info.writes_layer)
2978 pos_args[1].out[2] = layer_value;
2979
2980 if (shader->selector->info.writes_viewport_index) {
2981 LLVMValueRef v = viewport_index_value;
2982
2983 v = ac_to_integer(&ctx->ac, v);
2984 v = LLVMBuildShl(ctx->ac.builder, v,
2985 LLVMConstInt(ctx->i32, 16, 0), "");
2986 v = LLVMBuildOr(ctx->ac.builder, v,
2987 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2988 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2989 pos_args[1].enabled_channels |= 1 << 2;
2990 }
2991 } else {
2992 if (shader->selector->info.writes_layer)
2993 pos_args[1].out[2] = layer_value;
2994
2995 if (shader->selector->info.writes_viewport_index) {
2996 pos_args[1].out[3] = viewport_index_value;
2997 pos_args[1].enabled_channels |= 1 << 3;
2998 }
2999 }
3000 }
3001
3002 for (i = 0; i < 4; i++)
3003 if (pos_args[i].out[0])
3004 shader->info.nr_pos_exports++;
3005
3006 pos_idx = 0;
3007 for (i = 0; i < 4; i++) {
3008 if (!pos_args[i].out[0])
3009 continue;
3010
3011 /* Specify the target we are exporting */
3012 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3013
3014 if (pos_idx == shader->info.nr_pos_exports)
3015 /* Specify that this is the last export */
3016 pos_args[i].done = 1;
3017
3018 ac_build_export(&ctx->ac, &pos_args[i]);
3019 }
3020
3021 /* Build parameter exports. */
3022 si_build_param_exports(ctx, outputs, noutput);
3023 }
3024
3025 /**
3026 * Forward all outputs from the vertex shader to the TES. This is only used
3027 * for the fixed function TCS.
3028 */
3029 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3030 {
3031 struct si_shader_context *ctx = si_shader_context(bld_base);
3032 LLVMValueRef invocation_id, buffer, buffer_offset;
3033 LLVMValueRef lds_vertex_stride, lds_base;
3034 uint64_t inputs;
3035
3036 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3037 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3038 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3039
3040 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3041 lds_base = get_tcs_in_current_patch_offset(ctx);
3042 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3043 lds_base);
3044
3045 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3046 while (inputs) {
3047 unsigned i = u_bit_scan64(&inputs);
3048
3049 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3050 LLVMConstInt(ctx->i32, 4 * i, 0),
3051 "");
3052
3053 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3054 get_rel_patch_id(ctx),
3055 invocation_id,
3056 LLVMConstInt(ctx->i32, i, 0));
3057
3058 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3059 lds_ptr);
3060
3061 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3062 buffer_offset, 0, 1, 0, true, false);
3063 }
3064 }
3065
3066 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3067 LLVMValueRef rel_patch_id,
3068 LLVMValueRef invocation_id,
3069 LLVMValueRef tcs_out_current_patch_data_offset,
3070 LLVMValueRef invoc0_tf_outer[4],
3071 LLVMValueRef invoc0_tf_inner[2])
3072 {
3073 struct si_shader_context *ctx = si_shader_context(bld_base);
3074 struct si_shader *shader = ctx->shader;
3075 unsigned tess_inner_index, tess_outer_index;
3076 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3077 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3078 unsigned stride, outer_comps, inner_comps, i, offset;
3079 struct lp_build_if_state if_ctx, inner_if_ctx;
3080
3081 /* Add a barrier before loading tess factors from LDS. */
3082 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3083 si_llvm_emit_barrier(NULL, bld_base, NULL);
3084
3085 /* Do this only for invocation 0, because the tess levels are per-patch,
3086 * not per-vertex.
3087 *
3088 * This can't jump, because invocation 0 executes this. It should
3089 * at least mask out the loads and stores for other invocations.
3090 */
3091 lp_build_if(&if_ctx, &ctx->gallivm,
3092 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3093 invocation_id, ctx->i32_0, ""));
3094
3095 /* Determine the layout of one tess factor element in the buffer. */
3096 switch (shader->key.part.tcs.epilog.prim_mode) {
3097 case PIPE_PRIM_LINES:
3098 stride = 2; /* 2 dwords, 1 vec2 store */
3099 outer_comps = 2;
3100 inner_comps = 0;
3101 break;
3102 case PIPE_PRIM_TRIANGLES:
3103 stride = 4; /* 4 dwords, 1 vec4 store */
3104 outer_comps = 3;
3105 inner_comps = 1;
3106 break;
3107 case PIPE_PRIM_QUADS:
3108 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3109 outer_comps = 4;
3110 inner_comps = 2;
3111 break;
3112 default:
3113 assert(0);
3114 return;
3115 }
3116
3117 for (i = 0; i < 4; i++) {
3118 inner[i] = LLVMGetUndef(ctx->i32);
3119 outer[i] = LLVMGetUndef(ctx->i32);
3120 }
3121
3122 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3123 /* Tess factors are in VGPRs. */
3124 for (i = 0; i < outer_comps; i++)
3125 outer[i] = out[i] = invoc0_tf_outer[i];
3126 for (i = 0; i < inner_comps; i++)
3127 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3128 } else {
3129 /* Load tess_inner and tess_outer from LDS.
3130 * Any invocation can write them, so we can't get them from a temporary.
3131 */
3132 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3133 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3134
3135 lds_base = tcs_out_current_patch_data_offset;
3136 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3137 LLVMConstInt(ctx->i32,
3138 tess_inner_index * 4, 0), "");
3139 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3140 LLVMConstInt(ctx->i32,
3141 tess_outer_index * 4, 0), "");
3142
3143 for (i = 0; i < outer_comps; i++) {
3144 outer[i] = out[i] =
3145 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3146 }
3147 for (i = 0; i < inner_comps; i++) {
3148 inner[i] = out[outer_comps+i] =
3149 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3150 }
3151 }
3152
3153 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3154 /* For isolines, the hardware expects tess factors in the
3155 * reverse order from what GLSL / TGSI specify.
3156 */
3157 LLVMValueRef tmp = out[0];
3158 out[0] = out[1];
3159 out[1] = tmp;
3160 }
3161
3162 /* Convert the outputs to vectors for stores. */
3163 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3164 vec1 = NULL;
3165
3166 if (stride > 4)
3167 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3168
3169 /* Get the buffer. */
3170 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3171
3172 /* Get the offset. */
3173 tf_base = LLVMGetParam(ctx->main_fn,
3174 ctx->param_tcs_factor_offset);
3175 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3176 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3177
3178 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3179 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3180 rel_patch_id, ctx->i32_0, ""));
3181
3182 /* Store the dynamic HS control word. */
3183 offset = 0;
3184 if (ctx->screen->info.chip_class <= VI) {
3185 ac_build_buffer_store_dword(&ctx->ac, buffer,
3186 LLVMConstInt(ctx->i32, 0x80000000, 0),
3187 1, ctx->i32_0, tf_base,
3188 offset, 1, 0, true, false);
3189 offset += 4;
3190 }
3191
3192 lp_build_endif(&inner_if_ctx);
3193
3194 /* Store the tessellation factors. */
3195 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3196 MIN2(stride, 4), byteoffset, tf_base,
3197 offset, 1, 0, true, false);
3198 offset += 16;
3199 if (vec1)
3200 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3201 stride - 4, byteoffset, tf_base,
3202 offset, 1, 0, true, false);
3203
3204 /* Store the tess factors into the offchip buffer if TES reads them. */
3205 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3206 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3207 LLVMValueRef tf_inner_offset;
3208 unsigned param_outer, param_inner;
3209
3210 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3211 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3212
3213 param_outer = si_shader_io_get_unique_index_patch(
3214 TGSI_SEMANTIC_TESSOUTER, 0);
3215 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3216 LLVMConstInt(ctx->i32, param_outer, 0));
3217
3218 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3219 util_next_power_of_two(outer_comps));
3220
3221 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3222 outer_comps, tf_outer_offset,
3223 base, 0, 1, 0, true, false);
3224 if (inner_comps) {
3225 param_inner = si_shader_io_get_unique_index_patch(
3226 TGSI_SEMANTIC_TESSINNER, 0);
3227 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3228 LLVMConstInt(ctx->i32, param_inner, 0));
3229
3230 inner_vec = inner_comps == 1 ? inner[0] :
3231 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3232 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3233 inner_comps, tf_inner_offset,
3234 base, 0, 1, 0, true, false);
3235 }
3236 }
3237
3238 lp_build_endif(&if_ctx);
3239 }
3240
3241 static LLVMValueRef
3242 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3243 unsigned param, unsigned return_index)
3244 {
3245 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3246 LLVMGetParam(ctx->main_fn, param),
3247 return_index, "");
3248 }
3249
3250 static LLVMValueRef
3251 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3252 unsigned param, unsigned return_index)
3253 {
3254 LLVMBuilderRef builder = ctx->ac.builder;
3255 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3256
3257 return LLVMBuildInsertValue(builder, ret,
3258 ac_to_float(&ctx->ac, p),
3259 return_index, "");
3260 }
3261
3262 static LLVMValueRef
3263 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3264 unsigned param, unsigned return_index)
3265 {
3266 LLVMBuilderRef builder = ctx->ac.builder;
3267 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3268 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3269 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3270 }
3271
3272 /* This only writes the tessellation factor levels. */
3273 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3274 unsigned max_outputs,
3275 LLVMValueRef *addrs)
3276 {
3277 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3278 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3279 LLVMBuilderRef builder = ctx->ac.builder;
3280 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3281
3282 si_copy_tcs_inputs(bld_base);
3283
3284 rel_patch_id = get_rel_patch_id(ctx);
3285 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3286 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3287
3288 if (ctx->screen->info.chip_class >= GFX9) {
3289 LLVMBasicBlockRef blocks[2] = {
3290 LLVMGetInsertBlock(builder),
3291 ctx->merged_wrap_if_state.entry_block
3292 };
3293 LLVMValueRef values[2];
3294
3295 lp_build_endif(&ctx->merged_wrap_if_state);
3296
3297 values[0] = rel_patch_id;
3298 values[1] = LLVMGetUndef(ctx->i32);
3299 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3300
3301 values[0] = tf_lds_offset;
3302 values[1] = LLVMGetUndef(ctx->i32);
3303 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3304
3305 values[0] = invocation_id;
3306 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3307 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3308 }
3309
3310 /* Return epilog parameters from this function. */
3311 LLVMValueRef ret = ctx->return_value;
3312 unsigned vgpr;
3313
3314 if (ctx->screen->info.chip_class >= GFX9) {
3315 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3316 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3317 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3318 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3319 /* Tess offchip and tess factor offsets are at the beginning. */
3320 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3322 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3323 } else {
3324 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3325 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3326 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3327 GFX6_SGPR_TCS_OUT_LAYOUT);
3328 /* Tess offchip and tess factor offsets are after user SGPRs. */
3329 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3330 GFX6_TCS_NUM_USER_SGPR);
3331 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3332 GFX6_TCS_NUM_USER_SGPR + 1);
3333 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3334 }
3335
3336 /* VGPRs */
3337 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3338 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3339 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3340
3341 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3342 * the invocation_id output does not alias the tcs_rel_ids input,
3343 * which saves a V_MOV on gfx9.
3344 */
3345 vgpr += 2;
3346
3347 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3348 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3349
3350 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3351 vgpr++; /* skip the tess factor LDS offset */
3352 for (unsigned i = 0; i < 6; i++) {
3353 LLVMValueRef value =
3354 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3355 value = ac_to_float(&ctx->ac, value);
3356 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3357 }
3358 } else {
3359 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3360 }
3361 ctx->return_value = ret;
3362 }
3363
3364 /* Pass TCS inputs from LS to TCS on GFX9. */
3365 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3366 {
3367 LLVMValueRef ret = ctx->return_value;
3368
3369 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3370 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3372 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3373 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3375
3376 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3377 8 + SI_SGPR_RW_BUFFERS);
3378 ret = si_insert_input_ptr(ctx, ret,
3379 ctx->param_bindless_samplers_and_images,
3380 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3381
3382 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3383 8 + SI_SGPR_VS_STATE_BITS);
3384
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3386 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3387 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3388 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3389 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3390 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3391
3392 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3393 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3394 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3395 vgpr++, "");
3396 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3397 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3398 vgpr++, "");
3399 ctx->return_value = ret;
3400 }
3401
3402 /* Pass GS inputs from ES to GS on GFX9. */
3403 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3404 {
3405 LLVMValueRef ret = ctx->return_value;
3406
3407 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3408 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3409 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3410 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3411 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3412
3413 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3414 8 + SI_SGPR_RW_BUFFERS);
3415 ret = si_insert_input_ptr(ctx, ret,
3416 ctx->param_bindless_samplers_and_images,
3417 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3418
3419 unsigned vgpr;
3420 if (ctx->type == PIPE_SHADER_VERTEX)
3421 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3422 else
3423 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3424
3425 for (unsigned i = 0; i < 5; i++) {
3426 unsigned param = ctx->param_gs_vtx01_offset + i;
3427 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3428 }
3429 ctx->return_value = ret;
3430 }
3431
3432 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3433 unsigned max_outputs,
3434 LLVMValueRef *addrs)
3435 {
3436 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3437 struct si_shader *shader = ctx->shader;
3438 struct tgsi_shader_info *info = &shader->selector->info;
3439 unsigned i, chan;
3440 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3441 ctx->param_rel_auto_id);
3442 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3443 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3444 vertex_dw_stride, "");
3445
3446 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3447 * its inputs from it. */
3448 for (i = 0; i < info->num_outputs; i++) {
3449 unsigned name = info->output_semantic_name[i];
3450 unsigned index = info->output_semantic_index[i];
3451
3452 /* The ARB_shader_viewport_layer_array spec contains the
3453 * following issue:
3454 *
3455 * 2) What happens if gl_ViewportIndex or gl_Layer is
3456 * written in the vertex shader and a geometry shader is
3457 * present?
3458 *
3459 * RESOLVED: The value written by the last vertex processing
3460 * stage is used. If the last vertex processing stage
3461 * (vertex, tessellation evaluation or geometry) does not
3462 * statically assign to gl_ViewportIndex or gl_Layer, index
3463 * or layer zero is assumed.
3464 *
3465 * So writes to those outputs in VS-as-LS are simply ignored.
3466 */
3467 if (name == TGSI_SEMANTIC_LAYER ||
3468 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3469 continue;
3470
3471 int param = si_shader_io_get_unique_index(name, index, false);
3472 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3473 LLVMConstInt(ctx->i32, param * 4, 0), "");
3474
3475 for (chan = 0; chan < 4; chan++) {
3476 if (!(info->output_usagemask[i] & (1 << chan)))
3477 continue;
3478
3479 lds_store(ctx, chan, dw_addr,
3480 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3481 }
3482 }
3483
3484 if (ctx->screen->info.chip_class >= GFX9)
3485 si_set_ls_return_value_for_tcs(ctx);
3486 }
3487
3488 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3489 unsigned max_outputs,
3490 LLVMValueRef *addrs)
3491 {
3492 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3493 struct si_shader *es = ctx->shader;
3494 struct tgsi_shader_info *info = &es->selector->info;
3495 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3496 ctx->param_es2gs_offset);
3497 LLVMValueRef lds_base = NULL;
3498 unsigned chan;
3499 int i;
3500
3501 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3502 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3503 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3504 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3505 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3506 LLVMBuildMul(ctx->ac.builder, wave_idx,
3507 LLVMConstInt(ctx->i32, 64, false), ""), "");
3508 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3509 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3510 }
3511
3512 for (i = 0; i < info->num_outputs; i++) {
3513 int param;
3514
3515 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3516 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3517 continue;
3518
3519 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3520 info->output_semantic_index[i], false);
3521
3522 for (chan = 0; chan < 4; chan++) {
3523 if (!(info->output_usagemask[i] & (1 << chan)))
3524 continue;
3525
3526 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3527 out_val = ac_to_integer(&ctx->ac, out_val);
3528
3529 /* GFX9 has the ESGS ring in LDS. */
3530 if (ctx->screen->info.chip_class >= GFX9) {
3531 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3532 continue;
3533 }
3534
3535 ac_build_buffer_store_dword(&ctx->ac,
3536 ctx->esgs_ring,
3537 out_val, 1, NULL, soffset,
3538 (4 * param + chan) * 4,
3539 1, 1, true, true);
3540 }
3541 }
3542
3543 if (ctx->screen->info.chip_class >= GFX9)
3544 si_set_es_return_value_for_gs(ctx);
3545 }
3546
3547 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3548 {
3549 if (ctx->screen->info.chip_class >= GFX9)
3550 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3551 else
3552 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3553 }
3554
3555 static void emit_gs_epilogue(struct si_shader_context *ctx)
3556 {
3557 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3558 si_get_gs_wave_id(ctx));
3559
3560 if (ctx->screen->info.chip_class >= GFX9)
3561 lp_build_endif(&ctx->merged_wrap_if_state);
3562 }
3563
3564 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3565 unsigned max_outputs,
3566 LLVMValueRef *addrs)
3567 {
3568 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3569 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3570
3571 assert(info->num_outputs <= max_outputs);
3572
3573 emit_gs_epilogue(ctx);
3574 }
3575
3576 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3577 {
3578 struct si_shader_context *ctx = si_shader_context(bld_base);
3579 emit_gs_epilogue(ctx);
3580 }
3581
3582 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3583 unsigned max_outputs,
3584 LLVMValueRef *addrs)
3585 {
3586 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3587 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3588 struct si_shader_output_values *outputs = NULL;
3589 int i,j;
3590
3591 assert(!ctx->shader->is_gs_copy_shader);
3592 assert(info->num_outputs <= max_outputs);
3593
3594 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3595
3596 /* Vertex color clamping.
3597 *
3598 * This uses a state constant loaded in a user data SGPR and
3599 * an IF statement is added that clamps all colors if the constant
3600 * is true.
3601 */
3602 struct lp_build_if_state if_ctx;
3603 LLVMValueRef cond = NULL;
3604 LLVMValueRef addr, val;
3605
3606 for (i = 0; i < info->num_outputs; i++) {
3607 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3608 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3609 continue;
3610
3611 /* We've found a color. */
3612 if (!cond) {
3613 /* The state is in the first bit of the user SGPR. */
3614 cond = LLVMGetParam(ctx->main_fn,
3615 ctx->param_vs_state_bits);
3616 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3617 ctx->i1, "");
3618 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3619 }
3620
3621 for (j = 0; j < 4; j++) {
3622 addr = addrs[4 * i + j];
3623 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3624 val = ac_build_clamp(&ctx->ac, val);
3625 LLVMBuildStore(ctx->ac.builder, val, addr);
3626 }
3627 }
3628
3629 if (cond)
3630 lp_build_endif(&if_ctx);
3631
3632 for (i = 0; i < info->num_outputs; i++) {
3633 outputs[i].semantic_name = info->output_semantic_name[i];
3634 outputs[i].semantic_index = info->output_semantic_index[i];
3635
3636 for (j = 0; j < 4; j++) {
3637 outputs[i].values[j] =
3638 LLVMBuildLoad(ctx->ac.builder,
3639 addrs[4 * i + j],
3640 "");
3641 outputs[i].vertex_stream[j] =
3642 (info->output_streams[i] >> (2 * j)) & 3;
3643 }
3644 }
3645
3646 if (ctx->shader->selector->so.num_outputs)
3647 si_llvm_emit_streamout(ctx, outputs, i, 0);
3648
3649 /* Export PrimitiveID. */
3650 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3651 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3652 outputs[i].semantic_index = 0;
3653 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3654 for (j = 1; j < 4; j++)
3655 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3656
3657 memset(outputs[i].vertex_stream, 0,
3658 sizeof(outputs[i].vertex_stream));
3659 i++;
3660 }
3661
3662 si_llvm_export_vs(ctx, outputs, i);
3663 FREE(outputs);
3664 }
3665
3666 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3667 {
3668 struct si_shader_context *ctx = si_shader_context(bld_base);
3669
3670 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3671 &ctx->outputs[0][0]);
3672 }
3673
3674 struct si_ps_exports {
3675 unsigned num;
3676 struct ac_export_args args[10];
3677 };
3678
3679 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3680 LLVMValueRef depth, LLVMValueRef stencil,
3681 LLVMValueRef samplemask, struct si_ps_exports *exp)
3682 {
3683 struct si_shader_context *ctx = si_shader_context(bld_base);
3684 struct ac_export_args args;
3685
3686 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3687
3688 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3689 }
3690
3691 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3692 LLVMValueRef *color, unsigned index,
3693 unsigned samplemask_param,
3694 bool is_last, struct si_ps_exports *exp)
3695 {
3696 struct si_shader_context *ctx = si_shader_context(bld_base);
3697 int i;
3698
3699 /* Clamp color */
3700 if (ctx->shader->key.part.ps.epilog.clamp_color)
3701 for (i = 0; i < 4; i++)
3702 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3703
3704 /* Alpha to one */
3705 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3706 color[3] = ctx->ac.f32_1;
3707
3708 /* Alpha test */
3709 if (index == 0 &&
3710 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3711 si_alpha_test(bld_base, color[3]);
3712
3713 /* Line & polygon smoothing */
3714 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3715 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3716 samplemask_param);
3717
3718 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3719 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3720 struct ac_export_args args[8];
3721 int c, last = -1;
3722
3723 /* Get the export arguments, also find out what the last one is. */
3724 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3725 si_llvm_init_export_args(ctx, color,
3726 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3727 if (args[c].enabled_channels)
3728 last = c;
3729 }
3730
3731 /* Emit all exports. */
3732 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3733 if (is_last && last == c) {
3734 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3735 args[c].done = 1; /* DONE bit */
3736 } else if (!args[c].enabled_channels)
3737 continue; /* unnecessary NULL export */
3738
3739 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3740 }
3741 } else {
3742 struct ac_export_args args;
3743
3744 /* Export */
3745 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3746 &args);
3747 if (is_last) {
3748 args.valid_mask = 1; /* whether the EXEC mask is valid */
3749 args.done = 1; /* DONE bit */
3750 } else if (!args.enabled_channels)
3751 return; /* unnecessary NULL export */
3752
3753 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3754 }
3755 }
3756
3757 static void si_emit_ps_exports(struct si_shader_context *ctx,
3758 struct si_ps_exports *exp)
3759 {
3760 for (unsigned i = 0; i < exp->num; i++)
3761 ac_build_export(&ctx->ac, &exp->args[i]);
3762 }
3763
3764 /**
3765 * Return PS outputs in this order:
3766 *
3767 * v[0:3] = color0.xyzw
3768 * v[4:7] = color1.xyzw
3769 * ...
3770 * vN+0 = Depth
3771 * vN+1 = Stencil
3772 * vN+2 = SampleMask
3773 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3774 *
3775 * The alpha-ref SGPR is returned via its original location.
3776 */
3777 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3778 unsigned max_outputs,
3779 LLVMValueRef *addrs)
3780 {
3781 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3782 struct si_shader *shader = ctx->shader;
3783 struct tgsi_shader_info *info = &shader->selector->info;
3784 LLVMBuilderRef builder = ctx->ac.builder;
3785 unsigned i, j, first_vgpr, vgpr;
3786
3787 LLVMValueRef color[8][4] = {};
3788 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3789 LLVMValueRef ret;
3790
3791 if (ctx->postponed_kill)
3792 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3793
3794 /* Read the output values. */
3795 for (i = 0; i < info->num_outputs; i++) {
3796 unsigned semantic_name = info->output_semantic_name[i];
3797 unsigned semantic_index = info->output_semantic_index[i];
3798
3799 switch (semantic_name) {
3800 case TGSI_SEMANTIC_COLOR:
3801 assert(semantic_index < 8);
3802 for (j = 0; j < 4; j++) {
3803 LLVMValueRef ptr = addrs[4 * i + j];
3804 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3805 color[semantic_index][j] = result;
3806 }
3807 break;
3808 case TGSI_SEMANTIC_POSITION:
3809 depth = LLVMBuildLoad(builder,
3810 addrs[4 * i + 2], "");
3811 break;
3812 case TGSI_SEMANTIC_STENCIL:
3813 stencil = LLVMBuildLoad(builder,
3814 addrs[4 * i + 1], "");
3815 break;
3816 case TGSI_SEMANTIC_SAMPLEMASK:
3817 samplemask = LLVMBuildLoad(builder,
3818 addrs[4 * i + 0], "");
3819 break;
3820 default:
3821 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3822 semantic_name);
3823 }
3824 }
3825
3826 /* Fill the return structure. */
3827 ret = ctx->return_value;
3828
3829 /* Set SGPRs. */
3830 ret = LLVMBuildInsertValue(builder, ret,
3831 ac_to_integer(&ctx->ac,
3832 LLVMGetParam(ctx->main_fn,
3833 SI_PARAM_ALPHA_REF)),
3834 SI_SGPR_ALPHA_REF, "");
3835
3836 /* Set VGPRs */
3837 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3838 for (i = 0; i < ARRAY_SIZE(color); i++) {
3839 if (!color[i][0])
3840 continue;
3841
3842 for (j = 0; j < 4; j++)
3843 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3844 }
3845 if (depth)
3846 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3847 if (stencil)
3848 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3849 if (samplemask)
3850 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3851
3852 /* Add the input sample mask for smoothing at the end. */
3853 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3854 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3855 ret = LLVMBuildInsertValue(builder, ret,
3856 LLVMGetParam(ctx->main_fn,
3857 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3858
3859 ctx->return_value = ret;
3860 }
3861
3862 static void membar_emit(
3863 const struct lp_build_tgsi_action *action,
3864 struct lp_build_tgsi_context *bld_base,
3865 struct lp_build_emit_data *emit_data)
3866 {
3867 struct si_shader_context *ctx = si_shader_context(bld_base);
3868 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3869 unsigned flags = LLVMConstIntGetZExtValue(src0);
3870 unsigned waitcnt = NOOP_WAITCNT;
3871
3872 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3873 waitcnt &= VM_CNT & LGKM_CNT;
3874
3875 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3876 TGSI_MEMBAR_SHADER_BUFFER |
3877 TGSI_MEMBAR_SHADER_IMAGE))
3878 waitcnt &= VM_CNT;
3879
3880 if (flags & TGSI_MEMBAR_SHARED)
3881 waitcnt &= LGKM_CNT;
3882
3883 if (waitcnt != NOOP_WAITCNT)
3884 ac_build_waitcnt(&ctx->ac, waitcnt);
3885 }
3886
3887 static void clock_emit(
3888 const struct lp_build_tgsi_action *action,
3889 struct lp_build_tgsi_context *bld_base,
3890 struct lp_build_emit_data *emit_data)
3891 {
3892 struct si_shader_context *ctx = si_shader_context(bld_base);
3893 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3894
3895 emit_data->output[0] =
3896 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3897 emit_data->output[1] =
3898 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3899 }
3900
3901 static void si_llvm_emit_ddxy(
3902 const struct lp_build_tgsi_action *action,
3903 struct lp_build_tgsi_context *bld_base,
3904 struct lp_build_emit_data *emit_data)
3905 {
3906 struct si_shader_context *ctx = si_shader_context(bld_base);
3907 unsigned opcode = emit_data->info->opcode;
3908 LLVMValueRef val;
3909 int idx;
3910 unsigned mask;
3911
3912 if (opcode == TGSI_OPCODE_DDX_FINE)
3913 mask = AC_TID_MASK_LEFT;
3914 else if (opcode == TGSI_OPCODE_DDY_FINE)
3915 mask = AC_TID_MASK_TOP;
3916 else
3917 mask = AC_TID_MASK_TOP_LEFT;
3918
3919 /* for DDX we want to next X pixel, DDY next Y pixel. */
3920 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3921
3922 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3923 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3924 emit_data->output[emit_data->chan] = val;
3925 }
3926
3927 /*
3928 * this takes an I,J coordinate pair,
3929 * and works out the X and Y derivatives.
3930 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3931 */
3932 static LLVMValueRef si_llvm_emit_ddxy_interp(
3933 struct lp_build_tgsi_context *bld_base,
3934 LLVMValueRef interp_ij)
3935 {
3936 struct si_shader_context *ctx = si_shader_context(bld_base);
3937 LLVMValueRef result[4], a;
3938 unsigned i;
3939
3940 for (i = 0; i < 2; i++) {
3941 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3942 LLVMConstInt(ctx->i32, i, 0), "");
3943 result[i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 1,
3944 ac_to_integer(&ctx->ac, a)); /* DDX */
3945 result[2+i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 2,
3946 ac_to_integer(&ctx->ac, a)); /* DDY */
3947 }
3948
3949 return ac_build_gather_values(&ctx->ac, result, 4);
3950 }
3951
3952 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3953 struct lp_build_tgsi_context *bld_base,
3954 struct lp_build_emit_data *emit_data)
3955 {
3956 struct si_shader_context *ctx = si_shader_context(bld_base);
3957 struct si_shader *shader = ctx->shader;
3958 const struct tgsi_shader_info *info = &shader->selector->info;
3959 LLVMValueRef interp_param;
3960 const struct tgsi_full_instruction *inst = emit_data->inst;
3961 const struct tgsi_full_src_register *input = &inst->Src[0];
3962 int input_base, input_array_size;
3963 int chan;
3964 int i;
3965 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3966 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3967 int interp_param_idx;
3968 unsigned interp;
3969 unsigned location;
3970
3971 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3972 /* offset is in second src, first two channels */
3973 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3974 TGSI_CHAN_X);
3975 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3976 TGSI_CHAN_Y);
3977 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3978 LLVMValueRef sample_position;
3979 LLVMValueRef sample_id;
3980 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3981
3982 /* fetch sample ID, then fetch its sample position,
3983 * and place into first two channels.
3984 */
3985 sample_id = lp_build_emit_fetch(bld_base,
3986 emit_data->inst, 1, TGSI_CHAN_X);
3987 sample_id = ac_to_integer(&ctx->ac, sample_id);
3988
3989 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3990 * Language 4.50 spec says about interpolateAtSample:
3991 *
3992 * "Returns the value of the input interpolant variable at
3993 * the location of sample number sample. If multisample
3994 * buffers are not available, the input variable will be
3995 * evaluated at the center of the pixel. If sample sample
3996 * does not exist, the position used to interpolate the
3997 * input variable is undefined."
3998 *
3999 * This means that sample_id values outside of the valid are
4000 * in fact valid input, and the usual mechanism for loading the
4001 * sample position doesn't work.
4002 */
4003 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4004 LLVMValueRef center[4] = {
4005 LLVMConstReal(ctx->f32, 0.5),
4006 LLVMConstReal(ctx->f32, 0.5),
4007 ctx->ac.f32_0,
4008 ctx->ac.f32_0,
4009 };
4010
4011 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4012 } else {
4013 sample_position = load_sample_position(&ctx->abi, sample_id);
4014 }
4015
4016 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4017 ctx->i32_0, "");
4018
4019 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4020 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4021 ctx->i32_1, "");
4022 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4023 }
4024
4025 assert(input->Register.File == TGSI_FILE_INPUT);
4026
4027 if (input->Register.Indirect) {
4028 unsigned array_id = input->Indirect.ArrayID;
4029
4030 if (array_id) {
4031 input_base = info->input_array_first[array_id];
4032 input_array_size = info->input_array_last[array_id] - input_base + 1;
4033 } else {
4034 input_base = inst->Src[0].Register.Index;
4035 input_array_size = info->num_inputs - input_base;
4036 }
4037
4038 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4039 1, input->Register.Index - input_base);
4040 } else {
4041 input_base = inst->Src[0].Register.Index;
4042 input_array_size = 1;
4043 array_idx = ctx->i32_0;
4044 }
4045
4046 interp = shader->selector->info.input_interpolate[input_base];
4047
4048 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4049 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4050 location = TGSI_INTERPOLATE_LOC_CENTER;
4051 else
4052 location = TGSI_INTERPOLATE_LOC_CENTROID;
4053
4054 interp_param_idx = lookup_interp_param_index(interp, location);
4055 if (interp_param_idx == -1)
4056 return;
4057 else if (interp_param_idx)
4058 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4059 else
4060 interp_param = NULL;
4061
4062 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4063 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4064 LLVMValueRef ij_out[2];
4065 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4066
4067 /*
4068 * take the I then J parameters, and the DDX/Y for it, and
4069 * calculate the IJ inputs for the interpolator.
4070 * temp1 = ddx * offset/sample.x + I;
4071 * interp_param.I = ddy * offset/sample.y + temp1;
4072 * temp1 = ddx * offset/sample.x + J;
4073 * interp_param.J = ddy * offset/sample.y + temp1;
4074 */
4075 for (i = 0; i < 2; i++) {
4076 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4077 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4078 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4079 ddxy_out, ix_ll, "");
4080 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4081 ddxy_out, iy_ll, "");
4082 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4083 interp_param, ix_ll, "");
4084 LLVMValueRef temp;
4085
4086 interp_el = ac_to_float(&ctx->ac, interp_el);
4087
4088 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4089 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4090 }
4091 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4092 }
4093
4094 if (interp_param)
4095 interp_param = ac_to_float(&ctx->ac, interp_param);
4096
4097 for (chan = 0; chan < 4; chan++) {
4098 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4099 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4100
4101 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4102 LLVMValueRef v, i = NULL, j = NULL;
4103
4104 if (interp_param) {
4105 i = LLVMBuildExtractElement(
4106 ctx->ac.builder, interp_param, ctx->i32_0, "");
4107 j = LLVMBuildExtractElement(
4108 ctx->ac.builder, interp_param, ctx->i32_1, "");
4109 }
4110 v = si_build_fs_interp(ctx, input_base + idx, schan,
4111 prim_mask, i, j);
4112
4113 gather = LLVMBuildInsertElement(ctx->ac.builder,
4114 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4115 }
4116
4117 emit_data->output[chan] = LLVMBuildExtractElement(
4118 ctx->ac.builder, gather, array_idx, "");
4119 }
4120 }
4121
4122 static void vote_all_emit(
4123 const struct lp_build_tgsi_action *action,
4124 struct lp_build_tgsi_context *bld_base,
4125 struct lp_build_emit_data *emit_data)
4126 {
4127 struct si_shader_context *ctx = si_shader_context(bld_base);
4128
4129 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4130 emit_data->output[emit_data->chan] =
4131 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4132 }
4133
4134 static void vote_any_emit(
4135 const struct lp_build_tgsi_action *action,
4136 struct lp_build_tgsi_context *bld_base,
4137 struct lp_build_emit_data *emit_data)
4138 {
4139 struct si_shader_context *ctx = si_shader_context(bld_base);
4140
4141 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4142 emit_data->output[emit_data->chan] =
4143 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4144 }
4145
4146 static void vote_eq_emit(
4147 const struct lp_build_tgsi_action *action,
4148 struct lp_build_tgsi_context *bld_base,
4149 struct lp_build_emit_data *emit_data)
4150 {
4151 struct si_shader_context *ctx = si_shader_context(bld_base);
4152
4153 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4154 emit_data->output[emit_data->chan] =
4155 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4156 }
4157
4158 static void ballot_emit(
4159 const struct lp_build_tgsi_action *action,
4160 struct lp_build_tgsi_context *bld_base,
4161 struct lp_build_emit_data *emit_data)
4162 {
4163 struct si_shader_context *ctx = si_shader_context(bld_base);
4164 LLVMBuilderRef builder = ctx->ac.builder;
4165 LLVMValueRef tmp;
4166
4167 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4168 tmp = ac_build_ballot(&ctx->ac, tmp);
4169 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4170
4171 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4172 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4173 }
4174
4175 static void read_lane_emit(
4176 const struct lp_build_tgsi_action *action,
4177 struct lp_build_tgsi_context *bld_base,
4178 struct lp_build_emit_data *emit_data)
4179 {
4180 struct si_shader_context *ctx = si_shader_context(bld_base);
4181
4182 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4183 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4184 0, emit_data->src_chan);
4185
4186 /* Always read the source invocation (= lane) from the X channel. */
4187 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4188 1, TGSI_CHAN_X);
4189 emit_data->arg_count = 2;
4190 }
4191
4192 /* We currently have no other way to prevent LLVM from lifting the icmp
4193 * calls to a dominating basic block.
4194 */
4195 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4196
4197 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4198 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4199
4200 emit_data->output[emit_data->chan] =
4201 ac_build_intrinsic(&ctx->ac, action->intr_name,
4202 ctx->i32, emit_data->args, emit_data->arg_count,
4203 AC_FUNC_ATTR_READNONE |
4204 AC_FUNC_ATTR_CONVERGENT);
4205 }
4206
4207 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4208 struct lp_build_emit_data *emit_data)
4209 {
4210 struct si_shader_context *ctx = si_shader_context(bld_base);
4211 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4212 LLVMValueRef imm;
4213 unsigned stream;
4214
4215 assert(src0.File == TGSI_FILE_IMMEDIATE);
4216
4217 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4218 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4219 return stream;
4220 }
4221
4222 /* Emit one vertex from the geometry shader */
4223 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4224 unsigned stream,
4225 LLVMValueRef *addrs)
4226 {
4227 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4228 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4229 struct si_shader *shader = ctx->shader;
4230 struct lp_build_if_state if_state;
4231 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4232 ctx->param_gs2vs_offset);
4233 LLVMValueRef gs_next_vertex;
4234 LLVMValueRef can_emit;
4235 unsigned chan, offset;
4236 int i;
4237
4238 /* Write vertex attribute values to GSVS ring */
4239 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4240 ctx->gs_next_vertex[stream],
4241 "");
4242
4243 /* If this thread has already emitted the declared maximum number of
4244 * vertices, skip the write: excessive vertex emissions are not
4245 * supposed to have any effect.
4246 *
4247 * If the shader has no writes to memory, kill it instead. This skips
4248 * further memory loads and may allow LLVM to skip to the end
4249 * altogether.
4250 */
4251 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4252 LLVMConstInt(ctx->i32,
4253 shader->selector->gs_max_out_vertices, 0), "");
4254
4255 bool use_kill = !info->writes_memory;
4256 if (use_kill) {
4257 ac_build_kill_if_false(&ctx->ac, can_emit);
4258 } else {
4259 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4260 }
4261
4262 offset = 0;
4263 for (i = 0; i < info->num_outputs; i++) {
4264 for (chan = 0; chan < 4; chan++) {
4265 if (!(info->output_usagemask[i] & (1 << chan)) ||
4266 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4267 continue;
4268
4269 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4270 LLVMValueRef voffset =
4271 LLVMConstInt(ctx->i32, offset *
4272 shader->selector->gs_max_out_vertices, 0);
4273 offset++;
4274
4275 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4276 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4277 LLVMConstInt(ctx->i32, 4, 0), "");
4278
4279 out_val = ac_to_integer(&ctx->ac, out_val);
4280
4281 ac_build_buffer_store_dword(&ctx->ac,
4282 ctx->gsvs_ring[stream],
4283 out_val, 1,
4284 voffset, soffset, 0,
4285 1, 1, true, true);
4286 }
4287 }
4288
4289 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4290 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4291
4292 /* Signal vertex emission if vertex data was written. */
4293 if (offset) {
4294 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4295 si_get_gs_wave_id(ctx));
4296 }
4297
4298 if (!use_kill)
4299 lp_build_endif(&if_state);
4300 }
4301
4302 /* Emit one vertex from the geometry shader */
4303 static void si_tgsi_emit_vertex(
4304 const struct lp_build_tgsi_action *action,
4305 struct lp_build_tgsi_context *bld_base,
4306 struct lp_build_emit_data *emit_data)
4307 {
4308 struct si_shader_context *ctx = si_shader_context(bld_base);
4309 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4310
4311 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4312 }
4313
4314 /* Cut one primitive from the geometry shader */
4315 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4316 unsigned stream)
4317 {
4318 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4319
4320 /* Signal primitive cut */
4321 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4322 si_get_gs_wave_id(ctx));
4323 }
4324
4325 /* Cut one primitive from the geometry shader */
4326 static void si_tgsi_emit_primitive(
4327 const struct lp_build_tgsi_action *action,
4328 struct lp_build_tgsi_context *bld_base,
4329 struct lp_build_emit_data *emit_data)
4330 {
4331 struct si_shader_context *ctx = si_shader_context(bld_base);
4332
4333 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4334 }
4335
4336 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4337 struct lp_build_tgsi_context *bld_base,
4338 struct lp_build_emit_data *emit_data)
4339 {
4340 struct si_shader_context *ctx = si_shader_context(bld_base);
4341
4342 /* SI only (thanks to a hw bug workaround):
4343 * The real barrier instruction isn’t needed, because an entire patch
4344 * always fits into a single wave.
4345 */
4346 if (ctx->screen->info.chip_class == SI &&
4347 ctx->type == PIPE_SHADER_TESS_CTRL) {
4348 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4349 return;
4350 }
4351
4352 ac_build_s_barrier(&ctx->ac);
4353 }
4354
4355 static void si_create_function(struct si_shader_context *ctx,
4356 const char *name,
4357 LLVMTypeRef *returns, unsigned num_returns,
4358 struct si_function_info *fninfo,
4359 unsigned max_workgroup_size)
4360 {
4361 int i;
4362
4363 si_llvm_create_func(ctx, name, returns, num_returns,
4364 fninfo->types, fninfo->num_params);
4365 ctx->return_value = LLVMGetUndef(ctx->return_type);
4366
4367 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4368 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4369
4370 /* The combination of:
4371 * - noalias
4372 * - dereferenceable
4373 * - invariant.load
4374 * allows the optimization passes to move loads and reduces
4375 * SGPR spilling significantly.
4376 */
4377 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4378 AC_FUNC_ATTR_INREG);
4379
4380 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4381 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4382 AC_FUNC_ATTR_NOALIAS);
4383 ac_add_attr_dereferenceable(P, UINT64_MAX);
4384 }
4385 }
4386
4387 for (i = 0; i < fninfo->num_params; ++i) {
4388 if (fninfo->assign[i])
4389 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4390 }
4391
4392 if (ctx->screen->info.address32_hi) {
4393 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4394 "amdgpu-32bit-address-high-bits",
4395 ctx->screen->info.address32_hi);
4396 }
4397
4398 if (max_workgroup_size) {
4399 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4400 "amdgpu-max-work-group-size",
4401 max_workgroup_size);
4402 }
4403 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4404 "no-signed-zeros-fp-math",
4405 "true");
4406
4407 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4408 /* These were copied from some LLVM test. */
4409 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4410 "less-precise-fpmad",
4411 "true");
4412 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4413 "no-infs-fp-math",
4414 "true");
4415 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4416 "no-nans-fp-math",
4417 "true");
4418 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4419 "unsafe-fp-math",
4420 "true");
4421 }
4422 }
4423
4424 static void declare_streamout_params(struct si_shader_context *ctx,
4425 struct pipe_stream_output_info *so,
4426 struct si_function_info *fninfo)
4427 {
4428 int i;
4429
4430 /* Streamout SGPRs. */
4431 if (so->num_outputs) {
4432 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4433 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4434 else
4435 ctx->param_streamout_config = fninfo->num_params - 1;
4436
4437 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4438 }
4439 /* A streamout buffer offset is loaded if the stride is non-zero. */
4440 for (i = 0; i < 4; i++) {
4441 if (!so->stride[i])
4442 continue;
4443
4444 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4445 }
4446 }
4447
4448 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4449 {
4450 switch (shader->selector->type) {
4451 case PIPE_SHADER_TESS_CTRL:
4452 /* Return this so that LLVM doesn't remove s_barrier
4453 * instructions on chips where we use s_barrier. */
4454 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4455
4456 case PIPE_SHADER_GEOMETRY:
4457 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4458
4459 case PIPE_SHADER_COMPUTE:
4460 break; /* see below */
4461
4462 default:
4463 return 0;
4464 }
4465
4466 const unsigned *properties = shader->selector->info.properties;
4467 unsigned max_work_group_size =
4468 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4469 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4470 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4471
4472 if (!max_work_group_size) {
4473 /* This is a variable group size compute shader,
4474 * compile it for the maximum possible group size.
4475 */
4476 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4477 }
4478 return max_work_group_size;
4479 }
4480
4481 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4482 struct si_function_info *fninfo,
4483 bool assign_params)
4484 {
4485 LLVMTypeRef const_shader_buf_type;
4486
4487 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4488 ctx->shader->selector->info.shader_buffers_declared == 0)
4489 const_shader_buf_type = ctx->f32;
4490 else
4491 const_shader_buf_type = ctx->v4i32;
4492
4493 unsigned const_and_shader_buffers =
4494 add_arg(fninfo, ARG_SGPR,
4495 ac_array_in_const32_addr_space(const_shader_buf_type));
4496
4497 if (assign_params)
4498 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4499 }
4500
4501 static void declare_samplers_and_images(struct si_shader_context *ctx,
4502 struct si_function_info *fninfo,
4503 bool assign_params)
4504 {
4505 unsigned samplers_and_images =
4506 add_arg(fninfo, ARG_SGPR,
4507 ac_array_in_const32_addr_space(ctx->v8i32));
4508
4509 if (assign_params)
4510 ctx->param_samplers_and_images = samplers_and_images;
4511 }
4512
4513 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4514 struct si_function_info *fninfo,
4515 bool assign_params)
4516 {
4517 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4518 declare_samplers_and_images(ctx, fninfo, assign_params);
4519 }
4520
4521 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4522 struct si_function_info *fninfo)
4523 {
4524 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4525 ac_array_in_const32_addr_space(ctx->v4i32));
4526 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4527 ac_array_in_const32_addr_space(ctx->v8i32));
4528 }
4529
4530 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4531 struct si_function_info *fninfo)
4532 {
4533 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4534 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4535 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4536 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4537 }
4538
4539 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4540 struct si_function_info *fninfo,
4541 unsigned *num_prolog_vgprs)
4542 {
4543 struct si_shader *shader = ctx->shader;
4544
4545 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4546 if (shader->key.as_ls) {
4547 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4548 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4549 } else {
4550 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4551 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4552 }
4553 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4554
4555 if (!shader->is_gs_copy_shader) {
4556 /* Vertex load indices. */
4557 ctx->param_vertex_index0 = fninfo->num_params;
4558 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4559 add_arg(fninfo, ARG_VGPR, ctx->i32);
4560 *num_prolog_vgprs += shader->selector->info.num_inputs;
4561 }
4562 }
4563
4564 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4565 struct si_function_info *fninfo,
4566 unsigned vs_blit_property)
4567 {
4568 ctx->param_vs_blit_inputs = fninfo->num_params;
4569 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4570 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4571 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4572
4573 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4574 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4575 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4576 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4577 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4578 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4579 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4580 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4581 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4582 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4583 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4584 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4585 }
4586 }
4587
4588 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4589 struct si_function_info *fninfo)
4590 {
4591 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4592 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4593 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4594 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4595 }
4596
4597 enum {
4598 /* Convenient merged shader definitions. */
4599 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4600 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4601 };
4602
4603 static void create_function(struct si_shader_context *ctx)
4604 {
4605 struct si_shader *shader = ctx->shader;
4606 struct si_function_info fninfo;
4607 LLVMTypeRef returns[16+32*4];
4608 unsigned i, num_return_sgprs;
4609 unsigned num_returns = 0;
4610 unsigned num_prolog_vgprs = 0;
4611 unsigned type = ctx->type;
4612 unsigned vs_blit_property =
4613 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4614
4615 si_init_function_info(&fninfo);
4616
4617 /* Set MERGED shaders. */
4618 if (ctx->screen->info.chip_class >= GFX9) {
4619 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4620 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4621 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4622 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4623 }
4624
4625 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4626
4627 switch (type) {
4628 case PIPE_SHADER_VERTEX:
4629 declare_global_desc_pointers(ctx, &fninfo);
4630
4631 if (vs_blit_property) {
4632 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4633
4634 /* VGPRs */
4635 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4636 break;
4637 }
4638
4639 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4640 declare_vs_specific_input_sgprs(ctx, &fninfo);
4641 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4642 ac_array_in_const32_addr_space(ctx->v4i32));
4643
4644 if (shader->key.as_es) {
4645 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4646 } else if (shader->key.as_ls) {
4647 /* no extra parameters */
4648 } else {
4649 if (shader->is_gs_copy_shader) {
4650 fninfo.num_params = ctx->param_vs_state_bits + 1;
4651 fninfo.num_sgpr_params = fninfo.num_params;
4652 }
4653
4654 /* The locations of the other parameters are assigned dynamically. */
4655 declare_streamout_params(ctx, &shader->selector->so,
4656 &fninfo);
4657 }
4658
4659 /* VGPRs */
4660 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4661 break;
4662
4663 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4664 declare_global_desc_pointers(ctx, &fninfo);
4665 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4666 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4667 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4668 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4669 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4670 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4671 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4672
4673 /* VGPRs */
4674 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4675 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4676
4677 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4678 * placed after the user SGPRs.
4679 */
4680 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4681 returns[num_returns++] = ctx->i32; /* SGPRs */
4682 for (i = 0; i < 11; i++)
4683 returns[num_returns++] = ctx->f32; /* VGPRs */
4684 break;
4685
4686 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4687 /* Merged stages have 8 system SGPRs at the beginning. */
4688 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4689 declare_per_stage_desc_pointers(ctx, &fninfo,
4690 ctx->type == PIPE_SHADER_TESS_CTRL);
4691 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4692 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4693 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4694 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4695 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4696 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4697
4698 declare_global_desc_pointers(ctx, &fninfo);
4699 declare_per_stage_desc_pointers(ctx, &fninfo,
4700 ctx->type == PIPE_SHADER_VERTEX);
4701 declare_vs_specific_input_sgprs(ctx, &fninfo);
4702
4703 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4704 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4705 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4706 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4707 ac_array_in_const32_addr_space(ctx->v4i32));
4708
4709 /* VGPRs (first TCS, then VS) */
4710 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4711 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4712
4713 if (ctx->type == PIPE_SHADER_VERTEX) {
4714 declare_vs_input_vgprs(ctx, &fninfo,
4715 &num_prolog_vgprs);
4716
4717 /* LS return values are inputs to the TCS main shader part. */
4718 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4719 returns[num_returns++] = ctx->i32; /* SGPRs */
4720 for (i = 0; i < 2; i++)
4721 returns[num_returns++] = ctx->f32; /* VGPRs */
4722 } else {
4723 /* TCS return values are inputs to the TCS epilog.
4724 *
4725 * param_tcs_offchip_offset, param_tcs_factor_offset,
4726 * param_tcs_offchip_layout, and param_rw_buffers
4727 * should be passed to the epilog.
4728 */
4729 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4730 returns[num_returns++] = ctx->i32; /* SGPRs */
4731 for (i = 0; i < 11; i++)
4732 returns[num_returns++] = ctx->f32; /* VGPRs */
4733 }
4734 break;
4735
4736 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4737 /* Merged stages have 8 system SGPRs at the beginning. */
4738 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4739 declare_per_stage_desc_pointers(ctx, &fninfo,
4740 ctx->type == PIPE_SHADER_GEOMETRY);
4741 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4742 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4745 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4746 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4747
4748 declare_global_desc_pointers(ctx, &fninfo);
4749 declare_per_stage_desc_pointers(ctx, &fninfo,
4750 (ctx->type == PIPE_SHADER_VERTEX ||
4751 ctx->type == PIPE_SHADER_TESS_EVAL));
4752 if (ctx->type == PIPE_SHADER_VERTEX) {
4753 declare_vs_specific_input_sgprs(ctx, &fninfo);
4754 } else {
4755 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4756 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4757 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4758 /* Declare as many input SGPRs as the VS has. */
4759 }
4760
4761 if (ctx->type == PIPE_SHADER_VERTEX) {
4762 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4763 ac_array_in_const32_addr_space(ctx->v4i32));
4764 }
4765
4766 /* VGPRs (first GS, then VS/TES) */
4767 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4768 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4769 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4770 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4771 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4772
4773 if (ctx->type == PIPE_SHADER_VERTEX) {
4774 declare_vs_input_vgprs(ctx, &fninfo,
4775 &num_prolog_vgprs);
4776 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4777 declare_tes_input_vgprs(ctx, &fninfo);
4778 }
4779
4780 if (ctx->type == PIPE_SHADER_VERTEX ||
4781 ctx->type == PIPE_SHADER_TESS_EVAL) {
4782 unsigned num_user_sgprs;
4783
4784 if (ctx->type == PIPE_SHADER_VERTEX)
4785 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4786 else
4787 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4788
4789 /* ES return values are inputs to GS. */
4790 for (i = 0; i < 8 + num_user_sgprs; i++)
4791 returns[num_returns++] = ctx->i32; /* SGPRs */
4792 for (i = 0; i < 5; i++)
4793 returns[num_returns++] = ctx->f32; /* VGPRs */
4794 }
4795 break;
4796
4797 case PIPE_SHADER_TESS_EVAL:
4798 declare_global_desc_pointers(ctx, &fninfo);
4799 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4800 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4801 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4802 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4803
4804 if (shader->key.as_es) {
4805 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4806 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4807 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4808 } else {
4809 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4810 declare_streamout_params(ctx, &shader->selector->so,
4811 &fninfo);
4812 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4813 }
4814
4815 /* VGPRs */
4816 declare_tes_input_vgprs(ctx, &fninfo);
4817 break;
4818
4819 case PIPE_SHADER_GEOMETRY:
4820 declare_global_desc_pointers(ctx, &fninfo);
4821 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4822 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4823 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4824
4825 /* VGPRs */
4826 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4827 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4828 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4829 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4830 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4831 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4832 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4833 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4834 break;
4835
4836 case PIPE_SHADER_FRAGMENT:
4837 declare_global_desc_pointers(ctx, &fninfo);
4838 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4839 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4840 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4841 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4842
4843 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4844 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4845 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4846 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4847 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4848 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4849 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4850 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4851 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4852 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4853 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4854 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4855 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4856 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4857 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4858 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4859 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4860 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4861 shader->info.face_vgpr_index = 20;
4862 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4863 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4864 shader->info.ancillary_vgpr_index = 21;
4865 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4866 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4867 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4868
4869 /* Color inputs from the prolog. */
4870 if (shader->selector->info.colors_read) {
4871 unsigned num_color_elements =
4872 util_bitcount(shader->selector->info.colors_read);
4873
4874 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4875 for (i = 0; i < num_color_elements; i++)
4876 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4877
4878 num_prolog_vgprs += num_color_elements;
4879 }
4880
4881 /* Outputs for the epilog. */
4882 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4883 num_returns =
4884 num_return_sgprs +
4885 util_bitcount(shader->selector->info.colors_written) * 4 +
4886 shader->selector->info.writes_z +
4887 shader->selector->info.writes_stencil +
4888 shader->selector->info.writes_samplemask +
4889 1 /* SampleMaskIn */;
4890
4891 num_returns = MAX2(num_returns,
4892 num_return_sgprs +
4893 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4894
4895 for (i = 0; i < num_return_sgprs; i++)
4896 returns[i] = ctx->i32;
4897 for (; i < num_returns; i++)
4898 returns[i] = ctx->f32;
4899 break;
4900
4901 case PIPE_SHADER_COMPUTE:
4902 declare_global_desc_pointers(ctx, &fninfo);
4903 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4904 if (shader->selector->info.uses_grid_size)
4905 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4906 if (shader->selector->info.uses_block_size &&
4907 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4908 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4909
4910 unsigned cs_user_data_dwords =
4911 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4912 if (cs_user_data_dwords) {
4913 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4914 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4915 }
4916
4917 for (i = 0; i < 3; i++) {
4918 ctx->abi.workgroup_ids[i] = NULL;
4919 if (shader->selector->info.uses_block_id[i])
4920 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4921 }
4922
4923 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4924 break;
4925 default:
4926 assert(0 && "unimplemented shader");
4927 return;
4928 }
4929
4930 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4931 si_get_max_workgroup_size(shader));
4932
4933 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4934 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4935 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4936 "InitialPSInputAddr",
4937 S_0286D0_PERSP_SAMPLE_ENA(1) |
4938 S_0286D0_PERSP_CENTER_ENA(1) |
4939 S_0286D0_PERSP_CENTROID_ENA(1) |
4940 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4941 S_0286D0_LINEAR_CENTER_ENA(1) |
4942 S_0286D0_LINEAR_CENTROID_ENA(1) |
4943 S_0286D0_FRONT_FACE_ENA(1) |
4944 S_0286D0_ANCILLARY_ENA(1) |
4945 S_0286D0_POS_FIXED_PT_ENA(1));
4946 }
4947
4948 shader->info.num_input_sgprs = 0;
4949 shader->info.num_input_vgprs = 0;
4950
4951 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4952 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4953
4954 for (; i < fninfo.num_params; ++i)
4955 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4956
4957 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4958 shader->info.num_input_vgprs -= num_prolog_vgprs;
4959
4960 if (shader->key.as_ls ||
4961 ctx->type == PIPE_SHADER_TESS_CTRL ||
4962 /* GFX9 has the ESGS ring buffer in LDS. */
4963 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4964 ac_declare_lds_as_pointer(&ctx->ac);
4965 }
4966
4967 /**
4968 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4969 * for later use.
4970 */
4971 static void preload_ring_buffers(struct si_shader_context *ctx)
4972 {
4973 LLVMBuilderRef builder = ctx->ac.builder;
4974
4975 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4976 ctx->param_rw_buffers);
4977
4978 if (ctx->screen->info.chip_class <= VI &&
4979 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4980 unsigned ring =
4981 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4982 : SI_ES_RING_ESGS;
4983 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4984
4985 ctx->esgs_ring =
4986 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4987 }
4988
4989 if (ctx->shader->is_gs_copy_shader) {
4990 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4991
4992 ctx->gsvs_ring[0] =
4993 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4994 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4995 const struct si_shader_selector *sel = ctx->shader->selector;
4996 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4997 LLVMValueRef base_ring;
4998
4999 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5000
5001 /* The conceptual layout of the GSVS ring is
5002 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5003 * but the real memory layout is swizzled across
5004 * threads:
5005 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5006 * t16v0c0 ..
5007 * Override the buffer descriptor accordingly.
5008 */
5009 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5010 uint64_t stream_offset = 0;
5011
5012 for (unsigned stream = 0; stream < 4; ++stream) {
5013 unsigned num_components;
5014 unsigned stride;
5015 unsigned num_records;
5016 LLVMValueRef ring, tmp;
5017
5018 num_components = sel->info.num_stream_output_components[stream];
5019 if (!num_components)
5020 continue;
5021
5022 stride = 4 * num_components * sel->gs_max_out_vertices;
5023
5024 /* Limit on the stride field for <= CIK. */
5025 assert(stride < (1 << 14));
5026
5027 num_records = 64;
5028
5029 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5030 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5031 tmp = LLVMBuildAdd(builder, tmp,
5032 LLVMConstInt(ctx->i64,
5033 stream_offset, 0), "");
5034 stream_offset += stride * 64;
5035
5036 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5037 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5038 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5039 tmp = LLVMBuildOr(builder, tmp,
5040 LLVMConstInt(ctx->i32,
5041 S_008F04_STRIDE(stride) |
5042 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5043 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5044 ring = LLVMBuildInsertElement(builder, ring,
5045 LLVMConstInt(ctx->i32, num_records, 0),
5046 LLVMConstInt(ctx->i32, 2, 0), "");
5047 ring = LLVMBuildInsertElement(builder, ring,
5048 LLVMConstInt(ctx->i32,
5049 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5050 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5051 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5052 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5053 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5054 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5055 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5056 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5057 S_008F0C_ADD_TID_ENABLE(1),
5058 0),
5059 LLVMConstInt(ctx->i32, 3, 0), "");
5060
5061 ctx->gsvs_ring[stream] = ring;
5062 }
5063 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5064 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5065 }
5066 }
5067
5068 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5069 LLVMValueRef param_rw_buffers,
5070 unsigned param_pos_fixed_pt)
5071 {
5072 LLVMBuilderRef builder = ctx->ac.builder;
5073 LLVMValueRef slot, desc, offset, row, bit, address[2];
5074
5075 /* Use the fixed-point gl_FragCoord input.
5076 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5077 * per coordinate to get the repeating effect.
5078 */
5079 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5080 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5081
5082 /* Load the buffer descriptor. */
5083 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5084 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5085
5086 /* The stipple pattern is 32x32, each row has 32 bits. */
5087 offset = LLVMBuildMul(builder, address[1],
5088 LLVMConstInt(ctx->i32, 4, 0), "");
5089 row = buffer_load_const(ctx, desc, offset);
5090 row = ac_to_integer(&ctx->ac, row);
5091 bit = LLVMBuildLShr(builder, row, address[0], "");
5092 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5093 ac_build_kill_if_false(&ctx->ac, bit);
5094 }
5095
5096 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5097 struct si_shader_config *conf,
5098 unsigned symbol_offset)
5099 {
5100 unsigned i;
5101 const unsigned char *config =
5102 ac_shader_binary_config_start(binary, symbol_offset);
5103 bool really_needs_scratch = false;
5104
5105 /* LLVM adds SGPR spills to the scratch size.
5106 * Find out if we really need the scratch buffer.
5107 */
5108 for (i = 0; i < binary->reloc_count; i++) {
5109 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5110
5111 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5112 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5113 really_needs_scratch = true;
5114 break;
5115 }
5116 }
5117
5118 /* XXX: We may be able to emit some of these values directly rather than
5119 * extracting fields to be emitted later.
5120 */
5121
5122 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5123 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5124 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5125 switch (reg) {
5126 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5127 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5128 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5129 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5130 case R_00B848_COMPUTE_PGM_RSRC1:
5131 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5132 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5133 conf->float_mode = G_00B028_FLOAT_MODE(value);
5134 conf->rsrc1 = value;
5135 break;
5136 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5137 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5138 break;
5139 case R_00B84C_COMPUTE_PGM_RSRC2:
5140 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5141 conf->rsrc2 = value;
5142 break;
5143 case R_0286CC_SPI_PS_INPUT_ENA:
5144 conf->spi_ps_input_ena = value;
5145 break;
5146 case R_0286D0_SPI_PS_INPUT_ADDR:
5147 conf->spi_ps_input_addr = value;
5148 break;
5149 case R_0286E8_SPI_TMPRING_SIZE:
5150 case R_00B860_COMPUTE_TMPRING_SIZE:
5151 /* WAVESIZE is in units of 256 dwords. */
5152 if (really_needs_scratch)
5153 conf->scratch_bytes_per_wave =
5154 G_00B860_WAVESIZE(value) * 256 * 4;
5155 break;
5156 case 0x4: /* SPILLED_SGPRS */
5157 conf->spilled_sgprs = value;
5158 break;
5159 case 0x8: /* SPILLED_VGPRS */
5160 conf->spilled_vgprs = value;
5161 break;
5162 default:
5163 {
5164 static bool printed;
5165
5166 if (!printed) {
5167 fprintf(stderr, "Warning: LLVM emitted unknown "
5168 "config register: 0x%x\n", reg);
5169 printed = true;
5170 }
5171 }
5172 break;
5173 }
5174 }
5175
5176 if (!conf->spi_ps_input_addr)
5177 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5178 }
5179
5180 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5181 uint64_t scratch_va)
5182 {
5183 unsigned i;
5184 uint32_t scratch_rsrc_dword0 = scratch_va;
5185 uint32_t scratch_rsrc_dword1 =
5186 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5187
5188 /* Enable scratch coalescing. */
5189 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5190
5191 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5192 const struct ac_shader_reloc *reloc =
5193 &shader->binary.relocs[i];
5194 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5195 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5196 &scratch_rsrc_dword0, 4);
5197 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5198 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5199 &scratch_rsrc_dword1, 4);
5200 }
5201 }
5202 }
5203
5204 /* For the UMR disassembler. */
5205 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5206 #define DEBUGGER_NUM_MARKERS 5
5207
5208 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5209 {
5210 unsigned size = shader->binary.code_size;
5211
5212 if (shader->prolog)
5213 size += shader->prolog->binary.code_size;
5214 if (shader->previous_stage)
5215 size += shader->previous_stage->binary.code_size;
5216 if (shader->prolog2)
5217 size += shader->prolog2->binary.code_size;
5218 if (shader->epilog)
5219 size += shader->epilog->binary.code_size;
5220 return size + DEBUGGER_NUM_MARKERS * 4;
5221 }
5222
5223 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5224 {
5225 const struct ac_shader_binary *prolog =
5226 shader->prolog ? &shader->prolog->binary : NULL;
5227 const struct ac_shader_binary *previous_stage =
5228 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5229 const struct ac_shader_binary *prolog2 =
5230 shader->prolog2 ? &shader->prolog2->binary : NULL;
5231 const struct ac_shader_binary *epilog =
5232 shader->epilog ? &shader->epilog->binary : NULL;
5233 const struct ac_shader_binary *mainb = &shader->binary;
5234 unsigned bo_size = si_get_shader_binary_size(shader) +
5235 (!epilog ? mainb->rodata_size : 0);
5236 unsigned char *ptr;
5237
5238 assert(!prolog || !prolog->rodata_size);
5239 assert(!previous_stage || !previous_stage->rodata_size);
5240 assert(!prolog2 || !prolog2->rodata_size);
5241 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5242 !mainb->rodata_size);
5243 assert(!epilog || !epilog->rodata_size);
5244
5245 si_resource_reference(&shader->bo, NULL);
5246 shader->bo = si_aligned_buffer_create(&sscreen->b,
5247 sscreen->cpdma_prefetch_writes_memory ?
5248 0 : SI_RESOURCE_FLAG_READ_ONLY,
5249 PIPE_USAGE_IMMUTABLE,
5250 align(bo_size, SI_CPDMA_ALIGNMENT),
5251 256);
5252 if (!shader->bo)
5253 return -ENOMEM;
5254
5255 /* Upload. */
5256 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5257 PIPE_TRANSFER_READ_WRITE |
5258 PIPE_TRANSFER_UNSYNCHRONIZED |
5259 RADEON_TRANSFER_TEMPORARY);
5260
5261 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5262 * endian-independent. */
5263 if (prolog) {
5264 memcpy(ptr, prolog->code, prolog->code_size);
5265 ptr += prolog->code_size;
5266 }
5267 if (previous_stage) {
5268 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5269 ptr += previous_stage->code_size;
5270 }
5271 if (prolog2) {
5272 memcpy(ptr, prolog2->code, prolog2->code_size);
5273 ptr += prolog2->code_size;
5274 }
5275
5276 memcpy(ptr, mainb->code, mainb->code_size);
5277 ptr += mainb->code_size;
5278
5279 if (epilog) {
5280 memcpy(ptr, epilog->code, epilog->code_size);
5281 ptr += epilog->code_size;
5282 } else if (mainb->rodata_size > 0) {
5283 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5284 ptr += mainb->rodata_size;
5285 }
5286
5287 /* Add end-of-code markers for the UMR disassembler. */
5288 uint32_t *ptr32 = (uint32_t*)ptr;
5289 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5290 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5291
5292 sscreen->ws->buffer_unmap(shader->bo->buf);
5293 return 0;
5294 }
5295
5296 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5297 struct pipe_debug_callback *debug,
5298 const char *name, FILE *file)
5299 {
5300 char *line, *p;
5301 unsigned i, count;
5302
5303 if (binary->disasm_string) {
5304 fprintf(file, "Shader %s disassembly:\n", name);
5305 fprintf(file, "%s", binary->disasm_string);
5306
5307 if (debug && debug->debug_message) {
5308 /* Very long debug messages are cut off, so send the
5309 * disassembly one line at a time. This causes more
5310 * overhead, but on the plus side it simplifies
5311 * parsing of resulting logs.
5312 */
5313 pipe_debug_message(debug, SHADER_INFO,
5314 "Shader Disassembly Begin");
5315
5316 line = binary->disasm_string;
5317 while (*line) {
5318 p = util_strchrnul(line, '\n');
5319 count = p - line;
5320
5321 if (count) {
5322 pipe_debug_message(debug, SHADER_INFO,
5323 "%.*s", count, line);
5324 }
5325
5326 if (!*p)
5327 break;
5328 line = p + 1;
5329 }
5330
5331 pipe_debug_message(debug, SHADER_INFO,
5332 "Shader Disassembly End");
5333 }
5334 } else {
5335 fprintf(file, "Shader %s binary:\n", name);
5336 for (i = 0; i < binary->code_size; i += 4) {
5337 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5338 binary->code[i + 3], binary->code[i + 2],
5339 binary->code[i + 1], binary->code[i]);
5340 }
5341 }
5342 }
5343
5344 static void si_calculate_max_simd_waves(struct si_shader *shader)
5345 {
5346 struct si_screen *sscreen = shader->selector->screen;
5347 struct si_shader_config *conf = &shader->config;
5348 unsigned num_inputs = shader->selector->info.num_inputs;
5349 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5350 unsigned lds_per_wave = 0;
5351 unsigned max_simd_waves;
5352
5353 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5354
5355 /* Compute LDS usage for PS. */
5356 switch (shader->selector->type) {
5357 case PIPE_SHADER_FRAGMENT:
5358 /* The minimum usage per wave is (num_inputs * 48). The maximum
5359 * usage is (num_inputs * 48 * 16).
5360 * We can get anything in between and it varies between waves.
5361 *
5362 * The 48 bytes per input for a single primitive is equal to
5363 * 4 bytes/component * 4 components/input * 3 points.
5364 *
5365 * Other stages don't know the size at compile time or don't
5366 * allocate LDS per wave, but instead they do it per thread group.
5367 */
5368 lds_per_wave = conf->lds_size * lds_increment +
5369 align(num_inputs * 48, lds_increment);
5370 break;
5371 case PIPE_SHADER_COMPUTE:
5372 if (shader->selector) {
5373 unsigned max_workgroup_size =
5374 si_get_max_workgroup_size(shader);
5375 lds_per_wave = (conf->lds_size * lds_increment) /
5376 DIV_ROUND_UP(max_workgroup_size, 64);
5377 }
5378 break;
5379 }
5380
5381 /* Compute the per-SIMD wave counts. */
5382 if (conf->num_sgprs) {
5383 max_simd_waves =
5384 MIN2(max_simd_waves,
5385 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5386 }
5387
5388 if (conf->num_vgprs)
5389 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5390
5391 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5392 * 16KB makes some SIMDs unoccupied). */
5393 if (lds_per_wave)
5394 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5395
5396 conf->max_simd_waves = max_simd_waves;
5397 }
5398
5399 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5400 struct pipe_debug_callback *debug)
5401 {
5402 const struct si_shader_config *conf = &shader->config;
5403
5404 pipe_debug_message(debug, SHADER_INFO,
5405 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5406 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5407 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5408 conf->num_sgprs, conf->num_vgprs,
5409 si_get_shader_binary_size(shader),
5410 conf->lds_size, conf->scratch_bytes_per_wave,
5411 conf->max_simd_waves, conf->spilled_sgprs,
5412 conf->spilled_vgprs, conf->private_mem_vgprs);
5413 }
5414
5415 static void si_shader_dump_stats(struct si_screen *sscreen,
5416 const struct si_shader *shader,
5417 unsigned processor,
5418 FILE *file,
5419 bool check_debug_option)
5420 {
5421 const struct si_shader_config *conf = &shader->config;
5422
5423 if (!check_debug_option ||
5424 si_can_dump_shader(sscreen, processor)) {
5425 if (processor == PIPE_SHADER_FRAGMENT) {
5426 fprintf(file, "*** SHADER CONFIG ***\n"
5427 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5428 "SPI_PS_INPUT_ENA = 0x%04x\n",
5429 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5430 }
5431
5432 fprintf(file, "*** SHADER STATS ***\n"
5433 "SGPRS: %d\n"
5434 "VGPRS: %d\n"
5435 "Spilled SGPRs: %d\n"
5436 "Spilled VGPRs: %d\n"
5437 "Private memory VGPRs: %d\n"
5438 "Code Size: %d bytes\n"
5439 "LDS: %d blocks\n"
5440 "Scratch: %d bytes per wave\n"
5441 "Max Waves: %d\n"
5442 "********************\n\n\n",
5443 conf->num_sgprs, conf->num_vgprs,
5444 conf->spilled_sgprs, conf->spilled_vgprs,
5445 conf->private_mem_vgprs,
5446 si_get_shader_binary_size(shader),
5447 conf->lds_size, conf->scratch_bytes_per_wave,
5448 conf->max_simd_waves);
5449 }
5450 }
5451
5452 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5453 {
5454 switch (processor) {
5455 case PIPE_SHADER_VERTEX:
5456 if (shader->key.as_es)
5457 return "Vertex Shader as ES";
5458 else if (shader->key.as_ls)
5459 return "Vertex Shader as LS";
5460 else
5461 return "Vertex Shader as VS";
5462 case PIPE_SHADER_TESS_CTRL:
5463 return "Tessellation Control Shader";
5464 case PIPE_SHADER_TESS_EVAL:
5465 if (shader->key.as_es)
5466 return "Tessellation Evaluation Shader as ES";
5467 else
5468 return "Tessellation Evaluation Shader as VS";
5469 case PIPE_SHADER_GEOMETRY:
5470 if (shader->is_gs_copy_shader)
5471 return "GS Copy Shader as VS";
5472 else
5473 return "Geometry Shader";
5474 case PIPE_SHADER_FRAGMENT:
5475 return "Pixel Shader";
5476 case PIPE_SHADER_COMPUTE:
5477 return "Compute Shader";
5478 default:
5479 return "Unknown Shader";
5480 }
5481 }
5482
5483 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5484 struct pipe_debug_callback *debug, unsigned processor,
5485 FILE *file, bool check_debug_option)
5486 {
5487 if (!check_debug_option ||
5488 si_can_dump_shader(sscreen, processor))
5489 si_dump_shader_key(processor, shader, file);
5490
5491 if (!check_debug_option && shader->binary.llvm_ir_string) {
5492 if (shader->previous_stage &&
5493 shader->previous_stage->binary.llvm_ir_string) {
5494 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5495 si_get_shader_name(shader, processor));
5496 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5497 }
5498
5499 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5500 si_get_shader_name(shader, processor));
5501 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5502 }
5503
5504 if (!check_debug_option ||
5505 (si_can_dump_shader(sscreen, processor) &&
5506 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5507 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5508
5509 if (shader->prolog)
5510 si_shader_dump_disassembly(&shader->prolog->binary,
5511 debug, "prolog", file);
5512 if (shader->previous_stage)
5513 si_shader_dump_disassembly(&shader->previous_stage->binary,
5514 debug, "previous stage", file);
5515 if (shader->prolog2)
5516 si_shader_dump_disassembly(&shader->prolog2->binary,
5517 debug, "prolog2", file);
5518
5519 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5520
5521 if (shader->epilog)
5522 si_shader_dump_disassembly(&shader->epilog->binary,
5523 debug, "epilog", file);
5524 fprintf(file, "\n");
5525 }
5526
5527 si_shader_dump_stats(sscreen, shader, processor, file,
5528 check_debug_option);
5529 }
5530
5531 static int si_compile_llvm(struct si_screen *sscreen,
5532 struct ac_shader_binary *binary,
5533 struct si_shader_config *conf,
5534 struct ac_llvm_compiler *compiler,
5535 LLVMModuleRef mod,
5536 struct pipe_debug_callback *debug,
5537 unsigned processor,
5538 const char *name,
5539 bool less_optimized)
5540 {
5541 int r = 0;
5542 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5543
5544 if (si_can_dump_shader(sscreen, processor)) {
5545 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5546
5547 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5548 fprintf(stderr, "%s LLVM IR:\n\n", name);
5549 ac_dump_module(mod);
5550 fprintf(stderr, "\n");
5551 }
5552 }
5553
5554 if (sscreen->record_llvm_ir) {
5555 char *ir = LLVMPrintModuleToString(mod);
5556 binary->llvm_ir_string = strdup(ir);
5557 LLVMDisposeMessage(ir);
5558 }
5559
5560 if (!si_replace_shader(count, binary)) {
5561 r = si_llvm_compile(mod, binary, compiler, debug,
5562 less_optimized);
5563 if (r)
5564 return r;
5565 }
5566
5567 si_shader_binary_read_config(binary, conf, 0);
5568
5569 /* Enable 64-bit and 16-bit denormals, because there is no performance
5570 * cost.
5571 *
5572 * If denormals are enabled, all floating-point output modifiers are
5573 * ignored.
5574 *
5575 * Don't enable denormals for 32-bit floats, because:
5576 * - Floating-point output modifiers would be ignored by the hw.
5577 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5578 * have to stop using those.
5579 * - SI & CI would be very slow.
5580 */
5581 conf->float_mode |= V_00B028_FP_64_DENORMS;
5582
5583 FREE(binary->config);
5584 FREE(binary->global_symbol_offsets);
5585 binary->config = NULL;
5586 binary->global_symbol_offsets = NULL;
5587
5588 /* Some shaders can't have rodata because their binaries can be
5589 * concatenated.
5590 */
5591 if (binary->rodata_size &&
5592 (processor == PIPE_SHADER_VERTEX ||
5593 processor == PIPE_SHADER_TESS_CTRL ||
5594 processor == PIPE_SHADER_TESS_EVAL ||
5595 processor == PIPE_SHADER_FRAGMENT)) {
5596 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5597 return -EINVAL;
5598 }
5599
5600 return r;
5601 }
5602
5603 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5604 {
5605 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5606 LLVMBuildRetVoid(ctx->ac.builder);
5607 else
5608 LLVMBuildRet(ctx->ac.builder, ret);
5609 }
5610
5611 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5612 struct si_shader *
5613 si_generate_gs_copy_shader(struct si_screen *sscreen,
5614 struct ac_llvm_compiler *compiler,
5615 struct si_shader_selector *gs_selector,
5616 struct pipe_debug_callback *debug)
5617 {
5618 struct si_shader_context ctx;
5619 struct si_shader *shader;
5620 LLVMBuilderRef builder;
5621 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5622 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5623 int i, r;
5624
5625
5626 shader = CALLOC_STRUCT(si_shader);
5627 if (!shader)
5628 return NULL;
5629
5630 /* We can leave the fence as permanently signaled because the GS copy
5631 * shader only becomes visible globally after it has been compiled. */
5632 util_queue_fence_init(&shader->ready);
5633
5634 shader->selector = gs_selector;
5635 shader->is_gs_copy_shader = true;
5636
5637 si_init_shader_ctx(&ctx, sscreen, compiler);
5638 ctx.shader = shader;
5639 ctx.type = PIPE_SHADER_VERTEX;
5640
5641 builder = ctx.ac.builder;
5642
5643 create_function(&ctx);
5644 preload_ring_buffers(&ctx);
5645
5646 LLVMValueRef voffset =
5647 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5648 LLVMConstInt(ctx.i32, 4, 0), "");
5649
5650 /* Fetch the vertex stream ID.*/
5651 LLVMValueRef stream_id;
5652
5653 if (gs_selector->so.num_outputs)
5654 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5655 else
5656 stream_id = ctx.i32_0;
5657
5658 /* Fill in output information. */
5659 for (i = 0; i < gsinfo->num_outputs; ++i) {
5660 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5661 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5662
5663 for (int chan = 0; chan < 4; chan++) {
5664 outputs[i].vertex_stream[chan] =
5665 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5666 }
5667 }
5668
5669 LLVMBasicBlockRef end_bb;
5670 LLVMValueRef switch_inst;
5671
5672 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5673 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5674
5675 for (int stream = 0; stream < 4; stream++) {
5676 LLVMBasicBlockRef bb;
5677 unsigned offset;
5678
5679 if (!gsinfo->num_stream_output_components[stream])
5680 continue;
5681
5682 if (stream > 0 && !gs_selector->so.num_outputs)
5683 continue;
5684
5685 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5686 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5687 LLVMPositionBuilderAtEnd(builder, bb);
5688
5689 /* Fetch vertex data from GSVS ring */
5690 offset = 0;
5691 for (i = 0; i < gsinfo->num_outputs; ++i) {
5692 for (unsigned chan = 0; chan < 4; chan++) {
5693 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5694 outputs[i].vertex_stream[chan] != stream) {
5695 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5696 continue;
5697 }
5698
5699 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5700 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5701 offset++;
5702
5703 outputs[i].values[chan] =
5704 ac_build_buffer_load(&ctx.ac,
5705 ctx.gsvs_ring[0], 1,
5706 ctx.i32_0, voffset,
5707 soffset, 0, 1, 1,
5708 true, false);
5709 }
5710 }
5711
5712 /* Streamout and exports. */
5713 if (gs_selector->so.num_outputs) {
5714 si_llvm_emit_streamout(&ctx, outputs,
5715 gsinfo->num_outputs,
5716 stream);
5717 }
5718
5719 if (stream == 0) {
5720 /* Vertex color clamping.
5721 *
5722 * This uses a state constant loaded in a user data SGPR and
5723 * an IF statement is added that clamps all colors if the constant
5724 * is true.
5725 */
5726 struct lp_build_if_state if_ctx;
5727 LLVMValueRef v[2], cond = NULL;
5728 LLVMBasicBlockRef blocks[2];
5729
5730 for (unsigned i = 0; i < gsinfo->num_outputs; i++) {
5731 if (gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
5732 gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
5733 continue;
5734
5735 /* We've found a color. */
5736 if (!cond) {
5737 /* The state is in the first bit of the user SGPR. */
5738 cond = LLVMGetParam(ctx.main_fn,
5739 ctx.param_vs_state_bits);
5740 cond = LLVMBuildTrunc(ctx.ac.builder, cond,
5741 ctx.i1, "");
5742 lp_build_if(&if_ctx, &ctx.gallivm, cond);
5743 /* Remember blocks for Phi. */
5744 blocks[0] = if_ctx.true_block;
5745 blocks[1] = if_ctx.entry_block;
5746 }
5747
5748 for (unsigned j = 0; j < 4; j++) {
5749 /* Insert clamp into the true block. */
5750 v[0] = ac_build_clamp(&ctx.ac, outputs[i].values[j]);
5751 v[1] = outputs[i].values[j];
5752
5753 /* Insert Phi into the endif block. */
5754 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.merge_block);
5755 outputs[i].values[j] = ac_build_phi(&ctx.ac, ctx.f32, 2, v, blocks);
5756 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.true_block);
5757 }
5758 }
5759 if (cond)
5760 lp_build_endif(&if_ctx);
5761
5762 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5763 }
5764
5765 LLVMBuildBr(builder, end_bb);
5766 }
5767
5768 LLVMPositionBuilderAtEnd(builder, end_bb);
5769
5770 LLVMBuildRetVoid(ctx.ac.builder);
5771
5772 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5773 si_llvm_optimize_module(&ctx);
5774
5775 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5776 &ctx.shader->config, ctx.compiler,
5777 ctx.ac.module,
5778 debug, PIPE_SHADER_GEOMETRY,
5779 "GS Copy Shader", false);
5780 if (!r) {
5781 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5782 fprintf(stderr, "GS Copy Shader:\n");
5783 si_shader_dump(sscreen, ctx.shader, debug,
5784 PIPE_SHADER_GEOMETRY, stderr, true);
5785 r = si_shader_binary_upload(sscreen, ctx.shader);
5786 }
5787
5788 si_llvm_dispose(&ctx);
5789
5790 if (r != 0) {
5791 FREE(shader);
5792 shader = NULL;
5793 } else {
5794 si_fix_resource_usage(sscreen, shader);
5795 }
5796 return shader;
5797 }
5798
5799 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5800 const struct si_vs_prolog_bits *prolog,
5801 const char *prefix, FILE *f)
5802 {
5803 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5804 prefix, prolog->instance_divisor_is_one);
5805 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5806 prefix, prolog->instance_divisor_is_fetched);
5807 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5808 prefix, prolog->ls_vgpr_fix);
5809
5810 fprintf(f, " mono.vs.fix_fetch = {");
5811 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5812 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5813 fprintf(f, "}\n");
5814 }
5815
5816 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5817 FILE *f)
5818 {
5819 const struct si_shader_key *key = &shader->key;
5820
5821 fprintf(f, "SHADER KEY\n");
5822
5823 switch (processor) {
5824 case PIPE_SHADER_VERTEX:
5825 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5826 "part.vs.prolog", f);
5827 fprintf(f, " as_es = %u\n", key->as_es);
5828 fprintf(f, " as_ls = %u\n", key->as_ls);
5829 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5830 key->mono.u.vs_export_prim_id);
5831 break;
5832
5833 case PIPE_SHADER_TESS_CTRL:
5834 if (shader->selector->screen->info.chip_class >= GFX9) {
5835 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5836 "part.tcs.ls_prolog", f);
5837 }
5838 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5839 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5840 break;
5841
5842 case PIPE_SHADER_TESS_EVAL:
5843 fprintf(f, " as_es = %u\n", key->as_es);
5844 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5845 key->mono.u.vs_export_prim_id);
5846 break;
5847
5848 case PIPE_SHADER_GEOMETRY:
5849 if (shader->is_gs_copy_shader)
5850 break;
5851
5852 if (shader->selector->screen->info.chip_class >= GFX9 &&
5853 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5854 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5855 "part.gs.vs_prolog", f);
5856 }
5857 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5858 break;
5859
5860 case PIPE_SHADER_COMPUTE:
5861 break;
5862
5863 case PIPE_SHADER_FRAGMENT:
5864 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5865 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5866 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5867 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5868 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5869 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5870 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5871 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5872 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5873 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5874 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5875 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5876 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5877 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5878 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5879 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5880 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5881 break;
5882
5883 default:
5884 assert(0);
5885 }
5886
5887 if ((processor == PIPE_SHADER_GEOMETRY ||
5888 processor == PIPE_SHADER_TESS_EVAL ||
5889 processor == PIPE_SHADER_VERTEX) &&
5890 !key->as_es && !key->as_ls) {
5891 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5892 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5893 }
5894 }
5895
5896 static void si_init_shader_ctx(struct si_shader_context *ctx,
5897 struct si_screen *sscreen,
5898 struct ac_llvm_compiler *compiler)
5899 {
5900 struct lp_build_tgsi_context *bld_base;
5901
5902 si_llvm_context_init(ctx, sscreen, compiler);
5903
5904 bld_base = &ctx->bld_base;
5905 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5906
5907 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5908 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5909 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5910
5911 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5912
5913 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5914
5915 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5916 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5917 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5918 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5919
5920 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5921 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5922 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5923 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5924 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5925 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5926 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5927 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5928
5929 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5930 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5931 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5932 }
5933
5934 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5935 {
5936 struct si_shader *shader = ctx->shader;
5937 struct tgsi_shader_info *info = &shader->selector->info;
5938
5939 if ((ctx->type != PIPE_SHADER_VERTEX &&
5940 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5941 shader->key.as_ls ||
5942 shader->key.as_es)
5943 return;
5944
5945 ac_optimize_vs_outputs(&ctx->ac,
5946 ctx->main_fn,
5947 shader->info.vs_output_param_offset,
5948 info->num_outputs,
5949 &shader->info.nr_param_exports);
5950 }
5951
5952 static void si_init_exec_from_input(struct si_shader_context *ctx,
5953 unsigned param, unsigned bitoffset)
5954 {
5955 LLVMValueRef args[] = {
5956 LLVMGetParam(ctx->main_fn, param),
5957 LLVMConstInt(ctx->i32, bitoffset, 0),
5958 };
5959 ac_build_intrinsic(&ctx->ac,
5960 "llvm.amdgcn.init.exec.from.input",
5961 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5962 }
5963
5964 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5965 const struct si_vs_prolog_bits *key)
5966 {
5967 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5968 * VS prolog. */
5969 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5970 }
5971
5972 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5973 {
5974 struct si_shader *shader = ctx->shader;
5975 struct si_shader_selector *sel = shader->selector;
5976 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5977
5978 // TODO clean all this up!
5979 switch (ctx->type) {
5980 case PIPE_SHADER_VERTEX:
5981 ctx->load_input = declare_input_vs;
5982 if (shader->key.as_ls)
5983 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5984 else if (shader->key.as_es)
5985 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5986 else
5987 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5988 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5989 ctx->abi.load_base_vertex = get_base_vertex;
5990 break;
5991 case PIPE_SHADER_TESS_CTRL:
5992 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5993 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5994 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5995 bld_base->emit_store = store_output_tcs;
5996 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5997 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5998 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5999 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6000 break;
6001 case PIPE_SHADER_TESS_EVAL:
6002 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6003 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6004 ctx->abi.load_tess_coord = si_load_tess_coord;
6005 ctx->abi.load_tess_level = si_load_tess_level;
6006 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6007 if (shader->key.as_es)
6008 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6009 else
6010 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6011 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6012 break;
6013 case PIPE_SHADER_GEOMETRY:
6014 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6015 ctx->abi.load_inputs = si_nir_load_input_gs;
6016 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6017 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6018 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6019 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6020 break;
6021 case PIPE_SHADER_FRAGMENT:
6022 ctx->load_input = declare_input_fs;
6023 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6024 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6025 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6026 ctx->abi.load_sample_position = load_sample_position;
6027 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6028 ctx->abi.emit_kill = si_llvm_emit_kill;
6029 break;
6030 case PIPE_SHADER_COMPUTE:
6031 ctx->abi.load_local_group_size = get_block_size;
6032 break;
6033 default:
6034 assert(!"Unsupported shader type");
6035 return false;
6036 }
6037
6038 ctx->abi.load_ubo = load_ubo;
6039 ctx->abi.load_ssbo = load_ssbo;
6040
6041 create_function(ctx);
6042 preload_ring_buffers(ctx);
6043
6044 /* For GFX9 merged shaders:
6045 * - Set EXEC for the first shader. If the prolog is present, set
6046 * EXEC there instead.
6047 * - Add a barrier before the second shader.
6048 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6049 * an if-statement. This is required for correctness in geometry
6050 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6051 * GS_CUT messages.
6052 *
6053 * For monolithic merged shaders, the first shader is wrapped in an
6054 * if-block together with its prolog in si_build_wrapper_function.
6055 */
6056 if (ctx->screen->info.chip_class >= GFX9) {
6057 if (!shader->is_monolithic &&
6058 sel->info.num_instructions > 1 && /* not empty shader */
6059 (shader->key.as_es || shader->key.as_ls) &&
6060 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6061 (ctx->type == PIPE_SHADER_VERTEX &&
6062 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6063 si_init_exec_from_input(ctx,
6064 ctx->param_merged_wave_info, 0);
6065 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6066 ctx->type == PIPE_SHADER_GEOMETRY) {
6067 if (!shader->is_monolithic)
6068 ac_init_exec_full_mask(&ctx->ac);
6069
6070 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6071 LLVMValueRef ena =
6072 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6073 ac_get_thread_id(&ctx->ac), num_threads, "");
6074 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6075
6076 /* The barrier must execute for all shaders in a
6077 * threadgroup.
6078 *
6079 * Execute the barrier inside the conditional block,
6080 * so that empty waves can jump directly to s_endpgm,
6081 * which will also signal the barrier.
6082 *
6083 * If the shader is TCS and the TCS epilog is present
6084 * and contains a barrier, it will wait there and then
6085 * reach s_endpgm.
6086 */
6087 si_llvm_emit_barrier(NULL, bld_base, NULL);
6088 }
6089 }
6090
6091 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6092 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6093 for (unsigned i = 0; i < 6; i++) {
6094 ctx->invoc0_tess_factors[i] =
6095 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6096 }
6097 }
6098
6099 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6100 int i;
6101 for (i = 0; i < 4; i++) {
6102 ctx->gs_next_vertex[i] =
6103 ac_build_alloca(&ctx->ac, ctx->i32, "");
6104 }
6105 }
6106
6107 if (sel->force_correct_derivs_after_kill) {
6108 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6109 /* true = don't kill. */
6110 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6111 ctx->postponed_kill);
6112 }
6113
6114 if (sel->tokens) {
6115 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6116 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6117 return false;
6118 }
6119 } else {
6120 if (!si_nir_build_llvm(ctx, sel->nir)) {
6121 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6122 return false;
6123 }
6124 }
6125
6126 si_llvm_build_ret(ctx, ctx->return_value);
6127 return true;
6128 }
6129
6130 /**
6131 * Compute the VS prolog key, which contains all the information needed to
6132 * build the VS prolog function, and set shader->info bits where needed.
6133 *
6134 * \param info Shader info of the vertex shader.
6135 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6136 * \param prolog_key Key of the VS prolog
6137 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6138 * \param key Output shader part key.
6139 */
6140 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6141 unsigned num_input_sgprs,
6142 const struct si_vs_prolog_bits *prolog_key,
6143 struct si_shader *shader_out,
6144 union si_shader_part_key *key)
6145 {
6146 memset(key, 0, sizeof(*key));
6147 key->vs_prolog.states = *prolog_key;
6148 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6149 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6150 key->vs_prolog.as_ls = shader_out->key.as_ls;
6151 key->vs_prolog.as_es = shader_out->key.as_es;
6152
6153 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6154 key->vs_prolog.as_ls = 1;
6155 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6156 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6157 key->vs_prolog.as_es = 1;
6158 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6159 }
6160
6161 /* Enable loading the InstanceID VGPR. */
6162 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6163
6164 if ((key->vs_prolog.states.instance_divisor_is_one |
6165 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6166 shader_out->info.uses_instanceid = true;
6167 }
6168
6169 /**
6170 * Compute the PS prolog key, which contains all the information needed to
6171 * build the PS prolog function, and set related bits in shader->config.
6172 */
6173 static void si_get_ps_prolog_key(struct si_shader *shader,
6174 union si_shader_part_key *key,
6175 bool separate_prolog)
6176 {
6177 struct tgsi_shader_info *info = &shader->selector->info;
6178
6179 memset(key, 0, sizeof(*key));
6180 key->ps_prolog.states = shader->key.part.ps.prolog;
6181 key->ps_prolog.colors_read = info->colors_read;
6182 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6183 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6184 key->ps_prolog.wqm = info->uses_derivatives &&
6185 (key->ps_prolog.colors_read ||
6186 key->ps_prolog.states.force_persp_sample_interp ||
6187 key->ps_prolog.states.force_linear_sample_interp ||
6188 key->ps_prolog.states.force_persp_center_interp ||
6189 key->ps_prolog.states.force_linear_center_interp ||
6190 key->ps_prolog.states.bc_optimize_for_persp ||
6191 key->ps_prolog.states.bc_optimize_for_linear);
6192 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6193
6194 if (info->colors_read) {
6195 unsigned *color = shader->selector->color_attr_index;
6196
6197 if (shader->key.part.ps.prolog.color_two_side) {
6198 /* BCOLORs are stored after the last input. */
6199 key->ps_prolog.num_interp_inputs = info->num_inputs;
6200 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6201 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6202 }
6203
6204 for (unsigned i = 0; i < 2; i++) {
6205 unsigned interp = info->input_interpolate[color[i]];
6206 unsigned location = info->input_interpolate_loc[color[i]];
6207
6208 if (!(info->colors_read & (0xf << i*4)))
6209 continue;
6210
6211 key->ps_prolog.color_attr_index[i] = color[i];
6212
6213 if (shader->key.part.ps.prolog.flatshade_colors &&
6214 interp == TGSI_INTERPOLATE_COLOR)
6215 interp = TGSI_INTERPOLATE_CONSTANT;
6216
6217 switch (interp) {
6218 case TGSI_INTERPOLATE_CONSTANT:
6219 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6220 break;
6221 case TGSI_INTERPOLATE_PERSPECTIVE:
6222 case TGSI_INTERPOLATE_COLOR:
6223 /* Force the interpolation location for colors here. */
6224 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6225 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6226 if (shader->key.part.ps.prolog.force_persp_center_interp)
6227 location = TGSI_INTERPOLATE_LOC_CENTER;
6228
6229 switch (location) {
6230 case TGSI_INTERPOLATE_LOC_SAMPLE:
6231 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6232 shader->config.spi_ps_input_ena |=
6233 S_0286CC_PERSP_SAMPLE_ENA(1);
6234 break;
6235 case TGSI_INTERPOLATE_LOC_CENTER:
6236 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6237 shader->config.spi_ps_input_ena |=
6238 S_0286CC_PERSP_CENTER_ENA(1);
6239 break;
6240 case TGSI_INTERPOLATE_LOC_CENTROID:
6241 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6242 shader->config.spi_ps_input_ena |=
6243 S_0286CC_PERSP_CENTROID_ENA(1);
6244 break;
6245 default:
6246 assert(0);
6247 }
6248 break;
6249 case TGSI_INTERPOLATE_LINEAR:
6250 /* Force the interpolation location for colors here. */
6251 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6252 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6253 if (shader->key.part.ps.prolog.force_linear_center_interp)
6254 location = TGSI_INTERPOLATE_LOC_CENTER;
6255
6256 /* The VGPR assignment for non-monolithic shaders
6257 * works because InitialPSInputAddr is set on the
6258 * main shader and PERSP_PULL_MODEL is never used.
6259 */
6260 switch (location) {
6261 case TGSI_INTERPOLATE_LOC_SAMPLE:
6262 key->ps_prolog.color_interp_vgpr_index[i] =
6263 separate_prolog ? 6 : 9;
6264 shader->config.spi_ps_input_ena |=
6265 S_0286CC_LINEAR_SAMPLE_ENA(1);
6266 break;
6267 case TGSI_INTERPOLATE_LOC_CENTER:
6268 key->ps_prolog.color_interp_vgpr_index[i] =
6269 separate_prolog ? 8 : 11;
6270 shader->config.spi_ps_input_ena |=
6271 S_0286CC_LINEAR_CENTER_ENA(1);
6272 break;
6273 case TGSI_INTERPOLATE_LOC_CENTROID:
6274 key->ps_prolog.color_interp_vgpr_index[i] =
6275 separate_prolog ? 10 : 13;
6276 shader->config.spi_ps_input_ena |=
6277 S_0286CC_LINEAR_CENTROID_ENA(1);
6278 break;
6279 default:
6280 assert(0);
6281 }
6282 break;
6283 default:
6284 assert(0);
6285 }
6286 }
6287 }
6288 }
6289
6290 /**
6291 * Check whether a PS prolog is required based on the key.
6292 */
6293 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6294 {
6295 return key->ps_prolog.colors_read ||
6296 key->ps_prolog.states.force_persp_sample_interp ||
6297 key->ps_prolog.states.force_linear_sample_interp ||
6298 key->ps_prolog.states.force_persp_center_interp ||
6299 key->ps_prolog.states.force_linear_center_interp ||
6300 key->ps_prolog.states.bc_optimize_for_persp ||
6301 key->ps_prolog.states.bc_optimize_for_linear ||
6302 key->ps_prolog.states.poly_stipple ||
6303 key->ps_prolog.states.samplemask_log_ps_iter;
6304 }
6305
6306 /**
6307 * Compute the PS epilog key, which contains all the information needed to
6308 * build the PS epilog function.
6309 */
6310 static void si_get_ps_epilog_key(struct si_shader *shader,
6311 union si_shader_part_key *key)
6312 {
6313 struct tgsi_shader_info *info = &shader->selector->info;
6314 memset(key, 0, sizeof(*key));
6315 key->ps_epilog.colors_written = info->colors_written;
6316 key->ps_epilog.writes_z = info->writes_z;
6317 key->ps_epilog.writes_stencil = info->writes_stencil;
6318 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6319 key->ps_epilog.states = shader->key.part.ps.epilog;
6320 }
6321
6322 /**
6323 * Build the GS prolog function. Rotate the input vertices for triangle strips
6324 * with adjacency.
6325 */
6326 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6327 union si_shader_part_key *key)
6328 {
6329 unsigned num_sgprs, num_vgprs;
6330 struct si_function_info fninfo;
6331 LLVMBuilderRef builder = ctx->ac.builder;
6332 LLVMTypeRef returns[48];
6333 LLVMValueRef func, ret;
6334
6335 si_init_function_info(&fninfo);
6336
6337 if (ctx->screen->info.chip_class >= GFX9) {
6338 if (key->gs_prolog.states.gfx9_prev_is_vs)
6339 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6340 else
6341 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6342 num_vgprs = 5; /* ES inputs are not needed by GS */
6343 } else {
6344 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6345 num_vgprs = 8;
6346 }
6347
6348 for (unsigned i = 0; i < num_sgprs; ++i) {
6349 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6350 returns[i] = ctx->i32;
6351 }
6352
6353 for (unsigned i = 0; i < num_vgprs; ++i) {
6354 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6355 returns[num_sgprs + i] = ctx->f32;
6356 }
6357
6358 /* Create the function. */
6359 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6360 &fninfo, 0);
6361 func = ctx->main_fn;
6362
6363 /* Set the full EXEC mask for the prolog, because we are only fiddling
6364 * with registers here. The main shader part will set the correct EXEC
6365 * mask.
6366 */
6367 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6368 ac_init_exec_full_mask(&ctx->ac);
6369
6370 /* Copy inputs to outputs. This should be no-op, as the registers match,
6371 * but it will prevent the compiler from overwriting them unintentionally.
6372 */
6373 ret = ctx->return_value;
6374 for (unsigned i = 0; i < num_sgprs; i++) {
6375 LLVMValueRef p = LLVMGetParam(func, i);
6376 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6377 }
6378 for (unsigned i = 0; i < num_vgprs; i++) {
6379 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6380 p = ac_to_float(&ctx->ac, p);
6381 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6382 }
6383
6384 if (key->gs_prolog.states.tri_strip_adj_fix) {
6385 /* Remap the input vertices for every other primitive. */
6386 const unsigned gfx6_vtx_params[6] = {
6387 num_sgprs,
6388 num_sgprs + 1,
6389 num_sgprs + 3,
6390 num_sgprs + 4,
6391 num_sgprs + 5,
6392 num_sgprs + 6
6393 };
6394 const unsigned gfx9_vtx_params[3] = {
6395 num_sgprs,
6396 num_sgprs + 1,
6397 num_sgprs + 4,
6398 };
6399 LLVMValueRef vtx_in[6], vtx_out[6];
6400 LLVMValueRef prim_id, rotate;
6401
6402 if (ctx->screen->info.chip_class >= GFX9) {
6403 for (unsigned i = 0; i < 3; i++) {
6404 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6405 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6406 }
6407 } else {
6408 for (unsigned i = 0; i < 6; i++)
6409 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6410 }
6411
6412 prim_id = LLVMGetParam(func, num_sgprs + 2);
6413 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6414
6415 for (unsigned i = 0; i < 6; ++i) {
6416 LLVMValueRef base, rotated;
6417 base = vtx_in[i];
6418 rotated = vtx_in[(i + 4) % 6];
6419 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6420 }
6421
6422 if (ctx->screen->info.chip_class >= GFX9) {
6423 for (unsigned i = 0; i < 3; i++) {
6424 LLVMValueRef hi, out;
6425
6426 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6427 LLVMConstInt(ctx->i32, 16, 0), "");
6428 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6429 out = ac_to_float(&ctx->ac, out);
6430 ret = LLVMBuildInsertValue(builder, ret, out,
6431 gfx9_vtx_params[i], "");
6432 }
6433 } else {
6434 for (unsigned i = 0; i < 6; i++) {
6435 LLVMValueRef out;
6436
6437 out = ac_to_float(&ctx->ac, vtx_out[i]);
6438 ret = LLVMBuildInsertValue(builder, ret, out,
6439 gfx6_vtx_params[i], "");
6440 }
6441 }
6442 }
6443
6444 LLVMBuildRet(builder, ret);
6445 }
6446
6447 /**
6448 * Given a list of shader part functions, build a wrapper function that
6449 * runs them in sequence to form a monolithic shader.
6450 */
6451 static void si_build_wrapper_function(struct si_shader_context *ctx,
6452 LLVMValueRef *parts,
6453 unsigned num_parts,
6454 unsigned main_part,
6455 unsigned next_shader_first_part)
6456 {
6457 LLVMBuilderRef builder = ctx->ac.builder;
6458 /* PS epilog has one arg per color component; gfx9 merged shader
6459 * prologs need to forward 32 user SGPRs.
6460 */
6461 struct si_function_info fninfo;
6462 LLVMValueRef initial[64], out[64];
6463 LLVMTypeRef function_type;
6464 unsigned num_first_params;
6465 unsigned num_out, initial_num_out;
6466 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6467 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6468 unsigned num_sgprs, num_vgprs;
6469 unsigned gprs;
6470 struct lp_build_if_state if_state;
6471
6472 si_init_function_info(&fninfo);
6473
6474 for (unsigned i = 0; i < num_parts; ++i) {
6475 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6476 AC_FUNC_ATTR_ALWAYSINLINE);
6477 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6478 }
6479
6480 /* The parameters of the wrapper function correspond to those of the
6481 * first part in terms of SGPRs and VGPRs, but we use the types of the
6482 * main part to get the right types. This is relevant for the
6483 * dereferenceable attribute on descriptor table pointers.
6484 */
6485 num_sgprs = 0;
6486 num_vgprs = 0;
6487
6488 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6489 num_first_params = LLVMCountParamTypes(function_type);
6490
6491 for (unsigned i = 0; i < num_first_params; ++i) {
6492 LLVMValueRef param = LLVMGetParam(parts[0], i);
6493
6494 if (ac_is_sgpr_param(param)) {
6495 assert(num_vgprs == 0);
6496 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6497 } else {
6498 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6499 }
6500 }
6501
6502 gprs = 0;
6503 while (gprs < num_sgprs + num_vgprs) {
6504 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6505 LLVMTypeRef type = LLVMTypeOf(param);
6506 unsigned size = ac_get_type_size(type) / 4;
6507
6508 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6509
6510 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6511 assert(gprs + size <= num_sgprs + num_vgprs &&
6512 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6513
6514 gprs += size;
6515 }
6516
6517 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6518 si_get_max_workgroup_size(ctx->shader));
6519
6520 if (is_merged_shader(ctx))
6521 ac_init_exec_full_mask(&ctx->ac);
6522
6523 /* Record the arguments of the function as if they were an output of
6524 * a previous part.
6525 */
6526 num_out = 0;
6527 num_out_sgpr = 0;
6528
6529 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6530 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6531 LLVMTypeRef param_type = LLVMTypeOf(param);
6532 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6533 unsigned size = ac_get_type_size(param_type) / 4;
6534
6535 if (size == 1) {
6536 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6537 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6538 param_type = ctx->i32;
6539 }
6540
6541 if (param_type != out_type)
6542 param = LLVMBuildBitCast(builder, param, out_type, "");
6543 out[num_out++] = param;
6544 } else {
6545 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6546
6547 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6548 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6549 param_type = ctx->i64;
6550 }
6551
6552 if (param_type != vector_type)
6553 param = LLVMBuildBitCast(builder, param, vector_type, "");
6554
6555 for (unsigned j = 0; j < size; ++j)
6556 out[num_out++] = LLVMBuildExtractElement(
6557 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6558 }
6559
6560 if (i < fninfo.num_sgpr_params)
6561 num_out_sgpr = num_out;
6562 }
6563
6564 memcpy(initial, out, sizeof(out));
6565 initial_num_out = num_out;
6566 initial_num_out_sgpr = num_out_sgpr;
6567
6568 /* Now chain the parts. */
6569 for (unsigned part = 0; part < num_parts; ++part) {
6570 LLVMValueRef in[48];
6571 LLVMValueRef ret;
6572 LLVMTypeRef ret_type;
6573 unsigned out_idx = 0;
6574 unsigned num_params = LLVMCountParams(parts[part]);
6575
6576 /* Merged shaders are executed conditionally depending
6577 * on the number of enabled threads passed in the input SGPRs. */
6578 if (is_merged_shader(ctx) && part == 0) {
6579 LLVMValueRef ena, count = initial[3];
6580
6581 count = LLVMBuildAnd(builder, count,
6582 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6583 ena = LLVMBuildICmp(builder, LLVMIntULT,
6584 ac_get_thread_id(&ctx->ac), count, "");
6585 lp_build_if(&if_state, &ctx->gallivm, ena);
6586 }
6587
6588 /* Derive arguments for the next part from outputs of the
6589 * previous one.
6590 */
6591 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6592 LLVMValueRef param;
6593 LLVMTypeRef param_type;
6594 bool is_sgpr;
6595 unsigned param_size;
6596 LLVMValueRef arg = NULL;
6597
6598 param = LLVMGetParam(parts[part], param_idx);
6599 param_type = LLVMTypeOf(param);
6600 param_size = ac_get_type_size(param_type) / 4;
6601 is_sgpr = ac_is_sgpr_param(param);
6602
6603 if (is_sgpr) {
6604 ac_add_function_attr(ctx->ac.context, parts[part],
6605 param_idx + 1, AC_FUNC_ATTR_INREG);
6606 } else if (out_idx < num_out_sgpr) {
6607 /* Skip returned SGPRs the current part doesn't
6608 * declare on the input. */
6609 out_idx = num_out_sgpr;
6610 }
6611
6612 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6613
6614 if (param_size == 1)
6615 arg = out[out_idx];
6616 else
6617 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6618
6619 if (LLVMTypeOf(arg) != param_type) {
6620 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6621 if (LLVMGetPointerAddressSpace(param_type) ==
6622 AC_ADDR_SPACE_CONST_32BIT) {
6623 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6624 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6625 } else {
6626 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6627 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6628 }
6629 } else {
6630 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6631 }
6632 }
6633
6634 in[param_idx] = arg;
6635 out_idx += param_size;
6636 }
6637
6638 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6639
6640 if (is_merged_shader(ctx) &&
6641 part + 1 == next_shader_first_part) {
6642 lp_build_endif(&if_state);
6643
6644 /* The second half of the merged shader should use
6645 * the inputs from the toplevel (wrapper) function,
6646 * not the return value from the last call.
6647 *
6648 * That's because the last call was executed condi-
6649 * tionally, so we can't consume it in the main
6650 * block.
6651 */
6652 memcpy(out, initial, sizeof(initial));
6653 num_out = initial_num_out;
6654 num_out_sgpr = initial_num_out_sgpr;
6655 continue;
6656 }
6657
6658 /* Extract the returned GPRs. */
6659 ret_type = LLVMTypeOf(ret);
6660 num_out = 0;
6661 num_out_sgpr = 0;
6662
6663 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6664 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6665
6666 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6667
6668 for (unsigned i = 0; i < ret_size; ++i) {
6669 LLVMValueRef val =
6670 LLVMBuildExtractValue(builder, ret, i, "");
6671
6672 assert(num_out < ARRAY_SIZE(out));
6673 out[num_out++] = val;
6674
6675 if (LLVMTypeOf(val) == ctx->i32) {
6676 assert(num_out_sgpr + 1 == num_out);
6677 num_out_sgpr = num_out;
6678 }
6679 }
6680 }
6681 }
6682
6683 LLVMBuildRetVoid(builder);
6684 }
6685
6686 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6687 struct si_shader_selector *sel)
6688 {
6689 if (!compiler->low_opt_passes)
6690 return false;
6691
6692 /* Assume a slow CPU. */
6693 assert(!sel->screen->info.has_dedicated_vram &&
6694 sel->screen->info.chip_class <= VI);
6695
6696 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6697 * buffer stores. */
6698 return sel->type == PIPE_SHADER_COMPUTE &&
6699 sel->info.num_memory_instructions > 1000;
6700 }
6701
6702 int si_compile_tgsi_shader(struct si_screen *sscreen,
6703 struct ac_llvm_compiler *compiler,
6704 struct si_shader *shader,
6705 struct pipe_debug_callback *debug)
6706 {
6707 struct si_shader_selector *sel = shader->selector;
6708 struct si_shader_context ctx;
6709 int r = -1;
6710
6711 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6712 * conversion fails. */
6713 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6714 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6715 if (sel->tokens)
6716 tgsi_dump(sel->tokens, 0);
6717 else
6718 nir_print_shader(sel->nir, stderr);
6719 si_dump_streamout(&sel->so);
6720 }
6721
6722 si_init_shader_ctx(&ctx, sscreen, compiler);
6723 si_llvm_context_set_tgsi(&ctx, shader);
6724
6725 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6726 sizeof(shader->info.vs_output_param_offset));
6727
6728 shader->info.uses_instanceid = sel->info.uses_instanceid;
6729
6730 if (!si_compile_tgsi_main(&ctx)) {
6731 si_llvm_dispose(&ctx);
6732 return -1;
6733 }
6734
6735 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6736 LLVMValueRef parts[2];
6737 bool need_prolog = sel->vs_needs_prolog;
6738
6739 parts[1] = ctx.main_fn;
6740
6741 if (need_prolog) {
6742 union si_shader_part_key prolog_key;
6743 si_get_vs_prolog_key(&sel->info,
6744 shader->info.num_input_sgprs,
6745 &shader->key.part.vs.prolog,
6746 shader, &prolog_key);
6747 si_build_vs_prolog_function(&ctx, &prolog_key);
6748 parts[0] = ctx.main_fn;
6749 }
6750
6751 si_build_wrapper_function(&ctx, parts + !need_prolog,
6752 1 + need_prolog, need_prolog, 0);
6753 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6754 if (sscreen->info.chip_class >= GFX9) {
6755 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6756 LLVMValueRef parts[4];
6757 bool vs_needs_prolog =
6758 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6759
6760 /* TCS main part */
6761 parts[2] = ctx.main_fn;
6762
6763 /* TCS epilog */
6764 union si_shader_part_key tcs_epilog_key;
6765 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6766 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6767 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6768 parts[3] = ctx.main_fn;
6769
6770 /* VS as LS main part */
6771 struct si_shader shader_ls = {};
6772 shader_ls.selector = ls;
6773 shader_ls.key.as_ls = 1;
6774 shader_ls.key.mono = shader->key.mono;
6775 shader_ls.key.opt = shader->key.opt;
6776 shader_ls.is_monolithic = true;
6777 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6778
6779 if (!si_compile_tgsi_main(&ctx)) {
6780 si_llvm_dispose(&ctx);
6781 return -1;
6782 }
6783 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6784 parts[1] = ctx.main_fn;
6785
6786 /* LS prolog */
6787 if (vs_needs_prolog) {
6788 union si_shader_part_key vs_prolog_key;
6789 si_get_vs_prolog_key(&ls->info,
6790 shader_ls.info.num_input_sgprs,
6791 &shader->key.part.tcs.ls_prolog,
6792 shader, &vs_prolog_key);
6793 vs_prolog_key.vs_prolog.is_monolithic = true;
6794 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6795 parts[0] = ctx.main_fn;
6796 }
6797
6798 /* Reset the shader context. */
6799 ctx.shader = shader;
6800 ctx.type = PIPE_SHADER_TESS_CTRL;
6801
6802 si_build_wrapper_function(&ctx,
6803 parts + !vs_needs_prolog,
6804 4 - !vs_needs_prolog, vs_needs_prolog,
6805 vs_needs_prolog ? 2 : 1);
6806 } else {
6807 LLVMValueRef parts[2];
6808 union si_shader_part_key epilog_key;
6809
6810 parts[0] = ctx.main_fn;
6811
6812 memset(&epilog_key, 0, sizeof(epilog_key));
6813 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6814 si_build_tcs_epilog_function(&ctx, &epilog_key);
6815 parts[1] = ctx.main_fn;
6816
6817 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6818 }
6819 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6820 if (ctx.screen->info.chip_class >= GFX9) {
6821 struct si_shader_selector *es = shader->key.part.gs.es;
6822 LLVMValueRef es_prolog = NULL;
6823 LLVMValueRef es_main = NULL;
6824 LLVMValueRef gs_prolog = NULL;
6825 LLVMValueRef gs_main = ctx.main_fn;
6826
6827 /* GS prolog */
6828 union si_shader_part_key gs_prolog_key;
6829 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6830 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6831 gs_prolog_key.gs_prolog.is_monolithic = true;
6832 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6833 gs_prolog = ctx.main_fn;
6834
6835 /* ES main part */
6836 struct si_shader shader_es = {};
6837 shader_es.selector = es;
6838 shader_es.key.as_es = 1;
6839 shader_es.key.mono = shader->key.mono;
6840 shader_es.key.opt = shader->key.opt;
6841 shader_es.is_monolithic = true;
6842 si_llvm_context_set_tgsi(&ctx, &shader_es);
6843
6844 if (!si_compile_tgsi_main(&ctx)) {
6845 si_llvm_dispose(&ctx);
6846 return -1;
6847 }
6848 shader->info.uses_instanceid |= es->info.uses_instanceid;
6849 es_main = ctx.main_fn;
6850
6851 /* ES prolog */
6852 if (es->vs_needs_prolog) {
6853 union si_shader_part_key vs_prolog_key;
6854 si_get_vs_prolog_key(&es->info,
6855 shader_es.info.num_input_sgprs,
6856 &shader->key.part.gs.vs_prolog,
6857 shader, &vs_prolog_key);
6858 vs_prolog_key.vs_prolog.is_monolithic = true;
6859 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6860 es_prolog = ctx.main_fn;
6861 }
6862
6863 /* Reset the shader context. */
6864 ctx.shader = shader;
6865 ctx.type = PIPE_SHADER_GEOMETRY;
6866
6867 /* Prepare the array of shader parts. */
6868 LLVMValueRef parts[4];
6869 unsigned num_parts = 0, main_part, next_first_part;
6870
6871 if (es_prolog)
6872 parts[num_parts++] = es_prolog;
6873
6874 parts[main_part = num_parts++] = es_main;
6875 parts[next_first_part = num_parts++] = gs_prolog;
6876 parts[num_parts++] = gs_main;
6877
6878 si_build_wrapper_function(&ctx, parts, num_parts,
6879 main_part, next_first_part);
6880 } else {
6881 LLVMValueRef parts[2];
6882 union si_shader_part_key prolog_key;
6883
6884 parts[1] = ctx.main_fn;
6885
6886 memset(&prolog_key, 0, sizeof(prolog_key));
6887 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6888 si_build_gs_prolog_function(&ctx, &prolog_key);
6889 parts[0] = ctx.main_fn;
6890
6891 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6892 }
6893 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6894 LLVMValueRef parts[3];
6895 union si_shader_part_key prolog_key;
6896 union si_shader_part_key epilog_key;
6897 bool need_prolog;
6898
6899 si_get_ps_prolog_key(shader, &prolog_key, false);
6900 need_prolog = si_need_ps_prolog(&prolog_key);
6901
6902 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6903
6904 if (need_prolog) {
6905 si_build_ps_prolog_function(&ctx, &prolog_key);
6906 parts[0] = ctx.main_fn;
6907 }
6908
6909 si_get_ps_epilog_key(shader, &epilog_key);
6910 si_build_ps_epilog_function(&ctx, &epilog_key);
6911 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6912
6913 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6914 need_prolog ? 1 : 0, 0);
6915 }
6916
6917 si_llvm_optimize_module(&ctx);
6918
6919 /* Post-optimization transformations and analysis. */
6920 si_optimize_vs_outputs(&ctx);
6921
6922 if ((debug && debug->debug_message) ||
6923 si_can_dump_shader(sscreen, ctx.type)) {
6924 ctx.shader->config.private_mem_vgprs =
6925 ac_count_scratch_private_memory(ctx.main_fn);
6926 }
6927
6928 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6929 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6930 LLVMPointerTypeKind);
6931
6932 /* Compile to bytecode. */
6933 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6934 ctx.ac.module, debug, ctx.type,
6935 si_get_shader_name(shader, ctx.type),
6936 si_should_optimize_less(compiler, shader->selector));
6937 si_llvm_dispose(&ctx);
6938 if (r) {
6939 fprintf(stderr, "LLVM failed to compile shader\n");
6940 return r;
6941 }
6942
6943 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6944 * LLVM 3.9svn has this bug.
6945 */
6946 if (sel->type == PIPE_SHADER_COMPUTE) {
6947 unsigned wave_size = 64;
6948 unsigned max_vgprs = 256;
6949 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6950 unsigned max_sgprs_per_wave = 128;
6951 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6952 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6953 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6954
6955 max_vgprs = max_vgprs / min_waves_per_simd;
6956 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6957
6958 if (shader->config.num_sgprs > max_sgprs ||
6959 shader->config.num_vgprs > max_vgprs) {
6960 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6961 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6962 shader->config.num_sgprs, shader->config.num_vgprs,
6963 max_sgprs, max_vgprs);
6964
6965 /* Just terminate the process, because dependent
6966 * shaders can hang due to bad input data, but use
6967 * the env var to allow shader-db to work.
6968 */
6969 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6970 abort();
6971 }
6972 }
6973
6974 /* Add the scratch offset to input SGPRs. */
6975 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6976 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6977
6978 /* Calculate the number of fragment input VGPRs. */
6979 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6980 shader->info.num_input_vgprs = 0;
6981 shader->info.face_vgpr_index = -1;
6982 shader->info.ancillary_vgpr_index = -1;
6983
6984 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6985 shader->info.num_input_vgprs += 2;
6986 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6987 shader->info.num_input_vgprs += 2;
6988 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6989 shader->info.num_input_vgprs += 2;
6990 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6991 shader->info.num_input_vgprs += 3;
6992 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6993 shader->info.num_input_vgprs += 2;
6994 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6995 shader->info.num_input_vgprs += 2;
6996 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6997 shader->info.num_input_vgprs += 2;
6998 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6999 shader->info.num_input_vgprs += 1;
7000 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7001 shader->info.num_input_vgprs += 1;
7002 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7003 shader->info.num_input_vgprs += 1;
7004 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7005 shader->info.num_input_vgprs += 1;
7006 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7007 shader->info.num_input_vgprs += 1;
7008 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7009 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7010 shader->info.num_input_vgprs += 1;
7011 }
7012 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7013 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7014 shader->info.num_input_vgprs += 1;
7015 }
7016 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7017 shader->info.num_input_vgprs += 1;
7018 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7019 shader->info.num_input_vgprs += 1;
7020 }
7021
7022 si_calculate_max_simd_waves(shader);
7023 si_shader_dump_stats_for_shader_db(shader, debug);
7024 return 0;
7025 }
7026
7027 /**
7028 * Create, compile and return a shader part (prolog or epilog).
7029 *
7030 * \param sscreen screen
7031 * \param list list of shader parts of the same category
7032 * \param type shader type
7033 * \param key shader part key
7034 * \param prolog whether the part being requested is a prolog
7035 * \param tm LLVM target machine
7036 * \param debug debug callback
7037 * \param build the callback responsible for building the main function
7038 * \return non-NULL on success
7039 */
7040 static struct si_shader_part *
7041 si_get_shader_part(struct si_screen *sscreen,
7042 struct si_shader_part **list,
7043 enum pipe_shader_type type,
7044 bool prolog,
7045 union si_shader_part_key *key,
7046 struct ac_llvm_compiler *compiler,
7047 struct pipe_debug_callback *debug,
7048 void (*build)(struct si_shader_context *,
7049 union si_shader_part_key *),
7050 const char *name)
7051 {
7052 struct si_shader_part *result;
7053
7054 mtx_lock(&sscreen->shader_parts_mutex);
7055
7056 /* Find existing. */
7057 for (result = *list; result; result = result->next) {
7058 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7059 mtx_unlock(&sscreen->shader_parts_mutex);
7060 return result;
7061 }
7062 }
7063
7064 /* Compile a new one. */
7065 result = CALLOC_STRUCT(si_shader_part);
7066 result->key = *key;
7067
7068 struct si_shader shader = {};
7069 struct si_shader_context ctx;
7070
7071 si_init_shader_ctx(&ctx, sscreen, compiler);
7072 ctx.shader = &shader;
7073 ctx.type = type;
7074
7075 switch (type) {
7076 case PIPE_SHADER_VERTEX:
7077 shader.key.as_ls = key->vs_prolog.as_ls;
7078 shader.key.as_es = key->vs_prolog.as_es;
7079 break;
7080 case PIPE_SHADER_TESS_CTRL:
7081 assert(!prolog);
7082 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7083 break;
7084 case PIPE_SHADER_GEOMETRY:
7085 assert(prolog);
7086 break;
7087 case PIPE_SHADER_FRAGMENT:
7088 if (prolog)
7089 shader.key.part.ps.prolog = key->ps_prolog.states;
7090 else
7091 shader.key.part.ps.epilog = key->ps_epilog.states;
7092 break;
7093 default:
7094 unreachable("bad shader part");
7095 }
7096
7097 build(&ctx, key);
7098
7099 /* Compile. */
7100 si_llvm_optimize_module(&ctx);
7101
7102 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7103 ctx.ac.module, debug, ctx.type, name, false)) {
7104 FREE(result);
7105 result = NULL;
7106 goto out;
7107 }
7108
7109 result->next = *list;
7110 *list = result;
7111
7112 out:
7113 si_llvm_dispose(&ctx);
7114 mtx_unlock(&sscreen->shader_parts_mutex);
7115 return result;
7116 }
7117
7118 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7119 {
7120 LLVMValueRef ptr[2], list;
7121 bool merged_shader = is_merged_shader(ctx);
7122
7123 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7124 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7125 ac_array_in_const32_addr_space(ctx->v4i32), "");
7126 return list;
7127 }
7128
7129 /**
7130 * Build the vertex shader prolog function.
7131 *
7132 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7133 * All inputs are returned unmodified. The vertex load indices are
7134 * stored after them, which will be used by the API VS for fetching inputs.
7135 *
7136 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7137 * input_v0,
7138 * input_v1,
7139 * input_v2,
7140 * input_v3,
7141 * (VertexID + BaseVertex),
7142 * (InstanceID + StartInstance),
7143 * (InstanceID / 2 + StartInstance)
7144 */
7145 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7146 union si_shader_part_key *key)
7147 {
7148 struct si_function_info fninfo;
7149 LLVMTypeRef *returns;
7150 LLVMValueRef ret, func;
7151 int num_returns, i;
7152 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7153 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7154 LLVMValueRef input_vgprs[9];
7155 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7156 num_input_vgprs;
7157 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7158
7159 si_init_function_info(&fninfo);
7160
7161 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7162 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7163 sizeof(LLVMTypeRef));
7164 num_returns = 0;
7165
7166 /* Declare input and output SGPRs. */
7167 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7168 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7169 returns[num_returns++] = ctx->i32;
7170 }
7171
7172 /* Preloaded VGPRs (outputs must be floats) */
7173 for (i = 0; i < num_input_vgprs; i++) {
7174 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7175 returns[num_returns++] = ctx->f32;
7176 }
7177
7178 /* Vertex load indices. */
7179 for (i = 0; i <= key->vs_prolog.last_input; i++)
7180 returns[num_returns++] = ctx->f32;
7181
7182 /* Create the function. */
7183 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7184 func = ctx->main_fn;
7185
7186 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7187 if (!key->vs_prolog.is_monolithic)
7188 si_init_exec_from_input(ctx, 3, 0);
7189
7190 if (key->vs_prolog.as_ls &&
7191 ctx->screen->has_ls_vgpr_init_bug) {
7192 /* If there are no HS threads, SPI loads the LS VGPRs
7193 * starting at VGPR 0. Shift them back to where they
7194 * belong.
7195 */
7196 LLVMValueRef has_hs_threads =
7197 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7198 si_unpack_param(ctx, 3, 8, 8),
7199 ctx->i32_0, "");
7200
7201 for (i = 4; i > 0; --i) {
7202 input_vgprs[i + 1] =
7203 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7204 input_vgprs[i + 1],
7205 input_vgprs[i - 1], "");
7206 }
7207 }
7208 }
7209
7210 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7211 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7212
7213 /* Copy inputs to outputs. This should be no-op, as the registers match,
7214 * but it will prevent the compiler from overwriting them unintentionally.
7215 */
7216 ret = ctx->return_value;
7217 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7218 LLVMValueRef p = LLVMGetParam(func, i);
7219 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7220 }
7221 for (i = 0; i < num_input_vgprs; i++) {
7222 LLVMValueRef p = input_vgprs[i];
7223 p = ac_to_float(&ctx->ac, p);
7224 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7225 key->vs_prolog.num_input_sgprs + i, "");
7226 }
7227
7228 /* Compute vertex load indices from instance divisors. */
7229 LLVMValueRef instance_divisor_constbuf = NULL;
7230
7231 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7232 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7233 LLVMValueRef buf_index =
7234 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7235 instance_divisor_constbuf =
7236 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7237 }
7238
7239 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7240 bool divisor_is_one =
7241 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7242 bool divisor_is_fetched =
7243 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7244 LLVMValueRef index = NULL;
7245
7246 if (divisor_is_one) {
7247 index = ctx->abi.instance_id;
7248 } else if (divisor_is_fetched) {
7249 LLVMValueRef udiv_factors[4];
7250
7251 for (unsigned j = 0; j < 4; j++) {
7252 udiv_factors[j] =
7253 buffer_load_const(ctx, instance_divisor_constbuf,
7254 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7255 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7256 }
7257 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7258 * Such InstanceID might not be achievable in a reasonable time though.
7259 */
7260 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7261 udiv_factors[0], udiv_factors[1],
7262 udiv_factors[2], udiv_factors[3]);
7263 }
7264
7265 if (divisor_is_one || divisor_is_fetched) {
7266 /* Add StartInstance. */
7267 index = LLVMBuildAdd(ctx->ac.builder, index,
7268 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7269 SI_SGPR_START_INSTANCE), "");
7270 } else {
7271 /* VertexID + BaseVertex */
7272 index = LLVMBuildAdd(ctx->ac.builder,
7273 ctx->abi.vertex_id,
7274 LLVMGetParam(func, user_sgpr_base +
7275 SI_SGPR_BASE_VERTEX), "");
7276 }
7277
7278 index = ac_to_float(&ctx->ac, index);
7279 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7280 fninfo.num_params + i, "");
7281 }
7282
7283 si_llvm_build_ret(ctx, ret);
7284 }
7285
7286 static bool si_get_vs_prolog(struct si_screen *sscreen,
7287 struct ac_llvm_compiler *compiler,
7288 struct si_shader *shader,
7289 struct pipe_debug_callback *debug,
7290 struct si_shader *main_part,
7291 const struct si_vs_prolog_bits *key)
7292 {
7293 struct si_shader_selector *vs = main_part->selector;
7294
7295 if (!si_vs_needs_prolog(vs, key))
7296 return true;
7297
7298 /* Get the prolog. */
7299 union si_shader_part_key prolog_key;
7300 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7301 key, shader, &prolog_key);
7302
7303 shader->prolog =
7304 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7305 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7306 debug, si_build_vs_prolog_function,
7307 "Vertex Shader Prolog");
7308 return shader->prolog != NULL;
7309 }
7310
7311 /**
7312 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7313 */
7314 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7315 struct ac_llvm_compiler *compiler,
7316 struct si_shader *shader,
7317 struct pipe_debug_callback *debug)
7318 {
7319 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7320 &shader->key.part.vs.prolog);
7321 }
7322
7323 /**
7324 * Compile the TCS epilog function. This writes tesselation factors to memory
7325 * based on the output primitive type of the tesselator (determined by TES).
7326 */
7327 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7328 union si_shader_part_key *key)
7329 {
7330 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7331 struct si_function_info fninfo;
7332 LLVMValueRef func;
7333
7334 si_init_function_info(&fninfo);
7335
7336 if (ctx->screen->info.chip_class >= GFX9) {
7337 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7340 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7341 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7344 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7345 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7346 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7347 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7348 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7349 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7351 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7352 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7353 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7354 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7355 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7356 } else {
7357 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7358 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7359 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7360 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7361 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7362 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7363 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7364 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7365 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7366 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7367 }
7368
7369 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7370 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7371 unsigned tess_factors_idx =
7372 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7373 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7374 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7375
7376 for (unsigned i = 0; i < 6; i++)
7377 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7378
7379 /* Create the function. */
7380 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7381 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7382 ac_declare_lds_as_pointer(&ctx->ac);
7383 func = ctx->main_fn;
7384
7385 LLVMValueRef invoc0_tess_factors[6];
7386 for (unsigned i = 0; i < 6; i++)
7387 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7388
7389 si_write_tess_factors(bld_base,
7390 LLVMGetParam(func, tess_factors_idx),
7391 LLVMGetParam(func, tess_factors_idx + 1),
7392 LLVMGetParam(func, tess_factors_idx + 2),
7393 invoc0_tess_factors, invoc0_tess_factors + 4);
7394
7395 LLVMBuildRetVoid(ctx->ac.builder);
7396 }
7397
7398 /**
7399 * Select and compile (or reuse) TCS parts (epilog).
7400 */
7401 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7402 struct ac_llvm_compiler *compiler,
7403 struct si_shader *shader,
7404 struct pipe_debug_callback *debug)
7405 {
7406 if (sscreen->info.chip_class >= GFX9) {
7407 struct si_shader *ls_main_part =
7408 shader->key.part.tcs.ls->main_shader_part_ls;
7409
7410 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7411 &shader->key.part.tcs.ls_prolog))
7412 return false;
7413
7414 shader->previous_stage = ls_main_part;
7415 }
7416
7417 /* Get the epilog. */
7418 union si_shader_part_key epilog_key;
7419 memset(&epilog_key, 0, sizeof(epilog_key));
7420 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7421
7422 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7423 PIPE_SHADER_TESS_CTRL, false,
7424 &epilog_key, compiler, debug,
7425 si_build_tcs_epilog_function,
7426 "Tessellation Control Shader Epilog");
7427 return shader->epilog != NULL;
7428 }
7429
7430 /**
7431 * Select and compile (or reuse) GS parts (prolog).
7432 */
7433 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7434 struct ac_llvm_compiler *compiler,
7435 struct si_shader *shader,
7436 struct pipe_debug_callback *debug)
7437 {
7438 if (sscreen->info.chip_class >= GFX9) {
7439 struct si_shader *es_main_part =
7440 shader->key.part.gs.es->main_shader_part_es;
7441
7442 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7443 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7444 &shader->key.part.gs.vs_prolog))
7445 return false;
7446
7447 shader->previous_stage = es_main_part;
7448 }
7449
7450 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7451 return true;
7452
7453 union si_shader_part_key prolog_key;
7454 memset(&prolog_key, 0, sizeof(prolog_key));
7455 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7456
7457 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7458 PIPE_SHADER_GEOMETRY, true,
7459 &prolog_key, compiler, debug,
7460 si_build_gs_prolog_function,
7461 "Geometry Shader Prolog");
7462 return shader->prolog2 != NULL;
7463 }
7464
7465 /**
7466 * Build the pixel shader prolog function. This handles:
7467 * - two-side color selection and interpolation
7468 * - overriding interpolation parameters for the API PS
7469 * - polygon stippling
7470 *
7471 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7472 * overriden by other states. (e.g. per-sample interpolation)
7473 * Interpolated colors are stored after the preloaded VGPRs.
7474 */
7475 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7476 union si_shader_part_key *key)
7477 {
7478 struct si_function_info fninfo;
7479 LLVMValueRef ret, func;
7480 int num_returns, i, num_color_channels;
7481
7482 assert(si_need_ps_prolog(key));
7483
7484 si_init_function_info(&fninfo);
7485
7486 /* Declare inputs. */
7487 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7488 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7489
7490 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7491 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7492
7493 /* Declare outputs (same as inputs + add colors if needed) */
7494 num_returns = fninfo.num_params;
7495 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7496 for (i = 0; i < num_color_channels; i++)
7497 fninfo.types[num_returns++] = ctx->f32;
7498
7499 /* Create the function. */
7500 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7501 &fninfo, 0);
7502 func = ctx->main_fn;
7503
7504 /* Copy inputs to outputs. This should be no-op, as the registers match,
7505 * but it will prevent the compiler from overwriting them unintentionally.
7506 */
7507 ret = ctx->return_value;
7508 for (i = 0; i < fninfo.num_params; i++) {
7509 LLVMValueRef p = LLVMGetParam(func, i);
7510 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7511 }
7512
7513 /* Polygon stippling. */
7514 if (key->ps_prolog.states.poly_stipple) {
7515 /* POS_FIXED_PT is always last. */
7516 unsigned pos = key->ps_prolog.num_input_sgprs +
7517 key->ps_prolog.num_input_vgprs - 1;
7518 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7519
7520 si_llvm_emit_polygon_stipple(ctx, list, pos);
7521 }
7522
7523 if (key->ps_prolog.states.bc_optimize_for_persp ||
7524 key->ps_prolog.states.bc_optimize_for_linear) {
7525 unsigned i, base = key->ps_prolog.num_input_sgprs;
7526 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7527
7528 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7529 * The hw doesn't compute CENTROID if the whole wave only
7530 * contains fully-covered quads.
7531 *
7532 * PRIM_MASK is after user SGPRs.
7533 */
7534 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7535 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7536 LLVMConstInt(ctx->i32, 31, 0), "");
7537 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7538 ctx->i1, "");
7539
7540 if (key->ps_prolog.states.bc_optimize_for_persp) {
7541 /* Read PERSP_CENTER. */
7542 for (i = 0; i < 2; i++)
7543 center[i] = LLVMGetParam(func, base + 2 + i);
7544 /* Read PERSP_CENTROID. */
7545 for (i = 0; i < 2; i++)
7546 centroid[i] = LLVMGetParam(func, base + 4 + i);
7547 /* Select PERSP_CENTROID. */
7548 for (i = 0; i < 2; i++) {
7549 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7550 center[i], centroid[i], "");
7551 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7552 tmp, base + 4 + i, "");
7553 }
7554 }
7555 if (key->ps_prolog.states.bc_optimize_for_linear) {
7556 /* Read LINEAR_CENTER. */
7557 for (i = 0; i < 2; i++)
7558 center[i] = LLVMGetParam(func, base + 8 + i);
7559 /* Read LINEAR_CENTROID. */
7560 for (i = 0; i < 2; i++)
7561 centroid[i] = LLVMGetParam(func, base + 10 + i);
7562 /* Select LINEAR_CENTROID. */
7563 for (i = 0; i < 2; i++) {
7564 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7565 center[i], centroid[i], "");
7566 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7567 tmp, base + 10 + i, "");
7568 }
7569 }
7570 }
7571
7572 /* Force per-sample interpolation. */
7573 if (key->ps_prolog.states.force_persp_sample_interp) {
7574 unsigned i, base = key->ps_prolog.num_input_sgprs;
7575 LLVMValueRef persp_sample[2];
7576
7577 /* Read PERSP_SAMPLE. */
7578 for (i = 0; i < 2; i++)
7579 persp_sample[i] = LLVMGetParam(func, base + i);
7580 /* Overwrite PERSP_CENTER. */
7581 for (i = 0; i < 2; i++)
7582 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7583 persp_sample[i], base + 2 + i, "");
7584 /* Overwrite PERSP_CENTROID. */
7585 for (i = 0; i < 2; i++)
7586 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7587 persp_sample[i], base + 4 + i, "");
7588 }
7589 if (key->ps_prolog.states.force_linear_sample_interp) {
7590 unsigned i, base = key->ps_prolog.num_input_sgprs;
7591 LLVMValueRef linear_sample[2];
7592
7593 /* Read LINEAR_SAMPLE. */
7594 for (i = 0; i < 2; i++)
7595 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7596 /* Overwrite LINEAR_CENTER. */
7597 for (i = 0; i < 2; i++)
7598 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7599 linear_sample[i], base + 8 + i, "");
7600 /* Overwrite LINEAR_CENTROID. */
7601 for (i = 0; i < 2; i++)
7602 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7603 linear_sample[i], base + 10 + i, "");
7604 }
7605
7606 /* Force center interpolation. */
7607 if (key->ps_prolog.states.force_persp_center_interp) {
7608 unsigned i, base = key->ps_prolog.num_input_sgprs;
7609 LLVMValueRef persp_center[2];
7610
7611 /* Read PERSP_CENTER. */
7612 for (i = 0; i < 2; i++)
7613 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7614 /* Overwrite PERSP_SAMPLE. */
7615 for (i = 0; i < 2; i++)
7616 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7617 persp_center[i], base + i, "");
7618 /* Overwrite PERSP_CENTROID. */
7619 for (i = 0; i < 2; i++)
7620 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7621 persp_center[i], base + 4 + i, "");
7622 }
7623 if (key->ps_prolog.states.force_linear_center_interp) {
7624 unsigned i, base = key->ps_prolog.num_input_sgprs;
7625 LLVMValueRef linear_center[2];
7626
7627 /* Read LINEAR_CENTER. */
7628 for (i = 0; i < 2; i++)
7629 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7630 /* Overwrite LINEAR_SAMPLE. */
7631 for (i = 0; i < 2; i++)
7632 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7633 linear_center[i], base + 6 + i, "");
7634 /* Overwrite LINEAR_CENTROID. */
7635 for (i = 0; i < 2; i++)
7636 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7637 linear_center[i], base + 10 + i, "");
7638 }
7639
7640 /* Interpolate colors. */
7641 unsigned color_out_idx = 0;
7642 for (i = 0; i < 2; i++) {
7643 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7644 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7645 key->ps_prolog.face_vgpr_index;
7646 LLVMValueRef interp[2], color[4];
7647 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7648
7649 if (!writemask)
7650 continue;
7651
7652 /* If the interpolation qualifier is not CONSTANT (-1). */
7653 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7654 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7655 key->ps_prolog.color_interp_vgpr_index[i];
7656
7657 /* Get the (i,j) updated by bc_optimize handling. */
7658 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7659 interp_vgpr, "");
7660 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7661 interp_vgpr + 1, "");
7662 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7663 }
7664
7665 /* Use the absolute location of the input. */
7666 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7667
7668 if (key->ps_prolog.states.color_two_side) {
7669 face = LLVMGetParam(func, face_vgpr);
7670 face = ac_to_integer(&ctx->ac, face);
7671 }
7672
7673 interp_fs_input(ctx,
7674 key->ps_prolog.color_attr_index[i],
7675 TGSI_SEMANTIC_COLOR, i,
7676 key->ps_prolog.num_interp_inputs,
7677 key->ps_prolog.colors_read, interp_ij,
7678 prim_mask, face, color);
7679
7680 while (writemask) {
7681 unsigned chan = u_bit_scan(&writemask);
7682 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7683 fninfo.num_params + color_out_idx++, "");
7684 }
7685 }
7686
7687 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7688 * says:
7689 *
7690 * "When per-sample shading is active due to the use of a fragment
7691 * input qualified by sample or due to the use of the gl_SampleID
7692 * or gl_SamplePosition variables, only the bit for the current
7693 * sample is set in gl_SampleMaskIn. When state specifies multiple
7694 * fragment shader invocations for a given fragment, the sample
7695 * mask for any single fragment shader invocation may specify a
7696 * subset of the covered samples for the fragment. In this case,
7697 * the bit corresponding to each covered sample will be set in
7698 * exactly one fragment shader invocation."
7699 *
7700 * The samplemask loaded by hardware is always the coverage of the
7701 * entire pixel/fragment, so mask bits out based on the sample ID.
7702 */
7703 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7704 /* The bit pattern matches that used by fixed function fragment
7705 * processing. */
7706 static const uint16_t ps_iter_masks[] = {
7707 0xffff, /* not used */
7708 0x5555,
7709 0x1111,
7710 0x0101,
7711 0x0001,
7712 };
7713 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7714
7715 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7716 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7717 key->ps_prolog.ancillary_vgpr_index;
7718 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7719 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7720
7721 samplemask = ac_to_integer(&ctx->ac, samplemask);
7722 samplemask = LLVMBuildAnd(
7723 ctx->ac.builder,
7724 samplemask,
7725 LLVMBuildShl(ctx->ac.builder,
7726 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7727 sampleid, ""),
7728 "");
7729 samplemask = ac_to_float(&ctx->ac, samplemask);
7730
7731 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7732 ancillary_vgpr + 1, "");
7733 }
7734
7735 /* Tell LLVM to insert WQM instruction sequence when needed. */
7736 if (key->ps_prolog.wqm) {
7737 LLVMAddTargetDependentFunctionAttr(func,
7738 "amdgpu-ps-wqm-outputs", "");
7739 }
7740
7741 si_llvm_build_ret(ctx, ret);
7742 }
7743
7744 /**
7745 * Build the pixel shader epilog function. This handles everything that must be
7746 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7747 */
7748 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7749 union si_shader_part_key *key)
7750 {
7751 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7752 struct si_function_info fninfo;
7753 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7754 int i;
7755 struct si_ps_exports exp = {};
7756
7757 si_init_function_info(&fninfo);
7758
7759 /* Declare input SGPRs. */
7760 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7761 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7762 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7763 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7764 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7765
7766 /* Declare input VGPRs. */
7767 unsigned required_num_params =
7768 fninfo.num_sgpr_params +
7769 util_bitcount(key->ps_epilog.colors_written) * 4 +
7770 key->ps_epilog.writes_z +
7771 key->ps_epilog.writes_stencil +
7772 key->ps_epilog.writes_samplemask;
7773
7774 required_num_params = MAX2(required_num_params,
7775 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7776
7777 while (fninfo.num_params < required_num_params)
7778 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7779
7780 /* Create the function. */
7781 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7782 /* Disable elimination of unused inputs. */
7783 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7784 "InitialPSInputAddr", 0xffffff);
7785
7786 /* Process colors. */
7787 unsigned vgpr = fninfo.num_sgpr_params;
7788 unsigned colors_written = key->ps_epilog.colors_written;
7789 int last_color_export = -1;
7790
7791 /* Find the last color export. */
7792 if (!key->ps_epilog.writes_z &&
7793 !key->ps_epilog.writes_stencil &&
7794 !key->ps_epilog.writes_samplemask) {
7795 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7796
7797 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7798 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7799 /* Just set this if any of the colorbuffers are enabled. */
7800 if (spi_format &
7801 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7802 last_color_export = 0;
7803 } else {
7804 for (i = 0; i < 8; i++)
7805 if (colors_written & (1 << i) &&
7806 (spi_format >> (i * 4)) & 0xf)
7807 last_color_export = i;
7808 }
7809 }
7810
7811 while (colors_written) {
7812 LLVMValueRef color[4];
7813 int mrt = u_bit_scan(&colors_written);
7814
7815 for (i = 0; i < 4; i++)
7816 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7817
7818 si_export_mrt_color(bld_base, color, mrt,
7819 fninfo.num_params - 1,
7820 mrt == last_color_export, &exp);
7821 }
7822
7823 /* Process depth, stencil, samplemask. */
7824 if (key->ps_epilog.writes_z)
7825 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7826 if (key->ps_epilog.writes_stencil)
7827 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7828 if (key->ps_epilog.writes_samplemask)
7829 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7830
7831 if (depth || stencil || samplemask)
7832 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7833 else if (last_color_export == -1)
7834 ac_build_export_null(&ctx->ac);
7835
7836 if (exp.num)
7837 si_emit_ps_exports(ctx, &exp);
7838
7839 /* Compile. */
7840 LLVMBuildRetVoid(ctx->ac.builder);
7841 }
7842
7843 /**
7844 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7845 */
7846 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7847 struct ac_llvm_compiler *compiler,
7848 struct si_shader *shader,
7849 struct pipe_debug_callback *debug)
7850 {
7851 union si_shader_part_key prolog_key;
7852 union si_shader_part_key epilog_key;
7853
7854 /* Get the prolog. */
7855 si_get_ps_prolog_key(shader, &prolog_key, true);
7856
7857 /* The prolog is a no-op if these aren't set. */
7858 if (si_need_ps_prolog(&prolog_key)) {
7859 shader->prolog =
7860 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7861 PIPE_SHADER_FRAGMENT, true,
7862 &prolog_key, compiler, debug,
7863 si_build_ps_prolog_function,
7864 "Fragment Shader Prolog");
7865 if (!shader->prolog)
7866 return false;
7867 }
7868
7869 /* Get the epilog. */
7870 si_get_ps_epilog_key(shader, &epilog_key);
7871
7872 shader->epilog =
7873 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7874 PIPE_SHADER_FRAGMENT, false,
7875 &epilog_key, compiler, debug,
7876 si_build_ps_epilog_function,
7877 "Fragment Shader Epilog");
7878 if (!shader->epilog)
7879 return false;
7880
7881 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7882 if (shader->key.part.ps.prolog.poly_stipple) {
7883 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7884 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7885 }
7886
7887 /* Set up the enable bits for per-sample shading if needed. */
7888 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7889 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7890 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7891 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7892 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7893 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7894 }
7895 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7896 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7897 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7898 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7899 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7900 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7901 }
7902 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7903 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7904 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7905 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7906 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7907 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7908 }
7909 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7910 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7911 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7912 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7913 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7914 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7915 }
7916
7917 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7918 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7919 !(shader->config.spi_ps_input_ena & 0xf)) {
7920 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7921 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7922 }
7923
7924 /* At least one pair of interpolation weights must be enabled. */
7925 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7926 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7927 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7928 }
7929
7930 /* Samplemask fixup requires the sample ID. */
7931 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7932 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7933 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7934 }
7935
7936 /* The sample mask input is always enabled, because the API shader always
7937 * passes it through to the epilog. Disable it here if it's unused.
7938 */
7939 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7940 !shader->selector->info.reads_samplemask)
7941 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7942
7943 return true;
7944 }
7945
7946 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7947 unsigned *lds_size)
7948 {
7949 /* If tessellation is all offchip and on-chip GS isn't used, this
7950 * workaround is not needed.
7951 */
7952 return;
7953
7954 /* SPI barrier management bug:
7955 * Make sure we have at least 4k of LDS in use to avoid the bug.
7956 * It applies to workgroup sizes of more than one wavefront.
7957 */
7958 if (sscreen->info.family == CHIP_BONAIRE ||
7959 sscreen->info.family == CHIP_KABINI ||
7960 sscreen->info.family == CHIP_MULLINS)
7961 *lds_size = MAX2(*lds_size, 8);
7962 }
7963
7964 static void si_fix_resource_usage(struct si_screen *sscreen,
7965 struct si_shader *shader)
7966 {
7967 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7968
7969 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7970
7971 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7972 si_get_max_workgroup_size(shader) > 64) {
7973 si_multiwave_lds_size_workaround(sscreen,
7974 &shader->config.lds_size);
7975 }
7976 }
7977
7978 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7979 struct si_shader *shader,
7980 struct pipe_debug_callback *debug)
7981 {
7982 struct si_shader_selector *sel = shader->selector;
7983 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7984 int r;
7985
7986 /* LS, ES, VS are compiled on demand if the main part hasn't been
7987 * compiled for that stage.
7988 *
7989 * Vertex shaders are compiled on demand when a vertex fetch
7990 * workaround must be applied.
7991 */
7992 if (shader->is_monolithic) {
7993 /* Monolithic shader (compiled as a whole, has many variants,
7994 * may take a long time to compile).
7995 */
7996 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7997 if (r)
7998 return r;
7999 } else {
8000 /* The shader consists of several parts:
8001 *
8002 * - the middle part is the user shader, it has 1 variant only
8003 * and it was compiled during the creation of the shader
8004 * selector
8005 * - the prolog part is inserted at the beginning
8006 * - the epilog part is inserted at the end
8007 *
8008 * The prolog and epilog have many (but simple) variants.
8009 *
8010 * Starting with gfx9, geometry and tessellation control
8011 * shaders also contain the prolog and user shader parts of
8012 * the previous shader stage.
8013 */
8014
8015 if (!mainp)
8016 return -1;
8017
8018 /* Copy the compiled TGSI shader data over. */
8019 shader->is_binary_shared = true;
8020 shader->binary = mainp->binary;
8021 shader->config = mainp->config;
8022 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8023 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8024 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8025 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8026 memcpy(shader->info.vs_output_param_offset,
8027 mainp->info.vs_output_param_offset,
8028 sizeof(mainp->info.vs_output_param_offset));
8029 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8030 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8031 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8032
8033 /* Select prologs and/or epilogs. */
8034 switch (sel->type) {
8035 case PIPE_SHADER_VERTEX:
8036 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8037 return -1;
8038 break;
8039 case PIPE_SHADER_TESS_CTRL:
8040 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8041 return -1;
8042 break;
8043 case PIPE_SHADER_TESS_EVAL:
8044 break;
8045 case PIPE_SHADER_GEOMETRY:
8046 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8047 return -1;
8048 break;
8049 case PIPE_SHADER_FRAGMENT:
8050 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8051 return -1;
8052
8053 /* Make sure we have at least as many VGPRs as there
8054 * are allocated inputs.
8055 */
8056 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8057 shader->info.num_input_vgprs);
8058 break;
8059 }
8060
8061 /* Update SGPR and VGPR counts. */
8062 if (shader->prolog) {
8063 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8064 shader->prolog->config.num_sgprs);
8065 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8066 shader->prolog->config.num_vgprs);
8067 }
8068 if (shader->previous_stage) {
8069 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8070 shader->previous_stage->config.num_sgprs);
8071 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8072 shader->previous_stage->config.num_vgprs);
8073 shader->config.spilled_sgprs =
8074 MAX2(shader->config.spilled_sgprs,
8075 shader->previous_stage->config.spilled_sgprs);
8076 shader->config.spilled_vgprs =
8077 MAX2(shader->config.spilled_vgprs,
8078 shader->previous_stage->config.spilled_vgprs);
8079 shader->config.private_mem_vgprs =
8080 MAX2(shader->config.private_mem_vgprs,
8081 shader->previous_stage->config.private_mem_vgprs);
8082 shader->config.scratch_bytes_per_wave =
8083 MAX2(shader->config.scratch_bytes_per_wave,
8084 shader->previous_stage->config.scratch_bytes_per_wave);
8085 shader->info.uses_instanceid |=
8086 shader->previous_stage->info.uses_instanceid;
8087 }
8088 if (shader->prolog2) {
8089 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8090 shader->prolog2->config.num_sgprs);
8091 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8092 shader->prolog2->config.num_vgprs);
8093 }
8094 if (shader->epilog) {
8095 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8096 shader->epilog->config.num_sgprs);
8097 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8098 shader->epilog->config.num_vgprs);
8099 }
8100 si_calculate_max_simd_waves(shader);
8101 }
8102
8103 si_fix_resource_usage(sscreen, shader);
8104 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8105 stderr, true);
8106
8107 /* Upload. */
8108 r = si_shader_binary_upload(sscreen, shader);
8109 if (r) {
8110 fprintf(stderr, "LLVM failed to upload shader\n");
8111 return r;
8112 }
8113
8114 return 0;
8115 }
8116
8117 void si_shader_destroy(struct si_shader *shader)
8118 {
8119 if (shader->scratch_bo)
8120 si_resource_reference(&shader->scratch_bo, NULL);
8121
8122 si_resource_reference(&shader->bo, NULL);
8123
8124 if (!shader->is_binary_shared)
8125 ac_shader_binary_clean(&shader->binary);
8126
8127 free(shader->shader_log);
8128 }