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radeonsi/gfx10: update si_get_shader_name
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler);
53
54 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
55 struct lp_build_tgsi_context *bld_base,
56 struct lp_build_emit_data *emit_data);
57
58 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
59 FILE *f);
60
61 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
62 union si_shader_part_key *key);
63 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
64 union si_shader_part_key *key);
65 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
66 union si_shader_part_key *key);
67 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
68 union si_shader_part_key *key);
69 static void si_fix_resource_usage(struct si_screen *sscreen,
70 struct si_shader *shader);
71
72 /* Ideally pass the sample mask input to the PS epilog as v14, which
73 * is its usual location, so that the shader doesn't have to add v_mov.
74 */
75 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
76
77 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
78 LLVMTypeRef type)
79 {
80 if (type == ctx->ac.i64 || type == ctx->ac.f64)
81 return true;
82
83 return false;
84 }
85
86 static bool is_merged_shader(struct si_shader_context *ctx)
87 {
88 if (ctx->screen->info.chip_class <= GFX8)
89 return false;
90
91 return ctx->shader->key.as_ls ||
92 ctx->shader->key.as_es ||
93 ctx->type == PIPE_SHADER_TESS_CTRL ||
94 ctx->type == PIPE_SHADER_GEOMETRY;
95 }
96
97 void si_init_function_info(struct si_function_info *fninfo)
98 {
99 fninfo->num_params = 0;
100 fninfo->num_sgpr_params = 0;
101 }
102
103 unsigned add_arg_assign(struct si_function_info *fninfo,
104 enum si_arg_regfile regfile, LLVMTypeRef type,
105 LLVMValueRef *assign)
106 {
107 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
108
109 unsigned idx = fninfo->num_params++;
110 assert(idx < ARRAY_SIZE(fninfo->types));
111
112 if (regfile == ARG_SGPR)
113 fninfo->num_sgpr_params = fninfo->num_params;
114
115 fninfo->types[idx] = type;
116 fninfo->assign[idx] = assign;
117 return idx;
118 }
119
120 static unsigned add_arg(struct si_function_info *fninfo,
121 enum si_arg_regfile regfile, LLVMTypeRef type)
122 {
123 return add_arg_assign(fninfo, regfile, type, NULL);
124 }
125
126 static void add_arg_assign_checked(struct si_function_info *fninfo,
127 enum si_arg_regfile regfile, LLVMTypeRef type,
128 LLVMValueRef *assign, unsigned idx)
129 {
130 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
131 assert(actual == idx);
132 }
133
134 static void add_arg_checked(struct si_function_info *fninfo,
135 enum si_arg_regfile regfile, LLVMTypeRef type,
136 unsigned idx)
137 {
138 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
139 }
140
141 /**
142 * Returns a unique index for a per-patch semantic name and index. The index
143 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
144 * can be calculated.
145 */
146 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
147 {
148 switch (semantic_name) {
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 assert(index < 30);
155 return 2 + index;
156
157 default:
158 assert(!"invalid semantic name");
159 return 0;
160 }
161 }
162
163 /**
164 * Returns a unique index for a semantic name and index. The index must be
165 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
166 * calculated.
167 */
168 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
169 unsigned is_varying)
170 {
171 switch (semantic_name) {
172 case TGSI_SEMANTIC_POSITION:
173 return 0;
174 case TGSI_SEMANTIC_GENERIC:
175 /* Since some shader stages use the the highest used IO index
176 * to determine the size to allocate for inputs/outputs
177 * (in LDS, tess and GS rings). GENERIC should be placed right
178 * after POSITION to make that size as small as possible.
179 */
180 if (index < SI_MAX_IO_GENERIC)
181 return 1 + index;
182
183 assert(!"invalid generic index");
184 return 0;
185 case TGSI_SEMANTIC_PSIZE:
186 return SI_MAX_IO_GENERIC + 1;
187 case TGSI_SEMANTIC_CLIPDIST:
188 assert(index <= 1);
189 return SI_MAX_IO_GENERIC + 2 + index;
190 case TGSI_SEMANTIC_FOG:
191 return SI_MAX_IO_GENERIC + 4;
192 case TGSI_SEMANTIC_LAYER:
193 return SI_MAX_IO_GENERIC + 5;
194 case TGSI_SEMANTIC_VIEWPORT_INDEX:
195 return SI_MAX_IO_GENERIC + 6;
196 case TGSI_SEMANTIC_PRIMID:
197 return SI_MAX_IO_GENERIC + 7;
198 case TGSI_SEMANTIC_COLOR:
199 assert(index < 2);
200 return SI_MAX_IO_GENERIC + 8 + index;
201 case TGSI_SEMANTIC_BCOLOR:
202 assert(index < 2);
203 /* If it's a varying, COLOR and BCOLOR alias. */
204 if (is_varying)
205 return SI_MAX_IO_GENERIC + 8 + index;
206 else
207 return SI_MAX_IO_GENERIC + 10 + index;
208 case TGSI_SEMANTIC_TEXCOORD:
209 assert(index < 8);
210 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
211 return SI_MAX_IO_GENERIC + 12 + index;
212 case TGSI_SEMANTIC_CLIPVERTEX:
213 return 63;
214 default:
215 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
216 assert(!"invalid semantic name");
217 return 0;
218 }
219 }
220
221 /**
222 * Get the value of a shader input parameter and extract a bitfield.
223 */
224 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
225 LLVMValueRef value, unsigned rshift,
226 unsigned bitwidth)
227 {
228 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
229 value = ac_to_integer(&ctx->ac, value);
230
231 if (rshift)
232 value = LLVMBuildLShr(ctx->ac.builder, value,
233 LLVMConstInt(ctx->i32, rshift, 0), "");
234
235 if (rshift + bitwidth < 32) {
236 unsigned mask = (1 << bitwidth) - 1;
237 value = LLVMBuildAnd(ctx->ac.builder, value,
238 LLVMConstInt(ctx->i32, mask, 0), "");
239 }
240
241 return value;
242 }
243
244 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
245 unsigned param, unsigned rshift,
246 unsigned bitwidth)
247 {
248 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
249
250 return unpack_llvm_param(ctx, value, rshift, bitwidth);
251 }
252
253 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
254 {
255 switch (ctx->type) {
256 case PIPE_SHADER_TESS_CTRL:
257 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
258
259 case PIPE_SHADER_TESS_EVAL:
260 return LLVMGetParam(ctx->main_fn,
261 ctx->param_tes_rel_patch_id);
262
263 default:
264 assert(0);
265 return NULL;
266 }
267 }
268
269 /* Tessellation shaders pass outputs to the next shader using LDS.
270 *
271 * LS outputs = TCS inputs
272 * TCS outputs = TES inputs
273 *
274 * The LDS layout is:
275 * - TCS inputs for patch 0
276 * - TCS inputs for patch 1
277 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
278 * - ...
279 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
280 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
281 * - TCS outputs for patch 1
282 * - Per-patch TCS outputs for patch 1
283 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
284 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
285 * - ...
286 *
287 * All three shaders VS(LS), TCS, TES share the same LDS space.
288 */
289
290 static LLVMValueRef
291 get_tcs_in_patch_stride(struct si_shader_context *ctx)
292 {
293 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
294 }
295
296 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
297 {
298 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
299
300 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
301 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
302
303 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
304 }
305
306 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
307 {
308 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
309
310 return LLVMConstInt(ctx->i32, stride, 0);
311 }
312
313 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
314 {
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
317
318 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
319 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
320 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
321 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
322 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
323 num_patch_outputs * 4;
324 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
325 }
326
327 static LLVMValueRef
328 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
329 {
330 return LLVMBuildMul(ctx->ac.builder,
331 si_unpack_param(ctx,
332 ctx->param_tcs_out_lds_offsets,
333 0, 16),
334 LLVMConstInt(ctx->i32, 4, 0), "");
335 }
336
337 static LLVMValueRef
338 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
339 {
340 return LLVMBuildMul(ctx->ac.builder,
341 si_unpack_param(ctx,
342 ctx->param_tcs_out_lds_offsets,
343 16, 16),
344 LLVMConstInt(ctx->i32, 4, 0), "");
345 }
346
347 static LLVMValueRef
348 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
349 {
350 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
351 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
352
353 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
354 }
355
356 static LLVMValueRef
357 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
358 {
359 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
360 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
361 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
362
363 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
364 }
365
366 static LLVMValueRef
367 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
368 {
369 LLVMValueRef patch0_patch_data_offset =
370 get_tcs_out_patch0_patch_data_offset(ctx);
371 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
372 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
373
374 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
375 }
376
377 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
378 {
379 unsigned tcs_out_vertices =
380 ctx->shader->selector ?
381 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
382
383 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
384 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
385 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
386
387 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
388 }
389
390 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
391 {
392 unsigned stride;
393
394 switch (ctx->type) {
395 case PIPE_SHADER_VERTEX:
396 stride = ctx->shader->selector->lshs_vertex_stride / 4;
397 return LLVMConstInt(ctx->i32, stride, 0);
398
399 case PIPE_SHADER_TESS_CTRL:
400 if (ctx->screen->info.chip_class >= GFX9 &&
401 ctx->shader->is_monolithic) {
402 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
403 return LLVMConstInt(ctx->i32, stride, 0);
404 }
405 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
406
407 default:
408 assert(0);
409 return NULL;
410 }
411 }
412
413 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
414 LLVMValueRef i32, unsigned index)
415 {
416 assert(index <= 1);
417
418 if (index == 1)
419 return LLVMBuildAShr(ctx->ac.builder, i32,
420 LLVMConstInt(ctx->i32, 16, 0), "");
421
422 return LLVMBuildSExt(ctx->ac.builder,
423 LLVMBuildTrunc(ctx->ac.builder, i32,
424 ctx->ac.i16, ""),
425 ctx->i32, "");
426 }
427
428 void si_llvm_load_input_vs(
429 struct si_shader_context *ctx,
430 unsigned input_index,
431 LLVMValueRef out[4])
432 {
433 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
434 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
435
436 if (vs_blit_property) {
437 LLVMValueRef vertex_id = ctx->abi.vertex_id;
438 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
439 LLVMIntULE, vertex_id,
440 ctx->i32_1, "");
441 /* Use LLVMIntNE, because we have 3 vertices and only
442 * the middle one should use y2.
443 */
444 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
445 LLVMIntNE, vertex_id,
446 ctx->i32_1, "");
447
448 if (input_index == 0) {
449 /* Position: */
450 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
451 ctx->param_vs_blit_inputs);
452 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
453 ctx->param_vs_blit_inputs + 1);
454
455 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
456 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
457 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
458 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
459
460 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
461 x1, x2, "");
462 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
463 y1, y2, "");
464
465 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
466 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
467 out[2] = LLVMGetParam(ctx->main_fn,
468 ctx->param_vs_blit_inputs + 2);
469 out[3] = ctx->ac.f32_1;
470 return;
471 }
472
473 /* Color or texture coordinates: */
474 assert(input_index == 1);
475
476 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
477 for (int i = 0; i < 4; i++) {
478 out[i] = LLVMGetParam(ctx->main_fn,
479 ctx->param_vs_blit_inputs + 3 + i);
480 }
481 } else {
482 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
483 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
484 ctx->param_vs_blit_inputs + 3);
485 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_blit_inputs + 4);
487 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
488 ctx->param_vs_blit_inputs + 5);
489 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs + 6);
491
492 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
493 x1, x2, "");
494 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
495 y1, y2, "");
496 out[2] = LLVMGetParam(ctx->main_fn,
497 ctx->param_vs_blit_inputs + 7);
498 out[3] = LLVMGetParam(ctx->main_fn,
499 ctx->param_vs_blit_inputs + 8);
500 }
501 return;
502 }
503
504 union si_vs_fix_fetch fix_fetch;
505 LLVMValueRef t_list_ptr;
506 LLVMValueRef t_offset;
507 LLVMValueRef t_list;
508 LLVMValueRef vertex_index;
509 LLVMValueRef tmp;
510
511 /* Load the T list */
512 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
513
514 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
515
516 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
517
518 vertex_index = LLVMGetParam(ctx->main_fn,
519 ctx->param_vertex_index0 +
520 input_index);
521
522 /* Use the open-coded implementation for all loads of doubles and
523 * of dword-sized data that needs fixups. We need to insert conversion
524 * code anyway, and the amd/common code does it for us.
525 *
526 * Note: On LLVM <= 8, we can only open-code formats with
527 * channel size >= 4 bytes.
528 */
529 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
530 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
531 if (opencode ||
532 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
533 (fix_fetch.u.log_size == 2)) {
534 tmp = ac_build_opencoded_load_format(
535 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
536 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
537 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0,
538 false, false, true);
539 for (unsigned i = 0; i < 4; ++i)
540 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
541 return;
542 }
543
544 /* Do multiple loads for special formats. */
545 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
546 LLVMValueRef fetches[4];
547 unsigned num_fetches;
548 unsigned fetch_stride;
549 unsigned channels_per_fetch;
550
551 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
552 num_fetches = MIN2(required_channels, 3);
553 fetch_stride = 1 << fix_fetch.u.log_size;
554 channels_per_fetch = 1;
555 } else {
556 num_fetches = 1;
557 fetch_stride = 0;
558 channels_per_fetch = required_channels;
559 }
560
561 for (unsigned i = 0; i < num_fetches; ++i) {
562 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
563 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
564 channels_per_fetch, false, true);
565 }
566
567 if (num_fetches == 1 && channels_per_fetch > 1) {
568 LLVMValueRef fetch = fetches[0];
569 for (unsigned i = 0; i < channels_per_fetch; ++i) {
570 tmp = LLVMConstInt(ctx->i32, i, false);
571 fetches[i] = LLVMBuildExtractElement(
572 ctx->ac.builder, fetch, tmp, "");
573 }
574 num_fetches = channels_per_fetch;
575 channels_per_fetch = 1;
576 }
577
578 for (unsigned i = num_fetches; i < 4; ++i)
579 fetches[i] = LLVMGetUndef(ctx->f32);
580
581 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
582 required_channels == 4) {
583 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
584 fetches[3] = ctx->ac.i32_1;
585 else
586 fetches[3] = ctx->ac.f32_1;
587 } else if (fix_fetch.u.log_size == 3 &&
588 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
589 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
590 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
591 required_channels == 4) {
592 /* For 2_10_10_10, the hardware returns an unsigned value;
593 * convert it to a signed one.
594 */
595 LLVMValueRef tmp = fetches[3];
596 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
597
598 /* First, recover the sign-extended signed integer value. */
599 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
600 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
601 else
602 tmp = ac_to_integer(&ctx->ac, tmp);
603
604 /* For the integer-like cases, do a natural sign extension.
605 *
606 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
607 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
608 * exponent.
609 */
610 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
611 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
612 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
613 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
614
615 /* Convert back to the right type. */
616 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
617 LLVMValueRef clamp;
618 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
619 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
620 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
621 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
622 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
623 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
624 }
625
626 fetches[3] = tmp;
627 }
628
629 for (unsigned i = 0; i < 4; ++i)
630 out[i] = ac_to_float(&ctx->ac, fetches[i]);
631 }
632
633 static void declare_input_vs(
634 struct si_shader_context *ctx,
635 unsigned input_index,
636 const struct tgsi_full_declaration *decl,
637 LLVMValueRef out[4])
638 {
639 si_llvm_load_input_vs(ctx, input_index, out);
640 }
641
642 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
643 unsigned swizzle)
644 {
645 if (swizzle > 0)
646 return ctx->i32_0;
647
648 switch (ctx->type) {
649 case PIPE_SHADER_VERTEX:
650 return LLVMGetParam(ctx->main_fn,
651 ctx->param_vs_prim_id);
652 case PIPE_SHADER_TESS_CTRL:
653 return ctx->abi.tcs_patch_id;
654 case PIPE_SHADER_TESS_EVAL:
655 return ctx->abi.tes_patch_id;
656 case PIPE_SHADER_GEOMETRY:
657 return ctx->abi.gs_prim_id;
658 default:
659 assert(0);
660 return ctx->i32_0;
661 }
662 }
663
664 /**
665 * Return the value of tgsi_ind_register for indexing.
666 * This is the indirect index with the constant offset added to it.
667 */
668 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
669 const struct tgsi_ind_register *ind,
670 unsigned addr_mul,
671 int rel_index)
672 {
673 LLVMValueRef result;
674
675 if (ind->File == TGSI_FILE_ADDRESS) {
676 result = ctx->addrs[ind->Index][ind->Swizzle];
677 result = LLVMBuildLoad(ctx->ac.builder, result, "");
678 } else {
679 struct tgsi_full_src_register src = {};
680
681 src.Register.File = ind->File;
682 src.Register.Index = ind->Index;
683
684 /* Set the second index to 0 for constants. */
685 if (ind->File == TGSI_FILE_CONSTANT)
686 src.Register.Dimension = 1;
687
688 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
689 TGSI_TYPE_SIGNED,
690 ind->Swizzle);
691 result = ac_to_integer(&ctx->ac, result);
692 }
693
694 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
695 LLVMConstInt(ctx->i32, rel_index, 0));
696 }
697
698 /**
699 * Like si_get_indirect_index, but restricts the return value to a (possibly
700 * undefined) value inside [0..num).
701 */
702 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
703 const struct tgsi_ind_register *ind,
704 int rel_index, unsigned num)
705 {
706 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
707
708 return si_llvm_bound_index(ctx, result, num);
709 }
710
711 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
712 LLVMValueRef vertex_dw_stride,
713 LLVMValueRef base_addr,
714 LLVMValueRef vertex_index,
715 LLVMValueRef param_index,
716 unsigned input_index,
717 ubyte *name,
718 ubyte *index,
719 bool is_patch)
720 {
721 if (vertex_dw_stride) {
722 base_addr = ac_build_imad(&ctx->ac, vertex_index,
723 vertex_dw_stride, base_addr);
724 }
725
726 if (param_index) {
727 base_addr = ac_build_imad(&ctx->ac, param_index,
728 LLVMConstInt(ctx->i32, 4, 0), base_addr);
729 }
730
731 int param = is_patch ?
732 si_shader_io_get_unique_index_patch(name[input_index],
733 index[input_index]) :
734 si_shader_io_get_unique_index(name[input_index],
735 index[input_index], false);
736
737 /* Add the base address of the element. */
738 return LLVMBuildAdd(ctx->ac.builder, base_addr,
739 LLVMConstInt(ctx->i32, param * 4, 0), "");
740 }
741
742 /**
743 * Calculate a dword address given an input or output register and a stride.
744 */
745 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
746 const struct tgsi_full_dst_register *dst,
747 const struct tgsi_full_src_register *src,
748 LLVMValueRef vertex_dw_stride,
749 LLVMValueRef base_addr)
750 {
751 struct tgsi_shader_info *info = &ctx->shader->selector->info;
752 ubyte *name, *index, *array_first;
753 int input_index;
754 struct tgsi_full_dst_register reg;
755 LLVMValueRef vertex_index = NULL;
756 LLVMValueRef ind_index = NULL;
757
758 /* Set the register description. The address computation is the same
759 * for sources and destinations. */
760 if (src) {
761 reg.Register.File = src->Register.File;
762 reg.Register.Index = src->Register.Index;
763 reg.Register.Indirect = src->Register.Indirect;
764 reg.Register.Dimension = src->Register.Dimension;
765 reg.Indirect = src->Indirect;
766 reg.Dimension = src->Dimension;
767 reg.DimIndirect = src->DimIndirect;
768 } else
769 reg = *dst;
770
771 /* If the register is 2-dimensional (e.g. an array of vertices
772 * in a primitive), calculate the base address of the vertex. */
773 if (reg.Register.Dimension) {
774 if (reg.Dimension.Indirect)
775 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
776 1, reg.Dimension.Index);
777 else
778 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
779 }
780
781 /* Get information about the register. */
782 if (reg.Register.File == TGSI_FILE_INPUT) {
783 name = info->input_semantic_name;
784 index = info->input_semantic_index;
785 array_first = info->input_array_first;
786 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
787 name = info->output_semantic_name;
788 index = info->output_semantic_index;
789 array_first = info->output_array_first;
790 } else {
791 assert(0);
792 return NULL;
793 }
794
795 if (reg.Register.Indirect) {
796 /* Add the relative address of the element. */
797 if (reg.Indirect.ArrayID)
798 input_index = array_first[reg.Indirect.ArrayID];
799 else
800 input_index = reg.Register.Index;
801
802 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
803 1, reg.Register.Index - input_index);
804 } else {
805 input_index = reg.Register.Index;
806 }
807
808 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
809 base_addr, vertex_index,
810 ind_index, input_index,
811 name, index,
812 !reg.Register.Dimension);
813 }
814
815 /* The offchip buffer layout for TCS->TES is
816 *
817 * - attribute 0 of patch 0 vertex 0
818 * - attribute 0 of patch 0 vertex 1
819 * - attribute 0 of patch 0 vertex 2
820 * ...
821 * - attribute 0 of patch 1 vertex 0
822 * - attribute 0 of patch 1 vertex 1
823 * ...
824 * - attribute 1 of patch 0 vertex 0
825 * - attribute 1 of patch 0 vertex 1
826 * ...
827 * - per patch attribute 0 of patch 0
828 * - per patch attribute 0 of patch 1
829 * ...
830 *
831 * Note that every attribute has 4 components.
832 */
833 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
834 LLVMValueRef rel_patch_id,
835 LLVMValueRef vertex_index,
836 LLVMValueRef param_index)
837 {
838 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
839 LLVMValueRef param_stride, constant16;
840
841 vertices_per_patch = get_num_tcs_out_vertices(ctx);
842 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
843 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
844 num_patches, "");
845
846 constant16 = LLVMConstInt(ctx->i32, 16, 0);
847 if (vertex_index) {
848 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
849 vertices_per_patch, vertex_index);
850 param_stride = total_vertices;
851 } else {
852 base_addr = rel_patch_id;
853 param_stride = num_patches;
854 }
855
856 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
857 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
858
859 if (!vertex_index) {
860 LLVMValueRef patch_data_offset =
861 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
862
863 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
864 patch_data_offset, "");
865 }
866 return base_addr;
867 }
868
869 /* This is a generic helper that can be shared by the NIR and TGSI backends */
870 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
871 struct si_shader_context *ctx,
872 LLVMValueRef vertex_index,
873 LLVMValueRef param_index,
874 unsigned param_base,
875 ubyte *name,
876 ubyte *index,
877 bool is_patch)
878 {
879 unsigned param_index_base;
880
881 param_index_base = is_patch ?
882 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
883 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
884
885 if (param_index) {
886 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
887 LLVMConstInt(ctx->i32, param_index_base, 0),
888 "");
889 } else {
890 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
891 }
892
893 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
894 vertex_index, param_index);
895 }
896
897 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
898 struct si_shader_context *ctx,
899 const struct tgsi_full_dst_register *dst,
900 const struct tgsi_full_src_register *src)
901 {
902 struct tgsi_shader_info *info = &ctx->shader->selector->info;
903 ubyte *name, *index, *array_first;
904 struct tgsi_full_src_register reg;
905 LLVMValueRef vertex_index = NULL;
906 LLVMValueRef param_index = NULL;
907 unsigned param_base;
908
909 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
910
911 if (reg.Register.Dimension) {
912
913 if (reg.Dimension.Indirect)
914 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
915 1, reg.Dimension.Index);
916 else
917 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
918 }
919
920 /* Get information about the register. */
921 if (reg.Register.File == TGSI_FILE_INPUT) {
922 name = info->input_semantic_name;
923 index = info->input_semantic_index;
924 array_first = info->input_array_first;
925 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
926 name = info->output_semantic_name;
927 index = info->output_semantic_index;
928 array_first = info->output_array_first;
929 } else {
930 assert(0);
931 return NULL;
932 }
933
934 if (reg.Register.Indirect) {
935 if (reg.Indirect.ArrayID)
936 param_base = array_first[reg.Indirect.ArrayID];
937 else
938 param_base = reg.Register.Index;
939
940 param_index = si_get_indirect_index(ctx, &reg.Indirect,
941 1, reg.Register.Index - param_base);
942
943 } else {
944 param_base = reg.Register.Index;
945 }
946
947 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
948 param_index, param_base,
949 name, index, !reg.Register.Dimension);
950 }
951
952 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
953 LLVMTypeRef type, unsigned swizzle,
954 LLVMValueRef buffer, LLVMValueRef offset,
955 LLVMValueRef base, bool can_speculate)
956 {
957 struct si_shader_context *ctx = si_shader_context(bld_base);
958 LLVMValueRef value, value2;
959 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
960
961 if (swizzle == ~0) {
962 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
963 0, 1, 0, can_speculate, false);
964
965 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
966 }
967
968 if (!llvm_type_is_64bit(ctx, type)) {
969 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
970 0, 1, 0, can_speculate, false);
971
972 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
973 return LLVMBuildExtractElement(ctx->ac.builder, value,
974 LLVMConstInt(ctx->i32, swizzle, 0), "");
975 }
976
977 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
978 swizzle * 4, 1, 0, can_speculate, false);
979
980 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
981 swizzle * 4 + 4, 1, 0, can_speculate, false);
982
983 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
984 }
985
986 /**
987 * Load from LSHS LDS storage.
988 *
989 * \param type output value type
990 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
991 * \param dw_addr address in dwords
992 */
993 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
994 LLVMTypeRef type, unsigned swizzle,
995 LLVMValueRef dw_addr)
996 {
997 struct si_shader_context *ctx = si_shader_context(bld_base);
998 LLVMValueRef value;
999
1000 if (swizzle == ~0) {
1001 LLVMValueRef values[TGSI_NUM_CHANNELS];
1002
1003 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1004 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1005
1006 return ac_build_gather_values(&ctx->ac, values,
1007 TGSI_NUM_CHANNELS);
1008 }
1009
1010 /* Split 64-bit loads. */
1011 if (llvm_type_is_64bit(ctx, type)) {
1012 LLVMValueRef lo, hi;
1013
1014 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1015 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1016 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1017 }
1018
1019 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1020 LLVMConstInt(ctx->i32, swizzle, 0), "");
1021
1022 value = ac_lds_load(&ctx->ac, dw_addr);
1023
1024 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1025 }
1026
1027 /**
1028 * Store to LSHS LDS storage.
1029 *
1030 * \param swizzle offset (typically 0..3)
1031 * \param dw_addr address in dwords
1032 * \param value value to store
1033 */
1034 static void lshs_lds_store(struct si_shader_context *ctx,
1035 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1036 LLVMValueRef value)
1037 {
1038 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1039 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1040
1041 ac_lds_store(&ctx->ac, dw_addr, value);
1042 }
1043
1044 enum si_tess_ring {
1045 TCS_FACTOR_RING,
1046 TESS_OFFCHIP_RING_TCS,
1047 TESS_OFFCHIP_RING_TES,
1048 };
1049
1050 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1051 enum si_tess_ring ring)
1052 {
1053 LLVMBuilderRef builder = ctx->ac.builder;
1054 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1055 ctx->param_tcs_out_lds_layout;
1056 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1057
1058 /* TCS only receives high 13 bits of the address. */
1059 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1060 addr = LLVMBuildAnd(builder, addr,
1061 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1062 }
1063
1064 if (ring == TCS_FACTOR_RING) {
1065 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1066 addr = LLVMBuildAdd(builder, addr,
1067 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1068 }
1069
1070 LLVMValueRef desc[4];
1071 desc[0] = addr;
1072 desc[1] = LLVMConstInt(ctx->i32,
1073 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1074 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1075 desc[3] = LLVMConstInt(ctx->i32,
1076 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1077 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1078 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1079 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1080 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1081 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1082
1083 return ac_build_gather_values(&ctx->ac, desc, 4);
1084 }
1085
1086 static LLVMValueRef fetch_input_tcs(
1087 struct lp_build_tgsi_context *bld_base,
1088 const struct tgsi_full_src_register *reg,
1089 enum tgsi_opcode_type type, unsigned swizzle_in)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef dw_addr, stride;
1093 unsigned swizzle = swizzle_in & 0xffff;
1094 stride = get_tcs_in_vertex_dw_stride(ctx);
1095 dw_addr = get_tcs_in_current_patch_offset(ctx);
1096 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1097
1098 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1099 }
1100
1101 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1102 LLVMTypeRef type,
1103 LLVMValueRef vertex_index,
1104 LLVMValueRef param_index,
1105 unsigned const_index,
1106 unsigned location,
1107 unsigned driver_location,
1108 unsigned component,
1109 unsigned num_components,
1110 bool is_patch,
1111 bool is_compact,
1112 bool load_input)
1113 {
1114 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1115 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1116 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1117 LLVMValueRef dw_addr, stride;
1118
1119 driver_location = driver_location / 4;
1120
1121 if (load_input) {
1122 stride = get_tcs_in_vertex_dw_stride(ctx);
1123 dw_addr = get_tcs_in_current_patch_offset(ctx);
1124 } else {
1125 if (is_patch) {
1126 stride = NULL;
1127 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1128 } else {
1129 stride = get_tcs_out_vertex_dw_stride(ctx);
1130 dw_addr = get_tcs_out_current_patch_offset(ctx);
1131 }
1132 }
1133
1134 if (param_index) {
1135 /* Add the constant index to the indirect index */
1136 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1137 LLVMConstInt(ctx->i32, const_index, 0), "");
1138 } else {
1139 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1140 }
1141
1142 ubyte *names;
1143 ubyte *indices;
1144 if (load_input) {
1145 names = info->input_semantic_name;
1146 indices = info->input_semantic_index;
1147 } else {
1148 names = info->output_semantic_name;
1149 indices = info->output_semantic_index;
1150 }
1151
1152 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1153 vertex_index, param_index,
1154 driver_location,
1155 names, indices,
1156 is_patch);
1157
1158 LLVMValueRef value[4];
1159 for (unsigned i = 0; i < num_components; i++) {
1160 unsigned offset = i;
1161 if (llvm_type_is_64bit(ctx, type))
1162 offset *= 2;
1163
1164 offset += component;
1165 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1166 }
1167
1168 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1169 }
1170
1171 static LLVMValueRef fetch_output_tcs(
1172 struct lp_build_tgsi_context *bld_base,
1173 const struct tgsi_full_src_register *reg,
1174 enum tgsi_opcode_type type, unsigned swizzle_in)
1175 {
1176 struct si_shader_context *ctx = si_shader_context(bld_base);
1177 LLVMValueRef dw_addr, stride;
1178 unsigned swizzle = (swizzle_in & 0xffff);
1179
1180 if (reg->Register.Dimension) {
1181 stride = get_tcs_out_vertex_dw_stride(ctx);
1182 dw_addr = get_tcs_out_current_patch_offset(ctx);
1183 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1184 } else {
1185 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1186 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1187 }
1188
1189 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1190 }
1191
1192 static LLVMValueRef fetch_input_tes(
1193 struct lp_build_tgsi_context *bld_base,
1194 const struct tgsi_full_src_register *reg,
1195 enum tgsi_opcode_type type, unsigned swizzle_in)
1196 {
1197 struct si_shader_context *ctx = si_shader_context(bld_base);
1198 LLVMValueRef base, addr;
1199 unsigned swizzle = (swizzle_in & 0xffff);
1200
1201 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1202 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1203
1204 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1205 ctx->tess_offchip_ring, base, addr, true);
1206 }
1207
1208 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1209 LLVMTypeRef type,
1210 LLVMValueRef vertex_index,
1211 LLVMValueRef param_index,
1212 unsigned const_index,
1213 unsigned location,
1214 unsigned driver_location,
1215 unsigned component,
1216 unsigned num_components,
1217 bool is_patch,
1218 bool is_compact,
1219 bool load_input)
1220 {
1221 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1222 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1223 LLVMValueRef base, addr;
1224
1225 driver_location = driver_location / 4;
1226
1227 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1228
1229 if (param_index) {
1230 /* Add the constant index to the indirect index */
1231 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1232 LLVMConstInt(ctx->i32, const_index, 0), "");
1233 } else {
1234 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1235 }
1236
1237 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1238 param_index, driver_location,
1239 info->input_semantic_name,
1240 info->input_semantic_index,
1241 is_patch);
1242
1243 /* TODO: This will generate rather ordinary llvm code, although it
1244 * should be easy for the optimiser to fix up. In future we might want
1245 * to refactor buffer_load(), but for now this maximises code sharing
1246 * between the NIR and TGSI backends.
1247 */
1248 LLVMValueRef value[4];
1249 for (unsigned i = 0; i < num_components; i++) {
1250 unsigned offset = i;
1251 if (llvm_type_is_64bit(ctx, type)) {
1252 offset *= 2;
1253 if (offset == 4) {
1254 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1255 vertex_index,
1256 param_index,
1257 driver_location + 1,
1258 info->input_semantic_name,
1259 info->input_semantic_index,
1260 is_patch);
1261 }
1262
1263 offset = offset % 4;
1264 }
1265
1266 offset += component;
1267 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1268 ctx->tess_offchip_ring, base, addr, true);
1269 }
1270
1271 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1272 }
1273
1274 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1275 const struct tgsi_full_instruction *inst,
1276 const struct tgsi_opcode_info *info,
1277 unsigned index,
1278 LLVMValueRef dst[4])
1279 {
1280 struct si_shader_context *ctx = si_shader_context(bld_base);
1281 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1282 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1283 unsigned chan_index;
1284 LLVMValueRef dw_addr, stride;
1285 LLVMValueRef buffer, base, buf_addr;
1286 LLVMValueRef values[4];
1287 bool skip_lds_store;
1288 bool is_tess_factor = false, is_tess_inner = false;
1289
1290 /* Only handle per-patch and per-vertex outputs here.
1291 * Vectors will be lowered to scalars and this function will be called again.
1292 */
1293 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1294 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1295 si_llvm_emit_store(bld_base, inst, info, index, dst);
1296 return;
1297 }
1298
1299 if (reg->Register.Dimension) {
1300 stride = get_tcs_out_vertex_dw_stride(ctx);
1301 dw_addr = get_tcs_out_current_patch_offset(ctx);
1302 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1303 skip_lds_store = !sh_info->reads_pervertex_outputs;
1304 } else {
1305 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1306 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1307 skip_lds_store = !sh_info->reads_perpatch_outputs;
1308
1309 if (!reg->Register.Indirect) {
1310 int name = sh_info->output_semantic_name[reg->Register.Index];
1311
1312 /* Always write tess factors into LDS for the TCS epilog. */
1313 if (name == TGSI_SEMANTIC_TESSINNER ||
1314 name == TGSI_SEMANTIC_TESSOUTER) {
1315 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1316 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1317 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1318 is_tess_factor = true;
1319 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1320 }
1321 }
1322 }
1323
1324 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1325
1326 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1327 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1328
1329 uint32_t writemask = reg->Register.WriteMask;
1330 while (writemask) {
1331 chan_index = u_bit_scan(&writemask);
1332 LLVMValueRef value = dst[chan_index];
1333
1334 if (inst->Instruction.Saturate)
1335 value = ac_build_clamp(&ctx->ac, value);
1336
1337 /* Skip LDS stores if there is no LDS read of this output. */
1338 if (!skip_lds_store)
1339 lshs_lds_store(ctx, chan_index, dw_addr, value);
1340
1341 value = ac_to_integer(&ctx->ac, value);
1342 values[chan_index] = value;
1343
1344 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1345 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1346 buf_addr, base,
1347 4 * chan_index, 1, 0, false);
1348 }
1349
1350 /* Write tess factors into VGPRs for the epilog. */
1351 if (is_tess_factor &&
1352 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1353 if (!is_tess_inner) {
1354 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1355 ctx->invoc0_tess_factors[chan_index]);
1356 } else if (chan_index < 2) {
1357 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1358 ctx->invoc0_tess_factors[4 + chan_index]);
1359 }
1360 }
1361 }
1362
1363 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1364 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1365 values, 4);
1366 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1367 base, 0, 1, 0, false);
1368 }
1369 }
1370
1371 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1372 const struct nir_variable *var,
1373 LLVMValueRef vertex_index,
1374 LLVMValueRef param_index,
1375 unsigned const_index,
1376 LLVMValueRef src,
1377 unsigned writemask)
1378 {
1379 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1380 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1381 const unsigned component = var->data.location_frac;
1382 const bool is_patch = var->data.patch;
1383 unsigned driver_location = var->data.driver_location;
1384 LLVMValueRef dw_addr, stride;
1385 LLVMValueRef buffer, base, addr;
1386 LLVMValueRef values[8];
1387 bool skip_lds_store;
1388 bool is_tess_factor = false, is_tess_inner = false;
1389
1390 driver_location = driver_location / 4;
1391
1392 if (param_index) {
1393 /* Add the constant index to the indirect index */
1394 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1395 LLVMConstInt(ctx->i32, const_index, 0), "");
1396 } else {
1397 if (const_index != 0)
1398 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1399 }
1400
1401 if (!is_patch) {
1402 stride = get_tcs_out_vertex_dw_stride(ctx);
1403 dw_addr = get_tcs_out_current_patch_offset(ctx);
1404 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1405 vertex_index, param_index,
1406 driver_location,
1407 info->output_semantic_name,
1408 info->output_semantic_index,
1409 is_patch);
1410
1411 skip_lds_store = !info->reads_pervertex_outputs;
1412 } else {
1413 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1414 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1415 vertex_index, param_index,
1416 driver_location,
1417 info->output_semantic_name,
1418 info->output_semantic_index,
1419 is_patch);
1420
1421 skip_lds_store = !info->reads_perpatch_outputs;
1422
1423 if (!param_index) {
1424 int name = info->output_semantic_name[driver_location];
1425
1426 /* Always write tess factors into LDS for the TCS epilog. */
1427 if (name == TGSI_SEMANTIC_TESSINNER ||
1428 name == TGSI_SEMANTIC_TESSOUTER) {
1429 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1430 skip_lds_store = !info->reads_tessfactor_outputs &&
1431 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1432 is_tess_factor = true;
1433 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1434 }
1435 }
1436 }
1437
1438 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1439
1440 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1441
1442 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1443 param_index, driver_location,
1444 info->output_semantic_name,
1445 info->output_semantic_index,
1446 is_patch);
1447
1448 for (unsigned chan = 0; chan < 8; chan++) {
1449 if (!(writemask & (1 << chan)))
1450 continue;
1451 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1452
1453 unsigned buffer_store_offset = chan % 4;
1454 if (chan == 4) {
1455 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1456 vertex_index,
1457 param_index,
1458 driver_location + 1,
1459 info->output_semantic_name,
1460 info->output_semantic_index,
1461 is_patch);
1462 }
1463
1464 /* Skip LDS stores if there is no LDS read of this output. */
1465 if (!skip_lds_store)
1466 lshs_lds_store(ctx, chan, dw_addr, value);
1467
1468 value = ac_to_integer(&ctx->ac, value);
1469 values[chan] = value;
1470
1471 if (writemask != 0xF && !is_tess_factor) {
1472 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1473 addr, base,
1474 4 * buffer_store_offset,
1475 1, 0, false);
1476 }
1477
1478 /* Write tess factors into VGPRs for the epilog. */
1479 if (is_tess_factor &&
1480 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1481 if (!is_tess_inner) {
1482 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1483 ctx->invoc0_tess_factors[chan]);
1484 } else if (chan < 2) {
1485 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1486 ctx->invoc0_tess_factors[4 + chan]);
1487 }
1488 }
1489 }
1490
1491 if (writemask == 0xF && !is_tess_factor) {
1492 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1493 values, 4);
1494 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1495 base, 0, 1, 0, false);
1496 }
1497 }
1498
1499 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1500 unsigned input_index,
1501 unsigned vtx_offset_param,
1502 LLVMTypeRef type,
1503 unsigned swizzle)
1504 {
1505 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1506 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1507 struct si_shader *shader = ctx->shader;
1508 LLVMValueRef vtx_offset, soffset;
1509 struct tgsi_shader_info *info = &shader->selector->info;
1510 unsigned semantic_name = info->input_semantic_name[input_index];
1511 unsigned semantic_index = info->input_semantic_index[input_index];
1512 unsigned param;
1513 LLVMValueRef value;
1514
1515 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1516
1517 /* GFX9 has the ESGS ring in LDS. */
1518 if (ctx->screen->info.chip_class >= GFX9) {
1519 unsigned index = vtx_offset_param;
1520
1521 switch (index / 2) {
1522 case 0:
1523 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1524 index % 2 ? 16 : 0, 16);
1525 break;
1526 case 1:
1527 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1528 index % 2 ? 16 : 0, 16);
1529 break;
1530 case 2:
1531 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1532 index % 2 ? 16 : 0, 16);
1533 break;
1534 default:
1535 assert(0);
1536 return NULL;
1537 }
1538
1539 unsigned offset = param * 4 + swizzle;
1540 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1541 LLVMConstInt(ctx->i32, offset, false), "");
1542
1543 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1544 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1545 if (llvm_type_is_64bit(ctx, type)) {
1546 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1547 &ctx->ac.i32_1, 1, "");
1548 LLVMValueRef values[2] = {
1549 value,
1550 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1551 };
1552 value = ac_build_gather_values(&ctx->ac, values, 2);
1553 }
1554 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1555 }
1556
1557 /* GFX6: input load from the ESGS ring in memory. */
1558 if (swizzle == ~0) {
1559 LLVMValueRef values[TGSI_NUM_CHANNELS];
1560 unsigned chan;
1561 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1562 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1563 type, chan);
1564 }
1565 return ac_build_gather_values(&ctx->ac, values,
1566 TGSI_NUM_CHANNELS);
1567 }
1568
1569 /* Get the vertex offset parameter on GFX6. */
1570 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1571
1572 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1573 LLVMConstInt(ctx->i32, 4, 0), "");
1574
1575 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1576
1577 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1578 vtx_offset, soffset, 0, 1, 0, true, false);
1579 if (llvm_type_is_64bit(ctx, type)) {
1580 LLVMValueRef value2;
1581 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1582
1583 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1584 ctx->i32_0, vtx_offset, soffset,
1585 0, 1, 0, true, false);
1586 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1587 }
1588 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1589 }
1590
1591 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1592 unsigned location,
1593 unsigned driver_location,
1594 unsigned component,
1595 unsigned num_components,
1596 unsigned vertex_index,
1597 unsigned const_index,
1598 LLVMTypeRef type)
1599 {
1600 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1601
1602 LLVMValueRef value[4];
1603 for (unsigned i = 0; i < num_components; i++) {
1604 unsigned offset = i;
1605 if (llvm_type_is_64bit(ctx, type))
1606 offset *= 2;
1607
1608 offset += component;
1609 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1610 vertex_index, type, offset);
1611 }
1612
1613 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1614 }
1615
1616 static LLVMValueRef fetch_input_gs(
1617 struct lp_build_tgsi_context *bld_base,
1618 const struct tgsi_full_src_register *reg,
1619 enum tgsi_opcode_type type,
1620 unsigned swizzle_in)
1621 {
1622 struct si_shader_context *ctx = si_shader_context(bld_base);
1623 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1624 unsigned swizzle = swizzle_in & 0xffff;
1625
1626 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1627 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1628 return si_get_primitive_id(ctx, swizzle);
1629
1630 if (!reg->Register.Dimension)
1631 return NULL;
1632
1633 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1634 reg->Dimension.Index,
1635 tgsi2llvmtype(bld_base, type),
1636 swizzle);
1637 }
1638
1639 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1640 {
1641 switch (interpolate) {
1642 case TGSI_INTERPOLATE_CONSTANT:
1643 return 0;
1644
1645 case TGSI_INTERPOLATE_LINEAR:
1646 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1647 return SI_PARAM_LINEAR_SAMPLE;
1648 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1649 return SI_PARAM_LINEAR_CENTROID;
1650 else
1651 return SI_PARAM_LINEAR_CENTER;
1652 break;
1653 case TGSI_INTERPOLATE_COLOR:
1654 case TGSI_INTERPOLATE_PERSPECTIVE:
1655 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1656 return SI_PARAM_PERSP_SAMPLE;
1657 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1658 return SI_PARAM_PERSP_CENTROID;
1659 else
1660 return SI_PARAM_PERSP_CENTER;
1661 break;
1662 default:
1663 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1664 return -1;
1665 }
1666 }
1667
1668 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1669 unsigned attr_index, unsigned chan,
1670 LLVMValueRef prim_mask,
1671 LLVMValueRef i, LLVMValueRef j)
1672 {
1673 if (i || j) {
1674 return ac_build_fs_interp(&ctx->ac,
1675 LLVMConstInt(ctx->i32, chan, 0),
1676 LLVMConstInt(ctx->i32, attr_index, 0),
1677 prim_mask, i, j);
1678 }
1679 return ac_build_fs_interp_mov(&ctx->ac,
1680 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1681 LLVMConstInt(ctx->i32, chan, 0),
1682 LLVMConstInt(ctx->i32, attr_index, 0),
1683 prim_mask);
1684 }
1685
1686 /**
1687 * Interpolate a fragment shader input.
1688 *
1689 * @param ctx context
1690 * @param input_index index of the input in hardware
1691 * @param semantic_name TGSI_SEMANTIC_*
1692 * @param semantic_index semantic index
1693 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1694 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1695 * @param interp_param interpolation weights (i,j)
1696 * @param prim_mask SI_PARAM_PRIM_MASK
1697 * @param face SI_PARAM_FRONT_FACE
1698 * @param result the return value (4 components)
1699 */
1700 static void interp_fs_input(struct si_shader_context *ctx,
1701 unsigned input_index,
1702 unsigned semantic_name,
1703 unsigned semantic_index,
1704 unsigned num_interp_inputs,
1705 unsigned colors_read_mask,
1706 LLVMValueRef interp_param,
1707 LLVMValueRef prim_mask,
1708 LLVMValueRef face,
1709 LLVMValueRef result[4])
1710 {
1711 LLVMValueRef i = NULL, j = NULL;
1712 unsigned chan;
1713
1714 /* fs.constant returns the param from the middle vertex, so it's not
1715 * really useful for flat shading. It's meant to be used for custom
1716 * interpolation (but the intrinsic can't fetch from the other two
1717 * vertices).
1718 *
1719 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1720 * to do the right thing. The only reason we use fs.constant is that
1721 * fs.interp cannot be used on integers, because they can be equal
1722 * to NaN.
1723 *
1724 * When interp is false we will use fs.constant or for newer llvm,
1725 * amdgcn.interp.mov.
1726 */
1727 bool interp = interp_param != NULL;
1728
1729 if (interp) {
1730 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1731 LLVMVectorType(ctx->f32, 2), "");
1732
1733 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1734 ctx->i32_0, "");
1735 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1736 ctx->i32_1, "");
1737 }
1738
1739 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1740 ctx->shader->key.part.ps.prolog.color_two_side) {
1741 LLVMValueRef is_face_positive;
1742
1743 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1744 * otherwise it's at offset "num_inputs".
1745 */
1746 unsigned back_attr_offset = num_interp_inputs;
1747 if (semantic_index == 1 && colors_read_mask & 0xf)
1748 back_attr_offset += 1;
1749
1750 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1751 face, ctx->i32_0, "");
1752
1753 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1754 LLVMValueRef front, back;
1755
1756 front = si_build_fs_interp(ctx,
1757 input_index, chan,
1758 prim_mask, i, j);
1759 back = si_build_fs_interp(ctx,
1760 back_attr_offset, chan,
1761 prim_mask, i, j);
1762
1763 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1764 is_face_positive,
1765 front,
1766 back,
1767 "");
1768 }
1769 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1770 result[0] = si_build_fs_interp(ctx, input_index,
1771 0, prim_mask, i, j);
1772 result[1] =
1773 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1774 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1775 } else {
1776 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1777 result[chan] = si_build_fs_interp(ctx,
1778 input_index, chan,
1779 prim_mask, i, j);
1780 }
1781 }
1782 }
1783
1784 void si_llvm_load_input_fs(
1785 struct si_shader_context *ctx,
1786 unsigned input_index,
1787 LLVMValueRef out[4])
1788 {
1789 struct si_shader *shader = ctx->shader;
1790 struct tgsi_shader_info *info = &shader->selector->info;
1791 LLVMValueRef main_fn = ctx->main_fn;
1792 LLVMValueRef interp_param = NULL;
1793 int interp_param_idx;
1794 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1795 unsigned semantic_index = info->input_semantic_index[input_index];
1796 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1797 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1798
1799 /* Get colors from input VGPRs (set by the prolog). */
1800 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1801 unsigned colors_read = shader->selector->info.colors_read;
1802 unsigned mask = colors_read >> (semantic_index * 4);
1803 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1804 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1805 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1806
1807 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1808 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1809 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1810 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1811 return;
1812 }
1813
1814 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1815 if (interp_param_idx == -1)
1816 return;
1817 else if (interp_param_idx) {
1818 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1819 }
1820
1821 interp_fs_input(ctx, input_index, semantic_name,
1822 semantic_index, 0, /* this param is unused */
1823 shader->selector->info.colors_read, interp_param,
1824 ctx->abi.prim_mask,
1825 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1826 &out[0]);
1827 }
1828
1829 static void declare_input_fs(
1830 struct si_shader_context *ctx,
1831 unsigned input_index,
1832 const struct tgsi_full_declaration *decl,
1833 LLVMValueRef out[4])
1834 {
1835 si_llvm_load_input_fs(ctx, input_index, out);
1836 }
1837
1838 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1839 {
1840 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1841 }
1842
1843 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1844 {
1845 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1846
1847 /* For non-indexed draws, the base vertex set by the driver
1848 * (for direct draws) or the CP (for indirect draws) is the
1849 * first vertex ID, but GLSL expects 0 to be returned.
1850 */
1851 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1852 ctx->param_vs_state_bits);
1853 LLVMValueRef indexed;
1854
1855 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1856 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1857
1858 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1859 ctx->i32_0, "");
1860 }
1861
1862 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1863 {
1864 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1865
1866 LLVMValueRef values[3];
1867 LLVMValueRef result;
1868 unsigned i;
1869 unsigned *properties = ctx->shader->selector->info.properties;
1870
1871 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1872 unsigned sizes[3] = {
1873 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1874 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1875 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1876 };
1877
1878 for (i = 0; i < 3; ++i)
1879 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1880
1881 result = ac_build_gather_values(&ctx->ac, values, 3);
1882 } else {
1883 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1884 }
1885
1886 return result;
1887 }
1888
1889 /**
1890 * Load a dword from a constant buffer.
1891 */
1892 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1893 LLVMValueRef resource,
1894 LLVMValueRef offset)
1895 {
1896 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1897 0, 0, 0, true, true);
1898 }
1899
1900 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1901 {
1902 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1903 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1904 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1905 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1906
1907 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1908 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1909 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1910
1911 LLVMValueRef pos[4] = {
1912 buffer_load_const(ctx, resource, offset0),
1913 buffer_load_const(ctx, resource, offset1),
1914 LLVMConstReal(ctx->f32, 0),
1915 LLVMConstReal(ctx->f32, 0)
1916 };
1917
1918 return ac_build_gather_values(&ctx->ac, pos, 4);
1919 }
1920
1921 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1922 {
1923 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1924 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1925 }
1926
1927 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1928 {
1929 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1930 LLVMValueRef coord[4] = {
1931 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1932 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1933 ctx->ac.f32_0,
1934 ctx->ac.f32_0
1935 };
1936
1937 /* For triangles, the vector should be (u, v, 1-u-v). */
1938 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1939 PIPE_PRIM_TRIANGLES) {
1940 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1941 LLVMBuildFAdd(ctx->ac.builder,
1942 coord[0], coord[1], ""), "");
1943 }
1944 return ac_build_gather_values(&ctx->ac, coord, 4);
1945 }
1946
1947 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1948 unsigned semantic_name)
1949 {
1950 LLVMValueRef base, addr;
1951
1952 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1953
1954 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1955 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1956 LLVMConstInt(ctx->i32, param, 0));
1957
1958 return buffer_load(&ctx->bld_base, ctx->f32,
1959 ~0, ctx->tess_offchip_ring, base, addr, true);
1960
1961 }
1962
1963 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1964 unsigned varying_id)
1965 {
1966 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1967 unsigned semantic_name;
1968
1969 switch (varying_id) {
1970 case VARYING_SLOT_TESS_LEVEL_INNER:
1971 semantic_name = TGSI_SEMANTIC_TESSINNER;
1972 break;
1973 case VARYING_SLOT_TESS_LEVEL_OUTER:
1974 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1975 break;
1976 default:
1977 unreachable("unknown tess level");
1978 }
1979
1980 return load_tess_level(ctx, semantic_name);
1981
1982 }
1983
1984 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1985 {
1986 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1987 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1988 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
1989 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1990 return get_num_tcs_out_vertices(ctx);
1991 else
1992 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1993 }
1994
1995 void si_load_system_value(struct si_shader_context *ctx,
1996 unsigned index,
1997 const struct tgsi_full_declaration *decl)
1998 {
1999 LLVMValueRef value = 0;
2000
2001 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2002
2003 switch (decl->Semantic.Name) {
2004 case TGSI_SEMANTIC_INSTANCEID:
2005 value = ctx->abi.instance_id;
2006 break;
2007
2008 case TGSI_SEMANTIC_VERTEXID:
2009 value = LLVMBuildAdd(ctx->ac.builder,
2010 ctx->abi.vertex_id,
2011 ctx->abi.base_vertex, "");
2012 break;
2013
2014 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2015 /* Unused. Clarify the meaning in indexed vs. non-indexed
2016 * draws if this is ever used again. */
2017 assert(false);
2018 break;
2019
2020 case TGSI_SEMANTIC_BASEVERTEX:
2021 value = get_base_vertex(&ctx->abi);
2022 break;
2023
2024 case TGSI_SEMANTIC_BASEINSTANCE:
2025 value = ctx->abi.start_instance;
2026 break;
2027
2028 case TGSI_SEMANTIC_DRAWID:
2029 value = ctx->abi.draw_id;
2030 break;
2031
2032 case TGSI_SEMANTIC_INVOCATIONID:
2033 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2034 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2035 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2036 value = ctx->abi.gs_invocation_id;
2037 else
2038 assert(!"INVOCATIONID not implemented");
2039 break;
2040
2041 case TGSI_SEMANTIC_POSITION:
2042 {
2043 LLVMValueRef pos[4] = {
2044 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2045 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2046 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2047 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2048 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2049 };
2050 value = ac_build_gather_values(&ctx->ac, pos, 4);
2051 break;
2052 }
2053
2054 case TGSI_SEMANTIC_FACE:
2055 value = ctx->abi.front_face;
2056 break;
2057
2058 case TGSI_SEMANTIC_SAMPLEID:
2059 value = si_get_sample_id(ctx);
2060 break;
2061
2062 case TGSI_SEMANTIC_SAMPLEPOS: {
2063 LLVMValueRef pos[4] = {
2064 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2065 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2066 LLVMConstReal(ctx->f32, 0),
2067 LLVMConstReal(ctx->f32, 0)
2068 };
2069 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2070 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2071 value = ac_build_gather_values(&ctx->ac, pos, 4);
2072 break;
2073 }
2074
2075 case TGSI_SEMANTIC_SAMPLEMASK:
2076 /* This can only occur with the OpenGL Core profile, which
2077 * doesn't support smoothing.
2078 */
2079 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2080 break;
2081
2082 case TGSI_SEMANTIC_TESSCOORD:
2083 value = si_load_tess_coord(&ctx->abi);
2084 break;
2085
2086 case TGSI_SEMANTIC_VERTICESIN:
2087 value = si_load_patch_vertices_in(&ctx->abi);
2088 break;
2089
2090 case TGSI_SEMANTIC_TESSINNER:
2091 case TGSI_SEMANTIC_TESSOUTER:
2092 value = load_tess_level(ctx, decl->Semantic.Name);
2093 break;
2094
2095 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2096 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2097 {
2098 LLVMValueRef buf, slot, val[4];
2099 int i, offset;
2100
2101 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2102 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2103 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2104 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2105
2106 for (i = 0; i < 4; i++)
2107 val[i] = buffer_load_const(ctx, buf,
2108 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2109 value = ac_build_gather_values(&ctx->ac, val, 4);
2110 break;
2111 }
2112
2113 case TGSI_SEMANTIC_PRIMID:
2114 value = si_get_primitive_id(ctx, 0);
2115 break;
2116
2117 case TGSI_SEMANTIC_GRID_SIZE:
2118 value = ctx->abi.num_work_groups;
2119 break;
2120
2121 case TGSI_SEMANTIC_BLOCK_SIZE:
2122 value = get_block_size(&ctx->abi);
2123 break;
2124
2125 case TGSI_SEMANTIC_BLOCK_ID:
2126 {
2127 LLVMValueRef values[3];
2128
2129 for (int i = 0; i < 3; i++) {
2130 values[i] = ctx->i32_0;
2131 if (ctx->abi.workgroup_ids[i]) {
2132 values[i] = ctx->abi.workgroup_ids[i];
2133 }
2134 }
2135 value = ac_build_gather_values(&ctx->ac, values, 3);
2136 break;
2137 }
2138
2139 case TGSI_SEMANTIC_THREAD_ID:
2140 value = ctx->abi.local_invocation_ids;
2141 break;
2142
2143 case TGSI_SEMANTIC_HELPER_INVOCATION:
2144 value = ac_build_load_helper_invocation(&ctx->ac);
2145 break;
2146
2147 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2148 value = LLVMConstInt(ctx->i32, 64, 0);
2149 break;
2150
2151 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2152 value = ac_get_thread_id(&ctx->ac);
2153 break;
2154
2155 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2156 {
2157 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2158 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2159 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2160 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2161 break;
2162 }
2163
2164 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2165 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2166 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2167 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2168 {
2169 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2170 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2171 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2172 /* All bits set except LSB */
2173 value = LLVMConstInt(ctx->i64, -2, 0);
2174 } else {
2175 /* All bits set */
2176 value = LLVMConstInt(ctx->i64, -1, 0);
2177 }
2178 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2179 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2180 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2181 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2182 value = LLVMBuildNot(ctx->ac.builder, value, "");
2183 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2184 break;
2185 }
2186
2187 case TGSI_SEMANTIC_CS_USER_DATA:
2188 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2189 break;
2190
2191 default:
2192 assert(!"unknown system value");
2193 return;
2194 }
2195
2196 ctx->system_values[index] = value;
2197 }
2198
2199 void si_declare_compute_memory(struct si_shader_context *ctx)
2200 {
2201 struct si_shader_selector *sel = ctx->shader->selector;
2202 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2203
2204 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2205 LLVMValueRef var;
2206
2207 assert(!ctx->ac.lds);
2208
2209 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2210 LLVMArrayType(ctx->i8, lds_size),
2211 "compute_lds",
2212 AC_ADDR_SPACE_LDS);
2213 LLVMSetAlignment(var, 64 * 1024);
2214
2215 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2216 }
2217
2218 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2219 const struct tgsi_full_declaration *decl)
2220 {
2221 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2222 assert(decl->Range.First == decl->Range.Last);
2223
2224 si_declare_compute_memory(ctx);
2225 }
2226
2227 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2228 {
2229 LLVMValueRef ptr =
2230 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2231 struct si_shader_selector *sel = ctx->shader->selector;
2232
2233 /* Do the bounds checking with a descriptor, because
2234 * doing computation and manual bounds checking of 64-bit
2235 * addresses generates horrible VALU code with very high
2236 * VGPR usage and very low SIMD occupancy.
2237 */
2238 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2239
2240 LLVMValueRef desc0, desc1;
2241 desc0 = ptr;
2242 desc1 = LLVMConstInt(ctx->i32,
2243 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2244
2245 LLVMValueRef desc_elems[] = {
2246 desc0,
2247 desc1,
2248 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2249 LLVMConstInt(ctx->i32,
2250 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2254 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2256 };
2257
2258 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2259 }
2260
2261 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2262 {
2263 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2264 ctx->param_const_and_shader_buffers);
2265
2266 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2267 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2268 }
2269
2270 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2271 {
2272 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2273 struct si_shader_selector *sel = ctx->shader->selector;
2274
2275 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2276
2277 if (sel->info.const_buffers_declared == 1 &&
2278 sel->info.shader_buffers_declared == 0) {
2279 return load_const_buffer_desc_fast_path(ctx);
2280 }
2281
2282 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2283 index = LLVMBuildAdd(ctx->ac.builder, index,
2284 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2285
2286 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2287 }
2288
2289 static LLVMValueRef
2290 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2291 {
2292 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2293 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2294 ctx->param_const_and_shader_buffers);
2295
2296 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2297 index = LLVMBuildSub(ctx->ac.builder,
2298 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2299 index, "");
2300
2301 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2302 }
2303
2304 static LLVMValueRef fetch_constant(
2305 struct lp_build_tgsi_context *bld_base,
2306 const struct tgsi_full_src_register *reg,
2307 enum tgsi_opcode_type type,
2308 unsigned swizzle_in)
2309 {
2310 struct si_shader_context *ctx = si_shader_context(bld_base);
2311 struct si_shader_selector *sel = ctx->shader->selector;
2312 const struct tgsi_ind_register *ireg = &reg->Indirect;
2313 unsigned buf, idx;
2314 unsigned swizzle = swizzle_in & 0xffff;
2315
2316 LLVMValueRef addr, bufp;
2317
2318 if (swizzle_in == LP_CHAN_ALL) {
2319 unsigned chan;
2320 LLVMValueRef values[4];
2321 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2322 values[chan] = fetch_constant(bld_base, reg, type, chan);
2323
2324 return ac_build_gather_values(&ctx->ac, values, 4);
2325 }
2326
2327 /* Split 64-bit loads. */
2328 if (tgsi_type_is_64bit(type)) {
2329 LLVMValueRef lo, hi;
2330
2331 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2332 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2333 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2334 lo, hi);
2335 }
2336
2337 idx = reg->Register.Index * 4 + swizzle;
2338 if (reg->Register.Indirect) {
2339 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2340 } else {
2341 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2342 }
2343
2344 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2345 if (sel->info.const_buffers_declared == 1 &&
2346 sel->info.shader_buffers_declared == 0) {
2347 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2348 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2349 return bitcast(bld_base, type, result);
2350 }
2351
2352 assert(reg->Register.Dimension);
2353 buf = reg->Dimension.Index;
2354
2355 if (reg->Dimension.Indirect) {
2356 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2357 LLVMValueRef index;
2358 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2359 reg->Dimension.Index,
2360 ctx->num_const_buffers);
2361 index = LLVMBuildAdd(ctx->ac.builder, index,
2362 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2363 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2364 } else
2365 bufp = load_const_buffer_desc(ctx, buf);
2366
2367 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2368 }
2369
2370 /* Initialize arguments for the shader export intrinsic */
2371 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2372 LLVMValueRef *values,
2373 unsigned target,
2374 struct ac_export_args *args)
2375 {
2376 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2377 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2378 unsigned chan;
2379 bool is_int8, is_int10;
2380
2381 /* Default is 0xf. Adjusted below depending on the format. */
2382 args->enabled_channels = 0xf; /* writemask */
2383
2384 /* Specify whether the EXEC mask represents the valid mask */
2385 args->valid_mask = 0;
2386
2387 /* Specify whether this is the last export */
2388 args->done = 0;
2389
2390 /* Specify the target we are exporting */
2391 args->target = target;
2392
2393 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2394 const struct si_shader_key *key = &ctx->shader->key;
2395 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2396 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2397
2398 assert(cbuf >= 0 && cbuf < 8);
2399 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2400 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2401 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2402 }
2403
2404 args->compr = false;
2405 args->out[0] = f32undef;
2406 args->out[1] = f32undef;
2407 args->out[2] = f32undef;
2408 args->out[3] = f32undef;
2409
2410 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2411 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2412 unsigned bits, bool hi) = NULL;
2413
2414 switch (spi_shader_col_format) {
2415 case V_028714_SPI_SHADER_ZERO:
2416 args->enabled_channels = 0; /* writemask */
2417 args->target = V_008DFC_SQ_EXP_NULL;
2418 break;
2419
2420 case V_028714_SPI_SHADER_32_R:
2421 args->enabled_channels = 1; /* writemask */
2422 args->out[0] = values[0];
2423 break;
2424
2425 case V_028714_SPI_SHADER_32_GR:
2426 args->enabled_channels = 0x3; /* writemask */
2427 args->out[0] = values[0];
2428 args->out[1] = values[1];
2429 break;
2430
2431 case V_028714_SPI_SHADER_32_AR:
2432 args->enabled_channels = 0x9; /* writemask */
2433 args->out[0] = values[0];
2434 args->out[3] = values[3];
2435 break;
2436
2437 case V_028714_SPI_SHADER_FP16_ABGR:
2438 packf = ac_build_cvt_pkrtz_f16;
2439 break;
2440
2441 case V_028714_SPI_SHADER_UNORM16_ABGR:
2442 packf = ac_build_cvt_pknorm_u16;
2443 break;
2444
2445 case V_028714_SPI_SHADER_SNORM16_ABGR:
2446 packf = ac_build_cvt_pknorm_i16;
2447 break;
2448
2449 case V_028714_SPI_SHADER_UINT16_ABGR:
2450 packi = ac_build_cvt_pk_u16;
2451 break;
2452
2453 case V_028714_SPI_SHADER_SINT16_ABGR:
2454 packi = ac_build_cvt_pk_i16;
2455 break;
2456
2457 case V_028714_SPI_SHADER_32_ABGR:
2458 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2459 break;
2460 }
2461
2462 /* Pack f16 or norm_i16/u16. */
2463 if (packf) {
2464 for (chan = 0; chan < 2; chan++) {
2465 LLVMValueRef pack_args[2] = {
2466 values[2 * chan],
2467 values[2 * chan + 1]
2468 };
2469 LLVMValueRef packed;
2470
2471 packed = packf(&ctx->ac, pack_args);
2472 args->out[chan] = ac_to_float(&ctx->ac, packed);
2473 }
2474 args->compr = 1; /* COMPR flag */
2475 }
2476 /* Pack i16/u16. */
2477 if (packi) {
2478 for (chan = 0; chan < 2; chan++) {
2479 LLVMValueRef pack_args[2] = {
2480 ac_to_integer(&ctx->ac, values[2 * chan]),
2481 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2482 };
2483 LLVMValueRef packed;
2484
2485 packed = packi(&ctx->ac, pack_args,
2486 is_int8 ? 8 : is_int10 ? 10 : 16,
2487 chan == 1);
2488 args->out[chan] = ac_to_float(&ctx->ac, packed);
2489 }
2490 args->compr = 1; /* COMPR flag */
2491 }
2492 }
2493
2494 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2495 LLVMValueRef alpha)
2496 {
2497 struct si_shader_context *ctx = si_shader_context(bld_base);
2498
2499 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2500 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2501 [PIPE_FUNC_LESS] = LLVMRealOLT,
2502 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2503 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2504 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2505 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2506 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2507 };
2508 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2509 assert(cond);
2510
2511 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2512 SI_PARAM_ALPHA_REF);
2513 LLVMValueRef alpha_pass =
2514 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2515 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2516 } else {
2517 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2518 }
2519 }
2520
2521 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2522 LLVMValueRef alpha,
2523 unsigned samplemask_param)
2524 {
2525 struct si_shader_context *ctx = si_shader_context(bld_base);
2526 LLVMValueRef coverage;
2527
2528 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2529 coverage = LLVMGetParam(ctx->main_fn,
2530 samplemask_param);
2531 coverage = ac_to_integer(&ctx->ac, coverage);
2532
2533 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2534 ctx->i32,
2535 &coverage, 1, AC_FUNC_ATTR_READNONE);
2536
2537 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2538 ctx->f32, "");
2539
2540 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2541 LLVMConstReal(ctx->f32,
2542 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2543
2544 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2545 }
2546
2547 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2548 struct ac_export_args *pos, LLVMValueRef *out_elts)
2549 {
2550 unsigned reg_index;
2551 unsigned chan;
2552 unsigned const_chan;
2553 LLVMValueRef base_elt;
2554 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2555 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2556 SI_VS_CONST_CLIP_PLANES, 0);
2557 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2558
2559 for (reg_index = 0; reg_index < 2; reg_index ++) {
2560 struct ac_export_args *args = &pos[2 + reg_index];
2561
2562 args->out[0] =
2563 args->out[1] =
2564 args->out[2] =
2565 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2566
2567 /* Compute dot products of position and user clip plane vectors */
2568 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2569 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2570 LLVMValueRef addr =
2571 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2572 const_chan) * 4, 0);
2573 base_elt = buffer_load_const(ctx, const_resource,
2574 addr);
2575 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2576 out_elts[const_chan], args->out[chan]);
2577 }
2578 }
2579
2580 args->enabled_channels = 0xf;
2581 args->valid_mask = 0;
2582 args->done = 0;
2583 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2584 args->compr = 0;
2585 }
2586 }
2587
2588 static void si_dump_streamout(struct pipe_stream_output_info *so)
2589 {
2590 unsigned i;
2591
2592 if (so->num_outputs)
2593 fprintf(stderr, "STREAMOUT\n");
2594
2595 for (i = 0; i < so->num_outputs; i++) {
2596 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2597 so->output[i].start_component;
2598 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2599 i, so->output[i].output_buffer,
2600 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2601 so->output[i].register_index,
2602 mask & 1 ? "x" : "",
2603 mask & 2 ? "y" : "",
2604 mask & 4 ? "z" : "",
2605 mask & 8 ? "w" : "");
2606 }
2607 }
2608
2609 void si_emit_streamout_output(struct si_shader_context *ctx,
2610 LLVMValueRef const *so_buffers,
2611 LLVMValueRef const *so_write_offsets,
2612 struct pipe_stream_output *stream_out,
2613 struct si_shader_output_values *shader_out)
2614 {
2615 unsigned buf_idx = stream_out->output_buffer;
2616 unsigned start = stream_out->start_component;
2617 unsigned num_comps = stream_out->num_components;
2618 LLVMValueRef out[4];
2619
2620 assert(num_comps && num_comps <= 4);
2621 if (!num_comps || num_comps > 4)
2622 return;
2623
2624 /* Load the output as int. */
2625 for (int j = 0; j < num_comps; j++) {
2626 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2627
2628 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2629 }
2630
2631 /* Pack the output. */
2632 LLVMValueRef vdata = NULL;
2633
2634 switch (num_comps) {
2635 case 1: /* as i32 */
2636 vdata = out[0];
2637 break;
2638 case 2: /* as v2i32 */
2639 case 3: /* as v3i32 */
2640 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2641 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2642 break;
2643 }
2644 /* as v4i32 (aligned to 4) */
2645 out[3] = LLVMGetUndef(ctx->i32);
2646 /* fall through */
2647 case 4: /* as v4i32 */
2648 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2649 break;
2650 }
2651
2652 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2653 vdata, num_comps,
2654 so_write_offsets[buf_idx],
2655 ctx->i32_0,
2656 stream_out->dst_offset * 4, 1, 1, false);
2657 }
2658
2659 /**
2660 * Write streamout data to buffers for vertex stream @p stream (different
2661 * vertex streams can occur for GS copy shaders).
2662 */
2663 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2664 struct si_shader_output_values *outputs,
2665 unsigned noutput, unsigned stream)
2666 {
2667 struct si_shader_selector *sel = ctx->shader->selector;
2668 struct pipe_stream_output_info *so = &sel->so;
2669 LLVMBuilderRef builder = ctx->ac.builder;
2670 int i;
2671 struct lp_build_if_state if_ctx;
2672
2673 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2674 LLVMValueRef so_vtx_count =
2675 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2676
2677 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2678
2679 /* can_emit = tid < so_vtx_count; */
2680 LLVMValueRef can_emit =
2681 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2682
2683 /* Emit the streamout code conditionally. This actually avoids
2684 * out-of-bounds buffer access. The hw tells us via the SGPR
2685 * (so_vtx_count) which threads are allowed to emit streamout data. */
2686 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2687 {
2688 /* The buffer offset is computed as follows:
2689 * ByteOffset = streamout_offset[buffer_id]*4 +
2690 * (streamout_write_index + thread_id)*stride[buffer_id] +
2691 * attrib_offset
2692 */
2693
2694 LLVMValueRef so_write_index =
2695 LLVMGetParam(ctx->main_fn,
2696 ctx->param_streamout_write_index);
2697
2698 /* Compute (streamout_write_index + thread_id). */
2699 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2700
2701 /* Load the descriptor and compute the write offset for each
2702 * enabled buffer. */
2703 LLVMValueRef so_write_offset[4] = {};
2704 LLVMValueRef so_buffers[4];
2705 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2706 ctx->param_rw_buffers);
2707
2708 for (i = 0; i < 4; i++) {
2709 if (!so->stride[i])
2710 continue;
2711
2712 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2713 SI_VS_STREAMOUT_BUF0 + i, 0);
2714
2715 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2716
2717 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2718 ctx->param_streamout_offset[i]);
2719 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2720
2721 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2722 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2723 so_offset);
2724 }
2725
2726 /* Write streamout data. */
2727 for (i = 0; i < so->num_outputs; i++) {
2728 unsigned reg = so->output[i].register_index;
2729
2730 if (reg >= noutput)
2731 continue;
2732
2733 if (stream != so->output[i].stream)
2734 continue;
2735
2736 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2737 &so->output[i], &outputs[reg]);
2738 }
2739 }
2740 lp_build_endif(&if_ctx);
2741 }
2742
2743 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2744 LLVMValueRef *values)
2745 {
2746 struct ac_export_args args;
2747
2748 si_llvm_init_export_args(ctx, values,
2749 V_008DFC_SQ_EXP_PARAM + index, &args);
2750 ac_build_export(&ctx->ac, &args);
2751 }
2752
2753 static void si_build_param_exports(struct si_shader_context *ctx,
2754 struct si_shader_output_values *outputs,
2755 unsigned noutput)
2756 {
2757 struct si_shader *shader = ctx->shader;
2758 unsigned param_count = 0;
2759
2760 for (unsigned i = 0; i < noutput; i++) {
2761 unsigned semantic_name = outputs[i].semantic_name;
2762 unsigned semantic_index = outputs[i].semantic_index;
2763
2764 if (outputs[i].vertex_stream[0] != 0 &&
2765 outputs[i].vertex_stream[1] != 0 &&
2766 outputs[i].vertex_stream[2] != 0 &&
2767 outputs[i].vertex_stream[3] != 0)
2768 continue;
2769
2770 switch (semantic_name) {
2771 case TGSI_SEMANTIC_LAYER:
2772 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2773 case TGSI_SEMANTIC_CLIPDIST:
2774 case TGSI_SEMANTIC_COLOR:
2775 case TGSI_SEMANTIC_BCOLOR:
2776 case TGSI_SEMANTIC_PRIMID:
2777 case TGSI_SEMANTIC_FOG:
2778 case TGSI_SEMANTIC_TEXCOORD:
2779 case TGSI_SEMANTIC_GENERIC:
2780 break;
2781 default:
2782 continue;
2783 }
2784
2785 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2786 semantic_index < SI_MAX_IO_GENERIC) &&
2787 shader->key.opt.kill_outputs &
2788 (1ull << si_shader_io_get_unique_index(semantic_name,
2789 semantic_index, true)))
2790 continue;
2791
2792 si_export_param(ctx, param_count, outputs[i].values);
2793
2794 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2795 shader->info.vs_output_param_offset[i] = param_count++;
2796 }
2797
2798 shader->info.nr_param_exports = param_count;
2799 }
2800
2801 /**
2802 * Vertex color clamping.
2803 *
2804 * This uses a state constant loaded in a user data SGPR and
2805 * an IF statement is added that clamps all colors if the constant
2806 * is true.
2807 */
2808 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2809 struct si_shader_output_values *outputs,
2810 unsigned noutput)
2811 {
2812 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2813 bool has_colors = false;
2814
2815 /* Store original colors to alloca variables. */
2816 for (unsigned i = 0; i < noutput; i++) {
2817 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2818 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2819 continue;
2820
2821 for (unsigned j = 0; j < 4; j++) {
2822 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2823 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2824 }
2825 has_colors = true;
2826 }
2827
2828 if (!has_colors)
2829 return;
2830
2831 /* The state is in the first bit of the user SGPR. */
2832 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2833 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2834
2835 struct lp_build_if_state if_ctx;
2836 lp_build_if(&if_ctx, &ctx->gallivm, cond);
2837
2838 /* Store clamped colors to alloca variables within the conditional block. */
2839 for (unsigned i = 0; i < noutput; i++) {
2840 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2841 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2842 continue;
2843
2844 for (unsigned j = 0; j < 4; j++) {
2845 LLVMBuildStore(ctx->ac.builder,
2846 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2847 addr[i][j]);
2848 }
2849 }
2850 lp_build_endif(&if_ctx);
2851
2852 /* Load clamped colors */
2853 for (unsigned i = 0; i < noutput; i++) {
2854 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2855 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2856 continue;
2857
2858 for (unsigned j = 0; j < 4; j++) {
2859 outputs[i].values[j] =
2860 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2861 }
2862 }
2863 }
2864
2865 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2866 * (position and parameter data only).
2867 */
2868 void si_llvm_export_vs(struct si_shader_context *ctx,
2869 struct si_shader_output_values *outputs,
2870 unsigned noutput)
2871 {
2872 struct si_shader *shader = ctx->shader;
2873 struct ac_export_args pos_args[4] = {};
2874 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2875 unsigned pos_idx;
2876 int i;
2877
2878 si_vertex_color_clamping(ctx, outputs, noutput);
2879
2880 /* Build position exports. */
2881 for (i = 0; i < noutput; i++) {
2882 switch (outputs[i].semantic_name) {
2883 case TGSI_SEMANTIC_POSITION:
2884 si_llvm_init_export_args(ctx, outputs[i].values,
2885 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2886 break;
2887 case TGSI_SEMANTIC_PSIZE:
2888 psize_value = outputs[i].values[0];
2889 break;
2890 case TGSI_SEMANTIC_LAYER:
2891 layer_value = outputs[i].values[0];
2892 break;
2893 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2894 viewport_index_value = outputs[i].values[0];
2895 break;
2896 case TGSI_SEMANTIC_EDGEFLAG:
2897 edgeflag_value = outputs[i].values[0];
2898 break;
2899 case TGSI_SEMANTIC_CLIPDIST:
2900 if (!shader->key.opt.clip_disable) {
2901 unsigned index = 2 + outputs[i].semantic_index;
2902 si_llvm_init_export_args(ctx, outputs[i].values,
2903 V_008DFC_SQ_EXP_POS + index,
2904 &pos_args[index]);
2905 }
2906 break;
2907 case TGSI_SEMANTIC_CLIPVERTEX:
2908 if (!shader->key.opt.clip_disable) {
2909 si_llvm_emit_clipvertex(ctx, pos_args,
2910 outputs[i].values);
2911 }
2912 break;
2913 }
2914 }
2915
2916 /* We need to add the position output manually if it's missing. */
2917 if (!pos_args[0].out[0]) {
2918 pos_args[0].enabled_channels = 0xf; /* writemask */
2919 pos_args[0].valid_mask = 0; /* EXEC mask */
2920 pos_args[0].done = 0; /* last export? */
2921 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2922 pos_args[0].compr = 0; /* COMPR flag */
2923 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2924 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2925 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2926 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2927 }
2928
2929 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2930 if (shader->selector->info.writes_psize ||
2931 shader->selector->info.writes_edgeflag ||
2932 shader->selector->info.writes_viewport_index ||
2933 shader->selector->info.writes_layer) {
2934 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2935 (shader->selector->info.writes_edgeflag << 1) |
2936 (shader->selector->info.writes_layer << 2);
2937
2938 pos_args[1].valid_mask = 0; /* EXEC mask */
2939 pos_args[1].done = 0; /* last export? */
2940 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2941 pos_args[1].compr = 0; /* COMPR flag */
2942 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2943 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2944 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2945 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2946
2947 if (shader->selector->info.writes_psize)
2948 pos_args[1].out[0] = psize_value;
2949
2950 if (shader->selector->info.writes_edgeflag) {
2951 /* The output is a float, but the hw expects an integer
2952 * with the first bit containing the edge flag. */
2953 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2954 edgeflag_value,
2955 ctx->i32, "");
2956 edgeflag_value = ac_build_umin(&ctx->ac,
2957 edgeflag_value,
2958 ctx->i32_1);
2959
2960 /* The LLVM intrinsic expects a float. */
2961 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2962 }
2963
2964 if (ctx->screen->info.chip_class >= GFX9) {
2965 /* GFX9 has the layer in out.z[10:0] and the viewport
2966 * index in out.z[19:16].
2967 */
2968 if (shader->selector->info.writes_layer)
2969 pos_args[1].out[2] = layer_value;
2970
2971 if (shader->selector->info.writes_viewport_index) {
2972 LLVMValueRef v = viewport_index_value;
2973
2974 v = ac_to_integer(&ctx->ac, v);
2975 v = LLVMBuildShl(ctx->ac.builder, v,
2976 LLVMConstInt(ctx->i32, 16, 0), "");
2977 v = LLVMBuildOr(ctx->ac.builder, v,
2978 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2979 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2980 pos_args[1].enabled_channels |= 1 << 2;
2981 }
2982 } else {
2983 if (shader->selector->info.writes_layer)
2984 pos_args[1].out[2] = layer_value;
2985
2986 if (shader->selector->info.writes_viewport_index) {
2987 pos_args[1].out[3] = viewport_index_value;
2988 pos_args[1].enabled_channels |= 1 << 3;
2989 }
2990 }
2991 }
2992
2993 for (i = 0; i < 4; i++)
2994 if (pos_args[i].out[0])
2995 shader->info.nr_pos_exports++;
2996
2997 pos_idx = 0;
2998 for (i = 0; i < 4; i++) {
2999 if (!pos_args[i].out[0])
3000 continue;
3001
3002 /* Specify the target we are exporting */
3003 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3004
3005 if (pos_idx == shader->info.nr_pos_exports)
3006 /* Specify that this is the last export */
3007 pos_args[i].done = 1;
3008
3009 ac_build_export(&ctx->ac, &pos_args[i]);
3010 }
3011
3012 /* Build parameter exports. */
3013 si_build_param_exports(ctx, outputs, noutput);
3014 }
3015
3016 /**
3017 * Forward all outputs from the vertex shader to the TES. This is only used
3018 * for the fixed function TCS.
3019 */
3020 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3021 {
3022 struct si_shader_context *ctx = si_shader_context(bld_base);
3023 LLVMValueRef invocation_id, buffer, buffer_offset;
3024 LLVMValueRef lds_vertex_stride, lds_base;
3025 uint64_t inputs;
3026
3027 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3028 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3029 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3030
3031 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3032 lds_base = get_tcs_in_current_patch_offset(ctx);
3033 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3034 lds_base);
3035
3036 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3037 while (inputs) {
3038 unsigned i = u_bit_scan64(&inputs);
3039
3040 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3041 LLVMConstInt(ctx->i32, 4 * i, 0),
3042 "");
3043
3044 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3045 get_rel_patch_id(ctx),
3046 invocation_id,
3047 LLVMConstInt(ctx->i32, i, 0));
3048
3049 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3050
3051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3052 buffer_offset, 0, 1, 0, false);
3053 }
3054 }
3055
3056 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3057 LLVMValueRef rel_patch_id,
3058 LLVMValueRef invocation_id,
3059 LLVMValueRef tcs_out_current_patch_data_offset,
3060 LLVMValueRef invoc0_tf_outer[4],
3061 LLVMValueRef invoc0_tf_inner[2])
3062 {
3063 struct si_shader_context *ctx = si_shader_context(bld_base);
3064 struct si_shader *shader = ctx->shader;
3065 unsigned tess_inner_index, tess_outer_index;
3066 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3067 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3068 unsigned stride, outer_comps, inner_comps, i, offset;
3069 struct lp_build_if_state if_ctx, inner_if_ctx;
3070
3071 /* Add a barrier before loading tess factors from LDS. */
3072 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3073 si_llvm_emit_barrier(NULL, bld_base, NULL);
3074
3075 /* Do this only for invocation 0, because the tess levels are per-patch,
3076 * not per-vertex.
3077 *
3078 * This can't jump, because invocation 0 executes this. It should
3079 * at least mask out the loads and stores for other invocations.
3080 */
3081 lp_build_if(&if_ctx, &ctx->gallivm,
3082 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3083 invocation_id, ctx->i32_0, ""));
3084
3085 /* Determine the layout of one tess factor element in the buffer. */
3086 switch (shader->key.part.tcs.epilog.prim_mode) {
3087 case PIPE_PRIM_LINES:
3088 stride = 2; /* 2 dwords, 1 vec2 store */
3089 outer_comps = 2;
3090 inner_comps = 0;
3091 break;
3092 case PIPE_PRIM_TRIANGLES:
3093 stride = 4; /* 4 dwords, 1 vec4 store */
3094 outer_comps = 3;
3095 inner_comps = 1;
3096 break;
3097 case PIPE_PRIM_QUADS:
3098 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3099 outer_comps = 4;
3100 inner_comps = 2;
3101 break;
3102 default:
3103 assert(0);
3104 return;
3105 }
3106
3107 for (i = 0; i < 4; i++) {
3108 inner[i] = LLVMGetUndef(ctx->i32);
3109 outer[i] = LLVMGetUndef(ctx->i32);
3110 }
3111
3112 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3113 /* Tess factors are in VGPRs. */
3114 for (i = 0; i < outer_comps; i++)
3115 outer[i] = out[i] = invoc0_tf_outer[i];
3116 for (i = 0; i < inner_comps; i++)
3117 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3118 } else {
3119 /* Load tess_inner and tess_outer from LDS.
3120 * Any invocation can write them, so we can't get them from a temporary.
3121 */
3122 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3123 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3124
3125 lds_base = tcs_out_current_patch_data_offset;
3126 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3127 LLVMConstInt(ctx->i32,
3128 tess_inner_index * 4, 0), "");
3129 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3130 LLVMConstInt(ctx->i32,
3131 tess_outer_index * 4, 0), "");
3132
3133 for (i = 0; i < outer_comps; i++) {
3134 outer[i] = out[i] =
3135 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3136 }
3137 for (i = 0; i < inner_comps; i++) {
3138 inner[i] = out[outer_comps+i] =
3139 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3140 }
3141 }
3142
3143 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3144 /* For isolines, the hardware expects tess factors in the
3145 * reverse order from what GLSL / TGSI specify.
3146 */
3147 LLVMValueRef tmp = out[0];
3148 out[0] = out[1];
3149 out[1] = tmp;
3150 }
3151
3152 /* Convert the outputs to vectors for stores. */
3153 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3154 vec1 = NULL;
3155
3156 if (stride > 4)
3157 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3158
3159 /* Get the buffer. */
3160 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3161
3162 /* Get the offset. */
3163 tf_base = LLVMGetParam(ctx->main_fn,
3164 ctx->param_tcs_factor_offset);
3165 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3166 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3167
3168 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3169 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3170 rel_patch_id, ctx->i32_0, ""));
3171
3172 /* Store the dynamic HS control word. */
3173 offset = 0;
3174 if (ctx->screen->info.chip_class <= GFX8) {
3175 ac_build_buffer_store_dword(&ctx->ac, buffer,
3176 LLVMConstInt(ctx->i32, 0x80000000, 0),
3177 1, ctx->i32_0, tf_base,
3178 offset, 1, 0, false);
3179 offset += 4;
3180 }
3181
3182 lp_build_endif(&inner_if_ctx);
3183
3184 /* Store the tessellation factors. */
3185 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3186 MIN2(stride, 4), byteoffset, tf_base,
3187 offset, 1, 0, false);
3188 offset += 16;
3189 if (vec1)
3190 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3191 stride - 4, byteoffset, tf_base,
3192 offset, 1, 0, false);
3193
3194 /* Store the tess factors into the offchip buffer if TES reads them. */
3195 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3196 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3197 LLVMValueRef tf_inner_offset;
3198 unsigned param_outer, param_inner;
3199
3200 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3201 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3202
3203 param_outer = si_shader_io_get_unique_index_patch(
3204 TGSI_SEMANTIC_TESSOUTER, 0);
3205 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3206 LLVMConstInt(ctx->i32, param_outer, 0));
3207
3208 unsigned outer_vec_size =
3209 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3210 outer_comps : util_next_power_of_two(outer_comps);
3211 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3212
3213 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3214 outer_comps, tf_outer_offset,
3215 base, 0, 1, 0, false);
3216 if (inner_comps) {
3217 param_inner = si_shader_io_get_unique_index_patch(
3218 TGSI_SEMANTIC_TESSINNER, 0);
3219 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3220 LLVMConstInt(ctx->i32, param_inner, 0));
3221
3222 inner_vec = inner_comps == 1 ? inner[0] :
3223 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3224 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3225 inner_comps, tf_inner_offset,
3226 base, 0, 1, 0, false);
3227 }
3228 }
3229
3230 lp_build_endif(&if_ctx);
3231 }
3232
3233 static LLVMValueRef
3234 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3235 unsigned param, unsigned return_index)
3236 {
3237 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3238 LLVMGetParam(ctx->main_fn, param),
3239 return_index, "");
3240 }
3241
3242 static LLVMValueRef
3243 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3244 unsigned param, unsigned return_index)
3245 {
3246 LLVMBuilderRef builder = ctx->ac.builder;
3247 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3248
3249 return LLVMBuildInsertValue(builder, ret,
3250 ac_to_float(&ctx->ac, p),
3251 return_index, "");
3252 }
3253
3254 static LLVMValueRef
3255 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3256 unsigned param, unsigned return_index)
3257 {
3258 LLVMBuilderRef builder = ctx->ac.builder;
3259 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3260 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3261 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3262 }
3263
3264 /* This only writes the tessellation factor levels. */
3265 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3266 unsigned max_outputs,
3267 LLVMValueRef *addrs)
3268 {
3269 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3270 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3271 LLVMBuilderRef builder = ctx->ac.builder;
3272 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3273
3274 si_copy_tcs_inputs(bld_base);
3275
3276 rel_patch_id = get_rel_patch_id(ctx);
3277 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3278 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3279
3280 if (ctx->screen->info.chip_class >= GFX9) {
3281 LLVMBasicBlockRef blocks[2] = {
3282 LLVMGetInsertBlock(builder),
3283 ctx->merged_wrap_if_state.entry_block
3284 };
3285 LLVMValueRef values[2];
3286
3287 lp_build_endif(&ctx->merged_wrap_if_state);
3288
3289 values[0] = rel_patch_id;
3290 values[1] = LLVMGetUndef(ctx->i32);
3291 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3292
3293 values[0] = tf_lds_offset;
3294 values[1] = LLVMGetUndef(ctx->i32);
3295 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3296
3297 values[0] = invocation_id;
3298 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3299 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3300 }
3301
3302 /* Return epilog parameters from this function. */
3303 LLVMValueRef ret = ctx->return_value;
3304 unsigned vgpr;
3305
3306 if (ctx->screen->info.chip_class >= GFX9) {
3307 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3308 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3309 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3310 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3311 /* Tess offchip and tess factor offsets are at the beginning. */
3312 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3313 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3314 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3315 } else {
3316 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3317 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3318 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3319 GFX6_SGPR_TCS_OUT_LAYOUT);
3320 /* Tess offchip and tess factor offsets are after user SGPRs. */
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3322 GFX6_TCS_NUM_USER_SGPR);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3324 GFX6_TCS_NUM_USER_SGPR + 1);
3325 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3326 }
3327
3328 /* VGPRs */
3329 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3330 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3331 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3332
3333 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3334 * the invocation_id output does not alias the tcs_rel_ids input,
3335 * which saves a V_MOV on gfx9.
3336 */
3337 vgpr += 2;
3338
3339 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3340 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3341
3342 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3343 vgpr++; /* skip the tess factor LDS offset */
3344 for (unsigned i = 0; i < 6; i++) {
3345 LLVMValueRef value =
3346 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3347 value = ac_to_float(&ctx->ac, value);
3348 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3349 }
3350 } else {
3351 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3352 }
3353 ctx->return_value = ret;
3354 }
3355
3356 /* Pass TCS inputs from LS to TCS on GFX9. */
3357 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3358 {
3359 LLVMValueRef ret = ctx->return_value;
3360
3361 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3362 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3363 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3364 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3365 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3366 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3367
3368 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3369 8 + SI_SGPR_RW_BUFFERS);
3370 ret = si_insert_input_ptr(ctx, ret,
3371 ctx->param_bindless_samplers_and_images,
3372 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3373
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3375 8 + SI_SGPR_VS_STATE_BITS);
3376
3377 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3378 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3379 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3380 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3381 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3382 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3383
3384 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3385 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3386 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3387 vgpr++, "");
3388 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3389 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3390 vgpr++, "");
3391 ctx->return_value = ret;
3392 }
3393
3394 /* Pass GS inputs from ES to GS on GFX9. */
3395 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3396 {
3397 LLVMValueRef ret = ctx->return_value;
3398
3399 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3400 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3401 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3402 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3403 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3404
3405 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3406 8 + SI_SGPR_RW_BUFFERS);
3407 ret = si_insert_input_ptr(ctx, ret,
3408 ctx->param_bindless_samplers_and_images,
3409 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3410
3411 unsigned vgpr;
3412 if (ctx->type == PIPE_SHADER_VERTEX)
3413 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3414 else
3415 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3416
3417 for (unsigned i = 0; i < 5; i++) {
3418 unsigned param = ctx->param_gs_vtx01_offset + i;
3419 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3420 }
3421 ctx->return_value = ret;
3422 }
3423
3424 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3425 unsigned max_outputs,
3426 LLVMValueRef *addrs)
3427 {
3428 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3429 struct si_shader *shader = ctx->shader;
3430 struct tgsi_shader_info *info = &shader->selector->info;
3431 unsigned i, chan;
3432 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3433 ctx->param_rel_auto_id);
3434 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3435 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3436 vertex_dw_stride, "");
3437
3438 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3439 * its inputs from it. */
3440 for (i = 0; i < info->num_outputs; i++) {
3441 unsigned name = info->output_semantic_name[i];
3442 unsigned index = info->output_semantic_index[i];
3443
3444 /* The ARB_shader_viewport_layer_array spec contains the
3445 * following issue:
3446 *
3447 * 2) What happens if gl_ViewportIndex or gl_Layer is
3448 * written in the vertex shader and a geometry shader is
3449 * present?
3450 *
3451 * RESOLVED: The value written by the last vertex processing
3452 * stage is used. If the last vertex processing stage
3453 * (vertex, tessellation evaluation or geometry) does not
3454 * statically assign to gl_ViewportIndex or gl_Layer, index
3455 * or layer zero is assumed.
3456 *
3457 * So writes to those outputs in VS-as-LS are simply ignored.
3458 */
3459 if (name == TGSI_SEMANTIC_LAYER ||
3460 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3461 continue;
3462
3463 int param = si_shader_io_get_unique_index(name, index, false);
3464 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3465 LLVMConstInt(ctx->i32, param * 4, 0), "");
3466
3467 for (chan = 0; chan < 4; chan++) {
3468 if (!(info->output_usagemask[i] & (1 << chan)))
3469 continue;
3470
3471 lshs_lds_store(ctx, chan, dw_addr,
3472 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3473 }
3474 }
3475
3476 if (ctx->screen->info.chip_class >= GFX9)
3477 si_set_ls_return_value_for_tcs(ctx);
3478 }
3479
3480 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3481 unsigned max_outputs,
3482 LLVMValueRef *addrs)
3483 {
3484 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3485 struct si_shader *es = ctx->shader;
3486 struct tgsi_shader_info *info = &es->selector->info;
3487 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3488 ctx->param_es2gs_offset);
3489 LLVMValueRef lds_base = NULL;
3490 unsigned chan;
3491 int i;
3492
3493 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3494 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3495 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3496 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3497 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3498 LLVMBuildMul(ctx->ac.builder, wave_idx,
3499 LLVMConstInt(ctx->i32, 64, false), ""), "");
3500 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3501 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3502 }
3503
3504 for (i = 0; i < info->num_outputs; i++) {
3505 int param;
3506
3507 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3508 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3509 continue;
3510
3511 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3512 info->output_semantic_index[i], false);
3513
3514 for (chan = 0; chan < 4; chan++) {
3515 if (!(info->output_usagemask[i] & (1 << chan)))
3516 continue;
3517
3518 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3519 out_val = ac_to_integer(&ctx->ac, out_val);
3520
3521 /* GFX9 has the ESGS ring in LDS. */
3522 if (ctx->screen->info.chip_class >= GFX9) {
3523 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
3524 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
3525 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
3526 continue;
3527 }
3528
3529 ac_build_buffer_store_dword(&ctx->ac,
3530 ctx->esgs_ring,
3531 out_val, 1, NULL, soffset,
3532 (4 * param + chan) * 4,
3533 1, 1, true);
3534 }
3535 }
3536
3537 if (ctx->screen->info.chip_class >= GFX9)
3538 si_set_es_return_value_for_gs(ctx);
3539 }
3540
3541 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3542 {
3543 if (ctx->screen->info.chip_class >= GFX9)
3544 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3545 else
3546 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3547 }
3548
3549 static void emit_gs_epilogue(struct si_shader_context *ctx)
3550 {
3551 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3552 si_get_gs_wave_id(ctx));
3553
3554 if (ctx->screen->info.chip_class >= GFX9)
3555 lp_build_endif(&ctx->merged_wrap_if_state);
3556 }
3557
3558 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3559 unsigned max_outputs,
3560 LLVMValueRef *addrs)
3561 {
3562 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3563 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3564
3565 assert(info->num_outputs <= max_outputs);
3566
3567 emit_gs_epilogue(ctx);
3568 }
3569
3570 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3571 {
3572 struct si_shader_context *ctx = si_shader_context(bld_base);
3573 emit_gs_epilogue(ctx);
3574 }
3575
3576 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3577 unsigned max_outputs,
3578 LLVMValueRef *addrs)
3579 {
3580 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3581 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3582 struct si_shader_output_values *outputs = NULL;
3583 int i,j;
3584
3585 assert(!ctx->shader->is_gs_copy_shader);
3586 assert(info->num_outputs <= max_outputs);
3587
3588 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3589
3590 for (i = 0; i < info->num_outputs; i++) {
3591 outputs[i].semantic_name = info->output_semantic_name[i];
3592 outputs[i].semantic_index = info->output_semantic_index[i];
3593
3594 for (j = 0; j < 4; j++) {
3595 outputs[i].values[j] =
3596 LLVMBuildLoad(ctx->ac.builder,
3597 addrs[4 * i + j],
3598 "");
3599 outputs[i].vertex_stream[j] =
3600 (info->output_streams[i] >> (2 * j)) & 3;
3601 }
3602 }
3603
3604 if (ctx->shader->selector->so.num_outputs)
3605 si_llvm_emit_streamout(ctx, outputs, i, 0);
3606
3607 /* Export PrimitiveID. */
3608 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3609 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3610 outputs[i].semantic_index = 0;
3611 outputs[i].values[0] = ac_to_float(&ctx->ac, si_get_primitive_id(ctx, 0));
3612 for (j = 1; j < 4; j++)
3613 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3614
3615 memset(outputs[i].vertex_stream, 0,
3616 sizeof(outputs[i].vertex_stream));
3617 i++;
3618 }
3619
3620 si_llvm_export_vs(ctx, outputs, i);
3621 FREE(outputs);
3622 }
3623
3624 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3625 unsigned max_outputs,
3626 LLVMValueRef *addrs)
3627 {
3628 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3629 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3630 LLVMValueRef pos[4] = {};
3631
3632 assert(info->num_outputs <= max_outputs);
3633
3634 for (unsigned i = 0; i < info->num_outputs; i++) {
3635 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3636 continue;
3637
3638 for (unsigned chan = 0; chan < 4; chan++)
3639 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3640 break;
3641 }
3642 assert(pos[0] != NULL);
3643
3644 /* Return the position output. */
3645 LLVMValueRef ret = ctx->return_value;
3646 for (unsigned chan = 0; chan < 4; chan++)
3647 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3648 ctx->return_value = ret;
3649 }
3650
3651 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3652 {
3653 struct si_shader_context *ctx = si_shader_context(bld_base);
3654
3655 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3656 &ctx->outputs[0][0]);
3657 }
3658
3659 struct si_ps_exports {
3660 unsigned num;
3661 struct ac_export_args args[10];
3662 };
3663
3664 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3665 LLVMValueRef depth, LLVMValueRef stencil,
3666 LLVMValueRef samplemask, struct si_ps_exports *exp)
3667 {
3668 struct si_shader_context *ctx = si_shader_context(bld_base);
3669 struct ac_export_args args;
3670
3671 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3672
3673 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3674 }
3675
3676 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3677 LLVMValueRef *color, unsigned index,
3678 unsigned samplemask_param,
3679 bool is_last, struct si_ps_exports *exp)
3680 {
3681 struct si_shader_context *ctx = si_shader_context(bld_base);
3682 int i;
3683
3684 /* Clamp color */
3685 if (ctx->shader->key.part.ps.epilog.clamp_color)
3686 for (i = 0; i < 4; i++)
3687 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3688
3689 /* Alpha to one */
3690 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3691 color[3] = ctx->ac.f32_1;
3692
3693 /* Alpha test */
3694 if (index == 0 &&
3695 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3696 si_alpha_test(bld_base, color[3]);
3697
3698 /* Line & polygon smoothing */
3699 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3700 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3701 samplemask_param);
3702
3703 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3704 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3705 struct ac_export_args args[8];
3706 int c, last = -1;
3707
3708 /* Get the export arguments, also find out what the last one is. */
3709 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3710 si_llvm_init_export_args(ctx, color,
3711 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3712 if (args[c].enabled_channels)
3713 last = c;
3714 }
3715
3716 /* Emit all exports. */
3717 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3718 if (is_last && last == c) {
3719 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3720 args[c].done = 1; /* DONE bit */
3721 } else if (!args[c].enabled_channels)
3722 continue; /* unnecessary NULL export */
3723
3724 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3725 }
3726 } else {
3727 struct ac_export_args args;
3728
3729 /* Export */
3730 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3731 &args);
3732 if (is_last) {
3733 args.valid_mask = 1; /* whether the EXEC mask is valid */
3734 args.done = 1; /* DONE bit */
3735 } else if (!args.enabled_channels)
3736 return; /* unnecessary NULL export */
3737
3738 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3739 }
3740 }
3741
3742 static void si_emit_ps_exports(struct si_shader_context *ctx,
3743 struct si_ps_exports *exp)
3744 {
3745 for (unsigned i = 0; i < exp->num; i++)
3746 ac_build_export(&ctx->ac, &exp->args[i]);
3747 }
3748
3749 /**
3750 * Return PS outputs in this order:
3751 *
3752 * v[0:3] = color0.xyzw
3753 * v[4:7] = color1.xyzw
3754 * ...
3755 * vN+0 = Depth
3756 * vN+1 = Stencil
3757 * vN+2 = SampleMask
3758 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3759 *
3760 * The alpha-ref SGPR is returned via its original location.
3761 */
3762 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3763 unsigned max_outputs,
3764 LLVMValueRef *addrs)
3765 {
3766 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3767 struct si_shader *shader = ctx->shader;
3768 struct tgsi_shader_info *info = &shader->selector->info;
3769 LLVMBuilderRef builder = ctx->ac.builder;
3770 unsigned i, j, first_vgpr, vgpr;
3771
3772 LLVMValueRef color[8][4] = {};
3773 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3774 LLVMValueRef ret;
3775
3776 if (ctx->postponed_kill)
3777 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3778
3779 /* Read the output values. */
3780 for (i = 0; i < info->num_outputs; i++) {
3781 unsigned semantic_name = info->output_semantic_name[i];
3782 unsigned semantic_index = info->output_semantic_index[i];
3783
3784 switch (semantic_name) {
3785 case TGSI_SEMANTIC_COLOR:
3786 assert(semantic_index < 8);
3787 for (j = 0; j < 4; j++) {
3788 LLVMValueRef ptr = addrs[4 * i + j];
3789 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3790 color[semantic_index][j] = result;
3791 }
3792 break;
3793 case TGSI_SEMANTIC_POSITION:
3794 depth = LLVMBuildLoad(builder,
3795 addrs[4 * i + 2], "");
3796 break;
3797 case TGSI_SEMANTIC_STENCIL:
3798 stencil = LLVMBuildLoad(builder,
3799 addrs[4 * i + 1], "");
3800 break;
3801 case TGSI_SEMANTIC_SAMPLEMASK:
3802 samplemask = LLVMBuildLoad(builder,
3803 addrs[4 * i + 0], "");
3804 break;
3805 default:
3806 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3807 semantic_name);
3808 }
3809 }
3810
3811 /* Fill the return structure. */
3812 ret = ctx->return_value;
3813
3814 /* Set SGPRs. */
3815 ret = LLVMBuildInsertValue(builder, ret,
3816 ac_to_integer(&ctx->ac,
3817 LLVMGetParam(ctx->main_fn,
3818 SI_PARAM_ALPHA_REF)),
3819 SI_SGPR_ALPHA_REF, "");
3820
3821 /* Set VGPRs */
3822 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3823 for (i = 0; i < ARRAY_SIZE(color); i++) {
3824 if (!color[i][0])
3825 continue;
3826
3827 for (j = 0; j < 4; j++)
3828 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3829 }
3830 if (depth)
3831 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3832 if (stencil)
3833 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3834 if (samplemask)
3835 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3836
3837 /* Add the input sample mask for smoothing at the end. */
3838 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3839 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3840 ret = LLVMBuildInsertValue(builder, ret,
3841 LLVMGetParam(ctx->main_fn,
3842 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3843
3844 ctx->return_value = ret;
3845 }
3846
3847 static void membar_emit(
3848 const struct lp_build_tgsi_action *action,
3849 struct lp_build_tgsi_context *bld_base,
3850 struct lp_build_emit_data *emit_data)
3851 {
3852 struct si_shader_context *ctx = si_shader_context(bld_base);
3853 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3854 unsigned flags = LLVMConstIntGetZExtValue(src0);
3855 unsigned waitcnt = NOOP_WAITCNT;
3856
3857 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3858 waitcnt &= VM_CNT & LGKM_CNT;
3859
3860 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3861 TGSI_MEMBAR_SHADER_BUFFER |
3862 TGSI_MEMBAR_SHADER_IMAGE))
3863 waitcnt &= VM_CNT;
3864
3865 if (flags & TGSI_MEMBAR_SHARED)
3866 waitcnt &= LGKM_CNT;
3867
3868 if (waitcnt != NOOP_WAITCNT)
3869 ac_build_waitcnt(&ctx->ac, waitcnt);
3870 }
3871
3872 static void clock_emit(
3873 const struct lp_build_tgsi_action *action,
3874 struct lp_build_tgsi_context *bld_base,
3875 struct lp_build_emit_data *emit_data)
3876 {
3877 struct si_shader_context *ctx = si_shader_context(bld_base);
3878 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3879
3880 emit_data->output[0] =
3881 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3882 emit_data->output[1] =
3883 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3884 }
3885
3886 static void si_llvm_emit_ddxy(
3887 const struct lp_build_tgsi_action *action,
3888 struct lp_build_tgsi_context *bld_base,
3889 struct lp_build_emit_data *emit_data)
3890 {
3891 struct si_shader_context *ctx = si_shader_context(bld_base);
3892 unsigned opcode = emit_data->info->opcode;
3893 LLVMValueRef val;
3894 int idx;
3895 unsigned mask;
3896
3897 if (opcode == TGSI_OPCODE_DDX_FINE)
3898 mask = AC_TID_MASK_LEFT;
3899 else if (opcode == TGSI_OPCODE_DDY_FINE)
3900 mask = AC_TID_MASK_TOP;
3901 else
3902 mask = AC_TID_MASK_TOP_LEFT;
3903
3904 /* for DDX we want to next X pixel, DDY next Y pixel. */
3905 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3906
3907 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3908 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3909 emit_data->output[emit_data->chan] = val;
3910 }
3911
3912 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3913 struct lp_build_tgsi_context *bld_base,
3914 struct lp_build_emit_data *emit_data)
3915 {
3916 struct si_shader_context *ctx = si_shader_context(bld_base);
3917 struct si_shader *shader = ctx->shader;
3918 const struct tgsi_shader_info *info = &shader->selector->info;
3919 LLVMValueRef interp_param;
3920 const struct tgsi_full_instruction *inst = emit_data->inst;
3921 const struct tgsi_full_src_register *input = &inst->Src[0];
3922 int input_base, input_array_size;
3923 int chan;
3924 int i;
3925 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3926 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3927 int interp_param_idx;
3928 unsigned interp;
3929 unsigned location;
3930
3931 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3932 /* offset is in second src, first two channels */
3933 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3934 TGSI_CHAN_X);
3935 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3936 TGSI_CHAN_Y);
3937 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3938 LLVMValueRef sample_position;
3939 LLVMValueRef sample_id;
3940 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3941
3942 /* fetch sample ID, then fetch its sample position,
3943 * and place into first two channels.
3944 */
3945 sample_id = lp_build_emit_fetch(bld_base,
3946 emit_data->inst, 1, TGSI_CHAN_X);
3947 sample_id = ac_to_integer(&ctx->ac, sample_id);
3948
3949 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3950 * Language 4.50 spec says about interpolateAtSample:
3951 *
3952 * "Returns the value of the input interpolant variable at
3953 * the location of sample number sample. If multisample
3954 * buffers are not available, the input variable will be
3955 * evaluated at the center of the pixel. If sample sample
3956 * does not exist, the position used to interpolate the
3957 * input variable is undefined."
3958 *
3959 * This means that sample_id values outside of the valid are
3960 * in fact valid input, and the usual mechanism for loading the
3961 * sample position doesn't work.
3962 */
3963 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3964 LLVMValueRef center[4] = {
3965 LLVMConstReal(ctx->f32, 0.5),
3966 LLVMConstReal(ctx->f32, 0.5),
3967 ctx->ac.f32_0,
3968 ctx->ac.f32_0,
3969 };
3970
3971 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
3972 } else {
3973 sample_position = load_sample_position(&ctx->abi, sample_id);
3974 }
3975
3976 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3977 ctx->i32_0, "");
3978
3979 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
3980 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3981 ctx->i32_1, "");
3982 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
3983 }
3984
3985 assert(input->Register.File == TGSI_FILE_INPUT);
3986
3987 if (input->Register.Indirect) {
3988 unsigned array_id = input->Indirect.ArrayID;
3989
3990 if (array_id) {
3991 input_base = info->input_array_first[array_id];
3992 input_array_size = info->input_array_last[array_id] - input_base + 1;
3993 } else {
3994 input_base = inst->Src[0].Register.Index;
3995 input_array_size = info->num_inputs - input_base;
3996 }
3997
3998 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3999 1, input->Register.Index - input_base);
4000 } else {
4001 input_base = inst->Src[0].Register.Index;
4002 input_array_size = 1;
4003 array_idx = ctx->i32_0;
4004 }
4005
4006 interp = shader->selector->info.input_interpolate[input_base];
4007
4008 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4009 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4010 location = TGSI_INTERPOLATE_LOC_CENTER;
4011 else
4012 location = TGSI_INTERPOLATE_LOC_CENTROID;
4013
4014 interp_param_idx = lookup_interp_param_index(interp, location);
4015 if (interp_param_idx == -1)
4016 return;
4017 else if (interp_param_idx)
4018 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4019 else
4020 interp_param = NULL;
4021
4022 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4023 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4024 LLVMValueRef ij_out[2];
4025 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4026
4027 /*
4028 * take the I then J parameters, and the DDX/Y for it, and
4029 * calculate the IJ inputs for the interpolator.
4030 * temp1 = ddx * offset/sample.x + I;
4031 * interp_param.I = ddy * offset/sample.y + temp1;
4032 * temp1 = ddx * offset/sample.x + J;
4033 * interp_param.J = ddy * offset/sample.y + temp1;
4034 */
4035 for (i = 0; i < 2; i++) {
4036 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4037 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4038 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4039 ddxy_out, ix_ll, "");
4040 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4041 ddxy_out, iy_ll, "");
4042 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4043 interp_param, ix_ll, "");
4044 LLVMValueRef temp;
4045
4046 interp_el = ac_to_float(&ctx->ac, interp_el);
4047
4048 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4049 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4050 }
4051 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4052 }
4053
4054 if (interp_param)
4055 interp_param = ac_to_float(&ctx->ac, interp_param);
4056
4057 for (chan = 0; chan < 4; chan++) {
4058 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4059 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4060
4061 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4062 LLVMValueRef v, i = NULL, j = NULL;
4063
4064 if (interp_param) {
4065 i = LLVMBuildExtractElement(
4066 ctx->ac.builder, interp_param, ctx->i32_0, "");
4067 j = LLVMBuildExtractElement(
4068 ctx->ac.builder, interp_param, ctx->i32_1, "");
4069 }
4070 v = si_build_fs_interp(ctx, input_base + idx, schan,
4071 prim_mask, i, j);
4072
4073 gather = LLVMBuildInsertElement(ctx->ac.builder,
4074 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4075 }
4076
4077 emit_data->output[chan] = LLVMBuildExtractElement(
4078 ctx->ac.builder, gather, array_idx, "");
4079 }
4080 }
4081
4082 static void vote_all_emit(
4083 const struct lp_build_tgsi_action *action,
4084 struct lp_build_tgsi_context *bld_base,
4085 struct lp_build_emit_data *emit_data)
4086 {
4087 struct si_shader_context *ctx = si_shader_context(bld_base);
4088
4089 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4090 emit_data->output[emit_data->chan] =
4091 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4092 }
4093
4094 static void vote_any_emit(
4095 const struct lp_build_tgsi_action *action,
4096 struct lp_build_tgsi_context *bld_base,
4097 struct lp_build_emit_data *emit_data)
4098 {
4099 struct si_shader_context *ctx = si_shader_context(bld_base);
4100
4101 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4102 emit_data->output[emit_data->chan] =
4103 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4104 }
4105
4106 static void vote_eq_emit(
4107 const struct lp_build_tgsi_action *action,
4108 struct lp_build_tgsi_context *bld_base,
4109 struct lp_build_emit_data *emit_data)
4110 {
4111 struct si_shader_context *ctx = si_shader_context(bld_base);
4112
4113 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4114 emit_data->output[emit_data->chan] =
4115 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4116 }
4117
4118 static void ballot_emit(
4119 const struct lp_build_tgsi_action *action,
4120 struct lp_build_tgsi_context *bld_base,
4121 struct lp_build_emit_data *emit_data)
4122 {
4123 struct si_shader_context *ctx = si_shader_context(bld_base);
4124 LLVMBuilderRef builder = ctx->ac.builder;
4125 LLVMValueRef tmp;
4126
4127 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4128 tmp = ac_build_ballot(&ctx->ac, tmp);
4129 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4130
4131 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4132 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4133 }
4134
4135 static void read_lane_emit(
4136 const struct lp_build_tgsi_action *action,
4137 struct lp_build_tgsi_context *bld_base,
4138 struct lp_build_emit_data *emit_data)
4139 {
4140 struct si_shader_context *ctx = si_shader_context(bld_base);
4141
4142 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4143 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4144 0, emit_data->src_chan);
4145
4146 /* Always read the source invocation (= lane) from the X channel. */
4147 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4148 1, TGSI_CHAN_X);
4149 emit_data->arg_count = 2;
4150 }
4151
4152 /* We currently have no other way to prevent LLVM from lifting the icmp
4153 * calls to a dominating basic block.
4154 */
4155 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4156
4157 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4158 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4159
4160 emit_data->output[emit_data->chan] =
4161 ac_build_intrinsic(&ctx->ac, action->intr_name,
4162 ctx->i32, emit_data->args, emit_data->arg_count,
4163 AC_FUNC_ATTR_READNONE |
4164 AC_FUNC_ATTR_CONVERGENT);
4165 }
4166
4167 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4168 struct lp_build_emit_data *emit_data)
4169 {
4170 struct si_shader_context *ctx = si_shader_context(bld_base);
4171 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4172 LLVMValueRef imm;
4173 unsigned stream;
4174
4175 assert(src0.File == TGSI_FILE_IMMEDIATE);
4176
4177 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4178 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4179 return stream;
4180 }
4181
4182 /* Emit one vertex from the geometry shader */
4183 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4184 unsigned stream,
4185 LLVMValueRef *addrs)
4186 {
4187 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4188 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4189 struct si_shader *shader = ctx->shader;
4190 struct lp_build_if_state if_state;
4191 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4192 ctx->param_gs2vs_offset);
4193 LLVMValueRef gs_next_vertex;
4194 LLVMValueRef can_emit;
4195 unsigned chan, offset;
4196 int i;
4197
4198 /* Write vertex attribute values to GSVS ring */
4199 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4200 ctx->gs_next_vertex[stream],
4201 "");
4202
4203 /* If this thread has already emitted the declared maximum number of
4204 * vertices, skip the write: excessive vertex emissions are not
4205 * supposed to have any effect.
4206 *
4207 * If the shader has no writes to memory, kill it instead. This skips
4208 * further memory loads and may allow LLVM to skip to the end
4209 * altogether.
4210 */
4211 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4212 LLVMConstInt(ctx->i32,
4213 shader->selector->gs_max_out_vertices, 0), "");
4214
4215 bool use_kill = !info->writes_memory;
4216 if (use_kill) {
4217 ac_build_kill_if_false(&ctx->ac, can_emit);
4218 } else {
4219 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4220 }
4221
4222 offset = 0;
4223 for (i = 0; i < info->num_outputs; i++) {
4224 for (chan = 0; chan < 4; chan++) {
4225 if (!(info->output_usagemask[i] & (1 << chan)) ||
4226 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4227 continue;
4228
4229 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4230 LLVMValueRef voffset =
4231 LLVMConstInt(ctx->i32, offset *
4232 shader->selector->gs_max_out_vertices, 0);
4233 offset++;
4234
4235 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4236 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4237 LLVMConstInt(ctx->i32, 4, 0), "");
4238
4239 out_val = ac_to_integer(&ctx->ac, out_val);
4240
4241 ac_build_buffer_store_dword(&ctx->ac,
4242 ctx->gsvs_ring[stream],
4243 out_val, 1,
4244 voffset, soffset, 0,
4245 1, 1, true);
4246 }
4247 }
4248
4249 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4250 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4251
4252 /* Signal vertex emission if vertex data was written. */
4253 if (offset) {
4254 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4255 si_get_gs_wave_id(ctx));
4256 }
4257
4258 if (!use_kill)
4259 lp_build_endif(&if_state);
4260 }
4261
4262 /* Emit one vertex from the geometry shader */
4263 static void si_tgsi_emit_vertex(
4264 const struct lp_build_tgsi_action *action,
4265 struct lp_build_tgsi_context *bld_base,
4266 struct lp_build_emit_data *emit_data)
4267 {
4268 struct si_shader_context *ctx = si_shader_context(bld_base);
4269 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4270
4271 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4272 }
4273
4274 /* Cut one primitive from the geometry shader */
4275 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4276 unsigned stream)
4277 {
4278 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4279
4280 /* Signal primitive cut */
4281 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4282 si_get_gs_wave_id(ctx));
4283 }
4284
4285 /* Cut one primitive from the geometry shader */
4286 static void si_tgsi_emit_primitive(
4287 const struct lp_build_tgsi_action *action,
4288 struct lp_build_tgsi_context *bld_base,
4289 struct lp_build_emit_data *emit_data)
4290 {
4291 struct si_shader_context *ctx = si_shader_context(bld_base);
4292
4293 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4294 }
4295
4296 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4297 struct lp_build_tgsi_context *bld_base,
4298 struct lp_build_emit_data *emit_data)
4299 {
4300 struct si_shader_context *ctx = si_shader_context(bld_base);
4301
4302 /* GFX6 only (thanks to a hw bug workaround):
4303 * The real barrier instruction isn’t needed, because an entire patch
4304 * always fits into a single wave.
4305 */
4306 if (ctx->screen->info.chip_class == GFX6 &&
4307 ctx->type == PIPE_SHADER_TESS_CTRL) {
4308 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4309 return;
4310 }
4311
4312 ac_build_s_barrier(&ctx->ac);
4313 }
4314
4315 void si_create_function(struct si_shader_context *ctx,
4316 const char *name,
4317 LLVMTypeRef *returns, unsigned num_returns,
4318 struct si_function_info *fninfo,
4319 unsigned max_workgroup_size)
4320 {
4321 int i;
4322
4323 si_llvm_create_func(ctx, name, returns, num_returns,
4324 fninfo->types, fninfo->num_params);
4325 ctx->return_value = LLVMGetUndef(ctx->return_type);
4326
4327 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4328 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4329
4330 /* The combination of:
4331 * - noalias
4332 * - dereferenceable
4333 * - invariant.load
4334 * allows the optimization passes to move loads and reduces
4335 * SGPR spilling significantly.
4336 */
4337 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4338 AC_FUNC_ATTR_INREG);
4339
4340 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4341 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4342 AC_FUNC_ATTR_NOALIAS);
4343 ac_add_attr_dereferenceable(P, UINT64_MAX);
4344 }
4345 }
4346
4347 for (i = 0; i < fninfo->num_params; ++i) {
4348 if (fninfo->assign[i])
4349 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4350 }
4351
4352 if (ctx->screen->info.address32_hi) {
4353 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4354 "amdgpu-32bit-address-high-bits",
4355 ctx->screen->info.address32_hi);
4356 }
4357
4358 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4359
4360 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4361 "no-signed-zeros-fp-math",
4362 "true");
4363
4364 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4365 /* These were copied from some LLVM test. */
4366 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4367 "less-precise-fpmad",
4368 "true");
4369 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4370 "no-infs-fp-math",
4371 "true");
4372 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4373 "no-nans-fp-math",
4374 "true");
4375 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4376 "unsafe-fp-math",
4377 "true");
4378 }
4379 }
4380
4381 static void declare_streamout_params(struct si_shader_context *ctx,
4382 struct pipe_stream_output_info *so,
4383 struct si_function_info *fninfo)
4384 {
4385 int i;
4386
4387 /* Streamout SGPRs. */
4388 if (so->num_outputs) {
4389 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4390 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4391 else
4392 ctx->param_streamout_config = fninfo->num_params - 1;
4393
4394 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4395 }
4396 /* A streamout buffer offset is loaded if the stride is non-zero. */
4397 for (i = 0; i < 4; i++) {
4398 if (!so->stride[i])
4399 continue;
4400
4401 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4402 }
4403 }
4404
4405 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4406 {
4407 switch (shader->selector->type) {
4408 case PIPE_SHADER_TESS_CTRL:
4409 /* Return this so that LLVM doesn't remove s_barrier
4410 * instructions on chips where we use s_barrier. */
4411 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 64;
4412
4413 case PIPE_SHADER_GEOMETRY:
4414 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4415
4416 case PIPE_SHADER_COMPUTE:
4417 break; /* see below */
4418
4419 default:
4420 return 0;
4421 }
4422
4423 const unsigned *properties = shader->selector->info.properties;
4424 unsigned max_work_group_size =
4425 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4426 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4427 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4428
4429 if (!max_work_group_size) {
4430 /* This is a variable group size compute shader,
4431 * compile it for the maximum possible group size.
4432 */
4433 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4434 }
4435 return max_work_group_size;
4436 }
4437
4438 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4439 struct si_function_info *fninfo,
4440 bool assign_params)
4441 {
4442 LLVMTypeRef const_shader_buf_type;
4443
4444 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4445 ctx->shader->selector->info.shader_buffers_declared == 0)
4446 const_shader_buf_type = ctx->f32;
4447 else
4448 const_shader_buf_type = ctx->v4i32;
4449
4450 unsigned const_and_shader_buffers =
4451 add_arg(fninfo, ARG_SGPR,
4452 ac_array_in_const32_addr_space(const_shader_buf_type));
4453
4454 if (assign_params)
4455 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4456 }
4457
4458 static void declare_samplers_and_images(struct si_shader_context *ctx,
4459 struct si_function_info *fninfo,
4460 bool assign_params)
4461 {
4462 unsigned samplers_and_images =
4463 add_arg(fninfo, ARG_SGPR,
4464 ac_array_in_const32_addr_space(ctx->v8i32));
4465
4466 if (assign_params)
4467 ctx->param_samplers_and_images = samplers_and_images;
4468 }
4469
4470 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4471 struct si_function_info *fninfo,
4472 bool assign_params)
4473 {
4474 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4475 declare_samplers_and_images(ctx, fninfo, assign_params);
4476 }
4477
4478 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4479 struct si_function_info *fninfo)
4480 {
4481 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4482 ac_array_in_const32_addr_space(ctx->v4i32));
4483 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4484 ac_array_in_const32_addr_space(ctx->v8i32));
4485 }
4486
4487 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4488 struct si_function_info *fninfo)
4489 {
4490 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4491 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4492 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4493 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4494 }
4495
4496 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4497 struct si_function_info *fninfo,
4498 unsigned *num_prolog_vgprs)
4499 {
4500 struct si_shader *shader = ctx->shader;
4501
4502 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4503 if (shader->key.as_ls) {
4504 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4505 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4506 } else {
4507 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4508 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4509 }
4510 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4511
4512 if (!shader->is_gs_copy_shader) {
4513 /* Vertex load indices. */
4514 ctx->param_vertex_index0 = fninfo->num_params;
4515 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4516 add_arg(fninfo, ARG_VGPR, ctx->i32);
4517 *num_prolog_vgprs += shader->selector->info.num_inputs;
4518 }
4519 }
4520
4521 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4522 struct si_function_info *fninfo,
4523 unsigned vs_blit_property)
4524 {
4525 ctx->param_vs_blit_inputs = fninfo->num_params;
4526 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4527 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4528 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4529
4530 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4531 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4532 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4533 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4534 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4535 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4536 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4537 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4538 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4539 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4540 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4541 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4542 }
4543 }
4544
4545 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4546 struct si_function_info *fninfo)
4547 {
4548 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4549 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4550 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4551 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4552 }
4553
4554 enum {
4555 /* Convenient merged shader definitions. */
4556 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4557 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4558 };
4559
4560 static void create_function(struct si_shader_context *ctx)
4561 {
4562 struct si_shader *shader = ctx->shader;
4563 struct si_function_info fninfo;
4564 LLVMTypeRef returns[16+32*4];
4565 unsigned i, num_return_sgprs;
4566 unsigned num_returns = 0;
4567 unsigned num_prolog_vgprs = 0;
4568 unsigned type = ctx->type;
4569 unsigned vs_blit_property =
4570 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4571
4572 si_init_function_info(&fninfo);
4573
4574 /* Set MERGED shaders. */
4575 if (ctx->screen->info.chip_class >= GFX9) {
4576 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4577 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4578 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4579 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4580 }
4581
4582 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4583
4584 switch (type) {
4585 case PIPE_SHADER_VERTEX:
4586 declare_global_desc_pointers(ctx, &fninfo);
4587
4588 if (vs_blit_property) {
4589 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4590
4591 /* VGPRs */
4592 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4593 break;
4594 }
4595
4596 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4597 declare_vs_specific_input_sgprs(ctx, &fninfo);
4598 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4599 ac_array_in_const32_addr_space(ctx->v4i32));
4600
4601 if (shader->key.as_es) {
4602 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4603 } else if (shader->key.as_ls) {
4604 /* no extra parameters */
4605 } else {
4606 if (shader->is_gs_copy_shader) {
4607 fninfo.num_params = ctx->param_vs_state_bits + 1;
4608 fninfo.num_sgpr_params = fninfo.num_params;
4609 }
4610
4611 /* The locations of the other parameters are assigned dynamically. */
4612 declare_streamout_params(ctx, &shader->selector->so,
4613 &fninfo);
4614 }
4615
4616 /* VGPRs */
4617 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4618
4619 /* Return values */
4620 if (shader->key.opt.vs_as_prim_discard_cs) {
4621 for (i = 0; i < 4; i++)
4622 returns[num_returns++] = ctx->f32; /* VGPRs */
4623 }
4624 break;
4625
4626 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4627 declare_global_desc_pointers(ctx, &fninfo);
4628 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4629 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4630 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4631 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4632 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4633 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4634 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4635
4636 /* VGPRs */
4637 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4638 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4639
4640 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4641 * placed after the user SGPRs.
4642 */
4643 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4644 returns[num_returns++] = ctx->i32; /* SGPRs */
4645 for (i = 0; i < 11; i++)
4646 returns[num_returns++] = ctx->f32; /* VGPRs */
4647 break;
4648
4649 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4650 /* Merged stages have 8 system SGPRs at the beginning. */
4651 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4652 declare_per_stage_desc_pointers(ctx, &fninfo,
4653 ctx->type == PIPE_SHADER_TESS_CTRL);
4654 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4655 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4656 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4657 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4658 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4659 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4660
4661 declare_global_desc_pointers(ctx, &fninfo);
4662 declare_per_stage_desc_pointers(ctx, &fninfo,
4663 ctx->type == PIPE_SHADER_VERTEX);
4664 declare_vs_specific_input_sgprs(ctx, &fninfo);
4665
4666 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4667 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4668 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4669 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4670 ac_array_in_const32_addr_space(ctx->v4i32));
4671
4672 /* VGPRs (first TCS, then VS) */
4673 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4674 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4675
4676 if (ctx->type == PIPE_SHADER_VERTEX) {
4677 declare_vs_input_vgprs(ctx, &fninfo,
4678 &num_prolog_vgprs);
4679
4680 /* LS return values are inputs to the TCS main shader part. */
4681 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4682 returns[num_returns++] = ctx->i32; /* SGPRs */
4683 for (i = 0; i < 2; i++)
4684 returns[num_returns++] = ctx->f32; /* VGPRs */
4685 } else {
4686 /* TCS return values are inputs to the TCS epilog.
4687 *
4688 * param_tcs_offchip_offset, param_tcs_factor_offset,
4689 * param_tcs_offchip_layout, and param_rw_buffers
4690 * should be passed to the epilog.
4691 */
4692 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4693 returns[num_returns++] = ctx->i32; /* SGPRs */
4694 for (i = 0; i < 11; i++)
4695 returns[num_returns++] = ctx->f32; /* VGPRs */
4696 }
4697 break;
4698
4699 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4700 /* Merged stages have 8 system SGPRs at the beginning. */
4701 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4702 declare_per_stage_desc_pointers(ctx, &fninfo,
4703 ctx->type == PIPE_SHADER_GEOMETRY);
4704 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4705 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4706 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4707 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4708 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4709 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4710
4711 declare_global_desc_pointers(ctx, &fninfo);
4712 declare_per_stage_desc_pointers(ctx, &fninfo,
4713 (ctx->type == PIPE_SHADER_VERTEX ||
4714 ctx->type == PIPE_SHADER_TESS_EVAL));
4715 if (ctx->type == PIPE_SHADER_VERTEX) {
4716 declare_vs_specific_input_sgprs(ctx, &fninfo);
4717 } else {
4718 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4719 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4720 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 /* Declare as many input SGPRs as the VS has. */
4722 }
4723
4724 if (ctx->type == PIPE_SHADER_VERTEX) {
4725 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4726 ac_array_in_const32_addr_space(ctx->v4i32));
4727 }
4728
4729 /* VGPRs (first GS, then VS/TES) */
4730 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4731 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4732 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4733 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4734 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4735
4736 if (ctx->type == PIPE_SHADER_VERTEX) {
4737 declare_vs_input_vgprs(ctx, &fninfo,
4738 &num_prolog_vgprs);
4739 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4740 declare_tes_input_vgprs(ctx, &fninfo);
4741 }
4742
4743 if (ctx->type == PIPE_SHADER_VERTEX ||
4744 ctx->type == PIPE_SHADER_TESS_EVAL) {
4745 unsigned num_user_sgprs;
4746
4747 if (ctx->type == PIPE_SHADER_VERTEX)
4748 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4749 else
4750 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4751
4752 /* ES return values are inputs to GS. */
4753 for (i = 0; i < 8 + num_user_sgprs; i++)
4754 returns[num_returns++] = ctx->i32; /* SGPRs */
4755 for (i = 0; i < 5; i++)
4756 returns[num_returns++] = ctx->f32; /* VGPRs */
4757 }
4758 break;
4759
4760 case PIPE_SHADER_TESS_EVAL:
4761 declare_global_desc_pointers(ctx, &fninfo);
4762 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4763 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4764 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4765 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4766
4767 if (shader->key.as_es) {
4768 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4769 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4770 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4771 } else {
4772 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4773 declare_streamout_params(ctx, &shader->selector->so,
4774 &fninfo);
4775 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776 }
4777
4778 /* VGPRs */
4779 declare_tes_input_vgprs(ctx, &fninfo);
4780 break;
4781
4782 case PIPE_SHADER_GEOMETRY:
4783 declare_global_desc_pointers(ctx, &fninfo);
4784 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4785 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4786 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4787
4788 /* VGPRs */
4789 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4790 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4791 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4792 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4793 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4794 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4795 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4796 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4797 break;
4798
4799 case PIPE_SHADER_FRAGMENT:
4800 declare_global_desc_pointers(ctx, &fninfo);
4801 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4802 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4803 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4804 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4805
4806 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4807 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4808 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4809 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4810 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4811 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4812 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4813 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4814 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4815 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4816 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4817 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4818 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4819 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4820 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4821 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4822 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4823 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4824 shader->info.face_vgpr_index = 20;
4825 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4826 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4827 shader->info.ancillary_vgpr_index = 21;
4828 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4829 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4830 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4831
4832 /* Color inputs from the prolog. */
4833 if (shader->selector->info.colors_read) {
4834 unsigned num_color_elements =
4835 util_bitcount(shader->selector->info.colors_read);
4836
4837 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4838 for (i = 0; i < num_color_elements; i++)
4839 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4840
4841 num_prolog_vgprs += num_color_elements;
4842 }
4843
4844 /* Outputs for the epilog. */
4845 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4846 num_returns =
4847 num_return_sgprs +
4848 util_bitcount(shader->selector->info.colors_written) * 4 +
4849 shader->selector->info.writes_z +
4850 shader->selector->info.writes_stencil +
4851 shader->selector->info.writes_samplemask +
4852 1 /* SampleMaskIn */;
4853
4854 num_returns = MAX2(num_returns,
4855 num_return_sgprs +
4856 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4857
4858 for (i = 0; i < num_return_sgprs; i++)
4859 returns[i] = ctx->i32;
4860 for (; i < num_returns; i++)
4861 returns[i] = ctx->f32;
4862 break;
4863
4864 case PIPE_SHADER_COMPUTE:
4865 declare_global_desc_pointers(ctx, &fninfo);
4866 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4867 if (shader->selector->info.uses_grid_size)
4868 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4869 if (shader->selector->info.uses_block_size &&
4870 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4871 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4872
4873 unsigned cs_user_data_dwords =
4874 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4875 if (cs_user_data_dwords) {
4876 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4877 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4878 }
4879
4880 for (i = 0; i < 3; i++) {
4881 ctx->abi.workgroup_ids[i] = NULL;
4882 if (shader->selector->info.uses_block_id[i])
4883 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4884 }
4885
4886 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4887 break;
4888 default:
4889 assert(0 && "unimplemented shader");
4890 return;
4891 }
4892
4893 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4894 si_get_max_workgroup_size(shader));
4895
4896 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4897 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4898 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4899 "InitialPSInputAddr",
4900 S_0286D0_PERSP_SAMPLE_ENA(1) |
4901 S_0286D0_PERSP_CENTER_ENA(1) |
4902 S_0286D0_PERSP_CENTROID_ENA(1) |
4903 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4904 S_0286D0_LINEAR_CENTER_ENA(1) |
4905 S_0286D0_LINEAR_CENTROID_ENA(1) |
4906 S_0286D0_FRONT_FACE_ENA(1) |
4907 S_0286D0_ANCILLARY_ENA(1) |
4908 S_0286D0_POS_FIXED_PT_ENA(1));
4909 }
4910
4911 shader->info.num_input_sgprs = 0;
4912 shader->info.num_input_vgprs = 0;
4913
4914 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4915 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4916
4917 for (; i < fninfo.num_params; ++i)
4918 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4919
4920 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4921 shader->info.num_input_vgprs -= num_prolog_vgprs;
4922
4923 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
4924 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
4925 /* The LSHS size is not known until draw time, so we append it
4926 * at the end of whatever LDS use there may be in the rest of
4927 * the shader (currently none, unless LLVM decides to do its
4928 * own LDS-based lowering).
4929 */
4930 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
4931 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
4932 "__lds_end", AC_ADDR_SPACE_LDS);
4933 LLVMSetAlignment(ctx->ac.lds, 256);
4934 } else {
4935 ac_declare_lds_as_pointer(&ctx->ac);
4936 }
4937 }
4938 }
4939
4940 /**
4941 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4942 * for later use.
4943 */
4944 static void preload_ring_buffers(struct si_shader_context *ctx)
4945 {
4946 LLVMBuilderRef builder = ctx->ac.builder;
4947
4948 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4949 ctx->param_rw_buffers);
4950
4951 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
4952 if (ctx->screen->info.chip_class <= GFX8) {
4953 unsigned ring =
4954 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4955 : SI_ES_RING_ESGS;
4956 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4957
4958 ctx->esgs_ring =
4959 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4960 } else {
4961 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
4962 /* Declare the ESGS ring as an explicit LDS symbol.
4963 * For monolithic shaders, we declare the ring only once.
4964 *
4965 * We declare it with 64KB alignment as a hint that the
4966 * pointer value will always be 0.
4967 */
4968 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4969 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
4970 "esgs_ring",
4971 AC_ADDR_SPACE_LDS);
4972 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4973 } else {
4974 ac_declare_lds_as_pointer(&ctx->ac);
4975 ctx->esgs_ring = ctx->ac.lds;
4976 }
4977 }
4978 }
4979
4980 if (ctx->shader->is_gs_copy_shader) {
4981 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4982
4983 ctx->gsvs_ring[0] =
4984 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4985 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4986 const struct si_shader_selector *sel = ctx->shader->selector;
4987 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4988 LLVMValueRef base_ring;
4989
4990 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4991
4992 /* The conceptual layout of the GSVS ring is
4993 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4994 * but the real memory layout is swizzled across
4995 * threads:
4996 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4997 * t16v0c0 ..
4998 * Override the buffer descriptor accordingly.
4999 */
5000 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5001 uint64_t stream_offset = 0;
5002
5003 for (unsigned stream = 0; stream < 4; ++stream) {
5004 unsigned num_components;
5005 unsigned stride;
5006 unsigned num_records;
5007 LLVMValueRef ring, tmp;
5008
5009 num_components = sel->info.num_stream_output_components[stream];
5010 if (!num_components)
5011 continue;
5012
5013 stride = 4 * num_components * sel->gs_max_out_vertices;
5014
5015 /* Limit on the stride field for <= GFX7. */
5016 assert(stride < (1 << 14));
5017
5018 num_records = 64;
5019
5020 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5021 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5022 tmp = LLVMBuildAdd(builder, tmp,
5023 LLVMConstInt(ctx->i64,
5024 stream_offset, 0), "");
5025 stream_offset += stride * 64;
5026
5027 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5028 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5029 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5030 tmp = LLVMBuildOr(builder, tmp,
5031 LLVMConstInt(ctx->i32,
5032 S_008F04_STRIDE(stride) |
5033 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5034 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5035 ring = LLVMBuildInsertElement(builder, ring,
5036 LLVMConstInt(ctx->i32, num_records, 0),
5037 LLVMConstInt(ctx->i32, 2, 0), "");
5038 ring = LLVMBuildInsertElement(builder, ring,
5039 LLVMConstInt(ctx->i32,
5040 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5041 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5042 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5043 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5044 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5045 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5046 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5047 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5048 S_008F0C_ADD_TID_ENABLE(1),
5049 0),
5050 LLVMConstInt(ctx->i32, 3, 0), "");
5051
5052 ctx->gsvs_ring[stream] = ring;
5053 }
5054 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5055 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5056 }
5057 }
5058
5059 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5060 LLVMValueRef param_rw_buffers,
5061 unsigned param_pos_fixed_pt)
5062 {
5063 LLVMBuilderRef builder = ctx->ac.builder;
5064 LLVMValueRef slot, desc, offset, row, bit, address[2];
5065
5066 /* Use the fixed-point gl_FragCoord input.
5067 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5068 * per coordinate to get the repeating effect.
5069 */
5070 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5071 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5072
5073 /* Load the buffer descriptor. */
5074 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5075 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5076
5077 /* The stipple pattern is 32x32, each row has 32 bits. */
5078 offset = LLVMBuildMul(builder, address[1],
5079 LLVMConstInt(ctx->i32, 4, 0), "");
5080 row = buffer_load_const(ctx, desc, offset);
5081 row = ac_to_integer(&ctx->ac, row);
5082 bit = LLVMBuildLShr(builder, row, address[0], "");
5083 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5084 ac_build_kill_if_false(&ctx->ac, bit);
5085 }
5086
5087 /* For the UMR disassembler. */
5088 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5089 #define DEBUGGER_NUM_MARKERS 5
5090
5091 static bool si_shader_binary_open(struct si_screen *screen,
5092 struct si_shader *shader,
5093 struct ac_rtld_binary *rtld)
5094 {
5095 const struct si_shader_selector *sel = shader->selector;
5096 enum pipe_shader_type shader_type = sel ? sel->type : PIPE_SHADER_COMPUTE;
5097 const char *part_elfs[5];
5098 size_t part_sizes[5];
5099 unsigned num_parts = 0;
5100
5101 #define add_part(shader_or_part) \
5102 if (shader_or_part) { \
5103 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5104 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5105 num_parts++; \
5106 }
5107
5108 add_part(shader->prolog);
5109 add_part(shader->previous_stage);
5110 add_part(shader->prolog2);
5111 add_part(shader);
5112 add_part(shader->epilog);
5113
5114 #undef add_part
5115
5116 struct ac_rtld_symbol lds_symbols[1];
5117 unsigned num_lds_symbols = 0;
5118
5119 if (sel && screen->info.chip_class >= GFX9 &&
5120 sel->type == PIPE_SHADER_GEOMETRY && !shader->is_gs_copy_shader) {
5121 /* We add this symbol even on LLVM <= 8 to ensure that
5122 * shader->config.lds_size is set correctly below.
5123 */
5124 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5125 sym->name = "esgs_ring";
5126 sym->size = shader->gs_info.esgs_ring_size;
5127 sym->align = 64 * 1024;
5128 }
5129
5130 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
5131 .info = &screen->info,
5132 .options = {
5133 .halt_at_entry = screen->options.halt_shaders,
5134 },
5135 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5136 .num_parts = num_parts,
5137 .elf_ptrs = part_elfs,
5138 .elf_sizes = part_sizes,
5139 .num_shared_lds_symbols = num_lds_symbols,
5140 .shared_lds_symbols = lds_symbols });
5141
5142 if (rtld->lds_size > 0) {
5143 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
5144 shader->config.lds_size =
5145 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
5146 }
5147
5148 return ok;
5149 }
5150
5151 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
5152 {
5153 struct ac_rtld_binary rtld;
5154 si_shader_binary_open(screen, shader, &rtld);
5155 return rtld.rx_size;
5156 }
5157
5158
5159 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
5160 {
5161 uint64_t *scratch_va = data;
5162
5163 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
5164 *value = (uint32_t)*scratch_va;
5165 return true;
5166 }
5167 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
5168 /* Enable scratch coalescing. */
5169 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
5170 S_008F04_SWIZZLE_ENABLE(1);
5171 if (HAVE_LLVM < 0x0800) {
5172 /* Old LLVM created an R_ABS32_HI relocation for
5173 * this symbol. */
5174 *value <<= 32;
5175 }
5176 return true;
5177 }
5178
5179 return false;
5180 }
5181
5182 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
5183 uint64_t scratch_va)
5184 {
5185 struct ac_rtld_binary binary;
5186 if (!si_shader_binary_open(sscreen, shader, &binary))
5187 return false;
5188
5189 si_resource_reference(&shader->bo, NULL);
5190 shader->bo = si_aligned_buffer_create(&sscreen->b,
5191 sscreen->cpdma_prefetch_writes_memory ?
5192 0 : SI_RESOURCE_FLAG_READ_ONLY,
5193 PIPE_USAGE_IMMUTABLE,
5194 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
5195 256);
5196 if (!shader->bo)
5197 return false;
5198
5199 /* Upload. */
5200 struct ac_rtld_upload_info u = {};
5201 u.binary = &binary;
5202 u.get_external_symbol = si_get_external_symbol;
5203 u.cb_data = &scratch_va;
5204 u.rx_va = shader->bo->gpu_address;
5205 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5206 PIPE_TRANSFER_READ_WRITE |
5207 PIPE_TRANSFER_UNSYNCHRONIZED |
5208 RADEON_TRANSFER_TEMPORARY);
5209 if (!u.rx_ptr)
5210 return false;
5211
5212 bool ok = ac_rtld_upload(&u);
5213
5214 sscreen->ws->buffer_unmap(shader->bo->buf);
5215 ac_rtld_close(&binary);
5216
5217 return ok;
5218 }
5219
5220 static void si_shader_dump_disassembly(struct si_screen *screen,
5221 const struct si_shader_binary *binary,
5222 struct pipe_debug_callback *debug,
5223 const char *name, FILE *file)
5224 {
5225 struct ac_rtld_binary rtld_binary;
5226
5227 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
5228 .info = &screen->info,
5229 .num_parts = 1,
5230 .elf_ptrs = &binary->elf_buffer,
5231 .elf_sizes = &binary->elf_size }))
5232 return;
5233
5234 const char *disasm;
5235 size_t nbytes;
5236
5237 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
5238 goto out;
5239
5240 if (nbytes > INT_MAX)
5241 goto out;
5242
5243 if (debug && debug->debug_message) {
5244 /* Very long debug messages are cut off, so send the
5245 * disassembly one line at a time. This causes more
5246 * overhead, but on the plus side it simplifies
5247 * parsing of resulting logs.
5248 */
5249 pipe_debug_message(debug, SHADER_INFO,
5250 "Shader Disassembly Begin");
5251
5252 uint64_t line = 0;
5253 while (line < nbytes) {
5254 int count = nbytes - line;
5255 const char *nl = memchr(disasm + line, '\n', nbytes - line);
5256 if (nl)
5257 count = nl - (disasm + line);
5258
5259 if (count) {
5260 pipe_debug_message(debug, SHADER_INFO,
5261 "%.*s", count, disasm + line);
5262 }
5263
5264 line += count + 1;
5265 }
5266
5267 pipe_debug_message(debug, SHADER_INFO,
5268 "Shader Disassembly End");
5269 }
5270
5271 if (file) {
5272 fprintf(file, "Shader %s disassembly:\n", name);
5273 fprintf(file, "%*s", (int)nbytes, disasm);
5274 }
5275
5276 out:
5277 ac_rtld_close(&rtld_binary);
5278 }
5279
5280 static void si_calculate_max_simd_waves(struct si_shader *shader)
5281 {
5282 struct si_screen *sscreen = shader->selector->screen;
5283 struct ac_shader_config *conf = &shader->config;
5284 unsigned num_inputs = shader->selector->info.num_inputs;
5285 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5286 unsigned lds_per_wave = 0;
5287 unsigned max_simd_waves;
5288
5289 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5290
5291 /* Compute LDS usage for PS. */
5292 switch (shader->selector->type) {
5293 case PIPE_SHADER_FRAGMENT:
5294 /* The minimum usage per wave is (num_inputs * 48). The maximum
5295 * usage is (num_inputs * 48 * 16).
5296 * We can get anything in between and it varies between waves.
5297 *
5298 * The 48 bytes per input for a single primitive is equal to
5299 * 4 bytes/component * 4 components/input * 3 points.
5300 *
5301 * Other stages don't know the size at compile time or don't
5302 * allocate LDS per wave, but instead they do it per thread group.
5303 */
5304 lds_per_wave = conf->lds_size * lds_increment +
5305 align(num_inputs * 48, lds_increment);
5306 break;
5307 case PIPE_SHADER_COMPUTE:
5308 if (shader->selector) {
5309 unsigned max_workgroup_size =
5310 si_get_max_workgroup_size(shader);
5311 lds_per_wave = (conf->lds_size * lds_increment) /
5312 DIV_ROUND_UP(max_workgroup_size, 64);
5313 }
5314 break;
5315 }
5316
5317 /* Compute the per-SIMD wave counts. */
5318 if (conf->num_sgprs) {
5319 max_simd_waves =
5320 MIN2(max_simd_waves,
5321 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5322 }
5323
5324 if (conf->num_vgprs)
5325 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5326
5327 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5328 * 16KB makes some SIMDs unoccupied). */
5329 if (lds_per_wave)
5330 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5331
5332 shader->info.max_simd_waves = max_simd_waves;
5333 }
5334
5335 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
5336 struct si_shader *shader,
5337 struct pipe_debug_callback *debug)
5338 {
5339 const struct ac_shader_config *conf = &shader->config;
5340
5341 if (screen->options.debug_disassembly)
5342 si_shader_dump_disassembly(screen, &shader->binary, debug, "main", NULL);
5343
5344 pipe_debug_message(debug, SHADER_INFO,
5345 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5346 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5347 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5348 conf->num_sgprs, conf->num_vgprs,
5349 si_get_shader_binary_size(screen, shader),
5350 conf->lds_size, conf->scratch_bytes_per_wave,
5351 shader->info.max_simd_waves, conf->spilled_sgprs,
5352 conf->spilled_vgprs, shader->info.private_mem_vgprs);
5353 }
5354
5355 static void si_shader_dump_stats(struct si_screen *sscreen,
5356 struct si_shader *shader,
5357 unsigned processor,
5358 FILE *file,
5359 bool check_debug_option)
5360 {
5361 const struct ac_shader_config *conf = &shader->config;
5362
5363 if (!check_debug_option ||
5364 si_can_dump_shader(sscreen, processor)) {
5365 if (processor == PIPE_SHADER_FRAGMENT) {
5366 fprintf(file, "*** SHADER CONFIG ***\n"
5367 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5368 "SPI_PS_INPUT_ENA = 0x%04x\n",
5369 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5370 }
5371
5372 fprintf(file, "*** SHADER STATS ***\n"
5373 "SGPRS: %d\n"
5374 "VGPRS: %d\n"
5375 "Spilled SGPRs: %d\n"
5376 "Spilled VGPRs: %d\n"
5377 "Private memory VGPRs: %d\n"
5378 "Code Size: %d bytes\n"
5379 "LDS: %d blocks\n"
5380 "Scratch: %d bytes per wave\n"
5381 "Max Waves: %d\n"
5382 "********************\n\n\n",
5383 conf->num_sgprs, conf->num_vgprs,
5384 conf->spilled_sgprs, conf->spilled_vgprs,
5385 shader->info.private_mem_vgprs,
5386 si_get_shader_binary_size(sscreen, shader),
5387 conf->lds_size, conf->scratch_bytes_per_wave,
5388 shader->info.max_simd_waves);
5389 }
5390 }
5391
5392 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5393 {
5394 switch (processor) {
5395 case PIPE_SHADER_VERTEX:
5396 if (shader->key.as_es)
5397 return "Vertex Shader as ES";
5398 else if (shader->key.as_ls)
5399 return "Vertex Shader as LS";
5400 else if (shader->key.opt.vs_as_prim_discard_cs)
5401 return "Vertex Shader as Primitive Discard CS";
5402 else if (shader->key.as_ngg)
5403 return "Vertex Shader as ESGS";
5404 else
5405 return "Vertex Shader as VS";
5406 case PIPE_SHADER_TESS_CTRL:
5407 return "Tessellation Control Shader";
5408 case PIPE_SHADER_TESS_EVAL:
5409 if (shader->key.as_es)
5410 return "Tessellation Evaluation Shader as ES";
5411 else if (shader->key.as_ngg)
5412 return "Tessellation Evaluation Shader as ESGS";
5413 else
5414 return "Tessellation Evaluation Shader as VS";
5415 case PIPE_SHADER_GEOMETRY:
5416 if (shader->is_gs_copy_shader)
5417 return "GS Copy Shader as VS";
5418 else
5419 return "Geometry Shader";
5420 case PIPE_SHADER_FRAGMENT:
5421 return "Pixel Shader";
5422 case PIPE_SHADER_COMPUTE:
5423 return "Compute Shader";
5424 default:
5425 return "Unknown Shader";
5426 }
5427 }
5428
5429 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5430 struct pipe_debug_callback *debug, unsigned processor,
5431 FILE *file, bool check_debug_option)
5432 {
5433 if (!check_debug_option ||
5434 si_can_dump_shader(sscreen, processor))
5435 si_dump_shader_key(processor, shader, file);
5436
5437 if (!check_debug_option && shader->binary.llvm_ir_string) {
5438 if (shader->previous_stage &&
5439 shader->previous_stage->binary.llvm_ir_string) {
5440 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5441 si_get_shader_name(shader, processor));
5442 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5443 }
5444
5445 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5446 si_get_shader_name(shader, processor));
5447 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5448 }
5449
5450 if (!check_debug_option ||
5451 (si_can_dump_shader(sscreen, processor) &&
5452 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5453 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5454
5455 if (shader->prolog)
5456 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
5457 debug, "prolog", file);
5458 if (shader->previous_stage)
5459 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
5460 debug, "previous stage", file);
5461 if (shader->prolog2)
5462 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
5463 debug, "prolog2", file);
5464
5465 si_shader_dump_disassembly(sscreen, &shader->binary, debug, "main", file);
5466
5467 if (shader->epilog)
5468 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
5469 debug, "epilog", file);
5470 fprintf(file, "\n");
5471 }
5472
5473 si_shader_dump_stats(sscreen, shader, processor, file,
5474 check_debug_option);
5475 }
5476
5477 static int si_compile_llvm(struct si_screen *sscreen,
5478 struct si_shader_binary *binary,
5479 struct ac_shader_config *conf,
5480 struct ac_llvm_compiler *compiler,
5481 LLVMModuleRef mod,
5482 struct pipe_debug_callback *debug,
5483 unsigned processor,
5484 const char *name,
5485 bool less_optimized)
5486 {
5487 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5488
5489 if (si_can_dump_shader(sscreen, processor)) {
5490 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5491
5492 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5493 fprintf(stderr, "%s LLVM IR:\n\n", name);
5494 ac_dump_module(mod);
5495 fprintf(stderr, "\n");
5496 }
5497 }
5498
5499 if (sscreen->record_llvm_ir) {
5500 char *ir = LLVMPrintModuleToString(mod);
5501 binary->llvm_ir_string = strdup(ir);
5502 LLVMDisposeMessage(ir);
5503 }
5504
5505 if (!si_replace_shader(count, binary)) {
5506 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
5507 less_optimized);
5508 if (r)
5509 return r;
5510 }
5511
5512 struct ac_rtld_binary rtld;
5513 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
5514 .info = &sscreen->info,
5515 .num_parts = 1,
5516 .elf_ptrs = &binary->elf_buffer,
5517 .elf_sizes = &binary->elf_size }))
5518 return -1;
5519
5520 bool ok = ac_rtld_read_config(&rtld, conf);
5521 ac_rtld_close(&rtld);
5522 if (!ok)
5523 return -1;
5524
5525 /* Enable 64-bit and 16-bit denormals, because there is no performance
5526 * cost.
5527 *
5528 * If denormals are enabled, all floating-point output modifiers are
5529 * ignored.
5530 *
5531 * Don't enable denormals for 32-bit floats, because:
5532 * - Floating-point output modifiers would be ignored by the hw.
5533 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5534 * have to stop using those.
5535 * - GFX6 & GFX7 would be very slow.
5536 */
5537 conf->float_mode |= V_00B028_FP_64_DENORMS;
5538
5539 return 0;
5540 }
5541
5542 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5543 {
5544 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5545 LLVMBuildRetVoid(ctx->ac.builder);
5546 else
5547 LLVMBuildRet(ctx->ac.builder, ret);
5548 }
5549
5550 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5551 struct si_shader *
5552 si_generate_gs_copy_shader(struct si_screen *sscreen,
5553 struct ac_llvm_compiler *compiler,
5554 struct si_shader_selector *gs_selector,
5555 struct pipe_debug_callback *debug)
5556 {
5557 struct si_shader_context ctx;
5558 struct si_shader *shader;
5559 LLVMBuilderRef builder;
5560 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5561 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5562 int i;
5563
5564
5565 shader = CALLOC_STRUCT(si_shader);
5566 if (!shader)
5567 return NULL;
5568
5569 /* We can leave the fence as permanently signaled because the GS copy
5570 * shader only becomes visible globally after it has been compiled. */
5571 util_queue_fence_init(&shader->ready);
5572
5573 shader->selector = gs_selector;
5574 shader->is_gs_copy_shader = true;
5575
5576 si_init_shader_ctx(&ctx, sscreen, compiler);
5577 ctx.shader = shader;
5578 ctx.type = PIPE_SHADER_VERTEX;
5579
5580 builder = ctx.ac.builder;
5581
5582 create_function(&ctx);
5583 preload_ring_buffers(&ctx);
5584
5585 LLVMValueRef voffset =
5586 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5587 LLVMConstInt(ctx.i32, 4, 0), "");
5588
5589 /* Fetch the vertex stream ID.*/
5590 LLVMValueRef stream_id;
5591
5592 if (gs_selector->so.num_outputs)
5593 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5594 else
5595 stream_id = ctx.i32_0;
5596
5597 /* Fill in output information. */
5598 for (i = 0; i < gsinfo->num_outputs; ++i) {
5599 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5600 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5601
5602 for (int chan = 0; chan < 4; chan++) {
5603 outputs[i].vertex_stream[chan] =
5604 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5605 }
5606 }
5607
5608 LLVMBasicBlockRef end_bb;
5609 LLVMValueRef switch_inst;
5610
5611 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5612 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5613
5614 for (int stream = 0; stream < 4; stream++) {
5615 LLVMBasicBlockRef bb;
5616 unsigned offset;
5617
5618 if (!gsinfo->num_stream_output_components[stream])
5619 continue;
5620
5621 if (stream > 0 && !gs_selector->so.num_outputs)
5622 continue;
5623
5624 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5625 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5626 LLVMPositionBuilderAtEnd(builder, bb);
5627
5628 /* Fetch vertex data from GSVS ring */
5629 offset = 0;
5630 for (i = 0; i < gsinfo->num_outputs; ++i) {
5631 for (unsigned chan = 0; chan < 4; chan++) {
5632 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5633 outputs[i].vertex_stream[chan] != stream) {
5634 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5635 continue;
5636 }
5637
5638 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5639 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5640 offset++;
5641
5642 outputs[i].values[chan] =
5643 ac_build_buffer_load(&ctx.ac,
5644 ctx.gsvs_ring[0], 1,
5645 ctx.i32_0, voffset,
5646 soffset, 0, 1, 1,
5647 true, false);
5648 }
5649 }
5650
5651 /* Streamout and exports. */
5652 if (gs_selector->so.num_outputs) {
5653 si_llvm_emit_streamout(&ctx, outputs,
5654 gsinfo->num_outputs,
5655 stream);
5656 }
5657
5658 if (stream == 0)
5659 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5660
5661 LLVMBuildBr(builder, end_bb);
5662 }
5663
5664 LLVMPositionBuilderAtEnd(builder, end_bb);
5665
5666 LLVMBuildRetVoid(ctx.ac.builder);
5667
5668 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5669 si_llvm_optimize_module(&ctx);
5670
5671 bool ok = false;
5672 if (si_compile_llvm(sscreen, &ctx.shader->binary,
5673 &ctx.shader->config, ctx.compiler,
5674 ctx.ac.module,
5675 debug, PIPE_SHADER_GEOMETRY,
5676 "GS Copy Shader", false) == 0) {
5677 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5678 fprintf(stderr, "GS Copy Shader:\n");
5679 si_shader_dump(sscreen, ctx.shader, debug,
5680 PIPE_SHADER_GEOMETRY, stderr, true);
5681
5682 if (!ctx.shader->config.scratch_bytes_per_wave)
5683 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
5684 else
5685 ok = true;
5686 }
5687
5688 si_llvm_dispose(&ctx);
5689
5690 if (!ok) {
5691 FREE(shader);
5692 shader = NULL;
5693 } else {
5694 si_fix_resource_usage(sscreen, shader);
5695 }
5696 return shader;
5697 }
5698
5699 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5700 const struct si_vs_prolog_bits *prolog,
5701 const char *prefix, FILE *f)
5702 {
5703 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5704 prefix, prolog->instance_divisor_is_one);
5705 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5706 prefix, prolog->instance_divisor_is_fetched);
5707 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5708 prefix, prolog->unpack_instance_id_from_vertex_id);
5709 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5710 prefix, prolog->ls_vgpr_fix);
5711
5712 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5713 fprintf(f, " mono.vs.fix_fetch = {");
5714 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5715 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5716 if (i)
5717 fprintf(f, ", ");
5718 if (!fix.bits)
5719 fprintf(f, "0");
5720 else
5721 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5722 fix.u.num_channels_m1, fix.u.format);
5723 }
5724 fprintf(f, "}\n");
5725 }
5726
5727 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5728 FILE *f)
5729 {
5730 const struct si_shader_key *key = &shader->key;
5731
5732 fprintf(f, "SHADER KEY\n");
5733
5734 switch (processor) {
5735 case PIPE_SHADER_VERTEX:
5736 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5737 "part.vs.prolog", f);
5738 fprintf(f, " as_es = %u\n", key->as_es);
5739 fprintf(f, " as_ls = %u\n", key->as_ls);
5740 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5741 key->mono.u.vs_export_prim_id);
5742 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5743 key->opt.vs_as_prim_discard_cs);
5744 fprintf(f, " opt.cs_prim_type = %s\n",
5745 tgsi_primitive_names[key->opt.cs_prim_type]);
5746 fprintf(f, " opt.cs_indexed = %u\n",
5747 key->opt.cs_indexed);
5748 fprintf(f, " opt.cs_instancing = %u\n",
5749 key->opt.cs_instancing);
5750 fprintf(f, " opt.cs_primitive_restart = %u\n",
5751 key->opt.cs_primitive_restart);
5752 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5753 key->opt.cs_provoking_vertex_first);
5754 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5755 key->opt.cs_need_correct_orientation);
5756 fprintf(f, " opt.cs_cull_front = %u\n",
5757 key->opt.cs_cull_front);
5758 fprintf(f, " opt.cs_cull_back = %u\n",
5759 key->opt.cs_cull_back);
5760 fprintf(f, " opt.cs_cull_z = %u\n",
5761 key->opt.cs_cull_z);
5762 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5763 key->opt.cs_halfz_clip_space);
5764 break;
5765
5766 case PIPE_SHADER_TESS_CTRL:
5767 if (shader->selector->screen->info.chip_class >= GFX9) {
5768 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5769 "part.tcs.ls_prolog", f);
5770 }
5771 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5772 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5773 break;
5774
5775 case PIPE_SHADER_TESS_EVAL:
5776 fprintf(f, " as_es = %u\n", key->as_es);
5777 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5778 key->mono.u.vs_export_prim_id);
5779 break;
5780
5781 case PIPE_SHADER_GEOMETRY:
5782 if (shader->is_gs_copy_shader)
5783 break;
5784
5785 if (shader->selector->screen->info.chip_class >= GFX9 &&
5786 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5787 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5788 "part.gs.vs_prolog", f);
5789 }
5790 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5791 break;
5792
5793 case PIPE_SHADER_COMPUTE:
5794 break;
5795
5796 case PIPE_SHADER_FRAGMENT:
5797 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5798 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5799 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5800 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5801 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5802 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5803 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5804 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5805 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5806 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5807 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5808 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5809 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5810 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5811 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5812 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5813 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5814 break;
5815
5816 default:
5817 assert(0);
5818 }
5819
5820 if ((processor == PIPE_SHADER_GEOMETRY ||
5821 processor == PIPE_SHADER_TESS_EVAL ||
5822 processor == PIPE_SHADER_VERTEX) &&
5823 !key->as_es && !key->as_ls) {
5824 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5825 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5826 }
5827 }
5828
5829 static void si_init_shader_ctx(struct si_shader_context *ctx,
5830 struct si_screen *sscreen,
5831 struct ac_llvm_compiler *compiler)
5832 {
5833 struct lp_build_tgsi_context *bld_base;
5834
5835 si_llvm_context_init(ctx, sscreen, compiler);
5836
5837 bld_base = &ctx->bld_base;
5838 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5839
5840 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5841 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5842 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5843
5844 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5845
5846 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5847
5848 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5849 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5850 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5851 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5852
5853 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5854 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5855 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5856 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5857 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5858 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5859 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5860 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5861
5862 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5863 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5864 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5865 }
5866
5867 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5868 {
5869 struct si_shader *shader = ctx->shader;
5870 struct tgsi_shader_info *info = &shader->selector->info;
5871
5872 if ((ctx->type != PIPE_SHADER_VERTEX &&
5873 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5874 shader->key.as_ls ||
5875 shader->key.as_es)
5876 return;
5877
5878 ac_optimize_vs_outputs(&ctx->ac,
5879 ctx->main_fn,
5880 shader->info.vs_output_param_offset,
5881 info->num_outputs,
5882 &shader->info.nr_param_exports);
5883 }
5884
5885 static void si_init_exec_from_input(struct si_shader_context *ctx,
5886 unsigned param, unsigned bitoffset)
5887 {
5888 LLVMValueRef args[] = {
5889 LLVMGetParam(ctx->main_fn, param),
5890 LLVMConstInt(ctx->i32, bitoffset, 0),
5891 };
5892 ac_build_intrinsic(&ctx->ac,
5893 "llvm.amdgcn.init.exec.from.input",
5894 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5895 }
5896
5897 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5898 const struct si_vs_prolog_bits *key)
5899 {
5900 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5901 * VS prolog. */
5902 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5903 }
5904
5905 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5906 {
5907 struct si_shader *shader = ctx->shader;
5908 struct si_shader_selector *sel = shader->selector;
5909 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5910
5911 // TODO clean all this up!
5912 switch (ctx->type) {
5913 case PIPE_SHADER_VERTEX:
5914 ctx->load_input = declare_input_vs;
5915 if (shader->key.as_ls)
5916 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5917 else if (shader->key.as_es)
5918 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5919 else if (shader->key.opt.vs_as_prim_discard_cs)
5920 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
5921 else
5922 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5923 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5924 ctx->abi.load_base_vertex = get_base_vertex;
5925 break;
5926 case PIPE_SHADER_TESS_CTRL:
5927 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5928 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5929 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5930 bld_base->emit_store = store_output_tcs;
5931 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5932 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5933 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5934 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5935 break;
5936 case PIPE_SHADER_TESS_EVAL:
5937 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5938 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5939 ctx->abi.load_tess_coord = si_load_tess_coord;
5940 ctx->abi.load_tess_level = si_load_tess_level;
5941 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5942 if (shader->key.as_es)
5943 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5944 else
5945 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5946 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5947 break;
5948 case PIPE_SHADER_GEOMETRY:
5949 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5950 ctx->abi.load_inputs = si_nir_load_input_gs;
5951 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5952 ctx->abi.emit_primitive = si_llvm_emit_primitive;
5953 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5954 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5955 break;
5956 case PIPE_SHADER_FRAGMENT:
5957 ctx->load_input = declare_input_fs;
5958 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5959 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5960 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
5961 ctx->abi.load_sample_position = load_sample_position;
5962 ctx->abi.load_sample_mask_in = load_sample_mask_in;
5963 ctx->abi.emit_kill = si_llvm_emit_kill;
5964 break;
5965 case PIPE_SHADER_COMPUTE:
5966 ctx->abi.load_local_group_size = get_block_size;
5967 break;
5968 default:
5969 assert(!"Unsupported shader type");
5970 return false;
5971 }
5972
5973 ctx->abi.load_ubo = load_ubo;
5974 ctx->abi.load_ssbo = load_ssbo;
5975
5976 create_function(ctx);
5977 preload_ring_buffers(ctx);
5978
5979 /* For GFX9 merged shaders:
5980 * - Set EXEC for the first shader. If the prolog is present, set
5981 * EXEC there instead.
5982 * - Add a barrier before the second shader.
5983 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5984 * an if-statement. This is required for correctness in geometry
5985 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5986 * GS_CUT messages.
5987 *
5988 * For monolithic merged shaders, the first shader is wrapped in an
5989 * if-block together with its prolog in si_build_wrapper_function.
5990 */
5991 if (ctx->screen->info.chip_class >= GFX9) {
5992 if (!shader->is_monolithic &&
5993 sel->info.num_instructions > 1 && /* not empty shader */
5994 (shader->key.as_es || shader->key.as_ls) &&
5995 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5996 (ctx->type == PIPE_SHADER_VERTEX &&
5997 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5998 si_init_exec_from_input(ctx,
5999 ctx->param_merged_wave_info, 0);
6000 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6001 ctx->type == PIPE_SHADER_GEOMETRY) {
6002 if (!shader->is_monolithic)
6003 ac_init_exec_full_mask(&ctx->ac);
6004
6005 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6006 LLVMValueRef ena =
6007 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6008 ac_get_thread_id(&ctx->ac), num_threads, "");
6009 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6010
6011 /* The barrier must execute for all shaders in a
6012 * threadgroup.
6013 *
6014 * Execute the barrier inside the conditional block,
6015 * so that empty waves can jump directly to s_endpgm,
6016 * which will also signal the barrier.
6017 *
6018 * If the shader is TCS and the TCS epilog is present
6019 * and contains a barrier, it will wait there and then
6020 * reach s_endpgm.
6021 */
6022 si_llvm_emit_barrier(NULL, bld_base, NULL);
6023 }
6024 }
6025
6026 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6027 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6028 for (unsigned i = 0; i < 6; i++) {
6029 ctx->invoc0_tess_factors[i] =
6030 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6031 }
6032 }
6033
6034 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6035 int i;
6036 for (i = 0; i < 4; i++) {
6037 ctx->gs_next_vertex[i] =
6038 ac_build_alloca(&ctx->ac, ctx->i32, "");
6039 }
6040 }
6041
6042 if (sel->force_correct_derivs_after_kill) {
6043 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6044 /* true = don't kill. */
6045 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6046 ctx->postponed_kill);
6047 }
6048
6049 if (sel->tokens) {
6050 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6051 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6052 return false;
6053 }
6054 } else {
6055 if (!si_nir_build_llvm(ctx, sel->nir)) {
6056 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6057 return false;
6058 }
6059 }
6060
6061 si_llvm_build_ret(ctx, ctx->return_value);
6062 return true;
6063 }
6064
6065 /**
6066 * Compute the VS prolog key, which contains all the information needed to
6067 * build the VS prolog function, and set shader->info bits where needed.
6068 *
6069 * \param info Shader info of the vertex shader.
6070 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6071 * \param prolog_key Key of the VS prolog
6072 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6073 * \param key Output shader part key.
6074 */
6075 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6076 unsigned num_input_sgprs,
6077 const struct si_vs_prolog_bits *prolog_key,
6078 struct si_shader *shader_out,
6079 union si_shader_part_key *key)
6080 {
6081 memset(key, 0, sizeof(*key));
6082 key->vs_prolog.states = *prolog_key;
6083 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6084 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6085 key->vs_prolog.as_ls = shader_out->key.as_ls;
6086 key->vs_prolog.as_es = shader_out->key.as_es;
6087 key->vs_prolog.as_ngg = shader_out->key.as_ngg;
6088
6089 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6090 key->vs_prolog.as_ls = 1;
6091 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6092 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6093 key->vs_prolog.as_es = 1;
6094 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6095 }
6096
6097 /* Enable loading the InstanceID VGPR. */
6098 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6099
6100 if ((key->vs_prolog.states.instance_divisor_is_one |
6101 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6102 shader_out->info.uses_instanceid = true;
6103 }
6104
6105 /**
6106 * Compute the PS prolog key, which contains all the information needed to
6107 * build the PS prolog function, and set related bits in shader->config.
6108 */
6109 static void si_get_ps_prolog_key(struct si_shader *shader,
6110 union si_shader_part_key *key,
6111 bool separate_prolog)
6112 {
6113 struct tgsi_shader_info *info = &shader->selector->info;
6114
6115 memset(key, 0, sizeof(*key));
6116 key->ps_prolog.states = shader->key.part.ps.prolog;
6117 key->ps_prolog.colors_read = info->colors_read;
6118 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6119 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6120 key->ps_prolog.wqm = info->uses_derivatives &&
6121 (key->ps_prolog.colors_read ||
6122 key->ps_prolog.states.force_persp_sample_interp ||
6123 key->ps_prolog.states.force_linear_sample_interp ||
6124 key->ps_prolog.states.force_persp_center_interp ||
6125 key->ps_prolog.states.force_linear_center_interp ||
6126 key->ps_prolog.states.bc_optimize_for_persp ||
6127 key->ps_prolog.states.bc_optimize_for_linear);
6128 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6129
6130 if (info->colors_read) {
6131 unsigned *color = shader->selector->color_attr_index;
6132
6133 if (shader->key.part.ps.prolog.color_two_side) {
6134 /* BCOLORs are stored after the last input. */
6135 key->ps_prolog.num_interp_inputs = info->num_inputs;
6136 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6137 if (separate_prolog)
6138 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6139 }
6140
6141 for (unsigned i = 0; i < 2; i++) {
6142 unsigned interp = info->input_interpolate[color[i]];
6143 unsigned location = info->input_interpolate_loc[color[i]];
6144
6145 if (!(info->colors_read & (0xf << i*4)))
6146 continue;
6147
6148 key->ps_prolog.color_attr_index[i] = color[i];
6149
6150 if (shader->key.part.ps.prolog.flatshade_colors &&
6151 interp == TGSI_INTERPOLATE_COLOR)
6152 interp = TGSI_INTERPOLATE_CONSTANT;
6153
6154 switch (interp) {
6155 case TGSI_INTERPOLATE_CONSTANT:
6156 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6157 break;
6158 case TGSI_INTERPOLATE_PERSPECTIVE:
6159 case TGSI_INTERPOLATE_COLOR:
6160 /* Force the interpolation location for colors here. */
6161 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6162 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6163 if (shader->key.part.ps.prolog.force_persp_center_interp)
6164 location = TGSI_INTERPOLATE_LOC_CENTER;
6165
6166 switch (location) {
6167 case TGSI_INTERPOLATE_LOC_SAMPLE:
6168 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6169 if (separate_prolog) {
6170 shader->config.spi_ps_input_ena |=
6171 S_0286CC_PERSP_SAMPLE_ENA(1);
6172 }
6173 break;
6174 case TGSI_INTERPOLATE_LOC_CENTER:
6175 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6176 if (separate_prolog) {
6177 shader->config.spi_ps_input_ena |=
6178 S_0286CC_PERSP_CENTER_ENA(1);
6179 }
6180 break;
6181 case TGSI_INTERPOLATE_LOC_CENTROID:
6182 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6183 if (separate_prolog) {
6184 shader->config.spi_ps_input_ena |=
6185 S_0286CC_PERSP_CENTROID_ENA(1);
6186 }
6187 break;
6188 default:
6189 assert(0);
6190 }
6191 break;
6192 case TGSI_INTERPOLATE_LINEAR:
6193 /* Force the interpolation location for colors here. */
6194 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6195 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6196 if (shader->key.part.ps.prolog.force_linear_center_interp)
6197 location = TGSI_INTERPOLATE_LOC_CENTER;
6198
6199 /* The VGPR assignment for non-monolithic shaders
6200 * works because InitialPSInputAddr is set on the
6201 * main shader and PERSP_PULL_MODEL is never used.
6202 */
6203 switch (location) {
6204 case TGSI_INTERPOLATE_LOC_SAMPLE:
6205 key->ps_prolog.color_interp_vgpr_index[i] =
6206 separate_prolog ? 6 : 9;
6207 if (separate_prolog) {
6208 shader->config.spi_ps_input_ena |=
6209 S_0286CC_LINEAR_SAMPLE_ENA(1);
6210 }
6211 break;
6212 case TGSI_INTERPOLATE_LOC_CENTER:
6213 key->ps_prolog.color_interp_vgpr_index[i] =
6214 separate_prolog ? 8 : 11;
6215 if (separate_prolog) {
6216 shader->config.spi_ps_input_ena |=
6217 S_0286CC_LINEAR_CENTER_ENA(1);
6218 }
6219 break;
6220 case TGSI_INTERPOLATE_LOC_CENTROID:
6221 key->ps_prolog.color_interp_vgpr_index[i] =
6222 separate_prolog ? 10 : 13;
6223 if (separate_prolog) {
6224 shader->config.spi_ps_input_ena |=
6225 S_0286CC_LINEAR_CENTROID_ENA(1);
6226 }
6227 break;
6228 default:
6229 assert(0);
6230 }
6231 break;
6232 default:
6233 assert(0);
6234 }
6235 }
6236 }
6237 }
6238
6239 /**
6240 * Check whether a PS prolog is required based on the key.
6241 */
6242 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6243 {
6244 return key->ps_prolog.colors_read ||
6245 key->ps_prolog.states.force_persp_sample_interp ||
6246 key->ps_prolog.states.force_linear_sample_interp ||
6247 key->ps_prolog.states.force_persp_center_interp ||
6248 key->ps_prolog.states.force_linear_center_interp ||
6249 key->ps_prolog.states.bc_optimize_for_persp ||
6250 key->ps_prolog.states.bc_optimize_for_linear ||
6251 key->ps_prolog.states.poly_stipple ||
6252 key->ps_prolog.states.samplemask_log_ps_iter;
6253 }
6254
6255 /**
6256 * Compute the PS epilog key, which contains all the information needed to
6257 * build the PS epilog function.
6258 */
6259 static void si_get_ps_epilog_key(struct si_shader *shader,
6260 union si_shader_part_key *key)
6261 {
6262 struct tgsi_shader_info *info = &shader->selector->info;
6263 memset(key, 0, sizeof(*key));
6264 key->ps_epilog.colors_written = info->colors_written;
6265 key->ps_epilog.writes_z = info->writes_z;
6266 key->ps_epilog.writes_stencil = info->writes_stencil;
6267 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6268 key->ps_epilog.states = shader->key.part.ps.epilog;
6269 }
6270
6271 /**
6272 * Build the GS prolog function. Rotate the input vertices for triangle strips
6273 * with adjacency.
6274 */
6275 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6276 union si_shader_part_key *key)
6277 {
6278 unsigned num_sgprs, num_vgprs;
6279 struct si_function_info fninfo;
6280 LLVMBuilderRef builder = ctx->ac.builder;
6281 LLVMTypeRef returns[48];
6282 LLVMValueRef func, ret;
6283
6284 si_init_function_info(&fninfo);
6285
6286 if (ctx->screen->info.chip_class >= GFX9) {
6287 if (key->gs_prolog.states.gfx9_prev_is_vs)
6288 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6289 else
6290 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6291 num_vgprs = 5; /* ES inputs are not needed by GS */
6292 } else {
6293 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6294 num_vgprs = 8;
6295 }
6296
6297 for (unsigned i = 0; i < num_sgprs; ++i) {
6298 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6299 returns[i] = ctx->i32;
6300 }
6301
6302 for (unsigned i = 0; i < num_vgprs; ++i) {
6303 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6304 returns[num_sgprs + i] = ctx->f32;
6305 }
6306
6307 /* Create the function. */
6308 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6309 &fninfo, 0);
6310 func = ctx->main_fn;
6311
6312 /* Set the full EXEC mask for the prolog, because we are only fiddling
6313 * with registers here. The main shader part will set the correct EXEC
6314 * mask.
6315 */
6316 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6317 ac_init_exec_full_mask(&ctx->ac);
6318
6319 /* Copy inputs to outputs. This should be no-op, as the registers match,
6320 * but it will prevent the compiler from overwriting them unintentionally.
6321 */
6322 ret = ctx->return_value;
6323 for (unsigned i = 0; i < num_sgprs; i++) {
6324 LLVMValueRef p = LLVMGetParam(func, i);
6325 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6326 }
6327 for (unsigned i = 0; i < num_vgprs; i++) {
6328 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6329 p = ac_to_float(&ctx->ac, p);
6330 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6331 }
6332
6333 if (key->gs_prolog.states.tri_strip_adj_fix) {
6334 /* Remap the input vertices for every other primitive. */
6335 const unsigned gfx6_vtx_params[6] = {
6336 num_sgprs,
6337 num_sgprs + 1,
6338 num_sgprs + 3,
6339 num_sgprs + 4,
6340 num_sgprs + 5,
6341 num_sgprs + 6
6342 };
6343 const unsigned gfx9_vtx_params[3] = {
6344 num_sgprs,
6345 num_sgprs + 1,
6346 num_sgprs + 4,
6347 };
6348 LLVMValueRef vtx_in[6], vtx_out[6];
6349 LLVMValueRef prim_id, rotate;
6350
6351 if (ctx->screen->info.chip_class >= GFX9) {
6352 for (unsigned i = 0; i < 3; i++) {
6353 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6354 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6355 }
6356 } else {
6357 for (unsigned i = 0; i < 6; i++)
6358 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6359 }
6360
6361 prim_id = LLVMGetParam(func, num_sgprs + 2);
6362 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6363
6364 for (unsigned i = 0; i < 6; ++i) {
6365 LLVMValueRef base, rotated;
6366 base = vtx_in[i];
6367 rotated = vtx_in[(i + 4) % 6];
6368 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6369 }
6370
6371 if (ctx->screen->info.chip_class >= GFX9) {
6372 for (unsigned i = 0; i < 3; i++) {
6373 LLVMValueRef hi, out;
6374
6375 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6376 LLVMConstInt(ctx->i32, 16, 0), "");
6377 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6378 out = ac_to_float(&ctx->ac, out);
6379 ret = LLVMBuildInsertValue(builder, ret, out,
6380 gfx9_vtx_params[i], "");
6381 }
6382 } else {
6383 for (unsigned i = 0; i < 6; i++) {
6384 LLVMValueRef out;
6385
6386 out = ac_to_float(&ctx->ac, vtx_out[i]);
6387 ret = LLVMBuildInsertValue(builder, ret, out,
6388 gfx6_vtx_params[i], "");
6389 }
6390 }
6391 }
6392
6393 LLVMBuildRet(builder, ret);
6394 }
6395
6396 /**
6397 * Given a list of shader part functions, build a wrapper function that
6398 * runs them in sequence to form a monolithic shader.
6399 */
6400 static void si_build_wrapper_function(struct si_shader_context *ctx,
6401 LLVMValueRef *parts,
6402 unsigned num_parts,
6403 unsigned main_part,
6404 unsigned next_shader_first_part)
6405 {
6406 LLVMBuilderRef builder = ctx->ac.builder;
6407 /* PS epilog has one arg per color component; gfx9 merged shader
6408 * prologs need to forward 32 user SGPRs.
6409 */
6410 struct si_function_info fninfo;
6411 LLVMValueRef initial[64], out[64];
6412 LLVMTypeRef function_type;
6413 unsigned num_first_params;
6414 unsigned num_out, initial_num_out;
6415 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6416 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6417 unsigned num_sgprs, num_vgprs;
6418 unsigned gprs;
6419 struct lp_build_if_state if_state;
6420
6421 si_init_function_info(&fninfo);
6422
6423 for (unsigned i = 0; i < num_parts; ++i) {
6424 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6425 AC_FUNC_ATTR_ALWAYSINLINE);
6426 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6427 }
6428
6429 /* The parameters of the wrapper function correspond to those of the
6430 * first part in terms of SGPRs and VGPRs, but we use the types of the
6431 * main part to get the right types. This is relevant for the
6432 * dereferenceable attribute on descriptor table pointers.
6433 */
6434 num_sgprs = 0;
6435 num_vgprs = 0;
6436
6437 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6438 num_first_params = LLVMCountParamTypes(function_type);
6439
6440 for (unsigned i = 0; i < num_first_params; ++i) {
6441 LLVMValueRef param = LLVMGetParam(parts[0], i);
6442
6443 if (ac_is_sgpr_param(param)) {
6444 assert(num_vgprs == 0);
6445 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6446 } else {
6447 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6448 }
6449 }
6450
6451 gprs = 0;
6452 while (gprs < num_sgprs + num_vgprs) {
6453 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6454 LLVMTypeRef type = LLVMTypeOf(param);
6455 unsigned size = ac_get_type_size(type) / 4;
6456
6457 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6458
6459 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6460 assert(gprs + size <= num_sgprs + num_vgprs &&
6461 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6462
6463 gprs += size;
6464 }
6465
6466 /* Prepare the return type. */
6467 unsigned num_returns = 0;
6468 LLVMTypeRef returns[32], last_func_type, return_type;
6469
6470 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6471 return_type = LLVMGetReturnType(last_func_type);
6472
6473 switch (LLVMGetTypeKind(return_type)) {
6474 case LLVMStructTypeKind:
6475 num_returns = LLVMCountStructElementTypes(return_type);
6476 assert(num_returns <= ARRAY_SIZE(returns));
6477 LLVMGetStructElementTypes(return_type, returns);
6478 break;
6479 case LLVMVoidTypeKind:
6480 break;
6481 default:
6482 unreachable("unexpected type");
6483 }
6484
6485 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6486 si_get_max_workgroup_size(ctx->shader));
6487
6488 if (is_merged_shader(ctx))
6489 ac_init_exec_full_mask(&ctx->ac);
6490
6491 /* Record the arguments of the function as if they were an output of
6492 * a previous part.
6493 */
6494 num_out = 0;
6495 num_out_sgpr = 0;
6496
6497 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6498 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6499 LLVMTypeRef param_type = LLVMTypeOf(param);
6500 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6501 unsigned size = ac_get_type_size(param_type) / 4;
6502
6503 if (size == 1) {
6504 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6505 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6506 param_type = ctx->i32;
6507 }
6508
6509 if (param_type != out_type)
6510 param = LLVMBuildBitCast(builder, param, out_type, "");
6511 out[num_out++] = param;
6512 } else {
6513 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6514
6515 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6516 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6517 param_type = ctx->i64;
6518 }
6519
6520 if (param_type != vector_type)
6521 param = LLVMBuildBitCast(builder, param, vector_type, "");
6522
6523 for (unsigned j = 0; j < size; ++j)
6524 out[num_out++] = LLVMBuildExtractElement(
6525 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6526 }
6527
6528 if (i < fninfo.num_sgpr_params)
6529 num_out_sgpr = num_out;
6530 }
6531
6532 memcpy(initial, out, sizeof(out));
6533 initial_num_out = num_out;
6534 initial_num_out_sgpr = num_out_sgpr;
6535
6536 /* Now chain the parts. */
6537 LLVMValueRef ret;
6538 for (unsigned part = 0; part < num_parts; ++part) {
6539 LLVMValueRef in[48];
6540 LLVMTypeRef ret_type;
6541 unsigned out_idx = 0;
6542 unsigned num_params = LLVMCountParams(parts[part]);
6543
6544 /* Merged shaders are executed conditionally depending
6545 * on the number of enabled threads passed in the input SGPRs. */
6546 if (is_merged_shader(ctx) && part == 0) {
6547 LLVMValueRef ena, count = initial[3];
6548
6549 count = LLVMBuildAnd(builder, count,
6550 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6551 ena = LLVMBuildICmp(builder, LLVMIntULT,
6552 ac_get_thread_id(&ctx->ac), count, "");
6553 lp_build_if(&if_state, &ctx->gallivm, ena);
6554 }
6555
6556 /* Derive arguments for the next part from outputs of the
6557 * previous one.
6558 */
6559 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6560 LLVMValueRef param;
6561 LLVMTypeRef param_type;
6562 bool is_sgpr;
6563 unsigned param_size;
6564 LLVMValueRef arg = NULL;
6565
6566 param = LLVMGetParam(parts[part], param_idx);
6567 param_type = LLVMTypeOf(param);
6568 param_size = ac_get_type_size(param_type) / 4;
6569 is_sgpr = ac_is_sgpr_param(param);
6570
6571 if (is_sgpr) {
6572 ac_add_function_attr(ctx->ac.context, parts[part],
6573 param_idx + 1, AC_FUNC_ATTR_INREG);
6574 } else if (out_idx < num_out_sgpr) {
6575 /* Skip returned SGPRs the current part doesn't
6576 * declare on the input. */
6577 out_idx = num_out_sgpr;
6578 }
6579
6580 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6581
6582 if (param_size == 1)
6583 arg = out[out_idx];
6584 else
6585 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6586
6587 if (LLVMTypeOf(arg) != param_type) {
6588 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6589 if (LLVMGetPointerAddressSpace(param_type) ==
6590 AC_ADDR_SPACE_CONST_32BIT) {
6591 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6592 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6593 } else {
6594 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6595 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6596 }
6597 } else {
6598 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6599 }
6600 }
6601
6602 in[param_idx] = arg;
6603 out_idx += param_size;
6604 }
6605
6606 ret = ac_build_call(&ctx->ac, parts[part], in, num_params);
6607
6608 if (is_merged_shader(ctx) &&
6609 part + 1 == next_shader_first_part) {
6610 lp_build_endif(&if_state);
6611
6612 /* The second half of the merged shader should use
6613 * the inputs from the toplevel (wrapper) function,
6614 * not the return value from the last call.
6615 *
6616 * That's because the last call was executed condi-
6617 * tionally, so we can't consume it in the main
6618 * block.
6619 */
6620 memcpy(out, initial, sizeof(initial));
6621 num_out = initial_num_out;
6622 num_out_sgpr = initial_num_out_sgpr;
6623 continue;
6624 }
6625
6626 /* Extract the returned GPRs. */
6627 ret_type = LLVMTypeOf(ret);
6628 num_out = 0;
6629 num_out_sgpr = 0;
6630
6631 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6632 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6633
6634 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6635
6636 for (unsigned i = 0; i < ret_size; ++i) {
6637 LLVMValueRef val =
6638 LLVMBuildExtractValue(builder, ret, i, "");
6639
6640 assert(num_out < ARRAY_SIZE(out));
6641 out[num_out++] = val;
6642
6643 if (LLVMTypeOf(val) == ctx->i32) {
6644 assert(num_out_sgpr + 1 == num_out);
6645 num_out_sgpr = num_out;
6646 }
6647 }
6648 }
6649 }
6650
6651 /* Return the value from the last part. */
6652 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6653 LLVMBuildRetVoid(builder);
6654 else
6655 LLVMBuildRet(builder, ret);
6656 }
6657
6658 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6659 struct si_shader_selector *sel)
6660 {
6661 if (!compiler->low_opt_passes)
6662 return false;
6663
6664 /* Assume a slow CPU. */
6665 assert(!sel->screen->info.has_dedicated_vram &&
6666 sel->screen->info.chip_class <= GFX8);
6667
6668 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6669 * buffer stores. */
6670 return sel->type == PIPE_SHADER_COMPUTE &&
6671 sel->info.num_memory_instructions > 1000;
6672 }
6673
6674 int si_compile_tgsi_shader(struct si_screen *sscreen,
6675 struct ac_llvm_compiler *compiler,
6676 struct si_shader *shader,
6677 struct pipe_debug_callback *debug)
6678 {
6679 struct si_shader_selector *sel = shader->selector;
6680 struct si_shader_context ctx;
6681 int r = -1;
6682
6683 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6684 * conversion fails. */
6685 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6686 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6687 if (sel->tokens)
6688 tgsi_dump(sel->tokens, 0);
6689 else
6690 nir_print_shader(sel->nir, stderr);
6691 si_dump_streamout(&sel->so);
6692 }
6693
6694 si_init_shader_ctx(&ctx, sscreen, compiler);
6695 si_llvm_context_set_tgsi(&ctx, shader);
6696
6697 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6698 sizeof(shader->info.vs_output_param_offset));
6699
6700 shader->info.uses_instanceid = sel->info.uses_instanceid;
6701
6702 if (!si_compile_tgsi_main(&ctx)) {
6703 si_llvm_dispose(&ctx);
6704 return -1;
6705 }
6706
6707 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6708 LLVMValueRef parts[2];
6709 bool need_prolog = sel->vs_needs_prolog;
6710
6711 parts[1] = ctx.main_fn;
6712
6713 if (need_prolog) {
6714 union si_shader_part_key prolog_key;
6715 si_get_vs_prolog_key(&sel->info,
6716 shader->info.num_input_sgprs,
6717 &shader->key.part.vs.prolog,
6718 shader, &prolog_key);
6719 si_build_vs_prolog_function(&ctx, &prolog_key);
6720 parts[0] = ctx.main_fn;
6721 }
6722
6723 si_build_wrapper_function(&ctx, parts + !need_prolog,
6724 1 + need_prolog, need_prolog, 0);
6725
6726 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6727 si_build_prim_discard_compute_shader(&ctx);
6728 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6729 if (sscreen->info.chip_class >= GFX9) {
6730 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6731 LLVMValueRef parts[4];
6732 bool vs_needs_prolog =
6733 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6734
6735 /* TCS main part */
6736 parts[2] = ctx.main_fn;
6737
6738 /* TCS epilog */
6739 union si_shader_part_key tcs_epilog_key;
6740 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6741 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6742 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6743 parts[3] = ctx.main_fn;
6744
6745 /* VS as LS main part */
6746 struct si_shader shader_ls = {};
6747 shader_ls.selector = ls;
6748 shader_ls.key.as_ls = 1;
6749 shader_ls.key.mono = shader->key.mono;
6750 shader_ls.key.opt = shader->key.opt;
6751 shader_ls.is_monolithic = true;
6752 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6753
6754 if (!si_compile_tgsi_main(&ctx)) {
6755 si_llvm_dispose(&ctx);
6756 return -1;
6757 }
6758 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6759 parts[1] = ctx.main_fn;
6760
6761 /* LS prolog */
6762 if (vs_needs_prolog) {
6763 union si_shader_part_key vs_prolog_key;
6764 si_get_vs_prolog_key(&ls->info,
6765 shader_ls.info.num_input_sgprs,
6766 &shader->key.part.tcs.ls_prolog,
6767 shader, &vs_prolog_key);
6768 vs_prolog_key.vs_prolog.is_monolithic = true;
6769 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6770 parts[0] = ctx.main_fn;
6771 }
6772
6773 /* Reset the shader context. */
6774 ctx.shader = shader;
6775 ctx.type = PIPE_SHADER_TESS_CTRL;
6776
6777 si_build_wrapper_function(&ctx,
6778 parts + !vs_needs_prolog,
6779 4 - !vs_needs_prolog, vs_needs_prolog,
6780 vs_needs_prolog ? 2 : 1);
6781 } else {
6782 LLVMValueRef parts[2];
6783 union si_shader_part_key epilog_key;
6784
6785 parts[0] = ctx.main_fn;
6786
6787 memset(&epilog_key, 0, sizeof(epilog_key));
6788 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6789 si_build_tcs_epilog_function(&ctx, &epilog_key);
6790 parts[1] = ctx.main_fn;
6791
6792 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6793 }
6794 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6795 if (ctx.screen->info.chip_class >= GFX9) {
6796 struct si_shader_selector *es = shader->key.part.gs.es;
6797 LLVMValueRef es_prolog = NULL;
6798 LLVMValueRef es_main = NULL;
6799 LLVMValueRef gs_prolog = NULL;
6800 LLVMValueRef gs_main = ctx.main_fn;
6801
6802 /* GS prolog */
6803 union si_shader_part_key gs_prolog_key;
6804 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6805 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6806 gs_prolog_key.gs_prolog.is_monolithic = true;
6807 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6808 gs_prolog = ctx.main_fn;
6809
6810 /* ES main part */
6811 struct si_shader shader_es = {};
6812 shader_es.selector = es;
6813 shader_es.key.as_es = 1;
6814 shader_es.key.mono = shader->key.mono;
6815 shader_es.key.opt = shader->key.opt;
6816 shader_es.is_monolithic = true;
6817 si_llvm_context_set_tgsi(&ctx, &shader_es);
6818
6819 if (!si_compile_tgsi_main(&ctx)) {
6820 si_llvm_dispose(&ctx);
6821 return -1;
6822 }
6823 shader->info.uses_instanceid |= es->info.uses_instanceid;
6824 es_main = ctx.main_fn;
6825
6826 /* ES prolog */
6827 if (es->vs_needs_prolog) {
6828 union si_shader_part_key vs_prolog_key;
6829 si_get_vs_prolog_key(&es->info,
6830 shader_es.info.num_input_sgprs,
6831 &shader->key.part.gs.vs_prolog,
6832 shader, &vs_prolog_key);
6833 vs_prolog_key.vs_prolog.is_monolithic = true;
6834 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6835 es_prolog = ctx.main_fn;
6836 }
6837
6838 /* Reset the shader context. */
6839 ctx.shader = shader;
6840 ctx.type = PIPE_SHADER_GEOMETRY;
6841
6842 /* Prepare the array of shader parts. */
6843 LLVMValueRef parts[4];
6844 unsigned num_parts = 0, main_part, next_first_part;
6845
6846 if (es_prolog)
6847 parts[num_parts++] = es_prolog;
6848
6849 parts[main_part = num_parts++] = es_main;
6850 parts[next_first_part = num_parts++] = gs_prolog;
6851 parts[num_parts++] = gs_main;
6852
6853 si_build_wrapper_function(&ctx, parts, num_parts,
6854 main_part, next_first_part);
6855 } else {
6856 LLVMValueRef parts[2];
6857 union si_shader_part_key prolog_key;
6858
6859 parts[1] = ctx.main_fn;
6860
6861 memset(&prolog_key, 0, sizeof(prolog_key));
6862 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6863 si_build_gs_prolog_function(&ctx, &prolog_key);
6864 parts[0] = ctx.main_fn;
6865
6866 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6867 }
6868 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6869 LLVMValueRef parts[3];
6870 union si_shader_part_key prolog_key;
6871 union si_shader_part_key epilog_key;
6872 bool need_prolog;
6873
6874 si_get_ps_prolog_key(shader, &prolog_key, false);
6875 need_prolog = si_need_ps_prolog(&prolog_key);
6876
6877 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6878
6879 if (need_prolog) {
6880 si_build_ps_prolog_function(&ctx, &prolog_key);
6881 parts[0] = ctx.main_fn;
6882 }
6883
6884 si_get_ps_epilog_key(shader, &epilog_key);
6885 si_build_ps_epilog_function(&ctx, &epilog_key);
6886 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6887
6888 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6889 need_prolog ? 1 : 0, 0);
6890 }
6891
6892 si_llvm_optimize_module(&ctx);
6893
6894 /* Post-optimization transformations and analysis. */
6895 si_optimize_vs_outputs(&ctx);
6896
6897 if ((debug && debug->debug_message) ||
6898 si_can_dump_shader(sscreen, ctx.type)) {
6899 ctx.shader->info.private_mem_vgprs =
6900 ac_count_scratch_private_memory(ctx.main_fn);
6901 }
6902
6903 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6904 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6905 LLVMPointerTypeKind);
6906
6907 /* Compile to bytecode. */
6908 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6909 ctx.ac.module, debug, ctx.type,
6910 si_get_shader_name(shader, ctx.type),
6911 si_should_optimize_less(compiler, shader->selector));
6912 si_llvm_dispose(&ctx);
6913 if (r) {
6914 fprintf(stderr, "LLVM failed to compile shader\n");
6915 return r;
6916 }
6917
6918 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6919 * LLVM 3.9svn has this bug.
6920 */
6921 if (sel->type == PIPE_SHADER_COMPUTE) {
6922 unsigned wave_size = 64;
6923 unsigned max_vgprs = 256;
6924 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
6925 unsigned max_sgprs_per_wave = 128;
6926 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6927 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6928 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6929
6930 max_vgprs = max_vgprs / min_waves_per_simd;
6931 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6932
6933 if (shader->config.num_sgprs > max_sgprs ||
6934 shader->config.num_vgprs > max_vgprs) {
6935 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6936 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6937 shader->config.num_sgprs, shader->config.num_vgprs,
6938 max_sgprs, max_vgprs);
6939
6940 /* Just terminate the process, because dependent
6941 * shaders can hang due to bad input data, but use
6942 * the env var to allow shader-db to work.
6943 */
6944 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6945 abort();
6946 }
6947 }
6948
6949 /* Add the scratch offset to input SGPRs. */
6950 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6951 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6952
6953 /* Calculate the number of fragment input VGPRs. */
6954 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6955 shader->info.num_input_vgprs = 0;
6956 shader->info.face_vgpr_index = -1;
6957 shader->info.ancillary_vgpr_index = -1;
6958
6959 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6960 shader->info.num_input_vgprs += 2;
6961 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6962 shader->info.num_input_vgprs += 2;
6963 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6964 shader->info.num_input_vgprs += 2;
6965 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6966 shader->info.num_input_vgprs += 3;
6967 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6968 shader->info.num_input_vgprs += 2;
6969 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6970 shader->info.num_input_vgprs += 2;
6971 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6972 shader->info.num_input_vgprs += 2;
6973 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6974 shader->info.num_input_vgprs += 1;
6975 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6976 shader->info.num_input_vgprs += 1;
6977 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6978 shader->info.num_input_vgprs += 1;
6979 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6980 shader->info.num_input_vgprs += 1;
6981 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6982 shader->info.num_input_vgprs += 1;
6983 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6984 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6985 shader->info.num_input_vgprs += 1;
6986 }
6987 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6988 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6989 shader->info.num_input_vgprs += 1;
6990 }
6991 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6992 shader->info.num_input_vgprs += 1;
6993 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6994 shader->info.num_input_vgprs += 1;
6995 }
6996
6997 si_calculate_max_simd_waves(shader);
6998 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
6999 return 0;
7000 }
7001
7002 /**
7003 * Create, compile and return a shader part (prolog or epilog).
7004 *
7005 * \param sscreen screen
7006 * \param list list of shader parts of the same category
7007 * \param type shader type
7008 * \param key shader part key
7009 * \param prolog whether the part being requested is a prolog
7010 * \param tm LLVM target machine
7011 * \param debug debug callback
7012 * \param build the callback responsible for building the main function
7013 * \return non-NULL on success
7014 */
7015 static struct si_shader_part *
7016 si_get_shader_part(struct si_screen *sscreen,
7017 struct si_shader_part **list,
7018 enum pipe_shader_type type,
7019 bool prolog,
7020 union si_shader_part_key *key,
7021 struct ac_llvm_compiler *compiler,
7022 struct pipe_debug_callback *debug,
7023 void (*build)(struct si_shader_context *,
7024 union si_shader_part_key *),
7025 const char *name)
7026 {
7027 struct si_shader_part *result;
7028
7029 mtx_lock(&sscreen->shader_parts_mutex);
7030
7031 /* Find existing. */
7032 for (result = *list; result; result = result->next) {
7033 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7034 mtx_unlock(&sscreen->shader_parts_mutex);
7035 return result;
7036 }
7037 }
7038
7039 /* Compile a new one. */
7040 result = CALLOC_STRUCT(si_shader_part);
7041 result->key = *key;
7042
7043 struct si_shader shader = {};
7044 struct si_shader_context ctx;
7045
7046 si_init_shader_ctx(&ctx, sscreen, compiler);
7047 ctx.shader = &shader;
7048 ctx.type = type;
7049
7050 switch (type) {
7051 case PIPE_SHADER_VERTEX:
7052 shader.key.as_ls = key->vs_prolog.as_ls;
7053 shader.key.as_es = key->vs_prolog.as_es;
7054 shader.key.as_ngg = key->vs_prolog.as_ngg;
7055 break;
7056 case PIPE_SHADER_TESS_CTRL:
7057 assert(!prolog);
7058 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7059 break;
7060 case PIPE_SHADER_GEOMETRY:
7061 assert(prolog);
7062 break;
7063 case PIPE_SHADER_FRAGMENT:
7064 if (prolog)
7065 shader.key.part.ps.prolog = key->ps_prolog.states;
7066 else
7067 shader.key.part.ps.epilog = key->ps_epilog.states;
7068 break;
7069 default:
7070 unreachable("bad shader part");
7071 }
7072
7073 build(&ctx, key);
7074
7075 /* Compile. */
7076 si_llvm_optimize_module(&ctx);
7077
7078 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7079 ctx.ac.module, debug, ctx.type, name, false)) {
7080 FREE(result);
7081 result = NULL;
7082 goto out;
7083 }
7084
7085 result->next = *list;
7086 *list = result;
7087
7088 out:
7089 si_llvm_dispose(&ctx);
7090 mtx_unlock(&sscreen->shader_parts_mutex);
7091 return result;
7092 }
7093
7094 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7095 {
7096 LLVMValueRef ptr[2], list;
7097 bool merged_shader = is_merged_shader(ctx);
7098
7099 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7100 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7101 ac_array_in_const32_addr_space(ctx->v4i32), "");
7102 return list;
7103 }
7104
7105 /**
7106 * Build the vertex shader prolog function.
7107 *
7108 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7109 * All inputs are returned unmodified. The vertex load indices are
7110 * stored after them, which will be used by the API VS for fetching inputs.
7111 *
7112 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7113 * input_v0,
7114 * input_v1,
7115 * input_v2,
7116 * input_v3,
7117 * (VertexID + BaseVertex),
7118 * (InstanceID + StartInstance),
7119 * (InstanceID / 2 + StartInstance)
7120 */
7121 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7122 union si_shader_part_key *key)
7123 {
7124 struct si_function_info fninfo;
7125 LLVMTypeRef *returns;
7126 LLVMValueRef ret, func;
7127 int num_returns, i;
7128 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7129 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7130 LLVMValueRef input_vgprs[9];
7131 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7132 num_input_vgprs;
7133 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7134
7135 si_init_function_info(&fninfo);
7136
7137 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7138 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7139 sizeof(LLVMTypeRef));
7140 num_returns = 0;
7141
7142 /* Declare input and output SGPRs. */
7143 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7144 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7145 returns[num_returns++] = ctx->i32;
7146 }
7147
7148 /* Preloaded VGPRs (outputs must be floats) */
7149 for (i = 0; i < num_input_vgprs; i++) {
7150 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7151 returns[num_returns++] = ctx->f32;
7152 }
7153
7154 /* Vertex load indices. */
7155 for (i = 0; i <= key->vs_prolog.last_input; i++)
7156 returns[num_returns++] = ctx->f32;
7157
7158 /* Create the function. */
7159 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7160 func = ctx->main_fn;
7161
7162 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7163 if (!key->vs_prolog.is_monolithic)
7164 si_init_exec_from_input(ctx, 3, 0);
7165
7166 if (key->vs_prolog.as_ls &&
7167 ctx->screen->has_ls_vgpr_init_bug) {
7168 /* If there are no HS threads, SPI loads the LS VGPRs
7169 * starting at VGPR 0. Shift them back to where they
7170 * belong.
7171 */
7172 LLVMValueRef has_hs_threads =
7173 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7174 si_unpack_param(ctx, 3, 8, 8),
7175 ctx->i32_0, "");
7176
7177 for (i = 4; i > 0; --i) {
7178 input_vgprs[i + 1] =
7179 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7180 input_vgprs[i + 1],
7181 input_vgprs[i - 1], "");
7182 }
7183 }
7184 }
7185
7186 unsigned vertex_id_vgpr = first_vs_vgpr;
7187 unsigned instance_id_vgpr = first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7188
7189 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7190 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7191
7192 /* InstanceID = VertexID >> 16;
7193 * VertexID = VertexID & 0xffff;
7194 */
7195 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7196 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7197 LLVMConstInt(ctx->i32, 16, 0), "");
7198 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7199 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7200 }
7201
7202 /* Copy inputs to outputs. This should be no-op, as the registers match,
7203 * but it will prevent the compiler from overwriting them unintentionally.
7204 */
7205 ret = ctx->return_value;
7206 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7207 LLVMValueRef p = LLVMGetParam(func, i);
7208 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7209 }
7210 for (i = 0; i < num_input_vgprs; i++) {
7211 LLVMValueRef p = input_vgprs[i];
7212
7213 if (i == vertex_id_vgpr)
7214 p = ctx->abi.vertex_id;
7215 else if (i == instance_id_vgpr)
7216 p = ctx->abi.instance_id;
7217
7218 p = ac_to_float(&ctx->ac, p);
7219 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7220 key->vs_prolog.num_input_sgprs + i, "");
7221 }
7222
7223 /* Compute vertex load indices from instance divisors. */
7224 LLVMValueRef instance_divisor_constbuf = NULL;
7225
7226 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7227 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7228 LLVMValueRef buf_index =
7229 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7230 instance_divisor_constbuf =
7231 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7232 }
7233
7234 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7235 bool divisor_is_one =
7236 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7237 bool divisor_is_fetched =
7238 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7239 LLVMValueRef index = NULL;
7240
7241 if (divisor_is_one) {
7242 index = ctx->abi.instance_id;
7243 } else if (divisor_is_fetched) {
7244 LLVMValueRef udiv_factors[4];
7245
7246 for (unsigned j = 0; j < 4; j++) {
7247 udiv_factors[j] =
7248 buffer_load_const(ctx, instance_divisor_constbuf,
7249 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7250 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7251 }
7252 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7253 * Such InstanceID might not be achievable in a reasonable time though.
7254 */
7255 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7256 udiv_factors[0], udiv_factors[1],
7257 udiv_factors[2], udiv_factors[3]);
7258 }
7259
7260 if (divisor_is_one || divisor_is_fetched) {
7261 /* Add StartInstance. */
7262 index = LLVMBuildAdd(ctx->ac.builder, index,
7263 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7264 SI_SGPR_START_INSTANCE), "");
7265 } else {
7266 /* VertexID + BaseVertex */
7267 index = LLVMBuildAdd(ctx->ac.builder,
7268 ctx->abi.vertex_id,
7269 LLVMGetParam(func, user_sgpr_base +
7270 SI_SGPR_BASE_VERTEX), "");
7271 }
7272
7273 index = ac_to_float(&ctx->ac, index);
7274 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7275 fninfo.num_params + i, "");
7276 }
7277
7278 si_llvm_build_ret(ctx, ret);
7279 }
7280
7281 static bool si_get_vs_prolog(struct si_screen *sscreen,
7282 struct ac_llvm_compiler *compiler,
7283 struct si_shader *shader,
7284 struct pipe_debug_callback *debug,
7285 struct si_shader *main_part,
7286 const struct si_vs_prolog_bits *key)
7287 {
7288 struct si_shader_selector *vs = main_part->selector;
7289
7290 if (!si_vs_needs_prolog(vs, key))
7291 return true;
7292
7293 /* Get the prolog. */
7294 union si_shader_part_key prolog_key;
7295 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7296 key, shader, &prolog_key);
7297
7298 shader->prolog =
7299 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7300 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7301 debug, si_build_vs_prolog_function,
7302 "Vertex Shader Prolog");
7303 return shader->prolog != NULL;
7304 }
7305
7306 /**
7307 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7308 */
7309 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7310 struct ac_llvm_compiler *compiler,
7311 struct si_shader *shader,
7312 struct pipe_debug_callback *debug)
7313 {
7314 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7315 &shader->key.part.vs.prolog);
7316 }
7317
7318 /**
7319 * Compile the TCS epilog function. This writes tesselation factors to memory
7320 * based on the output primitive type of the tesselator (determined by TES).
7321 */
7322 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7323 union si_shader_part_key *key)
7324 {
7325 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7326 struct si_function_info fninfo;
7327 LLVMValueRef func;
7328
7329 si_init_function_info(&fninfo);
7330
7331 if (ctx->screen->info.chip_class >= GFX9) {
7332 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7333 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7334 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7336 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7340 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7341 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7342 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7343 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7344 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7345 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7346 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7347 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7348 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7349 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7351 } else {
7352 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7353 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7354 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7355 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7356 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7357 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7358 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7359 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7360 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7361 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7362 }
7363
7364 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7365 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7366 unsigned tess_factors_idx =
7367 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7368 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7369 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7370
7371 for (unsigned i = 0; i < 6; i++)
7372 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7373
7374 /* Create the function. */
7375 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7376 ctx->screen->info.chip_class >= GFX7 ? 128 : 64);
7377 ac_declare_lds_as_pointer(&ctx->ac);
7378 func = ctx->main_fn;
7379
7380 LLVMValueRef invoc0_tess_factors[6];
7381 for (unsigned i = 0; i < 6; i++)
7382 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7383
7384 si_write_tess_factors(bld_base,
7385 LLVMGetParam(func, tess_factors_idx),
7386 LLVMGetParam(func, tess_factors_idx + 1),
7387 LLVMGetParam(func, tess_factors_idx + 2),
7388 invoc0_tess_factors, invoc0_tess_factors + 4);
7389
7390 LLVMBuildRetVoid(ctx->ac.builder);
7391 }
7392
7393 /**
7394 * Select and compile (or reuse) TCS parts (epilog).
7395 */
7396 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7397 struct ac_llvm_compiler *compiler,
7398 struct si_shader *shader,
7399 struct pipe_debug_callback *debug)
7400 {
7401 if (sscreen->info.chip_class >= GFX9) {
7402 struct si_shader *ls_main_part =
7403 shader->key.part.tcs.ls->main_shader_part_ls;
7404
7405 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7406 &shader->key.part.tcs.ls_prolog))
7407 return false;
7408
7409 shader->previous_stage = ls_main_part;
7410 }
7411
7412 /* Get the epilog. */
7413 union si_shader_part_key epilog_key;
7414 memset(&epilog_key, 0, sizeof(epilog_key));
7415 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7416
7417 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7418 PIPE_SHADER_TESS_CTRL, false,
7419 &epilog_key, compiler, debug,
7420 si_build_tcs_epilog_function,
7421 "Tessellation Control Shader Epilog");
7422 return shader->epilog != NULL;
7423 }
7424
7425 /**
7426 * Select and compile (or reuse) GS parts (prolog).
7427 */
7428 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7429 struct ac_llvm_compiler *compiler,
7430 struct si_shader *shader,
7431 struct pipe_debug_callback *debug)
7432 {
7433 if (sscreen->info.chip_class >= GFX9) {
7434 struct si_shader *es_main_part =
7435 shader->key.part.gs.es->main_shader_part_es;
7436
7437 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7438 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7439 &shader->key.part.gs.vs_prolog))
7440 return false;
7441
7442 shader->previous_stage = es_main_part;
7443 }
7444
7445 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7446 return true;
7447
7448 union si_shader_part_key prolog_key;
7449 memset(&prolog_key, 0, sizeof(prolog_key));
7450 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7451
7452 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7453 PIPE_SHADER_GEOMETRY, true,
7454 &prolog_key, compiler, debug,
7455 si_build_gs_prolog_function,
7456 "Geometry Shader Prolog");
7457 return shader->prolog2 != NULL;
7458 }
7459
7460 /**
7461 * Build the pixel shader prolog function. This handles:
7462 * - two-side color selection and interpolation
7463 * - overriding interpolation parameters for the API PS
7464 * - polygon stippling
7465 *
7466 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7467 * overriden by other states. (e.g. per-sample interpolation)
7468 * Interpolated colors are stored after the preloaded VGPRs.
7469 */
7470 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7471 union si_shader_part_key *key)
7472 {
7473 struct si_function_info fninfo;
7474 LLVMValueRef ret, func;
7475 int num_returns, i, num_color_channels;
7476
7477 assert(si_need_ps_prolog(key));
7478
7479 si_init_function_info(&fninfo);
7480
7481 /* Declare inputs. */
7482 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7483 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7484
7485 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7486 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7487
7488 /* Declare outputs (same as inputs + add colors if needed) */
7489 num_returns = fninfo.num_params;
7490 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7491 for (i = 0; i < num_color_channels; i++)
7492 fninfo.types[num_returns++] = ctx->f32;
7493
7494 /* Create the function. */
7495 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7496 &fninfo, 0);
7497 func = ctx->main_fn;
7498
7499 /* Copy inputs to outputs. This should be no-op, as the registers match,
7500 * but it will prevent the compiler from overwriting them unintentionally.
7501 */
7502 ret = ctx->return_value;
7503 for (i = 0; i < fninfo.num_params; i++) {
7504 LLVMValueRef p = LLVMGetParam(func, i);
7505 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7506 }
7507
7508 /* Polygon stippling. */
7509 if (key->ps_prolog.states.poly_stipple) {
7510 /* POS_FIXED_PT is always last. */
7511 unsigned pos = key->ps_prolog.num_input_sgprs +
7512 key->ps_prolog.num_input_vgprs - 1;
7513 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7514
7515 si_llvm_emit_polygon_stipple(ctx, list, pos);
7516 }
7517
7518 if (key->ps_prolog.states.bc_optimize_for_persp ||
7519 key->ps_prolog.states.bc_optimize_for_linear) {
7520 unsigned i, base = key->ps_prolog.num_input_sgprs;
7521 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7522
7523 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7524 * The hw doesn't compute CENTROID if the whole wave only
7525 * contains fully-covered quads.
7526 *
7527 * PRIM_MASK is after user SGPRs.
7528 */
7529 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7530 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7531 LLVMConstInt(ctx->i32, 31, 0), "");
7532 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7533 ctx->i1, "");
7534
7535 if (key->ps_prolog.states.bc_optimize_for_persp) {
7536 /* Read PERSP_CENTER. */
7537 for (i = 0; i < 2; i++)
7538 center[i] = LLVMGetParam(func, base + 2 + i);
7539 /* Read PERSP_CENTROID. */
7540 for (i = 0; i < 2; i++)
7541 centroid[i] = LLVMGetParam(func, base + 4 + i);
7542 /* Select PERSP_CENTROID. */
7543 for (i = 0; i < 2; i++) {
7544 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7545 center[i], centroid[i], "");
7546 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7547 tmp, base + 4 + i, "");
7548 }
7549 }
7550 if (key->ps_prolog.states.bc_optimize_for_linear) {
7551 /* Read LINEAR_CENTER. */
7552 for (i = 0; i < 2; i++)
7553 center[i] = LLVMGetParam(func, base + 8 + i);
7554 /* Read LINEAR_CENTROID. */
7555 for (i = 0; i < 2; i++)
7556 centroid[i] = LLVMGetParam(func, base + 10 + i);
7557 /* Select LINEAR_CENTROID. */
7558 for (i = 0; i < 2; i++) {
7559 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7560 center[i], centroid[i], "");
7561 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7562 tmp, base + 10 + i, "");
7563 }
7564 }
7565 }
7566
7567 /* Force per-sample interpolation. */
7568 if (key->ps_prolog.states.force_persp_sample_interp) {
7569 unsigned i, base = key->ps_prolog.num_input_sgprs;
7570 LLVMValueRef persp_sample[2];
7571
7572 /* Read PERSP_SAMPLE. */
7573 for (i = 0; i < 2; i++)
7574 persp_sample[i] = LLVMGetParam(func, base + i);
7575 /* Overwrite PERSP_CENTER. */
7576 for (i = 0; i < 2; i++)
7577 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7578 persp_sample[i], base + 2 + i, "");
7579 /* Overwrite PERSP_CENTROID. */
7580 for (i = 0; i < 2; i++)
7581 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7582 persp_sample[i], base + 4 + i, "");
7583 }
7584 if (key->ps_prolog.states.force_linear_sample_interp) {
7585 unsigned i, base = key->ps_prolog.num_input_sgprs;
7586 LLVMValueRef linear_sample[2];
7587
7588 /* Read LINEAR_SAMPLE. */
7589 for (i = 0; i < 2; i++)
7590 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7591 /* Overwrite LINEAR_CENTER. */
7592 for (i = 0; i < 2; i++)
7593 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7594 linear_sample[i], base + 8 + i, "");
7595 /* Overwrite LINEAR_CENTROID. */
7596 for (i = 0; i < 2; i++)
7597 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7598 linear_sample[i], base + 10 + i, "");
7599 }
7600
7601 /* Force center interpolation. */
7602 if (key->ps_prolog.states.force_persp_center_interp) {
7603 unsigned i, base = key->ps_prolog.num_input_sgprs;
7604 LLVMValueRef persp_center[2];
7605
7606 /* Read PERSP_CENTER. */
7607 for (i = 0; i < 2; i++)
7608 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7609 /* Overwrite PERSP_SAMPLE. */
7610 for (i = 0; i < 2; i++)
7611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7612 persp_center[i], base + i, "");
7613 /* Overwrite PERSP_CENTROID. */
7614 for (i = 0; i < 2; i++)
7615 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7616 persp_center[i], base + 4 + i, "");
7617 }
7618 if (key->ps_prolog.states.force_linear_center_interp) {
7619 unsigned i, base = key->ps_prolog.num_input_sgprs;
7620 LLVMValueRef linear_center[2];
7621
7622 /* Read LINEAR_CENTER. */
7623 for (i = 0; i < 2; i++)
7624 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7625 /* Overwrite LINEAR_SAMPLE. */
7626 for (i = 0; i < 2; i++)
7627 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7628 linear_center[i], base + 6 + i, "");
7629 /* Overwrite LINEAR_CENTROID. */
7630 for (i = 0; i < 2; i++)
7631 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7632 linear_center[i], base + 10 + i, "");
7633 }
7634
7635 /* Interpolate colors. */
7636 unsigned color_out_idx = 0;
7637 for (i = 0; i < 2; i++) {
7638 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7639 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7640 key->ps_prolog.face_vgpr_index;
7641 LLVMValueRef interp[2], color[4];
7642 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7643
7644 if (!writemask)
7645 continue;
7646
7647 /* If the interpolation qualifier is not CONSTANT (-1). */
7648 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7649 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7650 key->ps_prolog.color_interp_vgpr_index[i];
7651
7652 /* Get the (i,j) updated by bc_optimize handling. */
7653 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7654 interp_vgpr, "");
7655 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7656 interp_vgpr + 1, "");
7657 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7658 }
7659
7660 /* Use the absolute location of the input. */
7661 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7662
7663 if (key->ps_prolog.states.color_two_side) {
7664 face = LLVMGetParam(func, face_vgpr);
7665 face = ac_to_integer(&ctx->ac, face);
7666 }
7667
7668 interp_fs_input(ctx,
7669 key->ps_prolog.color_attr_index[i],
7670 TGSI_SEMANTIC_COLOR, i,
7671 key->ps_prolog.num_interp_inputs,
7672 key->ps_prolog.colors_read, interp_ij,
7673 prim_mask, face, color);
7674
7675 while (writemask) {
7676 unsigned chan = u_bit_scan(&writemask);
7677 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7678 fninfo.num_params + color_out_idx++, "");
7679 }
7680 }
7681
7682 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7683 * says:
7684 *
7685 * "When per-sample shading is active due to the use of a fragment
7686 * input qualified by sample or due to the use of the gl_SampleID
7687 * or gl_SamplePosition variables, only the bit for the current
7688 * sample is set in gl_SampleMaskIn. When state specifies multiple
7689 * fragment shader invocations for a given fragment, the sample
7690 * mask for any single fragment shader invocation may specify a
7691 * subset of the covered samples for the fragment. In this case,
7692 * the bit corresponding to each covered sample will be set in
7693 * exactly one fragment shader invocation."
7694 *
7695 * The samplemask loaded by hardware is always the coverage of the
7696 * entire pixel/fragment, so mask bits out based on the sample ID.
7697 */
7698 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7699 /* The bit pattern matches that used by fixed function fragment
7700 * processing. */
7701 static const uint16_t ps_iter_masks[] = {
7702 0xffff, /* not used */
7703 0x5555,
7704 0x1111,
7705 0x0101,
7706 0x0001,
7707 };
7708 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7709
7710 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7711 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7712 key->ps_prolog.ancillary_vgpr_index;
7713 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7714 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7715
7716 samplemask = ac_to_integer(&ctx->ac, samplemask);
7717 samplemask = LLVMBuildAnd(
7718 ctx->ac.builder,
7719 samplemask,
7720 LLVMBuildShl(ctx->ac.builder,
7721 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7722 sampleid, ""),
7723 "");
7724 samplemask = ac_to_float(&ctx->ac, samplemask);
7725
7726 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7727 ancillary_vgpr + 1, "");
7728 }
7729
7730 /* Tell LLVM to insert WQM instruction sequence when needed. */
7731 if (key->ps_prolog.wqm) {
7732 LLVMAddTargetDependentFunctionAttr(func,
7733 "amdgpu-ps-wqm-outputs", "");
7734 }
7735
7736 si_llvm_build_ret(ctx, ret);
7737 }
7738
7739 /**
7740 * Build the pixel shader epilog function. This handles everything that must be
7741 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7742 */
7743 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7744 union si_shader_part_key *key)
7745 {
7746 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7747 struct si_function_info fninfo;
7748 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7749 int i;
7750 struct si_ps_exports exp = {};
7751
7752 si_init_function_info(&fninfo);
7753
7754 /* Declare input SGPRs. */
7755 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7756 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7757 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7758 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7759 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7760
7761 /* Declare input VGPRs. */
7762 unsigned required_num_params =
7763 fninfo.num_sgpr_params +
7764 util_bitcount(key->ps_epilog.colors_written) * 4 +
7765 key->ps_epilog.writes_z +
7766 key->ps_epilog.writes_stencil +
7767 key->ps_epilog.writes_samplemask;
7768
7769 required_num_params = MAX2(required_num_params,
7770 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7771
7772 while (fninfo.num_params < required_num_params)
7773 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7774
7775 /* Create the function. */
7776 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7777 /* Disable elimination of unused inputs. */
7778 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7779 "InitialPSInputAddr", 0xffffff);
7780
7781 /* Process colors. */
7782 unsigned vgpr = fninfo.num_sgpr_params;
7783 unsigned colors_written = key->ps_epilog.colors_written;
7784 int last_color_export = -1;
7785
7786 /* Find the last color export. */
7787 if (!key->ps_epilog.writes_z &&
7788 !key->ps_epilog.writes_stencil &&
7789 !key->ps_epilog.writes_samplemask) {
7790 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7791
7792 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7793 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7794 /* Just set this if any of the colorbuffers are enabled. */
7795 if (spi_format &
7796 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7797 last_color_export = 0;
7798 } else {
7799 for (i = 0; i < 8; i++)
7800 if (colors_written & (1 << i) &&
7801 (spi_format >> (i * 4)) & 0xf)
7802 last_color_export = i;
7803 }
7804 }
7805
7806 while (colors_written) {
7807 LLVMValueRef color[4];
7808 int mrt = u_bit_scan(&colors_written);
7809
7810 for (i = 0; i < 4; i++)
7811 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7812
7813 si_export_mrt_color(bld_base, color, mrt,
7814 fninfo.num_params - 1,
7815 mrt == last_color_export, &exp);
7816 }
7817
7818 /* Process depth, stencil, samplemask. */
7819 if (key->ps_epilog.writes_z)
7820 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7821 if (key->ps_epilog.writes_stencil)
7822 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7823 if (key->ps_epilog.writes_samplemask)
7824 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7825
7826 if (depth || stencil || samplemask)
7827 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7828 else if (last_color_export == -1)
7829 ac_build_export_null(&ctx->ac);
7830
7831 if (exp.num)
7832 si_emit_ps_exports(ctx, &exp);
7833
7834 /* Compile. */
7835 LLVMBuildRetVoid(ctx->ac.builder);
7836 }
7837
7838 /**
7839 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7840 */
7841 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7842 struct ac_llvm_compiler *compiler,
7843 struct si_shader *shader,
7844 struct pipe_debug_callback *debug)
7845 {
7846 union si_shader_part_key prolog_key;
7847 union si_shader_part_key epilog_key;
7848
7849 /* Get the prolog. */
7850 si_get_ps_prolog_key(shader, &prolog_key, true);
7851
7852 /* The prolog is a no-op if these aren't set. */
7853 if (si_need_ps_prolog(&prolog_key)) {
7854 shader->prolog =
7855 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7856 PIPE_SHADER_FRAGMENT, true,
7857 &prolog_key, compiler, debug,
7858 si_build_ps_prolog_function,
7859 "Fragment Shader Prolog");
7860 if (!shader->prolog)
7861 return false;
7862 }
7863
7864 /* Get the epilog. */
7865 si_get_ps_epilog_key(shader, &epilog_key);
7866
7867 shader->epilog =
7868 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7869 PIPE_SHADER_FRAGMENT, false,
7870 &epilog_key, compiler, debug,
7871 si_build_ps_epilog_function,
7872 "Fragment Shader Epilog");
7873 if (!shader->epilog)
7874 return false;
7875
7876 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7877 if (shader->key.part.ps.prolog.poly_stipple) {
7878 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7879 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7880 }
7881
7882 /* Set up the enable bits for per-sample shading if needed. */
7883 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7884 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7885 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7886 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7887 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7888 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7889 }
7890 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7891 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7892 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7893 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7894 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7895 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7896 }
7897 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7898 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7899 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7900 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7901 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7902 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7903 }
7904 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7905 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7906 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7907 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7908 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7909 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7910 }
7911
7912 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7913 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7914 !(shader->config.spi_ps_input_ena & 0xf)) {
7915 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7916 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7917 }
7918
7919 /* At least one pair of interpolation weights must be enabled. */
7920 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7921 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7922 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7923 }
7924
7925 /* Samplemask fixup requires the sample ID. */
7926 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7927 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7928 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7929 }
7930
7931 /* The sample mask input is always enabled, because the API shader always
7932 * passes it through to the epilog. Disable it here if it's unused.
7933 */
7934 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7935 !shader->selector->info.reads_samplemask)
7936 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7937
7938 return true;
7939 }
7940
7941 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7942 unsigned *lds_size)
7943 {
7944 /* If tessellation is all offchip and on-chip GS isn't used, this
7945 * workaround is not needed.
7946 */
7947 return;
7948
7949 /* SPI barrier management bug:
7950 * Make sure we have at least 4k of LDS in use to avoid the bug.
7951 * It applies to workgroup sizes of more than one wavefront.
7952 */
7953 if (sscreen->info.family == CHIP_BONAIRE ||
7954 sscreen->info.family == CHIP_KABINI)
7955 *lds_size = MAX2(*lds_size, 8);
7956 }
7957
7958 static void si_fix_resource_usage(struct si_screen *sscreen,
7959 struct si_shader *shader)
7960 {
7961 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7962
7963 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7964
7965 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7966 si_get_max_workgroup_size(shader) > 64) {
7967 si_multiwave_lds_size_workaround(sscreen,
7968 &shader->config.lds_size);
7969 }
7970 }
7971
7972 bool si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7973 struct si_shader *shader,
7974 struct pipe_debug_callback *debug)
7975 {
7976 struct si_shader_selector *sel = shader->selector;
7977 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7978 int r;
7979
7980 /* LS, ES, VS are compiled on demand if the main part hasn't been
7981 * compiled for that stage.
7982 *
7983 * GS are compiled on demand if the main part hasn't been compiled
7984 * for the chosen NGG-ness.
7985 *
7986 * Vertex shaders are compiled on demand when a vertex fetch
7987 * workaround must be applied.
7988 */
7989 if (shader->is_monolithic) {
7990 /* Monolithic shader (compiled as a whole, has many variants,
7991 * may take a long time to compile).
7992 */
7993 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7994 if (r)
7995 return false;
7996 } else {
7997 /* The shader consists of several parts:
7998 *
7999 * - the middle part is the user shader, it has 1 variant only
8000 * and it was compiled during the creation of the shader
8001 * selector
8002 * - the prolog part is inserted at the beginning
8003 * - the epilog part is inserted at the end
8004 *
8005 * The prolog and epilog have many (but simple) variants.
8006 *
8007 * Starting with gfx9, geometry and tessellation control
8008 * shaders also contain the prolog and user shader parts of
8009 * the previous shader stage.
8010 */
8011
8012 if (!mainp)
8013 return false;
8014
8015 /* Copy the compiled TGSI shader data over. */
8016 shader->is_binary_shared = true;
8017 shader->binary = mainp->binary;
8018 shader->config = mainp->config;
8019 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8020 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8021 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8022 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8023 memcpy(shader->info.vs_output_param_offset,
8024 mainp->info.vs_output_param_offset,
8025 sizeof(mainp->info.vs_output_param_offset));
8026 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8027 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8028 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8029
8030 /* Select prologs and/or epilogs. */
8031 switch (sel->type) {
8032 case PIPE_SHADER_VERTEX:
8033 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8034 return false;
8035 break;
8036 case PIPE_SHADER_TESS_CTRL:
8037 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8038 return false;
8039 break;
8040 case PIPE_SHADER_TESS_EVAL:
8041 break;
8042 case PIPE_SHADER_GEOMETRY:
8043 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8044 return false;
8045 break;
8046 case PIPE_SHADER_FRAGMENT:
8047 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8048 return false;
8049
8050 /* Make sure we have at least as many VGPRs as there
8051 * are allocated inputs.
8052 */
8053 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8054 shader->info.num_input_vgprs);
8055 break;
8056 }
8057
8058 /* Update SGPR and VGPR counts. */
8059 if (shader->prolog) {
8060 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8061 shader->prolog->config.num_sgprs);
8062 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8063 shader->prolog->config.num_vgprs);
8064 }
8065 if (shader->previous_stage) {
8066 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8067 shader->previous_stage->config.num_sgprs);
8068 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8069 shader->previous_stage->config.num_vgprs);
8070 shader->config.spilled_sgprs =
8071 MAX2(shader->config.spilled_sgprs,
8072 shader->previous_stage->config.spilled_sgprs);
8073 shader->config.spilled_vgprs =
8074 MAX2(shader->config.spilled_vgprs,
8075 shader->previous_stage->config.spilled_vgprs);
8076 shader->info.private_mem_vgprs =
8077 MAX2(shader->info.private_mem_vgprs,
8078 shader->previous_stage->info.private_mem_vgprs);
8079 shader->config.scratch_bytes_per_wave =
8080 MAX2(shader->config.scratch_bytes_per_wave,
8081 shader->previous_stage->config.scratch_bytes_per_wave);
8082 shader->info.uses_instanceid |=
8083 shader->previous_stage->info.uses_instanceid;
8084 }
8085 if (shader->prolog2) {
8086 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8087 shader->prolog2->config.num_sgprs);
8088 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8089 shader->prolog2->config.num_vgprs);
8090 }
8091 if (shader->epilog) {
8092 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8093 shader->epilog->config.num_sgprs);
8094 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8095 shader->epilog->config.num_vgprs);
8096 }
8097 si_calculate_max_simd_waves(shader);
8098 }
8099
8100 if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY)
8101 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
8102
8103 si_fix_resource_usage(sscreen, shader);
8104 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8105 stderr, true);
8106
8107 /* Upload. */
8108 if (!si_shader_binary_upload(sscreen, shader, 0)) {
8109 fprintf(stderr, "LLVM failed to upload shader\n");
8110 return false;
8111 }
8112
8113 return true;
8114 }
8115
8116 void si_shader_destroy(struct si_shader *shader)
8117 {
8118 if (shader->scratch_bo)
8119 si_resource_reference(&shader->scratch_bo, NULL);
8120
8121 si_resource_reference(&shader->bo, NULL);
8122
8123 if (!shader->is_binary_shared)
8124 si_shader_binary_clean(&shader->binary);
8125
8126 free(shader->shader_log);
8127 }