2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "radeon/radeon_llvm_emit.h"
38 #include "util/u_memory.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
44 #include "si_shader.h"
49 struct si_shader_output_values
51 LLVMValueRef values
[4];
56 struct si_shader_context
58 struct radeon_llvm_context radeon_bld
;
59 struct tgsi_parse_context parse
;
60 struct tgsi_token
* tokens
;
61 struct si_shader
*shader
;
62 struct si_screen
*screen
;
63 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config
;
65 int param_streamout_write_index
;
66 int param_streamout_offset
[4];
68 int param_instance_id
;
69 LLVMValueRef const_md
;
70 LLVMValueRef const_resource
[SI_NUM_CONST_BUFFERS
];
71 LLVMValueRef ddxy_lds
;
72 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
73 LLVMValueRef resources
[SI_NUM_SAMPLER_VIEWS
];
74 LLVMValueRef samplers
[SI_NUM_SAMPLER_STATES
];
75 LLVMValueRef so_buffers
[4];
76 LLVMValueRef esgs_ring
;
77 LLVMValueRef gsvs_ring
;
78 LLVMValueRef gs_next_vertex
;
81 static struct si_shader_context
* si_shader_context(
82 struct lp_build_tgsi_context
* bld_base
)
84 return (struct si_shader_context
*)bld_base
;
88 #define PERSPECTIVE_BASE 0
91 #define SAMPLE_OFFSET 0
92 #define CENTER_OFFSET 2
93 #define CENTROID_OFSET 4
95 #define USE_SGPR_MAX_SUFFIX_LEN 5
96 #define CONST_ADDR_SPACE 2
97 #define LOCAL_ADDR_SPACE 3
98 #define USER_SGPR_ADDR_SPACE 8
102 #define SENDMSG_GS_DONE 3
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
110 * Returns a unique index for a semantic name and index. The index must be
111 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
114 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
116 switch (semantic_name
) {
117 case TGSI_SEMANTIC_POSITION
:
119 case TGSI_SEMANTIC_PSIZE
:
121 case TGSI_SEMANTIC_CLIPDIST
:
124 case TGSI_SEMANTIC_CLIPVERTEX
:
126 case TGSI_SEMANTIC_COLOR
:
129 case TGSI_SEMANTIC_BCOLOR
:
132 case TGSI_SEMANTIC_FOG
:
134 case TGSI_SEMANTIC_EDGEFLAG
:
136 case TGSI_SEMANTIC_GENERIC
:
137 assert(index
<= 63-11);
146 * Given a semantic name and index of a parameter and a mask of used parameters
147 * (inputs or outputs), return the index of the parameter in the list of all
150 * For example, assume this list of parameters:
151 * POSITION, PSIZE, GENERIC0, GENERIC2
152 * which has the mask:
155 * querying POSITION returns 0,
156 * querying PSIZE returns 1,
157 * querying GENERIC0 returns 2,
158 * querying GENERIC2 returns 3.
160 * Which can be used as an offset to a parameter buffer in units of vec4s.
162 static int get_param_index(unsigned semantic_name
, unsigned index
,
165 unsigned unique_index
= si_shader_io_get_unique_index(semantic_name
, index
);
166 int i
, param_index
= 0;
168 /* If not present... */
169 if (!((1llu << unique_index
) & mask
))
172 for (i
= 0; mask
; i
++) {
173 uint64_t bit
= 1llu << i
;
176 if (i
== unique_index
)
184 assert(!"unreachable");
189 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
190 * It's equivalent to doing a load from &base_ptr[index].
192 * \param base_ptr Where the array starts.
193 * \param index The element index into the array.
195 static LLVMValueRef
build_indexed_load(struct si_shader_context
*si_shader_ctx
,
196 LLVMValueRef base_ptr
, LLVMValueRef index
)
198 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
199 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
200 LLVMValueRef indices
[2], pointer
;
202 indices
[0] = bld_base
->uint_bld
.zero
;
205 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
206 return LLVMBuildLoad(gallivm
->builder
, pointer
, "");
210 * Do a load from &base_ptr[index], but also add a flag that it's loading
213 static LLVMValueRef
build_indexed_load_const(
214 struct si_shader_context
* si_shader_ctx
,
215 LLVMValueRef base_ptr
, LLVMValueRef index
)
217 LLVMValueRef result
= build_indexed_load(si_shader_ctx
, base_ptr
, index
);
218 LLVMSetMetadata(result
, 1, si_shader_ctx
->const_md
);
222 static LLVMValueRef
get_instance_index_for_fetch(
223 struct radeon_llvm_context
* radeon_bld
,
226 struct si_shader_context
*si_shader_ctx
=
227 si_shader_context(&radeon_bld
->soa
.bld_base
);
228 struct gallivm_state
* gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
230 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
231 si_shader_ctx
->param_instance_id
);
232 result
= LLVMBuildAdd(gallivm
->builder
, result
, LLVMGetParam(
233 radeon_bld
->main_fn
, SI_PARAM_START_INSTANCE
), "");
236 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
237 lp_build_const_int32(gallivm
, divisor
), "");
242 static void declare_input_vs(
243 struct radeon_llvm_context
*radeon_bld
,
244 unsigned input_index
,
245 const struct tgsi_full_declaration
*decl
)
247 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
248 struct gallivm_state
*gallivm
= base
->gallivm
;
249 struct si_shader_context
*si_shader_ctx
=
250 si_shader_context(&radeon_bld
->soa
.bld_base
);
251 unsigned divisor
= si_shader_ctx
->shader
->key
.vs
.instance_divisors
[input_index
];
255 LLVMValueRef t_list_ptr
;
256 LLVMValueRef t_offset
;
258 LLVMValueRef attribute_offset
;
259 LLVMValueRef buffer_index
;
260 LLVMValueRef args
[3];
261 LLVMTypeRef vec4_type
;
264 /* Load the T list */
265 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFER
);
267 t_offset
= lp_build_const_int32(gallivm
, input_index
);
269 t_list
= build_indexed_load_const(si_shader_ctx
, t_list_ptr
, t_offset
);
271 /* Build the attribute offset */
272 attribute_offset
= lp_build_const_int32(gallivm
, 0);
275 /* Build index from instance ID, start instance and divisor */
276 si_shader_ctx
->shader
->uses_instanceid
= true;
277 buffer_index
= get_instance_index_for_fetch(&si_shader_ctx
->radeon_bld
, divisor
);
279 /* Load the buffer index for vertices. */
280 LLVMValueRef vertex_id
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
281 si_shader_ctx
->param_vertex_id
);
282 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
283 SI_PARAM_BASE_VERTEX
);
284 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
287 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
289 args
[1] = attribute_offset
;
290 args
[2] = buffer_index
;
291 input
= build_intrinsic(gallivm
->builder
,
292 "llvm.SI.vs.load.input", vec4_type
, args
, 3,
293 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
295 /* Break up the vec4 into individual components */
296 for (chan
= 0; chan
< 4; chan
++) {
297 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
298 /* XXX: Use a helper function for this. There is one in
300 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
301 LLVMBuildExtractElement(gallivm
->builder
,
302 input
, llvm_chan
, "");
306 static LLVMValueRef
fetch_input_gs(
307 struct lp_build_tgsi_context
*bld_base
,
308 const struct tgsi_full_src_register
*reg
,
309 enum tgsi_opcode_type type
,
312 struct lp_build_context
*base
= &bld_base
->base
;
313 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
314 struct si_shader
*shader
= si_shader_ctx
->shader
;
315 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
316 struct gallivm_state
*gallivm
= base
->gallivm
;
317 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
318 LLVMValueRef vtx_offset
;
319 LLVMValueRef args
[9];
320 unsigned vtx_offset_param
;
321 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
322 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
323 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
325 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
) {
327 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
328 SI_PARAM_PRIMITIVE_ID
);
333 if (!reg
->Register
.Dimension
)
337 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
339 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
340 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
342 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
346 /* Get the vertex offset parameter */
347 vtx_offset_param
= reg
->Dimension
.Index
;
348 if (vtx_offset_param
< 2) {
349 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
351 assert(vtx_offset_param
< 6);
352 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
354 vtx_offset
= lp_build_mul_imm(uint
,
355 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
359 args
[0] = si_shader_ctx
->esgs_ring
;
360 args
[1] = vtx_offset
;
361 args
[2] = lp_build_const_int32(gallivm
,
362 (get_param_index(semantic_name
, semantic_index
,
363 shader
->selector
->gs_used_inputs
) * 4 +
365 args
[3] = uint
->zero
;
366 args
[4] = uint
->one
; /* OFFEN */
367 args
[5] = uint
->zero
; /* IDXEN */
368 args
[6] = uint
->one
; /* GLC */
369 args
[7] = uint
->zero
; /* SLC */
370 args
[8] = uint
->zero
; /* TFE */
372 return LLVMBuildBitCast(gallivm
->builder
,
373 build_intrinsic(gallivm
->builder
,
374 "llvm.SI.buffer.load.dword.i32.i32",
376 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
377 tgsi2llvmtype(bld_base
, type
), "");
380 static void declare_input_fs(
381 struct radeon_llvm_context
*radeon_bld
,
382 unsigned input_index
,
383 const struct tgsi_full_declaration
*decl
)
385 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
386 struct si_shader_context
*si_shader_ctx
=
387 si_shader_context(&radeon_bld
->soa
.bld_base
);
388 struct si_shader
*shader
= si_shader_ctx
->shader
;
389 struct lp_build_context
*uint
= &radeon_bld
->soa
.bld_base
.uint_bld
;
390 struct gallivm_state
*gallivm
= base
->gallivm
;
391 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
392 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
394 LLVMValueRef interp_param
;
395 const char * intr_name
;
398 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
399 * quad begins a new primitive. Bit 0 always needs
401 * [32:16] ParamOffset
404 LLVMValueRef params
= LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
405 LLVMValueRef attr_number
;
409 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) {
410 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
412 radeon_llvm_reg_index_soa(input_index
, chan
);
413 radeon_bld
->inputs
[soa_index
] =
414 LLVMGetParam(main_fn
, SI_PARAM_POS_X_FLOAT
+ chan
);
417 /* RCP for fragcoord.w */
418 radeon_bld
->inputs
[soa_index
] =
419 LLVMBuildFDiv(gallivm
->builder
,
420 lp_build_const_float(gallivm
, 1.0f
),
421 radeon_bld
->inputs
[soa_index
],
427 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
428 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
429 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
430 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
431 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
432 lp_build_const_float(gallivm
, 0.0f
);
433 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
434 lp_build_const_float(gallivm
, 1.0f
);
439 shader
->ps_input_param_offset
[input_index
] = shader
->nparam
++;
440 attr_number
= lp_build_const_int32(gallivm
,
441 shader
->ps_input_param_offset
[input_index
]);
443 switch (decl
->Interp
.Interpolate
) {
444 case TGSI_INTERPOLATE_CONSTANT
:
447 case TGSI_INTERPOLATE_LINEAR
:
448 if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
449 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_SAMPLE
);
450 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
451 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTROID
);
453 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTER
);
455 case TGSI_INTERPOLATE_COLOR
:
456 case TGSI_INTERPOLATE_PERSPECTIVE
:
457 if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
458 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_SAMPLE
);
459 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
460 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTROID
);
462 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTER
);
465 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
469 /* fs.constant returns the param from the middle vertex, so it's not
470 * really useful for flat shading. It's meant to be used for custom
471 * interpolation (but the intrinsic can't fetch from the other two
474 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
475 * to do the right thing. The only reason we use fs.constant is that
476 * fs.interp cannot be used on integers, because they can be equal
479 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
481 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
482 si_shader_ctx
->shader
->key
.ps
.color_two_side
) {
483 LLVMValueRef args
[4];
484 LLVMValueRef face
, is_face_positive
;
485 LLVMValueRef back_attr_number
=
486 lp_build_const_int32(gallivm
,
487 shader
->ps_input_param_offset
[input_index
] + 1);
489 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
491 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
493 lp_build_const_float(gallivm
, 0.0f
),
497 args
[3] = interp_param
;
498 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
499 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
500 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
501 LLVMValueRef front
, back
;
504 args
[1] = attr_number
;
505 front
= build_intrinsic(gallivm
->builder
, intr_name
,
506 input_type
, args
, args
[3] ? 4 : 3,
507 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
509 args
[1] = back_attr_number
;
510 back
= build_intrinsic(gallivm
->builder
, intr_name
,
511 input_type
, args
, args
[3] ? 4 : 3,
512 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
514 radeon_bld
->inputs
[soa_index
] =
515 LLVMBuildSelect(gallivm
->builder
,
523 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FOG
) {
524 LLVMValueRef args
[4];
526 args
[0] = uint
->zero
;
527 args
[1] = attr_number
;
529 args
[3] = interp_param
;
530 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
531 build_intrinsic(gallivm
->builder
, intr_name
,
532 input_type
, args
, args
[3] ? 4 : 3,
533 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
534 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
535 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
536 lp_build_const_float(gallivm
, 0.0f
);
537 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
538 lp_build_const_float(gallivm
, 1.0f
);
540 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
541 LLVMValueRef args
[4];
542 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
543 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
545 args
[1] = attr_number
;
547 args
[3] = interp_param
;
548 radeon_bld
->inputs
[soa_index
] =
549 build_intrinsic(gallivm
->builder
, intr_name
,
550 input_type
, args
, args
[3] ? 4 : 3,
551 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
556 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
558 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
559 LLVMValueRef value
= LLVMGetParam(radeon_bld
->main_fn
,
561 value
= LLVMBuildLShr(gallivm
->builder
, value
,
562 lp_build_const_int32(gallivm
, 8), "");
563 value
= LLVMBuildAnd(gallivm
->builder
, value
,
564 lp_build_const_int32(gallivm
, 0xf), "");
569 * Load a dword from a constant buffer.
571 static LLVMValueRef
buffer_load_const(LLVMBuilderRef builder
, LLVMValueRef resource
,
572 LLVMValueRef offset
, LLVMTypeRef return_type
)
574 LLVMValueRef args
[2] = {resource
, offset
};
576 return build_intrinsic(builder
, "llvm.SI.load.const", return_type
, args
, 2,
577 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
580 static void declare_system_value(
581 struct radeon_llvm_context
* radeon_bld
,
583 const struct tgsi_full_declaration
*decl
)
585 struct si_shader_context
*si_shader_ctx
=
586 si_shader_context(&radeon_bld
->soa
.bld_base
);
587 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
588 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
589 LLVMValueRef value
= 0;
591 switch (decl
->Semantic
.Name
) {
592 case TGSI_SEMANTIC_INSTANCEID
:
593 value
= LLVMGetParam(radeon_bld
->main_fn
,
594 si_shader_ctx
->param_instance_id
);
597 case TGSI_SEMANTIC_VERTEXID
:
598 value
= LLVMBuildAdd(gallivm
->builder
,
599 LLVMGetParam(radeon_bld
->main_fn
,
600 si_shader_ctx
->param_vertex_id
),
601 LLVMGetParam(radeon_bld
->main_fn
,
602 SI_PARAM_BASE_VERTEX
), "");
605 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
606 value
= LLVMGetParam(radeon_bld
->main_fn
,
607 si_shader_ctx
->param_vertex_id
);
610 case TGSI_SEMANTIC_BASEVERTEX
:
611 value
= LLVMGetParam(radeon_bld
->main_fn
,
612 SI_PARAM_BASE_VERTEX
);
615 case TGSI_SEMANTIC_SAMPLEID
:
616 value
= get_sample_id(radeon_bld
);
619 case TGSI_SEMANTIC_SAMPLEPOS
:
621 LLVMBuilderRef builder
= gallivm
->builder
;
622 LLVMValueRef desc
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
623 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_DRIVER_STATE_CONST_BUF
);
624 LLVMValueRef resource
= build_indexed_load_const(si_shader_ctx
, desc
, buf_index
);
626 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
627 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, get_sample_id(radeon_bld
), 8);
628 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
630 LLVMValueRef pos
[4] = {
631 buffer_load_const(builder
, resource
, offset0
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
632 buffer_load_const(builder
, resource
, offset1
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
633 lp_build_const_float(gallivm
, 0),
634 lp_build_const_float(gallivm
, 0)
636 value
= lp_build_gather_values(gallivm
, pos
, 4);
641 assert(!"unknown system value");
645 radeon_bld
->system_values
[index
] = value
;
648 static LLVMValueRef
fetch_constant(
649 struct lp_build_tgsi_context
* bld_base
,
650 const struct tgsi_full_src_register
*reg
,
651 enum tgsi_opcode_type type
,
654 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
655 struct lp_build_context
* base
= &bld_base
->base
;
656 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
662 if (swizzle
== LP_CHAN_ALL
) {
664 LLVMValueRef values
[4];
665 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
666 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
668 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
671 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
672 idx
= reg
->Register
.Index
* 4 + swizzle
;
674 if (!reg
->Register
.Indirect
)
675 return bitcast(bld_base
, type
, si_shader_ctx
->constants
[buf
][idx
]);
677 addr
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
678 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
679 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
680 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
681 lp_build_const_int32(base
->gallivm
, idx
* 4));
683 result
= buffer_load_const(base
->gallivm
->builder
, si_shader_ctx
->const_resource
[buf
],
684 addr
, base
->elem_type
);
686 return bitcast(bld_base
, type
, result
);
689 /* Initialize arguments for the shader export intrinsic */
690 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
691 LLVMValueRef
*values
,
695 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
696 struct lp_build_context
*uint
=
697 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
698 struct lp_build_context
*base
= &bld_base
->base
;
699 unsigned compressed
= 0;
702 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
703 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
705 if (cbuf
>= 0 && cbuf
< 8) {
706 compressed
= (si_shader_ctx
->shader
->key
.ps
.export_16bpc
>> cbuf
) & 0x1;
709 si_shader_ctx
->shader
->spi_shader_col_format
|=
710 V_028714_SPI_SHADER_FP16_ABGR
<< (4 * cbuf
);
712 si_shader_ctx
->shader
->spi_shader_col_format
|=
713 V_028714_SPI_SHADER_32_ABGR
<< (4 * cbuf
);
715 si_shader_ctx
->shader
->cb_shader_mask
|= 0xf << (4 * cbuf
);
720 /* Pixel shader needs to pack output values before export */
721 for (chan
= 0; chan
< 2; chan
++ ) {
722 args
[0] = values
[2 * chan
];
723 args
[1] = values
[2 * chan
+ 1];
725 build_intrinsic(base
->gallivm
->builder
,
727 LLVMInt32TypeInContext(base
->gallivm
->context
),
729 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
730 args
[chan
+ 7] = args
[chan
+ 5] =
731 LLVMBuildBitCast(base
->gallivm
->builder
,
733 LLVMFloatTypeInContext(base
->gallivm
->context
),
740 for (chan
= 0; chan
< 4; chan
++ )
741 /* +5 because the first output value will be
742 * the 6th argument to the intrinsic. */
743 args
[chan
+ 5] = values
[chan
];
745 /* Clear COMPR flag */
746 args
[4] = uint
->zero
;
749 /* XXX: This controls which components of the output
750 * registers actually get exported. (e.g bit 0 means export
751 * X component, bit 1 means export Y component, etc.) I'm
752 * hard coding this to 0xf for now. In the future, we might
753 * want to do something else. */
754 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
756 /* Specify whether the EXEC mask represents the valid mask */
757 args
[1] = uint
->zero
;
759 /* Specify whether this is the last export */
760 args
[2] = uint
->zero
;
762 /* Specify the target we are exporting */
763 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
765 /* XXX: We probably need to keep track of the output
766 * values, so we know what we are passing to the next
770 /* Load from output pointers and initialize arguments for the shader export intrinsic */
771 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context
*bld_base
,
772 LLVMValueRef
*out_ptr
,
776 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
777 LLVMValueRef values
[4];
780 for (i
= 0; i
< 4; i
++)
781 values
[i
] = LLVMBuildLoad(gallivm
->builder
, out_ptr
[i
], "");
783 si_llvm_init_export_args(bld_base
, values
, target
, args
);
786 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
787 LLVMValueRef
*out_ptr
)
789 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
790 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
792 if (si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_NEVER
) {
793 LLVMValueRef alpha_ref
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
796 LLVMValueRef alpha_pass
=
797 lp_build_cmp(&bld_base
->base
,
798 si_shader_ctx
->shader
->key
.ps
.alpha_func
,
799 LLVMBuildLoad(gallivm
->builder
, out_ptr
[3], ""),
802 lp_build_select(&bld_base
->base
,
804 lp_build_const_float(gallivm
, 1.0f
),
805 lp_build_const_float(gallivm
, -1.0f
));
807 build_intrinsic(gallivm
->builder
,
809 LLVMVoidTypeInContext(gallivm
->context
),
812 build_intrinsic(gallivm
->builder
,
814 LLVMVoidTypeInContext(gallivm
->context
),
818 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
821 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
* bld_base
,
822 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
824 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
825 struct lp_build_context
*base
= &bld_base
->base
;
826 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
830 LLVMValueRef base_elt
;
831 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
832 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
, SI_DRIVER_STATE_CONST_BUF
);
833 LLVMValueRef const_resource
= build_indexed_load_const(si_shader_ctx
, ptr
, constbuf_index
);
835 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
836 LLVMValueRef
*args
= pos
[2 + reg_index
];
841 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
843 /* Compute dot products of position and user clip plane vectors */
844 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
845 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
846 args
[1] = lp_build_const_int32(base
->gallivm
,
847 ((reg_index
* 4 + chan
) * 4 +
849 base_elt
= buffer_load_const(base
->gallivm
->builder
, const_resource
,
850 args
[1], base
->elem_type
);
852 lp_build_add(base
, args
[5 + chan
],
853 lp_build_mul(base
, base_elt
,
854 out_elts
[const_chan
]));
858 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
859 args
[1] = uint
->zero
;
860 args
[2] = uint
->zero
;
861 args
[3] = lp_build_const_int32(base
->gallivm
,
862 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
863 args
[4] = uint
->zero
;
867 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
872 fprintf(stderr
, "STREAMOUT\n");
874 for (i
= 0; i
< so
->num_outputs
; i
++) {
875 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
876 so
->output
[i
].start_component
;
877 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
878 i
, so
->output
[i
].output_buffer
,
879 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
880 so
->output
[i
].register_index
,
884 mask
& 8 ? "w" : "");
888 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
889 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
890 * or v4i32 (num_channels=3,4). */
891 static void build_tbuffer_store(struct si_shader_context
*shader
,
894 unsigned num_channels
,
896 LLVMValueRef soffset
,
897 unsigned inst_offset
,
906 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
907 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
908 LLVMValueRef args
[] = {
911 LLVMConstInt(i32
, num_channels
, 0),
914 LLVMConstInt(i32
, inst_offset
, 0),
915 LLVMConstInt(i32
, dfmt
, 0),
916 LLVMConstInt(i32
, nfmt
, 0),
917 LLVMConstInt(i32
, offen
, 0),
918 LLVMConstInt(i32
, idxen
, 0),
919 LLVMConstInt(i32
, glc
, 0),
920 LLVMConstInt(i32
, slc
, 0),
921 LLVMConstInt(i32
, tfe
, 0)
924 /* The instruction offset field has 12 bits */
925 assert(offen
|| inst_offset
< (1 << 12));
927 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
928 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
929 const char *types
[] = {"i32", "v2i32", "v4i32"};
931 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
933 lp_build_intrinsic(gallivm
->builder
, name
,
934 LLVMVoidTypeInContext(gallivm
->context
),
935 args
, Elements(args
));
938 static void build_streamout_store(struct si_shader_context
*shader
,
941 unsigned num_channels
,
943 LLVMValueRef soffset
,
944 unsigned inst_offset
)
946 static unsigned dfmt
[] = {
947 V_008F0C_BUF_DATA_FORMAT_32
,
948 V_008F0C_BUF_DATA_FORMAT_32_32
,
949 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
950 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
952 assert(num_channels
>= 1 && num_channels
<= 4);
954 build_tbuffer_store(shader
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
955 inst_offset
, dfmt
[num_channels
-1],
956 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
959 /* On SI, the vertex shader is responsible for writing streamout data
961 static void si_llvm_emit_streamout(struct si_shader_context
*shader
,
962 struct si_shader_output_values
*outputs
,
965 struct pipe_stream_output_info
*so
= &shader
->shader
->selector
->so
;
966 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
967 LLVMBuilderRef builder
= gallivm
->builder
;
969 struct lp_build_if_state if_ctx
;
971 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
973 LLVMValueRef so_param
=
974 LLVMGetParam(shader
->radeon_bld
.main_fn
,
975 shader
->param_streamout_config
);
977 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
978 LLVMValueRef so_vtx_count
=
979 LLVMBuildAnd(builder
,
980 LLVMBuildLShr(builder
, so_param
,
981 LLVMConstInt(i32
, 16, 0), ""),
982 LLVMConstInt(i32
, 127, 0), "");
984 LLVMValueRef tid
= build_intrinsic(builder
, "llvm.SI.tid", i32
,
985 NULL
, 0, LLVMReadNoneAttribute
);
987 /* can_emit = tid < so_vtx_count; */
988 LLVMValueRef can_emit
=
989 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
991 /* Emit the streamout code conditionally. This actually avoids
992 * out-of-bounds buffer access. The hw tells us via the SGPR
993 * (so_vtx_count) which threads are allowed to emit streamout data. */
994 lp_build_if(&if_ctx
, gallivm
, can_emit
);
996 /* The buffer offset is computed as follows:
997 * ByteOffset = streamout_offset[buffer_id]*4 +
998 * (streamout_write_index + thread_id)*stride[buffer_id] +
1002 LLVMValueRef so_write_index
=
1003 LLVMGetParam(shader
->radeon_bld
.main_fn
,
1004 shader
->param_streamout_write_index
);
1006 /* Compute (streamout_write_index + thread_id). */
1007 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
1009 /* Compute the write offset for each enabled buffer. */
1010 LLVMValueRef so_write_offset
[4] = {};
1011 for (i
= 0; i
< 4; i
++) {
1015 LLVMValueRef so_offset
= LLVMGetParam(shader
->radeon_bld
.main_fn
,
1016 shader
->param_streamout_offset
[i
]);
1017 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(i32
, 4, 0), "");
1019 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
1020 LLVMConstInt(i32
, so
->stride
[i
]*4, 0), "");
1021 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
1024 /* Write streamout data. */
1025 for (i
= 0; i
< so
->num_outputs
; i
++) {
1026 unsigned buf_idx
= so
->output
[i
].output_buffer
;
1027 unsigned reg
= so
->output
[i
].register_index
;
1028 unsigned start
= so
->output
[i
].start_component
;
1029 unsigned num_comps
= so
->output
[i
].num_components
;
1030 LLVMValueRef out
[4];
1032 assert(num_comps
&& num_comps
<= 4);
1033 if (!num_comps
|| num_comps
> 4)
1039 /* Load the output as int. */
1040 for (j
= 0; j
< num_comps
; j
++) {
1041 out
[j
] = LLVMBuildBitCast(builder
,
1042 outputs
[reg
].values
[start
+j
],
1046 /* Pack the output. */
1047 LLVMValueRef vdata
= NULL
;
1049 switch (num_comps
) {
1050 case 1: /* as i32 */
1053 case 2: /* as v2i32 */
1054 case 3: /* as v4i32 (aligned to 4) */
1055 case 4: /* as v4i32 */
1056 vdata
= LLVMGetUndef(LLVMVectorType(i32
, util_next_power_of_two(num_comps
)));
1057 for (j
= 0; j
< num_comps
; j
++) {
1058 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
1059 LLVMConstInt(i32
, j
, 0), "");
1064 build_streamout_store(shader
, shader
->so_buffers
[buf_idx
],
1066 so_write_offset
[buf_idx
],
1067 LLVMConstInt(i32
, 0, 0),
1068 so
->output
[i
].dst_offset
*4);
1071 lp_build_endif(&if_ctx
);
1075 /* Generate export instructions for hardware VS shader stage */
1076 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
1077 struct si_shader_output_values
*outputs
,
1080 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1081 struct si_shader
* shader
= si_shader_ctx
->shader
;
1082 struct lp_build_context
* base
= &bld_base
->base
;
1083 struct lp_build_context
* uint
=
1084 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1085 LLVMValueRef args
[9];
1086 LLVMValueRef pos_args
[4][9] = { { 0 } };
1087 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
;
1088 unsigned semantic_name
, semantic_index
;
1090 unsigned param_count
= 0;
1094 if (outputs
&& si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
1095 si_llvm_emit_streamout(si_shader_ctx
, outputs
, noutput
);
1098 for (i
= 0; i
< noutput
; i
++) {
1099 semantic_name
= outputs
[i
].name
;
1100 semantic_index
= outputs
[i
].sid
;
1103 /* Select the correct target */
1104 switch(semantic_name
) {
1105 case TGSI_SEMANTIC_PSIZE
:
1106 psize_value
= outputs
[i
].values
[0];
1108 case TGSI_SEMANTIC_EDGEFLAG
:
1109 edgeflag_value
= outputs
[i
].values
[0];
1111 case TGSI_SEMANTIC_LAYER
:
1112 layer_value
= outputs
[i
].values
[0];
1114 case TGSI_SEMANTIC_POSITION
:
1115 target
= V_008DFC_SQ_EXP_POS
;
1117 case TGSI_SEMANTIC_COLOR
:
1118 case TGSI_SEMANTIC_BCOLOR
:
1119 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1120 shader
->vs_output_param_offset
[i
] = param_count
;
1123 case TGSI_SEMANTIC_CLIPDIST
:
1124 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
1126 case TGSI_SEMANTIC_CLIPVERTEX
:
1127 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
1129 case TGSI_SEMANTIC_PRIMID
:
1130 case TGSI_SEMANTIC_FOG
:
1131 case TGSI_SEMANTIC_GENERIC
:
1132 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1133 shader
->vs_output_param_offset
[i
] = param_count
;
1139 "Warning: SI unhandled vs output type:%d\n",
1143 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
1145 if (target
>= V_008DFC_SQ_EXP_POS
&&
1146 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
1147 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
1148 args
, sizeof(args
));
1150 lp_build_intrinsic(base
->gallivm
->builder
,
1152 LLVMVoidTypeInContext(base
->gallivm
->context
),
1156 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
1157 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1158 goto handle_semantic
;
1162 /* We need to add the position output manually if it's missing. */
1163 if (!pos_args
[0][0]) {
1164 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1165 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
1166 pos_args
[0][2] = uint
->zero
; /* last export? */
1167 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
1168 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
1169 pos_args
[0][5] = base
->zero
; /* X */
1170 pos_args
[0][6] = base
->zero
; /* Y */
1171 pos_args
[0][7] = base
->zero
; /* Z */
1172 pos_args
[0][8] = base
->one
; /* W */
1175 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1176 if (shader
->selector
->info
.writes_psize
||
1177 shader
->selector
->info
.writes_edgeflag
||
1178 shader
->selector
->info
.writes_layer
) {
1179 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
1180 shader
->selector
->info
.writes_psize
|
1181 (shader
->selector
->info
.writes_edgeflag
<< 1) |
1182 (shader
->selector
->info
.writes_layer
<< 2));
1183 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
1184 pos_args
[1][2] = uint
->zero
; /* last export? */
1185 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
1186 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
1187 pos_args
[1][5] = base
->zero
; /* X */
1188 pos_args
[1][6] = base
->zero
; /* Y */
1189 pos_args
[1][7] = base
->zero
; /* Z */
1190 pos_args
[1][8] = base
->zero
; /* W */
1192 if (shader
->selector
->info
.writes_psize
)
1193 pos_args
[1][5] = psize_value
;
1195 if (shader
->selector
->info
.writes_edgeflag
) {
1196 /* The output is a float, but the hw expects an integer
1197 * with the first bit containing the edge flag. */
1198 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
1200 bld_base
->uint_bld
.elem_type
, "");
1201 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
1203 bld_base
->int_bld
.one
);
1205 /* The LLVM intrinsic expects a float. */
1206 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
1208 base
->elem_type
, "");
1211 if (shader
->selector
->info
.writes_layer
)
1212 pos_args
[1][7] = layer_value
;
1215 for (i
= 0; i
< 4; i
++)
1217 shader
->nr_pos_exports
++;
1220 for (i
= 0; i
< 4; i
++) {
1221 if (!pos_args
[i
][0])
1224 /* Specify the target we are exporting */
1225 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
1227 if (pos_idx
== shader
->nr_pos_exports
)
1228 /* Specify that this is the last export */
1229 pos_args
[i
][2] = uint
->one
;
1231 lp_build_intrinsic(base
->gallivm
->builder
,
1233 LLVMVoidTypeInContext(base
->gallivm
->context
),
1238 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
* bld_base
)
1240 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1241 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1242 struct si_shader
*es
= si_shader_ctx
->shader
;
1243 struct tgsi_shader_info
*info
= &es
->selector
->info
;
1244 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1245 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1246 SI_PARAM_ES2GS_OFFSET
);
1250 for (i
= 0; i
< info
->num_outputs
; i
++) {
1251 LLVMValueRef
*out_ptr
=
1252 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
1253 int param_index
= get_param_index(info
->output_semantic_name
[i
],
1254 info
->output_semantic_index
[i
],
1255 es
->key
.vs
.gs_used_inputs
);
1257 if (param_index
< 0)
1260 for (chan
= 0; chan
< 4; chan
++) {
1261 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
1262 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
1264 build_tbuffer_store(si_shader_ctx
,
1265 si_shader_ctx
->esgs_ring
,
1267 LLVMGetUndef(i32
), soffset
,
1268 (4 * param_index
+ chan
) * 4,
1269 V_008F0C_BUF_DATA_FORMAT_32
,
1270 V_008F0C_BUF_NUM_FORMAT_UINT
,
1276 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
1278 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1279 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1280 LLVMValueRef args
[2];
1282 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
1283 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
1284 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
1285 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
1286 LLVMNoUnwindAttribute
);
1289 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1291 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1292 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1293 struct tgsi_shader_info
*info
= &si_shader_ctx
->shader
->selector
->info
;
1294 struct si_shader_output_values
*outputs
= NULL
;
1297 outputs
= MALLOC(info
->num_outputs
* sizeof(outputs
[0]));
1299 for (i
= 0; i
< info
->num_outputs
; i
++) {
1300 outputs
[i
].name
= info
->output_semantic_name
[i
];
1301 outputs
[i
].sid
= info
->output_semantic_index
[i
];
1303 for (j
= 0; j
< 4; j
++)
1304 outputs
[i
].values
[j
] =
1305 LLVMBuildLoad(gallivm
->builder
,
1306 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][j
],
1310 si_llvm_export_vs(bld_base
, outputs
, info
->num_outputs
);
1314 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1316 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1317 struct si_shader
* shader
= si_shader_ctx
->shader
;
1318 struct lp_build_context
* base
= &bld_base
->base
;
1319 struct lp_build_context
* uint
= &bld_base
->uint_bld
;
1320 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1321 LLVMValueRef args
[9];
1322 LLVMValueRef last_args
[9] = { 0 };
1323 int depth_index
= -1, stencil_index
= -1, samplemask_index
= -1;
1326 for (i
= 0; i
< info
->num_outputs
; i
++) {
1327 unsigned semantic_name
= info
->output_semantic_name
[i
];
1328 unsigned semantic_index
= info
->output_semantic_index
[i
];
1331 /* Select the correct target */
1332 switch (semantic_name
) {
1333 case TGSI_SEMANTIC_POSITION
:
1336 case TGSI_SEMANTIC_STENCIL
:
1339 case TGSI_SEMANTIC_SAMPLEMASK
:
1340 samplemask_index
= i
;
1342 case TGSI_SEMANTIC_COLOR
:
1343 target
= V_008DFC_SQ_EXP_MRT
+ semantic_index
;
1344 if (si_shader_ctx
->shader
->key
.ps
.alpha_to_one
)
1345 LLVMBuildStore(bld_base
->base
.gallivm
->builder
,
1347 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][3]);
1349 if (semantic_index
== 0 &&
1350 si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
1351 si_alpha_test(bld_base
,
1352 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
]);
1357 "Warning: SI unhandled fs output type:%d\n",
1361 si_llvm_init_export_args_load(bld_base
,
1362 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
],
1365 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1366 /* If there is an export instruction waiting to be emitted, do so now. */
1368 lp_build_intrinsic(base
->gallivm
->builder
,
1370 LLVMVoidTypeInContext(base
->gallivm
->context
),
1374 /* This instruction will be emitted at the end of the shader. */
1375 memcpy(last_args
, args
, sizeof(args
));
1377 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1378 if (shader
->selector
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1379 semantic_index
== 0 &&
1380 si_shader_ctx
->shader
->key
.ps
.last_cbuf
> 0) {
1381 for (int c
= 1; c
<= si_shader_ctx
->shader
->key
.ps
.last_cbuf
; c
++) {
1382 si_llvm_init_export_args_load(bld_base
,
1383 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
],
1384 V_008DFC_SQ_EXP_MRT
+ c
, args
);
1385 lp_build_intrinsic(base
->gallivm
->builder
,
1387 LLVMVoidTypeInContext(base
->gallivm
->context
),
1392 lp_build_intrinsic(base
->gallivm
->builder
,
1394 LLVMVoidTypeInContext(base
->gallivm
->context
),
1399 if (depth_index
>= 0 || stencil_index
>= 0 || samplemask_index
>= 0) {
1400 LLVMValueRef out_ptr
;
1403 /* Specify the target we are exporting */
1404 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
1406 args
[5] = base
->zero
; /* R, depth */
1407 args
[6] = base
->zero
; /* G, stencil test value[0:7], stencil op value[8:15] */
1408 args
[7] = base
->zero
; /* B, sample mask */
1409 args
[8] = base
->zero
; /* A, alpha to mask */
1411 if (depth_index
>= 0) {
1412 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[depth_index
][2];
1413 args
[5] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1415 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
1418 if (stencil_index
>= 0) {
1419 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[stencil_index
][1];
1420 args
[6] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1422 si_shader_ctx
->shader
->db_shader_control
|=
1423 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1426 if (samplemask_index
>= 0) {
1427 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[samplemask_index
][0];
1428 args
[7] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1430 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(1);
1433 /* SI (except OLAND) has a bug that it only looks
1434 * at the X writemask component. */
1435 if (si_shader_ctx
->screen
->b
.chip_class
== SI
&&
1436 si_shader_ctx
->screen
->b
.family
!= CHIP_OLAND
)
1439 if (samplemask_index
>= 0)
1440 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_ABGR
;
1441 else if (stencil_index
>= 0)
1442 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
1444 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
1446 /* Specify which components to enable */
1447 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
1451 args
[4] = uint
->zero
;
1454 lp_build_intrinsic(base
->gallivm
->builder
,
1456 LLVMVoidTypeInContext(base
->gallivm
->context
),
1459 memcpy(last_args
, args
, sizeof(args
));
1462 if (!last_args
[0]) {
1463 /* Specify which components to enable */
1464 last_args
[0] = lp_build_const_int32(base
->gallivm
, 0x0);
1466 /* Specify the target we are exporting */
1467 last_args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRT
);
1469 /* Set COMPR flag to zero to export data as 32-bit */
1470 last_args
[4] = uint
->zero
;
1473 last_args
[5]= uint
->zero
;
1474 last_args
[6]= uint
->zero
;
1475 last_args
[7]= uint
->zero
;
1476 last_args
[8]= uint
->zero
;
1479 /* Specify whether the EXEC mask represents the valid mask */
1480 last_args
[1] = uint
->one
;
1482 /* Specify that this is the last export */
1483 last_args
[2] = lp_build_const_int32(base
->gallivm
, 1);
1485 lp_build_intrinsic(base
->gallivm
->builder
,
1487 LLVMVoidTypeInContext(base
->gallivm
->context
),
1491 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1492 struct lp_build_tgsi_context
* bld_base
,
1493 struct lp_build_emit_data
* emit_data
);
1495 static bool tgsi_is_shadow_sampler(unsigned target
)
1497 return target
== TGSI_TEXTURE_SHADOW1D
||
1498 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1499 target
== TGSI_TEXTURE_SHADOW2D
||
1500 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1501 target
== TGSI_TEXTURE_SHADOWCUBE
||
1502 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
1503 target
== TGSI_TEXTURE_SHADOWRECT
;
1506 static const struct lp_build_tgsi_action tex_action
;
1508 static void tex_fetch_args(
1509 struct lp_build_tgsi_context
* bld_base
,
1510 struct lp_build_emit_data
* emit_data
)
1512 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1513 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1514 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
1515 unsigned opcode
= inst
->Instruction
.Opcode
;
1516 unsigned target
= inst
->Texture
.Texture
;
1517 LLVMValueRef coords
[4];
1518 LLVMValueRef address
[16];
1520 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
, &ref_pos
);
1523 unsigned sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1524 unsigned sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
1525 bool has_offset
= HAVE_LLVM
>= 0x0305 ? inst
->Texture
.NumOffsets
> 0 : false;
1527 if (target
== TGSI_TEXTURE_BUFFER
) {
1528 LLVMTypeRef i128
= LLVMIntTypeInContext(gallivm
->context
, 128);
1529 LLVMTypeRef v2i128
= LLVMVectorType(i128
, 2);
1530 LLVMTypeRef i8
= LLVMInt8TypeInContext(gallivm
->context
);
1531 LLVMTypeRef v16i8
= LLVMVectorType(i8
, 16);
1533 /* Bitcast and truncate v8i32 to v16i8. */
1534 LLVMValueRef res
= si_shader_ctx
->resources
[sampler_index
];
1535 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
1536 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.zero
, "");
1537 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v16i8
, "");
1539 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
1540 emit_data
->args
[0] = res
;
1541 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
1542 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
1543 emit_data
->arg_count
= 3;
1547 /* Fetch and project texture coordinates */
1548 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1549 for (chan
= 0; chan
< 3; chan
++ ) {
1550 coords
[chan
] = lp_build_emit_fetch(bld_base
,
1553 if (opcode
== TGSI_OPCODE_TXP
)
1554 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1560 if (opcode
== TGSI_OPCODE_TXP
)
1561 coords
[3] = bld_base
->base
.one
;
1564 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
1565 /* The offsets are six-bit signed integers packed like this:
1566 * X=[5:0], Y=[13:8], and Z=[21:16].
1568 LLVMValueRef offset
[3], pack
;
1570 assert(inst
->Texture
.NumOffsets
== 1);
1572 for (chan
= 0; chan
< 3; chan
++) {
1573 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1574 emit_data
->inst
, 0, chan
);
1575 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
1576 lp_build_const_int32(gallivm
, 0x3f), "");
1578 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
1579 lp_build_const_int32(gallivm
, chan
*8), "");
1582 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
1583 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
1584 address
[count
++] = pack
;
1587 /* Pack LOD bias value */
1588 if (opcode
== TGSI_OPCODE_TXB
)
1589 address
[count
++] = coords
[3];
1590 if (opcode
== TGSI_OPCODE_TXB2
)
1591 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1593 /* Pack depth comparison value */
1594 if (tgsi_is_shadow_sampler(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1595 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1596 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1598 assert(ref_pos
>= 0);
1599 address
[count
++] = coords
[ref_pos
];
1603 if (target
== TGSI_TEXTURE_CUBE
||
1604 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1605 target
== TGSI_TEXTURE_SHADOWCUBE
||
1606 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1607 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
1609 /* Pack user derivatives */
1610 if (opcode
== TGSI_OPCODE_TXD
) {
1611 int num_deriv_channels
, param
;
1614 case TGSI_TEXTURE_3D
:
1615 num_deriv_channels
= 3;
1617 case TGSI_TEXTURE_2D
:
1618 case TGSI_TEXTURE_SHADOW2D
:
1619 case TGSI_TEXTURE_RECT
:
1620 case TGSI_TEXTURE_SHADOWRECT
:
1621 case TGSI_TEXTURE_2D_ARRAY
:
1622 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1623 case TGSI_TEXTURE_CUBE
:
1624 case TGSI_TEXTURE_SHADOWCUBE
:
1625 case TGSI_TEXTURE_CUBE_ARRAY
:
1626 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1627 num_deriv_channels
= 2;
1629 case TGSI_TEXTURE_1D
:
1630 case TGSI_TEXTURE_SHADOW1D
:
1631 case TGSI_TEXTURE_1D_ARRAY
:
1632 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1633 num_deriv_channels
= 1;
1636 assert(0); /* no other targets are valid here */
1639 for (param
= 1; param
<= 2; param
++)
1640 for (chan
= 0; chan
< num_deriv_channels
; chan
++)
1641 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, param
, chan
);
1644 /* Pack texture coordinates */
1645 address
[count
++] = coords
[0];
1647 address
[count
++] = coords
[1];
1649 address
[count
++] = coords
[2];
1651 /* Pack LOD or sample index */
1652 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
1653 address
[count
++] = coords
[3];
1654 else if (opcode
== TGSI_OPCODE_TXL2
)
1655 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1658 assert(!"Cannot handle more than 16 texture address parameters");
1662 for (chan
= 0; chan
< count
; chan
++ ) {
1663 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
1665 LLVMInt32TypeInContext(gallivm
->context
),
1669 /* Adjust the sample index according to FMASK.
1671 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1672 * which is the identity mapping. Each nibble says which physical sample
1673 * should be fetched to get that sample.
1675 * For example, 0x11111100 means there are only 2 samples stored and
1676 * the second sample covers 3/4 of the pixel. When reading samples 0
1677 * and 1, return physical sample 0 (determined by the first two 0s
1678 * in FMASK), otherwise return physical sample 1.
1680 * The sample index should be adjusted as follows:
1681 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1683 if (target
== TGSI_TEXTURE_2D_MSAA
||
1684 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1685 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1686 struct lp_build_emit_data txf_emit_data
= *emit_data
;
1687 LLVMValueRef txf_address
[4];
1688 unsigned txf_count
= count
;
1689 struct tgsi_full_instruction inst
= {};
1691 memcpy(txf_address
, address
, sizeof(txf_address
));
1693 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1694 txf_address
[2] = bld_base
->uint_bld
.zero
;
1696 txf_address
[3] = bld_base
->uint_bld
.zero
;
1698 /* Pad to a power-of-two size. */
1699 while (txf_count
< util_next_power_of_two(txf_count
))
1700 txf_address
[txf_count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1702 /* Read FMASK using TXF. */
1703 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
1704 inst
.Texture
.Texture
= target
== TGSI_TEXTURE_2D_MSAA
? TGSI_TEXTURE_2D
: TGSI_TEXTURE_2D_ARRAY
;
1705 txf_emit_data
.inst
= &inst
;
1706 txf_emit_data
.chan
= 0;
1707 txf_emit_data
.dst_type
= LLVMVectorType(
1708 LLVMInt32TypeInContext(gallivm
->context
), 4);
1709 txf_emit_data
.args
[0] = lp_build_gather_values(gallivm
, txf_address
, txf_count
);
1710 txf_emit_data
.args
[1] = si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
];
1711 txf_emit_data
.args
[2] = lp_build_const_int32(gallivm
, inst
.Texture
.Texture
);
1712 txf_emit_data
.arg_count
= 3;
1714 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
1716 /* Initialize some constants. */
1717 LLVMValueRef four
= LLVMConstInt(uint_bld
->elem_type
, 4, 0);
1718 LLVMValueRef F
= LLVMConstInt(uint_bld
->elem_type
, 0xF, 0);
1720 /* Apply the formula. */
1721 LLVMValueRef fmask
=
1722 LLVMBuildExtractElement(gallivm
->builder
,
1723 txf_emit_data
.output
[0],
1724 uint_bld
->zero
, "");
1726 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
1728 LLVMValueRef sample_index4
=
1729 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
1731 LLVMValueRef shifted_fmask
=
1732 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
1734 LLVMValueRef final_sample
=
1735 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
1737 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1738 * resource descriptor is 0 (invalid),
1740 LLVMValueRef fmask_desc
=
1741 LLVMBuildBitCast(gallivm
->builder
,
1742 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
],
1743 LLVMVectorType(uint_bld
->elem_type
, 8), "");
1745 LLVMValueRef fmask_word1
=
1746 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
1749 LLVMValueRef word1_is_nonzero
=
1750 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1751 fmask_word1
, uint_bld
->zero
, "");
1753 /* Replace the MSAA sample index. */
1754 address
[sample_chan
] =
1755 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
1756 final_sample
, address
[sample_chan
], "");
1760 emit_data
->args
[1] = si_shader_ctx
->resources
[sampler_index
];
1762 if (opcode
== TGSI_OPCODE_TXF
) {
1763 /* add tex offsets */
1764 if (inst
->Texture
.NumOffsets
) {
1765 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1766 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
1767 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
1769 assert(inst
->Texture
.NumOffsets
== 1);
1772 case TGSI_TEXTURE_3D
:
1773 address
[2] = lp_build_add(uint_bld
, address
[2],
1774 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
1776 case TGSI_TEXTURE_2D
:
1777 case TGSI_TEXTURE_SHADOW2D
:
1778 case TGSI_TEXTURE_RECT
:
1779 case TGSI_TEXTURE_SHADOWRECT
:
1780 case TGSI_TEXTURE_2D_ARRAY
:
1781 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1783 lp_build_add(uint_bld
, address
[1],
1784 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
1786 case TGSI_TEXTURE_1D
:
1787 case TGSI_TEXTURE_SHADOW1D
:
1788 case TGSI_TEXTURE_1D_ARRAY
:
1789 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1791 lp_build_add(uint_bld
, address
[0],
1792 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
1794 /* texture offsets do not apply to other texture targets */
1798 emit_data
->args
[2] = lp_build_const_int32(gallivm
, target
);
1799 emit_data
->arg_count
= 3;
1801 emit_data
->dst_type
= LLVMVectorType(
1802 LLVMInt32TypeInContext(gallivm
->context
),
1804 } else if (opcode
== TGSI_OPCODE_TG4
||
1805 opcode
== TGSI_OPCODE_LODQ
||
1807 unsigned is_array
= target
== TGSI_TEXTURE_1D_ARRAY
||
1808 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1809 target
== TGSI_TEXTURE_2D_ARRAY
||
1810 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1811 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1812 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
1813 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
1814 unsigned dmask
= 0xf;
1816 if (opcode
== TGSI_OPCODE_TG4
) {
1817 unsigned gather_comp
= 0;
1819 /* DMASK was repurposed for GATHER4. 4 components are always
1820 * returned and DMASK works like a swizzle - it selects
1821 * the component to fetch. The only valid DMASK values are
1822 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1823 * (red,red,red,red) etc.) The ISA document doesn't mention
1827 /* Get the component index from src1.x for Gather4. */
1828 if (!tgsi_is_shadow_sampler(target
)) {
1829 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
1830 LLVMValueRef comp_imm
;
1831 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1833 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1835 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
1836 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1837 gather_comp
= CLAMP(gather_comp
, 0, 3);
1840 dmask
= 1 << gather_comp
;
1843 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1844 emit_data
->args
[3] = lp_build_const_int32(gallivm
, dmask
);
1845 emit_data
->args
[4] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
1846 emit_data
->args
[5] = lp_build_const_int32(gallivm
, 0); /* r128 */
1847 emit_data
->args
[6] = lp_build_const_int32(gallivm
, is_array
); /* da */
1848 emit_data
->args
[7] = lp_build_const_int32(gallivm
, 0); /* glc */
1849 emit_data
->args
[8] = lp_build_const_int32(gallivm
, 0); /* slc */
1850 emit_data
->args
[9] = lp_build_const_int32(gallivm
, 0); /* tfe */
1851 emit_data
->args
[10] = lp_build_const_int32(gallivm
, 0); /* lwe */
1853 emit_data
->arg_count
= 11;
1855 emit_data
->dst_type
= LLVMVectorType(
1856 LLVMFloatTypeInContext(gallivm
->context
),
1859 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1860 emit_data
->args
[3] = lp_build_const_int32(gallivm
, target
);
1861 emit_data
->arg_count
= 4;
1863 emit_data
->dst_type
= LLVMVectorType(
1864 LLVMFloatTypeInContext(gallivm
->context
),
1868 /* The fetch opcode has been converted to a 2D array fetch.
1869 * This simplifies the LLVM backend. */
1870 if (target
== TGSI_TEXTURE_CUBE_ARRAY
)
1871 target
= TGSI_TEXTURE_2D_ARRAY
;
1872 else if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1873 target
= TGSI_TEXTURE_SHADOW2D_ARRAY
;
1875 /* Pad to power of two vector */
1876 while (count
< util_next_power_of_two(count
))
1877 address
[count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1879 emit_data
->args
[0] = lp_build_gather_values(gallivm
, address
, count
);
1882 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1883 struct lp_build_tgsi_context
* bld_base
,
1884 struct lp_build_emit_data
* emit_data
)
1886 struct lp_build_context
* base
= &bld_base
->base
;
1887 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
1888 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1889 char intr_name
[127];
1890 bool has_offset
= HAVE_LLVM
>= 0x0305 ?
1891 emit_data
->inst
->Texture
.NumOffsets
> 0 : false;
1893 if (target
== TGSI_TEXTURE_BUFFER
) {
1894 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1895 base
->gallivm
->builder
,
1896 "llvm.SI.vs.load.input", emit_data
->dst_type
,
1897 emit_data
->args
, emit_data
->arg_count
,
1898 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1902 if (opcode
== TGSI_OPCODE_TG4
||
1903 opcode
== TGSI_OPCODE_LODQ
||
1904 (opcode
!= TGSI_OPCODE_TXF
&& has_offset
)) {
1905 bool is_shadow
= tgsi_is_shadow_sampler(target
);
1906 const char *name
= "llvm.SI.image.sample";
1907 const char *infix
= "";
1910 case TGSI_OPCODE_TEX
:
1911 case TGSI_OPCODE_TEX2
:
1912 case TGSI_OPCODE_TXP
:
1914 case TGSI_OPCODE_TXB
:
1915 case TGSI_OPCODE_TXB2
:
1918 case TGSI_OPCODE_TXL
:
1919 case TGSI_OPCODE_TXL2
:
1922 case TGSI_OPCODE_TXD
:
1925 case TGSI_OPCODE_TG4
:
1926 name
= "llvm.SI.gather4";
1928 case TGSI_OPCODE_LODQ
:
1929 name
= "llvm.SI.getlod";
1938 /* Add the type and suffixes .c, .o if needed. */
1939 sprintf(intr_name
, "%s%s%s%s.v%ui32", name
,
1940 is_shadow
? ".c" : "", infix
, has_offset
? ".o" : "",
1941 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
1943 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1944 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
1945 emit_data
->args
, emit_data
->arg_count
,
1946 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1948 LLVMTypeRef i8
, v16i8
, v32i8
;
1952 case TGSI_OPCODE_TEX
:
1953 case TGSI_OPCODE_TEX2
:
1954 case TGSI_OPCODE_TXP
:
1955 name
= "llvm.SI.sample";
1957 case TGSI_OPCODE_TXB
:
1958 case TGSI_OPCODE_TXB2
:
1959 name
= "llvm.SI.sampleb";
1961 case TGSI_OPCODE_TXD
:
1962 name
= "llvm.SI.sampled";
1964 case TGSI_OPCODE_TXF
:
1965 name
= "llvm.SI.imageload";
1967 case TGSI_OPCODE_TXL
:
1968 case TGSI_OPCODE_TXL2
:
1969 name
= "llvm.SI.samplel";
1976 i8
= LLVMInt8TypeInContext(base
->gallivm
->context
);
1977 v16i8
= LLVMVectorType(i8
, 16);
1978 v32i8
= LLVMVectorType(i8
, 32);
1980 emit_data
->args
[1] = LLVMBuildBitCast(base
->gallivm
->builder
,
1981 emit_data
->args
[1], v32i8
, "");
1982 if (opcode
!= TGSI_OPCODE_TXF
) {
1983 emit_data
->args
[2] = LLVMBuildBitCast(base
->gallivm
->builder
,
1984 emit_data
->args
[2], v16i8
, "");
1987 sprintf(intr_name
, "%s.v%ui32", name
,
1988 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
1990 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1991 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
1992 emit_data
->args
, emit_data
->arg_count
,
1993 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1997 static void txq_fetch_args(
1998 struct lp_build_tgsi_context
* bld_base
,
1999 struct lp_build_emit_data
* emit_data
)
2001 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2002 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2003 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2004 unsigned target
= inst
->Texture
.Texture
;
2006 if (target
== TGSI_TEXTURE_BUFFER
) {
2007 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2008 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
2010 /* Read the size from the buffer descriptor directly. */
2011 LLVMValueRef size
= si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2012 size
= LLVMBuildBitCast(gallivm
->builder
, size
, v8i32
, "");
2013 size
= LLVMBuildExtractElement(gallivm
->builder
, size
,
2014 lp_build_const_int32(gallivm
, 2), "");
2015 emit_data
->args
[0] = size
;
2020 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
2023 emit_data
->args
[1] = si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2025 /* Texture target */
2026 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2027 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
2028 target
= TGSI_TEXTURE_2D_ARRAY
;
2030 emit_data
->args
[2] = lp_build_const_int32(bld_base
->base
.gallivm
,
2033 emit_data
->arg_count
= 3;
2035 emit_data
->dst_type
= LLVMVectorType(
2036 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
),
2040 static void build_txq_intrinsic(const struct lp_build_tgsi_action
* action
,
2041 struct lp_build_tgsi_context
* bld_base
,
2042 struct lp_build_emit_data
* emit_data
)
2044 unsigned target
= emit_data
->inst
->Texture
.Texture
;
2046 if (target
== TGSI_TEXTURE_BUFFER
) {
2047 /* Just return the buffer size. */
2048 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
2052 build_tgsi_intrinsic_nomem(action
, bld_base
, emit_data
);
2054 /* Divide the number of layers by 6 to get the number of cubes. */
2055 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2056 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
2057 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2058 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
2059 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
2061 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
2062 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
2063 z
= LLVMBuildSDiv(builder
, z
, six
, "");
2065 emit_data
->output
[emit_data
->chan
] =
2066 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
2070 static void si_llvm_emit_ddxy(
2071 const struct lp_build_tgsi_action
* action
,
2072 struct lp_build_tgsi_context
* bld_base
,
2073 struct lp_build_emit_data
* emit_data
)
2075 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2076 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2077 struct lp_build_context
* base
= &bld_base
->base
;
2078 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2079 unsigned opcode
= inst
->Instruction
.Opcode
;
2080 LLVMValueRef indices
[2];
2081 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
2082 LLVMValueRef tl
, trbl
, result
[4];
2084 unsigned swizzle
[4];
2087 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2089 indices
[0] = bld_base
->uint_bld
.zero
;
2090 indices
[1] = build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
2091 NULL
, 0, LLVMReadNoneAttribute
);
2092 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2095 indices
[1] = LLVMBuildAnd(gallivm
->builder
, indices
[1],
2096 lp_build_const_int32(gallivm
, 0xfffffffc), "");
2097 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2100 indices
[1] = LLVMBuildAdd(gallivm
->builder
, indices
[1],
2101 lp_build_const_int32(gallivm
,
2102 opcode
== TGSI_OPCODE_DDX
? 1 : 2),
2104 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2107 for (c
= 0; c
< 4; ++c
) {
2110 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
2111 for (i
= 0; i
< c
; ++i
) {
2112 if (swizzle
[i
] == swizzle
[c
]) {
2113 result
[c
] = result
[i
];
2120 LLVMBuildStore(gallivm
->builder
,
2121 LLVMBuildBitCast(gallivm
->builder
,
2122 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
2126 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
2127 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
2129 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
2130 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, base
->elem_type
, "");
2132 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
2135 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
2138 /* Emit one vertex from the geometry shader */
2139 static void si_llvm_emit_vertex(
2140 const struct lp_build_tgsi_action
*action
,
2141 struct lp_build_tgsi_context
*bld_base
,
2142 struct lp_build_emit_data
*emit_data
)
2144 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2145 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2146 struct si_shader
*shader
= si_shader_ctx
->shader
;
2147 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2148 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2149 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2150 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2151 SI_PARAM_GS2VS_OFFSET
);
2152 LLVMValueRef gs_next_vertex
;
2153 LLVMValueRef can_emit
, kill
;
2154 LLVMValueRef args
[2];
2158 /* Write vertex attribute values to GSVS ring */
2159 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
, si_shader_ctx
->gs_next_vertex
, "");
2161 /* If this thread has already emitted the declared maximum number of
2162 * vertices, kill it: excessive vertex emissions are not supposed to
2163 * have any effect, and GS threads have no externally observable
2164 * effects other than emitting vertices.
2166 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
2167 lp_build_const_int32(gallivm
,
2168 shader
->selector
->gs_max_out_vertices
), "");
2169 kill
= lp_build_select(&bld_base
->base
, can_emit
,
2170 lp_build_const_float(gallivm
, 1.0f
),
2171 lp_build_const_float(gallivm
, -1.0f
));
2172 build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2173 LLVMVoidTypeInContext(gallivm
->context
), &kill
, 1, 0);
2175 for (i
= 0; i
< info
->num_outputs
; i
++) {
2176 LLVMValueRef
*out_ptr
=
2177 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
2179 for (chan
= 0; chan
< 4; chan
++) {
2180 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2181 LLVMValueRef voffset
=
2182 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
2183 shader
->selector
->gs_max_out_vertices
);
2185 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
2186 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
2188 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
2190 build_tbuffer_store(si_shader_ctx
,
2191 si_shader_ctx
->gsvs_ring
,
2193 voffset
, soffset
, 0,
2194 V_008F0C_BUF_DATA_FORMAT_32
,
2195 V_008F0C_BUF_NUM_FORMAT_UINT
,
2199 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
2200 lp_build_const_int32(gallivm
, 1));
2201 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, si_shader_ctx
->gs_next_vertex
);
2203 /* Signal vertex emission */
2204 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
);
2205 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2206 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2207 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2208 LLVMNoUnwindAttribute
);
2211 /* Cut one primitive from the geometry shader */
2212 static void si_llvm_emit_primitive(
2213 const struct lp_build_tgsi_action
*action
,
2214 struct lp_build_tgsi_context
*bld_base
,
2215 struct lp_build_emit_data
*emit_data
)
2217 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2218 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2219 LLVMValueRef args
[2];
2221 /* Signal primitive cut */
2222 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
);
2223 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2224 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2225 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2226 LLVMNoUnwindAttribute
);
2229 static const struct lp_build_tgsi_action tex_action
= {
2230 .fetch_args
= tex_fetch_args
,
2231 .emit
= build_tex_intrinsic
,
2234 static const struct lp_build_tgsi_action txq_action
= {
2235 .fetch_args
= txq_fetch_args
,
2236 .emit
= build_txq_intrinsic
,
2237 .intr_name
= "llvm.SI.resinfo"
2240 static void create_meta_data(struct si_shader_context
*si_shader_ctx
)
2242 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
2243 LLVMValueRef args
[3];
2245 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
2247 args
[2] = lp_build_const_int32(gallivm
, 1);
2249 si_shader_ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
2252 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
2254 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
2258 static void create_function(struct si_shader_context
*si_shader_ctx
)
2260 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2261 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2262 struct si_shader
*shader
= si_shader_ctx
->shader
;
2263 LLVMTypeRef params
[SI_NUM_PARAMS
], f32
, i8
, i32
, v2i32
, v3i32
, v16i8
, v4i32
, v8i32
;
2264 unsigned i
, last_array_pointer
, last_sgpr
, num_params
;
2266 i8
= LLVMInt8TypeInContext(gallivm
->context
);
2267 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2268 f32
= LLVMFloatTypeInContext(gallivm
->context
);
2269 v2i32
= LLVMVectorType(i32
, 2);
2270 v3i32
= LLVMVectorType(i32
, 3);
2271 v4i32
= LLVMVectorType(i32
, 4);
2272 v8i32
= LLVMVectorType(i32
, 8);
2273 v16i8
= LLVMVectorType(i8
, 16);
2275 params
[SI_PARAM_RW_BUFFERS
] = const_array(v16i8
, SI_NUM_RW_BUFFERS
);
2276 params
[SI_PARAM_CONST
] = const_array(v16i8
, SI_NUM_CONST_BUFFERS
);
2277 params
[SI_PARAM_SAMPLER
] = const_array(v4i32
, SI_NUM_SAMPLER_STATES
);
2278 params
[SI_PARAM_RESOURCE
] = const_array(v8i32
, SI_NUM_SAMPLER_VIEWS
);
2279 last_array_pointer
= SI_PARAM_RESOURCE
;
2281 switch (si_shader_ctx
->type
) {
2282 case TGSI_PROCESSOR_VERTEX
:
2283 params
[SI_PARAM_VERTEX_BUFFER
] = const_array(v16i8
, SI_NUM_VERTEX_BUFFERS
);
2284 last_array_pointer
= SI_PARAM_VERTEX_BUFFER
;
2285 params
[SI_PARAM_BASE_VERTEX
] = i32
;
2286 params
[SI_PARAM_START_INSTANCE
] = i32
;
2287 num_params
= SI_PARAM_START_INSTANCE
+1;
2289 if (shader
->key
.vs
.as_es
) {
2290 params
[SI_PARAM_ES2GS_OFFSET
] = i32
;
2293 if (shader
->is_gs_copy_shader
) {
2294 last_array_pointer
= SI_PARAM_CONST
;
2295 num_params
= SI_PARAM_CONST
+1;
2298 /* The locations of the other parameters are assigned dynamically. */
2300 /* Streamout SGPRs. */
2301 if (shader
->selector
->so
.num_outputs
) {
2302 params
[si_shader_ctx
->param_streamout_config
= num_params
++] = i32
;
2303 params
[si_shader_ctx
->param_streamout_write_index
= num_params
++] = i32
;
2305 /* A streamout buffer offset is loaded if the stride is non-zero. */
2306 for (i
= 0; i
< 4; i
++) {
2307 if (!shader
->selector
->so
.stride
[i
])
2310 params
[si_shader_ctx
->param_streamout_offset
[i
] = num_params
++] = i32
;
2314 last_sgpr
= num_params
-1;
2317 params
[si_shader_ctx
->param_vertex_id
= num_params
++] = i32
;
2318 params
[num_params
++] = i32
; /* unused*/
2319 params
[num_params
++] = i32
; /* unused */
2320 params
[si_shader_ctx
->param_instance_id
= num_params
++] = i32
;
2323 case TGSI_PROCESSOR_GEOMETRY
:
2324 params
[SI_PARAM_GS2VS_OFFSET
] = i32
;
2325 params
[SI_PARAM_GS_WAVE_ID
] = i32
;
2326 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
2329 params
[SI_PARAM_VTX0_OFFSET
] = i32
;
2330 params
[SI_PARAM_VTX1_OFFSET
] = i32
;
2331 params
[SI_PARAM_PRIMITIVE_ID
] = i32
;
2332 params
[SI_PARAM_VTX2_OFFSET
] = i32
;
2333 params
[SI_PARAM_VTX3_OFFSET
] = i32
;
2334 params
[SI_PARAM_VTX4_OFFSET
] = i32
;
2335 params
[SI_PARAM_VTX5_OFFSET
] = i32
;
2336 params
[SI_PARAM_GS_INSTANCE_ID
] = i32
;
2337 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
2340 case TGSI_PROCESSOR_FRAGMENT
:
2341 params
[SI_PARAM_ALPHA_REF
] = f32
;
2342 params
[SI_PARAM_PRIM_MASK
] = i32
;
2343 last_sgpr
= SI_PARAM_PRIM_MASK
;
2344 params
[SI_PARAM_PERSP_SAMPLE
] = v2i32
;
2345 params
[SI_PARAM_PERSP_CENTER
] = v2i32
;
2346 params
[SI_PARAM_PERSP_CENTROID
] = v2i32
;
2347 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
2348 params
[SI_PARAM_LINEAR_SAMPLE
] = v2i32
;
2349 params
[SI_PARAM_LINEAR_CENTER
] = v2i32
;
2350 params
[SI_PARAM_LINEAR_CENTROID
] = v2i32
;
2351 params
[SI_PARAM_LINE_STIPPLE_TEX
] = f32
;
2352 params
[SI_PARAM_POS_X_FLOAT
] = f32
;
2353 params
[SI_PARAM_POS_Y_FLOAT
] = f32
;
2354 params
[SI_PARAM_POS_Z_FLOAT
] = f32
;
2355 params
[SI_PARAM_POS_W_FLOAT
] = f32
;
2356 params
[SI_PARAM_FRONT_FACE
] = f32
;
2357 params
[SI_PARAM_ANCILLARY
] = i32
;
2358 params
[SI_PARAM_SAMPLE_COVERAGE
] = f32
;
2359 params
[SI_PARAM_POS_FIXED_PT
] = f32
;
2360 num_params
= SI_PARAM_POS_FIXED_PT
+1;
2364 assert(0 && "unimplemented shader");
2368 assert(num_params
<= Elements(params
));
2369 radeon_llvm_create_func(&si_shader_ctx
->radeon_bld
, params
, num_params
);
2370 radeon_llvm_shader_type(si_shader_ctx
->radeon_bld
.main_fn
, si_shader_ctx
->type
);
2372 for (i
= 0; i
<= last_sgpr
; ++i
) {
2373 LLVMValueRef P
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, i
);
2375 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2376 * to move load. Inputs are constant so this is fine. */
2377 if (i
<= last_array_pointer
)
2378 LLVMAddAttribute(P
, LLVMByValAttribute
);
2380 LLVMAddAttribute(P
, LLVMInRegAttribute
);
2383 if (bld_base
->info
&&
2384 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
2385 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0))
2386 si_shader_ctx
->ddxy_lds
=
2387 LLVMAddGlobalInAddressSpace(gallivm
->module
,
2388 LLVMArrayType(i32
, 64),
2393 static void preload_constants(struct si_shader_context
*si_shader_ctx
)
2395 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2396 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2397 const struct tgsi_shader_info
* info
= bld_base
->info
;
2399 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
2401 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
2402 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
2407 /* Allocate space for the constant values */
2408 si_shader_ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
2410 /* Load the resource descriptor */
2411 si_shader_ctx
->const_resource
[buf
] =
2412 build_indexed_load_const(si_shader_ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
2414 /* Load the constants, we rely on the code sinking to do the rest */
2415 for (i
= 0; i
< num_const
* 4; ++i
) {
2416 si_shader_ctx
->constants
[buf
][i
] =
2417 buffer_load_const(gallivm
->builder
,
2418 si_shader_ctx
->const_resource
[buf
],
2419 lp_build_const_int32(gallivm
, i
* 4),
2420 bld_base
->base
.elem_type
);
2425 static void preload_samplers(struct si_shader_context
*si_shader_ctx
)
2427 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2428 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2429 const struct tgsi_shader_info
* info
= bld_base
->info
;
2431 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
2433 LLVMValueRef res_ptr
, samp_ptr
;
2434 LLVMValueRef offset
;
2436 if (num_samplers
== 0)
2439 res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_RESOURCE
);
2440 samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER
);
2442 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2443 for (i
= 0; i
< num_samplers
; ++i
) {
2445 offset
= lp_build_const_int32(gallivm
, i
);
2446 si_shader_ctx
->resources
[i
] = build_indexed_load_const(si_shader_ctx
, res_ptr
, offset
);
2449 offset
= lp_build_const_int32(gallivm
, i
);
2450 si_shader_ctx
->samplers
[i
] = build_indexed_load_const(si_shader_ctx
, samp_ptr
, offset
);
2452 /* FMASK resource */
2453 if (info
->is_msaa_sampler
[i
]) {
2454 offset
= lp_build_const_int32(gallivm
, SI_FMASK_TEX_OFFSET
+ i
);
2455 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ i
] =
2456 build_indexed_load_const(si_shader_ctx
, res_ptr
, offset
);
2461 static void preload_streamout_buffers(struct si_shader_context
*si_shader_ctx
)
2463 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2464 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2467 if (si_shader_ctx
->type
!= TGSI_PROCESSOR_VERTEX
||
2468 si_shader_ctx
->shader
->key
.vs
.as_es
||
2469 !si_shader_ctx
->shader
->selector
->so
.num_outputs
)
2472 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2473 SI_PARAM_RW_BUFFERS
);
2475 /* Load the resources, we rely on the code sinking to do the rest */
2476 for (i
= 0; i
< 4; ++i
) {
2477 if (si_shader_ctx
->shader
->selector
->so
.stride
[i
]) {
2478 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
2479 SI_SO_BUF_OFFSET
+ i
);
2481 si_shader_ctx
->so_buffers
[i
] = build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
2487 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2490 static void preload_ring_buffers(struct si_shader_context
*si_shader_ctx
)
2492 struct gallivm_state
*gallivm
=
2493 si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
2495 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2496 SI_PARAM_RW_BUFFERS
);
2498 if ((si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&&
2499 si_shader_ctx
->shader
->key
.vs
.as_es
) ||
2500 si_shader_ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
2501 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_RING_ESGS
);
2503 si_shader_ctx
->esgs_ring
=
2504 build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
2507 if (si_shader_ctx
->type
== TGSI_PROCESSOR_GEOMETRY
||
2508 si_shader_ctx
->shader
->is_gs_copy_shader
) {
2509 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_RING_GSVS
);
2511 si_shader_ctx
->gsvs_ring
=
2512 build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
2516 void si_shader_binary_read_config(const struct radeon_shader_binary
*binary
,
2517 struct si_shader
*shader
,
2518 unsigned symbol_offset
)
2521 const unsigned char *config
=
2522 radeon_shader_binary_config_start(binary
, symbol_offset
);
2524 /* XXX: We may be able to emit some of these values directly rather than
2525 * extracting fields to be emitted later.
2528 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
2529 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
2530 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
2532 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
2533 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
2534 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
2535 case R_00B848_COMPUTE_PGM_RSRC1
:
2536 shader
->num_sgprs
= MAX2(shader
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
2537 shader
->num_vgprs
= MAX2(shader
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
2539 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
2540 shader
->lds_size
= MAX2(shader
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
2542 case R_00B84C_COMPUTE_PGM_RSRC2
:
2543 shader
->lds_size
= MAX2(shader
->lds_size
, G_00B84C_LDS_SIZE(value
));
2545 case R_0286CC_SPI_PS_INPUT_ENA
:
2546 shader
->spi_ps_input_ena
= value
;
2548 case R_00B860_COMPUTE_TMPRING_SIZE
:
2549 /* WAVESIZE is in units of 256 dwords. */
2550 shader
->scratch_bytes_per_wave
=
2551 G_00B860_WAVESIZE(value
) * 256 * 4 * 1;
2554 fprintf(stderr
, "Warning: Compiler emitted unknown "
2555 "config register: 0x%x\n", reg
);
2561 int si_shader_binary_read(struct si_screen
*sscreen
,
2562 struct si_shader
*shader
,
2563 const struct radeon_shader_binary
*binary
)
2569 bool dump
= r600_can_dump_shader(&sscreen
->b
,
2570 shader
->selector
? shader
->selector
->tokens
: NULL
);
2572 if (dump
&& !binary
->disassembled
) {
2573 fprintf(stderr
, "SI CODE:\n");
2574 for (i
= 0; i
< binary
->code_size
; i
+=4 ) {
2575 fprintf(stderr
, "@0x%x: %02x%02x%02x%02x\n", i
, binary
->code
[i
+ 3],
2576 binary
->code
[i
+ 2], binary
->code
[i
+ 1],
2581 si_shader_binary_read_config(binary
, shader
, 0);
2583 /* copy new shader */
2584 code_size
= binary
->code_size
+ binary
->rodata_size
;
2585 r600_resource_reference(&shader
->bo
, NULL
);
2586 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
, PIPE_USAGE_IMMUTABLE
,
2588 if (shader
->bo
== NULL
) {
2593 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->cs_buf
, NULL
, PIPE_TRANSFER_READ_WRITE
);
2594 util_memcpy_cpu_to_le32(ptr
, binary
->code
, binary
->code_size
);
2595 if (binary
->rodata_size
> 0) {
2596 ptr
+= binary
->code_size
;
2597 util_memcpy_cpu_to_le32(ptr
, binary
->rodata
, binary
->rodata_size
);
2600 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->cs_buf
);
2605 int si_compile_llvm(struct si_screen
*sscreen
, struct si_shader
*shader
,
2609 struct radeon_shader_binary binary
;
2610 bool dump
= r600_can_dump_shader(&sscreen
->b
,
2611 shader
->selector
? shader
->selector
->tokens
: NULL
);
2612 memset(&binary
, 0, sizeof(binary
));
2613 r
= radeon_llvm_compile(mod
, &binary
,
2614 r600_get_llvm_processor_name(sscreen
->b
.family
), dump
, sscreen
->tm
);
2619 r
= si_shader_binary_read(sscreen
, shader
, &binary
);
2621 FREE(binary
.config
);
2622 FREE(binary
.rodata
);
2626 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2627 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
2628 struct si_shader_context
*si_shader_ctx
,
2629 struct si_shader
*gs
, bool dump
)
2631 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
2632 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2633 struct lp_build_context
*base
= &bld_base
->base
;
2634 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2635 struct si_shader
*shader
= si_shader_ctx
->shader
;
2636 struct si_shader_output_values
*outputs
;
2637 struct tgsi_shader_info
*gsinfo
= &gs
->selector
->info
;
2638 LLVMValueRef args
[9];
2641 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
2643 si_shader_ctx
->type
= TGSI_PROCESSOR_VERTEX
;
2644 shader
->is_gs_copy_shader
= true;
2646 radeon_llvm_context_init(&si_shader_ctx
->radeon_bld
);
2648 create_meta_data(si_shader_ctx
);
2649 create_function(si_shader_ctx
);
2650 preload_streamout_buffers(si_shader_ctx
);
2651 preload_ring_buffers(si_shader_ctx
);
2653 args
[0] = si_shader_ctx
->gsvs_ring
;
2654 args
[1] = lp_build_mul_imm(uint
,
2655 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2656 si_shader_ctx
->param_vertex_id
),
2658 args
[3] = uint
->zero
;
2659 args
[4] = uint
->one
; /* OFFEN */
2660 args
[5] = uint
->zero
; /* IDXEN */
2661 args
[6] = uint
->one
; /* GLC */
2662 args
[7] = uint
->one
; /* SLC */
2663 args
[8] = uint
->zero
; /* TFE */
2665 /* Fetch vertex data from GSVS ring */
2666 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
2669 outputs
[i
].name
= gsinfo
->output_semantic_name
[i
];
2670 outputs
[i
].sid
= gsinfo
->output_semantic_index
[i
];
2672 for (chan
= 0; chan
< 4; chan
++) {
2673 args
[2] = lp_build_const_int32(gallivm
,
2675 gs
->selector
->gs_max_out_vertices
* 16 * 4);
2677 outputs
[i
].values
[chan
] =
2678 LLVMBuildBitCast(gallivm
->builder
,
2679 build_intrinsic(gallivm
->builder
,
2680 "llvm.SI.buffer.load.dword.i32.i32",
2681 LLVMInt32TypeInContext(gallivm
->context
),
2683 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
2684 base
->elem_type
, "");
2688 si_llvm_export_vs(bld_base
, outputs
, gsinfo
->num_outputs
);
2690 radeon_llvm_finalize_module(&si_shader_ctx
->radeon_bld
);
2693 fprintf(stderr
, "Copy Vertex Shader for Geometry Shader:\n\n");
2695 r
= si_compile_llvm(sscreen
, si_shader_ctx
->shader
,
2696 bld_base
->base
.gallivm
->module
);
2698 radeon_llvm_dispose(&si_shader_ctx
->radeon_bld
);
2704 int si_shader_create(struct si_screen
*sscreen
, struct si_shader
*shader
)
2706 struct si_shader_selector
*sel
= shader
->selector
;
2707 struct si_shader_context si_shader_ctx
;
2708 struct lp_build_tgsi_context
* bld_base
;
2711 bool dump
= r600_can_dump_shader(&sscreen
->b
, sel
->tokens
);
2713 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2714 * conversion fails. */
2716 tgsi_dump(sel
->tokens
, 0);
2717 si_dump_streamout(&sel
->so
);
2720 assert(shader
->nparam
== 0);
2722 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
2723 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
2724 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
2726 if (sel
->info
.uses_kill
)
2727 shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
2729 shader
->uses_instanceid
= sel
->info
.uses_instanceid
;
2730 bld_base
->info
= &sel
->info
;
2731 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
2733 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
2734 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
2735 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
2736 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
2737 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
2738 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
2739 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
2740 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
2741 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
2742 bld_base
->op_actions
[TGSI_OPCODE_TXQ
] = txq_action
;
2743 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
2744 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
2746 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
2747 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
2749 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
2750 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
2752 if (HAVE_LLVM
>= 0x0306) {
2753 bld_base
->op_actions
[TGSI_OPCODE_MAX
].emit
= build_tgsi_intrinsic_nomem
;
2754 bld_base
->op_actions
[TGSI_OPCODE_MAX
].intr_name
= "llvm.maxnum.f32";
2755 bld_base
->op_actions
[TGSI_OPCODE_MIN
].emit
= build_tgsi_intrinsic_nomem
;
2756 bld_base
->op_actions
[TGSI_OPCODE_MIN
].intr_name
= "llvm.minnum.f32";
2759 si_shader_ctx
.radeon_bld
.load_system_value
= declare_system_value
;
2760 si_shader_ctx
.tokens
= sel
->tokens
;
2761 tgsi_parse_init(&si_shader_ctx
.parse
, si_shader_ctx
.tokens
);
2762 si_shader_ctx
.shader
= shader
;
2763 si_shader_ctx
.type
= si_shader_ctx
.parse
.FullHeader
.Processor
.Processor
;
2764 si_shader_ctx
.screen
= sscreen
;
2766 switch (si_shader_ctx
.type
) {
2767 case TGSI_PROCESSOR_VERTEX
:
2768 si_shader_ctx
.radeon_bld
.load_input
= declare_input_vs
;
2769 if (shader
->key
.vs
.as_es
) {
2770 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
2772 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
2775 case TGSI_PROCESSOR_GEOMETRY
:
2776 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
2777 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
2779 case TGSI_PROCESSOR_FRAGMENT
:
2780 si_shader_ctx
.radeon_bld
.load_input
= declare_input_fs
;
2781 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
2783 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2784 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2785 shader
->db_shader_control
|=
2786 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2788 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2789 shader
->db_shader_control
|=
2790 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2795 assert(!"Unsupported shader type");
2799 create_meta_data(&si_shader_ctx
);
2800 create_function(&si_shader_ctx
);
2801 preload_constants(&si_shader_ctx
);
2802 preload_samplers(&si_shader_ctx
);
2803 preload_streamout_buffers(&si_shader_ctx
);
2804 preload_ring_buffers(&si_shader_ctx
);
2806 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2807 si_shader_ctx
.gs_next_vertex
=
2808 lp_build_alloca(bld_base
->base
.gallivm
,
2809 bld_base
->uint_bld
.elem_type
, "");
2812 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
2813 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
2817 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
2819 mod
= bld_base
->base
.gallivm
->module
;
2820 r
= si_compile_llvm(sscreen
, shader
, mod
);
2822 fprintf(stderr
, "LLVM failed to compile shader\n");
2826 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
2828 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2829 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
2830 shader
->gs_copy_shader
->selector
= shader
->selector
;
2831 shader
->gs_copy_shader
->key
= shader
->key
;
2832 si_shader_ctx
.shader
= shader
->gs_copy_shader
;
2833 if ((r
= si_generate_gs_copy_shader(sscreen
, &si_shader_ctx
,
2835 free(shader
->gs_copy_shader
);
2836 shader
->gs_copy_shader
= NULL
;
2841 tgsi_parse_free(&si_shader_ctx
.parse
);
2844 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
2845 FREE(si_shader_ctx
.constants
[i
]);
2850 void si_shader_destroy(struct pipe_context
*ctx
, struct si_shader
*shader
)
2852 if (shader
->gs_copy_shader
)
2853 si_shader_destroy(ctx
, shader
->gs_copy_shader
);
2855 r600_resource_reference(&shader
->bo
, NULL
);
2856 r600_resource_reference(&shader
->scratch_bo
, NULL
);