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radeonsi: allow specifying simm16 of emit_waitcnt at call sites
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 static void si_init_shader_ctx(struct si_shader_context *ctx,
63 struct si_screen *sscreen,
64 struct si_shader *shader,
65 LLVMTargetMachineRef tm);
66
67 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
68 struct lp_build_tgsi_context *bld_base,
69 struct lp_build_emit_data *emit_data);
70
71 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
72 FILE *f);
73
74 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
77 union si_shader_part_key *key);
78 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
79 union si_shader_part_key *key);
80 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
81 union si_shader_part_key *key);
82 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
83 union si_shader_part_key *key);
84
85 /* Ideally pass the sample mask input to the PS epilog as v13, which
86 * is its usual location, so that the shader doesn't have to add v_mov.
87 */
88 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
89
90 /* The VS location of the PrimitiveID input is the same in the epilog,
91 * so that the main shader part doesn't have to move it.
92 */
93 #define VS_EPILOG_PRIMID_LOC 2
94
95 enum {
96 CONST_ADDR_SPACE = 2,
97 LOCAL_ADDR_SPACE = 3,
98 };
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_GENERIC:
124 if (index <= 63-4)
125 return 4 + index;
126
127 assert(!"invalid generic index");
128 return 0;
129
130 /* patch indices are completely separate and thus start from 0 */
131 case TGSI_SEMANTIC_TESSOUTER:
132 return 0;
133 case TGSI_SEMANTIC_TESSINNER:
134 return 1;
135 case TGSI_SEMANTIC_PATCH:
136 return 2 + index;
137
138 default:
139 assert(!"invalid semantic name");
140 return 0;
141 }
142 }
143
144 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
145 {
146 switch (name) {
147 case TGSI_SEMANTIC_FOG:
148 return 0;
149 case TGSI_SEMANTIC_LAYER:
150 return 1;
151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
152 return 2;
153 case TGSI_SEMANTIC_PRIMID:
154 return 3;
155 case TGSI_SEMANTIC_COLOR: /* these alias */
156 case TGSI_SEMANTIC_BCOLOR:
157 return 4 + index;
158 case TGSI_SEMANTIC_TEXCOORD:
159 return 6 + index;
160 default:
161 assert(!"invalid semantic name");
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &ctx->gallivm;
174 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
175 param);
176
177 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
178 value = bitcast(&ctx->soa.bld_base,
179 TGSI_TYPE_UNSIGNED, value);
180
181 if (rshift)
182 value = LLVMBuildLShr(gallivm->builder, value,
183 lp_build_const_int32(gallivm, rshift), "");
184
185 if (rshift + bitwidth < 32) {
186 unsigned mask = (1 << bitwidth) - 1;
187 value = LLVMBuildAnd(gallivm->builder, value,
188 lp_build_const_int32(gallivm, mask), "");
189 }
190
191 return value;
192 }
193
194 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
195 {
196 switch (ctx->type) {
197 case PIPE_SHADER_TESS_CTRL:
198 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
199
200 case PIPE_SHADER_TESS_EVAL:
201 return LLVMGetParam(ctx->main_fn,
202 ctx->param_tes_rel_patch_id);
203
204 default:
205 assert(0);
206 return NULL;
207 }
208 }
209
210 /* Tessellation shaders pass outputs to the next shader using LDS.
211 *
212 * LS outputs = TCS inputs
213 * TCS outputs = TES inputs
214 *
215 * The LDS layout is:
216 * - TCS inputs for patch 0
217 * - TCS inputs for patch 1
218 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
219 * - ...
220 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
221 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
222 * - TCS outputs for patch 1
223 * - Per-patch TCS outputs for patch 1
224 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
225 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
226 * - ...
227 *
228 * All three shaders VS(LS), TCS, TES share the same LDS space.
229 */
230
231 static LLVMValueRef
232 get_tcs_in_patch_stride(struct si_shader_context *ctx)
233 {
234 if (ctx->type == PIPE_SHADER_VERTEX)
235 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
236 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
237 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
238 else {
239 assert(0);
240 return NULL;
241 }
242 }
243
244 static LLVMValueRef
245 get_tcs_out_patch_stride(struct si_shader_context *ctx)
246 {
247 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
248 }
249
250 static LLVMValueRef
251 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
252 {
253 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
254 unpack_param(ctx,
255 SI_PARAM_TCS_OUT_OFFSETS,
256 0, 16),
257 4);
258 }
259
260 static LLVMValueRef
261 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
262 {
263 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
264 unpack_param(ctx,
265 SI_PARAM_TCS_OUT_OFFSETS,
266 16, 16),
267 4);
268 }
269
270 static LLVMValueRef
271 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
272 {
273 struct gallivm_state *gallivm = &ctx->gallivm;
274 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
275 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
276
277 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
278 }
279
280 static LLVMValueRef
281 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
282 {
283 struct gallivm_state *gallivm = &ctx->gallivm;
284 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
285 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
286 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
287
288 return LLVMBuildAdd(gallivm->builder, patch0_offset,
289 LLVMBuildMul(gallivm->builder, patch_stride,
290 rel_patch_id, ""),
291 "");
292 }
293
294 static LLVMValueRef
295 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
296 {
297 struct gallivm_state *gallivm = &ctx->gallivm;
298 LLVMValueRef patch0_patch_data_offset =
299 get_tcs_out_patch0_patch_data_offset(ctx);
300 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
304 LLVMBuildMul(gallivm->builder, patch_stride,
305 rel_patch_id, ""),
306 "");
307 }
308
309 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
310 LLVMValueRef base_ptr, LLVMValueRef index)
311 {
312 LLVMValueRef indices[2] = {
313 LLVMConstInt(ctx->i32, 0, 0),
314 index,
315 };
316 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
317 indices, 2, "");
318 }
319
320 static void build_indexed_store(struct si_shader_context *ctx,
321 LLVMValueRef base_ptr, LLVMValueRef index,
322 LLVMValueRef value)
323 {
324 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
325 struct gallivm_state *gallivm = bld_base->base.gallivm;
326
327 LLVMBuildStore(gallivm->builder, value,
328 build_gep0(ctx, base_ptr, index));
329 }
330
331 /**
332 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
333 * It's equivalent to doing a load from &base_ptr[index].
334 *
335 * \param base_ptr Where the array starts.
336 * \param index The element index into the array.
337 * \param uniform Whether the base_ptr and index can be assumed to be
338 * dynamically uniform
339 */
340 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
341 LLVMValueRef base_ptr, LLVMValueRef index,
342 bool uniform)
343 {
344 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
345 struct gallivm_state *gallivm = bld_base->base.gallivm;
346 LLVMValueRef pointer;
347
348 pointer = build_gep0(ctx, base_ptr, index);
349 if (uniform)
350 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
351 return LLVMBuildLoad(gallivm->builder, pointer, "");
352 }
353
354 /**
355 * Do a load from &base_ptr[index], but also add a flag that it's loading
356 * a constant from a dynamically uniform index.
357 */
358 static LLVMValueRef build_indexed_load_const(
359 struct si_shader_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index)
361 {
362 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
363 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
364 return result;
365 }
366
367 static LLVMValueRef get_instance_index_for_fetch(
368 struct si_shader_context *radeon_bld,
369 unsigned param_start_instance, unsigned divisor)
370 {
371 struct si_shader_context *ctx =
372 si_shader_context(&radeon_bld->soa.bld_base);
373 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
374
375 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
376 ctx->param_instance_id);
377
378 /* The division must be done before START_INSTANCE is added. */
379 if (divisor > 1)
380 result = LLVMBuildUDiv(gallivm->builder, result,
381 lp_build_const_int32(gallivm, divisor), "");
382
383 return LLVMBuildAdd(gallivm->builder, result,
384 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
385 }
386
387 static void declare_input_vs(
388 struct si_shader_context *ctx,
389 unsigned input_index,
390 const struct tgsi_full_declaration *decl,
391 LLVMValueRef out[4])
392 {
393 struct lp_build_context *base = &ctx->soa.bld_base.base;
394 struct gallivm_state *gallivm = base->gallivm;
395
396 unsigned chan;
397 unsigned fix_fetch;
398
399 LLVMValueRef t_list_ptr;
400 LLVMValueRef t_offset;
401 LLVMValueRef t_list;
402 LLVMValueRef attribute_offset;
403 LLVMValueRef buffer_index;
404 LLVMValueRef args[3];
405 LLVMValueRef input;
406
407 /* Load the T list */
408 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
409
410 t_offset = lp_build_const_int32(gallivm, input_index);
411
412 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
413
414 /* Build the attribute offset */
415 attribute_offset = lp_build_const_int32(gallivm, 0);
416
417 buffer_index = LLVMGetParam(ctx->main_fn,
418 ctx->param_vertex_index0 +
419 input_index);
420
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
426 LP_FUNC_ATTR_READNONE);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 out[chan] = LLVMBuildExtractElement(gallivm->builder,
432 input, llvm_chan, "");
433 }
434
435 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
436 if (fix_fetch) {
437 /* The hardware returns an unsigned value; convert it to a
438 * signed one.
439 */
440 LLVMValueRef tmp = out[3];
441 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
442
443 /* First, recover the sign-extended signed integer value. */
444 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
445 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
446 else
447 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
448
449 /* For the integer-like cases, do a natural sign extension.
450 *
451 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
452 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
453 * exponent.
454 */
455 tmp = LLVMBuildShl(gallivm->builder, tmp,
456 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
457 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
458 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
459
460 /* Convert back to the right type. */
461 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
462 LLVMValueRef clamp;
463 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
464 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
465 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
466 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
467 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
468 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
469 }
470
471 out[3] = tmp;
472 }
473 }
474
475 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
476 unsigned swizzle)
477 {
478 struct si_shader_context *ctx = si_shader_context(bld_base);
479
480 if (swizzle > 0)
481 return bld_base->uint_bld.zero;
482
483 switch (ctx->type) {
484 case PIPE_SHADER_VERTEX:
485 return LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_prim_id);
487 case PIPE_SHADER_TESS_CTRL:
488 return LLVMGetParam(ctx->main_fn,
489 SI_PARAM_PATCH_ID);
490 case PIPE_SHADER_TESS_EVAL:
491 return LLVMGetParam(ctx->main_fn,
492 ctx->param_tes_patch_id);
493 case PIPE_SHADER_GEOMETRY:
494 return LLVMGetParam(ctx->main_fn,
495 SI_PARAM_PRIMITIVE_ID);
496 default:
497 assert(0);
498 return bld_base->uint_bld.zero;
499 }
500 }
501
502 /**
503 * Return the value of tgsi_ind_register for indexing.
504 * This is the indirect index with the constant offset added to it.
505 */
506 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
507 const struct tgsi_ind_register *ind,
508 int rel_index)
509 {
510 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
511 LLVMValueRef result;
512
513 result = ctx->soa.addr[ind->Index][ind->Swizzle];
514 result = LLVMBuildLoad(gallivm->builder, result, "");
515 result = LLVMBuildAdd(gallivm->builder, result,
516 lp_build_const_int32(gallivm, rel_index), "");
517 return result;
518 }
519
520 /**
521 * Like get_indirect_index, but restricts the return value to a (possibly
522 * undefined) value inside [0..num).
523 */
524 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index, unsigned num)
527 {
528 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
529
530 /* LLVM 3.8: If indirect resource indexing is used:
531 * - SI & CIK hang
532 * - VI crashes
533 */
534 if (HAVE_LLVM <= 0x0308)
535 return LLVMGetUndef(ctx->i32);
536
537 return si_llvm_bound_index(ctx, result, num);
538 }
539
540
541 /**
542 * Calculate a dword address given an input or output register and a stride.
543 */
544 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
545 const struct tgsi_full_dst_register *dst,
546 const struct tgsi_full_src_register *src,
547 LLVMValueRef vertex_dw_stride,
548 LLVMValueRef base_addr)
549 {
550 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
551 struct tgsi_shader_info *info = &ctx->shader->selector->info;
552 ubyte *name, *index, *array_first;
553 int first, param;
554 struct tgsi_full_dst_register reg;
555
556 /* Set the register description. The address computation is the same
557 * for sources and destinations. */
558 if (src) {
559 reg.Register.File = src->Register.File;
560 reg.Register.Index = src->Register.Index;
561 reg.Register.Indirect = src->Register.Indirect;
562 reg.Register.Dimension = src->Register.Dimension;
563 reg.Indirect = src->Indirect;
564 reg.Dimension = src->Dimension;
565 reg.DimIndirect = src->DimIndirect;
566 } else
567 reg = *dst;
568
569 /* If the register is 2-dimensional (e.g. an array of vertices
570 * in a primitive), calculate the base address of the vertex. */
571 if (reg.Register.Dimension) {
572 LLVMValueRef index;
573
574 if (reg.Dimension.Indirect)
575 index = get_indirect_index(ctx, &reg.DimIndirect,
576 reg.Dimension.Index);
577 else
578 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
579
580 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
581 LLVMBuildMul(gallivm->builder, index,
582 vertex_dw_stride, ""), "");
583 }
584
585 /* Get information about the register. */
586 if (reg.Register.File == TGSI_FILE_INPUT) {
587 name = info->input_semantic_name;
588 index = info->input_semantic_index;
589 array_first = info->input_array_first;
590 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
591 name = info->output_semantic_name;
592 index = info->output_semantic_index;
593 array_first = info->output_array_first;
594 } else {
595 assert(0);
596 return NULL;
597 }
598
599 if (reg.Register.Indirect) {
600 /* Add the relative address of the element. */
601 LLVMValueRef ind_index;
602
603 if (reg.Indirect.ArrayID)
604 first = array_first[reg.Indirect.ArrayID];
605 else
606 first = reg.Register.Index;
607
608 ind_index = get_indirect_index(ctx, &reg.Indirect,
609 reg.Register.Index - first);
610
611 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
612 LLVMBuildMul(gallivm->builder, ind_index,
613 lp_build_const_int32(gallivm, 4), ""), "");
614
615 param = si_shader_io_get_unique_index(name[first], index[first]);
616 } else {
617 param = si_shader_io_get_unique_index(name[reg.Register.Index],
618 index[reg.Register.Index]);
619 }
620
621 /* Add the base address of the element. */
622 return LLVMBuildAdd(gallivm->builder, base_addr,
623 lp_build_const_int32(gallivm, param * 4), "");
624 }
625
626 /* The offchip buffer layout for TCS->TES is
627 *
628 * - attribute 0 of patch 0 vertex 0
629 * - attribute 0 of patch 0 vertex 1
630 * - attribute 0 of patch 0 vertex 2
631 * ...
632 * - attribute 0 of patch 1 vertex 0
633 * - attribute 0 of patch 1 vertex 1
634 * ...
635 * - attribute 1 of patch 0 vertex 0
636 * - attribute 1 of patch 0 vertex 1
637 * ...
638 * - per patch attribute 0 of patch 0
639 * - per patch attribute 0 of patch 1
640 * ...
641 *
642 * Note that every attribute has 4 components.
643 */
644 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
645 LLVMValueRef vertex_index,
646 LLVMValueRef param_index)
647 {
648 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
649 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
650 LLVMValueRef param_stride, constant16;
651
652 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
653 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
654 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
655 num_patches, "");
656
657 constant16 = lp_build_const_int32(gallivm, 16);
658 if (vertex_index) {
659 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
660 vertices_per_patch, "");
661
662 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
663 vertex_index, "");
664
665 param_stride = total_vertices;
666 } else {
667 base_addr = get_rel_patch_id(ctx);
668 param_stride = num_patches;
669 }
670
671 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
672 LLVMBuildMul(gallivm->builder, param_index,
673 param_stride, ""), "");
674
675 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
676
677 if (!vertex_index) {
678 LLVMValueRef patch_data_offset =
679 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
680
681 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
682 patch_data_offset, "");
683 }
684 return base_addr;
685 }
686
687 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
688 struct si_shader_context *ctx,
689 const struct tgsi_full_dst_register *dst,
690 const struct tgsi_full_src_register *src)
691 {
692 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 struct tgsi_full_src_register reg;
696 LLVMValueRef vertex_index = NULL;
697 LLVMValueRef param_index = NULL;
698 unsigned param_index_base, param_base;
699
700 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
701
702 if (reg.Register.Dimension) {
703
704 if (reg.Dimension.Indirect)
705 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
706 reg.Dimension.Index);
707 else
708 vertex_index = lp_build_const_int32(gallivm,
709 reg.Dimension.Index);
710 }
711
712 /* Get information about the register. */
713 if (reg.Register.File == TGSI_FILE_INPUT) {
714 name = info->input_semantic_name;
715 index = info->input_semantic_index;
716 array_first = info->input_array_first;
717 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
718 name = info->output_semantic_name;
719 index = info->output_semantic_index;
720 array_first = info->output_array_first;
721 } else {
722 assert(0);
723 return NULL;
724 }
725
726 if (reg.Register.Indirect) {
727 if (reg.Indirect.ArrayID)
728 param_base = array_first[reg.Indirect.ArrayID];
729 else
730 param_base = reg.Register.Index;
731
732 param_index = get_indirect_index(ctx, &reg.Indirect,
733 reg.Register.Index - param_base);
734
735 } else {
736 param_base = reg.Register.Index;
737 param_index = lp_build_const_int32(gallivm, 0);
738 }
739
740 param_index_base = si_shader_io_get_unique_index(name[param_base],
741 index[param_base]);
742
743 param_index = LLVMBuildAdd(gallivm->builder, param_index,
744 lp_build_const_int32(gallivm, param_index_base),
745 "");
746
747 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
748 }
749
750 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
751 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
752 * or v4i32 (num_channels=3,4). */
753 static void build_tbuffer_store(struct si_shader_context *ctx,
754 LLVMValueRef rsrc,
755 LLVMValueRef vdata,
756 unsigned num_channels,
757 LLVMValueRef vaddr,
758 LLVMValueRef soffset,
759 unsigned inst_offset,
760 unsigned dfmt,
761 unsigned nfmt,
762 unsigned offen,
763 unsigned idxen,
764 unsigned glc,
765 unsigned slc,
766 unsigned tfe)
767 {
768 struct gallivm_state *gallivm = &ctx->gallivm;
769 LLVMValueRef args[] = {
770 rsrc,
771 vdata,
772 LLVMConstInt(ctx->i32, num_channels, 0),
773 vaddr,
774 soffset,
775 LLVMConstInt(ctx->i32, inst_offset, 0),
776 LLVMConstInt(ctx->i32, dfmt, 0),
777 LLVMConstInt(ctx->i32, nfmt, 0),
778 LLVMConstInt(ctx->i32, offen, 0),
779 LLVMConstInt(ctx->i32, idxen, 0),
780 LLVMConstInt(ctx->i32, glc, 0),
781 LLVMConstInt(ctx->i32, slc, 0),
782 LLVMConstInt(ctx->i32, tfe, 0)
783 };
784
785 /* The instruction offset field has 12 bits */
786 assert(offen || inst_offset < (1 << 12));
787
788 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
789 unsigned func = CLAMP(num_channels, 1, 3) - 1;
790 const char *types[] = {"i32", "v2i32", "v4i32"};
791 char name[256];
792 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
793
794 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
795 args, ARRAY_SIZE(args), 0);
796 }
797
798 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
799 LLVMValueRef rsrc,
800 LLVMValueRef vdata,
801 unsigned num_channels,
802 LLVMValueRef vaddr,
803 LLVMValueRef soffset,
804 unsigned inst_offset)
805 {
806 static unsigned dfmt[] = {
807 V_008F0C_BUF_DATA_FORMAT_32,
808 V_008F0C_BUF_DATA_FORMAT_32_32,
809 V_008F0C_BUF_DATA_FORMAT_32_32_32,
810 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
811 };
812 assert(num_channels >= 1 && num_channels <= 4);
813
814 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
815 inst_offset, dfmt[num_channels-1],
816 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
817 }
818
819 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
820 LLVMValueRef rsrc,
821 int num_channels,
822 LLVMValueRef vindex,
823 LLVMValueRef voffset,
824 LLVMValueRef soffset,
825 unsigned inst_offset,
826 unsigned glc,
827 unsigned slc)
828 {
829 struct gallivm_state *gallivm = &ctx->gallivm;
830 unsigned func = CLAMP(num_channels, 1, 3) - 1;
831
832 if (HAVE_LLVM >= 0x309) {
833 LLVMValueRef args[] = {
834 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
835 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
836 LLVMConstInt(ctx->i32, inst_offset, 0),
837 LLVMConstInt(ctx->i1, glc, 0),
838 LLVMConstInt(ctx->i1, slc, 0)
839 };
840
841 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
842 ctx->v4f32};
843 const char *type_names[] = {"f32", "v2f32", "v4f32"};
844 char name[256];
845
846 if (voffset) {
847 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
848 "");
849 }
850
851 if (soffset) {
852 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
853 "");
854 }
855
856 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
857 type_names[func]);
858
859 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
860 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
861 } else {
862 LLVMValueRef args[] = {
863 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
864 voffset ? voffset : vindex,
865 soffset,
866 LLVMConstInt(ctx->i32, inst_offset, 0),
867 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
868 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
869 LLVMConstInt(ctx->i32, glc, 0),
870 LLVMConstInt(ctx->i32, slc, 0),
871 LLVMConstInt(ctx->i32, 0, 0), // TFE
872 };
873
874 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
875 ctx->v4i32};
876 const char *type_names[] = {"i32", "v2i32", "v4i32"};
877 const char *arg_type = "i32";
878 char name[256];
879
880 if (voffset && vindex) {
881 LLVMValueRef vaddr[] = {vindex, voffset};
882
883 arg_type = "v2i32";
884 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
885 }
886
887 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
888 type_names[func], arg_type);
889
890 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
891 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
892 }
893 }
894
895 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
896 enum tgsi_opcode_type type, unsigned swizzle,
897 LLVMValueRef buffer, LLVMValueRef offset,
898 LLVMValueRef base)
899 {
900 struct si_shader_context *ctx = si_shader_context(bld_base);
901 struct gallivm_state *gallivm = bld_base->base.gallivm;
902 LLVMValueRef value, value2;
903 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
904 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
905
906 if (swizzle == ~0) {
907 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
908 0, 1, 0);
909
910 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
911 }
912
913 if (!tgsi_type_is_64bit(type)) {
914 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
915 0, 1, 0);
916
917 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
918 return LLVMBuildExtractElement(gallivm->builder, value,
919 lp_build_const_int32(gallivm, swizzle), "");
920 }
921
922 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
923 swizzle * 4, 1, 0);
924
925 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
926 swizzle * 4 + 4, 1, 0);
927
928 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
929 }
930
931 /**
932 * Load from LDS.
933 *
934 * \param type output value type
935 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
936 * \param dw_addr address in dwords
937 */
938 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
939 enum tgsi_opcode_type type, unsigned swizzle,
940 LLVMValueRef dw_addr)
941 {
942 struct si_shader_context *ctx = si_shader_context(bld_base);
943 struct gallivm_state *gallivm = bld_base->base.gallivm;
944 LLVMValueRef value;
945
946 if (swizzle == ~0) {
947 LLVMValueRef values[TGSI_NUM_CHANNELS];
948
949 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
950 values[chan] = lds_load(bld_base, type, chan, dw_addr);
951
952 return lp_build_gather_values(bld_base->base.gallivm, values,
953 TGSI_NUM_CHANNELS);
954 }
955
956 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
957 lp_build_const_int32(gallivm, swizzle));
958
959 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
960 if (tgsi_type_is_64bit(type)) {
961 LLVMValueRef value2;
962 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
963 lp_build_const_int32(gallivm, 1));
964 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
965 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
966 }
967
968 return LLVMBuildBitCast(gallivm->builder, value,
969 tgsi2llvmtype(bld_base, type), "");
970 }
971
972 /**
973 * Store to LDS.
974 *
975 * \param swizzle offset (typically 0..3)
976 * \param dw_addr address in dwords
977 * \param value value to store
978 */
979 static void lds_store(struct lp_build_tgsi_context *bld_base,
980 unsigned swizzle, LLVMValueRef dw_addr,
981 LLVMValueRef value)
982 {
983 struct si_shader_context *ctx = si_shader_context(bld_base);
984 struct gallivm_state *gallivm = bld_base->base.gallivm;
985
986 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
987 lp_build_const_int32(gallivm, swizzle));
988
989 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
990 build_indexed_store(ctx, ctx->lds,
991 dw_addr, value);
992 }
993
994 static LLVMValueRef fetch_input_tcs(
995 struct lp_build_tgsi_context *bld_base,
996 const struct tgsi_full_src_register *reg,
997 enum tgsi_opcode_type type, unsigned swizzle)
998 {
999 struct si_shader_context *ctx = si_shader_context(bld_base);
1000 LLVMValueRef dw_addr, stride;
1001
1002 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1003 dw_addr = get_tcs_in_current_patch_offset(ctx);
1004 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1005
1006 return lds_load(bld_base, type, swizzle, dw_addr);
1007 }
1008
1009 static LLVMValueRef fetch_output_tcs(
1010 struct lp_build_tgsi_context *bld_base,
1011 const struct tgsi_full_src_register *reg,
1012 enum tgsi_opcode_type type, unsigned swizzle)
1013 {
1014 struct si_shader_context *ctx = si_shader_context(bld_base);
1015 LLVMValueRef dw_addr, stride;
1016
1017 if (reg->Register.Dimension) {
1018 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1019 dw_addr = get_tcs_out_current_patch_offset(ctx);
1020 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1021 } else {
1022 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1023 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1024 }
1025
1026 return lds_load(bld_base, type, swizzle, dw_addr);
1027 }
1028
1029 static LLVMValueRef fetch_input_tes(
1030 struct lp_build_tgsi_context *bld_base,
1031 const struct tgsi_full_src_register *reg,
1032 enum tgsi_opcode_type type, unsigned swizzle)
1033 {
1034 struct si_shader_context *ctx = si_shader_context(bld_base);
1035 struct gallivm_state *gallivm = bld_base->base.gallivm;
1036 LLVMValueRef rw_buffers, buffer, base, addr;
1037
1038 rw_buffers = LLVMGetParam(ctx->main_fn,
1039 SI_PARAM_RW_BUFFERS);
1040 buffer = build_indexed_load_const(ctx, rw_buffers,
1041 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1042
1043 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1044 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1045
1046 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1047 }
1048
1049 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_instruction *inst,
1051 const struct tgsi_opcode_info *info,
1052 LLVMValueRef dst[4])
1053 {
1054 struct si_shader_context *ctx = si_shader_context(bld_base);
1055 struct gallivm_state *gallivm = bld_base->base.gallivm;
1056 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1057 unsigned chan_index;
1058 LLVMValueRef dw_addr, stride;
1059 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1060 LLVMValueRef values[4];
1061
1062 /* Only handle per-patch and per-vertex outputs here.
1063 * Vectors will be lowered to scalars and this function will be called again.
1064 */
1065 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1066 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1067 si_llvm_emit_store(bld_base, inst, info, dst);
1068 return;
1069 }
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1078 }
1079
1080 rw_buffers = LLVMGetParam(ctx->main_fn,
1081 SI_PARAM_RW_BUFFERS);
1082 buffer = build_indexed_load_const(ctx, rw_buffers,
1083 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1084
1085 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1086 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1087
1088
1089 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1090 LLVMValueRef value = dst[chan_index];
1091
1092 if (inst->Instruction.Saturate)
1093 value = si_llvm_saturate(bld_base, value);
1094
1095 lds_store(bld_base, chan_index, dw_addr, value);
1096
1097 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1098 values[chan_index] = value;
1099
1100 if (inst->Dst[0].Register.WriteMask != 0xF) {
1101 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1102 buf_addr, base,
1103 4 * chan_index);
1104 }
1105 }
1106
1107 if (inst->Dst[0].Register.WriteMask == 0xF) {
1108 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1109 values, 4);
1110 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1111 base, 0);
1112 }
1113 }
1114
1115 static LLVMValueRef fetch_input_gs(
1116 struct lp_build_tgsi_context *bld_base,
1117 const struct tgsi_full_src_register *reg,
1118 enum tgsi_opcode_type type,
1119 unsigned swizzle)
1120 {
1121 struct lp_build_context *base = &bld_base->base;
1122 struct si_shader_context *ctx = si_shader_context(bld_base);
1123 struct si_shader *shader = ctx->shader;
1124 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1125 struct gallivm_state *gallivm = base->gallivm;
1126 LLVMValueRef vtx_offset;
1127 LLVMValueRef args[9];
1128 unsigned vtx_offset_param;
1129 struct tgsi_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1131 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1136 return get_primitive_id(bld_base, swizzle);
1137
1138 if (!reg->Register.Dimension)
1139 return NULL;
1140
1141 if (swizzle == ~0) {
1142 LLVMValueRef values[TGSI_NUM_CHANNELS];
1143 unsigned chan;
1144 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1145 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1146 }
1147 return lp_build_gather_values(bld_base->base.gallivm, values,
1148 TGSI_NUM_CHANNELS);
1149 }
1150
1151 /* Get the vertex offset parameter */
1152 vtx_offset_param = reg->Dimension.Index;
1153 if (vtx_offset_param < 2) {
1154 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1155 } else {
1156 assert(vtx_offset_param < 6);
1157 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1158 }
1159 vtx_offset = lp_build_mul_imm(uint,
1160 LLVMGetParam(ctx->main_fn,
1161 vtx_offset_param),
1162 4);
1163
1164 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1165 args[0] = ctx->esgs_ring;
1166 args[1] = vtx_offset;
1167 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1168 args[3] = uint->zero;
1169 args[4] = uint->one; /* OFFEN */
1170 args[5] = uint->zero; /* IDXEN */
1171 args[6] = uint->one; /* GLC */
1172 args[7] = uint->zero; /* SLC */
1173 args[8] = uint->zero; /* TFE */
1174
1175 value = lp_build_intrinsic(gallivm->builder,
1176 "llvm.SI.buffer.load.dword.i32.i32",
1177 ctx->i32, args, 9,
1178 LP_FUNC_ATTR_READONLY);
1179 if (tgsi_type_is_64bit(type)) {
1180 LLVMValueRef value2;
1181 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1182 value2 = lp_build_intrinsic(gallivm->builder,
1183 "llvm.SI.buffer.load.dword.i32.i32",
1184 ctx->i32, args, 9,
1185 LP_FUNC_ATTR_READONLY);
1186 return si_llvm_emit_fetch_64bit(bld_base, type,
1187 value, value2);
1188 }
1189 return LLVMBuildBitCast(gallivm->builder,
1190 value,
1191 tgsi2llvmtype(bld_base, type), "");
1192 }
1193
1194 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1195 {
1196 switch (interpolate) {
1197 case TGSI_INTERPOLATE_CONSTANT:
1198 return 0;
1199
1200 case TGSI_INTERPOLATE_LINEAR:
1201 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1202 return SI_PARAM_LINEAR_SAMPLE;
1203 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1204 return SI_PARAM_LINEAR_CENTROID;
1205 else
1206 return SI_PARAM_LINEAR_CENTER;
1207 break;
1208 case TGSI_INTERPOLATE_COLOR:
1209 case TGSI_INTERPOLATE_PERSPECTIVE:
1210 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1211 return SI_PARAM_PERSP_SAMPLE;
1212 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1213 return SI_PARAM_PERSP_CENTROID;
1214 else
1215 return SI_PARAM_PERSP_CENTER;
1216 break;
1217 default:
1218 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1219 return -1;
1220 }
1221 }
1222
1223 static LLVMValueRef build_fs_interp(
1224 struct lp_build_tgsi_context *bld_base,
1225 LLVMValueRef llvm_chan,
1226 LLVMValueRef attr_number,
1227 LLVMValueRef params,
1228 LLVMValueRef i,
1229 LLVMValueRef j) {
1230
1231 struct si_shader_context *ctx = si_shader_context(bld_base);
1232 struct gallivm_state *gallivm = bld_base->base.gallivm;
1233 LLVMValueRef args[5];
1234 LLVMValueRef p1;
1235 if (HAVE_LLVM < 0x0400) {
1236 LLVMValueRef ij[2];
1237 ij[0] = LLVMBuildBitCast(gallivm->builder, i, ctx->i32, "");
1238 ij[1] = LLVMBuildBitCast(gallivm->builder, j, ctx->i32, "");
1239
1240 args[0] = llvm_chan;
1241 args[1] = attr_number;
1242 args[2] = params;
1243 args[3] = lp_build_gather_values(gallivm, ij, 2);
1244 return lp_build_intrinsic(gallivm->builder, "llvm.fs.interp",
1245 ctx->f32, args, 4,
1246 LP_FUNC_ATTR_READNONE);
1247 }
1248
1249 args[0] = i;
1250 args[1] = llvm_chan;
1251 args[2] = attr_number;
1252 args[3] = params;
1253
1254 p1 = lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p1",
1255 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1256
1257 args[0] = p1;
1258 args[1] = j;
1259 args[2] = llvm_chan;
1260 args[3] = attr_number;
1261 args[4] = params;
1262
1263 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p2",
1264 ctx->f32, args, 5, LP_FUNC_ATTR_READNONE);
1265 }
1266
1267 static LLVMValueRef build_fs_interp_mov(
1268 struct lp_build_tgsi_context *bld_base,
1269 LLVMValueRef parameter,
1270 LLVMValueRef llvm_chan,
1271 LLVMValueRef attr_number,
1272 LLVMValueRef params) {
1273
1274 struct si_shader_context *ctx = si_shader_context(bld_base);
1275 struct gallivm_state *gallivm = bld_base->base.gallivm;
1276 LLVMValueRef args[4];
1277 if (HAVE_LLVM < 0x0400) {
1278 args[0] = llvm_chan;
1279 args[1] = attr_number;
1280 args[2] = params;
1281
1282 return lp_build_intrinsic(gallivm->builder,
1283 "llvm.SI.fs.constant",
1284 ctx->f32, args, 3,
1285 LP_FUNC_ATTR_READNONE);
1286 }
1287
1288 args[0] = parameter;
1289 args[1] = llvm_chan;
1290 args[2] = attr_number;
1291 args[3] = params;
1292
1293 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.mov",
1294 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1295 }
1296
1297 /**
1298 * Interpolate a fragment shader input.
1299 *
1300 * @param ctx context
1301 * @param input_index index of the input in hardware
1302 * @param semantic_name TGSI_SEMANTIC_*
1303 * @param semantic_index semantic index
1304 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1305 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1306 * @param interp_param interpolation weights (i,j)
1307 * @param prim_mask SI_PARAM_PRIM_MASK
1308 * @param face SI_PARAM_FRONT_FACE
1309 * @param result the return value (4 components)
1310 */
1311 static void interp_fs_input(struct si_shader_context *ctx,
1312 unsigned input_index,
1313 unsigned semantic_name,
1314 unsigned semantic_index,
1315 unsigned num_interp_inputs,
1316 unsigned colors_read_mask,
1317 LLVMValueRef interp_param,
1318 LLVMValueRef prim_mask,
1319 LLVMValueRef face,
1320 LLVMValueRef result[4])
1321 {
1322 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
1323 struct lp_build_context *base = &bld_base->base;
1324 struct lp_build_context *uint = &bld_base->uint_bld;
1325 struct gallivm_state *gallivm = base->gallivm;
1326 LLVMValueRef attr_number;
1327 LLVMValueRef i, j;
1328
1329 unsigned chan;
1330
1331 /* fs.constant returns the param from the middle vertex, so it's not
1332 * really useful for flat shading. It's meant to be used for custom
1333 * interpolation (but the intrinsic can't fetch from the other two
1334 * vertices).
1335 *
1336 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1337 * to do the right thing. The only reason we use fs.constant is that
1338 * fs.interp cannot be used on integers, because they can be equal
1339 * to NaN.
1340 *
1341 * When interp is false we will use fs.constant or for newer llvm,
1342 * amdgcn.interp.mov.
1343 */
1344 bool interp = interp_param != NULL;
1345
1346 attr_number = lp_build_const_int32(gallivm, input_index);
1347
1348 if (interp) {
1349 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1350 LLVMVectorType(ctx->f32, 2), "");
1351
1352 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1353 uint->zero, "");
1354 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1355 uint->one, "");
1356 }
1357
1358 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1359 ctx->shader->key.part.ps.prolog.color_two_side) {
1360 LLVMValueRef is_face_positive;
1361 LLVMValueRef back_attr_number;
1362
1363 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1364 * otherwise it's at offset "num_inputs".
1365 */
1366 unsigned back_attr_offset = num_interp_inputs;
1367 if (semantic_index == 1 && colors_read_mask & 0xf)
1368 back_attr_offset += 1;
1369
1370 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1371
1372 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1373 face, uint->zero, "");
1374
1375 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1376 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1377 LLVMValueRef front, back;
1378
1379 if (interp) {
1380 front = build_fs_interp(bld_base, llvm_chan,
1381 attr_number, prim_mask,
1382 i, j);
1383 back = build_fs_interp(bld_base, llvm_chan,
1384 back_attr_number, prim_mask,
1385 i, j);
1386 } else {
1387 front = build_fs_interp_mov(bld_base,
1388 lp_build_const_int32(gallivm, 2), /* P0 */
1389 llvm_chan, attr_number, prim_mask);
1390 back = build_fs_interp_mov(bld_base,
1391 lp_build_const_int32(gallivm, 2), /* P0 */
1392 llvm_chan, back_attr_number, prim_mask);
1393 }
1394
1395 result[chan] = LLVMBuildSelect(gallivm->builder,
1396 is_face_positive,
1397 front,
1398 back,
1399 "");
1400 }
1401 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1402 if (interp) {
1403 result[0] = build_fs_interp(bld_base, uint->zero,
1404 attr_number, prim_mask, i, j);
1405 } else {
1406 result[0] = build_fs_interp_mov(bld_base, uint->zero,
1407 lp_build_const_int32(gallivm, 2), /* P0 */
1408 attr_number, prim_mask);
1409 }
1410 result[1] =
1411 result[2] = lp_build_const_float(gallivm, 0.0f);
1412 result[3] = lp_build_const_float(gallivm, 1.0f);
1413 } else {
1414 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1415 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1416
1417 if (interp) {
1418 result[chan] = build_fs_interp(bld_base,
1419 llvm_chan, attr_number, prim_mask, i, j);
1420 } else {
1421 result[chan] = build_fs_interp_mov(bld_base,
1422 lp_build_const_int32(gallivm, 2), /* P0 */
1423 llvm_chan, attr_number, prim_mask);
1424 }
1425 }
1426 }
1427 }
1428
1429 static void declare_input_fs(
1430 struct si_shader_context *radeon_bld,
1431 unsigned input_index,
1432 const struct tgsi_full_declaration *decl,
1433 LLVMValueRef out[4])
1434 {
1435 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1436 struct si_shader_context *ctx =
1437 si_shader_context(&radeon_bld->soa.bld_base);
1438 struct si_shader *shader = ctx->shader;
1439 LLVMValueRef main_fn = radeon_bld->main_fn;
1440 LLVMValueRef interp_param = NULL;
1441 int interp_param_idx;
1442
1443 /* Get colors from input VGPRs (set by the prolog). */
1444 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1445 unsigned i = decl->Semantic.Index;
1446 unsigned colors_read = shader->selector->info.colors_read;
1447 unsigned mask = colors_read >> (i * 4);
1448 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1449 (i ? util_bitcount(colors_read & 0xf) : 0);
1450
1451 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1452 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1453 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1454 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1455 return;
1456 }
1457
1458 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1459 decl->Interp.Location);
1460 if (interp_param_idx == -1)
1461 return;
1462 else if (interp_param_idx) {
1463 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1464 }
1465
1466 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1467 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1468 ctx->shader->key.part.ps.prolog.flatshade_colors)
1469 interp_param = NULL; /* load the constant color */
1470
1471 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1472 decl->Semantic.Index, shader->selector->info.num_inputs,
1473 shader->selector->info.colors_read, interp_param,
1474 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1475 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1476 &out[0]);
1477 }
1478
1479 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1480 {
1481 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1482 SI_PARAM_ANCILLARY, 8, 4);
1483 }
1484
1485 /**
1486 * Set range metadata on an instruction. This can only be used on load and
1487 * call instructions. If you know an instruction can only produce the values
1488 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1489 * \p lo is the minimum value inclusive.
1490 * \p hi is the maximum value exclusive.
1491 */
1492 static void set_range_metadata(struct si_shader_context *ctx,
1493 LLVMValueRef value, unsigned lo, unsigned hi)
1494 {
1495 LLVMValueRef range_md, md_args[2];
1496 LLVMTypeRef type = LLVMTypeOf(value);
1497 LLVMContextRef context = LLVMGetTypeContext(type);
1498
1499 md_args[0] = LLVMConstInt(type, lo, false);
1500 md_args[1] = LLVMConstInt(type, hi, false);
1501 range_md = LLVMMDNodeInContext(context, md_args, 2);
1502 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1503 }
1504
1505 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1506 {
1507 struct gallivm_state *gallivm = &ctx->gallivm;
1508 LLVMValueRef tid;
1509
1510 if (HAVE_LLVM < 0x0308) {
1511 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1512 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1513 } else {
1514 LLVMValueRef tid_args[2];
1515 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1516 tid_args[1] = lp_build_const_int32(gallivm, 0);
1517 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1518 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1519 tid_args, 2, LP_FUNC_ATTR_READNONE);
1520
1521 tid = lp_build_intrinsic(gallivm->builder,
1522 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1523 tid_args, 2, LP_FUNC_ATTR_READNONE);
1524 }
1525 set_range_metadata(ctx, tid, 0, 64);
1526 return tid;
1527 }
1528
1529 /**
1530 * Load a dword from a constant buffer.
1531 */
1532 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1533 LLVMValueRef resource,
1534 LLVMValueRef offset)
1535 {
1536 LLVMBuilderRef builder = ctx->gallivm.builder;
1537 LLVMValueRef args[2] = {resource, offset};
1538
1539 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1540 LP_FUNC_ATTR_READNONE);
1541 }
1542
1543 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1544 {
1545 struct si_shader_context *ctx =
1546 si_shader_context(&radeon_bld->soa.bld_base);
1547 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1548 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1549 LLVMBuilderRef builder = gallivm->builder;
1550 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1551 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1552 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1553
1554 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1555 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1556 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1557
1558 LLVMValueRef pos[4] = {
1559 buffer_load_const(ctx, resource, offset0),
1560 buffer_load_const(ctx, resource, offset1),
1561 lp_build_const_float(gallivm, 0),
1562 lp_build_const_float(gallivm, 0)
1563 };
1564
1565 return lp_build_gather_values(gallivm, pos, 4);
1566 }
1567
1568 static void declare_system_value(
1569 struct si_shader_context *radeon_bld,
1570 unsigned index,
1571 const struct tgsi_full_declaration *decl)
1572 {
1573 struct si_shader_context *ctx =
1574 si_shader_context(&radeon_bld->soa.bld_base);
1575 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1576 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1577 LLVMValueRef value = 0;
1578
1579 switch (decl->Semantic.Name) {
1580 case TGSI_SEMANTIC_INSTANCEID:
1581 value = LLVMGetParam(radeon_bld->main_fn,
1582 ctx->param_instance_id);
1583 break;
1584
1585 case TGSI_SEMANTIC_VERTEXID:
1586 value = LLVMBuildAdd(gallivm->builder,
1587 LLVMGetParam(radeon_bld->main_fn,
1588 ctx->param_vertex_id),
1589 LLVMGetParam(radeon_bld->main_fn,
1590 SI_PARAM_BASE_VERTEX), "");
1591 break;
1592
1593 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1594 value = LLVMGetParam(radeon_bld->main_fn,
1595 ctx->param_vertex_id);
1596 break;
1597
1598 case TGSI_SEMANTIC_BASEVERTEX:
1599 value = LLVMGetParam(radeon_bld->main_fn,
1600 SI_PARAM_BASE_VERTEX);
1601 break;
1602
1603 case TGSI_SEMANTIC_BASEINSTANCE:
1604 value = LLVMGetParam(radeon_bld->main_fn,
1605 SI_PARAM_START_INSTANCE);
1606 break;
1607
1608 case TGSI_SEMANTIC_DRAWID:
1609 value = LLVMGetParam(radeon_bld->main_fn,
1610 SI_PARAM_DRAWID);
1611 break;
1612
1613 case TGSI_SEMANTIC_INVOCATIONID:
1614 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1615 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1616 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1617 value = LLVMGetParam(radeon_bld->main_fn,
1618 SI_PARAM_GS_INSTANCE_ID);
1619 else
1620 assert(!"INVOCATIONID not implemented");
1621 break;
1622
1623 case TGSI_SEMANTIC_POSITION:
1624 {
1625 LLVMValueRef pos[4] = {
1626 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1627 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1628 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1629 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1630 LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_POS_W_FLOAT)),
1632 };
1633 value = lp_build_gather_values(gallivm, pos, 4);
1634 break;
1635 }
1636
1637 case TGSI_SEMANTIC_FACE:
1638 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1639 break;
1640
1641 case TGSI_SEMANTIC_SAMPLEID:
1642 value = get_sample_id(radeon_bld);
1643 break;
1644
1645 case TGSI_SEMANTIC_SAMPLEPOS: {
1646 LLVMValueRef pos[4] = {
1647 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1648 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1649 lp_build_const_float(gallivm, 0),
1650 lp_build_const_float(gallivm, 0)
1651 };
1652 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1653 TGSI_OPCODE_FRC, pos[0]);
1654 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1655 TGSI_OPCODE_FRC, pos[1]);
1656 value = lp_build_gather_values(gallivm, pos, 4);
1657 break;
1658 }
1659
1660 case TGSI_SEMANTIC_SAMPLEMASK:
1661 /* This can only occur with the OpenGL Core profile, which
1662 * doesn't support smoothing.
1663 */
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1665 break;
1666
1667 case TGSI_SEMANTIC_TESSCOORD:
1668 {
1669 LLVMValueRef coord[4] = {
1670 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1671 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1672 bld->zero,
1673 bld->zero
1674 };
1675
1676 /* For triangles, the vector should be (u, v, 1-u-v). */
1677 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1678 PIPE_PRIM_TRIANGLES)
1679 coord[2] = lp_build_sub(bld, bld->one,
1680 lp_build_add(bld, coord[0], coord[1]));
1681
1682 value = lp_build_gather_values(gallivm, coord, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_VERTICESIN:
1687 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1688 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1689 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1690 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1691 else
1692 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1693 break;
1694
1695 case TGSI_SEMANTIC_TESSINNER:
1696 case TGSI_SEMANTIC_TESSOUTER:
1697 {
1698 LLVMValueRef rw_buffers, buffer, base, addr;
1699 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1700
1701 rw_buffers = LLVMGetParam(ctx->main_fn,
1702 SI_PARAM_RW_BUFFERS);
1703 buffer = build_indexed_load_const(ctx, rw_buffers,
1704 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1705
1706 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1707 addr = get_tcs_tes_buffer_address(ctx, NULL,
1708 lp_build_const_int32(gallivm, param));
1709
1710 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1711 ~0, buffer, base, addr);
1712
1713 break;
1714 }
1715
1716 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1717 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1718 {
1719 LLVMValueRef buf, slot, val[4];
1720 int i, offset;
1721
1722 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1723 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1724 buf = build_indexed_load_const(ctx, buf, slot);
1725 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1726
1727 for (i = 0; i < 4; i++)
1728 val[i] = buffer_load_const(ctx, buf,
1729 lp_build_const_int32(gallivm, (offset + i) * 4));
1730 value = lp_build_gather_values(gallivm, val, 4);
1731 break;
1732 }
1733
1734 case TGSI_SEMANTIC_PRIMID:
1735 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1736 break;
1737
1738 case TGSI_SEMANTIC_GRID_SIZE:
1739 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1740 break;
1741
1742 case TGSI_SEMANTIC_BLOCK_SIZE:
1743 {
1744 LLVMValueRef values[3];
1745 unsigned i;
1746 unsigned *properties = ctx->shader->selector->info.properties;
1747
1748 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1749 unsigned sizes[3] = {
1750 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1751 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1752 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1753 };
1754
1755 for (i = 0; i < 3; ++i)
1756 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1757
1758 value = lp_build_gather_values(gallivm, values, 3);
1759 } else {
1760 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1761 }
1762 break;
1763 }
1764
1765 case TGSI_SEMANTIC_BLOCK_ID:
1766 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1767 break;
1768
1769 case TGSI_SEMANTIC_THREAD_ID:
1770 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1771 break;
1772
1773 #if HAVE_LLVM >= 0x0309
1774 case TGSI_SEMANTIC_HELPER_INVOCATION:
1775 value = lp_build_intrinsic(gallivm->builder,
1776 "llvm.amdgcn.ps.live",
1777 ctx->i1, NULL, 0,
1778 LP_FUNC_ATTR_READNONE);
1779 value = LLVMBuildNot(gallivm->builder, value, "");
1780 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1781 break;
1782 #endif
1783
1784 default:
1785 assert(!"unknown system value");
1786 return;
1787 }
1788
1789 radeon_bld->system_values[index] = value;
1790 }
1791
1792 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1793 const struct tgsi_full_declaration *decl)
1794 {
1795 struct si_shader_context *ctx =
1796 si_shader_context(&radeon_bld->soa.bld_base);
1797 struct si_shader_selector *sel = ctx->shader->selector;
1798 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1799
1800 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1801 LLVMValueRef var;
1802
1803 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1804 assert(decl->Range.First == decl->Range.Last);
1805 assert(!ctx->shared_memory);
1806
1807 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1808 LLVMArrayType(ctx->i8, sel->local_size),
1809 "compute_lds",
1810 LOCAL_ADDR_SPACE);
1811 LLVMSetAlignment(var, 4);
1812
1813 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1814 }
1815
1816 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1817 {
1818 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1819 SI_PARAM_CONST_BUFFERS);
1820
1821 return build_indexed_load_const(ctx, list_ptr,
1822 LLVMConstInt(ctx->i32, i, 0));
1823 }
1824
1825 static LLVMValueRef fetch_constant(
1826 struct lp_build_tgsi_context *bld_base,
1827 const struct tgsi_full_src_register *reg,
1828 enum tgsi_opcode_type type,
1829 unsigned swizzle)
1830 {
1831 struct si_shader_context *ctx = si_shader_context(bld_base);
1832 struct lp_build_context *base = &bld_base->base;
1833 const struct tgsi_ind_register *ireg = &reg->Indirect;
1834 unsigned buf, idx;
1835
1836 LLVMValueRef addr, bufp;
1837 LLVMValueRef result;
1838
1839 if (swizzle == LP_CHAN_ALL) {
1840 unsigned chan;
1841 LLVMValueRef values[4];
1842 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1843 values[chan] = fetch_constant(bld_base, reg, type, chan);
1844
1845 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1846 }
1847
1848 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1849 idx = reg->Register.Index * 4 + swizzle;
1850
1851 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1852 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1853 LLVMValueRef index;
1854 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1855 reg->Dimension.Index,
1856 SI_NUM_CONST_BUFFERS);
1857 bufp = build_indexed_load_const(ctx, ptr, index);
1858 } else
1859 bufp = load_const_buffer_desc(ctx, buf);
1860
1861 if (reg->Register.Indirect) {
1862 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1863 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1864 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1865 addr = lp_build_add(&bld_base->uint_bld, addr,
1866 lp_build_const_int32(base->gallivm, idx * 4));
1867 } else {
1868 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1869 }
1870
1871 result = buffer_load_const(ctx, bufp, addr);
1872
1873 if (!tgsi_type_is_64bit(type))
1874 result = bitcast(bld_base, type, result);
1875 else {
1876 LLVMValueRef addr2, result2;
1877
1878 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1879 LLVMConstInt(ctx->i32, 4, 0));
1880 result2 = buffer_load_const(ctx, bufp, addr2);
1881
1882 result = si_llvm_emit_fetch_64bit(bld_base, type,
1883 result, result2);
1884 }
1885 return result;
1886 }
1887
1888 /* Upper 16 bits must be zero. */
1889 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1890 LLVMValueRef val[2])
1891 {
1892 return LLVMBuildOr(gallivm->builder, val[0],
1893 LLVMBuildShl(gallivm->builder, val[1],
1894 lp_build_const_int32(gallivm, 16),
1895 ""), "");
1896 }
1897
1898 /* Upper 16 bits are ignored and will be dropped. */
1899 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1900 LLVMValueRef val[2])
1901 {
1902 LLVMValueRef v[2] = {
1903 LLVMBuildAnd(gallivm->builder, val[0],
1904 lp_build_const_int32(gallivm, 0xffff), ""),
1905 val[1],
1906 };
1907 return si_llvm_pack_two_int16(gallivm, v);
1908 }
1909
1910 /* Initialize arguments for the shader export intrinsic */
1911 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1912 LLVMValueRef *values,
1913 unsigned target,
1914 LLVMValueRef *args)
1915 {
1916 struct si_shader_context *ctx = si_shader_context(bld_base);
1917 struct lp_build_context *uint =
1918 &ctx->soa.bld_base.uint_bld;
1919 struct lp_build_context *base = &bld_base->base;
1920 struct gallivm_state *gallivm = base->gallivm;
1921 LLVMBuilderRef builder = base->gallivm->builder;
1922 LLVMValueRef val[4];
1923 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1924 unsigned chan;
1925 bool is_int8;
1926
1927 /* Default is 0xf. Adjusted below depending on the format. */
1928 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1929
1930 /* Specify whether the EXEC mask represents the valid mask */
1931 args[1] = uint->zero;
1932
1933 /* Specify whether this is the last export */
1934 args[2] = uint->zero;
1935
1936 /* Specify the target we are exporting */
1937 args[3] = lp_build_const_int32(base->gallivm, target);
1938
1939 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1940 const struct si_shader_key *key = &ctx->shader->key;
1941 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1942 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1943
1944 assert(cbuf >= 0 && cbuf < 8);
1945 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1946 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1947 }
1948
1949 args[4] = uint->zero; /* COMPR flag */
1950 args[5] = base->undef;
1951 args[6] = base->undef;
1952 args[7] = base->undef;
1953 args[8] = base->undef;
1954
1955 switch (spi_shader_col_format) {
1956 case V_028714_SPI_SHADER_ZERO:
1957 args[0] = uint->zero; /* writemask */
1958 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1959 break;
1960
1961 case V_028714_SPI_SHADER_32_R:
1962 args[0] = uint->one; /* writemask */
1963 args[5] = values[0];
1964 break;
1965
1966 case V_028714_SPI_SHADER_32_GR:
1967 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1968 args[5] = values[0];
1969 args[6] = values[1];
1970 break;
1971
1972 case V_028714_SPI_SHADER_32_AR:
1973 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1974 args[5] = values[0];
1975 args[8] = values[3];
1976 break;
1977
1978 case V_028714_SPI_SHADER_FP16_ABGR:
1979 args[4] = uint->one; /* COMPR flag */
1980
1981 for (chan = 0; chan < 2; chan++) {
1982 LLVMValueRef pack_args[2] = {
1983 values[2 * chan],
1984 values[2 * chan + 1]
1985 };
1986 LLVMValueRef packed;
1987
1988 packed = lp_build_intrinsic(base->gallivm->builder,
1989 "llvm.SI.packf16",
1990 ctx->i32, pack_args, 2,
1991 LP_FUNC_ATTR_READNONE);
1992 args[chan + 5] =
1993 LLVMBuildBitCast(base->gallivm->builder,
1994 packed, ctx->f32, "");
1995 }
1996 break;
1997
1998 case V_028714_SPI_SHADER_UNORM16_ABGR:
1999 for (chan = 0; chan < 4; chan++) {
2000 val[chan] = si_llvm_saturate(bld_base, values[chan]);
2001 val[chan] = LLVMBuildFMul(builder, val[chan],
2002 lp_build_const_float(gallivm, 65535), "");
2003 val[chan] = LLVMBuildFAdd(builder, val[chan],
2004 lp_build_const_float(gallivm, 0.5), "");
2005 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2006 ctx->i32, "");
2007 }
2008
2009 args[4] = uint->one; /* COMPR flag */
2010 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2011 si_llvm_pack_two_int16(gallivm, val));
2012 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2013 si_llvm_pack_two_int16(gallivm, val+2));
2014 break;
2015
2016 case V_028714_SPI_SHADER_SNORM16_ABGR:
2017 for (chan = 0; chan < 4; chan++) {
2018 /* Clamp between [-1, 1]. */
2019 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2020 values[chan],
2021 lp_build_const_float(gallivm, 1));
2022 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2023 val[chan],
2024 lp_build_const_float(gallivm, -1));
2025 /* Convert to a signed integer in [-32767, 32767]. */
2026 val[chan] = LLVMBuildFMul(builder, val[chan],
2027 lp_build_const_float(gallivm, 32767), "");
2028 /* If positive, add 0.5, else add -0.5. */
2029 val[chan] = LLVMBuildFAdd(builder, val[chan],
2030 LLVMBuildSelect(builder,
2031 LLVMBuildFCmp(builder, LLVMRealOGE,
2032 val[chan], base->zero, ""),
2033 lp_build_const_float(gallivm, 0.5),
2034 lp_build_const_float(gallivm, -0.5), ""), "");
2035 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2036 }
2037
2038 args[4] = uint->one; /* COMPR flag */
2039 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2040 si_llvm_pack_two_int32_as_int16(gallivm, val));
2041 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2042 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2043 break;
2044
2045 case V_028714_SPI_SHADER_UINT16_ABGR: {
2046 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2047 255 : 65535);
2048 /* Clamp. */
2049 for (chan = 0; chan < 4; chan++) {
2050 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2051 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2052 val[chan], max);
2053 }
2054
2055 args[4] = uint->one; /* COMPR flag */
2056 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2057 si_llvm_pack_two_int16(gallivm, val));
2058 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2059 si_llvm_pack_two_int16(gallivm, val+2));
2060 break;
2061 }
2062
2063 case V_028714_SPI_SHADER_SINT16_ABGR: {
2064 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2065 127 : 32767);
2066 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2067 -128 : -32768);
2068 /* Clamp. */
2069 for (chan = 0; chan < 4; chan++) {
2070 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2071 val[chan] = lp_build_emit_llvm_binary(bld_base,
2072 TGSI_OPCODE_IMIN,
2073 val[chan], max);
2074 val[chan] = lp_build_emit_llvm_binary(bld_base,
2075 TGSI_OPCODE_IMAX,
2076 val[chan], min);
2077 }
2078
2079 args[4] = uint->one; /* COMPR flag */
2080 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2081 si_llvm_pack_two_int32_as_int16(gallivm, val));
2082 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2084 break;
2085 }
2086
2087 case V_028714_SPI_SHADER_32_ABGR:
2088 memcpy(&args[5], values, sizeof(values[0]) * 4);
2089 break;
2090 }
2091 }
2092
2093 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2094 LLVMValueRef alpha)
2095 {
2096 struct si_shader_context *ctx = si_shader_context(bld_base);
2097 struct gallivm_state *gallivm = bld_base->base.gallivm;
2098
2099 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2100 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2101 SI_PARAM_ALPHA_REF);
2102
2103 LLVMValueRef alpha_pass =
2104 lp_build_cmp(&bld_base->base,
2105 ctx->shader->key.part.ps.epilog.alpha_func,
2106 alpha, alpha_ref);
2107 LLVMValueRef arg =
2108 lp_build_select(&bld_base->base,
2109 alpha_pass,
2110 lp_build_const_float(gallivm, 1.0f),
2111 lp_build_const_float(gallivm, -1.0f));
2112
2113 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2114 ctx->voidt, &arg, 1, 0);
2115 } else {
2116 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2117 ctx->voidt, NULL, 0, 0);
2118 }
2119 }
2120
2121 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2122 LLVMValueRef alpha,
2123 unsigned samplemask_param)
2124 {
2125 struct si_shader_context *ctx = si_shader_context(bld_base);
2126 struct gallivm_state *gallivm = bld_base->base.gallivm;
2127 LLVMValueRef coverage;
2128
2129 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2130 coverage = LLVMGetParam(ctx->main_fn,
2131 samplemask_param);
2132 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2133
2134 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2135 ctx->i32,
2136 &coverage, 1, LP_FUNC_ATTR_READNONE);
2137
2138 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2139 ctx->f32, "");
2140
2141 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2142 lp_build_const_float(gallivm,
2143 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2144
2145 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2146 }
2147
2148 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2149 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2150 {
2151 struct si_shader_context *ctx = si_shader_context(bld_base);
2152 struct lp_build_context *base = &bld_base->base;
2153 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2154 unsigned reg_index;
2155 unsigned chan;
2156 unsigned const_chan;
2157 LLVMValueRef base_elt;
2158 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2159 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2160 SI_VS_CONST_CLIP_PLANES);
2161 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2162
2163 for (reg_index = 0; reg_index < 2; reg_index ++) {
2164 LLVMValueRef *args = pos[2 + reg_index];
2165
2166 args[5] =
2167 args[6] =
2168 args[7] =
2169 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2170
2171 /* Compute dot products of position and user clip plane vectors */
2172 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2173 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2174 args[1] = lp_build_const_int32(base->gallivm,
2175 ((reg_index * 4 + chan) * 4 +
2176 const_chan) * 4);
2177 base_elt = buffer_load_const(ctx, const_resource,
2178 args[1]);
2179 args[5 + chan] =
2180 lp_build_add(base, args[5 + chan],
2181 lp_build_mul(base, base_elt,
2182 out_elts[const_chan]));
2183 }
2184 }
2185
2186 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2187 args[1] = uint->zero;
2188 args[2] = uint->zero;
2189 args[3] = lp_build_const_int32(base->gallivm,
2190 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2191 args[4] = uint->zero;
2192 }
2193 }
2194
2195 static void si_dump_streamout(struct pipe_stream_output_info *so)
2196 {
2197 unsigned i;
2198
2199 if (so->num_outputs)
2200 fprintf(stderr, "STREAMOUT\n");
2201
2202 for (i = 0; i < so->num_outputs; i++) {
2203 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2204 so->output[i].start_component;
2205 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2206 i, so->output[i].output_buffer,
2207 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2208 so->output[i].register_index,
2209 mask & 1 ? "x" : "",
2210 mask & 2 ? "y" : "",
2211 mask & 4 ? "z" : "",
2212 mask & 8 ? "w" : "");
2213 }
2214 }
2215
2216 /* On SI, the vertex shader is responsible for writing streamout data
2217 * to buffers. */
2218 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2219 struct si_shader_output_values *outputs,
2220 unsigned noutput)
2221 {
2222 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2223 struct gallivm_state *gallivm = &ctx->gallivm;
2224 LLVMBuilderRef builder = gallivm->builder;
2225 int i, j;
2226 struct lp_build_if_state if_ctx;
2227 LLVMValueRef so_buffers[4];
2228 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2229 SI_PARAM_RW_BUFFERS);
2230
2231 /* Load the descriptors. */
2232 for (i = 0; i < 4; ++i) {
2233 if (ctx->shader->selector->so.stride[i]) {
2234 LLVMValueRef offset = lp_build_const_int32(gallivm,
2235 SI_VS_STREAMOUT_BUF0 + i);
2236
2237 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2238 }
2239 }
2240
2241 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2242 LLVMValueRef so_vtx_count =
2243 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2244
2245 LLVMValueRef tid = get_thread_id(ctx);
2246
2247 /* can_emit = tid < so_vtx_count; */
2248 LLVMValueRef can_emit =
2249 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2250
2251 LLVMValueRef stream_id =
2252 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2253
2254 /* Emit the streamout code conditionally. This actually avoids
2255 * out-of-bounds buffer access. The hw tells us via the SGPR
2256 * (so_vtx_count) which threads are allowed to emit streamout data. */
2257 lp_build_if(&if_ctx, gallivm, can_emit);
2258 {
2259 /* The buffer offset is computed as follows:
2260 * ByteOffset = streamout_offset[buffer_id]*4 +
2261 * (streamout_write_index + thread_id)*stride[buffer_id] +
2262 * attrib_offset
2263 */
2264
2265 LLVMValueRef so_write_index =
2266 LLVMGetParam(ctx->main_fn,
2267 ctx->param_streamout_write_index);
2268
2269 /* Compute (streamout_write_index + thread_id). */
2270 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2271
2272 /* Compute the write offset for each enabled buffer. */
2273 LLVMValueRef so_write_offset[4] = {};
2274 for (i = 0; i < 4; i++) {
2275 if (!so->stride[i])
2276 continue;
2277
2278 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2279 ctx->param_streamout_offset[i]);
2280 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2281
2282 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2283 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2284 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2285 }
2286
2287 /* Write streamout data. */
2288 for (i = 0; i < so->num_outputs; i++) {
2289 unsigned buf_idx = so->output[i].output_buffer;
2290 unsigned reg = so->output[i].register_index;
2291 unsigned start = so->output[i].start_component;
2292 unsigned num_comps = so->output[i].num_components;
2293 unsigned stream = so->output[i].stream;
2294 LLVMValueRef out[4];
2295 struct lp_build_if_state if_ctx_stream;
2296
2297 assert(num_comps && num_comps <= 4);
2298 if (!num_comps || num_comps > 4)
2299 continue;
2300
2301 if (reg >= noutput)
2302 continue;
2303
2304 /* Load the output as int. */
2305 for (j = 0; j < num_comps; j++) {
2306 out[j] = LLVMBuildBitCast(builder,
2307 outputs[reg].values[start+j],
2308 ctx->i32, "");
2309 }
2310
2311 /* Pack the output. */
2312 LLVMValueRef vdata = NULL;
2313
2314 switch (num_comps) {
2315 case 1: /* as i32 */
2316 vdata = out[0];
2317 break;
2318 case 2: /* as v2i32 */
2319 case 3: /* as v4i32 (aligned to 4) */
2320 case 4: /* as v4i32 */
2321 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2322 for (j = 0; j < num_comps; j++) {
2323 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2324 LLVMConstInt(ctx->i32, j, 0), "");
2325 }
2326 break;
2327 }
2328
2329 LLVMValueRef can_emit_stream =
2330 LLVMBuildICmp(builder, LLVMIntEQ,
2331 stream_id,
2332 lp_build_const_int32(gallivm, stream), "");
2333
2334 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2335 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2336 vdata, num_comps,
2337 so_write_offset[buf_idx],
2338 LLVMConstInt(ctx->i32, 0, 0),
2339 so->output[i].dst_offset*4);
2340 lp_build_endif(&if_ctx_stream);
2341 }
2342 }
2343 lp_build_endif(&if_ctx);
2344 }
2345
2346
2347 /* Generate export instructions for hardware VS shader stage */
2348 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2349 struct si_shader_output_values *outputs,
2350 unsigned noutput)
2351 {
2352 struct si_shader_context *ctx = si_shader_context(bld_base);
2353 struct si_shader *shader = ctx->shader;
2354 struct lp_build_context *base = &bld_base->base;
2355 struct lp_build_context *uint =
2356 &ctx->soa.bld_base.uint_bld;
2357 LLVMValueRef args[9];
2358 LLVMValueRef pos_args[4][9] = { { 0 } };
2359 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2360 unsigned semantic_name, semantic_index;
2361 unsigned target;
2362 unsigned param_count = 0;
2363 unsigned pos_idx;
2364 int i;
2365
2366 if (outputs && ctx->shader->selector->so.num_outputs) {
2367 si_llvm_emit_streamout(ctx, outputs, noutput);
2368 }
2369
2370 for (i = 0; i < noutput; i++) {
2371 semantic_name = outputs[i].name;
2372 semantic_index = outputs[i].sid;
2373 bool export_param = true;
2374
2375 switch (semantic_name) {
2376 case TGSI_SEMANTIC_POSITION: /* ignore these */
2377 case TGSI_SEMANTIC_PSIZE:
2378 case TGSI_SEMANTIC_CLIPVERTEX:
2379 case TGSI_SEMANTIC_EDGEFLAG:
2380 break;
2381 case TGSI_SEMANTIC_GENERIC:
2382 case TGSI_SEMANTIC_CLIPDIST:
2383 if (shader->key.opt.hw_vs.kill_outputs &
2384 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2385 export_param = false;
2386 break;
2387 default:
2388 if (shader->key.opt.hw_vs.kill_outputs2 &
2389 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2390 export_param = false;
2391 break;
2392 }
2393
2394 handle_semantic:
2395 /* Select the correct target */
2396 switch(semantic_name) {
2397 case TGSI_SEMANTIC_PSIZE:
2398 psize_value = outputs[i].values[0];
2399 continue;
2400 case TGSI_SEMANTIC_EDGEFLAG:
2401 edgeflag_value = outputs[i].values[0];
2402 continue;
2403 case TGSI_SEMANTIC_LAYER:
2404 layer_value = outputs[i].values[0];
2405 semantic_name = TGSI_SEMANTIC_GENERIC;
2406 goto handle_semantic;
2407 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2408 viewport_index_value = outputs[i].values[0];
2409 semantic_name = TGSI_SEMANTIC_GENERIC;
2410 goto handle_semantic;
2411 case TGSI_SEMANTIC_POSITION:
2412 target = V_008DFC_SQ_EXP_POS;
2413 break;
2414 case TGSI_SEMANTIC_COLOR:
2415 case TGSI_SEMANTIC_BCOLOR:
2416 if (!export_param)
2417 continue;
2418 target = V_008DFC_SQ_EXP_PARAM + param_count;
2419 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2420 shader->info.vs_output_param_offset[i] = param_count;
2421 param_count++;
2422 break;
2423 case TGSI_SEMANTIC_CLIPDIST:
2424 if (shader->key.opt.hw_vs.clip_disable) {
2425 semantic_name = TGSI_SEMANTIC_GENERIC;
2426 goto handle_semantic;
2427 }
2428 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2429 break;
2430 case TGSI_SEMANTIC_CLIPVERTEX:
2431 if (shader->key.opt.hw_vs.clip_disable)
2432 continue;
2433 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2434 continue;
2435 case TGSI_SEMANTIC_PRIMID:
2436 case TGSI_SEMANTIC_FOG:
2437 case TGSI_SEMANTIC_TEXCOORD:
2438 case TGSI_SEMANTIC_GENERIC:
2439 if (!export_param)
2440 continue;
2441 target = V_008DFC_SQ_EXP_PARAM + param_count;
2442 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2443 shader->info.vs_output_param_offset[i] = param_count;
2444 param_count++;
2445 break;
2446 default:
2447 target = 0;
2448 fprintf(stderr,
2449 "Warning: SI unhandled vs output type:%d\n",
2450 semantic_name);
2451 }
2452
2453 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2454
2455 if (target >= V_008DFC_SQ_EXP_POS &&
2456 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2457 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2458 args, sizeof(args));
2459 } else {
2460 lp_build_intrinsic(base->gallivm->builder,
2461 "llvm.SI.export", ctx->voidt,
2462 args, 9, 0);
2463 }
2464
2465 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2466 semantic_name = TGSI_SEMANTIC_GENERIC;
2467 goto handle_semantic;
2468 }
2469 }
2470
2471 shader->info.nr_param_exports = param_count;
2472
2473 /* We need to add the position output manually if it's missing. */
2474 if (!pos_args[0][0]) {
2475 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2476 pos_args[0][1] = uint->zero; /* EXEC mask */
2477 pos_args[0][2] = uint->zero; /* last export? */
2478 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2479 pos_args[0][4] = uint->zero; /* COMPR flag */
2480 pos_args[0][5] = base->zero; /* X */
2481 pos_args[0][6] = base->zero; /* Y */
2482 pos_args[0][7] = base->zero; /* Z */
2483 pos_args[0][8] = base->one; /* W */
2484 }
2485
2486 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2487 if (shader->selector->info.writes_psize ||
2488 shader->selector->info.writes_edgeflag ||
2489 shader->selector->info.writes_viewport_index ||
2490 shader->selector->info.writes_layer) {
2491 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2492 shader->selector->info.writes_psize |
2493 (shader->selector->info.writes_edgeflag << 1) |
2494 (shader->selector->info.writes_layer << 2) |
2495 (shader->selector->info.writes_viewport_index << 3));
2496 pos_args[1][1] = uint->zero; /* EXEC mask */
2497 pos_args[1][2] = uint->zero; /* last export? */
2498 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2499 pos_args[1][4] = uint->zero; /* COMPR flag */
2500 pos_args[1][5] = base->zero; /* X */
2501 pos_args[1][6] = base->zero; /* Y */
2502 pos_args[1][7] = base->zero; /* Z */
2503 pos_args[1][8] = base->zero; /* W */
2504
2505 if (shader->selector->info.writes_psize)
2506 pos_args[1][5] = psize_value;
2507
2508 if (shader->selector->info.writes_edgeflag) {
2509 /* The output is a float, but the hw expects an integer
2510 * with the first bit containing the edge flag. */
2511 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2512 edgeflag_value,
2513 ctx->i32, "");
2514 edgeflag_value = lp_build_min(&bld_base->int_bld,
2515 edgeflag_value,
2516 bld_base->int_bld.one);
2517
2518 /* The LLVM intrinsic expects a float. */
2519 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2520 edgeflag_value,
2521 ctx->f32, "");
2522 }
2523
2524 if (shader->selector->info.writes_layer)
2525 pos_args[1][7] = layer_value;
2526
2527 if (shader->selector->info.writes_viewport_index)
2528 pos_args[1][8] = viewport_index_value;
2529 }
2530
2531 for (i = 0; i < 4; i++)
2532 if (pos_args[i][0])
2533 shader->info.nr_pos_exports++;
2534
2535 pos_idx = 0;
2536 for (i = 0; i < 4; i++) {
2537 if (!pos_args[i][0])
2538 continue;
2539
2540 /* Specify the target we are exporting */
2541 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2542
2543 if (pos_idx == shader->info.nr_pos_exports)
2544 /* Specify that this is the last export */
2545 pos_args[i][2] = uint->one;
2546
2547 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2548 ctx->voidt, pos_args[i], 9, 0);
2549 }
2550 }
2551
2552 /**
2553 * Forward all outputs from the vertex shader to the TES. This is only used
2554 * for the fixed function TCS.
2555 */
2556 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2557 {
2558 struct si_shader_context *ctx = si_shader_context(bld_base);
2559 struct gallivm_state *gallivm = bld_base->base.gallivm;
2560 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2561 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2562 uint64_t inputs;
2563
2564 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2565
2566 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2567 buffer = build_indexed_load_const(ctx, rw_buffers,
2568 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2569
2570 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2571
2572 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2573 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2574 lds_vertex_stride, "");
2575 lds_base = get_tcs_in_current_patch_offset(ctx);
2576 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2577
2578 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2579 while (inputs) {
2580 unsigned i = u_bit_scan64(&inputs);
2581
2582 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2583 lp_build_const_int32(gallivm, 4 * i),
2584 "");
2585
2586 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2587 invocation_id,
2588 lp_build_const_int32(gallivm, i));
2589
2590 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2591 lds_ptr);
2592
2593 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2594 buffer_offset, 0);
2595 }
2596 }
2597
2598 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2599 LLVMValueRef rel_patch_id,
2600 LLVMValueRef invocation_id,
2601 LLVMValueRef tcs_out_current_patch_data_offset)
2602 {
2603 struct si_shader_context *ctx = si_shader_context(bld_base);
2604 struct gallivm_state *gallivm = bld_base->base.gallivm;
2605 struct si_shader *shader = ctx->shader;
2606 unsigned tess_inner_index, tess_outer_index;
2607 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2608 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2609 unsigned stride, outer_comps, inner_comps, i;
2610 struct lp_build_if_state if_ctx, inner_if_ctx;
2611
2612 si_llvm_emit_barrier(NULL, bld_base, NULL);
2613
2614 /* Do this only for invocation 0, because the tess levels are per-patch,
2615 * not per-vertex.
2616 *
2617 * This can't jump, because invocation 0 executes this. It should
2618 * at least mask out the loads and stores for other invocations.
2619 */
2620 lp_build_if(&if_ctx, gallivm,
2621 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2622 invocation_id, bld_base->uint_bld.zero, ""));
2623
2624 /* Determine the layout of one tess factor element in the buffer. */
2625 switch (shader->key.part.tcs.epilog.prim_mode) {
2626 case PIPE_PRIM_LINES:
2627 stride = 2; /* 2 dwords, 1 vec2 store */
2628 outer_comps = 2;
2629 inner_comps = 0;
2630 break;
2631 case PIPE_PRIM_TRIANGLES:
2632 stride = 4; /* 4 dwords, 1 vec4 store */
2633 outer_comps = 3;
2634 inner_comps = 1;
2635 break;
2636 case PIPE_PRIM_QUADS:
2637 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2638 outer_comps = 4;
2639 inner_comps = 2;
2640 break;
2641 default:
2642 assert(0);
2643 return;
2644 }
2645
2646 /* Load tess_inner and tess_outer from LDS.
2647 * Any invocation can write them, so we can't get them from a temporary.
2648 */
2649 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2650 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2651
2652 lds_base = tcs_out_current_patch_data_offset;
2653 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2654 lp_build_const_int32(gallivm,
2655 tess_inner_index * 4), "");
2656 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2657 lp_build_const_int32(gallivm,
2658 tess_outer_index * 4), "");
2659
2660 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2661 /* For isolines, the hardware expects tess factors in the
2662 * reverse order from what GLSL / TGSI specify.
2663 */
2664 out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2665 out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2666 } else {
2667 for (i = 0; i < outer_comps; i++)
2668 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2669 for (i = 0; i < inner_comps; i++)
2670 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2671 }
2672
2673 /* Convert the outputs to vectors for stores. */
2674 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2675 vec1 = NULL;
2676
2677 if (stride > 4)
2678 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2679
2680 /* Get the buffer. */
2681 rw_buffers = LLVMGetParam(ctx->main_fn,
2682 SI_PARAM_RW_BUFFERS);
2683 buffer = build_indexed_load_const(ctx, rw_buffers,
2684 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2685
2686 /* Get the offset. */
2687 tf_base = LLVMGetParam(ctx->main_fn,
2688 SI_PARAM_TESS_FACTOR_OFFSET);
2689 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2690 lp_build_const_int32(gallivm, 4 * stride), "");
2691
2692 lp_build_if(&inner_if_ctx, gallivm,
2693 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2694 rel_patch_id, bld_base->uint_bld.zero, ""));
2695
2696 /* Store the dynamic HS control word. */
2697 build_tbuffer_store_dwords(ctx, buffer,
2698 lp_build_const_int32(gallivm, 0x80000000),
2699 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2700
2701 lp_build_endif(&inner_if_ctx);
2702
2703 /* Store the tessellation factors. */
2704 build_tbuffer_store_dwords(ctx, buffer, vec0,
2705 MIN2(stride, 4), byteoffset, tf_base, 4);
2706 if (vec1)
2707 build_tbuffer_store_dwords(ctx, buffer, vec1,
2708 stride - 4, byteoffset, tf_base, 20);
2709 lp_build_endif(&if_ctx);
2710 }
2711
2712 /* This only writes the tessellation factor levels. */
2713 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2714 {
2715 struct si_shader_context *ctx = si_shader_context(bld_base);
2716 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2717
2718 si_copy_tcs_inputs(bld_base);
2719
2720 rel_patch_id = get_rel_patch_id(ctx);
2721 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2722 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2723
2724 /* Return epilog parameters from this function. */
2725 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2726 LLVMValueRef ret = ctx->return_value;
2727 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2728 unsigned vgpr;
2729
2730 /* RW_BUFFERS pointer */
2731 rw_buffers = LLVMGetParam(ctx->main_fn,
2732 SI_PARAM_RW_BUFFERS);
2733 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2734 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2735 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2736 bld_base->uint_bld.zero, "");
2737 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2738 bld_base->uint_bld.one, "");
2739 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2740 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2741
2742 /* Tess factor buffer soffset is after user SGPRs. */
2743 tf_soffset = LLVMGetParam(ctx->main_fn,
2744 SI_PARAM_TESS_FACTOR_OFFSET);
2745 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2746 SI_TCS_NUM_USER_SGPR + 1, "");
2747
2748 /* VGPRs */
2749 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2750 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2751 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2752
2753 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2754 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2755 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2756 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2757 ctx->return_value = ret;
2758 }
2759
2760 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2761 {
2762 struct si_shader_context *ctx = si_shader_context(bld_base);
2763 struct si_shader *shader = ctx->shader;
2764 struct tgsi_shader_info *info = &shader->selector->info;
2765 struct gallivm_state *gallivm = bld_base->base.gallivm;
2766 unsigned i, chan;
2767 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2768 ctx->param_rel_auto_id);
2769 LLVMValueRef vertex_dw_stride =
2770 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2771 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2772 vertex_dw_stride, "");
2773
2774 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2775 * its inputs from it. */
2776 for (i = 0; i < info->num_outputs; i++) {
2777 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2778 unsigned name = info->output_semantic_name[i];
2779 unsigned index = info->output_semantic_index[i];
2780 int param = si_shader_io_get_unique_index(name, index);
2781 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2782 lp_build_const_int32(gallivm, param * 4), "");
2783
2784 for (chan = 0; chan < 4; chan++) {
2785 lds_store(bld_base, chan, dw_addr,
2786 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2787 }
2788 }
2789 }
2790
2791 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2792 {
2793 struct si_shader_context *ctx = si_shader_context(bld_base);
2794 struct gallivm_state *gallivm = bld_base->base.gallivm;
2795 struct si_shader *es = ctx->shader;
2796 struct tgsi_shader_info *info = &es->selector->info;
2797 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2798 ctx->param_es2gs_offset);
2799 unsigned chan;
2800 int i;
2801
2802 for (i = 0; i < info->num_outputs; i++) {
2803 LLVMValueRef *out_ptr =
2804 ctx->soa.outputs[i];
2805 int param_index;
2806
2807 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2808 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2809 continue;
2810
2811 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2812 info->output_semantic_index[i]);
2813
2814 for (chan = 0; chan < 4; chan++) {
2815 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2816 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2817
2818 build_tbuffer_store(ctx,
2819 ctx->esgs_ring,
2820 out_val, 1,
2821 LLVMGetUndef(ctx->i32), soffset,
2822 (4 * param_index + chan) * 4,
2823 V_008F0C_BUF_DATA_FORMAT_32,
2824 V_008F0C_BUF_NUM_FORMAT_UINT,
2825 0, 0, 1, 1, 0);
2826 }
2827 }
2828 }
2829
2830 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2831 {
2832 struct si_shader_context *ctx = si_shader_context(bld_base);
2833 struct gallivm_state *gallivm = bld_base->base.gallivm;
2834 LLVMValueRef args[2];
2835
2836 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2837 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2838 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2839 ctx->voidt, args, 2, 0);
2840 }
2841
2842 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2843 {
2844 struct si_shader_context *ctx = si_shader_context(bld_base);
2845 struct gallivm_state *gallivm = bld_base->base.gallivm;
2846 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2847 struct si_shader_output_values *outputs = NULL;
2848 int i,j;
2849
2850 assert(!ctx->shader->is_gs_copy_shader);
2851
2852 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2853
2854 /* Vertex color clamping.
2855 *
2856 * This uses a state constant loaded in a user data SGPR and
2857 * an IF statement is added that clamps all colors if the constant
2858 * is true.
2859 */
2860 if (ctx->type == PIPE_SHADER_VERTEX) {
2861 struct lp_build_if_state if_ctx;
2862 LLVMValueRef cond = NULL;
2863 LLVMValueRef addr, val;
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2867 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2868 continue;
2869
2870 /* We've found a color. */
2871 if (!cond) {
2872 /* The state is in the first bit of the user SGPR. */
2873 cond = LLVMGetParam(ctx->main_fn,
2874 SI_PARAM_VS_STATE_BITS);
2875 cond = LLVMBuildTrunc(gallivm->builder, cond,
2876 ctx->i1, "");
2877 lp_build_if(&if_ctx, gallivm, cond);
2878 }
2879
2880 for (j = 0; j < 4; j++) {
2881 addr = ctx->soa.outputs[i][j];
2882 val = LLVMBuildLoad(gallivm->builder, addr, "");
2883 val = si_llvm_saturate(bld_base, val);
2884 LLVMBuildStore(gallivm->builder, val, addr);
2885 }
2886 }
2887
2888 if (cond)
2889 lp_build_endif(&if_ctx);
2890 }
2891
2892 for (i = 0; i < info->num_outputs; i++) {
2893 outputs[i].name = info->output_semantic_name[i];
2894 outputs[i].sid = info->output_semantic_index[i];
2895
2896 for (j = 0; j < 4; j++)
2897 outputs[i].values[j] =
2898 LLVMBuildLoad(gallivm->builder,
2899 ctx->soa.outputs[i][j],
2900 "");
2901 }
2902
2903 /* Return the primitive ID from the LLVM function. */
2904 ctx->return_value =
2905 LLVMBuildInsertValue(gallivm->builder,
2906 ctx->return_value,
2907 bitcast(bld_base, TGSI_TYPE_FLOAT,
2908 get_primitive_id(bld_base, 0)),
2909 VS_EPILOG_PRIMID_LOC, "");
2910
2911 si_llvm_export_vs(bld_base, outputs, i);
2912 FREE(outputs);
2913 }
2914
2915 struct si_ps_exports {
2916 unsigned num;
2917 LLVMValueRef args[10][9];
2918 };
2919
2920 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2921 bool writes_samplemask)
2922 {
2923 if (writes_z) {
2924 /* Z needs 32 bits. */
2925 if (writes_samplemask)
2926 return V_028710_SPI_SHADER_32_ABGR;
2927 else if (writes_stencil)
2928 return V_028710_SPI_SHADER_32_GR;
2929 else
2930 return V_028710_SPI_SHADER_32_R;
2931 } else if (writes_stencil || writes_samplemask) {
2932 /* Both stencil and sample mask need only 16 bits. */
2933 return V_028710_SPI_SHADER_UINT16_ABGR;
2934 } else {
2935 return V_028710_SPI_SHADER_ZERO;
2936 }
2937 }
2938
2939 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2940 LLVMValueRef depth, LLVMValueRef stencil,
2941 LLVMValueRef samplemask, struct si_ps_exports *exp)
2942 {
2943 struct si_shader_context *ctx = si_shader_context(bld_base);
2944 struct lp_build_context *base = &bld_base->base;
2945 struct lp_build_context *uint = &bld_base->uint_bld;
2946 LLVMValueRef args[9];
2947 unsigned mask = 0;
2948 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2949 stencil != NULL,
2950 samplemask != NULL);
2951
2952 assert(depth || stencil || samplemask);
2953
2954 args[1] = uint->one; /* whether the EXEC mask is valid */
2955 args[2] = uint->one; /* DONE bit */
2956
2957 /* Specify the target we are exporting */
2958 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2959
2960 args[4] = uint->zero; /* COMP flag */
2961 args[5] = base->undef; /* R, depth */
2962 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2963 args[7] = base->undef; /* B, sample mask */
2964 args[8] = base->undef; /* A, alpha to mask */
2965
2966 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2967 assert(!depth);
2968 args[4] = uint->one; /* COMPR flag */
2969
2970 if (stencil) {
2971 /* Stencil should be in X[23:16]. */
2972 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2973 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2974 LLVMConstInt(ctx->i32, 16, 0), "");
2975 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2976 mask |= 0x3;
2977 }
2978 if (samplemask) {
2979 /* SampleMask should be in Y[15:0]. */
2980 args[6] = samplemask;
2981 mask |= 0xc;
2982 }
2983 } else {
2984 if (depth) {
2985 args[5] = depth;
2986 mask |= 0x1;
2987 }
2988 if (stencil) {
2989 args[6] = stencil;
2990 mask |= 0x2;
2991 }
2992 if (samplemask) {
2993 args[7] = samplemask;
2994 mask |= 0x4;
2995 }
2996 }
2997
2998 /* SI (except OLAND and HAINAN) has a bug that it only looks
2999 * at the X writemask component. */
3000 if (ctx->screen->b.chip_class == SI &&
3001 ctx->screen->b.family != CHIP_OLAND &&
3002 ctx->screen->b.family != CHIP_HAINAN)
3003 mask |= 0x1;
3004
3005 /* Specify which components to enable */
3006 args[0] = lp_build_const_int32(base->gallivm, mask);
3007
3008 memcpy(exp->args[exp->num++], args, sizeof(args));
3009 }
3010
3011 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3012 LLVMValueRef *color, unsigned index,
3013 unsigned samplemask_param,
3014 bool is_last, struct si_ps_exports *exp)
3015 {
3016 struct si_shader_context *ctx = si_shader_context(bld_base);
3017 struct lp_build_context *base = &bld_base->base;
3018 int i;
3019
3020 /* Clamp color */
3021 if (ctx->shader->key.part.ps.epilog.clamp_color)
3022 for (i = 0; i < 4; i++)
3023 color[i] = si_llvm_saturate(bld_base, color[i]);
3024
3025 /* Alpha to one */
3026 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3027 color[3] = base->one;
3028
3029 /* Alpha test */
3030 if (index == 0 &&
3031 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3032 si_alpha_test(bld_base, color[3]);
3033
3034 /* Line & polygon smoothing */
3035 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3036 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3037 samplemask_param);
3038
3039 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3040 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3041 LLVMValueRef args[8][9];
3042 int c, last = -1;
3043
3044 /* Get the export arguments, also find out what the last one is. */
3045 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3046 si_llvm_init_export_args(bld_base, color,
3047 V_008DFC_SQ_EXP_MRT + c, args[c]);
3048 if (args[c][0] != bld_base->uint_bld.zero)
3049 last = c;
3050 }
3051
3052 /* Emit all exports. */
3053 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3054 if (is_last && last == c) {
3055 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3056 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3057 } else if (args[c][0] == bld_base->uint_bld.zero)
3058 continue; /* unnecessary NULL export */
3059
3060 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3061 }
3062 } else {
3063 LLVMValueRef args[9];
3064
3065 /* Export */
3066 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3067 args);
3068 if (is_last) {
3069 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3070 args[2] = bld_base->uint_bld.one; /* DONE bit */
3071 } else if (args[0] == bld_base->uint_bld.zero)
3072 return; /* unnecessary NULL export */
3073
3074 memcpy(exp->args[exp->num++], args, sizeof(args));
3075 }
3076 }
3077
3078 static void si_emit_ps_exports(struct si_shader_context *ctx,
3079 struct si_ps_exports *exp)
3080 {
3081 for (unsigned i = 0; i < exp->num; i++)
3082 lp_build_intrinsic(ctx->gallivm.builder,
3083 "llvm.SI.export", ctx->voidt,
3084 exp->args[i], 9, 0);
3085 }
3086
3087 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3088 {
3089 struct si_shader_context *ctx = si_shader_context(bld_base);
3090 struct lp_build_context *base = &bld_base->base;
3091 struct lp_build_context *uint = &bld_base->uint_bld;
3092 LLVMValueRef args[9];
3093
3094 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3095 args[1] = uint->one; /* whether the EXEC mask is valid */
3096 args[2] = uint->one; /* DONE bit */
3097 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3098 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3099 args[5] = base->undef; /* R */
3100 args[6] = base->undef; /* G */
3101 args[7] = base->undef; /* B */
3102 args[8] = base->undef; /* A */
3103
3104 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3105 ctx->voidt, args, 9, 0);
3106 }
3107
3108 /**
3109 * Return PS outputs in this order:
3110 *
3111 * v[0:3] = color0.xyzw
3112 * v[4:7] = color1.xyzw
3113 * ...
3114 * vN+0 = Depth
3115 * vN+1 = Stencil
3116 * vN+2 = SampleMask
3117 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3118 *
3119 * The alpha-ref SGPR is returned via its original location.
3120 */
3121 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3122 {
3123 struct si_shader_context *ctx = si_shader_context(bld_base);
3124 struct si_shader *shader = ctx->shader;
3125 struct lp_build_context *base = &bld_base->base;
3126 struct tgsi_shader_info *info = &shader->selector->info;
3127 LLVMBuilderRef builder = base->gallivm->builder;
3128 unsigned i, j, first_vgpr, vgpr;
3129
3130 LLVMValueRef color[8][4] = {};
3131 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3132 LLVMValueRef ret;
3133
3134 /* Read the output values. */
3135 for (i = 0; i < info->num_outputs; i++) {
3136 unsigned semantic_name = info->output_semantic_name[i];
3137 unsigned semantic_index = info->output_semantic_index[i];
3138
3139 switch (semantic_name) {
3140 case TGSI_SEMANTIC_COLOR:
3141 assert(semantic_index < 8);
3142 for (j = 0; j < 4; j++) {
3143 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3144 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3145 color[semantic_index][j] = result;
3146 }
3147 break;
3148 case TGSI_SEMANTIC_POSITION:
3149 depth = LLVMBuildLoad(builder,
3150 ctx->soa.outputs[i][2], "");
3151 break;
3152 case TGSI_SEMANTIC_STENCIL:
3153 stencil = LLVMBuildLoad(builder,
3154 ctx->soa.outputs[i][1], "");
3155 break;
3156 case TGSI_SEMANTIC_SAMPLEMASK:
3157 samplemask = LLVMBuildLoad(builder,
3158 ctx->soa.outputs[i][0], "");
3159 break;
3160 default:
3161 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3162 semantic_name);
3163 }
3164 }
3165
3166 /* Fill the return structure. */
3167 ret = ctx->return_value;
3168
3169 /* Set SGPRs. */
3170 ret = LLVMBuildInsertValue(builder, ret,
3171 bitcast(bld_base, TGSI_TYPE_SIGNED,
3172 LLVMGetParam(ctx->main_fn,
3173 SI_PARAM_ALPHA_REF)),
3174 SI_SGPR_ALPHA_REF, "");
3175
3176 /* Set VGPRs */
3177 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3178 for (i = 0; i < ARRAY_SIZE(color); i++) {
3179 if (!color[i][0])
3180 continue;
3181
3182 for (j = 0; j < 4; j++)
3183 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3184 }
3185 if (depth)
3186 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3187 if (stencil)
3188 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3189 if (samplemask)
3190 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3191
3192 /* Add the input sample mask for smoothing at the end. */
3193 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3194 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3195 ret = LLVMBuildInsertValue(builder, ret,
3196 LLVMGetParam(ctx->main_fn,
3197 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3198
3199 ctx->return_value = ret;
3200 }
3201
3202 /**
3203 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3204 * buffer in number of elements and return it as an i32.
3205 */
3206 static LLVMValueRef get_buffer_size(
3207 struct lp_build_tgsi_context *bld_base,
3208 LLVMValueRef descriptor)
3209 {
3210 struct si_shader_context *ctx = si_shader_context(bld_base);
3211 struct gallivm_state *gallivm = bld_base->base.gallivm;
3212 LLVMBuilderRef builder = gallivm->builder;
3213 LLVMValueRef size =
3214 LLVMBuildExtractElement(builder, descriptor,
3215 lp_build_const_int32(gallivm, 2), "");
3216
3217 if (ctx->screen->b.chip_class >= VI) {
3218 /* On VI, the descriptor contains the size in bytes,
3219 * but TXQ must return the size in elements.
3220 * The stride is always non-zero for resources using TXQ.
3221 */
3222 LLVMValueRef stride =
3223 LLVMBuildExtractElement(builder, descriptor,
3224 lp_build_const_int32(gallivm, 1), "");
3225 stride = LLVMBuildLShr(builder, stride,
3226 lp_build_const_int32(gallivm, 16), "");
3227 stride = LLVMBuildAnd(builder, stride,
3228 lp_build_const_int32(gallivm, 0x3FFF), "");
3229
3230 size = LLVMBuildUDiv(builder, size, stride, "");
3231 }
3232
3233 return size;
3234 }
3235
3236 /**
3237 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3238 * intrinsic names).
3239 */
3240 static void build_type_name_for_intr(
3241 LLVMTypeRef type,
3242 char *buf, unsigned bufsize)
3243 {
3244 LLVMTypeRef elem_type = type;
3245
3246 assert(bufsize >= 8);
3247
3248 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3249 int ret = snprintf(buf, bufsize, "v%u",
3250 LLVMGetVectorSize(type));
3251 if (ret < 0) {
3252 char *type_name = LLVMPrintTypeToString(type);
3253 fprintf(stderr, "Error building type name for: %s\n",
3254 type_name);
3255 return;
3256 }
3257 elem_type = LLVMGetElementType(type);
3258 buf += ret;
3259 bufsize -= ret;
3260 }
3261 switch (LLVMGetTypeKind(elem_type)) {
3262 default: break;
3263 case LLVMIntegerTypeKind:
3264 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3265 break;
3266 case LLVMFloatTypeKind:
3267 snprintf(buf, bufsize, "f32");
3268 break;
3269 case LLVMDoubleTypeKind:
3270 snprintf(buf, bufsize, "f64");
3271 break;
3272 }
3273 }
3274
3275 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3276 struct lp_build_tgsi_context *bld_base,
3277 struct lp_build_emit_data *emit_data);
3278
3279 /* Prevent optimizations (at least of memory accesses) across the current
3280 * point in the program by emitting empty inline assembly that is marked as
3281 * having side effects.
3282 */
3283 static void emit_optimization_barrier(struct si_shader_context *ctx)
3284 {
3285 LLVMBuilderRef builder = ctx->gallivm.builder;
3286 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3287 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3288 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3289 }
3290
3291 #define VM_CNT 0xf70
3292
3293 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3294 {
3295 struct gallivm_state *gallivm = &ctx->gallivm;
3296 LLVMBuilderRef builder = gallivm->builder;
3297 LLVMValueRef args[1] = {
3298 lp_build_const_int32(gallivm, simm16)
3299 };
3300 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3301 ctx->voidt, args, 1, 0);
3302 }
3303
3304 static void membar_emit(
3305 const struct lp_build_tgsi_action *action,
3306 struct lp_build_tgsi_context *bld_base,
3307 struct lp_build_emit_data *emit_data)
3308 {
3309 struct si_shader_context *ctx = si_shader_context(bld_base);
3310
3311 emit_waitcnt(ctx, VM_CNT);
3312 }
3313
3314 static LLVMValueRef
3315 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3316 const struct tgsi_full_src_register *reg)
3317 {
3318 LLVMValueRef index;
3319 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3320 SI_PARAM_SHADER_BUFFERS);
3321
3322 if (!reg->Register.Indirect)
3323 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3324 else
3325 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3326 reg->Register.Index,
3327 SI_NUM_SHADER_BUFFERS);
3328
3329 return build_indexed_load_const(ctx, rsrc_ptr, index);
3330 }
3331
3332 static bool tgsi_is_array_sampler(unsigned target)
3333 {
3334 return target == TGSI_TEXTURE_1D_ARRAY ||
3335 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3336 target == TGSI_TEXTURE_2D_ARRAY ||
3337 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3338 target == TGSI_TEXTURE_CUBE_ARRAY ||
3339 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3340 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3341 }
3342
3343 static bool tgsi_is_array_image(unsigned target)
3344 {
3345 return target == TGSI_TEXTURE_3D ||
3346 target == TGSI_TEXTURE_CUBE ||
3347 target == TGSI_TEXTURE_1D_ARRAY ||
3348 target == TGSI_TEXTURE_2D_ARRAY ||
3349 target == TGSI_TEXTURE_CUBE_ARRAY ||
3350 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3351 }
3352
3353 /**
3354 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3355 *
3356 * At least on Tonga, executing image stores on images with DCC enabled and
3357 * non-trivial can eventually lead to lockups. This can occur when an
3358 * application binds an image as read-only but then uses a shader that writes
3359 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3360 * program termination) in this case, but it doesn't cost much to be a bit
3361 * nicer: disabling DCC in the shader still leads to undefined results but
3362 * avoids the lockup.
3363 */
3364 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3365 LLVMValueRef rsrc)
3366 {
3367 if (ctx->screen->b.chip_class <= CIK) {
3368 return rsrc;
3369 } else {
3370 LLVMBuilderRef builder = ctx->gallivm.builder;
3371 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3372 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3373 LLVMValueRef tmp;
3374
3375 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3376 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3377 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3378 }
3379 }
3380
3381 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3382 {
3383 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3384 CONST_ADDR_SPACE);
3385 }
3386
3387 /**
3388 * Load the resource descriptor for \p image.
3389 */
3390 static void
3391 image_fetch_rsrc(
3392 struct lp_build_tgsi_context *bld_base,
3393 const struct tgsi_full_src_register *image,
3394 bool is_store, unsigned target,
3395 LLVMValueRef *rsrc)
3396 {
3397 struct si_shader_context *ctx = si_shader_context(bld_base);
3398 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3399 SI_PARAM_IMAGES);
3400 LLVMValueRef index, tmp;
3401 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3402
3403 assert(image->Register.File == TGSI_FILE_IMAGE);
3404
3405 if (!image->Register.Indirect) {
3406 const struct tgsi_shader_info *info = bld_base->info;
3407
3408 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3409
3410 if (info->images_writemask & (1 << image->Register.Index) &&
3411 target != TGSI_TEXTURE_BUFFER)
3412 dcc_off = true;
3413 } else {
3414 /* From the GL_ARB_shader_image_load_store extension spec:
3415 *
3416 * If a shader performs an image load, store, or atomic
3417 * operation using an image variable declared as an array,
3418 * and if the index used to select an individual element is
3419 * negative or greater than or equal to the size of the
3420 * array, the results of the operation are undefined but may
3421 * not lead to termination.
3422 */
3423 index = get_bounded_indirect_index(ctx, &image->Indirect,
3424 image->Register.Index,
3425 SI_NUM_IMAGES);
3426 }
3427
3428 if (target == TGSI_TEXTURE_BUFFER) {
3429 LLVMBuilderRef builder = ctx->gallivm.builder;
3430
3431 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3432 const_array(ctx->v4i32, 0), "");
3433 index = LLVMBuildMul(builder, index,
3434 LLVMConstInt(ctx->i32, 2, 0), "");
3435 index = LLVMBuildAdd(builder, index,
3436 LLVMConstInt(ctx->i32, 1, 0), "");
3437 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3438 return;
3439 }
3440
3441 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3442 if (dcc_off)
3443 tmp = force_dcc_off(ctx, tmp);
3444 *rsrc = tmp;
3445 }
3446
3447 static LLVMValueRef image_fetch_coords(
3448 struct lp_build_tgsi_context *bld_base,
3449 const struct tgsi_full_instruction *inst,
3450 unsigned src)
3451 {
3452 struct gallivm_state *gallivm = bld_base->base.gallivm;
3453 LLVMBuilderRef builder = gallivm->builder;
3454 unsigned target = inst->Memory.Texture;
3455 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3456 LLVMValueRef coords[4];
3457 LLVMValueRef tmp;
3458 int chan;
3459
3460 for (chan = 0; chan < num_coords; ++chan) {
3461 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3462 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3463 coords[chan] = tmp;
3464 }
3465
3466 if (num_coords == 1)
3467 return coords[0];
3468
3469 if (num_coords == 3) {
3470 /* LLVM has difficulties lowering 3-element vectors. */
3471 coords[3] = bld_base->uint_bld.undef;
3472 num_coords = 4;
3473 }
3474
3475 return lp_build_gather_values(gallivm, coords, num_coords);
3476 }
3477
3478 /**
3479 * Append the extra mode bits that are used by image load and store.
3480 */
3481 static void image_append_args(
3482 struct si_shader_context *ctx,
3483 struct lp_build_emit_data * emit_data,
3484 unsigned target,
3485 bool atomic,
3486 bool force_glc)
3487 {
3488 const struct tgsi_full_instruction *inst = emit_data->inst;
3489 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3490 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3491 LLVMValueRef r128 = i1false;
3492 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3493 LLVMValueRef glc =
3494 force_glc ||
3495 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3496 i1true : i1false;
3497 LLVMValueRef slc = i1false;
3498 LLVMValueRef lwe = i1false;
3499
3500 if (atomic || (HAVE_LLVM <= 0x0309)) {
3501 emit_data->args[emit_data->arg_count++] = r128;
3502 emit_data->args[emit_data->arg_count++] = da;
3503 if (!atomic) {
3504 emit_data->args[emit_data->arg_count++] = glc;
3505 }
3506 emit_data->args[emit_data->arg_count++] = slc;
3507 return;
3508 }
3509
3510 /* HAVE_LLVM >= 0x0400 */
3511 emit_data->args[emit_data->arg_count++] = glc;
3512 emit_data->args[emit_data->arg_count++] = slc;
3513 emit_data->args[emit_data->arg_count++] = lwe;
3514 emit_data->args[emit_data->arg_count++] = da;
3515 }
3516
3517 /**
3518 * Append the resource and indexing arguments for buffer intrinsics.
3519 *
3520 * \param rsrc the v4i32 buffer resource
3521 * \param index index into the buffer (stride-based)
3522 * \param offset byte offset into the buffer
3523 */
3524 static void buffer_append_args(
3525 struct si_shader_context *ctx,
3526 struct lp_build_emit_data *emit_data,
3527 LLVMValueRef rsrc,
3528 LLVMValueRef index,
3529 LLVMValueRef offset,
3530 bool atomic,
3531 bool force_glc)
3532 {
3533 const struct tgsi_full_instruction *inst = emit_data->inst;
3534 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3535 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3536
3537 emit_data->args[emit_data->arg_count++] = rsrc;
3538 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3539 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3540 if (!atomic) {
3541 emit_data->args[emit_data->arg_count++] =
3542 force_glc ||
3543 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3544 i1true : i1false; /* glc */
3545 }
3546 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3547 }
3548
3549 static void load_fetch_args(
3550 struct lp_build_tgsi_context * bld_base,
3551 struct lp_build_emit_data * emit_data)
3552 {
3553 struct si_shader_context *ctx = si_shader_context(bld_base);
3554 struct gallivm_state *gallivm = bld_base->base.gallivm;
3555 const struct tgsi_full_instruction * inst = emit_data->inst;
3556 unsigned target = inst->Memory.Texture;
3557 LLVMValueRef rsrc;
3558
3559 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3560
3561 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3562 LLVMBuilderRef builder = gallivm->builder;
3563 LLVMValueRef offset;
3564 LLVMValueRef tmp;
3565
3566 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3567
3568 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3569 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3570
3571 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3572 offset, false, false);
3573 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3574 LLVMValueRef coords;
3575
3576 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3577 coords = image_fetch_coords(bld_base, inst, 1);
3578
3579 if (target == TGSI_TEXTURE_BUFFER) {
3580 buffer_append_args(ctx, emit_data, rsrc, coords,
3581 bld_base->uint_bld.zero, false, false);
3582 } else {
3583 emit_data->args[0] = coords;
3584 emit_data->args[1] = rsrc;
3585 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3586 emit_data->arg_count = 3;
3587
3588 image_append_args(ctx, emit_data, target, false, false);
3589 }
3590 }
3591 }
3592
3593 static void load_emit_buffer(struct si_shader_context *ctx,
3594 struct lp_build_emit_data *emit_data)
3595 {
3596 const struct tgsi_full_instruction *inst = emit_data->inst;
3597 struct gallivm_state *gallivm = &ctx->gallivm;
3598 LLVMBuilderRef builder = gallivm->builder;
3599 uint writemask = inst->Dst[0].Register.WriteMask;
3600 uint count = util_last_bit(writemask);
3601 const char *intrinsic_name;
3602 LLVMTypeRef dst_type;
3603
3604 switch (count) {
3605 case 1:
3606 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3607 dst_type = ctx->f32;
3608 break;
3609 case 2:
3610 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3611 dst_type = LLVMVectorType(ctx->f32, 2);
3612 break;
3613 default: // 3 & 4
3614 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3615 dst_type = ctx->v4f32;
3616 count = 4;
3617 }
3618
3619 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3620 builder, intrinsic_name, dst_type,
3621 emit_data->args, emit_data->arg_count,
3622 LP_FUNC_ATTR_READONLY);
3623 }
3624
3625 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3626 const struct tgsi_full_instruction *inst,
3627 LLVMTypeRef type, int arg)
3628 {
3629 struct gallivm_state *gallivm = &ctx->gallivm;
3630 LLVMBuilderRef builder = gallivm->builder;
3631 LLVMValueRef offset, ptr;
3632 int addr_space;
3633
3634 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3635 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3636
3637 ptr = ctx->shared_memory;
3638 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3639 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3640 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3641
3642 return ptr;
3643 }
3644
3645 static void load_emit_memory(
3646 struct si_shader_context *ctx,
3647 struct lp_build_emit_data *emit_data)
3648 {
3649 const struct tgsi_full_instruction *inst = emit_data->inst;
3650 struct lp_build_context *base = &ctx->soa.bld_base.base;
3651 struct gallivm_state *gallivm = &ctx->gallivm;
3652 LLVMBuilderRef builder = gallivm->builder;
3653 unsigned writemask = inst->Dst[0].Register.WriteMask;
3654 LLVMValueRef channels[4], ptr, derived_ptr, index;
3655 int chan;
3656
3657 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3658
3659 for (chan = 0; chan < 4; ++chan) {
3660 if (!(writemask & (1 << chan))) {
3661 channels[chan] = LLVMGetUndef(base->elem_type);
3662 continue;
3663 }
3664
3665 index = lp_build_const_int32(gallivm, chan);
3666 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3667 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3668 }
3669 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3670 }
3671
3672 static void get_image_intr_name(const char *base_name,
3673 LLVMTypeRef data_type,
3674 LLVMTypeRef coords_type,
3675 LLVMTypeRef rsrc_type,
3676 char *out_name, unsigned out_len)
3677 {
3678 char coords_type_name[8];
3679
3680 build_type_name_for_intr(coords_type, coords_type_name,
3681 sizeof(coords_type_name));
3682
3683 if (HAVE_LLVM <= 0x0309) {
3684 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3685 } else {
3686 char data_type_name[8];
3687 char rsrc_type_name[8];
3688
3689 build_type_name_for_intr(data_type, data_type_name,
3690 sizeof(data_type_name));
3691 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3692 sizeof(rsrc_type_name));
3693 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3694 data_type_name, coords_type_name, rsrc_type_name);
3695 }
3696 }
3697
3698 static void load_emit(
3699 const struct lp_build_tgsi_action *action,
3700 struct lp_build_tgsi_context *bld_base,
3701 struct lp_build_emit_data *emit_data)
3702 {
3703 struct si_shader_context *ctx = si_shader_context(bld_base);
3704 struct gallivm_state *gallivm = bld_base->base.gallivm;
3705 LLVMBuilderRef builder = gallivm->builder;
3706 const struct tgsi_full_instruction * inst = emit_data->inst;
3707 char intrinsic_name[64];
3708
3709 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3710 load_emit_memory(ctx, emit_data);
3711 return;
3712 }
3713
3714 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3715 emit_waitcnt(ctx, VM_CNT);
3716
3717 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3718 load_emit_buffer(ctx, emit_data);
3719 return;
3720 }
3721
3722 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3723 emit_data->output[emit_data->chan] =
3724 lp_build_intrinsic(
3725 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3726 emit_data->args, emit_data->arg_count,
3727 LP_FUNC_ATTR_READONLY);
3728 } else {
3729 get_image_intr_name("llvm.amdgcn.image.load",
3730 emit_data->dst_type, /* vdata */
3731 LLVMTypeOf(emit_data->args[0]), /* coords */
3732 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3733 intrinsic_name, sizeof(intrinsic_name));
3734
3735 emit_data->output[emit_data->chan] =
3736 lp_build_intrinsic(
3737 builder, intrinsic_name, emit_data->dst_type,
3738 emit_data->args, emit_data->arg_count,
3739 LP_FUNC_ATTR_READONLY);
3740 }
3741 }
3742
3743 static void store_fetch_args(
3744 struct lp_build_tgsi_context * bld_base,
3745 struct lp_build_emit_data * emit_data)
3746 {
3747 struct si_shader_context *ctx = si_shader_context(bld_base);
3748 struct gallivm_state *gallivm = bld_base->base.gallivm;
3749 LLVMBuilderRef builder = gallivm->builder;
3750 const struct tgsi_full_instruction * inst = emit_data->inst;
3751 struct tgsi_full_src_register memory;
3752 LLVMValueRef chans[4];
3753 LLVMValueRef data;
3754 LLVMValueRef rsrc;
3755 unsigned chan;
3756
3757 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3758
3759 for (chan = 0; chan < 4; ++chan) {
3760 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3761 }
3762 data = lp_build_gather_values(gallivm, chans, 4);
3763
3764 emit_data->args[emit_data->arg_count++] = data;
3765
3766 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3767
3768 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3769 LLVMValueRef offset;
3770 LLVMValueRef tmp;
3771
3772 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3773
3774 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3775 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3776
3777 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3778 offset, false, false);
3779 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3780 unsigned target = inst->Memory.Texture;
3781 LLVMValueRef coords;
3782
3783 /* 8bit/16bit TC L1 write corruption bug on SI.
3784 * All store opcodes not aligned to a dword are affected.
3785 *
3786 * The only way to get unaligned stores in radeonsi is through
3787 * shader images.
3788 */
3789 bool force_glc = ctx->screen->b.chip_class == SI;
3790
3791 coords = image_fetch_coords(bld_base, inst, 0);
3792
3793 if (target == TGSI_TEXTURE_BUFFER) {
3794 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3795 buffer_append_args(ctx, emit_data, rsrc, coords,
3796 bld_base->uint_bld.zero, false, force_glc);
3797 } else {
3798 emit_data->args[1] = coords;
3799 image_fetch_rsrc(bld_base, &memory, true, target,
3800 &emit_data->args[2]);
3801 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3802 emit_data->arg_count = 4;
3803
3804 image_append_args(ctx, emit_data, target, false, force_glc);
3805 }
3806 }
3807 }
3808
3809 static void store_emit_buffer(
3810 struct si_shader_context *ctx,
3811 struct lp_build_emit_data *emit_data)
3812 {
3813 const struct tgsi_full_instruction *inst = emit_data->inst;
3814 struct gallivm_state *gallivm = &ctx->gallivm;
3815 LLVMBuilderRef builder = gallivm->builder;
3816 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3817 LLVMValueRef base_data = emit_data->args[0];
3818 LLVMValueRef base_offset = emit_data->args[3];
3819 unsigned writemask = inst->Dst[0].Register.WriteMask;
3820
3821 while (writemask) {
3822 int start, count;
3823 const char *intrinsic_name;
3824 LLVMValueRef data;
3825 LLVMValueRef offset;
3826 LLVMValueRef tmp;
3827
3828 u_bit_scan_consecutive_range(&writemask, &start, &count);
3829
3830 /* Due to an LLVM limitation, split 3-element writes
3831 * into a 2-element and a 1-element write. */
3832 if (count == 3) {
3833 writemask |= 1 << (start + 2);
3834 count = 2;
3835 }
3836
3837 if (count == 4) {
3838 data = base_data;
3839 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3840 } else if (count == 2) {
3841 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3842
3843 tmp = LLVMBuildExtractElement(
3844 builder, base_data,
3845 lp_build_const_int32(gallivm, start), "");
3846 data = LLVMBuildInsertElement(
3847 builder, LLVMGetUndef(v2f32), tmp,
3848 uint_bld->zero, "");
3849
3850 tmp = LLVMBuildExtractElement(
3851 builder, base_data,
3852 lp_build_const_int32(gallivm, start + 1), "");
3853 data = LLVMBuildInsertElement(
3854 builder, data, tmp, uint_bld->one, "");
3855
3856 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3857 } else {
3858 assert(count == 1);
3859 data = LLVMBuildExtractElement(
3860 builder, base_data,
3861 lp_build_const_int32(gallivm, start), "");
3862 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3863 }
3864
3865 offset = base_offset;
3866 if (start != 0) {
3867 offset = LLVMBuildAdd(
3868 builder, offset,
3869 lp_build_const_int32(gallivm, start * 4), "");
3870 }
3871
3872 emit_data->args[0] = data;
3873 emit_data->args[3] = offset;
3874
3875 lp_build_intrinsic(
3876 builder, intrinsic_name, emit_data->dst_type,
3877 emit_data->args, emit_data->arg_count, 0);
3878 }
3879 }
3880
3881 static void store_emit_memory(
3882 struct si_shader_context *ctx,
3883 struct lp_build_emit_data *emit_data)
3884 {
3885 const struct tgsi_full_instruction *inst = emit_data->inst;
3886 struct gallivm_state *gallivm = &ctx->gallivm;
3887 struct lp_build_context *base = &ctx->soa.bld_base.base;
3888 LLVMBuilderRef builder = gallivm->builder;
3889 unsigned writemask = inst->Dst[0].Register.WriteMask;
3890 LLVMValueRef ptr, derived_ptr, data, index;
3891 int chan;
3892
3893 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3894
3895 for (chan = 0; chan < 4; ++chan) {
3896 if (!(writemask & (1 << chan))) {
3897 continue;
3898 }
3899 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3900 index = lp_build_const_int32(gallivm, chan);
3901 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3902 LLVMBuildStore(builder, data, derived_ptr);
3903 }
3904 }
3905
3906 static void store_emit(
3907 const struct lp_build_tgsi_action *action,
3908 struct lp_build_tgsi_context *bld_base,
3909 struct lp_build_emit_data *emit_data)
3910 {
3911 struct si_shader_context *ctx = si_shader_context(bld_base);
3912 struct gallivm_state *gallivm = bld_base->base.gallivm;
3913 LLVMBuilderRef builder = gallivm->builder;
3914 const struct tgsi_full_instruction * inst = emit_data->inst;
3915 unsigned target = inst->Memory.Texture;
3916 char intrinsic_name[64];
3917
3918 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3919 store_emit_memory(ctx, emit_data);
3920 return;
3921 }
3922
3923 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3924 emit_waitcnt(ctx, VM_CNT);
3925
3926 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3927 store_emit_buffer(ctx, emit_data);
3928 return;
3929 }
3930
3931 if (target == TGSI_TEXTURE_BUFFER) {
3932 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3933 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3934 emit_data->dst_type, emit_data->args,
3935 emit_data->arg_count, 0);
3936 } else {
3937 get_image_intr_name("llvm.amdgcn.image.store",
3938 LLVMTypeOf(emit_data->args[0]), /* vdata */
3939 LLVMTypeOf(emit_data->args[1]), /* coords */
3940 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3941 intrinsic_name, sizeof(intrinsic_name));
3942
3943 emit_data->output[emit_data->chan] =
3944 lp_build_intrinsic(
3945 builder, intrinsic_name, emit_data->dst_type,
3946 emit_data->args, emit_data->arg_count, 0);
3947 }
3948 }
3949
3950 static void atomic_fetch_args(
3951 struct lp_build_tgsi_context * bld_base,
3952 struct lp_build_emit_data * emit_data)
3953 {
3954 struct si_shader_context *ctx = si_shader_context(bld_base);
3955 struct gallivm_state *gallivm = bld_base->base.gallivm;
3956 LLVMBuilderRef builder = gallivm->builder;
3957 const struct tgsi_full_instruction * inst = emit_data->inst;
3958 LLVMValueRef data1, data2;
3959 LLVMValueRef rsrc;
3960 LLVMValueRef tmp;
3961
3962 emit_data->dst_type = bld_base->base.elem_type;
3963
3964 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3965 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3966
3967 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3968 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3969 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3970 }
3971
3972 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3973 * of arguments, which is reversed relative to TGSI (and GLSL)
3974 */
3975 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3976 emit_data->args[emit_data->arg_count++] = data2;
3977 emit_data->args[emit_data->arg_count++] = data1;
3978
3979 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3980 LLVMValueRef offset;
3981
3982 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3983
3984 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3985 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3986
3987 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3988 offset, true, false);
3989 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3990 unsigned target = inst->Memory.Texture;
3991 LLVMValueRef coords;
3992
3993 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3994 coords = image_fetch_coords(bld_base, inst, 1);
3995
3996 if (target == TGSI_TEXTURE_BUFFER) {
3997 buffer_append_args(ctx, emit_data, rsrc, coords,
3998 bld_base->uint_bld.zero, true, false);
3999 } else {
4000 emit_data->args[emit_data->arg_count++] = coords;
4001 emit_data->args[emit_data->arg_count++] = rsrc;
4002
4003 image_append_args(ctx, emit_data, target, true, false);
4004 }
4005 }
4006 }
4007
4008 static void atomic_emit_memory(struct si_shader_context *ctx,
4009 struct lp_build_emit_data *emit_data) {
4010 struct gallivm_state *gallivm = &ctx->gallivm;
4011 LLVMBuilderRef builder = gallivm->builder;
4012 const struct tgsi_full_instruction * inst = emit_data->inst;
4013 LLVMValueRef ptr, result, arg;
4014
4015 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4016
4017 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
4018 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4019
4020 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4021 LLVMValueRef new_data;
4022 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
4023 inst, 3, 0);
4024
4025 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4026
4027 #if HAVE_LLVM >= 0x309
4028 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4029 LLVMAtomicOrderingSequentiallyConsistent,
4030 LLVMAtomicOrderingSequentiallyConsistent,
4031 false);
4032 #endif
4033
4034 result = LLVMBuildExtractValue(builder, result, 0, "");
4035 } else {
4036 LLVMAtomicRMWBinOp op;
4037
4038 switch(inst->Instruction.Opcode) {
4039 case TGSI_OPCODE_ATOMUADD:
4040 op = LLVMAtomicRMWBinOpAdd;
4041 break;
4042 case TGSI_OPCODE_ATOMXCHG:
4043 op = LLVMAtomicRMWBinOpXchg;
4044 break;
4045 case TGSI_OPCODE_ATOMAND:
4046 op = LLVMAtomicRMWBinOpAnd;
4047 break;
4048 case TGSI_OPCODE_ATOMOR:
4049 op = LLVMAtomicRMWBinOpOr;
4050 break;
4051 case TGSI_OPCODE_ATOMXOR:
4052 op = LLVMAtomicRMWBinOpXor;
4053 break;
4054 case TGSI_OPCODE_ATOMUMIN:
4055 op = LLVMAtomicRMWBinOpUMin;
4056 break;
4057 case TGSI_OPCODE_ATOMUMAX:
4058 op = LLVMAtomicRMWBinOpUMax;
4059 break;
4060 case TGSI_OPCODE_ATOMIMIN:
4061 op = LLVMAtomicRMWBinOpMin;
4062 break;
4063 case TGSI_OPCODE_ATOMIMAX:
4064 op = LLVMAtomicRMWBinOpMax;
4065 break;
4066 default:
4067 unreachable("unknown atomic opcode");
4068 }
4069
4070 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4071 LLVMAtomicOrderingSequentiallyConsistent,
4072 false);
4073 }
4074 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4075 }
4076
4077 static void atomic_emit(
4078 const struct lp_build_tgsi_action *action,
4079 struct lp_build_tgsi_context *bld_base,
4080 struct lp_build_emit_data *emit_data)
4081 {
4082 struct si_shader_context *ctx = si_shader_context(bld_base);
4083 struct gallivm_state *gallivm = bld_base->base.gallivm;
4084 LLVMBuilderRef builder = gallivm->builder;
4085 const struct tgsi_full_instruction * inst = emit_data->inst;
4086 char intrinsic_name[40];
4087 LLVMValueRef tmp;
4088
4089 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4090 atomic_emit_memory(ctx, emit_data);
4091 return;
4092 }
4093
4094 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4095 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4096 snprintf(intrinsic_name, sizeof(intrinsic_name),
4097 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4098 } else {
4099 LLVMValueRef coords;
4100 char coords_type[8];
4101
4102 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4103 coords = emit_data->args[2];
4104 else
4105 coords = emit_data->args[1];
4106
4107 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4108 snprintf(intrinsic_name, sizeof(intrinsic_name),
4109 "llvm.amdgcn.image.atomic.%s.%s",
4110 action->intr_name, coords_type);
4111 }
4112
4113 tmp = lp_build_intrinsic(
4114 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4115 emit_data->args, emit_data->arg_count, 0);
4116 emit_data->output[emit_data->chan] =
4117 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4118 }
4119
4120 static void resq_fetch_args(
4121 struct lp_build_tgsi_context * bld_base,
4122 struct lp_build_emit_data * emit_data)
4123 {
4124 struct si_shader_context *ctx = si_shader_context(bld_base);
4125 struct gallivm_state *gallivm = bld_base->base.gallivm;
4126 const struct tgsi_full_instruction *inst = emit_data->inst;
4127 const struct tgsi_full_src_register *reg = &inst->Src[0];
4128
4129 emit_data->dst_type = ctx->v4i32;
4130
4131 if (reg->Register.File == TGSI_FILE_BUFFER) {
4132 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4133 emit_data->arg_count = 1;
4134 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4135 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4136 &emit_data->args[0]);
4137 emit_data->arg_count = 1;
4138 } else {
4139 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4140 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4141 &emit_data->args[1]);
4142 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4143 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4144 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4145 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4146 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4147 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4148 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4149 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4150 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4151 emit_data->arg_count = 10;
4152 }
4153 }
4154
4155 static void resq_emit(
4156 const struct lp_build_tgsi_action *action,
4157 struct lp_build_tgsi_context *bld_base,
4158 struct lp_build_emit_data *emit_data)
4159 {
4160 struct gallivm_state *gallivm = bld_base->base.gallivm;
4161 LLVMBuilderRef builder = gallivm->builder;
4162 const struct tgsi_full_instruction *inst = emit_data->inst;
4163 LLVMValueRef out;
4164
4165 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4166 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4167 lp_build_const_int32(gallivm, 2), "");
4168 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4169 out = get_buffer_size(bld_base, emit_data->args[0]);
4170 } else {
4171 out = lp_build_intrinsic(
4172 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4173 emit_data->args, emit_data->arg_count,
4174 LP_FUNC_ATTR_READNONE);
4175
4176 /* Divide the number of layers by 6 to get the number of cubes. */
4177 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4178 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4179 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4180
4181 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4182 z = LLVMBuildSDiv(builder, z, imm6, "");
4183 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4184 }
4185 }
4186
4187 emit_data->output[emit_data->chan] = out;
4188 }
4189
4190 static void set_tex_fetch_args(struct si_shader_context *ctx,
4191 struct lp_build_emit_data *emit_data,
4192 unsigned opcode, unsigned target,
4193 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4194 LLVMValueRef *param, unsigned count,
4195 unsigned dmask)
4196 {
4197 struct gallivm_state *gallivm = &ctx->gallivm;
4198 unsigned num_args;
4199 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4200
4201 /* Pad to power of two vector */
4202 while (count < util_next_power_of_two(count))
4203 param[count++] = LLVMGetUndef(ctx->i32);
4204
4205 /* Texture coordinates. */
4206 if (count > 1)
4207 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4208 else
4209 emit_data->args[0] = param[0];
4210
4211 /* Resource. */
4212 emit_data->args[1] = res_ptr;
4213 num_args = 2;
4214
4215 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4216 emit_data->dst_type = ctx->v4i32;
4217 else {
4218 emit_data->dst_type = ctx->v4f32;
4219
4220 emit_data->args[num_args++] = samp_ptr;
4221 }
4222
4223 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4224 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4225 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4226 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4227 tgsi_is_array_sampler(target)); /* da */
4228 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4229 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4230 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4231 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4232
4233 emit_data->arg_count = num_args;
4234 }
4235
4236 static const struct lp_build_tgsi_action tex_action;
4237
4238 enum desc_type {
4239 DESC_IMAGE,
4240 DESC_BUFFER,
4241 DESC_FMASK,
4242 DESC_SAMPLER,
4243 };
4244
4245 /**
4246 * Load an image view, fmask view. or sampler state descriptor.
4247 */
4248 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4249 LLVMValueRef list, LLVMValueRef index,
4250 enum desc_type type)
4251 {
4252 struct gallivm_state *gallivm = &ctx->gallivm;
4253 LLVMBuilderRef builder = gallivm->builder;
4254
4255 switch (type) {
4256 case DESC_IMAGE:
4257 /* The image is at [0:7]. */
4258 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4259 break;
4260 case DESC_BUFFER:
4261 /* The buffer is in [4:7]. */
4262 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4263 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4264 list = LLVMBuildPointerCast(builder, list,
4265 const_array(ctx->v4i32, 0), "");
4266 break;
4267 case DESC_FMASK:
4268 /* The FMASK is at [8:15]. */
4269 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4270 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4271 break;
4272 case DESC_SAMPLER:
4273 /* The sampler state is at [12:15]. */
4274 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4275 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4276 list = LLVMBuildPointerCast(builder, list,
4277 const_array(ctx->v4i32, 0), "");
4278 break;
4279 }
4280
4281 return build_indexed_load_const(ctx, list, index);
4282 }
4283
4284 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4285 LLVMValueRef index, enum desc_type type)
4286 {
4287 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4288 SI_PARAM_SAMPLERS);
4289
4290 return load_sampler_desc_custom(ctx, list, index, type);
4291 }
4292
4293 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4294 *
4295 * SI-CI:
4296 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4297 * filtering manually. The driver sets img7 to a mask clearing
4298 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4299 * s_and_b32 samp0, samp0, img7
4300 *
4301 * VI:
4302 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4303 */
4304 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4305 LLVMValueRef res, LLVMValueRef samp)
4306 {
4307 LLVMBuilderRef builder = ctx->gallivm.builder;
4308 LLVMValueRef img7, samp0;
4309
4310 if (ctx->screen->b.chip_class >= VI)
4311 return samp;
4312
4313 img7 = LLVMBuildExtractElement(builder, res,
4314 LLVMConstInt(ctx->i32, 7, 0), "");
4315 samp0 = LLVMBuildExtractElement(builder, samp,
4316 LLVMConstInt(ctx->i32, 0, 0), "");
4317 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4318 return LLVMBuildInsertElement(builder, samp, samp0,
4319 LLVMConstInt(ctx->i32, 0, 0), "");
4320 }
4321
4322 static void tex_fetch_ptrs(
4323 struct lp_build_tgsi_context *bld_base,
4324 struct lp_build_emit_data *emit_data,
4325 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4326 {
4327 struct si_shader_context *ctx = si_shader_context(bld_base);
4328 const struct tgsi_full_instruction *inst = emit_data->inst;
4329 unsigned target = inst->Texture.Texture;
4330 unsigned sampler_src;
4331 unsigned sampler_index;
4332 LLVMValueRef index;
4333
4334 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4335 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4336
4337 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4338 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4339
4340 index = get_bounded_indirect_index(ctx,
4341 &reg->Indirect,
4342 reg->Register.Index,
4343 SI_NUM_SAMPLERS);
4344 } else {
4345 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4346 }
4347
4348 if (target == TGSI_TEXTURE_BUFFER)
4349 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4350 else
4351 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4352
4353 if (samp_ptr)
4354 *samp_ptr = NULL;
4355 if (fmask_ptr)
4356 *fmask_ptr = NULL;
4357
4358 if (target == TGSI_TEXTURE_2D_MSAA ||
4359 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4360 if (fmask_ptr)
4361 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4362 } else if (target != TGSI_TEXTURE_BUFFER) {
4363 if (samp_ptr) {
4364 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4365 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4366 }
4367 }
4368 }
4369
4370 static void txq_fetch_args(
4371 struct lp_build_tgsi_context *bld_base,
4372 struct lp_build_emit_data *emit_data)
4373 {
4374 struct si_shader_context *ctx = si_shader_context(bld_base);
4375 const struct tgsi_full_instruction *inst = emit_data->inst;
4376 unsigned target = inst->Texture.Texture;
4377 LLVMValueRef res_ptr;
4378 LLVMValueRef address;
4379
4380 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4381
4382 if (target == TGSI_TEXTURE_BUFFER) {
4383 /* Read the size from the buffer descriptor directly. */
4384 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4385 return;
4386 }
4387
4388 /* Textures - set the mip level. */
4389 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4390
4391 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4392 NULL, &address, 1, 0xf);
4393 }
4394
4395 static void txq_emit(const struct lp_build_tgsi_action *action,
4396 struct lp_build_tgsi_context *bld_base,
4397 struct lp_build_emit_data *emit_data)
4398 {
4399 struct lp_build_context *base = &bld_base->base;
4400 unsigned target = emit_data->inst->Texture.Texture;
4401
4402 if (target == TGSI_TEXTURE_BUFFER) {
4403 /* Just return the buffer size. */
4404 emit_data->output[emit_data->chan] = emit_data->args[0];
4405 return;
4406 }
4407
4408 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4409 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4410 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4411 LP_FUNC_ATTR_READNONE);
4412
4413 /* Divide the number of layers by 6 to get the number of cubes. */
4414 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4415 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4416 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4417 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4418 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4419
4420 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4421 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4422 z = LLVMBuildSDiv(builder, z, six, "");
4423
4424 emit_data->output[emit_data->chan] =
4425 LLVMBuildInsertElement(builder, v4, z, two, "");
4426 }
4427 }
4428
4429 static void tex_fetch_args(
4430 struct lp_build_tgsi_context *bld_base,
4431 struct lp_build_emit_data *emit_data)
4432 {
4433 struct si_shader_context *ctx = si_shader_context(bld_base);
4434 struct gallivm_state *gallivm = bld_base->base.gallivm;
4435 const struct tgsi_full_instruction *inst = emit_data->inst;
4436 unsigned opcode = inst->Instruction.Opcode;
4437 unsigned target = inst->Texture.Texture;
4438 LLVMValueRef coords[5], derivs[6];
4439 LLVMValueRef address[16];
4440 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4441 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4442 unsigned count = 0;
4443 unsigned chan;
4444 unsigned num_deriv_channels = 0;
4445 bool has_offset = inst->Texture.NumOffsets > 0;
4446 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4447 unsigned dmask = 0xf;
4448
4449 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4450
4451 if (target == TGSI_TEXTURE_BUFFER) {
4452 emit_data->dst_type = ctx->v4f32;
4453 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4454 ctx->v16i8, "");
4455 emit_data->args[1] = bld_base->uint_bld.zero;
4456 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4457 emit_data->arg_count = 3;
4458 return;
4459 }
4460
4461 /* Fetch and project texture coordinates */
4462 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4463 for (chan = 0; chan < 3; chan++ ) {
4464 coords[chan] = lp_build_emit_fetch(bld_base,
4465 emit_data->inst, 0,
4466 chan);
4467 if (opcode == TGSI_OPCODE_TXP)
4468 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4469 TGSI_OPCODE_DIV,
4470 coords[chan],
4471 coords[3]);
4472 }
4473
4474 if (opcode == TGSI_OPCODE_TXP)
4475 coords[3] = bld_base->base.one;
4476
4477 /* Pack offsets. */
4478 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4479 /* The offsets are six-bit signed integers packed like this:
4480 * X=[5:0], Y=[13:8], and Z=[21:16].
4481 */
4482 LLVMValueRef offset[3], pack;
4483
4484 assert(inst->Texture.NumOffsets == 1);
4485
4486 for (chan = 0; chan < 3; chan++) {
4487 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4488 emit_data->inst, 0, chan);
4489 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4490 lp_build_const_int32(gallivm, 0x3f), "");
4491 if (chan)
4492 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4493 lp_build_const_int32(gallivm, chan*8), "");
4494 }
4495
4496 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4497 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4498 address[count++] = pack;
4499 }
4500
4501 /* Pack LOD bias value */
4502 if (opcode == TGSI_OPCODE_TXB)
4503 address[count++] = coords[3];
4504 if (opcode == TGSI_OPCODE_TXB2)
4505 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4506
4507 /* Pack depth comparison value */
4508 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4509 LLVMValueRef z;
4510
4511 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4512 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4513 } else {
4514 assert(ref_pos >= 0);
4515 z = coords[ref_pos];
4516 }
4517
4518 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4519 * so the depth comparison value isn't clamped for Z16 and
4520 * Z24 anymore. Do it manually here.
4521 *
4522 * It's unnecessary if the original texture format was
4523 * Z32_FLOAT, but we don't know that here.
4524 */
4525 if (ctx->screen->b.chip_class == VI)
4526 z = si_llvm_saturate(bld_base, z);
4527
4528 address[count++] = z;
4529 }
4530
4531 /* Pack user derivatives */
4532 if (opcode == TGSI_OPCODE_TXD) {
4533 int param, num_src_deriv_channels;
4534
4535 switch (target) {
4536 case TGSI_TEXTURE_3D:
4537 num_src_deriv_channels = 3;
4538 num_deriv_channels = 3;
4539 break;
4540 case TGSI_TEXTURE_2D:
4541 case TGSI_TEXTURE_SHADOW2D:
4542 case TGSI_TEXTURE_RECT:
4543 case TGSI_TEXTURE_SHADOWRECT:
4544 case TGSI_TEXTURE_2D_ARRAY:
4545 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4546 num_src_deriv_channels = 2;
4547 num_deriv_channels = 2;
4548 break;
4549 case TGSI_TEXTURE_CUBE:
4550 case TGSI_TEXTURE_SHADOWCUBE:
4551 case TGSI_TEXTURE_CUBE_ARRAY:
4552 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4553 /* Cube derivatives will be converted to 2D. */
4554 num_src_deriv_channels = 3;
4555 num_deriv_channels = 2;
4556 break;
4557 case TGSI_TEXTURE_1D:
4558 case TGSI_TEXTURE_SHADOW1D:
4559 case TGSI_TEXTURE_1D_ARRAY:
4560 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4561 num_src_deriv_channels = 1;
4562 num_deriv_channels = 1;
4563 break;
4564 default:
4565 unreachable("invalid target");
4566 }
4567
4568 for (param = 0; param < 2; param++)
4569 for (chan = 0; chan < num_src_deriv_channels; chan++)
4570 derivs[param * num_src_deriv_channels + chan] =
4571 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4572 }
4573
4574 if (target == TGSI_TEXTURE_CUBE ||
4575 target == TGSI_TEXTURE_CUBE_ARRAY ||
4576 target == TGSI_TEXTURE_SHADOWCUBE ||
4577 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4578 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4579
4580 if (opcode == TGSI_OPCODE_TXD)
4581 for (int i = 0; i < num_deriv_channels * 2; i++)
4582 address[count++] = derivs[i];
4583
4584 /* Pack texture coordinates */
4585 address[count++] = coords[0];
4586 if (num_coords > 1)
4587 address[count++] = coords[1];
4588 if (num_coords > 2)
4589 address[count++] = coords[2];
4590
4591 /* Pack LOD or sample index */
4592 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4593 address[count++] = coords[3];
4594 else if (opcode == TGSI_OPCODE_TXL2)
4595 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4596
4597 if (count > 16) {
4598 assert(!"Cannot handle more than 16 texture address parameters");
4599 count = 16;
4600 }
4601
4602 for (chan = 0; chan < count; chan++ ) {
4603 address[chan] = LLVMBuildBitCast(gallivm->builder,
4604 address[chan], ctx->i32, "");
4605 }
4606
4607 /* Adjust the sample index according to FMASK.
4608 *
4609 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4610 * which is the identity mapping. Each nibble says which physical sample
4611 * should be fetched to get that sample.
4612 *
4613 * For example, 0x11111100 means there are only 2 samples stored and
4614 * the second sample covers 3/4 of the pixel. When reading samples 0
4615 * and 1, return physical sample 0 (determined by the first two 0s
4616 * in FMASK), otherwise return physical sample 1.
4617 *
4618 * The sample index should be adjusted as follows:
4619 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4620 */
4621 if (target == TGSI_TEXTURE_2D_MSAA ||
4622 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4623 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4624 struct lp_build_emit_data txf_emit_data = *emit_data;
4625 LLVMValueRef txf_address[4];
4626 unsigned txf_count = count;
4627 struct tgsi_full_instruction inst = {};
4628
4629 memcpy(txf_address, address, sizeof(txf_address));
4630
4631 if (target == TGSI_TEXTURE_2D_MSAA) {
4632 txf_address[2] = bld_base->uint_bld.zero;
4633 }
4634 txf_address[3] = bld_base->uint_bld.zero;
4635
4636 /* Read FMASK using TXF. */
4637 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4638 inst.Texture.Texture = target;
4639 txf_emit_data.inst = &inst;
4640 txf_emit_data.chan = 0;
4641 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4642 target, fmask_ptr, NULL,
4643 txf_address, txf_count, 0xf);
4644 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4645
4646 /* Initialize some constants. */
4647 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4648 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4649
4650 /* Apply the formula. */
4651 LLVMValueRef fmask =
4652 LLVMBuildExtractElement(gallivm->builder,
4653 txf_emit_data.output[0],
4654 uint_bld->zero, "");
4655
4656 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4657
4658 LLVMValueRef sample_index4 =
4659 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4660
4661 LLVMValueRef shifted_fmask =
4662 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4663
4664 LLVMValueRef final_sample =
4665 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4666
4667 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4668 * resource descriptor is 0 (invalid),
4669 */
4670 LLVMValueRef fmask_desc =
4671 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4672 ctx->v8i32, "");
4673
4674 LLVMValueRef fmask_word1 =
4675 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4676 uint_bld->one, "");
4677
4678 LLVMValueRef word1_is_nonzero =
4679 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4680 fmask_word1, uint_bld->zero, "");
4681
4682 /* Replace the MSAA sample index. */
4683 address[sample_chan] =
4684 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4685 final_sample, address[sample_chan], "");
4686 }
4687
4688 if (opcode == TGSI_OPCODE_TXF) {
4689 /* add tex offsets */
4690 if (inst->Texture.NumOffsets) {
4691 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4692 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4693 const struct tgsi_texture_offset *off = inst->TexOffsets;
4694
4695 assert(inst->Texture.NumOffsets == 1);
4696
4697 switch (target) {
4698 case TGSI_TEXTURE_3D:
4699 address[2] = lp_build_add(uint_bld, address[2],
4700 bld->immediates[off->Index][off->SwizzleZ]);
4701 /* fall through */
4702 case TGSI_TEXTURE_2D:
4703 case TGSI_TEXTURE_SHADOW2D:
4704 case TGSI_TEXTURE_RECT:
4705 case TGSI_TEXTURE_SHADOWRECT:
4706 case TGSI_TEXTURE_2D_ARRAY:
4707 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4708 address[1] =
4709 lp_build_add(uint_bld, address[1],
4710 bld->immediates[off->Index][off->SwizzleY]);
4711 /* fall through */
4712 case TGSI_TEXTURE_1D:
4713 case TGSI_TEXTURE_SHADOW1D:
4714 case TGSI_TEXTURE_1D_ARRAY:
4715 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4716 address[0] =
4717 lp_build_add(uint_bld, address[0],
4718 bld->immediates[off->Index][off->SwizzleX]);
4719 break;
4720 /* texture offsets do not apply to other texture targets */
4721 }
4722 }
4723 }
4724
4725 if (opcode == TGSI_OPCODE_TG4) {
4726 unsigned gather_comp = 0;
4727
4728 /* DMASK was repurposed for GATHER4. 4 components are always
4729 * returned and DMASK works like a swizzle - it selects
4730 * the component to fetch. The only valid DMASK values are
4731 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4732 * (red,red,red,red) etc.) The ISA document doesn't mention
4733 * this.
4734 */
4735
4736 /* Get the component index from src1.x for Gather4. */
4737 if (!tgsi_is_shadow_target(target)) {
4738 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4739 LLVMValueRef comp_imm;
4740 struct tgsi_src_register src1 = inst->Src[1].Register;
4741
4742 assert(src1.File == TGSI_FILE_IMMEDIATE);
4743
4744 comp_imm = imms[src1.Index][src1.SwizzleX];
4745 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4746 gather_comp = CLAMP(gather_comp, 0, 3);
4747 }
4748
4749 dmask = 1 << gather_comp;
4750 }
4751
4752 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4753 samp_ptr, address, count, dmask);
4754 }
4755
4756 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4757 * incorrectly forces nearest filtering if the texture format is integer.
4758 * The only effect it has on Gather4, which always returns 4 texels for
4759 * bilinear filtering, is that the final coordinates are off by 0.5 of
4760 * the texel size.
4761 *
4762 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4763 * or (0.5 / size) from the normalized coordinates.
4764 */
4765 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4766 struct lp_build_emit_data *emit_data,
4767 const char *intr_name,
4768 unsigned coord_vgpr_index)
4769 {
4770 LLVMBuilderRef builder = ctx->gallivm.builder;
4771 LLVMValueRef coord = emit_data->args[0];
4772 LLVMValueRef half_texel[2];
4773 int c;
4774
4775 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4776 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4777 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4778 } else {
4779 struct tgsi_full_instruction txq_inst = {};
4780 struct lp_build_emit_data txq_emit_data = {};
4781
4782 /* Query the texture size. */
4783 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4784 txq_emit_data.inst = &txq_inst;
4785 txq_emit_data.dst_type = ctx->v4i32;
4786 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4787 txq_inst.Texture.Texture,
4788 emit_data->args[1], NULL,
4789 &ctx->soa.bld_base.uint_bld.zero,
4790 1, 0xf);
4791 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4792
4793 /* Compute -0.5 / size. */
4794 for (c = 0; c < 2; c++) {
4795 half_texel[c] =
4796 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4797 LLVMConstInt(ctx->i32, c, 0), "");
4798 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4799 half_texel[c] =
4800 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4801 TGSI_OPCODE_RCP, half_texel[c]);
4802 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4803 LLVMConstReal(ctx->f32, -0.5), "");
4804 }
4805 }
4806
4807 for (c = 0; c < 2; c++) {
4808 LLVMValueRef tmp;
4809 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4810
4811 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4812 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4813 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4814 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4815 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4816 }
4817
4818 emit_data->args[0] = coord;
4819 emit_data->output[emit_data->chan] =
4820 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4821 emit_data->args, emit_data->arg_count,
4822 LP_FUNC_ATTR_READNONE);
4823 }
4824
4825 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4826 struct lp_build_tgsi_context *bld_base,
4827 struct lp_build_emit_data *emit_data)
4828 {
4829 struct si_shader_context *ctx = si_shader_context(bld_base);
4830 struct lp_build_context *base = &bld_base->base;
4831 const struct tgsi_full_instruction *inst = emit_data->inst;
4832 unsigned opcode = inst->Instruction.Opcode;
4833 unsigned target = inst->Texture.Texture;
4834 char intr_name[127];
4835 bool has_offset = inst->Texture.NumOffsets > 0;
4836 bool is_shadow = tgsi_is_shadow_target(target);
4837 char type[64];
4838 const char *name = "llvm.SI.image.sample";
4839 const char *infix = "";
4840
4841 if (target == TGSI_TEXTURE_BUFFER) {
4842 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4843 base->gallivm->builder,
4844 "llvm.SI.vs.load.input", emit_data->dst_type,
4845 emit_data->args, emit_data->arg_count,
4846 LP_FUNC_ATTR_READNONE);
4847 return;
4848 }
4849
4850 switch (opcode) {
4851 case TGSI_OPCODE_TXF:
4852 name = target == TGSI_TEXTURE_2D_MSAA ||
4853 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4854 "llvm.SI.image.load" :
4855 "llvm.SI.image.load.mip";
4856 is_shadow = false;
4857 has_offset = false;
4858 break;
4859 case TGSI_OPCODE_LODQ:
4860 name = "llvm.SI.getlod";
4861 is_shadow = false;
4862 has_offset = false;
4863 break;
4864 case TGSI_OPCODE_TEX:
4865 case TGSI_OPCODE_TEX2:
4866 case TGSI_OPCODE_TXP:
4867 if (ctx->type != PIPE_SHADER_FRAGMENT)
4868 infix = ".lz";
4869 break;
4870 case TGSI_OPCODE_TXB:
4871 case TGSI_OPCODE_TXB2:
4872 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4873 infix = ".b";
4874 break;
4875 case TGSI_OPCODE_TXL:
4876 case TGSI_OPCODE_TXL2:
4877 infix = ".l";
4878 break;
4879 case TGSI_OPCODE_TXD:
4880 infix = ".d";
4881 break;
4882 case TGSI_OPCODE_TG4:
4883 name = "llvm.SI.gather4";
4884 infix = ".lz";
4885 break;
4886 default:
4887 assert(0);
4888 return;
4889 }
4890
4891 /* Add the type and suffixes .c, .o if needed. */
4892 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4893 sprintf(intr_name, "%s%s%s%s.%s",
4894 name, is_shadow ? ".c" : "", infix,
4895 has_offset ? ".o" : "", type);
4896
4897 /* The hardware needs special lowering for Gather4 with integer formats. */
4898 if (opcode == TGSI_OPCODE_TG4) {
4899 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4900 /* This will also work with non-constant indexing because of how
4901 * glsl_to_tgsi works and we intent to preserve that behavior.
4902 */
4903 const unsigned src_idx = 2;
4904 unsigned sampler = inst->Src[src_idx].Register.Index;
4905
4906 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4907
4908 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4909 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4910 /* Texture coordinates start after:
4911 * {offset, bias, z-compare, derivatives}
4912 * Only the offset and z-compare can occur here.
4913 */
4914 si_lower_gather4_integer(ctx, emit_data, intr_name,
4915 (int)has_offset + (int)is_shadow);
4916 return;
4917 }
4918 }
4919
4920 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4921 base->gallivm->builder, intr_name, emit_data->dst_type,
4922 emit_data->args, emit_data->arg_count,
4923 LP_FUNC_ATTR_READNONE);
4924 }
4925
4926 static void si_llvm_emit_txqs(
4927 const struct lp_build_tgsi_action *action,
4928 struct lp_build_tgsi_context *bld_base,
4929 struct lp_build_emit_data *emit_data)
4930 {
4931 struct si_shader_context *ctx = si_shader_context(bld_base);
4932 struct gallivm_state *gallivm = bld_base->base.gallivm;
4933 LLVMBuilderRef builder = gallivm->builder;
4934 LLVMValueRef res, samples;
4935 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4936
4937 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4938
4939
4940 /* Read the samples from the descriptor directly. */
4941 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4942 samples = LLVMBuildExtractElement(
4943 builder, res,
4944 lp_build_const_int32(gallivm, 3), "");
4945 samples = LLVMBuildLShr(builder, samples,
4946 lp_build_const_int32(gallivm, 16), "");
4947 samples = LLVMBuildAnd(builder, samples,
4948 lp_build_const_int32(gallivm, 0xf), "");
4949 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4950 samples, "");
4951
4952 emit_data->output[emit_data->chan] = samples;
4953 }
4954
4955 /*
4956 * SI implements derivatives using the local data store (LDS)
4957 * All writes to the LDS happen in all executing threads at
4958 * the same time. TID is the Thread ID for the current
4959 * thread and is a value between 0 and 63, representing
4960 * the thread's position in the wavefront.
4961 *
4962 * For the pixel shader threads are grouped into quads of four pixels.
4963 * The TIDs of the pixels of a quad are:
4964 *
4965 * +------+------+
4966 * |4n + 0|4n + 1|
4967 * +------+------+
4968 * |4n + 2|4n + 3|
4969 * +------+------+
4970 *
4971 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4972 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4973 * the current pixel's column, and masking with 0xfffffffe yields the TID
4974 * of the left pixel of the current pixel's row.
4975 *
4976 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4977 * adding 2 yields the TID of the pixel below the top pixel.
4978 */
4979 /* masks for thread ID. */
4980 #define TID_MASK_TOP_LEFT 0xfffffffc
4981 #define TID_MASK_TOP 0xfffffffd
4982 #define TID_MASK_LEFT 0xfffffffe
4983
4984 static void si_llvm_emit_ddxy(
4985 const struct lp_build_tgsi_action *action,
4986 struct lp_build_tgsi_context *bld_base,
4987 struct lp_build_emit_data *emit_data)
4988 {
4989 struct si_shader_context *ctx = si_shader_context(bld_base);
4990 struct gallivm_state *gallivm = bld_base->base.gallivm;
4991 unsigned opcode = emit_data->info->opcode;
4992 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
4993 int idx;
4994 unsigned mask;
4995
4996 thread_id = get_thread_id(ctx);
4997
4998 if (opcode == TGSI_OPCODE_DDX_FINE)
4999 mask = TID_MASK_LEFT;
5000 else if (opcode == TGSI_OPCODE_DDY_FINE)
5001 mask = TID_MASK_TOP;
5002 else
5003 mask = TID_MASK_TOP_LEFT;
5004
5005 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5006 lp_build_const_int32(gallivm, mask), "");
5007
5008 /* for DDX we want to next X pixel, DDY next Y pixel. */
5009 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5010 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5011 lp_build_const_int32(gallivm, idx), "");
5012
5013 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5014
5015 if (ctx->screen->has_ds_bpermute) {
5016 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5017 lp_build_const_int32(gallivm, 4), "");
5018 args[1] = val;
5019 tl = lp_build_intrinsic(gallivm->builder,
5020 "llvm.amdgcn.ds.bpermute", ctx->i32,
5021 args, 2, LP_FUNC_ATTR_READNONE);
5022
5023 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5024 lp_build_const_int32(gallivm, 4), "");
5025 trbl = lp_build_intrinsic(gallivm->builder,
5026 "llvm.amdgcn.ds.bpermute", ctx->i32,
5027 args, 2, LP_FUNC_ATTR_READNONE);
5028 } else {
5029 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5030
5031 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5032 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5033 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5034
5035 LLVMBuildStore(gallivm->builder, val, store_ptr);
5036 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5037 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5038 }
5039
5040 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5041 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5042
5043 emit_data->output[emit_data->chan] =
5044 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5045 }
5046
5047 /*
5048 * this takes an I,J coordinate pair,
5049 * and works out the X and Y derivatives.
5050 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5051 */
5052 static LLVMValueRef si_llvm_emit_ddxy_interp(
5053 struct lp_build_tgsi_context *bld_base,
5054 LLVMValueRef interp_ij)
5055 {
5056 struct si_shader_context *ctx = si_shader_context(bld_base);
5057 struct gallivm_state *gallivm = bld_base->base.gallivm;
5058 LLVMValueRef result[4], a;
5059 unsigned i;
5060
5061 for (i = 0; i < 2; i++) {
5062 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5063 LLVMConstInt(ctx->i32, i, 0), "");
5064 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5065 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5066 }
5067
5068 return lp_build_gather_values(gallivm, result, 4);
5069 }
5070
5071 static void interp_fetch_args(
5072 struct lp_build_tgsi_context *bld_base,
5073 struct lp_build_emit_data *emit_data)
5074 {
5075 struct si_shader_context *ctx = si_shader_context(bld_base);
5076 struct gallivm_state *gallivm = bld_base->base.gallivm;
5077 const struct tgsi_full_instruction *inst = emit_data->inst;
5078
5079 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5080 /* offset is in second src, first two channels */
5081 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5082 emit_data->inst, 1,
5083 TGSI_CHAN_X);
5084 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5085 emit_data->inst, 1,
5086 TGSI_CHAN_Y);
5087 emit_data->arg_count = 2;
5088 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5089 LLVMValueRef sample_position;
5090 LLVMValueRef sample_id;
5091 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5092
5093 /* fetch sample ID, then fetch its sample position,
5094 * and place into first two channels.
5095 */
5096 sample_id = lp_build_emit_fetch(bld_base,
5097 emit_data->inst, 1, TGSI_CHAN_X);
5098 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5099 ctx->i32, "");
5100 sample_position = load_sample_position(ctx, sample_id);
5101
5102 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5103 sample_position,
5104 lp_build_const_int32(gallivm, 0), "");
5105
5106 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5107 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5108 sample_position,
5109 lp_build_const_int32(gallivm, 1), "");
5110 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5111 emit_data->arg_count = 2;
5112 }
5113 }
5114
5115 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5116 struct lp_build_tgsi_context *bld_base,
5117 struct lp_build_emit_data *emit_data)
5118 {
5119 struct si_shader_context *ctx = si_shader_context(bld_base);
5120 struct si_shader *shader = ctx->shader;
5121 struct gallivm_state *gallivm = bld_base->base.gallivm;
5122 struct lp_build_context *uint = &bld_base->uint_bld;
5123 LLVMValueRef interp_param;
5124 const struct tgsi_full_instruction *inst = emit_data->inst;
5125 int input_index = inst->Src[0].Register.Index;
5126 int chan;
5127 int i;
5128 LLVMValueRef attr_number;
5129 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5130 int interp_param_idx;
5131 unsigned interp = shader->selector->info.input_interpolate[input_index];
5132 unsigned location;
5133
5134 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5135
5136 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5137 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5138 location = TGSI_INTERPOLATE_LOC_CENTER;
5139 else
5140 location = TGSI_INTERPOLATE_LOC_CENTROID;
5141
5142 interp_param_idx = lookup_interp_param_index(interp, location);
5143 if (interp_param_idx == -1)
5144 return;
5145 else if (interp_param_idx)
5146 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5147 else
5148 interp_param = NULL;
5149
5150 attr_number = lp_build_const_int32(gallivm, input_index);
5151
5152 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5153 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5154 LLVMValueRef ij_out[2];
5155 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5156
5157 /*
5158 * take the I then J parameters, and the DDX/Y for it, and
5159 * calculate the IJ inputs for the interpolator.
5160 * temp1 = ddx * offset/sample.x + I;
5161 * interp_param.I = ddy * offset/sample.y + temp1;
5162 * temp1 = ddx * offset/sample.x + J;
5163 * interp_param.J = ddy * offset/sample.y + temp1;
5164 */
5165 for (i = 0; i < 2; i++) {
5166 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5167 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5168 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5169 ddxy_out, ix_ll, "");
5170 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5171 ddxy_out, iy_ll, "");
5172 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5173 interp_param, ix_ll, "");
5174 LLVMValueRef temp1, temp2;
5175
5176 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5177 ctx->f32, "");
5178
5179 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5180
5181 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5182
5183 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5184
5185 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5186 }
5187 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5188 }
5189
5190 for (chan = 0; chan < 4; chan++) {
5191 LLVMValueRef llvm_chan;
5192 unsigned schan;
5193
5194 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5195 llvm_chan = lp_build_const_int32(gallivm, schan);
5196
5197 if (interp_param) {
5198 interp_param = LLVMBuildBitCast(gallivm->builder,
5199 interp_param, LLVMVectorType(ctx->f32, 2), "");
5200 LLVMValueRef i = LLVMBuildExtractElement(
5201 gallivm->builder, interp_param, uint->zero, "");
5202 LLVMValueRef j = LLVMBuildExtractElement(
5203 gallivm->builder, interp_param, uint->one, "");
5204 emit_data->output[chan] = build_fs_interp(bld_base,
5205 llvm_chan, attr_number, params,
5206 i, j);
5207 } else {
5208 emit_data->output[chan] = build_fs_interp_mov(bld_base,
5209 lp_build_const_int32(gallivm, 2), /* P0 */
5210 llvm_chan, attr_number, params);
5211 }
5212 }
5213 }
5214
5215 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5216 struct lp_build_emit_data *emit_data)
5217 {
5218 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5219 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5220 unsigned stream;
5221
5222 assert(src0.File == TGSI_FILE_IMMEDIATE);
5223
5224 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5225 return stream;
5226 }
5227
5228 /* Emit one vertex from the geometry shader */
5229 static void si_llvm_emit_vertex(
5230 const struct lp_build_tgsi_action *action,
5231 struct lp_build_tgsi_context *bld_base,
5232 struct lp_build_emit_data *emit_data)
5233 {
5234 struct si_shader_context *ctx = si_shader_context(bld_base);
5235 struct lp_build_context *uint = &bld_base->uint_bld;
5236 struct si_shader *shader = ctx->shader;
5237 struct tgsi_shader_info *info = &shader->selector->info;
5238 struct gallivm_state *gallivm = bld_base->base.gallivm;
5239 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5240 SI_PARAM_GS2VS_OFFSET);
5241 LLVMValueRef gs_next_vertex;
5242 LLVMValueRef can_emit, kill;
5243 LLVMValueRef args[2];
5244 unsigned chan;
5245 int i;
5246 unsigned stream;
5247
5248 stream = si_llvm_get_stream(bld_base, emit_data);
5249
5250 /* Write vertex attribute values to GSVS ring */
5251 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5252 ctx->gs_next_vertex[stream],
5253 "");
5254
5255 /* If this thread has already emitted the declared maximum number of
5256 * vertices, kill it: excessive vertex emissions are not supposed to
5257 * have any effect, and GS threads have no externally observable
5258 * effects other than emitting vertices.
5259 */
5260 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5261 lp_build_const_int32(gallivm,
5262 shader->selector->gs_max_out_vertices), "");
5263 kill = lp_build_select(&bld_base->base, can_emit,
5264 lp_build_const_float(gallivm, 1.0f),
5265 lp_build_const_float(gallivm, -1.0f));
5266
5267 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5268 ctx->voidt, &kill, 1, 0);
5269
5270 for (i = 0; i < info->num_outputs; i++) {
5271 LLVMValueRef *out_ptr =
5272 ctx->soa.outputs[i];
5273
5274 for (chan = 0; chan < 4; chan++) {
5275 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5276 LLVMValueRef voffset =
5277 lp_build_const_int32(gallivm, (i * 4 + chan) *
5278 shader->selector->gs_max_out_vertices);
5279
5280 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5281 voffset = lp_build_mul_imm(uint, voffset, 4);
5282
5283 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5284
5285 build_tbuffer_store(ctx,
5286 ctx->gsvs_ring[stream],
5287 out_val, 1,
5288 voffset, soffset, 0,
5289 V_008F0C_BUF_DATA_FORMAT_32,
5290 V_008F0C_BUF_NUM_FORMAT_UINT,
5291 1, 0, 1, 1, 0);
5292 }
5293 }
5294 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5295 lp_build_const_int32(gallivm, 1));
5296
5297 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5298
5299 /* Signal vertex emission */
5300 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5301 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5302 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5303 ctx->voidt, args, 2, 0);
5304 }
5305
5306 /* Cut one primitive from the geometry shader */
5307 static void si_llvm_emit_primitive(
5308 const struct lp_build_tgsi_action *action,
5309 struct lp_build_tgsi_context *bld_base,
5310 struct lp_build_emit_data *emit_data)
5311 {
5312 struct si_shader_context *ctx = si_shader_context(bld_base);
5313 struct gallivm_state *gallivm = bld_base->base.gallivm;
5314 LLVMValueRef args[2];
5315 unsigned stream;
5316
5317 /* Signal primitive cut */
5318 stream = si_llvm_get_stream(bld_base, emit_data);
5319 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5320 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5321 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5322 ctx->voidt, args, 2, 0);
5323 }
5324
5325 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5326 struct lp_build_tgsi_context *bld_base,
5327 struct lp_build_emit_data *emit_data)
5328 {
5329 struct si_shader_context *ctx = si_shader_context(bld_base);
5330 struct gallivm_state *gallivm = bld_base->base.gallivm;
5331
5332 /* The real barrier instruction isn’t needed, because an entire patch
5333 * always fits into a single wave.
5334 */
5335 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5336 emit_optimization_barrier(ctx);
5337 return;
5338 }
5339
5340 lp_build_intrinsic(gallivm->builder,
5341 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5342 : "llvm.AMDGPU.barrier.local",
5343 ctx->voidt, NULL, 0, 0);
5344 }
5345
5346 static const struct lp_build_tgsi_action tex_action = {
5347 .fetch_args = tex_fetch_args,
5348 .emit = build_tex_intrinsic,
5349 };
5350
5351 static const struct lp_build_tgsi_action interp_action = {
5352 .fetch_args = interp_fetch_args,
5353 .emit = build_interp_intrinsic,
5354 };
5355
5356 static void si_create_function(struct si_shader_context *ctx,
5357 const char *name,
5358 LLVMTypeRef *returns, unsigned num_returns,
5359 LLVMTypeRef *params, unsigned num_params,
5360 int last_sgpr)
5361 {
5362 int i;
5363
5364 si_llvm_create_func(ctx, name, returns, num_returns,
5365 params, num_params);
5366 si_llvm_shader_type(ctx->main_fn, ctx->type);
5367 ctx->return_value = LLVMGetUndef(ctx->return_type);
5368
5369 for (i = 0; i <= last_sgpr; ++i) {
5370 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5371
5372 /* The combination of:
5373 * - ByVal
5374 * - dereferenceable
5375 * - invariant.load
5376 * allows the optimization passes to move loads and reduces
5377 * SGPR spilling significantly.
5378 */
5379 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5380 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5381 lp_add_attr_dereferenceable(P, UINT64_MAX);
5382 } else
5383 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5384 }
5385
5386 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5387 /* These were copied from some LLVM test. */
5388 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5389 "less-precise-fpmad",
5390 "true");
5391 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5392 "no-infs-fp-math",
5393 "true");
5394 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5395 "no-nans-fp-math",
5396 "true");
5397 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5398 "unsafe-fp-math",
5399 "true");
5400 }
5401 }
5402
5403 static void create_meta_data(struct si_shader_context *ctx)
5404 {
5405 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5406
5407 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5408 "invariant.load", 14);
5409 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5410 "range", 5);
5411 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5412 "amdgpu.uniform", 14);
5413
5414 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5415 }
5416
5417 static void declare_streamout_params(struct si_shader_context *ctx,
5418 struct pipe_stream_output_info *so,
5419 LLVMTypeRef *params, LLVMTypeRef i32,
5420 unsigned *num_params)
5421 {
5422 int i;
5423
5424 /* Streamout SGPRs. */
5425 if (so->num_outputs) {
5426 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5427 params[ctx->param_streamout_config = (*num_params)++] = i32;
5428 else
5429 ctx->param_streamout_config = ctx->param_tess_offchip;
5430
5431 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5432 }
5433 /* A streamout buffer offset is loaded if the stride is non-zero. */
5434 for (i = 0; i < 4; i++) {
5435 if (!so->stride[i])
5436 continue;
5437
5438 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5439 }
5440 }
5441
5442 static unsigned llvm_get_type_size(LLVMTypeRef type)
5443 {
5444 LLVMTypeKind kind = LLVMGetTypeKind(type);
5445
5446 switch (kind) {
5447 case LLVMIntegerTypeKind:
5448 return LLVMGetIntTypeWidth(type) / 8;
5449 case LLVMFloatTypeKind:
5450 return 4;
5451 case LLVMPointerTypeKind:
5452 return 8;
5453 case LLVMVectorTypeKind:
5454 return LLVMGetVectorSize(type) *
5455 llvm_get_type_size(LLVMGetElementType(type));
5456 case LLVMArrayTypeKind:
5457 return LLVMGetArrayLength(type) *
5458 llvm_get_type_size(LLVMGetElementType(type));
5459 default:
5460 assert(0);
5461 return 0;
5462 }
5463 }
5464
5465 static void declare_tess_lds(struct si_shader_context *ctx)
5466 {
5467 struct gallivm_state *gallivm = &ctx->gallivm;
5468 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5469 struct lp_build_context *uint = &bld_base->uint_bld;
5470
5471 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5472 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5473 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5474 "tess_lds");
5475 }
5476
5477 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5478 {
5479 const unsigned *properties = shader->selector->info.properties;
5480 unsigned max_work_group_size =
5481 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5482 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5483 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5484
5485 if (!max_work_group_size) {
5486 /* This is a variable group size compute shader,
5487 * compile it for the maximum possible group size.
5488 */
5489 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5490 }
5491 return max_work_group_size;
5492 }
5493
5494 static void create_function(struct si_shader_context *ctx)
5495 {
5496 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5497 struct gallivm_state *gallivm = bld_base->base.gallivm;
5498 struct si_shader *shader = ctx->shader;
5499 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5500 LLVMTypeRef returns[16+32*4];
5501 unsigned i, last_sgpr, num_params, num_return_sgprs;
5502 unsigned num_returns = 0;
5503 unsigned num_prolog_vgprs = 0;
5504
5505 v3i32 = LLVMVectorType(ctx->i32, 3);
5506
5507 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5508 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5509 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5510 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5511 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5512
5513 switch (ctx->type) {
5514 case PIPE_SHADER_VERTEX:
5515 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5516 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5517 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5518 params[SI_PARAM_DRAWID] = ctx->i32;
5519 num_params = SI_PARAM_DRAWID+1;
5520
5521 if (shader->key.as_es) {
5522 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5523 } else if (shader->key.as_ls) {
5524 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5525 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5526 } else {
5527 if (shader->is_gs_copy_shader) {
5528 num_params = SI_PARAM_RW_BUFFERS+1;
5529 } else {
5530 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5531 num_params = SI_PARAM_VS_STATE_BITS+1;
5532 }
5533
5534 /* The locations of the other parameters are assigned dynamically. */
5535 declare_streamout_params(ctx, &shader->selector->so,
5536 params, ctx->i32, &num_params);
5537 }
5538
5539 last_sgpr = num_params-1;
5540
5541 /* VGPRs */
5542 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5543 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5544 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5545 params[ctx->param_instance_id = num_params++] = ctx->i32;
5546
5547 if (!shader->is_gs_copy_shader) {
5548 /* Vertex load indices. */
5549 ctx->param_vertex_index0 = num_params;
5550
5551 for (i = 0; i < shader->selector->info.num_inputs; i++)
5552 params[num_params++] = ctx->i32;
5553
5554 num_prolog_vgprs += shader->selector->info.num_inputs;
5555
5556 /* PrimitiveID output. */
5557 if (!shader->key.as_es && !shader->key.as_ls)
5558 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5559 returns[num_returns++] = ctx->f32;
5560 }
5561 break;
5562
5563 case PIPE_SHADER_TESS_CTRL:
5564 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5565 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5566 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5567 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5568 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5569 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5570 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5571
5572 /* VGPRs */
5573 params[SI_PARAM_PATCH_ID] = ctx->i32;
5574 params[SI_PARAM_REL_IDS] = ctx->i32;
5575 num_params = SI_PARAM_REL_IDS+1;
5576
5577 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5578 * placed after the user SGPRs.
5579 */
5580 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5581 returns[num_returns++] = ctx->i32; /* SGPRs */
5582
5583 for (i = 0; i < 3; i++)
5584 returns[num_returns++] = ctx->f32; /* VGPRs */
5585 break;
5586
5587 case PIPE_SHADER_TESS_EVAL:
5588 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5589 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5590
5591 if (shader->key.as_es) {
5592 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5593 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5594 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5595 } else {
5596 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5597 declare_streamout_params(ctx, &shader->selector->so,
5598 params, ctx->i32, &num_params);
5599 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5600 }
5601 last_sgpr = num_params - 1;
5602
5603 /* VGPRs */
5604 params[ctx->param_tes_u = num_params++] = ctx->f32;
5605 params[ctx->param_tes_v = num_params++] = ctx->f32;
5606 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5607 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5608
5609 /* PrimitiveID output. */
5610 if (!shader->key.as_es)
5611 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5612 returns[num_returns++] = ctx->f32;
5613 break;
5614
5615 case PIPE_SHADER_GEOMETRY:
5616 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5617 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5618 last_sgpr = SI_PARAM_GS_WAVE_ID;
5619
5620 /* VGPRs */
5621 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5622 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5623 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5624 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5625 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5626 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5627 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5628 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5629 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5630 break;
5631
5632 case PIPE_SHADER_FRAGMENT:
5633 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5634 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5635 last_sgpr = SI_PARAM_PRIM_MASK;
5636 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5637 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5638 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5639 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5640 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5641 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5642 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5643 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5644 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5645 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5646 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5647 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5648 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5649 shader->info.face_vgpr_index = 20;
5650 params[SI_PARAM_ANCILLARY] = ctx->i32;
5651 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5652 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5653 num_params = SI_PARAM_POS_FIXED_PT+1;
5654
5655 /* Color inputs from the prolog. */
5656 if (shader->selector->info.colors_read) {
5657 unsigned num_color_elements =
5658 util_bitcount(shader->selector->info.colors_read);
5659
5660 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5661 for (i = 0; i < num_color_elements; i++)
5662 params[num_params++] = ctx->f32;
5663
5664 num_prolog_vgprs += num_color_elements;
5665 }
5666
5667 /* Outputs for the epilog. */
5668 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5669 num_returns =
5670 num_return_sgprs +
5671 util_bitcount(shader->selector->info.colors_written) * 4 +
5672 shader->selector->info.writes_z +
5673 shader->selector->info.writes_stencil +
5674 shader->selector->info.writes_samplemask +
5675 1 /* SampleMaskIn */;
5676
5677 num_returns = MAX2(num_returns,
5678 num_return_sgprs +
5679 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5680
5681 for (i = 0; i < num_return_sgprs; i++)
5682 returns[i] = ctx->i32;
5683 for (; i < num_returns; i++)
5684 returns[i] = ctx->f32;
5685 break;
5686
5687 case PIPE_SHADER_COMPUTE:
5688 params[SI_PARAM_GRID_SIZE] = v3i32;
5689 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5690 params[SI_PARAM_BLOCK_ID] = v3i32;
5691 last_sgpr = SI_PARAM_BLOCK_ID;
5692
5693 params[SI_PARAM_THREAD_ID] = v3i32;
5694 num_params = SI_PARAM_THREAD_ID + 1;
5695 break;
5696 default:
5697 assert(0 && "unimplemented shader");
5698 return;
5699 }
5700
5701 assert(num_params <= ARRAY_SIZE(params));
5702
5703 si_create_function(ctx, "main", returns, num_returns, params,
5704 num_params, last_sgpr);
5705
5706 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5707 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5708 ctx->separate_prolog) {
5709 si_llvm_add_attribute(ctx->main_fn,
5710 "InitialPSInputAddr",
5711 S_0286D0_PERSP_SAMPLE_ENA(1) |
5712 S_0286D0_PERSP_CENTER_ENA(1) |
5713 S_0286D0_PERSP_CENTROID_ENA(1) |
5714 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5715 S_0286D0_LINEAR_CENTER_ENA(1) |
5716 S_0286D0_LINEAR_CENTROID_ENA(1) |
5717 S_0286D0_FRONT_FACE_ENA(1) |
5718 S_0286D0_POS_FIXED_PT_ENA(1));
5719 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5720 si_llvm_add_attribute(ctx->main_fn,
5721 "amdgpu-max-work-group-size",
5722 si_get_max_workgroup_size(shader));
5723 }
5724
5725 shader->info.num_input_sgprs = 0;
5726 shader->info.num_input_vgprs = 0;
5727
5728 for (i = 0; i <= last_sgpr; ++i)
5729 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5730
5731 for (; i < num_params; ++i)
5732 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5733
5734 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5735 shader->info.num_input_vgprs -= num_prolog_vgprs;
5736
5737 if (!ctx->screen->has_ds_bpermute &&
5738 bld_base->info &&
5739 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5740 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5741 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5742 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5743 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5744 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5745 ctx->lds =
5746 LLVMAddGlobalInAddressSpace(gallivm->module,
5747 LLVMArrayType(ctx->i32, 64),
5748 "ddxy_lds",
5749 LOCAL_ADDR_SPACE);
5750
5751 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5752 ctx->type == PIPE_SHADER_TESS_CTRL ||
5753 ctx->type == PIPE_SHADER_TESS_EVAL)
5754 declare_tess_lds(ctx);
5755 }
5756
5757 /**
5758 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5759 * for later use.
5760 */
5761 static void preload_ring_buffers(struct si_shader_context *ctx)
5762 {
5763 struct gallivm_state *gallivm =
5764 ctx->soa.bld_base.base.gallivm;
5765
5766 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5767 SI_PARAM_RW_BUFFERS);
5768
5769 if ((ctx->type == PIPE_SHADER_VERTEX &&
5770 ctx->shader->key.as_es) ||
5771 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5772 ctx->shader->key.as_es) ||
5773 ctx->type == PIPE_SHADER_GEOMETRY) {
5774 unsigned ring =
5775 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5776 : SI_ES_RING_ESGS;
5777 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5778
5779 ctx->esgs_ring =
5780 build_indexed_load_const(ctx, buf_ptr, offset);
5781 }
5782
5783 if (ctx->shader->is_gs_copy_shader) {
5784 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5785
5786 ctx->gsvs_ring[0] =
5787 build_indexed_load_const(ctx, buf_ptr, offset);
5788 }
5789 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5790 int i;
5791 for (i = 0; i < 4; i++) {
5792 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5793
5794 ctx->gsvs_ring[i] =
5795 build_indexed_load_const(ctx, buf_ptr, offset);
5796 }
5797 }
5798 }
5799
5800 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5801 LLVMValueRef param_rw_buffers,
5802 unsigned param_pos_fixed_pt)
5803 {
5804 struct lp_build_tgsi_context *bld_base =
5805 &ctx->soa.bld_base;
5806 struct gallivm_state *gallivm = bld_base->base.gallivm;
5807 LLVMBuilderRef builder = gallivm->builder;
5808 LLVMValueRef slot, desc, offset, row, bit, address[2];
5809
5810 /* Use the fixed-point gl_FragCoord input.
5811 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5812 * per coordinate to get the repeating effect.
5813 */
5814 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5815 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5816
5817 /* Load the buffer descriptor. */
5818 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5819 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5820
5821 /* The stipple pattern is 32x32, each row has 32 bits. */
5822 offset = LLVMBuildMul(builder, address[1],
5823 LLVMConstInt(ctx->i32, 4, 0), "");
5824 row = buffer_load_const(ctx, desc, offset);
5825 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5826 bit = LLVMBuildLShr(builder, row, address[0], "");
5827 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5828
5829 /* The intrinsic kills the thread if arg < 0. */
5830 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5831 LLVMConstReal(ctx->f32, -1), "");
5832 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5833 }
5834
5835 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5836 struct si_shader_config *conf,
5837 unsigned symbol_offset)
5838 {
5839 unsigned i;
5840 const unsigned char *config =
5841 radeon_shader_binary_config_start(binary, symbol_offset);
5842 bool really_needs_scratch = false;
5843
5844 /* LLVM adds SGPR spills to the scratch size.
5845 * Find out if we really need the scratch buffer.
5846 */
5847 for (i = 0; i < binary->reloc_count; i++) {
5848 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5849
5850 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5851 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5852 really_needs_scratch = true;
5853 break;
5854 }
5855 }
5856
5857 /* XXX: We may be able to emit some of these values directly rather than
5858 * extracting fields to be emitted later.
5859 */
5860
5861 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5862 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5863 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5864 switch (reg) {
5865 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5866 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5867 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5868 case R_00B848_COMPUTE_PGM_RSRC1:
5869 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5870 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5871 conf->float_mode = G_00B028_FLOAT_MODE(value);
5872 conf->rsrc1 = value;
5873 break;
5874 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5875 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5876 break;
5877 case R_00B84C_COMPUTE_PGM_RSRC2:
5878 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5879 conf->rsrc2 = value;
5880 break;
5881 case R_0286CC_SPI_PS_INPUT_ENA:
5882 conf->spi_ps_input_ena = value;
5883 break;
5884 case R_0286D0_SPI_PS_INPUT_ADDR:
5885 conf->spi_ps_input_addr = value;
5886 break;
5887 case R_0286E8_SPI_TMPRING_SIZE:
5888 case R_00B860_COMPUTE_TMPRING_SIZE:
5889 /* WAVESIZE is in units of 256 dwords. */
5890 if (really_needs_scratch)
5891 conf->scratch_bytes_per_wave =
5892 G_00B860_WAVESIZE(value) * 256 * 4;
5893 break;
5894 case 0x4: /* SPILLED_SGPRS */
5895 conf->spilled_sgprs = value;
5896 break;
5897 case 0x8: /* SPILLED_VGPRS */
5898 conf->spilled_vgprs = value;
5899 break;
5900 default:
5901 {
5902 static bool printed;
5903
5904 if (!printed) {
5905 fprintf(stderr, "Warning: LLVM emitted unknown "
5906 "config register: 0x%x\n", reg);
5907 printed = true;
5908 }
5909 }
5910 break;
5911 }
5912 }
5913
5914 if (!conf->spi_ps_input_addr)
5915 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5916 }
5917
5918 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5919 struct si_shader *shader,
5920 struct si_shader_config *config,
5921 uint64_t scratch_va)
5922 {
5923 unsigned i;
5924 uint32_t scratch_rsrc_dword0 = scratch_va;
5925 uint32_t scratch_rsrc_dword1 =
5926 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5927
5928 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5929 * correctly.
5930 */
5931 if (HAVE_LLVM >= 0x0309)
5932 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5933 else
5934 scratch_rsrc_dword1 |=
5935 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5936
5937 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5938 const struct radeon_shader_reloc *reloc =
5939 &shader->binary.relocs[i];
5940 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5941 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5942 &scratch_rsrc_dword0, 4);
5943 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5944 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5945 &scratch_rsrc_dword1, 4);
5946 }
5947 }
5948 }
5949
5950 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5951 {
5952 unsigned size = shader->binary.code_size;
5953
5954 if (shader->prolog)
5955 size += shader->prolog->binary.code_size;
5956 if (shader->epilog)
5957 size += shader->epilog->binary.code_size;
5958 return size;
5959 }
5960
5961 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5962 {
5963 const struct radeon_shader_binary *prolog =
5964 shader->prolog ? &shader->prolog->binary : NULL;
5965 const struct radeon_shader_binary *epilog =
5966 shader->epilog ? &shader->epilog->binary : NULL;
5967 const struct radeon_shader_binary *mainb = &shader->binary;
5968 unsigned bo_size = si_get_shader_binary_size(shader) +
5969 (!epilog ? mainb->rodata_size : 0);
5970 unsigned char *ptr;
5971
5972 assert(!prolog || !prolog->rodata_size);
5973 assert((!prolog && !epilog) || !mainb->rodata_size);
5974 assert(!epilog || !epilog->rodata_size);
5975
5976 r600_resource_reference(&shader->bo, NULL);
5977 shader->bo = (struct r600_resource*)
5978 pipe_buffer_create(&sscreen->b.b, 0,
5979 PIPE_USAGE_IMMUTABLE, bo_size);
5980 if (!shader->bo)
5981 return -ENOMEM;
5982
5983 /* Upload. */
5984 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5985 PIPE_TRANSFER_READ_WRITE);
5986
5987 if (prolog) {
5988 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5989 ptr += prolog->code_size;
5990 }
5991
5992 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5993 ptr += mainb->code_size;
5994
5995 if (epilog)
5996 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5997 else if (mainb->rodata_size > 0)
5998 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5999
6000 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6001 return 0;
6002 }
6003
6004 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6005 struct pipe_debug_callback *debug,
6006 const char *name, FILE *file)
6007 {
6008 char *line, *p;
6009 unsigned i, count;
6010
6011 if (binary->disasm_string) {
6012 fprintf(file, "Shader %s disassembly:\n", name);
6013 fprintf(file, "%s", binary->disasm_string);
6014
6015 if (debug && debug->debug_message) {
6016 /* Very long debug messages are cut off, so send the
6017 * disassembly one line at a time. This causes more
6018 * overhead, but on the plus side it simplifies
6019 * parsing of resulting logs.
6020 */
6021 pipe_debug_message(debug, SHADER_INFO,
6022 "Shader Disassembly Begin");
6023
6024 line = binary->disasm_string;
6025 while (*line) {
6026 p = util_strchrnul(line, '\n');
6027 count = p - line;
6028
6029 if (count) {
6030 pipe_debug_message(debug, SHADER_INFO,
6031 "%.*s", count, line);
6032 }
6033
6034 if (!*p)
6035 break;
6036 line = p + 1;
6037 }
6038
6039 pipe_debug_message(debug, SHADER_INFO,
6040 "Shader Disassembly End");
6041 }
6042 } else {
6043 fprintf(file, "Shader %s binary:\n", name);
6044 for (i = 0; i < binary->code_size; i += 4) {
6045 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6046 binary->code[i + 3], binary->code[i + 2],
6047 binary->code[i + 1], binary->code[i]);
6048 }
6049 }
6050 }
6051
6052 static void si_shader_dump_stats(struct si_screen *sscreen,
6053 struct si_shader *shader,
6054 struct pipe_debug_callback *debug,
6055 unsigned processor,
6056 FILE *file)
6057 {
6058 struct si_shader_config *conf = &shader->config;
6059 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6060 unsigned code_size = si_get_shader_binary_size(shader);
6061 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6062 unsigned lds_per_wave = 0;
6063 unsigned max_simd_waves = 10;
6064
6065 /* Compute LDS usage for PS. */
6066 switch (processor) {
6067 case PIPE_SHADER_FRAGMENT:
6068 /* The minimum usage per wave is (num_inputs * 48). The maximum
6069 * usage is (num_inputs * 48 * 16).
6070 * We can get anything in between and it varies between waves.
6071 *
6072 * The 48 bytes per input for a single primitive is equal to
6073 * 4 bytes/component * 4 components/input * 3 points.
6074 *
6075 * Other stages don't know the size at compile time or don't
6076 * allocate LDS per wave, but instead they do it per thread group.
6077 */
6078 lds_per_wave = conf->lds_size * lds_increment +
6079 align(num_inputs * 48, lds_increment);
6080 break;
6081 case PIPE_SHADER_COMPUTE:
6082 if (shader->selector) {
6083 unsigned max_workgroup_size =
6084 si_get_max_workgroup_size(shader);
6085 lds_per_wave = (conf->lds_size * lds_increment) /
6086 DIV_ROUND_UP(max_workgroup_size, 64);
6087 }
6088 break;
6089 }
6090
6091 /* Compute the per-SIMD wave counts. */
6092 if (conf->num_sgprs) {
6093 if (sscreen->b.chip_class >= VI)
6094 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6095 else
6096 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6097 }
6098
6099 if (conf->num_vgprs)
6100 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6101
6102 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6103 * 16KB makes some SIMDs unoccupied). */
6104 if (lds_per_wave)
6105 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6106
6107 if (file != stderr ||
6108 r600_can_dump_shader(&sscreen->b, processor)) {
6109 if (processor == PIPE_SHADER_FRAGMENT) {
6110 fprintf(file, "*** SHADER CONFIG ***\n"
6111 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6112 "SPI_PS_INPUT_ENA = 0x%04x\n",
6113 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6114 }
6115
6116 fprintf(file, "*** SHADER STATS ***\n"
6117 "SGPRS: %d\n"
6118 "VGPRS: %d\n"
6119 "Spilled SGPRs: %d\n"
6120 "Spilled VGPRs: %d\n"
6121 "Private memory VGPRs: %d\n"
6122 "Code Size: %d bytes\n"
6123 "LDS: %d blocks\n"
6124 "Scratch: %d bytes per wave\n"
6125 "Max Waves: %d\n"
6126 "********************\n\n\n",
6127 conf->num_sgprs, conf->num_vgprs,
6128 conf->spilled_sgprs, conf->spilled_vgprs,
6129 conf->private_mem_vgprs, code_size,
6130 conf->lds_size, conf->scratch_bytes_per_wave,
6131 max_simd_waves);
6132 }
6133
6134 pipe_debug_message(debug, SHADER_INFO,
6135 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6136 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6137 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6138 conf->num_sgprs, conf->num_vgprs, code_size,
6139 conf->lds_size, conf->scratch_bytes_per_wave,
6140 max_simd_waves, conf->spilled_sgprs,
6141 conf->spilled_vgprs, conf->private_mem_vgprs);
6142 }
6143
6144 static const char *si_get_shader_name(struct si_shader *shader,
6145 unsigned processor)
6146 {
6147 switch (processor) {
6148 case PIPE_SHADER_VERTEX:
6149 if (shader->key.as_es)
6150 return "Vertex Shader as ES";
6151 else if (shader->key.as_ls)
6152 return "Vertex Shader as LS";
6153 else
6154 return "Vertex Shader as VS";
6155 case PIPE_SHADER_TESS_CTRL:
6156 return "Tessellation Control Shader";
6157 case PIPE_SHADER_TESS_EVAL:
6158 if (shader->key.as_es)
6159 return "Tessellation Evaluation Shader as ES";
6160 else
6161 return "Tessellation Evaluation Shader as VS";
6162 case PIPE_SHADER_GEOMETRY:
6163 if (shader->is_gs_copy_shader)
6164 return "GS Copy Shader as VS";
6165 else
6166 return "Geometry Shader";
6167 case PIPE_SHADER_FRAGMENT:
6168 return "Pixel Shader";
6169 case PIPE_SHADER_COMPUTE:
6170 return "Compute Shader";
6171 default:
6172 return "Unknown Shader";
6173 }
6174 }
6175
6176 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6177 struct pipe_debug_callback *debug, unsigned processor,
6178 FILE *file)
6179 {
6180 if (file != stderr ||
6181 r600_can_dump_shader(&sscreen->b, processor))
6182 si_dump_shader_key(processor, &shader->key, file);
6183
6184 if (file != stderr && shader->binary.llvm_ir_string) {
6185 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6186 si_get_shader_name(shader, processor));
6187 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6188 }
6189
6190 if (file != stderr ||
6191 (r600_can_dump_shader(&sscreen->b, processor) &&
6192 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6193 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6194
6195 if (shader->prolog)
6196 si_shader_dump_disassembly(&shader->prolog->binary,
6197 debug, "prolog", file);
6198
6199 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6200
6201 if (shader->epilog)
6202 si_shader_dump_disassembly(&shader->epilog->binary,
6203 debug, "epilog", file);
6204 fprintf(file, "\n");
6205 }
6206
6207 si_shader_dump_stats(sscreen, shader, debug, processor, file);
6208 }
6209
6210 int si_compile_llvm(struct si_screen *sscreen,
6211 struct radeon_shader_binary *binary,
6212 struct si_shader_config *conf,
6213 LLVMTargetMachineRef tm,
6214 LLVMModuleRef mod,
6215 struct pipe_debug_callback *debug,
6216 unsigned processor,
6217 const char *name)
6218 {
6219 int r = 0;
6220 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6221
6222 if (r600_can_dump_shader(&sscreen->b, processor)) {
6223 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6224
6225 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6226 fprintf(stderr, "%s LLVM IR:\n\n", name);
6227 LLVMDumpModule(mod);
6228 fprintf(stderr, "\n");
6229 }
6230 }
6231
6232 if (sscreen->record_llvm_ir) {
6233 char *ir = LLVMPrintModuleToString(mod);
6234 binary->llvm_ir_string = strdup(ir);
6235 LLVMDisposeMessage(ir);
6236 }
6237
6238 if (!si_replace_shader(count, binary)) {
6239 r = si_llvm_compile(mod, binary, tm, debug);
6240 if (r)
6241 return r;
6242 }
6243
6244 si_shader_binary_read_config(binary, conf, 0);
6245
6246 /* Enable 64-bit and 16-bit denormals, because there is no performance
6247 * cost.
6248 *
6249 * If denormals are enabled, all floating-point output modifiers are
6250 * ignored.
6251 *
6252 * Don't enable denormals for 32-bit floats, because:
6253 * - Floating-point output modifiers would be ignored by the hw.
6254 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6255 * have to stop using those.
6256 * - SI & CI would be very slow.
6257 */
6258 conf->float_mode |= V_00B028_FP_64_DENORMS;
6259
6260 FREE(binary->config);
6261 FREE(binary->global_symbol_offsets);
6262 binary->config = NULL;
6263 binary->global_symbol_offsets = NULL;
6264
6265 /* Some shaders can't have rodata because their binaries can be
6266 * concatenated.
6267 */
6268 if (binary->rodata_size &&
6269 (processor == PIPE_SHADER_VERTEX ||
6270 processor == PIPE_SHADER_TESS_CTRL ||
6271 processor == PIPE_SHADER_TESS_EVAL ||
6272 processor == PIPE_SHADER_FRAGMENT)) {
6273 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6274 return -EINVAL;
6275 }
6276
6277 return r;
6278 }
6279
6280 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6281 {
6282 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6283 LLVMBuildRetVoid(ctx->gallivm.builder);
6284 else
6285 LLVMBuildRet(ctx->gallivm.builder, ret);
6286 }
6287
6288 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6289 struct si_shader *
6290 si_generate_gs_copy_shader(struct si_screen *sscreen,
6291 LLVMTargetMachineRef tm,
6292 struct si_shader_selector *gs_selector,
6293 struct pipe_debug_callback *debug)
6294 {
6295 struct si_shader_context ctx;
6296 struct si_shader *shader;
6297 struct gallivm_state *gallivm = &ctx.gallivm;
6298 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6299 struct lp_build_context *uint = &bld_base->uint_bld;
6300 struct si_shader_output_values *outputs;
6301 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6302 LLVMValueRef args[9];
6303 int i, r;
6304
6305 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6306
6307 if (!outputs)
6308 return NULL;
6309
6310 shader = CALLOC_STRUCT(si_shader);
6311 if (!shader) {
6312 FREE(outputs);
6313 return NULL;
6314 }
6315
6316
6317 shader->selector = gs_selector;
6318 shader->is_gs_copy_shader = true;
6319
6320 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6321 ctx.type = PIPE_SHADER_VERTEX;
6322
6323 create_meta_data(&ctx);
6324 create_function(&ctx);
6325 preload_ring_buffers(&ctx);
6326
6327 args[0] = ctx.gsvs_ring[0];
6328 args[1] = lp_build_mul_imm(uint,
6329 LLVMGetParam(ctx.main_fn,
6330 ctx.param_vertex_id),
6331 4);
6332 args[3] = uint->zero;
6333 args[4] = uint->one; /* OFFEN */
6334 args[5] = uint->zero; /* IDXEN */
6335 args[6] = uint->one; /* GLC */
6336 args[7] = uint->one; /* SLC */
6337 args[8] = uint->zero; /* TFE */
6338
6339 /* Fetch vertex data from GSVS ring */
6340 for (i = 0; i < gsinfo->num_outputs; ++i) {
6341 unsigned chan;
6342
6343 outputs[i].name = gsinfo->output_semantic_name[i];
6344 outputs[i].sid = gsinfo->output_semantic_index[i];
6345
6346 for (chan = 0; chan < 4; chan++) {
6347 args[2] = lp_build_const_int32(gallivm,
6348 (i * 4 + chan) *
6349 gs_selector->gs_max_out_vertices * 16 * 4);
6350
6351 outputs[i].values[chan] =
6352 LLVMBuildBitCast(gallivm->builder,
6353 lp_build_intrinsic(gallivm->builder,
6354 "llvm.SI.buffer.load.dword.i32.i32",
6355 ctx.i32, args, 9,
6356 LP_FUNC_ATTR_READONLY),
6357 ctx.f32, "");
6358 }
6359 }
6360
6361 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6362
6363 LLVMBuildRetVoid(gallivm->builder);
6364
6365 /* Dump LLVM IR before any optimization passes */
6366 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6367 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6368 LLVMDumpModule(bld_base->base.gallivm->module);
6369
6370 si_llvm_finalize_module(&ctx,
6371 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6372
6373 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6374 &ctx.shader->config, ctx.tm,
6375 bld_base->base.gallivm->module,
6376 debug, PIPE_SHADER_GEOMETRY,
6377 "GS Copy Shader");
6378 if (!r) {
6379 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6380 fprintf(stderr, "GS Copy Shader:\n");
6381 si_shader_dump(sscreen, ctx.shader, debug,
6382 PIPE_SHADER_GEOMETRY, stderr);
6383 r = si_shader_binary_upload(sscreen, ctx.shader);
6384 }
6385
6386 si_llvm_dispose(&ctx);
6387
6388 FREE(outputs);
6389
6390 if (r != 0) {
6391 FREE(shader);
6392 shader = NULL;
6393 }
6394 return shader;
6395 }
6396
6397 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6398 FILE *f)
6399 {
6400 int i;
6401
6402 fprintf(f, "SHADER KEY\n");
6403
6404 switch (shader) {
6405 case PIPE_SHADER_VERTEX:
6406 fprintf(f, " part.vs.prolog.instance_divisors = {");
6407 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6408 fprintf(f, !i ? "%u" : ", %u",
6409 key->part.vs.prolog.instance_divisors[i]);
6410 fprintf(f, "}\n");
6411 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6412 fprintf(f, " as_es = %u\n", key->as_es);
6413 fprintf(f, " as_ls = %u\n", key->as_ls);
6414 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6415 break;
6416
6417 case PIPE_SHADER_TESS_CTRL:
6418 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6419 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6420 break;
6421
6422 case PIPE_SHADER_TESS_EVAL:
6423 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6424 fprintf(f, " as_es = %u\n", key->as_es);
6425 break;
6426
6427 case PIPE_SHADER_GEOMETRY:
6428 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6429 break;
6430
6431 case PIPE_SHADER_COMPUTE:
6432 break;
6433
6434 case PIPE_SHADER_FRAGMENT:
6435 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6436 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6437 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6438 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6439 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6440 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6441 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6442 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6443 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6444 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6445 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6446 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6447 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6448 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6449 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6450 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6451 break;
6452
6453 default:
6454 assert(0);
6455 }
6456
6457 if ((shader == PIPE_SHADER_GEOMETRY ||
6458 shader == PIPE_SHADER_TESS_EVAL ||
6459 shader == PIPE_SHADER_VERTEX) &&
6460 !key->as_es && !key->as_ls) {
6461 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6462 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6463 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6464 }
6465 }
6466
6467 static void si_init_shader_ctx(struct si_shader_context *ctx,
6468 struct si_screen *sscreen,
6469 struct si_shader *shader,
6470 LLVMTargetMachineRef tm)
6471 {
6472 struct lp_build_tgsi_context *bld_base;
6473 struct lp_build_tgsi_action tmpl = {};
6474
6475 si_llvm_context_init(ctx, sscreen, shader, tm,
6476 (shader && shader->selector) ? &shader->selector->info : NULL,
6477 (shader && shader->selector) ? shader->selector->tokens : NULL);
6478
6479 bld_base = &ctx->soa.bld_base;
6480 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6481
6482 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6483 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6484 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6485
6486 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6487 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6488 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6489 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6490 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6491 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6492 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6493 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6494 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6495 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6496 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6497 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6498 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6499 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6500
6501 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6502 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6503 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6504 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6505 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6506 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6507
6508 tmpl.fetch_args = atomic_fetch_args;
6509 tmpl.emit = atomic_emit;
6510 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6511 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6512 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6513 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6514 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6515 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6516 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6517 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6518 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6519 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6520 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6521 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6522 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6523 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6524 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6525 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6526 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6527 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6528 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6529 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6530
6531 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6532
6533 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6534 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6535 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6536 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6537
6538 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6539 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6540 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6541 }
6542
6543 /* Return true if the PARAM export has been eliminated. */
6544 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6545 LLVMValueRef inst, unsigned offset)
6546 {
6547 struct si_shader *shader = ctx->shader;
6548 unsigned num_outputs = shader->selector->info.num_outputs;
6549 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6550 bool is_zero[4] = {}, is_one[4] = {};
6551
6552 for (i = 0; i < 4; i++) {
6553 LLVMBool loses_info;
6554 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6555
6556 /* It's a constant expression. Undef outputs are eliminated too. */
6557 if (LLVMIsUndef(p)) {
6558 is_zero[i] = true;
6559 is_one[i] = true;
6560 } else if (LLVMIsAConstantFP(p)) {
6561 double a = LLVMConstRealGetDouble(p, &loses_info);
6562
6563 if (a == 0)
6564 is_zero[i] = true;
6565 else if (a == 1)
6566 is_one[i] = true;
6567 else
6568 return false; /* other constant */
6569 } else
6570 return false;
6571 }
6572
6573 /* Only certain combinations of 0 and 1 can be eliminated. */
6574 if (is_zero[0] && is_zero[1] && is_zero[2])
6575 default_val = is_zero[3] ? 0 : 1;
6576 else if (is_one[0] && is_one[1] && is_one[2])
6577 default_val = is_zero[3] ? 2 : 3;
6578 else
6579 return false;
6580
6581 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6582 LLVMInstructionEraseFromParent(inst);
6583
6584 /* Change OFFSET to DEFAULT_VAL. */
6585 for (i = 0; i < num_outputs; i++) {
6586 if (shader->info.vs_output_param_offset[i] == offset) {
6587 shader->info.vs_output_param_offset[i] =
6588 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6589 break;
6590 }
6591 }
6592 return true;
6593 }
6594
6595 struct si_vs_exports {
6596 unsigned num;
6597 unsigned offset[SI_MAX_VS_OUTPUTS];
6598 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6599 };
6600
6601 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6602 {
6603 struct si_shader *shader = ctx->shader;
6604 struct tgsi_shader_info *info = &shader->selector->info;
6605 LLVMBasicBlockRef bb;
6606 struct si_vs_exports exports;
6607 bool removed_any = false;
6608
6609 exports.num = 0;
6610
6611 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6612 ctx->type == PIPE_SHADER_COMPUTE ||
6613 shader->key.as_es ||
6614 shader->key.as_ls)
6615 return;
6616
6617 /* Process all LLVM instructions. */
6618 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6619 while (bb) {
6620 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6621
6622 while (inst) {
6623 LLVMValueRef cur = inst;
6624 inst = LLVMGetNextInstruction(inst);
6625
6626 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6627 continue;
6628
6629 LLVMValueRef callee = lp_get_called_value(cur);
6630
6631 if (!lp_is_function(callee))
6632 continue;
6633
6634 const char *name = LLVMGetValueName(callee);
6635 unsigned num_args = LLVMCountParams(callee);
6636
6637 /* Check if this is an export instruction. */
6638 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6639 continue;
6640
6641 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6642 unsigned target = LLVMConstIntGetZExtValue(arg);
6643
6644 if (target < V_008DFC_SQ_EXP_PARAM)
6645 continue;
6646
6647 target -= V_008DFC_SQ_EXP_PARAM;
6648
6649 /* Eliminate constant value PARAM exports. */
6650 if (si_eliminate_const_output(ctx, cur, target)) {
6651 removed_any = true;
6652 } else {
6653 exports.offset[exports.num] = target;
6654 exports.inst[exports.num] = cur;
6655 exports.num++;
6656 }
6657 }
6658 bb = LLVMGetNextBasicBlock(bb);
6659 }
6660
6661 /* Remove holes in export memory due to removed PARAM exports.
6662 * This is done by renumbering all PARAM exports.
6663 */
6664 if (removed_any) {
6665 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6666 unsigned new_count = 0;
6667 unsigned out, i;
6668
6669 /* Make a copy of the offsets. We need the old version while
6670 * we are modifying some of them. */
6671 assert(sizeof(current_offset) ==
6672 sizeof(shader->info.vs_output_param_offset));
6673 memcpy(current_offset, shader->info.vs_output_param_offset,
6674 sizeof(current_offset));
6675
6676 for (i = 0; i < exports.num; i++) {
6677 unsigned offset = exports.offset[i];
6678
6679 for (out = 0; out < info->num_outputs; out++) {
6680 if (current_offset[out] != offset)
6681 continue;
6682
6683 LLVMSetOperand(exports.inst[i], 3,
6684 LLVMConstInt(ctx->i32,
6685 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6686 shader->info.vs_output_param_offset[out] = new_count;
6687 new_count++;
6688 break;
6689 }
6690 }
6691 shader->info.nr_param_exports = new_count;
6692 }
6693 }
6694
6695 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6696 {
6697 ctx->shader->config.private_mem_vgprs = 0;
6698
6699 /* Process all LLVM instructions. */
6700 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6701 while (bb) {
6702 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6703
6704 while (next) {
6705 LLVMValueRef inst = next;
6706 next = LLVMGetNextInstruction(next);
6707
6708 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6709 continue;
6710
6711 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6712 /* No idea why LLVM aligns allocas to 4 elements. */
6713 unsigned alignment = LLVMGetAlignment(inst);
6714 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6715 ctx->shader->config.private_mem_vgprs += dw_size;
6716 }
6717 bb = LLVMGetNextBasicBlock(bb);
6718 }
6719 }
6720
6721 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6722 struct si_shader *shader)
6723 {
6724 struct si_shader_selector *sel = shader->selector;
6725 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6726
6727 switch (ctx->type) {
6728 case PIPE_SHADER_VERTEX:
6729 ctx->load_input = declare_input_vs;
6730 if (shader->key.as_ls)
6731 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6732 else if (shader->key.as_es)
6733 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6734 else
6735 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6736 break;
6737 case PIPE_SHADER_TESS_CTRL:
6738 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6739 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6740 bld_base->emit_store = store_output_tcs;
6741 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6742 break;
6743 case PIPE_SHADER_TESS_EVAL:
6744 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6745 if (shader->key.as_es)
6746 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6747 else
6748 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6749 break;
6750 case PIPE_SHADER_GEOMETRY:
6751 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6752 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6753 break;
6754 case PIPE_SHADER_FRAGMENT:
6755 ctx->load_input = declare_input_fs;
6756 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6757 break;
6758 case PIPE_SHADER_COMPUTE:
6759 ctx->declare_memory_region = declare_compute_memory;
6760 break;
6761 default:
6762 assert(!"Unsupported shader type");
6763 return false;
6764 }
6765
6766 create_meta_data(ctx);
6767 create_function(ctx);
6768 preload_ring_buffers(ctx);
6769
6770 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6771 int i;
6772 for (i = 0; i < 4; i++) {
6773 ctx->gs_next_vertex[i] =
6774 lp_build_alloca(bld_base->base.gallivm,
6775 ctx->i32, "");
6776 }
6777 }
6778
6779 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6780 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6781 return false;
6782 }
6783
6784 si_llvm_build_ret(ctx, ctx->return_value);
6785 return true;
6786 }
6787
6788 /**
6789 * Compute the VS prolog key, which contains all the information needed to
6790 * build the VS prolog function, and set shader->info bits where needed.
6791 */
6792 static void si_get_vs_prolog_key(struct si_shader *shader,
6793 union si_shader_part_key *key)
6794 {
6795 struct tgsi_shader_info *info = &shader->selector->info;
6796
6797 memset(key, 0, sizeof(*key));
6798 key->vs_prolog.states = shader->key.part.vs.prolog;
6799 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6800 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6801
6802 /* Set the instanceID flag. */
6803 for (unsigned i = 0; i < info->num_inputs; i++)
6804 if (key->vs_prolog.states.instance_divisors[i])
6805 shader->info.uses_instanceid = true;
6806 }
6807
6808 /**
6809 * Compute the VS epilog key, which contains all the information needed to
6810 * build the VS epilog function, and set the PrimitiveID output offset.
6811 */
6812 static void si_get_vs_epilog_key(struct si_shader *shader,
6813 struct si_vs_epilog_bits *states,
6814 union si_shader_part_key *key)
6815 {
6816 memset(key, 0, sizeof(*key));
6817 key->vs_epilog.states = *states;
6818
6819 /* Set up the PrimitiveID output. */
6820 if (shader->key.part.vs.epilog.export_prim_id) {
6821 unsigned index = shader->selector->info.num_outputs;
6822 unsigned offset = shader->info.nr_param_exports++;
6823
6824 key->vs_epilog.prim_id_param_offset = offset;
6825 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6826 shader->info.vs_output_param_offset[index] = offset;
6827 }
6828 }
6829
6830 /**
6831 * Compute the PS prolog key, which contains all the information needed to
6832 * build the PS prolog function, and set related bits in shader->config.
6833 */
6834 static void si_get_ps_prolog_key(struct si_shader *shader,
6835 union si_shader_part_key *key,
6836 bool separate_prolog)
6837 {
6838 struct tgsi_shader_info *info = &shader->selector->info;
6839
6840 memset(key, 0, sizeof(*key));
6841 key->ps_prolog.states = shader->key.part.ps.prolog;
6842 key->ps_prolog.colors_read = info->colors_read;
6843 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6844 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6845 key->ps_prolog.wqm = info->uses_derivatives &&
6846 (key->ps_prolog.colors_read ||
6847 key->ps_prolog.states.force_persp_sample_interp ||
6848 key->ps_prolog.states.force_linear_sample_interp ||
6849 key->ps_prolog.states.force_persp_center_interp ||
6850 key->ps_prolog.states.force_linear_center_interp ||
6851 key->ps_prolog.states.bc_optimize_for_persp ||
6852 key->ps_prolog.states.bc_optimize_for_linear);
6853
6854 if (info->colors_read) {
6855 unsigned *color = shader->selector->color_attr_index;
6856
6857 if (shader->key.part.ps.prolog.color_two_side) {
6858 /* BCOLORs are stored after the last input. */
6859 key->ps_prolog.num_interp_inputs = info->num_inputs;
6860 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6861 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6862 }
6863
6864 for (unsigned i = 0; i < 2; i++) {
6865 unsigned interp = info->input_interpolate[color[i]];
6866 unsigned location = info->input_interpolate_loc[color[i]];
6867
6868 if (!(info->colors_read & (0xf << i*4)))
6869 continue;
6870
6871 key->ps_prolog.color_attr_index[i] = color[i];
6872
6873 if (shader->key.part.ps.prolog.flatshade_colors &&
6874 interp == TGSI_INTERPOLATE_COLOR)
6875 interp = TGSI_INTERPOLATE_CONSTANT;
6876
6877 switch (interp) {
6878 case TGSI_INTERPOLATE_CONSTANT:
6879 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6880 break;
6881 case TGSI_INTERPOLATE_PERSPECTIVE:
6882 case TGSI_INTERPOLATE_COLOR:
6883 /* Force the interpolation location for colors here. */
6884 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6885 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6886 if (shader->key.part.ps.prolog.force_persp_center_interp)
6887 location = TGSI_INTERPOLATE_LOC_CENTER;
6888
6889 switch (location) {
6890 case TGSI_INTERPOLATE_LOC_SAMPLE:
6891 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6892 shader->config.spi_ps_input_ena |=
6893 S_0286CC_PERSP_SAMPLE_ENA(1);
6894 break;
6895 case TGSI_INTERPOLATE_LOC_CENTER:
6896 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6897 shader->config.spi_ps_input_ena |=
6898 S_0286CC_PERSP_CENTER_ENA(1);
6899 break;
6900 case TGSI_INTERPOLATE_LOC_CENTROID:
6901 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6902 shader->config.spi_ps_input_ena |=
6903 S_0286CC_PERSP_CENTROID_ENA(1);
6904 break;
6905 default:
6906 assert(0);
6907 }
6908 break;
6909 case TGSI_INTERPOLATE_LINEAR:
6910 /* Force the interpolation location for colors here. */
6911 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6912 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6913 if (shader->key.part.ps.prolog.force_linear_center_interp)
6914 location = TGSI_INTERPOLATE_LOC_CENTER;
6915
6916 /* The VGPR assignment for non-monolithic shaders
6917 * works because InitialPSInputAddr is set on the
6918 * main shader and PERSP_PULL_MODEL is never used.
6919 */
6920 switch (location) {
6921 case TGSI_INTERPOLATE_LOC_SAMPLE:
6922 key->ps_prolog.color_interp_vgpr_index[i] =
6923 separate_prolog ? 6 : 9;
6924 shader->config.spi_ps_input_ena |=
6925 S_0286CC_LINEAR_SAMPLE_ENA(1);
6926 break;
6927 case TGSI_INTERPOLATE_LOC_CENTER:
6928 key->ps_prolog.color_interp_vgpr_index[i] =
6929 separate_prolog ? 8 : 11;
6930 shader->config.spi_ps_input_ena |=
6931 S_0286CC_LINEAR_CENTER_ENA(1);
6932 break;
6933 case TGSI_INTERPOLATE_LOC_CENTROID:
6934 key->ps_prolog.color_interp_vgpr_index[i] =
6935 separate_prolog ? 10 : 13;
6936 shader->config.spi_ps_input_ena |=
6937 S_0286CC_LINEAR_CENTROID_ENA(1);
6938 break;
6939 default:
6940 assert(0);
6941 }
6942 break;
6943 default:
6944 assert(0);
6945 }
6946 }
6947 }
6948 }
6949
6950 /**
6951 * Check whether a PS prolog is required based on the key.
6952 */
6953 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6954 {
6955 return key->ps_prolog.colors_read ||
6956 key->ps_prolog.states.force_persp_sample_interp ||
6957 key->ps_prolog.states.force_linear_sample_interp ||
6958 key->ps_prolog.states.force_persp_center_interp ||
6959 key->ps_prolog.states.force_linear_center_interp ||
6960 key->ps_prolog.states.bc_optimize_for_persp ||
6961 key->ps_prolog.states.bc_optimize_for_linear ||
6962 key->ps_prolog.states.poly_stipple;
6963 }
6964
6965 /**
6966 * Compute the PS epilog key, which contains all the information needed to
6967 * build the PS epilog function.
6968 */
6969 static void si_get_ps_epilog_key(struct si_shader *shader,
6970 union si_shader_part_key *key)
6971 {
6972 struct tgsi_shader_info *info = &shader->selector->info;
6973 memset(key, 0, sizeof(*key));
6974 key->ps_epilog.colors_written = info->colors_written;
6975 key->ps_epilog.writes_z = info->writes_z;
6976 key->ps_epilog.writes_stencil = info->writes_stencil;
6977 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6978 key->ps_epilog.states = shader->key.part.ps.epilog;
6979 }
6980
6981 /**
6982 * Build the GS prolog function. Rotate the input vertices for triangle strips
6983 * with adjacency.
6984 */
6985 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6986 union si_shader_part_key *key)
6987 {
6988 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6989 const unsigned num_vgprs = 8;
6990 struct gallivm_state *gallivm = &ctx->gallivm;
6991 LLVMBuilderRef builder = gallivm->builder;
6992 LLVMTypeRef params[32];
6993 LLVMTypeRef returns[32];
6994 LLVMValueRef func, ret;
6995
6996 for (unsigned i = 0; i < num_sgprs; ++i) {
6997 params[i] = ctx->i32;
6998 returns[i] = ctx->i32;
6999 }
7000
7001 for (unsigned i = 0; i < num_vgprs; ++i) {
7002 params[num_sgprs + i] = ctx->i32;
7003 returns[num_sgprs + i] = ctx->f32;
7004 }
7005
7006 /* Create the function. */
7007 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7008 params, num_sgprs + num_vgprs, num_sgprs - 1);
7009 func = ctx->main_fn;
7010
7011 /* Copy inputs to outputs. This should be no-op, as the registers match,
7012 * but it will prevent the compiler from overwriting them unintentionally.
7013 */
7014 ret = ctx->return_value;
7015 for (unsigned i = 0; i < num_sgprs; i++) {
7016 LLVMValueRef p = LLVMGetParam(func, i);
7017 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7018 }
7019 for (unsigned i = 0; i < num_vgprs; i++) {
7020 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7021 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7022 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7023 }
7024
7025 if (key->gs_prolog.states.tri_strip_adj_fix) {
7026 /* Remap the input vertices for every other primitive. */
7027 const unsigned vtx_params[6] = {
7028 num_sgprs,
7029 num_sgprs + 1,
7030 num_sgprs + 3,
7031 num_sgprs + 4,
7032 num_sgprs + 5,
7033 num_sgprs + 6
7034 };
7035 LLVMValueRef prim_id, rotate;
7036
7037 prim_id = LLVMGetParam(func, num_sgprs + 2);
7038 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7039
7040 for (unsigned i = 0; i < 6; ++i) {
7041 LLVMValueRef base, rotated, actual;
7042 base = LLVMGetParam(func, vtx_params[i]);
7043 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7044 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7045 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7046 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7047 }
7048 }
7049
7050 LLVMBuildRet(builder, ret);
7051 }
7052
7053 /**
7054 * Given a list of shader part functions, build a wrapper function that
7055 * runs them in sequence to form a monolithic shader.
7056 */
7057 static void si_build_wrapper_function(struct si_shader_context *ctx,
7058 LLVMValueRef *parts,
7059 unsigned num_parts,
7060 unsigned main_part)
7061 {
7062 struct gallivm_state *gallivm = &ctx->gallivm;
7063 LLVMBuilderRef builder = ctx->gallivm.builder;
7064 /* PS epilog has one arg per color component */
7065 LLVMTypeRef param_types[48];
7066 LLVMValueRef out[48];
7067 LLVMTypeRef function_type;
7068 unsigned num_params;
7069 unsigned num_out;
7070 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7071 unsigned num_sgprs, num_vgprs;
7072 unsigned last_sgpr_param;
7073 unsigned gprs;
7074
7075 for (unsigned i = 0; i < num_parts; ++i) {
7076 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7077 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7078 }
7079
7080 /* The parameters of the wrapper function correspond to those of the
7081 * first part in terms of SGPRs and VGPRs, but we use the types of the
7082 * main part to get the right types. This is relevant for the
7083 * dereferenceable attribute on descriptor table pointers.
7084 */
7085 num_sgprs = 0;
7086 num_vgprs = 0;
7087
7088 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7089 num_params = LLVMCountParamTypes(function_type);
7090
7091 for (unsigned i = 0; i < num_params; ++i) {
7092 LLVMValueRef param = LLVMGetParam(parts[0], i);
7093
7094 if (ac_is_sgpr_param(param)) {
7095 assert(num_vgprs == 0);
7096 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7097 } else {
7098 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7099 }
7100 }
7101 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7102
7103 num_params = 0;
7104 last_sgpr_param = 0;
7105 gprs = 0;
7106 while (gprs < num_sgprs + num_vgprs) {
7107 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7108 unsigned size;
7109
7110 param_types[num_params] = LLVMTypeOf(param);
7111 if (gprs < num_sgprs)
7112 last_sgpr_param = num_params;
7113 size = llvm_get_type_size(param_types[num_params]) / 4;
7114 num_params++;
7115
7116 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7117 assert(gprs + size <= num_sgprs + num_vgprs &&
7118 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7119
7120 gprs += size;
7121 }
7122
7123 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7124
7125 /* Record the arguments of the function as if they were an output of
7126 * a previous part.
7127 */
7128 num_out = 0;
7129 num_out_sgpr = 0;
7130
7131 for (unsigned i = 0; i < num_params; ++i) {
7132 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7133 LLVMTypeRef param_type = LLVMTypeOf(param);
7134 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7135 unsigned size = llvm_get_type_size(param_type) / 4;
7136
7137 if (size == 1) {
7138 if (param_type != out_type)
7139 param = LLVMBuildBitCast(builder, param, out_type, "");
7140 out[num_out++] = param;
7141 } else {
7142 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7143
7144 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7145 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7146 param_type = ctx->i64;
7147 }
7148
7149 if (param_type != vector_type)
7150 param = LLVMBuildBitCast(builder, param, vector_type, "");
7151
7152 for (unsigned j = 0; j < size; ++j)
7153 out[num_out++] = LLVMBuildExtractElement(
7154 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7155 }
7156
7157 if (i <= last_sgpr_param)
7158 num_out_sgpr = num_out;
7159 }
7160
7161 /* Now chain the parts. */
7162 for (unsigned part = 0; part < num_parts; ++part) {
7163 LLVMValueRef in[48];
7164 LLVMValueRef ret;
7165 LLVMTypeRef ret_type;
7166 unsigned out_idx = 0;
7167
7168 num_params = LLVMCountParams(parts[part]);
7169 assert(num_params <= ARRAY_SIZE(param_types));
7170
7171 /* Derive arguments for the next part from outputs of the
7172 * previous one.
7173 */
7174 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7175 LLVMValueRef param;
7176 LLVMTypeRef param_type;
7177 bool is_sgpr;
7178 unsigned param_size;
7179 LLVMValueRef arg = NULL;
7180
7181 param = LLVMGetParam(parts[part], param_idx);
7182 param_type = LLVMTypeOf(param);
7183 param_size = llvm_get_type_size(param_type) / 4;
7184 is_sgpr = ac_is_sgpr_param(param);
7185
7186 if (is_sgpr) {
7187 #if HAVE_LLVM < 0x0400
7188 LLVMRemoveAttribute(param, LLVMByValAttribute);
7189 #else
7190 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7191 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7192 #endif
7193 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7194 }
7195
7196 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7197 assert(is_sgpr || out_idx >= num_out_sgpr);
7198
7199 if (param_size == 1)
7200 arg = out[out_idx];
7201 else
7202 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7203
7204 if (LLVMTypeOf(arg) != param_type) {
7205 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7206 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7207 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7208 } else {
7209 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7210 }
7211 }
7212
7213 in[param_idx] = arg;
7214 out_idx += param_size;
7215 }
7216
7217 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7218 ret_type = LLVMTypeOf(ret);
7219
7220 /* Extract the returned GPRs. */
7221 num_out = 0;
7222 num_out_sgpr = 0;
7223
7224 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7225 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7226
7227 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7228
7229 for (unsigned i = 0; i < ret_size; ++i) {
7230 LLVMValueRef val =
7231 LLVMBuildExtractValue(builder, ret, i, "");
7232
7233 out[num_out++] = val;
7234
7235 if (LLVMTypeOf(val) == ctx->i32) {
7236 assert(num_out_sgpr + 1 == num_out);
7237 num_out_sgpr = num_out;
7238 }
7239 }
7240 }
7241 }
7242
7243 LLVMBuildRetVoid(builder);
7244 }
7245
7246 int si_compile_tgsi_shader(struct si_screen *sscreen,
7247 LLVMTargetMachineRef tm,
7248 struct si_shader *shader,
7249 bool is_monolithic,
7250 struct pipe_debug_callback *debug)
7251 {
7252 struct si_shader_selector *sel = shader->selector;
7253 struct si_shader_context ctx;
7254 struct lp_build_tgsi_context *bld_base;
7255 LLVMModuleRef mod;
7256 int r = -1;
7257
7258 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7259 * conversion fails. */
7260 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7261 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7262 tgsi_dump(sel->tokens, 0);
7263 si_dump_streamout(&sel->so);
7264 }
7265
7266 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7267 ctx.separate_prolog = !is_monolithic;
7268
7269 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7270 sizeof(shader->info.vs_output_param_offset));
7271
7272 shader->info.uses_instanceid = sel->info.uses_instanceid;
7273
7274 bld_base = &ctx.soa.bld_base;
7275 ctx.load_system_value = declare_system_value;
7276
7277 if (!si_compile_tgsi_main(&ctx, shader)) {
7278 si_llvm_dispose(&ctx);
7279 return -1;
7280 }
7281
7282 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7283 LLVMValueRef parts[3];
7284 bool need_prolog;
7285 bool need_epilog;
7286
7287 need_prolog = sel->info.num_inputs;
7288 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7289
7290 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7291
7292 if (need_prolog) {
7293 union si_shader_part_key prolog_key;
7294 si_get_vs_prolog_key(shader, &prolog_key);
7295 si_build_vs_prolog_function(&ctx, &prolog_key);
7296 parts[0] = ctx.main_fn;
7297 }
7298
7299 if (need_epilog) {
7300 union si_shader_part_key epilog_key;
7301 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7302 si_build_vs_epilog_function(&ctx, &epilog_key);
7303 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7304 }
7305
7306 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7307 need_prolog ? 1 : 0);
7308 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7309 LLVMValueRef parts[2];
7310 union si_shader_part_key epilog_key;
7311
7312 parts[0] = ctx.main_fn;
7313
7314 memset(&epilog_key, 0, sizeof(epilog_key));
7315 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7316 si_build_tcs_epilog_function(&ctx, &epilog_key);
7317 parts[1] = ctx.main_fn;
7318
7319 si_build_wrapper_function(&ctx, parts, 2, 0);
7320 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7321 !shader->key.as_es) {
7322 LLVMValueRef parts[2];
7323 union si_shader_part_key epilog_key;
7324
7325 parts[0] = ctx.main_fn;
7326
7327 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7328 si_build_vs_epilog_function(&ctx, &epilog_key);
7329 parts[1] = ctx.main_fn;
7330
7331 si_build_wrapper_function(&ctx, parts, 2, 0);
7332 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7333 LLVMValueRef parts[2];
7334 union si_shader_part_key prolog_key;
7335
7336 parts[1] = ctx.main_fn;
7337
7338 memset(&prolog_key, 0, sizeof(prolog_key));
7339 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7340 si_build_gs_prolog_function(&ctx, &prolog_key);
7341 parts[0] = ctx.main_fn;
7342
7343 si_build_wrapper_function(&ctx, parts, 2, 1);
7344 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7345 LLVMValueRef parts[3];
7346 union si_shader_part_key prolog_key;
7347 union si_shader_part_key epilog_key;
7348 bool need_prolog;
7349
7350 si_get_ps_prolog_key(shader, &prolog_key, false);
7351 need_prolog = si_need_ps_prolog(&prolog_key);
7352
7353 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7354
7355 if (need_prolog) {
7356 si_build_ps_prolog_function(&ctx, &prolog_key);
7357 parts[0] = ctx.main_fn;
7358 }
7359
7360 si_get_ps_epilog_key(shader, &epilog_key);
7361 si_build_ps_epilog_function(&ctx, &epilog_key);
7362 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7363
7364 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7365 }
7366
7367 mod = bld_base->base.gallivm->module;
7368
7369 /* Dump LLVM IR before any optimization passes */
7370 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7371 r600_can_dump_shader(&sscreen->b, ctx.type))
7372 LLVMDumpModule(mod);
7373
7374 si_llvm_finalize_module(&ctx,
7375 r600_extra_shader_checks(&sscreen->b, ctx.type));
7376
7377 /* Post-optimization transformations and analysis. */
7378 si_eliminate_const_vs_outputs(&ctx);
7379
7380 if ((debug && debug->debug_message) ||
7381 r600_can_dump_shader(&sscreen->b, ctx.type))
7382 si_count_scratch_private_memory(&ctx);
7383
7384 /* Compile to bytecode. */
7385 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7386 mod, debug, ctx.type, "TGSI shader");
7387 si_llvm_dispose(&ctx);
7388 if (r) {
7389 fprintf(stderr, "LLVM failed to compile shader\n");
7390 return r;
7391 }
7392
7393 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7394 * LLVM 3.9svn has this bug.
7395 */
7396 if (sel->type == PIPE_SHADER_COMPUTE) {
7397 unsigned wave_size = 64;
7398 unsigned max_vgprs = 256;
7399 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7400 unsigned max_sgprs_per_wave = 128;
7401 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7402 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7403 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7404
7405 max_vgprs = max_vgprs / min_waves_per_simd;
7406 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7407
7408 if (shader->config.num_sgprs > max_sgprs ||
7409 shader->config.num_vgprs > max_vgprs) {
7410 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7411 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7412 shader->config.num_sgprs, shader->config.num_vgprs,
7413 max_sgprs, max_vgprs);
7414
7415 /* Just terminate the process, because dependent
7416 * shaders can hang due to bad input data, but use
7417 * the env var to allow shader-db to work.
7418 */
7419 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7420 abort();
7421 }
7422 }
7423
7424 /* Add the scratch offset to input SGPRs. */
7425 if (shader->config.scratch_bytes_per_wave)
7426 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7427
7428 /* Calculate the number of fragment input VGPRs. */
7429 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7430 shader->info.num_input_vgprs = 0;
7431 shader->info.face_vgpr_index = -1;
7432
7433 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7434 shader->info.num_input_vgprs += 2;
7435 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7436 shader->info.num_input_vgprs += 2;
7437 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7438 shader->info.num_input_vgprs += 2;
7439 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7440 shader->info.num_input_vgprs += 3;
7441 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7442 shader->info.num_input_vgprs += 2;
7443 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7444 shader->info.num_input_vgprs += 2;
7445 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7446 shader->info.num_input_vgprs += 2;
7447 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7448 shader->info.num_input_vgprs += 1;
7449 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7450 shader->info.num_input_vgprs += 1;
7451 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7452 shader->info.num_input_vgprs += 1;
7453 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7454 shader->info.num_input_vgprs += 1;
7455 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7456 shader->info.num_input_vgprs += 1;
7457 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7458 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7459 shader->info.num_input_vgprs += 1;
7460 }
7461 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7462 shader->info.num_input_vgprs += 1;
7463 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7464 shader->info.num_input_vgprs += 1;
7465 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7466 shader->info.num_input_vgprs += 1;
7467 }
7468
7469 return 0;
7470 }
7471
7472 /**
7473 * Create, compile and return a shader part (prolog or epilog).
7474 *
7475 * \param sscreen screen
7476 * \param list list of shader parts of the same category
7477 * \param type shader type
7478 * \param key shader part key
7479 * \param prolog whether the part being requested is a prolog
7480 * \param tm LLVM target machine
7481 * \param debug debug callback
7482 * \param build the callback responsible for building the main function
7483 * \return non-NULL on success
7484 */
7485 static struct si_shader_part *
7486 si_get_shader_part(struct si_screen *sscreen,
7487 struct si_shader_part **list,
7488 enum pipe_shader_type type,
7489 bool prolog,
7490 union si_shader_part_key *key,
7491 LLVMTargetMachineRef tm,
7492 struct pipe_debug_callback *debug,
7493 void (*build)(struct si_shader_context *,
7494 union si_shader_part_key *),
7495 const char *name)
7496 {
7497 struct si_shader_part *result;
7498
7499 pipe_mutex_lock(sscreen->shader_parts_mutex);
7500
7501 /* Find existing. */
7502 for (result = *list; result; result = result->next) {
7503 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7504 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7505 return result;
7506 }
7507 }
7508
7509 /* Compile a new one. */
7510 result = CALLOC_STRUCT(si_shader_part);
7511 result->key = *key;
7512
7513 struct si_shader shader = {};
7514 struct si_shader_context ctx;
7515 struct gallivm_state *gallivm = &ctx.gallivm;
7516
7517 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7518 ctx.type = type;
7519
7520 switch (type) {
7521 case PIPE_SHADER_VERTEX:
7522 break;
7523 case PIPE_SHADER_TESS_CTRL:
7524 assert(!prolog);
7525 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7526 break;
7527 case PIPE_SHADER_GEOMETRY:
7528 assert(prolog);
7529 break;
7530 case PIPE_SHADER_FRAGMENT:
7531 if (prolog)
7532 shader.key.part.ps.prolog = key->ps_prolog.states;
7533 else
7534 shader.key.part.ps.epilog = key->ps_epilog.states;
7535 break;
7536 default:
7537 unreachable("bad shader part");
7538 }
7539
7540 build(&ctx, key);
7541
7542 /* Compile. */
7543 si_llvm_finalize_module(&ctx,
7544 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7545
7546 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7547 gallivm->module, debug, ctx.type, name)) {
7548 FREE(result);
7549 result = NULL;
7550 goto out;
7551 }
7552
7553 result->next = *list;
7554 *list = result;
7555
7556 out:
7557 si_llvm_dispose(&ctx);
7558 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7559 return result;
7560 }
7561
7562 /**
7563 * Build the vertex shader prolog function.
7564 *
7565 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7566 * All inputs are returned unmodified. The vertex load indices are
7567 * stored after them, which will be used by the API VS for fetching inputs.
7568 *
7569 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7570 * input_v0,
7571 * input_v1,
7572 * input_v2,
7573 * input_v3,
7574 * (VertexID + BaseVertex),
7575 * (InstanceID + StartInstance),
7576 * (InstanceID / 2 + StartInstance)
7577 */
7578 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7579 union si_shader_part_key *key)
7580 {
7581 struct gallivm_state *gallivm = &ctx->gallivm;
7582 LLVMTypeRef *params, *returns;
7583 LLVMValueRef ret, func;
7584 int last_sgpr, num_params, num_returns, i;
7585
7586 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7587 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7588
7589 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7590 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7591 sizeof(LLVMTypeRef));
7592 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7593 key->vs_prolog.last_input + 1) *
7594 sizeof(LLVMTypeRef));
7595 num_params = 0;
7596 num_returns = 0;
7597
7598 /* Declare input and output SGPRs. */
7599 num_params = 0;
7600 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7601 params[num_params++] = ctx->i32;
7602 returns[num_returns++] = ctx->i32;
7603 }
7604 last_sgpr = num_params - 1;
7605
7606 /* 4 preloaded VGPRs (outputs must be floats) */
7607 for (i = 0; i < 4; i++) {
7608 params[num_params++] = ctx->i32;
7609 returns[num_returns++] = ctx->f32;
7610 }
7611
7612 /* Vertex load indices. */
7613 for (i = 0; i <= key->vs_prolog.last_input; i++)
7614 returns[num_returns++] = ctx->f32;
7615
7616 /* Create the function. */
7617 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7618 num_params, last_sgpr);
7619 func = ctx->main_fn;
7620
7621 /* Copy inputs to outputs. This should be no-op, as the registers match,
7622 * but it will prevent the compiler from overwriting them unintentionally.
7623 */
7624 ret = ctx->return_value;
7625 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7626 LLVMValueRef p = LLVMGetParam(func, i);
7627 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7628 }
7629 for (i = num_params - 4; i < num_params; i++) {
7630 LLVMValueRef p = LLVMGetParam(func, i);
7631 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7632 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7633 }
7634
7635 /* Compute vertex load indices from instance divisors. */
7636 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7637 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7638 LLVMValueRef index;
7639
7640 if (divisor) {
7641 /* InstanceID / Divisor + StartInstance */
7642 index = get_instance_index_for_fetch(ctx,
7643 SI_SGPR_START_INSTANCE,
7644 divisor);
7645 } else {
7646 /* VertexID + BaseVertex */
7647 index = LLVMBuildAdd(gallivm->builder,
7648 LLVMGetParam(func, ctx->param_vertex_id),
7649 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7650 }
7651
7652 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7653 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7654 num_params++, "");
7655 }
7656
7657 si_llvm_build_ret(ctx, ret);
7658 }
7659
7660 /**
7661 * Build the vertex shader epilog function. This is also used by the tessellation
7662 * evaluation shader compiled as VS.
7663 *
7664 * The input is PrimitiveID.
7665 *
7666 * If PrimitiveID is required by the pixel shader, export it.
7667 * Otherwise, do nothing.
7668 */
7669 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7670 union si_shader_part_key *key)
7671 {
7672 struct gallivm_state *gallivm = &ctx->gallivm;
7673 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7674 LLVMTypeRef params[5];
7675 int num_params, i;
7676
7677 /* Declare input VGPRs. */
7678 num_params = key->vs_epilog.states.export_prim_id ?
7679 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7680 assert(num_params <= ARRAY_SIZE(params));
7681
7682 for (i = 0; i < num_params; i++)
7683 params[i] = ctx->f32;
7684
7685 /* Create the function. */
7686 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7687
7688 /* Emit exports. */
7689 if (key->vs_epilog.states.export_prim_id) {
7690 struct lp_build_context *base = &bld_base->base;
7691 struct lp_build_context *uint = &bld_base->uint_bld;
7692 LLVMValueRef args[9];
7693
7694 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7695 args[1] = uint->zero; /* whether the EXEC mask is valid */
7696 args[2] = uint->zero; /* DONE bit */
7697 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7698 key->vs_epilog.prim_id_param_offset);
7699 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7700 args[5] = LLVMGetParam(ctx->main_fn,
7701 VS_EPILOG_PRIMID_LOC); /* X */
7702 args[6] = base->undef; /* Y */
7703 args[7] = base->undef; /* Z */
7704 args[8] = base->undef; /* W */
7705
7706 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7707 LLVMVoidTypeInContext(base->gallivm->context),
7708 args, 9, 0);
7709 }
7710
7711 LLVMBuildRetVoid(gallivm->builder);
7712 }
7713
7714 /**
7715 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7716 */
7717 static bool si_get_vs_epilog(struct si_screen *sscreen,
7718 LLVMTargetMachineRef tm,
7719 struct si_shader *shader,
7720 struct pipe_debug_callback *debug,
7721 struct si_vs_epilog_bits *states)
7722 {
7723 union si_shader_part_key epilog_key;
7724
7725 si_get_vs_epilog_key(shader, states, &epilog_key);
7726
7727 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7728 PIPE_SHADER_VERTEX, true,
7729 &epilog_key, tm, debug,
7730 si_build_vs_epilog_function,
7731 "Vertex Shader Epilog");
7732 return shader->epilog != NULL;
7733 }
7734
7735 /**
7736 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7737 */
7738 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7739 LLVMTargetMachineRef tm,
7740 struct si_shader *shader,
7741 struct pipe_debug_callback *debug)
7742 {
7743 struct tgsi_shader_info *info = &shader->selector->info;
7744 union si_shader_part_key prolog_key;
7745
7746 /* Get the prolog. */
7747 si_get_vs_prolog_key(shader, &prolog_key);
7748
7749 /* The prolog is a no-op if there are no inputs. */
7750 if (info->num_inputs) {
7751 shader->prolog =
7752 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7753 PIPE_SHADER_VERTEX, true,
7754 &prolog_key, tm, debug,
7755 si_build_vs_prolog_function,
7756 "Vertex Shader Prolog");
7757 if (!shader->prolog)
7758 return false;
7759 }
7760
7761 /* Get the epilog. */
7762 if (!shader->key.as_es && !shader->key.as_ls &&
7763 !si_get_vs_epilog(sscreen, tm, shader, debug,
7764 &shader->key.part.vs.epilog))
7765 return false;
7766
7767 return true;
7768 }
7769
7770 /**
7771 * Select and compile (or reuse) TES parts (epilog).
7772 */
7773 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7774 LLVMTargetMachineRef tm,
7775 struct si_shader *shader,
7776 struct pipe_debug_callback *debug)
7777 {
7778 if (shader->key.as_es)
7779 return true;
7780
7781 /* TES compiled as VS. */
7782 return si_get_vs_epilog(sscreen, tm, shader, debug,
7783 &shader->key.part.tes.epilog);
7784 }
7785
7786 /**
7787 * Compile the TCS epilog function. This writes tesselation factors to memory
7788 * based on the output primitive type of the tesselator (determined by TES).
7789 */
7790 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7791 union si_shader_part_key *key)
7792 {
7793 struct gallivm_state *gallivm = &ctx->gallivm;
7794 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7795 LLVMTypeRef params[16];
7796 LLVMValueRef func;
7797 int last_sgpr, num_params;
7798
7799 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7800 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7801 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7802 params[SI_PARAM_SAMPLERS] = ctx->i64;
7803 params[SI_PARAM_IMAGES] = ctx->i64;
7804 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7805 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7806 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7807 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7808 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7809 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7810 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7811 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7812 num_params = last_sgpr + 1;
7813
7814 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7815 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7816 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7817
7818 /* Create the function. */
7819 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7820 declare_tess_lds(ctx);
7821 func = ctx->main_fn;
7822
7823 si_write_tess_factors(bld_base,
7824 LLVMGetParam(func, last_sgpr + 1),
7825 LLVMGetParam(func, last_sgpr + 2),
7826 LLVMGetParam(func, last_sgpr + 3));
7827
7828 LLVMBuildRetVoid(gallivm->builder);
7829 }
7830
7831 /**
7832 * Select and compile (or reuse) TCS parts (epilog).
7833 */
7834 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7835 LLVMTargetMachineRef tm,
7836 struct si_shader *shader,
7837 struct pipe_debug_callback *debug)
7838 {
7839 union si_shader_part_key epilog_key;
7840
7841 /* Get the epilog. */
7842 memset(&epilog_key, 0, sizeof(epilog_key));
7843 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7844
7845 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7846 PIPE_SHADER_TESS_CTRL, false,
7847 &epilog_key, tm, debug,
7848 si_build_tcs_epilog_function,
7849 "Tessellation Control Shader Epilog");
7850 return shader->epilog != NULL;
7851 }
7852
7853 /**
7854 * Select and compile (or reuse) GS parts (prolog).
7855 */
7856 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7857 LLVMTargetMachineRef tm,
7858 struct si_shader *shader,
7859 struct pipe_debug_callback *debug)
7860 {
7861 union si_shader_part_key prolog_key;
7862
7863 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7864 return true;
7865
7866 memset(&prolog_key, 0, sizeof(prolog_key));
7867 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7868
7869 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7870 PIPE_SHADER_GEOMETRY, true,
7871 &prolog_key, tm, debug,
7872 si_build_gs_prolog_function,
7873 "Geometry Shader Prolog");
7874 return shader->prolog != NULL;
7875 }
7876
7877 /**
7878 * Build the pixel shader prolog function. This handles:
7879 * - two-side color selection and interpolation
7880 * - overriding interpolation parameters for the API PS
7881 * - polygon stippling
7882 *
7883 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7884 * overriden by other states. (e.g. per-sample interpolation)
7885 * Interpolated colors are stored after the preloaded VGPRs.
7886 */
7887 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7888 union si_shader_part_key *key)
7889 {
7890 struct gallivm_state *gallivm = &ctx->gallivm;
7891 LLVMTypeRef *params;
7892 LLVMValueRef ret, func;
7893 int last_sgpr, num_params, num_returns, i, num_color_channels;
7894
7895 assert(si_need_ps_prolog(key));
7896
7897 /* Number of inputs + 8 color elements. */
7898 params = alloca((key->ps_prolog.num_input_sgprs +
7899 key->ps_prolog.num_input_vgprs + 8) *
7900 sizeof(LLVMTypeRef));
7901
7902 /* Declare inputs. */
7903 num_params = 0;
7904 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7905 params[num_params++] = ctx->i32;
7906 last_sgpr = num_params - 1;
7907
7908 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7909 params[num_params++] = ctx->f32;
7910
7911 /* Declare outputs (same as inputs + add colors if needed) */
7912 num_returns = num_params;
7913 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7914 for (i = 0; i < num_color_channels; i++)
7915 params[num_returns++] = ctx->f32;
7916
7917 /* Create the function. */
7918 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7919 num_params, last_sgpr);
7920 func = ctx->main_fn;
7921
7922 /* Copy inputs to outputs. This should be no-op, as the registers match,
7923 * but it will prevent the compiler from overwriting them unintentionally.
7924 */
7925 ret = ctx->return_value;
7926 for (i = 0; i < num_params; i++) {
7927 LLVMValueRef p = LLVMGetParam(func, i);
7928 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7929 }
7930
7931 /* Polygon stippling. */
7932 if (key->ps_prolog.states.poly_stipple) {
7933 /* POS_FIXED_PT is always last. */
7934 unsigned pos = key->ps_prolog.num_input_sgprs +
7935 key->ps_prolog.num_input_vgprs - 1;
7936 LLVMValueRef ptr[2], list;
7937
7938 /* Get the pointer to rw buffers. */
7939 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7940 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7941 list = lp_build_gather_values(gallivm, ptr, 2);
7942 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7943 list = LLVMBuildIntToPtr(gallivm->builder, list,
7944 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7945
7946 si_llvm_emit_polygon_stipple(ctx, list, pos);
7947 }
7948
7949 if (key->ps_prolog.states.bc_optimize_for_persp ||
7950 key->ps_prolog.states.bc_optimize_for_linear) {
7951 unsigned i, base = key->ps_prolog.num_input_sgprs;
7952 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7953
7954 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7955 * The hw doesn't compute CENTROID if the whole wave only
7956 * contains fully-covered quads.
7957 *
7958 * PRIM_MASK is after user SGPRs.
7959 */
7960 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7961 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7962 LLVMConstInt(ctx->i32, 31, 0), "");
7963 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7964 ctx->i1, "");
7965
7966 if (key->ps_prolog.states.bc_optimize_for_persp) {
7967 /* Read PERSP_CENTER. */
7968 for (i = 0; i < 2; i++)
7969 center[i] = LLVMGetParam(func, base + 2 + i);
7970 /* Read PERSP_CENTROID. */
7971 for (i = 0; i < 2; i++)
7972 centroid[i] = LLVMGetParam(func, base + 4 + i);
7973 /* Select PERSP_CENTROID. */
7974 for (i = 0; i < 2; i++) {
7975 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7976 center[i], centroid[i], "");
7977 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7978 tmp, base + 4 + i, "");
7979 }
7980 }
7981 if (key->ps_prolog.states.bc_optimize_for_linear) {
7982 /* Read LINEAR_CENTER. */
7983 for (i = 0; i < 2; i++)
7984 center[i] = LLVMGetParam(func, base + 8 + i);
7985 /* Read LINEAR_CENTROID. */
7986 for (i = 0; i < 2; i++)
7987 centroid[i] = LLVMGetParam(func, base + 10 + i);
7988 /* Select LINEAR_CENTROID. */
7989 for (i = 0; i < 2; i++) {
7990 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7991 center[i], centroid[i], "");
7992 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7993 tmp, base + 10 + i, "");
7994 }
7995 }
7996 }
7997
7998 /* Force per-sample interpolation. */
7999 if (key->ps_prolog.states.force_persp_sample_interp) {
8000 unsigned i, base = key->ps_prolog.num_input_sgprs;
8001 LLVMValueRef persp_sample[2];
8002
8003 /* Read PERSP_SAMPLE. */
8004 for (i = 0; i < 2; i++)
8005 persp_sample[i] = LLVMGetParam(func, base + i);
8006 /* Overwrite PERSP_CENTER. */
8007 for (i = 0; i < 2; i++)
8008 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8009 persp_sample[i], base + 2 + i, "");
8010 /* Overwrite PERSP_CENTROID. */
8011 for (i = 0; i < 2; i++)
8012 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8013 persp_sample[i], base + 4 + i, "");
8014 }
8015 if (key->ps_prolog.states.force_linear_sample_interp) {
8016 unsigned i, base = key->ps_prolog.num_input_sgprs;
8017 LLVMValueRef linear_sample[2];
8018
8019 /* Read LINEAR_SAMPLE. */
8020 for (i = 0; i < 2; i++)
8021 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8022 /* Overwrite LINEAR_CENTER. */
8023 for (i = 0; i < 2; i++)
8024 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8025 linear_sample[i], base + 8 + i, "");
8026 /* Overwrite LINEAR_CENTROID. */
8027 for (i = 0; i < 2; i++)
8028 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8029 linear_sample[i], base + 10 + i, "");
8030 }
8031
8032 /* Force center interpolation. */
8033 if (key->ps_prolog.states.force_persp_center_interp) {
8034 unsigned i, base = key->ps_prolog.num_input_sgprs;
8035 LLVMValueRef persp_center[2];
8036
8037 /* Read PERSP_CENTER. */
8038 for (i = 0; i < 2; i++)
8039 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8040 /* Overwrite PERSP_SAMPLE. */
8041 for (i = 0; i < 2; i++)
8042 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8043 persp_center[i], base + i, "");
8044 /* Overwrite PERSP_CENTROID. */
8045 for (i = 0; i < 2; i++)
8046 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8047 persp_center[i], base + 4 + i, "");
8048 }
8049 if (key->ps_prolog.states.force_linear_center_interp) {
8050 unsigned i, base = key->ps_prolog.num_input_sgprs;
8051 LLVMValueRef linear_center[2];
8052
8053 /* Read LINEAR_CENTER. */
8054 for (i = 0; i < 2; i++)
8055 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8056 /* Overwrite LINEAR_SAMPLE. */
8057 for (i = 0; i < 2; i++)
8058 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8059 linear_center[i], base + 6 + i, "");
8060 /* Overwrite LINEAR_CENTROID. */
8061 for (i = 0; i < 2; i++)
8062 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8063 linear_center[i], base + 10 + i, "");
8064 }
8065
8066 /* Interpolate colors. */
8067 for (i = 0; i < 2; i++) {
8068 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8069 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8070 key->ps_prolog.face_vgpr_index;
8071 LLVMValueRef interp[2], color[4];
8072 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8073
8074 if (!writemask)
8075 continue;
8076
8077 /* If the interpolation qualifier is not CONSTANT (-1). */
8078 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8079 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8080 key->ps_prolog.color_interp_vgpr_index[i];
8081
8082 /* Get the (i,j) updated by bc_optimize handling. */
8083 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8084 interp_vgpr, "");
8085 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8086 interp_vgpr + 1, "");
8087 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8088 }
8089
8090 /* Use the absolute location of the input. */
8091 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8092
8093 if (key->ps_prolog.states.color_two_side) {
8094 face = LLVMGetParam(func, face_vgpr);
8095 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8096 }
8097
8098 interp_fs_input(ctx,
8099 key->ps_prolog.color_attr_index[i],
8100 TGSI_SEMANTIC_COLOR, i,
8101 key->ps_prolog.num_interp_inputs,
8102 key->ps_prolog.colors_read, interp_ij,
8103 prim_mask, face, color);
8104
8105 while (writemask) {
8106 unsigned chan = u_bit_scan(&writemask);
8107 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8108 num_params++, "");
8109 }
8110 }
8111
8112 /* Tell LLVM to insert WQM instruction sequence when needed. */
8113 if (key->ps_prolog.wqm) {
8114 LLVMAddTargetDependentFunctionAttr(func,
8115 "amdgpu-ps-wqm-outputs", "");
8116 }
8117
8118 si_llvm_build_ret(ctx, ret);
8119 }
8120
8121 /**
8122 * Build the pixel shader epilog function. This handles everything that must be
8123 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8124 */
8125 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8126 union si_shader_part_key *key)
8127 {
8128 struct gallivm_state *gallivm = &ctx->gallivm;
8129 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
8130 LLVMTypeRef params[16+8*4+3];
8131 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8132 int last_sgpr, num_params, i;
8133 struct si_ps_exports exp = {};
8134
8135 /* Declare input SGPRs. */
8136 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8137 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8138 params[SI_PARAM_SAMPLERS] = ctx->i64;
8139 params[SI_PARAM_IMAGES] = ctx->i64;
8140 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8141 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8142 last_sgpr = SI_PARAM_ALPHA_REF;
8143
8144 /* Declare input VGPRs. */
8145 num_params = (last_sgpr + 1) +
8146 util_bitcount(key->ps_epilog.colors_written) * 4 +
8147 key->ps_epilog.writes_z +
8148 key->ps_epilog.writes_stencil +
8149 key->ps_epilog.writes_samplemask;
8150
8151 num_params = MAX2(num_params,
8152 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8153
8154 assert(num_params <= ARRAY_SIZE(params));
8155
8156 for (i = last_sgpr + 1; i < num_params; i++)
8157 params[i] = ctx->f32;
8158
8159 /* Create the function. */
8160 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8161 /* Disable elimination of unused inputs. */
8162 si_llvm_add_attribute(ctx->main_fn,
8163 "InitialPSInputAddr", 0xffffff);
8164
8165 /* Process colors. */
8166 unsigned vgpr = last_sgpr + 1;
8167 unsigned colors_written = key->ps_epilog.colors_written;
8168 int last_color_export = -1;
8169
8170 /* Find the last color export. */
8171 if (!key->ps_epilog.writes_z &&
8172 !key->ps_epilog.writes_stencil &&
8173 !key->ps_epilog.writes_samplemask) {
8174 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8175
8176 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8177 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8178 /* Just set this if any of the colorbuffers are enabled. */
8179 if (spi_format &
8180 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8181 last_color_export = 0;
8182 } else {
8183 for (i = 0; i < 8; i++)
8184 if (colors_written & (1 << i) &&
8185 (spi_format >> (i * 4)) & 0xf)
8186 last_color_export = i;
8187 }
8188 }
8189
8190 while (colors_written) {
8191 LLVMValueRef color[4];
8192 int mrt = u_bit_scan(&colors_written);
8193
8194 for (i = 0; i < 4; i++)
8195 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8196
8197 si_export_mrt_color(bld_base, color, mrt,
8198 num_params - 1,
8199 mrt == last_color_export, &exp);
8200 }
8201
8202 /* Process depth, stencil, samplemask. */
8203 if (key->ps_epilog.writes_z)
8204 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8205 if (key->ps_epilog.writes_stencil)
8206 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8207 if (key->ps_epilog.writes_samplemask)
8208 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8209
8210 if (depth || stencil || samplemask)
8211 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8212 else if (last_color_export == -1)
8213 si_export_null(bld_base);
8214
8215 if (exp.num)
8216 si_emit_ps_exports(ctx, &exp);
8217
8218 /* Compile. */
8219 LLVMBuildRetVoid(gallivm->builder);
8220 }
8221
8222 /**
8223 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8224 */
8225 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8226 LLVMTargetMachineRef tm,
8227 struct si_shader *shader,
8228 struct pipe_debug_callback *debug)
8229 {
8230 union si_shader_part_key prolog_key;
8231 union si_shader_part_key epilog_key;
8232
8233 /* Get the prolog. */
8234 si_get_ps_prolog_key(shader, &prolog_key, true);
8235
8236 /* The prolog is a no-op if these aren't set. */
8237 if (si_need_ps_prolog(&prolog_key)) {
8238 shader->prolog =
8239 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8240 PIPE_SHADER_FRAGMENT, true,
8241 &prolog_key, tm, debug,
8242 si_build_ps_prolog_function,
8243 "Fragment Shader Prolog");
8244 if (!shader->prolog)
8245 return false;
8246 }
8247
8248 /* Get the epilog. */
8249 si_get_ps_epilog_key(shader, &epilog_key);
8250
8251 shader->epilog =
8252 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8253 PIPE_SHADER_FRAGMENT, false,
8254 &epilog_key, tm, debug,
8255 si_build_ps_epilog_function,
8256 "Fragment Shader Epilog");
8257 if (!shader->epilog)
8258 return false;
8259
8260 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8261 if (shader->key.part.ps.prolog.poly_stipple) {
8262 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8263 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8264 }
8265
8266 /* Set up the enable bits for per-sample shading if needed. */
8267 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8268 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8269 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8270 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8271 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8272 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8273 }
8274 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8275 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8276 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8277 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8278 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8279 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8280 }
8281 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8282 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8283 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8284 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8285 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8286 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8287 }
8288 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8289 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8290 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8291 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8292 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8293 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8294 }
8295
8296 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8297 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8298 !(shader->config.spi_ps_input_ena & 0xf)) {
8299 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8300 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8301 }
8302
8303 /* At least one pair of interpolation weights must be enabled. */
8304 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8305 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8306 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8307 }
8308
8309 /* The sample mask input is always enabled, because the API shader always
8310 * passes it through to the epilog. Disable it here if it's unused.
8311 */
8312 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8313 !shader->selector->info.reads_samplemask)
8314 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8315
8316 return true;
8317 }
8318
8319 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8320 unsigned *lds_size)
8321 {
8322 /* SPI barrier management bug:
8323 * Make sure we have at least 4k of LDS in use to avoid the bug.
8324 * It applies to workgroup sizes of more than one wavefront.
8325 */
8326 if (sscreen->b.family == CHIP_BONAIRE ||
8327 sscreen->b.family == CHIP_KABINI ||
8328 sscreen->b.family == CHIP_MULLINS)
8329 *lds_size = MAX2(*lds_size, 8);
8330 }
8331
8332 static void si_fix_resource_usage(struct si_screen *sscreen,
8333 struct si_shader *shader)
8334 {
8335 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8336
8337 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8338
8339 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8340 si_get_max_workgroup_size(shader) > 64) {
8341 si_multiwave_lds_size_workaround(sscreen,
8342 &shader->config.lds_size);
8343 }
8344 }
8345
8346 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8347 struct si_shader *shader,
8348 struct pipe_debug_callback *debug)
8349 {
8350 struct si_shader_selector *sel = shader->selector;
8351 struct si_shader *mainp = sel->main_shader_part;
8352 int r;
8353
8354 /* LS, ES, VS are compiled on demand if the main part hasn't been
8355 * compiled for that stage.
8356 *
8357 * Vertex shaders are compiled on demand when a vertex fetch
8358 * workaround must be applied.
8359 */
8360 if (shader->is_monolithic) {
8361 /* Monolithic shader (compiled as a whole, has many variants,
8362 * may take a long time to compile).
8363 */
8364 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8365 if (r)
8366 return r;
8367 } else {
8368 /* The shader consists of 2-3 parts:
8369 *
8370 * - the middle part is the user shader, it has 1 variant only
8371 * and it was compiled during the creation of the shader
8372 * selector
8373 * - the prolog part is inserted at the beginning
8374 * - the epilog part is inserted at the end
8375 *
8376 * The prolog and epilog have many (but simple) variants.
8377 */
8378
8379 /* Copy the compiled TGSI shader data over. */
8380 shader->is_binary_shared = true;
8381 shader->binary = mainp->binary;
8382 shader->config = mainp->config;
8383 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8384 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8385 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8386 memcpy(shader->info.vs_output_param_offset,
8387 mainp->info.vs_output_param_offset,
8388 sizeof(mainp->info.vs_output_param_offset));
8389 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8390 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8391 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8392
8393 /* Select prologs and/or epilogs. */
8394 switch (sel->type) {
8395 case PIPE_SHADER_VERTEX:
8396 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8397 return -1;
8398 break;
8399 case PIPE_SHADER_TESS_CTRL:
8400 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8401 return -1;
8402 break;
8403 case PIPE_SHADER_TESS_EVAL:
8404 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8405 return -1;
8406 break;
8407 case PIPE_SHADER_GEOMETRY:
8408 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8409 return -1;
8410 break;
8411 case PIPE_SHADER_FRAGMENT:
8412 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8413 return -1;
8414
8415 /* Make sure we have at least as many VGPRs as there
8416 * are allocated inputs.
8417 */
8418 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8419 shader->info.num_input_vgprs);
8420 break;
8421 }
8422
8423 /* Update SGPR and VGPR counts. */
8424 if (shader->prolog) {
8425 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8426 shader->prolog->config.num_sgprs);
8427 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8428 shader->prolog->config.num_vgprs);
8429 }
8430 if (shader->epilog) {
8431 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8432 shader->epilog->config.num_sgprs);
8433 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8434 shader->epilog->config.num_vgprs);
8435 }
8436 }
8437
8438 si_fix_resource_usage(sscreen, shader);
8439 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8440 stderr);
8441
8442 /* Upload. */
8443 r = si_shader_binary_upload(sscreen, shader);
8444 if (r) {
8445 fprintf(stderr, "LLVM failed to upload shader\n");
8446 return r;
8447 }
8448
8449 return 0;
8450 }
8451
8452 void si_shader_destroy(struct si_shader *shader)
8453 {
8454 if (shader->scratch_bo)
8455 r600_resource_reference(&shader->scratch_bo, NULL);
8456
8457 r600_resource_reference(&shader->bo, NULL);
8458
8459 if (!shader->is_binary_shared)
8460 radeon_shader_binary_clean(&shader->binary);
8461
8462 free(shader->shader_log);
8463 }