2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
42 #include "compiler/nir/nir.h"
44 static const char scratch_rsrc_dword0_symbol
[] =
45 "SCRATCH_RSRC_DWORD0";
47 static const char scratch_rsrc_dword1_symbol
[] =
48 "SCRATCH_RSRC_DWORD1";
50 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
51 struct si_screen
*sscreen
,
52 struct ac_llvm_compiler
*compiler
);
54 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
55 struct lp_build_tgsi_context
*bld_base
,
56 struct lp_build_emit_data
*emit_data
);
58 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
61 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
62 union si_shader_part_key
*key
);
63 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
64 union si_shader_part_key
*key
);
65 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
66 union si_shader_part_key
*key
);
67 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
68 union si_shader_part_key
*key
);
69 static void si_fix_resource_usage(struct si_screen
*sscreen
,
70 struct si_shader
*shader
);
72 /* Ideally pass the sample mask input to the PS epilog as v14, which
73 * is its usual location, so that the shader doesn't have to add v_mov.
75 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
77 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
80 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
86 /** Whether the shader runs as a combination of multiple API shaders */
87 static bool is_multi_part_shader(struct si_shader_context
*ctx
)
89 if (ctx
->screen
->info
.chip_class
<= GFX8
)
92 return ctx
->shader
->key
.as_ls
||
93 ctx
->shader
->key
.as_es
||
94 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
95 ctx
->type
== PIPE_SHADER_GEOMETRY
;
98 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
99 static bool is_merged_shader(struct si_shader_context
*ctx
)
101 return ctx
->shader
->key
.as_ngg
|| is_multi_part_shader(ctx
);
104 void si_init_function_info(struct si_function_info
*fninfo
)
106 fninfo
->num_params
= 0;
107 fninfo
->num_sgpr_params
= 0;
110 unsigned add_arg_assign(struct si_function_info
*fninfo
,
111 enum si_arg_regfile regfile
, LLVMTypeRef type
,
112 LLVMValueRef
*assign
)
114 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
116 unsigned idx
= fninfo
->num_params
++;
117 assert(idx
< ARRAY_SIZE(fninfo
->types
));
119 if (regfile
== ARG_SGPR
)
120 fninfo
->num_sgpr_params
= fninfo
->num_params
;
122 fninfo
->types
[idx
] = type
;
123 fninfo
->assign
[idx
] = assign
;
127 static unsigned add_arg(struct si_function_info
*fninfo
,
128 enum si_arg_regfile regfile
, LLVMTypeRef type
)
130 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
133 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
134 enum si_arg_regfile regfile
, LLVMTypeRef type
,
135 LLVMValueRef
*assign
, unsigned idx
)
137 MAYBE_UNUSED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
138 assert(actual
== idx
);
141 static void add_arg_checked(struct si_function_info
*fninfo
,
142 enum si_arg_regfile regfile
, LLVMTypeRef type
,
145 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
149 * Returns a unique index for a per-patch semantic name and index. The index
150 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
153 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
155 switch (semantic_name
) {
156 case TGSI_SEMANTIC_TESSOUTER
:
158 case TGSI_SEMANTIC_TESSINNER
:
160 case TGSI_SEMANTIC_PATCH
:
165 assert(!"invalid semantic name");
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
,
178 switch (semantic_name
) {
179 case TGSI_SEMANTIC_POSITION
:
181 case TGSI_SEMANTIC_GENERIC
:
182 /* Since some shader stages use the the highest used IO index
183 * to determine the size to allocate for inputs/outputs
184 * (in LDS, tess and GS rings). GENERIC should be placed right
185 * after POSITION to make that size as small as possible.
187 if (index
< SI_MAX_IO_GENERIC
)
190 assert(!"invalid generic index");
192 case TGSI_SEMANTIC_PSIZE
:
193 return SI_MAX_IO_GENERIC
+ 1;
194 case TGSI_SEMANTIC_CLIPDIST
:
196 return SI_MAX_IO_GENERIC
+ 2 + index
;
197 case TGSI_SEMANTIC_FOG
:
198 return SI_MAX_IO_GENERIC
+ 4;
199 case TGSI_SEMANTIC_LAYER
:
200 return SI_MAX_IO_GENERIC
+ 5;
201 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
202 return SI_MAX_IO_GENERIC
+ 6;
203 case TGSI_SEMANTIC_PRIMID
:
204 return SI_MAX_IO_GENERIC
+ 7;
205 case TGSI_SEMANTIC_COLOR
:
207 return SI_MAX_IO_GENERIC
+ 8 + index
;
208 case TGSI_SEMANTIC_BCOLOR
:
210 /* If it's a varying, COLOR and BCOLOR alias. */
212 return SI_MAX_IO_GENERIC
+ 8 + index
;
214 return SI_MAX_IO_GENERIC
+ 10 + index
;
215 case TGSI_SEMANTIC_TEXCOORD
:
217 STATIC_ASSERT(SI_MAX_IO_GENERIC
+ 12 + 8 <= 63);
218 return SI_MAX_IO_GENERIC
+ 12 + index
;
219 case TGSI_SEMANTIC_CLIPVERTEX
:
222 fprintf(stderr
, "invalid semantic name = %u\n", semantic_name
);
223 assert(!"invalid semantic name");
229 * Get the value of a shader input parameter and extract a bitfield.
231 static LLVMValueRef
unpack_llvm_param(struct si_shader_context
*ctx
,
232 LLVMValueRef value
, unsigned rshift
,
235 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
236 value
= ac_to_integer(&ctx
->ac
, value
);
239 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
240 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
242 if (rshift
+ bitwidth
< 32) {
243 unsigned mask
= (1 << bitwidth
) - 1;
244 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
245 LLVMConstInt(ctx
->i32
, mask
, 0), "");
251 LLVMValueRef
si_unpack_param(struct si_shader_context
*ctx
,
252 unsigned param
, unsigned rshift
,
255 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
, param
);
257 return unpack_llvm_param(ctx
, value
, rshift
, bitwidth
);
260 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
263 case PIPE_SHADER_TESS_CTRL
:
264 return unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 0, 8);
266 case PIPE_SHADER_TESS_EVAL
:
267 return LLVMGetParam(ctx
->main_fn
,
268 ctx
->param_tes_rel_patch_id
);
276 /* Tessellation shaders pass outputs to the next shader using LDS.
278 * LS outputs = TCS inputs
279 * TCS outputs = TES inputs
282 * - TCS inputs for patch 0
283 * - TCS inputs for patch 1
284 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
286 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
287 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
288 * - TCS outputs for patch 1
289 * - Per-patch TCS outputs for patch 1
290 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
291 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
294 * All three shaders VS(LS), TCS, TES share the same LDS space.
298 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
300 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
303 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
305 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
307 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
308 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
310 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
313 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
315 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
317 return LLVMConstInt(ctx
->i32
, stride
, 0);
320 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
322 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
323 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
325 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
326 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
327 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
328 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
329 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
330 num_patch_outputs
* 4;
331 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
335 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
337 return LLVMBuildMul(ctx
->ac
.builder
,
339 ctx
->param_tcs_out_lds_offsets
,
341 LLVMConstInt(ctx
->i32
, 4, 0), "");
345 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
347 return LLVMBuildMul(ctx
->ac
.builder
,
349 ctx
->param_tcs_out_lds_offsets
,
351 LLVMConstInt(ctx
->i32
, 4, 0), "");
355 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
357 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
358 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
360 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
364 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
366 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
367 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
368 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
370 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
, patch0_offset
);
374 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
376 LLVMValueRef patch0_patch_data_offset
=
377 get_tcs_out_patch0_patch_data_offset(ctx
);
378 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
379 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
381 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
, patch0_patch_data_offset
);
384 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
386 unsigned tcs_out_vertices
=
387 ctx
->shader
->selector
?
388 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
390 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
391 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
392 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
394 return si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
397 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
402 case PIPE_SHADER_VERTEX
:
403 stride
= ctx
->shader
->selector
->lshs_vertex_stride
/ 4;
404 return LLVMConstInt(ctx
->i32
, stride
, 0);
406 case PIPE_SHADER_TESS_CTRL
:
407 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
408 ctx
->shader
->is_monolithic
) {
409 stride
= ctx
->shader
->key
.part
.tcs
.ls
->lshs_vertex_stride
/ 4;
410 return LLVMConstInt(ctx
->i32
, stride
, 0);
412 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
420 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
421 LLVMValueRef i32
, unsigned index
)
426 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
427 LLVMConstInt(ctx
->i32
, 16, 0), "");
429 return LLVMBuildSExt(ctx
->ac
.builder
,
430 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
435 void si_llvm_load_input_vs(
436 struct si_shader_context
*ctx
,
437 unsigned input_index
,
440 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
441 unsigned vs_blit_property
= info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
443 if (vs_blit_property
) {
444 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
445 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
446 LLVMIntULE
, vertex_id
,
448 /* Use LLVMIntNE, because we have 3 vertices and only
449 * the middle one should use y2.
451 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
452 LLVMIntNE
, vertex_id
,
455 if (input_index
== 0) {
457 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
458 ctx
->param_vs_blit_inputs
);
459 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
460 ctx
->param_vs_blit_inputs
+ 1);
462 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
463 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
464 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
465 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
467 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
469 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
472 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
473 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
474 out
[2] = LLVMGetParam(ctx
->main_fn
,
475 ctx
->param_vs_blit_inputs
+ 2);
476 out
[3] = ctx
->ac
.f32_1
;
480 /* Color or texture coordinates: */
481 assert(input_index
== 1);
483 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
484 for (int i
= 0; i
< 4; i
++) {
485 out
[i
] = LLVMGetParam(ctx
->main_fn
,
486 ctx
->param_vs_blit_inputs
+ 3 + i
);
489 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
490 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
491 ctx
->param_vs_blit_inputs
+ 3);
492 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
493 ctx
->param_vs_blit_inputs
+ 4);
494 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
495 ctx
->param_vs_blit_inputs
+ 5);
496 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
497 ctx
->param_vs_blit_inputs
+ 6);
499 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
501 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
503 out
[2] = LLVMGetParam(ctx
->main_fn
,
504 ctx
->param_vs_blit_inputs
+ 7);
505 out
[3] = LLVMGetParam(ctx
->main_fn
,
506 ctx
->param_vs_blit_inputs
+ 8);
511 union si_vs_fix_fetch fix_fetch
;
512 LLVMValueRef t_list_ptr
;
513 LLVMValueRef t_offset
;
515 LLVMValueRef vertex_index
;
518 /* Load the T list */
519 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
521 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
523 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
525 vertex_index
= LLVMGetParam(ctx
->main_fn
,
526 ctx
->param_vertex_index0
+
529 /* Use the open-coded implementation for all loads of doubles and
530 * of dword-sized data that needs fixups. We need to insert conversion
531 * code anyway, and the amd/common code does it for us.
533 * Note: On LLVM <= 8, we can only open-code formats with
534 * channel size >= 4 bytes.
536 bool opencode
= ctx
->shader
->key
.mono
.vs_fetch_opencode
& (1 << input_index
);
537 fix_fetch
.bits
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
].bits
;
539 (fix_fetch
.u
.log_size
== 3 && fix_fetch
.u
.format
== AC_FETCH_FORMAT_FLOAT
) ||
540 (fix_fetch
.u
.log_size
== 2)) {
541 tmp
= ac_build_opencoded_load_format(
542 &ctx
->ac
, fix_fetch
.u
.log_size
, fix_fetch
.u
.num_channels_m1
+ 1,
543 fix_fetch
.u
.format
, fix_fetch
.u
.reverse
, !opencode
,
544 t_list
, vertex_index
, ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
546 for (unsigned i
= 0; i
< 4; ++i
)
547 out
[i
] = LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, LLVMConstInt(ctx
->i32
, i
, false), "");
551 /* Do multiple loads for special formats. */
552 unsigned required_channels
= util_last_bit(info
->input_usage_mask
[input_index
]);
553 LLVMValueRef fetches
[4];
554 unsigned num_fetches
;
555 unsigned fetch_stride
;
556 unsigned channels_per_fetch
;
558 if (fix_fetch
.u
.log_size
<= 1 && fix_fetch
.u
.num_channels_m1
== 2) {
559 num_fetches
= MIN2(required_channels
, 3);
560 fetch_stride
= 1 << fix_fetch
.u
.log_size
;
561 channels_per_fetch
= 1;
565 channels_per_fetch
= required_channels
;
568 for (unsigned i
= 0; i
< num_fetches
; ++i
) {
569 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
570 fetches
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
, vertex_index
, voffset
,
571 channels_per_fetch
, false, true);
574 if (num_fetches
== 1 && channels_per_fetch
> 1) {
575 LLVMValueRef fetch
= fetches
[0];
576 for (unsigned i
= 0; i
< channels_per_fetch
; ++i
) {
577 tmp
= LLVMConstInt(ctx
->i32
, i
, false);
578 fetches
[i
] = LLVMBuildExtractElement(
579 ctx
->ac
.builder
, fetch
, tmp
, "");
581 num_fetches
= channels_per_fetch
;
582 channels_per_fetch
= 1;
585 for (unsigned i
= num_fetches
; i
< 4; ++i
)
586 fetches
[i
] = LLVMGetUndef(ctx
->f32
);
588 if (fix_fetch
.u
.log_size
<= 1 && fix_fetch
.u
.num_channels_m1
== 2 &&
589 required_channels
== 4) {
590 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_UINT
|| fix_fetch
.u
.format
== AC_FETCH_FORMAT_SINT
)
591 fetches
[3] = ctx
->ac
.i32_1
;
593 fetches
[3] = ctx
->ac
.f32_1
;
594 } else if (fix_fetch
.u
.log_size
== 3 &&
595 (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
||
596 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
||
597 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SINT
) &&
598 required_channels
== 4) {
599 /* For 2_10_10_10, the hardware returns an unsigned value;
600 * convert it to a signed one.
602 LLVMValueRef tmp
= fetches
[3];
603 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
605 /* First, recover the sign-extended signed integer value. */
606 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
)
607 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
609 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
611 /* For the integer-like cases, do a natural sign extension.
613 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
614 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
617 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
618 fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
?
619 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
620 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
622 /* Convert back to the right type. */
623 if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SNORM
) {
625 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
626 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
627 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
628 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
629 } else if (fix_fetch
.u
.format
== AC_FETCH_FORMAT_SSCALED
) {
630 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
636 for (unsigned i
= 0; i
< 4; ++i
)
637 out
[i
] = ac_to_float(&ctx
->ac
, fetches
[i
]);
640 static void declare_input_vs(
641 struct si_shader_context
*ctx
,
642 unsigned input_index
,
643 const struct tgsi_full_declaration
*decl
,
646 si_llvm_load_input_vs(ctx
, input_index
, out
);
649 LLVMValueRef
si_get_primitive_id(struct si_shader_context
*ctx
,
656 case PIPE_SHADER_VERTEX
:
657 return LLVMGetParam(ctx
->main_fn
,
658 ctx
->param_vs_prim_id
);
659 case PIPE_SHADER_TESS_CTRL
:
660 return ctx
->abi
.tcs_patch_id
;
661 case PIPE_SHADER_TESS_EVAL
:
662 return ctx
->abi
.tes_patch_id
;
663 case PIPE_SHADER_GEOMETRY
:
664 return ctx
->abi
.gs_prim_id
;
672 * Return the value of tgsi_ind_register for indexing.
673 * This is the indirect index with the constant offset added to it.
675 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
676 const struct tgsi_ind_register
*ind
,
682 if (ind
->File
== TGSI_FILE_ADDRESS
) {
683 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
684 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
686 struct tgsi_full_src_register src
= {};
688 src
.Register
.File
= ind
->File
;
689 src
.Register
.Index
= ind
->Index
;
691 /* Set the second index to 0 for constants. */
692 if (ind
->File
== TGSI_FILE_CONSTANT
)
693 src
.Register
.Dimension
= 1;
695 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
698 result
= ac_to_integer(&ctx
->ac
, result
);
701 return ac_build_imad(&ctx
->ac
, result
, LLVMConstInt(ctx
->i32
, addr_mul
, 0),
702 LLVMConstInt(ctx
->i32
, rel_index
, 0));
706 * Like si_get_indirect_index, but restricts the return value to a (possibly
707 * undefined) value inside [0..num).
709 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
710 const struct tgsi_ind_register
*ind
,
711 int rel_index
, unsigned num
)
713 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
715 return si_llvm_bound_index(ctx
, result
, num
);
718 static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context
*ctx
,
719 LLVMValueRef vertex_dw_stride
,
720 LLVMValueRef base_addr
,
721 LLVMValueRef vertex_index
,
722 LLVMValueRef param_index
,
723 unsigned input_index
,
728 if (vertex_dw_stride
) {
729 base_addr
= ac_build_imad(&ctx
->ac
, vertex_index
,
730 vertex_dw_stride
, base_addr
);
734 base_addr
= ac_build_imad(&ctx
->ac
, param_index
,
735 LLVMConstInt(ctx
->i32
, 4, 0), base_addr
);
738 int param
= is_patch
?
739 si_shader_io_get_unique_index_patch(name
[input_index
],
740 index
[input_index
]) :
741 si_shader_io_get_unique_index(name
[input_index
],
742 index
[input_index
], false);
744 /* Add the base address of the element. */
745 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
746 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
750 * Calculate a dword address given an input or output register and a stride.
752 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
753 const struct tgsi_full_dst_register
*dst
,
754 const struct tgsi_full_src_register
*src
,
755 LLVMValueRef vertex_dw_stride
,
756 LLVMValueRef base_addr
)
758 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
759 ubyte
*name
, *index
, *array_first
;
761 struct tgsi_full_dst_register reg
;
762 LLVMValueRef vertex_index
= NULL
;
763 LLVMValueRef ind_index
= NULL
;
765 /* Set the register description. The address computation is the same
766 * for sources and destinations. */
768 reg
.Register
.File
= src
->Register
.File
;
769 reg
.Register
.Index
= src
->Register
.Index
;
770 reg
.Register
.Indirect
= src
->Register
.Indirect
;
771 reg
.Register
.Dimension
= src
->Register
.Dimension
;
772 reg
.Indirect
= src
->Indirect
;
773 reg
.Dimension
= src
->Dimension
;
774 reg
.DimIndirect
= src
->DimIndirect
;
778 /* If the register is 2-dimensional (e.g. an array of vertices
779 * in a primitive), calculate the base address of the vertex. */
780 if (reg
.Register
.Dimension
) {
781 if (reg
.Dimension
.Indirect
)
782 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
783 1, reg
.Dimension
.Index
);
785 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
788 /* Get information about the register. */
789 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
790 name
= info
->input_semantic_name
;
791 index
= info
->input_semantic_index
;
792 array_first
= info
->input_array_first
;
793 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
794 name
= info
->output_semantic_name
;
795 index
= info
->output_semantic_index
;
796 array_first
= info
->output_array_first
;
802 if (reg
.Register
.Indirect
) {
803 /* Add the relative address of the element. */
804 if (reg
.Indirect
.ArrayID
)
805 input_index
= array_first
[reg
.Indirect
.ArrayID
];
807 input_index
= reg
.Register
.Index
;
809 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
810 1, reg
.Register
.Index
- input_index
);
812 input_index
= reg
.Register
.Index
;
815 return get_dw_address_from_generic_indices(ctx
, vertex_dw_stride
,
816 base_addr
, vertex_index
,
817 ind_index
, input_index
,
819 !reg
.Register
.Dimension
);
822 /* The offchip buffer layout for TCS->TES is
824 * - attribute 0 of patch 0 vertex 0
825 * - attribute 0 of patch 0 vertex 1
826 * - attribute 0 of patch 0 vertex 2
828 * - attribute 0 of patch 1 vertex 0
829 * - attribute 0 of patch 1 vertex 1
831 * - attribute 1 of patch 0 vertex 0
832 * - attribute 1 of patch 0 vertex 1
834 * - per patch attribute 0 of patch 0
835 * - per patch attribute 0 of patch 1
838 * Note that every attribute has 4 components.
840 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
841 LLVMValueRef rel_patch_id
,
842 LLVMValueRef vertex_index
,
843 LLVMValueRef param_index
)
845 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
846 LLVMValueRef param_stride
, constant16
;
848 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
849 num_patches
= si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
850 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
853 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
855 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
856 vertices_per_patch
, vertex_index
);
857 param_stride
= total_vertices
;
859 base_addr
= rel_patch_id
;
860 param_stride
= num_patches
;
863 base_addr
= ac_build_imad(&ctx
->ac
, param_index
, param_stride
, base_addr
);
864 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
867 LLVMValueRef patch_data_offset
=
868 si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
870 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
871 patch_data_offset
, "");
876 /* This is a generic helper that can be shared by the NIR and TGSI backends */
877 static LLVMValueRef
get_tcs_tes_buffer_address_from_generic_indices(
878 struct si_shader_context
*ctx
,
879 LLVMValueRef vertex_index
,
880 LLVMValueRef param_index
,
886 unsigned param_index_base
;
888 param_index_base
= is_patch
?
889 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]) :
890 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
], false);
893 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
894 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
897 param_index
= LLVMConstInt(ctx
->i32
, param_index_base
, 0);
900 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
901 vertex_index
, param_index
);
904 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
905 struct si_shader_context
*ctx
,
906 const struct tgsi_full_dst_register
*dst
,
907 const struct tgsi_full_src_register
*src
)
909 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
910 ubyte
*name
, *index
, *array_first
;
911 struct tgsi_full_src_register reg
;
912 LLVMValueRef vertex_index
= NULL
;
913 LLVMValueRef param_index
= NULL
;
916 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
918 if (reg
.Register
.Dimension
) {
920 if (reg
.Dimension
.Indirect
)
921 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
922 1, reg
.Dimension
.Index
);
924 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
927 /* Get information about the register. */
928 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
929 name
= info
->input_semantic_name
;
930 index
= info
->input_semantic_index
;
931 array_first
= info
->input_array_first
;
932 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
933 name
= info
->output_semantic_name
;
934 index
= info
->output_semantic_index
;
935 array_first
= info
->output_array_first
;
941 if (reg
.Register
.Indirect
) {
942 if (reg
.Indirect
.ArrayID
)
943 param_base
= array_first
[reg
.Indirect
.ArrayID
];
945 param_base
= reg
.Register
.Index
;
947 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
948 1, reg
.Register
.Index
- param_base
);
951 param_base
= reg
.Register
.Index
;
954 return get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
955 param_index
, param_base
,
956 name
, index
, !reg
.Register
.Dimension
);
959 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
960 LLVMTypeRef type
, unsigned swizzle
,
961 LLVMValueRef buffer
, LLVMValueRef offset
,
962 LLVMValueRef base
, bool can_speculate
)
964 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
965 LLVMValueRef value
, value2
;
966 LLVMTypeRef vec_type
= LLVMVectorType(type
, 4);
969 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
970 0, 1, 0, can_speculate
, false);
972 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
975 if (!llvm_type_is_64bit(ctx
, type
)) {
976 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
977 0, 1, 0, can_speculate
, false);
979 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
980 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
981 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
984 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
985 swizzle
* 4, 1, 0, can_speculate
, false);
987 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
988 swizzle
* 4 + 4, 1, 0, can_speculate
, false);
990 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
994 * Load from LSHS LDS storage.
996 * \param type output value type
997 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
998 * \param dw_addr address in dwords
1000 static LLVMValueRef
lshs_lds_load(struct lp_build_tgsi_context
*bld_base
,
1001 LLVMTypeRef type
, unsigned swizzle
,
1002 LLVMValueRef dw_addr
)
1004 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1007 if (swizzle
== ~0) {
1008 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1010 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1011 values
[chan
] = lshs_lds_load(bld_base
, type
, chan
, dw_addr
);
1013 return ac_build_gather_values(&ctx
->ac
, values
,
1017 /* Split 64-bit loads. */
1018 if (llvm_type_is_64bit(ctx
, type
)) {
1019 LLVMValueRef lo
, hi
;
1021 lo
= lshs_lds_load(bld_base
, ctx
->i32
, swizzle
, dw_addr
);
1022 hi
= lshs_lds_load(bld_base
, ctx
->i32
, swizzle
+ 1, dw_addr
);
1023 return si_llvm_emit_fetch_64bit(bld_base
, type
, lo
, hi
);
1026 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1027 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1029 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1031 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1035 * Store to LSHS LDS storage.
1037 * \param swizzle offset (typically 0..3)
1038 * \param dw_addr address in dwords
1039 * \param value value to store
1041 static void lshs_lds_store(struct si_shader_context
*ctx
,
1042 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1045 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1046 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0), "");
1048 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1053 TESS_OFFCHIP_RING_TCS
,
1054 TESS_OFFCHIP_RING_TES
,
1057 static LLVMValueRef
get_tess_ring_descriptor(struct si_shader_context
*ctx
,
1058 enum si_tess_ring ring
)
1060 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1061 unsigned param
= ring
== TESS_OFFCHIP_RING_TES
? ctx
->param_tes_offchip_addr
:
1062 ctx
->param_tcs_out_lds_layout
;
1063 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1065 /* TCS only receives high 13 bits of the address. */
1066 if (ring
== TESS_OFFCHIP_RING_TCS
|| ring
== TCS_FACTOR_RING
) {
1067 addr
= LLVMBuildAnd(builder
, addr
,
1068 LLVMConstInt(ctx
->i32
, 0xfff80000, 0), "");
1071 if (ring
== TCS_FACTOR_RING
) {
1072 unsigned tf_offset
= ctx
->screen
->tess_offchip_ring_size
;
1073 addr
= LLVMBuildAdd(builder
, addr
,
1074 LLVMConstInt(ctx
->i32
, tf_offset
, 0), "");
1077 uint32_t rsrc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1078 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1079 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1080 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1082 if (ctx
->screen
->info
.chip_class
>= GFX10
)
1083 rsrc3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1084 S_008F0C_OOB_SELECT(3) |
1085 S_008F0C_RESOURCE_LEVEL(1);
1087 rsrc3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1088 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1090 LLVMValueRef desc
[4];
1092 desc
[1] = LLVMConstInt(ctx
->i32
,
1093 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
1094 desc
[2] = LLVMConstInt(ctx
->i32
, 0xffffffff, 0);
1095 desc
[3] = LLVMConstInt(ctx
->i32
, rsrc3
, false);
1097 return ac_build_gather_values(&ctx
->ac
, desc
, 4);
1100 static LLVMValueRef
fetch_input_tcs(
1101 struct lp_build_tgsi_context
*bld_base
,
1102 const struct tgsi_full_src_register
*reg
,
1103 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1105 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1106 LLVMValueRef dw_addr
, stride
;
1107 unsigned swizzle
= swizzle_in
& 0xffff;
1108 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1109 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1110 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1112 return lshs_lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1115 static LLVMValueRef
si_nir_load_tcs_varyings(struct ac_shader_abi
*abi
,
1117 LLVMValueRef vertex_index
,
1118 LLVMValueRef param_index
,
1119 unsigned const_index
,
1121 unsigned driver_location
,
1123 unsigned num_components
,
1128 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1129 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1130 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1131 LLVMValueRef dw_addr
, stride
;
1133 driver_location
= driver_location
/ 4;
1136 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1137 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1141 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1143 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1144 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1149 /* Add the constant index to the indirect index */
1150 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1151 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1153 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1159 names
= info
->input_semantic_name
;
1160 indices
= info
->input_semantic_index
;
1162 names
= info
->output_semantic_name
;
1163 indices
= info
->output_semantic_index
;
1166 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1167 vertex_index
, param_index
,
1172 LLVMValueRef value
[4];
1173 for (unsigned i
= 0; i
< num_components
; i
++) {
1174 unsigned offset
= i
;
1175 if (llvm_type_is_64bit(ctx
, type
))
1178 offset
+= component
;
1179 value
[i
+ component
] = lshs_lds_load(bld_base
, type
, offset
, dw_addr
);
1182 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1185 static LLVMValueRef
fetch_output_tcs(
1186 struct lp_build_tgsi_context
*bld_base
,
1187 const struct tgsi_full_src_register
*reg
,
1188 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1190 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1191 LLVMValueRef dw_addr
, stride
;
1192 unsigned swizzle
= (swizzle_in
& 0xffff);
1194 if (reg
->Register
.Dimension
) {
1195 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1196 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1197 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1199 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1200 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1203 return lshs_lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1206 static LLVMValueRef
fetch_input_tes(
1207 struct lp_build_tgsi_context
*bld_base
,
1208 const struct tgsi_full_src_register
*reg
,
1209 enum tgsi_opcode_type type
, unsigned swizzle_in
)
1211 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1212 LLVMValueRef base
, addr
;
1213 unsigned swizzle
= (swizzle_in
& 0xffff);
1215 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1216 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1218 return buffer_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
,
1219 ctx
->tess_offchip_ring
, base
, addr
, true);
1222 LLVMValueRef
si_nir_load_input_tes(struct ac_shader_abi
*abi
,
1224 LLVMValueRef vertex_index
,
1225 LLVMValueRef param_index
,
1226 unsigned const_index
,
1228 unsigned driver_location
,
1230 unsigned num_components
,
1235 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1236 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1237 LLVMValueRef base
, addr
;
1239 driver_location
= driver_location
/ 4;
1241 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1244 /* Add the constant index to the indirect index */
1245 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1246 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1248 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1251 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1252 param_index
, driver_location
,
1253 info
->input_semantic_name
,
1254 info
->input_semantic_index
,
1257 /* TODO: This will generate rather ordinary llvm code, although it
1258 * should be easy for the optimiser to fix up. In future we might want
1259 * to refactor buffer_load(), but for now this maximises code sharing
1260 * between the NIR and TGSI backends.
1262 LLVMValueRef value
[4];
1263 for (unsigned i
= 0; i
< num_components
; i
++) {
1264 unsigned offset
= i
;
1265 if (llvm_type_is_64bit(ctx
, type
)) {
1268 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
,
1271 driver_location
+ 1,
1272 info
->input_semantic_name
,
1273 info
->input_semantic_index
,
1277 offset
= offset
% 4;
1280 offset
+= component
;
1281 value
[i
+ component
] = buffer_load(&ctx
->bld_base
, type
, offset
,
1282 ctx
->tess_offchip_ring
, base
, addr
, true);
1285 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1288 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1289 const struct tgsi_full_instruction
*inst
,
1290 const struct tgsi_opcode_info
*info
,
1292 LLVMValueRef dst
[4])
1294 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1295 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1296 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1297 unsigned chan_index
;
1298 LLVMValueRef dw_addr
, stride
;
1299 LLVMValueRef buffer
, base
, buf_addr
;
1300 LLVMValueRef values
[4];
1301 bool skip_lds_store
;
1302 bool is_tess_factor
= false, is_tess_inner
= false;
1304 /* Only handle per-patch and per-vertex outputs here.
1305 * Vectors will be lowered to scalars and this function will be called again.
1307 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1308 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1309 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1313 if (reg
->Register
.Dimension
) {
1314 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1315 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1316 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1317 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1319 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1320 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1321 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1323 if (!reg
->Register
.Indirect
) {
1324 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1326 /* Always write tess factors into LDS for the TCS epilog. */
1327 if (name
== TGSI_SEMANTIC_TESSINNER
||
1328 name
== TGSI_SEMANTIC_TESSOUTER
) {
1329 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1330 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1331 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1332 is_tess_factor
= true;
1333 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1338 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1340 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1341 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1343 uint32_t writemask
= reg
->Register
.WriteMask
;
1345 chan_index
= u_bit_scan(&writemask
);
1346 LLVMValueRef value
= dst
[chan_index
];
1348 if (inst
->Instruction
.Saturate
)
1349 value
= ac_build_clamp(&ctx
->ac
, value
);
1351 /* Skip LDS stores if there is no LDS read of this output. */
1352 if (!skip_lds_store
)
1353 lshs_lds_store(ctx
, chan_index
, dw_addr
, value
);
1355 value
= ac_to_integer(&ctx
->ac
, value
);
1356 values
[chan_index
] = value
;
1358 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1359 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1361 4 * chan_index
, 1, 0, false);
1364 /* Write tess factors into VGPRs for the epilog. */
1365 if (is_tess_factor
&&
1366 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1367 if (!is_tess_inner
) {
1368 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1369 ctx
->invoc0_tess_factors
[chan_index
]);
1370 } else if (chan_index
< 2) {
1371 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1372 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1377 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1378 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1380 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1381 base
, 0, 1, 0, false);
1385 static void si_nir_store_output_tcs(struct ac_shader_abi
*abi
,
1386 const struct nir_variable
*var
,
1387 LLVMValueRef vertex_index
,
1388 LLVMValueRef param_index
,
1389 unsigned const_index
,
1393 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1394 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1395 const unsigned component
= var
->data
.location_frac
;
1396 const bool is_patch
= var
->data
.patch
;
1397 unsigned driver_location
= var
->data
.driver_location
;
1398 LLVMValueRef dw_addr
, stride
;
1399 LLVMValueRef buffer
, base
, addr
;
1400 LLVMValueRef values
[8];
1401 bool skip_lds_store
;
1402 bool is_tess_factor
= false, is_tess_inner
= false;
1404 driver_location
= driver_location
/ 4;
1407 /* Add the constant index to the indirect index */
1408 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1409 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1411 if (const_index
!= 0)
1412 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1416 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1417 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1418 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1419 vertex_index
, param_index
,
1421 info
->output_semantic_name
,
1422 info
->output_semantic_index
,
1425 skip_lds_store
= !info
->reads_pervertex_outputs
;
1427 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1428 dw_addr
= get_dw_address_from_generic_indices(ctx
, NULL
, dw_addr
,
1429 vertex_index
, param_index
,
1431 info
->output_semantic_name
,
1432 info
->output_semantic_index
,
1435 skip_lds_store
= !info
->reads_perpatch_outputs
;
1438 int name
= info
->output_semantic_name
[driver_location
];
1440 /* Always write tess factors into LDS for the TCS epilog. */
1441 if (name
== TGSI_SEMANTIC_TESSINNER
||
1442 name
== TGSI_SEMANTIC_TESSOUTER
) {
1443 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1444 skip_lds_store
= !info
->reads_tessfactor_outputs
&&
1445 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1446 is_tess_factor
= true;
1447 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1452 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1454 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1456 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1457 param_index
, driver_location
,
1458 info
->output_semantic_name
,
1459 info
->output_semantic_index
,
1462 for (unsigned chan
= 0; chan
< 8; chan
++) {
1463 if (!(writemask
& (1 << chan
)))
1465 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1467 unsigned buffer_store_offset
= chan
% 4;
1469 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
,
1472 driver_location
+ 1,
1473 info
->output_semantic_name
,
1474 info
->output_semantic_index
,
1478 /* Skip LDS stores if there is no LDS read of this output. */
1479 if (!skip_lds_store
)
1480 lshs_lds_store(ctx
, chan
, dw_addr
, value
);
1482 value
= ac_to_integer(&ctx
->ac
, value
);
1483 values
[chan
] = value
;
1485 if (writemask
!= 0xF && !is_tess_factor
) {
1486 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1488 4 * buffer_store_offset
,
1492 /* Write tess factors into VGPRs for the epilog. */
1493 if (is_tess_factor
&&
1494 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1495 if (!is_tess_inner
) {
1496 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1497 ctx
->invoc0_tess_factors
[chan
]);
1498 } else if (chan
< 2) {
1499 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1500 ctx
->invoc0_tess_factors
[4 + chan
]);
1505 if (writemask
== 0xF && !is_tess_factor
) {
1506 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1508 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, addr
,
1509 base
, 0, 1, 0, false);
1513 LLVMValueRef
si_llvm_load_input_gs(struct ac_shader_abi
*abi
,
1514 unsigned input_index
,
1515 unsigned vtx_offset_param
,
1519 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1520 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1521 struct si_shader
*shader
= ctx
->shader
;
1522 LLVMValueRef vtx_offset
, soffset
;
1523 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1524 unsigned semantic_name
= info
->input_semantic_name
[input_index
];
1525 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1529 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
, false);
1531 /* GFX9 has the ESGS ring in LDS. */
1532 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1533 unsigned index
= vtx_offset_param
;
1535 switch (index
/ 2) {
1537 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1538 index
% 2 ? 16 : 0, 16);
1541 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1542 index
% 2 ? 16 : 0, 16);
1545 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1546 index
% 2 ? 16 : 0, 16);
1553 unsigned offset
= param
* 4 + swizzle
;
1554 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1555 LLVMConstInt(ctx
->i32
, offset
, false), "");
1557 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, vtx_offset
);
1558 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
1559 if (llvm_type_is_64bit(ctx
, type
)) {
1560 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
,
1561 &ctx
->ac
.i32_1
, 1, "");
1562 LLVMValueRef values
[2] = {
1564 LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "")
1566 value
= ac_build_gather_values(&ctx
->ac
, values
, 2);
1568 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1571 /* GFX6: input load from the ESGS ring in memory. */
1572 if (swizzle
== ~0) {
1573 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1575 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1576 values
[chan
] = si_llvm_load_input_gs(abi
, input_index
, vtx_offset_param
,
1579 return ac_build_gather_values(&ctx
->ac
, values
,
1583 /* Get the vertex offset parameter on GFX6. */
1584 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1586 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, gs_vtx_offset
,
1587 LLVMConstInt(ctx
->i32
, 4, 0), "");
1589 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1591 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1592 vtx_offset
, soffset
, 0, 1, 0, true, false);
1593 if (llvm_type_is_64bit(ctx
, type
)) {
1594 LLVMValueRef value2
;
1595 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1597 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1598 ctx
->i32_0
, vtx_offset
, soffset
,
1599 0, 1, 0, true, false);
1600 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1602 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1605 static LLVMValueRef
si_nir_load_input_gs(struct ac_shader_abi
*abi
,
1607 unsigned driver_location
,
1609 unsigned num_components
,
1610 unsigned vertex_index
,
1611 unsigned const_index
,
1614 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1616 LLVMValueRef value
[4];
1617 for (unsigned i
= 0; i
< num_components
; i
++) {
1618 unsigned offset
= i
;
1619 if (llvm_type_is_64bit(ctx
, type
))
1622 offset
+= component
;
1623 value
[i
+ component
] = si_llvm_load_input_gs(&ctx
->abi
, driver_location
/ 4,
1624 vertex_index
, type
, offset
);
1627 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1630 static LLVMValueRef
fetch_input_gs(
1631 struct lp_build_tgsi_context
*bld_base
,
1632 const struct tgsi_full_src_register
*reg
,
1633 enum tgsi_opcode_type type
,
1634 unsigned swizzle_in
)
1636 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1637 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1638 unsigned swizzle
= swizzle_in
& 0xffff;
1640 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1641 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1642 return si_get_primitive_id(ctx
, swizzle
);
1644 if (!reg
->Register
.Dimension
)
1647 return si_llvm_load_input_gs(&ctx
->abi
, reg
->Register
.Index
,
1648 reg
->Dimension
.Index
,
1649 tgsi2llvmtype(bld_base
, type
),
1653 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1655 switch (interpolate
) {
1656 case TGSI_INTERPOLATE_CONSTANT
:
1659 case TGSI_INTERPOLATE_LINEAR
:
1660 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1661 return SI_PARAM_LINEAR_SAMPLE
;
1662 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1663 return SI_PARAM_LINEAR_CENTROID
;
1665 return SI_PARAM_LINEAR_CENTER
;
1667 case TGSI_INTERPOLATE_COLOR
:
1668 case TGSI_INTERPOLATE_PERSPECTIVE
:
1669 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1670 return SI_PARAM_PERSP_SAMPLE
;
1671 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1672 return SI_PARAM_PERSP_CENTROID
;
1674 return SI_PARAM_PERSP_CENTER
;
1677 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1682 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1683 unsigned attr_index
, unsigned chan
,
1684 LLVMValueRef prim_mask
,
1685 LLVMValueRef i
, LLVMValueRef j
)
1688 return ac_build_fs_interp(&ctx
->ac
,
1689 LLVMConstInt(ctx
->i32
, chan
, 0),
1690 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1693 return ac_build_fs_interp_mov(&ctx
->ac
,
1694 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1695 LLVMConstInt(ctx
->i32
, chan
, 0),
1696 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1701 * Interpolate a fragment shader input.
1703 * @param ctx context
1704 * @param input_index index of the input in hardware
1705 * @param semantic_name TGSI_SEMANTIC_*
1706 * @param semantic_index semantic index
1707 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1708 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1709 * @param interp_param interpolation weights (i,j)
1710 * @param prim_mask SI_PARAM_PRIM_MASK
1711 * @param face SI_PARAM_FRONT_FACE
1712 * @param result the return value (4 components)
1714 static void interp_fs_input(struct si_shader_context
*ctx
,
1715 unsigned input_index
,
1716 unsigned semantic_name
,
1717 unsigned semantic_index
,
1718 unsigned num_interp_inputs
,
1719 unsigned colors_read_mask
,
1720 LLVMValueRef interp_param
,
1721 LLVMValueRef prim_mask
,
1723 LLVMValueRef result
[4])
1725 LLVMValueRef i
= NULL
, j
= NULL
;
1728 /* fs.constant returns the param from the middle vertex, so it's not
1729 * really useful for flat shading. It's meant to be used for custom
1730 * interpolation (but the intrinsic can't fetch from the other two
1733 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1734 * to do the right thing. The only reason we use fs.constant is that
1735 * fs.interp cannot be used on integers, because they can be equal
1738 * When interp is false we will use fs.constant or for newer llvm,
1739 * amdgcn.interp.mov.
1741 bool interp
= interp_param
!= NULL
;
1744 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1745 LLVMVectorType(ctx
->f32
, 2), "");
1747 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1749 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1753 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1754 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1755 LLVMValueRef is_face_positive
;
1757 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1758 * otherwise it's at offset "num_inputs".
1760 unsigned back_attr_offset
= num_interp_inputs
;
1761 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1762 back_attr_offset
+= 1;
1764 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1765 face
, ctx
->i32_0
, "");
1767 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1768 LLVMValueRef front
, back
;
1770 front
= si_build_fs_interp(ctx
,
1773 back
= si_build_fs_interp(ctx
,
1774 back_attr_offset
, chan
,
1777 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1783 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1784 result
[0] = si_build_fs_interp(ctx
, input_index
,
1785 0, prim_mask
, i
, j
);
1787 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1788 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1790 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1791 result
[chan
] = si_build_fs_interp(ctx
,
1798 void si_llvm_load_input_fs(
1799 struct si_shader_context
*ctx
,
1800 unsigned input_index
,
1801 LLVMValueRef out
[4])
1803 struct si_shader
*shader
= ctx
->shader
;
1804 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1805 LLVMValueRef main_fn
= ctx
->main_fn
;
1806 LLVMValueRef interp_param
= NULL
;
1807 int interp_param_idx
;
1808 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1809 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1810 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1811 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1813 /* Get colors from input VGPRs (set by the prolog). */
1814 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1815 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1816 unsigned mask
= colors_read
>> (semantic_index
* 4);
1817 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1818 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1819 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1821 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1822 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1823 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1824 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1828 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1829 if (interp_param_idx
== -1)
1831 else if (interp_param_idx
) {
1832 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1835 interp_fs_input(ctx
, input_index
, semantic_name
,
1836 semantic_index
, 0, /* this param is unused */
1837 shader
->selector
->info
.colors_read
, interp_param
,
1839 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1843 static void declare_input_fs(
1844 struct si_shader_context
*ctx
,
1845 unsigned input_index
,
1846 const struct tgsi_full_declaration
*decl
,
1847 LLVMValueRef out
[4])
1849 si_llvm_load_input_fs(ctx
, input_index
, out
);
1852 LLVMValueRef
si_get_sample_id(struct si_shader_context
*ctx
)
1854 return si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1857 static LLVMValueRef
get_base_vertex(struct ac_shader_abi
*abi
)
1859 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1861 /* For non-indexed draws, the base vertex set by the driver
1862 * (for direct draws) or the CP (for indirect draws) is the
1863 * first vertex ID, but GLSL expects 0 to be returned.
1865 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
,
1866 ctx
->param_vs_state_bits
);
1867 LLVMValueRef indexed
;
1869 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1870 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1872 return LLVMBuildSelect(ctx
->ac
.builder
, indexed
, ctx
->abi
.base_vertex
,
1876 static LLVMValueRef
get_block_size(struct ac_shader_abi
*abi
)
1878 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1880 LLVMValueRef values
[3];
1881 LLVMValueRef result
;
1883 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1885 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1886 unsigned sizes
[3] = {
1887 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1888 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1889 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1892 for (i
= 0; i
< 3; ++i
)
1893 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1895 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
1897 result
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1904 * Load a dword from a constant buffer.
1906 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1907 LLVMValueRef resource
,
1908 LLVMValueRef offset
)
1910 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1911 0, 0, 0, true, true);
1914 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
, LLVMValueRef sample_id
)
1916 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1917 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1918 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
1919 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
1921 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1922 LLVMValueRef offset0
= LLVMBuildMul(ctx
->ac
.builder
, sample_id
, LLVMConstInt(ctx
->i32
, 8, 0), "");
1923 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1925 LLVMValueRef pos
[4] = {
1926 buffer_load_const(ctx
, resource
, offset0
),
1927 buffer_load_const(ctx
, resource
, offset1
),
1928 LLVMConstReal(ctx
->f32
, 0),
1929 LLVMConstReal(ctx
->f32
, 0)
1932 return ac_build_gather_values(&ctx
->ac
, pos
, 4);
1935 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1937 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1938 return ac_to_integer(&ctx
->ac
, abi
->sample_coverage
);
1941 static LLVMValueRef
si_load_tess_coord(struct ac_shader_abi
*abi
)
1943 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1944 LLVMValueRef coord
[4] = {
1945 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
1946 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
1951 /* For triangles, the vector should be (u, v, 1-u-v). */
1952 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1953 PIPE_PRIM_TRIANGLES
) {
1954 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1955 LLVMBuildFAdd(ctx
->ac
.builder
,
1956 coord
[0], coord
[1], ""), "");
1958 return ac_build_gather_values(&ctx
->ac
, coord
, 4);
1961 static LLVMValueRef
load_tess_level(struct si_shader_context
*ctx
,
1962 unsigned semantic_name
)
1964 LLVMValueRef base
, addr
;
1966 int param
= si_shader_io_get_unique_index_patch(semantic_name
, 0);
1968 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1969 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
1970 LLVMConstInt(ctx
->i32
, param
, 0));
1972 return buffer_load(&ctx
->bld_base
, ctx
->f32
,
1973 ~0, ctx
->tess_offchip_ring
, base
, addr
, true);
1977 static LLVMValueRef
si_load_tess_level(struct ac_shader_abi
*abi
,
1978 unsigned varying_id
)
1980 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1981 unsigned semantic_name
;
1983 switch (varying_id
) {
1984 case VARYING_SLOT_TESS_LEVEL_INNER
:
1985 semantic_name
= TGSI_SEMANTIC_TESSINNER
;
1987 case VARYING_SLOT_TESS_LEVEL_OUTER
:
1988 semantic_name
= TGSI_SEMANTIC_TESSOUTER
;
1991 unreachable("unknown tess level");
1994 return load_tess_level(ctx
, semantic_name
);
1998 static LLVMValueRef
si_load_patch_vertices_in(struct ac_shader_abi
*abi
)
2000 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2001 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2002 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 13, 6);
2003 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
2004 return get_num_tcs_out_vertices(ctx
);
2006 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2009 void si_load_system_value(struct si_shader_context
*ctx
,
2011 const struct tgsi_full_declaration
*decl
)
2013 LLVMValueRef value
= 0;
2015 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
2017 switch (decl
->Semantic
.Name
) {
2018 case TGSI_SEMANTIC_INSTANCEID
:
2019 value
= ctx
->abi
.instance_id
;
2022 case TGSI_SEMANTIC_VERTEXID
:
2023 value
= LLVMBuildAdd(ctx
->ac
.builder
,
2025 ctx
->abi
.base_vertex
, "");
2028 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
2029 /* Unused. Clarify the meaning in indexed vs. non-indexed
2030 * draws if this is ever used again. */
2034 case TGSI_SEMANTIC_BASEVERTEX
:
2035 value
= get_base_vertex(&ctx
->abi
);
2038 case TGSI_SEMANTIC_BASEINSTANCE
:
2039 value
= ctx
->abi
.start_instance
;
2042 case TGSI_SEMANTIC_DRAWID
:
2043 value
= ctx
->abi
.draw_id
;
2046 case TGSI_SEMANTIC_INVOCATIONID
:
2047 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
2048 value
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2049 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
2050 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
2051 value
= LLVMBuildAnd(ctx
->ac
.builder
,
2052 ctx
->abi
.gs_invocation_id
,
2053 LLVMConstInt(ctx
->i32
, 127, 0), "");
2055 value
= ctx
->abi
.gs_invocation_id
;
2058 assert(!"INVOCATIONID not implemented");
2062 case TGSI_SEMANTIC_POSITION
:
2064 LLVMValueRef pos
[4] = {
2065 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2066 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2067 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
2068 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2069 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
)),
2071 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2075 case TGSI_SEMANTIC_FACE
:
2076 value
= ctx
->abi
.front_face
;
2079 case TGSI_SEMANTIC_SAMPLEID
:
2080 value
= si_get_sample_id(ctx
);
2083 case TGSI_SEMANTIC_SAMPLEPOS
: {
2084 LLVMValueRef pos
[4] = {
2085 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2086 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2087 LLVMConstReal(ctx
->f32
, 0),
2088 LLVMConstReal(ctx
->f32
, 0)
2090 pos
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
2091 pos
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
2092 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2096 case TGSI_SEMANTIC_SAMPLEMASK
:
2097 /* This can only occur with the OpenGL Core profile, which
2098 * doesn't support smoothing.
2100 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
2103 case TGSI_SEMANTIC_TESSCOORD
:
2104 value
= si_load_tess_coord(&ctx
->abi
);
2107 case TGSI_SEMANTIC_VERTICESIN
:
2108 value
= si_load_patch_vertices_in(&ctx
->abi
);
2111 case TGSI_SEMANTIC_TESSINNER
:
2112 case TGSI_SEMANTIC_TESSOUTER
:
2113 value
= load_tess_level(ctx
, decl
->Semantic
.Name
);
2116 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
2117 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
2119 LLVMValueRef buf
, slot
, val
[4];
2122 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
2123 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2124 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
2125 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
2127 for (i
= 0; i
< 4; i
++)
2128 val
[i
] = buffer_load_const(ctx
, buf
,
2129 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
2130 value
= ac_build_gather_values(&ctx
->ac
, val
, 4);
2134 case TGSI_SEMANTIC_PRIMID
:
2135 value
= si_get_primitive_id(ctx
, 0);
2138 case TGSI_SEMANTIC_GRID_SIZE
:
2139 value
= ctx
->abi
.num_work_groups
;
2142 case TGSI_SEMANTIC_BLOCK_SIZE
:
2143 value
= get_block_size(&ctx
->abi
);
2146 case TGSI_SEMANTIC_BLOCK_ID
:
2148 LLVMValueRef values
[3];
2150 for (int i
= 0; i
< 3; i
++) {
2151 values
[i
] = ctx
->i32_0
;
2152 if (ctx
->abi
.workgroup_ids
[i
]) {
2153 values
[i
] = ctx
->abi
.workgroup_ids
[i
];
2156 value
= ac_build_gather_values(&ctx
->ac
, values
, 3);
2160 case TGSI_SEMANTIC_THREAD_ID
:
2161 value
= ctx
->abi
.local_invocation_ids
;
2164 case TGSI_SEMANTIC_HELPER_INVOCATION
:
2165 value
= ac_build_load_helper_invocation(&ctx
->ac
);
2168 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
2169 value
= LLVMConstInt(ctx
->i32
, 64, 0);
2172 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
2173 value
= ac_get_thread_id(&ctx
->ac
);
2176 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
2178 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2179 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2180 value
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->i64
, 1, 0), id
, "");
2181 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2185 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
2186 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
2187 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
2188 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
2190 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2191 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
2192 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
2193 /* All bits set except LSB */
2194 value
= LLVMConstInt(ctx
->i64
, -2, 0);
2197 value
= LLVMConstInt(ctx
->i64
, -1, 0);
2199 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2200 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
2201 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
2202 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
2203 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2204 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2208 case TGSI_SEMANTIC_CS_USER_DATA
:
2209 value
= LLVMGetParam(ctx
->main_fn
, ctx
->param_cs_user_data
);
2213 assert(!"unknown system value");
2217 ctx
->system_values
[index
] = value
;
2220 void si_declare_compute_memory(struct si_shader_context
*ctx
)
2222 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2223 unsigned lds_size
= sel
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
];
2225 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, AC_ADDR_SPACE_LDS
);
2228 assert(!ctx
->ac
.lds
);
2230 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
2231 LLVMArrayType(ctx
->i8
, lds_size
),
2234 LLVMSetAlignment(var
, 64 * 1024);
2236 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
2239 void si_tgsi_declare_compute_memory(struct si_shader_context
*ctx
,
2240 const struct tgsi_full_declaration
*decl
)
2242 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
2243 assert(decl
->Range
.First
== decl
->Range
.Last
);
2245 si_declare_compute_memory(ctx
);
2248 static LLVMValueRef
load_const_buffer_desc_fast_path(struct si_shader_context
*ctx
)
2251 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2252 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2254 /* Do the bounds checking with a descriptor, because
2255 * doing computation and manual bounds checking of 64-bit
2256 * addresses generates horrible VALU code with very high
2257 * VGPR usage and very low SIMD occupancy.
2259 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->ac
.intptr
, "");
2261 LLVMValueRef desc0
, desc1
;
2263 desc1
= LLVMConstInt(ctx
->i32
,
2264 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
2266 uint32_t rsrc3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2267 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2268 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2269 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2271 if (ctx
->screen
->info
.chip_class
>= GFX10
)
2272 rsrc3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2273 S_008F0C_OOB_SELECT(3) |
2274 S_008F0C_RESOURCE_LEVEL(1);
2276 rsrc3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2277 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2279 LLVMValueRef desc_elems
[] = {
2282 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2283 LLVMConstInt(ctx
->i32
, rsrc3
, false)
2286 return ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2289 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
2291 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
2292 ctx
->param_const_and_shader_buffers
);
2294 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
2295 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
2298 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
2300 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2301 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2303 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2305 if (sel
->info
.const_buffers_declared
== 1 &&
2306 sel
->info
.shader_buffers_declared
== 0) {
2307 return load_const_buffer_desc_fast_path(ctx
);
2310 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
2311 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2312 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2314 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2318 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
2320 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2321 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
2322 ctx
->param_const_and_shader_buffers
);
2324 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
2325 index
= LLVMBuildSub(ctx
->ac
.builder
,
2326 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
2329 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
2332 static LLVMValueRef
fetch_constant(
2333 struct lp_build_tgsi_context
*bld_base
,
2334 const struct tgsi_full_src_register
*reg
,
2335 enum tgsi_opcode_type type
,
2336 unsigned swizzle_in
)
2338 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2339 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2340 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
2342 unsigned swizzle
= swizzle_in
& 0xffff;
2344 LLVMValueRef addr
, bufp
;
2346 if (swizzle_in
== LP_CHAN_ALL
) {
2348 LLVMValueRef values
[4];
2349 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
2350 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
2352 return ac_build_gather_values(&ctx
->ac
, values
, 4);
2355 /* Split 64-bit loads. */
2356 if (tgsi_type_is_64bit(type
)) {
2357 LLVMValueRef lo
, hi
;
2359 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
2360 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, (swizzle_in
>> 16));
2361 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
2365 idx
= reg
->Register
.Index
* 4 + swizzle
;
2366 if (reg
->Register
.Indirect
) {
2367 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2369 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2372 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2373 if (sel
->info
.const_buffers_declared
== 1 &&
2374 sel
->info
.shader_buffers_declared
== 0) {
2375 LLVMValueRef desc
= load_const_buffer_desc_fast_path(ctx
);
2376 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2377 return bitcast(bld_base
, type
, result
);
2380 assert(reg
->Register
.Dimension
);
2381 buf
= reg
->Dimension
.Index
;
2383 if (reg
->Dimension
.Indirect
) {
2384 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2386 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2387 reg
->Dimension
.Index
,
2388 ctx
->num_const_buffers
);
2389 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2390 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2391 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2393 bufp
= load_const_buffer_desc(ctx
, buf
);
2395 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2398 /* Initialize arguments for the shader export intrinsic */
2399 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2400 LLVMValueRef
*values
,
2402 struct ac_export_args
*args
)
2404 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2405 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2407 bool is_int8
, is_int10
;
2409 /* Default is 0xf. Adjusted below depending on the format. */
2410 args
->enabled_channels
= 0xf; /* writemask */
2412 /* Specify whether the EXEC mask represents the valid mask */
2413 args
->valid_mask
= 0;
2415 /* Specify whether this is the last export */
2418 /* Specify the target we are exporting */
2419 args
->target
= target
;
2421 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2422 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2423 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2424 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2426 assert(cbuf
>= 0 && cbuf
< 8);
2427 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2428 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2429 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2432 args
->compr
= false;
2433 args
->out
[0] = f32undef
;
2434 args
->out
[1] = f32undef
;
2435 args
->out
[2] = f32undef
;
2436 args
->out
[3] = f32undef
;
2438 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2439 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2440 unsigned bits
, bool hi
) = NULL
;
2442 switch (spi_shader_col_format
) {
2443 case V_028714_SPI_SHADER_ZERO
:
2444 args
->enabled_channels
= 0; /* writemask */
2445 args
->target
= V_008DFC_SQ_EXP_NULL
;
2448 case V_028714_SPI_SHADER_32_R
:
2449 args
->enabled_channels
= 1; /* writemask */
2450 args
->out
[0] = values
[0];
2453 case V_028714_SPI_SHADER_32_GR
:
2454 args
->enabled_channels
= 0x3; /* writemask */
2455 args
->out
[0] = values
[0];
2456 args
->out
[1] = values
[1];
2459 case V_028714_SPI_SHADER_32_AR
:
2460 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
2461 args
->enabled_channels
= 0x3; /* writemask */
2462 args
->out
[0] = values
[0];
2463 args
->out
[1] = values
[3];
2465 args
->enabled_channels
= 0x9; /* writemask */
2466 args
->out
[0] = values
[0];
2467 args
->out
[3] = values
[3];
2471 case V_028714_SPI_SHADER_FP16_ABGR
:
2472 packf
= ac_build_cvt_pkrtz_f16
;
2475 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2476 packf
= ac_build_cvt_pknorm_u16
;
2479 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2480 packf
= ac_build_cvt_pknorm_i16
;
2483 case V_028714_SPI_SHADER_UINT16_ABGR
:
2484 packi
= ac_build_cvt_pk_u16
;
2487 case V_028714_SPI_SHADER_SINT16_ABGR
:
2488 packi
= ac_build_cvt_pk_i16
;
2491 case V_028714_SPI_SHADER_32_ABGR
:
2492 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2496 /* Pack f16 or norm_i16/u16. */
2498 for (chan
= 0; chan
< 2; chan
++) {
2499 LLVMValueRef pack_args
[2] = {
2501 values
[2 * chan
+ 1]
2503 LLVMValueRef packed
;
2505 packed
= packf(&ctx
->ac
, pack_args
);
2506 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2508 args
->compr
= 1; /* COMPR flag */
2512 for (chan
= 0; chan
< 2; chan
++) {
2513 LLVMValueRef pack_args
[2] = {
2514 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2515 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2517 LLVMValueRef packed
;
2519 packed
= packi(&ctx
->ac
, pack_args
,
2520 is_int8
? 8 : is_int10
? 10 : 16,
2522 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2524 args
->compr
= 1; /* COMPR flag */
2528 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2531 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2533 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2534 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2535 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2536 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2537 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2538 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2539 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2540 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2542 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2545 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2546 SI_PARAM_ALPHA_REF
);
2547 LLVMValueRef alpha_pass
=
2548 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2549 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2551 ac_build_kill_if_false(&ctx
->ac
, ctx
->i1false
);
2555 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2557 unsigned samplemask_param
)
2559 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2560 LLVMValueRef coverage
;
2562 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2563 coverage
= LLVMGetParam(ctx
->main_fn
,
2565 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2567 coverage
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32",
2569 &coverage
, 1, AC_FUNC_ATTR_READNONE
);
2571 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2574 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2575 LLVMConstReal(ctx
->f32
,
2576 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2578 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2581 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2582 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2586 unsigned const_chan
;
2587 LLVMValueRef base_elt
;
2588 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2589 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2590 SI_VS_CONST_CLIP_PLANES
, 0);
2591 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2593 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2594 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2599 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2601 /* Compute dot products of position and user clip plane vectors */
2602 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2603 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2605 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2606 const_chan
) * 4, 0);
2607 base_elt
= buffer_load_const(ctx
, const_resource
,
2609 args
->out
[chan
] = ac_build_fmad(&ctx
->ac
, base_elt
,
2610 out_elts
[const_chan
], args
->out
[chan
]);
2614 args
->enabled_channels
= 0xf;
2615 args
->valid_mask
= 0;
2617 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2622 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2626 if (so
->num_outputs
)
2627 fprintf(stderr
, "STREAMOUT\n");
2629 for (i
= 0; i
< so
->num_outputs
; i
++) {
2630 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2631 so
->output
[i
].start_component
;
2632 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2633 i
, so
->output
[i
].output_buffer
,
2634 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2635 so
->output
[i
].register_index
,
2636 mask
& 1 ? "x" : "",
2637 mask
& 2 ? "y" : "",
2638 mask
& 4 ? "z" : "",
2639 mask
& 8 ? "w" : "");
2643 void si_emit_streamout_output(struct si_shader_context
*ctx
,
2644 LLVMValueRef
const *so_buffers
,
2645 LLVMValueRef
const *so_write_offsets
,
2646 struct pipe_stream_output
*stream_out
,
2647 struct si_shader_output_values
*shader_out
)
2649 unsigned buf_idx
= stream_out
->output_buffer
;
2650 unsigned start
= stream_out
->start_component
;
2651 unsigned num_comps
= stream_out
->num_components
;
2652 LLVMValueRef out
[4];
2654 assert(num_comps
&& num_comps
<= 4);
2655 if (!num_comps
|| num_comps
> 4)
2658 /* Load the output as int. */
2659 for (int j
= 0; j
< num_comps
; j
++) {
2660 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2662 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2665 /* Pack the output. */
2666 LLVMValueRef vdata
= NULL
;
2668 switch (num_comps
) {
2669 case 1: /* as i32 */
2672 case 2: /* as v2i32 */
2673 case 3: /* as v3i32 */
2674 if (ac_has_vec3_support(ctx
->screen
->info
.chip_class
, false)) {
2675 vdata
= ac_build_gather_values(&ctx
->ac
, out
, num_comps
);
2678 /* as v4i32 (aligned to 4) */
2679 out
[3] = LLVMGetUndef(ctx
->i32
);
2681 case 4: /* as v4i32 */
2682 vdata
= ac_build_gather_values(&ctx
->ac
, out
, util_next_power_of_two(num_comps
));
2686 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2688 so_write_offsets
[buf_idx
],
2690 stream_out
->dst_offset
* 4, 1, 1, false);
2694 * Write streamout data to buffers for vertex stream @p stream (different
2695 * vertex streams can occur for GS copy shaders).
2697 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2698 struct si_shader_output_values
*outputs
,
2699 unsigned noutput
, unsigned stream
)
2701 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2702 struct pipe_stream_output_info
*so
= &sel
->so
;
2703 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2705 struct lp_build_if_state if_ctx
;
2707 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2708 LLVMValueRef so_vtx_count
=
2709 si_unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2711 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2713 /* can_emit = tid < so_vtx_count; */
2714 LLVMValueRef can_emit
=
2715 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2717 /* Emit the streamout code conditionally. This actually avoids
2718 * out-of-bounds buffer access. The hw tells us via the SGPR
2719 * (so_vtx_count) which threads are allowed to emit streamout data. */
2720 lp_build_if(&if_ctx
, &ctx
->gallivm
, can_emit
);
2722 /* The buffer offset is computed as follows:
2723 * ByteOffset = streamout_offset[buffer_id]*4 +
2724 * (streamout_write_index + thread_id)*stride[buffer_id] +
2728 LLVMValueRef so_write_index
=
2729 LLVMGetParam(ctx
->main_fn
,
2730 ctx
->param_streamout_write_index
);
2732 /* Compute (streamout_write_index + thread_id). */
2733 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2735 /* Load the descriptor and compute the write offset for each
2736 * enabled buffer. */
2737 LLVMValueRef so_write_offset
[4] = {};
2738 LLVMValueRef so_buffers
[4];
2739 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2740 ctx
->param_rw_buffers
);
2742 for (i
= 0; i
< 4; i
++) {
2746 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2747 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2749 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2751 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2752 ctx
->param_streamout_offset
[i
]);
2753 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2755 so_write_offset
[i
] = ac_build_imad(&ctx
->ac
, so_write_index
,
2756 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0),
2760 /* Write streamout data. */
2761 for (i
= 0; i
< so
->num_outputs
; i
++) {
2762 unsigned reg
= so
->output
[i
].register_index
;
2767 if (stream
!= so
->output
[i
].stream
)
2770 si_emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2771 &so
->output
[i
], &outputs
[reg
]);
2774 lp_build_endif(&if_ctx
);
2777 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2778 LLVMValueRef
*values
)
2780 struct ac_export_args args
;
2782 si_llvm_init_export_args(ctx
, values
,
2783 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2784 ac_build_export(&ctx
->ac
, &args
);
2787 static void si_build_param_exports(struct si_shader_context
*ctx
,
2788 struct si_shader_output_values
*outputs
,
2791 struct si_shader
*shader
= ctx
->shader
;
2792 unsigned param_count
= 0;
2794 for (unsigned i
= 0; i
< noutput
; i
++) {
2795 unsigned semantic_name
= outputs
[i
].semantic_name
;
2796 unsigned semantic_index
= outputs
[i
].semantic_index
;
2798 if (outputs
[i
].vertex_stream
[0] != 0 &&
2799 outputs
[i
].vertex_stream
[1] != 0 &&
2800 outputs
[i
].vertex_stream
[2] != 0 &&
2801 outputs
[i
].vertex_stream
[3] != 0)
2804 switch (semantic_name
) {
2805 case TGSI_SEMANTIC_LAYER
:
2806 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2807 case TGSI_SEMANTIC_CLIPDIST
:
2808 case TGSI_SEMANTIC_COLOR
:
2809 case TGSI_SEMANTIC_BCOLOR
:
2810 case TGSI_SEMANTIC_PRIMID
:
2811 case TGSI_SEMANTIC_FOG
:
2812 case TGSI_SEMANTIC_TEXCOORD
:
2813 case TGSI_SEMANTIC_GENERIC
:
2819 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2820 semantic_index
< SI_MAX_IO_GENERIC
) &&
2821 shader
->key
.opt
.kill_outputs
&
2822 (1ull << si_shader_io_get_unique_index(semantic_name
,
2823 semantic_index
, true)))
2826 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2828 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2829 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2832 shader
->info
.nr_param_exports
= param_count
;
2836 * Vertex color clamping.
2838 * This uses a state constant loaded in a user data SGPR and
2839 * an IF statement is added that clamps all colors if the constant
2842 static void si_vertex_color_clamping(struct si_shader_context
*ctx
,
2843 struct si_shader_output_values
*outputs
,
2846 LLVMValueRef addr
[SI_MAX_VS_OUTPUTS
][4];
2847 bool has_colors
= false;
2849 /* Store original colors to alloca variables. */
2850 for (unsigned i
= 0; i
< noutput
; i
++) {
2851 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2852 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2855 for (unsigned j
= 0; j
< 4; j
++) {
2856 addr
[i
][j
] = ac_build_alloca_undef(&ctx
->ac
, ctx
->f32
, "");
2857 LLVMBuildStore(ctx
->ac
.builder
, outputs
[i
].values
[j
], addr
[i
][j
]);
2865 /* The state is in the first bit of the user SGPR. */
2866 LLVMValueRef cond
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vs_state_bits
);
2867 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
, ctx
->i1
, "");
2869 struct lp_build_if_state if_ctx
;
2870 lp_build_if(&if_ctx
, &ctx
->gallivm
, cond
);
2872 /* Store clamped colors to alloca variables within the conditional block. */
2873 for (unsigned i
= 0; i
< noutput
; i
++) {
2874 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2875 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2878 for (unsigned j
= 0; j
< 4; j
++) {
2879 LLVMBuildStore(ctx
->ac
.builder
,
2880 ac_build_clamp(&ctx
->ac
, outputs
[i
].values
[j
]),
2884 lp_build_endif(&if_ctx
);
2886 /* Load clamped colors */
2887 for (unsigned i
= 0; i
< noutput
; i
++) {
2888 if (outputs
[i
].semantic_name
!= TGSI_SEMANTIC_COLOR
&&
2889 outputs
[i
].semantic_name
!= TGSI_SEMANTIC_BCOLOR
)
2892 for (unsigned j
= 0; j
< 4; j
++) {
2893 outputs
[i
].values
[j
] =
2894 LLVMBuildLoad(ctx
->ac
.builder
, addr
[i
][j
], "");
2899 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2900 * (position and parameter data only).
2902 void si_llvm_export_vs(struct si_shader_context
*ctx
,
2903 struct si_shader_output_values
*outputs
,
2906 struct si_shader
*shader
= ctx
->shader
;
2907 struct ac_export_args pos_args
[4] = {};
2908 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2912 si_vertex_color_clamping(ctx
, outputs
, noutput
);
2914 /* Build position exports. */
2915 for (i
= 0; i
< noutput
; i
++) {
2916 switch (outputs
[i
].semantic_name
) {
2917 case TGSI_SEMANTIC_POSITION
:
2918 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2919 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2921 case TGSI_SEMANTIC_PSIZE
:
2922 psize_value
= outputs
[i
].values
[0];
2924 case TGSI_SEMANTIC_LAYER
:
2925 layer_value
= outputs
[i
].values
[0];
2927 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2928 viewport_index_value
= outputs
[i
].values
[0];
2930 case TGSI_SEMANTIC_EDGEFLAG
:
2931 edgeflag_value
= outputs
[i
].values
[0];
2933 case TGSI_SEMANTIC_CLIPDIST
:
2934 if (!shader
->key
.opt
.clip_disable
) {
2935 unsigned index
= 2 + outputs
[i
].semantic_index
;
2936 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2937 V_008DFC_SQ_EXP_POS
+ index
,
2941 case TGSI_SEMANTIC_CLIPVERTEX
:
2942 if (!shader
->key
.opt
.clip_disable
) {
2943 si_llvm_emit_clipvertex(ctx
, pos_args
,
2950 /* We need to add the position output manually if it's missing. */
2951 if (!pos_args
[0].out
[0]) {
2952 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2953 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2954 pos_args
[0].done
= 0; /* last export? */
2955 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2956 pos_args
[0].compr
= 0; /* COMPR flag */
2957 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2958 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2959 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2960 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2963 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2964 if (shader
->selector
->info
.writes_psize
||
2965 shader
->selector
->info
.writes_edgeflag
||
2966 shader
->selector
->info
.writes_viewport_index
||
2967 shader
->selector
->info
.writes_layer
) {
2968 pos_args
[1].enabled_channels
= shader
->selector
->info
.writes_psize
|
2969 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2970 (shader
->selector
->info
.writes_layer
<< 2);
2972 pos_args
[1].valid_mask
= 0; /* EXEC mask */
2973 pos_args
[1].done
= 0; /* last export? */
2974 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2975 pos_args
[1].compr
= 0; /* COMPR flag */
2976 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2977 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2978 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2979 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2981 if (shader
->selector
->info
.writes_psize
)
2982 pos_args
[1].out
[0] = psize_value
;
2984 if (shader
->selector
->info
.writes_edgeflag
) {
2985 /* The output is a float, but the hw expects an integer
2986 * with the first bit containing the edge flag. */
2987 edgeflag_value
= LLVMBuildFPToUI(ctx
->ac
.builder
,
2990 edgeflag_value
= ac_build_umin(&ctx
->ac
,
2994 /* The LLVM intrinsic expects a float. */
2995 pos_args
[1].out
[1] = ac_to_float(&ctx
->ac
, edgeflag_value
);
2998 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
2999 /* GFX9 has the layer in out.z[10:0] and the viewport
3000 * index in out.z[19:16].
3002 if (shader
->selector
->info
.writes_layer
)
3003 pos_args
[1].out
[2] = layer_value
;
3005 if (shader
->selector
->info
.writes_viewport_index
) {
3006 LLVMValueRef v
= viewport_index_value
;
3008 v
= ac_to_integer(&ctx
->ac
, v
);
3009 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
3010 LLVMConstInt(ctx
->i32
, 16, 0), "");
3011 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
3012 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
3013 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
3014 pos_args
[1].enabled_channels
|= 1 << 2;
3017 if (shader
->selector
->info
.writes_layer
)
3018 pos_args
[1].out
[2] = layer_value
;
3020 if (shader
->selector
->info
.writes_viewport_index
) {
3021 pos_args
[1].out
[3] = viewport_index_value
;
3022 pos_args
[1].enabled_channels
|= 1 << 3;
3027 for (i
= 0; i
< 4; i
++)
3028 if (pos_args
[i
].out
[0])
3029 shader
->info
.nr_pos_exports
++;
3031 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3032 * Setting valid_mask=1 prevents it and has no other effect.
3034 if (ctx
->screen
->info
.family
== CHIP_NAVI10
||
3035 ctx
->screen
->info
.family
== CHIP_NAVI12
||
3036 ctx
->screen
->info
.family
== CHIP_NAVI14
)
3037 pos_args
[0].valid_mask
= 1;
3040 for (i
= 0; i
< 4; i
++) {
3041 if (!pos_args
[i
].out
[0])
3044 /* Specify the target we are exporting */
3045 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
3047 if (pos_idx
== shader
->info
.nr_pos_exports
)
3048 /* Specify that this is the last export */
3049 pos_args
[i
].done
= 1;
3051 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
3054 /* Build parameter exports. */
3055 si_build_param_exports(ctx
, outputs
, noutput
);
3059 * Forward all outputs from the vertex shader to the TES. This is only used
3060 * for the fixed function TCS.
3062 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
3064 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3065 LLVMValueRef invocation_id
, buffer
, buffer_offset
;
3066 LLVMValueRef lds_vertex_stride
, lds_base
;
3069 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3070 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3071 buffer_offset
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3073 lds_vertex_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3074 lds_base
= get_tcs_in_current_patch_offset(ctx
);
3075 lds_base
= ac_build_imad(&ctx
->ac
, invocation_id
, lds_vertex_stride
,
3078 inputs
= ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
;
3080 unsigned i
= u_bit_scan64(&inputs
);
3082 LLVMValueRef lds_ptr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3083 LLVMConstInt(ctx
->i32
, 4 * i
, 0),
3086 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
3087 get_rel_patch_id(ctx
),
3089 LLVMConstInt(ctx
->i32
, i
, 0));
3091 LLVMValueRef value
= lshs_lds_load(bld_base
, ctx
->ac
.i32
, ~0, lds_ptr
);
3093 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buffer_addr
,
3094 buffer_offset
, 0, 1, 0, false);
3098 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
3099 LLVMValueRef rel_patch_id
,
3100 LLVMValueRef invocation_id
,
3101 LLVMValueRef tcs_out_current_patch_data_offset
,
3102 LLVMValueRef invoc0_tf_outer
[4],
3103 LLVMValueRef invoc0_tf_inner
[2])
3105 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3106 struct si_shader
*shader
= ctx
->shader
;
3107 unsigned tess_inner_index
, tess_outer_index
;
3108 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
3109 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3110 unsigned stride
, outer_comps
, inner_comps
, i
, offset
;
3111 struct lp_build_if_state if_ctx
, inner_if_ctx
;
3113 /* Add a barrier before loading tess factors from LDS. */
3114 if (!shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
)
3115 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
3117 /* Do this only for invocation 0, because the tess levels are per-patch,
3120 * This can't jump, because invocation 0 executes this. It should
3121 * at least mask out the loads and stores for other invocations.
3123 lp_build_if(&if_ctx
, &ctx
->gallivm
,
3124 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3125 invocation_id
, ctx
->i32_0
, ""));
3127 /* Determine the layout of one tess factor element in the buffer. */
3128 switch (shader
->key
.part
.tcs
.epilog
.prim_mode
) {
3129 case PIPE_PRIM_LINES
:
3130 stride
= 2; /* 2 dwords, 1 vec2 store */
3134 case PIPE_PRIM_TRIANGLES
:
3135 stride
= 4; /* 4 dwords, 1 vec4 store */
3139 case PIPE_PRIM_QUADS
:
3140 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3149 for (i
= 0; i
< 4; i
++) {
3150 inner
[i
] = LLVMGetUndef(ctx
->i32
);
3151 outer
[i
] = LLVMGetUndef(ctx
->i32
);
3154 if (shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
) {
3155 /* Tess factors are in VGPRs. */
3156 for (i
= 0; i
< outer_comps
; i
++)
3157 outer
[i
] = out
[i
] = invoc0_tf_outer
[i
];
3158 for (i
= 0; i
< inner_comps
; i
++)
3159 inner
[i
] = out
[outer_comps
+i
] = invoc0_tf_inner
[i
];
3161 /* Load tess_inner and tess_outer from LDS.
3162 * Any invocation can write them, so we can't get them from a temporary.
3164 tess_inner_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0);
3165 tess_outer_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0);
3167 lds_base
= tcs_out_current_patch_data_offset
;
3168 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3169 LLVMConstInt(ctx
->i32
,
3170 tess_inner_index
* 4, 0), "");
3171 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3172 LLVMConstInt(ctx
->i32
,
3173 tess_outer_index
* 4, 0), "");
3175 for (i
= 0; i
< outer_comps
; i
++) {
3177 lshs_lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_outer
);
3179 for (i
= 0; i
< inner_comps
; i
++) {
3180 inner
[i
] = out
[outer_comps
+i
] =
3181 lshs_lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_inner
);
3185 if (shader
->key
.part
.tcs
.epilog
.prim_mode
== PIPE_PRIM_LINES
) {
3186 /* For isolines, the hardware expects tess factors in the
3187 * reverse order from what GLSL / TGSI specify.
3189 LLVMValueRef tmp
= out
[0];
3194 /* Convert the outputs to vectors for stores. */
3195 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3199 vec1
= ac_build_gather_values(&ctx
->ac
, out
+4, stride
- 4);
3201 /* Get the buffer. */
3202 buffer
= get_tess_ring_descriptor(ctx
, TCS_FACTOR_RING
);
3204 /* Get the offset. */
3205 tf_base
= LLVMGetParam(ctx
->main_fn
,
3206 ctx
->param_tcs_factor_offset
);
3207 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3208 LLVMConstInt(ctx
->i32
, 4 * stride
, 0), "");
3210 lp_build_if(&inner_if_ctx
, &ctx
->gallivm
,
3211 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3212 rel_patch_id
, ctx
->i32_0
, ""));
3214 /* Store the dynamic HS control word. */
3216 if (ctx
->screen
->info
.chip_class
<= GFX8
) {
3217 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3218 LLVMConstInt(ctx
->i32
, 0x80000000, 0),
3219 1, ctx
->i32_0
, tf_base
,
3220 offset
, 1, 0, false);
3224 lp_build_endif(&inner_if_ctx
);
3226 /* Store the tessellation factors. */
3227 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3228 MIN2(stride
, 4), byteoffset
, tf_base
,
3229 offset
, 1, 0, false);
3232 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3233 stride
- 4, byteoffset
, tf_base
,
3234 offset
, 1, 0, false);
3236 /* Store the tess factors into the offchip buffer if TES reads them. */
3237 if (shader
->key
.part
.tcs
.epilog
.tes_reads_tess_factors
) {
3238 LLVMValueRef buf
, base
, inner_vec
, outer_vec
, tf_outer_offset
;
3239 LLVMValueRef tf_inner_offset
;
3240 unsigned param_outer
, param_inner
;
3242 buf
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3243 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3245 param_outer
= si_shader_io_get_unique_index_patch(
3246 TGSI_SEMANTIC_TESSOUTER
, 0);
3247 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3248 LLVMConstInt(ctx
->i32
, param_outer
, 0));
3250 unsigned outer_vec_size
=
3251 ac_has_vec3_support(ctx
->screen
->info
.chip_class
, false) ?
3252 outer_comps
: util_next_power_of_two(outer_comps
);
3253 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
, outer_vec_size
);
3255 ac_build_buffer_store_dword(&ctx
->ac
, buf
, outer_vec
,
3256 outer_comps
, tf_outer_offset
,
3257 base
, 0, 1, 0, false);
3259 param_inner
= si_shader_io_get_unique_index_patch(
3260 TGSI_SEMANTIC_TESSINNER
, 0);
3261 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3262 LLVMConstInt(ctx
->i32
, param_inner
, 0));
3264 inner_vec
= inner_comps
== 1 ? inner
[0] :
3265 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3266 ac_build_buffer_store_dword(&ctx
->ac
, buf
, inner_vec
,
3267 inner_comps
, tf_inner_offset
,
3268 base
, 0, 1, 0, false);
3272 lp_build_endif(&if_ctx
);
3276 si_insert_input_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3277 unsigned param
, unsigned return_index
)
3279 return LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3280 LLVMGetParam(ctx
->main_fn
, param
),
3285 si_insert_input_ret_float(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3286 unsigned param
, unsigned return_index
)
3288 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3289 LLVMValueRef p
= LLVMGetParam(ctx
->main_fn
, param
);
3291 return LLVMBuildInsertValue(builder
, ret
,
3292 ac_to_float(&ctx
->ac
, p
),
3297 si_insert_input_ptr(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3298 unsigned param
, unsigned return_index
)
3300 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3301 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, param
);
3302 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i32
, "");
3303 return LLVMBuildInsertValue(builder
, ret
, ptr
, return_index
, "");
3306 /* This only writes the tessellation factor levels. */
3307 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi
*abi
,
3308 unsigned max_outputs
,
3309 LLVMValueRef
*addrs
)
3311 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3312 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
3313 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3314 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
3316 si_copy_tcs_inputs(bld_base
);
3318 rel_patch_id
= get_rel_patch_id(ctx
);
3319 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3320 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
3322 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3323 LLVMBasicBlockRef blocks
[2] = {
3324 LLVMGetInsertBlock(builder
),
3325 ctx
->merged_wrap_if_state
.entry_block
3327 LLVMValueRef values
[2];
3329 lp_build_endif(&ctx
->merged_wrap_if_state
);
3331 values
[0] = rel_patch_id
;
3332 values
[1] = LLVMGetUndef(ctx
->i32
);
3333 rel_patch_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3335 values
[0] = tf_lds_offset
;
3336 values
[1] = LLVMGetUndef(ctx
->i32
);
3337 tf_lds_offset
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3339 values
[0] = invocation_id
;
3340 values
[1] = ctx
->i32_1
; /* cause the epilog to skip threads */
3341 invocation_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3344 /* Return epilog parameters from this function. */
3345 LLVMValueRef ret
= ctx
->return_value
;
3348 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3349 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3350 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3351 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3352 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3353 /* Tess offchip and tess factor offsets are at the beginning. */
3354 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3355 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3356 vgpr
= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
+ 1;
3358 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3359 GFX6_SGPR_TCS_OFFCHIP_LAYOUT
);
3360 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3361 GFX6_SGPR_TCS_OUT_LAYOUT
);
3362 /* Tess offchip and tess factor offsets are after user SGPRs. */
3363 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
,
3364 GFX6_TCS_NUM_USER_SGPR
);
3365 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
,
3366 GFX6_TCS_NUM_USER_SGPR
+ 1);
3367 vgpr
= GFX6_TCS_NUM_USER_SGPR
+ 2;
3371 rel_patch_id
= ac_to_float(&ctx
->ac
, rel_patch_id
);
3372 invocation_id
= ac_to_float(&ctx
->ac
, invocation_id
);
3373 tf_lds_offset
= ac_to_float(&ctx
->ac
, tf_lds_offset
);
3375 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3376 * the invocation_id output does not alias the tcs_rel_ids input,
3377 * which saves a V_MOV on gfx9.
3381 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
3382 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
3384 if (ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
3385 vgpr
++; /* skip the tess factor LDS offset */
3386 for (unsigned i
= 0; i
< 6; i
++) {
3387 LLVMValueRef value
=
3388 LLVMBuildLoad(builder
, ctx
->invoc0_tess_factors
[i
], "");
3389 value
= ac_to_float(&ctx
->ac
, value
);
3390 ret
= LLVMBuildInsertValue(builder
, ret
, value
, vgpr
++, "");
3393 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
3395 ctx
->return_value
= ret
;
3398 /* Pass TCS inputs from LS to TCS on GFX9. */
3399 static void si_set_ls_return_value_for_tcs(struct si_shader_context
*ctx
)
3401 LLVMValueRef ret
= ctx
->return_value
;
3403 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3404 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3405 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3406 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3407 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3408 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3410 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3411 8 + SI_SGPR_RW_BUFFERS
);
3412 ret
= si_insert_input_ptr(ctx
, ret
,
3413 ctx
->param_bindless_samplers_and_images
,
3414 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3416 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_vs_state_bits
,
3417 8 + SI_SGPR_VS_STATE_BITS
);
3419 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3420 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3421 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_offsets
,
3422 8 + GFX9_SGPR_TCS_OUT_OFFSETS
);
3423 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3424 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3426 unsigned vgpr
= 8 + GFX9_TCS_NUM_USER_SGPR
;
3427 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3428 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_patch_id
),
3430 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3431 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
),
3433 ctx
->return_value
= ret
;
3436 /* Pass GS inputs from ES to GS on GFX9. */
3437 static void si_set_es_return_value_for_gs(struct si_shader_context
*ctx
)
3439 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3440 LLVMValueRef ret
= ctx
->return_value
;
3442 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3443 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3444 if (ctx
->shader
->key
.as_ngg
)
3445 ret
= LLVMBuildInsertValue(builder
, ret
, ctx
->gs_tg_info
, 2, "");
3447 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_gs2vs_offset
, 2);
3448 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3449 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3451 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3452 8 + SI_SGPR_RW_BUFFERS
);
3453 ret
= si_insert_input_ptr(ctx
, ret
,
3454 ctx
->param_bindless_samplers_and_images
,
3455 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3456 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
3457 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_vs_state_bits
,
3458 8 + SI_SGPR_VS_STATE_BITS
);
3462 if (ctx
->type
== PIPE_SHADER_VERTEX
)
3463 vgpr
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
3465 vgpr
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
3467 for (unsigned i
= 0; i
< 5; i
++) {
3468 unsigned param
= ctx
->param_gs_vtx01_offset
+ i
;
3469 ret
= si_insert_input_ret_float(ctx
, ret
, param
, vgpr
++);
3471 ctx
->return_value
= ret
;
3474 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi
*abi
,
3475 unsigned max_outputs
,
3476 LLVMValueRef
*addrs
)
3478 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3479 struct si_shader
*shader
= ctx
->shader
;
3480 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3482 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->main_fn
,
3483 ctx
->param_rel_auto_id
);
3484 LLVMValueRef vertex_dw_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3485 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3486 vertex_dw_stride
, "");
3488 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3489 * its inputs from it. */
3490 for (i
= 0; i
< info
->num_outputs
; i
++) {
3491 unsigned name
= info
->output_semantic_name
[i
];
3492 unsigned index
= info
->output_semantic_index
[i
];
3494 /* The ARB_shader_viewport_layer_array spec contains the
3497 * 2) What happens if gl_ViewportIndex or gl_Layer is
3498 * written in the vertex shader and a geometry shader is
3501 * RESOLVED: The value written by the last vertex processing
3502 * stage is used. If the last vertex processing stage
3503 * (vertex, tessellation evaluation or geometry) does not
3504 * statically assign to gl_ViewportIndex or gl_Layer, index
3505 * or layer zero is assumed.
3507 * So writes to those outputs in VS-as-LS are simply ignored.
3509 if (name
== TGSI_SEMANTIC_LAYER
||
3510 name
== TGSI_SEMANTIC_VIEWPORT_INDEX
)
3513 int param
= si_shader_io_get_unique_index(name
, index
, false);
3514 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3515 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
3517 for (chan
= 0; chan
< 4; chan
++) {
3518 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3521 lshs_lds_store(ctx
, chan
, dw_addr
,
3522 LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], ""));
3526 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3527 si_set_ls_return_value_for_tcs(ctx
);
3530 static void si_llvm_emit_es_epilogue(struct ac_shader_abi
*abi
,
3531 unsigned max_outputs
,
3532 LLVMValueRef
*addrs
)
3534 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3535 struct si_shader
*es
= ctx
->shader
;
3536 struct tgsi_shader_info
*info
= &es
->selector
->info
;
3537 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
3538 ctx
->param_es2gs_offset
);
3539 LLVMValueRef lds_base
= NULL
;
3543 if (ctx
->screen
->info
.chip_class
>= GFX9
&& info
->num_outputs
) {
3544 unsigned itemsize_dw
= es
->selector
->esgs_itemsize
/ 4;
3545 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3546 LLVMValueRef wave_idx
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 24, 4);
3547 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3548 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3549 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
3550 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3551 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
3554 for (i
= 0; i
< info
->num_outputs
; i
++) {
3557 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
3558 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
3561 param
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
3562 info
->output_semantic_index
[i
], false);
3564 for (chan
= 0; chan
< 4; chan
++) {
3565 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3568 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3569 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3571 /* GFX9 has the ESGS ring in LDS. */
3572 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3573 LLVMValueRef idx
= LLVMConstInt(ctx
->i32
, param
* 4 + chan
, false);
3574 idx
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
, idx
, "");
3575 ac_build_indexed_store(&ctx
->ac
, ctx
->esgs_ring
, idx
, out_val
);
3579 ac_build_buffer_store_dword(&ctx
->ac
,
3581 out_val
, 1, NULL
, soffset
,
3582 (4 * param
+ chan
) * 4,
3587 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3588 si_set_es_return_value_for_gs(ctx
);
3591 static LLVMValueRef
si_get_gs_wave_id(struct si_shader_context
*ctx
)
3593 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3594 return si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 16, 8);
3596 return LLVMGetParam(ctx
->main_fn
, ctx
->param_gs_wave_id
);
3599 static void emit_gs_epilogue(struct si_shader_context
*ctx
)
3601 if (ctx
->shader
->key
.as_ngg
) {
3602 gfx10_ngg_gs_emit_epilogue(ctx
);
3606 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
,
3607 si_get_gs_wave_id(ctx
));
3609 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3610 lp_build_endif(&ctx
->merged_wrap_if_state
);
3613 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi
*abi
,
3614 unsigned max_outputs
,
3615 LLVMValueRef
*addrs
)
3617 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3618 struct tgsi_shader_info UNUSED
*info
= &ctx
->shader
->selector
->info
;
3620 assert(info
->num_outputs
<= max_outputs
);
3622 emit_gs_epilogue(ctx
);
3625 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3627 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3628 emit_gs_epilogue(ctx
);
3631 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi
*abi
,
3632 unsigned max_outputs
,
3633 LLVMValueRef
*addrs
)
3635 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3636 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3637 struct si_shader_output_values
*outputs
= NULL
;
3640 assert(!ctx
->shader
->is_gs_copy_shader
);
3641 assert(info
->num_outputs
<= max_outputs
);
3643 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
3645 for (i
= 0; i
< info
->num_outputs
; i
++) {
3646 outputs
[i
].semantic_name
= info
->output_semantic_name
[i
];
3647 outputs
[i
].semantic_index
= info
->output_semantic_index
[i
];
3649 for (j
= 0; j
< 4; j
++) {
3650 outputs
[i
].values
[j
] =
3651 LLVMBuildLoad(ctx
->ac
.builder
,
3654 outputs
[i
].vertex_stream
[j
] =
3655 (info
->output_streams
[i
] >> (2 * j
)) & 3;
3659 if (ctx
->ac
.chip_class
<= GFX9
&&
3660 ctx
->shader
->selector
->so
.num_outputs
)
3661 si_llvm_emit_streamout(ctx
, outputs
, i
, 0);
3663 /* Export PrimitiveID. */
3664 if (ctx
->shader
->key
.mono
.u
.vs_export_prim_id
) {
3665 outputs
[i
].semantic_name
= TGSI_SEMANTIC_PRIMID
;
3666 outputs
[i
].semantic_index
= 0;
3667 outputs
[i
].values
[0] = ac_to_float(&ctx
->ac
, si_get_primitive_id(ctx
, 0));
3668 for (j
= 1; j
< 4; j
++)
3669 outputs
[i
].values
[j
] = LLVMConstReal(ctx
->f32
, 0);
3671 memset(outputs
[i
].vertex_stream
, 0,
3672 sizeof(outputs
[i
].vertex_stream
));
3676 si_llvm_export_vs(ctx
, outputs
, i
);
3680 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi
*abi
,
3681 unsigned max_outputs
,
3682 LLVMValueRef
*addrs
)
3684 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3685 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3686 LLVMValueRef pos
[4] = {};
3688 assert(info
->num_outputs
<= max_outputs
);
3690 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3691 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_POSITION
)
3694 for (unsigned chan
= 0; chan
< 4; chan
++)
3695 pos
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3698 assert(pos
[0] != NULL
);
3700 /* Return the position output. */
3701 LLVMValueRef ret
= ctx
->return_value
;
3702 for (unsigned chan
= 0; chan
< 4; chan
++)
3703 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, pos
[chan
], chan
, "");
3704 ctx
->return_value
= ret
;
3707 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context
*bld_base
)
3709 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3711 ctx
->abi
.emit_outputs(&ctx
->abi
, RADEON_LLVM_MAX_OUTPUTS
,
3712 &ctx
->outputs
[0][0]);
3715 struct si_ps_exports
{
3717 struct ac_export_args args
[10];
3720 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
3721 LLVMValueRef depth
, LLVMValueRef stencil
,
3722 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
3724 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3725 struct ac_export_args args
;
3727 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3729 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3732 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
3733 LLVMValueRef
*color
, unsigned index
,
3734 unsigned samplemask_param
,
3735 bool is_last
, struct si_ps_exports
*exp
)
3737 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3741 if (ctx
->shader
->key
.part
.ps
.epilog
.clamp_color
)
3742 for (i
= 0; i
< 4; i
++)
3743 color
[i
] = ac_build_clamp(&ctx
->ac
, color
[i
]);
3746 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_to_one
)
3747 color
[3] = ctx
->ac
.f32_1
;
3751 ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
3752 si_alpha_test(bld_base
, color
[3]);
3754 /* Line & polygon smoothing */
3755 if (ctx
->shader
->key
.part
.ps
.epilog
.poly_line_smoothing
)
3756 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3759 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3760 if (ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
> 0) {
3761 struct ac_export_args args
[8];
3764 /* Get the export arguments, also find out what the last one is. */
3765 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3766 si_llvm_init_export_args(ctx
, color
,
3767 V_008DFC_SQ_EXP_MRT
+ c
, &args
[c
]);
3768 if (args
[c
].enabled_channels
)
3772 /* Emit all exports. */
3773 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3774 if (is_last
&& last
== c
) {
3775 args
[c
].valid_mask
= 1; /* whether the EXEC mask is valid */
3776 args
[c
].done
= 1; /* DONE bit */
3777 } else if (!args
[c
].enabled_channels
)
3778 continue; /* unnecessary NULL export */
3780 memcpy(&exp
->args
[exp
->num
++], &args
[c
], sizeof(args
[c
]));
3783 struct ac_export_args args
;
3786 si_llvm_init_export_args(ctx
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3789 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3790 args
.done
= 1; /* DONE bit */
3791 } else if (!args
.enabled_channels
)
3792 return; /* unnecessary NULL export */
3794 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3798 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3799 struct si_ps_exports
*exp
)
3801 for (unsigned i
= 0; i
< exp
->num
; i
++)
3802 ac_build_export(&ctx
->ac
, &exp
->args
[i
]);
3806 * Return PS outputs in this order:
3808 * v[0:3] = color0.xyzw
3809 * v[4:7] = color1.xyzw
3814 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3816 * The alpha-ref SGPR is returned via its original location.
3818 static void si_llvm_return_fs_outputs(struct ac_shader_abi
*abi
,
3819 unsigned max_outputs
,
3820 LLVMValueRef
*addrs
)
3822 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3823 struct si_shader
*shader
= ctx
->shader
;
3824 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3825 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3826 unsigned i
, j
, first_vgpr
, vgpr
;
3828 LLVMValueRef color
[8][4] = {};
3829 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3832 if (ctx
->postponed_kill
)
3833 ac_build_kill_if_false(&ctx
->ac
, LLVMBuildLoad(builder
, ctx
->postponed_kill
, ""));
3835 /* Read the output values. */
3836 for (i
= 0; i
< info
->num_outputs
; i
++) {
3837 unsigned semantic_name
= info
->output_semantic_name
[i
];
3838 unsigned semantic_index
= info
->output_semantic_index
[i
];
3840 switch (semantic_name
) {
3841 case TGSI_SEMANTIC_COLOR
:
3842 assert(semantic_index
< 8);
3843 for (j
= 0; j
< 4; j
++) {
3844 LLVMValueRef ptr
= addrs
[4 * i
+ j
];
3845 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3846 color
[semantic_index
][j
] = result
;
3849 case TGSI_SEMANTIC_POSITION
:
3850 depth
= LLVMBuildLoad(builder
,
3851 addrs
[4 * i
+ 2], "");
3853 case TGSI_SEMANTIC_STENCIL
:
3854 stencil
= LLVMBuildLoad(builder
,
3855 addrs
[4 * i
+ 1], "");
3857 case TGSI_SEMANTIC_SAMPLEMASK
:
3858 samplemask
= LLVMBuildLoad(builder
,
3859 addrs
[4 * i
+ 0], "");
3862 fprintf(stderr
, "Warning: GFX6 unhandled fs output type:%d\n",
3867 /* Fill the return structure. */
3868 ret
= ctx
->return_value
;
3871 ret
= LLVMBuildInsertValue(builder
, ret
,
3872 ac_to_integer(&ctx
->ac
,
3873 LLVMGetParam(ctx
->main_fn
,
3874 SI_PARAM_ALPHA_REF
)),
3875 SI_SGPR_ALPHA_REF
, "");
3878 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3879 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3883 for (j
= 0; j
< 4; j
++)
3884 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3887 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3889 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3891 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3893 /* Add the input sample mask for smoothing at the end. */
3894 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3895 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3896 ret
= LLVMBuildInsertValue(builder
, ret
,
3897 LLVMGetParam(ctx
->main_fn
,
3898 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3900 ctx
->return_value
= ret
;
3903 static void membar_emit(
3904 const struct lp_build_tgsi_action
*action
,
3905 struct lp_build_tgsi_context
*bld_base
,
3906 struct lp_build_emit_data
*emit_data
)
3908 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3909 LLVMValueRef src0
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
3910 unsigned flags
= LLVMConstIntGetZExtValue(src0
);
3911 unsigned waitcnt
= NOOP_WAITCNT
;
3913 if (flags
& TGSI_MEMBAR_THREAD_GROUP
)
3914 waitcnt
&= VM_CNT
& LGKM_CNT
;
3916 if (flags
& (TGSI_MEMBAR_ATOMIC_BUFFER
|
3917 TGSI_MEMBAR_SHADER_BUFFER
|
3918 TGSI_MEMBAR_SHADER_IMAGE
))
3921 if (flags
& TGSI_MEMBAR_SHARED
)
3922 waitcnt
&= LGKM_CNT
;
3924 if (waitcnt
!= NOOP_WAITCNT
)
3925 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3928 static void clock_emit(
3929 const struct lp_build_tgsi_action
*action
,
3930 struct lp_build_tgsi_context
*bld_base
,
3931 struct lp_build_emit_data
*emit_data
)
3933 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3934 LLVMValueRef tmp
= ac_build_shader_clock(&ctx
->ac
);
3936 emit_data
->output
[0] =
3937 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_0
, "");
3938 emit_data
->output
[1] =
3939 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_1
, "");
3942 static void si_llvm_emit_ddxy(
3943 const struct lp_build_tgsi_action
*action
,
3944 struct lp_build_tgsi_context
*bld_base
,
3945 struct lp_build_emit_data
*emit_data
)
3947 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3948 unsigned opcode
= emit_data
->info
->opcode
;
3953 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3954 mask
= AC_TID_MASK_LEFT
;
3955 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3956 mask
= AC_TID_MASK_TOP
;
3958 mask
= AC_TID_MASK_TOP_LEFT
;
3960 /* for DDX we want to next X pixel, DDY next Y pixel. */
3961 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
3963 val
= ac_to_integer(&ctx
->ac
, emit_data
->args
[0]);
3964 val
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, val
);
3965 emit_data
->output
[emit_data
->chan
] = val
;
3968 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
3969 struct lp_build_tgsi_context
*bld_base
,
3970 struct lp_build_emit_data
*emit_data
)
3972 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3973 struct si_shader
*shader
= ctx
->shader
;
3974 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3975 LLVMValueRef interp_param
;
3976 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3977 const struct tgsi_full_src_register
*input
= &inst
->Src
[0];
3978 int input_base
, input_array_size
;
3981 LLVMValueRef prim_mask
= ctx
->abi
.prim_mask
;
3982 LLVMValueRef array_idx
, offset_x
= NULL
, offset_y
= NULL
;
3983 int interp_param_idx
;
3987 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
3988 /* offset is in second src, first two channels */
3989 offset_x
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 1,
3991 offset_y
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 1,
3993 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3994 LLVMValueRef sample_position
;
3995 LLVMValueRef sample_id
;
3996 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
3998 /* fetch sample ID, then fetch its sample position,
3999 * and place into first two channels.
4001 sample_id
= lp_build_emit_fetch(bld_base
,
4002 emit_data
->inst
, 1, TGSI_CHAN_X
);
4003 sample_id
= ac_to_integer(&ctx
->ac
, sample_id
);
4005 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4006 * Language 4.50 spec says about interpolateAtSample:
4008 * "Returns the value of the input interpolant variable at
4009 * the location of sample number sample. If multisample
4010 * buffers are not available, the input variable will be
4011 * evaluated at the center of the pixel. If sample sample
4012 * does not exist, the position used to interpolate the
4013 * input variable is undefined."
4015 * This means that sample_id values outside of the valid are
4016 * in fact valid input, and the usual mechanism for loading the
4017 * sample position doesn't work.
4019 if (ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
) {
4020 LLVMValueRef center
[4] = {
4021 LLVMConstReal(ctx
->f32
, 0.5),
4022 LLVMConstReal(ctx
->f32
, 0.5),
4027 sample_position
= ac_build_gather_values(&ctx
->ac
, center
, 4);
4029 sample_position
= load_sample_position(&ctx
->abi
, sample_id
);
4032 offset_x
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
,
4035 offset_x
= LLVMBuildFSub(ctx
->ac
.builder
, offset_x
, halfval
, "");
4036 offset_y
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
,
4038 offset_y
= LLVMBuildFSub(ctx
->ac
.builder
, offset_y
, halfval
, "");
4041 assert(input
->Register
.File
== TGSI_FILE_INPUT
);
4043 if (input
->Register
.Indirect
) {
4044 unsigned array_id
= input
->Indirect
.ArrayID
;
4047 input_base
= info
->input_array_first
[array_id
];
4048 input_array_size
= info
->input_array_last
[array_id
] - input_base
+ 1;
4050 input_base
= inst
->Src
[0].Register
.Index
;
4051 input_array_size
= info
->num_inputs
- input_base
;
4054 array_idx
= si_get_indirect_index(ctx
, &input
->Indirect
,
4055 1, input
->Register
.Index
- input_base
);
4057 input_base
= inst
->Src
[0].Register
.Index
;
4058 input_array_size
= 1;
4059 array_idx
= ctx
->i32_0
;
4062 interp
= shader
->selector
->info
.input_interpolate
[input_base
];
4064 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4065 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
4066 location
= TGSI_INTERPOLATE_LOC_CENTER
;
4068 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
4070 interp_param_idx
= lookup_interp_param_index(interp
, location
);
4071 if (interp_param_idx
== -1)
4073 else if (interp_param_idx
)
4074 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
4076 interp_param
= NULL
;
4078 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4079 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4080 LLVMValueRef ij_out
[2];
4081 LLVMValueRef ddxy_out
= ac_build_ddxy_interp(&ctx
->ac
, interp_param
);
4084 * take the I then J parameters, and the DDX/Y for it, and
4085 * calculate the IJ inputs for the interpolator.
4086 * temp1 = ddx * offset/sample.x + I;
4087 * interp_param.I = ddy * offset/sample.y + temp1;
4088 * temp1 = ddx * offset/sample.x + J;
4089 * interp_param.J = ddy * offset/sample.y + temp1;
4091 for (i
= 0; i
< 2; i
++) {
4092 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, 0);
4093 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, 0);
4094 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4095 ddxy_out
, ix_ll
, "");
4096 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4097 ddxy_out
, iy_ll
, "");
4098 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4099 interp_param
, ix_ll
, "");
4102 interp_el
= ac_to_float(&ctx
->ac
, interp_el
);
4104 temp
= ac_build_fmad(&ctx
->ac
, ddx_el
, offset_x
, interp_el
);
4105 ij_out
[i
] = ac_build_fmad(&ctx
->ac
, ddy_el
, offset_y
, temp
);
4107 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4111 interp_param
= ac_to_float(&ctx
->ac
, interp_param
);
4113 for (chan
= 0; chan
< 4; chan
++) {
4114 LLVMValueRef gather
= LLVMGetUndef(LLVMVectorType(ctx
->f32
, input_array_size
));
4115 unsigned schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
4117 for (unsigned idx
= 0; idx
< input_array_size
; ++idx
) {
4118 LLVMValueRef v
, i
= NULL
, j
= NULL
;
4121 i
= LLVMBuildExtractElement(
4122 ctx
->ac
.builder
, interp_param
, ctx
->i32_0
, "");
4123 j
= LLVMBuildExtractElement(
4124 ctx
->ac
.builder
, interp_param
, ctx
->i32_1
, "");
4126 v
= si_build_fs_interp(ctx
, input_base
+ idx
, schan
,
4129 gather
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4130 gather
, v
, LLVMConstInt(ctx
->i32
, idx
, false), "");
4133 emit_data
->output
[chan
] = LLVMBuildExtractElement(
4134 ctx
->ac
.builder
, gather
, array_idx
, "");
4138 static void vote_all_emit(
4139 const struct lp_build_tgsi_action
*action
,
4140 struct lp_build_tgsi_context
*bld_base
,
4141 struct lp_build_emit_data
*emit_data
)
4143 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4145 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, emit_data
->args
[0]);
4146 emit_data
->output
[emit_data
->chan
] =
4147 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4150 static void vote_any_emit(
4151 const struct lp_build_tgsi_action
*action
,
4152 struct lp_build_tgsi_context
*bld_base
,
4153 struct lp_build_emit_data
*emit_data
)
4155 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4157 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, emit_data
->args
[0]);
4158 emit_data
->output
[emit_data
->chan
] =
4159 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4162 static void vote_eq_emit(
4163 const struct lp_build_tgsi_action
*action
,
4164 struct lp_build_tgsi_context
*bld_base
,
4165 struct lp_build_emit_data
*emit_data
)
4167 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4169 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, emit_data
->args
[0]);
4170 emit_data
->output
[emit_data
->chan
] =
4171 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4174 static void ballot_emit(
4175 const struct lp_build_tgsi_action
*action
,
4176 struct lp_build_tgsi_context
*bld_base
,
4177 struct lp_build_emit_data
*emit_data
)
4179 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4180 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4183 tmp
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4184 tmp
= ac_build_ballot(&ctx
->ac
, tmp
);
4185 tmp
= LLVMBuildBitCast(builder
, tmp
, ctx
->v2i32
, "");
4187 emit_data
->output
[0] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_0
, "");
4188 emit_data
->output
[1] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_1
, "");
4191 static void read_lane_emit(
4192 const struct lp_build_tgsi_action
*action
,
4193 struct lp_build_tgsi_context
*bld_base
,
4194 struct lp_build_emit_data
*emit_data
)
4196 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4198 if (emit_data
->inst
->Instruction
.Opcode
== TGSI_OPCODE_READ_INVOC
) {
4199 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4200 0, emit_data
->src_chan
);
4202 /* Always read the source invocation (= lane) from the X channel. */
4203 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4205 emit_data
->arg_count
= 2;
4208 /* We currently have no other way to prevent LLVM from lifting the icmp
4209 * calls to a dominating basic block.
4211 ac_build_optimization_barrier(&ctx
->ac
, &emit_data
->args
[0]);
4213 for (unsigned i
= 0; i
< emit_data
->arg_count
; ++i
)
4214 emit_data
->args
[i
] = ac_to_integer(&ctx
->ac
, emit_data
->args
[i
]);
4216 emit_data
->output
[emit_data
->chan
] =
4217 ac_build_intrinsic(&ctx
->ac
, action
->intr_name
,
4218 ctx
->i32
, emit_data
->args
, emit_data
->arg_count
,
4219 AC_FUNC_ATTR_READNONE
|
4220 AC_FUNC_ATTR_CONVERGENT
);
4223 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
4224 struct lp_build_emit_data
*emit_data
)
4226 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4227 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
4231 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
4233 imm
= ctx
->imms
[src0
.Index
* TGSI_NUM_CHANNELS
+ src0
.SwizzleX
];
4234 stream
= LLVMConstIntGetZExtValue(imm
) & 0x3;
4238 /* Emit one vertex from the geometry shader */
4239 static void si_llvm_emit_vertex(struct ac_shader_abi
*abi
,
4241 LLVMValueRef
*addrs
)
4243 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4245 if (ctx
->shader
->key
.as_ngg
) {
4246 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
4250 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
4251 struct si_shader
*shader
= ctx
->shader
;
4252 struct lp_build_if_state if_state
;
4253 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
4254 ctx
->param_gs2vs_offset
);
4255 LLVMValueRef gs_next_vertex
;
4256 LLVMValueRef can_emit
;
4257 unsigned chan
, offset
;
4260 /* Write vertex attribute values to GSVS ring */
4261 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4262 ctx
->gs_next_vertex
[stream
],
4265 /* If this thread has already emitted the declared maximum number of
4266 * vertices, skip the write: excessive vertex emissions are not
4267 * supposed to have any effect.
4269 * If the shader has no writes to memory, kill it instead. This skips
4270 * further memory loads and may allow LLVM to skip to the end
4273 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4274 LLVMConstInt(ctx
->i32
,
4275 shader
->selector
->gs_max_out_vertices
, 0), "");
4277 bool use_kill
= !info
->writes_memory
;
4279 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4281 lp_build_if(&if_state
, &ctx
->gallivm
, can_emit
);
4285 for (i
= 0; i
< info
->num_outputs
; i
++) {
4286 for (chan
= 0; chan
< 4; chan
++) {
4287 if (!(info
->output_usagemask
[i
] & (1 << chan
)) ||
4288 ((info
->output_streams
[i
] >> (2 * chan
)) & 3) != stream
)
4291 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
4292 LLVMValueRef voffset
=
4293 LLVMConstInt(ctx
->i32
, offset
*
4294 shader
->selector
->gs_max_out_vertices
, 0);
4297 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4298 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
,
4299 LLVMConstInt(ctx
->i32
, 4, 0), "");
4301 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4303 ac_build_buffer_store_dword(&ctx
->ac
,
4304 ctx
->gsvs_ring
[stream
],
4306 voffset
, soffset
, 0,
4311 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
, ctx
->i32_1
, "");
4312 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
4314 /* Signal vertex emission if vertex data was written. */
4316 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
4317 si_get_gs_wave_id(ctx
));
4321 lp_build_endif(&if_state
);
4324 /* Emit one vertex from the geometry shader */
4325 static void si_tgsi_emit_vertex(
4326 const struct lp_build_tgsi_action
*action
,
4327 struct lp_build_tgsi_context
*bld_base
,
4328 struct lp_build_emit_data
*emit_data
)
4330 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4331 unsigned stream
= si_llvm_get_stream(bld_base
, emit_data
);
4333 si_llvm_emit_vertex(&ctx
->abi
, stream
, ctx
->outputs
[0]);
4336 /* Cut one primitive from the geometry shader */
4337 static void si_llvm_emit_primitive(struct ac_shader_abi
*abi
,
4340 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4342 if (ctx
->shader
->key
.as_ngg
) {
4343 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
4347 /* Signal primitive cut */
4348 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8),
4349 si_get_gs_wave_id(ctx
));
4352 /* Cut one primitive from the geometry shader */
4353 static void si_tgsi_emit_primitive(
4354 const struct lp_build_tgsi_action
*action
,
4355 struct lp_build_tgsi_context
*bld_base
,
4356 struct lp_build_emit_data
*emit_data
)
4358 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4360 si_llvm_emit_primitive(&ctx
->abi
, si_llvm_get_stream(bld_base
, emit_data
));
4363 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
4364 struct lp_build_tgsi_context
*bld_base
,
4365 struct lp_build_emit_data
*emit_data
)
4367 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4369 /* GFX6 only (thanks to a hw bug workaround):
4370 * The real barrier instruction isn’t needed, because an entire patch
4371 * always fits into a single wave.
4373 if (ctx
->screen
->info
.chip_class
== GFX6
&&
4374 ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
4375 ac_build_waitcnt(&ctx
->ac
, LGKM_CNT
& VM_CNT
);
4379 ac_build_s_barrier(&ctx
->ac
);
4382 void si_create_function(struct si_shader_context
*ctx
,
4384 LLVMTypeRef
*returns
, unsigned num_returns
,
4385 struct si_function_info
*fninfo
,
4386 unsigned max_workgroup_size
)
4390 si_llvm_create_func(ctx
, name
, returns
, num_returns
,
4391 fninfo
->types
, fninfo
->num_params
);
4392 ctx
->return_value
= LLVMGetUndef(ctx
->return_type
);
4394 for (i
= 0; i
< fninfo
->num_sgpr_params
; ++i
) {
4395 LLVMValueRef P
= LLVMGetParam(ctx
->main_fn
, i
);
4397 /* The combination of:
4401 * allows the optimization passes to move loads and reduces
4402 * SGPR spilling significantly.
4404 ac_add_function_attr(ctx
->ac
.context
, ctx
->main_fn
, i
+ 1,
4405 AC_FUNC_ATTR_INREG
);
4407 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
4408 ac_add_function_attr(ctx
->ac
.context
, ctx
->main_fn
, i
+ 1,
4409 AC_FUNC_ATTR_NOALIAS
);
4410 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
4414 for (i
= 0; i
< fninfo
->num_params
; ++i
) {
4415 if (fninfo
->assign
[i
])
4416 *fninfo
->assign
[i
] = LLVMGetParam(ctx
->main_fn
, i
);
4419 if (ctx
->screen
->info
.address32_hi
) {
4420 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4421 "amdgpu-32bit-address-high-bits",
4422 ctx
->screen
->info
.address32_hi
);
4425 ac_llvm_set_workgroup_size(ctx
->main_fn
, max_workgroup_size
);
4427 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4428 "no-signed-zeros-fp-math",
4431 if (ctx
->screen
->debug_flags
& DBG(UNSAFE_MATH
)) {
4432 /* These were copied from some LLVM test. */
4433 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4434 "less-precise-fpmad",
4436 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4439 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4442 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4448 static void declare_streamout_params(struct si_shader_context
*ctx
,
4449 struct pipe_stream_output_info
*so
,
4450 struct si_function_info
*fninfo
)
4452 if (ctx
->ac
.chip_class
>= GFX10
)
4455 /* Streamout SGPRs. */
4456 if (so
->num_outputs
) {
4457 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
4458 ctx
->param_streamout_config
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4460 ctx
->param_streamout_config
= fninfo
->num_params
- 1;
4462 ctx
->param_streamout_write_index
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4464 /* A streamout buffer offset is loaded if the stride is non-zero. */
4465 for (int i
= 0; i
< 4; i
++) {
4469 ctx
->param_streamout_offset
[i
] = add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4473 static unsigned si_get_max_workgroup_size(const struct si_shader
*shader
)
4475 switch (shader
->selector
->type
) {
4476 case PIPE_SHADER_VERTEX
:
4477 case PIPE_SHADER_TESS_EVAL
:
4478 return shader
->key
.as_ngg
? 128 : 0;
4480 case PIPE_SHADER_TESS_CTRL
:
4481 /* Return this so that LLVM doesn't remove s_barrier
4482 * instructions on chips where we use s_barrier. */
4483 return shader
->selector
->screen
->info
.chip_class
>= GFX7
? 128 : 64;
4485 case PIPE_SHADER_GEOMETRY
:
4486 return shader
->selector
->screen
->info
.chip_class
>= GFX9
? 128 : 64;
4488 case PIPE_SHADER_COMPUTE
:
4489 break; /* see below */
4495 const unsigned *properties
= shader
->selector
->info
.properties
;
4496 unsigned max_work_group_size
=
4497 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
4498 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
4499 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
4501 if (!max_work_group_size
) {
4502 /* This is a variable group size compute shader,
4503 * compile it for the maximum possible group size.
4505 max_work_group_size
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
4507 return max_work_group_size
;
4510 static void declare_const_and_shader_buffers(struct si_shader_context
*ctx
,
4511 struct si_function_info
*fninfo
,
4514 LLVMTypeRef const_shader_buf_type
;
4516 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
4517 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
4518 const_shader_buf_type
= ctx
->f32
;
4520 const_shader_buf_type
= ctx
->v4i32
;
4522 unsigned const_and_shader_buffers
=
4523 add_arg(fninfo
, ARG_SGPR
,
4524 ac_array_in_const32_addr_space(const_shader_buf_type
));
4527 ctx
->param_const_and_shader_buffers
= const_and_shader_buffers
;
4530 static void declare_samplers_and_images(struct si_shader_context
*ctx
,
4531 struct si_function_info
*fninfo
,
4534 unsigned samplers_and_images
=
4535 add_arg(fninfo
, ARG_SGPR
,
4536 ac_array_in_const32_addr_space(ctx
->v8i32
));
4539 ctx
->param_samplers_and_images
= samplers_and_images
;
4542 static void declare_per_stage_desc_pointers(struct si_shader_context
*ctx
,
4543 struct si_function_info
*fninfo
,
4546 declare_const_and_shader_buffers(ctx
, fninfo
, assign_params
);
4547 declare_samplers_and_images(ctx
, fninfo
, assign_params
);
4550 static void declare_global_desc_pointers(struct si_shader_context
*ctx
,
4551 struct si_function_info
*fninfo
)
4553 ctx
->param_rw_buffers
= add_arg(fninfo
, ARG_SGPR
,
4554 ac_array_in_const32_addr_space(ctx
->v4i32
));
4555 ctx
->param_bindless_samplers_and_images
= add_arg(fninfo
, ARG_SGPR
,
4556 ac_array_in_const32_addr_space(ctx
->v8i32
));
4559 static void declare_vs_specific_input_sgprs(struct si_shader_context
*ctx
,
4560 struct si_function_info
*fninfo
)
4562 ctx
->param_vs_state_bits
= add_arg(fninfo
, ARG_SGPR
, ctx
->i32
);
4563 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.base_vertex
);
4564 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.start_instance
);
4565 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.draw_id
);
4568 static void declare_vs_input_vgprs(struct si_shader_context
*ctx
,
4569 struct si_function_info
*fninfo
,
4570 unsigned *num_prolog_vgprs
)
4572 struct si_shader
*shader
= ctx
->shader
;
4574 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.vertex_id
);
4575 if (shader
->key
.as_ls
) {
4576 ctx
->param_rel_auto_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4577 if (ctx
->screen
->info
.chip_class
>= GFX10
) {
4578 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* user VGPR */
4579 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4581 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4582 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4584 } else if (ctx
->screen
->info
.chip_class
== GFX10
&&
4585 !shader
->is_gs_copy_shader
) {
4586 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* user vgpr */
4587 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* user vgpr */
4588 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4590 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4591 ctx
->param_vs_prim_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4592 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4595 if (!shader
->is_gs_copy_shader
) {
4596 /* Vertex load indices. */
4597 ctx
->param_vertex_index0
= fninfo
->num_params
;
4598 for (unsigned i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
4599 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4600 *num_prolog_vgprs
+= shader
->selector
->info
.num_inputs
;
4604 static void declare_vs_blit_inputs(struct si_shader_context
*ctx
,
4605 struct si_function_info
*fninfo
,
4606 unsigned vs_blit_property
)
4608 ctx
->param_vs_blit_inputs
= fninfo
->num_params
;
4609 add_arg(fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x1, y1 */
4610 add_arg(fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x2, y2 */
4611 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* depth */
4613 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
4614 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* color0 */
4615 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* color1 */
4616 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* color2 */
4617 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* color3 */
4618 } else if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
) {
4619 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x1 */
4620 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y1 */
4621 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x2 */
4622 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y2 */
4623 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.z */
4624 add_arg(fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.w */
4628 static void declare_tes_input_vgprs(struct si_shader_context
*ctx
,
4629 struct si_function_info
*fninfo
)
4631 ctx
->param_tes_u
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4632 ctx
->param_tes_v
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4633 ctx
->param_tes_rel_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4634 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tes_patch_id
);
4638 /* Convenient merged shader definitions. */
4639 SI_SHADER_MERGED_VERTEX_TESSCTRL
= PIPE_SHADER_TYPES
,
4640 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
,
4643 static void create_function(struct si_shader_context
*ctx
)
4645 struct si_shader
*shader
= ctx
->shader
;
4646 struct si_function_info fninfo
;
4647 LLVMTypeRef returns
[16+32*4];
4648 unsigned i
, num_return_sgprs
;
4649 unsigned num_returns
= 0;
4650 unsigned num_prolog_vgprs
= 0;
4651 unsigned type
= ctx
->type
;
4652 unsigned vs_blit_property
=
4653 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
4655 si_init_function_info(&fninfo
);
4657 /* Set MERGED shaders. */
4658 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
4659 if (shader
->key
.as_ls
|| type
== PIPE_SHADER_TESS_CTRL
)
4660 type
= SI_SHADER_MERGED_VERTEX_TESSCTRL
; /* LS or HS */
4661 else if (shader
->key
.as_es
|| shader
->key
.as_ngg
|| type
== PIPE_SHADER_GEOMETRY
)
4662 type
= SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
;
4665 LLVMTypeRef v3i32
= LLVMVectorType(ctx
->i32
, 3);
4668 case PIPE_SHADER_VERTEX
:
4669 declare_global_desc_pointers(ctx
, &fninfo
);
4671 if (vs_blit_property
) {
4672 declare_vs_blit_inputs(ctx
, &fninfo
, vs_blit_property
);
4675 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4679 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4680 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4681 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4682 ac_array_in_const32_addr_space(ctx
->v4i32
));
4684 if (shader
->key
.as_es
) {
4685 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4686 } else if (shader
->key
.as_ls
) {
4687 /* no extra parameters */
4689 if (shader
->is_gs_copy_shader
) {
4690 fninfo
.num_params
= ctx
->param_vs_state_bits
+ 1;
4691 fninfo
.num_sgpr_params
= fninfo
.num_params
;
4694 /* The locations of the other parameters are assigned dynamically. */
4695 declare_streamout_params(ctx
, &shader
->selector
->so
,
4700 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4703 if (shader
->key
.opt
.vs_as_prim_discard_cs
) {
4704 for (i
= 0; i
< 4; i
++)
4705 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4709 case PIPE_SHADER_TESS_CTRL
: /* GFX6-GFX8 */
4710 declare_global_desc_pointers(ctx
, &fninfo
);
4711 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4712 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4713 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4714 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4715 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4716 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4717 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4720 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4721 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4723 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4724 * placed after the user SGPRs.
4726 for (i
= 0; i
< GFX6_TCS_NUM_USER_SGPR
+ 2; i
++)
4727 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4728 for (i
= 0; i
< 11; i
++)
4729 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4732 case SI_SHADER_MERGED_VERTEX_TESSCTRL
:
4733 /* Merged stages have 8 system SGPRs at the beginning. */
4734 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4735 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4736 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4737 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4738 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4739 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4740 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4741 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4742 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4744 declare_global_desc_pointers(ctx
, &fninfo
);
4745 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4746 ctx
->type
== PIPE_SHADER_VERTEX
);
4747 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4749 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4750 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4751 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4752 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4753 ac_array_in_const32_addr_space(ctx
->v4i32
));
4755 /* VGPRs (first TCS, then VS) */
4756 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4757 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4759 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4760 declare_vs_input_vgprs(ctx
, &fninfo
,
4763 /* LS return values are inputs to the TCS main shader part. */
4764 for (i
= 0; i
< 8 + GFX9_TCS_NUM_USER_SGPR
; i
++)
4765 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4766 for (i
= 0; i
< 2; i
++)
4767 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4769 /* TCS return values are inputs to the TCS epilog.
4771 * param_tcs_offchip_offset, param_tcs_factor_offset,
4772 * param_tcs_offchip_layout, and param_rw_buffers
4773 * should be passed to the epilog.
4775 for (i
= 0; i
<= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
; i
++)
4776 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4777 for (i
= 0; i
< 11; i
++)
4778 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4782 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
:
4783 /* Merged stages have 8 system SGPRs at the beginning. */
4784 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4785 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4786 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4788 if (ctx
->shader
->key
.as_ngg
)
4789 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->gs_tg_info
);
4791 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4793 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4794 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4795 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4796 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4797 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4799 declare_global_desc_pointers(ctx
, &fninfo
);
4800 if (ctx
->type
!= PIPE_SHADER_VERTEX
|| !vs_blit_property
) {
4801 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4802 (ctx
->type
== PIPE_SHADER_VERTEX
||
4803 ctx
->type
== PIPE_SHADER_TESS_EVAL
));
4806 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4807 if (vs_blit_property
)
4808 declare_vs_blit_inputs(ctx
, &fninfo
, vs_blit_property
);
4810 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4812 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4813 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4814 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4815 /* Declare as many input SGPRs as the VS has. */
4818 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4819 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4820 ac_array_in_const32_addr_space(ctx
->v4i32
));
4823 /* VGPRs (first GS, then VS/TES) */
4824 ctx
->param_gs_vtx01_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4825 ctx
->param_gs_vtx23_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4826 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4827 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4828 ctx
->param_gs_vtx45_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4830 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4831 declare_vs_input_vgprs(ctx
, &fninfo
,
4833 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4834 declare_tes_input_vgprs(ctx
, &fninfo
);
4837 if (ctx
->shader
->key
.as_es
&&
4838 (ctx
->type
== PIPE_SHADER_VERTEX
||
4839 ctx
->type
== PIPE_SHADER_TESS_EVAL
)) {
4840 unsigned num_user_sgprs
;
4842 if (ctx
->type
== PIPE_SHADER_VERTEX
)
4843 num_user_sgprs
= GFX9_VSGS_NUM_USER_SGPR
;
4845 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
4847 /* ES return values are inputs to GS. */
4848 for (i
= 0; i
< 8 + num_user_sgprs
; i
++)
4849 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4850 for (i
= 0; i
< 5; i
++)
4851 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4855 case PIPE_SHADER_TESS_EVAL
:
4856 declare_global_desc_pointers(ctx
, &fninfo
);
4857 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4858 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4859 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4860 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4862 if (shader
->key
.as_es
) {
4863 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4864 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4865 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4867 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4868 declare_streamout_params(ctx
, &shader
->selector
->so
,
4870 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4874 declare_tes_input_vgprs(ctx
, &fninfo
);
4877 case PIPE_SHADER_GEOMETRY
:
4878 declare_global_desc_pointers(ctx
, &fninfo
);
4879 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4880 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4881 ctx
->param_gs_wave_id
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4884 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]);
4885 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]);
4886 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4887 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
4888 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
4889 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
4890 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
4891 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4894 case PIPE_SHADER_FRAGMENT
:
4895 declare_global_desc_pointers(ctx
, &fninfo
);
4896 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4897 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
4898 add_arg_assign_checked(&fninfo
, ARG_SGPR
, ctx
->i32
,
4899 &ctx
->abi
.prim_mask
, SI_PARAM_PRIM_MASK
);
4901 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_SAMPLE
);
4902 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTER
);
4903 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTROID
);
4904 add_arg_checked(&fninfo
, ARG_VGPR
, v3i32
, SI_PARAM_PERSP_PULL_MODEL
);
4905 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_SAMPLE
);
4906 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTER
);
4907 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTROID
);
4908 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->f32
, SI_PARAM_LINE_STIPPLE_TEX
);
4909 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4910 &ctx
->abi
.frag_pos
[0], SI_PARAM_POS_X_FLOAT
);
4911 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4912 &ctx
->abi
.frag_pos
[1], SI_PARAM_POS_Y_FLOAT
);
4913 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4914 &ctx
->abi
.frag_pos
[2], SI_PARAM_POS_Z_FLOAT
);
4915 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4916 &ctx
->abi
.frag_pos
[3], SI_PARAM_POS_W_FLOAT
);
4917 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4918 &ctx
->abi
.front_face
, SI_PARAM_FRONT_FACE
);
4919 shader
->info
.face_vgpr_index
= 20;
4920 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4921 &ctx
->abi
.ancillary
, SI_PARAM_ANCILLARY
);
4922 shader
->info
.ancillary_vgpr_index
= 21;
4923 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4924 &ctx
->abi
.sample_coverage
, SI_PARAM_SAMPLE_COVERAGE
);
4925 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->i32
, SI_PARAM_POS_FIXED_PT
);
4927 /* Color inputs from the prolog. */
4928 if (shader
->selector
->info
.colors_read
) {
4929 unsigned num_color_elements
=
4930 util_bitcount(shader
->selector
->info
.colors_read
);
4932 assert(fninfo
.num_params
+ num_color_elements
<= ARRAY_SIZE(fninfo
.types
));
4933 for (i
= 0; i
< num_color_elements
; i
++)
4934 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
4936 num_prolog_vgprs
+= num_color_elements
;
4939 /* Outputs for the epilog. */
4940 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
4943 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
4944 shader
->selector
->info
.writes_z
+
4945 shader
->selector
->info
.writes_stencil
+
4946 shader
->selector
->info
.writes_samplemask
+
4947 1 /* SampleMaskIn */;
4949 num_returns
= MAX2(num_returns
,
4951 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
4953 for (i
= 0; i
< num_return_sgprs
; i
++)
4954 returns
[i
] = ctx
->i32
;
4955 for (; i
< num_returns
; i
++)
4956 returns
[i
] = ctx
->f32
;
4959 case PIPE_SHADER_COMPUTE
:
4960 declare_global_desc_pointers(ctx
, &fninfo
);
4961 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4962 if (shader
->selector
->info
.uses_grid_size
)
4963 add_arg_assign(&fninfo
, ARG_SGPR
, v3i32
, &ctx
->abi
.num_work_groups
);
4964 if (shader
->selector
->info
.uses_block_size
&&
4965 shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
4966 ctx
->param_block_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
4968 unsigned cs_user_data_dwords
=
4969 shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_USER_DATA_DWORDS
];
4970 if (cs_user_data_dwords
) {
4971 ctx
->param_cs_user_data
= add_arg(&fninfo
, ARG_SGPR
,
4972 LLVMVectorType(ctx
->i32
, cs_user_data_dwords
));
4975 for (i
= 0; i
< 3; i
++) {
4976 ctx
->abi
.workgroup_ids
[i
] = NULL
;
4977 if (shader
->selector
->info
.uses_block_id
[i
])
4978 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.workgroup_ids
[i
]);
4981 add_arg_assign(&fninfo
, ARG_VGPR
, v3i32
, &ctx
->abi
.local_invocation_ids
);
4984 assert(0 && "unimplemented shader");
4988 si_create_function(ctx
, "main", returns
, num_returns
, &fninfo
,
4989 si_get_max_workgroup_size(shader
));
4991 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4992 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&& !ctx
->shader
->is_monolithic
) {
4993 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4994 "InitialPSInputAddr",
4995 S_0286D0_PERSP_SAMPLE_ENA(1) |
4996 S_0286D0_PERSP_CENTER_ENA(1) |
4997 S_0286D0_PERSP_CENTROID_ENA(1) |
4998 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4999 S_0286D0_LINEAR_CENTER_ENA(1) |
5000 S_0286D0_LINEAR_CENTROID_ENA(1) |
5001 S_0286D0_FRONT_FACE_ENA(1) |
5002 S_0286D0_ANCILLARY_ENA(1) |
5003 S_0286D0_POS_FIXED_PT_ENA(1));
5006 shader
->info
.num_input_sgprs
= 0;
5007 shader
->info
.num_input_vgprs
= 0;
5009 for (i
= 0; i
< fninfo
.num_sgpr_params
; ++i
)
5010 shader
->info
.num_input_sgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5012 for (; i
< fninfo
.num_params
; ++i
)
5013 shader
->info
.num_input_vgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5015 assert(shader
->info
.num_input_vgprs
>= num_prolog_vgprs
);
5016 shader
->info
.num_input_vgprs
-= num_prolog_vgprs
;
5018 if (shader
->key
.as_ls
|| ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
5019 if (USE_LDS_SYMBOLS
&& HAVE_LLVM
>= 0x0900) {
5020 /* The LSHS size is not known until draw time, so we append it
5021 * at the end of whatever LDS use there may be in the rest of
5022 * the shader (currently none, unless LLVM decides to do its
5023 * own LDS-based lowering).
5025 ctx
->ac
.lds
= LLVMAddGlobalInAddressSpace(
5026 ctx
->ac
.module
, LLVMArrayType(ctx
->i32
, 0),
5027 "__lds_end", AC_ADDR_SPACE_LDS
);
5028 LLVMSetAlignment(ctx
->ac
.lds
, 256);
5030 ac_declare_lds_as_pointer(&ctx
->ac
);
5035 /* Ensure that the esgs ring is declared.
5037 * We declare it with 64KB alignment as a hint that the
5038 * pointer value will always be 0.
5040 static void declare_esgs_ring(struct si_shader_context
*ctx
)
5045 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
5047 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
5048 ctx
->ac
.module
, LLVMArrayType(ctx
->i32
, 0),
5051 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
5052 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
5056 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5059 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5061 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5063 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
5064 ctx
->param_rw_buffers
);
5066 if (ctx
->shader
->key
.as_es
|| ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5067 if (ctx
->screen
->info
.chip_class
<= GFX8
) {
5069 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5071 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, ring
, 0);
5074 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5076 if (USE_LDS_SYMBOLS
&& HAVE_LLVM
>= 0x0900) {
5077 /* Declare the ESGS ring as an explicit LDS symbol. */
5078 declare_esgs_ring(ctx
);
5080 ac_declare_lds_as_pointer(&ctx
->ac
);
5081 ctx
->esgs_ring
= ctx
->ac
.lds
;
5086 if (ctx
->shader
->is_gs_copy_shader
) {
5087 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5090 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5091 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5092 const struct si_shader_selector
*sel
= ctx
->shader
->selector
;
5093 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5094 LLVMValueRef base_ring
;
5096 base_ring
= ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5098 /* The conceptual layout of the GSVS ring is
5099 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5100 * but the real memory layout is swizzled across
5102 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5104 * Override the buffer descriptor accordingly.
5106 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->i64
, 2);
5107 uint64_t stream_offset
= 0;
5109 for (unsigned stream
= 0; stream
< 4; ++stream
) {
5110 unsigned num_components
;
5112 unsigned num_records
;
5113 LLVMValueRef ring
, tmp
;
5115 num_components
= sel
->info
.num_stream_output_components
[stream
];
5116 if (!num_components
)
5119 stride
= 4 * num_components
* sel
->gs_max_out_vertices
;
5121 /* Limit on the stride field for <= GFX7. */
5122 assert(stride
< (1 << 14));
5126 ring
= LLVMBuildBitCast(builder
, base_ring
, v2i64
, "");
5127 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_0
, "");
5128 tmp
= LLVMBuildAdd(builder
, tmp
,
5129 LLVMConstInt(ctx
->i64
,
5130 stream_offset
, 0), "");
5131 stream_offset
+= stride
* 64;
5133 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_0
, "");
5134 ring
= LLVMBuildBitCast(builder
, ring
, ctx
->v4i32
, "");
5135 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_1
, "");
5136 tmp
= LLVMBuildOr(builder
, tmp
,
5137 LLVMConstInt(ctx
->i32
,
5138 S_008F04_STRIDE(stride
) |
5139 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5140 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_1
, "");
5141 ring
= LLVMBuildInsertElement(builder
, ring
,
5142 LLVMConstInt(ctx
->i32
, num_records
, 0),
5143 LLVMConstInt(ctx
->i32
, 2, 0), "");
5146 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5147 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5148 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5149 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
5150 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5151 S_008F0C_ADD_TID_ENABLE(1);
5153 if (ctx
->ac
.chip_class
>= GFX10
) {
5154 rsrc3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5155 S_008F0C_OOB_SELECT(2) |
5156 S_008F0C_RESOURCE_LEVEL(1);
5158 rsrc3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5159 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
5160 S_008F0C_ELEMENT_SIZE(1); /* element_size = 4 (bytes) */
5163 ring
= LLVMBuildInsertElement(builder
, ring
,
5164 LLVMConstInt(ctx
->i32
, rsrc3
, false),
5165 LLVMConstInt(ctx
->i32
, 3, 0), "");
5167 ctx
->gsvs_ring
[stream
] = ring
;
5169 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
5170 ctx
->tess_offchip_ring
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TES
);
5174 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5175 LLVMValueRef param_rw_buffers
,
5176 unsigned param_pos_fixed_pt
)
5178 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5179 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5181 /* Use the fixed-point gl_FragCoord input.
5182 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5183 * per coordinate to get the repeating effect.
5185 address
[0] = si_unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5186 address
[1] = si_unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5188 /* Load the buffer descriptor. */
5189 slot
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_POLY_STIPPLE
, 0);
5190 desc
= ac_build_load_to_sgpr(&ctx
->ac
, param_rw_buffers
, slot
);
5192 /* The stipple pattern is 32x32, each row has 32 bits. */
5193 offset
= LLVMBuildMul(builder
, address
[1],
5194 LLVMConstInt(ctx
->i32
, 4, 0), "");
5195 row
= buffer_load_const(ctx
, desc
, offset
);
5196 row
= ac_to_integer(&ctx
->ac
, row
);
5197 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5198 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5199 ac_build_kill_if_false(&ctx
->ac
, bit
);
5202 /* For the UMR disassembler. */
5203 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5204 #define DEBUGGER_NUM_MARKERS 5
5206 static bool si_shader_binary_open(struct si_screen
*screen
,
5207 struct si_shader
*shader
,
5208 struct ac_rtld_binary
*rtld
)
5210 const struct si_shader_selector
*sel
= shader
->selector
;
5211 enum pipe_shader_type shader_type
= sel
? sel
->type
: PIPE_SHADER_COMPUTE
;
5212 const char *part_elfs
[5];
5213 size_t part_sizes
[5];
5214 unsigned num_parts
= 0;
5216 #define add_part(shader_or_part) \
5217 if (shader_or_part) { \
5218 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5219 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5223 add_part(shader
->prolog
);
5224 add_part(shader
->previous_stage
);
5225 add_part(shader
->prolog2
);
5227 add_part(shader
->epilog
);
5231 struct ac_rtld_symbol lds_symbols
[2];
5232 unsigned num_lds_symbols
= 0;
5233 unsigned esgs_ring_size
= 0;
5235 if (sel
&& screen
->info
.chip_class
>= GFX9
&&
5236 sel
->type
== PIPE_SHADER_GEOMETRY
&& !shader
->is_gs_copy_shader
) {
5237 esgs_ring_size
= shader
->gs_info
.esgs_ring_size
;
5240 if (sel
&& shader
->key
.as_ngg
) {
5241 if (sel
->so
.num_outputs
) {
5242 unsigned esgs_vertex_bytes
= 4 * (4 * sel
->info
.num_outputs
+ 1);
5243 esgs_ring_size
= MAX2(esgs_ring_size
,
5244 shader
->ngg
.max_out_verts
* esgs_vertex_bytes
);
5247 /* GS stores Primitive IDs into LDS at the address corresponding
5248 * to the ES thread of the provoking vertex. All ES threads
5249 * load and export PrimitiveID for their thread.
5251 if (sel
->type
== PIPE_SHADER_VERTEX
&&
5252 shader
->key
.mono
.u
.vs_export_prim_id
)
5253 esgs_ring_size
= MAX2(esgs_ring_size
, shader
->ngg
.max_out_verts
* 4);
5256 if (esgs_ring_size
) {
5257 /* We add this symbol even on LLVM <= 8 to ensure that
5258 * shader->config.lds_size is set correctly below.
5260 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
5261 sym
->name
= "esgs_ring";
5262 sym
->size
= esgs_ring_size
;
5263 sym
->align
= 64 * 1024;
5266 if (shader
->key
.as_ngg
&& sel
->type
== PIPE_SHADER_GEOMETRY
) {
5267 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
5268 sym
->name
= "ngg_emit";
5269 sym
->size
= shader
->ngg
.ngg_emit_size
* 4;
5273 bool ok
= ac_rtld_open(rtld
, (struct ac_rtld_open_info
){
5274 .info
= &screen
->info
,
5276 .halt_at_entry
= screen
->options
.halt_shaders
,
5278 .shader_type
= tgsi_processor_to_shader_stage(shader_type
),
5279 .num_parts
= num_parts
,
5280 .elf_ptrs
= part_elfs
,
5281 .elf_sizes
= part_sizes
,
5282 .num_shared_lds_symbols
= num_lds_symbols
,
5283 .shared_lds_symbols
= lds_symbols
});
5285 if (rtld
->lds_size
> 0) {
5286 unsigned alloc_granularity
= screen
->info
.chip_class
>= GFX7
? 512 : 256;
5287 shader
->config
.lds_size
=
5288 align(rtld
->lds_size
, alloc_granularity
) / alloc_granularity
;
5294 static unsigned si_get_shader_binary_size(struct si_screen
*screen
, struct si_shader
*shader
)
5296 struct ac_rtld_binary rtld
;
5297 si_shader_binary_open(screen
, shader
, &rtld
);
5298 return rtld
.rx_size
;
5301 static bool si_get_external_symbol(void *data
, const char *name
, uint64_t *value
)
5303 uint64_t *scratch_va
= data
;
5305 if (!strcmp(scratch_rsrc_dword0_symbol
, name
)) {
5306 *value
= (uint32_t)*scratch_va
;
5309 if (!strcmp(scratch_rsrc_dword1_symbol
, name
)) {
5310 /* Enable scratch coalescing. */
5311 *value
= S_008F04_BASE_ADDRESS_HI(*scratch_va
>> 32) |
5312 S_008F04_SWIZZLE_ENABLE(1);
5313 if (HAVE_LLVM
< 0x0800) {
5314 /* Old LLVM created an R_ABS32_HI relocation for
5324 bool si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
,
5325 uint64_t scratch_va
)
5327 struct ac_rtld_binary binary
;
5328 if (!si_shader_binary_open(sscreen
, shader
, &binary
))
5331 si_resource_reference(&shader
->bo
, NULL
);
5332 shader
->bo
= si_aligned_buffer_create(&sscreen
->b
,
5333 sscreen
->cpdma_prefetch_writes_memory
?
5334 0 : SI_RESOURCE_FLAG_READ_ONLY
,
5335 PIPE_USAGE_IMMUTABLE
,
5336 align(binary
.rx_size
, SI_CPDMA_ALIGNMENT
),
5342 struct ac_rtld_upload_info u
= {};
5344 u
.get_external_symbol
= si_get_external_symbol
;
5345 u
.cb_data
= &scratch_va
;
5346 u
.rx_va
= shader
->bo
->gpu_address
;
5347 u
.rx_ptr
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
5348 PIPE_TRANSFER_READ_WRITE
|
5349 PIPE_TRANSFER_UNSYNCHRONIZED
|
5350 RADEON_TRANSFER_TEMPORARY
);
5354 bool ok
= ac_rtld_upload(&u
);
5356 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
5357 ac_rtld_close(&binary
);
5362 static void si_shader_dump_disassembly(struct si_screen
*screen
,
5363 const struct si_shader_binary
*binary
,
5364 struct pipe_debug_callback
*debug
,
5365 const char *name
, FILE *file
)
5367 struct ac_rtld_binary rtld_binary
;
5369 if (!ac_rtld_open(&rtld_binary
, (struct ac_rtld_open_info
){
5370 .info
= &screen
->info
,
5372 .elf_ptrs
= &binary
->elf_buffer
,
5373 .elf_sizes
= &binary
->elf_size
}))
5379 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm
, &nbytes
))
5382 if (nbytes
> INT_MAX
)
5385 if (debug
&& debug
->debug_message
) {
5386 /* Very long debug messages are cut off, so send the
5387 * disassembly one line at a time. This causes more
5388 * overhead, but on the plus side it simplifies
5389 * parsing of resulting logs.
5391 pipe_debug_message(debug
, SHADER_INFO
,
5392 "Shader Disassembly Begin");
5395 while (line
< nbytes
) {
5396 int count
= nbytes
- line
;
5397 const char *nl
= memchr(disasm
+ line
, '\n', nbytes
- line
);
5399 count
= nl
- (disasm
+ line
);
5402 pipe_debug_message(debug
, SHADER_INFO
,
5403 "%.*s", count
, disasm
+ line
);
5409 pipe_debug_message(debug
, SHADER_INFO
,
5410 "Shader Disassembly End");
5414 fprintf(file
, "Shader %s disassembly:\n", name
);
5415 fprintf(file
, "%*s", (int)nbytes
, disasm
);
5419 ac_rtld_close(&rtld_binary
);
5422 static void si_calculate_max_simd_waves(struct si_shader
*shader
)
5424 struct si_screen
*sscreen
= shader
->selector
->screen
;
5425 struct ac_shader_config
*conf
= &shader
->config
;
5426 unsigned num_inputs
= shader
->selector
->info
.num_inputs
;
5427 unsigned lds_increment
= sscreen
->info
.chip_class
>= GFX7
? 512 : 256;
5428 unsigned lds_per_wave
= 0;
5429 unsigned max_simd_waves
;
5431 max_simd_waves
= ac_get_max_simd_waves(sscreen
->info
.family
);
5433 /* Compute LDS usage for PS. */
5434 switch (shader
->selector
->type
) {
5435 case PIPE_SHADER_FRAGMENT
:
5436 /* The minimum usage per wave is (num_inputs * 48). The maximum
5437 * usage is (num_inputs * 48 * 16).
5438 * We can get anything in between and it varies between waves.
5440 * The 48 bytes per input for a single primitive is equal to
5441 * 4 bytes/component * 4 components/input * 3 points.
5443 * Other stages don't know the size at compile time or don't
5444 * allocate LDS per wave, but instead they do it per thread group.
5446 lds_per_wave
= conf
->lds_size
* lds_increment
+
5447 align(num_inputs
* 48, lds_increment
);
5449 case PIPE_SHADER_COMPUTE
:
5450 if (shader
->selector
) {
5451 unsigned max_workgroup_size
=
5452 si_get_max_workgroup_size(shader
);
5453 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
5454 DIV_ROUND_UP(max_workgroup_size
, 64);
5459 /* Compute the per-SIMD wave counts. */
5460 if (conf
->num_sgprs
) {
5462 MIN2(max_simd_waves
,
5463 ac_get_num_physical_sgprs(sscreen
->info
.chip_class
) / conf
->num_sgprs
);
5466 if (conf
->num_vgprs
)
5467 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
5469 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5470 * 16KB makes some SIMDs unoccupied). */
5472 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
5474 shader
->info
.max_simd_waves
= max_simd_waves
;
5477 void si_shader_dump_stats_for_shader_db(struct si_screen
*screen
,
5478 struct si_shader
*shader
,
5479 struct pipe_debug_callback
*debug
)
5481 const struct ac_shader_config
*conf
= &shader
->config
;
5483 if (screen
->options
.debug_disassembly
)
5484 si_shader_dump_disassembly(screen
, &shader
->binary
, debug
, "main", NULL
);
5486 pipe_debug_message(debug
, SHADER_INFO
,
5487 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5488 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5489 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5490 conf
->num_sgprs
, conf
->num_vgprs
,
5491 si_get_shader_binary_size(screen
, shader
),
5492 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5493 shader
->info
.max_simd_waves
, conf
->spilled_sgprs
,
5494 conf
->spilled_vgprs
, shader
->info
.private_mem_vgprs
);
5497 static void si_shader_dump_stats(struct si_screen
*sscreen
,
5498 struct si_shader
*shader
,
5501 bool check_debug_option
)
5503 const struct ac_shader_config
*conf
= &shader
->config
;
5505 if (!check_debug_option
||
5506 si_can_dump_shader(sscreen
, processor
)) {
5507 if (processor
== PIPE_SHADER_FRAGMENT
) {
5508 fprintf(file
, "*** SHADER CONFIG ***\n"
5509 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5510 "SPI_PS_INPUT_ENA = 0x%04x\n",
5511 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
5514 fprintf(file
, "*** SHADER STATS ***\n"
5517 "Spilled SGPRs: %d\n"
5518 "Spilled VGPRs: %d\n"
5519 "Private memory VGPRs: %d\n"
5520 "Code Size: %d bytes\n"
5522 "Scratch: %d bytes per wave\n"
5524 "********************\n\n\n",
5525 conf
->num_sgprs
, conf
->num_vgprs
,
5526 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
5527 shader
->info
.private_mem_vgprs
,
5528 si_get_shader_binary_size(sscreen
, shader
),
5529 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5530 shader
->info
.max_simd_waves
);
5534 const char *si_get_shader_name(const struct si_shader
*shader
, unsigned processor
)
5536 switch (processor
) {
5537 case PIPE_SHADER_VERTEX
:
5538 if (shader
->key
.as_es
)
5539 return "Vertex Shader as ES";
5540 else if (shader
->key
.as_ls
)
5541 return "Vertex Shader as LS";
5542 else if (shader
->key
.opt
.vs_as_prim_discard_cs
)
5543 return "Vertex Shader as Primitive Discard CS";
5544 else if (shader
->key
.as_ngg
)
5545 return "Vertex Shader as ESGS";
5547 return "Vertex Shader as VS";
5548 case PIPE_SHADER_TESS_CTRL
:
5549 return "Tessellation Control Shader";
5550 case PIPE_SHADER_TESS_EVAL
:
5551 if (shader
->key
.as_es
)
5552 return "Tessellation Evaluation Shader as ES";
5553 else if (shader
->key
.as_ngg
)
5554 return "Tessellation Evaluation Shader as ESGS";
5556 return "Tessellation Evaluation Shader as VS";
5557 case PIPE_SHADER_GEOMETRY
:
5558 if (shader
->is_gs_copy_shader
)
5559 return "GS Copy Shader as VS";
5561 return "Geometry Shader";
5562 case PIPE_SHADER_FRAGMENT
:
5563 return "Pixel Shader";
5564 case PIPE_SHADER_COMPUTE
:
5565 return "Compute Shader";
5567 return "Unknown Shader";
5571 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
5572 struct pipe_debug_callback
*debug
, unsigned processor
,
5573 FILE *file
, bool check_debug_option
)
5575 if (!check_debug_option
||
5576 si_can_dump_shader(sscreen
, processor
))
5577 si_dump_shader_key(processor
, shader
, file
);
5579 if (!check_debug_option
&& shader
->binary
.llvm_ir_string
) {
5580 if (shader
->previous_stage
&&
5581 shader
->previous_stage
->binary
.llvm_ir_string
) {
5582 fprintf(file
, "\n%s - previous stage - LLVM IR:\n\n",
5583 si_get_shader_name(shader
, processor
));
5584 fprintf(file
, "%s\n", shader
->previous_stage
->binary
.llvm_ir_string
);
5587 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
5588 si_get_shader_name(shader
, processor
));
5589 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
5592 if (!check_debug_option
||
5593 (si_can_dump_shader(sscreen
, processor
) &&
5594 !(sscreen
->debug_flags
& DBG(NO_ASM
)))) {
5595 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
5598 si_shader_dump_disassembly(sscreen
, &shader
->prolog
->binary
,
5599 debug
, "prolog", file
);
5600 if (shader
->previous_stage
)
5601 si_shader_dump_disassembly(sscreen
, &shader
->previous_stage
->binary
,
5602 debug
, "previous stage", file
);
5603 if (shader
->prolog2
)
5604 si_shader_dump_disassembly(sscreen
, &shader
->prolog2
->binary
,
5605 debug
, "prolog2", file
);
5607 si_shader_dump_disassembly(sscreen
, &shader
->binary
, debug
, "main", file
);
5610 si_shader_dump_disassembly(sscreen
, &shader
->epilog
->binary
,
5611 debug
, "epilog", file
);
5612 fprintf(file
, "\n");
5615 si_shader_dump_stats(sscreen
, shader
, processor
, file
,
5616 check_debug_option
);
5619 static int si_compile_llvm(struct si_screen
*sscreen
,
5620 struct si_shader_binary
*binary
,
5621 struct ac_shader_config
*conf
,
5622 struct ac_llvm_compiler
*compiler
,
5624 struct pipe_debug_callback
*debug
,
5627 bool less_optimized
)
5629 unsigned count
= p_atomic_inc_return(&sscreen
->num_compilations
);
5631 if (si_can_dump_shader(sscreen
, processor
)) {
5632 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
5634 if (!(sscreen
->debug_flags
& (DBG(NO_IR
) | DBG(PREOPT_IR
)))) {
5635 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5636 ac_dump_module(mod
);
5637 fprintf(stderr
, "\n");
5641 if (sscreen
->record_llvm_ir
) {
5642 char *ir
= LLVMPrintModuleToString(mod
);
5643 binary
->llvm_ir_string
= strdup(ir
);
5644 LLVMDisposeMessage(ir
);
5647 if (!si_replace_shader(count
, binary
)) {
5648 unsigned r
= si_llvm_compile(mod
, binary
, compiler
, debug
,
5654 struct ac_rtld_binary rtld
;
5655 if (!ac_rtld_open(&rtld
, (struct ac_rtld_open_info
){
5656 .info
= &sscreen
->info
,
5658 .elf_ptrs
= &binary
->elf_buffer
,
5659 .elf_sizes
= &binary
->elf_size
}))
5662 bool ok
= ac_rtld_read_config(&rtld
, conf
);
5663 ac_rtld_close(&rtld
);
5667 /* Enable 64-bit and 16-bit denormals, because there is no performance
5670 * If denormals are enabled, all floating-point output modifiers are
5673 * Don't enable denormals for 32-bit floats, because:
5674 * - Floating-point output modifiers would be ignored by the hw.
5675 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5676 * have to stop using those.
5677 * - GFX6 & GFX7 would be very slow.
5679 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
5684 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
5686 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
5687 LLVMBuildRetVoid(ctx
->ac
.builder
);
5689 LLVMBuildRet(ctx
->ac
.builder
, ret
);
5692 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5694 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
5695 struct ac_llvm_compiler
*compiler
,
5696 struct si_shader_selector
*gs_selector
,
5697 struct pipe_debug_callback
*debug
)
5699 struct si_shader_context ctx
;
5700 struct si_shader
*shader
;
5701 LLVMBuilderRef builder
;
5702 struct si_shader_output_values outputs
[SI_MAX_VS_OUTPUTS
];
5703 struct tgsi_shader_info
*gsinfo
= &gs_selector
->info
;
5707 shader
= CALLOC_STRUCT(si_shader
);
5711 /* We can leave the fence as permanently signaled because the GS copy
5712 * shader only becomes visible globally after it has been compiled. */
5713 util_queue_fence_init(&shader
->ready
);
5715 shader
->selector
= gs_selector
;
5716 shader
->is_gs_copy_shader
= true;
5718 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
5719 ctx
.shader
= shader
;
5720 ctx
.type
= PIPE_SHADER_VERTEX
;
5722 builder
= ctx
.ac
.builder
;
5724 create_function(&ctx
);
5725 preload_ring_buffers(&ctx
);
5727 LLVMValueRef voffset
=
5728 LLVMBuildMul(ctx
.ac
.builder
, ctx
.abi
.vertex_id
,
5729 LLVMConstInt(ctx
.i32
, 4, 0), "");
5731 /* Fetch the vertex stream ID.*/
5732 LLVMValueRef stream_id
;
5734 if (gs_selector
->so
.num_outputs
)
5735 stream_id
= si_unpack_param(&ctx
, ctx
.param_streamout_config
, 24, 2);
5737 stream_id
= ctx
.i32_0
;
5739 /* Fill in output information. */
5740 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5741 outputs
[i
].semantic_name
= gsinfo
->output_semantic_name
[i
];
5742 outputs
[i
].semantic_index
= gsinfo
->output_semantic_index
[i
];
5744 for (int chan
= 0; chan
< 4; chan
++) {
5745 outputs
[i
].vertex_stream
[chan
] =
5746 (gsinfo
->output_streams
[i
] >> (2 * chan
)) & 3;
5750 LLVMBasicBlockRef end_bb
;
5751 LLVMValueRef switch_inst
;
5753 end_bb
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, ctx
.main_fn
, "end");
5754 switch_inst
= LLVMBuildSwitch(builder
, stream_id
, end_bb
, 4);
5756 for (int stream
= 0; stream
< 4; stream
++) {
5757 LLVMBasicBlockRef bb
;
5760 if (!gsinfo
->num_stream_output_components
[stream
])
5763 if (stream
> 0 && !gs_selector
->so
.num_outputs
)
5766 bb
= LLVMInsertBasicBlockInContext(ctx
.ac
.context
, end_bb
, "out");
5767 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
.i32
, stream
, 0), bb
);
5768 LLVMPositionBuilderAtEnd(builder
, bb
);
5770 /* Fetch vertex data from GSVS ring */
5772 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5773 for (unsigned chan
= 0; chan
< 4; chan
++) {
5774 if (!(gsinfo
->output_usagemask
[i
] & (1 << chan
)) ||
5775 outputs
[i
].vertex_stream
[chan
] != stream
) {
5776 outputs
[i
].values
[chan
] = LLVMGetUndef(ctx
.f32
);
5780 LLVMValueRef soffset
= LLVMConstInt(ctx
.i32
,
5781 offset
* gs_selector
->gs_max_out_vertices
* 16 * 4, 0);
5784 outputs
[i
].values
[chan
] =
5785 ac_build_buffer_load(&ctx
.ac
,
5786 ctx
.gsvs_ring
[0], 1,
5793 /* Streamout and exports. */
5794 if (ctx
.ac
.chip_class
<= GFX9
&& gs_selector
->so
.num_outputs
) {
5795 si_llvm_emit_streamout(&ctx
, outputs
,
5796 gsinfo
->num_outputs
,
5801 si_llvm_export_vs(&ctx
, outputs
, gsinfo
->num_outputs
);
5803 LLVMBuildBr(builder
, end_bb
);
5806 LLVMPositionBuilderAtEnd(builder
, end_bb
);
5808 LLVMBuildRetVoid(ctx
.ac
.builder
);
5810 ctx
.type
= PIPE_SHADER_GEOMETRY
; /* override for shader dumping */
5811 si_llvm_optimize_module(&ctx
);
5814 if (si_compile_llvm(sscreen
, &ctx
.shader
->binary
,
5815 &ctx
.shader
->config
, ctx
.compiler
,
5817 debug
, PIPE_SHADER_GEOMETRY
,
5818 "GS Copy Shader", false) == 0) {
5819 if (si_can_dump_shader(sscreen
, PIPE_SHADER_GEOMETRY
))
5820 fprintf(stderr
, "GS Copy Shader:\n");
5821 si_shader_dump(sscreen
, ctx
.shader
, debug
,
5822 PIPE_SHADER_GEOMETRY
, stderr
, true);
5824 if (!ctx
.shader
->config
.scratch_bytes_per_wave
)
5825 ok
= si_shader_binary_upload(sscreen
, ctx
.shader
, 0);
5830 si_llvm_dispose(&ctx
);
5836 si_fix_resource_usage(sscreen
, shader
);
5841 static void si_dump_shader_key_vs(const struct si_shader_key
*key
,
5842 const struct si_vs_prolog_bits
*prolog
,
5843 const char *prefix
, FILE *f
)
5845 fprintf(f
, " %s.instance_divisor_is_one = %u\n",
5846 prefix
, prolog
->instance_divisor_is_one
);
5847 fprintf(f
, " %s.instance_divisor_is_fetched = %u\n",
5848 prefix
, prolog
->instance_divisor_is_fetched
);
5849 fprintf(f
, " %s.unpack_instance_id_from_vertex_id = %u\n",
5850 prefix
, prolog
->unpack_instance_id_from_vertex_id
);
5851 fprintf(f
, " %s.ls_vgpr_fix = %u\n",
5852 prefix
, prolog
->ls_vgpr_fix
);
5854 fprintf(f
, " mono.vs.fetch_opencode = %x\n", key
->mono
.vs_fetch_opencode
);
5855 fprintf(f
, " mono.vs.fix_fetch = {");
5856 for (int i
= 0; i
< SI_MAX_ATTRIBS
; i
++) {
5857 union si_vs_fix_fetch fix
= key
->mono
.vs_fix_fetch
[i
];
5863 fprintf(f
, "%u.%u.%u.%u", fix
.u
.reverse
, fix
.u
.log_size
,
5864 fix
.u
.num_channels_m1
, fix
.u
.format
);
5869 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
5872 const struct si_shader_key
*key
= &shader
->key
;
5874 fprintf(f
, "SHADER KEY\n");
5876 switch (processor
) {
5877 case PIPE_SHADER_VERTEX
:
5878 si_dump_shader_key_vs(key
, &key
->part
.vs
.prolog
,
5879 "part.vs.prolog", f
);
5880 fprintf(f
, " as_es = %u\n", key
->as_es
);
5881 fprintf(f
, " as_ls = %u\n", key
->as_ls
);
5882 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5883 key
->mono
.u
.vs_export_prim_id
);
5884 fprintf(f
, " opt.vs_as_prim_discard_cs = %u\n",
5885 key
->opt
.vs_as_prim_discard_cs
);
5886 fprintf(f
, " opt.cs_prim_type = %s\n",
5887 tgsi_primitive_names
[key
->opt
.cs_prim_type
]);
5888 fprintf(f
, " opt.cs_indexed = %u\n",
5889 key
->opt
.cs_indexed
);
5890 fprintf(f
, " opt.cs_instancing = %u\n",
5891 key
->opt
.cs_instancing
);
5892 fprintf(f
, " opt.cs_primitive_restart = %u\n",
5893 key
->opt
.cs_primitive_restart
);
5894 fprintf(f
, " opt.cs_provoking_vertex_first = %u\n",
5895 key
->opt
.cs_provoking_vertex_first
);
5896 fprintf(f
, " opt.cs_need_correct_orientation = %u\n",
5897 key
->opt
.cs_need_correct_orientation
);
5898 fprintf(f
, " opt.cs_cull_front = %u\n",
5899 key
->opt
.cs_cull_front
);
5900 fprintf(f
, " opt.cs_cull_back = %u\n",
5901 key
->opt
.cs_cull_back
);
5902 fprintf(f
, " opt.cs_cull_z = %u\n",
5903 key
->opt
.cs_cull_z
);
5904 fprintf(f
, " opt.cs_halfz_clip_space = %u\n",
5905 key
->opt
.cs_halfz_clip_space
);
5908 case PIPE_SHADER_TESS_CTRL
:
5909 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
) {
5910 si_dump_shader_key_vs(key
, &key
->part
.tcs
.ls_prolog
,
5911 "part.tcs.ls_prolog", f
);
5913 fprintf(f
, " part.tcs.epilog.prim_mode = %u\n", key
->part
.tcs
.epilog
.prim_mode
);
5914 fprintf(f
, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64
"\n", key
->mono
.u
.ff_tcs_inputs_to_copy
);
5917 case PIPE_SHADER_TESS_EVAL
:
5918 fprintf(f
, " as_es = %u\n", key
->as_es
);
5919 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5920 key
->mono
.u
.vs_export_prim_id
);
5923 case PIPE_SHADER_GEOMETRY
:
5924 if (shader
->is_gs_copy_shader
)
5927 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
&&
5928 key
->part
.gs
.es
->type
== PIPE_SHADER_VERTEX
) {
5929 si_dump_shader_key_vs(key
, &key
->part
.gs
.vs_prolog
,
5930 "part.gs.vs_prolog", f
);
5932 fprintf(f
, " part.gs.prolog.tri_strip_adj_fix = %u\n", key
->part
.gs
.prolog
.tri_strip_adj_fix
);
5935 case PIPE_SHADER_COMPUTE
:
5938 case PIPE_SHADER_FRAGMENT
:
5939 fprintf(f
, " part.ps.prolog.color_two_side = %u\n", key
->part
.ps
.prolog
.color_two_side
);
5940 fprintf(f
, " part.ps.prolog.flatshade_colors = %u\n", key
->part
.ps
.prolog
.flatshade_colors
);
5941 fprintf(f
, " part.ps.prolog.poly_stipple = %u\n", key
->part
.ps
.prolog
.poly_stipple
);
5942 fprintf(f
, " part.ps.prolog.force_persp_sample_interp = %u\n", key
->part
.ps
.prolog
.force_persp_sample_interp
);
5943 fprintf(f
, " part.ps.prolog.force_linear_sample_interp = %u\n", key
->part
.ps
.prolog
.force_linear_sample_interp
);
5944 fprintf(f
, " part.ps.prolog.force_persp_center_interp = %u\n", key
->part
.ps
.prolog
.force_persp_center_interp
);
5945 fprintf(f
, " part.ps.prolog.force_linear_center_interp = %u\n", key
->part
.ps
.prolog
.force_linear_center_interp
);
5946 fprintf(f
, " part.ps.prolog.bc_optimize_for_persp = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_persp
);
5947 fprintf(f
, " part.ps.prolog.bc_optimize_for_linear = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_linear
);
5948 fprintf(f
, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key
->part
.ps
.epilog
.spi_shader_col_format
);
5949 fprintf(f
, " part.ps.epilog.color_is_int8 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int8
);
5950 fprintf(f
, " part.ps.epilog.color_is_int10 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int10
);
5951 fprintf(f
, " part.ps.epilog.last_cbuf = %u\n", key
->part
.ps
.epilog
.last_cbuf
);
5952 fprintf(f
, " part.ps.epilog.alpha_func = %u\n", key
->part
.ps
.epilog
.alpha_func
);
5953 fprintf(f
, " part.ps.epilog.alpha_to_one = %u\n", key
->part
.ps
.epilog
.alpha_to_one
);
5954 fprintf(f
, " part.ps.epilog.poly_line_smoothing = %u\n", key
->part
.ps
.epilog
.poly_line_smoothing
);
5955 fprintf(f
, " part.ps.epilog.clamp_color = %u\n", key
->part
.ps
.epilog
.clamp_color
);
5962 if ((processor
== PIPE_SHADER_GEOMETRY
||
5963 processor
== PIPE_SHADER_TESS_EVAL
||
5964 processor
== PIPE_SHADER_VERTEX
) &&
5965 !key
->as_es
&& !key
->as_ls
) {
5966 fprintf(f
, " opt.kill_outputs = 0x%"PRIx64
"\n", key
->opt
.kill_outputs
);
5967 fprintf(f
, " opt.clip_disable = %u\n", key
->opt
.clip_disable
);
5971 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
5972 struct si_screen
*sscreen
,
5973 struct ac_llvm_compiler
*compiler
)
5975 struct lp_build_tgsi_context
*bld_base
;
5977 si_llvm_context_init(ctx
, sscreen
, compiler
);
5979 bld_base
= &ctx
->bld_base
;
5980 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
5982 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
].emit
= build_interp_intrinsic
;
5983 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
].emit
= build_interp_intrinsic
;
5984 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
].emit
= build_interp_intrinsic
;
5986 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
5988 bld_base
->op_actions
[TGSI_OPCODE_CLOCK
].emit
= clock_emit
;
5990 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
5991 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
5992 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
5993 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
5995 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ALL
].emit
= vote_all_emit
;
5996 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ANY
].emit
= vote_any_emit
;
5997 bld_base
->op_actions
[TGSI_OPCODE_VOTE_EQ
].emit
= vote_eq_emit
;
5998 bld_base
->op_actions
[TGSI_OPCODE_BALLOT
].emit
= ballot_emit
;
5999 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].intr_name
= "llvm.amdgcn.readfirstlane";
6000 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].emit
= read_lane_emit
;
6001 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].intr_name
= "llvm.amdgcn.readlane";
6002 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].emit
= read_lane_emit
;
6004 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_tgsi_emit_vertex
;
6005 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_tgsi_emit_primitive
;
6006 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6009 static void si_optimize_vs_outputs(struct si_shader_context
*ctx
)
6011 struct si_shader
*shader
= ctx
->shader
;
6012 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6014 if ((ctx
->type
!= PIPE_SHADER_VERTEX
&&
6015 ctx
->type
!= PIPE_SHADER_TESS_EVAL
) ||
6016 shader
->key
.as_ls
||
6020 ac_optimize_vs_outputs(&ctx
->ac
,
6022 shader
->info
.vs_output_param_offset
,
6024 &shader
->info
.nr_param_exports
);
6027 static void si_init_exec_from_input(struct si_shader_context
*ctx
,
6028 unsigned param
, unsigned bitoffset
)
6030 LLVMValueRef args
[] = {
6031 LLVMGetParam(ctx
->main_fn
, param
),
6032 LLVMConstInt(ctx
->i32
, bitoffset
, 0),
6034 ac_build_intrinsic(&ctx
->ac
,
6035 "llvm.amdgcn.init.exec.from.input",
6036 ctx
->voidt
, args
, 2, AC_FUNC_ATTR_CONVERGENT
);
6039 static bool si_vs_needs_prolog(const struct si_shader_selector
*sel
,
6040 const struct si_vs_prolog_bits
*key
)
6042 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6044 return sel
->vs_needs_prolog
|| key
->ls_vgpr_fix
;
6047 static bool si_compile_tgsi_main(struct si_shader_context
*ctx
)
6049 struct si_shader
*shader
= ctx
->shader
;
6050 struct si_shader_selector
*sel
= shader
->selector
;
6051 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
6053 // TODO clean all this up!
6054 switch (ctx
->type
) {
6055 case PIPE_SHADER_VERTEX
:
6056 ctx
->load_input
= declare_input_vs
;
6057 if (shader
->key
.as_ls
)
6058 ctx
->abi
.emit_outputs
= si_llvm_emit_ls_epilogue
;
6059 else if (shader
->key
.as_es
)
6060 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6061 else if (shader
->key
.opt
.vs_as_prim_discard_cs
)
6062 ctx
->abi
.emit_outputs
= si_llvm_emit_prim_discard_cs_epilogue
;
6063 else if (shader
->key
.as_ngg
)
6064 ctx
->abi
.emit_outputs
= gfx10_emit_ngg_epilogue
;
6066 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6067 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6068 ctx
->abi
.load_base_vertex
= get_base_vertex
;
6070 case PIPE_SHADER_TESS_CTRL
:
6071 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6072 ctx
->abi
.load_tess_varyings
= si_nir_load_tcs_varyings
;
6073 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6074 bld_base
->emit_store
= store_output_tcs
;
6075 ctx
->abi
.store_tcs_outputs
= si_nir_store_output_tcs
;
6076 ctx
->abi
.emit_outputs
= si_llvm_emit_tcs_epilogue
;
6077 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6078 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6080 case PIPE_SHADER_TESS_EVAL
:
6081 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6082 ctx
->abi
.load_tess_varyings
= si_nir_load_input_tes
;
6083 ctx
->abi
.load_tess_coord
= si_load_tess_coord
;
6084 ctx
->abi
.load_tess_level
= si_load_tess_level
;
6085 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6086 if (shader
->key
.as_es
)
6087 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6088 else if (shader
->key
.as_ngg
)
6089 ctx
->abi
.emit_outputs
= gfx10_emit_ngg_epilogue
;
6091 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6092 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6094 case PIPE_SHADER_GEOMETRY
:
6095 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6096 ctx
->abi
.load_inputs
= si_nir_load_input_gs
;
6097 ctx
->abi
.emit_vertex
= si_llvm_emit_vertex
;
6098 ctx
->abi
.emit_primitive
= si_llvm_emit_primitive
;
6099 ctx
->abi
.emit_outputs
= si_llvm_emit_gs_epilogue
;
6100 bld_base
->emit_epilogue
= si_tgsi_emit_gs_epilogue
;
6102 case PIPE_SHADER_FRAGMENT
:
6103 ctx
->load_input
= declare_input_fs
;
6104 ctx
->abi
.emit_outputs
= si_llvm_return_fs_outputs
;
6105 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6106 ctx
->abi
.lookup_interp_param
= si_nir_lookup_interp_param
;
6107 ctx
->abi
.load_sample_position
= load_sample_position
;
6108 ctx
->abi
.load_sample_mask_in
= load_sample_mask_in
;
6109 ctx
->abi
.emit_kill
= si_llvm_emit_kill
;
6111 case PIPE_SHADER_COMPUTE
:
6112 ctx
->abi
.load_local_group_size
= get_block_size
;
6115 assert(!"Unsupported shader type");
6119 ctx
->abi
.load_ubo
= load_ubo
;
6120 ctx
->abi
.load_ssbo
= load_ssbo
;
6122 create_function(ctx
);
6123 preload_ring_buffers(ctx
);
6125 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&&
6126 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
6127 for (unsigned i
= 0; i
< 6; i
++) {
6128 ctx
->invoc0_tess_factors
[i
] =
6129 ac_build_alloca_undef(&ctx
->ac
, ctx
->i32
, "");
6133 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6134 for (unsigned i
= 0; i
< 4; i
++) {
6135 ctx
->gs_next_vertex
[i
] =
6136 ac_build_alloca(&ctx
->ac
, ctx
->i32
, "");
6138 if (shader
->key
.as_ngg
) {
6139 for (unsigned i
= 0; i
< 4; ++i
) {
6140 ctx
->gs_curprim_verts
[i
] =
6141 lp_build_alloca(&ctx
->gallivm
, ctx
->ac
.i32
, "");
6142 ctx
->gs_generated_prims
[i
] =
6143 lp_build_alloca(&ctx
->gallivm
, ctx
->ac
.i32
, "");
6146 unsigned scratch_size
= 8;
6147 if (sel
->so
.num_outputs
)
6150 LLVMTypeRef ai32
= LLVMArrayType(ctx
->i32
, scratch_size
);
6151 ctx
->gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
6152 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
6153 LLVMSetInitializer(ctx
->gs_ngg_scratch
, LLVMGetUndef(ai32
));
6154 LLVMSetAlignment(ctx
->gs_ngg_scratch
, 4);
6156 ctx
->gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
6157 LLVMArrayType(ctx
->i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
6158 LLVMSetLinkage(ctx
->gs_ngg_emit
, LLVMExternalLinkage
);
6159 LLVMSetAlignment(ctx
->gs_ngg_emit
, 4);
6163 if (shader
->key
.as_ngg
&& ctx
->type
!= PIPE_SHADER_GEOMETRY
) {
6164 /* Unconditionally declare scratch space base for streamout and
6165 * vertex compaction. Whether space is actually allocated is
6166 * determined during linking / PM4 creation.
6168 * Add an extra dword per vertex to ensure an odd stride, which
6169 * avoids bank conflicts for SoA accesses.
6171 declare_esgs_ring(ctx
);
6173 /* This is really only needed when streamout and / or vertex
6174 * compaction is enabled.
6176 LLVMTypeRef asi32
= LLVMArrayType(ctx
->i32
, 8);
6177 ctx
->gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
6178 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
6179 LLVMSetInitializer(ctx
->gs_ngg_scratch
, LLVMGetUndef(asi32
));
6180 LLVMSetAlignment(ctx
->gs_ngg_scratch
, 4);
6183 /* For GFX9 merged shaders:
6184 * - Set EXEC for the first shader. If the prolog is present, set
6185 * EXEC there instead.
6186 * - Add a barrier before the second shader.
6187 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6188 * an if-statement. This is required for correctness in geometry
6189 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6192 * For monolithic merged shaders, the first shader is wrapped in an
6193 * if-block together with its prolog in si_build_wrapper_function.
6195 * NGG vertex and tess eval shaders running as the last
6196 * vertex/geometry stage handle execution explicitly using
6199 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6200 if (!shader
->is_monolithic
&&
6201 sel
->info
.num_instructions
> 1 && /* not empty shader */
6202 (shader
->key
.as_es
|| shader
->key
.as_ls
) &&
6203 (ctx
->type
== PIPE_SHADER_TESS_EVAL
||
6204 (ctx
->type
== PIPE_SHADER_VERTEX
&&
6205 !si_vs_needs_prolog(sel
, &shader
->key
.part
.vs
.prolog
)))) {
6206 si_init_exec_from_input(ctx
,
6207 ctx
->param_merged_wave_info
, 0);
6208 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6209 ctx
->type
== PIPE_SHADER_GEOMETRY
||
6210 shader
->key
.as_ngg
) {
6211 LLVMValueRef num_threads
;
6212 bool nested_barrier
;
6214 if (!shader
->is_monolithic
||
6215 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
6216 shader
->key
.as_ngg
))
6217 ac_init_exec_full_mask(&ctx
->ac
);
6219 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6220 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6221 if (ctx
->type
== PIPE_SHADER_GEOMETRY
&& shader
->key
.as_ngg
) {
6222 gfx10_ngg_gs_emit_prologue(ctx
);
6223 nested_barrier
= false;
6225 nested_barrier
= true;
6228 /* Number of patches / primitives */
6229 num_threads
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 8, 8);
6231 /* Number of vertices */
6232 num_threads
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 0, 8);
6233 nested_barrier
= false;
6237 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
6238 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
6239 lp_build_if(&ctx
->merged_wrap_if_state
, &ctx
->gallivm
, ena
);
6241 if (nested_barrier
) {
6242 /* Execute a barrier before the second shader in
6245 * Execute the barrier inside the conditional block,
6246 * so that empty waves can jump directly to s_endpgm,
6247 * which will also signal the barrier.
6249 * This is possible in gfx9, because an empty wave
6250 * for the second shader does not participate in
6251 * the epilogue. With NGG, empty waves may still
6252 * be required to export data (e.g. GS output vertices),
6253 * so we cannot let them exit early.
6255 * If the shader is TCS and the TCS epilog is present
6256 * and contains a barrier, it will wait there and then
6259 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
6264 if (sel
->force_correct_derivs_after_kill
) {
6265 ctx
->postponed_kill
= ac_build_alloca_undef(&ctx
->ac
, ctx
->i1
, "");
6266 /* true = don't kill. */
6267 LLVMBuildStore(ctx
->ac
.builder
, ctx
->i1true
,
6268 ctx
->postponed_kill
);
6272 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6273 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6277 if (!si_nir_build_llvm(ctx
, sel
->nir
)) {
6278 fprintf(stderr
, "Failed to translate shader from NIR to LLVM\n");
6283 si_llvm_build_ret(ctx
, ctx
->return_value
);
6288 * Compute the VS prolog key, which contains all the information needed to
6289 * build the VS prolog function, and set shader->info bits where needed.
6291 * \param info Shader info of the vertex shader.
6292 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6293 * \param prolog_key Key of the VS prolog
6294 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6295 * \param key Output shader part key.
6297 static void si_get_vs_prolog_key(const struct tgsi_shader_info
*info
,
6298 unsigned num_input_sgprs
,
6299 const struct si_vs_prolog_bits
*prolog_key
,
6300 struct si_shader
*shader_out
,
6301 union si_shader_part_key
*key
)
6303 memset(key
, 0, sizeof(*key
));
6304 key
->vs_prolog
.states
= *prolog_key
;
6305 key
->vs_prolog
.num_input_sgprs
= num_input_sgprs
;
6306 key
->vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
6307 key
->vs_prolog
.as_ls
= shader_out
->key
.as_ls
;
6308 key
->vs_prolog
.as_es
= shader_out
->key
.as_es
;
6309 key
->vs_prolog
.as_ngg
= shader_out
->key
.as_ngg
;
6311 if (shader_out
->selector
->type
== PIPE_SHADER_TESS_CTRL
) {
6312 key
->vs_prolog
.as_ls
= 1;
6313 key
->vs_prolog
.num_merged_next_stage_vgprs
= 2;
6314 } else if (shader_out
->selector
->type
== PIPE_SHADER_GEOMETRY
) {
6315 key
->vs_prolog
.as_es
= 1;
6316 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
6317 } else if (shader_out
->key
.as_ngg
) {
6318 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
6321 /* Enable loading the InstanceID VGPR. */
6322 uint16_t input_mask
= u_bit_consecutive(0, info
->num_inputs
);
6324 if ((key
->vs_prolog
.states
.instance_divisor_is_one
|
6325 key
->vs_prolog
.states
.instance_divisor_is_fetched
) & input_mask
)
6326 shader_out
->info
.uses_instanceid
= true;
6330 * Compute the PS prolog key, which contains all the information needed to
6331 * build the PS prolog function, and set related bits in shader->config.
6333 static void si_get_ps_prolog_key(struct si_shader
*shader
,
6334 union si_shader_part_key
*key
,
6335 bool separate_prolog
)
6337 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6339 memset(key
, 0, sizeof(*key
));
6340 key
->ps_prolog
.states
= shader
->key
.part
.ps
.prolog
;
6341 key
->ps_prolog
.colors_read
= info
->colors_read
;
6342 key
->ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
6343 key
->ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
6344 key
->ps_prolog
.wqm
= info
->uses_derivatives
&&
6345 (key
->ps_prolog
.colors_read
||
6346 key
->ps_prolog
.states
.force_persp_sample_interp
||
6347 key
->ps_prolog
.states
.force_linear_sample_interp
||
6348 key
->ps_prolog
.states
.force_persp_center_interp
||
6349 key
->ps_prolog
.states
.force_linear_center_interp
||
6350 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6351 key
->ps_prolog
.states
.bc_optimize_for_linear
);
6352 key
->ps_prolog
.ancillary_vgpr_index
= shader
->info
.ancillary_vgpr_index
;
6354 if (info
->colors_read
) {
6355 unsigned *color
= shader
->selector
->color_attr_index
;
6357 if (shader
->key
.part
.ps
.prolog
.color_two_side
) {
6358 /* BCOLORs are stored after the last input. */
6359 key
->ps_prolog
.num_interp_inputs
= info
->num_inputs
;
6360 key
->ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
6361 if (separate_prolog
)
6362 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
6365 for (unsigned i
= 0; i
< 2; i
++) {
6366 unsigned interp
= info
->input_interpolate
[color
[i
]];
6367 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
6369 if (!(info
->colors_read
& (0xf << i
*4)))
6372 key
->ps_prolog
.color_attr_index
[i
] = color
[i
];
6374 if (shader
->key
.part
.ps
.prolog
.flatshade_colors
&&
6375 interp
== TGSI_INTERPOLATE_COLOR
)
6376 interp
= TGSI_INTERPOLATE_CONSTANT
;
6379 case TGSI_INTERPOLATE_CONSTANT
:
6380 key
->ps_prolog
.color_interp_vgpr_index
[i
] = -1;
6382 case TGSI_INTERPOLATE_PERSPECTIVE
:
6383 case TGSI_INTERPOLATE_COLOR
:
6384 /* Force the interpolation location for colors here. */
6385 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
)
6386 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6387 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
)
6388 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6391 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6392 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 0;
6393 if (separate_prolog
) {
6394 shader
->config
.spi_ps_input_ena
|=
6395 S_0286CC_PERSP_SAMPLE_ENA(1);
6398 case TGSI_INTERPOLATE_LOC_CENTER
:
6399 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 2;
6400 if (separate_prolog
) {
6401 shader
->config
.spi_ps_input_ena
|=
6402 S_0286CC_PERSP_CENTER_ENA(1);
6405 case TGSI_INTERPOLATE_LOC_CENTROID
:
6406 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 4;
6407 if (separate_prolog
) {
6408 shader
->config
.spi_ps_input_ena
|=
6409 S_0286CC_PERSP_CENTROID_ENA(1);
6416 case TGSI_INTERPOLATE_LINEAR
:
6417 /* Force the interpolation location for colors here. */
6418 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
)
6419 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6420 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
)
6421 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6423 /* The VGPR assignment for non-monolithic shaders
6424 * works because InitialPSInputAddr is set on the
6425 * main shader and PERSP_PULL_MODEL is never used.
6428 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6429 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6430 separate_prolog
? 6 : 9;
6431 if (separate_prolog
) {
6432 shader
->config
.spi_ps_input_ena
|=
6433 S_0286CC_LINEAR_SAMPLE_ENA(1);
6436 case TGSI_INTERPOLATE_LOC_CENTER
:
6437 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6438 separate_prolog
? 8 : 11;
6439 if (separate_prolog
) {
6440 shader
->config
.spi_ps_input_ena
|=
6441 S_0286CC_LINEAR_CENTER_ENA(1);
6444 case TGSI_INTERPOLATE_LOC_CENTROID
:
6445 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6446 separate_prolog
? 10 : 13;
6447 if (separate_prolog
) {
6448 shader
->config
.spi_ps_input_ena
|=
6449 S_0286CC_LINEAR_CENTROID_ENA(1);
6464 * Check whether a PS prolog is required based on the key.
6466 static bool si_need_ps_prolog(const union si_shader_part_key
*key
)
6468 return key
->ps_prolog
.colors_read
||
6469 key
->ps_prolog
.states
.force_persp_sample_interp
||
6470 key
->ps_prolog
.states
.force_linear_sample_interp
||
6471 key
->ps_prolog
.states
.force_persp_center_interp
||
6472 key
->ps_prolog
.states
.force_linear_center_interp
||
6473 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6474 key
->ps_prolog
.states
.bc_optimize_for_linear
||
6475 key
->ps_prolog
.states
.poly_stipple
||
6476 key
->ps_prolog
.states
.samplemask_log_ps_iter
;
6480 * Compute the PS epilog key, which contains all the information needed to
6481 * build the PS epilog function.
6483 static void si_get_ps_epilog_key(struct si_shader
*shader
,
6484 union si_shader_part_key
*key
)
6486 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6487 memset(key
, 0, sizeof(*key
));
6488 key
->ps_epilog
.colors_written
= info
->colors_written
;
6489 key
->ps_epilog
.writes_z
= info
->writes_z
;
6490 key
->ps_epilog
.writes_stencil
= info
->writes_stencil
;
6491 key
->ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
6492 key
->ps_epilog
.states
= shader
->key
.part
.ps
.epilog
;
6496 * Build the GS prolog function. Rotate the input vertices for triangle strips
6499 static void si_build_gs_prolog_function(struct si_shader_context
*ctx
,
6500 union si_shader_part_key
*key
)
6502 unsigned num_sgprs
, num_vgprs
;
6503 struct si_function_info fninfo
;
6504 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6505 LLVMTypeRef returns
[48];
6506 LLVMValueRef func
, ret
;
6508 si_init_function_info(&fninfo
);
6510 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6511 if (key
->gs_prolog
.states
.gfx9_prev_is_vs
)
6512 num_sgprs
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
6514 num_sgprs
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
6515 num_vgprs
= 5; /* ES inputs are not needed by GS */
6517 num_sgprs
= GFX6_GS_NUM_USER_SGPR
+ 2;
6521 for (unsigned i
= 0; i
< num_sgprs
; ++i
) {
6522 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6523 returns
[i
] = ctx
->i32
;
6526 for (unsigned i
= 0; i
< num_vgprs
; ++i
) {
6527 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
6528 returns
[num_sgprs
+ i
] = ctx
->f32
;
6531 /* Create the function. */
6532 si_create_function(ctx
, "gs_prolog", returns
, num_sgprs
+ num_vgprs
,
6534 func
= ctx
->main_fn
;
6536 /* Set the full EXEC mask for the prolog, because we are only fiddling
6537 * with registers here. The main shader part will set the correct EXEC
6540 if (ctx
->screen
->info
.chip_class
>= GFX9
&& !key
->gs_prolog
.is_monolithic
)
6541 ac_init_exec_full_mask(&ctx
->ac
);
6543 /* Copy inputs to outputs. This should be no-op, as the registers match,
6544 * but it will prevent the compiler from overwriting them unintentionally.
6546 ret
= ctx
->return_value
;
6547 for (unsigned i
= 0; i
< num_sgprs
; i
++) {
6548 LLVMValueRef p
= LLVMGetParam(func
, i
);
6549 ret
= LLVMBuildInsertValue(builder
, ret
, p
, i
, "");
6551 for (unsigned i
= 0; i
< num_vgprs
; i
++) {
6552 LLVMValueRef p
= LLVMGetParam(func
, num_sgprs
+ i
);
6553 p
= ac_to_float(&ctx
->ac
, p
);
6554 ret
= LLVMBuildInsertValue(builder
, ret
, p
, num_sgprs
+ i
, "");
6557 if (key
->gs_prolog
.states
.tri_strip_adj_fix
) {
6558 /* Remap the input vertices for every other primitive. */
6559 const unsigned gfx6_vtx_params
[6] = {
6567 const unsigned gfx9_vtx_params
[3] = {
6572 LLVMValueRef vtx_in
[6], vtx_out
[6];
6573 LLVMValueRef prim_id
, rotate
;
6575 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6576 for (unsigned i
= 0; i
< 3; i
++) {
6577 vtx_in
[i
*2] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 0, 16);
6578 vtx_in
[i
*2+1] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 16, 16);
6581 for (unsigned i
= 0; i
< 6; i
++)
6582 vtx_in
[i
] = LLVMGetParam(func
, gfx6_vtx_params
[i
]);
6585 prim_id
= LLVMGetParam(func
, num_sgprs
+ 2);
6586 rotate
= LLVMBuildTrunc(builder
, prim_id
, ctx
->i1
, "");
6588 for (unsigned i
= 0; i
< 6; ++i
) {
6589 LLVMValueRef base
, rotated
;
6591 rotated
= vtx_in
[(i
+ 4) % 6];
6592 vtx_out
[i
] = LLVMBuildSelect(builder
, rotate
, rotated
, base
, "");
6595 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6596 for (unsigned i
= 0; i
< 3; i
++) {
6597 LLVMValueRef hi
, out
;
6599 hi
= LLVMBuildShl(builder
, vtx_out
[i
*2+1],
6600 LLVMConstInt(ctx
->i32
, 16, 0), "");
6601 out
= LLVMBuildOr(builder
, vtx_out
[i
*2], hi
, "");
6602 out
= ac_to_float(&ctx
->ac
, out
);
6603 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6604 gfx9_vtx_params
[i
], "");
6607 for (unsigned i
= 0; i
< 6; i
++) {
6610 out
= ac_to_float(&ctx
->ac
, vtx_out
[i
]);
6611 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6612 gfx6_vtx_params
[i
], "");
6617 LLVMBuildRet(builder
, ret
);
6621 * Given a list of shader part functions, build a wrapper function that
6622 * runs them in sequence to form a monolithic shader.
6624 static void si_build_wrapper_function(struct si_shader_context
*ctx
,
6625 LLVMValueRef
*parts
,
6628 unsigned next_shader_first_part
)
6630 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6631 /* PS epilog has one arg per color component; gfx9 merged shader
6632 * prologs need to forward 32 user SGPRs.
6634 struct si_function_info fninfo
;
6635 LLVMValueRef initial
[64], out
[64];
6636 LLVMTypeRef function_type
;
6637 unsigned num_first_params
;
6638 unsigned num_out
, initial_num_out
;
6639 MAYBE_UNUSED
unsigned num_out_sgpr
; /* used in debug checks */
6640 MAYBE_UNUSED
unsigned initial_num_out_sgpr
; /* used in debug checks */
6641 unsigned num_sgprs
, num_vgprs
;
6643 struct lp_build_if_state if_state
;
6645 si_init_function_info(&fninfo
);
6647 for (unsigned i
= 0; i
< num_parts
; ++i
) {
6648 ac_add_function_attr(ctx
->ac
.context
, parts
[i
], -1,
6649 AC_FUNC_ATTR_ALWAYSINLINE
);
6650 LLVMSetLinkage(parts
[i
], LLVMPrivateLinkage
);
6653 /* The parameters of the wrapper function correspond to those of the
6654 * first part in terms of SGPRs and VGPRs, but we use the types of the
6655 * main part to get the right types. This is relevant for the
6656 * dereferenceable attribute on descriptor table pointers.
6661 function_type
= LLVMGetElementType(LLVMTypeOf(parts
[0]));
6662 num_first_params
= LLVMCountParamTypes(function_type
);
6664 for (unsigned i
= 0; i
< num_first_params
; ++i
) {
6665 LLVMValueRef param
= LLVMGetParam(parts
[0], i
);
6667 if (ac_is_sgpr_param(param
)) {
6668 assert(num_vgprs
== 0);
6669 num_sgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6671 num_vgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6676 while (gprs
< num_sgprs
+ num_vgprs
) {
6677 LLVMValueRef param
= LLVMGetParam(parts
[main_part
], fninfo
.num_params
);
6678 LLVMTypeRef type
= LLVMTypeOf(param
);
6679 unsigned size
= ac_get_type_size(type
) / 4;
6681 add_arg(&fninfo
, gprs
< num_sgprs
? ARG_SGPR
: ARG_VGPR
, type
);
6683 assert(ac_is_sgpr_param(param
) == (gprs
< num_sgprs
));
6684 assert(gprs
+ size
<= num_sgprs
+ num_vgprs
&&
6685 (gprs
>= num_sgprs
|| gprs
+ size
<= num_sgprs
));
6690 /* Prepare the return type. */
6691 unsigned num_returns
= 0;
6692 LLVMTypeRef returns
[32], last_func_type
, return_type
;
6694 last_func_type
= LLVMGetElementType(LLVMTypeOf(parts
[num_parts
- 1]));
6695 return_type
= LLVMGetReturnType(last_func_type
);
6697 switch (LLVMGetTypeKind(return_type
)) {
6698 case LLVMStructTypeKind
:
6699 num_returns
= LLVMCountStructElementTypes(return_type
);
6700 assert(num_returns
<= ARRAY_SIZE(returns
));
6701 LLVMGetStructElementTypes(return_type
, returns
);
6703 case LLVMVoidTypeKind
:
6706 unreachable("unexpected type");
6709 si_create_function(ctx
, "wrapper", returns
, num_returns
, &fninfo
,
6710 si_get_max_workgroup_size(ctx
->shader
));
6712 if (is_merged_shader(ctx
))
6713 ac_init_exec_full_mask(&ctx
->ac
);
6715 /* Record the arguments of the function as if they were an output of
6721 for (unsigned i
= 0; i
< fninfo
.num_params
; ++i
) {
6722 LLVMValueRef param
= LLVMGetParam(ctx
->main_fn
, i
);
6723 LLVMTypeRef param_type
= LLVMTypeOf(param
);
6724 LLVMTypeRef out_type
= i
< fninfo
.num_sgpr_params
? ctx
->i32
: ctx
->f32
;
6725 unsigned size
= ac_get_type_size(param_type
) / 4;
6728 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6729 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i32
, "");
6730 param_type
= ctx
->i32
;
6733 if (param_type
!= out_type
)
6734 param
= LLVMBuildBitCast(builder
, param
, out_type
, "");
6735 out
[num_out
++] = param
;
6737 LLVMTypeRef vector_type
= LLVMVectorType(out_type
, size
);
6739 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6740 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i64
, "");
6741 param_type
= ctx
->i64
;
6744 if (param_type
!= vector_type
)
6745 param
= LLVMBuildBitCast(builder
, param
, vector_type
, "");
6747 for (unsigned j
= 0; j
< size
; ++j
)
6748 out
[num_out
++] = LLVMBuildExtractElement(
6749 builder
, param
, LLVMConstInt(ctx
->i32
, j
, 0), "");
6752 if (i
< fninfo
.num_sgpr_params
)
6753 num_out_sgpr
= num_out
;
6756 memcpy(initial
, out
, sizeof(out
));
6757 initial_num_out
= num_out
;
6758 initial_num_out_sgpr
= num_out_sgpr
;
6760 /* Now chain the parts. */
6762 for (unsigned part
= 0; part
< num_parts
; ++part
) {
6763 LLVMValueRef in
[48];
6764 LLVMTypeRef ret_type
;
6765 unsigned out_idx
= 0;
6766 unsigned num_params
= LLVMCountParams(parts
[part
]);
6768 /* Merged shaders are executed conditionally depending
6769 * on the number of enabled threads passed in the input SGPRs. */
6770 if (is_multi_part_shader(ctx
) && part
== 0) {
6771 LLVMValueRef ena
, count
= initial
[3];
6773 count
= LLVMBuildAnd(builder
, count
,
6774 LLVMConstInt(ctx
->i32
, 0x7f, 0), "");
6775 ena
= LLVMBuildICmp(builder
, LLVMIntULT
,
6776 ac_get_thread_id(&ctx
->ac
), count
, "");
6777 lp_build_if(&if_state
, &ctx
->gallivm
, ena
);
6780 /* Derive arguments for the next part from outputs of the
6783 for (unsigned param_idx
= 0; param_idx
< num_params
; ++param_idx
) {
6785 LLVMTypeRef param_type
;
6787 unsigned param_size
;
6788 LLVMValueRef arg
= NULL
;
6790 param
= LLVMGetParam(parts
[part
], param_idx
);
6791 param_type
= LLVMTypeOf(param
);
6792 param_size
= ac_get_type_size(param_type
) / 4;
6793 is_sgpr
= ac_is_sgpr_param(param
);
6796 ac_add_function_attr(ctx
->ac
.context
, parts
[part
],
6797 param_idx
+ 1, AC_FUNC_ATTR_INREG
);
6798 } else if (out_idx
< num_out_sgpr
) {
6799 /* Skip returned SGPRs the current part doesn't
6800 * declare on the input. */
6801 out_idx
= num_out_sgpr
;
6804 assert(out_idx
+ param_size
<= (is_sgpr
? num_out_sgpr
: num_out
));
6806 if (param_size
== 1)
6809 arg
= ac_build_gather_values(&ctx
->ac
, &out
[out_idx
], param_size
);
6811 if (LLVMTypeOf(arg
) != param_type
) {
6812 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6813 if (LLVMGetPointerAddressSpace(param_type
) ==
6814 AC_ADDR_SPACE_CONST_32BIT
) {
6815 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
6816 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6818 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i64
, "");
6819 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6822 arg
= LLVMBuildBitCast(builder
, arg
, param_type
, "");
6826 in
[param_idx
] = arg
;
6827 out_idx
+= param_size
;
6830 ret
= ac_build_call(&ctx
->ac
, parts
[part
], in
, num_params
);
6832 if (is_multi_part_shader(ctx
) &&
6833 part
+ 1 == next_shader_first_part
) {
6834 lp_build_endif(&if_state
);
6836 /* The second half of the merged shader should use
6837 * the inputs from the toplevel (wrapper) function,
6838 * not the return value from the last call.
6840 * That's because the last call was executed condi-
6841 * tionally, so we can't consume it in the main
6844 memcpy(out
, initial
, sizeof(initial
));
6845 num_out
= initial_num_out
;
6846 num_out_sgpr
= initial_num_out_sgpr
;
6850 /* Extract the returned GPRs. */
6851 ret_type
= LLVMTypeOf(ret
);
6855 if (LLVMGetTypeKind(ret_type
) != LLVMVoidTypeKind
) {
6856 assert(LLVMGetTypeKind(ret_type
) == LLVMStructTypeKind
);
6858 unsigned ret_size
= LLVMCountStructElementTypes(ret_type
);
6860 for (unsigned i
= 0; i
< ret_size
; ++i
) {
6862 LLVMBuildExtractValue(builder
, ret
, i
, "");
6864 assert(num_out
< ARRAY_SIZE(out
));
6865 out
[num_out
++] = val
;
6867 if (LLVMTypeOf(val
) == ctx
->i32
) {
6868 assert(num_out_sgpr
+ 1 == num_out
);
6869 num_out_sgpr
= num_out
;
6875 /* Return the value from the last part. */
6876 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
6877 LLVMBuildRetVoid(builder
);
6879 LLVMBuildRet(builder
, ret
);
6882 static bool si_should_optimize_less(struct ac_llvm_compiler
*compiler
,
6883 struct si_shader_selector
*sel
)
6885 if (!compiler
->low_opt_passes
)
6888 /* Assume a slow CPU. */
6889 assert(!sel
->screen
->info
.has_dedicated_vram
&&
6890 sel
->screen
->info
.chip_class
<= GFX8
);
6892 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6894 return sel
->type
== PIPE_SHADER_COMPUTE
&&
6895 sel
->info
.num_memory_instructions
> 1000;
6898 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6899 struct ac_llvm_compiler
*compiler
,
6900 struct si_shader
*shader
,
6901 struct pipe_debug_callback
*debug
)
6903 struct si_shader_selector
*sel
= shader
->selector
;
6904 struct si_shader_context ctx
;
6907 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6908 * conversion fails. */
6909 if (si_can_dump_shader(sscreen
, sel
->info
.processor
) &&
6910 !(sscreen
->debug_flags
& DBG(NO_TGSI
))) {
6912 tgsi_dump(sel
->tokens
, 0);
6914 nir_print_shader(sel
->nir
, stderr
);
6915 si_dump_streamout(&sel
->so
);
6918 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
6919 si_llvm_context_set_tgsi(&ctx
, shader
);
6921 memset(shader
->info
.vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6922 sizeof(shader
->info
.vs_output_param_offset
));
6924 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6926 if (!si_compile_tgsi_main(&ctx
)) {
6927 si_llvm_dispose(&ctx
);
6931 if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_VERTEX
) {
6932 LLVMValueRef parts
[2];
6933 bool need_prolog
= sel
->vs_needs_prolog
;
6935 parts
[1] = ctx
.main_fn
;
6938 union si_shader_part_key prolog_key
;
6939 si_get_vs_prolog_key(&sel
->info
,
6940 shader
->info
.num_input_sgprs
,
6941 &shader
->key
.part
.vs
.prolog
,
6942 shader
, &prolog_key
);
6943 si_build_vs_prolog_function(&ctx
, &prolog_key
);
6944 parts
[0] = ctx
.main_fn
;
6947 si_build_wrapper_function(&ctx
, parts
+ !need_prolog
,
6948 1 + need_prolog
, need_prolog
, 0);
6950 if (ctx
.shader
->key
.opt
.vs_as_prim_discard_cs
)
6951 si_build_prim_discard_compute_shader(&ctx
);
6952 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
6953 if (sscreen
->info
.chip_class
>= GFX9
) {
6954 struct si_shader_selector
*ls
= shader
->key
.part
.tcs
.ls
;
6955 LLVMValueRef parts
[4];
6956 bool vs_needs_prolog
=
6957 si_vs_needs_prolog(ls
, &shader
->key
.part
.tcs
.ls_prolog
);
6960 parts
[2] = ctx
.main_fn
;
6963 union si_shader_part_key tcs_epilog_key
;
6964 memset(&tcs_epilog_key
, 0, sizeof(tcs_epilog_key
));
6965 tcs_epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6966 si_build_tcs_epilog_function(&ctx
, &tcs_epilog_key
);
6967 parts
[3] = ctx
.main_fn
;
6969 /* VS as LS main part */
6970 struct si_shader shader_ls
= {};
6971 shader_ls
.selector
= ls
;
6972 shader_ls
.key
.as_ls
= 1;
6973 shader_ls
.key
.mono
= shader
->key
.mono
;
6974 shader_ls
.key
.opt
= shader
->key
.opt
;
6975 shader_ls
.is_monolithic
= true;
6976 si_llvm_context_set_tgsi(&ctx
, &shader_ls
);
6978 if (!si_compile_tgsi_main(&ctx
)) {
6979 si_llvm_dispose(&ctx
);
6982 shader
->info
.uses_instanceid
|= ls
->info
.uses_instanceid
;
6983 parts
[1] = ctx
.main_fn
;
6986 if (vs_needs_prolog
) {
6987 union si_shader_part_key vs_prolog_key
;
6988 si_get_vs_prolog_key(&ls
->info
,
6989 shader_ls
.info
.num_input_sgprs
,
6990 &shader
->key
.part
.tcs
.ls_prolog
,
6991 shader
, &vs_prolog_key
);
6992 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6993 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6994 parts
[0] = ctx
.main_fn
;
6997 /* Reset the shader context. */
6998 ctx
.shader
= shader
;
6999 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
7001 si_build_wrapper_function(&ctx
,
7002 parts
+ !vs_needs_prolog
,
7003 4 - !vs_needs_prolog
, vs_needs_prolog
,
7004 vs_needs_prolog
? 2 : 1);
7006 LLVMValueRef parts
[2];
7007 union si_shader_part_key epilog_key
;
7009 parts
[0] = ctx
.main_fn
;
7011 memset(&epilog_key
, 0, sizeof(epilog_key
));
7012 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7013 si_build_tcs_epilog_function(&ctx
, &epilog_key
);
7014 parts
[1] = ctx
.main_fn
;
7016 si_build_wrapper_function(&ctx
, parts
, 2, 0, 0);
7018 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_GEOMETRY
) {
7019 if (ctx
.screen
->info
.chip_class
>= GFX9
) {
7020 struct si_shader_selector
*es
= shader
->key
.part
.gs
.es
;
7021 LLVMValueRef es_prolog
= NULL
;
7022 LLVMValueRef es_main
= NULL
;
7023 LLVMValueRef gs_prolog
= NULL
;
7024 LLVMValueRef gs_main
= ctx
.main_fn
;
7027 union si_shader_part_key gs_prolog_key
;
7028 memset(&gs_prolog_key
, 0, sizeof(gs_prolog_key
));
7029 gs_prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7030 gs_prolog_key
.gs_prolog
.is_monolithic
= true;
7031 si_build_gs_prolog_function(&ctx
, &gs_prolog_key
);
7032 gs_prolog
= ctx
.main_fn
;
7035 struct si_shader shader_es
= {};
7036 shader_es
.selector
= es
;
7037 shader_es
.key
.as_es
= 1;
7038 shader_es
.key
.mono
= shader
->key
.mono
;
7039 shader_es
.key
.opt
= shader
->key
.opt
;
7040 shader_es
.is_monolithic
= true;
7041 si_llvm_context_set_tgsi(&ctx
, &shader_es
);
7043 if (!si_compile_tgsi_main(&ctx
)) {
7044 si_llvm_dispose(&ctx
);
7047 shader
->info
.uses_instanceid
|= es
->info
.uses_instanceid
;
7048 es_main
= ctx
.main_fn
;
7051 if (es
->vs_needs_prolog
) {
7052 union si_shader_part_key vs_prolog_key
;
7053 si_get_vs_prolog_key(&es
->info
,
7054 shader_es
.info
.num_input_sgprs
,
7055 &shader
->key
.part
.gs
.vs_prolog
,
7056 shader
, &vs_prolog_key
);
7057 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
7058 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
7059 es_prolog
= ctx
.main_fn
;
7062 /* Reset the shader context. */
7063 ctx
.shader
= shader
;
7064 ctx
.type
= PIPE_SHADER_GEOMETRY
;
7066 /* Prepare the array of shader parts. */
7067 LLVMValueRef parts
[4];
7068 unsigned num_parts
= 0, main_part
, next_first_part
;
7071 parts
[num_parts
++] = es_prolog
;
7073 parts
[main_part
= num_parts
++] = es_main
;
7074 parts
[next_first_part
= num_parts
++] = gs_prolog
;
7075 parts
[num_parts
++] = gs_main
;
7077 si_build_wrapper_function(&ctx
, parts
, num_parts
,
7078 main_part
, next_first_part
);
7080 LLVMValueRef parts
[2];
7081 union si_shader_part_key prolog_key
;
7083 parts
[1] = ctx
.main_fn
;
7085 memset(&prolog_key
, 0, sizeof(prolog_key
));
7086 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7087 si_build_gs_prolog_function(&ctx
, &prolog_key
);
7088 parts
[0] = ctx
.main_fn
;
7090 si_build_wrapper_function(&ctx
, parts
, 2, 1, 0);
7092 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
7093 LLVMValueRef parts
[3];
7094 union si_shader_part_key prolog_key
;
7095 union si_shader_part_key epilog_key
;
7098 si_get_ps_prolog_key(shader
, &prolog_key
, false);
7099 need_prolog
= si_need_ps_prolog(&prolog_key
);
7101 parts
[need_prolog
? 1 : 0] = ctx
.main_fn
;
7104 si_build_ps_prolog_function(&ctx
, &prolog_key
);
7105 parts
[0] = ctx
.main_fn
;
7108 si_get_ps_epilog_key(shader
, &epilog_key
);
7109 si_build_ps_epilog_function(&ctx
, &epilog_key
);
7110 parts
[need_prolog
? 2 : 1] = ctx
.main_fn
;
7112 si_build_wrapper_function(&ctx
, parts
, need_prolog
? 3 : 2,
7113 need_prolog
? 1 : 0, 0);
7116 si_llvm_optimize_module(&ctx
);
7118 /* Post-optimization transformations and analysis. */
7119 si_optimize_vs_outputs(&ctx
);
7121 if ((debug
&& debug
->debug_message
) ||
7122 si_can_dump_shader(sscreen
, ctx
.type
)) {
7123 ctx
.shader
->info
.private_mem_vgprs
=
7124 ac_count_scratch_private_memory(ctx
.main_fn
);
7127 /* Make sure the input is a pointer and not integer followed by inttoptr. */
7128 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx
.main_fn
, 0))) ==
7129 LLVMPointerTypeKind
);
7131 /* Compile to bytecode. */
7132 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, compiler
,
7133 ctx
.ac
.module
, debug
, ctx
.type
,
7134 si_get_shader_name(shader
, ctx
.type
),
7135 si_should_optimize_less(compiler
, shader
->selector
));
7136 si_llvm_dispose(&ctx
);
7138 fprintf(stderr
, "LLVM failed to compile shader\n");
7142 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7143 * LLVM 3.9svn has this bug.
7145 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
7146 unsigned wave_size
= 64;
7147 unsigned max_vgprs
= 256;
7148 unsigned max_sgprs
= sscreen
->info
.chip_class
>= GFX8
? 800 : 512;
7149 unsigned max_sgprs_per_wave
= 128;
7150 unsigned max_block_threads
= si_get_max_workgroup_size(shader
);
7151 unsigned min_waves_per_cu
= DIV_ROUND_UP(max_block_threads
, wave_size
);
7152 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
7154 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
7155 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
7157 if (shader
->config
.num_sgprs
> max_sgprs
||
7158 shader
->config
.num_vgprs
> max_vgprs
) {
7159 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
7160 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7161 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
7162 max_sgprs
, max_vgprs
);
7164 /* Just terminate the process, because dependent
7165 * shaders can hang due to bad input data, but use
7166 * the env var to allow shader-db to work.
7168 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7173 /* Add the scratch offset to input SGPRs. */
7174 if (shader
->config
.scratch_bytes_per_wave
&& !is_merged_shader(&ctx
))
7175 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
7177 /* Calculate the number of fragment input VGPRs. */
7178 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
7179 shader
->info
.num_input_vgprs
= 0;
7180 shader
->info
.face_vgpr_index
= -1;
7181 shader
->info
.ancillary_vgpr_index
= -1;
7183 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7184 shader
->info
.num_input_vgprs
+= 2;
7185 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7186 shader
->info
.num_input_vgprs
+= 2;
7187 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7188 shader
->info
.num_input_vgprs
+= 2;
7189 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
7190 shader
->info
.num_input_vgprs
+= 3;
7191 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7192 shader
->info
.num_input_vgprs
+= 2;
7193 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7194 shader
->info
.num_input_vgprs
+= 2;
7195 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7196 shader
->info
.num_input_vgprs
+= 2;
7197 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
7198 shader
->info
.num_input_vgprs
+= 1;
7199 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7200 shader
->info
.num_input_vgprs
+= 1;
7201 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7202 shader
->info
.num_input_vgprs
+= 1;
7203 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7204 shader
->info
.num_input_vgprs
+= 1;
7205 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7206 shader
->info
.num_input_vgprs
+= 1;
7207 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
7208 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
7209 shader
->info
.num_input_vgprs
+= 1;
7211 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
)) {
7212 shader
->info
.ancillary_vgpr_index
= shader
->info
.num_input_vgprs
;
7213 shader
->info
.num_input_vgprs
+= 1;
7215 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
7216 shader
->info
.num_input_vgprs
+= 1;
7217 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
7218 shader
->info
.num_input_vgprs
+= 1;
7221 si_calculate_max_simd_waves(shader
);
7222 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
7227 * Create, compile and return a shader part (prolog or epilog).
7229 * \param sscreen screen
7230 * \param list list of shader parts of the same category
7231 * \param type shader type
7232 * \param key shader part key
7233 * \param prolog whether the part being requested is a prolog
7234 * \param tm LLVM target machine
7235 * \param debug debug callback
7236 * \param build the callback responsible for building the main function
7237 * \return non-NULL on success
7239 static struct si_shader_part
*
7240 si_get_shader_part(struct si_screen
*sscreen
,
7241 struct si_shader_part
**list
,
7242 enum pipe_shader_type type
,
7244 union si_shader_part_key
*key
,
7245 struct ac_llvm_compiler
*compiler
,
7246 struct pipe_debug_callback
*debug
,
7247 void (*build
)(struct si_shader_context
*,
7248 union si_shader_part_key
*),
7251 struct si_shader_part
*result
;
7253 mtx_lock(&sscreen
->shader_parts_mutex
);
7255 /* Find existing. */
7256 for (result
= *list
; result
; result
= result
->next
) {
7257 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
7258 mtx_unlock(&sscreen
->shader_parts_mutex
);
7263 /* Compile a new one. */
7264 result
= CALLOC_STRUCT(si_shader_part
);
7267 struct si_shader shader
= {};
7268 struct si_shader_context ctx
;
7270 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
7271 ctx
.shader
= &shader
;
7275 case PIPE_SHADER_VERTEX
:
7276 shader
.key
.as_ls
= key
->vs_prolog
.as_ls
;
7277 shader
.key
.as_es
= key
->vs_prolog
.as_es
;
7278 shader
.key
.as_ngg
= key
->vs_prolog
.as_ngg
;
7280 case PIPE_SHADER_TESS_CTRL
:
7282 shader
.key
.part
.tcs
.epilog
= key
->tcs_epilog
.states
;
7284 case PIPE_SHADER_GEOMETRY
:
7287 case PIPE_SHADER_FRAGMENT
:
7289 shader
.key
.part
.ps
.prolog
= key
->ps_prolog
.states
;
7291 shader
.key
.part
.ps
.epilog
= key
->ps_epilog
.states
;
7294 unreachable("bad shader part");
7300 si_llvm_optimize_module(&ctx
);
7302 if (si_compile_llvm(sscreen
, &result
->binary
, &result
->config
, compiler
,
7303 ctx
.ac
.module
, debug
, ctx
.type
, name
, false)) {
7309 result
->next
= *list
;
7313 si_llvm_dispose(&ctx
);
7314 mtx_unlock(&sscreen
->shader_parts_mutex
);
7318 static LLVMValueRef
si_prolog_get_rw_buffers(struct si_shader_context
*ctx
)
7320 LLVMValueRef ptr
[2], list
;
7321 bool merged_shader
= is_merged_shader(ctx
);
7323 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
7324 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, ptr
[0],
7325 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
7330 * Build the vertex shader prolog function.
7332 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7333 * All inputs are returned unmodified. The vertex load indices are
7334 * stored after them, which will be used by the API VS for fetching inputs.
7336 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7341 * (VertexID + BaseVertex),
7342 * (InstanceID + StartInstance),
7343 * (InstanceID / 2 + StartInstance)
7345 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
7346 union si_shader_part_key
*key
)
7348 struct si_function_info fninfo
;
7349 LLVMTypeRef
*returns
;
7350 LLVMValueRef ret
, func
;
7352 unsigned first_vs_vgpr
= key
->vs_prolog
.num_merged_next_stage_vgprs
;
7353 unsigned num_input_vgprs
= key
->vs_prolog
.num_merged_next_stage_vgprs
+ 4;
7354 LLVMValueRef input_vgprs
[9];
7355 unsigned num_all_input_regs
= key
->vs_prolog
.num_input_sgprs
+
7357 unsigned user_sgpr_base
= key
->vs_prolog
.num_merged_next_stage_vgprs
? 8 : 0;
7359 si_init_function_info(&fninfo
);
7361 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7362 returns
= alloca((num_all_input_regs
+ key
->vs_prolog
.last_input
+ 1) *
7363 sizeof(LLVMTypeRef
));
7366 /* Declare input and output SGPRs. */
7367 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7368 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7369 returns
[num_returns
++] = ctx
->i32
;
7372 /* Preloaded VGPRs (outputs must be floats) */
7373 for (i
= 0; i
< num_input_vgprs
; i
++) {
7374 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &input_vgprs
[i
]);
7375 returns
[num_returns
++] = ctx
->f32
;
7378 /* Vertex load indices. */
7379 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
7380 returns
[num_returns
++] = ctx
->f32
;
7382 /* Create the function. */
7383 si_create_function(ctx
, "vs_prolog", returns
, num_returns
, &fninfo
, 0);
7384 func
= ctx
->main_fn
;
7386 if (key
->vs_prolog
.num_merged_next_stage_vgprs
) {
7387 if (!key
->vs_prolog
.is_monolithic
)
7388 si_init_exec_from_input(ctx
, 3, 0);
7390 if (key
->vs_prolog
.as_ls
&&
7391 ctx
->screen
->has_ls_vgpr_init_bug
) {
7392 /* If there are no HS threads, SPI loads the LS VGPRs
7393 * starting at VGPR 0. Shift them back to where they
7396 LLVMValueRef has_hs_threads
=
7397 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
7398 si_unpack_param(ctx
, 3, 8, 8),
7401 for (i
= 4; i
> 0; --i
) {
7402 input_vgprs
[i
+ 1] =
7403 LLVMBuildSelect(ctx
->ac
.builder
, has_hs_threads
,
7405 input_vgprs
[i
- 1], "");
7410 unsigned vertex_id_vgpr
= first_vs_vgpr
;
7411 unsigned instance_id_vgpr
=
7412 ctx
->screen
->info
.chip_class
>= GFX10
?
7414 first_vs_vgpr
+ (key
->vs_prolog
.as_ls
? 2 : 1);
7416 ctx
->abi
.vertex_id
= input_vgprs
[vertex_id_vgpr
];
7417 ctx
->abi
.instance_id
= input_vgprs
[instance_id_vgpr
];
7419 /* InstanceID = VertexID >> 16;
7420 * VertexID = VertexID & 0xffff;
7422 if (key
->vs_prolog
.states
.unpack_instance_id_from_vertex_id
) {
7423 ctx
->abi
.instance_id
= LLVMBuildLShr(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7424 LLVMConstInt(ctx
->i32
, 16, 0), "");
7425 ctx
->abi
.vertex_id
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7426 LLVMConstInt(ctx
->i32
, 0xffff, 0), "");
7429 /* Copy inputs to outputs. This should be no-op, as the registers match,
7430 * but it will prevent the compiler from overwriting them unintentionally.
7432 ret
= ctx
->return_value
;
7433 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7434 LLVMValueRef p
= LLVMGetParam(func
, i
);
7435 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7437 for (i
= 0; i
< num_input_vgprs
; i
++) {
7438 LLVMValueRef p
= input_vgprs
[i
];
7440 if (i
== vertex_id_vgpr
)
7441 p
= ctx
->abi
.vertex_id
;
7442 else if (i
== instance_id_vgpr
)
7443 p
= ctx
->abi
.instance_id
;
7445 p
= ac_to_float(&ctx
->ac
, p
);
7446 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
,
7447 key
->vs_prolog
.num_input_sgprs
+ i
, "");
7450 struct lp_build_if_state wrap_if_state
;
7451 LLVMValueRef original_ret
= ret
;
7452 bool wrapped
= false;
7454 if (key
->vs_prolog
.is_monolithic
&& key
->vs_prolog
.as_ngg
) {
7455 LLVMValueRef num_threads
;
7458 num_threads
= si_unpack_param(ctx
, 3, 0, 8);
7459 ena
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
7460 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
7461 lp_build_if(&wrap_if_state
, &ctx
->gallivm
, ena
);
7465 /* Compute vertex load indices from instance divisors. */
7466 LLVMValueRef instance_divisor_constbuf
= NULL
;
7468 if (key
->vs_prolog
.states
.instance_divisor_is_fetched
) {
7469 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7470 LLVMValueRef buf_index
=
7471 LLVMConstInt(ctx
->i32
, SI_VS_CONST_INSTANCE_DIVISORS
, 0);
7472 instance_divisor_constbuf
=
7473 ac_build_load_to_sgpr(&ctx
->ac
, list
, buf_index
);
7476 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
7477 bool divisor_is_one
=
7478 key
->vs_prolog
.states
.instance_divisor_is_one
& (1u << i
);
7479 bool divisor_is_fetched
=
7480 key
->vs_prolog
.states
.instance_divisor_is_fetched
& (1u << i
);
7481 LLVMValueRef index
= NULL
;
7483 if (divisor_is_one
) {
7484 index
= ctx
->abi
.instance_id
;
7485 } else if (divisor_is_fetched
) {
7486 LLVMValueRef udiv_factors
[4];
7488 for (unsigned j
= 0; j
< 4; j
++) {
7490 buffer_load_const(ctx
, instance_divisor_constbuf
,
7491 LLVMConstInt(ctx
->i32
, i
*16 + j
*4, 0));
7492 udiv_factors
[j
] = ac_to_integer(&ctx
->ac
, udiv_factors
[j
]);
7494 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7495 * Such InstanceID might not be achievable in a reasonable time though.
7497 index
= ac_build_fast_udiv_nuw(&ctx
->ac
, ctx
->abi
.instance_id
,
7498 udiv_factors
[0], udiv_factors
[1],
7499 udiv_factors
[2], udiv_factors
[3]);
7502 if (divisor_is_one
|| divisor_is_fetched
) {
7503 /* Add StartInstance. */
7504 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
7505 LLVMGetParam(ctx
->main_fn
, user_sgpr_base
+
7506 SI_SGPR_START_INSTANCE
), "");
7508 /* VertexID + BaseVertex */
7509 index
= LLVMBuildAdd(ctx
->ac
.builder
,
7511 LLVMGetParam(func
, user_sgpr_base
+
7512 SI_SGPR_BASE_VERTEX
), "");
7515 index
= ac_to_float(&ctx
->ac
, index
);
7516 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, index
,
7517 fninfo
.num_params
+ i
, "");
7521 lp_build_endif(&wrap_if_state
);
7523 LLVMValueRef values
[2] = {
7527 LLVMBasicBlockRef bbs
[2] = {
7528 wrap_if_state
.true_block
,
7529 wrap_if_state
.entry_block
7531 ret
= ac_build_phi(&ctx
->ac
, LLVMTypeOf(ret
), 2, values
, bbs
);
7534 si_llvm_build_ret(ctx
, ret
);
7537 static bool si_get_vs_prolog(struct si_screen
*sscreen
,
7538 struct ac_llvm_compiler
*compiler
,
7539 struct si_shader
*shader
,
7540 struct pipe_debug_callback
*debug
,
7541 struct si_shader
*main_part
,
7542 const struct si_vs_prolog_bits
*key
)
7544 struct si_shader_selector
*vs
= main_part
->selector
;
7546 if (!si_vs_needs_prolog(vs
, key
))
7549 /* Get the prolog. */
7550 union si_shader_part_key prolog_key
;
7551 si_get_vs_prolog_key(&vs
->info
, main_part
->info
.num_input_sgprs
,
7552 key
, shader
, &prolog_key
);
7555 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7556 PIPE_SHADER_VERTEX
, true, &prolog_key
, compiler
,
7557 debug
, si_build_vs_prolog_function
,
7558 "Vertex Shader Prolog");
7559 return shader
->prolog
!= NULL
;
7563 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7565 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7566 struct ac_llvm_compiler
*compiler
,
7567 struct si_shader
*shader
,
7568 struct pipe_debug_callback
*debug
)
7570 return si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, shader
,
7571 &shader
->key
.part
.vs
.prolog
);
7575 * Compile the TCS epilog function. This writes tesselation factors to memory
7576 * based on the output primitive type of the tesselator (determined by TES).
7578 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
7579 union si_shader_part_key
*key
)
7581 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7582 struct si_function_info fninfo
;
7585 si_init_function_info(&fninfo
);
7587 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
7588 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7589 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7590 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7591 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* wave info */
7592 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7593 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7594 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7595 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7596 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7597 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7598 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7599 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7600 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7601 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7602 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7603 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7604 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7605 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7606 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7608 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7609 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7610 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7611 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7612 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7613 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7614 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7615 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7616 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7617 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7620 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7621 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7622 unsigned tess_factors_idx
=
7623 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* patch index within the wave (REL_PATCH_ID) */
7624 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* invocation ID within the patch */
7625 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* LDS offset where tess factors should be loaded from */
7627 for (unsigned i
= 0; i
< 6; i
++)
7628 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* tess factors */
7630 /* Create the function. */
7631 si_create_function(ctx
, "tcs_epilog", NULL
, 0, &fninfo
,
7632 ctx
->screen
->info
.chip_class
>= GFX7
? 128 : 64);
7633 ac_declare_lds_as_pointer(&ctx
->ac
);
7634 func
= ctx
->main_fn
;
7636 LLVMValueRef invoc0_tess_factors
[6];
7637 for (unsigned i
= 0; i
< 6; i
++)
7638 invoc0_tess_factors
[i
] = LLVMGetParam(func
, tess_factors_idx
+ 3 + i
);
7640 si_write_tess_factors(bld_base
,
7641 LLVMGetParam(func
, tess_factors_idx
),
7642 LLVMGetParam(func
, tess_factors_idx
+ 1),
7643 LLVMGetParam(func
, tess_factors_idx
+ 2),
7644 invoc0_tess_factors
, invoc0_tess_factors
+ 4);
7646 LLVMBuildRetVoid(ctx
->ac
.builder
);
7650 * Select and compile (or reuse) TCS parts (epilog).
7652 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7653 struct ac_llvm_compiler
*compiler
,
7654 struct si_shader
*shader
,
7655 struct pipe_debug_callback
*debug
)
7657 if (sscreen
->info
.chip_class
>= GFX9
) {
7658 struct si_shader
*ls_main_part
=
7659 shader
->key
.part
.tcs
.ls
->main_shader_part_ls
;
7661 if (!si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, ls_main_part
,
7662 &shader
->key
.part
.tcs
.ls_prolog
))
7665 shader
->previous_stage
= ls_main_part
;
7668 /* Get the epilog. */
7669 union si_shader_part_key epilog_key
;
7670 memset(&epilog_key
, 0, sizeof(epilog_key
));
7671 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7673 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7674 PIPE_SHADER_TESS_CTRL
, false,
7675 &epilog_key
, compiler
, debug
,
7676 si_build_tcs_epilog_function
,
7677 "Tessellation Control Shader Epilog");
7678 return shader
->epilog
!= NULL
;
7682 * Select and compile (or reuse) GS parts (prolog).
7684 static bool si_shader_select_gs_parts(struct si_screen
*sscreen
,
7685 struct ac_llvm_compiler
*compiler
,
7686 struct si_shader
*shader
,
7687 struct pipe_debug_callback
*debug
)
7689 if (sscreen
->info
.chip_class
>= GFX9
) {
7690 struct si_shader
*es_main_part
=
7691 shader
->key
.part
.gs
.es
->main_shader_part_es
;
7693 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_VERTEX
&&
7694 !si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, es_main_part
,
7695 &shader
->key
.part
.gs
.vs_prolog
))
7698 shader
->previous_stage
= es_main_part
;
7701 if (!shader
->key
.part
.gs
.prolog
.tri_strip_adj_fix
)
7704 union si_shader_part_key prolog_key
;
7705 memset(&prolog_key
, 0, sizeof(prolog_key
));
7706 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7708 shader
->prolog2
= si_get_shader_part(sscreen
, &sscreen
->gs_prologs
,
7709 PIPE_SHADER_GEOMETRY
, true,
7710 &prolog_key
, compiler
, debug
,
7711 si_build_gs_prolog_function
,
7712 "Geometry Shader Prolog");
7713 return shader
->prolog2
!= NULL
;
7717 * Build the pixel shader prolog function. This handles:
7718 * - two-side color selection and interpolation
7719 * - overriding interpolation parameters for the API PS
7720 * - polygon stippling
7722 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7723 * overriden by other states. (e.g. per-sample interpolation)
7724 * Interpolated colors are stored after the preloaded VGPRs.
7726 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
7727 union si_shader_part_key
*key
)
7729 struct si_function_info fninfo
;
7730 LLVMValueRef ret
, func
;
7731 int num_returns
, i
, num_color_channels
;
7733 assert(si_need_ps_prolog(key
));
7735 si_init_function_info(&fninfo
);
7737 /* Declare inputs. */
7738 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7739 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7741 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7742 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7744 /* Declare outputs (same as inputs + add colors if needed) */
7745 num_returns
= fninfo
.num_params
;
7746 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7747 for (i
= 0; i
< num_color_channels
; i
++)
7748 fninfo
.types
[num_returns
++] = ctx
->f32
;
7750 /* Create the function. */
7751 si_create_function(ctx
, "ps_prolog", fninfo
.types
, num_returns
,
7753 func
= ctx
->main_fn
;
7755 /* Copy inputs to outputs. This should be no-op, as the registers match,
7756 * but it will prevent the compiler from overwriting them unintentionally.
7758 ret
= ctx
->return_value
;
7759 for (i
= 0; i
< fninfo
.num_params
; i
++) {
7760 LLVMValueRef p
= LLVMGetParam(func
, i
);
7761 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7764 /* Polygon stippling. */
7765 if (key
->ps_prolog
.states
.poly_stipple
) {
7766 /* POS_FIXED_PT is always last. */
7767 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7768 key
->ps_prolog
.num_input_vgprs
- 1;
7769 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7771 si_llvm_emit_polygon_stipple(ctx
, list
, pos
);
7774 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7775 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7776 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7777 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7779 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7780 * The hw doesn't compute CENTROID if the whole wave only
7781 * contains fully-covered quads.
7783 * PRIM_MASK is after user SGPRs.
7785 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7786 bc_optimize
= LLVMBuildLShr(ctx
->ac
.builder
, bc_optimize
,
7787 LLVMConstInt(ctx
->i32
, 31, 0), "");
7788 bc_optimize
= LLVMBuildTrunc(ctx
->ac
.builder
, bc_optimize
,
7791 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7792 /* Read PERSP_CENTER. */
7793 for (i
= 0; i
< 2; i
++)
7794 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7795 /* Read PERSP_CENTROID. */
7796 for (i
= 0; i
< 2; i
++)
7797 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7798 /* Select PERSP_CENTROID. */
7799 for (i
= 0; i
< 2; i
++) {
7800 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7801 center
[i
], centroid
[i
], "");
7802 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7803 tmp
, base
+ 4 + i
, "");
7806 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7807 /* Read LINEAR_CENTER. */
7808 for (i
= 0; i
< 2; i
++)
7809 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7810 /* Read LINEAR_CENTROID. */
7811 for (i
= 0; i
< 2; i
++)
7812 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7813 /* Select LINEAR_CENTROID. */
7814 for (i
= 0; i
< 2; i
++) {
7815 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7816 center
[i
], centroid
[i
], "");
7817 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7818 tmp
, base
+ 10 + i
, "");
7823 /* Force per-sample interpolation. */
7824 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7825 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7826 LLVMValueRef persp_sample
[2];
7828 /* Read PERSP_SAMPLE. */
7829 for (i
= 0; i
< 2; i
++)
7830 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7831 /* Overwrite PERSP_CENTER. */
7832 for (i
= 0; i
< 2; i
++)
7833 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7834 persp_sample
[i
], base
+ 2 + i
, "");
7835 /* Overwrite PERSP_CENTROID. */
7836 for (i
= 0; i
< 2; i
++)
7837 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7838 persp_sample
[i
], base
+ 4 + i
, "");
7840 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7841 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7842 LLVMValueRef linear_sample
[2];
7844 /* Read LINEAR_SAMPLE. */
7845 for (i
= 0; i
< 2; i
++)
7846 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7847 /* Overwrite LINEAR_CENTER. */
7848 for (i
= 0; i
< 2; i
++)
7849 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7850 linear_sample
[i
], base
+ 8 + i
, "");
7851 /* Overwrite LINEAR_CENTROID. */
7852 for (i
= 0; i
< 2; i
++)
7853 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7854 linear_sample
[i
], base
+ 10 + i
, "");
7857 /* Force center interpolation. */
7858 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7859 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7860 LLVMValueRef persp_center
[2];
7862 /* Read PERSP_CENTER. */
7863 for (i
= 0; i
< 2; i
++)
7864 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7865 /* Overwrite PERSP_SAMPLE. */
7866 for (i
= 0; i
< 2; i
++)
7867 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7868 persp_center
[i
], base
+ i
, "");
7869 /* Overwrite PERSP_CENTROID. */
7870 for (i
= 0; i
< 2; i
++)
7871 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7872 persp_center
[i
], base
+ 4 + i
, "");
7874 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7875 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7876 LLVMValueRef linear_center
[2];
7878 /* Read LINEAR_CENTER. */
7879 for (i
= 0; i
< 2; i
++)
7880 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7881 /* Overwrite LINEAR_SAMPLE. */
7882 for (i
= 0; i
< 2; i
++)
7883 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7884 linear_center
[i
], base
+ 6 + i
, "");
7885 /* Overwrite LINEAR_CENTROID. */
7886 for (i
= 0; i
< 2; i
++)
7887 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7888 linear_center
[i
], base
+ 10 + i
, "");
7891 /* Interpolate colors. */
7892 unsigned color_out_idx
= 0;
7893 for (i
= 0; i
< 2; i
++) {
7894 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7895 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7896 key
->ps_prolog
.face_vgpr_index
;
7897 LLVMValueRef interp
[2], color
[4];
7898 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7903 /* If the interpolation qualifier is not CONSTANT (-1). */
7904 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7905 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7906 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7908 /* Get the (i,j) updated by bc_optimize handling. */
7909 interp
[0] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7911 interp
[1] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7912 interp_vgpr
+ 1, "");
7913 interp_ij
= ac_build_gather_values(&ctx
->ac
, interp
, 2);
7916 /* Use the absolute location of the input. */
7917 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7919 if (key
->ps_prolog
.states
.color_two_side
) {
7920 face
= LLVMGetParam(func
, face_vgpr
);
7921 face
= ac_to_integer(&ctx
->ac
, face
);
7924 interp_fs_input(ctx
,
7925 key
->ps_prolog
.color_attr_index
[i
],
7926 TGSI_SEMANTIC_COLOR
, i
,
7927 key
->ps_prolog
.num_interp_inputs
,
7928 key
->ps_prolog
.colors_read
, interp_ij
,
7929 prim_mask
, face
, color
);
7932 unsigned chan
= u_bit_scan(&writemask
);
7933 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, color
[chan
],
7934 fninfo
.num_params
+ color_out_idx
++, "");
7938 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7941 * "When per-sample shading is active due to the use of a fragment
7942 * input qualified by sample or due to the use of the gl_SampleID
7943 * or gl_SamplePosition variables, only the bit for the current
7944 * sample is set in gl_SampleMaskIn. When state specifies multiple
7945 * fragment shader invocations for a given fragment, the sample
7946 * mask for any single fragment shader invocation may specify a
7947 * subset of the covered samples for the fragment. In this case,
7948 * the bit corresponding to each covered sample will be set in
7949 * exactly one fragment shader invocation."
7951 * The samplemask loaded by hardware is always the coverage of the
7952 * entire pixel/fragment, so mask bits out based on the sample ID.
7954 if (key
->ps_prolog
.states
.samplemask_log_ps_iter
) {
7955 /* The bit pattern matches that used by fixed function fragment
7957 static const uint16_t ps_iter_masks
[] = {
7958 0xffff, /* not used */
7964 assert(key
->ps_prolog
.states
.samplemask_log_ps_iter
< ARRAY_SIZE(ps_iter_masks
));
7966 uint32_t ps_iter_mask
= ps_iter_masks
[key
->ps_prolog
.states
.samplemask_log_ps_iter
];
7967 unsigned ancillary_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7968 key
->ps_prolog
.ancillary_vgpr_index
;
7969 LLVMValueRef sampleid
= si_unpack_param(ctx
, ancillary_vgpr
, 8, 4);
7970 LLVMValueRef samplemask
= LLVMGetParam(func
, ancillary_vgpr
+ 1);
7972 samplemask
= ac_to_integer(&ctx
->ac
, samplemask
);
7973 samplemask
= LLVMBuildAnd(
7976 LLVMBuildShl(ctx
->ac
.builder
,
7977 LLVMConstInt(ctx
->i32
, ps_iter_mask
, false),
7980 samplemask
= ac_to_float(&ctx
->ac
, samplemask
);
7982 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, samplemask
,
7983 ancillary_vgpr
+ 1, "");
7986 /* Tell LLVM to insert WQM instruction sequence when needed. */
7987 if (key
->ps_prolog
.wqm
) {
7988 LLVMAddTargetDependentFunctionAttr(func
,
7989 "amdgpu-ps-wqm-outputs", "");
7992 si_llvm_build_ret(ctx
, ret
);
7996 * Build the pixel shader epilog function. This handles everything that must be
7997 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7999 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
8000 union si_shader_part_key
*key
)
8002 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
8003 struct si_function_info fninfo
;
8004 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
8006 struct si_ps_exports exp
= {};
8008 si_init_function_info(&fninfo
);
8010 /* Declare input SGPRs. */
8011 ctx
->param_rw_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
8012 ctx
->param_bindless_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
8013 ctx
->param_const_and_shader_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
8014 ctx
->param_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
8015 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
8017 /* Declare input VGPRs. */
8018 unsigned required_num_params
=
8019 fninfo
.num_sgpr_params
+
8020 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
8021 key
->ps_epilog
.writes_z
+
8022 key
->ps_epilog
.writes_stencil
+
8023 key
->ps_epilog
.writes_samplemask
;
8025 required_num_params
= MAX2(required_num_params
,
8026 fninfo
.num_sgpr_params
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
8028 while (fninfo
.num_params
< required_num_params
)
8029 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
8031 /* Create the function. */
8032 si_create_function(ctx
, "ps_epilog", NULL
, 0, &fninfo
, 0);
8033 /* Disable elimination of unused inputs. */
8034 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
8035 "InitialPSInputAddr", 0xffffff);
8037 /* Process colors. */
8038 unsigned vgpr
= fninfo
.num_sgpr_params
;
8039 unsigned colors_written
= key
->ps_epilog
.colors_written
;
8040 int last_color_export
= -1;
8042 /* Find the last color export. */
8043 if (!key
->ps_epilog
.writes_z
&&
8044 !key
->ps_epilog
.writes_stencil
&&
8045 !key
->ps_epilog
.writes_samplemask
) {
8046 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
8048 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8049 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
8050 /* Just set this if any of the colorbuffers are enabled. */
8052 ((1ull << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
8053 last_color_export
= 0;
8055 for (i
= 0; i
< 8; i
++)
8056 if (colors_written
& (1 << i
) &&
8057 (spi_format
>> (i
* 4)) & 0xf)
8058 last_color_export
= i
;
8062 while (colors_written
) {
8063 LLVMValueRef color
[4];
8064 int mrt
= u_bit_scan(&colors_written
);
8066 for (i
= 0; i
< 4; i
++)
8067 color
[i
] = LLVMGetParam(ctx
->main_fn
, vgpr
++);
8069 si_export_mrt_color(bld_base
, color
, mrt
,
8070 fninfo
.num_params
- 1,
8071 mrt
== last_color_export
, &exp
);
8074 /* Process depth, stencil, samplemask. */
8075 if (key
->ps_epilog
.writes_z
)
8076 depth
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
8077 if (key
->ps_epilog
.writes_stencil
)
8078 stencil
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
8079 if (key
->ps_epilog
.writes_samplemask
)
8080 samplemask
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
8082 if (depth
|| stencil
|| samplemask
)
8083 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
8084 else if (last_color_export
== -1)
8085 ac_build_export_null(&ctx
->ac
);
8088 si_emit_ps_exports(ctx
, &exp
);
8091 LLVMBuildRetVoid(ctx
->ac
.builder
);
8095 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8097 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
8098 struct ac_llvm_compiler
*compiler
,
8099 struct si_shader
*shader
,
8100 struct pipe_debug_callback
*debug
)
8102 union si_shader_part_key prolog_key
;
8103 union si_shader_part_key epilog_key
;
8105 /* Get the prolog. */
8106 si_get_ps_prolog_key(shader
, &prolog_key
, true);
8108 /* The prolog is a no-op if these aren't set. */
8109 if (si_need_ps_prolog(&prolog_key
)) {
8111 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
8112 PIPE_SHADER_FRAGMENT
, true,
8113 &prolog_key
, compiler
, debug
,
8114 si_build_ps_prolog_function
,
8115 "Fragment Shader Prolog");
8116 if (!shader
->prolog
)
8120 /* Get the epilog. */
8121 si_get_ps_epilog_key(shader
, &epilog_key
);
8124 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
8125 PIPE_SHADER_FRAGMENT
, false,
8126 &epilog_key
, compiler
, debug
,
8127 si_build_ps_epilog_function
,
8128 "Fragment Shader Epilog");
8129 if (!shader
->epilog
)
8132 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8133 if (shader
->key
.part
.ps
.prolog
.poly_stipple
) {
8134 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
8135 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
8138 /* Set up the enable bits for per-sample shading if needed. */
8139 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
&&
8140 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
8141 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
8142 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
8143 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
8144 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
8146 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
&&
8147 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
8148 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
8149 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
8150 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
8151 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
8153 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
&&
8154 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
8155 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
8156 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
8157 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
8158 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
8160 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
&&
8161 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
8162 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
8163 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
8164 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
8165 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
8168 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8169 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
8170 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
8171 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
8172 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
8175 /* At least one pair of interpolation weights must be enabled. */
8176 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
8177 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
8178 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
8181 /* Samplemask fixup requires the sample ID. */
8182 if (shader
->key
.part
.ps
.prolog
.samplemask_log_ps_iter
) {
8183 shader
->config
.spi_ps_input_ena
|= S_0286CC_ANCILLARY_ENA(1);
8184 assert(G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
));
8187 /* The sample mask input is always enabled, because the API shader always
8188 * passes it through to the epilog. Disable it here if it's unused.
8190 if (!shader
->key
.part
.ps
.epilog
.poly_line_smoothing
&&
8191 !shader
->selector
->info
.reads_samplemask
)
8192 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
8197 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
8200 /* If tessellation is all offchip and on-chip GS isn't used, this
8201 * workaround is not needed.
8205 /* SPI barrier management bug:
8206 * Make sure we have at least 4k of LDS in use to avoid the bug.
8207 * It applies to workgroup sizes of more than one wavefront.
8209 if (sscreen
->info
.family
== CHIP_BONAIRE
||
8210 sscreen
->info
.family
== CHIP_KABINI
)
8211 *lds_size
= MAX2(*lds_size
, 8);
8214 static void si_fix_resource_usage(struct si_screen
*sscreen
,
8215 struct si_shader
*shader
)
8217 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
8219 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
8221 if (shader
->selector
->type
== PIPE_SHADER_COMPUTE
&&
8222 si_get_max_workgroup_size(shader
) > 64) {
8223 si_multiwave_lds_size_workaround(sscreen
,
8224 &shader
->config
.lds_size
);
8228 bool si_shader_create(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
,
8229 struct si_shader
*shader
,
8230 struct pipe_debug_callback
*debug
)
8232 struct si_shader_selector
*sel
= shader
->selector
;
8233 struct si_shader
*mainp
= *si_get_main_shader_part(sel
, &shader
->key
);
8236 /* LS, ES, VS are compiled on demand if the main part hasn't been
8237 * compiled for that stage.
8239 * GS are compiled on demand if the main part hasn't been compiled
8240 * for the chosen NGG-ness.
8242 * Vertex shaders are compiled on demand when a vertex fetch
8243 * workaround must be applied.
8245 if (shader
->is_monolithic
) {
8246 /* Monolithic shader (compiled as a whole, has many variants,
8247 * may take a long time to compile).
8249 r
= si_compile_tgsi_shader(sscreen
, compiler
, shader
, debug
);
8253 /* The shader consists of several parts:
8255 * - the middle part is the user shader, it has 1 variant only
8256 * and it was compiled during the creation of the shader
8258 * - the prolog part is inserted at the beginning
8259 * - the epilog part is inserted at the end
8261 * The prolog and epilog have many (but simple) variants.
8263 * Starting with gfx9, geometry and tessellation control
8264 * shaders also contain the prolog and user shader parts of
8265 * the previous shader stage.
8271 /* Copy the compiled TGSI shader data over. */
8272 shader
->is_binary_shared
= true;
8273 shader
->binary
= mainp
->binary
;
8274 shader
->config
= mainp
->config
;
8275 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
8276 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
8277 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
8278 shader
->info
.ancillary_vgpr_index
= mainp
->info
.ancillary_vgpr_index
;
8279 memcpy(shader
->info
.vs_output_param_offset
,
8280 mainp
->info
.vs_output_param_offset
,
8281 sizeof(mainp
->info
.vs_output_param_offset
));
8282 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
8283 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
8284 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
8286 /* Select prologs and/or epilogs. */
8287 switch (sel
->type
) {
8288 case PIPE_SHADER_VERTEX
:
8289 if (!si_shader_select_vs_parts(sscreen
, compiler
, shader
, debug
))
8292 case PIPE_SHADER_TESS_CTRL
:
8293 if (!si_shader_select_tcs_parts(sscreen
, compiler
, shader
, debug
))
8296 case PIPE_SHADER_TESS_EVAL
:
8298 case PIPE_SHADER_GEOMETRY
:
8299 if (!si_shader_select_gs_parts(sscreen
, compiler
, shader
, debug
))
8302 case PIPE_SHADER_FRAGMENT
:
8303 if (!si_shader_select_ps_parts(sscreen
, compiler
, shader
, debug
))
8306 /* Make sure we have at least as many VGPRs as there
8307 * are allocated inputs.
8309 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8310 shader
->info
.num_input_vgprs
);
8314 /* Update SGPR and VGPR counts. */
8315 if (shader
->prolog
) {
8316 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8317 shader
->prolog
->config
.num_sgprs
);
8318 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8319 shader
->prolog
->config
.num_vgprs
);
8321 if (shader
->previous_stage
) {
8322 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8323 shader
->previous_stage
->config
.num_sgprs
);
8324 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8325 shader
->previous_stage
->config
.num_vgprs
);
8326 shader
->config
.spilled_sgprs
=
8327 MAX2(shader
->config
.spilled_sgprs
,
8328 shader
->previous_stage
->config
.spilled_sgprs
);
8329 shader
->config
.spilled_vgprs
=
8330 MAX2(shader
->config
.spilled_vgprs
,
8331 shader
->previous_stage
->config
.spilled_vgprs
);
8332 shader
->info
.private_mem_vgprs
=
8333 MAX2(shader
->info
.private_mem_vgprs
,
8334 shader
->previous_stage
->info
.private_mem_vgprs
);
8335 shader
->config
.scratch_bytes_per_wave
=
8336 MAX2(shader
->config
.scratch_bytes_per_wave
,
8337 shader
->previous_stage
->config
.scratch_bytes_per_wave
);
8338 shader
->info
.uses_instanceid
|=
8339 shader
->previous_stage
->info
.uses_instanceid
;
8341 if (shader
->prolog2
) {
8342 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8343 shader
->prolog2
->config
.num_sgprs
);
8344 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8345 shader
->prolog2
->config
.num_vgprs
);
8347 if (shader
->epilog
) {
8348 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8349 shader
->epilog
->config
.num_sgprs
);
8350 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8351 shader
->epilog
->config
.num_vgprs
);
8353 si_calculate_max_simd_waves(shader
);
8356 if (shader
->key
.as_ngg
) {
8357 assert(!shader
->key
.as_es
&& !shader
->key
.as_ls
);
8358 gfx10_ngg_calculate_subgroup_info(shader
);
8359 } else if (sscreen
->info
.chip_class
>= GFX9
&& sel
->type
== PIPE_SHADER_GEOMETRY
) {
8360 gfx9_get_gs_info(shader
->previous_stage_sel
, sel
, &shader
->gs_info
);
8363 si_fix_resource_usage(sscreen
, shader
);
8364 si_shader_dump(sscreen
, shader
, debug
, sel
->info
.processor
,
8368 if (!si_shader_binary_upload(sscreen
, shader
, 0)) {
8369 fprintf(stderr
, "LLVM failed to upload shader\n");
8376 void si_shader_destroy(struct si_shader
*shader
)
8378 if (shader
->scratch_bo
)
8379 si_resource_reference(&shader
->scratch_bo
, NULL
);
8381 si_resource_reference(&shader
->bo
, NULL
);
8383 if (!shader
->is_binary_shared
)
8384 si_shader_binary_clean(&shader
->binary
);
8386 free(shader
->shader_log
);