2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
43 #include "si_shader.h"
48 struct si_shader_output_values
50 LLVMValueRef values
[4];
56 struct si_shader_context
58 struct radeon_llvm_context radeon_bld
;
59 struct tgsi_parse_context parse
;
60 struct tgsi_token
* tokens
;
61 struct si_shader
*shader
;
62 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config
;
64 int param_streamout_write_index
;
65 int param_streamout_offset
[4];
67 int param_instance_id
;
68 LLVMValueRef const_md
;
69 LLVMValueRef const_resource
[SI_NUM_CONST_BUFFERS
];
70 LLVMValueRef ddxy_lds
;
71 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
72 LLVMValueRef
*resources
;
73 LLVMValueRef
*samplers
;
74 LLVMValueRef so_buffers
[4];
75 LLVMValueRef gs_next_vertex
;
78 static struct si_shader_context
* si_shader_context(
79 struct lp_build_tgsi_context
* bld_base
)
81 return (struct si_shader_context
*)bld_base
;
85 #define PERSPECTIVE_BASE 0
88 #define SAMPLE_OFFSET 0
89 #define CENTER_OFFSET 2
90 #define CENTROID_OFSET 4
92 #define USE_SGPR_MAX_SUFFIX_LEN 5
93 #define CONST_ADDR_SPACE 2
94 #define LOCAL_ADDR_SPACE 3
95 #define USER_SGPR_ADDR_SPACE 8
99 #define SENDMSG_GS_DONE 3
101 #define SENDMSG_GS_OP_NOP (0 << 4)
102 #define SENDMSG_GS_OP_CUT (1 << 4)
103 #define SENDMSG_GS_OP_EMIT (2 << 4)
104 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107 * Returns a unique index for a semantic name and index. The index must be
108 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
113 switch (semantic_name
) {
114 case TGSI_SEMANTIC_POSITION
:
116 case TGSI_SEMANTIC_PSIZE
:
118 case TGSI_SEMANTIC_CLIPDIST
:
121 case TGSI_SEMANTIC_CLIPVERTEX
:
123 case TGSI_SEMANTIC_COLOR
:
126 case TGSI_SEMANTIC_BCOLOR
:
129 case TGSI_SEMANTIC_FOG
:
131 case TGSI_SEMANTIC_EDGEFLAG
:
133 case TGSI_SEMANTIC_GENERIC
:
134 assert(index
<= 63-11);
143 * Given a semantic name and index of a parameter and a mask of used parameters
144 * (inputs or outputs), return the index of the parameter in the list of all
147 * For example, assume this list of parameters:
148 * POSITION, PSIZE, GENERIC0, GENERIC2
149 * which has the mask:
152 * querying POSITION returns 0,
153 * querying PSIZE returns 1,
154 * querying GENERIC0 returns 2,
155 * querying GENERIC2 returns 3.
157 * Which can be used as an offset to a parameter buffer in units of vec4s.
159 static int get_param_index(unsigned semantic_name
, unsigned index
,
162 unsigned unique_index
= si_shader_io_get_unique_index(semantic_name
, index
);
163 int i
, param_index
= 0;
165 /* If not present... */
166 if (!((1llu << unique_index
) & mask
))
169 for (i
= 0; mask
; i
++) {
170 uint64_t bit
= 1llu << i
;
173 if (i
== unique_index
)
181 assert(!"unreachable");
186 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
188 * @param offset The offset parameter specifies the number of
189 * elements to offset, not the number of bytes or dwords. An element is the
190 * the type pointed to by the base_ptr parameter (e.g. int is the element of
193 * When LLVM lowers the load instruction, it will convert the element offset
194 * into a dword offset automatically.
197 static LLVMValueRef
build_indexed_load(
198 struct si_shader_context
* si_shader_ctx
,
199 LLVMValueRef base_ptr
,
202 struct lp_build_context
* base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
204 LLVMValueRef indices
[2] = {
205 LLVMConstInt(LLVMInt64TypeInContext(base
->gallivm
->context
), 0, false),
208 LLVMValueRef computed_ptr
= LLVMBuildGEP(
209 base
->gallivm
->builder
, base_ptr
, indices
, 2, "");
211 LLVMValueRef result
= LLVMBuildLoad(base
->gallivm
->builder
, computed_ptr
, "");
212 LLVMSetMetadata(result
, 1, si_shader_ctx
->const_md
);
216 static LLVMValueRef
get_instance_index_for_fetch(
217 struct radeon_llvm_context
* radeon_bld
,
220 struct si_shader_context
*si_shader_ctx
=
221 si_shader_context(&radeon_bld
->soa
.bld_base
);
222 struct gallivm_state
* gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
224 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
225 si_shader_ctx
->param_instance_id
);
226 result
= LLVMBuildAdd(gallivm
->builder
, result
, LLVMGetParam(
227 radeon_bld
->main_fn
, SI_PARAM_START_INSTANCE
), "");
230 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
231 lp_build_const_int32(gallivm
, divisor
), "");
236 static int si_store_shader_io_attribs(struct si_shader
*shader
,
237 const struct tgsi_full_declaration
*d
)
241 switch (d
->Declaration
.File
) {
242 case TGSI_FILE_INPUT
:
243 i
= shader
->ninput
++;
244 assert(i
< Elements(shader
->input
));
245 shader
->input
[i
].name
= d
->Semantic
.Name
;
246 shader
->input
[i
].sid
= d
->Semantic
.Index
;
247 shader
->input
[i
].index
= d
->Range
.First
;
248 shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
249 shader
->input
[i
].centroid
= d
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
;
252 case TGSI_FILE_OUTPUT
:
253 i
= shader
->noutput
++;
254 assert(i
< Elements(shader
->output
));
255 shader
->output
[i
].name
= d
->Semantic
.Name
;
256 shader
->output
[i
].sid
= d
->Semantic
.Index
;
257 shader
->output
[i
].index
= d
->Range
.First
;
264 static void declare_input_vs(
265 struct radeon_llvm_context
*radeon_bld
,
266 unsigned input_index
,
267 const struct tgsi_full_declaration
*decl
)
269 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
270 struct gallivm_state
*gallivm
= base
->gallivm
;
271 struct si_shader_context
*si_shader_ctx
=
272 si_shader_context(&radeon_bld
->soa
.bld_base
);
273 unsigned divisor
= si_shader_ctx
->shader
->key
.vs
.instance_divisors
[input_index
];
277 LLVMValueRef t_list_ptr
;
278 LLVMValueRef t_offset
;
280 LLVMValueRef attribute_offset
;
281 LLVMValueRef buffer_index
;
282 LLVMValueRef args
[3];
283 LLVMTypeRef vec4_type
;
286 /* Load the T list */
287 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFER
);
289 t_offset
= lp_build_const_int32(gallivm
, input_index
);
291 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
, t_offset
);
293 /* Build the attribute offset */
294 attribute_offset
= lp_build_const_int32(gallivm
, 0);
297 /* Build index from instance ID, start instance and divisor */
298 si_shader_ctx
->shader
->uses_instanceid
= true;
299 buffer_index
= get_instance_index_for_fetch(&si_shader_ctx
->radeon_bld
, divisor
);
301 /* Load the buffer index for vertices. */
302 LLVMValueRef vertex_id
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
303 si_shader_ctx
->param_vertex_id
);
304 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
305 SI_PARAM_BASE_VERTEX
);
306 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
309 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
311 args
[1] = attribute_offset
;
312 args
[2] = buffer_index
;
313 input
= build_intrinsic(gallivm
->builder
,
314 "llvm.SI.vs.load.input", vec4_type
, args
, 3,
315 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
317 /* Break up the vec4 into individual components */
318 for (chan
= 0; chan
< 4; chan
++) {
319 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
320 /* XXX: Use a helper function for this. There is one in
322 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
323 LLVMBuildExtractElement(gallivm
->builder
,
324 input
, llvm_chan
, "");
328 static void declare_input_gs(
329 struct radeon_llvm_context
*radeon_bld
,
330 unsigned input_index
,
331 const struct tgsi_full_declaration
*decl
)
333 struct si_shader_context
*si_shader_ctx
=
334 si_shader_context(&radeon_bld
->soa
.bld_base
);
335 struct si_shader
*shader
= si_shader_ctx
->shader
;
337 si_store_shader_io_attribs(shader
, decl
);
340 static LLVMValueRef
fetch_input_gs(
341 struct lp_build_tgsi_context
*bld_base
,
342 const struct tgsi_full_src_register
*reg
,
343 enum tgsi_opcode_type type
,
346 struct lp_build_context
*base
= &bld_base
->base
;
347 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
348 struct si_shader
*shader
= si_shader_ctx
->shader
;
349 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
350 struct gallivm_state
*gallivm
= base
->gallivm
;
351 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
352 LLVMValueRef vtx_offset
;
353 LLVMValueRef t_list_ptr
;
355 LLVMValueRef args
[9];
356 unsigned vtx_offset_param
;
357 struct si_shader_input
*input
= &shader
->input
[reg
->Register
.Index
];
360 shader
->input
[reg
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
362 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
363 SI_PARAM_PRIMITIVE_ID
);
368 if (!reg
->Register
.Dimension
)
372 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
374 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
375 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
377 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
381 /* Get the vertex offset parameter */
382 vtx_offset_param
= reg
->Dimension
.Index
;
383 if (vtx_offset_param
< 2) {
384 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
386 assert(vtx_offset_param
< 6);
387 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
389 vtx_offset
= lp_build_mul_imm(uint
,
390 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
394 /* Load the ESGS ring resource descriptor */
395 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
396 SI_PARAM_RW_BUFFERS
);
397 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
398 lp_build_const_int32(gallivm
, SI_RING_ESGS
));
401 args
[1] = vtx_offset
;
402 args
[2] = lp_build_const_int32(gallivm
,
403 (get_param_index(input
->name
, input
->sid
,
404 shader
->selector
->gs_used_inputs
) * 4 +
406 args
[3] = uint
->zero
;
407 args
[4] = uint
->one
; /* OFFEN */
408 args
[5] = uint
->zero
; /* IDXEN */
409 args
[6] = uint
->one
; /* GLC */
410 args
[7] = uint
->zero
; /* SLC */
411 args
[8] = uint
->zero
; /* TFE */
413 return LLVMBuildBitCast(gallivm
->builder
,
414 build_intrinsic(gallivm
->builder
,
415 "llvm.SI.buffer.load.dword.i32.i32",
417 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
418 tgsi2llvmtype(bld_base
, type
), "");
421 static void declare_input_fs(
422 struct radeon_llvm_context
*radeon_bld
,
423 unsigned input_index
,
424 const struct tgsi_full_declaration
*decl
)
426 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
427 struct si_shader_context
*si_shader_ctx
=
428 si_shader_context(&radeon_bld
->soa
.bld_base
);
429 struct si_shader
*shader
= si_shader_ctx
->shader
;
430 struct lp_build_context
*uint
= &radeon_bld
->soa
.bld_base
.uint_bld
;
431 struct gallivm_state
*gallivm
= base
->gallivm
;
432 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
433 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
435 LLVMValueRef interp_param
;
436 const char * intr_name
;
439 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
440 * quad begins a new primitive. Bit 0 always needs
442 * [32:16] ParamOffset
445 LLVMValueRef params
= LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
446 LLVMValueRef attr_number
;
450 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) {
451 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
453 radeon_llvm_reg_index_soa(input_index
, chan
);
454 radeon_bld
->inputs
[soa_index
] =
455 LLVMGetParam(main_fn
, SI_PARAM_POS_X_FLOAT
+ chan
);
458 /* RCP for fragcoord.w */
459 radeon_bld
->inputs
[soa_index
] =
460 LLVMBuildFDiv(gallivm
->builder
,
461 lp_build_const_float(gallivm
, 1.0f
),
462 radeon_bld
->inputs
[soa_index
],
468 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
469 LLVMValueRef face
, is_face_positive
;
471 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
473 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
475 lp_build_const_float(gallivm
, 0.0f
),
478 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
479 LLVMBuildSelect(gallivm
->builder
,
481 lp_build_const_float(gallivm
, 1.0f
),
482 lp_build_const_float(gallivm
, 0.0f
),
484 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
485 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
486 lp_build_const_float(gallivm
, 0.0f
);
487 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
488 lp_build_const_float(gallivm
, 1.0f
);
493 shader
->input
[input_index
].param_offset
= shader
->nparam
++;
494 attr_number
= lp_build_const_int32(gallivm
,
495 shader
->input
[input_index
].param_offset
);
497 switch (decl
->Interp
.Interpolate
) {
498 case TGSI_INTERPOLATE_CONSTANT
:
501 case TGSI_INTERPOLATE_LINEAR
:
502 if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
503 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_SAMPLE
);
504 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
505 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTROID
);
507 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTER
);
509 case TGSI_INTERPOLATE_COLOR
:
510 if (si_shader_ctx
->shader
->key
.ps
.flatshade
) {
514 /* fall through to perspective */
515 case TGSI_INTERPOLATE_PERSPECTIVE
:
516 if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
517 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_SAMPLE
);
518 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
519 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTROID
);
521 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTER
);
524 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
528 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
530 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
531 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
532 si_shader_ctx
->shader
->key
.ps
.color_two_side
) {
533 LLVMValueRef args
[4];
534 LLVMValueRef face
, is_face_positive
;
535 LLVMValueRef back_attr_number
=
536 lp_build_const_int32(gallivm
,
537 shader
->input
[input_index
].param_offset
+ 1);
539 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
541 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
543 lp_build_const_float(gallivm
, 0.0f
),
547 args
[3] = interp_param
;
548 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
549 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
550 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
551 LLVMValueRef front
, back
;
554 args
[1] = attr_number
;
555 front
= build_intrinsic(gallivm
->builder
, intr_name
,
556 input_type
, args
, args
[3] ? 4 : 3,
557 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
559 args
[1] = back_attr_number
;
560 back
= build_intrinsic(gallivm
->builder
, intr_name
,
561 input_type
, args
, args
[3] ? 4 : 3,
562 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
564 radeon_bld
->inputs
[soa_index
] =
565 LLVMBuildSelect(gallivm
->builder
,
573 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FOG
) {
574 LLVMValueRef args
[4];
576 args
[0] = uint
->zero
;
577 args
[1] = attr_number
;
579 args
[3] = interp_param
;
580 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
581 build_intrinsic(gallivm
->builder
, intr_name
,
582 input_type
, args
, args
[3] ? 4 : 3,
583 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
584 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
585 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
586 lp_build_const_float(gallivm
, 0.0f
);
587 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
588 lp_build_const_float(gallivm
, 1.0f
);
590 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
591 LLVMValueRef args
[4];
592 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
593 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
595 args
[1] = attr_number
;
597 args
[3] = interp_param
;
598 radeon_bld
->inputs
[soa_index
] =
599 build_intrinsic(gallivm
->builder
, intr_name
,
600 input_type
, args
, args
[3] ? 4 : 3,
601 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
606 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
608 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
609 LLVMValueRef value
= LLVMGetParam(radeon_bld
->main_fn
,
611 value
= LLVMBuildLShr(gallivm
->builder
, value
,
612 lp_build_const_int32(gallivm
, 8), "");
613 value
= LLVMBuildAnd(gallivm
->builder
, value
,
614 lp_build_const_int32(gallivm
, 0xf), "");
618 static LLVMValueRef
load_const(LLVMBuilderRef builder
, LLVMValueRef resource
,
619 LLVMValueRef offset
, LLVMTypeRef return_type
)
621 LLVMValueRef args
[2] = {resource
, offset
};
623 return build_intrinsic(builder
, "llvm.SI.load.const", return_type
, args
, 2,
624 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
627 static void declare_system_value(
628 struct radeon_llvm_context
* radeon_bld
,
630 const struct tgsi_full_declaration
*decl
)
632 struct si_shader_context
*si_shader_ctx
=
633 si_shader_context(&radeon_bld
->soa
.bld_base
);
634 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
635 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
636 LLVMValueRef value
= 0;
638 switch (decl
->Semantic
.Name
) {
639 case TGSI_SEMANTIC_INSTANCEID
:
640 value
= LLVMGetParam(radeon_bld
->main_fn
,
641 si_shader_ctx
->param_instance_id
);
644 case TGSI_SEMANTIC_VERTEXID
:
645 value
= LLVMGetParam(radeon_bld
->main_fn
,
646 si_shader_ctx
->param_vertex_id
);
649 case TGSI_SEMANTIC_SAMPLEID
:
650 value
= get_sample_id(radeon_bld
);
653 case TGSI_SEMANTIC_SAMPLEPOS
:
655 LLVMBuilderRef builder
= gallivm
->builder
;
656 LLVMValueRef desc
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
657 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_DRIVER_STATE_CONST_BUF
);
658 LLVMValueRef resource
= build_indexed_load(si_shader_ctx
, desc
, buf_index
);
660 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
661 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, get_sample_id(radeon_bld
), 8);
662 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
664 LLVMValueRef pos
[4] = {
665 load_const(builder
, resource
, offset0
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
666 load_const(builder
, resource
, offset1
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
667 lp_build_const_float(gallivm
, 0),
668 lp_build_const_float(gallivm
, 0)
670 value
= lp_build_gather_values(gallivm
, pos
, 4);
675 assert(!"unknown system value");
679 radeon_bld
->system_values
[index
] = value
;
682 static LLVMValueRef
fetch_constant(
683 struct lp_build_tgsi_context
* bld_base
,
684 const struct tgsi_full_src_register
*reg
,
685 enum tgsi_opcode_type type
,
688 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
689 struct lp_build_context
* base
= &bld_base
->base
;
690 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
696 if (swizzle
== LP_CHAN_ALL
) {
698 LLVMValueRef values
[4];
699 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
700 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
702 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
705 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
706 idx
= reg
->Register
.Index
* 4 + swizzle
;
708 if (!reg
->Register
.Indirect
)
709 return bitcast(bld_base
, type
, si_shader_ctx
->constants
[buf
][idx
]);
711 addr
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
712 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
713 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
714 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
715 lp_build_const_int32(base
->gallivm
, idx
* 4));
717 result
= load_const(base
->gallivm
->builder
, si_shader_ctx
->const_resource
[buf
],
718 addr
, base
->elem_type
);
720 return bitcast(bld_base
, type
, result
);
723 /* Initialize arguments for the shader export intrinsic */
724 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
725 LLVMValueRef
*values
,
729 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
730 struct lp_build_context
*uint
=
731 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
732 struct lp_build_context
*base
= &bld_base
->base
;
733 unsigned compressed
= 0;
736 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
737 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
739 if (cbuf
>= 0 && cbuf
< 8) {
740 compressed
= (si_shader_ctx
->shader
->key
.ps
.export_16bpc
>> cbuf
) & 0x1;
743 si_shader_ctx
->shader
->spi_shader_col_format
|=
744 V_028714_SPI_SHADER_FP16_ABGR
<< (4 * cbuf
);
746 si_shader_ctx
->shader
->spi_shader_col_format
|=
747 V_028714_SPI_SHADER_32_ABGR
<< (4 * cbuf
);
749 si_shader_ctx
->shader
->cb_shader_mask
|= 0xf << (4 * cbuf
);
754 /* Pixel shader needs to pack output values before export */
755 for (chan
= 0; chan
< 2; chan
++ ) {
756 args
[0] = values
[2 * chan
];
757 args
[1] = values
[2 * chan
+ 1];
759 build_intrinsic(base
->gallivm
->builder
,
761 LLVMInt32TypeInContext(base
->gallivm
->context
),
763 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
764 args
[chan
+ 7] = args
[chan
+ 5] =
765 LLVMBuildBitCast(base
->gallivm
->builder
,
767 LLVMFloatTypeInContext(base
->gallivm
->context
),
774 for (chan
= 0; chan
< 4; chan
++ )
775 /* +5 because the first output value will be
776 * the 6th argument to the intrinsic. */
777 args
[chan
+ 5] = values
[chan
];
779 /* Clear COMPR flag */
780 args
[4] = uint
->zero
;
783 /* XXX: This controls which components of the output
784 * registers actually get exported. (e.g bit 0 means export
785 * X component, bit 1 means export Y component, etc.) I'm
786 * hard coding this to 0xf for now. In the future, we might
787 * want to do something else. */
788 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
790 /* Specify whether the EXEC mask represents the valid mask */
791 args
[1] = uint
->zero
;
793 /* Specify whether this is the last export */
794 args
[2] = uint
->zero
;
796 /* Specify the target we are exporting */
797 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
799 /* XXX: We probably need to keep track of the output
800 * values, so we know what we are passing to the next
804 /* Load from output pointers and initialize arguments for the shader export intrinsic */
805 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context
*bld_base
,
806 LLVMValueRef
*out_ptr
,
810 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
811 LLVMValueRef values
[4];
814 for (i
= 0; i
< 4; i
++)
815 values
[i
] = LLVMBuildLoad(gallivm
->builder
, out_ptr
[i
], "");
817 si_llvm_init_export_args(bld_base
, values
, target
, args
);
820 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
821 LLVMValueRef
*out_ptr
)
823 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
824 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
826 if (si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_NEVER
) {
827 LLVMValueRef alpha_ref
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
830 LLVMValueRef alpha_pass
=
831 lp_build_cmp(&bld_base
->base
,
832 si_shader_ctx
->shader
->key
.ps
.alpha_func
,
833 LLVMBuildLoad(gallivm
->builder
, out_ptr
[3], ""),
836 lp_build_select(&bld_base
->base
,
838 lp_build_const_float(gallivm
, 1.0f
),
839 lp_build_const_float(gallivm
, -1.0f
));
841 build_intrinsic(gallivm
->builder
,
843 LLVMVoidTypeInContext(gallivm
->context
),
846 build_intrinsic(gallivm
->builder
,
848 LLVMVoidTypeInContext(gallivm
->context
),
852 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
855 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
* bld_base
,
856 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
858 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
859 struct si_shader
*shader
= si_shader_ctx
->shader
;
860 struct lp_build_context
*base
= &bld_base
->base
;
861 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
865 LLVMValueRef base_elt
;
866 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
867 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
, SI_DRIVER_STATE_CONST_BUF
);
868 LLVMValueRef const_resource
= build_indexed_load(si_shader_ctx
, ptr
, constbuf_index
);
870 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
871 LLVMValueRef
*args
= pos
[2 + reg_index
];
873 shader
->clip_dist_write
|= 0xf << (4 * reg_index
);
878 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
880 /* Compute dot products of position and user clip plane vectors */
881 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
882 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
883 args
[1] = lp_build_const_int32(base
->gallivm
,
884 ((reg_index
* 4 + chan
) * 4 +
886 base_elt
= load_const(base
->gallivm
->builder
, const_resource
,
887 args
[1], base
->elem_type
);
889 lp_build_add(base
, args
[5 + chan
],
890 lp_build_mul(base
, base_elt
,
891 out_elts
[const_chan
]));
895 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
896 args
[1] = uint
->zero
;
897 args
[2] = uint
->zero
;
898 args
[3] = lp_build_const_int32(base
->gallivm
,
899 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
900 args
[4] = uint
->zero
;
904 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
909 fprintf(stderr
, "STREAMOUT\n");
911 for (i
= 0; i
< so
->num_outputs
; i
++) {
912 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
913 so
->output
[i
].start_component
;
914 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
915 i
, so
->output
[i
].output_buffer
,
916 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
917 so
->output
[i
].register_index
,
921 mask
& 8 ? "w" : "");
925 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
926 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
927 * or v4i32 (num_channels=3,4). */
928 static void build_tbuffer_store(struct si_shader_context
*shader
,
931 unsigned num_channels
,
933 LLVMValueRef soffset
,
934 unsigned inst_offset
,
943 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
944 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
945 LLVMValueRef args
[] = {
948 LLVMConstInt(i32
, num_channels
, 0),
951 LLVMConstInt(i32
, inst_offset
, 0),
952 LLVMConstInt(i32
, dfmt
, 0),
953 LLVMConstInt(i32
, nfmt
, 0),
954 LLVMConstInt(i32
, offen
, 0),
955 LLVMConstInt(i32
, idxen
, 0),
956 LLVMConstInt(i32
, glc
, 0),
957 LLVMConstInt(i32
, slc
, 0),
958 LLVMConstInt(i32
, tfe
, 0)
961 /* The instruction offset field has 12 bits */
962 assert(offen
|| inst_offset
< (1 << 12));
964 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
965 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
966 const char *types
[] = {"i32", "v2i32", "v4i32"};
968 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
970 lp_build_intrinsic(gallivm
->builder
, name
,
971 LLVMVoidTypeInContext(gallivm
->context
),
972 args
, Elements(args
));
975 static void build_streamout_store(struct si_shader_context
*shader
,
978 unsigned num_channels
,
980 LLVMValueRef soffset
,
981 unsigned inst_offset
)
983 static unsigned dfmt
[] = {
984 V_008F0C_BUF_DATA_FORMAT_32
,
985 V_008F0C_BUF_DATA_FORMAT_32_32
,
986 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
987 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
989 assert(num_channels
>= 1 && num_channels
<= 4);
991 build_tbuffer_store(shader
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
992 inst_offset
, dfmt
[num_channels
-1],
993 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
996 /* On SI, the vertex shader is responsible for writing streamout data
998 static void si_llvm_emit_streamout(struct si_shader_context
*shader
,
999 struct si_shader_output_values
*outputs
,
1002 struct pipe_stream_output_info
*so
= &shader
->shader
->selector
->so
;
1003 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
1004 LLVMBuilderRef builder
= gallivm
->builder
;
1006 struct lp_build_if_state if_ctx
;
1008 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1010 LLVMValueRef so_param
=
1011 LLVMGetParam(shader
->radeon_bld
.main_fn
,
1012 shader
->param_streamout_config
);
1014 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1015 LLVMValueRef so_vtx_count
=
1016 LLVMBuildAnd(builder
,
1017 LLVMBuildLShr(builder
, so_param
,
1018 LLVMConstInt(i32
, 16, 0), ""),
1019 LLVMConstInt(i32
, 127, 0), "");
1021 LLVMValueRef tid
= build_intrinsic(builder
, "llvm.SI.tid", i32
,
1022 NULL
, 0, LLVMReadNoneAttribute
);
1024 /* can_emit = tid < so_vtx_count; */
1025 LLVMValueRef can_emit
=
1026 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
1028 /* Emit the streamout code conditionally. This actually avoids
1029 * out-of-bounds buffer access. The hw tells us via the SGPR
1030 * (so_vtx_count) which threads are allowed to emit streamout data. */
1031 lp_build_if(&if_ctx
, gallivm
, can_emit
);
1033 /* The buffer offset is computed as follows:
1034 * ByteOffset = streamout_offset[buffer_id]*4 +
1035 * (streamout_write_index + thread_id)*stride[buffer_id] +
1039 LLVMValueRef so_write_index
=
1040 LLVMGetParam(shader
->radeon_bld
.main_fn
,
1041 shader
->param_streamout_write_index
);
1043 /* Compute (streamout_write_index + thread_id). */
1044 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
1046 /* Compute the write offset for each enabled buffer. */
1047 LLVMValueRef so_write_offset
[4] = {};
1048 for (i
= 0; i
< 4; i
++) {
1052 LLVMValueRef so_offset
= LLVMGetParam(shader
->radeon_bld
.main_fn
,
1053 shader
->param_streamout_offset
[i
]);
1054 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(i32
, 4, 0), "");
1056 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
1057 LLVMConstInt(i32
, so
->stride
[i
]*4, 0), "");
1058 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
1061 /* Write streamout data. */
1062 for (i
= 0; i
< so
->num_outputs
; i
++) {
1063 unsigned buf_idx
= so
->output
[i
].output_buffer
;
1064 unsigned reg
= so
->output
[i
].register_index
;
1065 unsigned start
= so
->output
[i
].start_component
;
1066 unsigned num_comps
= so
->output
[i
].num_components
;
1067 LLVMValueRef out
[4];
1069 assert(num_comps
&& num_comps
<= 4);
1070 if (!num_comps
|| num_comps
> 4)
1073 /* Load the output as int. */
1074 for (j
= 0; j
< num_comps
; j
++) {
1075 unsigned outidx
= 0;
1077 while (outidx
< noutput
&& outputs
[outidx
].index
!= reg
)
1080 if (outidx
< noutput
)
1081 out
[j
] = LLVMBuildBitCast(builder
,
1082 outputs
[outidx
].values
[start
+j
],
1091 /* Pack the output. */
1092 LLVMValueRef vdata
= NULL
;
1094 switch (num_comps
) {
1095 case 1: /* as i32 */
1098 case 2: /* as v2i32 */
1099 case 3: /* as v4i32 (aligned to 4) */
1100 case 4: /* as v4i32 */
1101 vdata
= LLVMGetUndef(LLVMVectorType(i32
, util_next_power_of_two(num_comps
)));
1102 for (j
= 0; j
< num_comps
; j
++) {
1103 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
1104 LLVMConstInt(i32
, j
, 0), "");
1109 build_streamout_store(shader
, shader
->so_buffers
[buf_idx
],
1111 so_write_offset
[buf_idx
],
1112 LLVMConstInt(i32
, 0, 0),
1113 so
->output
[i
].dst_offset
*4);
1116 lp_build_endif(&if_ctx
);
1120 /* Generate export instructions for hardware VS shader stage */
1121 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
1122 struct si_shader_output_values
*outputs
,
1125 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1126 struct si_shader
* shader
= si_shader_ctx
->shader
;
1127 struct lp_build_context
* base
= &bld_base
->base
;
1128 struct lp_build_context
* uint
=
1129 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1130 LLVMValueRef args
[9];
1131 LLVMValueRef pos_args
[4][9] = { { 0 } };
1132 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
;
1133 unsigned semantic_name
, semantic_index
;
1135 unsigned param_count
= 0;
1139 if (outputs
&& si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
1140 si_llvm_emit_streamout(si_shader_ctx
, outputs
, noutput
);
1143 for (i
= 0; i
< noutput
; i
++) {
1144 semantic_name
= outputs
[i
].name
;
1145 semantic_index
= outputs
[i
].sid
;
1148 /* Select the correct target */
1149 switch(semantic_name
) {
1150 case TGSI_SEMANTIC_PSIZE
:
1151 shader
->vs_out_misc_write
= true;
1152 shader
->vs_out_point_size
= true;
1153 psize_value
= outputs
[i
].values
[0];
1155 case TGSI_SEMANTIC_EDGEFLAG
:
1156 shader
->vs_out_misc_write
= true;
1157 shader
->vs_out_edgeflag
= true;
1158 edgeflag_value
= outputs
[i
].values
[0];
1160 case TGSI_SEMANTIC_LAYER
:
1161 shader
->vs_out_misc_write
= true;
1162 shader
->vs_out_layer
= true;
1163 layer_value
= outputs
[i
].values
[0];
1165 case TGSI_SEMANTIC_POSITION
:
1166 target
= V_008DFC_SQ_EXP_POS
;
1168 case TGSI_SEMANTIC_COLOR
:
1169 case TGSI_SEMANTIC_BCOLOR
:
1170 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1171 shader
->output
[i
].param_offset
= param_count
;
1174 case TGSI_SEMANTIC_CLIPDIST
:
1175 shader
->clip_dist_write
|=
1176 0xf << (semantic_index
* 4);
1177 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
1179 case TGSI_SEMANTIC_CLIPVERTEX
:
1180 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
1182 case TGSI_SEMANTIC_PRIMID
:
1183 case TGSI_SEMANTIC_FOG
:
1184 case TGSI_SEMANTIC_GENERIC
:
1185 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1186 shader
->output
[i
].param_offset
= param_count
;
1192 "Warning: SI unhandled vs output type:%d\n",
1196 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
1198 if (target
>= V_008DFC_SQ_EXP_POS
&&
1199 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
1200 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
1201 args
, sizeof(args
));
1203 lp_build_intrinsic(base
->gallivm
->builder
,
1205 LLVMVoidTypeInContext(base
->gallivm
->context
),
1209 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
1210 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1211 goto handle_semantic
;
1215 /* We need to add the position output manually if it's missing. */
1216 if (!pos_args
[0][0]) {
1217 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1218 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
1219 pos_args
[0][2] = uint
->zero
; /* last export? */
1220 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
1221 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
1222 pos_args
[0][5] = base
->zero
; /* X */
1223 pos_args
[0][6] = base
->zero
; /* Y */
1224 pos_args
[0][7] = base
->zero
; /* Z */
1225 pos_args
[0][8] = base
->one
; /* W */
1228 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1229 if (shader
->vs_out_misc_write
) {
1230 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
1231 shader
->vs_out_point_size
|
1232 (shader
->vs_out_edgeflag
<< 1) |
1233 (shader
->vs_out_layer
<< 2));
1234 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
1235 pos_args
[1][2] = uint
->zero
; /* last export? */
1236 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
1237 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
1238 pos_args
[1][5] = base
->zero
; /* X */
1239 pos_args
[1][6] = base
->zero
; /* Y */
1240 pos_args
[1][7] = base
->zero
; /* Z */
1241 pos_args
[1][8] = base
->zero
; /* W */
1243 if (shader
->vs_out_point_size
)
1244 pos_args
[1][5] = psize_value
;
1246 if (shader
->vs_out_edgeflag
) {
1247 /* The output is a float, but the hw expects an integer
1248 * with the first bit containing the edge flag. */
1249 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
1251 bld_base
->uint_bld
.elem_type
, "");
1252 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
1254 bld_base
->int_bld
.one
);
1256 /* The LLVM intrinsic expects a float. */
1257 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
1259 base
->elem_type
, "");
1262 if (shader
->vs_out_layer
)
1263 pos_args
[1][7] = layer_value
;
1266 for (i
= 0; i
< 4; i
++)
1268 shader
->nr_pos_exports
++;
1271 for (i
= 0; i
< 4; i
++) {
1272 if (!pos_args
[i
][0])
1275 /* Specify the target we are exporting */
1276 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
1278 if (pos_idx
== shader
->nr_pos_exports
)
1279 /* Specify that this is the last export */
1280 pos_args
[i
][2] = uint
->one
;
1282 lp_build_intrinsic(base
->gallivm
->builder
,
1284 LLVMVoidTypeInContext(base
->gallivm
->context
),
1289 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
* bld_base
)
1291 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1292 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1293 struct si_shader
*es
= si_shader_ctx
->shader
;
1294 struct tgsi_shader_info
*info
= &es
->selector
->info
;
1295 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1296 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1297 SI_PARAM_ES2GS_OFFSET
);
1298 LLVMValueRef t_list_ptr
;
1299 LLVMValueRef t_list
;
1303 /* Load the ESGS ring resource descriptor */
1304 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1305 SI_PARAM_RW_BUFFERS
);
1306 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
1307 lp_build_const_int32(gallivm
, SI_RING_ESGS
));
1309 for (i
= 0; i
< info
->num_outputs
; i
++) {
1310 LLVMValueRef
*out_ptr
=
1311 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
1312 int param_index
= get_param_index(info
->output_semantic_name
[i
],
1313 info
->output_semantic_index
[i
],
1314 es
->key
.vs
.gs_used_inputs
);
1316 if (param_index
< 0)
1319 for (chan
= 0; chan
< 4; chan
++) {
1320 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
1321 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
1323 build_tbuffer_store(si_shader_ctx
, t_list
, out_val
, 1,
1324 LLVMGetUndef(i32
), soffset
,
1325 (4 * param_index
+ chan
) * 4,
1326 V_008F0C_BUF_DATA_FORMAT_32
,
1327 V_008F0C_BUF_NUM_FORMAT_UINT
,
1333 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
1335 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1336 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1337 LLVMValueRef args
[2];
1339 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
1340 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
1341 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
1342 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
1343 LLVMNoUnwindAttribute
);
1346 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1348 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1349 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1350 struct si_shader
*shader
= si_shader_ctx
->shader
;
1351 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
1352 struct si_shader_output_values
*outputs
= NULL
;
1353 unsigned noutput
= 0;
1356 while (!tgsi_parse_end_of_tokens(parse
)) {
1357 struct tgsi_full_declaration
*d
=
1358 &parse
->FullToken
.FullDeclaration
;
1361 tgsi_parse_token(parse
);
1363 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
1366 i
= si_store_shader_io_attribs(shader
, d
);
1370 outputs
= REALLOC(outputs
, noutput
* sizeof(outputs
[0]),
1371 (noutput
+ 1) * sizeof(outputs
[0]));
1372 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
1373 outputs
[noutput
].index
= index
;
1374 outputs
[noutput
].name
= d
->Semantic
.Name
;
1375 outputs
[noutput
].sid
= d
->Semantic
.Index
;
1377 for (i
= 0; i
< 4; i
++)
1378 outputs
[noutput
].values
[i
] =
1379 LLVMBuildLoad(gallivm
->builder
,
1380 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][i
],
1386 si_llvm_export_vs(bld_base
, outputs
, noutput
);
1390 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1392 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1393 struct si_shader
* shader
= si_shader_ctx
->shader
;
1394 struct lp_build_context
* base
= &bld_base
->base
;
1395 struct lp_build_context
* uint
=
1396 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1397 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
1398 LLVMValueRef args
[9];
1399 LLVMValueRef last_args
[9] = { 0 };
1400 unsigned semantic_name
;
1401 int depth_index
= -1, stencil_index
= -1, samplemask_index
= -1;
1404 while (!tgsi_parse_end_of_tokens(parse
)) {
1405 struct tgsi_full_declaration
*d
=
1406 &parse
->FullToken
.FullDeclaration
;
1410 tgsi_parse_token(parse
);
1412 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
1415 i
= si_store_shader_io_attribs(shader
, d
);
1419 semantic_name
= d
->Semantic
.Name
;
1420 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
1421 /* Select the correct target */
1422 switch(semantic_name
) {
1423 case TGSI_SEMANTIC_POSITION
:
1424 depth_index
= index
;
1426 case TGSI_SEMANTIC_STENCIL
:
1427 stencil_index
= index
;
1429 case TGSI_SEMANTIC_SAMPLEMASK
:
1430 samplemask_index
= index
;
1432 case TGSI_SEMANTIC_COLOR
:
1433 target
= V_008DFC_SQ_EXP_MRT
+ d
->Semantic
.Index
;
1434 if (si_shader_ctx
->shader
->key
.ps
.alpha_to_one
)
1435 LLVMBuildStore(bld_base
->base
.gallivm
->builder
,
1437 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][3]);
1439 if (d
->Semantic
.Index
== 0 &&
1440 si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
1441 si_alpha_test(bld_base
,
1442 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
]);
1447 "Warning: SI unhandled fs output type:%d\n",
1451 si_llvm_init_export_args_load(bld_base
,
1452 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
],
1455 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1456 /* If there is an export instruction waiting to be emitted, do so now. */
1458 lp_build_intrinsic(base
->gallivm
->builder
,
1460 LLVMVoidTypeInContext(base
->gallivm
->context
),
1464 /* This instruction will be emitted at the end of the shader. */
1465 memcpy(last_args
, args
, sizeof(args
));
1467 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1468 if (shader
->selector
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1469 shader
->output
[i
].sid
== 0 &&
1470 si_shader_ctx
->shader
->key
.ps
.last_cbuf
> 0) {
1471 for (int c
= 1; c
<= si_shader_ctx
->shader
->key
.ps
.last_cbuf
; c
++) {
1472 si_llvm_init_export_args_load(bld_base
,
1473 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
],
1474 V_008DFC_SQ_EXP_MRT
+ c
, args
);
1475 lp_build_intrinsic(base
->gallivm
->builder
,
1477 LLVMVoidTypeInContext(base
->gallivm
->context
),
1482 lp_build_intrinsic(base
->gallivm
->builder
,
1484 LLVMVoidTypeInContext(base
->gallivm
->context
),
1490 if (depth_index
>= 0 || stencil_index
>= 0 || samplemask_index
>= 0) {
1491 LLVMValueRef out_ptr
;
1494 /* Specify the target we are exporting */
1495 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
1497 args
[5] = base
->zero
; /* R, depth */
1498 args
[6] = base
->zero
; /* G, stencil test value[0:7], stencil op value[8:15] */
1499 args
[7] = base
->zero
; /* B, sample mask */
1500 args
[8] = base
->zero
; /* A, alpha to mask */
1502 if (depth_index
>= 0) {
1503 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[depth_index
][2];
1504 args
[5] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1506 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
1509 if (stencil_index
>= 0) {
1510 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[stencil_index
][1];
1511 args
[6] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1512 /* Only setting the stencil component bit (0x2) here
1513 * breaks some stencil piglit tests
1516 si_shader_ctx
->shader
->db_shader_control
|=
1517 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1520 if (samplemask_index
>= 0) {
1521 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[samplemask_index
][0];
1522 args
[7] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1523 mask
|= 0xf; /* Set all components. */
1524 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(1);
1527 if (samplemask_index
>= 0)
1528 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_ABGR
;
1529 else if (stencil_index
>= 0)
1530 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
1532 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
1534 /* Specify which components to enable */
1535 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
1539 args
[4] = uint
->zero
;
1542 lp_build_intrinsic(base
->gallivm
->builder
,
1544 LLVMVoidTypeInContext(base
->gallivm
->context
),
1547 memcpy(last_args
, args
, sizeof(args
));
1550 if (!last_args
[0]) {
1551 /* Specify which components to enable */
1552 last_args
[0] = lp_build_const_int32(base
->gallivm
, 0x0);
1554 /* Specify the target we are exporting */
1555 last_args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRT
);
1557 /* Set COMPR flag to zero to export data as 32-bit */
1558 last_args
[4] = uint
->zero
;
1561 last_args
[5]= uint
->zero
;
1562 last_args
[6]= uint
->zero
;
1563 last_args
[7]= uint
->zero
;
1564 last_args
[8]= uint
->zero
;
1567 /* Specify whether the EXEC mask represents the valid mask */
1568 last_args
[1] = uint
->one
;
1570 /* Specify that this is the last export */
1571 last_args
[2] = lp_build_const_int32(base
->gallivm
, 1);
1573 lp_build_intrinsic(base
->gallivm
->builder
,
1575 LLVMVoidTypeInContext(base
->gallivm
->context
),
1579 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1580 struct lp_build_tgsi_context
* bld_base
,
1581 struct lp_build_emit_data
* emit_data
);
1583 static bool tgsi_is_shadow_sampler(unsigned target
)
1585 return target
== TGSI_TEXTURE_SHADOW1D
||
1586 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1587 target
== TGSI_TEXTURE_SHADOW2D
||
1588 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1589 target
== TGSI_TEXTURE_SHADOWCUBE
||
1590 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
1591 target
== TGSI_TEXTURE_SHADOWRECT
;
1594 static const struct lp_build_tgsi_action tex_action
;
1596 static void tex_fetch_args(
1597 struct lp_build_tgsi_context
* bld_base
,
1598 struct lp_build_emit_data
* emit_data
)
1600 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1601 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1602 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
1603 unsigned opcode
= inst
->Instruction
.Opcode
;
1604 unsigned target
= inst
->Texture
.Texture
;
1605 LLVMValueRef coords
[4];
1606 LLVMValueRef address
[16];
1608 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
, &ref_pos
);
1611 unsigned sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1612 unsigned sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
1613 bool has_offset
= HAVE_LLVM
>= 0x0305 ? inst
->Texture
.NumOffsets
> 0 : false;
1615 if (target
== TGSI_TEXTURE_BUFFER
) {
1616 LLVMTypeRef i128
= LLVMIntTypeInContext(gallivm
->context
, 128);
1617 LLVMTypeRef v2i128
= LLVMVectorType(i128
, 2);
1618 LLVMTypeRef i8
= LLVMInt8TypeInContext(gallivm
->context
);
1619 LLVMTypeRef v16i8
= LLVMVectorType(i8
, 16);
1621 /* Bitcast and truncate v8i32 to v16i8. */
1622 LLVMValueRef res
= si_shader_ctx
->resources
[sampler_index
];
1623 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
1624 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.zero
, "");
1625 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v16i8
, "");
1627 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
1628 emit_data
->args
[0] = res
;
1629 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
1630 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
1631 emit_data
->arg_count
= 3;
1635 /* Fetch and project texture coordinates */
1636 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1637 for (chan
= 0; chan
< 3; chan
++ ) {
1638 coords
[chan
] = lp_build_emit_fetch(bld_base
,
1641 if (opcode
== TGSI_OPCODE_TXP
)
1642 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1648 if (opcode
== TGSI_OPCODE_TXP
)
1649 coords
[3] = bld_base
->base
.one
;
1652 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
1653 /* The offsets are six-bit signed integers packed like this:
1654 * X=[5:0], Y=[13:8], and Z=[21:16].
1656 LLVMValueRef offset
[3], pack
;
1658 assert(inst
->Texture
.NumOffsets
== 1);
1660 for (chan
= 0; chan
< 3; chan
++) {
1661 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1662 emit_data
->inst
, 0, chan
);
1663 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
1664 lp_build_const_int32(gallivm
, 0x3f), "");
1666 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
1667 lp_build_const_int32(gallivm
, chan
*8), "");
1670 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
1671 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
1672 address
[count
++] = pack
;
1675 /* Pack LOD bias value */
1676 if (opcode
== TGSI_OPCODE_TXB
)
1677 address
[count
++] = coords
[3];
1678 if (opcode
== TGSI_OPCODE_TXB2
)
1679 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1681 /* Pack depth comparison value */
1682 if (tgsi_is_shadow_sampler(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1683 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1684 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1686 assert(ref_pos
>= 0);
1687 address
[count
++] = coords
[ref_pos
];
1691 if (target
== TGSI_TEXTURE_CUBE
||
1692 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1693 target
== TGSI_TEXTURE_SHADOWCUBE
||
1694 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1695 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
1697 /* Pack user derivatives */
1698 if (opcode
== TGSI_OPCODE_TXD
) {
1699 int num_deriv_channels
, param
;
1702 case TGSI_TEXTURE_3D
:
1703 num_deriv_channels
= 3;
1705 case TGSI_TEXTURE_2D
:
1706 case TGSI_TEXTURE_SHADOW2D
:
1707 case TGSI_TEXTURE_RECT
:
1708 case TGSI_TEXTURE_SHADOWRECT
:
1709 case TGSI_TEXTURE_2D_ARRAY
:
1710 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1711 case TGSI_TEXTURE_CUBE
:
1712 case TGSI_TEXTURE_SHADOWCUBE
:
1713 case TGSI_TEXTURE_CUBE_ARRAY
:
1714 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1715 num_deriv_channels
= 2;
1717 case TGSI_TEXTURE_1D
:
1718 case TGSI_TEXTURE_SHADOW1D
:
1719 case TGSI_TEXTURE_1D_ARRAY
:
1720 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1721 num_deriv_channels
= 1;
1724 assert(0); /* no other targets are valid here */
1727 for (param
= 1; param
<= 2; param
++)
1728 for (chan
= 0; chan
< num_deriv_channels
; chan
++)
1729 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, param
, chan
);
1732 /* Pack texture coordinates */
1733 address
[count
++] = coords
[0];
1735 address
[count
++] = coords
[1];
1737 address
[count
++] = coords
[2];
1739 /* Pack LOD or sample index */
1740 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
1741 address
[count
++] = coords
[3];
1742 else if (opcode
== TGSI_OPCODE_TXL2
)
1743 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1746 assert(!"Cannot handle more than 16 texture address parameters");
1750 for (chan
= 0; chan
< count
; chan
++ ) {
1751 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
1753 LLVMInt32TypeInContext(gallivm
->context
),
1757 /* Adjust the sample index according to FMASK.
1759 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1760 * which is the identity mapping. Each nibble says which physical sample
1761 * should be fetched to get that sample.
1763 * For example, 0x11111100 means there are only 2 samples stored and
1764 * the second sample covers 3/4 of the pixel. When reading samples 0
1765 * and 1, return physical sample 0 (determined by the first two 0s
1766 * in FMASK), otherwise return physical sample 1.
1768 * The sample index should be adjusted as follows:
1769 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1771 if (target
== TGSI_TEXTURE_2D_MSAA
||
1772 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1773 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1774 struct lp_build_emit_data txf_emit_data
= *emit_data
;
1775 LLVMValueRef txf_address
[4];
1776 unsigned txf_count
= count
;
1777 struct tgsi_full_instruction inst
= {};
1779 memcpy(txf_address
, address
, sizeof(txf_address
));
1781 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1782 txf_address
[2] = bld_base
->uint_bld
.zero
;
1784 txf_address
[3] = bld_base
->uint_bld
.zero
;
1786 /* Pad to a power-of-two size. */
1787 while (txf_count
< util_next_power_of_two(txf_count
))
1788 txf_address
[txf_count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1790 /* Read FMASK using TXF. */
1791 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
1792 inst
.Texture
.Texture
= target
== TGSI_TEXTURE_2D_MSAA
? TGSI_TEXTURE_2D
: TGSI_TEXTURE_2D_ARRAY
;
1793 txf_emit_data
.inst
= &inst
;
1794 txf_emit_data
.chan
= 0;
1795 txf_emit_data
.dst_type
= LLVMVectorType(
1796 LLVMInt32TypeInContext(gallivm
->context
), 4);
1797 txf_emit_data
.args
[0] = lp_build_gather_values(gallivm
, txf_address
, txf_count
);
1798 txf_emit_data
.args
[1] = si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
];
1799 txf_emit_data
.args
[2] = lp_build_const_int32(gallivm
, inst
.Texture
.Texture
);
1800 txf_emit_data
.arg_count
= 3;
1802 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
1804 /* Initialize some constants. */
1805 LLVMValueRef four
= LLVMConstInt(uint_bld
->elem_type
, 4, 0);
1806 LLVMValueRef F
= LLVMConstInt(uint_bld
->elem_type
, 0xF, 0);
1808 /* Apply the formula. */
1809 LLVMValueRef fmask
=
1810 LLVMBuildExtractElement(gallivm
->builder
,
1811 txf_emit_data
.output
[0],
1812 uint_bld
->zero
, "");
1814 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
1816 LLVMValueRef sample_index4
=
1817 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
1819 LLVMValueRef shifted_fmask
=
1820 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
1822 LLVMValueRef final_sample
=
1823 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
1825 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1826 * resource descriptor is 0 (invalid),
1828 LLVMValueRef fmask_desc
=
1829 LLVMBuildBitCast(gallivm
->builder
,
1830 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
],
1831 LLVMVectorType(uint_bld
->elem_type
, 8), "");
1833 LLVMValueRef fmask_word1
=
1834 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
1837 LLVMValueRef word1_is_nonzero
=
1838 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1839 fmask_word1
, uint_bld
->zero
, "");
1841 /* Replace the MSAA sample index. */
1842 address
[sample_chan
] =
1843 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
1844 final_sample
, address
[sample_chan
], "");
1848 emit_data
->args
[1] = si_shader_ctx
->resources
[sampler_index
];
1850 if (opcode
== TGSI_OPCODE_TXF
) {
1851 /* add tex offsets */
1852 if (inst
->Texture
.NumOffsets
) {
1853 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1854 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
1855 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
1857 assert(inst
->Texture
.NumOffsets
== 1);
1860 case TGSI_TEXTURE_3D
:
1861 address
[2] = lp_build_add(uint_bld
, address
[2],
1862 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
1864 case TGSI_TEXTURE_2D
:
1865 case TGSI_TEXTURE_SHADOW2D
:
1866 case TGSI_TEXTURE_RECT
:
1867 case TGSI_TEXTURE_SHADOWRECT
:
1868 case TGSI_TEXTURE_2D_ARRAY
:
1869 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1871 lp_build_add(uint_bld
, address
[1],
1872 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
1874 case TGSI_TEXTURE_1D
:
1875 case TGSI_TEXTURE_SHADOW1D
:
1876 case TGSI_TEXTURE_1D_ARRAY
:
1877 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1879 lp_build_add(uint_bld
, address
[0],
1880 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
1882 /* texture offsets do not apply to other texture targets */
1886 emit_data
->args
[2] = lp_build_const_int32(gallivm
, target
);
1887 emit_data
->arg_count
= 3;
1889 emit_data
->dst_type
= LLVMVectorType(
1890 LLVMInt32TypeInContext(gallivm
->context
),
1892 } else if (opcode
== TGSI_OPCODE_TG4
||
1893 opcode
== TGSI_OPCODE_LODQ
||
1895 unsigned is_array
= target
== TGSI_TEXTURE_1D_ARRAY
||
1896 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1897 target
== TGSI_TEXTURE_2D_ARRAY
||
1898 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1899 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1900 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
1901 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
1902 unsigned dmask
= 0xf;
1904 if (opcode
== TGSI_OPCODE_TG4
) {
1905 unsigned gather_comp
= 0;
1907 /* DMASK was repurposed for GATHER4. 4 components are always
1908 * returned and DMASK works like a swizzle - it selects
1909 * the component to fetch. The only valid DMASK values are
1910 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1911 * (red,red,red,red) etc.) The ISA document doesn't mention
1915 /* Get the component index from src1.x for Gather4. */
1916 if (!tgsi_is_shadow_sampler(target
)) {
1917 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
1918 LLVMValueRef comp_imm
;
1919 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1921 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1923 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
1924 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1925 gather_comp
= CLAMP(gather_comp
, 0, 3);
1928 dmask
= 1 << gather_comp
;
1931 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1932 emit_data
->args
[3] = lp_build_const_int32(gallivm
, dmask
);
1933 emit_data
->args
[4] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
1934 emit_data
->args
[5] = lp_build_const_int32(gallivm
, 0); /* r128 */
1935 emit_data
->args
[6] = lp_build_const_int32(gallivm
, is_array
); /* da */
1936 emit_data
->args
[7] = lp_build_const_int32(gallivm
, 0); /* glc */
1937 emit_data
->args
[8] = lp_build_const_int32(gallivm
, 0); /* slc */
1938 emit_data
->args
[9] = lp_build_const_int32(gallivm
, 0); /* tfe */
1939 emit_data
->args
[10] = lp_build_const_int32(gallivm
, 0); /* lwe */
1941 emit_data
->arg_count
= 11;
1943 emit_data
->dst_type
= LLVMVectorType(
1944 LLVMFloatTypeInContext(gallivm
->context
),
1947 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1948 emit_data
->args
[3] = lp_build_const_int32(gallivm
, target
);
1949 emit_data
->arg_count
= 4;
1951 emit_data
->dst_type
= LLVMVectorType(
1952 LLVMFloatTypeInContext(gallivm
->context
),
1956 /* The fetch opcode has been converted to a 2D array fetch.
1957 * This simplifies the LLVM backend. */
1958 if (target
== TGSI_TEXTURE_CUBE_ARRAY
)
1959 target
= TGSI_TEXTURE_2D_ARRAY
;
1960 else if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1961 target
= TGSI_TEXTURE_SHADOW2D_ARRAY
;
1963 /* Pad to power of two vector */
1964 while (count
< util_next_power_of_two(count
))
1965 address
[count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1967 emit_data
->args
[0] = lp_build_gather_values(gallivm
, address
, count
);
1970 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1971 struct lp_build_tgsi_context
* bld_base
,
1972 struct lp_build_emit_data
* emit_data
)
1974 struct lp_build_context
* base
= &bld_base
->base
;
1975 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
1976 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1977 char intr_name
[127];
1978 bool has_offset
= HAVE_LLVM
>= 0x0305 ?
1979 emit_data
->inst
->Texture
.NumOffsets
> 0 : false;
1981 if (target
== TGSI_TEXTURE_BUFFER
) {
1982 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1983 base
->gallivm
->builder
,
1984 "llvm.SI.vs.load.input", emit_data
->dst_type
,
1985 emit_data
->args
, emit_data
->arg_count
,
1986 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1990 if (opcode
== TGSI_OPCODE_TG4
||
1991 opcode
== TGSI_OPCODE_LODQ
||
1992 (opcode
!= TGSI_OPCODE_TXF
&& has_offset
)) {
1993 bool is_shadow
= tgsi_is_shadow_sampler(target
);
1994 const char *name
= "llvm.SI.image.sample";
1995 const char *infix
= "";
1998 case TGSI_OPCODE_TEX
:
1999 case TGSI_OPCODE_TEX2
:
2000 case TGSI_OPCODE_TXP
:
2002 case TGSI_OPCODE_TXB
:
2003 case TGSI_OPCODE_TXB2
:
2006 case TGSI_OPCODE_TXL
:
2007 case TGSI_OPCODE_TXL2
:
2010 case TGSI_OPCODE_TXD
:
2013 case TGSI_OPCODE_TG4
:
2014 name
= "llvm.SI.gather4";
2016 case TGSI_OPCODE_LODQ
:
2017 name
= "llvm.SI.getlod";
2026 /* Add the type and suffixes .c, .o if needed. */
2027 sprintf(intr_name
, "%s%s%s%s.v%ui32", name
,
2028 is_shadow
? ".c" : "", infix
, has_offset
? ".o" : "",
2029 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
2031 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
2032 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
2033 emit_data
->args
, emit_data
->arg_count
,
2034 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
2036 LLVMTypeRef i8
, v16i8
, v32i8
;
2040 case TGSI_OPCODE_TEX
:
2041 case TGSI_OPCODE_TEX2
:
2042 case TGSI_OPCODE_TXP
:
2043 name
= "llvm.SI.sample";
2045 case TGSI_OPCODE_TXB
:
2046 case TGSI_OPCODE_TXB2
:
2047 name
= "llvm.SI.sampleb";
2049 case TGSI_OPCODE_TXD
:
2050 name
= "llvm.SI.sampled";
2052 case TGSI_OPCODE_TXF
:
2053 name
= "llvm.SI.imageload";
2055 case TGSI_OPCODE_TXL
:
2056 case TGSI_OPCODE_TXL2
:
2057 name
= "llvm.SI.samplel";
2064 i8
= LLVMInt8TypeInContext(base
->gallivm
->context
);
2065 v16i8
= LLVMVectorType(i8
, 16);
2066 v32i8
= LLVMVectorType(i8
, 32);
2068 emit_data
->args
[1] = LLVMBuildBitCast(base
->gallivm
->builder
,
2069 emit_data
->args
[1], v32i8
, "");
2070 if (opcode
!= TGSI_OPCODE_TXF
) {
2071 emit_data
->args
[2] = LLVMBuildBitCast(base
->gallivm
->builder
,
2072 emit_data
->args
[2], v16i8
, "");
2075 sprintf(intr_name
, "%s.v%ui32", name
,
2076 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
2078 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
2079 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
2080 emit_data
->args
, emit_data
->arg_count
,
2081 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
2085 static void txq_fetch_args(
2086 struct lp_build_tgsi_context
* bld_base
,
2087 struct lp_build_emit_data
* emit_data
)
2089 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2090 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2091 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2092 unsigned target
= inst
->Texture
.Texture
;
2094 if (target
== TGSI_TEXTURE_BUFFER
) {
2095 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2096 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
2098 /* Read the size from the buffer descriptor directly. */
2099 LLVMValueRef size
= si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2100 size
= LLVMBuildBitCast(gallivm
->builder
, size
, v8i32
, "");
2101 size
= LLVMBuildExtractElement(gallivm
->builder
, size
,
2102 lp_build_const_int32(gallivm
, 2), "");
2103 emit_data
->args
[0] = size
;
2108 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
2111 emit_data
->args
[1] = si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2113 /* Texture target */
2114 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2115 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
2116 target
= TGSI_TEXTURE_2D_ARRAY
;
2118 emit_data
->args
[2] = lp_build_const_int32(bld_base
->base
.gallivm
,
2121 emit_data
->arg_count
= 3;
2123 emit_data
->dst_type
= LLVMVectorType(
2124 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
),
2128 static void build_txq_intrinsic(const struct lp_build_tgsi_action
* action
,
2129 struct lp_build_tgsi_context
* bld_base
,
2130 struct lp_build_emit_data
* emit_data
)
2132 unsigned target
= emit_data
->inst
->Texture
.Texture
;
2134 if (target
== TGSI_TEXTURE_BUFFER
) {
2135 /* Just return the buffer size. */
2136 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
2140 build_tgsi_intrinsic_nomem(action
, bld_base
, emit_data
);
2142 /* Divide the number of layers by 6 to get the number of cubes. */
2143 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2144 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
2145 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2146 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
2147 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
2149 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
2150 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
2151 z
= LLVMBuildSDiv(builder
, z
, six
, "");
2153 emit_data
->output
[emit_data
->chan
] =
2154 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
2158 static void si_llvm_emit_ddxy(
2159 const struct lp_build_tgsi_action
* action
,
2160 struct lp_build_tgsi_context
* bld_base
,
2161 struct lp_build_emit_data
* emit_data
)
2163 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2164 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2165 struct lp_build_context
* base
= &bld_base
->base
;
2166 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2167 unsigned opcode
= inst
->Instruction
.Opcode
;
2168 LLVMValueRef indices
[2];
2169 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
2170 LLVMValueRef tl
, trbl
, result
[4];
2172 unsigned swizzle
[4];
2175 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2177 indices
[0] = bld_base
->uint_bld
.zero
;
2178 indices
[1] = build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
2179 NULL
, 0, LLVMReadNoneAttribute
);
2180 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2183 indices
[1] = LLVMBuildAnd(gallivm
->builder
, indices
[1],
2184 lp_build_const_int32(gallivm
, 0xfffffffc), "");
2185 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2188 indices
[1] = LLVMBuildAdd(gallivm
->builder
, indices
[1],
2189 lp_build_const_int32(gallivm
,
2190 opcode
== TGSI_OPCODE_DDX
? 1 : 2),
2192 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2195 for (c
= 0; c
< 4; ++c
) {
2198 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
2199 for (i
= 0; i
< c
; ++i
) {
2200 if (swizzle
[i
] == swizzle
[c
]) {
2201 result
[c
] = result
[i
];
2208 LLVMBuildStore(gallivm
->builder
,
2209 LLVMBuildBitCast(gallivm
->builder
,
2210 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
2214 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
2215 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
2217 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
2218 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, base
->elem_type
, "");
2220 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
2223 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
2226 /* Emit one vertex from the geometry shader */
2227 static void si_llvm_emit_vertex(
2228 const struct lp_build_tgsi_action
*action
,
2229 struct lp_build_tgsi_context
*bld_base
,
2230 struct lp_build_emit_data
*emit_data
)
2232 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2233 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2234 struct si_shader
*shader
= si_shader_ctx
->shader
;
2235 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2236 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2237 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2238 SI_PARAM_GS2VS_OFFSET
);
2239 LLVMValueRef gs_next_vertex
;
2240 LLVMValueRef can_emit
, kill
;
2241 LLVMValueRef t_list_ptr
;
2242 LLVMValueRef t_list
;
2243 LLVMValueRef args
[2];
2247 /* Load the GSVS ring resource descriptor */
2248 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2249 SI_PARAM_RW_BUFFERS
);
2250 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
2251 lp_build_const_int32(gallivm
, SI_RING_GSVS
));
2253 if (shader
->noutput
== 0) {
2254 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
2256 while (!tgsi_parse_end_of_tokens(parse
)) {
2257 tgsi_parse_token(parse
);
2259 if (parse
->FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
2260 struct tgsi_full_declaration
*d
= &parse
->FullToken
.FullDeclaration
;
2262 if (d
->Declaration
.File
== TGSI_FILE_OUTPUT
)
2263 si_store_shader_io_attribs(shader
, d
);
2268 /* Write vertex attribute values to GSVS ring */
2269 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
, si_shader_ctx
->gs_next_vertex
, "");
2271 /* If this thread has already emitted the declared maximum number of
2272 * vertices, kill it: excessive vertex emissions are not supposed to
2273 * have any effect, and GS threads have no externally observable
2274 * effects other than emitting vertices.
2276 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
2277 lp_build_const_int32(gallivm
,
2278 shader
->selector
->gs_max_out_vertices
), "");
2279 kill
= lp_build_select(&bld_base
->base
, can_emit
,
2280 lp_build_const_float(gallivm
, 1.0f
),
2281 lp_build_const_float(gallivm
, -1.0f
));
2282 build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2283 LLVMVoidTypeInContext(gallivm
->context
), &kill
, 1, 0);
2285 for (i
= 0; i
< shader
->noutput
; i
++) {
2286 LLVMValueRef
*out_ptr
=
2287 si_shader_ctx
->radeon_bld
.soa
.outputs
[shader
->output
[i
].index
];
2289 for (chan
= 0; chan
< 4; chan
++) {
2290 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2291 LLVMValueRef voffset
=
2292 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
2293 shader
->selector
->gs_max_out_vertices
);
2295 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
2296 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
2298 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
2300 build_tbuffer_store(si_shader_ctx
, t_list
, out_val
, 1,
2301 voffset
, soffset
, 0,
2302 V_008F0C_BUF_DATA_FORMAT_32
,
2303 V_008F0C_BUF_NUM_FORMAT_UINT
,
2307 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
2308 lp_build_const_int32(gallivm
, 1));
2309 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, si_shader_ctx
->gs_next_vertex
);
2311 /* Signal vertex emission */
2312 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
);
2313 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2314 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2315 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2316 LLVMNoUnwindAttribute
);
2319 /* Cut one primitive from the geometry shader */
2320 static void si_llvm_emit_primitive(
2321 const struct lp_build_tgsi_action
*action
,
2322 struct lp_build_tgsi_context
*bld_base
,
2323 struct lp_build_emit_data
*emit_data
)
2325 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2326 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2327 LLVMValueRef args
[2];
2329 /* Signal primitive cut */
2330 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
);
2331 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2332 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2333 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2334 LLVMNoUnwindAttribute
);
2337 static const struct lp_build_tgsi_action tex_action
= {
2338 .fetch_args
= tex_fetch_args
,
2339 .emit
= build_tex_intrinsic
,
2342 static const struct lp_build_tgsi_action txq_action
= {
2343 .fetch_args
= txq_fetch_args
,
2344 .emit
= build_txq_intrinsic
,
2345 .intr_name
= "llvm.SI.resinfo"
2348 static void create_meta_data(struct si_shader_context
*si_shader_ctx
)
2350 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
2351 LLVMValueRef args
[3];
2353 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
2355 args
[2] = lp_build_const_int32(gallivm
, 1);
2357 si_shader_ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
2360 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
2362 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
2366 static void create_function(struct si_shader_context
*si_shader_ctx
)
2368 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2369 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2370 struct si_shader
*shader
= si_shader_ctx
->shader
;
2371 LLVMTypeRef params
[SI_NUM_PARAMS
], f32
, i8
, i32
, v2i32
, v3i32
, v16i8
, v4i32
, v8i32
;
2372 unsigned i
, last_array_pointer
, last_sgpr
, num_params
;
2374 i8
= LLVMInt8TypeInContext(gallivm
->context
);
2375 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2376 f32
= LLVMFloatTypeInContext(gallivm
->context
);
2377 v2i32
= LLVMVectorType(i32
, 2);
2378 v3i32
= LLVMVectorType(i32
, 3);
2379 v4i32
= LLVMVectorType(i32
, 4);
2380 v8i32
= LLVMVectorType(i32
, 8);
2381 v16i8
= LLVMVectorType(i8
, 16);
2383 params
[SI_PARAM_RW_BUFFERS
] = const_array(v16i8
, SI_NUM_RW_BUFFERS
);
2384 params
[SI_PARAM_CONST
] = const_array(v16i8
, SI_NUM_CONST_BUFFERS
);
2385 params
[SI_PARAM_SAMPLER
] = const_array(v4i32
, SI_NUM_SAMPLER_STATES
);
2386 params
[SI_PARAM_RESOURCE
] = const_array(v8i32
, SI_NUM_SAMPLER_VIEWS
);
2387 last_array_pointer
= SI_PARAM_RESOURCE
;
2389 switch (si_shader_ctx
->type
) {
2390 case TGSI_PROCESSOR_VERTEX
:
2391 params
[SI_PARAM_VERTEX_BUFFER
] = const_array(v16i8
, SI_NUM_VERTEX_BUFFERS
);
2392 last_array_pointer
= SI_PARAM_VERTEX_BUFFER
;
2393 params
[SI_PARAM_BASE_VERTEX
] = i32
;
2394 params
[SI_PARAM_START_INSTANCE
] = i32
;
2395 num_params
= SI_PARAM_START_INSTANCE
+1;
2397 if (shader
->key
.vs
.as_es
) {
2398 params
[SI_PARAM_ES2GS_OFFSET
] = i32
;
2401 if (shader
->is_gs_copy_shader
) {
2402 last_array_pointer
= SI_PARAM_CONST
;
2403 num_params
= SI_PARAM_CONST
+1;
2406 /* The locations of the other parameters are assigned dynamically. */
2408 /* Streamout SGPRs. */
2409 if (shader
->selector
->so
.num_outputs
) {
2410 params
[si_shader_ctx
->param_streamout_config
= num_params
++] = i32
;
2411 params
[si_shader_ctx
->param_streamout_write_index
= num_params
++] = i32
;
2413 /* A streamout buffer offset is loaded if the stride is non-zero. */
2414 for (i
= 0; i
< 4; i
++) {
2415 if (!shader
->selector
->so
.stride
[i
])
2418 params
[si_shader_ctx
->param_streamout_offset
[i
] = num_params
++] = i32
;
2422 last_sgpr
= num_params
-1;
2425 params
[si_shader_ctx
->param_vertex_id
= num_params
++] = i32
;
2426 params
[num_params
++] = i32
; /* unused*/
2427 params
[num_params
++] = i32
; /* unused */
2428 params
[si_shader_ctx
->param_instance_id
= num_params
++] = i32
;
2431 case TGSI_PROCESSOR_GEOMETRY
:
2432 params
[SI_PARAM_GS2VS_OFFSET
] = i32
;
2433 params
[SI_PARAM_GS_WAVE_ID
] = i32
;
2434 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
2437 params
[SI_PARAM_VTX0_OFFSET
] = i32
;
2438 params
[SI_PARAM_VTX1_OFFSET
] = i32
;
2439 params
[SI_PARAM_PRIMITIVE_ID
] = i32
;
2440 params
[SI_PARAM_VTX2_OFFSET
] = i32
;
2441 params
[SI_PARAM_VTX3_OFFSET
] = i32
;
2442 params
[SI_PARAM_VTX4_OFFSET
] = i32
;
2443 params
[SI_PARAM_VTX5_OFFSET
] = i32
;
2444 params
[SI_PARAM_GS_INSTANCE_ID
] = i32
;
2445 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
2448 case TGSI_PROCESSOR_FRAGMENT
:
2449 params
[SI_PARAM_ALPHA_REF
] = f32
;
2450 params
[SI_PARAM_PRIM_MASK
] = i32
;
2451 last_sgpr
= SI_PARAM_PRIM_MASK
;
2452 params
[SI_PARAM_PERSP_SAMPLE
] = v2i32
;
2453 params
[SI_PARAM_PERSP_CENTER
] = v2i32
;
2454 params
[SI_PARAM_PERSP_CENTROID
] = v2i32
;
2455 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
2456 params
[SI_PARAM_LINEAR_SAMPLE
] = v2i32
;
2457 params
[SI_PARAM_LINEAR_CENTER
] = v2i32
;
2458 params
[SI_PARAM_LINEAR_CENTROID
] = v2i32
;
2459 params
[SI_PARAM_LINE_STIPPLE_TEX
] = f32
;
2460 params
[SI_PARAM_POS_X_FLOAT
] = f32
;
2461 params
[SI_PARAM_POS_Y_FLOAT
] = f32
;
2462 params
[SI_PARAM_POS_Z_FLOAT
] = f32
;
2463 params
[SI_PARAM_POS_W_FLOAT
] = f32
;
2464 params
[SI_PARAM_FRONT_FACE
] = f32
;
2465 params
[SI_PARAM_ANCILLARY
] = i32
;
2466 params
[SI_PARAM_SAMPLE_COVERAGE
] = f32
;
2467 params
[SI_PARAM_POS_FIXED_PT
] = f32
;
2468 num_params
= SI_PARAM_POS_FIXED_PT
+1;
2472 assert(0 && "unimplemented shader");
2476 assert(num_params
<= Elements(params
));
2477 radeon_llvm_create_func(&si_shader_ctx
->radeon_bld
, params
, num_params
);
2478 radeon_llvm_shader_type(si_shader_ctx
->radeon_bld
.main_fn
, si_shader_ctx
->type
);
2480 for (i
= 0; i
<= last_sgpr
; ++i
) {
2481 LLVMValueRef P
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, i
);
2483 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2484 * to move load. Inputs are constant so this is fine. */
2485 if (i
<= last_array_pointer
)
2486 LLVMAddAttribute(P
, LLVMByValAttribute
);
2488 LLVMAddAttribute(P
, LLVMInRegAttribute
);
2491 if (bld_base
->info
&&
2492 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
2493 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0))
2494 si_shader_ctx
->ddxy_lds
=
2495 LLVMAddGlobalInAddressSpace(gallivm
->module
,
2496 LLVMArrayType(i32
, 64),
2501 static void preload_constants(struct si_shader_context
*si_shader_ctx
)
2503 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2504 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2505 const struct tgsi_shader_info
* info
= bld_base
->info
;
2507 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
2509 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
2510 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
2515 /* Allocate space for the constant values */
2516 si_shader_ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
2518 /* Load the resource descriptor */
2519 si_shader_ctx
->const_resource
[buf
] =
2520 build_indexed_load(si_shader_ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
2522 /* Load the constants, we rely on the code sinking to do the rest */
2523 for (i
= 0; i
< num_const
* 4; ++i
) {
2524 si_shader_ctx
->constants
[buf
][i
] =
2525 load_const(gallivm
->builder
,
2526 si_shader_ctx
->const_resource
[buf
],
2527 lp_build_const_int32(gallivm
, i
* 4),
2528 bld_base
->base
.elem_type
);
2533 static void preload_samplers(struct si_shader_context
*si_shader_ctx
)
2535 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2536 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2537 const struct tgsi_shader_info
* info
= bld_base
->info
;
2539 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
2541 LLVMValueRef res_ptr
, samp_ptr
;
2542 LLVMValueRef offset
;
2544 if (num_samplers
== 0)
2547 /* Allocate space for the values */
2548 si_shader_ctx
->resources
= CALLOC(SI_NUM_SAMPLER_VIEWS
, sizeof(LLVMValueRef
));
2549 si_shader_ctx
->samplers
= CALLOC(num_samplers
, sizeof(LLVMValueRef
));
2551 res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_RESOURCE
);
2552 samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER
);
2554 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2555 for (i
= 0; i
< num_samplers
; ++i
) {
2557 offset
= lp_build_const_int32(gallivm
, i
);
2558 si_shader_ctx
->resources
[i
] = build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
2561 offset
= lp_build_const_int32(gallivm
, i
);
2562 si_shader_ctx
->samplers
[i
] = build_indexed_load(si_shader_ctx
, samp_ptr
, offset
);
2564 /* FMASK resource */
2565 if (info
->is_msaa_sampler
[i
]) {
2566 offset
= lp_build_const_int32(gallivm
, SI_FMASK_TEX_OFFSET
+ i
);
2567 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ i
] =
2568 build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
2573 static void preload_streamout_buffers(struct si_shader_context
*si_shader_ctx
)
2575 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2576 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2579 if (si_shader_ctx
->type
!= TGSI_PROCESSOR_VERTEX
||
2580 si_shader_ctx
->shader
->key
.vs
.as_es
||
2581 !si_shader_ctx
->shader
->selector
->so
.num_outputs
)
2584 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2585 SI_PARAM_RW_BUFFERS
);
2587 /* Load the resources, we rely on the code sinking to do the rest */
2588 for (i
= 0; i
< 4; ++i
) {
2589 if (si_shader_ctx
->shader
->selector
->so
.stride
[i
]) {
2590 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
2591 SI_SO_BUF_OFFSET
+ i
);
2593 si_shader_ctx
->so_buffers
[i
] = build_indexed_load(si_shader_ctx
, buf_ptr
, offset
);
2598 int si_compile_llvm(struct si_screen
*sscreen
, struct si_shader
*shader
,
2601 unsigned r
; /* llvm_compile result */
2604 struct radeon_shader_binary binary
;
2605 bool dump
= r600_can_dump_shader(&sscreen
->b
,
2606 shader
->selector
? shader
->selector
->tokens
: NULL
);
2607 const char * gpu_family
= r600_get_llvm_processor_name(sscreen
->b
.family
);
2610 /* Use LLVM to compile shader */
2611 memset(&binary
, 0, sizeof(binary
));
2612 r
= radeon_llvm_compile(mod
, &binary
, gpu_family
, dump
);
2614 /* Output binary dump if rscreen->debug_flags are set */
2615 if (dump
&& ! binary
.disassembled
) {
2616 fprintf(stderr
, "SI CODE:\n");
2617 for (i
= 0; i
< binary
.code_size
; i
+=4 ) {
2618 fprintf(stderr
, "%02x%02x%02x%02x\n", binary
.code
[i
+ 3],
2619 binary
.code
[i
+ 2], binary
.code
[i
+ 1],
2624 /* XXX: We may be able to emit some of these values directly rather than
2625 * extracting fields to be emitted later.
2627 /* Parse config data in compiled binary */
2628 for (i
= 0; i
< binary
.config_size
; i
+= 8) {
2629 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
));
2630 unsigned value
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
+ 4));
2632 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
2633 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
2634 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
2635 case R_00B848_COMPUTE_PGM_RSRC1
:
2636 shader
->num_sgprs
= (G_00B028_SGPRS(value
) + 1) * 8;
2637 shader
->num_vgprs
= (G_00B028_VGPRS(value
) + 1) * 4;
2639 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
2640 shader
->lds_size
= G_00B02C_EXTRA_LDS_SIZE(value
);
2642 case R_00B84C_COMPUTE_PGM_RSRC2
:
2643 shader
->lds_size
= G_00B84C_LDS_SIZE(value
);
2645 case R_0286CC_SPI_PS_INPUT_ENA
:
2646 shader
->spi_ps_input_ena
= value
;
2648 case R_00B860_COMPUTE_TMPRING_SIZE
:
2649 /* WAVESIZE is in units of 256 dwords. */
2650 shader
->scratch_bytes_per_wave
=
2651 G_00B860_WAVESIZE(value
) * 256 * 4 * 1;
2654 fprintf(stderr
, "Warning: Compiler emitted unknown "
2655 "config register: 0x%x\n", reg
);
2660 /* copy new shader */
2661 code_size
= binary
.code_size
+ binary
.rodata_size
;
2662 r600_resource_reference(&shader
->bo
, NULL
);
2663 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
, PIPE_USAGE_IMMUTABLE
,
2665 if (shader
->bo
== NULL
) {
2669 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
2670 util_memcpy_cpu_to_le32(ptr
, binary
.code
, binary
.code_size
);
2671 if (binary
.rodata_size
> 0) {
2672 ptr
+= binary
.code_size
;
2673 util_memcpy_cpu_to_le32(ptr
, binary
.rodata
, binary
.rodata_size
);
2676 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->cs_buf
);
2679 free(binary
.config
);
2680 free(binary
.rodata
);
2685 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2686 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
2687 struct si_shader_context
*si_shader_ctx
,
2688 struct si_shader
*gs
, bool dump
)
2690 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
2691 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2692 struct lp_build_context
*base
= &bld_base
->base
;
2693 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2694 struct si_shader
*shader
= si_shader_ctx
->shader
;
2695 struct si_shader_output_values
*outputs
;
2696 LLVMValueRef t_list_ptr
, t_list
;
2697 LLVMValueRef args
[9];
2700 outputs
= MALLOC(gs
->noutput
* sizeof(outputs
[0]));
2702 si_shader_ctx
->type
= TGSI_PROCESSOR_VERTEX
;
2703 shader
->is_gs_copy_shader
= true;
2705 radeon_llvm_context_init(&si_shader_ctx
->radeon_bld
);
2707 create_meta_data(si_shader_ctx
);
2708 create_function(si_shader_ctx
);
2709 preload_streamout_buffers(si_shader_ctx
);
2711 /* Load the GSVS ring resource descriptor */
2712 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2713 SI_PARAM_RW_BUFFERS
);
2714 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
2715 lp_build_const_int32(gallivm
, SI_RING_GSVS
));
2718 args
[1] = lp_build_mul_imm(uint
,
2719 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2720 si_shader_ctx
->param_vertex_id
),
2722 args
[3] = uint
->zero
;
2723 args
[4] = uint
->one
; /* OFFEN */
2724 args
[5] = uint
->zero
; /* IDXEN */
2725 args
[6] = uint
->one
; /* GLC */
2726 args
[7] = uint
->one
; /* SLC */
2727 args
[8] = uint
->zero
; /* TFE */
2729 /* Fetch vertex data from GSVS ring */
2730 for (i
= 0; i
< gs
->noutput
; ++i
) {
2731 struct si_shader_output
*out
= gs
->output
+ i
;
2734 shader
->output
[i
] = *out
;
2736 outputs
[i
].name
= out
->name
;
2737 outputs
[i
].index
= out
->index
;
2738 outputs
[i
].sid
= out
->sid
;
2740 for (chan
= 0; chan
< 4; chan
++) {
2741 args
[2] = lp_build_const_int32(gallivm
,
2743 gs
->selector
->gs_max_out_vertices
* 16 * 4);
2745 outputs
[i
].values
[chan
] =
2746 LLVMBuildBitCast(gallivm
->builder
,
2747 build_intrinsic(gallivm
->builder
,
2748 "llvm.SI.buffer.load.dword.i32.i32",
2749 LLVMInt32TypeInContext(gallivm
->context
),
2751 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
2752 base
->elem_type
, "");
2755 shader
->noutput
= gs
->noutput
;
2757 si_llvm_export_vs(bld_base
, outputs
, gs
->noutput
);
2759 radeon_llvm_finalize_module(&si_shader_ctx
->radeon_bld
);
2762 fprintf(stderr
, "Copy Vertex Shader for Geometry Shader:\n\n");
2764 r
= si_compile_llvm(sscreen
, si_shader_ctx
->shader
,
2765 bld_base
->base
.gallivm
->module
);
2767 radeon_llvm_dispose(&si_shader_ctx
->radeon_bld
);
2773 int si_shader_create(struct si_screen
*sscreen
, struct si_shader
*shader
)
2775 struct si_shader_selector
*sel
= shader
->selector
;
2776 struct si_shader_context si_shader_ctx
;
2777 struct lp_build_tgsi_context
* bld_base
;
2780 bool dump
= r600_can_dump_shader(&sscreen
->b
, sel
->tokens
);
2782 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2783 * conversion fails. */
2785 tgsi_dump(sel
->tokens
, 0);
2786 si_dump_streamout(&sel
->so
);
2789 assert(shader
->noutput
== 0);
2790 assert(shader
->nparam
== 0);
2791 assert(shader
->ninput
== 0);
2793 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
2794 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
2795 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
2797 if (sel
->info
.uses_kill
)
2798 shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
2800 shader
->uses_instanceid
= sel
->info
.uses_instanceid
;
2801 bld_base
->info
= &sel
->info
;
2802 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
2804 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
2805 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
2806 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
2807 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
2808 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
2809 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
2810 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
2811 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
2812 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
2813 bld_base
->op_actions
[TGSI_OPCODE_TXQ
] = txq_action
;
2814 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
2815 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
2817 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
2818 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
2820 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
2821 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
2823 si_shader_ctx
.radeon_bld
.load_system_value
= declare_system_value
;
2824 si_shader_ctx
.tokens
= sel
->tokens
;
2825 tgsi_parse_init(&si_shader_ctx
.parse
, si_shader_ctx
.tokens
);
2826 si_shader_ctx
.shader
= shader
;
2827 si_shader_ctx
.type
= si_shader_ctx
.parse
.FullHeader
.Processor
.Processor
;
2829 switch (si_shader_ctx
.type
) {
2830 case TGSI_PROCESSOR_VERTEX
:
2831 si_shader_ctx
.radeon_bld
.load_input
= declare_input_vs
;
2832 if (shader
->key
.vs
.as_es
) {
2833 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
2835 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
2838 case TGSI_PROCESSOR_GEOMETRY
:
2839 si_shader_ctx
.radeon_bld
.load_input
= declare_input_gs
;
2840 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
2841 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
2843 case TGSI_PROCESSOR_FRAGMENT
:
2844 si_shader_ctx
.radeon_bld
.load_input
= declare_input_fs
;
2845 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
2847 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2848 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2849 shader
->db_shader_control
|=
2850 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2852 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2853 shader
->db_shader_control
|=
2854 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2859 assert(!"Unsupported shader type");
2863 create_meta_data(&si_shader_ctx
);
2864 create_function(&si_shader_ctx
);
2865 preload_constants(&si_shader_ctx
);
2866 preload_samplers(&si_shader_ctx
);
2867 preload_streamout_buffers(&si_shader_ctx
);
2869 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2870 si_shader_ctx
.gs_next_vertex
=
2871 lp_build_alloca(bld_base
->base
.gallivm
,
2872 bld_base
->uint_bld
.elem_type
, "");
2875 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
2876 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
2880 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
2882 mod
= bld_base
->base
.gallivm
->module
;
2883 r
= si_compile_llvm(sscreen
, shader
, mod
);
2885 fprintf(stderr
, "LLVM failed to compile shader\n");
2889 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
2891 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2892 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
2893 shader
->gs_copy_shader
->selector
= shader
->selector
;
2894 shader
->gs_copy_shader
->key
= shader
->key
;
2895 si_shader_ctx
.shader
= shader
->gs_copy_shader
;
2896 if ((r
= si_generate_gs_copy_shader(sscreen
, &si_shader_ctx
,
2898 free(shader
->gs_copy_shader
);
2899 shader
->gs_copy_shader
= NULL
;
2904 tgsi_parse_free(&si_shader_ctx
.parse
);
2907 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
2908 FREE(si_shader_ctx
.constants
[i
]);
2909 FREE(si_shader_ctx
.resources
);
2910 FREE(si_shader_ctx
.samplers
);
2915 void si_shader_destroy(struct pipe_context
*ctx
, struct si_shader
*shader
)
2917 if (shader
->gs_copy_shader
)
2918 si_shader_destroy(ctx
, shader
->gs_copy_shader
);
2920 r600_resource_reference(&shader
->bo
, NULL
);
2921 r600_resource_reference(&shader
->scratch_bo
, NULL
);