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radeonsi: only use new versions of LLVM image and sample intrinsics
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Given a semantic name and index of a parameter and a mask of used parameters
168 * (inputs or outputs), return the index of the parameter in the list of all
169 * used parameters.
170 *
171 * For example, assume this list of parameters:
172 * POSITION, PSIZE, GENERIC0, GENERIC2
173 * which has the mask:
174 * 11000000000101
175 * Then:
176 * querying POSITION returns 0,
177 * querying PSIZE returns 1,
178 * querying GENERIC0 returns 2,
179 * querying GENERIC2 returns 3.
180 *
181 * Which can be used as an offset to a parameter buffer in units of vec4s.
182 */
183 static int get_param_index(unsigned semantic_name, unsigned index,
184 uint64_t mask)
185 {
186 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
187 int i, param_index = 0;
188
189 /* If not present... */
190 if (!((1llu << unique_index) & mask))
191 return -1;
192
193 for (i = 0; mask; i++) {
194 uint64_t bit = 1llu << i;
195
196 if (bit & mask) {
197 if (i == unique_index)
198 return param_index;
199
200 mask &= ~bit;
201 param_index++;
202 }
203 }
204
205 assert(!"unreachable");
206 return -1;
207 }
208
209 /**
210 * Get the value of a shader input parameter and extract a bitfield.
211 */
212 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
213 unsigned param, unsigned rshift,
214 unsigned bitwidth)
215 {
216 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
217 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
218 param);
219
220 if (rshift)
221 value = LLVMBuildLShr(gallivm->builder, value,
222 lp_build_const_int32(gallivm, rshift), "");
223
224 if (rshift + bitwidth < 32) {
225 unsigned mask = (1 << bitwidth) - 1;
226 value = LLVMBuildAnd(gallivm->builder, value,
227 lp_build_const_int32(gallivm, mask), "");
228 }
229
230 return value;
231 }
232
233 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
234 {
235 switch (si_shader_ctx->type) {
236 case TGSI_PROCESSOR_TESS_CTRL:
237 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
238
239 case TGSI_PROCESSOR_TESS_EVAL:
240 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
241 si_shader_ctx->param_tes_rel_patch_id);
242
243 default:
244 assert(0);
245 return NULL;
246 }
247 }
248
249 /* Tessellation shaders pass outputs to the next shader using LDS.
250 *
251 * LS outputs = TCS inputs
252 * TCS outputs = TES inputs
253 *
254 * The LDS layout is:
255 * - TCS inputs for patch 0
256 * - TCS inputs for patch 1
257 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
258 * - ...
259 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
260 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
261 * - TCS outputs for patch 1
262 * - Per-patch TCS outputs for patch 1
263 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
264 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
265 * - ...
266 *
267 * All three shaders VS(LS), TCS, TES share the same LDS space.
268 */
269
270 static LLVMValueRef
271 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
272 {
273 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
274 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
275 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
276 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
277 else {
278 assert(0);
279 return NULL;
280 }
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
285 {
286 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
287 }
288
289 static LLVMValueRef
290 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
291 {
292 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
293 unpack_param(si_shader_ctx,
294 SI_PARAM_TCS_OUT_OFFSETS,
295 0, 16),
296 4);
297 }
298
299 static LLVMValueRef
300 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
301 {
302 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
303 unpack_param(si_shader_ctx,
304 SI_PARAM_TCS_OUT_OFFSETS,
305 16, 16),
306 4);
307 }
308
309 static LLVMValueRef
310 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
311 {
312 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
313 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
315
316 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
321 {
322 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
323 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
326
327 return LLVMBuildAdd(gallivm->builder, patch0_offset,
328 LLVMBuildMul(gallivm->builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 static LLVMValueRef
334 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
335 {
336 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
337 LLVMValueRef patch0_patch_data_offset =
338 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index,
350 LLVMValueRef value)
351 {
352 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
353 struct gallivm_state *gallivm = bld_base->base.gallivm;
354 LLVMValueRef indices[2], pointer;
355
356 indices[0] = bld_base->uint_bld.zero;
357 indices[1] = index;
358
359 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
360 LLVMBuildStore(gallivm->builder, value, pointer);
361 }
362
363 /**
364 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
365 * It's equivalent to doing a load from &base_ptr[index].
366 *
367 * \param base_ptr Where the array starts.
368 * \param index The element index into the array.
369 */
370 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
374 struct gallivm_state *gallivm = bld_base->base.gallivm;
375 LLVMValueRef indices[2], pointer;
376
377 indices[0] = bld_base->uint_bld.zero;
378 indices[1] = index;
379
380 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
381 return LLVMBuildLoad(gallivm->builder, pointer, "");
382 }
383
384 /**
385 * Do a load from &base_ptr[index], but also add a flag that it's loading
386 * a constant.
387 */
388 static LLVMValueRef build_indexed_load_const(
389 struct si_shader_context * si_shader_ctx,
390 LLVMValueRef base_ptr, LLVMValueRef index)
391 {
392 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
393 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
394 return result;
395 }
396
397 static LLVMValueRef get_instance_index_for_fetch(
398 struct radeon_llvm_context * radeon_bld,
399 unsigned divisor)
400 {
401 struct si_shader_context *si_shader_ctx =
402 si_shader_context(&radeon_bld->soa.bld_base);
403 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
404
405 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
406 si_shader_ctx->param_instance_id);
407
408 /* The division must be done before START_INSTANCE is added. */
409 if (divisor > 1)
410 result = LLVMBuildUDiv(gallivm->builder, result,
411 lp_build_const_int32(gallivm, divisor), "");
412
413 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
414 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
415 }
416
417 static void declare_input_vs(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned input_index,
420 const struct tgsi_full_declaration *decl)
421 {
422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
423 struct gallivm_state *gallivm = base->gallivm;
424 struct si_shader_context *si_shader_ctx =
425 si_shader_context(&radeon_bld->soa.bld_base);
426 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
427
428 unsigned chan;
429
430 LLVMValueRef t_list_ptr;
431 LLVMValueRef t_offset;
432 LLVMValueRef t_list;
433 LLVMValueRef attribute_offset;
434 LLVMValueRef buffer_index;
435 LLVMValueRef args[3];
436 LLVMTypeRef vec4_type;
437 LLVMValueRef input;
438
439 /* Load the T list */
440 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
441
442 t_offset = lp_build_const_int32(gallivm, input_index);
443
444 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
445
446 /* Build the attribute offset */
447 attribute_offset = lp_build_const_int32(gallivm, 0);
448
449 if (divisor) {
450 /* Build index from instance ID, start instance and divisor */
451 si_shader_ctx->shader->uses_instanceid = true;
452 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
453 } else {
454 /* Load the buffer index for vertices. */
455 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_vertex_id);
457 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
458 SI_PARAM_BASE_VERTEX);
459 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
460 }
461
462 vec4_type = LLVMVectorType(base->elem_type, 4);
463 args[0] = t_list;
464 args[1] = attribute_offset;
465 args[2] = buffer_index;
466 input = lp_build_intrinsic(gallivm->builder,
467 "llvm.SI.vs.load.input", vec4_type, args, 3,
468 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
469
470 /* Break up the vec4 into individual components */
471 for (chan = 0; chan < 4; chan++) {
472 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
473 /* XXX: Use a helper function for this. There is one in
474 * tgsi_llvm.c. */
475 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
476 LLVMBuildExtractElement(gallivm->builder,
477 input, llvm_chan, "");
478 }
479 }
480
481 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
482 unsigned swizzle)
483 {
484 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
485
486 if (swizzle > 0)
487 return bld_base->uint_bld.zero;
488
489 switch (si_shader_ctx->type) {
490 case TGSI_PROCESSOR_VERTEX:
491 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
492 si_shader_ctx->param_vs_prim_id);
493 case TGSI_PROCESSOR_TESS_CTRL:
494 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
495 SI_PARAM_PATCH_ID);
496 case TGSI_PROCESSOR_TESS_EVAL:
497 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
498 si_shader_ctx->param_tes_patch_id);
499 case TGSI_PROCESSOR_GEOMETRY:
500 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
501 SI_PARAM_PRIMITIVE_ID);
502 default:
503 assert(0);
504 return bld_base->uint_bld.zero;
505 }
506 }
507
508 /**
509 * Return the value of tgsi_ind_register for indexing.
510 * This is the indirect index with the constant offset added to it.
511 */
512 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
513 const struct tgsi_ind_register *ind,
514 int rel_index)
515 {
516 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
517 LLVMValueRef result;
518
519 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
520 result = LLVMBuildLoad(gallivm->builder, result, "");
521 result = LLVMBuildAdd(gallivm->builder, result,
522 lp_build_const_int32(gallivm, rel_index), "");
523 return result;
524 }
525
526 /**
527 * Calculate a dword address given an input or output register and a stride.
528 */
529 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
530 const struct tgsi_full_dst_register *dst,
531 const struct tgsi_full_src_register *src,
532 LLVMValueRef vertex_dw_stride,
533 LLVMValueRef base_addr)
534 {
535 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
536 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
537 ubyte *name, *index, *array_first;
538 int first, param;
539 struct tgsi_full_dst_register reg;
540
541 /* Set the register description. The address computation is the same
542 * for sources and destinations. */
543 if (src) {
544 reg.Register.File = src->Register.File;
545 reg.Register.Index = src->Register.Index;
546 reg.Register.Indirect = src->Register.Indirect;
547 reg.Register.Dimension = src->Register.Dimension;
548 reg.Indirect = src->Indirect;
549 reg.Dimension = src->Dimension;
550 reg.DimIndirect = src->DimIndirect;
551 } else
552 reg = *dst;
553
554 /* If the register is 2-dimensional (e.g. an array of vertices
555 * in a primitive), calculate the base address of the vertex. */
556 if (reg.Register.Dimension) {
557 LLVMValueRef index;
558
559 if (reg.Dimension.Indirect)
560 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
561 reg.Dimension.Index);
562 else
563 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
564
565 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
566 LLVMBuildMul(gallivm->builder, index,
567 vertex_dw_stride, ""), "");
568 }
569
570 /* Get information about the register. */
571 if (reg.Register.File == TGSI_FILE_INPUT) {
572 name = info->input_semantic_name;
573 index = info->input_semantic_index;
574 array_first = info->input_array_first;
575 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
576 name = info->output_semantic_name;
577 index = info->output_semantic_index;
578 array_first = info->output_array_first;
579 } else {
580 assert(0);
581 return NULL;
582 }
583
584 if (reg.Register.Indirect) {
585 /* Add the relative address of the element. */
586 LLVMValueRef ind_index;
587
588 if (reg.Indirect.ArrayID)
589 first = array_first[reg.Indirect.ArrayID];
590 else
591 first = reg.Register.Index;
592
593 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
594 reg.Register.Index - first);
595
596 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
597 LLVMBuildMul(gallivm->builder, ind_index,
598 lp_build_const_int32(gallivm, 4), ""), "");
599
600 param = si_shader_io_get_unique_index(name[first], index[first]);
601 } else {
602 param = si_shader_io_get_unique_index(name[reg.Register.Index],
603 index[reg.Register.Index]);
604 }
605
606 /* Add the base address of the element. */
607 return LLVMBuildAdd(gallivm->builder, base_addr,
608 lp_build_const_int32(gallivm, param * 4), "");
609 }
610
611 /**
612 * Load from LDS.
613 *
614 * \param type output value type
615 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
616 * \param dw_addr address in dwords
617 */
618 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
619 enum tgsi_opcode_type type, unsigned swizzle,
620 LLVMValueRef dw_addr)
621 {
622 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
623 struct gallivm_state *gallivm = bld_base->base.gallivm;
624 LLVMValueRef value;
625
626 if (swizzle == ~0) {
627 LLVMValueRef values[TGSI_NUM_CHANNELS];
628
629 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
630 values[chan] = lds_load(bld_base, type, chan, dw_addr);
631
632 return lp_build_gather_values(bld_base->base.gallivm, values,
633 TGSI_NUM_CHANNELS);
634 }
635
636 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
637 lp_build_const_int32(gallivm, swizzle));
638
639 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
640 return LLVMBuildBitCast(gallivm->builder, value,
641 tgsi2llvmtype(bld_base, type), "");
642 }
643
644 /**
645 * Store to LDS.
646 *
647 * \param swizzle offset (typically 0..3)
648 * \param dw_addr address in dwords
649 * \param value value to store
650 */
651 static void lds_store(struct lp_build_tgsi_context * bld_base,
652 unsigned swizzle, LLVMValueRef dw_addr,
653 LLVMValueRef value)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct gallivm_state *gallivm = bld_base->base.gallivm;
657
658 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
659 lp_build_const_int32(gallivm, swizzle));
660
661 value = LLVMBuildBitCast(gallivm->builder, value,
662 LLVMInt32TypeInContext(gallivm->context), "");
663 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
664 dw_addr, value);
665 }
666
667 static LLVMValueRef fetch_input_tcs(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
676 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
677 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
678
679 return lds_load(bld_base, type, swizzle, dw_addr);
680 }
681
682 static LLVMValueRef fetch_output_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 if (reg->Register.Dimension) {
691 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
692 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
693 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
694 } else {
695 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
696 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
697 }
698
699 return lds_load(bld_base, type, swizzle, dw_addr);
700 }
701
702 static LLVMValueRef fetch_input_tes(
703 struct lp_build_tgsi_context *bld_base,
704 const struct tgsi_full_src_register *reg,
705 enum tgsi_opcode_type type, unsigned swizzle)
706 {
707 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
708 LLVMValueRef dw_addr, stride;
709
710 if (reg->Register.Dimension) {
711 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
712 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
714 } else {
715 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
716 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
717 }
718
719 return lds_load(bld_base, type, swizzle, dw_addr);
720 }
721
722 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
723 const struct tgsi_full_instruction * inst,
724 const struct tgsi_opcode_info * info,
725 LLVMValueRef dst[4])
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
729 unsigned chan_index;
730 LLVMValueRef dw_addr, stride;
731
732 /* Only handle per-patch and per-vertex outputs here.
733 * Vectors will be lowered to scalars and this function will be called again.
734 */
735 if (reg->Register.File != TGSI_FILE_OUTPUT ||
736 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
737 radeon_llvm_emit_store(bld_base, inst, info, dst);
738 return;
739 }
740
741 if (reg->Register.Dimension) {
742 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
743 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
744 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
745 } else {
746 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
747 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
748 }
749
750 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
751 LLVMValueRef value = dst[chan_index];
752
753 if (inst->Instruction.Saturate)
754 value = radeon_llvm_saturate(bld_base, value);
755
756 lds_store(bld_base, chan_index, dw_addr, value);
757 }
758 }
759
760 static LLVMValueRef fetch_input_gs(
761 struct lp_build_tgsi_context *bld_base,
762 const struct tgsi_full_src_register *reg,
763 enum tgsi_opcode_type type,
764 unsigned swizzle)
765 {
766 struct lp_build_context *base = &bld_base->base;
767 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
768 struct si_shader *shader = si_shader_ctx->shader;
769 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
770 struct gallivm_state *gallivm = base->gallivm;
771 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
772 LLVMValueRef vtx_offset;
773 LLVMValueRef args[9];
774 unsigned vtx_offset_param;
775 struct tgsi_shader_info *info = &shader->selector->info;
776 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
777 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
778
779 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
780 return get_primitive_id(bld_base, swizzle);
781
782 if (!reg->Register.Dimension)
783 return NULL;
784
785 if (swizzle == ~0) {
786 LLVMValueRef values[TGSI_NUM_CHANNELS];
787 unsigned chan;
788 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
789 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
790 }
791 return lp_build_gather_values(bld_base->base.gallivm, values,
792 TGSI_NUM_CHANNELS);
793 }
794
795 /* Get the vertex offset parameter */
796 vtx_offset_param = reg->Dimension.Index;
797 if (vtx_offset_param < 2) {
798 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
799 } else {
800 assert(vtx_offset_param < 6);
801 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
802 }
803 vtx_offset = lp_build_mul_imm(uint,
804 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
805 vtx_offset_param),
806 4);
807
808 args[0] = si_shader_ctx->esgs_ring;
809 args[1] = vtx_offset;
810 args[2] = lp_build_const_int32(gallivm,
811 (get_param_index(semantic_name, semantic_index,
812 shader->selector->inputs_read) * 4 +
813 swizzle) * 256);
814 args[3] = uint->zero;
815 args[4] = uint->one; /* OFFEN */
816 args[5] = uint->zero; /* IDXEN */
817 args[6] = uint->one; /* GLC */
818 args[7] = uint->zero; /* SLC */
819 args[8] = uint->zero; /* TFE */
820
821 return LLVMBuildBitCast(gallivm->builder,
822 lp_build_intrinsic(gallivm->builder,
823 "llvm.SI.buffer.load.dword.i32.i32",
824 i32, args, 9,
825 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
826 tgsi2llvmtype(bld_base, type), "");
827 }
828
829 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
830 {
831 switch (interpolate) {
832 case TGSI_INTERPOLATE_CONSTANT:
833 return 0;
834
835 case TGSI_INTERPOLATE_LINEAR:
836 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
837 return SI_PARAM_LINEAR_SAMPLE;
838 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
839 return SI_PARAM_LINEAR_CENTROID;
840 else
841 return SI_PARAM_LINEAR_CENTER;
842 break;
843 case TGSI_INTERPOLATE_COLOR:
844 case TGSI_INTERPOLATE_PERSPECTIVE:
845 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
846 return SI_PARAM_PERSP_SAMPLE;
847 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
848 return SI_PARAM_PERSP_CENTROID;
849 else
850 return SI_PARAM_PERSP_CENTER;
851 break;
852 default:
853 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
854 return -1;
855 }
856 }
857
858 static void declare_input_fs(
859 struct radeon_llvm_context *radeon_bld,
860 unsigned input_index,
861 const struct tgsi_full_declaration *decl)
862 {
863 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
864 struct si_shader_context *si_shader_ctx =
865 si_shader_context(&radeon_bld->soa.bld_base);
866 struct si_shader *shader = si_shader_ctx->shader;
867 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
868 struct gallivm_state *gallivm = base->gallivm;
869 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
870 LLVMValueRef main_fn = radeon_bld->main_fn;
871
872 LLVMValueRef interp_param = NULL;
873 int interp_param_idx;
874 const char * intr_name;
875
876 /* This value is:
877 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
878 * quad begins a new primitive. Bit 0 always needs
879 * to be unset)
880 * [32:16] ParamOffset
881 *
882 */
883 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
884 LLVMValueRef attr_number;
885
886 unsigned chan;
887
888 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
889 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
890 unsigned soa_index =
891 radeon_llvm_reg_index_soa(input_index, chan);
892 radeon_bld->inputs[soa_index] =
893 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
894
895 if (chan == 3)
896 /* RCP for fragcoord.w */
897 radeon_bld->inputs[soa_index] =
898 LLVMBuildFDiv(gallivm->builder,
899 lp_build_const_float(gallivm, 1.0f),
900 radeon_bld->inputs[soa_index],
901 "");
902 }
903 return;
904 }
905
906 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
907 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
908 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
909 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
910 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
911 lp_build_const_float(gallivm, 0.0f);
912 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
913 lp_build_const_float(gallivm, 1.0f);
914
915 return;
916 }
917
918 shader->ps_input_param_offset[input_index] = shader->nparam++;
919 attr_number = lp_build_const_int32(gallivm,
920 shader->ps_input_param_offset[input_index]);
921
922 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
923 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
924 decl->Interp.Location);
925 if (interp_param_idx == -1)
926 return;
927 else if (interp_param_idx)
928 interp_param = LLVMGetParam(main_fn, interp_param_idx);
929
930 /* fs.constant returns the param from the middle vertex, so it's not
931 * really useful for flat shading. It's meant to be used for custom
932 * interpolation (but the intrinsic can't fetch from the other two
933 * vertices).
934 *
935 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
936 * to do the right thing. The only reason we use fs.constant is that
937 * fs.interp cannot be used on integers, because they can be equal
938 * to NaN.
939 */
940 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
941
942 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
943 si_shader_ctx->shader->key.ps.color_two_side) {
944 LLVMValueRef args[4];
945 LLVMValueRef face, is_face_positive;
946 LLVMValueRef back_attr_number =
947 lp_build_const_int32(gallivm,
948 shader->ps_input_param_offset[input_index] + 1);
949
950 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
951
952 is_face_positive = LLVMBuildFCmp(gallivm->builder,
953 LLVMRealOGT, face,
954 lp_build_const_float(gallivm, 0.0f),
955 "");
956
957 args[2] = params;
958 args[3] = interp_param;
959 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
960 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
961 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
962 LLVMValueRef front, back;
963
964 args[0] = llvm_chan;
965 args[1] = attr_number;
966 front = lp_build_intrinsic(gallivm->builder, intr_name,
967 input_type, args, args[3] ? 4 : 3,
968 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
969
970 args[1] = back_attr_number;
971 back = lp_build_intrinsic(gallivm->builder, intr_name,
972 input_type, args, args[3] ? 4 : 3,
973 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
974
975 radeon_bld->inputs[soa_index] =
976 LLVMBuildSelect(gallivm->builder,
977 is_face_positive,
978 front,
979 back,
980 "");
981 }
982
983 shader->nparam++;
984 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
985 LLVMValueRef args[4];
986
987 args[0] = uint->zero;
988 args[1] = attr_number;
989 args[2] = params;
990 args[3] = interp_param;
991 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
992 lp_build_intrinsic(gallivm->builder, intr_name,
993 input_type, args, args[3] ? 4 : 3,
994 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
995 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
996 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
997 lp_build_const_float(gallivm, 0.0f);
998 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
999 lp_build_const_float(gallivm, 1.0f);
1000 } else {
1001 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1002 LLVMValueRef args[4];
1003 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1004 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1005 args[0] = llvm_chan;
1006 args[1] = attr_number;
1007 args[2] = params;
1008 args[3] = interp_param;
1009 radeon_bld->inputs[soa_index] =
1010 lp_build_intrinsic(gallivm->builder, intr_name,
1011 input_type, args, args[3] ? 4 : 3,
1012 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1013 }
1014 }
1015 }
1016
1017 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1018 {
1019 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1020 SI_PARAM_ANCILLARY, 8, 4);
1021 }
1022
1023 /**
1024 * Load a dword from a constant buffer.
1025 */
1026 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1027 LLVMValueRef offset, LLVMTypeRef return_type)
1028 {
1029 LLVMValueRef args[2] = {resource, offset};
1030
1031 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1032 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1033 }
1034
1035 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1036 {
1037 struct si_shader_context *si_shader_ctx =
1038 si_shader_context(&radeon_bld->soa.bld_base);
1039 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1040 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1041 LLVMBuilderRef builder = gallivm->builder;
1042 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1043 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1044 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1045
1046 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1047 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1048 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1049
1050 LLVMValueRef pos[4] = {
1051 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1052 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1053 lp_build_const_float(gallivm, 0),
1054 lp_build_const_float(gallivm, 0)
1055 };
1056
1057 return lp_build_gather_values(gallivm, pos, 4);
1058 }
1059
1060 static void declare_system_value(
1061 struct radeon_llvm_context * radeon_bld,
1062 unsigned index,
1063 const struct tgsi_full_declaration *decl)
1064 {
1065 struct si_shader_context *si_shader_ctx =
1066 si_shader_context(&radeon_bld->soa.bld_base);
1067 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1068 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1069 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1070 LLVMValueRef value = 0;
1071
1072 switch (decl->Semantic.Name) {
1073 case TGSI_SEMANTIC_INSTANCEID:
1074 value = LLVMGetParam(radeon_bld->main_fn,
1075 si_shader_ctx->param_instance_id);
1076 break;
1077
1078 case TGSI_SEMANTIC_VERTEXID:
1079 value = LLVMBuildAdd(gallivm->builder,
1080 LLVMGetParam(radeon_bld->main_fn,
1081 si_shader_ctx->param_vertex_id),
1082 LLVMGetParam(radeon_bld->main_fn,
1083 SI_PARAM_BASE_VERTEX), "");
1084 break;
1085
1086 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1087 value = LLVMGetParam(radeon_bld->main_fn,
1088 si_shader_ctx->param_vertex_id);
1089 break;
1090
1091 case TGSI_SEMANTIC_BASEVERTEX:
1092 value = LLVMGetParam(radeon_bld->main_fn,
1093 SI_PARAM_BASE_VERTEX);
1094 break;
1095
1096 case TGSI_SEMANTIC_INVOCATIONID:
1097 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1098 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1099 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1100 value = LLVMGetParam(radeon_bld->main_fn,
1101 SI_PARAM_GS_INSTANCE_ID);
1102 else
1103 assert(!"INVOCATIONID not implemented");
1104 break;
1105
1106 case TGSI_SEMANTIC_SAMPLEID:
1107 value = get_sample_id(radeon_bld);
1108 break;
1109
1110 case TGSI_SEMANTIC_SAMPLEPOS:
1111 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1112 break;
1113
1114 case TGSI_SEMANTIC_SAMPLEMASK:
1115 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1116 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1117 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1118 value = uint_bld->one;
1119 else
1120 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1121 break;
1122
1123 case TGSI_SEMANTIC_TESSCOORD:
1124 {
1125 LLVMValueRef coord[4] = {
1126 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1127 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1128 bld->zero,
1129 bld->zero
1130 };
1131
1132 /* For triangles, the vector should be (u, v, 1-u-v). */
1133 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1134 PIPE_PRIM_TRIANGLES)
1135 coord[2] = lp_build_sub(bld, bld->one,
1136 lp_build_add(bld, coord[0], coord[1]));
1137
1138 value = lp_build_gather_values(gallivm, coord, 4);
1139 break;
1140 }
1141
1142 case TGSI_SEMANTIC_VERTICESIN:
1143 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1144 break;
1145
1146 case TGSI_SEMANTIC_TESSINNER:
1147 case TGSI_SEMANTIC_TESSOUTER:
1148 {
1149 LLVMValueRef dw_addr;
1150 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1151
1152 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1153 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1154 lp_build_const_int32(gallivm, param * 4), "");
1155
1156 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1157 ~0, dw_addr);
1158 break;
1159 }
1160
1161 case TGSI_SEMANTIC_PRIMID:
1162 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1163 break;
1164
1165 default:
1166 assert(!"unknown system value");
1167 return;
1168 }
1169
1170 radeon_bld->system_values[index] = value;
1171 }
1172
1173 static LLVMValueRef fetch_constant(
1174 struct lp_build_tgsi_context * bld_base,
1175 const struct tgsi_full_src_register *reg,
1176 enum tgsi_opcode_type type,
1177 unsigned swizzle)
1178 {
1179 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1180 struct lp_build_context * base = &bld_base->base;
1181 const struct tgsi_ind_register *ireg = &reg->Indirect;
1182 unsigned buf, idx;
1183
1184 LLVMValueRef addr, bufp;
1185 LLVMValueRef result;
1186
1187 if (swizzle == LP_CHAN_ALL) {
1188 unsigned chan;
1189 LLVMValueRef values[4];
1190 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1191 values[chan] = fetch_constant(bld_base, reg, type, chan);
1192
1193 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1194 }
1195
1196 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1197 idx = reg->Register.Index * 4 + swizzle;
1198
1199 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1200 if (type != TGSI_TYPE_DOUBLE)
1201 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1202 else {
1203 return radeon_llvm_emit_fetch_double(bld_base,
1204 si_shader_ctx->constants[buf][idx],
1205 si_shader_ctx->constants[buf][idx + 1]);
1206 }
1207 }
1208
1209 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1210 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1211 LLVMValueRef index;
1212 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1213 reg->Dimension.Index);
1214 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1215 } else
1216 bufp = si_shader_ctx->const_resource[buf];
1217
1218 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1219 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1220 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1221 addr = lp_build_add(&bld_base->uint_bld, addr,
1222 lp_build_const_int32(base->gallivm, idx * 4));
1223
1224 result = buffer_load_const(base->gallivm->builder, bufp,
1225 addr, bld_base->base.elem_type);
1226
1227 if (type != TGSI_TYPE_DOUBLE)
1228 result = bitcast(bld_base, type, result);
1229 else {
1230 LLVMValueRef addr2, result2;
1231 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1232 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1233 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1234 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1235 lp_build_const_int32(base->gallivm, idx * 4));
1236
1237 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1238 addr2, bld_base->base.elem_type);
1239
1240 result = radeon_llvm_emit_fetch_double(bld_base,
1241 result, result2);
1242 }
1243 return result;
1244 }
1245
1246 /* Initialize arguments for the shader export intrinsic */
1247 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1248 LLVMValueRef *values,
1249 unsigned target,
1250 LLVMValueRef *args)
1251 {
1252 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1253 struct lp_build_context *uint =
1254 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1255 struct lp_build_context *base = &bld_base->base;
1256 unsigned compressed = 0;
1257 unsigned chan;
1258
1259 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1260 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1261
1262 if (cbuf >= 0 && cbuf < 8) {
1263 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1264
1265 if (compressed)
1266 si_shader_ctx->shader->spi_shader_col_format |=
1267 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1268 else
1269 si_shader_ctx->shader->spi_shader_col_format |=
1270 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1271
1272 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1273 }
1274 }
1275
1276 if (compressed) {
1277 /* Pixel shader needs to pack output values before export */
1278 for (chan = 0; chan < 2; chan++ ) {
1279 args[0] = values[2 * chan];
1280 args[1] = values[2 * chan + 1];
1281 args[chan + 5] =
1282 lp_build_intrinsic(base->gallivm->builder,
1283 "llvm.SI.packf16",
1284 LLVMInt32TypeInContext(base->gallivm->context),
1285 args, 2,
1286 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1287 args[chan + 7] = args[chan + 5] =
1288 LLVMBuildBitCast(base->gallivm->builder,
1289 args[chan + 5],
1290 LLVMFloatTypeInContext(base->gallivm->context),
1291 "");
1292 }
1293
1294 /* Set COMPR flag */
1295 args[4] = uint->one;
1296 } else {
1297 for (chan = 0; chan < 4; chan++ )
1298 /* +5 because the first output value will be
1299 * the 6th argument to the intrinsic. */
1300 args[chan + 5] = values[chan];
1301
1302 /* Clear COMPR flag */
1303 args[4] = uint->zero;
1304 }
1305
1306 /* XXX: This controls which components of the output
1307 * registers actually get exported. (e.g bit 0 means export
1308 * X component, bit 1 means export Y component, etc.) I'm
1309 * hard coding this to 0xf for now. In the future, we might
1310 * want to do something else. */
1311 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1312
1313 /* Specify whether the EXEC mask represents the valid mask */
1314 args[1] = uint->zero;
1315
1316 /* Specify whether this is the last export */
1317 args[2] = uint->zero;
1318
1319 /* Specify the target we are exporting */
1320 args[3] = lp_build_const_int32(base->gallivm, target);
1321
1322 /* XXX: We probably need to keep track of the output
1323 * values, so we know what we are passing to the next
1324 * stage. */
1325 }
1326
1327 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1328 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1329 LLVMValueRef *out_ptr,
1330 unsigned target,
1331 LLVMValueRef *args)
1332 {
1333 struct gallivm_state *gallivm = bld_base->base.gallivm;
1334 LLVMValueRef values[4];
1335 int i;
1336
1337 for (i = 0; i < 4; i++)
1338 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1339
1340 si_llvm_init_export_args(bld_base, values, target, args);
1341 }
1342
1343 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1344 LLVMValueRef alpha_ptr)
1345 {
1346 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1347 struct gallivm_state *gallivm = bld_base->base.gallivm;
1348
1349 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1350 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1351 SI_PARAM_ALPHA_REF);
1352
1353 LLVMValueRef alpha_pass =
1354 lp_build_cmp(&bld_base->base,
1355 si_shader_ctx->shader->key.ps.alpha_func,
1356 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1357 alpha_ref);
1358 LLVMValueRef arg =
1359 lp_build_select(&bld_base->base,
1360 alpha_pass,
1361 lp_build_const_float(gallivm, 1.0f),
1362 lp_build_const_float(gallivm, -1.0f));
1363
1364 lp_build_intrinsic(gallivm->builder,
1365 "llvm.AMDGPU.kill",
1366 LLVMVoidTypeInContext(gallivm->context),
1367 &arg, 1, 0);
1368 } else {
1369 lp_build_intrinsic(gallivm->builder,
1370 "llvm.AMDGPU.kilp",
1371 LLVMVoidTypeInContext(gallivm->context),
1372 NULL, 0, 0);
1373 }
1374
1375 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1376 }
1377
1378 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1379 LLVMValueRef alpha_ptr)
1380 {
1381 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1382 struct gallivm_state *gallivm = bld_base->base.gallivm;
1383 LLVMValueRef coverage, alpha;
1384
1385 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1386 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1387 SI_PARAM_SAMPLE_COVERAGE);
1388 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1389
1390 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1391 bld_base->int_bld.elem_type,
1392 &coverage, 1, LLVMReadNoneAttribute);
1393
1394 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1395 bld_base->base.elem_type, "");
1396
1397 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1398 lp_build_const_float(gallivm,
1399 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1400
1401 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1402 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1403 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1404 }
1405
1406 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1407 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1408 {
1409 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1410 struct lp_build_context *base = &bld_base->base;
1411 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1412 unsigned reg_index;
1413 unsigned chan;
1414 unsigned const_chan;
1415 LLVMValueRef base_elt;
1416 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1417 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1418 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1419
1420 for (reg_index = 0; reg_index < 2; reg_index ++) {
1421 LLVMValueRef *args = pos[2 + reg_index];
1422
1423 args[5] =
1424 args[6] =
1425 args[7] =
1426 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1427
1428 /* Compute dot products of position and user clip plane vectors */
1429 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1430 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1431 args[1] = lp_build_const_int32(base->gallivm,
1432 ((reg_index * 4 + chan) * 4 +
1433 const_chan) * 4);
1434 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1435 args[1], base->elem_type);
1436 args[5 + chan] =
1437 lp_build_add(base, args[5 + chan],
1438 lp_build_mul(base, base_elt,
1439 out_elts[const_chan]));
1440 }
1441 }
1442
1443 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1444 args[1] = uint->zero;
1445 args[2] = uint->zero;
1446 args[3] = lp_build_const_int32(base->gallivm,
1447 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1448 args[4] = uint->zero;
1449 }
1450 }
1451
1452 static void si_dump_streamout(struct pipe_stream_output_info *so)
1453 {
1454 unsigned i;
1455
1456 if (so->num_outputs)
1457 fprintf(stderr, "STREAMOUT\n");
1458
1459 for (i = 0; i < so->num_outputs; i++) {
1460 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1461 so->output[i].start_component;
1462 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1463 i, so->output[i].output_buffer,
1464 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1465 so->output[i].register_index,
1466 mask & 1 ? "x" : "",
1467 mask & 2 ? "y" : "",
1468 mask & 4 ? "z" : "",
1469 mask & 8 ? "w" : "");
1470 }
1471 }
1472
1473 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1474 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1475 * or v4i32 (num_channels=3,4). */
1476 static void build_tbuffer_store(struct si_shader_context *shader,
1477 LLVMValueRef rsrc,
1478 LLVMValueRef vdata,
1479 unsigned num_channels,
1480 LLVMValueRef vaddr,
1481 LLVMValueRef soffset,
1482 unsigned inst_offset,
1483 unsigned dfmt,
1484 unsigned nfmt,
1485 unsigned offen,
1486 unsigned idxen,
1487 unsigned glc,
1488 unsigned slc,
1489 unsigned tfe)
1490 {
1491 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1492 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1493 LLVMValueRef args[] = {
1494 rsrc,
1495 vdata,
1496 LLVMConstInt(i32, num_channels, 0),
1497 vaddr,
1498 soffset,
1499 LLVMConstInt(i32, inst_offset, 0),
1500 LLVMConstInt(i32, dfmt, 0),
1501 LLVMConstInt(i32, nfmt, 0),
1502 LLVMConstInt(i32, offen, 0),
1503 LLVMConstInt(i32, idxen, 0),
1504 LLVMConstInt(i32, glc, 0),
1505 LLVMConstInt(i32, slc, 0),
1506 LLVMConstInt(i32, tfe, 0)
1507 };
1508
1509 /* The instruction offset field has 12 bits */
1510 assert(offen || inst_offset < (1 << 12));
1511
1512 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1513 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1514 const char *types[] = {"i32", "v2i32", "v4i32"};
1515 char name[256];
1516 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1517
1518 lp_build_intrinsic(gallivm->builder, name,
1519 LLVMVoidTypeInContext(gallivm->context),
1520 args, Elements(args), 0);
1521 }
1522
1523 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1524 LLVMValueRef rsrc,
1525 LLVMValueRef vdata,
1526 unsigned num_channels,
1527 LLVMValueRef vaddr,
1528 LLVMValueRef soffset,
1529 unsigned inst_offset)
1530 {
1531 static unsigned dfmt[] = {
1532 V_008F0C_BUF_DATA_FORMAT_32,
1533 V_008F0C_BUF_DATA_FORMAT_32_32,
1534 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1535 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1536 };
1537 assert(num_channels >= 1 && num_channels <= 4);
1538
1539 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1540 inst_offset, dfmt[num_channels-1],
1541 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1542 }
1543
1544 /* On SI, the vertex shader is responsible for writing streamout data
1545 * to buffers. */
1546 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1547 struct si_shader_output_values *outputs,
1548 unsigned noutput)
1549 {
1550 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1551 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1552 LLVMBuilderRef builder = gallivm->builder;
1553 int i, j;
1554 struct lp_build_if_state if_ctx;
1555
1556 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1557
1558 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1559 LLVMValueRef so_vtx_count =
1560 unpack_param(shader, shader->param_streamout_config, 16, 7);
1561
1562 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1563 NULL, 0, LLVMReadNoneAttribute);
1564
1565 /* can_emit = tid < so_vtx_count; */
1566 LLVMValueRef can_emit =
1567 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1568
1569 LLVMValueRef stream_id =
1570 unpack_param(shader, shader->param_streamout_config, 24, 2);
1571
1572 /* Emit the streamout code conditionally. This actually avoids
1573 * out-of-bounds buffer access. The hw tells us via the SGPR
1574 * (so_vtx_count) which threads are allowed to emit streamout data. */
1575 lp_build_if(&if_ctx, gallivm, can_emit);
1576 {
1577 /* The buffer offset is computed as follows:
1578 * ByteOffset = streamout_offset[buffer_id]*4 +
1579 * (streamout_write_index + thread_id)*stride[buffer_id] +
1580 * attrib_offset
1581 */
1582
1583 LLVMValueRef so_write_index =
1584 LLVMGetParam(shader->radeon_bld.main_fn,
1585 shader->param_streamout_write_index);
1586
1587 /* Compute (streamout_write_index + thread_id). */
1588 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1589
1590 /* Compute the write offset for each enabled buffer. */
1591 LLVMValueRef so_write_offset[4] = {};
1592 for (i = 0; i < 4; i++) {
1593 if (!so->stride[i])
1594 continue;
1595
1596 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1597 shader->param_streamout_offset[i]);
1598 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1599
1600 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1601 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1602 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1603 }
1604
1605 /* Write streamout data. */
1606 for (i = 0; i < so->num_outputs; i++) {
1607 unsigned buf_idx = so->output[i].output_buffer;
1608 unsigned reg = so->output[i].register_index;
1609 unsigned start = so->output[i].start_component;
1610 unsigned num_comps = so->output[i].num_components;
1611 unsigned stream = so->output[i].stream;
1612 LLVMValueRef out[4];
1613 struct lp_build_if_state if_ctx_stream;
1614
1615 assert(num_comps && num_comps <= 4);
1616 if (!num_comps || num_comps > 4)
1617 continue;
1618
1619 if (reg >= noutput)
1620 continue;
1621
1622 /* Load the output as int. */
1623 for (j = 0; j < num_comps; j++) {
1624 out[j] = LLVMBuildBitCast(builder,
1625 outputs[reg].values[start+j],
1626 i32, "");
1627 }
1628
1629 /* Pack the output. */
1630 LLVMValueRef vdata = NULL;
1631
1632 switch (num_comps) {
1633 case 1: /* as i32 */
1634 vdata = out[0];
1635 break;
1636 case 2: /* as v2i32 */
1637 case 3: /* as v4i32 (aligned to 4) */
1638 case 4: /* as v4i32 */
1639 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1640 for (j = 0; j < num_comps; j++) {
1641 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1642 LLVMConstInt(i32, j, 0), "");
1643 }
1644 break;
1645 }
1646
1647 LLVMValueRef can_emit_stream =
1648 LLVMBuildICmp(builder, LLVMIntEQ,
1649 stream_id,
1650 lp_build_const_int32(gallivm, stream), "");
1651
1652 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1653 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1654 vdata, num_comps,
1655 so_write_offset[buf_idx],
1656 LLVMConstInt(i32, 0, 0),
1657 so->output[i].dst_offset*4);
1658 lp_build_endif(&if_ctx_stream);
1659 }
1660 }
1661 lp_build_endif(&if_ctx);
1662 }
1663
1664
1665 /* Generate export instructions for hardware VS shader stage */
1666 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1667 struct si_shader_output_values *outputs,
1668 unsigned noutput)
1669 {
1670 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1671 struct si_shader * shader = si_shader_ctx->shader;
1672 struct lp_build_context * base = &bld_base->base;
1673 struct lp_build_context * uint =
1674 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1675 LLVMValueRef args[9];
1676 LLVMValueRef pos_args[4][9] = { { 0 } };
1677 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1678 unsigned semantic_name, semantic_index;
1679 unsigned target;
1680 unsigned param_count = 0;
1681 unsigned pos_idx;
1682 int i;
1683
1684 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1685 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1686 }
1687
1688 for (i = 0; i < noutput; i++) {
1689 semantic_name = outputs[i].name;
1690 semantic_index = outputs[i].sid;
1691
1692 handle_semantic:
1693 /* Select the correct target */
1694 switch(semantic_name) {
1695 case TGSI_SEMANTIC_PSIZE:
1696 psize_value = outputs[i].values[0];
1697 continue;
1698 case TGSI_SEMANTIC_EDGEFLAG:
1699 edgeflag_value = outputs[i].values[0];
1700 continue;
1701 case TGSI_SEMANTIC_LAYER:
1702 layer_value = outputs[i].values[0];
1703 semantic_name = TGSI_SEMANTIC_GENERIC;
1704 goto handle_semantic;
1705 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1706 viewport_index_value = outputs[i].values[0];
1707 semantic_name = TGSI_SEMANTIC_GENERIC;
1708 goto handle_semantic;
1709 case TGSI_SEMANTIC_POSITION:
1710 target = V_008DFC_SQ_EXP_POS;
1711 break;
1712 case TGSI_SEMANTIC_COLOR:
1713 case TGSI_SEMANTIC_BCOLOR:
1714 target = V_008DFC_SQ_EXP_PARAM + param_count;
1715 shader->vs_output_param_offset[i] = param_count;
1716 param_count++;
1717 break;
1718 case TGSI_SEMANTIC_CLIPDIST:
1719 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1720 break;
1721 case TGSI_SEMANTIC_CLIPVERTEX:
1722 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1723 continue;
1724 case TGSI_SEMANTIC_PRIMID:
1725 case TGSI_SEMANTIC_FOG:
1726 case TGSI_SEMANTIC_TEXCOORD:
1727 case TGSI_SEMANTIC_GENERIC:
1728 target = V_008DFC_SQ_EXP_PARAM + param_count;
1729 shader->vs_output_param_offset[i] = param_count;
1730 param_count++;
1731 break;
1732 default:
1733 target = 0;
1734 fprintf(stderr,
1735 "Warning: SI unhandled vs output type:%d\n",
1736 semantic_name);
1737 }
1738
1739 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1740
1741 if (target >= V_008DFC_SQ_EXP_POS &&
1742 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1743 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1744 args, sizeof(args));
1745 } else {
1746 lp_build_intrinsic(base->gallivm->builder,
1747 "llvm.SI.export",
1748 LLVMVoidTypeInContext(base->gallivm->context),
1749 args, 9, 0);
1750 }
1751
1752 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1753 semantic_name = TGSI_SEMANTIC_GENERIC;
1754 goto handle_semantic;
1755 }
1756 }
1757
1758 shader->nr_param_exports = param_count;
1759
1760 /* We need to add the position output manually if it's missing. */
1761 if (!pos_args[0][0]) {
1762 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1763 pos_args[0][1] = uint->zero; /* EXEC mask */
1764 pos_args[0][2] = uint->zero; /* last export? */
1765 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1766 pos_args[0][4] = uint->zero; /* COMPR flag */
1767 pos_args[0][5] = base->zero; /* X */
1768 pos_args[0][6] = base->zero; /* Y */
1769 pos_args[0][7] = base->zero; /* Z */
1770 pos_args[0][8] = base->one; /* W */
1771 }
1772
1773 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1774 if (shader->selector->info.writes_psize ||
1775 shader->selector->info.writes_edgeflag ||
1776 shader->selector->info.writes_viewport_index ||
1777 shader->selector->info.writes_layer) {
1778 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1779 shader->selector->info.writes_psize |
1780 (shader->selector->info.writes_edgeflag << 1) |
1781 (shader->selector->info.writes_layer << 2) |
1782 (shader->selector->info.writes_viewport_index << 3));
1783 pos_args[1][1] = uint->zero; /* EXEC mask */
1784 pos_args[1][2] = uint->zero; /* last export? */
1785 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1786 pos_args[1][4] = uint->zero; /* COMPR flag */
1787 pos_args[1][5] = base->zero; /* X */
1788 pos_args[1][6] = base->zero; /* Y */
1789 pos_args[1][7] = base->zero; /* Z */
1790 pos_args[1][8] = base->zero; /* W */
1791
1792 if (shader->selector->info.writes_psize)
1793 pos_args[1][5] = psize_value;
1794
1795 if (shader->selector->info.writes_edgeflag) {
1796 /* The output is a float, but the hw expects an integer
1797 * with the first bit containing the edge flag. */
1798 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1799 edgeflag_value,
1800 bld_base->uint_bld.elem_type, "");
1801 edgeflag_value = lp_build_min(&bld_base->int_bld,
1802 edgeflag_value,
1803 bld_base->int_bld.one);
1804
1805 /* The LLVM intrinsic expects a float. */
1806 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1807 edgeflag_value,
1808 base->elem_type, "");
1809 }
1810
1811 if (shader->selector->info.writes_layer)
1812 pos_args[1][7] = layer_value;
1813
1814 if (shader->selector->info.writes_viewport_index)
1815 pos_args[1][8] = viewport_index_value;
1816 }
1817
1818 for (i = 0; i < 4; i++)
1819 if (pos_args[i][0])
1820 shader->nr_pos_exports++;
1821
1822 pos_idx = 0;
1823 for (i = 0; i < 4; i++) {
1824 if (!pos_args[i][0])
1825 continue;
1826
1827 /* Specify the target we are exporting */
1828 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1829
1830 if (pos_idx == shader->nr_pos_exports)
1831 /* Specify that this is the last export */
1832 pos_args[i][2] = uint->one;
1833
1834 lp_build_intrinsic(base->gallivm->builder,
1835 "llvm.SI.export",
1836 LLVMVoidTypeInContext(base->gallivm->context),
1837 pos_args[i], 9, 0);
1838 }
1839 }
1840
1841 /* This only writes the tessellation factor levels. */
1842 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1843 {
1844 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1845 struct gallivm_state *gallivm = bld_base->base.gallivm;
1846 struct si_shader *shader = si_shader_ctx->shader;
1847 unsigned tess_inner_index, tess_outer_index;
1848 LLVMValueRef lds_base, lds_inner, lds_outer;
1849 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1850 LLVMValueRef out[6], vec0, vec1, invocation_id;
1851 unsigned stride, outer_comps, inner_comps, i;
1852 struct lp_build_if_state if_ctx;
1853
1854 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1855
1856 /* Do this only for invocation 0, because the tess levels are per-patch,
1857 * not per-vertex.
1858 *
1859 * This can't jump, because invocation 0 executes this. It should
1860 * at least mask out the loads and stores for other invocations.
1861 */
1862 lp_build_if(&if_ctx, gallivm,
1863 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1864 invocation_id, bld_base->uint_bld.zero, ""));
1865
1866 /* Determine the layout of one tess factor element in the buffer. */
1867 switch (shader->key.tcs.prim_mode) {
1868 case PIPE_PRIM_LINES:
1869 stride = 2; /* 2 dwords, 1 vec2 store */
1870 outer_comps = 2;
1871 inner_comps = 0;
1872 break;
1873 case PIPE_PRIM_TRIANGLES:
1874 stride = 4; /* 4 dwords, 1 vec4 store */
1875 outer_comps = 3;
1876 inner_comps = 1;
1877 break;
1878 case PIPE_PRIM_QUADS:
1879 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1880 outer_comps = 4;
1881 inner_comps = 2;
1882 break;
1883 default:
1884 assert(0);
1885 return;
1886 }
1887
1888 /* Load tess_inner and tess_outer from LDS.
1889 * Any invocation can write them, so we can't get them from a temporary.
1890 */
1891 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1892 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1893
1894 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1895 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1896 lp_build_const_int32(gallivm,
1897 tess_inner_index * 4), "");
1898 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1899 lp_build_const_int32(gallivm,
1900 tess_outer_index * 4), "");
1901
1902 for (i = 0; i < outer_comps; i++)
1903 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1904 for (i = 0; i < inner_comps; i++)
1905 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1906
1907 /* Convert the outputs to vectors for stores. */
1908 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1909 vec1 = NULL;
1910
1911 if (stride > 4)
1912 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1913
1914 /* Get the buffer. */
1915 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1916 SI_PARAM_RW_BUFFERS);
1917 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1918 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1919
1920 /* Get the offset. */
1921 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1922 SI_PARAM_TESS_FACTOR_OFFSET);
1923 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1924 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1925 lp_build_const_int32(gallivm, 4 * stride), "");
1926
1927 /* Store the outputs. */
1928 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1929 MIN2(stride, 4), byteoffset, tf_base, 0);
1930 if (vec1)
1931 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1932 stride - 4, byteoffset, tf_base, 16);
1933 lp_build_endif(&if_ctx);
1934 }
1935
1936 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1937 {
1938 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1939 struct si_shader *shader = si_shader_ctx->shader;
1940 struct tgsi_shader_info *info = &shader->selector->info;
1941 struct gallivm_state *gallivm = bld_base->base.gallivm;
1942 unsigned i, chan;
1943 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1944 si_shader_ctx->param_rel_auto_id);
1945 LLVMValueRef vertex_dw_stride =
1946 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1947 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1948 vertex_dw_stride, "");
1949
1950 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1951 * its inputs from it. */
1952 for (i = 0; i < info->num_outputs; i++) {
1953 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1954 unsigned name = info->output_semantic_name[i];
1955 unsigned index = info->output_semantic_index[i];
1956 int param = si_shader_io_get_unique_index(name, index);
1957 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1958 lp_build_const_int32(gallivm, param * 4), "");
1959
1960 for (chan = 0; chan < 4; chan++) {
1961 lds_store(bld_base, chan, dw_addr,
1962 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1963 }
1964 }
1965 }
1966
1967 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1968 {
1969 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1970 struct gallivm_state *gallivm = bld_base->base.gallivm;
1971 struct si_shader *es = si_shader_ctx->shader;
1972 struct tgsi_shader_info *info = &es->selector->info;
1973 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1974 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1975 si_shader_ctx->param_es2gs_offset);
1976 uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
1977 es->key.tes.es_enabled_outputs :
1978 es->key.vs.es_enabled_outputs;
1979 unsigned chan;
1980 int i;
1981
1982 for (i = 0; i < info->num_outputs; i++) {
1983 LLVMValueRef *out_ptr =
1984 si_shader_ctx->radeon_bld.soa.outputs[i];
1985 int param_index;
1986
1987 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1988 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1989 continue;
1990
1991 param_index = get_param_index(info->output_semantic_name[i],
1992 info->output_semantic_index[i],
1993 enabled_outputs);
1994 if (param_index < 0)
1995 continue;
1996
1997 for (chan = 0; chan < 4; chan++) {
1998 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1999 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2000
2001 build_tbuffer_store(si_shader_ctx,
2002 si_shader_ctx->esgs_ring,
2003 out_val, 1,
2004 LLVMGetUndef(i32), soffset,
2005 (4 * param_index + chan) * 4,
2006 V_008F0C_BUF_DATA_FORMAT_32,
2007 V_008F0C_BUF_NUM_FORMAT_UINT,
2008 0, 0, 1, 1, 0);
2009 }
2010 }
2011 }
2012
2013 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2014 {
2015 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2016 struct gallivm_state *gallivm = bld_base->base.gallivm;
2017 LLVMValueRef args[2];
2018
2019 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2020 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2021 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2022 LLVMVoidTypeInContext(gallivm->context), args, 2,
2023 LLVMNoUnwindAttribute);
2024 }
2025
2026 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2027 {
2028 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2029 struct gallivm_state *gallivm = bld_base->base.gallivm;
2030 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2031 struct si_shader_output_values *outputs = NULL;
2032 int i,j;
2033
2034 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2035
2036 for (i = 0; i < info->num_outputs; i++) {
2037 outputs[i].name = info->output_semantic_name[i];
2038 outputs[i].sid = info->output_semantic_index[i];
2039
2040 for (j = 0; j < 4; j++)
2041 outputs[i].values[j] =
2042 LLVMBuildLoad(gallivm->builder,
2043 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2044 "");
2045 }
2046
2047 /* Export PrimitiveID when PS needs it. */
2048 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2049 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2050 outputs[i].sid = 0;
2051 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2052 get_primitive_id(bld_base, 0));
2053 outputs[i].values[1] = bld_base->base.undef;
2054 outputs[i].values[2] = bld_base->base.undef;
2055 outputs[i].values[3] = bld_base->base.undef;
2056 i++;
2057 }
2058
2059 si_llvm_export_vs(bld_base, outputs, i);
2060 FREE(outputs);
2061 }
2062
2063 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2064 {
2065 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2066 struct si_shader * shader = si_shader_ctx->shader;
2067 struct lp_build_context * base = &bld_base->base;
2068 struct lp_build_context * uint = &bld_base->uint_bld;
2069 struct tgsi_shader_info *info = &shader->selector->info;
2070 LLVMValueRef args[9];
2071 LLVMValueRef last_args[9] = { 0 };
2072 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2073 int i;
2074
2075 for (i = 0; i < info->num_outputs; i++) {
2076 unsigned semantic_name = info->output_semantic_name[i];
2077 unsigned semantic_index = info->output_semantic_index[i];
2078 unsigned target;
2079 LLVMValueRef alpha_ptr;
2080
2081 /* Select the correct target */
2082 switch (semantic_name) {
2083 case TGSI_SEMANTIC_POSITION:
2084 depth_index = i;
2085 continue;
2086 case TGSI_SEMANTIC_STENCIL:
2087 stencil_index = i;
2088 continue;
2089 case TGSI_SEMANTIC_SAMPLEMASK:
2090 samplemask_index = i;
2091 continue;
2092 case TGSI_SEMANTIC_COLOR:
2093 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2094 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2095
2096 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2097 LLVMBuildStore(base->gallivm->builder,
2098 base->one, alpha_ptr);
2099
2100 if (semantic_index == 0 &&
2101 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2102 si_alpha_test(bld_base, alpha_ptr);
2103
2104 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2105 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2106 break;
2107 default:
2108 target = 0;
2109 fprintf(stderr,
2110 "Warning: SI unhandled fs output type:%d\n",
2111 semantic_name);
2112 }
2113
2114 si_llvm_init_export_args_load(bld_base,
2115 si_shader_ctx->radeon_bld.soa.outputs[i],
2116 target, args);
2117
2118 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2119 /* If there is an export instruction waiting to be emitted, do so now. */
2120 if (last_args[0]) {
2121 lp_build_intrinsic(base->gallivm->builder,
2122 "llvm.SI.export",
2123 LLVMVoidTypeInContext(base->gallivm->context),
2124 last_args, 9, 0);
2125 }
2126
2127 /* This instruction will be emitted at the end of the shader. */
2128 memcpy(last_args, args, sizeof(args));
2129
2130 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2131 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2132 semantic_index == 0 &&
2133 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2134 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2135 si_llvm_init_export_args_load(bld_base,
2136 si_shader_ctx->radeon_bld.soa.outputs[i],
2137 V_008DFC_SQ_EXP_MRT + c, args);
2138 lp_build_intrinsic(base->gallivm->builder,
2139 "llvm.SI.export",
2140 LLVMVoidTypeInContext(base->gallivm->context),
2141 args, 9, 0);
2142 }
2143 }
2144 } else {
2145 lp_build_intrinsic(base->gallivm->builder,
2146 "llvm.SI.export",
2147 LLVMVoidTypeInContext(base->gallivm->context),
2148 args, 9, 0);
2149 }
2150 }
2151
2152 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2153 LLVMValueRef out_ptr;
2154 unsigned mask = 0;
2155
2156 /* Specify the target we are exporting */
2157 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2158
2159 args[5] = base->zero; /* R, depth */
2160 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2161 args[7] = base->zero; /* B, sample mask */
2162 args[8] = base->zero; /* A, alpha to mask */
2163
2164 if (depth_index >= 0) {
2165 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2166 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2167 mask |= 0x1;
2168 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2169 }
2170
2171 if (stencil_index >= 0) {
2172 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2173 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2174 mask |= 0x2;
2175 si_shader_ctx->shader->db_shader_control |=
2176 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2177 }
2178
2179 if (samplemask_index >= 0) {
2180 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2181 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2182 mask |= 0x4;
2183 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2184 }
2185
2186 /* SI (except OLAND) has a bug that it only looks
2187 * at the X writemask component. */
2188 if (si_shader_ctx->screen->b.chip_class == SI &&
2189 si_shader_ctx->screen->b.family != CHIP_OLAND)
2190 mask |= 0x1;
2191
2192 if (samplemask_index >= 0)
2193 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2194 else if (stencil_index >= 0)
2195 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2196 else
2197 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2198
2199 /* Specify which components to enable */
2200 args[0] = lp_build_const_int32(base->gallivm, mask);
2201
2202 args[1] =
2203 args[2] =
2204 args[4] = uint->zero;
2205
2206 if (last_args[0])
2207 lp_build_intrinsic(base->gallivm->builder,
2208 "llvm.SI.export",
2209 LLVMVoidTypeInContext(base->gallivm->context),
2210 args, 9, 0);
2211 else
2212 memcpy(last_args, args, sizeof(args));
2213 }
2214
2215 if (!last_args[0]) {
2216 /* Specify which components to enable */
2217 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2218
2219 /* Specify the target we are exporting */
2220 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2221
2222 /* Set COMPR flag to zero to export data as 32-bit */
2223 last_args[4] = uint->zero;
2224
2225 /* dummy bits */
2226 last_args[5]= uint->zero;
2227 last_args[6]= uint->zero;
2228 last_args[7]= uint->zero;
2229 last_args[8]= uint->zero;
2230 }
2231
2232 /* Specify whether the EXEC mask represents the valid mask */
2233 last_args[1] = uint->one;
2234
2235 /* Specify that this is the last export */
2236 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2237
2238 lp_build_intrinsic(base->gallivm->builder,
2239 "llvm.SI.export",
2240 LLVMVoidTypeInContext(base->gallivm->context),
2241 last_args, 9, 0);
2242 }
2243
2244 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2245 struct lp_build_tgsi_context * bld_base,
2246 struct lp_build_emit_data * emit_data);
2247
2248 static bool tgsi_is_array_sampler(unsigned target)
2249 {
2250 return target == TGSI_TEXTURE_1D_ARRAY ||
2251 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2252 target == TGSI_TEXTURE_2D_ARRAY ||
2253 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2254 target == TGSI_TEXTURE_CUBE_ARRAY ||
2255 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2256 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2257 }
2258
2259 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2260 struct lp_build_emit_data *emit_data,
2261 unsigned opcode, unsigned target,
2262 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2263 LLVMValueRef *param, unsigned count,
2264 unsigned dmask)
2265 {
2266 unsigned num_args;
2267 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2268 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2269
2270 /* Pad to power of two vector */
2271 while (count < util_next_power_of_two(count))
2272 param[count++] = LLVMGetUndef(i32);
2273
2274 /* Texture coordinates. */
2275 if (count > 1)
2276 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2277 else
2278 emit_data->args[0] = param[0];
2279
2280 /* Resource. */
2281 emit_data->args[1] = res_ptr;
2282 num_args = 2;
2283
2284 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2285 emit_data->dst_type = LLVMVectorType(i32, 4);
2286 else {
2287 emit_data->dst_type = LLVMVectorType(
2288 LLVMFloatTypeInContext(gallivm->context), 4);
2289
2290 emit_data->args[num_args++] = samp_ptr;
2291 }
2292
2293 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2294 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2295 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2296 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2297 tgsi_is_array_sampler(target)); /* da */
2298 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2299 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2300 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2301 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2302
2303 emit_data->arg_count = num_args;
2304 }
2305
2306 static const struct lp_build_tgsi_action tex_action;
2307
2308 static void tex_fetch_args(
2309 struct lp_build_tgsi_context * bld_base,
2310 struct lp_build_emit_data * emit_data)
2311 {
2312 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2313 struct gallivm_state *gallivm = bld_base->base.gallivm;
2314 LLVMBuilderRef builder = gallivm->builder;
2315 const struct tgsi_full_instruction * inst = emit_data->inst;
2316 unsigned opcode = inst->Instruction.Opcode;
2317 unsigned target = inst->Texture.Texture;
2318 LLVMValueRef coords[5], derivs[6];
2319 LLVMValueRef address[16];
2320 int ref_pos;
2321 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2322 unsigned count = 0;
2323 unsigned chan;
2324 unsigned sampler_src;
2325 unsigned sampler_index;
2326 unsigned num_deriv_channels = 0;
2327 bool has_offset = inst->Texture.NumOffsets > 0;
2328 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2329 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2330 unsigned dmask = 0xf;
2331
2332 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2333 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2334
2335 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2336 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2337 LLVMValueRef ind_index;
2338
2339 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2340
2341 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2342 res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
2343
2344 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2345 samp_ptr = build_indexed_load_const(si_shader_ctx, samp_ptr, ind_index);
2346
2347 if (target == TGSI_TEXTURE_2D_MSAA ||
2348 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2349 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2350 lp_build_const_int32(gallivm,
2351 SI_FMASK_TEX_OFFSET), "");
2352 fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2353 fmask_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
2354 }
2355 } else {
2356 res_ptr = si_shader_ctx->resources[sampler_index];
2357 samp_ptr = si_shader_ctx->samplers[sampler_index];
2358 fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2359 }
2360
2361 if (opcode == TGSI_OPCODE_TXQ) {
2362 if (target == TGSI_TEXTURE_BUFFER) {
2363 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2364
2365 /* Read the size from the buffer descriptor directly. */
2366 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2367 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2368 lp_build_const_int32(gallivm, 6), "");
2369
2370 if (si_shader_ctx->screen->b.chip_class >= VI) {
2371 /* On VI, the descriptor contains the size in bytes,
2372 * but TXQ must return the size in elements.
2373 * The stride is always non-zero for resources using TXQ.
2374 */
2375 LLVMValueRef stride =
2376 LLVMBuildExtractElement(builder, res,
2377 lp_build_const_int32(gallivm, 5), "");
2378 stride = LLVMBuildLShr(builder, stride,
2379 lp_build_const_int32(gallivm, 16), "");
2380 stride = LLVMBuildAnd(builder, stride,
2381 lp_build_const_int32(gallivm, 0x3FFF), "");
2382
2383 size = LLVMBuildUDiv(builder, size, stride, "");
2384 }
2385
2386 emit_data->args[0] = size;
2387 return;
2388 }
2389
2390 /* Textures - set the mip level. */
2391 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2392
2393 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2394 NULL, address, count, 0xf);
2395 return;
2396 }
2397
2398 if (target == TGSI_TEXTURE_BUFFER) {
2399 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2400 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2401 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2402 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2403
2404 /* Bitcast and truncate v8i32 to v16i8. */
2405 LLVMValueRef res = res_ptr;
2406 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2407 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2408 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2409
2410 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2411 emit_data->args[0] = res;
2412 emit_data->args[1] = bld_base->uint_bld.zero;
2413 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2414 emit_data->arg_count = 3;
2415 return;
2416 }
2417
2418 /* Fetch and project texture coordinates */
2419 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2420 for (chan = 0; chan < 3; chan++ ) {
2421 coords[chan] = lp_build_emit_fetch(bld_base,
2422 emit_data->inst, 0,
2423 chan);
2424 if (opcode == TGSI_OPCODE_TXP)
2425 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2426 TGSI_OPCODE_DIV,
2427 coords[chan],
2428 coords[3]);
2429 }
2430
2431 if (opcode == TGSI_OPCODE_TXP)
2432 coords[3] = bld_base->base.one;
2433
2434 /* Pack offsets. */
2435 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2436 /* The offsets are six-bit signed integers packed like this:
2437 * X=[5:0], Y=[13:8], and Z=[21:16].
2438 */
2439 LLVMValueRef offset[3], pack;
2440
2441 assert(inst->Texture.NumOffsets == 1);
2442
2443 for (chan = 0; chan < 3; chan++) {
2444 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2445 emit_data->inst, 0, chan);
2446 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2447 lp_build_const_int32(gallivm, 0x3f), "");
2448 if (chan)
2449 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2450 lp_build_const_int32(gallivm, chan*8), "");
2451 }
2452
2453 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2454 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2455 address[count++] = pack;
2456 }
2457
2458 /* Pack LOD bias value */
2459 if (opcode == TGSI_OPCODE_TXB)
2460 address[count++] = coords[3];
2461 if (opcode == TGSI_OPCODE_TXB2)
2462 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2463
2464 /* Pack depth comparison value */
2465 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2466 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2467 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2468 } else {
2469 assert(ref_pos >= 0);
2470 address[count++] = coords[ref_pos];
2471 }
2472 }
2473
2474 /* Pack user derivatives */
2475 if (opcode == TGSI_OPCODE_TXD) {
2476 int param, num_src_deriv_channels;
2477
2478 switch (target) {
2479 case TGSI_TEXTURE_3D:
2480 num_src_deriv_channels = 3;
2481 num_deriv_channels = 3;
2482 break;
2483 case TGSI_TEXTURE_2D:
2484 case TGSI_TEXTURE_SHADOW2D:
2485 case TGSI_TEXTURE_RECT:
2486 case TGSI_TEXTURE_SHADOWRECT:
2487 case TGSI_TEXTURE_2D_ARRAY:
2488 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2489 num_src_deriv_channels = 2;
2490 num_deriv_channels = 2;
2491 break;
2492 case TGSI_TEXTURE_CUBE:
2493 case TGSI_TEXTURE_SHADOWCUBE:
2494 case TGSI_TEXTURE_CUBE_ARRAY:
2495 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2496 /* Cube derivatives will be converted to 2D. */
2497 num_src_deriv_channels = 3;
2498 num_deriv_channels = 2;
2499 break;
2500 case TGSI_TEXTURE_1D:
2501 case TGSI_TEXTURE_SHADOW1D:
2502 case TGSI_TEXTURE_1D_ARRAY:
2503 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2504 num_src_deriv_channels = 1;
2505 num_deriv_channels = 1;
2506 break;
2507 default:
2508 unreachable("invalid target");
2509 }
2510
2511 for (param = 0; param < 2; param++)
2512 for (chan = 0; chan < num_src_deriv_channels; chan++)
2513 derivs[param * num_src_deriv_channels + chan] =
2514 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2515 }
2516
2517 if (target == TGSI_TEXTURE_CUBE ||
2518 target == TGSI_TEXTURE_CUBE_ARRAY ||
2519 target == TGSI_TEXTURE_SHADOWCUBE ||
2520 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2521 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2522
2523 if (opcode == TGSI_OPCODE_TXD)
2524 for (int i = 0; i < num_deriv_channels * 2; i++)
2525 address[count++] = derivs[i];
2526
2527 /* Pack texture coordinates */
2528 address[count++] = coords[0];
2529 if (num_coords > 1)
2530 address[count++] = coords[1];
2531 if (num_coords > 2)
2532 address[count++] = coords[2];
2533
2534 /* Pack LOD or sample index */
2535 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2536 address[count++] = coords[3];
2537 else if (opcode == TGSI_OPCODE_TXL2)
2538 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2539
2540 if (count > 16) {
2541 assert(!"Cannot handle more than 16 texture address parameters");
2542 count = 16;
2543 }
2544
2545 for (chan = 0; chan < count; chan++ ) {
2546 address[chan] = LLVMBuildBitCast(gallivm->builder,
2547 address[chan], i32, "");
2548 }
2549
2550 /* Adjust the sample index according to FMASK.
2551 *
2552 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2553 * which is the identity mapping. Each nibble says which physical sample
2554 * should be fetched to get that sample.
2555 *
2556 * For example, 0x11111100 means there are only 2 samples stored and
2557 * the second sample covers 3/4 of the pixel. When reading samples 0
2558 * and 1, return physical sample 0 (determined by the first two 0s
2559 * in FMASK), otherwise return physical sample 1.
2560 *
2561 * The sample index should be adjusted as follows:
2562 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2563 */
2564 if (target == TGSI_TEXTURE_2D_MSAA ||
2565 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2566 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2567 struct lp_build_emit_data txf_emit_data = *emit_data;
2568 LLVMValueRef txf_address[4];
2569 unsigned txf_count = count;
2570 struct tgsi_full_instruction inst = {};
2571
2572 memcpy(txf_address, address, sizeof(txf_address));
2573
2574 if (target == TGSI_TEXTURE_2D_MSAA) {
2575 txf_address[2] = bld_base->uint_bld.zero;
2576 }
2577 txf_address[3] = bld_base->uint_bld.zero;
2578
2579 /* Read FMASK using TXF. */
2580 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2581 inst.Texture.Texture = target;
2582 txf_emit_data.inst = &inst;
2583 txf_emit_data.chan = 0;
2584 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2585 target, fmask_ptr, NULL,
2586 txf_address, txf_count, 0xf);
2587 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2588
2589 /* Initialize some constants. */
2590 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2591 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2592
2593 /* Apply the formula. */
2594 LLVMValueRef fmask =
2595 LLVMBuildExtractElement(gallivm->builder,
2596 txf_emit_data.output[0],
2597 uint_bld->zero, "");
2598
2599 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2600
2601 LLVMValueRef sample_index4 =
2602 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2603
2604 LLVMValueRef shifted_fmask =
2605 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2606
2607 LLVMValueRef final_sample =
2608 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2609
2610 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2611 * resource descriptor is 0 (invalid),
2612 */
2613 LLVMValueRef fmask_desc =
2614 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2615 LLVMVectorType(uint_bld->elem_type, 8), "");
2616
2617 LLVMValueRef fmask_word1 =
2618 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2619 uint_bld->one, "");
2620
2621 LLVMValueRef word1_is_nonzero =
2622 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2623 fmask_word1, uint_bld->zero, "");
2624
2625 /* Replace the MSAA sample index. */
2626 address[sample_chan] =
2627 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2628 final_sample, address[sample_chan], "");
2629 }
2630
2631 if (opcode == TGSI_OPCODE_TXF) {
2632 /* add tex offsets */
2633 if (inst->Texture.NumOffsets) {
2634 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2635 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2636 const struct tgsi_texture_offset * off = inst->TexOffsets;
2637
2638 assert(inst->Texture.NumOffsets == 1);
2639
2640 switch (target) {
2641 case TGSI_TEXTURE_3D:
2642 address[2] = lp_build_add(uint_bld, address[2],
2643 bld->immediates[off->Index][off->SwizzleZ]);
2644 /* fall through */
2645 case TGSI_TEXTURE_2D:
2646 case TGSI_TEXTURE_SHADOW2D:
2647 case TGSI_TEXTURE_RECT:
2648 case TGSI_TEXTURE_SHADOWRECT:
2649 case TGSI_TEXTURE_2D_ARRAY:
2650 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2651 address[1] =
2652 lp_build_add(uint_bld, address[1],
2653 bld->immediates[off->Index][off->SwizzleY]);
2654 /* fall through */
2655 case TGSI_TEXTURE_1D:
2656 case TGSI_TEXTURE_SHADOW1D:
2657 case TGSI_TEXTURE_1D_ARRAY:
2658 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2659 address[0] =
2660 lp_build_add(uint_bld, address[0],
2661 bld->immediates[off->Index][off->SwizzleX]);
2662 break;
2663 /* texture offsets do not apply to other texture targets */
2664 }
2665 }
2666 }
2667
2668 if (opcode == TGSI_OPCODE_TG4) {
2669 unsigned gather_comp = 0;
2670
2671 /* DMASK was repurposed for GATHER4. 4 components are always
2672 * returned and DMASK works like a swizzle - it selects
2673 * the component to fetch. The only valid DMASK values are
2674 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2675 * (red,red,red,red) etc.) The ISA document doesn't mention
2676 * this.
2677 */
2678
2679 /* Get the component index from src1.x for Gather4. */
2680 if (!tgsi_is_shadow_target(target)) {
2681 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2682 LLVMValueRef comp_imm;
2683 struct tgsi_src_register src1 = inst->Src[1].Register;
2684
2685 assert(src1.File == TGSI_FILE_IMMEDIATE);
2686
2687 comp_imm = imms[src1.Index][src1.SwizzleX];
2688 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2689 gather_comp = CLAMP(gather_comp, 0, 3);
2690 }
2691
2692 dmask = 1 << gather_comp;
2693 }
2694
2695 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2696 samp_ptr, address, count, dmask);
2697 }
2698
2699 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2700 struct lp_build_tgsi_context * bld_base,
2701 struct lp_build_emit_data * emit_data)
2702 {
2703 struct lp_build_context * base = &bld_base->base;
2704 unsigned opcode = emit_data->inst->Instruction.Opcode;
2705 unsigned target = emit_data->inst->Texture.Texture;
2706 char intr_name[127];
2707 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2708 bool is_shadow = tgsi_is_shadow_target(target);
2709 char type[64];
2710 const char *name = "llvm.SI.image.sample";
2711 const char *infix = "";
2712
2713 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2714 /* Just return the buffer size. */
2715 emit_data->output[emit_data->chan] = emit_data->args[0];
2716 return;
2717 }
2718
2719 if (target == TGSI_TEXTURE_BUFFER) {
2720 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2721 base->gallivm->builder,
2722 "llvm.SI.vs.load.input", emit_data->dst_type,
2723 emit_data->args, emit_data->arg_count,
2724 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2725 return;
2726 }
2727
2728 switch (opcode) {
2729 case TGSI_OPCODE_TXF:
2730 name = target == TGSI_TEXTURE_2D_MSAA ||
2731 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2732 "llvm.SI.image.load" :
2733 "llvm.SI.image.load.mip";
2734 is_shadow = false;
2735 has_offset = false;
2736 break;
2737 case TGSI_OPCODE_TXQ:
2738 name = "llvm.SI.getresinfo";
2739 is_shadow = false;
2740 has_offset = false;
2741 break;
2742 case TGSI_OPCODE_LODQ:
2743 name = "llvm.SI.getlod";
2744 is_shadow = false;
2745 has_offset = false;
2746 break;
2747 case TGSI_OPCODE_TEX:
2748 case TGSI_OPCODE_TEX2:
2749 case TGSI_OPCODE_TXP:
2750 break;
2751 case TGSI_OPCODE_TXB:
2752 case TGSI_OPCODE_TXB2:
2753 infix = ".b";
2754 break;
2755 case TGSI_OPCODE_TXL:
2756 case TGSI_OPCODE_TXL2:
2757 infix = ".l";
2758 break;
2759 case TGSI_OPCODE_TXD:
2760 infix = ".d";
2761 break;
2762 case TGSI_OPCODE_TG4:
2763 name = "llvm.SI.gather4";
2764 break;
2765 default:
2766 assert(0);
2767 return;
2768 }
2769
2770 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2771 sprintf(type, ".v%ui32",
2772 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2773 else
2774 strcpy(type, ".i32");
2775
2776 /* Add the type and suffixes .c, .o if needed. */
2777 sprintf(intr_name, "%s%s%s%s%s",
2778 name, is_shadow ? ".c" : "", infix,
2779 has_offset ? ".o" : "", type);
2780
2781 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2782 base->gallivm->builder, intr_name, emit_data->dst_type,
2783 emit_data->args, emit_data->arg_count,
2784 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2785
2786 /* Divide the number of layers by 6 to get the number of cubes. */
2787 if (opcode == TGSI_OPCODE_TXQ &&
2788 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2789 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2790 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2791 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2792 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2793
2794 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2795 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2796 z = LLVMBuildSDiv(builder, z, six, "");
2797
2798 emit_data->output[emit_data->chan] =
2799 LLVMBuildInsertElement(builder, v4, z, two, "");
2800 }
2801 }
2802
2803 /*
2804 * SI implements derivatives using the local data store (LDS)
2805 * All writes to the LDS happen in all executing threads at
2806 * the same time. TID is the Thread ID for the current
2807 * thread and is a value between 0 and 63, representing
2808 * the thread's position in the wavefront.
2809 *
2810 * For the pixel shader threads are grouped into quads of four pixels.
2811 * The TIDs of the pixels of a quad are:
2812 *
2813 * +------+------+
2814 * |4n + 0|4n + 1|
2815 * +------+------+
2816 * |4n + 2|4n + 3|
2817 * +------+------+
2818 *
2819 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2820 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2821 * the current pixel's column, and masking with 0xfffffffe yields the TID
2822 * of the left pixel of the current pixel's row.
2823 *
2824 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2825 * adding 2 yields the TID of the pixel below the top pixel.
2826 */
2827 /* masks for thread ID. */
2828 #define TID_MASK_TOP_LEFT 0xfffffffc
2829 #define TID_MASK_TOP 0xfffffffd
2830 #define TID_MASK_LEFT 0xfffffffe
2831
2832 static void si_llvm_emit_ddxy(
2833 const struct lp_build_tgsi_action * action,
2834 struct lp_build_tgsi_context * bld_base,
2835 struct lp_build_emit_data * emit_data)
2836 {
2837 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2838 struct gallivm_state *gallivm = bld_base->base.gallivm;
2839 struct lp_build_context * base = &bld_base->base;
2840 const struct tgsi_full_instruction *inst = emit_data->inst;
2841 unsigned opcode = inst->Instruction.Opcode;
2842 LLVMValueRef indices[2];
2843 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2844 LLVMValueRef tl, trbl, result[4];
2845 LLVMTypeRef i32;
2846 unsigned swizzle[4];
2847 unsigned c;
2848 int idx;
2849 unsigned mask;
2850
2851 i32 = LLVMInt32TypeInContext(gallivm->context);
2852
2853 indices[0] = bld_base->uint_bld.zero;
2854 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2855 NULL, 0, LLVMReadNoneAttribute);
2856 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2857 indices, 2, "");
2858
2859 if (opcode == TGSI_OPCODE_DDX_FINE)
2860 mask = TID_MASK_LEFT;
2861 else if (opcode == TGSI_OPCODE_DDY_FINE)
2862 mask = TID_MASK_TOP;
2863 else
2864 mask = TID_MASK_TOP_LEFT;
2865
2866 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2867 lp_build_const_int32(gallivm, mask), "");
2868 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2869 indices, 2, "");
2870
2871 /* for DDX we want to next X pixel, DDY next Y pixel. */
2872 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2873 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2874 lp_build_const_int32(gallivm, idx), "");
2875 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2876 indices, 2, "");
2877
2878 for (c = 0; c < 4; ++c) {
2879 unsigned i;
2880
2881 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2882 for (i = 0; i < c; ++i) {
2883 if (swizzle[i] == swizzle[c]) {
2884 result[c] = result[i];
2885 break;
2886 }
2887 }
2888 if (i != c)
2889 continue;
2890
2891 LLVMBuildStore(gallivm->builder,
2892 LLVMBuildBitCast(gallivm->builder,
2893 lp_build_emit_fetch(bld_base, inst, 0, c),
2894 i32, ""),
2895 store_ptr);
2896
2897 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2898 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2899
2900 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2901 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2902
2903 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2904 }
2905
2906 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2907 }
2908
2909 /*
2910 * this takes an I,J coordinate pair,
2911 * and works out the X and Y derivatives.
2912 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
2913 */
2914 static LLVMValueRef si_llvm_emit_ddxy_interp(
2915 struct lp_build_tgsi_context *bld_base,
2916 LLVMValueRef interp_ij)
2917 {
2918 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2919 struct gallivm_state *gallivm = bld_base->base.gallivm;
2920 struct lp_build_context *base = &bld_base->base;
2921 LLVMValueRef indices[2];
2922 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
2923 LLVMValueRef tl, tr, bl, result[4];
2924 LLVMTypeRef i32;
2925 unsigned c;
2926
2927 i32 = LLVMInt32TypeInContext(gallivm->context);
2928
2929 indices[0] = bld_base->uint_bld.zero;
2930 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2931 NULL, 0, LLVMReadNoneAttribute);
2932 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2933 indices, 2, "");
2934
2935 temp = LLVMBuildAnd(gallivm->builder, indices[1],
2936 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
2937
2938 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
2939 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
2940
2941 indices[1] = temp;
2942 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2943 indices, 2, "");
2944
2945 indices[1] = temp2;
2946 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2947 indices, 2, "");
2948
2949 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
2950 lp_build_const_int32(gallivm, 1), "");
2951 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2952 indices, 2, "");
2953
2954 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
2955 lp_build_const_int32(gallivm, 2), "");
2956 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2957 indices, 2, "");
2958
2959 for (c = 0; c < 2; ++c) {
2960 LLVMValueRef store_val;
2961 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
2962
2963 store_val = LLVMBuildExtractElement(gallivm->builder,
2964 interp_ij, c_ll, "");
2965 LLVMBuildStore(gallivm->builder,
2966 store_val,
2967 store_ptr);
2968
2969 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
2970 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2971
2972 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
2973 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
2974
2975 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
2976
2977 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
2978 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2979
2980 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
2981 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
2982
2983 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
2984 }
2985
2986 return lp_build_gather_values(gallivm, result, 4);
2987 }
2988
2989 static void interp_fetch_args(
2990 struct lp_build_tgsi_context *bld_base,
2991 struct lp_build_emit_data *emit_data)
2992 {
2993 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2994 struct gallivm_state *gallivm = bld_base->base.gallivm;
2995 const struct tgsi_full_instruction *inst = emit_data->inst;
2996
2997 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
2998 /* offset is in second src, first two channels */
2999 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3000 emit_data->inst, 1,
3001 0);
3002 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3003 emit_data->inst, 1,
3004 1);
3005 emit_data->arg_count = 2;
3006 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3007 LLVMValueRef sample_position;
3008 LLVMValueRef sample_id;
3009 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3010
3011 /* fetch sample ID, then fetch its sample position,
3012 * and place into first two channels.
3013 */
3014 sample_id = lp_build_emit_fetch(bld_base,
3015 emit_data->inst, 1, 0);
3016 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3017 LLVMInt32TypeInContext(gallivm->context),
3018 "");
3019 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3020
3021 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3022 sample_position,
3023 lp_build_const_int32(gallivm, 0), "");
3024
3025 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3026 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3027 sample_position,
3028 lp_build_const_int32(gallivm, 1), "");
3029 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3030 emit_data->arg_count = 2;
3031 }
3032 }
3033
3034 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3035 struct lp_build_tgsi_context *bld_base,
3036 struct lp_build_emit_data *emit_data)
3037 {
3038 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3039 struct si_shader *shader = si_shader_ctx->shader;
3040 struct gallivm_state *gallivm = bld_base->base.gallivm;
3041 LLVMValueRef interp_param;
3042 const struct tgsi_full_instruction *inst = emit_data->inst;
3043 const char *intr_name;
3044 int input_index;
3045 int chan;
3046 int i;
3047 LLVMValueRef attr_number;
3048 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3049 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3050 int interp_param_idx;
3051 unsigned location;
3052
3053 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3054 input_index = inst->Src[0].Register.Index;
3055
3056 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3057 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3058 location = TGSI_INTERPOLATE_LOC_CENTER;
3059 else
3060 location = TGSI_INTERPOLATE_LOC_CENTROID;
3061
3062 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3063 location);
3064 if (interp_param_idx == -1)
3065 return;
3066 else if (interp_param_idx)
3067 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3068 else
3069 interp_param = NULL;
3070
3071 attr_number = lp_build_const_int32(gallivm,
3072 shader->ps_input_param_offset[input_index]);
3073
3074 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3075 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3076 LLVMValueRef ij_out[2];
3077 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3078
3079 /*
3080 * take the I then J parameters, and the DDX/Y for it, and
3081 * calculate the IJ inputs for the interpolator.
3082 * temp1 = ddx * offset/sample.x + I;
3083 * interp_param.I = ddy * offset/sample.y + temp1;
3084 * temp1 = ddx * offset/sample.x + J;
3085 * interp_param.J = ddy * offset/sample.y + temp1;
3086 */
3087 for (i = 0; i < 2; i++) {
3088 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3089 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3090 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3091 ddxy_out, ix_ll, "");
3092 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3093 ddxy_out, iy_ll, "");
3094 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3095 interp_param, ix_ll, "");
3096 LLVMValueRef temp1, temp2;
3097
3098 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3099 LLVMFloatTypeInContext(gallivm->context), "");
3100
3101 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3102
3103 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3104
3105 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3106
3107 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3108
3109 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3110 temp2,
3111 LLVMIntTypeInContext(gallivm->context, 32), "");
3112 }
3113 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3114 }
3115
3116 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3117 for (chan = 0; chan < 2; chan++) {
3118 LLVMValueRef args[4];
3119 LLVMValueRef llvm_chan;
3120 unsigned schan;
3121
3122 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3123 llvm_chan = lp_build_const_int32(gallivm, schan);
3124
3125 args[0] = llvm_chan;
3126 args[1] = attr_number;
3127 args[2] = params;
3128 args[3] = interp_param;
3129
3130 emit_data->output[chan] =
3131 lp_build_intrinsic(gallivm->builder, intr_name,
3132 input_type, args, args[3] ? 4 : 3,
3133 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3134 }
3135 }
3136
3137 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3138 struct lp_build_emit_data *emit_data)
3139 {
3140 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3141 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3142 unsigned stream;
3143
3144 assert(src0.File == TGSI_FILE_IMMEDIATE);
3145
3146 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3147 return stream;
3148 }
3149
3150 /* Emit one vertex from the geometry shader */
3151 static void si_llvm_emit_vertex(
3152 const struct lp_build_tgsi_action *action,
3153 struct lp_build_tgsi_context *bld_base,
3154 struct lp_build_emit_data *emit_data)
3155 {
3156 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3157 struct lp_build_context *uint = &bld_base->uint_bld;
3158 struct si_shader *shader = si_shader_ctx->shader;
3159 struct tgsi_shader_info *info = &shader->selector->info;
3160 struct gallivm_state *gallivm = bld_base->base.gallivm;
3161 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3162 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3163 SI_PARAM_GS2VS_OFFSET);
3164 LLVMValueRef gs_next_vertex;
3165 LLVMValueRef can_emit, kill;
3166 LLVMValueRef args[2];
3167 unsigned chan;
3168 int i;
3169 unsigned stream;
3170
3171 stream = si_llvm_get_stream(bld_base, emit_data);
3172
3173 /* Write vertex attribute values to GSVS ring */
3174 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3175 si_shader_ctx->gs_next_vertex[stream],
3176 "");
3177
3178 /* If this thread has already emitted the declared maximum number of
3179 * vertices, kill it: excessive vertex emissions are not supposed to
3180 * have any effect, and GS threads have no externally observable
3181 * effects other than emitting vertices.
3182 */
3183 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3184 lp_build_const_int32(gallivm,
3185 shader->selector->gs_max_out_vertices), "");
3186 kill = lp_build_select(&bld_base->base, can_emit,
3187 lp_build_const_float(gallivm, 1.0f),
3188 lp_build_const_float(gallivm, -1.0f));
3189
3190 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3191 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3192
3193 for (i = 0; i < info->num_outputs; i++) {
3194 LLVMValueRef *out_ptr =
3195 si_shader_ctx->radeon_bld.soa.outputs[i];
3196
3197 for (chan = 0; chan < 4; chan++) {
3198 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3199 LLVMValueRef voffset =
3200 lp_build_const_int32(gallivm, (i * 4 + chan) *
3201 shader->selector->gs_max_out_vertices);
3202
3203 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3204 voffset = lp_build_mul_imm(uint, voffset, 4);
3205
3206 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3207
3208 build_tbuffer_store(si_shader_ctx,
3209 si_shader_ctx->gsvs_ring[stream],
3210 out_val, 1,
3211 voffset, soffset, 0,
3212 V_008F0C_BUF_DATA_FORMAT_32,
3213 V_008F0C_BUF_NUM_FORMAT_UINT,
3214 1, 0, 1, 1, 0);
3215 }
3216 }
3217 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3218 lp_build_const_int32(gallivm, 1));
3219
3220 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3221
3222 /* Signal vertex emission */
3223 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3224 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3225 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3226 LLVMVoidTypeInContext(gallivm->context), args, 2,
3227 LLVMNoUnwindAttribute);
3228 }
3229
3230 /* Cut one primitive from the geometry shader */
3231 static void si_llvm_emit_primitive(
3232 const struct lp_build_tgsi_action *action,
3233 struct lp_build_tgsi_context *bld_base,
3234 struct lp_build_emit_data *emit_data)
3235 {
3236 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3237 struct gallivm_state *gallivm = bld_base->base.gallivm;
3238 LLVMValueRef args[2];
3239 unsigned stream;
3240
3241 /* Signal primitive cut */
3242 stream = si_llvm_get_stream(bld_base, emit_data);
3243 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3244 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3245 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3246 LLVMVoidTypeInContext(gallivm->context), args, 2,
3247 LLVMNoUnwindAttribute);
3248 }
3249
3250 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3251 struct lp_build_tgsi_context *bld_base,
3252 struct lp_build_emit_data *emit_data)
3253 {
3254 struct gallivm_state *gallivm = bld_base->base.gallivm;
3255
3256 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3257 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3258 LLVMNoUnwindAttribute);
3259 }
3260
3261 static const struct lp_build_tgsi_action tex_action = {
3262 .fetch_args = tex_fetch_args,
3263 .emit = build_tex_intrinsic,
3264 };
3265
3266 static const struct lp_build_tgsi_action interp_action = {
3267 .fetch_args = interp_fetch_args,
3268 .emit = build_interp_intrinsic,
3269 };
3270
3271 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3272 {
3273 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3274 LLVMValueRef args[3];
3275
3276 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3277 args[1] = 0;
3278 args[2] = lp_build_const_int32(gallivm, 1);
3279
3280 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3281 }
3282
3283 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3284 {
3285 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3286 CONST_ADDR_SPACE);
3287 }
3288
3289 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3290 struct pipe_stream_output_info *so,
3291 LLVMTypeRef *params, LLVMTypeRef i32,
3292 unsigned *num_params)
3293 {
3294 int i;
3295
3296 /* Streamout SGPRs. */
3297 if (so->num_outputs) {
3298 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3299 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3300 }
3301 /* A streamout buffer offset is loaded if the stride is non-zero. */
3302 for (i = 0; i < 4; i++) {
3303 if (!so->stride[i])
3304 continue;
3305
3306 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3307 }
3308 }
3309
3310 static void create_function(struct si_shader_context *si_shader_ctx)
3311 {
3312 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3313 struct gallivm_state *gallivm = bld_base->base.gallivm;
3314 struct si_shader *shader = si_shader_ctx->shader;
3315 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3316 unsigned i, last_array_pointer, last_sgpr, num_params;
3317
3318 i8 = LLVMInt8TypeInContext(gallivm->context);
3319 i32 = LLVMInt32TypeInContext(gallivm->context);
3320 f32 = LLVMFloatTypeInContext(gallivm->context);
3321 v2i32 = LLVMVectorType(i32, 2);
3322 v3i32 = LLVMVectorType(i32, 3);
3323 v4i32 = LLVMVectorType(i32, 4);
3324 v8i32 = LLVMVectorType(i32, 8);
3325 v16i8 = LLVMVectorType(i8, 16);
3326
3327 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3328 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3329 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3330 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3331 last_array_pointer = SI_PARAM_RESOURCE;
3332
3333 switch (si_shader_ctx->type) {
3334 case TGSI_PROCESSOR_VERTEX:
3335 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3336 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3337 params[SI_PARAM_BASE_VERTEX] = i32;
3338 params[SI_PARAM_START_INSTANCE] = i32;
3339 num_params = SI_PARAM_START_INSTANCE+1;
3340
3341 if (shader->key.vs.as_es) {
3342 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3343 } else if (shader->key.vs.as_ls) {
3344 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3345 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3346 } else {
3347 if (shader->is_gs_copy_shader) {
3348 last_array_pointer = SI_PARAM_CONST;
3349 num_params = SI_PARAM_CONST+1;
3350 }
3351
3352 /* The locations of the other parameters are assigned dynamically. */
3353 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3354 params, i32, &num_params);
3355 }
3356
3357 last_sgpr = num_params-1;
3358
3359 /* VGPRs */
3360 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3361 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3362 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3363 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3364 break;
3365
3366 case TGSI_PROCESSOR_TESS_CTRL:
3367 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3368 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3369 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3370 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3371 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3372
3373 /* VGPRs */
3374 params[SI_PARAM_PATCH_ID] = i32;
3375 params[SI_PARAM_REL_IDS] = i32;
3376 num_params = SI_PARAM_REL_IDS+1;
3377 break;
3378
3379 case TGSI_PROCESSOR_TESS_EVAL:
3380 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3381 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3382 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3383
3384 if (shader->key.tes.as_es) {
3385 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3386 } else {
3387 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3388 params, i32, &num_params);
3389 }
3390 last_sgpr = num_params - 1;
3391
3392 /* VGPRs */
3393 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3394 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3395 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3396 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3397 break;
3398
3399 case TGSI_PROCESSOR_GEOMETRY:
3400 params[SI_PARAM_GS2VS_OFFSET] = i32;
3401 params[SI_PARAM_GS_WAVE_ID] = i32;
3402 last_sgpr = SI_PARAM_GS_WAVE_ID;
3403
3404 /* VGPRs */
3405 params[SI_PARAM_VTX0_OFFSET] = i32;
3406 params[SI_PARAM_VTX1_OFFSET] = i32;
3407 params[SI_PARAM_PRIMITIVE_ID] = i32;
3408 params[SI_PARAM_VTX2_OFFSET] = i32;
3409 params[SI_PARAM_VTX3_OFFSET] = i32;
3410 params[SI_PARAM_VTX4_OFFSET] = i32;
3411 params[SI_PARAM_VTX5_OFFSET] = i32;
3412 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3413 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3414 break;
3415
3416 case TGSI_PROCESSOR_FRAGMENT:
3417 params[SI_PARAM_ALPHA_REF] = f32;
3418 params[SI_PARAM_PRIM_MASK] = i32;
3419 last_sgpr = SI_PARAM_PRIM_MASK;
3420 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3421 params[SI_PARAM_PERSP_CENTER] = v2i32;
3422 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3423 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3424 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3425 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3426 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3427 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3428 params[SI_PARAM_POS_X_FLOAT] = f32;
3429 params[SI_PARAM_POS_Y_FLOAT] = f32;
3430 params[SI_PARAM_POS_Z_FLOAT] = f32;
3431 params[SI_PARAM_POS_W_FLOAT] = f32;
3432 params[SI_PARAM_FRONT_FACE] = f32;
3433 params[SI_PARAM_ANCILLARY] = i32;
3434 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3435 params[SI_PARAM_POS_FIXED_PT] = f32;
3436 num_params = SI_PARAM_POS_FIXED_PT+1;
3437 break;
3438
3439 default:
3440 assert(0 && "unimplemented shader");
3441 return;
3442 }
3443
3444 assert(num_params <= Elements(params));
3445 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3446 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3447
3448 if (shader->dx10_clamp_mode)
3449 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3450 "enable-no-nans-fp-math", "true");
3451
3452 for (i = 0; i <= last_sgpr; ++i) {
3453 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3454
3455 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3456 * to move load. Inputs are constant so this is fine. */
3457 if (i <= last_array_pointer)
3458 LLVMAddAttribute(P, LLVMByValAttribute);
3459 else
3460 LLVMAddAttribute(P, LLVMInRegAttribute);
3461 }
3462
3463 if (bld_base->info &&
3464 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3465 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3466 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3467 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3468 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3469 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3470 si_shader_ctx->lds =
3471 LLVMAddGlobalInAddressSpace(gallivm->module,
3472 LLVMArrayType(i32, 64),
3473 "ddxy_lds",
3474 LOCAL_ADDR_SPACE);
3475
3476 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3477 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3478 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3479 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3480 unsigned vertex_data_dw_size = 32*32*4;
3481 unsigned patch_data_dw_size = 32*4;
3482 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3483 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3484 unsigned lds_dwords = patch_dw_size;
3485
3486 /* The actual size is computed outside of the shader to reduce
3487 * the number of shader variants. */
3488 si_shader_ctx->lds =
3489 LLVMAddGlobalInAddressSpace(gallivm->module,
3490 LLVMArrayType(i32, lds_dwords),
3491 "tess_lds",
3492 LOCAL_ADDR_SPACE);
3493 }
3494 }
3495
3496 static void preload_constants(struct si_shader_context *si_shader_ctx)
3497 {
3498 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3499 struct gallivm_state * gallivm = bld_base->base.gallivm;
3500 const struct tgsi_shader_info * info = bld_base->info;
3501 unsigned buf;
3502 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3503
3504 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3505 unsigned i, num_const = info->const_file_max[buf] + 1;
3506
3507 if (num_const == 0)
3508 continue;
3509
3510 /* Allocate space for the constant values */
3511 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3512
3513 /* Load the resource descriptor */
3514 si_shader_ctx->const_resource[buf] =
3515 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3516
3517 /* Load the constants, we rely on the code sinking to do the rest */
3518 for (i = 0; i < num_const * 4; ++i) {
3519 si_shader_ctx->constants[buf][i] =
3520 buffer_load_const(gallivm->builder,
3521 si_shader_ctx->const_resource[buf],
3522 lp_build_const_int32(gallivm, i * 4),
3523 bld_base->base.elem_type);
3524 }
3525 }
3526 }
3527
3528 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3529 {
3530 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3531 struct gallivm_state * gallivm = bld_base->base.gallivm;
3532 const struct tgsi_shader_info * info = bld_base->info;
3533
3534 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3535
3536 LLVMValueRef res_ptr, samp_ptr;
3537 LLVMValueRef offset;
3538
3539 if (num_samplers == 0)
3540 return;
3541
3542 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3543 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3544
3545 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3546 for (i = 0; i < num_samplers; ++i) {
3547 /* Resource */
3548 offset = lp_build_const_int32(gallivm, i);
3549 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3550
3551 /* Sampler */
3552 offset = lp_build_const_int32(gallivm, i);
3553 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3554
3555 /* FMASK resource */
3556 if (info->is_msaa_sampler[i]) {
3557 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3558 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3559 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3560 }
3561 }
3562 }
3563
3564 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3565 {
3566 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3567 struct gallivm_state * gallivm = bld_base->base.gallivm;
3568 unsigned i;
3569
3570 /* Streamout can only be used if the shader is compiled as VS. */
3571 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3572 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3573 (si_shader_ctx->shader->key.vs.as_es ||
3574 si_shader_ctx->shader->key.vs.as_ls)) ||
3575 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3576 si_shader_ctx->shader->key.tes.as_es))
3577 return;
3578
3579 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3580 SI_PARAM_RW_BUFFERS);
3581
3582 /* Load the resources, we rely on the code sinking to do the rest */
3583 for (i = 0; i < 4; ++i) {
3584 if (si_shader_ctx->shader->selector->so.stride[i]) {
3585 LLVMValueRef offset = lp_build_const_int32(gallivm,
3586 SI_SO_BUF_OFFSET + i);
3587
3588 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3589 }
3590 }
3591 }
3592
3593 /**
3594 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3595 * for later use.
3596 */
3597 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3598 {
3599 struct gallivm_state *gallivm =
3600 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3601
3602 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3603 SI_PARAM_RW_BUFFERS);
3604
3605 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3606 si_shader_ctx->shader->key.vs.as_es) ||
3607 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3608 si_shader_ctx->shader->key.tes.as_es) ||
3609 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3610 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3611
3612 si_shader_ctx->esgs_ring =
3613 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3614 }
3615
3616 if (si_shader_ctx->shader->is_gs_copy_shader) {
3617 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3618
3619 si_shader_ctx->gsvs_ring[0] =
3620 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3621 }
3622 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3623 int i;
3624 for (i = 0; i < 4; i++) {
3625 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3626
3627 si_shader_ctx->gsvs_ring[i] =
3628 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3629 }
3630 }
3631 }
3632
3633 void si_shader_binary_read_config(const struct si_screen *sscreen,
3634 struct si_shader *shader,
3635 unsigned symbol_offset)
3636 {
3637 unsigned i;
3638 const unsigned char *config =
3639 radeon_shader_binary_config_start(&shader->binary,
3640 symbol_offset);
3641
3642 /* XXX: We may be able to emit some of these values directly rather than
3643 * extracting fields to be emitted later.
3644 */
3645
3646 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3647 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3648 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3649 switch (reg) {
3650 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3651 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3652 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3653 case R_00B848_COMPUTE_PGM_RSRC1:
3654 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3655 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3656 shader->float_mode = G_00B028_FLOAT_MODE(value);
3657 break;
3658 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3659 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3660 break;
3661 case R_00B84C_COMPUTE_PGM_RSRC2:
3662 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3663 break;
3664 case R_0286CC_SPI_PS_INPUT_ENA:
3665 shader->spi_ps_input_ena = value;
3666 break;
3667 case R_0286E8_SPI_TMPRING_SIZE:
3668 case R_00B860_COMPUTE_TMPRING_SIZE:
3669 /* WAVESIZE is in units of 256 dwords. */
3670 shader->scratch_bytes_per_wave =
3671 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3672 break;
3673 default:
3674 fprintf(stderr, "Warning: Compiler emitted unknown "
3675 "config register: 0x%x\n", reg);
3676 break;
3677 }
3678 }
3679 }
3680
3681 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3682 struct si_shader *shader,
3683 uint64_t scratch_va)
3684 {
3685 unsigned i;
3686 uint32_t scratch_rsrc_dword0 = scratch_va;
3687 uint32_t scratch_rsrc_dword1 =
3688 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3689 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3690
3691 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3692 const struct radeon_shader_reloc *reloc =
3693 &shader->binary.relocs[i];
3694 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3695 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3696 &scratch_rsrc_dword0, 4);
3697 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3698 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3699 &scratch_rsrc_dword1, 4);
3700 }
3701 }
3702 }
3703
3704 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3705 {
3706 const struct radeon_shader_binary *binary = &shader->binary;
3707 unsigned code_size = binary->code_size + binary->rodata_size;
3708 unsigned char *ptr;
3709
3710 r600_resource_reference(&shader->bo, NULL);
3711 shader->bo = si_resource_create_custom(&sscreen->b.b,
3712 PIPE_USAGE_IMMUTABLE,
3713 code_size);
3714 if (!shader->bo)
3715 return -ENOMEM;
3716
3717 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3718 PIPE_TRANSFER_READ_WRITE);
3719 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3720 if (binary->rodata_size > 0) {
3721 ptr += binary->code_size;
3722 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3723 binary->rodata_size);
3724 }
3725
3726 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3727 return 0;
3728 }
3729
3730 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3731 {
3732 const struct radeon_shader_binary *binary = &shader->binary;
3733 unsigned i;
3734 bool dump = r600_can_dump_shader(&sscreen->b,
3735 shader->selector ? shader->selector->tokens : NULL);
3736
3737 si_shader_binary_read_config(sscreen, shader, 0);
3738 si_shader_binary_upload(sscreen, shader);
3739
3740 if (dump) {
3741 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3742 if (binary->disasm_string) {
3743 fprintf(stderr, "\nShader Disassembly:\n\n");
3744 fprintf(stderr, "%s\n", binary->disasm_string);
3745 } else {
3746 fprintf(stderr, "SI CODE:\n");
3747 for (i = 0; i < binary->code_size; i+=4 ) {
3748 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3749 binary->code[i + 2], binary->code[i + 1],
3750 binary->code[i]);
3751 }
3752 }
3753 }
3754
3755 fprintf(stderr, "*** SHADER STATS ***\n"
3756 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3757 "Scratch: %d bytes per wave\n********************\n",
3758 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3759 shader->lds_size, shader->scratch_bytes_per_wave);
3760 }
3761 return 0;
3762 }
3763
3764 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3765 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3766 {
3767 int r = 0;
3768 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3769 shader->selector ? shader->selector->tokens : NULL);
3770 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3771
3772 r = radeon_llvm_compile(mod, &shader->binary,
3773 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3774 if (r)
3775 return r;
3776
3777 r = si_shader_binary_read(sscreen, shader);
3778
3779 FREE(shader->binary.config);
3780 FREE(shader->binary.rodata);
3781 FREE(shader->binary.global_symbol_offsets);
3782 if (shader->scratch_bytes_per_wave == 0) {
3783 FREE(shader->binary.code);
3784 FREE(shader->binary.relocs);
3785 memset(&shader->binary, 0,
3786 offsetof(struct radeon_shader_binary, disasm_string));
3787 }
3788 return r;
3789 }
3790
3791 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3792 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3793 struct si_shader_context *si_shader_ctx,
3794 struct si_shader *gs, bool dump)
3795 {
3796 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3797 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3798 struct lp_build_context *base = &bld_base->base;
3799 struct lp_build_context *uint = &bld_base->uint_bld;
3800 struct si_shader *shader = si_shader_ctx->shader;
3801 struct si_shader_output_values *outputs;
3802 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3803 LLVMValueRef args[9];
3804 int i, r;
3805
3806 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3807
3808 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3809 shader->is_gs_copy_shader = true;
3810
3811 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3812
3813 create_meta_data(si_shader_ctx);
3814 create_function(si_shader_ctx);
3815 preload_streamout_buffers(si_shader_ctx);
3816 preload_ring_buffers(si_shader_ctx);
3817
3818 args[0] = si_shader_ctx->gsvs_ring[0];
3819 args[1] = lp_build_mul_imm(uint,
3820 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3821 si_shader_ctx->param_vertex_id),
3822 4);
3823 args[3] = uint->zero;
3824 args[4] = uint->one; /* OFFEN */
3825 args[5] = uint->zero; /* IDXEN */
3826 args[6] = uint->one; /* GLC */
3827 args[7] = uint->one; /* SLC */
3828 args[8] = uint->zero; /* TFE */
3829
3830 /* Fetch vertex data from GSVS ring */
3831 for (i = 0; i < gsinfo->num_outputs; ++i) {
3832 unsigned chan;
3833
3834 outputs[i].name = gsinfo->output_semantic_name[i];
3835 outputs[i].sid = gsinfo->output_semantic_index[i];
3836
3837 for (chan = 0; chan < 4; chan++) {
3838 args[2] = lp_build_const_int32(gallivm,
3839 (i * 4 + chan) *
3840 gs->selector->gs_max_out_vertices * 16 * 4);
3841
3842 outputs[i].values[chan] =
3843 LLVMBuildBitCast(gallivm->builder,
3844 lp_build_intrinsic(gallivm->builder,
3845 "llvm.SI.buffer.load.dword.i32.i32",
3846 LLVMInt32TypeInContext(gallivm->context),
3847 args, 9,
3848 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3849 base->elem_type, "");
3850 }
3851 }
3852
3853 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3854
3855 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3856
3857 if (dump)
3858 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3859
3860 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3861 si_shader_ctx->tm, bld_base->base.gallivm->module);
3862
3863 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3864
3865 FREE(outputs);
3866 return r;
3867 }
3868
3869 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
3870 {
3871 int i;
3872
3873 fprintf(f, "SHADER KEY\n");
3874
3875 switch (shader) {
3876 case PIPE_SHADER_VERTEX:
3877 fprintf(f, " instance_divisors = {");
3878 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
3879 fprintf(f, !i ? "%u" : ", %u",
3880 key->vs.instance_divisors[i]);
3881 fprintf(f, "}\n");
3882
3883 if (key->vs.as_es)
3884 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3885 key->vs.es_enabled_outputs);
3886 fprintf(f, " as_es = %u\n", key->vs.as_es);
3887 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
3888 break;
3889
3890 case PIPE_SHADER_TESS_CTRL:
3891 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
3892 break;
3893
3894 case PIPE_SHADER_TESS_EVAL:
3895 if (key->tes.as_es)
3896 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3897 key->tes.es_enabled_outputs);
3898 fprintf(f, " as_es = %u\n", key->tes.as_es);
3899 break;
3900
3901 case PIPE_SHADER_GEOMETRY:
3902 break;
3903
3904 case PIPE_SHADER_FRAGMENT:
3905 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
3906 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
3907 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
3908 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
3909 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
3910 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
3911 break;
3912
3913 default:
3914 assert(0);
3915 }
3916 }
3917
3918 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
3919 struct si_shader *shader)
3920 {
3921 struct si_shader_selector *sel = shader->selector;
3922 struct tgsi_token *tokens = sel->tokens;
3923 struct si_shader_context si_shader_ctx;
3924 struct lp_build_tgsi_context * bld_base;
3925 struct tgsi_shader_info stipple_shader_info;
3926 LLVMModuleRef mod;
3927 int r = 0;
3928 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
3929 shader->key.ps.poly_stipple;
3930 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
3931
3932 if (poly_stipple) {
3933 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
3934 SI_POLY_STIPPLE_SAMPLER);
3935 tgsi_scan_shader(tokens, &stipple_shader_info);
3936 }
3937
3938 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
3939 * conversion fails. */
3940 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
3941 si_dump_shader_key(sel->type, &shader->key, stderr);
3942 tgsi_dump(tokens, 0);
3943 si_dump_streamout(&sel->so);
3944 }
3945
3946 assert(shader->nparam == 0);
3947
3948 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
3949 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
3950 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
3951
3952 if (sel->type != PIPE_SHADER_COMPUTE)
3953 shader->dx10_clamp_mode = true;
3954
3955 if (sel->info.uses_kill)
3956 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
3957
3958 shader->uses_instanceid = sel->info.uses_instanceid;
3959 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
3960 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
3961
3962 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
3963 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
3964 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
3965
3966 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
3967 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
3968 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
3969 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
3970 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
3971 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
3972 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
3973 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
3974 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
3975 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
3976 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
3977 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
3978
3979 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
3980 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
3981 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
3982 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
3983
3984 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
3985 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
3986 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
3987
3988 if (HAVE_LLVM >= 0x0306) {
3989 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
3990 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
3991 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
3992 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
3993 }
3994
3995 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
3996 si_shader_ctx.shader = shader;
3997 si_shader_ctx.type = tgsi_get_processor_type(tokens);
3998 si_shader_ctx.screen = sscreen;
3999 si_shader_ctx.tm = tm;
4000
4001 switch (si_shader_ctx.type) {
4002 case TGSI_PROCESSOR_VERTEX:
4003 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4004 if (shader->key.vs.as_ls)
4005 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4006 else if (shader->key.vs.as_es)
4007 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4008 else
4009 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4010 break;
4011 case TGSI_PROCESSOR_TESS_CTRL:
4012 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4013 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4014 bld_base->emit_store = store_output_tcs;
4015 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4016 break;
4017 case TGSI_PROCESSOR_TESS_EVAL:
4018 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4019 if (shader->key.tes.as_es)
4020 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4021 else
4022 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4023 break;
4024 case TGSI_PROCESSOR_GEOMETRY:
4025 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4026 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4027 break;
4028 case TGSI_PROCESSOR_FRAGMENT:
4029 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4030 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4031
4032 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4033 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4034 shader->db_shader_control |=
4035 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4036 break;
4037 case TGSI_FS_DEPTH_LAYOUT_LESS:
4038 shader->db_shader_control |=
4039 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4040 break;
4041 }
4042 break;
4043 default:
4044 assert(!"Unsupported shader type");
4045 return -1;
4046 }
4047
4048 create_meta_data(&si_shader_ctx);
4049 create_function(&si_shader_ctx);
4050 preload_constants(&si_shader_ctx);
4051 preload_samplers(&si_shader_ctx);
4052 preload_streamout_buffers(&si_shader_ctx);
4053 preload_ring_buffers(&si_shader_ctx);
4054
4055 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4056 int i;
4057 for (i = 0; i < 4; i++) {
4058 si_shader_ctx.gs_next_vertex[i] =
4059 lp_build_alloca(bld_base->base.gallivm,
4060 bld_base->uint_bld.elem_type, "");
4061 }
4062 }
4063
4064 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4065 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4066 goto out;
4067 }
4068
4069 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4070
4071 mod = bld_base->base.gallivm->module;
4072 r = si_compile_llvm(sscreen, shader, tm, mod);
4073 if (r) {
4074 fprintf(stderr, "LLVM failed to compile shader\n");
4075 goto out;
4076 }
4077
4078 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4079
4080 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4081 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4082 shader->gs_copy_shader->selector = shader->selector;
4083 shader->gs_copy_shader->key = shader->key;
4084 si_shader_ctx.shader = shader->gs_copy_shader;
4085 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4086 shader, dump))) {
4087 free(shader->gs_copy_shader);
4088 shader->gs_copy_shader = NULL;
4089 goto out;
4090 }
4091 }
4092
4093 out:
4094 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4095 FREE(si_shader_ctx.constants[i]);
4096 if (poly_stipple)
4097 tgsi_free_tokens(tokens);
4098 return r;
4099 }
4100
4101 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
4102 {
4103 if (shader->gs_copy_shader)
4104 si_shader_destroy(ctx, shader->gs_copy_shader);
4105
4106 if (shader->scratch_bo)
4107 r600_resource_reference(&shader->scratch_bo, NULL);
4108
4109 r600_resource_reference(&shader->bo, NULL);
4110
4111 FREE(shader->binary.code);
4112 FREE(shader->binary.relocs);
4113 FREE(shader->binary.disasm_string);
4114 }