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radeonsi: Use param export count from si_llvm_export_vs in si_shader_vs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/r600_cs.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_pstipple.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "si_shader.h"
47 #include "sid.h"
48
49 #include <errno.h>
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned name;
61 unsigned sid;
62 };
63
64 struct si_shader_context
65 {
66 struct radeon_llvm_context radeon_bld;
67 struct si_shader *shader;
68 struct si_screen *screen;
69 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
70 int param_streamout_config;
71 int param_streamout_write_index;
72 int param_streamout_offset[4];
73 int param_vertex_id;
74 int param_instance_id;
75 LLVMTargetMachineRef tm;
76 LLVMValueRef const_md;
77 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
78 LLVMValueRef ddxy_lds;
79 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
80 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
81 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
82 LLVMValueRef so_buffers[4];
83 LLVMValueRef esgs_ring;
84 LLVMValueRef gsvs_ring;
85 LLVMValueRef gs_next_vertex;
86 };
87
88 static struct si_shader_context * si_shader_context(
89 struct lp_build_tgsi_context * bld_base)
90 {
91 return (struct si_shader_context *)bld_base;
92 }
93
94
95 #define PERSPECTIVE_BASE 0
96 #define LINEAR_BASE 9
97
98 #define SAMPLE_OFFSET 0
99 #define CENTER_OFFSET 2
100 #define CENTROID_OFSET 4
101
102 #define USE_SGPR_MAX_SUFFIX_LEN 5
103 #define CONST_ADDR_SPACE 2
104 #define LOCAL_ADDR_SPACE 3
105 #define USER_SGPR_ADDR_SPACE 8
106
107
108 #define SENDMSG_GS 2
109 #define SENDMSG_GS_DONE 3
110
111 #define SENDMSG_GS_OP_NOP (0 << 4)
112 #define SENDMSG_GS_OP_CUT (1 << 4)
113 #define SENDMSG_GS_OP_EMIT (2 << 4)
114 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
115
116 /**
117 * Returns a unique index for a semantic name and index. The index must be
118 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
119 * calculated.
120 */
121 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
122 {
123 switch (semantic_name) {
124 case TGSI_SEMANTIC_POSITION:
125 return 0;
126 case TGSI_SEMANTIC_PSIZE:
127 return 1;
128 case TGSI_SEMANTIC_CLIPDIST:
129 assert(index <= 1);
130 return 2 + index;
131 case TGSI_SEMANTIC_GENERIC:
132 assert(index <= 63-4);
133 return 4 + index;
134
135 default:
136 /* Don't fail here. The result of this function is only used
137 * for LS, TCS, TES, and GS, where legacy GL semantics can't
138 * occur, but this function is called for all vertex shaders
139 * before it's known whether LS will be compiled or not.
140 */
141 return 0;
142 }
143 }
144
145 /**
146 * Given a semantic name and index of a parameter and a mask of used parameters
147 * (inputs or outputs), return the index of the parameter in the list of all
148 * used parameters.
149 *
150 * For example, assume this list of parameters:
151 * POSITION, PSIZE, GENERIC0, GENERIC2
152 * which has the mask:
153 * 11000000000101
154 * Then:
155 * querying POSITION returns 0,
156 * querying PSIZE returns 1,
157 * querying GENERIC0 returns 2,
158 * querying GENERIC2 returns 3.
159 *
160 * Which can be used as an offset to a parameter buffer in units of vec4s.
161 */
162 static int get_param_index(unsigned semantic_name, unsigned index,
163 uint64_t mask)
164 {
165 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
166 int i, param_index = 0;
167
168 /* If not present... */
169 if (!((1llu << unique_index) & mask))
170 return -1;
171
172 for (i = 0; mask; i++) {
173 uint64_t bit = 1llu << i;
174
175 if (bit & mask) {
176 if (i == unique_index)
177 return param_index;
178
179 mask &= ~bit;
180 param_index++;
181 }
182 }
183
184 assert(!"unreachable");
185 return -1;
186 }
187
188 /**
189 * Get the value of a shader input parameter and extract a bitfield.
190 */
191 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
192 unsigned param, unsigned rshift,
193 unsigned bitwidth)
194 {
195 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
196 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
197 param);
198
199 if (rshift)
200 value = LLVMBuildLShr(gallivm->builder, value,
201 lp_build_const_int32(gallivm, rshift), "");
202
203 if (rshift + bitwidth < 32) {
204 unsigned mask = (1 << bitwidth) - 1;
205 value = LLVMBuildAnd(gallivm->builder, value,
206 lp_build_const_int32(gallivm, mask), "");
207 }
208
209 return value;
210 }
211
212 /**
213 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
214 * It's equivalent to doing a load from &base_ptr[index].
215 *
216 * \param base_ptr Where the array starts.
217 * \param index The element index into the array.
218 */
219 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
220 LLVMValueRef base_ptr, LLVMValueRef index)
221 {
222 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
223 struct gallivm_state *gallivm = bld_base->base.gallivm;
224 LLVMValueRef indices[2], pointer;
225
226 indices[0] = bld_base->uint_bld.zero;
227 indices[1] = index;
228
229 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
230 return LLVMBuildLoad(gallivm->builder, pointer, "");
231 }
232
233 /**
234 * Do a load from &base_ptr[index], but also add a flag that it's loading
235 * a constant.
236 */
237 static LLVMValueRef build_indexed_load_const(
238 struct si_shader_context * si_shader_ctx,
239 LLVMValueRef base_ptr, LLVMValueRef index)
240 {
241 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
242 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
243 return result;
244 }
245
246 static LLVMValueRef get_instance_index_for_fetch(
247 struct radeon_llvm_context * radeon_bld,
248 unsigned divisor)
249 {
250 struct si_shader_context *si_shader_ctx =
251 si_shader_context(&radeon_bld->soa.bld_base);
252 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
253
254 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
255 si_shader_ctx->param_instance_id);
256
257 /* The division must be done before START_INSTANCE is added. */
258 if (divisor > 1)
259 result = LLVMBuildUDiv(gallivm->builder, result,
260 lp_build_const_int32(gallivm, divisor), "");
261
262 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
263 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
264 }
265
266 static void declare_input_vs(
267 struct radeon_llvm_context *radeon_bld,
268 unsigned input_index,
269 const struct tgsi_full_declaration *decl)
270 {
271 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
272 struct gallivm_state *gallivm = base->gallivm;
273 struct si_shader_context *si_shader_ctx =
274 si_shader_context(&radeon_bld->soa.bld_base);
275 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
276
277 unsigned chan;
278
279 LLVMValueRef t_list_ptr;
280 LLVMValueRef t_offset;
281 LLVMValueRef t_list;
282 LLVMValueRef attribute_offset;
283 LLVMValueRef buffer_index;
284 LLVMValueRef args[3];
285 LLVMTypeRef vec4_type;
286 LLVMValueRef input;
287
288 /* Load the T list */
289 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
290
291 t_offset = lp_build_const_int32(gallivm, input_index);
292
293 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
294
295 /* Build the attribute offset */
296 attribute_offset = lp_build_const_int32(gallivm, 0);
297
298 if (divisor) {
299 /* Build index from instance ID, start instance and divisor */
300 si_shader_ctx->shader->uses_instanceid = true;
301 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
302 } else {
303 /* Load the buffer index for vertices. */
304 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
305 si_shader_ctx->param_vertex_id);
306 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
307 SI_PARAM_BASE_VERTEX);
308 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
309 }
310
311 vec4_type = LLVMVectorType(base->elem_type, 4);
312 args[0] = t_list;
313 args[1] = attribute_offset;
314 args[2] = buffer_index;
315 input = build_intrinsic(gallivm->builder,
316 "llvm.SI.vs.load.input", vec4_type, args, 3,
317 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
318
319 /* Break up the vec4 into individual components */
320 for (chan = 0; chan < 4; chan++) {
321 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
322 /* XXX: Use a helper function for this. There is one in
323 * tgsi_llvm.c. */
324 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
325 LLVMBuildExtractElement(gallivm->builder,
326 input, llvm_chan, "");
327 }
328 }
329
330 static LLVMValueRef fetch_input_gs(
331 struct lp_build_tgsi_context *bld_base,
332 const struct tgsi_full_src_register *reg,
333 enum tgsi_opcode_type type,
334 unsigned swizzle)
335 {
336 struct lp_build_context *base = &bld_base->base;
337 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
338 struct si_shader *shader = si_shader_ctx->shader;
339 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
340 struct gallivm_state *gallivm = base->gallivm;
341 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
342 LLVMValueRef vtx_offset;
343 LLVMValueRef args[9];
344 unsigned vtx_offset_param;
345 struct tgsi_shader_info *info = &shader->selector->info;
346 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
347 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
348
349 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
350 if (swizzle == 0)
351 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
352 SI_PARAM_PRIMITIVE_ID);
353 else
354 return uint->zero;
355 }
356
357 if (!reg->Register.Dimension)
358 return NULL;
359
360 if (swizzle == ~0) {
361 LLVMValueRef values[TGSI_NUM_CHANNELS];
362 unsigned chan;
363 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
364 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
365 }
366 return lp_build_gather_values(bld_base->base.gallivm, values,
367 TGSI_NUM_CHANNELS);
368 }
369
370 /* Get the vertex offset parameter */
371 vtx_offset_param = reg->Dimension.Index;
372 if (vtx_offset_param < 2) {
373 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
374 } else {
375 assert(vtx_offset_param < 6);
376 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
377 }
378 vtx_offset = lp_build_mul_imm(uint,
379 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
380 vtx_offset_param),
381 4);
382
383 args[0] = si_shader_ctx->esgs_ring;
384 args[1] = vtx_offset;
385 args[2] = lp_build_const_int32(gallivm,
386 (get_param_index(semantic_name, semantic_index,
387 shader->selector->gs_used_inputs) * 4 +
388 swizzle) * 256);
389 args[3] = uint->zero;
390 args[4] = uint->one; /* OFFEN */
391 args[5] = uint->zero; /* IDXEN */
392 args[6] = uint->one; /* GLC */
393 args[7] = uint->zero; /* SLC */
394 args[8] = uint->zero; /* TFE */
395
396 return LLVMBuildBitCast(gallivm->builder,
397 build_intrinsic(gallivm->builder,
398 "llvm.SI.buffer.load.dword.i32.i32",
399 i32, args, 9,
400 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
401 tgsi2llvmtype(bld_base, type), "");
402 }
403
404 static void declare_input_fs(
405 struct radeon_llvm_context *radeon_bld,
406 unsigned input_index,
407 const struct tgsi_full_declaration *decl)
408 {
409 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
410 struct si_shader_context *si_shader_ctx =
411 si_shader_context(&radeon_bld->soa.bld_base);
412 struct si_shader *shader = si_shader_ctx->shader;
413 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
414 struct gallivm_state *gallivm = base->gallivm;
415 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
416 LLVMValueRef main_fn = radeon_bld->main_fn;
417
418 LLVMValueRef interp_param;
419 const char * intr_name;
420
421 /* This value is:
422 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
423 * quad begins a new primitive. Bit 0 always needs
424 * to be unset)
425 * [32:16] ParamOffset
426 *
427 */
428 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
429 LLVMValueRef attr_number;
430
431 unsigned chan;
432
433 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
434 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
435 unsigned soa_index =
436 radeon_llvm_reg_index_soa(input_index, chan);
437 radeon_bld->inputs[soa_index] =
438 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
439
440 if (chan == 3)
441 /* RCP for fragcoord.w */
442 radeon_bld->inputs[soa_index] =
443 LLVMBuildFDiv(gallivm->builder,
444 lp_build_const_float(gallivm, 1.0f),
445 radeon_bld->inputs[soa_index],
446 "");
447 }
448 return;
449 }
450
451 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
452 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
453 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
454 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
455 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
456 lp_build_const_float(gallivm, 0.0f);
457 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
458 lp_build_const_float(gallivm, 1.0f);
459
460 return;
461 }
462
463 shader->ps_input_param_offset[input_index] = shader->nparam++;
464 attr_number = lp_build_const_int32(gallivm,
465 shader->ps_input_param_offset[input_index]);
466
467 switch (decl->Interp.Interpolate) {
468 case TGSI_INTERPOLATE_CONSTANT:
469 interp_param = 0;
470 break;
471 case TGSI_INTERPOLATE_LINEAR:
472 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
473 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
474 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
475 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
476 else
477 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
478 break;
479 case TGSI_INTERPOLATE_COLOR:
480 case TGSI_INTERPOLATE_PERSPECTIVE:
481 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
482 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
483 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
484 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
485 else
486 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
487 break;
488 default:
489 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
490 return;
491 }
492
493 /* fs.constant returns the param from the middle vertex, so it's not
494 * really useful for flat shading. It's meant to be used for custom
495 * interpolation (but the intrinsic can't fetch from the other two
496 * vertices).
497 *
498 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
499 * to do the right thing. The only reason we use fs.constant is that
500 * fs.interp cannot be used on integers, because they can be equal
501 * to NaN.
502 */
503 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
504
505 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
506 si_shader_ctx->shader->key.ps.color_two_side) {
507 LLVMValueRef args[4];
508 LLVMValueRef face, is_face_positive;
509 LLVMValueRef back_attr_number =
510 lp_build_const_int32(gallivm,
511 shader->ps_input_param_offset[input_index] + 1);
512
513 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
514
515 is_face_positive = LLVMBuildFCmp(gallivm->builder,
516 LLVMRealOGT, face,
517 lp_build_const_float(gallivm, 0.0f),
518 "");
519
520 args[2] = params;
521 args[3] = interp_param;
522 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
523 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
524 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
525 LLVMValueRef front, back;
526
527 args[0] = llvm_chan;
528 args[1] = attr_number;
529 front = build_intrinsic(gallivm->builder, intr_name,
530 input_type, args, args[3] ? 4 : 3,
531 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
532
533 args[1] = back_attr_number;
534 back = build_intrinsic(gallivm->builder, intr_name,
535 input_type, args, args[3] ? 4 : 3,
536 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
537
538 radeon_bld->inputs[soa_index] =
539 LLVMBuildSelect(gallivm->builder,
540 is_face_positive,
541 front,
542 back,
543 "");
544 }
545
546 shader->nparam++;
547 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
548 LLVMValueRef args[4];
549
550 args[0] = uint->zero;
551 args[1] = attr_number;
552 args[2] = params;
553 args[3] = interp_param;
554 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
555 build_intrinsic(gallivm->builder, intr_name,
556 input_type, args, args[3] ? 4 : 3,
557 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
558 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
559 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
560 lp_build_const_float(gallivm, 0.0f);
561 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
562 lp_build_const_float(gallivm, 1.0f);
563 } else {
564 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
565 LLVMValueRef args[4];
566 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
567 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
568 args[0] = llvm_chan;
569 args[1] = attr_number;
570 args[2] = params;
571 args[3] = interp_param;
572 radeon_bld->inputs[soa_index] =
573 build_intrinsic(gallivm->builder, intr_name,
574 input_type, args, args[3] ? 4 : 3,
575 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
576 }
577 }
578 }
579
580 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
581 {
582 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
583 SI_PARAM_ANCILLARY, 8, 4);
584 }
585
586 /**
587 * Load a dword from a constant buffer.
588 */
589 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
590 LLVMValueRef offset, LLVMTypeRef return_type)
591 {
592 LLVMValueRef args[2] = {resource, offset};
593
594 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
595 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
596 }
597
598 static void declare_system_value(
599 struct radeon_llvm_context * radeon_bld,
600 unsigned index,
601 const struct tgsi_full_declaration *decl)
602 {
603 struct si_shader_context *si_shader_ctx =
604 si_shader_context(&radeon_bld->soa.bld_base);
605 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
606 struct gallivm_state *gallivm = &radeon_bld->gallivm;
607 LLVMValueRef value = 0;
608
609 switch (decl->Semantic.Name) {
610 case TGSI_SEMANTIC_INSTANCEID:
611 value = LLVMGetParam(radeon_bld->main_fn,
612 si_shader_ctx->param_instance_id);
613 break;
614
615 case TGSI_SEMANTIC_VERTEXID:
616 value = LLVMBuildAdd(gallivm->builder,
617 LLVMGetParam(radeon_bld->main_fn,
618 si_shader_ctx->param_vertex_id),
619 LLVMGetParam(radeon_bld->main_fn,
620 SI_PARAM_BASE_VERTEX), "");
621 break;
622
623 case TGSI_SEMANTIC_VERTEXID_NOBASE:
624 value = LLVMGetParam(radeon_bld->main_fn,
625 si_shader_ctx->param_vertex_id);
626 break;
627
628 case TGSI_SEMANTIC_BASEVERTEX:
629 value = LLVMGetParam(radeon_bld->main_fn,
630 SI_PARAM_BASE_VERTEX);
631 break;
632
633 case TGSI_SEMANTIC_INVOCATIONID:
634 value = LLVMGetParam(radeon_bld->main_fn,
635 SI_PARAM_GS_INSTANCE_ID);
636 break;
637
638 case TGSI_SEMANTIC_SAMPLEID:
639 value = get_sample_id(radeon_bld);
640 break;
641
642 case TGSI_SEMANTIC_SAMPLEPOS:
643 {
644 LLVMBuilderRef builder = gallivm->builder;
645 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
646 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
647 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
648
649 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
650 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
651 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
652
653 LLVMValueRef pos[4] = {
654 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
655 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
656 lp_build_const_float(gallivm, 0),
657 lp_build_const_float(gallivm, 0)
658 };
659 value = lp_build_gather_values(gallivm, pos, 4);
660 break;
661 }
662
663 case TGSI_SEMANTIC_SAMPLEMASK:
664 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
665 * Therefore, force gl_SampleMaskIn to 1 for GL. */
666 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
667 value = uint_bld->one;
668 else
669 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
670 break;
671
672 default:
673 assert(!"unknown system value");
674 return;
675 }
676
677 radeon_bld->system_values[index] = value;
678 }
679
680 static LLVMValueRef fetch_constant(
681 struct lp_build_tgsi_context * bld_base,
682 const struct tgsi_full_src_register *reg,
683 enum tgsi_opcode_type type,
684 unsigned swizzle)
685 {
686 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
687 struct lp_build_context * base = &bld_base->base;
688 const struct tgsi_ind_register *ireg = &reg->Indirect;
689 unsigned buf, idx;
690
691 LLVMValueRef addr;
692 LLVMValueRef result;
693
694 if (swizzle == LP_CHAN_ALL) {
695 unsigned chan;
696 LLVMValueRef values[4];
697 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
698 values[chan] = fetch_constant(bld_base, reg, type, chan);
699
700 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
701 }
702
703 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
704 idx = reg->Register.Index * 4 + swizzle;
705
706 if (!reg->Register.Indirect)
707 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
708
709 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
710 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
711 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
712 addr = lp_build_add(&bld_base->uint_bld, addr,
713 lp_build_const_int32(base->gallivm, idx * 4));
714
715 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
716 addr, base->elem_type);
717
718 return bitcast(bld_base, type, result);
719 }
720
721 /* Initialize arguments for the shader export intrinsic */
722 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
723 LLVMValueRef *values,
724 unsigned target,
725 LLVMValueRef *args)
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 struct lp_build_context *uint =
729 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
730 struct lp_build_context *base = &bld_base->base;
731 unsigned compressed = 0;
732 unsigned chan;
733
734 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
735 int cbuf = target - V_008DFC_SQ_EXP_MRT;
736
737 if (cbuf >= 0 && cbuf < 8) {
738 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
739
740 if (compressed)
741 si_shader_ctx->shader->spi_shader_col_format |=
742 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
743 else
744 si_shader_ctx->shader->spi_shader_col_format |=
745 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
746
747 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
748 }
749 }
750
751 if (compressed) {
752 /* Pixel shader needs to pack output values before export */
753 for (chan = 0; chan < 2; chan++ ) {
754 args[0] = values[2 * chan];
755 args[1] = values[2 * chan + 1];
756 args[chan + 5] =
757 build_intrinsic(base->gallivm->builder,
758 "llvm.SI.packf16",
759 LLVMInt32TypeInContext(base->gallivm->context),
760 args, 2,
761 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
762 args[chan + 7] = args[chan + 5] =
763 LLVMBuildBitCast(base->gallivm->builder,
764 args[chan + 5],
765 LLVMFloatTypeInContext(base->gallivm->context),
766 "");
767 }
768
769 /* Set COMPR flag */
770 args[4] = uint->one;
771 } else {
772 for (chan = 0; chan < 4; chan++ )
773 /* +5 because the first output value will be
774 * the 6th argument to the intrinsic. */
775 args[chan + 5] = values[chan];
776
777 /* Clear COMPR flag */
778 args[4] = uint->zero;
779 }
780
781 /* XXX: This controls which components of the output
782 * registers actually get exported. (e.g bit 0 means export
783 * X component, bit 1 means export Y component, etc.) I'm
784 * hard coding this to 0xf for now. In the future, we might
785 * want to do something else. */
786 args[0] = lp_build_const_int32(base->gallivm, 0xf);
787
788 /* Specify whether the EXEC mask represents the valid mask */
789 args[1] = uint->zero;
790
791 /* Specify whether this is the last export */
792 args[2] = uint->zero;
793
794 /* Specify the target we are exporting */
795 args[3] = lp_build_const_int32(base->gallivm, target);
796
797 /* XXX: We probably need to keep track of the output
798 * values, so we know what we are passing to the next
799 * stage. */
800 }
801
802 /* Load from output pointers and initialize arguments for the shader export intrinsic */
803 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
804 LLVMValueRef *out_ptr,
805 unsigned target,
806 LLVMValueRef *args)
807 {
808 struct gallivm_state *gallivm = bld_base->base.gallivm;
809 LLVMValueRef values[4];
810 int i;
811
812 for (i = 0; i < 4; i++)
813 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
814
815 si_llvm_init_export_args(bld_base, values, target, args);
816 }
817
818 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
819 LLVMValueRef alpha_ptr)
820 {
821 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
822 struct gallivm_state *gallivm = bld_base->base.gallivm;
823
824 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
825 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
826 SI_PARAM_ALPHA_REF);
827
828 LLVMValueRef alpha_pass =
829 lp_build_cmp(&bld_base->base,
830 si_shader_ctx->shader->key.ps.alpha_func,
831 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
832 alpha_ref);
833 LLVMValueRef arg =
834 lp_build_select(&bld_base->base,
835 alpha_pass,
836 lp_build_const_float(gallivm, 1.0f),
837 lp_build_const_float(gallivm, -1.0f));
838
839 build_intrinsic(gallivm->builder,
840 "llvm.AMDGPU.kill",
841 LLVMVoidTypeInContext(gallivm->context),
842 &arg, 1, 0);
843 } else {
844 build_intrinsic(gallivm->builder,
845 "llvm.AMDGPU.kilp",
846 LLVMVoidTypeInContext(gallivm->context),
847 NULL, 0, 0);
848 }
849
850 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
851 }
852
853 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
854 LLVMValueRef alpha_ptr)
855 {
856 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
857 struct gallivm_state *gallivm = bld_base->base.gallivm;
858 LLVMValueRef coverage, alpha;
859
860 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
861 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
862 SI_PARAM_SAMPLE_COVERAGE);
863 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
864
865 coverage = build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
866 bld_base->int_bld.elem_type,
867 &coverage, 1, LLVMReadNoneAttribute);
868
869 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
870 bld_base->base.elem_type, "");
871
872 coverage = LLVMBuildFMul(gallivm->builder, coverage,
873 lp_build_const_float(gallivm,
874 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
875
876 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
877 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
878 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
879 }
880
881 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
882 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
883 {
884 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
885 struct lp_build_context *base = &bld_base->base;
886 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
887 unsigned reg_index;
888 unsigned chan;
889 unsigned const_chan;
890 LLVMValueRef base_elt;
891 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
892 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
893 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
894
895 for (reg_index = 0; reg_index < 2; reg_index ++) {
896 LLVMValueRef *args = pos[2 + reg_index];
897
898 args[5] =
899 args[6] =
900 args[7] =
901 args[8] = lp_build_const_float(base->gallivm, 0.0f);
902
903 /* Compute dot products of position and user clip plane vectors */
904 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
905 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
906 args[1] = lp_build_const_int32(base->gallivm,
907 ((reg_index * 4 + chan) * 4 +
908 const_chan) * 4);
909 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
910 args[1], base->elem_type);
911 args[5 + chan] =
912 lp_build_add(base, args[5 + chan],
913 lp_build_mul(base, base_elt,
914 out_elts[const_chan]));
915 }
916 }
917
918 args[0] = lp_build_const_int32(base->gallivm, 0xf);
919 args[1] = uint->zero;
920 args[2] = uint->zero;
921 args[3] = lp_build_const_int32(base->gallivm,
922 V_008DFC_SQ_EXP_POS + 2 + reg_index);
923 args[4] = uint->zero;
924 }
925 }
926
927 static void si_dump_streamout(struct pipe_stream_output_info *so)
928 {
929 unsigned i;
930
931 if (so->num_outputs)
932 fprintf(stderr, "STREAMOUT\n");
933
934 for (i = 0; i < so->num_outputs; i++) {
935 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
936 so->output[i].start_component;
937 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
938 i, so->output[i].output_buffer,
939 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
940 so->output[i].register_index,
941 mask & 1 ? "x" : "",
942 mask & 2 ? "y" : "",
943 mask & 4 ? "z" : "",
944 mask & 8 ? "w" : "");
945 }
946 }
947
948 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
949 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
950 * or v4i32 (num_channels=3,4). */
951 static void build_tbuffer_store(struct si_shader_context *shader,
952 LLVMValueRef rsrc,
953 LLVMValueRef vdata,
954 unsigned num_channels,
955 LLVMValueRef vaddr,
956 LLVMValueRef soffset,
957 unsigned inst_offset,
958 unsigned dfmt,
959 unsigned nfmt,
960 unsigned offen,
961 unsigned idxen,
962 unsigned glc,
963 unsigned slc,
964 unsigned tfe)
965 {
966 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
967 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
968 LLVMValueRef args[] = {
969 rsrc,
970 vdata,
971 LLVMConstInt(i32, num_channels, 0),
972 vaddr,
973 soffset,
974 LLVMConstInt(i32, inst_offset, 0),
975 LLVMConstInt(i32, dfmt, 0),
976 LLVMConstInt(i32, nfmt, 0),
977 LLVMConstInt(i32, offen, 0),
978 LLVMConstInt(i32, idxen, 0),
979 LLVMConstInt(i32, glc, 0),
980 LLVMConstInt(i32, slc, 0),
981 LLVMConstInt(i32, tfe, 0)
982 };
983
984 /* The instruction offset field has 12 bits */
985 assert(offen || inst_offset < (1 << 12));
986
987 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
988 unsigned func = CLAMP(num_channels, 1, 3) - 1;
989 const char *types[] = {"i32", "v2i32", "v4i32"};
990 char name[256];
991 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
992
993 lp_build_intrinsic(gallivm->builder, name,
994 LLVMVoidTypeInContext(gallivm->context),
995 args, Elements(args));
996 }
997
998 static void build_streamout_store(struct si_shader_context *shader,
999 LLVMValueRef rsrc,
1000 LLVMValueRef vdata,
1001 unsigned num_channels,
1002 LLVMValueRef vaddr,
1003 LLVMValueRef soffset,
1004 unsigned inst_offset)
1005 {
1006 static unsigned dfmt[] = {
1007 V_008F0C_BUF_DATA_FORMAT_32,
1008 V_008F0C_BUF_DATA_FORMAT_32_32,
1009 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1010 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1011 };
1012 assert(num_channels >= 1 && num_channels <= 4);
1013
1014 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1015 inst_offset, dfmt[num_channels-1],
1016 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1017 }
1018
1019 /* On SI, the vertex shader is responsible for writing streamout data
1020 * to buffers. */
1021 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1022 struct si_shader_output_values *outputs,
1023 unsigned noutput)
1024 {
1025 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1026 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1027 LLVMBuilderRef builder = gallivm->builder;
1028 int i, j;
1029 struct lp_build_if_state if_ctx;
1030
1031 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1032
1033 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1034 LLVMValueRef so_vtx_count =
1035 unpack_param(shader, shader->param_streamout_config, 16, 7);
1036
1037 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
1038 NULL, 0, LLVMReadNoneAttribute);
1039
1040 /* can_emit = tid < so_vtx_count; */
1041 LLVMValueRef can_emit =
1042 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1043
1044 /* Emit the streamout code conditionally. This actually avoids
1045 * out-of-bounds buffer access. The hw tells us via the SGPR
1046 * (so_vtx_count) which threads are allowed to emit streamout data. */
1047 lp_build_if(&if_ctx, gallivm, can_emit);
1048 {
1049 /* The buffer offset is computed as follows:
1050 * ByteOffset = streamout_offset[buffer_id]*4 +
1051 * (streamout_write_index + thread_id)*stride[buffer_id] +
1052 * attrib_offset
1053 */
1054
1055 LLVMValueRef so_write_index =
1056 LLVMGetParam(shader->radeon_bld.main_fn,
1057 shader->param_streamout_write_index);
1058
1059 /* Compute (streamout_write_index + thread_id). */
1060 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1061
1062 /* Compute the write offset for each enabled buffer. */
1063 LLVMValueRef so_write_offset[4] = {};
1064 for (i = 0; i < 4; i++) {
1065 if (!so->stride[i])
1066 continue;
1067
1068 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1069 shader->param_streamout_offset[i]);
1070 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1071
1072 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1073 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1074 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1075 }
1076
1077 /* Write streamout data. */
1078 for (i = 0; i < so->num_outputs; i++) {
1079 unsigned buf_idx = so->output[i].output_buffer;
1080 unsigned reg = so->output[i].register_index;
1081 unsigned start = so->output[i].start_component;
1082 unsigned num_comps = so->output[i].num_components;
1083 LLVMValueRef out[4];
1084
1085 assert(num_comps && num_comps <= 4);
1086 if (!num_comps || num_comps > 4)
1087 continue;
1088
1089 if (reg >= noutput)
1090 continue;
1091
1092 /* Load the output as int. */
1093 for (j = 0; j < num_comps; j++) {
1094 out[j] = LLVMBuildBitCast(builder,
1095 outputs[reg].values[start+j],
1096 i32, "");
1097 }
1098
1099 /* Pack the output. */
1100 LLVMValueRef vdata = NULL;
1101
1102 switch (num_comps) {
1103 case 1: /* as i32 */
1104 vdata = out[0];
1105 break;
1106 case 2: /* as v2i32 */
1107 case 3: /* as v4i32 (aligned to 4) */
1108 case 4: /* as v4i32 */
1109 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1110 for (j = 0; j < num_comps; j++) {
1111 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1112 LLVMConstInt(i32, j, 0), "");
1113 }
1114 break;
1115 }
1116
1117 build_streamout_store(shader, shader->so_buffers[buf_idx],
1118 vdata, num_comps,
1119 so_write_offset[buf_idx],
1120 LLVMConstInt(i32, 0, 0),
1121 so->output[i].dst_offset*4);
1122 }
1123 }
1124 lp_build_endif(&if_ctx);
1125 }
1126
1127
1128 /* Generate export instructions for hardware VS shader stage */
1129 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1130 struct si_shader_output_values *outputs,
1131 unsigned noutput)
1132 {
1133 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1134 struct si_shader * shader = si_shader_ctx->shader;
1135 struct lp_build_context * base = &bld_base->base;
1136 struct lp_build_context * uint =
1137 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1138 LLVMValueRef args[9];
1139 LLVMValueRef pos_args[4][9] = { { 0 } };
1140 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1141 unsigned semantic_name, semantic_index;
1142 unsigned target;
1143 unsigned param_count = 0;
1144 unsigned pos_idx;
1145 int i;
1146
1147 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1148 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1149 }
1150
1151 for (i = 0; i < noutput; i++) {
1152 semantic_name = outputs[i].name;
1153 semantic_index = outputs[i].sid;
1154
1155 handle_semantic:
1156 /* Select the correct target */
1157 switch(semantic_name) {
1158 case TGSI_SEMANTIC_PSIZE:
1159 psize_value = outputs[i].values[0];
1160 continue;
1161 case TGSI_SEMANTIC_EDGEFLAG:
1162 edgeflag_value = outputs[i].values[0];
1163 continue;
1164 case TGSI_SEMANTIC_LAYER:
1165 layer_value = outputs[i].values[0];
1166 semantic_name = TGSI_SEMANTIC_GENERIC;
1167 goto handle_semantic;
1168 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1169 viewport_index_value = outputs[i].values[0];
1170 semantic_name = TGSI_SEMANTIC_GENERIC;
1171 goto handle_semantic;
1172 case TGSI_SEMANTIC_POSITION:
1173 target = V_008DFC_SQ_EXP_POS;
1174 break;
1175 case TGSI_SEMANTIC_COLOR:
1176 case TGSI_SEMANTIC_BCOLOR:
1177 target = V_008DFC_SQ_EXP_PARAM + param_count;
1178 shader->vs_output_param_offset[i] = param_count;
1179 param_count++;
1180 break;
1181 case TGSI_SEMANTIC_CLIPDIST:
1182 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1183 break;
1184 case TGSI_SEMANTIC_CLIPVERTEX:
1185 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1186 continue;
1187 case TGSI_SEMANTIC_PRIMID:
1188 case TGSI_SEMANTIC_FOG:
1189 case TGSI_SEMANTIC_TEXCOORD:
1190 case TGSI_SEMANTIC_GENERIC:
1191 target = V_008DFC_SQ_EXP_PARAM + param_count;
1192 shader->vs_output_param_offset[i] = param_count;
1193 param_count++;
1194 break;
1195 default:
1196 target = 0;
1197 fprintf(stderr,
1198 "Warning: SI unhandled vs output type:%d\n",
1199 semantic_name);
1200 }
1201
1202 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1203
1204 if (target >= V_008DFC_SQ_EXP_POS &&
1205 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1206 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1207 args, sizeof(args));
1208 } else {
1209 lp_build_intrinsic(base->gallivm->builder,
1210 "llvm.SI.export",
1211 LLVMVoidTypeInContext(base->gallivm->context),
1212 args, 9);
1213 }
1214
1215 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1216 semantic_name = TGSI_SEMANTIC_GENERIC;
1217 goto handle_semantic;
1218 }
1219 }
1220
1221 shader->nr_param_exports = param_count;
1222
1223 /* We need to add the position output manually if it's missing. */
1224 if (!pos_args[0][0]) {
1225 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1226 pos_args[0][1] = uint->zero; /* EXEC mask */
1227 pos_args[0][2] = uint->zero; /* last export? */
1228 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1229 pos_args[0][4] = uint->zero; /* COMPR flag */
1230 pos_args[0][5] = base->zero; /* X */
1231 pos_args[0][6] = base->zero; /* Y */
1232 pos_args[0][7] = base->zero; /* Z */
1233 pos_args[0][8] = base->one; /* W */
1234 }
1235
1236 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1237 if (shader->selector->info.writes_psize ||
1238 shader->selector->info.writes_edgeflag ||
1239 shader->selector->info.writes_viewport_index ||
1240 shader->selector->info.writes_layer) {
1241 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1242 shader->selector->info.writes_psize |
1243 (shader->selector->info.writes_edgeflag << 1) |
1244 (shader->selector->info.writes_layer << 2) |
1245 (shader->selector->info.writes_viewport_index << 3));
1246 pos_args[1][1] = uint->zero; /* EXEC mask */
1247 pos_args[1][2] = uint->zero; /* last export? */
1248 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1249 pos_args[1][4] = uint->zero; /* COMPR flag */
1250 pos_args[1][5] = base->zero; /* X */
1251 pos_args[1][6] = base->zero; /* Y */
1252 pos_args[1][7] = base->zero; /* Z */
1253 pos_args[1][8] = base->zero; /* W */
1254
1255 if (shader->selector->info.writes_psize)
1256 pos_args[1][5] = psize_value;
1257
1258 if (shader->selector->info.writes_edgeflag) {
1259 /* The output is a float, but the hw expects an integer
1260 * with the first bit containing the edge flag. */
1261 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1262 edgeflag_value,
1263 bld_base->uint_bld.elem_type, "");
1264 edgeflag_value = lp_build_min(&bld_base->int_bld,
1265 edgeflag_value,
1266 bld_base->int_bld.one);
1267
1268 /* The LLVM intrinsic expects a float. */
1269 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1270 edgeflag_value,
1271 base->elem_type, "");
1272 }
1273
1274 if (shader->selector->info.writes_layer)
1275 pos_args[1][7] = layer_value;
1276
1277 if (shader->selector->info.writes_viewport_index)
1278 pos_args[1][8] = viewport_index_value;
1279 }
1280
1281 for (i = 0; i < 4; i++)
1282 if (pos_args[i][0])
1283 shader->nr_pos_exports++;
1284
1285 pos_idx = 0;
1286 for (i = 0; i < 4; i++) {
1287 if (!pos_args[i][0])
1288 continue;
1289
1290 /* Specify the target we are exporting */
1291 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1292
1293 if (pos_idx == shader->nr_pos_exports)
1294 /* Specify that this is the last export */
1295 pos_args[i][2] = uint->one;
1296
1297 lp_build_intrinsic(base->gallivm->builder,
1298 "llvm.SI.export",
1299 LLVMVoidTypeInContext(base->gallivm->context),
1300 pos_args[i], 9);
1301 }
1302 }
1303
1304 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1305 {
1306 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1307 struct gallivm_state *gallivm = bld_base->base.gallivm;
1308 struct si_shader *es = si_shader_ctx->shader;
1309 struct tgsi_shader_info *info = &es->selector->info;
1310 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1311 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1312 SI_PARAM_ES2GS_OFFSET);
1313 unsigned chan;
1314 int i;
1315
1316 for (i = 0; i < info->num_outputs; i++) {
1317 LLVMValueRef *out_ptr =
1318 si_shader_ctx->radeon_bld.soa.outputs[i];
1319 int param_index;
1320
1321 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1322 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1323 continue;
1324
1325 param_index = get_param_index(info->output_semantic_name[i],
1326 info->output_semantic_index[i],
1327 es->key.vs.gs_used_inputs);
1328 if (param_index < 0)
1329 continue;
1330
1331 for (chan = 0; chan < 4; chan++) {
1332 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1333 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1334
1335 build_tbuffer_store(si_shader_ctx,
1336 si_shader_ctx->esgs_ring,
1337 out_val, 1,
1338 LLVMGetUndef(i32), soffset,
1339 (4 * param_index + chan) * 4,
1340 V_008F0C_BUF_DATA_FORMAT_32,
1341 V_008F0C_BUF_NUM_FORMAT_UINT,
1342 0, 0, 1, 1, 0);
1343 }
1344 }
1345 }
1346
1347 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1348 {
1349 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1350 struct gallivm_state *gallivm = bld_base->base.gallivm;
1351 LLVMValueRef args[2];
1352
1353 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1354 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1355 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1356 LLVMVoidTypeInContext(gallivm->context), args, 2,
1357 LLVMNoUnwindAttribute);
1358 }
1359
1360 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1361 {
1362 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1363 struct gallivm_state *gallivm = bld_base->base.gallivm;
1364 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1365 struct si_shader_output_values *outputs = NULL;
1366 int i,j;
1367
1368 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1369
1370 for (i = 0; i < info->num_outputs; i++) {
1371 outputs[i].name = info->output_semantic_name[i];
1372 outputs[i].sid = info->output_semantic_index[i];
1373
1374 for (j = 0; j < 4; j++)
1375 outputs[i].values[j] =
1376 LLVMBuildLoad(gallivm->builder,
1377 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1378 "");
1379 }
1380
1381 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1382 FREE(outputs);
1383 }
1384
1385 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1386 {
1387 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1388 struct si_shader * shader = si_shader_ctx->shader;
1389 struct lp_build_context * base = &bld_base->base;
1390 struct lp_build_context * uint = &bld_base->uint_bld;
1391 struct tgsi_shader_info *info = &shader->selector->info;
1392 LLVMValueRef args[9];
1393 LLVMValueRef last_args[9] = { 0 };
1394 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1395 int i;
1396
1397 for (i = 0; i < info->num_outputs; i++) {
1398 unsigned semantic_name = info->output_semantic_name[i];
1399 unsigned semantic_index = info->output_semantic_index[i];
1400 unsigned target;
1401 LLVMValueRef alpha_ptr;
1402
1403 /* Select the correct target */
1404 switch (semantic_name) {
1405 case TGSI_SEMANTIC_POSITION:
1406 depth_index = i;
1407 continue;
1408 case TGSI_SEMANTIC_STENCIL:
1409 stencil_index = i;
1410 continue;
1411 case TGSI_SEMANTIC_SAMPLEMASK:
1412 samplemask_index = i;
1413 continue;
1414 case TGSI_SEMANTIC_COLOR:
1415 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1416 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
1417
1418 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1419 LLVMBuildStore(base->gallivm->builder,
1420 base->one, alpha_ptr);
1421
1422 if (semantic_index == 0 &&
1423 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1424 si_alpha_test(bld_base, alpha_ptr);
1425
1426 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1427 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
1428 break;
1429 default:
1430 target = 0;
1431 fprintf(stderr,
1432 "Warning: SI unhandled fs output type:%d\n",
1433 semantic_name);
1434 }
1435
1436 si_llvm_init_export_args_load(bld_base,
1437 si_shader_ctx->radeon_bld.soa.outputs[i],
1438 target, args);
1439
1440 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1441 /* If there is an export instruction waiting to be emitted, do so now. */
1442 if (last_args[0]) {
1443 lp_build_intrinsic(base->gallivm->builder,
1444 "llvm.SI.export",
1445 LLVMVoidTypeInContext(base->gallivm->context),
1446 last_args, 9);
1447 }
1448
1449 /* This instruction will be emitted at the end of the shader. */
1450 memcpy(last_args, args, sizeof(args));
1451
1452 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1453 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1454 semantic_index == 0 &&
1455 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1456 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1457 si_llvm_init_export_args_load(bld_base,
1458 si_shader_ctx->radeon_bld.soa.outputs[i],
1459 V_008DFC_SQ_EXP_MRT + c, args);
1460 lp_build_intrinsic(base->gallivm->builder,
1461 "llvm.SI.export",
1462 LLVMVoidTypeInContext(base->gallivm->context),
1463 args, 9);
1464 }
1465 }
1466 } else {
1467 lp_build_intrinsic(base->gallivm->builder,
1468 "llvm.SI.export",
1469 LLVMVoidTypeInContext(base->gallivm->context),
1470 args, 9);
1471 }
1472 }
1473
1474 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1475 LLVMValueRef out_ptr;
1476 unsigned mask = 0;
1477
1478 /* Specify the target we are exporting */
1479 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1480
1481 args[5] = base->zero; /* R, depth */
1482 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1483 args[7] = base->zero; /* B, sample mask */
1484 args[8] = base->zero; /* A, alpha to mask */
1485
1486 if (depth_index >= 0) {
1487 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1488 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1489 mask |= 0x1;
1490 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1491 }
1492
1493 if (stencil_index >= 0) {
1494 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1495 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1496 mask |= 0x2;
1497 si_shader_ctx->shader->db_shader_control |=
1498 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1499 }
1500
1501 if (samplemask_index >= 0) {
1502 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1503 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1504 mask |= 0x4;
1505 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1506 }
1507
1508 /* SI (except OLAND) has a bug that it only looks
1509 * at the X writemask component. */
1510 if (si_shader_ctx->screen->b.chip_class == SI &&
1511 si_shader_ctx->screen->b.family != CHIP_OLAND)
1512 mask |= 0x1;
1513
1514 if (samplemask_index >= 0)
1515 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1516 else if (stencil_index >= 0)
1517 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1518 else
1519 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1520
1521 /* Specify which components to enable */
1522 args[0] = lp_build_const_int32(base->gallivm, mask);
1523
1524 args[1] =
1525 args[2] =
1526 args[4] = uint->zero;
1527
1528 if (last_args[0])
1529 lp_build_intrinsic(base->gallivm->builder,
1530 "llvm.SI.export",
1531 LLVMVoidTypeInContext(base->gallivm->context),
1532 args, 9);
1533 else
1534 memcpy(last_args, args, sizeof(args));
1535 }
1536
1537 if (!last_args[0]) {
1538 /* Specify which components to enable */
1539 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1540
1541 /* Specify the target we are exporting */
1542 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1543
1544 /* Set COMPR flag to zero to export data as 32-bit */
1545 last_args[4] = uint->zero;
1546
1547 /* dummy bits */
1548 last_args[5]= uint->zero;
1549 last_args[6]= uint->zero;
1550 last_args[7]= uint->zero;
1551 last_args[8]= uint->zero;
1552 }
1553
1554 /* Specify whether the EXEC mask represents the valid mask */
1555 last_args[1] = uint->one;
1556
1557 /* Specify that this is the last export */
1558 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1559
1560 lp_build_intrinsic(base->gallivm->builder,
1561 "llvm.SI.export",
1562 LLVMVoidTypeInContext(base->gallivm->context),
1563 last_args, 9);
1564 }
1565
1566 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1567 struct lp_build_tgsi_context * bld_base,
1568 struct lp_build_emit_data * emit_data);
1569
1570 static bool tgsi_is_shadow_sampler(unsigned target)
1571 {
1572 return target == TGSI_TEXTURE_SHADOW1D ||
1573 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1574 target == TGSI_TEXTURE_SHADOW2D ||
1575 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1576 target == TGSI_TEXTURE_SHADOWCUBE ||
1577 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1578 target == TGSI_TEXTURE_SHADOWRECT;
1579 }
1580
1581 static const struct lp_build_tgsi_action tex_action;
1582
1583 static void tex_fetch_args(
1584 struct lp_build_tgsi_context * bld_base,
1585 struct lp_build_emit_data * emit_data)
1586 {
1587 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1588 struct gallivm_state *gallivm = bld_base->base.gallivm;
1589 const struct tgsi_full_instruction * inst = emit_data->inst;
1590 unsigned opcode = inst->Instruction.Opcode;
1591 unsigned target = inst->Texture.Texture;
1592 LLVMValueRef coords[5];
1593 LLVMValueRef address[16];
1594 int ref_pos;
1595 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1596 unsigned count = 0;
1597 unsigned chan;
1598 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1599 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1600 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1601
1602 if (target == TGSI_TEXTURE_BUFFER) {
1603 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1604 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1605 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1606 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1607
1608 /* Bitcast and truncate v8i32 to v16i8. */
1609 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1610 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1611 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
1612 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1613
1614 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1615 emit_data->args[0] = res;
1616 emit_data->args[1] = bld_base->uint_bld.zero;
1617 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1618 emit_data->arg_count = 3;
1619 return;
1620 }
1621
1622 /* Fetch and project texture coordinates */
1623 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1624 for (chan = 0; chan < 3; chan++ ) {
1625 coords[chan] = lp_build_emit_fetch(bld_base,
1626 emit_data->inst, 0,
1627 chan);
1628 if (opcode == TGSI_OPCODE_TXP)
1629 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1630 TGSI_OPCODE_DIV,
1631 coords[chan],
1632 coords[3]);
1633 }
1634
1635 if (opcode == TGSI_OPCODE_TXP)
1636 coords[3] = bld_base->base.one;
1637
1638 /* Pack offsets. */
1639 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1640 /* The offsets are six-bit signed integers packed like this:
1641 * X=[5:0], Y=[13:8], and Z=[21:16].
1642 */
1643 LLVMValueRef offset[3], pack;
1644
1645 assert(inst->Texture.NumOffsets == 1);
1646
1647 for (chan = 0; chan < 3; chan++) {
1648 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1649 emit_data->inst, 0, chan);
1650 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1651 lp_build_const_int32(gallivm, 0x3f), "");
1652 if (chan)
1653 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1654 lp_build_const_int32(gallivm, chan*8), "");
1655 }
1656
1657 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1658 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1659 address[count++] = pack;
1660 }
1661
1662 /* Pack LOD bias value */
1663 if (opcode == TGSI_OPCODE_TXB)
1664 address[count++] = coords[3];
1665 if (opcode == TGSI_OPCODE_TXB2)
1666 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1667
1668 /* Pack depth comparison value */
1669 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1670 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1671 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1672 } else {
1673 assert(ref_pos >= 0);
1674 address[count++] = coords[ref_pos];
1675 }
1676 }
1677
1678 if (target == TGSI_TEXTURE_CUBE ||
1679 target == TGSI_TEXTURE_CUBE_ARRAY ||
1680 target == TGSI_TEXTURE_SHADOWCUBE ||
1681 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1682 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1683
1684 /* Pack user derivatives */
1685 if (opcode == TGSI_OPCODE_TXD) {
1686 int num_deriv_channels, param;
1687
1688 switch (target) {
1689 case TGSI_TEXTURE_3D:
1690 num_deriv_channels = 3;
1691 break;
1692 case TGSI_TEXTURE_2D:
1693 case TGSI_TEXTURE_SHADOW2D:
1694 case TGSI_TEXTURE_RECT:
1695 case TGSI_TEXTURE_SHADOWRECT:
1696 case TGSI_TEXTURE_2D_ARRAY:
1697 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1698 case TGSI_TEXTURE_CUBE:
1699 case TGSI_TEXTURE_SHADOWCUBE:
1700 case TGSI_TEXTURE_CUBE_ARRAY:
1701 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1702 num_deriv_channels = 2;
1703 break;
1704 case TGSI_TEXTURE_1D:
1705 case TGSI_TEXTURE_SHADOW1D:
1706 case TGSI_TEXTURE_1D_ARRAY:
1707 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1708 num_deriv_channels = 1;
1709 break;
1710 default:
1711 assert(0); /* no other targets are valid here */
1712 }
1713
1714 for (param = 1; param <= 2; param++)
1715 for (chan = 0; chan < num_deriv_channels; chan++)
1716 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1717 }
1718
1719 /* Pack texture coordinates */
1720 address[count++] = coords[0];
1721 if (num_coords > 1)
1722 address[count++] = coords[1];
1723 if (num_coords > 2)
1724 address[count++] = coords[2];
1725
1726 /* Pack LOD or sample index */
1727 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1728 address[count++] = coords[3];
1729 else if (opcode == TGSI_OPCODE_TXL2)
1730 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1731
1732 if (count > 16) {
1733 assert(!"Cannot handle more than 16 texture address parameters");
1734 count = 16;
1735 }
1736
1737 for (chan = 0; chan < count; chan++ ) {
1738 address[chan] = LLVMBuildBitCast(gallivm->builder,
1739 address[chan],
1740 LLVMInt32TypeInContext(gallivm->context),
1741 "");
1742 }
1743
1744 /* Adjust the sample index according to FMASK.
1745 *
1746 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1747 * which is the identity mapping. Each nibble says which physical sample
1748 * should be fetched to get that sample.
1749 *
1750 * For example, 0x11111100 means there are only 2 samples stored and
1751 * the second sample covers 3/4 of the pixel. When reading samples 0
1752 * and 1, return physical sample 0 (determined by the first two 0s
1753 * in FMASK), otherwise return physical sample 1.
1754 *
1755 * The sample index should be adjusted as follows:
1756 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1757 */
1758 if (target == TGSI_TEXTURE_2D_MSAA ||
1759 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1760 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1761 struct lp_build_emit_data txf_emit_data = *emit_data;
1762 LLVMValueRef txf_address[4];
1763 unsigned txf_count = count;
1764 struct tgsi_full_instruction inst = {};
1765
1766 memcpy(txf_address, address, sizeof(txf_address));
1767
1768 if (target == TGSI_TEXTURE_2D_MSAA) {
1769 txf_address[2] = bld_base->uint_bld.zero;
1770 }
1771 txf_address[3] = bld_base->uint_bld.zero;
1772
1773 /* Pad to a power-of-two size. */
1774 while (txf_count < util_next_power_of_two(txf_count))
1775 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1776
1777 /* Read FMASK using TXF. */
1778 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1779 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1780 txf_emit_data.inst = &inst;
1781 txf_emit_data.chan = 0;
1782 txf_emit_data.dst_type = LLVMVectorType(
1783 LLVMInt32TypeInContext(gallivm->context), 4);
1784 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1785 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1786 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1787 txf_emit_data.arg_count = 3;
1788
1789 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1790
1791 /* Initialize some constants. */
1792 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1793 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1794
1795 /* Apply the formula. */
1796 LLVMValueRef fmask =
1797 LLVMBuildExtractElement(gallivm->builder,
1798 txf_emit_data.output[0],
1799 uint_bld->zero, "");
1800
1801 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1802
1803 LLVMValueRef sample_index4 =
1804 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1805
1806 LLVMValueRef shifted_fmask =
1807 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1808
1809 LLVMValueRef final_sample =
1810 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1811
1812 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1813 * resource descriptor is 0 (invalid),
1814 */
1815 LLVMValueRef fmask_desc =
1816 LLVMBuildBitCast(gallivm->builder,
1817 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1818 LLVMVectorType(uint_bld->elem_type, 8), "");
1819
1820 LLVMValueRef fmask_word1 =
1821 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1822 uint_bld->one, "");
1823
1824 LLVMValueRef word1_is_nonzero =
1825 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1826 fmask_word1, uint_bld->zero, "");
1827
1828 /* Replace the MSAA sample index. */
1829 address[sample_chan] =
1830 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1831 final_sample, address[sample_chan], "");
1832 }
1833
1834 /* Resource */
1835 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1836
1837 if (opcode == TGSI_OPCODE_TXF) {
1838 /* add tex offsets */
1839 if (inst->Texture.NumOffsets) {
1840 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1841 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1842 const struct tgsi_texture_offset * off = inst->TexOffsets;
1843
1844 assert(inst->Texture.NumOffsets == 1);
1845
1846 switch (target) {
1847 case TGSI_TEXTURE_3D:
1848 address[2] = lp_build_add(uint_bld, address[2],
1849 bld->immediates[off->Index][off->SwizzleZ]);
1850 /* fall through */
1851 case TGSI_TEXTURE_2D:
1852 case TGSI_TEXTURE_SHADOW2D:
1853 case TGSI_TEXTURE_RECT:
1854 case TGSI_TEXTURE_SHADOWRECT:
1855 case TGSI_TEXTURE_2D_ARRAY:
1856 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1857 address[1] =
1858 lp_build_add(uint_bld, address[1],
1859 bld->immediates[off->Index][off->SwizzleY]);
1860 /* fall through */
1861 case TGSI_TEXTURE_1D:
1862 case TGSI_TEXTURE_SHADOW1D:
1863 case TGSI_TEXTURE_1D_ARRAY:
1864 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1865 address[0] =
1866 lp_build_add(uint_bld, address[0],
1867 bld->immediates[off->Index][off->SwizzleX]);
1868 break;
1869 /* texture offsets do not apply to other texture targets */
1870 }
1871 }
1872
1873 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1874 emit_data->arg_count = 3;
1875
1876 emit_data->dst_type = LLVMVectorType(
1877 LLVMInt32TypeInContext(gallivm->context),
1878 4);
1879 } else if (opcode == TGSI_OPCODE_TG4 ||
1880 opcode == TGSI_OPCODE_LODQ ||
1881 has_offset) {
1882 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1883 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1884 target == TGSI_TEXTURE_2D_ARRAY ||
1885 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1886 target == TGSI_TEXTURE_CUBE_ARRAY ||
1887 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1888 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1889 unsigned dmask = 0xf;
1890
1891 if (opcode == TGSI_OPCODE_TG4) {
1892 unsigned gather_comp = 0;
1893
1894 /* DMASK was repurposed for GATHER4. 4 components are always
1895 * returned and DMASK works like a swizzle - it selects
1896 * the component to fetch. The only valid DMASK values are
1897 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1898 * (red,red,red,red) etc.) The ISA document doesn't mention
1899 * this.
1900 */
1901
1902 /* Get the component index from src1.x for Gather4. */
1903 if (!tgsi_is_shadow_sampler(target)) {
1904 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1905 LLVMValueRef comp_imm;
1906 struct tgsi_src_register src1 = inst->Src[1].Register;
1907
1908 assert(src1.File == TGSI_FILE_IMMEDIATE);
1909
1910 comp_imm = imms[src1.Index][src1.SwizzleX];
1911 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1912 gather_comp = CLAMP(gather_comp, 0, 3);
1913 }
1914
1915 dmask = 1 << gather_comp;
1916 }
1917
1918 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1919 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1920 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1921 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1922 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1923 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1924 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1925 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1926 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1927
1928 emit_data->arg_count = 11;
1929
1930 emit_data->dst_type = LLVMVectorType(
1931 LLVMFloatTypeInContext(gallivm->context),
1932 4);
1933 } else {
1934 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1935 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1936 emit_data->arg_count = 4;
1937
1938 emit_data->dst_type = LLVMVectorType(
1939 LLVMFloatTypeInContext(gallivm->context),
1940 4);
1941 }
1942
1943 /* The fetch opcode has been converted to a 2D array fetch.
1944 * This simplifies the LLVM backend. */
1945 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1946 target = TGSI_TEXTURE_2D_ARRAY;
1947 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1948 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1949
1950 /* Pad to power of two vector */
1951 while (count < util_next_power_of_two(count))
1952 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1953
1954 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1955 }
1956
1957 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1958 struct lp_build_tgsi_context * bld_base,
1959 struct lp_build_emit_data * emit_data)
1960 {
1961 struct lp_build_context * base = &bld_base->base;
1962 unsigned opcode = emit_data->inst->Instruction.Opcode;
1963 unsigned target = emit_data->inst->Texture.Texture;
1964 char intr_name[127];
1965 bool has_offset = HAVE_LLVM >= 0x0305 ?
1966 emit_data->inst->Texture.NumOffsets > 0 : false;
1967
1968 if (target == TGSI_TEXTURE_BUFFER) {
1969 emit_data->output[emit_data->chan] = build_intrinsic(
1970 base->gallivm->builder,
1971 "llvm.SI.vs.load.input", emit_data->dst_type,
1972 emit_data->args, emit_data->arg_count,
1973 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1974 return;
1975 }
1976
1977 if (opcode == TGSI_OPCODE_TG4 ||
1978 opcode == TGSI_OPCODE_LODQ ||
1979 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1980 bool is_shadow = tgsi_is_shadow_sampler(target);
1981 const char *name = "llvm.SI.image.sample";
1982 const char *infix = "";
1983
1984 switch (opcode) {
1985 case TGSI_OPCODE_TEX:
1986 case TGSI_OPCODE_TEX2:
1987 case TGSI_OPCODE_TXP:
1988 break;
1989 case TGSI_OPCODE_TXB:
1990 case TGSI_OPCODE_TXB2:
1991 infix = ".b";
1992 break;
1993 case TGSI_OPCODE_TXL:
1994 case TGSI_OPCODE_TXL2:
1995 infix = ".l";
1996 break;
1997 case TGSI_OPCODE_TXD:
1998 infix = ".d";
1999 break;
2000 case TGSI_OPCODE_TG4:
2001 name = "llvm.SI.gather4";
2002 break;
2003 case TGSI_OPCODE_LODQ:
2004 name = "llvm.SI.getlod";
2005 is_shadow = false;
2006 has_offset = false;
2007 break;
2008 default:
2009 assert(0);
2010 return;
2011 }
2012
2013 /* Add the type and suffixes .c, .o if needed. */
2014 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
2015 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
2016 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2017
2018 emit_data->output[emit_data->chan] = build_intrinsic(
2019 base->gallivm->builder, intr_name, emit_data->dst_type,
2020 emit_data->args, emit_data->arg_count,
2021 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2022 } else {
2023 LLVMTypeRef i8, v16i8, v32i8;
2024 const char *name;
2025
2026 switch (opcode) {
2027 case TGSI_OPCODE_TEX:
2028 case TGSI_OPCODE_TEX2:
2029 case TGSI_OPCODE_TXP:
2030 name = "llvm.SI.sample";
2031 break;
2032 case TGSI_OPCODE_TXB:
2033 case TGSI_OPCODE_TXB2:
2034 name = "llvm.SI.sampleb";
2035 break;
2036 case TGSI_OPCODE_TXD:
2037 name = "llvm.SI.sampled";
2038 break;
2039 case TGSI_OPCODE_TXF:
2040 name = "llvm.SI.imageload";
2041 break;
2042 case TGSI_OPCODE_TXL:
2043 case TGSI_OPCODE_TXL2:
2044 name = "llvm.SI.samplel";
2045 break;
2046 default:
2047 assert(0);
2048 return;
2049 }
2050
2051 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2052 v16i8 = LLVMVectorType(i8, 16);
2053 v32i8 = LLVMVectorType(i8, 32);
2054
2055 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2056 emit_data->args[1], v32i8, "");
2057 if (opcode != TGSI_OPCODE_TXF) {
2058 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2059 emit_data->args[2], v16i8, "");
2060 }
2061
2062 sprintf(intr_name, "%s.v%ui32", name,
2063 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2064
2065 emit_data->output[emit_data->chan] = build_intrinsic(
2066 base->gallivm->builder, intr_name, emit_data->dst_type,
2067 emit_data->args, emit_data->arg_count,
2068 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2069 }
2070 }
2071
2072 static void txq_fetch_args(
2073 struct lp_build_tgsi_context * bld_base,
2074 struct lp_build_emit_data * emit_data)
2075 {
2076 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2077 const struct tgsi_full_instruction *inst = emit_data->inst;
2078 struct gallivm_state *gallivm = bld_base->base.gallivm;
2079 unsigned target = inst->Texture.Texture;
2080
2081 if (target == TGSI_TEXTURE_BUFFER) {
2082 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2083 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2084
2085 /* Read the size from the buffer descriptor directly. */
2086 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2087 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2088 size = LLVMBuildExtractElement(gallivm->builder, size,
2089 lp_build_const_int32(gallivm, 6), "");
2090 emit_data->args[0] = size;
2091 return;
2092 }
2093
2094 /* Mip level */
2095 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2096
2097 /* Resource */
2098 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2099
2100 /* Texture target */
2101 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2102 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2103 target = TGSI_TEXTURE_2D_ARRAY;
2104
2105 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2106 target);
2107
2108 emit_data->arg_count = 3;
2109
2110 emit_data->dst_type = LLVMVectorType(
2111 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2112 4);
2113 }
2114
2115 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2116 struct lp_build_tgsi_context * bld_base,
2117 struct lp_build_emit_data * emit_data)
2118 {
2119 unsigned target = emit_data->inst->Texture.Texture;
2120
2121 if (target == TGSI_TEXTURE_BUFFER) {
2122 /* Just return the buffer size. */
2123 emit_data->output[emit_data->chan] = emit_data->args[0];
2124 return;
2125 }
2126
2127 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2128
2129 /* Divide the number of layers by 6 to get the number of cubes. */
2130 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2131 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2132 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2133 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2134 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2135
2136 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2137 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2138 z = LLVMBuildSDiv(builder, z, six, "");
2139
2140 emit_data->output[emit_data->chan] =
2141 LLVMBuildInsertElement(builder, v4, z, two, "");
2142 }
2143 }
2144
2145 static void si_llvm_emit_ddxy(
2146 const struct lp_build_tgsi_action * action,
2147 struct lp_build_tgsi_context * bld_base,
2148 struct lp_build_emit_data * emit_data)
2149 {
2150 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2151 struct gallivm_state *gallivm = bld_base->base.gallivm;
2152 struct lp_build_context * base = &bld_base->base;
2153 const struct tgsi_full_instruction *inst = emit_data->inst;
2154 unsigned opcode = inst->Instruction.Opcode;
2155 LLVMValueRef indices[2];
2156 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2157 LLVMValueRef tl, trbl, result[4];
2158 LLVMTypeRef i32;
2159 unsigned swizzle[4];
2160 unsigned c;
2161
2162 i32 = LLVMInt32TypeInContext(gallivm->context);
2163
2164 indices[0] = bld_base->uint_bld.zero;
2165 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2166 NULL, 0, LLVMReadNoneAttribute);
2167 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2168 indices, 2, "");
2169
2170 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2171 lp_build_const_int32(gallivm, 0xfffffffc), "");
2172 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2173 indices, 2, "");
2174
2175 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2176 lp_build_const_int32(gallivm,
2177 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2178 "");
2179 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2180 indices, 2, "");
2181
2182 for (c = 0; c < 4; ++c) {
2183 unsigned i;
2184
2185 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2186 for (i = 0; i < c; ++i) {
2187 if (swizzle[i] == swizzle[c]) {
2188 result[c] = result[i];
2189 break;
2190 }
2191 }
2192 if (i != c)
2193 continue;
2194
2195 LLVMBuildStore(gallivm->builder,
2196 LLVMBuildBitCast(gallivm->builder,
2197 lp_build_emit_fetch(bld_base, inst, 0, c),
2198 i32, ""),
2199 store_ptr);
2200
2201 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2202 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2203
2204 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2205 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2206
2207 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2208 }
2209
2210 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2211 }
2212
2213 /* Emit one vertex from the geometry shader */
2214 static void si_llvm_emit_vertex(
2215 const struct lp_build_tgsi_action *action,
2216 struct lp_build_tgsi_context *bld_base,
2217 struct lp_build_emit_data *emit_data)
2218 {
2219 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2220 struct lp_build_context *uint = &bld_base->uint_bld;
2221 struct si_shader *shader = si_shader_ctx->shader;
2222 struct tgsi_shader_info *info = &shader->selector->info;
2223 struct gallivm_state *gallivm = bld_base->base.gallivm;
2224 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2225 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2226 SI_PARAM_GS2VS_OFFSET);
2227 LLVMValueRef gs_next_vertex;
2228 LLVMValueRef can_emit, kill;
2229 LLVMValueRef args[2];
2230 unsigned chan;
2231 int i;
2232
2233 /* Write vertex attribute values to GSVS ring */
2234 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2235
2236 /* If this thread has already emitted the declared maximum number of
2237 * vertices, kill it: excessive vertex emissions are not supposed to
2238 * have any effect, and GS threads have no externally observable
2239 * effects other than emitting vertices.
2240 */
2241 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2242 lp_build_const_int32(gallivm,
2243 shader->selector->gs_max_out_vertices), "");
2244 kill = lp_build_select(&bld_base->base, can_emit,
2245 lp_build_const_float(gallivm, 1.0f),
2246 lp_build_const_float(gallivm, -1.0f));
2247 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2248 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2249
2250 for (i = 0; i < info->num_outputs; i++) {
2251 LLVMValueRef *out_ptr =
2252 si_shader_ctx->radeon_bld.soa.outputs[i];
2253
2254 for (chan = 0; chan < 4; chan++) {
2255 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2256 LLVMValueRef voffset =
2257 lp_build_const_int32(gallivm, (i * 4 + chan) *
2258 shader->selector->gs_max_out_vertices);
2259
2260 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2261 voffset = lp_build_mul_imm(uint, voffset, 4);
2262
2263 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2264
2265 build_tbuffer_store(si_shader_ctx,
2266 si_shader_ctx->gsvs_ring,
2267 out_val, 1,
2268 voffset, soffset, 0,
2269 V_008F0C_BUF_DATA_FORMAT_32,
2270 V_008F0C_BUF_NUM_FORMAT_UINT,
2271 1, 0, 1, 1, 0);
2272 }
2273 }
2274 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2275 lp_build_const_int32(gallivm, 1));
2276 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2277
2278 /* Signal vertex emission */
2279 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2280 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2281 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2282 LLVMVoidTypeInContext(gallivm->context), args, 2,
2283 LLVMNoUnwindAttribute);
2284 }
2285
2286 /* Cut one primitive from the geometry shader */
2287 static void si_llvm_emit_primitive(
2288 const struct lp_build_tgsi_action *action,
2289 struct lp_build_tgsi_context *bld_base,
2290 struct lp_build_emit_data *emit_data)
2291 {
2292 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2293 struct gallivm_state *gallivm = bld_base->base.gallivm;
2294 LLVMValueRef args[2];
2295
2296 /* Signal primitive cut */
2297 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2298 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2299 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2300 LLVMVoidTypeInContext(gallivm->context), args, 2,
2301 LLVMNoUnwindAttribute);
2302 }
2303
2304 static const struct lp_build_tgsi_action tex_action = {
2305 .fetch_args = tex_fetch_args,
2306 .emit = build_tex_intrinsic,
2307 };
2308
2309 static const struct lp_build_tgsi_action txq_action = {
2310 .fetch_args = txq_fetch_args,
2311 .emit = build_txq_intrinsic,
2312 .intr_name = "llvm.SI.resinfo"
2313 };
2314
2315 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2316 {
2317 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2318 LLVMValueRef args[3];
2319
2320 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2321 args[1] = 0;
2322 args[2] = lp_build_const_int32(gallivm, 1);
2323
2324 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2325 }
2326
2327 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2328 {
2329 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2330 CONST_ADDR_SPACE);
2331 }
2332
2333 static void create_function(struct si_shader_context *si_shader_ctx)
2334 {
2335 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2336 struct gallivm_state *gallivm = bld_base->base.gallivm;
2337 struct si_shader *shader = si_shader_ctx->shader;
2338 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2339 unsigned i, last_array_pointer, last_sgpr, num_params;
2340
2341 i8 = LLVMInt8TypeInContext(gallivm->context);
2342 i32 = LLVMInt32TypeInContext(gallivm->context);
2343 f32 = LLVMFloatTypeInContext(gallivm->context);
2344 v2i32 = LLVMVectorType(i32, 2);
2345 v3i32 = LLVMVectorType(i32, 3);
2346 v4i32 = LLVMVectorType(i32, 4);
2347 v8i32 = LLVMVectorType(i32, 8);
2348 v16i8 = LLVMVectorType(i8, 16);
2349
2350 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2351 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2352 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2353 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2354 last_array_pointer = SI_PARAM_RESOURCE;
2355
2356 switch (si_shader_ctx->type) {
2357 case TGSI_PROCESSOR_VERTEX:
2358 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2359 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2360 params[SI_PARAM_BASE_VERTEX] = i32;
2361 params[SI_PARAM_START_INSTANCE] = i32;
2362 num_params = SI_PARAM_START_INSTANCE+1;
2363
2364 if (shader->key.vs.as_es) {
2365 params[SI_PARAM_ES2GS_OFFSET] = i32;
2366 num_params++;
2367 } else {
2368 if (shader->is_gs_copy_shader) {
2369 last_array_pointer = SI_PARAM_CONST;
2370 num_params = SI_PARAM_CONST+1;
2371 }
2372
2373 /* The locations of the other parameters are assigned dynamically. */
2374
2375 /* Streamout SGPRs. */
2376 if (shader->selector->so.num_outputs) {
2377 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2378 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2379 }
2380 /* A streamout buffer offset is loaded if the stride is non-zero. */
2381 for (i = 0; i < 4; i++) {
2382 if (!shader->selector->so.stride[i])
2383 continue;
2384
2385 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2386 }
2387 }
2388
2389 last_sgpr = num_params-1;
2390
2391 /* VGPRs */
2392 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2393 params[num_params++] = i32; /* unused*/
2394 params[num_params++] = i32; /* unused */
2395 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2396 break;
2397
2398 case TGSI_PROCESSOR_GEOMETRY:
2399 params[SI_PARAM_GS2VS_OFFSET] = i32;
2400 params[SI_PARAM_GS_WAVE_ID] = i32;
2401 last_sgpr = SI_PARAM_GS_WAVE_ID;
2402
2403 /* VGPRs */
2404 params[SI_PARAM_VTX0_OFFSET] = i32;
2405 params[SI_PARAM_VTX1_OFFSET] = i32;
2406 params[SI_PARAM_PRIMITIVE_ID] = i32;
2407 params[SI_PARAM_VTX2_OFFSET] = i32;
2408 params[SI_PARAM_VTX3_OFFSET] = i32;
2409 params[SI_PARAM_VTX4_OFFSET] = i32;
2410 params[SI_PARAM_VTX5_OFFSET] = i32;
2411 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2412 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2413 break;
2414
2415 case TGSI_PROCESSOR_FRAGMENT:
2416 params[SI_PARAM_ALPHA_REF] = f32;
2417 params[SI_PARAM_PRIM_MASK] = i32;
2418 last_sgpr = SI_PARAM_PRIM_MASK;
2419 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2420 params[SI_PARAM_PERSP_CENTER] = v2i32;
2421 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2422 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2423 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2424 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2425 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2426 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2427 params[SI_PARAM_POS_X_FLOAT] = f32;
2428 params[SI_PARAM_POS_Y_FLOAT] = f32;
2429 params[SI_PARAM_POS_Z_FLOAT] = f32;
2430 params[SI_PARAM_POS_W_FLOAT] = f32;
2431 params[SI_PARAM_FRONT_FACE] = f32;
2432 params[SI_PARAM_ANCILLARY] = i32;
2433 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2434 params[SI_PARAM_POS_FIXED_PT] = f32;
2435 num_params = SI_PARAM_POS_FIXED_PT+1;
2436 break;
2437
2438 default:
2439 assert(0 && "unimplemented shader");
2440 return;
2441 }
2442
2443 assert(num_params <= Elements(params));
2444 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2445 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2446
2447 if (shader->dx10_clamp_mode)
2448 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
2449 "enable-no-nans-fp-math", "true");
2450
2451 for (i = 0; i <= last_sgpr; ++i) {
2452 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2453
2454 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2455 * to move load. Inputs are constant so this is fine. */
2456 if (i <= last_array_pointer)
2457 LLVMAddAttribute(P, LLVMByValAttribute);
2458 else
2459 LLVMAddAttribute(P, LLVMInRegAttribute);
2460 }
2461
2462 if (bld_base->info &&
2463 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2464 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2465 si_shader_ctx->ddxy_lds =
2466 LLVMAddGlobalInAddressSpace(gallivm->module,
2467 LLVMArrayType(i32, 64),
2468 "ddxy_lds",
2469 LOCAL_ADDR_SPACE);
2470 }
2471
2472 static void preload_constants(struct si_shader_context *si_shader_ctx)
2473 {
2474 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2475 struct gallivm_state * gallivm = bld_base->base.gallivm;
2476 const struct tgsi_shader_info * info = bld_base->info;
2477 unsigned buf;
2478 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2479
2480 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2481 unsigned i, num_const = info->const_file_max[buf] + 1;
2482
2483 if (num_const == 0)
2484 continue;
2485
2486 /* Allocate space for the constant values */
2487 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2488
2489 /* Load the resource descriptor */
2490 si_shader_ctx->const_resource[buf] =
2491 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2492
2493 /* Load the constants, we rely on the code sinking to do the rest */
2494 for (i = 0; i < num_const * 4; ++i) {
2495 si_shader_ctx->constants[buf][i] =
2496 buffer_load_const(gallivm->builder,
2497 si_shader_ctx->const_resource[buf],
2498 lp_build_const_int32(gallivm, i * 4),
2499 bld_base->base.elem_type);
2500 }
2501 }
2502 }
2503
2504 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2505 {
2506 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2507 struct gallivm_state * gallivm = bld_base->base.gallivm;
2508 const struct tgsi_shader_info * info = bld_base->info;
2509
2510 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2511
2512 LLVMValueRef res_ptr, samp_ptr;
2513 LLVMValueRef offset;
2514
2515 if (num_samplers == 0)
2516 return;
2517
2518 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2519 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2520
2521 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2522 for (i = 0; i < num_samplers; ++i) {
2523 /* Resource */
2524 offset = lp_build_const_int32(gallivm, i);
2525 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2526
2527 /* Sampler */
2528 offset = lp_build_const_int32(gallivm, i);
2529 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2530
2531 /* FMASK resource */
2532 if (info->is_msaa_sampler[i]) {
2533 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2534 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2535 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2536 }
2537 }
2538 }
2539
2540 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2541 {
2542 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2543 struct gallivm_state * gallivm = bld_base->base.gallivm;
2544 unsigned i;
2545
2546 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2547 si_shader_ctx->shader->key.vs.as_es ||
2548 !si_shader_ctx->shader->selector->so.num_outputs)
2549 return;
2550
2551 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2552 SI_PARAM_RW_BUFFERS);
2553
2554 /* Load the resources, we rely on the code sinking to do the rest */
2555 for (i = 0; i < 4; ++i) {
2556 if (si_shader_ctx->shader->selector->so.stride[i]) {
2557 LLVMValueRef offset = lp_build_const_int32(gallivm,
2558 SI_SO_BUF_OFFSET + i);
2559
2560 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2561 }
2562 }
2563 }
2564
2565 /**
2566 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2567 * for later use.
2568 */
2569 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2570 {
2571 struct gallivm_state *gallivm =
2572 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2573
2574 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2575 SI_PARAM_RW_BUFFERS);
2576
2577 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2578 si_shader_ctx->shader->key.vs.as_es) ||
2579 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2580 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2581
2582 si_shader_ctx->esgs_ring =
2583 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2584 }
2585
2586 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2587 si_shader_ctx->shader->is_gs_copy_shader) {
2588 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2589
2590 si_shader_ctx->gsvs_ring =
2591 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2592 }
2593 }
2594
2595 void si_shader_binary_read_config(const struct si_screen *sscreen,
2596 struct si_shader *shader,
2597 unsigned symbol_offset)
2598 {
2599 unsigned i;
2600 const unsigned char *config =
2601 radeon_shader_binary_config_start(&shader->binary,
2602 symbol_offset);
2603
2604 /* XXX: We may be able to emit some of these values directly rather than
2605 * extracting fields to be emitted later.
2606 */
2607
2608 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
2609 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2610 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2611 switch (reg) {
2612 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2613 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2614 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2615 case R_00B848_COMPUTE_PGM_RSRC1:
2616 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2617 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2618 shader->float_mode = G_00B028_FLOAT_MODE(value);
2619 break;
2620 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2621 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2622 break;
2623 case R_00B84C_COMPUTE_PGM_RSRC2:
2624 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2625 break;
2626 case R_0286CC_SPI_PS_INPUT_ENA:
2627 shader->spi_ps_input_ena = value;
2628 break;
2629 case R_0286E8_SPI_TMPRING_SIZE:
2630 case R_00B860_COMPUTE_TMPRING_SIZE:
2631 /* WAVESIZE is in units of 256 dwords. */
2632 shader->scratch_bytes_per_wave =
2633 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2634 break;
2635 default:
2636 fprintf(stderr, "Warning: Compiler emitted unknown "
2637 "config register: 0x%x\n", reg);
2638 break;
2639 }
2640 }
2641 }
2642
2643 void si_shader_apply_scratch_relocs(struct si_context *sctx,
2644 struct si_shader *shader,
2645 uint64_t scratch_va)
2646 {
2647 unsigned i;
2648 uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff;
2649 uint32_t scratch_rsrc_dword1 =
2650 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
2651 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
2652
2653 for (i = 0 ; i < shader->binary.reloc_count; i++) {
2654 const struct radeon_shader_reloc *reloc =
2655 &shader->binary.relocs[i];
2656 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
2657 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2658 &scratch_rsrc_dword0, 4);
2659 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
2660 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2661 &scratch_rsrc_dword1, 4);
2662 }
2663 }
2664 }
2665
2666 int si_shader_binary_read(struct si_screen *sscreen,
2667 struct si_shader *shader,
2668 const struct radeon_shader_binary *binary)
2669 {
2670
2671 unsigned i;
2672 unsigned code_size;
2673 unsigned char *ptr;
2674 bool dump = r600_can_dump_shader(&sscreen->b,
2675 shader->selector ? shader->selector->tokens : NULL);
2676
2677 si_shader_binary_read_config(sscreen, shader, 0);
2678
2679 if (dump) {
2680 if (!binary->disassembled) {
2681 fprintf(stderr, "SI CODE:\n");
2682 for (i = 0; i < binary->code_size; i+=4 ) {
2683 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2684 binary->code[i + 2], binary->code[i + 1],
2685 binary->code[i]);
2686 }
2687 }
2688
2689 fprintf(stderr, "*** SHADER STATS ***\n"
2690 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
2691 "Scratch: %d bytes per wave\n********************\n",
2692 shader->num_sgprs, shader->num_vgprs, binary->code_size,
2693 shader->lds_size, shader->scratch_bytes_per_wave);
2694 }
2695
2696 /* copy new shader */
2697 code_size = binary->code_size + binary->rodata_size;
2698 r600_resource_reference(&shader->bo, NULL);
2699 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2700 code_size);
2701 if (shader->bo == NULL) {
2702 return -ENOMEM;
2703 }
2704
2705
2706 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2707 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2708 if (binary->rodata_size > 0) {
2709 ptr += binary->code_size;
2710 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2711 }
2712
2713 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2714
2715 return 0;
2716 }
2717
2718 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2719 LLVMTargetMachineRef tm, LLVMModuleRef mod)
2720 {
2721 int r = 0;
2722 bool dump = r600_can_dump_shader(&sscreen->b,
2723 shader->selector ? shader->selector->tokens : NULL);
2724 r = radeon_llvm_compile(mod, &shader->binary,
2725 r600_get_llvm_processor_name(sscreen->b.family), dump, tm);
2726
2727 if (r) {
2728 return r;
2729 }
2730 r = si_shader_binary_read(sscreen, shader, &shader->binary);
2731
2732 FREE(shader->binary.config);
2733 FREE(shader->binary.rodata);
2734 FREE(shader->binary.global_symbol_offsets);
2735 if (shader->scratch_bytes_per_wave == 0) {
2736 FREE(shader->binary.code);
2737 FREE(shader->binary.relocs);
2738 memset(&shader->binary, 0, sizeof(shader->binary));
2739 }
2740 return r;
2741 }
2742
2743 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2744 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2745 struct si_shader_context *si_shader_ctx,
2746 struct si_shader *gs, bool dump)
2747 {
2748 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2749 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2750 struct lp_build_context *base = &bld_base->base;
2751 struct lp_build_context *uint = &bld_base->uint_bld;
2752 struct si_shader *shader = si_shader_ctx->shader;
2753 struct si_shader_output_values *outputs;
2754 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2755 LLVMValueRef args[9];
2756 int i, r;
2757
2758 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2759
2760 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2761 shader->is_gs_copy_shader = true;
2762
2763 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2764
2765 create_meta_data(si_shader_ctx);
2766 create_function(si_shader_ctx);
2767 preload_streamout_buffers(si_shader_ctx);
2768 preload_ring_buffers(si_shader_ctx);
2769
2770 args[0] = si_shader_ctx->gsvs_ring;
2771 args[1] = lp_build_mul_imm(uint,
2772 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2773 si_shader_ctx->param_vertex_id),
2774 4);
2775 args[3] = uint->zero;
2776 args[4] = uint->one; /* OFFEN */
2777 args[5] = uint->zero; /* IDXEN */
2778 args[6] = uint->one; /* GLC */
2779 args[7] = uint->one; /* SLC */
2780 args[8] = uint->zero; /* TFE */
2781
2782 /* Fetch vertex data from GSVS ring */
2783 for (i = 0; i < gsinfo->num_outputs; ++i) {
2784 unsigned chan;
2785
2786 outputs[i].name = gsinfo->output_semantic_name[i];
2787 outputs[i].sid = gsinfo->output_semantic_index[i];
2788
2789 for (chan = 0; chan < 4; chan++) {
2790 args[2] = lp_build_const_int32(gallivm,
2791 (i * 4 + chan) *
2792 gs->selector->gs_max_out_vertices * 16 * 4);
2793
2794 outputs[i].values[chan] =
2795 LLVMBuildBitCast(gallivm->builder,
2796 build_intrinsic(gallivm->builder,
2797 "llvm.SI.buffer.load.dword.i32.i32",
2798 LLVMInt32TypeInContext(gallivm->context),
2799 args, 9,
2800 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2801 base->elem_type, "");
2802 }
2803 }
2804
2805 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2806
2807 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2808
2809 if (dump)
2810 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2811
2812 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2813 si_shader_ctx->tm, bld_base->base.gallivm->module);
2814
2815 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2816
2817 FREE(outputs);
2818 return r;
2819 }
2820
2821 static void si_dump_key(unsigned shader, union si_shader_key *key)
2822 {
2823 int i;
2824
2825 fprintf(stderr, "SHADER KEY\n");
2826
2827 switch (shader) {
2828 case PIPE_SHADER_VERTEX:
2829 fprintf(stderr, " instance_divisors = {");
2830 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
2831 fprintf(stderr, !i ? "%u" : ", %u",
2832 key->vs.instance_divisors[i]);
2833 fprintf(stderr, "}\n");
2834
2835 if (key->vs.as_es)
2836 fprintf(stderr, " gs_used_inputs = 0x%"PRIx64"\n",
2837 key->vs.gs_used_inputs);
2838 fprintf(stderr, " as_es = %u\n", key->vs.as_es);
2839 break;
2840
2841 case PIPE_SHADER_GEOMETRY:
2842 break;
2843
2844 case PIPE_SHADER_FRAGMENT:
2845 fprintf(stderr, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
2846 fprintf(stderr, " last_cbuf = %u\n", key->ps.last_cbuf);
2847 fprintf(stderr, " color_two_side = %u\n", key->ps.color_two_side);
2848 fprintf(stderr, " alpha_func = %u\n", key->ps.alpha_func);
2849 fprintf(stderr, " alpha_to_one = %u\n", key->ps.alpha_to_one);
2850 fprintf(stderr, " poly_stipple = %u\n", key->ps.poly_stipple);
2851 break;
2852
2853 default:
2854 assert(0);
2855 }
2856 }
2857
2858 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
2859 struct si_shader *shader)
2860 {
2861 struct si_shader_selector *sel = shader->selector;
2862 struct tgsi_token *tokens = sel->tokens;
2863 struct si_shader_context si_shader_ctx;
2864 struct lp_build_tgsi_context * bld_base;
2865 struct tgsi_shader_info stipple_shader_info;
2866 LLVMModuleRef mod;
2867 int r = 0;
2868 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
2869 shader->key.ps.poly_stipple;
2870 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2871
2872 if (poly_stipple) {
2873 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
2874 SI_POLY_STIPPLE_SAMPLER);
2875 tgsi_scan_shader(tokens, &stipple_shader_info);
2876 }
2877
2878 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2879 * conversion fails. */
2880 if (dump) {
2881 si_dump_key(sel->type, &shader->key);
2882 tgsi_dump(tokens, 0);
2883 si_dump_streamout(&sel->so);
2884 }
2885
2886 assert(shader->nparam == 0);
2887
2888 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2889 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2890 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2891
2892 if (sel->type != PIPE_SHADER_COMPUTE)
2893 shader->dx10_clamp_mode = true;
2894
2895 if (sel->info.uses_kill)
2896 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2897
2898 shader->uses_instanceid = sel->info.uses_instanceid;
2899 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
2900 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2901
2902 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2903 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2904 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2905 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2906 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2907 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2908 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2909 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2910 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2911 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2912 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2913 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2914
2915 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2916 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2917
2918 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2919 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2920
2921 if (HAVE_LLVM >= 0x0306) {
2922 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2923 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2924 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2925 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2926 }
2927
2928 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2929 si_shader_ctx.shader = shader;
2930 si_shader_ctx.type = tgsi_get_processor_type(tokens);
2931 si_shader_ctx.screen = sscreen;
2932 si_shader_ctx.tm = tm;
2933
2934 switch (si_shader_ctx.type) {
2935 case TGSI_PROCESSOR_VERTEX:
2936 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2937 if (shader->key.vs.as_es) {
2938 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2939 } else {
2940 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2941 }
2942 break;
2943 case TGSI_PROCESSOR_GEOMETRY:
2944 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2945 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2946 break;
2947 case TGSI_PROCESSOR_FRAGMENT:
2948 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2949 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2950
2951 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2952 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2953 shader->db_shader_control |=
2954 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2955 break;
2956 case TGSI_FS_DEPTH_LAYOUT_LESS:
2957 shader->db_shader_control |=
2958 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2959 break;
2960 }
2961 break;
2962 default:
2963 assert(!"Unsupported shader type");
2964 return -1;
2965 }
2966
2967 create_meta_data(&si_shader_ctx);
2968 create_function(&si_shader_ctx);
2969 preload_constants(&si_shader_ctx);
2970 preload_samplers(&si_shader_ctx);
2971 preload_streamout_buffers(&si_shader_ctx);
2972 preload_ring_buffers(&si_shader_ctx);
2973
2974 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2975 si_shader_ctx.gs_next_vertex =
2976 lp_build_alloca(bld_base->base.gallivm,
2977 bld_base->uint_bld.elem_type, "");
2978 }
2979
2980 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
2981 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2982 goto out;
2983 }
2984
2985 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2986
2987 mod = bld_base->base.gallivm->module;
2988 r = si_compile_llvm(sscreen, shader, tm, mod);
2989 if (r) {
2990 fprintf(stderr, "LLVM failed to compile shader\n");
2991 goto out;
2992 }
2993
2994 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2995
2996 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2997 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2998 shader->gs_copy_shader->selector = shader->selector;
2999 shader->gs_copy_shader->key = shader->key;
3000 si_shader_ctx.shader = shader->gs_copy_shader;
3001 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
3002 shader, dump))) {
3003 free(shader->gs_copy_shader);
3004 shader->gs_copy_shader = NULL;
3005 goto out;
3006 }
3007 }
3008
3009 out:
3010 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
3011 FREE(si_shader_ctx.constants[i]);
3012 if (poly_stipple)
3013 tgsi_free_tokens(tokens);
3014 return r;
3015 }
3016
3017 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
3018 {
3019 if (shader->gs_copy_shader)
3020 si_shader_destroy(ctx, shader->gs_copy_shader);
3021
3022 if (shader->scratch_bo)
3023 r600_resource_reference(&shader->scratch_bo, NULL);
3024
3025 r600_resource_reference(&shader->bo, NULL);
3026
3027 FREE(shader->binary.code);
3028 FREE(shader->binary.relocs);
3029 }