projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: Add header and footer to shader stat dump
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/r600_cs.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_pstipple.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "si_shader.h"
47 #include "sid.h"
48
49 #include <errno.h>
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned name;
61 unsigned sid;
62 };
63
64 struct si_shader_context
65 {
66 struct radeon_llvm_context radeon_bld;
67 struct si_shader *shader;
68 struct si_screen *screen;
69 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
70 int param_streamout_config;
71 int param_streamout_write_index;
72 int param_streamout_offset[4];
73 int param_vertex_id;
74 int param_instance_id;
75 LLVMTargetMachineRef tm;
76 LLVMValueRef const_md;
77 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
78 LLVMValueRef ddxy_lds;
79 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
80 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
81 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
82 LLVMValueRef so_buffers[4];
83 LLVMValueRef esgs_ring;
84 LLVMValueRef gsvs_ring;
85 LLVMValueRef gs_next_vertex;
86 };
87
88 static struct si_shader_context * si_shader_context(
89 struct lp_build_tgsi_context * bld_base)
90 {
91 return (struct si_shader_context *)bld_base;
92 }
93
94
95 #define PERSPECTIVE_BASE 0
96 #define LINEAR_BASE 9
97
98 #define SAMPLE_OFFSET 0
99 #define CENTER_OFFSET 2
100 #define CENTROID_OFSET 4
101
102 #define USE_SGPR_MAX_SUFFIX_LEN 5
103 #define CONST_ADDR_SPACE 2
104 #define LOCAL_ADDR_SPACE 3
105 #define USER_SGPR_ADDR_SPACE 8
106
107
108 #define SENDMSG_GS 2
109 #define SENDMSG_GS_DONE 3
110
111 #define SENDMSG_GS_OP_NOP (0 << 4)
112 #define SENDMSG_GS_OP_CUT (1 << 4)
113 #define SENDMSG_GS_OP_EMIT (2 << 4)
114 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
115
116 /**
117 * Returns a unique index for a semantic name and index. The index must be
118 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
119 * calculated.
120 */
121 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
122 {
123 switch (semantic_name) {
124 case TGSI_SEMANTIC_POSITION:
125 return 0;
126 case TGSI_SEMANTIC_PSIZE:
127 return 1;
128 case TGSI_SEMANTIC_CLIPDIST:
129 assert(index <= 1);
130 return 2 + index;
131 case TGSI_SEMANTIC_CLIPVERTEX:
132 return 4;
133 case TGSI_SEMANTIC_COLOR:
134 assert(index <= 1);
135 return 5 + index;
136 case TGSI_SEMANTIC_BCOLOR:
137 assert(index <= 1);
138 return 7 + index;
139 case TGSI_SEMANTIC_FOG:
140 return 9;
141 case TGSI_SEMANTIC_EDGEFLAG:
142 return 10;
143 case TGSI_SEMANTIC_GENERIC:
144 assert(index <= 63-11);
145 return 11 + index;
146 default:
147 assert(0);
148 return 63;
149 }
150 }
151
152 /**
153 * Given a semantic name and index of a parameter and a mask of used parameters
154 * (inputs or outputs), return the index of the parameter in the list of all
155 * used parameters.
156 *
157 * For example, assume this list of parameters:
158 * POSITION, PSIZE, GENERIC0, GENERIC2
159 * which has the mask:
160 * 11000000000101
161 * Then:
162 * querying POSITION returns 0,
163 * querying PSIZE returns 1,
164 * querying GENERIC0 returns 2,
165 * querying GENERIC2 returns 3.
166 *
167 * Which can be used as an offset to a parameter buffer in units of vec4s.
168 */
169 static int get_param_index(unsigned semantic_name, unsigned index,
170 uint64_t mask)
171 {
172 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
173 int i, param_index = 0;
174
175 /* If not present... */
176 if (!((1llu << unique_index) & mask))
177 return -1;
178
179 for (i = 0; mask; i++) {
180 uint64_t bit = 1llu << i;
181
182 if (bit & mask) {
183 if (i == unique_index)
184 return param_index;
185
186 mask &= ~bit;
187 param_index++;
188 }
189 }
190
191 assert(!"unreachable");
192 return -1;
193 }
194
195 /**
196 * Get the value of a shader input parameter and extract a bitfield.
197 */
198 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
199 unsigned param, unsigned rshift,
200 unsigned bitwidth)
201 {
202 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
203 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
204 param);
205
206 if (rshift)
207 value = LLVMBuildLShr(gallivm->builder, value,
208 lp_build_const_int32(gallivm, rshift), "");
209
210 if (rshift + bitwidth < 32) {
211 unsigned mask = (1 << bitwidth) - 1;
212 value = LLVMBuildAnd(gallivm->builder, value,
213 lp_build_const_int32(gallivm, mask), "");
214 }
215
216 return value;
217 }
218
219 /**
220 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
221 * It's equivalent to doing a load from &base_ptr[index].
222 *
223 * \param base_ptr Where the array starts.
224 * \param index The element index into the array.
225 */
226 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
227 LLVMValueRef base_ptr, LLVMValueRef index)
228 {
229 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
230 struct gallivm_state *gallivm = bld_base->base.gallivm;
231 LLVMValueRef indices[2], pointer;
232
233 indices[0] = bld_base->uint_bld.zero;
234 indices[1] = index;
235
236 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
237 return LLVMBuildLoad(gallivm->builder, pointer, "");
238 }
239
240 /**
241 * Do a load from &base_ptr[index], but also add a flag that it's loading
242 * a constant.
243 */
244 static LLVMValueRef build_indexed_load_const(
245 struct si_shader_context * si_shader_ctx,
246 LLVMValueRef base_ptr, LLVMValueRef index)
247 {
248 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
249 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
250 return result;
251 }
252
253 static LLVMValueRef get_instance_index_for_fetch(
254 struct radeon_llvm_context * radeon_bld,
255 unsigned divisor)
256 {
257 struct si_shader_context *si_shader_ctx =
258 si_shader_context(&radeon_bld->soa.bld_base);
259 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
260
261 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
262 si_shader_ctx->param_instance_id);
263
264 /* The division must be done before START_INSTANCE is added. */
265 if (divisor > 1)
266 result = LLVMBuildUDiv(gallivm->builder, result,
267 lp_build_const_int32(gallivm, divisor), "");
268
269 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
270 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
271 }
272
273 static void declare_input_vs(
274 struct radeon_llvm_context *radeon_bld,
275 unsigned input_index,
276 const struct tgsi_full_declaration *decl)
277 {
278 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
279 struct gallivm_state *gallivm = base->gallivm;
280 struct si_shader_context *si_shader_ctx =
281 si_shader_context(&radeon_bld->soa.bld_base);
282 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
283
284 unsigned chan;
285
286 LLVMValueRef t_list_ptr;
287 LLVMValueRef t_offset;
288 LLVMValueRef t_list;
289 LLVMValueRef attribute_offset;
290 LLVMValueRef buffer_index;
291 LLVMValueRef args[3];
292 LLVMTypeRef vec4_type;
293 LLVMValueRef input;
294
295 /* Load the T list */
296 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
297
298 t_offset = lp_build_const_int32(gallivm, input_index);
299
300 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
301
302 /* Build the attribute offset */
303 attribute_offset = lp_build_const_int32(gallivm, 0);
304
305 if (divisor) {
306 /* Build index from instance ID, start instance and divisor */
307 si_shader_ctx->shader->uses_instanceid = true;
308 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
309 } else {
310 /* Load the buffer index for vertices. */
311 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
312 si_shader_ctx->param_vertex_id);
313 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
314 SI_PARAM_BASE_VERTEX);
315 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
316 }
317
318 vec4_type = LLVMVectorType(base->elem_type, 4);
319 args[0] = t_list;
320 args[1] = attribute_offset;
321 args[2] = buffer_index;
322 input = build_intrinsic(gallivm->builder,
323 "llvm.SI.vs.load.input", vec4_type, args, 3,
324 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
325
326 /* Break up the vec4 into individual components */
327 for (chan = 0; chan < 4; chan++) {
328 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
329 /* XXX: Use a helper function for this. There is one in
330 * tgsi_llvm.c. */
331 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
332 LLVMBuildExtractElement(gallivm->builder,
333 input, llvm_chan, "");
334 }
335 }
336
337 static LLVMValueRef fetch_input_gs(
338 struct lp_build_tgsi_context *bld_base,
339 const struct tgsi_full_src_register *reg,
340 enum tgsi_opcode_type type,
341 unsigned swizzle)
342 {
343 struct lp_build_context *base = &bld_base->base;
344 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
345 struct si_shader *shader = si_shader_ctx->shader;
346 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
347 struct gallivm_state *gallivm = base->gallivm;
348 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
349 LLVMValueRef vtx_offset;
350 LLVMValueRef args[9];
351 unsigned vtx_offset_param;
352 struct tgsi_shader_info *info = &shader->selector->info;
353 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
354 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
355
356 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
357 if (swizzle == 0)
358 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
359 SI_PARAM_PRIMITIVE_ID);
360 else
361 return uint->zero;
362 }
363
364 if (!reg->Register.Dimension)
365 return NULL;
366
367 if (swizzle == ~0) {
368 LLVMValueRef values[TGSI_NUM_CHANNELS];
369 unsigned chan;
370 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
371 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
372 }
373 return lp_build_gather_values(bld_base->base.gallivm, values,
374 TGSI_NUM_CHANNELS);
375 }
376
377 /* Get the vertex offset parameter */
378 vtx_offset_param = reg->Dimension.Index;
379 if (vtx_offset_param < 2) {
380 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
381 } else {
382 assert(vtx_offset_param < 6);
383 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
384 }
385 vtx_offset = lp_build_mul_imm(uint,
386 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
387 vtx_offset_param),
388 4);
389
390 args[0] = si_shader_ctx->esgs_ring;
391 args[1] = vtx_offset;
392 args[2] = lp_build_const_int32(gallivm,
393 (get_param_index(semantic_name, semantic_index,
394 shader->selector->gs_used_inputs) * 4 +
395 swizzle) * 256);
396 args[3] = uint->zero;
397 args[4] = uint->one; /* OFFEN */
398 args[5] = uint->zero; /* IDXEN */
399 args[6] = uint->one; /* GLC */
400 args[7] = uint->zero; /* SLC */
401 args[8] = uint->zero; /* TFE */
402
403 return LLVMBuildBitCast(gallivm->builder,
404 build_intrinsic(gallivm->builder,
405 "llvm.SI.buffer.load.dword.i32.i32",
406 i32, args, 9,
407 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
408 tgsi2llvmtype(bld_base, type), "");
409 }
410
411 static void declare_input_fs(
412 struct radeon_llvm_context *radeon_bld,
413 unsigned input_index,
414 const struct tgsi_full_declaration *decl)
415 {
416 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
417 struct si_shader_context *si_shader_ctx =
418 si_shader_context(&radeon_bld->soa.bld_base);
419 struct si_shader *shader = si_shader_ctx->shader;
420 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
421 struct gallivm_state *gallivm = base->gallivm;
422 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
423 LLVMValueRef main_fn = radeon_bld->main_fn;
424
425 LLVMValueRef interp_param;
426 const char * intr_name;
427
428 /* This value is:
429 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
430 * quad begins a new primitive. Bit 0 always needs
431 * to be unset)
432 * [32:16] ParamOffset
433 *
434 */
435 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
436 LLVMValueRef attr_number;
437
438 unsigned chan;
439
440 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
441 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
442 unsigned soa_index =
443 radeon_llvm_reg_index_soa(input_index, chan);
444 radeon_bld->inputs[soa_index] =
445 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
446
447 if (chan == 3)
448 /* RCP for fragcoord.w */
449 radeon_bld->inputs[soa_index] =
450 LLVMBuildFDiv(gallivm->builder,
451 lp_build_const_float(gallivm, 1.0f),
452 radeon_bld->inputs[soa_index],
453 "");
454 }
455 return;
456 }
457
458 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
459 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
460 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
461 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
462 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
463 lp_build_const_float(gallivm, 0.0f);
464 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
465 lp_build_const_float(gallivm, 1.0f);
466
467 return;
468 }
469
470 shader->ps_input_param_offset[input_index] = shader->nparam++;
471 attr_number = lp_build_const_int32(gallivm,
472 shader->ps_input_param_offset[input_index]);
473
474 switch (decl->Interp.Interpolate) {
475 case TGSI_INTERPOLATE_CONSTANT:
476 interp_param = 0;
477 break;
478 case TGSI_INTERPOLATE_LINEAR:
479 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
480 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
481 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
482 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
483 else
484 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
485 break;
486 case TGSI_INTERPOLATE_COLOR:
487 case TGSI_INTERPOLATE_PERSPECTIVE:
488 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
489 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
490 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
491 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
492 else
493 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
494 break;
495 default:
496 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
497 return;
498 }
499
500 /* fs.constant returns the param from the middle vertex, so it's not
501 * really useful for flat shading. It's meant to be used for custom
502 * interpolation (but the intrinsic can't fetch from the other two
503 * vertices).
504 *
505 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
506 * to do the right thing. The only reason we use fs.constant is that
507 * fs.interp cannot be used on integers, because they can be equal
508 * to NaN.
509 */
510 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
511
512 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
513 si_shader_ctx->shader->key.ps.color_two_side) {
514 LLVMValueRef args[4];
515 LLVMValueRef face, is_face_positive;
516 LLVMValueRef back_attr_number =
517 lp_build_const_int32(gallivm,
518 shader->ps_input_param_offset[input_index] + 1);
519
520 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
521
522 is_face_positive = LLVMBuildFCmp(gallivm->builder,
523 LLVMRealOGT, face,
524 lp_build_const_float(gallivm, 0.0f),
525 "");
526
527 args[2] = params;
528 args[3] = interp_param;
529 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
530 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
531 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
532 LLVMValueRef front, back;
533
534 args[0] = llvm_chan;
535 args[1] = attr_number;
536 front = build_intrinsic(gallivm->builder, intr_name,
537 input_type, args, args[3] ? 4 : 3,
538 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
539
540 args[1] = back_attr_number;
541 back = build_intrinsic(gallivm->builder, intr_name,
542 input_type, args, args[3] ? 4 : 3,
543 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
544
545 radeon_bld->inputs[soa_index] =
546 LLVMBuildSelect(gallivm->builder,
547 is_face_positive,
548 front,
549 back,
550 "");
551 }
552
553 shader->nparam++;
554 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
555 LLVMValueRef args[4];
556
557 args[0] = uint->zero;
558 args[1] = attr_number;
559 args[2] = params;
560 args[3] = interp_param;
561 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
562 build_intrinsic(gallivm->builder, intr_name,
563 input_type, args, args[3] ? 4 : 3,
564 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
565 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
566 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
567 lp_build_const_float(gallivm, 0.0f);
568 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
569 lp_build_const_float(gallivm, 1.0f);
570 } else {
571 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
572 LLVMValueRef args[4];
573 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
574 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
575 args[0] = llvm_chan;
576 args[1] = attr_number;
577 args[2] = params;
578 args[3] = interp_param;
579 radeon_bld->inputs[soa_index] =
580 build_intrinsic(gallivm->builder, intr_name,
581 input_type, args, args[3] ? 4 : 3,
582 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
583 }
584 }
585 }
586
587 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
588 {
589 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
590 SI_PARAM_ANCILLARY, 8, 4);
591 }
592
593 /**
594 * Load a dword from a constant buffer.
595 */
596 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
597 LLVMValueRef offset, LLVMTypeRef return_type)
598 {
599 LLVMValueRef args[2] = {resource, offset};
600
601 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
602 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
603 }
604
605 static void declare_system_value(
606 struct radeon_llvm_context * radeon_bld,
607 unsigned index,
608 const struct tgsi_full_declaration *decl)
609 {
610 struct si_shader_context *si_shader_ctx =
611 si_shader_context(&radeon_bld->soa.bld_base);
612 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
613 struct gallivm_state *gallivm = &radeon_bld->gallivm;
614 LLVMValueRef value = 0;
615
616 switch (decl->Semantic.Name) {
617 case TGSI_SEMANTIC_INSTANCEID:
618 value = LLVMGetParam(radeon_bld->main_fn,
619 si_shader_ctx->param_instance_id);
620 break;
621
622 case TGSI_SEMANTIC_VERTEXID:
623 value = LLVMBuildAdd(gallivm->builder,
624 LLVMGetParam(radeon_bld->main_fn,
625 si_shader_ctx->param_vertex_id),
626 LLVMGetParam(radeon_bld->main_fn,
627 SI_PARAM_BASE_VERTEX), "");
628 break;
629
630 case TGSI_SEMANTIC_VERTEXID_NOBASE:
631 value = LLVMGetParam(radeon_bld->main_fn,
632 si_shader_ctx->param_vertex_id);
633 break;
634
635 case TGSI_SEMANTIC_BASEVERTEX:
636 value = LLVMGetParam(radeon_bld->main_fn,
637 SI_PARAM_BASE_VERTEX);
638 break;
639
640 case TGSI_SEMANTIC_SAMPLEID:
641 value = get_sample_id(radeon_bld);
642 break;
643
644 case TGSI_SEMANTIC_SAMPLEPOS:
645 {
646 LLVMBuilderRef builder = gallivm->builder;
647 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
648 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
649 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
650
651 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
652 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
653 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
654
655 LLVMValueRef pos[4] = {
656 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
657 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
658 lp_build_const_float(gallivm, 0),
659 lp_build_const_float(gallivm, 0)
660 };
661 value = lp_build_gather_values(gallivm, pos, 4);
662 break;
663 }
664
665 case TGSI_SEMANTIC_SAMPLEMASK:
666 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
667 * Therefore, force gl_SampleMaskIn to 1 for GL. */
668 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
669 value = uint_bld->one;
670 else
671 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
672 break;
673
674 default:
675 assert(!"unknown system value");
676 return;
677 }
678
679 radeon_bld->system_values[index] = value;
680 }
681
682 static LLVMValueRef fetch_constant(
683 struct lp_build_tgsi_context * bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type,
686 unsigned swizzle)
687 {
688 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
689 struct lp_build_context * base = &bld_base->base;
690 const struct tgsi_ind_register *ireg = &reg->Indirect;
691 unsigned buf, idx;
692
693 LLVMValueRef addr;
694 LLVMValueRef result;
695
696 if (swizzle == LP_CHAN_ALL) {
697 unsigned chan;
698 LLVMValueRef values[4];
699 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
700 values[chan] = fetch_constant(bld_base, reg, type, chan);
701
702 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
703 }
704
705 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
706 idx = reg->Register.Index * 4 + swizzle;
707
708 if (!reg->Register.Indirect)
709 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
710
711 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
712 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
713 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
714 addr = lp_build_add(&bld_base->uint_bld, addr,
715 lp_build_const_int32(base->gallivm, idx * 4));
716
717 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
718 addr, base->elem_type);
719
720 return bitcast(bld_base, type, result);
721 }
722
723 /* Initialize arguments for the shader export intrinsic */
724 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
725 LLVMValueRef *values,
726 unsigned target,
727 LLVMValueRef *args)
728 {
729 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
730 struct lp_build_context *uint =
731 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
732 struct lp_build_context *base = &bld_base->base;
733 unsigned compressed = 0;
734 unsigned chan;
735
736 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
737 int cbuf = target - V_008DFC_SQ_EXP_MRT;
738
739 if (cbuf >= 0 && cbuf < 8) {
740 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
741
742 if (compressed)
743 si_shader_ctx->shader->spi_shader_col_format |=
744 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
745 else
746 si_shader_ctx->shader->spi_shader_col_format |=
747 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
748
749 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
750 }
751 }
752
753 if (compressed) {
754 /* Pixel shader needs to pack output values before export */
755 for (chan = 0; chan < 2; chan++ ) {
756 args[0] = values[2 * chan];
757 args[1] = values[2 * chan + 1];
758 args[chan + 5] =
759 build_intrinsic(base->gallivm->builder,
760 "llvm.SI.packf16",
761 LLVMInt32TypeInContext(base->gallivm->context),
762 args, 2,
763 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
764 args[chan + 7] = args[chan + 5] =
765 LLVMBuildBitCast(base->gallivm->builder,
766 args[chan + 5],
767 LLVMFloatTypeInContext(base->gallivm->context),
768 "");
769 }
770
771 /* Set COMPR flag */
772 args[4] = uint->one;
773 } else {
774 for (chan = 0; chan < 4; chan++ )
775 /* +5 because the first output value will be
776 * the 6th argument to the intrinsic. */
777 args[chan + 5] = values[chan];
778
779 /* Clear COMPR flag */
780 args[4] = uint->zero;
781 }
782
783 /* XXX: This controls which components of the output
784 * registers actually get exported. (e.g bit 0 means export
785 * X component, bit 1 means export Y component, etc.) I'm
786 * hard coding this to 0xf for now. In the future, we might
787 * want to do something else. */
788 args[0] = lp_build_const_int32(base->gallivm, 0xf);
789
790 /* Specify whether the EXEC mask represents the valid mask */
791 args[1] = uint->zero;
792
793 /* Specify whether this is the last export */
794 args[2] = uint->zero;
795
796 /* Specify the target we are exporting */
797 args[3] = lp_build_const_int32(base->gallivm, target);
798
799 /* XXX: We probably need to keep track of the output
800 * values, so we know what we are passing to the next
801 * stage. */
802 }
803
804 /* Load from output pointers and initialize arguments for the shader export intrinsic */
805 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
806 LLVMValueRef *out_ptr,
807 unsigned target,
808 LLVMValueRef *args)
809 {
810 struct gallivm_state *gallivm = bld_base->base.gallivm;
811 LLVMValueRef values[4];
812 int i;
813
814 for (i = 0; i < 4; i++)
815 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
816
817 si_llvm_init_export_args(bld_base, values, target, args);
818 }
819
820 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
821 LLVMValueRef alpha_ptr)
822 {
823 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
824 struct gallivm_state *gallivm = bld_base->base.gallivm;
825
826 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
827 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
828 SI_PARAM_ALPHA_REF);
829
830 LLVMValueRef alpha_pass =
831 lp_build_cmp(&bld_base->base,
832 si_shader_ctx->shader->key.ps.alpha_func,
833 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
834 alpha_ref);
835 LLVMValueRef arg =
836 lp_build_select(&bld_base->base,
837 alpha_pass,
838 lp_build_const_float(gallivm, 1.0f),
839 lp_build_const_float(gallivm, -1.0f));
840
841 build_intrinsic(gallivm->builder,
842 "llvm.AMDGPU.kill",
843 LLVMVoidTypeInContext(gallivm->context),
844 &arg, 1, 0);
845 } else {
846 build_intrinsic(gallivm->builder,
847 "llvm.AMDGPU.kilp",
848 LLVMVoidTypeInContext(gallivm->context),
849 NULL, 0, 0);
850 }
851
852 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
853 }
854
855 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
856 LLVMValueRef alpha_ptr)
857 {
858 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
859 struct gallivm_state *gallivm = bld_base->base.gallivm;
860 LLVMValueRef coverage, alpha;
861
862 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
863 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
864 SI_PARAM_SAMPLE_COVERAGE);
865 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
866
867 coverage = build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
868 bld_base->int_bld.elem_type,
869 &coverage, 1, LLVMReadNoneAttribute);
870
871 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
872 bld_base->base.elem_type, "");
873
874 coverage = LLVMBuildFMul(gallivm->builder, coverage,
875 lp_build_const_float(gallivm,
876 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
877
878 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
879 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
880 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
881 }
882
883 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
884 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
885 {
886 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
887 struct lp_build_context *base = &bld_base->base;
888 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
889 unsigned reg_index;
890 unsigned chan;
891 unsigned const_chan;
892 LLVMValueRef base_elt;
893 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
894 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
895 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
896
897 for (reg_index = 0; reg_index < 2; reg_index ++) {
898 LLVMValueRef *args = pos[2 + reg_index];
899
900 args[5] =
901 args[6] =
902 args[7] =
903 args[8] = lp_build_const_float(base->gallivm, 0.0f);
904
905 /* Compute dot products of position and user clip plane vectors */
906 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
907 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
908 args[1] = lp_build_const_int32(base->gallivm,
909 ((reg_index * 4 + chan) * 4 +
910 const_chan) * 4);
911 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
912 args[1], base->elem_type);
913 args[5 + chan] =
914 lp_build_add(base, args[5 + chan],
915 lp_build_mul(base, base_elt,
916 out_elts[const_chan]));
917 }
918 }
919
920 args[0] = lp_build_const_int32(base->gallivm, 0xf);
921 args[1] = uint->zero;
922 args[2] = uint->zero;
923 args[3] = lp_build_const_int32(base->gallivm,
924 V_008DFC_SQ_EXP_POS + 2 + reg_index);
925 args[4] = uint->zero;
926 }
927 }
928
929 static void si_dump_streamout(struct pipe_stream_output_info *so)
930 {
931 unsigned i;
932
933 if (so->num_outputs)
934 fprintf(stderr, "STREAMOUT\n");
935
936 for (i = 0; i < so->num_outputs; i++) {
937 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
938 so->output[i].start_component;
939 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
940 i, so->output[i].output_buffer,
941 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
942 so->output[i].register_index,
943 mask & 1 ? "x" : "",
944 mask & 2 ? "y" : "",
945 mask & 4 ? "z" : "",
946 mask & 8 ? "w" : "");
947 }
948 }
949
950 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
951 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
952 * or v4i32 (num_channels=3,4). */
953 static void build_tbuffer_store(struct si_shader_context *shader,
954 LLVMValueRef rsrc,
955 LLVMValueRef vdata,
956 unsigned num_channels,
957 LLVMValueRef vaddr,
958 LLVMValueRef soffset,
959 unsigned inst_offset,
960 unsigned dfmt,
961 unsigned nfmt,
962 unsigned offen,
963 unsigned idxen,
964 unsigned glc,
965 unsigned slc,
966 unsigned tfe)
967 {
968 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
969 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
970 LLVMValueRef args[] = {
971 rsrc,
972 vdata,
973 LLVMConstInt(i32, num_channels, 0),
974 vaddr,
975 soffset,
976 LLVMConstInt(i32, inst_offset, 0),
977 LLVMConstInt(i32, dfmt, 0),
978 LLVMConstInt(i32, nfmt, 0),
979 LLVMConstInt(i32, offen, 0),
980 LLVMConstInt(i32, idxen, 0),
981 LLVMConstInt(i32, glc, 0),
982 LLVMConstInt(i32, slc, 0),
983 LLVMConstInt(i32, tfe, 0)
984 };
985
986 /* The instruction offset field has 12 bits */
987 assert(offen || inst_offset < (1 << 12));
988
989 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
990 unsigned func = CLAMP(num_channels, 1, 3) - 1;
991 const char *types[] = {"i32", "v2i32", "v4i32"};
992 char name[256];
993 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
994
995 lp_build_intrinsic(gallivm->builder, name,
996 LLVMVoidTypeInContext(gallivm->context),
997 args, Elements(args));
998 }
999
1000 static void build_streamout_store(struct si_shader_context *shader,
1001 LLVMValueRef rsrc,
1002 LLVMValueRef vdata,
1003 unsigned num_channels,
1004 LLVMValueRef vaddr,
1005 LLVMValueRef soffset,
1006 unsigned inst_offset)
1007 {
1008 static unsigned dfmt[] = {
1009 V_008F0C_BUF_DATA_FORMAT_32,
1010 V_008F0C_BUF_DATA_FORMAT_32_32,
1011 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1012 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1013 };
1014 assert(num_channels >= 1 && num_channels <= 4);
1015
1016 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1017 inst_offset, dfmt[num_channels-1],
1018 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1019 }
1020
1021 /* On SI, the vertex shader is responsible for writing streamout data
1022 * to buffers. */
1023 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1024 struct si_shader_output_values *outputs,
1025 unsigned noutput)
1026 {
1027 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1028 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1029 LLVMBuilderRef builder = gallivm->builder;
1030 int i, j;
1031 struct lp_build_if_state if_ctx;
1032
1033 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1034
1035 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1036 LLVMValueRef so_vtx_count =
1037 unpack_param(shader, shader->param_streamout_config, 16, 7);
1038
1039 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
1040 NULL, 0, LLVMReadNoneAttribute);
1041
1042 /* can_emit = tid < so_vtx_count; */
1043 LLVMValueRef can_emit =
1044 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1045
1046 /* Emit the streamout code conditionally. This actually avoids
1047 * out-of-bounds buffer access. The hw tells us via the SGPR
1048 * (so_vtx_count) which threads are allowed to emit streamout data. */
1049 lp_build_if(&if_ctx, gallivm, can_emit);
1050 {
1051 /* The buffer offset is computed as follows:
1052 * ByteOffset = streamout_offset[buffer_id]*4 +
1053 * (streamout_write_index + thread_id)*stride[buffer_id] +
1054 * attrib_offset
1055 */
1056
1057 LLVMValueRef so_write_index =
1058 LLVMGetParam(shader->radeon_bld.main_fn,
1059 shader->param_streamout_write_index);
1060
1061 /* Compute (streamout_write_index + thread_id). */
1062 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1063
1064 /* Compute the write offset for each enabled buffer. */
1065 LLVMValueRef so_write_offset[4] = {};
1066 for (i = 0; i < 4; i++) {
1067 if (!so->stride[i])
1068 continue;
1069
1070 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1071 shader->param_streamout_offset[i]);
1072 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1073
1074 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1075 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1076 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1077 }
1078
1079 /* Write streamout data. */
1080 for (i = 0; i < so->num_outputs; i++) {
1081 unsigned buf_idx = so->output[i].output_buffer;
1082 unsigned reg = so->output[i].register_index;
1083 unsigned start = so->output[i].start_component;
1084 unsigned num_comps = so->output[i].num_components;
1085 LLVMValueRef out[4];
1086
1087 assert(num_comps && num_comps <= 4);
1088 if (!num_comps || num_comps > 4)
1089 continue;
1090
1091 if (reg >= noutput)
1092 continue;
1093
1094 /* Load the output as int. */
1095 for (j = 0; j < num_comps; j++) {
1096 out[j] = LLVMBuildBitCast(builder,
1097 outputs[reg].values[start+j],
1098 i32, "");
1099 }
1100
1101 /* Pack the output. */
1102 LLVMValueRef vdata = NULL;
1103
1104 switch (num_comps) {
1105 case 1: /* as i32 */
1106 vdata = out[0];
1107 break;
1108 case 2: /* as v2i32 */
1109 case 3: /* as v4i32 (aligned to 4) */
1110 case 4: /* as v4i32 */
1111 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1112 for (j = 0; j < num_comps; j++) {
1113 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1114 LLVMConstInt(i32, j, 0), "");
1115 }
1116 break;
1117 }
1118
1119 build_streamout_store(shader, shader->so_buffers[buf_idx],
1120 vdata, num_comps,
1121 so_write_offset[buf_idx],
1122 LLVMConstInt(i32, 0, 0),
1123 so->output[i].dst_offset*4);
1124 }
1125 }
1126 lp_build_endif(&if_ctx);
1127 }
1128
1129
1130 /* Generate export instructions for hardware VS shader stage */
1131 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1132 struct si_shader_output_values *outputs,
1133 unsigned noutput)
1134 {
1135 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1136 struct si_shader * shader = si_shader_ctx->shader;
1137 struct lp_build_context * base = &bld_base->base;
1138 struct lp_build_context * uint =
1139 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1140 LLVMValueRef args[9];
1141 LLVMValueRef pos_args[4][9] = { { 0 } };
1142 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1143 unsigned semantic_name, semantic_index;
1144 unsigned target;
1145 unsigned param_count = 0;
1146 unsigned pos_idx;
1147 int i;
1148
1149 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1150 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1151 }
1152
1153 for (i = 0; i < noutput; i++) {
1154 semantic_name = outputs[i].name;
1155 semantic_index = outputs[i].sid;
1156
1157 handle_semantic:
1158 /* Select the correct target */
1159 switch(semantic_name) {
1160 case TGSI_SEMANTIC_PSIZE:
1161 psize_value = outputs[i].values[0];
1162 continue;
1163 case TGSI_SEMANTIC_EDGEFLAG:
1164 edgeflag_value = outputs[i].values[0];
1165 continue;
1166 case TGSI_SEMANTIC_LAYER:
1167 layer_value = outputs[i].values[0];
1168 continue;
1169 case TGSI_SEMANTIC_POSITION:
1170 target = V_008DFC_SQ_EXP_POS;
1171 break;
1172 case TGSI_SEMANTIC_COLOR:
1173 case TGSI_SEMANTIC_BCOLOR:
1174 target = V_008DFC_SQ_EXP_PARAM + param_count;
1175 shader->vs_output_param_offset[i] = param_count;
1176 param_count++;
1177 break;
1178 case TGSI_SEMANTIC_CLIPDIST:
1179 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1180 break;
1181 case TGSI_SEMANTIC_CLIPVERTEX:
1182 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1183 continue;
1184 case TGSI_SEMANTIC_PRIMID:
1185 case TGSI_SEMANTIC_FOG:
1186 case TGSI_SEMANTIC_GENERIC:
1187 target = V_008DFC_SQ_EXP_PARAM + param_count;
1188 shader->vs_output_param_offset[i] = param_count;
1189 param_count++;
1190 break;
1191 default:
1192 target = 0;
1193 fprintf(stderr,
1194 "Warning: SI unhandled vs output type:%d\n",
1195 semantic_name);
1196 }
1197
1198 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1199
1200 if (target >= V_008DFC_SQ_EXP_POS &&
1201 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1202 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1203 args, sizeof(args));
1204 } else {
1205 lp_build_intrinsic(base->gallivm->builder,
1206 "llvm.SI.export",
1207 LLVMVoidTypeInContext(base->gallivm->context),
1208 args, 9);
1209 }
1210
1211 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1212 semantic_name = TGSI_SEMANTIC_GENERIC;
1213 goto handle_semantic;
1214 }
1215 }
1216
1217 /* We need to add the position output manually if it's missing. */
1218 if (!pos_args[0][0]) {
1219 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1220 pos_args[0][1] = uint->zero; /* EXEC mask */
1221 pos_args[0][2] = uint->zero; /* last export? */
1222 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1223 pos_args[0][4] = uint->zero; /* COMPR flag */
1224 pos_args[0][5] = base->zero; /* X */
1225 pos_args[0][6] = base->zero; /* Y */
1226 pos_args[0][7] = base->zero; /* Z */
1227 pos_args[0][8] = base->one; /* W */
1228 }
1229
1230 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1231 if (shader->selector->info.writes_psize ||
1232 shader->selector->info.writes_edgeflag ||
1233 shader->selector->info.writes_layer) {
1234 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1235 shader->selector->info.writes_psize |
1236 (shader->selector->info.writes_edgeflag << 1) |
1237 (shader->selector->info.writes_layer << 2));
1238 pos_args[1][1] = uint->zero; /* EXEC mask */
1239 pos_args[1][2] = uint->zero; /* last export? */
1240 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1241 pos_args[1][4] = uint->zero; /* COMPR flag */
1242 pos_args[1][5] = base->zero; /* X */
1243 pos_args[1][6] = base->zero; /* Y */
1244 pos_args[1][7] = base->zero; /* Z */
1245 pos_args[1][8] = base->zero; /* W */
1246
1247 if (shader->selector->info.writes_psize)
1248 pos_args[1][5] = psize_value;
1249
1250 if (shader->selector->info.writes_edgeflag) {
1251 /* The output is a float, but the hw expects an integer
1252 * with the first bit containing the edge flag. */
1253 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1254 edgeflag_value,
1255 bld_base->uint_bld.elem_type, "");
1256 edgeflag_value = lp_build_min(&bld_base->int_bld,
1257 edgeflag_value,
1258 bld_base->int_bld.one);
1259
1260 /* The LLVM intrinsic expects a float. */
1261 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1262 edgeflag_value,
1263 base->elem_type, "");
1264 }
1265
1266 if (shader->selector->info.writes_layer)
1267 pos_args[1][7] = layer_value;
1268 }
1269
1270 for (i = 0; i < 4; i++)
1271 if (pos_args[i][0])
1272 shader->nr_pos_exports++;
1273
1274 pos_idx = 0;
1275 for (i = 0; i < 4; i++) {
1276 if (!pos_args[i][0])
1277 continue;
1278
1279 /* Specify the target we are exporting */
1280 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1281
1282 if (pos_idx == shader->nr_pos_exports)
1283 /* Specify that this is the last export */
1284 pos_args[i][2] = uint->one;
1285
1286 lp_build_intrinsic(base->gallivm->builder,
1287 "llvm.SI.export",
1288 LLVMVoidTypeInContext(base->gallivm->context),
1289 pos_args[i], 9);
1290 }
1291 }
1292
1293 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1294 {
1295 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1296 struct gallivm_state *gallivm = bld_base->base.gallivm;
1297 struct si_shader *es = si_shader_ctx->shader;
1298 struct tgsi_shader_info *info = &es->selector->info;
1299 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1300 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1301 SI_PARAM_ES2GS_OFFSET);
1302 unsigned chan;
1303 int i;
1304
1305 for (i = 0; i < info->num_outputs; i++) {
1306 LLVMValueRef *out_ptr =
1307 si_shader_ctx->radeon_bld.soa.outputs[i];
1308 int param_index = get_param_index(info->output_semantic_name[i],
1309 info->output_semantic_index[i],
1310 es->key.vs.gs_used_inputs);
1311
1312 if (param_index < 0)
1313 continue;
1314
1315 for (chan = 0; chan < 4; chan++) {
1316 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1317 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1318
1319 build_tbuffer_store(si_shader_ctx,
1320 si_shader_ctx->esgs_ring,
1321 out_val, 1,
1322 LLVMGetUndef(i32), soffset,
1323 (4 * param_index + chan) * 4,
1324 V_008F0C_BUF_DATA_FORMAT_32,
1325 V_008F0C_BUF_NUM_FORMAT_UINT,
1326 0, 0, 1, 1, 0);
1327 }
1328 }
1329 }
1330
1331 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1332 {
1333 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1334 struct gallivm_state *gallivm = bld_base->base.gallivm;
1335 LLVMValueRef args[2];
1336
1337 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1338 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1339 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1340 LLVMVoidTypeInContext(gallivm->context), args, 2,
1341 LLVMNoUnwindAttribute);
1342 }
1343
1344 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1345 {
1346 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1347 struct gallivm_state *gallivm = bld_base->base.gallivm;
1348 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1349 struct si_shader_output_values *outputs = NULL;
1350 int i,j;
1351
1352 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1353
1354 for (i = 0; i < info->num_outputs; i++) {
1355 outputs[i].name = info->output_semantic_name[i];
1356 outputs[i].sid = info->output_semantic_index[i];
1357
1358 for (j = 0; j < 4; j++)
1359 outputs[i].values[j] =
1360 LLVMBuildLoad(gallivm->builder,
1361 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1362 "");
1363 }
1364
1365 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1366 FREE(outputs);
1367 }
1368
1369 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1370 {
1371 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1372 struct si_shader * shader = si_shader_ctx->shader;
1373 struct lp_build_context * base = &bld_base->base;
1374 struct lp_build_context * uint = &bld_base->uint_bld;
1375 struct tgsi_shader_info *info = &shader->selector->info;
1376 LLVMValueRef args[9];
1377 LLVMValueRef last_args[9] = { 0 };
1378 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1379 int i;
1380
1381 for (i = 0; i < info->num_outputs; i++) {
1382 unsigned semantic_name = info->output_semantic_name[i];
1383 unsigned semantic_index = info->output_semantic_index[i];
1384 unsigned target;
1385 LLVMValueRef alpha_ptr;
1386
1387 /* Select the correct target */
1388 switch (semantic_name) {
1389 case TGSI_SEMANTIC_POSITION:
1390 depth_index = i;
1391 continue;
1392 case TGSI_SEMANTIC_STENCIL:
1393 stencil_index = i;
1394 continue;
1395 case TGSI_SEMANTIC_SAMPLEMASK:
1396 samplemask_index = i;
1397 continue;
1398 case TGSI_SEMANTIC_COLOR:
1399 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1400 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
1401
1402 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1403 LLVMBuildStore(base->gallivm->builder,
1404 base->one, alpha_ptr);
1405
1406 if (semantic_index == 0 &&
1407 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1408 si_alpha_test(bld_base, alpha_ptr);
1409
1410 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1411 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
1412 break;
1413 default:
1414 target = 0;
1415 fprintf(stderr,
1416 "Warning: SI unhandled fs output type:%d\n",
1417 semantic_name);
1418 }
1419
1420 si_llvm_init_export_args_load(bld_base,
1421 si_shader_ctx->radeon_bld.soa.outputs[i],
1422 target, args);
1423
1424 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1425 /* If there is an export instruction waiting to be emitted, do so now. */
1426 if (last_args[0]) {
1427 lp_build_intrinsic(base->gallivm->builder,
1428 "llvm.SI.export",
1429 LLVMVoidTypeInContext(base->gallivm->context),
1430 last_args, 9);
1431 }
1432
1433 /* This instruction will be emitted at the end of the shader. */
1434 memcpy(last_args, args, sizeof(args));
1435
1436 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1437 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1438 semantic_index == 0 &&
1439 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1440 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1441 si_llvm_init_export_args_load(bld_base,
1442 si_shader_ctx->radeon_bld.soa.outputs[i],
1443 V_008DFC_SQ_EXP_MRT + c, args);
1444 lp_build_intrinsic(base->gallivm->builder,
1445 "llvm.SI.export",
1446 LLVMVoidTypeInContext(base->gallivm->context),
1447 args, 9);
1448 }
1449 }
1450 } else {
1451 lp_build_intrinsic(base->gallivm->builder,
1452 "llvm.SI.export",
1453 LLVMVoidTypeInContext(base->gallivm->context),
1454 args, 9);
1455 }
1456 }
1457
1458 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1459 LLVMValueRef out_ptr;
1460 unsigned mask = 0;
1461
1462 /* Specify the target we are exporting */
1463 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1464
1465 args[5] = base->zero; /* R, depth */
1466 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1467 args[7] = base->zero; /* B, sample mask */
1468 args[8] = base->zero; /* A, alpha to mask */
1469
1470 if (depth_index >= 0) {
1471 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1472 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1473 mask |= 0x1;
1474 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1475 }
1476
1477 if (stencil_index >= 0) {
1478 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1479 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1480 mask |= 0x2;
1481 si_shader_ctx->shader->db_shader_control |=
1482 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1483 }
1484
1485 if (samplemask_index >= 0) {
1486 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1487 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1488 mask |= 0x4;
1489 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1490 }
1491
1492 /* SI (except OLAND) has a bug that it only looks
1493 * at the X writemask component. */
1494 if (si_shader_ctx->screen->b.chip_class == SI &&
1495 si_shader_ctx->screen->b.family != CHIP_OLAND)
1496 mask |= 0x1;
1497
1498 if (samplemask_index >= 0)
1499 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1500 else if (stencil_index >= 0)
1501 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1502 else
1503 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1504
1505 /* Specify which components to enable */
1506 args[0] = lp_build_const_int32(base->gallivm, mask);
1507
1508 args[1] =
1509 args[2] =
1510 args[4] = uint->zero;
1511
1512 if (last_args[0])
1513 lp_build_intrinsic(base->gallivm->builder,
1514 "llvm.SI.export",
1515 LLVMVoidTypeInContext(base->gallivm->context),
1516 args, 9);
1517 else
1518 memcpy(last_args, args, sizeof(args));
1519 }
1520
1521 if (!last_args[0]) {
1522 /* Specify which components to enable */
1523 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1524
1525 /* Specify the target we are exporting */
1526 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1527
1528 /* Set COMPR flag to zero to export data as 32-bit */
1529 last_args[4] = uint->zero;
1530
1531 /* dummy bits */
1532 last_args[5]= uint->zero;
1533 last_args[6]= uint->zero;
1534 last_args[7]= uint->zero;
1535 last_args[8]= uint->zero;
1536 }
1537
1538 /* Specify whether the EXEC mask represents the valid mask */
1539 last_args[1] = uint->one;
1540
1541 /* Specify that this is the last export */
1542 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1543
1544 lp_build_intrinsic(base->gallivm->builder,
1545 "llvm.SI.export",
1546 LLVMVoidTypeInContext(base->gallivm->context),
1547 last_args, 9);
1548 }
1549
1550 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1551 struct lp_build_tgsi_context * bld_base,
1552 struct lp_build_emit_data * emit_data);
1553
1554 static bool tgsi_is_shadow_sampler(unsigned target)
1555 {
1556 return target == TGSI_TEXTURE_SHADOW1D ||
1557 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1558 target == TGSI_TEXTURE_SHADOW2D ||
1559 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1560 target == TGSI_TEXTURE_SHADOWCUBE ||
1561 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1562 target == TGSI_TEXTURE_SHADOWRECT;
1563 }
1564
1565 static const struct lp_build_tgsi_action tex_action;
1566
1567 static void tex_fetch_args(
1568 struct lp_build_tgsi_context * bld_base,
1569 struct lp_build_emit_data * emit_data)
1570 {
1571 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1572 struct gallivm_state *gallivm = bld_base->base.gallivm;
1573 const struct tgsi_full_instruction * inst = emit_data->inst;
1574 unsigned opcode = inst->Instruction.Opcode;
1575 unsigned target = inst->Texture.Texture;
1576 LLVMValueRef coords[5];
1577 LLVMValueRef address[16];
1578 int ref_pos;
1579 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1580 unsigned count = 0;
1581 unsigned chan;
1582 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1583 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1584 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1585
1586 if (target == TGSI_TEXTURE_BUFFER) {
1587 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1588 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1589 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1590 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1591
1592 /* Bitcast and truncate v8i32 to v16i8. */
1593 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1594 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1595 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
1596 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1597
1598 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1599 emit_data->args[0] = res;
1600 emit_data->args[1] = bld_base->uint_bld.zero;
1601 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1602 emit_data->arg_count = 3;
1603 return;
1604 }
1605
1606 /* Fetch and project texture coordinates */
1607 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1608 for (chan = 0; chan < 3; chan++ ) {
1609 coords[chan] = lp_build_emit_fetch(bld_base,
1610 emit_data->inst, 0,
1611 chan);
1612 if (opcode == TGSI_OPCODE_TXP)
1613 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1614 TGSI_OPCODE_DIV,
1615 coords[chan],
1616 coords[3]);
1617 }
1618
1619 if (opcode == TGSI_OPCODE_TXP)
1620 coords[3] = bld_base->base.one;
1621
1622 /* Pack offsets. */
1623 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1624 /* The offsets are six-bit signed integers packed like this:
1625 * X=[5:0], Y=[13:8], and Z=[21:16].
1626 */
1627 LLVMValueRef offset[3], pack;
1628
1629 assert(inst->Texture.NumOffsets == 1);
1630
1631 for (chan = 0; chan < 3; chan++) {
1632 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1633 emit_data->inst, 0, chan);
1634 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1635 lp_build_const_int32(gallivm, 0x3f), "");
1636 if (chan)
1637 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1638 lp_build_const_int32(gallivm, chan*8), "");
1639 }
1640
1641 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1642 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1643 address[count++] = pack;
1644 }
1645
1646 /* Pack LOD bias value */
1647 if (opcode == TGSI_OPCODE_TXB)
1648 address[count++] = coords[3];
1649 if (opcode == TGSI_OPCODE_TXB2)
1650 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1651
1652 /* Pack depth comparison value */
1653 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1654 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1655 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1656 } else {
1657 assert(ref_pos >= 0);
1658 address[count++] = coords[ref_pos];
1659 }
1660 }
1661
1662 if (target == TGSI_TEXTURE_CUBE ||
1663 target == TGSI_TEXTURE_CUBE_ARRAY ||
1664 target == TGSI_TEXTURE_SHADOWCUBE ||
1665 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1666 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1667
1668 /* Pack user derivatives */
1669 if (opcode == TGSI_OPCODE_TXD) {
1670 int num_deriv_channels, param;
1671
1672 switch (target) {
1673 case TGSI_TEXTURE_3D:
1674 num_deriv_channels = 3;
1675 break;
1676 case TGSI_TEXTURE_2D:
1677 case TGSI_TEXTURE_SHADOW2D:
1678 case TGSI_TEXTURE_RECT:
1679 case TGSI_TEXTURE_SHADOWRECT:
1680 case TGSI_TEXTURE_2D_ARRAY:
1681 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1682 case TGSI_TEXTURE_CUBE:
1683 case TGSI_TEXTURE_SHADOWCUBE:
1684 case TGSI_TEXTURE_CUBE_ARRAY:
1685 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1686 num_deriv_channels = 2;
1687 break;
1688 case TGSI_TEXTURE_1D:
1689 case TGSI_TEXTURE_SHADOW1D:
1690 case TGSI_TEXTURE_1D_ARRAY:
1691 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1692 num_deriv_channels = 1;
1693 break;
1694 default:
1695 assert(0); /* no other targets are valid here */
1696 }
1697
1698 for (param = 1; param <= 2; param++)
1699 for (chan = 0; chan < num_deriv_channels; chan++)
1700 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1701 }
1702
1703 /* Pack texture coordinates */
1704 address[count++] = coords[0];
1705 if (num_coords > 1)
1706 address[count++] = coords[1];
1707 if (num_coords > 2)
1708 address[count++] = coords[2];
1709
1710 /* Pack LOD or sample index */
1711 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1712 address[count++] = coords[3];
1713 else if (opcode == TGSI_OPCODE_TXL2)
1714 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1715
1716 if (count > 16) {
1717 assert(!"Cannot handle more than 16 texture address parameters");
1718 count = 16;
1719 }
1720
1721 for (chan = 0; chan < count; chan++ ) {
1722 address[chan] = LLVMBuildBitCast(gallivm->builder,
1723 address[chan],
1724 LLVMInt32TypeInContext(gallivm->context),
1725 "");
1726 }
1727
1728 /* Adjust the sample index according to FMASK.
1729 *
1730 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1731 * which is the identity mapping. Each nibble says which physical sample
1732 * should be fetched to get that sample.
1733 *
1734 * For example, 0x11111100 means there are only 2 samples stored and
1735 * the second sample covers 3/4 of the pixel. When reading samples 0
1736 * and 1, return physical sample 0 (determined by the first two 0s
1737 * in FMASK), otherwise return physical sample 1.
1738 *
1739 * The sample index should be adjusted as follows:
1740 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1741 */
1742 if (target == TGSI_TEXTURE_2D_MSAA ||
1743 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1744 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1745 struct lp_build_emit_data txf_emit_data = *emit_data;
1746 LLVMValueRef txf_address[4];
1747 unsigned txf_count = count;
1748 struct tgsi_full_instruction inst = {};
1749
1750 memcpy(txf_address, address, sizeof(txf_address));
1751
1752 if (target == TGSI_TEXTURE_2D_MSAA) {
1753 txf_address[2] = bld_base->uint_bld.zero;
1754 }
1755 txf_address[3] = bld_base->uint_bld.zero;
1756
1757 /* Pad to a power-of-two size. */
1758 while (txf_count < util_next_power_of_two(txf_count))
1759 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1760
1761 /* Read FMASK using TXF. */
1762 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1763 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1764 txf_emit_data.inst = &inst;
1765 txf_emit_data.chan = 0;
1766 txf_emit_data.dst_type = LLVMVectorType(
1767 LLVMInt32TypeInContext(gallivm->context), 4);
1768 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1769 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1770 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1771 txf_emit_data.arg_count = 3;
1772
1773 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1774
1775 /* Initialize some constants. */
1776 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1777 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1778
1779 /* Apply the formula. */
1780 LLVMValueRef fmask =
1781 LLVMBuildExtractElement(gallivm->builder,
1782 txf_emit_data.output[0],
1783 uint_bld->zero, "");
1784
1785 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1786
1787 LLVMValueRef sample_index4 =
1788 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1789
1790 LLVMValueRef shifted_fmask =
1791 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1792
1793 LLVMValueRef final_sample =
1794 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1795
1796 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1797 * resource descriptor is 0 (invalid),
1798 */
1799 LLVMValueRef fmask_desc =
1800 LLVMBuildBitCast(gallivm->builder,
1801 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1802 LLVMVectorType(uint_bld->elem_type, 8), "");
1803
1804 LLVMValueRef fmask_word1 =
1805 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1806 uint_bld->one, "");
1807
1808 LLVMValueRef word1_is_nonzero =
1809 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1810 fmask_word1, uint_bld->zero, "");
1811
1812 /* Replace the MSAA sample index. */
1813 address[sample_chan] =
1814 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1815 final_sample, address[sample_chan], "");
1816 }
1817
1818 /* Resource */
1819 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1820
1821 if (opcode == TGSI_OPCODE_TXF) {
1822 /* add tex offsets */
1823 if (inst->Texture.NumOffsets) {
1824 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1825 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1826 const struct tgsi_texture_offset * off = inst->TexOffsets;
1827
1828 assert(inst->Texture.NumOffsets == 1);
1829
1830 switch (target) {
1831 case TGSI_TEXTURE_3D:
1832 address[2] = lp_build_add(uint_bld, address[2],
1833 bld->immediates[off->Index][off->SwizzleZ]);
1834 /* fall through */
1835 case TGSI_TEXTURE_2D:
1836 case TGSI_TEXTURE_SHADOW2D:
1837 case TGSI_TEXTURE_RECT:
1838 case TGSI_TEXTURE_SHADOWRECT:
1839 case TGSI_TEXTURE_2D_ARRAY:
1840 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1841 address[1] =
1842 lp_build_add(uint_bld, address[1],
1843 bld->immediates[off->Index][off->SwizzleY]);
1844 /* fall through */
1845 case TGSI_TEXTURE_1D:
1846 case TGSI_TEXTURE_SHADOW1D:
1847 case TGSI_TEXTURE_1D_ARRAY:
1848 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1849 address[0] =
1850 lp_build_add(uint_bld, address[0],
1851 bld->immediates[off->Index][off->SwizzleX]);
1852 break;
1853 /* texture offsets do not apply to other texture targets */
1854 }
1855 }
1856
1857 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1858 emit_data->arg_count = 3;
1859
1860 emit_data->dst_type = LLVMVectorType(
1861 LLVMInt32TypeInContext(gallivm->context),
1862 4);
1863 } else if (opcode == TGSI_OPCODE_TG4 ||
1864 opcode == TGSI_OPCODE_LODQ ||
1865 has_offset) {
1866 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1867 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1868 target == TGSI_TEXTURE_2D_ARRAY ||
1869 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1870 target == TGSI_TEXTURE_CUBE_ARRAY ||
1871 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1872 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1873 unsigned dmask = 0xf;
1874
1875 if (opcode == TGSI_OPCODE_TG4) {
1876 unsigned gather_comp = 0;
1877
1878 /* DMASK was repurposed for GATHER4. 4 components are always
1879 * returned and DMASK works like a swizzle - it selects
1880 * the component to fetch. The only valid DMASK values are
1881 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1882 * (red,red,red,red) etc.) The ISA document doesn't mention
1883 * this.
1884 */
1885
1886 /* Get the component index from src1.x for Gather4. */
1887 if (!tgsi_is_shadow_sampler(target)) {
1888 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1889 LLVMValueRef comp_imm;
1890 struct tgsi_src_register src1 = inst->Src[1].Register;
1891
1892 assert(src1.File == TGSI_FILE_IMMEDIATE);
1893
1894 comp_imm = imms[src1.Index][src1.SwizzleX];
1895 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1896 gather_comp = CLAMP(gather_comp, 0, 3);
1897 }
1898
1899 dmask = 1 << gather_comp;
1900 }
1901
1902 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1903 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1904 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1905 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1906 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1907 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1908 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1909 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1910 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1911
1912 emit_data->arg_count = 11;
1913
1914 emit_data->dst_type = LLVMVectorType(
1915 LLVMFloatTypeInContext(gallivm->context),
1916 4);
1917 } else {
1918 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1919 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1920 emit_data->arg_count = 4;
1921
1922 emit_data->dst_type = LLVMVectorType(
1923 LLVMFloatTypeInContext(gallivm->context),
1924 4);
1925 }
1926
1927 /* The fetch opcode has been converted to a 2D array fetch.
1928 * This simplifies the LLVM backend. */
1929 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1930 target = TGSI_TEXTURE_2D_ARRAY;
1931 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1932 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1933
1934 /* Pad to power of two vector */
1935 while (count < util_next_power_of_two(count))
1936 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1937
1938 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1939 }
1940
1941 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1942 struct lp_build_tgsi_context * bld_base,
1943 struct lp_build_emit_data * emit_data)
1944 {
1945 struct lp_build_context * base = &bld_base->base;
1946 unsigned opcode = emit_data->inst->Instruction.Opcode;
1947 unsigned target = emit_data->inst->Texture.Texture;
1948 char intr_name[127];
1949 bool has_offset = HAVE_LLVM >= 0x0305 ?
1950 emit_data->inst->Texture.NumOffsets > 0 : false;
1951
1952 if (target == TGSI_TEXTURE_BUFFER) {
1953 emit_data->output[emit_data->chan] = build_intrinsic(
1954 base->gallivm->builder,
1955 "llvm.SI.vs.load.input", emit_data->dst_type,
1956 emit_data->args, emit_data->arg_count,
1957 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1958 return;
1959 }
1960
1961 if (opcode == TGSI_OPCODE_TG4 ||
1962 opcode == TGSI_OPCODE_LODQ ||
1963 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1964 bool is_shadow = tgsi_is_shadow_sampler(target);
1965 const char *name = "llvm.SI.image.sample";
1966 const char *infix = "";
1967
1968 switch (opcode) {
1969 case TGSI_OPCODE_TEX:
1970 case TGSI_OPCODE_TEX2:
1971 case TGSI_OPCODE_TXP:
1972 break;
1973 case TGSI_OPCODE_TXB:
1974 case TGSI_OPCODE_TXB2:
1975 infix = ".b";
1976 break;
1977 case TGSI_OPCODE_TXL:
1978 case TGSI_OPCODE_TXL2:
1979 infix = ".l";
1980 break;
1981 case TGSI_OPCODE_TXD:
1982 infix = ".d";
1983 break;
1984 case TGSI_OPCODE_TG4:
1985 name = "llvm.SI.gather4";
1986 break;
1987 case TGSI_OPCODE_LODQ:
1988 name = "llvm.SI.getlod";
1989 is_shadow = false;
1990 has_offset = false;
1991 break;
1992 default:
1993 assert(0);
1994 return;
1995 }
1996
1997 /* Add the type and suffixes .c, .o if needed. */
1998 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1999 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
2000 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2001
2002 emit_data->output[emit_data->chan] = build_intrinsic(
2003 base->gallivm->builder, intr_name, emit_data->dst_type,
2004 emit_data->args, emit_data->arg_count,
2005 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2006 } else {
2007 LLVMTypeRef i8, v16i8, v32i8;
2008 const char *name;
2009
2010 switch (opcode) {
2011 case TGSI_OPCODE_TEX:
2012 case TGSI_OPCODE_TEX2:
2013 case TGSI_OPCODE_TXP:
2014 name = "llvm.SI.sample";
2015 break;
2016 case TGSI_OPCODE_TXB:
2017 case TGSI_OPCODE_TXB2:
2018 name = "llvm.SI.sampleb";
2019 break;
2020 case TGSI_OPCODE_TXD:
2021 name = "llvm.SI.sampled";
2022 break;
2023 case TGSI_OPCODE_TXF:
2024 name = "llvm.SI.imageload";
2025 break;
2026 case TGSI_OPCODE_TXL:
2027 case TGSI_OPCODE_TXL2:
2028 name = "llvm.SI.samplel";
2029 break;
2030 default:
2031 assert(0);
2032 return;
2033 }
2034
2035 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2036 v16i8 = LLVMVectorType(i8, 16);
2037 v32i8 = LLVMVectorType(i8, 32);
2038
2039 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2040 emit_data->args[1], v32i8, "");
2041 if (opcode != TGSI_OPCODE_TXF) {
2042 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2043 emit_data->args[2], v16i8, "");
2044 }
2045
2046 sprintf(intr_name, "%s.v%ui32", name,
2047 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2048
2049 emit_data->output[emit_data->chan] = build_intrinsic(
2050 base->gallivm->builder, intr_name, emit_data->dst_type,
2051 emit_data->args, emit_data->arg_count,
2052 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2053 }
2054 }
2055
2056 static void txq_fetch_args(
2057 struct lp_build_tgsi_context * bld_base,
2058 struct lp_build_emit_data * emit_data)
2059 {
2060 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2061 const struct tgsi_full_instruction *inst = emit_data->inst;
2062 struct gallivm_state *gallivm = bld_base->base.gallivm;
2063 unsigned target = inst->Texture.Texture;
2064
2065 if (target == TGSI_TEXTURE_BUFFER) {
2066 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2067 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2068
2069 /* Read the size from the buffer descriptor directly. */
2070 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2071 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2072 size = LLVMBuildExtractElement(gallivm->builder, size,
2073 lp_build_const_int32(gallivm, 6), "");
2074 emit_data->args[0] = size;
2075 return;
2076 }
2077
2078 /* Mip level */
2079 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2080
2081 /* Resource */
2082 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2083
2084 /* Texture target */
2085 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2086 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2087 target = TGSI_TEXTURE_2D_ARRAY;
2088
2089 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2090 target);
2091
2092 emit_data->arg_count = 3;
2093
2094 emit_data->dst_type = LLVMVectorType(
2095 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2096 4);
2097 }
2098
2099 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2100 struct lp_build_tgsi_context * bld_base,
2101 struct lp_build_emit_data * emit_data)
2102 {
2103 unsigned target = emit_data->inst->Texture.Texture;
2104
2105 if (target == TGSI_TEXTURE_BUFFER) {
2106 /* Just return the buffer size. */
2107 emit_data->output[emit_data->chan] = emit_data->args[0];
2108 return;
2109 }
2110
2111 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2112
2113 /* Divide the number of layers by 6 to get the number of cubes. */
2114 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2115 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2116 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2117 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2118 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2119
2120 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2121 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2122 z = LLVMBuildSDiv(builder, z, six, "");
2123
2124 emit_data->output[emit_data->chan] =
2125 LLVMBuildInsertElement(builder, v4, z, two, "");
2126 }
2127 }
2128
2129 static void si_llvm_emit_ddxy(
2130 const struct lp_build_tgsi_action * action,
2131 struct lp_build_tgsi_context * bld_base,
2132 struct lp_build_emit_data * emit_data)
2133 {
2134 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2135 struct gallivm_state *gallivm = bld_base->base.gallivm;
2136 struct lp_build_context * base = &bld_base->base;
2137 const struct tgsi_full_instruction *inst = emit_data->inst;
2138 unsigned opcode = inst->Instruction.Opcode;
2139 LLVMValueRef indices[2];
2140 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2141 LLVMValueRef tl, trbl, result[4];
2142 LLVMTypeRef i32;
2143 unsigned swizzle[4];
2144 unsigned c;
2145
2146 i32 = LLVMInt32TypeInContext(gallivm->context);
2147
2148 indices[0] = bld_base->uint_bld.zero;
2149 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2150 NULL, 0, LLVMReadNoneAttribute);
2151 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2152 indices, 2, "");
2153
2154 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2155 lp_build_const_int32(gallivm, 0xfffffffc), "");
2156 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2157 indices, 2, "");
2158
2159 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2160 lp_build_const_int32(gallivm,
2161 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2162 "");
2163 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2164 indices, 2, "");
2165
2166 for (c = 0; c < 4; ++c) {
2167 unsigned i;
2168
2169 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2170 for (i = 0; i < c; ++i) {
2171 if (swizzle[i] == swizzle[c]) {
2172 result[c] = result[i];
2173 break;
2174 }
2175 }
2176 if (i != c)
2177 continue;
2178
2179 LLVMBuildStore(gallivm->builder,
2180 LLVMBuildBitCast(gallivm->builder,
2181 lp_build_emit_fetch(bld_base, inst, 0, c),
2182 i32, ""),
2183 store_ptr);
2184
2185 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2186 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2187
2188 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2189 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2190
2191 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2192 }
2193
2194 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2195 }
2196
2197 /* Emit one vertex from the geometry shader */
2198 static void si_llvm_emit_vertex(
2199 const struct lp_build_tgsi_action *action,
2200 struct lp_build_tgsi_context *bld_base,
2201 struct lp_build_emit_data *emit_data)
2202 {
2203 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2204 struct lp_build_context *uint = &bld_base->uint_bld;
2205 struct si_shader *shader = si_shader_ctx->shader;
2206 struct tgsi_shader_info *info = &shader->selector->info;
2207 struct gallivm_state *gallivm = bld_base->base.gallivm;
2208 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2209 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2210 SI_PARAM_GS2VS_OFFSET);
2211 LLVMValueRef gs_next_vertex;
2212 LLVMValueRef can_emit, kill;
2213 LLVMValueRef args[2];
2214 unsigned chan;
2215 int i;
2216
2217 /* Write vertex attribute values to GSVS ring */
2218 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2219
2220 /* If this thread has already emitted the declared maximum number of
2221 * vertices, kill it: excessive vertex emissions are not supposed to
2222 * have any effect, and GS threads have no externally observable
2223 * effects other than emitting vertices.
2224 */
2225 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2226 lp_build_const_int32(gallivm,
2227 shader->selector->gs_max_out_vertices), "");
2228 kill = lp_build_select(&bld_base->base, can_emit,
2229 lp_build_const_float(gallivm, 1.0f),
2230 lp_build_const_float(gallivm, -1.0f));
2231 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2232 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2233
2234 for (i = 0; i < info->num_outputs; i++) {
2235 LLVMValueRef *out_ptr =
2236 si_shader_ctx->radeon_bld.soa.outputs[i];
2237
2238 for (chan = 0; chan < 4; chan++) {
2239 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2240 LLVMValueRef voffset =
2241 lp_build_const_int32(gallivm, (i * 4 + chan) *
2242 shader->selector->gs_max_out_vertices);
2243
2244 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2245 voffset = lp_build_mul_imm(uint, voffset, 4);
2246
2247 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2248
2249 build_tbuffer_store(si_shader_ctx,
2250 si_shader_ctx->gsvs_ring,
2251 out_val, 1,
2252 voffset, soffset, 0,
2253 V_008F0C_BUF_DATA_FORMAT_32,
2254 V_008F0C_BUF_NUM_FORMAT_UINT,
2255 1, 0, 1, 1, 0);
2256 }
2257 }
2258 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2259 lp_build_const_int32(gallivm, 1));
2260 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2261
2262 /* Signal vertex emission */
2263 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2264 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2265 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2266 LLVMVoidTypeInContext(gallivm->context), args, 2,
2267 LLVMNoUnwindAttribute);
2268 }
2269
2270 /* Cut one primitive from the geometry shader */
2271 static void si_llvm_emit_primitive(
2272 const struct lp_build_tgsi_action *action,
2273 struct lp_build_tgsi_context *bld_base,
2274 struct lp_build_emit_data *emit_data)
2275 {
2276 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2277 struct gallivm_state *gallivm = bld_base->base.gallivm;
2278 LLVMValueRef args[2];
2279
2280 /* Signal primitive cut */
2281 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2282 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2283 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2284 LLVMVoidTypeInContext(gallivm->context), args, 2,
2285 LLVMNoUnwindAttribute);
2286 }
2287
2288 static const struct lp_build_tgsi_action tex_action = {
2289 .fetch_args = tex_fetch_args,
2290 .emit = build_tex_intrinsic,
2291 };
2292
2293 static const struct lp_build_tgsi_action txq_action = {
2294 .fetch_args = txq_fetch_args,
2295 .emit = build_txq_intrinsic,
2296 .intr_name = "llvm.SI.resinfo"
2297 };
2298
2299 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2300 {
2301 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2302 LLVMValueRef args[3];
2303
2304 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2305 args[1] = 0;
2306 args[2] = lp_build_const_int32(gallivm, 1);
2307
2308 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2309 }
2310
2311 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2312 {
2313 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2314 CONST_ADDR_SPACE);
2315 }
2316
2317 static void create_function(struct si_shader_context *si_shader_ctx)
2318 {
2319 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2320 struct gallivm_state *gallivm = bld_base->base.gallivm;
2321 struct si_shader *shader = si_shader_ctx->shader;
2322 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2323 unsigned i, last_array_pointer, last_sgpr, num_params;
2324
2325 i8 = LLVMInt8TypeInContext(gallivm->context);
2326 i32 = LLVMInt32TypeInContext(gallivm->context);
2327 f32 = LLVMFloatTypeInContext(gallivm->context);
2328 v2i32 = LLVMVectorType(i32, 2);
2329 v3i32 = LLVMVectorType(i32, 3);
2330 v4i32 = LLVMVectorType(i32, 4);
2331 v8i32 = LLVMVectorType(i32, 8);
2332 v16i8 = LLVMVectorType(i8, 16);
2333
2334 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2335 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2336 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2337 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2338 last_array_pointer = SI_PARAM_RESOURCE;
2339
2340 switch (si_shader_ctx->type) {
2341 case TGSI_PROCESSOR_VERTEX:
2342 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2343 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2344 params[SI_PARAM_BASE_VERTEX] = i32;
2345 params[SI_PARAM_START_INSTANCE] = i32;
2346 num_params = SI_PARAM_START_INSTANCE+1;
2347
2348 if (shader->key.vs.as_es) {
2349 params[SI_PARAM_ES2GS_OFFSET] = i32;
2350 num_params++;
2351 } else {
2352 if (shader->is_gs_copy_shader) {
2353 last_array_pointer = SI_PARAM_CONST;
2354 num_params = SI_PARAM_CONST+1;
2355 }
2356
2357 /* The locations of the other parameters are assigned dynamically. */
2358
2359 /* Streamout SGPRs. */
2360 if (shader->selector->so.num_outputs) {
2361 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2362 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2363 }
2364 /* A streamout buffer offset is loaded if the stride is non-zero. */
2365 for (i = 0; i < 4; i++) {
2366 if (!shader->selector->so.stride[i])
2367 continue;
2368
2369 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2370 }
2371 }
2372
2373 last_sgpr = num_params-1;
2374
2375 /* VGPRs */
2376 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2377 params[num_params++] = i32; /* unused*/
2378 params[num_params++] = i32; /* unused */
2379 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2380 break;
2381
2382 case TGSI_PROCESSOR_GEOMETRY:
2383 params[SI_PARAM_GS2VS_OFFSET] = i32;
2384 params[SI_PARAM_GS_WAVE_ID] = i32;
2385 last_sgpr = SI_PARAM_GS_WAVE_ID;
2386
2387 /* VGPRs */
2388 params[SI_PARAM_VTX0_OFFSET] = i32;
2389 params[SI_PARAM_VTX1_OFFSET] = i32;
2390 params[SI_PARAM_PRIMITIVE_ID] = i32;
2391 params[SI_PARAM_VTX2_OFFSET] = i32;
2392 params[SI_PARAM_VTX3_OFFSET] = i32;
2393 params[SI_PARAM_VTX4_OFFSET] = i32;
2394 params[SI_PARAM_VTX5_OFFSET] = i32;
2395 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2396 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2397 break;
2398
2399 case TGSI_PROCESSOR_FRAGMENT:
2400 params[SI_PARAM_ALPHA_REF] = f32;
2401 params[SI_PARAM_PRIM_MASK] = i32;
2402 last_sgpr = SI_PARAM_PRIM_MASK;
2403 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2404 params[SI_PARAM_PERSP_CENTER] = v2i32;
2405 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2406 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2407 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2408 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2409 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2410 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2411 params[SI_PARAM_POS_X_FLOAT] = f32;
2412 params[SI_PARAM_POS_Y_FLOAT] = f32;
2413 params[SI_PARAM_POS_Z_FLOAT] = f32;
2414 params[SI_PARAM_POS_W_FLOAT] = f32;
2415 params[SI_PARAM_FRONT_FACE] = f32;
2416 params[SI_PARAM_ANCILLARY] = i32;
2417 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2418 params[SI_PARAM_POS_FIXED_PT] = f32;
2419 num_params = SI_PARAM_POS_FIXED_PT+1;
2420 break;
2421
2422 default:
2423 assert(0 && "unimplemented shader");
2424 return;
2425 }
2426
2427 assert(num_params <= Elements(params));
2428 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2429 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2430
2431 if (shader->dx10_clamp_mode)
2432 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
2433 "enable-no-nans-fp-math", "true");
2434
2435 for (i = 0; i <= last_sgpr; ++i) {
2436 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2437
2438 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2439 * to move load. Inputs are constant so this is fine. */
2440 if (i <= last_array_pointer)
2441 LLVMAddAttribute(P, LLVMByValAttribute);
2442 else
2443 LLVMAddAttribute(P, LLVMInRegAttribute);
2444 }
2445
2446 if (bld_base->info &&
2447 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2448 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2449 si_shader_ctx->ddxy_lds =
2450 LLVMAddGlobalInAddressSpace(gallivm->module,
2451 LLVMArrayType(i32, 64),
2452 "ddxy_lds",
2453 LOCAL_ADDR_SPACE);
2454 }
2455
2456 static void preload_constants(struct si_shader_context *si_shader_ctx)
2457 {
2458 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2459 struct gallivm_state * gallivm = bld_base->base.gallivm;
2460 const struct tgsi_shader_info * info = bld_base->info;
2461 unsigned buf;
2462 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2463
2464 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2465 unsigned i, num_const = info->const_file_max[buf] + 1;
2466
2467 if (num_const == 0)
2468 continue;
2469
2470 /* Allocate space for the constant values */
2471 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2472
2473 /* Load the resource descriptor */
2474 si_shader_ctx->const_resource[buf] =
2475 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2476
2477 /* Load the constants, we rely on the code sinking to do the rest */
2478 for (i = 0; i < num_const * 4; ++i) {
2479 si_shader_ctx->constants[buf][i] =
2480 buffer_load_const(gallivm->builder,
2481 si_shader_ctx->const_resource[buf],
2482 lp_build_const_int32(gallivm, i * 4),
2483 bld_base->base.elem_type);
2484 }
2485 }
2486 }
2487
2488 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2489 {
2490 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2491 struct gallivm_state * gallivm = bld_base->base.gallivm;
2492 const struct tgsi_shader_info * info = bld_base->info;
2493
2494 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2495
2496 LLVMValueRef res_ptr, samp_ptr;
2497 LLVMValueRef offset;
2498
2499 if (num_samplers == 0)
2500 return;
2501
2502 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2503 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2504
2505 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2506 for (i = 0; i < num_samplers; ++i) {
2507 /* Resource */
2508 offset = lp_build_const_int32(gallivm, i);
2509 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2510
2511 /* Sampler */
2512 offset = lp_build_const_int32(gallivm, i);
2513 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2514
2515 /* FMASK resource */
2516 if (info->is_msaa_sampler[i]) {
2517 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2518 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2519 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2520 }
2521 }
2522 }
2523
2524 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2525 {
2526 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2527 struct gallivm_state * gallivm = bld_base->base.gallivm;
2528 unsigned i;
2529
2530 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2531 si_shader_ctx->shader->key.vs.as_es ||
2532 !si_shader_ctx->shader->selector->so.num_outputs)
2533 return;
2534
2535 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2536 SI_PARAM_RW_BUFFERS);
2537
2538 /* Load the resources, we rely on the code sinking to do the rest */
2539 for (i = 0; i < 4; ++i) {
2540 if (si_shader_ctx->shader->selector->so.stride[i]) {
2541 LLVMValueRef offset = lp_build_const_int32(gallivm,
2542 SI_SO_BUF_OFFSET + i);
2543
2544 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2545 }
2546 }
2547 }
2548
2549 /**
2550 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2551 * for later use.
2552 */
2553 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2554 {
2555 struct gallivm_state *gallivm =
2556 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2557
2558 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2559 SI_PARAM_RW_BUFFERS);
2560
2561 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2562 si_shader_ctx->shader->key.vs.as_es) ||
2563 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2564 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2565
2566 si_shader_ctx->esgs_ring =
2567 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2568 }
2569
2570 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2571 si_shader_ctx->shader->is_gs_copy_shader) {
2572 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2573
2574 si_shader_ctx->gsvs_ring =
2575 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2576 }
2577 }
2578
2579 void si_shader_binary_read_config(const struct si_screen *sscreen,
2580 struct si_shader *shader,
2581 unsigned symbol_offset)
2582 {
2583 unsigned i;
2584 const unsigned char *config =
2585 radeon_shader_binary_config_start(&shader->binary,
2586 symbol_offset);
2587
2588 /* XXX: We may be able to emit some of these values directly rather than
2589 * extracting fields to be emitted later.
2590 */
2591
2592 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
2593 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2594 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2595 switch (reg) {
2596 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2597 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2598 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2599 case R_00B848_COMPUTE_PGM_RSRC1:
2600 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2601 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2602 shader->float_mode = G_00B028_FLOAT_MODE(value);
2603 break;
2604 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2605 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2606 break;
2607 case R_00B84C_COMPUTE_PGM_RSRC2:
2608 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2609 break;
2610 case R_0286CC_SPI_PS_INPUT_ENA:
2611 shader->spi_ps_input_ena = value;
2612 break;
2613 case R_0286E8_SPI_TMPRING_SIZE:
2614 case R_00B860_COMPUTE_TMPRING_SIZE:
2615 /* WAVESIZE is in units of 256 dwords. */
2616 shader->scratch_bytes_per_wave =
2617 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2618 break;
2619 default:
2620 fprintf(stderr, "Warning: Compiler emitted unknown "
2621 "config register: 0x%x\n", reg);
2622 break;
2623 }
2624 }
2625 }
2626
2627 void si_shader_apply_scratch_relocs(struct si_context *sctx,
2628 struct si_shader *shader,
2629 uint64_t scratch_va)
2630 {
2631 unsigned i;
2632 uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff;
2633 uint32_t scratch_rsrc_dword1 =
2634 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
2635 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
2636
2637 for (i = 0 ; i < shader->binary.reloc_count; i++) {
2638 const struct radeon_shader_reloc *reloc =
2639 &shader->binary.relocs[i];
2640 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
2641 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2642 &scratch_rsrc_dword0, 4);
2643 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
2644 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2645 &scratch_rsrc_dword1, 4);
2646 }
2647 }
2648 }
2649
2650 int si_shader_binary_read(struct si_screen *sscreen,
2651 struct si_shader *shader,
2652 const struct radeon_shader_binary *binary)
2653 {
2654
2655 unsigned i;
2656 unsigned code_size;
2657 unsigned char *ptr;
2658 bool dump = r600_can_dump_shader(&sscreen->b,
2659 shader->selector ? shader->selector->tokens : NULL);
2660
2661 si_shader_binary_read_config(sscreen, shader, 0);
2662
2663 if (dump) {
2664 if (!binary->disassembled) {
2665 fprintf(stderr, "SI CODE:\n");
2666 for (i = 0; i < binary->code_size; i+=4 ) {
2667 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2668 binary->code[i + 2], binary->code[i + 1],
2669 binary->code[i]);
2670 }
2671 }
2672
2673 fprintf(stderr, "*** SHADER STATS ***\n"
2674 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
2675 "Scratch: %d bytes per wave\n********************\n",
2676 shader->num_sgprs, shader->num_vgprs, binary->code_size,
2677 shader->lds_size, shader->scratch_bytes_per_wave);
2678 }
2679
2680 /* copy new shader */
2681 code_size = binary->code_size + binary->rodata_size;
2682 r600_resource_reference(&shader->bo, NULL);
2683 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2684 code_size);
2685 if (shader->bo == NULL) {
2686 return -ENOMEM;
2687 }
2688
2689
2690 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2691 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2692 if (binary->rodata_size > 0) {
2693 ptr += binary->code_size;
2694 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2695 }
2696
2697 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2698
2699 return 0;
2700 }
2701
2702 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2703 LLVMTargetMachineRef tm, LLVMModuleRef mod)
2704 {
2705 int r = 0;
2706 bool dump = r600_can_dump_shader(&sscreen->b,
2707 shader->selector ? shader->selector->tokens : NULL);
2708 r = radeon_llvm_compile(mod, &shader->binary,
2709 r600_get_llvm_processor_name(sscreen->b.family), dump, tm);
2710
2711 if (r) {
2712 return r;
2713 }
2714 r = si_shader_binary_read(sscreen, shader, &shader->binary);
2715
2716 FREE(shader->binary.config);
2717 FREE(shader->binary.rodata);
2718 FREE(shader->binary.global_symbol_offsets);
2719 if (shader->scratch_bytes_per_wave == 0) {
2720 FREE(shader->binary.code);
2721 FREE(shader->binary.relocs);
2722 memset(&shader->binary, 0, sizeof(shader->binary));
2723 }
2724 return r;
2725 }
2726
2727 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2728 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2729 struct si_shader_context *si_shader_ctx,
2730 struct si_shader *gs, bool dump)
2731 {
2732 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2733 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2734 struct lp_build_context *base = &bld_base->base;
2735 struct lp_build_context *uint = &bld_base->uint_bld;
2736 struct si_shader *shader = si_shader_ctx->shader;
2737 struct si_shader_output_values *outputs;
2738 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2739 LLVMValueRef args[9];
2740 int i, r;
2741
2742 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2743
2744 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2745 shader->is_gs_copy_shader = true;
2746
2747 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2748
2749 create_meta_data(si_shader_ctx);
2750 create_function(si_shader_ctx);
2751 preload_streamout_buffers(si_shader_ctx);
2752 preload_ring_buffers(si_shader_ctx);
2753
2754 args[0] = si_shader_ctx->gsvs_ring;
2755 args[1] = lp_build_mul_imm(uint,
2756 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2757 si_shader_ctx->param_vertex_id),
2758 4);
2759 args[3] = uint->zero;
2760 args[4] = uint->one; /* OFFEN */
2761 args[5] = uint->zero; /* IDXEN */
2762 args[6] = uint->one; /* GLC */
2763 args[7] = uint->one; /* SLC */
2764 args[8] = uint->zero; /* TFE */
2765
2766 /* Fetch vertex data from GSVS ring */
2767 for (i = 0; i < gsinfo->num_outputs; ++i) {
2768 unsigned chan;
2769
2770 outputs[i].name = gsinfo->output_semantic_name[i];
2771 outputs[i].sid = gsinfo->output_semantic_index[i];
2772
2773 for (chan = 0; chan < 4; chan++) {
2774 args[2] = lp_build_const_int32(gallivm,
2775 (i * 4 + chan) *
2776 gs->selector->gs_max_out_vertices * 16 * 4);
2777
2778 outputs[i].values[chan] =
2779 LLVMBuildBitCast(gallivm->builder,
2780 build_intrinsic(gallivm->builder,
2781 "llvm.SI.buffer.load.dword.i32.i32",
2782 LLVMInt32TypeInContext(gallivm->context),
2783 args, 9,
2784 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2785 base->elem_type, "");
2786 }
2787 }
2788
2789 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2790
2791 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2792
2793 if (dump)
2794 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2795
2796 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2797 si_shader_ctx->tm, bld_base->base.gallivm->module);
2798
2799 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2800
2801 FREE(outputs);
2802 return r;
2803 }
2804
2805 static void si_dump_key(unsigned shader, union si_shader_key *key)
2806 {
2807 int i;
2808
2809 fprintf(stderr, "SHADER KEY\n");
2810
2811 switch (shader) {
2812 case PIPE_SHADER_VERTEX:
2813 fprintf(stderr, " instance_divisors = {");
2814 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
2815 fprintf(stderr, !i ? "%u" : ", %u",
2816 key->vs.instance_divisors[i]);
2817 fprintf(stderr, "}\n");
2818
2819 if (key->vs.as_es)
2820 fprintf(stderr, " gs_used_inputs = 0x%"PRIx64"\n",
2821 key->vs.gs_used_inputs);
2822 fprintf(stderr, " as_es = %u\n", key->vs.as_es);
2823 break;
2824
2825 case PIPE_SHADER_GEOMETRY:
2826 break;
2827
2828 case PIPE_SHADER_FRAGMENT:
2829 fprintf(stderr, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
2830 fprintf(stderr, " last_cbuf = %u\n", key->ps.last_cbuf);
2831 fprintf(stderr, " color_two_side = %u\n", key->ps.color_two_side);
2832 fprintf(stderr, " alpha_func = %u\n", key->ps.alpha_func);
2833 fprintf(stderr, " alpha_to_one = %u\n", key->ps.alpha_to_one);
2834 fprintf(stderr, " poly_stipple = %u\n", key->ps.poly_stipple);
2835 break;
2836
2837 default:
2838 assert(0);
2839 }
2840 }
2841
2842 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
2843 struct si_shader *shader)
2844 {
2845 struct si_shader_selector *sel = shader->selector;
2846 struct tgsi_token *tokens = sel->tokens;
2847 struct si_shader_context si_shader_ctx;
2848 struct lp_build_tgsi_context * bld_base;
2849 struct tgsi_shader_info stipple_shader_info;
2850 LLVMModuleRef mod;
2851 int r = 0;
2852 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
2853 shader->key.ps.poly_stipple;
2854 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2855
2856 if (poly_stipple) {
2857 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
2858 SI_POLY_STIPPLE_SAMPLER);
2859 tgsi_scan_shader(tokens, &stipple_shader_info);
2860 }
2861
2862 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2863 * conversion fails. */
2864 if (dump) {
2865 si_dump_key(sel->type, &shader->key);
2866 tgsi_dump(tokens, 0);
2867 si_dump_streamout(&sel->so);
2868 }
2869
2870 assert(shader->nparam == 0);
2871
2872 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2873 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2874 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2875
2876 if (sel->type != PIPE_SHADER_COMPUTE)
2877 shader->dx10_clamp_mode = true;
2878
2879 if (sel->info.uses_kill)
2880 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2881
2882 shader->uses_instanceid = sel->info.uses_instanceid;
2883 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
2884 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2885
2886 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2887 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2888 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2889 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2890 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2891 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2892 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2893 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2894 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2895 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2896 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2897 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2898
2899 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2900 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2901
2902 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2903 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2904
2905 if (HAVE_LLVM >= 0x0306) {
2906 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2907 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2908 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2909 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2910 }
2911
2912 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2913 si_shader_ctx.shader = shader;
2914 si_shader_ctx.type = tgsi_get_processor_type(tokens);
2915 si_shader_ctx.screen = sscreen;
2916 si_shader_ctx.tm = tm;
2917
2918 switch (si_shader_ctx.type) {
2919 case TGSI_PROCESSOR_VERTEX:
2920 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2921 if (shader->key.vs.as_es) {
2922 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2923 } else {
2924 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2925 }
2926 break;
2927 case TGSI_PROCESSOR_GEOMETRY:
2928 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2929 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2930 break;
2931 case TGSI_PROCESSOR_FRAGMENT:
2932 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2933 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2934
2935 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2936 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2937 shader->db_shader_control |=
2938 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2939 break;
2940 case TGSI_FS_DEPTH_LAYOUT_LESS:
2941 shader->db_shader_control |=
2942 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2943 break;
2944 }
2945 break;
2946 default:
2947 assert(!"Unsupported shader type");
2948 return -1;
2949 }
2950
2951 create_meta_data(&si_shader_ctx);
2952 create_function(&si_shader_ctx);
2953 preload_constants(&si_shader_ctx);
2954 preload_samplers(&si_shader_ctx);
2955 preload_streamout_buffers(&si_shader_ctx);
2956 preload_ring_buffers(&si_shader_ctx);
2957
2958 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2959 si_shader_ctx.gs_next_vertex =
2960 lp_build_alloca(bld_base->base.gallivm,
2961 bld_base->uint_bld.elem_type, "");
2962 }
2963
2964 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
2965 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2966 goto out;
2967 }
2968
2969 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2970
2971 mod = bld_base->base.gallivm->module;
2972 r = si_compile_llvm(sscreen, shader, tm, mod);
2973 if (r) {
2974 fprintf(stderr, "LLVM failed to compile shader\n");
2975 goto out;
2976 }
2977
2978 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2979
2980 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2981 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2982 shader->gs_copy_shader->selector = shader->selector;
2983 shader->gs_copy_shader->key = shader->key;
2984 si_shader_ctx.shader = shader->gs_copy_shader;
2985 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2986 shader, dump))) {
2987 free(shader->gs_copy_shader);
2988 shader->gs_copy_shader = NULL;
2989 goto out;
2990 }
2991 }
2992
2993 out:
2994 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2995 FREE(si_shader_ctx.constants[i]);
2996 if (poly_stipple)
2997 tgsi_free_tokens(tokens);
2998 return r;
2999 }
3000
3001 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
3002 {
3003 if (shader->gs_copy_shader)
3004 si_shader_destroy(ctx, shader->gs_copy_shader);
3005
3006 if (shader->scratch_bo)
3007 r600_resource_reference(&shader->scratch_bo, NULL);
3008
3009 r600_resource_reference(&shader->bo, NULL);
3010
3011 FREE(shader->binary.code);
3012 FREE(shader->binary.relocs);
3013 }