2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "gallivm/lp_bld_misc.h"
37 #include "radeon/r600_cs.h"
38 #include "radeon/radeon_llvm.h"
39 #include "radeon/radeon_elf_util.h"
40 #include "radeon/radeon_llvm_emit.h"
41 #include "util/u_memory.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
49 #include "si_shader.h"
54 static const char *scratch_rsrc_dword0_symbol
=
55 "SCRATCH_RSRC_DWORD0";
57 static const char *scratch_rsrc_dword1_symbol
=
58 "SCRATCH_RSRC_DWORD1";
60 struct si_shader_output_values
62 LLVMValueRef values
[4];
67 struct si_shader_context
69 struct radeon_llvm_context radeon_bld
;
70 struct si_shader
*shader
;
71 struct si_screen
*screen
;
73 unsigned type
; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader
;
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
81 int param_streamout_config
;
82 int param_streamout_write_index
;
83 int param_streamout_offset
[4];
85 int param_rel_auto_id
;
87 int param_instance_id
;
88 int param_vertex_index0
;
91 int param_tes_rel_patch_id
;
92 int param_tes_patch_id
;
93 int param_es2gs_offset
;
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
99 int param_tess_offchip
;
101 LLVMTargetMachineRef tm
;
103 unsigned invariant_load_md_kind
;
104 unsigned range_md_kind
;
105 unsigned uniform_md_kind
;
106 LLVMValueRef empty_md
;
108 LLVMValueRef const_buffers
[SI_NUM_CONST_BUFFERS
];
110 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
111 LLVMValueRef shader_buffers
[SI_NUM_SHADER_BUFFERS
];
112 LLVMValueRef sampler_views
[SI_NUM_SAMPLERS
];
113 LLVMValueRef sampler_states
[SI_NUM_SAMPLERS
];
114 LLVMValueRef fmasks
[SI_NUM_SAMPLERS
];
115 LLVMValueRef images
[SI_NUM_IMAGES
];
116 LLVMValueRef so_buffers
[4];
117 LLVMValueRef esgs_ring
;
118 LLVMValueRef gsvs_ring
[4];
119 LLVMValueRef gs_next_vertex
[4];
120 LLVMValueRef return_value
;
135 LLVMValueRef shared_memory
;
138 static struct si_shader_context
*si_shader_context(
139 struct lp_build_tgsi_context
*bld_base
)
141 return (struct si_shader_context
*)bld_base
;
144 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
145 struct si_screen
*sscreen
,
146 struct si_shader
*shader
,
147 LLVMTargetMachineRef tm
);
149 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
150 struct lp_build_tgsi_context
*bld_base
,
151 struct lp_build_emit_data
*emit_data
);
153 static void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
,
156 /* Ideally pass the sample mask input to the PS epilog as v13, which
157 * is its usual location, so that the shader doesn't have to add v_mov.
159 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
161 /* The VS location of the PrimitiveID input is the same in the epilog,
162 * so that the main shader part doesn't have to move it.
164 #define VS_EPILOG_PRIMID_LOC 2
166 #define PERSPECTIVE_BASE 0
167 #define LINEAR_BASE 9
169 #define SAMPLE_OFFSET 0
170 #define CENTER_OFFSET 2
171 #define CENTROID_OFSET 4
173 #define USE_SGPR_MAX_SUFFIX_LEN 5
174 #define CONST_ADDR_SPACE 2
175 #define LOCAL_ADDR_SPACE 3
176 #define USER_SGPR_ADDR_SPACE 8
180 #define SENDMSG_GS_DONE 3
182 #define SENDMSG_GS_OP_NOP (0 << 4)
183 #define SENDMSG_GS_OP_CUT (1 << 4)
184 #define SENDMSG_GS_OP_EMIT (2 << 4)
185 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
188 * Returns a unique index for a semantic name and index. The index must be
189 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
192 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
194 switch (semantic_name
) {
195 case TGSI_SEMANTIC_POSITION
:
197 case TGSI_SEMANTIC_PSIZE
:
199 case TGSI_SEMANTIC_CLIPDIST
:
202 case TGSI_SEMANTIC_GENERIC
:
206 /* same explanation as in the default statement,
207 * the only user hitting this is st/nine.
211 /* patch indices are completely separate and thus start from 0 */
212 case TGSI_SEMANTIC_TESSOUTER
:
214 case TGSI_SEMANTIC_TESSINNER
:
216 case TGSI_SEMANTIC_PATCH
:
220 /* Don't fail here. The result of this function is only used
221 * for LS, TCS, TES, and GS, where legacy GL semantics can't
222 * occur, but this function is called for all vertex shaders
223 * before it's known whether LS will be compiled or not.
230 * Get the value of a shader input parameter and extract a bitfield.
232 static LLVMValueRef
unpack_param(struct si_shader_context
*ctx
,
233 unsigned param
, unsigned rshift
,
236 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
237 LLVMValueRef value
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
240 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
241 value
= bitcast(&ctx
->radeon_bld
.soa
.bld_base
,
242 TGSI_TYPE_UNSIGNED
, value
);
245 value
= LLVMBuildLShr(gallivm
->builder
, value
,
246 lp_build_const_int32(gallivm
, rshift
), "");
248 if (rshift
+ bitwidth
< 32) {
249 unsigned mask
= (1 << bitwidth
) - 1;
250 value
= LLVMBuildAnd(gallivm
->builder
, value
,
251 lp_build_const_int32(gallivm
, mask
), "");
257 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
260 case PIPE_SHADER_TESS_CTRL
:
261 return unpack_param(ctx
, SI_PARAM_REL_IDS
, 0, 8);
263 case PIPE_SHADER_TESS_EVAL
:
264 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
265 ctx
->param_tes_rel_patch_id
);
273 /* Tessellation shaders pass outputs to the next shader using LDS.
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
295 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
297 if (ctx
->type
== PIPE_SHADER_VERTEX
)
298 return unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 0, 13);
299 else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
300 return unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 0, 13);
308 get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
310 return unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 0, 13);
314 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
316 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
318 SI_PARAM_TCS_OUT_OFFSETS
,
324 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
326 return lp_build_mul_imm(&ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
328 SI_PARAM_TCS_OUT_OFFSETS
,
334 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
336 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
337 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
338 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
340 return LLVMBuildMul(gallivm
->builder
, patch_stride
, rel_patch_id
, "");
344 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
346 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
347 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
348 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
349 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
351 return LLVMBuildAdd(gallivm
->builder
, patch0_offset
,
352 LLVMBuildMul(gallivm
->builder
, patch_stride
,
358 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
360 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
361 LLVMValueRef patch0_patch_data_offset
=
362 get_tcs_out_patch0_patch_data_offset(ctx
);
363 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
364 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
366 return LLVMBuildAdd(gallivm
->builder
, patch0_patch_data_offset
,
367 LLVMBuildMul(gallivm
->builder
, patch_stride
,
372 static void build_indexed_store(struct si_shader_context
*ctx
,
373 LLVMValueRef base_ptr
, LLVMValueRef index
,
376 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
377 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
378 LLVMValueRef indices
[2], pointer
;
380 indices
[0] = bld_base
->uint_bld
.zero
;
383 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
384 LLVMBuildStore(gallivm
->builder
, value
, pointer
);
388 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
389 * It's equivalent to doing a load from &base_ptr[index].
391 * \param base_ptr Where the array starts.
392 * \param index The element index into the array.
393 * \param uniform Whether the base_ptr and index can be assumed to be
394 * dynamically uniform
396 static LLVMValueRef
build_indexed_load(struct si_shader_context
*ctx
,
397 LLVMValueRef base_ptr
, LLVMValueRef index
,
400 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
401 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
402 LLVMValueRef indices
[2], pointer
;
404 indices
[0] = bld_base
->uint_bld
.zero
;
407 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
409 LLVMSetMetadata(pointer
, ctx
->uniform_md_kind
, ctx
->empty_md
);
410 return LLVMBuildLoad(gallivm
->builder
, pointer
, "");
414 * Do a load from &base_ptr[index], but also add a flag that it's loading
415 * a constant from a dynamically uniform index.
417 static LLVMValueRef
build_indexed_load_const(
418 struct si_shader_context
*ctx
,
419 LLVMValueRef base_ptr
, LLVMValueRef index
)
421 LLVMValueRef result
= build_indexed_load(ctx
, base_ptr
, index
, true);
422 LLVMSetMetadata(result
, ctx
->invariant_load_md_kind
, ctx
->empty_md
);
426 static LLVMValueRef
get_instance_index_for_fetch(
427 struct radeon_llvm_context
*radeon_bld
,
428 unsigned param_start_instance
, unsigned divisor
)
430 struct si_shader_context
*ctx
=
431 si_shader_context(&radeon_bld
->soa
.bld_base
);
432 struct gallivm_state
*gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
434 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
435 ctx
->param_instance_id
);
437 /* The division must be done before START_INSTANCE is added. */
439 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
440 lp_build_const_int32(gallivm
, divisor
), "");
442 return LLVMBuildAdd(gallivm
->builder
, result
,
443 LLVMGetParam(radeon_bld
->main_fn
, param_start_instance
), "");
446 static void declare_input_vs(
447 struct radeon_llvm_context
*radeon_bld
,
448 unsigned input_index
,
449 const struct tgsi_full_declaration
*decl
)
451 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
452 struct gallivm_state
*gallivm
= base
->gallivm
;
453 struct si_shader_context
*ctx
=
454 si_shader_context(&radeon_bld
->soa
.bld_base
);
456 ctx
->shader
->key
.vs
.prolog
.instance_divisors
[input_index
];
460 LLVMValueRef t_list_ptr
;
461 LLVMValueRef t_offset
;
463 LLVMValueRef attribute_offset
;
464 LLVMValueRef buffer_index
;
465 LLVMValueRef args
[3];
468 /* Load the T list */
469 t_list_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFERS
);
471 t_offset
= lp_build_const_int32(gallivm
, input_index
);
473 t_list
= build_indexed_load_const(ctx
, t_list_ptr
, t_offset
);
475 /* Build the attribute offset */
476 attribute_offset
= lp_build_const_int32(gallivm
, 0);
478 if (!ctx
->is_monolithic
) {
479 buffer_index
= LLVMGetParam(radeon_bld
->main_fn
,
480 ctx
->param_vertex_index0
+
482 } else if (divisor
) {
483 /* Build index from instance ID, start instance and divisor */
484 ctx
->shader
->info
.uses_instanceid
= true;
485 buffer_index
= get_instance_index_for_fetch(&ctx
->radeon_bld
,
486 SI_PARAM_START_INSTANCE
,
489 /* Load the buffer index for vertices. */
490 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
491 ctx
->param_vertex_id
);
492 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
493 SI_PARAM_BASE_VERTEX
);
494 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
498 args
[1] = attribute_offset
;
499 args
[2] = buffer_index
;
500 input
= lp_build_intrinsic(gallivm
->builder
,
501 "llvm.SI.vs.load.input", ctx
->v4f32
, args
, 3,
502 LLVMReadNoneAttribute
);
504 /* Break up the vec4 into individual components */
505 for (chan
= 0; chan
< 4; chan
++) {
506 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
507 /* XXX: Use a helper function for this. There is one in
509 ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
510 LLVMBuildExtractElement(gallivm
->builder
,
511 input
, llvm_chan
, "");
515 static LLVMValueRef
get_primitive_id(struct lp_build_tgsi_context
*bld_base
,
518 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
521 return bld_base
->uint_bld
.zero
;
524 case PIPE_SHADER_VERTEX
:
525 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
526 ctx
->param_vs_prim_id
);
527 case PIPE_SHADER_TESS_CTRL
:
528 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
530 case PIPE_SHADER_TESS_EVAL
:
531 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
532 ctx
->param_tes_patch_id
);
533 case PIPE_SHADER_GEOMETRY
:
534 return LLVMGetParam(ctx
->radeon_bld
.main_fn
,
535 SI_PARAM_PRIMITIVE_ID
);
538 return bld_base
->uint_bld
.zero
;
543 * Return the value of tgsi_ind_register for indexing.
544 * This is the indirect index with the constant offset added to it.
546 static LLVMValueRef
get_indirect_index(struct si_shader_context
*ctx
,
547 const struct tgsi_ind_register
*ind
,
550 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
553 result
= ctx
->radeon_bld
.soa
.addr
[ind
->Index
][ind
->Swizzle
];
554 result
= LLVMBuildLoad(gallivm
->builder
, result
, "");
555 result
= LLVMBuildAdd(gallivm
->builder
, result
,
556 lp_build_const_int32(gallivm
, rel_index
), "");
561 * Like get_indirect_index, but restricts the return value to a (possibly
562 * undefined) value inside [0..num).
564 static LLVMValueRef
get_bounded_indirect_index(struct si_shader_context
*ctx
,
565 const struct tgsi_ind_register
*ind
,
566 int rel_index
, unsigned num
)
568 LLVMValueRef result
= get_indirect_index(ctx
, ind
, rel_index
);
570 /* LLVM 3.8: If indirect resource indexing is used:
574 if (HAVE_LLVM
<= 0x0308)
575 return LLVMGetUndef(ctx
->i32
);
577 return radeon_llvm_bound_index(&ctx
->radeon_bld
, result
, num
);
582 * Calculate a dword address given an input or output register and a stride.
584 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
585 const struct tgsi_full_dst_register
*dst
,
586 const struct tgsi_full_src_register
*src
,
587 LLVMValueRef vertex_dw_stride
,
588 LLVMValueRef base_addr
)
590 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
591 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
592 ubyte
*name
, *index
, *array_first
;
594 struct tgsi_full_dst_register reg
;
596 /* Set the register description. The address computation is the same
597 * for sources and destinations. */
599 reg
.Register
.File
= src
->Register
.File
;
600 reg
.Register
.Index
= src
->Register
.Index
;
601 reg
.Register
.Indirect
= src
->Register
.Indirect
;
602 reg
.Register
.Dimension
= src
->Register
.Dimension
;
603 reg
.Indirect
= src
->Indirect
;
604 reg
.Dimension
= src
->Dimension
;
605 reg
.DimIndirect
= src
->DimIndirect
;
609 /* If the register is 2-dimensional (e.g. an array of vertices
610 * in a primitive), calculate the base address of the vertex. */
611 if (reg
.Register
.Dimension
) {
614 if (reg
.Dimension
.Indirect
)
615 index
= get_indirect_index(ctx
, ®
.DimIndirect
,
616 reg
.Dimension
.Index
);
618 index
= lp_build_const_int32(gallivm
, reg
.Dimension
.Index
);
620 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
621 LLVMBuildMul(gallivm
->builder
, index
,
622 vertex_dw_stride
, ""), "");
625 /* Get information about the register. */
626 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
627 name
= info
->input_semantic_name
;
628 index
= info
->input_semantic_index
;
629 array_first
= info
->input_array_first
;
630 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
631 name
= info
->output_semantic_name
;
632 index
= info
->output_semantic_index
;
633 array_first
= info
->output_array_first
;
639 if (reg
.Register
.Indirect
) {
640 /* Add the relative address of the element. */
641 LLVMValueRef ind_index
;
643 if (reg
.Indirect
.ArrayID
)
644 first
= array_first
[reg
.Indirect
.ArrayID
];
646 first
= reg
.Register
.Index
;
648 ind_index
= get_indirect_index(ctx
, ®
.Indirect
,
649 reg
.Register
.Index
- first
);
651 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
652 LLVMBuildMul(gallivm
->builder
, ind_index
,
653 lp_build_const_int32(gallivm
, 4), ""), "");
655 param
= si_shader_io_get_unique_index(name
[first
], index
[first
]);
657 param
= si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
658 index
[reg
.Register
.Index
]);
661 /* Add the base address of the element. */
662 return LLVMBuildAdd(gallivm
->builder
, base_addr
,
663 lp_build_const_int32(gallivm
, param
* 4), "");
666 /* The offchip buffer layout for TCS->TES is
668 * - attribute 0 of patch 0 vertex 0
669 * - attribute 0 of patch 0 vertex 1
670 * - attribute 0 of patch 0 vertex 2
672 * - attribute 0 of patch 1 vertex 0
673 * - attribute 0 of patch 1 vertex 1
675 * - attribute 1 of patch 0 vertex 0
676 * - attribute 1 of patch 0 vertex 1
678 * - per patch attribute 0 of patch 0
679 * - per patch attribute 0 of patch 1
682 * Note that every attribute has 4 components.
684 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
685 LLVMValueRef vertex_index
,
686 LLVMValueRef param_index
)
688 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
689 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
690 LLVMValueRef param_stride
, constant16
;
692 vertices_per_patch
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 9, 6);
693 num_patches
= unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 0, 9);
694 total_vertices
= LLVMBuildMul(gallivm
->builder
, vertices_per_patch
,
697 constant16
= lp_build_const_int32(gallivm
, 16);
699 base_addr
= LLVMBuildMul(gallivm
->builder
, get_rel_patch_id(ctx
),
700 vertices_per_patch
, "");
702 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
705 param_stride
= total_vertices
;
707 base_addr
= get_rel_patch_id(ctx
);
708 param_stride
= num_patches
;
711 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
712 LLVMBuildMul(gallivm
->builder
, param_index
,
713 param_stride
, ""), "");
715 base_addr
= LLVMBuildMul(gallivm
->builder
, base_addr
, constant16
, "");
718 LLVMValueRef patch_data_offset
=
719 unpack_param(ctx
, SI_PARAM_TCS_OFFCHIP_LAYOUT
, 16, 16);
721 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
722 patch_data_offset
, "");
727 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
728 struct si_shader_context
*ctx
,
729 const struct tgsi_full_dst_register
*dst
,
730 const struct tgsi_full_src_register
*src
)
732 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
733 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
734 ubyte
*name
, *index
, *array_first
;
735 struct tgsi_full_src_register reg
;
736 LLVMValueRef vertex_index
= NULL
;
737 LLVMValueRef param_index
= NULL
;
738 unsigned param_index_base
, param_base
;
740 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
742 if (reg
.Register
.Dimension
) {
744 if (reg
.Dimension
.Indirect
)
745 vertex_index
= get_indirect_index(ctx
, ®
.DimIndirect
,
746 reg
.Dimension
.Index
);
748 vertex_index
= lp_build_const_int32(gallivm
,
749 reg
.Dimension
.Index
);
752 /* Get information about the register. */
753 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
754 name
= info
->input_semantic_name
;
755 index
= info
->input_semantic_index
;
756 array_first
= info
->input_array_first
;
757 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
758 name
= info
->output_semantic_name
;
759 index
= info
->output_semantic_index
;
760 array_first
= info
->output_array_first
;
766 if (reg
.Register
.Indirect
) {
767 if (reg
.Indirect
.ArrayID
)
768 param_base
= array_first
[reg
.Indirect
.ArrayID
];
770 param_base
= reg
.Register
.Index
;
772 param_index
= get_indirect_index(ctx
, ®
.Indirect
,
773 reg
.Register
.Index
- param_base
);
776 param_base
= reg
.Register
.Index
;
777 param_index
= lp_build_const_int32(gallivm
, 0);
780 param_index_base
= si_shader_io_get_unique_index(name
[param_base
],
783 param_index
= LLVMBuildAdd(gallivm
->builder
, param_index
,
784 lp_build_const_int32(gallivm
, param_index_base
),
787 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
790 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
791 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
792 * or v4i32 (num_channels=3,4). */
793 static void build_tbuffer_store(struct si_shader_context
*ctx
,
796 unsigned num_channels
,
798 LLVMValueRef soffset
,
799 unsigned inst_offset
,
808 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
809 LLVMValueRef args
[] = {
812 LLVMConstInt(ctx
->i32
, num_channels
, 0),
815 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
816 LLVMConstInt(ctx
->i32
, dfmt
, 0),
817 LLVMConstInt(ctx
->i32
, nfmt
, 0),
818 LLVMConstInt(ctx
->i32
, offen
, 0),
819 LLVMConstInt(ctx
->i32
, idxen
, 0),
820 LLVMConstInt(ctx
->i32
, glc
, 0),
821 LLVMConstInt(ctx
->i32
, slc
, 0),
822 LLVMConstInt(ctx
->i32
, tfe
, 0)
825 /* The instruction offset field has 12 bits */
826 assert(offen
|| inst_offset
< (1 << 12));
828 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
829 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
830 const char *types
[] = {"i32", "v2i32", "v4i32"};
832 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
834 lp_build_intrinsic(gallivm
->builder
, name
, ctx
->voidt
,
835 args
, ARRAY_SIZE(args
), 0);
838 static void build_tbuffer_store_dwords(struct si_shader_context
*ctx
,
841 unsigned num_channels
,
843 LLVMValueRef soffset
,
844 unsigned inst_offset
)
846 static unsigned dfmt
[] = {
847 V_008F0C_BUF_DATA_FORMAT_32
,
848 V_008F0C_BUF_DATA_FORMAT_32_32
,
849 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
850 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
852 assert(num_channels
>= 1 && num_channels
<= 4);
854 build_tbuffer_store(ctx
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
855 inst_offset
, dfmt
[num_channels
-1],
856 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
859 static LLVMValueRef
build_buffer_load(struct si_shader_context
*ctx
,
863 LLVMValueRef voffset
,
864 LLVMValueRef soffset
,
865 unsigned inst_offset
,
869 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
870 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
872 if (HAVE_LLVM
>= 0x309) {
873 LLVMValueRef args
[] = {
874 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, ""),
875 vindex
? vindex
: LLVMConstInt(ctx
->i32
, 0, 0),
876 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
877 LLVMConstInt(ctx
->i1
, glc
, 0),
878 LLVMConstInt(ctx
->i1
, slc
, 0)
881 LLVMTypeRef types
[] = {ctx
->f32
, LLVMVectorType(ctx
->f32
, 2),
883 const char *type_names
[] = {"f32", "v2f32", "v4f32"};
887 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], voffset
,
892 args
[2] = LLVMBuildAdd(gallivm
->builder
, args
[2], soffset
,
896 snprintf(name
, sizeof(name
), "llvm.amdgcn.buffer.load.%s",
899 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
900 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
902 LLVMValueRef args
[] = {
903 LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v16i8
, ""),
904 voffset
? voffset
: vindex
,
906 LLVMConstInt(ctx
->i32
, inst_offset
, 0),
907 LLVMConstInt(ctx
->i32
, voffset
? 1 : 0, 0), // offen
908 LLVMConstInt(ctx
->i32
, vindex
? 1 : 0, 0), //idxen
909 LLVMConstInt(ctx
->i32
, glc
, 0),
910 LLVMConstInt(ctx
->i32
, slc
, 0),
911 LLVMConstInt(ctx
->i32
, 0, 0), // TFE
914 LLVMTypeRef types
[] = {ctx
->i32
, LLVMVectorType(ctx
->i32
, 2),
916 const char *type_names
[] = {"i32", "v2i32", "v4i32"};
917 const char *arg_type
= "i32";
920 if (voffset
&& vindex
) {
921 LLVMValueRef vaddr
[] = {vindex
, voffset
};
924 args
[1] = lp_build_gather_values(gallivm
, vaddr
, 2);
927 snprintf(name
, sizeof(name
), "llvm.SI.buffer.load.dword.%s.%s",
928 type_names
[func
], arg_type
);
930 return lp_build_intrinsic(gallivm
->builder
, name
, types
[func
], args
,
931 ARRAY_SIZE(args
), LLVMReadOnlyAttribute
);
935 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
936 enum tgsi_opcode_type type
, unsigned swizzle
,
937 LLVMValueRef buffer
, LLVMValueRef offset
,
940 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
941 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
942 LLVMValueRef value
, value2
;
943 LLVMTypeRef llvm_type
= tgsi2llvmtype(bld_base
, type
);
944 LLVMTypeRef vec_type
= LLVMVectorType(llvm_type
, 4);
947 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
950 return LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
953 if (!tgsi_type_is_64bit(type
)) {
954 value
= build_buffer_load(ctx
, buffer
, 4, NULL
, base
, offset
,
957 value
= LLVMBuildBitCast(gallivm
->builder
, value
, vec_type
, "");
958 return LLVMBuildExtractElement(gallivm
->builder
, value
,
959 lp_build_const_int32(gallivm
, swizzle
), "");
962 value
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
965 value2
= build_buffer_load(ctx
, buffer
, 1, NULL
, base
, offset
,
966 swizzle
* 4 + 4, 1, 0);
968 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
974 * \param type output value type
975 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
976 * \param dw_addr address in dwords
978 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
979 enum tgsi_opcode_type type
, unsigned swizzle
,
980 LLVMValueRef dw_addr
)
982 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
983 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
987 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
989 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
990 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
992 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
996 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
997 lp_build_const_int32(gallivm
, swizzle
));
999 value
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1000 if (tgsi_type_is_64bit(type
)) {
1001 LLVMValueRef value2
;
1002 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1003 lp_build_const_int32(gallivm
, swizzle
+ 1));
1004 value2
= build_indexed_load(ctx
, ctx
->lds
, dw_addr
, false);
1005 return radeon_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1008 return LLVMBuildBitCast(gallivm
->builder
, value
,
1009 tgsi2llvmtype(bld_base
, type
), "");
1015 * \param swizzle offset (typically 0..3)
1016 * \param dw_addr address in dwords
1017 * \param value value to store
1019 static void lds_store(struct lp_build_tgsi_context
*bld_base
,
1020 unsigned swizzle
, LLVMValueRef dw_addr
,
1023 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1024 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1026 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
1027 lp_build_const_int32(gallivm
, swizzle
));
1029 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1030 build_indexed_store(ctx
, ctx
->lds
,
1034 static LLVMValueRef
fetch_input_tcs(
1035 struct lp_build_tgsi_context
*bld_base
,
1036 const struct tgsi_full_src_register
*reg
,
1037 enum tgsi_opcode_type type
, unsigned swizzle
)
1039 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1040 LLVMValueRef dw_addr
, stride
;
1042 stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
1043 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1044 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1046 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1049 static LLVMValueRef
fetch_output_tcs(
1050 struct lp_build_tgsi_context
*bld_base
,
1051 const struct tgsi_full_src_register
*reg
,
1052 enum tgsi_opcode_type type
, unsigned swizzle
)
1054 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1055 LLVMValueRef dw_addr
, stride
;
1057 if (reg
->Register
.Dimension
) {
1058 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1059 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1060 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1062 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1063 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1066 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
1069 static LLVMValueRef
fetch_input_tes(
1070 struct lp_build_tgsi_context
*bld_base
,
1071 const struct tgsi_full_src_register
*reg
,
1072 enum tgsi_opcode_type type
, unsigned swizzle
)
1074 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1075 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1076 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1078 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1079 SI_PARAM_RW_BUFFERS
);
1080 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1081 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1083 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1084 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1086 return buffer_load(bld_base
, type
, swizzle
, buffer
, base
, addr
);
1089 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1090 const struct tgsi_full_instruction
*inst
,
1091 const struct tgsi_opcode_info
*info
,
1092 LLVMValueRef dst
[4])
1094 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1095 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1096 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
1097 unsigned chan_index
;
1098 LLVMValueRef dw_addr
, stride
;
1099 LLVMValueRef rw_buffers
, buffer
, base
, buf_addr
;
1100 LLVMValueRef values
[4];
1102 /* Only handle per-patch and per-vertex outputs here.
1103 * Vectors will be lowered to scalars and this function will be called again.
1105 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1106 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1107 radeon_llvm_emit_store(bld_base
, inst
, info
, dst
);
1111 if (reg
->Register
.Dimension
) {
1112 stride
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
1113 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1114 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1116 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1117 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1120 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1121 SI_PARAM_RW_BUFFERS
);
1122 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1123 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1125 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1126 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1129 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan_index
) {
1130 LLVMValueRef value
= dst
[chan_index
];
1132 if (inst
->Instruction
.Saturate
)
1133 value
= radeon_llvm_saturate(bld_base
, value
);
1135 lds_store(bld_base
, chan_index
, dw_addr
, value
);
1137 value
= LLVMBuildBitCast(gallivm
->builder
, value
, ctx
->i32
, "");
1138 values
[chan_index
] = value
;
1140 if (inst
->Dst
[0].Register
.WriteMask
!= 0xF) {
1141 build_tbuffer_store_dwords(ctx
, buffer
, value
, 1,
1147 if (inst
->Dst
[0].Register
.WriteMask
== 0xF) {
1148 LLVMValueRef value
= lp_build_gather_values(bld_base
->base
.gallivm
,
1150 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buf_addr
,
1155 static LLVMValueRef
fetch_input_gs(
1156 struct lp_build_tgsi_context
*bld_base
,
1157 const struct tgsi_full_src_register
*reg
,
1158 enum tgsi_opcode_type type
,
1161 struct lp_build_context
*base
= &bld_base
->base
;
1162 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1163 struct si_shader
*shader
= ctx
->shader
;
1164 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1165 struct gallivm_state
*gallivm
= base
->gallivm
;
1166 LLVMValueRef vtx_offset
;
1167 LLVMValueRef args
[9];
1168 unsigned vtx_offset_param
;
1169 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1170 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1171 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
1175 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1176 return get_primitive_id(bld_base
, swizzle
);
1178 if (!reg
->Register
.Dimension
)
1181 if (swizzle
== ~0) {
1182 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1184 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1185 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
1187 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
1191 /* Get the vertex offset parameter */
1192 vtx_offset_param
= reg
->Dimension
.Index
;
1193 if (vtx_offset_param
< 2) {
1194 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
1196 assert(vtx_offset_param
< 6);
1197 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
1199 vtx_offset
= lp_build_mul_imm(uint
,
1200 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1204 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
1205 args
[0] = ctx
->esgs_ring
;
1206 args
[1] = vtx_offset
;
1207 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
) * 256);
1208 args
[3] = uint
->zero
;
1209 args
[4] = uint
->one
; /* OFFEN */
1210 args
[5] = uint
->zero
; /* IDXEN */
1211 args
[6] = uint
->one
; /* GLC */
1212 args
[7] = uint
->zero
; /* SLC */
1213 args
[8] = uint
->zero
; /* TFE */
1215 value
= lp_build_intrinsic(gallivm
->builder
,
1216 "llvm.SI.buffer.load.dword.i32.i32",
1218 LLVMReadOnlyAttribute
);
1219 if (tgsi_type_is_64bit(type
)) {
1220 LLVMValueRef value2
;
1221 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
+ 1) * 256);
1222 value2
= lp_build_intrinsic(gallivm
->builder
,
1223 "llvm.SI.buffer.load.dword.i32.i32",
1225 LLVMReadOnlyAttribute
);
1226 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1229 return LLVMBuildBitCast(gallivm
->builder
,
1231 tgsi2llvmtype(bld_base
, type
), "");
1234 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1236 switch (interpolate
) {
1237 case TGSI_INTERPOLATE_CONSTANT
:
1240 case TGSI_INTERPOLATE_LINEAR
:
1241 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1242 return SI_PARAM_LINEAR_SAMPLE
;
1243 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1244 return SI_PARAM_LINEAR_CENTROID
;
1246 return SI_PARAM_LINEAR_CENTER
;
1248 case TGSI_INTERPOLATE_COLOR
:
1249 case TGSI_INTERPOLATE_PERSPECTIVE
:
1250 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1251 return SI_PARAM_PERSP_SAMPLE
;
1252 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1253 return SI_PARAM_PERSP_CENTROID
;
1255 return SI_PARAM_PERSP_CENTER
;
1258 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1263 /* This shouldn't be used by explicit INTERP opcodes. */
1264 static unsigned select_interp_param(struct si_shader_context
*ctx
,
1267 if (!ctx
->is_monolithic
)
1270 if (ctx
->shader
->key
.ps
.prolog
.force_persp_sample_interp
) {
1272 case SI_PARAM_PERSP_CENTROID
:
1273 case SI_PARAM_PERSP_CENTER
:
1274 return SI_PARAM_PERSP_SAMPLE
;
1277 if (ctx
->shader
->key
.ps
.prolog
.force_linear_sample_interp
) {
1279 case SI_PARAM_LINEAR_CENTROID
:
1280 case SI_PARAM_LINEAR_CENTER
:
1281 return SI_PARAM_LINEAR_SAMPLE
;
1284 if (ctx
->shader
->key
.ps
.prolog
.force_persp_center_interp
) {
1286 case SI_PARAM_PERSP_CENTROID
:
1287 case SI_PARAM_PERSP_SAMPLE
:
1288 return SI_PARAM_PERSP_CENTER
;
1291 if (ctx
->shader
->key
.ps
.prolog
.force_linear_center_interp
) {
1293 case SI_PARAM_LINEAR_CENTROID
:
1294 case SI_PARAM_LINEAR_SAMPLE
:
1295 return SI_PARAM_LINEAR_CENTER
;
1303 * Interpolate a fragment shader input.
1305 * @param ctx context
1306 * @param input_index index of the input in hardware
1307 * @param semantic_name TGSI_SEMANTIC_*
1308 * @param semantic_index semantic index
1309 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1310 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1311 * @param interp_param interpolation weights (i,j)
1312 * @param prim_mask SI_PARAM_PRIM_MASK
1313 * @param face SI_PARAM_FRONT_FACE
1314 * @param result the return value (4 components)
1316 static void interp_fs_input(struct si_shader_context
*ctx
,
1317 unsigned input_index
,
1318 unsigned semantic_name
,
1319 unsigned semantic_index
,
1320 unsigned num_interp_inputs
,
1321 unsigned colors_read_mask
,
1322 LLVMValueRef interp_param
,
1323 LLVMValueRef prim_mask
,
1325 LLVMValueRef result
[4])
1327 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
1328 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1329 struct gallivm_state
*gallivm
= base
->gallivm
;
1330 const char *intr_name
;
1331 LLVMValueRef attr_number
;
1335 attr_number
= lp_build_const_int32(gallivm
, input_index
);
1337 /* fs.constant returns the param from the middle vertex, so it's not
1338 * really useful for flat shading. It's meant to be used for custom
1339 * interpolation (but the intrinsic can't fetch from the other two
1342 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1343 * to do the right thing. The only reason we use fs.constant is that
1344 * fs.interp cannot be used on integers, because they can be equal
1347 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1349 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1350 ctx
->shader
->key
.ps
.prolog
.color_two_side
) {
1351 LLVMValueRef args
[4];
1352 LLVMValueRef is_face_positive
;
1353 LLVMValueRef back_attr_number
;
1355 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1356 * otherwise it's at offset "num_inputs".
1358 unsigned back_attr_offset
= num_interp_inputs
;
1359 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1360 back_attr_offset
+= 1;
1362 back_attr_number
= lp_build_const_int32(gallivm
, back_attr_offset
);
1364 is_face_positive
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1365 face
, uint
->zero
, "");
1367 args
[2] = prim_mask
;
1368 args
[3] = interp_param
;
1369 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1370 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1371 LLVMValueRef front
, back
;
1373 args
[0] = llvm_chan
;
1374 args
[1] = attr_number
;
1375 front
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1376 ctx
->f32
, args
, args
[3] ? 4 : 3,
1377 LLVMReadNoneAttribute
);
1379 args
[1] = back_attr_number
;
1380 back
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
1381 ctx
->f32
, args
, args
[3] ? 4 : 3,
1382 LLVMReadNoneAttribute
);
1384 result
[chan
] = LLVMBuildSelect(gallivm
->builder
,
1390 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1391 LLVMValueRef args
[4];
1393 args
[0] = uint
->zero
;
1394 args
[1] = attr_number
;
1395 args
[2] = prim_mask
;
1396 args
[3] = interp_param
;
1397 result
[0] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1398 ctx
->f32
, args
, args
[3] ? 4 : 3,
1399 LLVMReadNoneAttribute
);
1401 result
[2] = lp_build_const_float(gallivm
, 0.0f
);
1402 result
[3] = lp_build_const_float(gallivm
, 1.0f
);
1404 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1405 LLVMValueRef args
[4];
1406 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
1408 args
[0] = llvm_chan
;
1409 args
[1] = attr_number
;
1410 args
[2] = prim_mask
;
1411 args
[3] = interp_param
;
1412 result
[chan
] = lp_build_intrinsic(gallivm
->builder
, intr_name
,
1413 ctx
->f32
, args
, args
[3] ? 4 : 3,
1414 LLVMReadNoneAttribute
);
1419 /* LLVMGetParam with bc_optimize resolved. */
1420 static LLVMValueRef
get_interp_param(struct si_shader_context
*ctx
,
1421 int interp_param_idx
)
1423 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
1424 LLVMValueRef main_fn
= ctx
->radeon_bld
.main_fn
;
1425 LLVMValueRef param
= NULL
;
1427 /* Handle PRIM_MASK[31] (bc_optimize). */
1428 if (ctx
->is_monolithic
&&
1429 ((ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1430 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) ||
1431 (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1432 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
))) {
1433 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1434 * The hw doesn't compute CENTROID if the whole wave only
1435 * contains fully-covered quads.
1437 LLVMValueRef bc_optimize
=
1438 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
1439 bc_optimize
= LLVMBuildLShr(builder
,
1441 LLVMConstInt(ctx
->i32
, 31, 0), "");
1442 bc_optimize
= LLVMBuildTrunc(builder
, bc_optimize
, ctx
->i1
, "");
1444 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_persp
&&
1445 interp_param_idx
== SI_PARAM_PERSP_CENTROID
) {
1446 param
= LLVMBuildSelect(builder
, bc_optimize
,
1447 LLVMGetParam(main_fn
,
1448 SI_PARAM_PERSP_CENTER
),
1449 LLVMGetParam(main_fn
,
1450 SI_PARAM_PERSP_CENTROID
),
1453 if (ctx
->shader
->key
.ps
.prolog
.bc_optimize_for_linear
&&
1454 interp_param_idx
== SI_PARAM_LINEAR_CENTROID
) {
1455 param
= LLVMBuildSelect(builder
, bc_optimize
,
1456 LLVMGetParam(main_fn
,
1457 SI_PARAM_LINEAR_CENTER
),
1458 LLVMGetParam(main_fn
,
1459 SI_PARAM_LINEAR_CENTROID
),
1465 param
= LLVMGetParam(main_fn
, interp_param_idx
);
1469 static void declare_input_fs(
1470 struct radeon_llvm_context
*radeon_bld
,
1471 unsigned input_index
,
1472 const struct tgsi_full_declaration
*decl
)
1474 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
1475 struct si_shader_context
*ctx
=
1476 si_shader_context(&radeon_bld
->soa
.bld_base
);
1477 struct si_shader
*shader
= ctx
->shader
;
1478 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
1479 LLVMValueRef interp_param
= NULL
;
1480 int interp_param_idx
;
1482 /* Get colors from input VGPRs (set by the prolog). */
1483 if (!ctx
->is_monolithic
&&
1484 decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
) {
1485 unsigned i
= decl
->Semantic
.Index
;
1486 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1487 unsigned mask
= colors_read
>> (i
* 4);
1488 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1489 (i
? util_bitcount(colors_read
& 0xf) : 0);
1491 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
1492 mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1493 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
1494 mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1495 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
1496 mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1497 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
1498 mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : base
->undef
;
1502 interp_param_idx
= lookup_interp_param_index(decl
->Interp
.Interpolate
,
1503 decl
->Interp
.Location
);
1504 if (interp_param_idx
== -1)
1506 else if (interp_param_idx
) {
1507 interp_param_idx
= select_interp_param(ctx
,
1509 interp_param
= get_interp_param(ctx
, interp_param_idx
);
1512 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
1513 decl
->Interp
.Interpolate
== TGSI_INTERPOLATE_COLOR
&&
1514 ctx
->shader
->key
.ps
.prolog
.flatshade_colors
)
1515 interp_param
= NULL
; /* load the constant color */
1517 interp_fs_input(ctx
, input_index
, decl
->Semantic
.Name
,
1518 decl
->Semantic
.Index
, shader
->selector
->info
.num_inputs
,
1519 shader
->selector
->info
.colors_read
, interp_param
,
1520 LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
),
1521 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1522 &radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)]);
1525 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
1527 return unpack_param(si_shader_context(&radeon_bld
->soa
.bld_base
),
1528 SI_PARAM_ANCILLARY
, 8, 4);
1532 * Set range metadata on an instruction. This can only be used on load and
1533 * call instructions. If you know an instruction can only produce the values
1534 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1535 * \p lo is the minimum value inclusive.
1536 * \p hi is the maximum value exclusive.
1538 static void set_range_metadata(struct si_shader_context
*ctx
,
1539 LLVMValueRef value
, unsigned lo
, unsigned hi
)
1541 LLVMValueRef range_md
, md_args
[2];
1542 LLVMTypeRef type
= LLVMTypeOf(value
);
1543 LLVMContextRef context
= LLVMGetTypeContext(type
);
1545 md_args
[0] = LLVMConstInt(type
, lo
, false);
1546 md_args
[1] = LLVMConstInt(type
, hi
, false);
1547 range_md
= LLVMMDNodeInContext(context
, md_args
, 2);
1548 LLVMSetMetadata(value
, ctx
->range_md_kind
, range_md
);
1551 static LLVMValueRef
get_thread_id(struct si_shader_context
*ctx
)
1553 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
1556 if (HAVE_LLVM
< 0x0308) {
1557 tid
= lp_build_intrinsic(gallivm
->builder
, "llvm.SI.tid",
1558 ctx
->i32
, NULL
, 0, LLVMReadNoneAttribute
);
1560 LLVMValueRef tid_args
[2];
1561 tid_args
[0] = lp_build_const_int32(gallivm
, 0xffffffff);
1562 tid_args
[1] = lp_build_const_int32(gallivm
, 0);
1563 tid_args
[1] = lp_build_intrinsic(gallivm
->builder
,
1564 "llvm.amdgcn.mbcnt.lo", ctx
->i32
,
1565 tid_args
, 2, LLVMReadNoneAttribute
);
1567 tid
= lp_build_intrinsic(gallivm
->builder
,
1568 "llvm.amdgcn.mbcnt.hi", ctx
->i32
,
1569 tid_args
, 2, LLVMReadNoneAttribute
);
1571 set_range_metadata(ctx
, tid
, 0, 64);
1576 * Load a dword from a constant buffer.
1578 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1579 LLVMValueRef resource
,
1580 LLVMValueRef offset
)
1582 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
1583 LLVMValueRef args
[2] = {resource
, offset
};
1585 return lp_build_intrinsic(builder
, "llvm.SI.load.const", ctx
->f32
, args
, 2,
1586 LLVMReadNoneAttribute
);
1589 static LLVMValueRef
load_sample_position(struct radeon_llvm_context
*radeon_bld
, LLVMValueRef sample_id
)
1591 struct si_shader_context
*ctx
=
1592 si_shader_context(&radeon_bld
->soa
.bld_base
);
1593 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
1594 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1595 LLVMBuilderRef builder
= gallivm
->builder
;
1596 LLVMValueRef desc
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1597 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_PS_CONST_SAMPLE_POSITIONS
);
1598 LLVMValueRef resource
= build_indexed_load_const(ctx
, desc
, buf_index
);
1600 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1601 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1602 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
1604 LLVMValueRef pos
[4] = {
1605 buffer_load_const(ctx
, resource
, offset0
),
1606 buffer_load_const(ctx
, resource
, offset1
),
1607 lp_build_const_float(gallivm
, 0),
1608 lp_build_const_float(gallivm
, 0)
1611 return lp_build_gather_values(gallivm
, pos
, 4);
1614 static void declare_system_value(
1615 struct radeon_llvm_context
*radeon_bld
,
1617 const struct tgsi_full_declaration
*decl
)
1619 struct si_shader_context
*ctx
=
1620 si_shader_context(&radeon_bld
->soa
.bld_base
);
1621 struct lp_build_context
*bld
= &radeon_bld
->soa
.bld_base
.base
;
1622 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1623 LLVMValueRef value
= 0;
1625 switch (decl
->Semantic
.Name
) {
1626 case TGSI_SEMANTIC_INSTANCEID
:
1627 value
= LLVMGetParam(radeon_bld
->main_fn
,
1628 ctx
->param_instance_id
);
1631 case TGSI_SEMANTIC_VERTEXID
:
1632 value
= LLVMBuildAdd(gallivm
->builder
,
1633 LLVMGetParam(radeon_bld
->main_fn
,
1634 ctx
->param_vertex_id
),
1635 LLVMGetParam(radeon_bld
->main_fn
,
1636 SI_PARAM_BASE_VERTEX
), "");
1639 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1640 value
= LLVMGetParam(radeon_bld
->main_fn
,
1641 ctx
->param_vertex_id
);
1644 case TGSI_SEMANTIC_BASEVERTEX
:
1645 value
= LLVMGetParam(radeon_bld
->main_fn
,
1646 SI_PARAM_BASE_VERTEX
);
1649 case TGSI_SEMANTIC_BASEINSTANCE
:
1650 value
= LLVMGetParam(radeon_bld
->main_fn
,
1651 SI_PARAM_START_INSTANCE
);
1654 case TGSI_SEMANTIC_DRAWID
:
1655 value
= LLVMGetParam(radeon_bld
->main_fn
,
1659 case TGSI_SEMANTIC_INVOCATIONID
:
1660 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
1661 value
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
1662 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
1663 value
= LLVMGetParam(radeon_bld
->main_fn
,
1664 SI_PARAM_GS_INSTANCE_ID
);
1666 assert(!"INVOCATIONID not implemented");
1669 case TGSI_SEMANTIC_POSITION
:
1671 LLVMValueRef pos
[4] = {
1672 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1673 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1674 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1675 lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
, TGSI_OPCODE_RCP
,
1676 LLVMGetParam(radeon_bld
->main_fn
,
1677 SI_PARAM_POS_W_FLOAT
)),
1679 value
= lp_build_gather_values(gallivm
, pos
, 4);
1683 case TGSI_SEMANTIC_FACE
:
1684 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_FRONT_FACE
);
1687 case TGSI_SEMANTIC_SAMPLEID
:
1688 value
= get_sample_id(radeon_bld
);
1691 case TGSI_SEMANTIC_SAMPLEPOS
: {
1692 LLVMValueRef pos
[4] = {
1693 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1694 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1695 lp_build_const_float(gallivm
, 0),
1696 lp_build_const_float(gallivm
, 0)
1698 pos
[0] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1699 TGSI_OPCODE_FRC
, pos
[0]);
1700 pos
[1] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1701 TGSI_OPCODE_FRC
, pos
[1]);
1702 value
= lp_build_gather_values(gallivm
, pos
, 4);
1706 case TGSI_SEMANTIC_SAMPLEMASK
:
1707 /* This can only occur with the OpenGL Core profile, which
1708 * doesn't support smoothing.
1710 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1713 case TGSI_SEMANTIC_TESSCOORD
:
1715 LLVMValueRef coord
[4] = {
1716 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_u
),
1717 LLVMGetParam(radeon_bld
->main_fn
, ctx
->param_tes_v
),
1722 /* For triangles, the vector should be (u, v, 1-u-v). */
1723 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1724 PIPE_PRIM_TRIANGLES
)
1725 coord
[2] = lp_build_sub(bld
, bld
->one
,
1726 lp_build_add(bld
, coord
[0], coord
[1]));
1728 value
= lp_build_gather_values(gallivm
, coord
, 4);
1732 case TGSI_SEMANTIC_VERTICESIN
:
1733 value
= unpack_param(ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 26, 6);
1736 case TGSI_SEMANTIC_TESSINNER
:
1737 case TGSI_SEMANTIC_TESSOUTER
:
1739 LLVMValueRef rw_buffers
, buffer
, base
, addr
;
1740 int param
= si_shader_io_get_unique_index(decl
->Semantic
.Name
, 0);
1742 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
1743 SI_PARAM_RW_BUFFERS
);
1744 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
1745 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
1747 base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
1748 addr
= get_tcs_tes_buffer_address(ctx
, NULL
,
1749 lp_build_const_int32(gallivm
, param
));
1751 value
= buffer_load(&radeon_bld
->soa
.bld_base
, TGSI_TYPE_FLOAT
,
1752 ~0, buffer
, base
, addr
);
1757 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
1758 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
1760 LLVMValueRef buf
, slot
, val
[4];
1763 slot
= lp_build_const_int32(gallivm
, SI_HS_CONST_DEFAULT_TESS_LEVELS
);
1764 buf
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
1765 buf
= build_indexed_load_const(ctx
, buf
, slot
);
1766 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
1768 for (i
= 0; i
< 4; i
++)
1769 val
[i
] = buffer_load_const(ctx
, buf
,
1770 lp_build_const_int32(gallivm
, (offset
+ i
) * 4));
1771 value
= lp_build_gather_values(gallivm
, val
, 4);
1775 case TGSI_SEMANTIC_PRIMID
:
1776 value
= get_primitive_id(&radeon_bld
->soa
.bld_base
, 0);
1779 case TGSI_SEMANTIC_GRID_SIZE
:
1780 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_GRID_SIZE
);
1783 case TGSI_SEMANTIC_BLOCK_SIZE
:
1785 LLVMValueRef values
[3];
1787 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1788 unsigned sizes
[3] = {
1789 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1790 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1791 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1794 for (i
= 0; i
< 3; ++i
)
1795 values
[i
] = lp_build_const_int32(gallivm
, sizes
[i
]);
1797 value
= lp_build_gather_values(gallivm
, values
, 3);
1801 case TGSI_SEMANTIC_BLOCK_ID
:
1802 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_BLOCK_ID
);
1805 case TGSI_SEMANTIC_THREAD_ID
:
1806 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_THREAD_ID
);
1809 #if HAVE_LLVM >= 0x0309
1810 case TGSI_SEMANTIC_HELPER_INVOCATION
:
1811 value
= lp_build_intrinsic(gallivm
->builder
,
1812 "llvm.amdgcn.ps.live",
1814 LLVMReadNoneAttribute
);
1815 value
= LLVMBuildNot(gallivm
->builder
, value
, "");
1816 value
= LLVMBuildSExt(gallivm
->builder
, value
, ctx
->i32
, "");
1821 assert(!"unknown system value");
1825 radeon_bld
->system_values
[index
] = value
;
1828 static void declare_compute_memory(struct radeon_llvm_context
*radeon_bld
,
1829 const struct tgsi_full_declaration
*decl
)
1831 struct si_shader_context
*ctx
=
1832 si_shader_context(&radeon_bld
->soa
.bld_base
);
1833 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
1834 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1836 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, LOCAL_ADDR_SPACE
);
1839 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
1840 assert(decl
->Range
.First
== decl
->Range
.Last
);
1841 assert(!ctx
->shared_memory
);
1843 var
= LLVMAddGlobalInAddressSpace(gallivm
->module
,
1844 LLVMArrayType(ctx
->i8
, sel
->local_size
),
1847 LLVMSetAlignment(var
, 4);
1849 ctx
->shared_memory
= LLVMBuildBitCast(gallivm
->builder
, var
, i8p
, "");
1852 static LLVMValueRef
fetch_constant(
1853 struct lp_build_tgsi_context
*bld_base
,
1854 const struct tgsi_full_src_register
*reg
,
1855 enum tgsi_opcode_type type
,
1858 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1859 struct lp_build_context
*base
= &bld_base
->base
;
1860 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1863 LLVMValueRef addr
, bufp
;
1864 LLVMValueRef result
;
1866 if (swizzle
== LP_CHAN_ALL
) {
1868 LLVMValueRef values
[4];
1869 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1870 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1872 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
1875 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
1876 idx
= reg
->Register
.Index
* 4 + swizzle
;
1878 if (!reg
->Register
.Indirect
&& !reg
->Dimension
.Indirect
) {
1879 if (!tgsi_type_is_64bit(type
))
1880 return bitcast(bld_base
, type
, ctx
->constants
[buf
][idx
]);
1882 return radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1883 ctx
->constants
[buf
][idx
],
1884 ctx
->constants
[buf
][idx
+ 1]);
1888 if (reg
->Register
.Dimension
&& reg
->Dimension
.Indirect
) {
1889 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1891 index
= get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
1892 reg
->Dimension
.Index
,
1893 SI_NUM_CONST_BUFFERS
);
1894 bufp
= build_indexed_load_const(ctx
, ptr
, index
);
1896 bufp
= ctx
->const_buffers
[buf
];
1898 addr
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
1899 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
1900 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
1901 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
1902 lp_build_const_int32(base
->gallivm
, idx
* 4));
1904 result
= buffer_load_const(ctx
, bufp
, addr
);
1906 if (!tgsi_type_is_64bit(type
))
1907 result
= bitcast(bld_base
, type
, result
);
1909 LLVMValueRef addr2
, result2
;
1910 addr2
= ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
+ 1];
1911 addr2
= LLVMBuildLoad(base
->gallivm
->builder
, addr2
, "load addr reg2");
1912 addr2
= lp_build_mul_imm(&bld_base
->uint_bld
, addr2
, 16);
1913 addr2
= lp_build_add(&bld_base
->uint_bld
, addr2
,
1914 lp_build_const_int32(base
->gallivm
, idx
* 4));
1916 result2
= buffer_load_const(ctx
, ctx
->const_buffers
[buf
],
1919 result
= radeon_llvm_emit_fetch_64bit(bld_base
, type
,
1925 /* Upper 16 bits must be zero. */
1926 static LLVMValueRef
si_llvm_pack_two_int16(struct gallivm_state
*gallivm
,
1927 LLVMValueRef val
[2])
1929 return LLVMBuildOr(gallivm
->builder
, val
[0],
1930 LLVMBuildShl(gallivm
->builder
, val
[1],
1931 lp_build_const_int32(gallivm
, 16),
1935 /* Upper 16 bits are ignored and will be dropped. */
1936 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct gallivm_state
*gallivm
,
1937 LLVMValueRef val
[2])
1939 LLVMValueRef v
[2] = {
1940 LLVMBuildAnd(gallivm
->builder
, val
[0],
1941 lp_build_const_int32(gallivm
, 0xffff), ""),
1944 return si_llvm_pack_two_int16(gallivm
, v
);
1947 /* Initialize arguments for the shader export intrinsic */
1948 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
1949 LLVMValueRef
*values
,
1953 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1954 struct lp_build_context
*uint
=
1955 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1956 struct lp_build_context
*base
= &bld_base
->base
;
1957 struct gallivm_state
*gallivm
= base
->gallivm
;
1958 LLVMBuilderRef builder
= base
->gallivm
->builder
;
1959 LLVMValueRef val
[4];
1960 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
1964 /* Default is 0xf. Adjusted below depending on the format. */
1965 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1967 /* Specify whether the EXEC mask represents the valid mask */
1968 args
[1] = uint
->zero
;
1970 /* Specify whether this is the last export */
1971 args
[2] = uint
->zero
;
1973 /* Specify the target we are exporting */
1974 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
1976 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
1977 const union si_shader_key
*key
= &ctx
->shader
->key
;
1978 unsigned col_formats
= key
->ps
.epilog
.spi_shader_col_format
;
1979 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
1981 assert(cbuf
>= 0 && cbuf
< 8);
1982 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
1983 is_int8
= (key
->ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
1986 args
[4] = uint
->zero
; /* COMPR flag */
1987 args
[5] = base
->undef
;
1988 args
[6] = base
->undef
;
1989 args
[7] = base
->undef
;
1990 args
[8] = base
->undef
;
1992 switch (spi_shader_col_format
) {
1993 case V_028714_SPI_SHADER_ZERO
:
1994 args
[0] = uint
->zero
; /* writemask */
1995 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
1998 case V_028714_SPI_SHADER_32_R
:
1999 args
[0] = uint
->one
; /* writemask */
2000 args
[5] = values
[0];
2003 case V_028714_SPI_SHADER_32_GR
:
2004 args
[0] = lp_build_const_int32(base
->gallivm
, 0x3); /* writemask */
2005 args
[5] = values
[0];
2006 args
[6] = values
[1];
2009 case V_028714_SPI_SHADER_32_AR
:
2010 args
[0] = lp_build_const_int32(base
->gallivm
, 0x9); /* writemask */
2011 args
[5] = values
[0];
2012 args
[8] = values
[3];
2015 case V_028714_SPI_SHADER_FP16_ABGR
:
2016 args
[4] = uint
->one
; /* COMPR flag */
2018 for (chan
= 0; chan
< 2; chan
++) {
2019 LLVMValueRef pack_args
[2] = {
2021 values
[2 * chan
+ 1]
2023 LLVMValueRef packed
;
2025 packed
= lp_build_intrinsic(base
->gallivm
->builder
,
2027 ctx
->i32
, pack_args
, 2,
2028 LLVMReadNoneAttribute
);
2030 LLVMBuildBitCast(base
->gallivm
->builder
,
2031 packed
, ctx
->f32
, "");
2035 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2036 for (chan
= 0; chan
< 4; chan
++) {
2037 val
[chan
] = radeon_llvm_saturate(bld_base
, values
[chan
]);
2038 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2039 lp_build_const_float(gallivm
, 65535), "");
2040 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2041 lp_build_const_float(gallivm
, 0.5), "");
2042 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
2046 args
[4] = uint
->one
; /* COMPR flag */
2047 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2048 si_llvm_pack_two_int16(gallivm
, val
));
2049 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2050 si_llvm_pack_two_int16(gallivm
, val
+2));
2053 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2054 for (chan
= 0; chan
< 4; chan
++) {
2055 /* Clamp between [-1, 1]. */
2056 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MIN
,
2058 lp_build_const_float(gallivm
, 1));
2059 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MAX
,
2061 lp_build_const_float(gallivm
, -1));
2062 /* Convert to a signed integer in [-32767, 32767]. */
2063 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
2064 lp_build_const_float(gallivm
, 32767), "");
2065 /* If positive, add 0.5, else add -0.5. */
2066 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
2067 LLVMBuildSelect(builder
,
2068 LLVMBuildFCmp(builder
, LLVMRealOGE
,
2069 val
[chan
], base
->zero
, ""),
2070 lp_build_const_float(gallivm
, 0.5),
2071 lp_build_const_float(gallivm
, -0.5), ""), "");
2072 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], ctx
->i32
, "");
2075 args
[4] = uint
->one
; /* COMPR flag */
2076 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2077 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2078 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2079 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2082 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2083 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2086 for (chan
= 0; chan
< 4; chan
++) {
2087 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2088 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_UMIN
,
2092 args
[4] = uint
->one
; /* COMPR flag */
2093 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2094 si_llvm_pack_two_int16(gallivm
, val
));
2095 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2096 si_llvm_pack_two_int16(gallivm
, val
+2));
2100 case V_028714_SPI_SHADER_SINT16_ABGR
: {
2101 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
2103 LLVMValueRef min
= lp_build_const_int32(gallivm
, is_int8
?
2106 for (chan
= 0; chan
< 4; chan
++) {
2107 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
2108 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2111 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2116 args
[4] = uint
->one
; /* COMPR flag */
2117 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2118 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
2119 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2120 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
2124 case V_028714_SPI_SHADER_32_ABGR
:
2125 memcpy(&args
[5], values
, sizeof(values
[0]) * 4);
2130 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2133 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2134 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2136 if (ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2137 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2138 SI_PARAM_ALPHA_REF
);
2140 LLVMValueRef alpha_pass
=
2141 lp_build_cmp(&bld_base
->base
,
2142 ctx
->shader
->key
.ps
.epilog
.alpha_func
,
2145 lp_build_select(&bld_base
->base
,
2147 lp_build_const_float(gallivm
, 1.0f
),
2148 lp_build_const_float(gallivm
, -1.0f
));
2150 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2151 ctx
->voidt
, &arg
, 1, 0);
2153 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kilp",
2154 ctx
->voidt
, NULL
, 0, 0);
2158 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2160 unsigned samplemask_param
)
2162 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2163 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2164 LLVMValueRef coverage
;
2166 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2167 coverage
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2169 coverage
= bitcast(bld_base
, TGSI_TYPE_SIGNED
, coverage
);
2171 coverage
= lp_build_intrinsic(gallivm
->builder
, "llvm.ctpop.i32",
2173 &coverage
, 1, LLVMReadNoneAttribute
);
2175 coverage
= LLVMBuildUIToFP(gallivm
->builder
, coverage
,
2178 coverage
= LLVMBuildFMul(gallivm
->builder
, coverage
,
2179 lp_build_const_float(gallivm
,
2180 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2182 return LLVMBuildFMul(gallivm
->builder
, alpha
, coverage
, "");
2185 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
*bld_base
,
2186 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
2188 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2189 struct lp_build_context
*base
= &bld_base
->base
;
2190 struct lp_build_context
*uint
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2193 unsigned const_chan
;
2194 LLVMValueRef base_elt
;
2195 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2196 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
,
2197 SI_VS_CONST_CLIP_PLANES
);
2198 LLVMValueRef const_resource
= build_indexed_load_const(ctx
, ptr
, constbuf_index
);
2200 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2201 LLVMValueRef
*args
= pos
[2 + reg_index
];
2206 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
2208 /* Compute dot products of position and user clip plane vectors */
2209 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2210 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2211 args
[1] = lp_build_const_int32(base
->gallivm
,
2212 ((reg_index
* 4 + chan
) * 4 +
2214 base_elt
= buffer_load_const(ctx
, const_resource
,
2217 lp_build_add(base
, args
[5 + chan
],
2218 lp_build_mul(base
, base_elt
,
2219 out_elts
[const_chan
]));
2223 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
2224 args
[1] = uint
->zero
;
2225 args
[2] = uint
->zero
;
2226 args
[3] = lp_build_const_int32(base
->gallivm
,
2227 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
2228 args
[4] = uint
->zero
;
2232 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2236 if (so
->num_outputs
)
2237 fprintf(stderr
, "STREAMOUT\n");
2239 for (i
= 0; i
< so
->num_outputs
; i
++) {
2240 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2241 so
->output
[i
].start_component
;
2242 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2243 i
, so
->output
[i
].output_buffer
,
2244 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2245 so
->output
[i
].register_index
,
2246 mask
& 1 ? "x" : "",
2247 mask
& 2 ? "y" : "",
2248 mask
& 4 ? "z" : "",
2249 mask
& 8 ? "w" : "");
2253 /* On SI, the vertex shader is responsible for writing streamout data
2255 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2256 struct si_shader_output_values
*outputs
,
2259 struct pipe_stream_output_info
*so
= &ctx
->shader
->selector
->so
;
2260 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
2261 LLVMBuilderRef builder
= gallivm
->builder
;
2263 struct lp_build_if_state if_ctx
;
2265 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2266 LLVMValueRef so_vtx_count
=
2267 unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2269 LLVMValueRef tid
= get_thread_id(ctx
);
2271 /* can_emit = tid < so_vtx_count; */
2272 LLVMValueRef can_emit
=
2273 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2275 LLVMValueRef stream_id
=
2276 unpack_param(ctx
, ctx
->param_streamout_config
, 24, 2);
2278 /* Emit the streamout code conditionally. This actually avoids
2279 * out-of-bounds buffer access. The hw tells us via the SGPR
2280 * (so_vtx_count) which threads are allowed to emit streamout data. */
2281 lp_build_if(&if_ctx
, gallivm
, can_emit
);
2283 /* The buffer offset is computed as follows:
2284 * ByteOffset = streamout_offset[buffer_id]*4 +
2285 * (streamout_write_index + thread_id)*stride[buffer_id] +
2289 LLVMValueRef so_write_index
=
2290 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2291 ctx
->param_streamout_write_index
);
2293 /* Compute (streamout_write_index + thread_id). */
2294 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2296 /* Compute the write offset for each enabled buffer. */
2297 LLVMValueRef so_write_offset
[4] = {};
2298 for (i
= 0; i
< 4; i
++) {
2302 LLVMValueRef so_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2303 ctx
->param_streamout_offset
[i
]);
2304 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2306 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2307 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2308 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2311 /* Write streamout data. */
2312 for (i
= 0; i
< so
->num_outputs
; i
++) {
2313 unsigned buf_idx
= so
->output
[i
].output_buffer
;
2314 unsigned reg
= so
->output
[i
].register_index
;
2315 unsigned start
= so
->output
[i
].start_component
;
2316 unsigned num_comps
= so
->output
[i
].num_components
;
2317 unsigned stream
= so
->output
[i
].stream
;
2318 LLVMValueRef out
[4];
2319 struct lp_build_if_state if_ctx_stream
;
2321 assert(num_comps
&& num_comps
<= 4);
2322 if (!num_comps
|| num_comps
> 4)
2328 /* Load the output as int. */
2329 for (j
= 0; j
< num_comps
; j
++) {
2330 out
[j
] = LLVMBuildBitCast(builder
,
2331 outputs
[reg
].values
[start
+j
],
2335 /* Pack the output. */
2336 LLVMValueRef vdata
= NULL
;
2338 switch (num_comps
) {
2339 case 1: /* as i32 */
2342 case 2: /* as v2i32 */
2343 case 3: /* as v4i32 (aligned to 4) */
2344 case 4: /* as v4i32 */
2345 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2346 for (j
= 0; j
< num_comps
; j
++) {
2347 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
2348 LLVMConstInt(ctx
->i32
, j
, 0), "");
2353 LLVMValueRef can_emit_stream
=
2354 LLVMBuildICmp(builder
, LLVMIntEQ
,
2356 lp_build_const_int32(gallivm
, stream
), "");
2358 lp_build_if(&if_ctx_stream
, gallivm
, can_emit_stream
);
2359 build_tbuffer_store_dwords(ctx
, ctx
->so_buffers
[buf_idx
],
2361 so_write_offset
[buf_idx
],
2362 LLVMConstInt(ctx
->i32
, 0, 0),
2363 so
->output
[i
].dst_offset
*4);
2364 lp_build_endif(&if_ctx_stream
);
2367 lp_build_endif(&if_ctx
);
2371 /* Generate export instructions for hardware VS shader stage */
2372 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
2373 struct si_shader_output_values
*outputs
,
2376 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2377 struct si_shader
*shader
= ctx
->shader
;
2378 struct lp_build_context
*base
= &bld_base
->base
;
2379 struct lp_build_context
*uint
=
2380 &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
2381 LLVMValueRef args
[9];
2382 LLVMValueRef pos_args
[4][9] = { { 0 } };
2383 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2384 unsigned semantic_name
, semantic_index
;
2386 unsigned param_count
= 0;
2390 if (outputs
&& ctx
->shader
->selector
->so
.num_outputs
) {
2391 si_llvm_emit_streamout(ctx
, outputs
, noutput
);
2394 for (i
= 0; i
< noutput
; i
++) {
2395 semantic_name
= outputs
[i
].name
;
2396 semantic_index
= outputs
[i
].sid
;
2399 /* Select the correct target */
2400 switch(semantic_name
) {
2401 case TGSI_SEMANTIC_PSIZE
:
2402 psize_value
= outputs
[i
].values
[0];
2404 case TGSI_SEMANTIC_EDGEFLAG
:
2405 edgeflag_value
= outputs
[i
].values
[0];
2407 case TGSI_SEMANTIC_LAYER
:
2408 layer_value
= outputs
[i
].values
[0];
2409 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2410 goto handle_semantic
;
2411 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2412 viewport_index_value
= outputs
[i
].values
[0];
2413 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2414 goto handle_semantic
;
2415 case TGSI_SEMANTIC_POSITION
:
2416 target
= V_008DFC_SQ_EXP_POS
;
2418 case TGSI_SEMANTIC_COLOR
:
2419 case TGSI_SEMANTIC_BCOLOR
:
2420 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2421 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2422 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2425 case TGSI_SEMANTIC_CLIPDIST
:
2426 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
2428 case TGSI_SEMANTIC_CLIPVERTEX
:
2429 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
2431 case TGSI_SEMANTIC_PRIMID
:
2432 case TGSI_SEMANTIC_FOG
:
2433 case TGSI_SEMANTIC_TEXCOORD
:
2434 case TGSI_SEMANTIC_GENERIC
:
2435 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
2436 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2437 shader
->info
.vs_output_param_offset
[i
] = param_count
;
2443 "Warning: SI unhandled vs output type:%d\n",
2447 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
2449 if (target
>= V_008DFC_SQ_EXP_POS
&&
2450 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
2451 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2452 args
, sizeof(args
));
2454 lp_build_intrinsic(base
->gallivm
->builder
,
2455 "llvm.SI.export", ctx
->voidt
,
2459 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
2460 semantic_name
= TGSI_SEMANTIC_GENERIC
;
2461 goto handle_semantic
;
2465 shader
->info
.nr_param_exports
= param_count
;
2467 /* We need to add the position output manually if it's missing. */
2468 if (!pos_args
[0][0]) {
2469 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
2470 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
2471 pos_args
[0][2] = uint
->zero
; /* last export? */
2472 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
2473 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
2474 pos_args
[0][5] = base
->zero
; /* X */
2475 pos_args
[0][6] = base
->zero
; /* Y */
2476 pos_args
[0][7] = base
->zero
; /* Z */
2477 pos_args
[0][8] = base
->one
; /* W */
2480 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2481 if (shader
->selector
->info
.writes_psize
||
2482 shader
->selector
->info
.writes_edgeflag
||
2483 shader
->selector
->info
.writes_viewport_index
||
2484 shader
->selector
->info
.writes_layer
) {
2485 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
2486 shader
->selector
->info
.writes_psize
|
2487 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2488 (shader
->selector
->info
.writes_layer
<< 2) |
2489 (shader
->selector
->info
.writes_viewport_index
<< 3));
2490 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
2491 pos_args
[1][2] = uint
->zero
; /* last export? */
2492 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
2493 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
2494 pos_args
[1][5] = base
->zero
; /* X */
2495 pos_args
[1][6] = base
->zero
; /* Y */
2496 pos_args
[1][7] = base
->zero
; /* Z */
2497 pos_args
[1][8] = base
->zero
; /* W */
2499 if (shader
->selector
->info
.writes_psize
)
2500 pos_args
[1][5] = psize_value
;
2502 if (shader
->selector
->info
.writes_edgeflag
) {
2503 /* The output is a float, but the hw expects an integer
2504 * with the first bit containing the edge flag. */
2505 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
2508 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
2510 bld_base
->int_bld
.one
);
2512 /* The LLVM intrinsic expects a float. */
2513 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
2518 if (shader
->selector
->info
.writes_layer
)
2519 pos_args
[1][7] = layer_value
;
2521 if (shader
->selector
->info
.writes_viewport_index
)
2522 pos_args
[1][8] = viewport_index_value
;
2525 for (i
= 0; i
< 4; i
++)
2527 shader
->info
.nr_pos_exports
++;
2530 for (i
= 0; i
< 4; i
++) {
2531 if (!pos_args
[i
][0])
2534 /* Specify the target we are exporting */
2535 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
2537 if (pos_idx
== shader
->info
.nr_pos_exports
)
2538 /* Specify that this is the last export */
2539 pos_args
[i
][2] = uint
->one
;
2541 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2542 ctx
->voidt
, pos_args
[i
], 9, 0);
2546 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
2548 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2549 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2550 LLVMValueRef invocation_id
, rw_buffers
, buffer
, buffer_offset
;
2551 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
2554 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2556 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_RW_BUFFERS
);
2557 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2558 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_OFFCHIP
));
2560 buffer_offset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, ctx
->param_oc_lds
);
2562 lds_vertex_stride
= unpack_param(ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
2563 lds_vertex_offset
= LLVMBuildMul(gallivm
->builder
, invocation_id
,
2564 lds_vertex_stride
, "");
2565 lds_base
= get_tcs_in_current_patch_offset(ctx
);
2566 lds_base
= LLVMBuildAdd(gallivm
->builder
, lds_base
, lds_vertex_offset
, "");
2568 inputs
= ctx
->shader
->key
.tcs
.epilog
.inputs_to_copy
;
2570 unsigned i
= u_bit_scan64(&inputs
);
2572 LLVMValueRef lds_ptr
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2573 lp_build_const_int32(gallivm
, 4 * i
),
2576 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
2578 lp_build_const_int32(gallivm
, i
));
2580 LLVMValueRef value
= lds_load(bld_base
, TGSI_TYPE_SIGNED
, ~0,
2583 build_tbuffer_store_dwords(ctx
, buffer
, value
, 4, buffer_addr
,
2588 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
2589 LLVMValueRef rel_patch_id
,
2590 LLVMValueRef invocation_id
,
2591 LLVMValueRef tcs_out_current_patch_data_offset
)
2593 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2594 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2595 struct si_shader
*shader
= ctx
->shader
;
2596 unsigned tess_inner_index
, tess_outer_index
;
2597 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
2598 LLVMValueRef out
[6], vec0
, vec1
, rw_buffers
, tf_base
;
2599 unsigned stride
, outer_comps
, inner_comps
, i
;
2600 struct lp_build_if_state if_ctx
, inner_if_ctx
;
2602 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
2604 /* Do this only for invocation 0, because the tess levels are per-patch,
2607 * This can't jump, because invocation 0 executes this. It should
2608 * at least mask out the loads and stores for other invocations.
2610 lp_build_if(&if_ctx
, gallivm
,
2611 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2612 invocation_id
, bld_base
->uint_bld
.zero
, ""));
2614 /* Determine the layout of one tess factor element in the buffer. */
2615 switch (shader
->key
.tcs
.epilog
.prim_mode
) {
2616 case PIPE_PRIM_LINES
:
2617 stride
= 2; /* 2 dwords, 1 vec2 store */
2621 case PIPE_PRIM_TRIANGLES
:
2622 stride
= 4; /* 4 dwords, 1 vec4 store */
2626 case PIPE_PRIM_QUADS
:
2627 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2636 /* Load tess_inner and tess_outer from LDS.
2637 * Any invocation can write them, so we can't get them from a temporary.
2639 tess_inner_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0);
2640 tess_outer_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0);
2642 lds_base
= tcs_out_current_patch_data_offset
;
2643 lds_inner
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2644 lp_build_const_int32(gallivm
,
2645 tess_inner_index
* 4), "");
2646 lds_outer
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2647 lp_build_const_int32(gallivm
,
2648 tess_outer_index
* 4), "");
2650 for (i
= 0; i
< outer_comps
; i
++)
2651 out
[i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_outer
);
2652 for (i
= 0; i
< inner_comps
; i
++)
2653 out
[outer_comps
+i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_inner
);
2655 /* Convert the outputs to vectors for stores. */
2656 vec0
= lp_build_gather_values(gallivm
, out
, MIN2(stride
, 4));
2660 vec1
= lp_build_gather_values(gallivm
, out
+4, stride
- 4);
2662 /* Get the buffer. */
2663 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2664 SI_PARAM_RW_BUFFERS
);
2665 buffer
= build_indexed_load_const(ctx
, rw_buffers
,
2666 lp_build_const_int32(gallivm
, SI_HS_RING_TESS_FACTOR
));
2668 /* Get the offset. */
2669 tf_base
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2670 SI_PARAM_TESS_FACTOR_OFFSET
);
2671 byteoffset
= LLVMBuildMul(gallivm
->builder
, rel_patch_id
,
2672 lp_build_const_int32(gallivm
, 4 * stride
), "");
2674 lp_build_if(&inner_if_ctx
, gallivm
,
2675 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
2676 rel_patch_id
, bld_base
->uint_bld
.zero
, ""));
2678 /* Store the dynamic HS control word. */
2679 build_tbuffer_store_dwords(ctx
, buffer
,
2680 lp_build_const_int32(gallivm
, 0x80000000),
2681 1, lp_build_const_int32(gallivm
, 0), tf_base
, 0);
2683 lp_build_endif(&inner_if_ctx
);
2685 /* Store the tessellation factors. */
2686 build_tbuffer_store_dwords(ctx
, buffer
, vec0
,
2687 MIN2(stride
, 4), byteoffset
, tf_base
, 4);
2689 build_tbuffer_store_dwords(ctx
, buffer
, vec1
,
2690 stride
- 4, byteoffset
, tf_base
, 20);
2691 lp_build_endif(&if_ctx
);
2694 /* This only writes the tessellation factor levels. */
2695 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2697 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2698 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
2700 rel_patch_id
= get_rel_patch_id(ctx
);
2701 invocation_id
= unpack_param(ctx
, SI_PARAM_REL_IDS
, 8, 5);
2702 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
2704 if (!ctx
->is_monolithic
) {
2705 /* Return epilog parameters from this function. */
2706 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2707 LLVMValueRef ret
= ctx
->return_value
;
2708 LLVMValueRef rw_buffers
, rw0
, rw1
, tf_soffset
;
2711 /* RW_BUFFERS pointer */
2712 rw_buffers
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2713 SI_PARAM_RW_BUFFERS
);
2714 rw_buffers
= LLVMBuildPtrToInt(builder
, rw_buffers
, ctx
->i64
, "");
2715 rw_buffers
= LLVMBuildBitCast(builder
, rw_buffers
, ctx
->v2i32
, "");
2716 rw0
= LLVMBuildExtractElement(builder
, rw_buffers
,
2717 bld_base
->uint_bld
.zero
, "");
2718 rw1
= LLVMBuildExtractElement(builder
, rw_buffers
,
2719 bld_base
->uint_bld
.one
, "");
2720 ret
= LLVMBuildInsertValue(builder
, ret
, rw0
, 0, "");
2721 ret
= LLVMBuildInsertValue(builder
, ret
, rw1
, 1, "");
2723 /* Tess factor buffer soffset is after user SGPRs. */
2724 tf_soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2725 SI_PARAM_TESS_FACTOR_OFFSET
);
2726 ret
= LLVMBuildInsertValue(builder
, ret
, tf_soffset
,
2727 SI_TCS_NUM_USER_SGPR
+ 1, "");
2730 rel_patch_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, rel_patch_id
);
2731 invocation_id
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, invocation_id
);
2732 tf_lds_offset
= bitcast(bld_base
, TGSI_TYPE_FLOAT
, tf_lds_offset
);
2734 vgpr
= SI_TCS_NUM_USER_SGPR
+ 2;
2735 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
2736 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
2737 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
2738 ctx
->return_value
= ret
;
2742 si_copy_tcs_inputs(bld_base
);
2743 si_write_tess_factors(bld_base
, rel_patch_id
, invocation_id
, tf_lds_offset
);
2746 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context
*bld_base
)
2748 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2749 struct si_shader
*shader
= ctx
->shader
;
2750 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2751 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2753 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2754 ctx
->param_rel_auto_id
);
2755 LLVMValueRef vertex_dw_stride
=
2756 unpack_param(ctx
, SI_PARAM_LS_OUT_LAYOUT
, 13, 8);
2757 LLVMValueRef base_dw_addr
= LLVMBuildMul(gallivm
->builder
, vertex_id
,
2758 vertex_dw_stride
, "");
2760 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2761 * its inputs from it. */
2762 for (i
= 0; i
< info
->num_outputs
; i
++) {
2763 LLVMValueRef
*out_ptr
= ctx
->radeon_bld
.soa
.outputs
[i
];
2764 unsigned name
= info
->output_semantic_name
[i
];
2765 unsigned index
= info
->output_semantic_index
[i
];
2766 int param
= si_shader_io_get_unique_index(name
, index
);
2767 LLVMValueRef dw_addr
= LLVMBuildAdd(gallivm
->builder
, base_dw_addr
,
2768 lp_build_const_int32(gallivm
, param
* 4), "");
2770 for (chan
= 0; chan
< 4; chan
++) {
2771 lds_store(bld_base
, chan
, dw_addr
,
2772 LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], ""));
2777 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
*bld_base
)
2779 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2780 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2781 struct si_shader
*es
= ctx
->shader
;
2782 struct tgsi_shader_info
*info
= &es
->selector
->info
;
2783 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2784 ctx
->param_es2gs_offset
);
2788 for (i
= 0; i
< info
->num_outputs
; i
++) {
2789 LLVMValueRef
*out_ptr
=
2790 ctx
->radeon_bld
.soa
.outputs
[i
];
2793 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
2794 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
2797 param_index
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
2798 info
->output_semantic_index
[i
]);
2800 for (chan
= 0; chan
< 4; chan
++) {
2801 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2802 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
2804 build_tbuffer_store(ctx
,
2807 LLVMGetUndef(ctx
->i32
), soffset
,
2808 (4 * param_index
+ chan
) * 4,
2809 V_008F0C_BUF_DATA_FORMAT_32
,
2810 V_008F0C_BUF_NUM_FORMAT_UINT
,
2816 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2818 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2819 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2820 LLVMValueRef args
[2];
2822 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
2823 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2824 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2825 ctx
->voidt
, args
, 2, 0);
2828 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2830 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2831 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2832 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
2833 struct si_shader_output_values
*outputs
= NULL
;
2836 assert(!ctx
->is_gs_copy_shader
);
2838 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
2840 /* Vertex color clamping.
2842 * This uses a state constant loaded in a user data SGPR and
2843 * an IF statement is added that clamps all colors if the constant
2846 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
2847 struct lp_build_if_state if_ctx
;
2848 LLVMValueRef cond
= NULL
;
2849 LLVMValueRef addr
, val
;
2851 for (i
= 0; i
< info
->num_outputs
; i
++) {
2852 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
2853 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
2856 /* We've found a color. */
2858 /* The state is in the first bit of the user SGPR. */
2859 cond
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
2860 SI_PARAM_VS_STATE_BITS
);
2861 cond
= LLVMBuildTrunc(gallivm
->builder
, cond
,
2863 lp_build_if(&if_ctx
, gallivm
, cond
);
2866 for (j
= 0; j
< 4; j
++) {
2867 addr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
2868 val
= LLVMBuildLoad(gallivm
->builder
, addr
, "");
2869 val
= radeon_llvm_saturate(bld_base
, val
);
2870 LLVMBuildStore(gallivm
->builder
, val
, addr
);
2875 lp_build_endif(&if_ctx
);
2878 for (i
= 0; i
< info
->num_outputs
; i
++) {
2879 outputs
[i
].name
= info
->output_semantic_name
[i
];
2880 outputs
[i
].sid
= info
->output_semantic_index
[i
];
2882 for (j
= 0; j
< 4; j
++)
2883 outputs
[i
].values
[j
] =
2884 LLVMBuildLoad(gallivm
->builder
,
2885 ctx
->radeon_bld
.soa
.outputs
[i
][j
],
2889 if (ctx
->is_monolithic
) {
2890 /* Export PrimitiveID when PS needs it. */
2891 if (si_vs_exports_prim_id(ctx
->shader
)) {
2892 outputs
[i
].name
= TGSI_SEMANTIC_PRIMID
;
2894 outputs
[i
].values
[0] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2895 get_primitive_id(bld_base
, 0));
2896 outputs
[i
].values
[1] = bld_base
->base
.undef
;
2897 outputs
[i
].values
[2] = bld_base
->base
.undef
;
2898 outputs
[i
].values
[3] = bld_base
->base
.undef
;
2902 /* Return the primitive ID from the LLVM function. */
2904 LLVMBuildInsertValue(gallivm
->builder
,
2906 bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2907 get_primitive_id(bld_base
, 0)),
2908 VS_EPILOG_PRIMID_LOC
, "");
2911 si_llvm_export_vs(bld_base
, outputs
, i
);
2915 struct si_ps_exports
{
2917 LLVMValueRef args
[10][9];
2920 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
2921 LLVMValueRef depth
, LLVMValueRef stencil
,
2922 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
2924 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2925 struct lp_build_context
*base
= &bld_base
->base
;
2926 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2927 LLVMValueRef args
[9];
2930 assert(depth
|| stencil
|| samplemask
);
2932 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
2933 args
[2] = uint
->one
; /* DONE bit */
2935 /* Specify the target we are exporting */
2936 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
2938 args
[4] = uint
->zero
; /* COMP flag */
2939 args
[5] = base
->undef
; /* R, depth */
2940 args
[6] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
2941 args
[7] = base
->undef
; /* B, sample mask */
2942 args
[8] = base
->undef
; /* A, alpha to mask */
2955 args
[7] = samplemask
;
2959 /* SI (except OLAND) has a bug that it only looks
2960 * at the X writemask component. */
2961 if (ctx
->screen
->b
.chip_class
== SI
&&
2962 ctx
->screen
->b
.family
!= CHIP_OLAND
)
2965 /* Specify which components to enable */
2966 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
2968 memcpy(exp
->args
[exp
->num
++], args
, sizeof(args
));
2971 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
2972 LLVMValueRef
*color
, unsigned index
,
2973 unsigned samplemask_param
,
2974 bool is_last
, struct si_ps_exports
*exp
)
2976 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2977 struct lp_build_context
*base
= &bld_base
->base
;
2981 if (ctx
->shader
->key
.ps
.epilog
.clamp_color
)
2982 for (i
= 0; i
< 4; i
++)
2983 color
[i
] = radeon_llvm_saturate(bld_base
, color
[i
]);
2986 if (ctx
->shader
->key
.ps
.epilog
.alpha_to_one
)
2987 color
[3] = base
->one
;
2991 ctx
->shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
2992 si_alpha_test(bld_base
, color
[3]);
2994 /* Line & polygon smoothing */
2995 if (ctx
->shader
->key
.ps
.epilog
.poly_line_smoothing
)
2996 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
2999 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3000 if (ctx
->shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3001 LLVMValueRef args
[8][9];
3004 /* Get the export arguments, also find out what the last one is. */
3005 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3006 si_llvm_init_export_args(bld_base
, color
,
3007 V_008DFC_SQ_EXP_MRT
+ c
, args
[c
]);
3008 if (args
[c
][0] != bld_base
->uint_bld
.zero
)
3012 /* Emit all exports. */
3013 for (c
= 0; c
<= ctx
->shader
->key
.ps
.epilog
.last_cbuf
; c
++) {
3014 if (is_last
&& last
== c
) {
3015 args
[c
][1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3016 args
[c
][2] = bld_base
->uint_bld
.one
; /* DONE bit */
3017 } else if (args
[c
][0] == bld_base
->uint_bld
.zero
)
3018 continue; /* unnecessary NULL export */
3020 memcpy(exp
->args
[exp
->num
++], args
[c
], sizeof(args
[c
]));
3023 LLVMValueRef args
[9];
3026 si_llvm_init_export_args(bld_base
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3029 args
[1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
3030 args
[2] = bld_base
->uint_bld
.one
; /* DONE bit */
3031 } else if (args
[0] == bld_base
->uint_bld
.zero
)
3032 return; /* unnecessary NULL export */
3034 memcpy(exp
->args
[exp
->num
++], args
, sizeof(args
));
3038 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3039 struct si_ps_exports
*exp
)
3041 for (unsigned i
= 0; i
< exp
->num
; i
++)
3042 lp_build_intrinsic(ctx
->radeon_bld
.gallivm
.builder
,
3043 "llvm.SI.export", ctx
->voidt
,
3044 exp
->args
[i
], 9, 0);
3047 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
3049 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3050 struct lp_build_context
*base
= &bld_base
->base
;
3051 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
3052 LLVMValueRef args
[9];
3054 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
3055 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
3056 args
[2] = uint
->one
; /* DONE bit */
3057 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
3058 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
3059 args
[5] = base
->undef
; /* R */
3060 args
[6] = base
->undef
; /* G */
3061 args
[7] = base
->undef
; /* B */
3062 args
[8] = base
->undef
; /* A */
3064 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
3065 ctx
->voidt
, args
, 9, 0);
3068 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3070 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3071 struct si_shader
*shader
= ctx
->shader
;
3072 struct lp_build_context
*base
= &bld_base
->base
;
3073 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3074 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3075 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3076 int last_color_export
= -1;
3078 struct si_ps_exports exp
= {};
3080 /* Determine the last export. If MRTZ is present, it's always last.
3081 * Otherwise, find the last color export.
3083 if (!info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
) {
3084 unsigned spi_format
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
3086 /* Don't export NULL and return if alpha-test is enabled. */
3087 if (shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
&&
3088 shader
->key
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
&&
3089 (spi_format
& 0xf) == 0)
3090 spi_format
|= V_028714_SPI_SHADER_32_AR
;
3092 for (i
= 0; i
< info
->num_outputs
; i
++) {
3093 unsigned index
= info
->output_semantic_index
[i
];
3095 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
)
3098 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3099 if (shader
->key
.ps
.epilog
.last_cbuf
> 0) {
3100 /* Just set this if any of the colorbuffers are enabled. */
3102 ((1llu << (4 * (shader
->key
.ps
.epilog
.last_cbuf
+ 1))) - 1))
3103 last_color_export
= i
;
3107 if ((spi_format
>> (index
* 4)) & 0xf)
3108 last_color_export
= i
;
3111 /* If there are no outputs, export NULL. */
3112 if (last_color_export
== -1) {
3113 si_export_null(bld_base
);
3118 for (i
= 0; i
< info
->num_outputs
; i
++) {
3119 unsigned semantic_name
= info
->output_semantic_name
[i
];
3120 unsigned semantic_index
= info
->output_semantic_index
[i
];
3122 LLVMValueRef color
[4] = {};
3124 /* Select the correct target */
3125 switch (semantic_name
) {
3126 case TGSI_SEMANTIC_POSITION
:
3127 depth
= LLVMBuildLoad(builder
,
3128 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3130 case TGSI_SEMANTIC_STENCIL
:
3131 stencil
= LLVMBuildLoad(builder
,
3132 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3134 case TGSI_SEMANTIC_SAMPLEMASK
:
3135 samplemask
= LLVMBuildLoad(builder
,
3136 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3138 case TGSI_SEMANTIC_COLOR
:
3139 for (j
= 0; j
< 4; j
++)
3140 color
[j
] = LLVMBuildLoad(builder
,
3141 ctx
->radeon_bld
.soa
.outputs
[i
][j
], "");
3143 si_export_mrt_color(bld_base
, color
, semantic_index
,
3144 SI_PARAM_SAMPLE_COVERAGE
,
3145 last_color_export
== i
, &exp
);
3149 "Warning: SI unhandled fs output type:%d\n",
3154 if (depth
|| stencil
|| samplemask
)
3155 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
3157 si_emit_ps_exports(ctx
, &exp
);
3161 * Return PS outputs in this order:
3163 * v[0:3] = color0.xyzw
3164 * v[4:7] = color1.xyzw
3169 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3171 * The alpha-ref SGPR is returned via its original location.
3173 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context
*bld_base
)
3175 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3176 struct si_shader
*shader
= ctx
->shader
;
3177 struct lp_build_context
*base
= &bld_base
->base
;
3178 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3179 LLVMBuilderRef builder
= base
->gallivm
->builder
;
3180 unsigned i
, j
, first_vgpr
, vgpr
;
3182 LLVMValueRef color
[8][4] = {};
3183 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3186 /* Read the output values. */
3187 for (i
= 0; i
< info
->num_outputs
; i
++) {
3188 unsigned semantic_name
= info
->output_semantic_name
[i
];
3189 unsigned semantic_index
= info
->output_semantic_index
[i
];
3191 switch (semantic_name
) {
3192 case TGSI_SEMANTIC_COLOR
:
3193 assert(semantic_index
< 8);
3194 for (j
= 0; j
< 4; j
++) {
3195 LLVMValueRef ptr
= ctx
->radeon_bld
.soa
.outputs
[i
][j
];
3196 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3197 color
[semantic_index
][j
] = result
;
3200 case TGSI_SEMANTIC_POSITION
:
3201 depth
= LLVMBuildLoad(builder
,
3202 ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
3204 case TGSI_SEMANTIC_STENCIL
:
3205 stencil
= LLVMBuildLoad(builder
,
3206 ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
3208 case TGSI_SEMANTIC_SAMPLEMASK
:
3209 samplemask
= LLVMBuildLoad(builder
,
3210 ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
3213 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3218 /* Fill the return structure. */
3219 ret
= ctx
->return_value
;
3222 ret
= LLVMBuildInsertValue(builder
, ret
,
3223 bitcast(bld_base
, TGSI_TYPE_SIGNED
,
3224 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3225 SI_PARAM_ALPHA_REF
)),
3226 SI_SGPR_ALPHA_REF
, "");
3229 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3230 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3234 for (j
= 0; j
< 4; j
++)
3235 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3238 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3240 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3242 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3244 /* Add the input sample mask for smoothing at the end. */
3245 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3246 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3247 ret
= LLVMBuildInsertValue(builder
, ret
,
3248 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
3249 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3251 ctx
->return_value
= ret
;
3255 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3256 * buffer in number of elements and return it as an i32.
3258 static LLVMValueRef
get_buffer_size(
3259 struct lp_build_tgsi_context
*bld_base
,
3260 LLVMValueRef descriptor
)
3262 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3263 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3264 LLVMBuilderRef builder
= gallivm
->builder
;
3266 LLVMBuildExtractElement(builder
, descriptor
,
3267 lp_build_const_int32(gallivm
, 6), "");
3269 if (ctx
->screen
->b
.chip_class
>= VI
) {
3270 /* On VI, the descriptor contains the size in bytes,
3271 * but TXQ must return the size in elements.
3272 * The stride is always non-zero for resources using TXQ.
3274 LLVMValueRef stride
=
3275 LLVMBuildExtractElement(builder
, descriptor
,
3276 lp_build_const_int32(gallivm
, 5), "");
3277 stride
= LLVMBuildLShr(builder
, stride
,
3278 lp_build_const_int32(gallivm
, 16), "");
3279 stride
= LLVMBuildAnd(builder
, stride
,
3280 lp_build_const_int32(gallivm
, 0x3FFF), "");
3282 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
3289 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3292 static void build_int_type_name(
3294 char *buf
, unsigned bufsize
)
3296 assert(bufsize
>= 6);
3298 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
3299 snprintf(buf
, bufsize
, "v%ui32",
3300 LLVMGetVectorSize(type
));
3305 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
3306 struct lp_build_tgsi_context
*bld_base
,
3307 struct lp_build_emit_data
*emit_data
);
3309 /* Prevent optimizations (at least of memory accesses) across the current
3310 * point in the program by emitting empty inline assembly that is marked as
3311 * having side effects.
3313 static void emit_optimization_barrier(struct si_shader_context
*ctx
)
3315 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3316 LLVMTypeRef ftype
= LLVMFunctionType(ctx
->voidt
, NULL
, 0, false);
3317 LLVMValueRef inlineasm
= LLVMConstInlineAsm(ftype
, "", "", true, false);
3318 LLVMBuildCall(builder
, inlineasm
, NULL
, 0, "");
3321 static void emit_waitcnt(struct si_shader_context
*ctx
)
3323 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3324 LLVMBuilderRef builder
= gallivm
->builder
;
3325 LLVMValueRef args
[1] = {
3326 lp_build_const_int32(gallivm
, 0xf70)
3328 lp_build_intrinsic(builder
, "llvm.amdgcn.s.waitcnt",
3329 ctx
->voidt
, args
, 1, 0);
3332 static void membar_emit(
3333 const struct lp_build_tgsi_action
*action
,
3334 struct lp_build_tgsi_context
*bld_base
,
3335 struct lp_build_emit_data
*emit_data
)
3337 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3343 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
3344 const struct tgsi_full_src_register
*reg
)
3346 LLVMValueRef ind_index
;
3347 LLVMValueRef rsrc_ptr
;
3349 if (!reg
->Register
.Indirect
)
3350 return ctx
->shader_buffers
[reg
->Register
.Index
];
3352 ind_index
= get_bounded_indirect_index(ctx
, ®
->Indirect
,
3353 reg
->Register
.Index
,
3354 SI_NUM_SHADER_BUFFERS
);
3356 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
3357 return build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3360 static bool tgsi_is_array_sampler(unsigned target
)
3362 return target
== TGSI_TEXTURE_1D_ARRAY
||
3363 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
3364 target
== TGSI_TEXTURE_2D_ARRAY
||
3365 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
3366 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3367 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
3368 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3371 static bool tgsi_is_array_image(unsigned target
)
3373 return target
== TGSI_TEXTURE_3D
||
3374 target
== TGSI_TEXTURE_CUBE
||
3375 target
== TGSI_TEXTURE_1D_ARRAY
||
3376 target
== TGSI_TEXTURE_2D_ARRAY
||
3377 target
== TGSI_TEXTURE_CUBE_ARRAY
||
3378 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
3382 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3384 * At least on Tonga, executing image stores on images with DCC enabled and
3385 * non-trivial can eventually lead to lockups. This can occur when an
3386 * application binds an image as read-only but then uses a shader that writes
3387 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3388 * program termination) in this case, but it doesn't cost much to be a bit
3389 * nicer: disabling DCC in the shader still leads to undefined results but
3390 * avoids the lockup.
3392 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
3395 if (ctx
->screen
->b
.chip_class
<= CIK
) {
3398 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
3399 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
3400 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
3403 tmp
= LLVMBuildExtractElement(builder
, rsrc
, i32_6
, "");
3404 tmp
= LLVMBuildAnd(builder
, tmp
, i32_C
, "");
3405 return LLVMBuildInsertElement(builder
, rsrc
, tmp
, i32_6
, "");
3410 * Load the resource descriptor for \p image.
3414 struct lp_build_tgsi_context
*bld_base
,
3415 const struct tgsi_full_src_register
*image
,
3419 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3421 assert(image
->Register
.File
== TGSI_FILE_IMAGE
);
3423 if (!image
->Register
.Indirect
) {
3424 /* Fast path: use preloaded resources */
3425 *rsrc
= ctx
->images
[image
->Register
.Index
];
3427 /* Indexing and manual load */
3428 LLVMValueRef ind_index
;
3429 LLVMValueRef rsrc_ptr
;
3432 /* From the GL_ARB_shader_image_load_store extension spec:
3434 * If a shader performs an image load, store, or atomic
3435 * operation using an image variable declared as an array,
3436 * and if the index used to select an individual element is
3437 * negative or greater than or equal to the size of the
3438 * array, the results of the operation are undefined but may
3439 * not lead to termination.
3441 ind_index
= get_bounded_indirect_index(ctx
, &image
->Indirect
,
3442 image
->Register
.Index
,
3445 rsrc_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
3446 tmp
= build_indexed_load_const(ctx
, rsrc_ptr
, ind_index
);
3448 tmp
= force_dcc_off(ctx
, tmp
);
3453 static LLVMValueRef
image_fetch_coords(
3454 struct lp_build_tgsi_context
*bld_base
,
3455 const struct tgsi_full_instruction
*inst
,
3458 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3459 LLVMBuilderRef builder
= gallivm
->builder
;
3460 unsigned target
= inst
->Memory
.Texture
;
3461 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
3462 LLVMValueRef coords
[4];
3466 for (chan
= 0; chan
< num_coords
; ++chan
) {
3467 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
3468 tmp
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3472 if (num_coords
== 1)
3475 if (num_coords
== 3) {
3476 /* LLVM has difficulties lowering 3-element vectors. */
3477 coords
[3] = bld_base
->uint_bld
.undef
;
3481 return lp_build_gather_values(gallivm
, coords
, num_coords
);
3485 * Append the extra mode bits that are used by image load and store.
3487 static void image_append_args(
3488 struct si_shader_context
*ctx
,
3489 struct lp_build_emit_data
* emit_data
,
3493 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3494 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3495 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3497 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* r128 */
3498 emit_data
->args
[emit_data
->arg_count
++] =
3499 tgsi_is_array_image(target
) ? i1true
: i1false
; /* da */
3501 emit_data
->args
[emit_data
->arg_count
++] =
3502 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3503 i1true
: i1false
; /* glc */
3505 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3509 * Given a 256 bit resource, extract the top half (which stores the buffer
3510 * resource in the case of textures and images).
3512 static LLVMValueRef
extract_rsrc_top_half(
3513 struct si_shader_context
*ctx
,
3516 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3517 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
3518 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
3520 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, v2i128
, "");
3521 rsrc
= LLVMBuildExtractElement(gallivm
->builder
, rsrc
, bld_base
->uint_bld
.one
, "");
3522 rsrc
= LLVMBuildBitCast(gallivm
->builder
, rsrc
, ctx
->v4i32
, "");
3528 * Append the resource and indexing arguments for buffer intrinsics.
3530 * \param rsrc the v4i32 buffer resource
3531 * \param index index into the buffer (stride-based)
3532 * \param offset byte offset into the buffer
3534 static void buffer_append_args(
3535 struct si_shader_context
*ctx
,
3536 struct lp_build_emit_data
*emit_data
,
3539 LLVMValueRef offset
,
3542 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3543 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
3544 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
3546 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3547 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
3548 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
3550 emit_data
->args
[emit_data
->arg_count
++] =
3551 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
3552 i1true
: i1false
; /* glc */
3554 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
3557 static void load_fetch_args(
3558 struct lp_build_tgsi_context
* bld_base
,
3559 struct lp_build_emit_data
* emit_data
)
3561 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3562 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3563 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3564 unsigned target
= inst
->Memory
.Texture
;
3567 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
3569 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3570 LLVMBuilderRef builder
= gallivm
->builder
;
3571 LLVMValueRef offset
;
3574 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3576 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3577 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3579 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3581 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3582 LLVMValueRef coords
;
3584 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, &rsrc
);
3585 coords
= image_fetch_coords(bld_base
, inst
, 1);
3587 if (target
== TGSI_TEXTURE_BUFFER
) {
3588 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3589 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3590 bld_base
->uint_bld
.zero
, false);
3592 emit_data
->args
[0] = coords
;
3593 emit_data
->args
[1] = rsrc
;
3594 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
3595 emit_data
->arg_count
= 3;
3597 image_append_args(ctx
, emit_data
, target
, false);
3602 static void load_emit_buffer(struct si_shader_context
*ctx
,
3603 struct lp_build_emit_data
*emit_data
)
3605 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3606 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3607 LLVMBuilderRef builder
= gallivm
->builder
;
3608 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
3609 uint count
= util_last_bit(writemask
);
3610 const char *intrinsic_name
;
3611 LLVMTypeRef dst_type
;
3615 intrinsic_name
= "llvm.amdgcn.buffer.load.f32";
3616 dst_type
= ctx
->f32
;
3619 intrinsic_name
= "llvm.amdgcn.buffer.load.v2f32";
3620 dst_type
= LLVMVectorType(ctx
->f32
, 2);
3623 intrinsic_name
= "llvm.amdgcn.buffer.load.v4f32";
3624 dst_type
= ctx
->v4f32
;
3628 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3629 builder
, intrinsic_name
, dst_type
,
3630 emit_data
->args
, emit_data
->arg_count
,
3631 LLVMReadOnlyAttribute
);
3634 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
3635 const struct tgsi_full_instruction
*inst
,
3636 LLVMTypeRef type
, int arg
)
3638 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3639 LLVMBuilderRef builder
= gallivm
->builder
;
3640 LLVMValueRef offset
, ptr
;
3643 offset
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, arg
, 0);
3644 offset
= LLVMBuildBitCast(builder
, offset
, ctx
->i32
, "");
3646 ptr
= ctx
->shared_memory
;
3647 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
3648 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
3649 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
3654 static void load_emit_memory(
3655 struct si_shader_context
*ctx
,
3656 struct lp_build_emit_data
*emit_data
)
3658 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3659 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3660 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3661 LLVMBuilderRef builder
= gallivm
->builder
;
3662 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3663 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
3666 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 1);
3668 for (chan
= 0; chan
< 4; ++chan
) {
3669 if (!(writemask
& (1 << chan
))) {
3670 channels
[chan
] = LLVMGetUndef(base
->elem_type
);
3674 index
= lp_build_const_int32(gallivm
, chan
);
3675 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3676 channels
[chan
] = LLVMBuildLoad(builder
, derived_ptr
, "");
3678 emit_data
->output
[emit_data
->chan
] = lp_build_gather_values(gallivm
, channels
, 4);
3681 static void load_emit(
3682 const struct lp_build_tgsi_action
*action
,
3683 struct lp_build_tgsi_context
*bld_base
,
3684 struct lp_build_emit_data
*emit_data
)
3686 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3687 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3688 LLVMBuilderRef builder
= gallivm
->builder
;
3689 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3690 char intrinsic_name
[32];
3691 char coords_type
[8];
3693 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3694 load_emit_memory(ctx
, emit_data
);
3698 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3701 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3702 load_emit_buffer(ctx
, emit_data
);
3706 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
3707 emit_data
->output
[emit_data
->chan
] =
3709 builder
, "llvm.amdgcn.buffer.load.format.v4f32", emit_data
->dst_type
,
3710 emit_data
->args
, emit_data
->arg_count
,
3711 LLVMReadOnlyAttribute
);
3713 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]),
3714 coords_type
, sizeof(coords_type
));
3716 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3717 "llvm.amdgcn.image.load.%s", coords_type
);
3719 emit_data
->output
[emit_data
->chan
] =
3721 builder
, intrinsic_name
, emit_data
->dst_type
,
3722 emit_data
->args
, emit_data
->arg_count
,
3723 LLVMReadOnlyAttribute
);
3727 static void store_fetch_args(
3728 struct lp_build_tgsi_context
* bld_base
,
3729 struct lp_build_emit_data
* emit_data
)
3731 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3732 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3733 LLVMBuilderRef builder
= gallivm
->builder
;
3734 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3735 struct tgsi_full_src_register memory
;
3736 LLVMValueRef chans
[4];
3741 emit_data
->dst_type
= LLVMVoidTypeInContext(gallivm
->context
);
3743 for (chan
= 0; chan
< 4; ++chan
) {
3744 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
3746 data
= lp_build_gather_values(gallivm
, chans
, 4);
3748 emit_data
->args
[emit_data
->arg_count
++] = data
;
3750 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
3752 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3753 LLVMValueRef offset
;
3756 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
);
3758 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
3759 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3761 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3763 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3764 unsigned target
= inst
->Memory
.Texture
;
3765 LLVMValueRef coords
;
3767 coords
= image_fetch_coords(bld_base
, inst
, 0);
3769 if (target
== TGSI_TEXTURE_BUFFER
) {
3770 image_fetch_rsrc(bld_base
, &memory
, false, &rsrc
);
3772 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3773 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3774 bld_base
->uint_bld
.zero
, false);
3776 emit_data
->args
[1] = coords
;
3777 image_fetch_rsrc(bld_base
, &memory
, true, &emit_data
->args
[2]);
3778 emit_data
->args
[3] = lp_build_const_int32(gallivm
, 15); /* dmask */
3779 emit_data
->arg_count
= 4;
3781 image_append_args(ctx
, emit_data
, target
, false);
3786 static void store_emit_buffer(
3787 struct si_shader_context
*ctx
,
3788 struct lp_build_emit_data
*emit_data
)
3790 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3791 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3792 LLVMBuilderRef builder
= gallivm
->builder
;
3793 struct lp_build_context
*uint_bld
= &ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
3794 LLVMValueRef base_data
= emit_data
->args
[0];
3795 LLVMValueRef base_offset
= emit_data
->args
[3];
3796 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3800 const char *intrinsic_name
;
3802 LLVMValueRef offset
;
3805 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
3807 /* Due to an LLVM limitation, split 3-element writes
3808 * into a 2-element and a 1-element write. */
3810 writemask
|= 1 << (start
+ 2);
3816 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
3817 } else if (count
== 2) {
3818 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
3820 tmp
= LLVMBuildExtractElement(
3822 lp_build_const_int32(gallivm
, start
), "");
3823 data
= LLVMBuildInsertElement(
3824 builder
, LLVMGetUndef(v2f32
), tmp
,
3825 uint_bld
->zero
, "");
3827 tmp
= LLVMBuildExtractElement(
3829 lp_build_const_int32(gallivm
, start
+ 1), "");
3830 data
= LLVMBuildInsertElement(
3831 builder
, data
, tmp
, uint_bld
->one
, "");
3833 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
3836 data
= LLVMBuildExtractElement(
3838 lp_build_const_int32(gallivm
, start
), "");
3839 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
3842 offset
= base_offset
;
3844 offset
= LLVMBuildAdd(
3846 lp_build_const_int32(gallivm
, start
* 4), "");
3849 emit_data
->args
[0] = data
;
3850 emit_data
->args
[3] = offset
;
3853 builder
, intrinsic_name
, emit_data
->dst_type
,
3854 emit_data
->args
, emit_data
->arg_count
, 0);
3858 static void store_emit_memory(
3859 struct si_shader_context
*ctx
,
3860 struct lp_build_emit_data
*emit_data
)
3862 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3863 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3864 struct lp_build_context
*base
= &ctx
->radeon_bld
.soa
.bld_base
.base
;
3865 LLVMBuilderRef builder
= gallivm
->builder
;
3866 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
3867 LLVMValueRef ptr
, derived_ptr
, data
, index
;
3870 ptr
= get_memory_ptr(ctx
, inst
, base
->elem_type
, 0);
3872 for (chan
= 0; chan
< 4; ++chan
) {
3873 if (!(writemask
& (1 << chan
))) {
3876 data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 1, chan
);
3877 index
= lp_build_const_int32(gallivm
, chan
);
3878 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3879 LLVMBuildStore(builder
, data
, derived_ptr
);
3883 static void store_emit(
3884 const struct lp_build_tgsi_action
*action
,
3885 struct lp_build_tgsi_context
*bld_base
,
3886 struct lp_build_emit_data
*emit_data
)
3888 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3889 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3890 LLVMBuilderRef builder
= gallivm
->builder
;
3891 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3892 unsigned target
= inst
->Memory
.Texture
;
3893 char intrinsic_name
[32];
3894 char coords_type
[8];
3896 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
3897 store_emit_memory(ctx
, emit_data
);
3901 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
3904 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3905 store_emit_buffer(ctx
, emit_data
);
3909 if (target
== TGSI_TEXTURE_BUFFER
) {
3910 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
3911 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
3912 emit_data
->dst_type
, emit_data
->args
,
3913 emit_data
->arg_count
, 0);
3915 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
3916 coords_type
, sizeof(coords_type
));
3917 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3918 "llvm.amdgcn.image.store.%s", coords_type
);
3920 emit_data
->output
[emit_data
->chan
] =
3922 builder
, intrinsic_name
, emit_data
->dst_type
,
3923 emit_data
->args
, emit_data
->arg_count
, 0);
3927 static void atomic_fetch_args(
3928 struct lp_build_tgsi_context
* bld_base
,
3929 struct lp_build_emit_data
* emit_data
)
3931 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3932 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3933 LLVMBuilderRef builder
= gallivm
->builder
;
3934 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3935 LLVMValueRef data1
, data2
;
3939 emit_data
->dst_type
= bld_base
->base
.elem_type
;
3941 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
3942 data1
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3944 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
3945 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
3946 data2
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3949 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3950 * of arguments, which is reversed relative to TGSI (and GLSL)
3952 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
3953 emit_data
->args
[emit_data
->arg_count
++] = data2
;
3954 emit_data
->args
[emit_data
->arg_count
++] = data1
;
3956 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
3957 LLVMValueRef offset
;
3959 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0]);
3961 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
3962 offset
= LLVMBuildBitCast(builder
, tmp
, bld_base
->uint_bld
.elem_type
, "");
3964 buffer_append_args(ctx
, emit_data
, rsrc
, bld_base
->uint_bld
.zero
,
3966 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
3967 unsigned target
= inst
->Memory
.Texture
;
3968 LLVMValueRef coords
;
3970 image_fetch_rsrc(bld_base
, &inst
->Src
[0],
3971 target
!= TGSI_TEXTURE_BUFFER
, &rsrc
);
3972 coords
= image_fetch_coords(bld_base
, inst
, 1);
3974 if (target
== TGSI_TEXTURE_BUFFER
) {
3975 rsrc
= extract_rsrc_top_half(ctx
, rsrc
);
3976 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
3977 bld_base
->uint_bld
.zero
, true);
3979 emit_data
->args
[emit_data
->arg_count
++] = coords
;
3980 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
3982 image_append_args(ctx
, emit_data
, target
, true);
3987 static void atomic_emit_memory(struct si_shader_context
*ctx
,
3988 struct lp_build_emit_data
*emit_data
) {
3989 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
3990 LLVMBuilderRef builder
= gallivm
->builder
;
3991 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
3992 LLVMValueRef ptr
, result
, arg
;
3994 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
3996 arg
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
, inst
, 2, 0);
3997 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
3999 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4000 LLVMValueRef new_data
;
4001 new_data
= lp_build_emit_fetch(&ctx
->radeon_bld
.soa
.bld_base
,
4004 new_data
= LLVMBuildBitCast(builder
, new_data
, ctx
->i32
, "");
4006 #if HAVE_LLVM >= 0x309
4007 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
4008 LLVMAtomicOrderingSequentiallyConsistent
,
4009 LLVMAtomicOrderingSequentiallyConsistent
,
4013 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
4015 LLVMAtomicRMWBinOp op
;
4017 switch(inst
->Instruction
.Opcode
) {
4018 case TGSI_OPCODE_ATOMUADD
:
4019 op
= LLVMAtomicRMWBinOpAdd
;
4021 case TGSI_OPCODE_ATOMXCHG
:
4022 op
= LLVMAtomicRMWBinOpXchg
;
4024 case TGSI_OPCODE_ATOMAND
:
4025 op
= LLVMAtomicRMWBinOpAnd
;
4027 case TGSI_OPCODE_ATOMOR
:
4028 op
= LLVMAtomicRMWBinOpOr
;
4030 case TGSI_OPCODE_ATOMXOR
:
4031 op
= LLVMAtomicRMWBinOpXor
;
4033 case TGSI_OPCODE_ATOMUMIN
:
4034 op
= LLVMAtomicRMWBinOpUMin
;
4036 case TGSI_OPCODE_ATOMUMAX
:
4037 op
= LLVMAtomicRMWBinOpUMax
;
4039 case TGSI_OPCODE_ATOMIMIN
:
4040 op
= LLVMAtomicRMWBinOpMin
;
4042 case TGSI_OPCODE_ATOMIMAX
:
4043 op
= LLVMAtomicRMWBinOpMax
;
4046 unreachable("unknown atomic opcode");
4049 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
4050 LLVMAtomicOrderingSequentiallyConsistent
,
4053 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
4056 static void atomic_emit(
4057 const struct lp_build_tgsi_action
*action
,
4058 struct lp_build_tgsi_context
*bld_base
,
4059 struct lp_build_emit_data
*emit_data
)
4061 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4062 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4063 LLVMBuilderRef builder
= gallivm
->builder
;
4064 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
4065 char intrinsic_name
[40];
4068 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
4069 atomic_emit_memory(ctx
, emit_data
);
4073 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
4074 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4075 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4076 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
4078 char coords_type
[8];
4080 build_int_type_name(LLVMTypeOf(emit_data
->args
[1]),
4081 coords_type
, sizeof(coords_type
));
4082 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
4083 "llvm.amdgcn.image.atomic.%s.%s",
4084 action
->intr_name
, coords_type
);
4087 tmp
= lp_build_intrinsic(
4088 builder
, intrinsic_name
, bld_base
->uint_bld
.elem_type
,
4089 emit_data
->args
, emit_data
->arg_count
, 0);
4090 emit_data
->output
[emit_data
->chan
] =
4091 LLVMBuildBitCast(builder
, tmp
, bld_base
->base
.elem_type
, "");
4094 static void resq_fetch_args(
4095 struct lp_build_tgsi_context
* bld_base
,
4096 struct lp_build_emit_data
* emit_data
)
4098 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4099 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4100 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4101 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
4103 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
4105 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
4106 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
);
4107 emit_data
->arg_count
= 1;
4108 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4109 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[0]);
4110 emit_data
->arg_count
= 1;
4112 emit_data
->args
[0] = bld_base
->uint_bld
.zero
; /* mip level */
4113 image_fetch_rsrc(bld_base
, reg
, false, &emit_data
->args
[1]);
4114 emit_data
->args
[2] = lp_build_const_int32(gallivm
, 15); /* dmask */
4115 emit_data
->args
[3] = bld_base
->uint_bld
.zero
; /* unorm */
4116 emit_data
->args
[4] = bld_base
->uint_bld
.zero
; /* r128 */
4117 emit_data
->args
[5] = tgsi_is_array_image(inst
->Memory
.Texture
) ?
4118 bld_base
->uint_bld
.one
: bld_base
->uint_bld
.zero
; /* da */
4119 emit_data
->args
[6] = bld_base
->uint_bld
.zero
; /* glc */
4120 emit_data
->args
[7] = bld_base
->uint_bld
.zero
; /* slc */
4121 emit_data
->args
[8] = bld_base
->uint_bld
.zero
; /* tfe */
4122 emit_data
->args
[9] = bld_base
->uint_bld
.zero
; /* lwe */
4123 emit_data
->arg_count
= 10;
4127 static void resq_emit(
4128 const struct lp_build_tgsi_action
*action
,
4129 struct lp_build_tgsi_context
*bld_base
,
4130 struct lp_build_emit_data
*emit_data
)
4132 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4133 LLVMBuilderRef builder
= gallivm
->builder
;
4134 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4137 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
4138 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
4139 lp_build_const_int32(gallivm
, 2), "");
4140 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
4141 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
4143 out
= lp_build_intrinsic(
4144 builder
, "llvm.SI.getresinfo.i32", emit_data
->dst_type
,
4145 emit_data
->args
, emit_data
->arg_count
,
4146 LLVMReadNoneAttribute
);
4148 /* Divide the number of layers by 6 to get the number of cubes. */
4149 if (inst
->Memory
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
) {
4150 LLVMValueRef imm2
= lp_build_const_int32(gallivm
, 2);
4151 LLVMValueRef imm6
= lp_build_const_int32(gallivm
, 6);
4153 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
4154 z
= LLVMBuildBitCast(builder
, z
, bld_base
->uint_bld
.elem_type
, "");
4155 z
= LLVMBuildSDiv(builder
, z
, imm6
, "");
4156 z
= LLVMBuildBitCast(builder
, z
, bld_base
->base
.elem_type
, "");
4157 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
4161 emit_data
->output
[emit_data
->chan
] = out
;
4164 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
4165 struct lp_build_emit_data
*emit_data
,
4166 unsigned opcode
, unsigned target
,
4167 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4168 LLVMValueRef
*param
, unsigned count
,
4171 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4173 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
4175 /* Pad to power of two vector */
4176 while (count
< util_next_power_of_two(count
))
4177 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4179 /* Texture coordinates. */
4181 emit_data
->args
[0] = lp_build_gather_values(gallivm
, param
, count
);
4183 emit_data
->args
[0] = param
[0];
4186 emit_data
->args
[1] = res_ptr
;
4189 if (opcode
== TGSI_OPCODE_TXF
|| opcode
== TGSI_OPCODE_TXQ
)
4190 emit_data
->dst_type
= ctx
->v4i32
;
4192 emit_data
->dst_type
= ctx
->v4f32
;
4194 emit_data
->args
[num_args
++] = samp_ptr
;
4197 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, dmask
);
4198 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
4199 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* r128 */
4200 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
,
4201 tgsi_is_array_sampler(target
)); /* da */
4202 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* glc */
4203 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* slc */
4204 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* tfe */
4205 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* lwe */
4207 emit_data
->arg_count
= num_args
;
4210 static const struct lp_build_tgsi_action tex_action
;
4218 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
4220 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
4225 * Load an image view, fmask view. or sampler state descriptor.
4227 static LLVMValueRef
get_sampler_desc_custom(struct si_shader_context
*ctx
,
4228 LLVMValueRef list
, LLVMValueRef index
,
4229 enum desc_type type
)
4231 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
4232 LLVMBuilderRef builder
= gallivm
->builder
;
4236 /* The image is at [0:7]. */
4237 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4240 /* The FMASK is at [8:15]. */
4241 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
4242 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 1, 0), "");
4245 /* The sampler state is at [12:15]. */
4246 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
4247 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
4248 list
= LLVMBuildPointerCast(builder
, list
,
4249 const_array(ctx
->v4i32
, 0), "");
4253 return build_indexed_load_const(ctx
, list
, index
);
4256 static LLVMValueRef
get_sampler_desc(struct si_shader_context
*ctx
,
4257 LLVMValueRef index
, enum desc_type type
)
4259 LLVMValueRef list
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
4262 return get_sampler_desc_custom(ctx
, list
, index
, type
);
4265 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4268 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4269 * filtering manually. The driver sets img7 to a mask clearing
4270 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4271 * s_and_b32 samp0, samp0, img7
4274 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4276 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
4277 LLVMValueRef res
, LLVMValueRef samp
)
4279 LLVMBuilderRef builder
= ctx
->radeon_bld
.gallivm
.builder
;
4280 LLVMValueRef img7
, samp0
;
4282 if (ctx
->screen
->b
.chip_class
>= VI
)
4285 img7
= LLVMBuildExtractElement(builder
, res
,
4286 LLVMConstInt(ctx
->i32
, 7, 0), "");
4287 samp0
= LLVMBuildExtractElement(builder
, samp
,
4288 LLVMConstInt(ctx
->i32
, 0, 0), "");
4289 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4290 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4291 LLVMConstInt(ctx
->i32
, 0, 0), "");
4294 static void tex_fetch_ptrs(
4295 struct lp_build_tgsi_context
*bld_base
,
4296 struct lp_build_emit_data
*emit_data
,
4297 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
4299 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4300 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4301 unsigned target
= inst
->Texture
.Texture
;
4302 unsigned sampler_src
;
4303 unsigned sampler_index
;
4305 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
4306 sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
4308 if (emit_data
->inst
->Src
[sampler_src
].Register
.Indirect
) {
4309 const struct tgsi_full_src_register
*reg
= &emit_data
->inst
->Src
[sampler_src
];
4310 LLVMValueRef ind_index
;
4312 ind_index
= get_bounded_indirect_index(ctx
,
4314 reg
->Register
.Index
,
4317 *res_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_IMAGE
);
4319 if (target
== TGSI_TEXTURE_2D_MSAA
||
4320 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4324 *fmask_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_FMASK
);
4327 *samp_ptr
= get_sampler_desc(ctx
, ind_index
, DESC_SAMPLER
);
4328 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4334 *res_ptr
= ctx
->sampler_views
[sampler_index
];
4336 *samp_ptr
= ctx
->sampler_states
[sampler_index
];
4338 *fmask_ptr
= ctx
->fmasks
[sampler_index
];
4342 static void txq_fetch_args(
4343 struct lp_build_tgsi_context
*bld_base
,
4344 struct lp_build_emit_data
*emit_data
)
4346 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4347 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4348 LLVMBuilderRef builder
= gallivm
->builder
;
4349 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4350 unsigned target
= inst
->Texture
.Texture
;
4351 LLVMValueRef res_ptr
;
4352 LLVMValueRef address
;
4354 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, NULL
, NULL
);
4356 if (target
== TGSI_TEXTURE_BUFFER
) {
4357 /* Read the size from the buffer descriptor directly. */
4358 LLVMValueRef res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4359 emit_data
->args
[0] = get_buffer_size(bld_base
, res
);
4363 /* Textures - set the mip level. */
4364 address
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
4366 set_tex_fetch_args(ctx
, emit_data
, TGSI_OPCODE_TXQ
, target
, res_ptr
,
4367 NULL
, &address
, 1, 0xf);
4370 static void txq_emit(const struct lp_build_tgsi_action
*action
,
4371 struct lp_build_tgsi_context
*bld_base
,
4372 struct lp_build_emit_data
*emit_data
)
4374 struct lp_build_context
*base
= &bld_base
->base
;
4375 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4377 if (target
== TGSI_TEXTURE_BUFFER
) {
4378 /* Just return the buffer size. */
4379 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
4383 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4384 base
->gallivm
->builder
, "llvm.SI.getresinfo.i32",
4385 emit_data
->dst_type
, emit_data
->args
, emit_data
->arg_count
,
4386 LLVMReadNoneAttribute
);
4388 /* Divide the number of layers by 6 to get the number of cubes. */
4389 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
4390 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4391 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
4392 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
4393 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
4395 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
4396 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
4397 z
= LLVMBuildSDiv(builder
, z
, six
, "");
4399 emit_data
->output
[emit_data
->chan
] =
4400 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
4404 static void tex_fetch_args(
4405 struct lp_build_tgsi_context
*bld_base
,
4406 struct lp_build_emit_data
*emit_data
)
4408 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4409 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4410 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4411 unsigned opcode
= inst
->Instruction
.Opcode
;
4412 unsigned target
= inst
->Texture
.Texture
;
4413 LLVMValueRef coords
[5], derivs
[6];
4414 LLVMValueRef address
[16];
4415 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
4416 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
4419 unsigned num_deriv_channels
= 0;
4420 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
4421 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4422 unsigned dmask
= 0xf;
4424 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4426 if (target
== TGSI_TEXTURE_BUFFER
) {
4427 LLVMTypeRef v2i128
= LLVMVectorType(ctx
->i128
, 2);
4429 /* Bitcast and truncate v8i32 to v16i8. */
4430 LLVMValueRef res
= res_ptr
;
4431 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
4432 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.one
, "");
4433 res
= LLVMBuildBitCast(gallivm
->builder
, res
, ctx
->v16i8
, "");
4435 emit_data
->dst_type
= ctx
->v4f32
;
4436 emit_data
->args
[0] = res
;
4437 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
4438 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4439 emit_data
->arg_count
= 3;
4443 /* Fetch and project texture coordinates */
4444 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
4445 for (chan
= 0; chan
< 3; chan
++ ) {
4446 coords
[chan
] = lp_build_emit_fetch(bld_base
,
4449 if (opcode
== TGSI_OPCODE_TXP
)
4450 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
4456 if (opcode
== TGSI_OPCODE_TXP
)
4457 coords
[3] = bld_base
->base
.one
;
4460 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
4461 /* The offsets are six-bit signed integers packed like this:
4462 * X=[5:0], Y=[13:8], and Z=[21:16].
4464 LLVMValueRef offset
[3], pack
;
4466 assert(inst
->Texture
.NumOffsets
== 1);
4468 for (chan
= 0; chan
< 3; chan
++) {
4469 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
4470 emit_data
->inst
, 0, chan
);
4471 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
4472 lp_build_const_int32(gallivm
, 0x3f), "");
4474 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
4475 lp_build_const_int32(gallivm
, chan
*8), "");
4478 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
4479 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
4480 address
[count
++] = pack
;
4483 /* Pack LOD bias value */
4484 if (opcode
== TGSI_OPCODE_TXB
)
4485 address
[count
++] = coords
[3];
4486 if (opcode
== TGSI_OPCODE_TXB2
)
4487 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4489 /* Pack depth comparison value */
4490 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
4491 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
4492 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4494 assert(ref_pos
>= 0);
4495 address
[count
++] = coords
[ref_pos
];
4499 /* Pack user derivatives */
4500 if (opcode
== TGSI_OPCODE_TXD
) {
4501 int param
, num_src_deriv_channels
;
4504 case TGSI_TEXTURE_3D
:
4505 num_src_deriv_channels
= 3;
4506 num_deriv_channels
= 3;
4508 case TGSI_TEXTURE_2D
:
4509 case TGSI_TEXTURE_SHADOW2D
:
4510 case TGSI_TEXTURE_RECT
:
4511 case TGSI_TEXTURE_SHADOWRECT
:
4512 case TGSI_TEXTURE_2D_ARRAY
:
4513 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4514 num_src_deriv_channels
= 2;
4515 num_deriv_channels
= 2;
4517 case TGSI_TEXTURE_CUBE
:
4518 case TGSI_TEXTURE_SHADOWCUBE
:
4519 case TGSI_TEXTURE_CUBE_ARRAY
:
4520 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
4521 /* Cube derivatives will be converted to 2D. */
4522 num_src_deriv_channels
= 3;
4523 num_deriv_channels
= 2;
4525 case TGSI_TEXTURE_1D
:
4526 case TGSI_TEXTURE_SHADOW1D
:
4527 case TGSI_TEXTURE_1D_ARRAY
:
4528 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4529 num_src_deriv_channels
= 1;
4530 num_deriv_channels
= 1;
4533 unreachable("invalid target");
4536 for (param
= 0; param
< 2; param
++)
4537 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
4538 derivs
[param
* num_src_deriv_channels
+ chan
] =
4539 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
4542 if (target
== TGSI_TEXTURE_CUBE
||
4543 target
== TGSI_TEXTURE_CUBE_ARRAY
||
4544 target
== TGSI_TEXTURE_SHADOWCUBE
||
4545 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
4546 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
, derivs
);
4548 if (opcode
== TGSI_OPCODE_TXD
)
4549 for (int i
= 0; i
< num_deriv_channels
* 2; i
++)
4550 address
[count
++] = derivs
[i
];
4552 /* Pack texture coordinates */
4553 address
[count
++] = coords
[0];
4555 address
[count
++] = coords
[1];
4557 address
[count
++] = coords
[2];
4559 /* Pack LOD or sample index */
4560 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
4561 address
[count
++] = coords
[3];
4562 else if (opcode
== TGSI_OPCODE_TXL2
)
4563 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
4566 assert(!"Cannot handle more than 16 texture address parameters");
4570 for (chan
= 0; chan
< count
; chan
++ ) {
4571 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
4572 address
[chan
], ctx
->i32
, "");
4575 /* Adjust the sample index according to FMASK.
4577 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4578 * which is the identity mapping. Each nibble says which physical sample
4579 * should be fetched to get that sample.
4581 * For example, 0x11111100 means there are only 2 samples stored and
4582 * the second sample covers 3/4 of the pixel. When reading samples 0
4583 * and 1, return physical sample 0 (determined by the first two 0s
4584 * in FMASK), otherwise return physical sample 1.
4586 * The sample index should be adjusted as follows:
4587 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4589 if (target
== TGSI_TEXTURE_2D_MSAA
||
4590 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
4591 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4592 struct lp_build_emit_data txf_emit_data
= *emit_data
;
4593 LLVMValueRef txf_address
[4];
4594 unsigned txf_count
= count
;
4595 struct tgsi_full_instruction inst
= {};
4597 memcpy(txf_address
, address
, sizeof(txf_address
));
4599 if (target
== TGSI_TEXTURE_2D_MSAA
) {
4600 txf_address
[2] = bld_base
->uint_bld
.zero
;
4602 txf_address
[3] = bld_base
->uint_bld
.zero
;
4604 /* Read FMASK using TXF. */
4605 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
4606 inst
.Texture
.Texture
= target
;
4607 txf_emit_data
.inst
= &inst
;
4608 txf_emit_data
.chan
= 0;
4609 set_tex_fetch_args(ctx
, &txf_emit_data
, TGSI_OPCODE_TXF
,
4610 target
, fmask_ptr
, NULL
,
4611 txf_address
, txf_count
, 0xf);
4612 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
4614 /* Initialize some constants. */
4615 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, 0);
4616 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xF, 0);
4618 /* Apply the formula. */
4619 LLVMValueRef fmask
=
4620 LLVMBuildExtractElement(gallivm
->builder
,
4621 txf_emit_data
.output
[0],
4622 uint_bld
->zero
, "");
4624 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
4626 LLVMValueRef sample_index4
=
4627 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
4629 LLVMValueRef shifted_fmask
=
4630 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
4632 LLVMValueRef final_sample
=
4633 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
4635 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4636 * resource descriptor is 0 (invalid),
4638 LLVMValueRef fmask_desc
=
4639 LLVMBuildBitCast(gallivm
->builder
, fmask_ptr
,
4642 LLVMValueRef fmask_word1
=
4643 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
4646 LLVMValueRef word1_is_nonzero
=
4647 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
4648 fmask_word1
, uint_bld
->zero
, "");
4650 /* Replace the MSAA sample index. */
4651 address
[sample_chan
] =
4652 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
4653 final_sample
, address
[sample_chan
], "");
4656 if (opcode
== TGSI_OPCODE_TXF
) {
4657 /* add tex offsets */
4658 if (inst
->Texture
.NumOffsets
) {
4659 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
4660 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
4661 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
4663 assert(inst
->Texture
.NumOffsets
== 1);
4666 case TGSI_TEXTURE_3D
:
4667 address
[2] = lp_build_add(uint_bld
, address
[2],
4668 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
4670 case TGSI_TEXTURE_2D
:
4671 case TGSI_TEXTURE_SHADOW2D
:
4672 case TGSI_TEXTURE_RECT
:
4673 case TGSI_TEXTURE_SHADOWRECT
:
4674 case TGSI_TEXTURE_2D_ARRAY
:
4675 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4677 lp_build_add(uint_bld
, address
[1],
4678 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
4680 case TGSI_TEXTURE_1D
:
4681 case TGSI_TEXTURE_SHADOW1D
:
4682 case TGSI_TEXTURE_1D_ARRAY
:
4683 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4685 lp_build_add(uint_bld
, address
[0],
4686 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
4688 /* texture offsets do not apply to other texture targets */
4693 if (opcode
== TGSI_OPCODE_TG4
) {
4694 unsigned gather_comp
= 0;
4696 /* DMASK was repurposed for GATHER4. 4 components are always
4697 * returned and DMASK works like a swizzle - it selects
4698 * the component to fetch. The only valid DMASK values are
4699 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4700 * (red,red,red,red) etc.) The ISA document doesn't mention
4704 /* Get the component index from src1.x for Gather4. */
4705 if (!tgsi_is_shadow_target(target
)) {
4706 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
4707 LLVMValueRef comp_imm
;
4708 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
4710 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
4712 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
4713 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
4714 gather_comp
= CLAMP(gather_comp
, 0, 3);
4717 dmask
= 1 << gather_comp
;
4720 set_tex_fetch_args(ctx
, emit_data
, opcode
, target
, res_ptr
,
4721 samp_ptr
, address
, count
, dmask
);
4724 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
4725 struct lp_build_tgsi_context
*bld_base
,
4726 struct lp_build_emit_data
*emit_data
)
4728 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4729 struct lp_build_context
*base
= &bld_base
->base
;
4730 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
4731 unsigned target
= emit_data
->inst
->Texture
.Texture
;
4732 char intr_name
[127];
4733 bool has_offset
= emit_data
->inst
->Texture
.NumOffsets
> 0;
4734 bool is_shadow
= tgsi_is_shadow_target(target
);
4736 const char *name
= "llvm.SI.image.sample";
4737 const char *infix
= "";
4739 if (target
== TGSI_TEXTURE_BUFFER
) {
4740 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4741 base
->gallivm
->builder
,
4742 "llvm.SI.vs.load.input", emit_data
->dst_type
,
4743 emit_data
->args
, emit_data
->arg_count
,
4744 LLVMReadNoneAttribute
);
4749 case TGSI_OPCODE_TXF
:
4750 name
= target
== TGSI_TEXTURE_2D_MSAA
||
4751 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
4752 "llvm.SI.image.load" :
4753 "llvm.SI.image.load.mip";
4757 case TGSI_OPCODE_LODQ
:
4758 name
= "llvm.SI.getlod";
4762 case TGSI_OPCODE_TEX
:
4763 case TGSI_OPCODE_TEX2
:
4764 case TGSI_OPCODE_TXP
:
4765 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
4768 case TGSI_OPCODE_TXB
:
4769 case TGSI_OPCODE_TXB2
:
4770 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
4773 case TGSI_OPCODE_TXL
:
4774 case TGSI_OPCODE_TXL2
:
4777 case TGSI_OPCODE_TXD
:
4780 case TGSI_OPCODE_TG4
:
4781 name
= "llvm.SI.gather4";
4789 /* Add the type and suffixes .c, .o if needed. */
4790 build_int_type_name(LLVMTypeOf(emit_data
->args
[0]), type
, sizeof(type
));
4791 sprintf(intr_name
, "%s%s%s%s.%s",
4792 name
, is_shadow
? ".c" : "", infix
,
4793 has_offset
? ".o" : "", type
);
4795 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
4796 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
4797 emit_data
->args
, emit_data
->arg_count
,
4798 LLVMReadNoneAttribute
);
4801 static void si_llvm_emit_txqs(
4802 const struct lp_build_tgsi_action
*action
,
4803 struct lp_build_tgsi_context
*bld_base
,
4804 struct lp_build_emit_data
*emit_data
)
4806 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4807 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4808 LLVMBuilderRef builder
= gallivm
->builder
;
4809 LLVMValueRef res
, samples
;
4810 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
4812 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4815 /* Read the samples from the descriptor directly. */
4816 res
= LLVMBuildBitCast(builder
, res_ptr
, ctx
->v8i32
, "");
4817 samples
= LLVMBuildExtractElement(
4819 lp_build_const_int32(gallivm
, 3), "");
4820 samples
= LLVMBuildLShr(builder
, samples
,
4821 lp_build_const_int32(gallivm
, 16), "");
4822 samples
= LLVMBuildAnd(builder
, samples
,
4823 lp_build_const_int32(gallivm
, 0xf), "");
4824 samples
= LLVMBuildShl(builder
, lp_build_const_int32(gallivm
, 1),
4827 emit_data
->output
[emit_data
->chan
] = samples
;
4831 * SI implements derivatives using the local data store (LDS)
4832 * All writes to the LDS happen in all executing threads at
4833 * the same time. TID is the Thread ID for the current
4834 * thread and is a value between 0 and 63, representing
4835 * the thread's position in the wavefront.
4837 * For the pixel shader threads are grouped into quads of four pixels.
4838 * The TIDs of the pixels of a quad are:
4846 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4847 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4848 * the current pixel's column, and masking with 0xfffffffe yields the TID
4849 * of the left pixel of the current pixel's row.
4851 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4852 * adding 2 yields the TID of the pixel below the top pixel.
4854 /* masks for thread ID. */
4855 #define TID_MASK_TOP_LEFT 0xfffffffc
4856 #define TID_MASK_TOP 0xfffffffd
4857 #define TID_MASK_LEFT 0xfffffffe
4859 static void si_llvm_emit_ddxy(
4860 const struct lp_build_tgsi_action
*action
,
4861 struct lp_build_tgsi_context
*bld_base
,
4862 struct lp_build_emit_data
*emit_data
)
4864 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4865 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4866 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4867 unsigned opcode
= inst
->Instruction
.Opcode
;
4868 LLVMValueRef indices
[2];
4869 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
4870 LLVMValueRef tl
, trbl
, result
[4];
4871 LLVMValueRef tl_tid
, trbl_tid
;
4872 unsigned swizzle
[4];
4877 indices
[0] = bld_base
->uint_bld
.zero
;
4878 indices
[1] = get_thread_id(ctx
);
4879 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4882 if (opcode
== TGSI_OPCODE_DDX_FINE
)
4883 mask
= TID_MASK_LEFT
;
4884 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
4885 mask
= TID_MASK_TOP
;
4887 mask
= TID_MASK_TOP_LEFT
;
4889 tl_tid
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4890 lp_build_const_int32(gallivm
, mask
), "");
4891 indices
[1] = tl_tid
;
4892 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4895 /* for DDX we want to next X pixel, DDY next Y pixel. */
4896 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
4897 trbl_tid
= LLVMBuildAdd(gallivm
->builder
, indices
[1],
4898 lp_build_const_int32(gallivm
, idx
), "");
4899 indices
[1] = trbl_tid
;
4900 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4903 for (c
= 0; c
< 4; ++c
) {
4906 LLVMValueRef args
[2];
4908 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
4909 for (i
= 0; i
< c
; ++i
) {
4910 if (swizzle
[i
] == swizzle
[c
]) {
4911 result
[c
] = result
[i
];
4918 val
= LLVMBuildBitCast(gallivm
->builder
,
4919 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
4922 if ((HAVE_LLVM
>= 0x0309) && ctx
->screen
->b
.family
>= CHIP_TONGA
) {
4924 args
[0] = LLVMBuildMul(gallivm
->builder
, tl_tid
,
4925 lp_build_const_int32(gallivm
, 4), "");
4927 tl
= lp_build_intrinsic(gallivm
->builder
,
4928 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4929 args
, 2, LLVMReadNoneAttribute
);
4931 args
[0] = LLVMBuildMul(gallivm
->builder
, trbl_tid
,
4932 lp_build_const_int32(gallivm
, 4), "");
4933 trbl
= lp_build_intrinsic(gallivm
->builder
,
4934 "llvm.amdgcn.ds.bpermute", ctx
->i32
,
4935 args
, 2, LLVMReadNoneAttribute
);
4937 LLVMBuildStore(gallivm
->builder
, val
, store_ptr
);
4938 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
4939 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
4941 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
4942 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, ctx
->f32
, "");
4943 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
4946 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
4950 * this takes an I,J coordinate pair,
4951 * and works out the X and Y derivatives.
4952 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4954 static LLVMValueRef
si_llvm_emit_ddxy_interp(
4955 struct lp_build_tgsi_context
*bld_base
,
4956 LLVMValueRef interp_ij
)
4958 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4959 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
4960 LLVMValueRef indices
[2];
4961 LLVMValueRef store_ptr
, load_ptr_x
, load_ptr_y
, load_ptr_ddx
, load_ptr_ddy
, temp
, temp2
;
4962 LLVMValueRef tl
, tr
, bl
, result
[4];
4965 indices
[0] = bld_base
->uint_bld
.zero
;
4966 indices
[1] = get_thread_id(ctx
);
4967 store_ptr
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4970 temp
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4971 lp_build_const_int32(gallivm
, TID_MASK_LEFT
), "");
4973 temp2
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
4974 lp_build_const_int32(gallivm
, TID_MASK_TOP
), "");
4977 load_ptr_x
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4981 load_ptr_y
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4984 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp
,
4985 lp_build_const_int32(gallivm
, 1), "");
4986 load_ptr_ddx
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4989 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp2
,
4990 lp_build_const_int32(gallivm
, 2), "");
4991 load_ptr_ddy
= LLVMBuildGEP(gallivm
->builder
, ctx
->lds
,
4994 for (c
= 0; c
< 2; ++c
) {
4995 LLVMValueRef store_val
;
4996 LLVMValueRef c_ll
= lp_build_const_int32(gallivm
, c
);
4998 store_val
= LLVMBuildExtractElement(gallivm
->builder
,
4999 interp_ij
, c_ll
, "");
5000 LLVMBuildStore(gallivm
->builder
,
5004 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_x
, "");
5005 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
5007 tr
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddx
, "");
5008 tr
= LLVMBuildBitCast(gallivm
->builder
, tr
, ctx
->f32
, "");
5010 result
[c
] = LLVMBuildFSub(gallivm
->builder
, tr
, tl
, "");
5012 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_y
, "");
5013 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, ctx
->f32
, "");
5015 bl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddy
, "");
5016 bl
= LLVMBuildBitCast(gallivm
->builder
, bl
, ctx
->f32
, "");
5018 result
[c
+ 2] = LLVMBuildFSub(gallivm
->builder
, bl
, tl
, "");
5021 return lp_build_gather_values(gallivm
, result
, 4);
5024 static void interp_fetch_args(
5025 struct lp_build_tgsi_context
*bld_base
,
5026 struct lp_build_emit_data
*emit_data
)
5028 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5029 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5030 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5032 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
5033 /* offset is in second src, first two channels */
5034 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
5037 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
5040 emit_data
->arg_count
= 2;
5041 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5042 LLVMValueRef sample_position
;
5043 LLVMValueRef sample_id
;
5044 LLVMValueRef halfval
= lp_build_const_float(gallivm
, 0.5f
);
5046 /* fetch sample ID, then fetch its sample position,
5047 * and place into first two channels.
5049 sample_id
= lp_build_emit_fetch(bld_base
,
5050 emit_data
->inst
, 1, TGSI_CHAN_X
);
5051 sample_id
= LLVMBuildBitCast(gallivm
->builder
, sample_id
,
5053 sample_position
= load_sample_position(&ctx
->radeon_bld
, sample_id
);
5055 emit_data
->args
[0] = LLVMBuildExtractElement(gallivm
->builder
,
5057 lp_build_const_int32(gallivm
, 0), "");
5059 emit_data
->args
[0] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[0], halfval
, "");
5060 emit_data
->args
[1] = LLVMBuildExtractElement(gallivm
->builder
,
5062 lp_build_const_int32(gallivm
, 1), "");
5063 emit_data
->args
[1] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[1], halfval
, "");
5064 emit_data
->arg_count
= 2;
5068 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
5069 struct lp_build_tgsi_context
*bld_base
,
5070 struct lp_build_emit_data
*emit_data
)
5072 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5073 struct si_shader
*shader
= ctx
->shader
;
5074 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5075 LLVMValueRef interp_param
;
5076 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
5077 const char *intr_name
;
5078 int input_index
= inst
->Src
[0].Register
.Index
;
5081 LLVMValueRef attr_number
;
5082 LLVMValueRef params
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_PRIM_MASK
);
5083 int interp_param_idx
;
5084 unsigned interp
= shader
->selector
->info
.input_interpolate
[input_index
];
5087 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
5089 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5090 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
5091 location
= TGSI_INTERPOLATE_LOC_CENTER
;
5093 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
5095 interp_param_idx
= lookup_interp_param_index(interp
, location
);
5096 if (interp_param_idx
== -1)
5098 else if (interp_param_idx
)
5099 interp_param
= get_interp_param(ctx
, interp_param_idx
);
5101 interp_param
= NULL
;
5103 attr_number
= lp_build_const_int32(gallivm
, input_index
);
5105 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
5106 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
5107 LLVMValueRef ij_out
[2];
5108 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
5111 * take the I then J parameters, and the DDX/Y for it, and
5112 * calculate the IJ inputs for the interpolator.
5113 * temp1 = ddx * offset/sample.x + I;
5114 * interp_param.I = ddy * offset/sample.y + temp1;
5115 * temp1 = ddx * offset/sample.x + J;
5116 * interp_param.J = ddy * offset/sample.y + temp1;
5118 for (i
= 0; i
< 2; i
++) {
5119 LLVMValueRef ix_ll
= lp_build_const_int32(gallivm
, i
);
5120 LLVMValueRef iy_ll
= lp_build_const_int32(gallivm
, i
+ 2);
5121 LLVMValueRef ddx_el
= LLVMBuildExtractElement(gallivm
->builder
,
5122 ddxy_out
, ix_ll
, "");
5123 LLVMValueRef ddy_el
= LLVMBuildExtractElement(gallivm
->builder
,
5124 ddxy_out
, iy_ll
, "");
5125 LLVMValueRef interp_el
= LLVMBuildExtractElement(gallivm
->builder
,
5126 interp_param
, ix_ll
, "");
5127 LLVMValueRef temp1
, temp2
;
5129 interp_el
= LLVMBuildBitCast(gallivm
->builder
, interp_el
,
5132 temp1
= LLVMBuildFMul(gallivm
->builder
, ddx_el
, emit_data
->args
[0], "");
5134 temp1
= LLVMBuildFAdd(gallivm
->builder
, temp1
, interp_el
, "");
5136 temp2
= LLVMBuildFMul(gallivm
->builder
, ddy_el
, emit_data
->args
[1], "");
5138 temp2
= LLVMBuildFAdd(gallivm
->builder
, temp2
, temp1
, "");
5140 ij_out
[i
] = LLVMBuildBitCast(gallivm
->builder
,
5141 temp2
, ctx
->i32
, "");
5143 interp_param
= lp_build_gather_values(bld_base
->base
.gallivm
, ij_out
, 2);
5146 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5147 for (chan
= 0; chan
< 2; chan
++) {
5148 LLVMValueRef args
[4];
5149 LLVMValueRef llvm_chan
;
5152 schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
5153 llvm_chan
= lp_build_const_int32(gallivm
, schan
);
5155 args
[0] = llvm_chan
;
5156 args
[1] = attr_number
;
5158 args
[3] = interp_param
;
5160 emit_data
->output
[chan
] =
5161 lp_build_intrinsic(gallivm
->builder
, intr_name
,
5162 ctx
->f32
, args
, args
[3] ? 4 : 3,
5163 LLVMReadNoneAttribute
);
5167 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
5168 struct lp_build_emit_data
*emit_data
)
5170 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
5171 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
5174 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
5176 stream
= LLVMConstIntGetZExtValue(imms
[src0
.Index
][src0
.SwizzleX
]) & 0x3;
5180 /* Emit one vertex from the geometry shader */
5181 static void si_llvm_emit_vertex(
5182 const struct lp_build_tgsi_action
*action
,
5183 struct lp_build_tgsi_context
*bld_base
,
5184 struct lp_build_emit_data
*emit_data
)
5186 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5187 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5188 struct si_shader
*shader
= ctx
->shader
;
5189 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
5190 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5191 LLVMValueRef soffset
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5192 SI_PARAM_GS2VS_OFFSET
);
5193 LLVMValueRef gs_next_vertex
;
5194 LLVMValueRef can_emit
, kill
;
5195 LLVMValueRef args
[2];
5200 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5202 /* Write vertex attribute values to GSVS ring */
5203 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
,
5204 ctx
->gs_next_vertex
[stream
],
5207 /* If this thread has already emitted the declared maximum number of
5208 * vertices, kill it: excessive vertex emissions are not supposed to
5209 * have any effect, and GS threads have no externally observable
5210 * effects other than emitting vertices.
5212 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
5213 lp_build_const_int32(gallivm
,
5214 shader
->selector
->gs_max_out_vertices
), "");
5215 kill
= lp_build_select(&bld_base
->base
, can_emit
,
5216 lp_build_const_float(gallivm
, 1.0f
),
5217 lp_build_const_float(gallivm
, -1.0f
));
5219 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
5220 ctx
->voidt
, &kill
, 1, 0);
5222 for (i
= 0; i
< info
->num_outputs
; i
++) {
5223 LLVMValueRef
*out_ptr
=
5224 ctx
->radeon_bld
.soa
.outputs
[i
];
5226 for (chan
= 0; chan
< 4; chan
++) {
5227 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
5228 LLVMValueRef voffset
=
5229 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
5230 shader
->selector
->gs_max_out_vertices
);
5232 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
5233 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
5235 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, ctx
->i32
, "");
5237 build_tbuffer_store(ctx
,
5238 ctx
->gsvs_ring
[stream
],
5240 voffset
, soffset
, 0,
5241 V_008F0C_BUF_DATA_FORMAT_32
,
5242 V_008F0C_BUF_NUM_FORMAT_UINT
,
5246 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
5247 lp_build_const_int32(gallivm
, 1));
5249 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
5251 /* Signal vertex emission */
5252 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
| (stream
<< 8));
5253 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5254 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5255 ctx
->voidt
, args
, 2, 0);
5258 /* Cut one primitive from the geometry shader */
5259 static void si_llvm_emit_primitive(
5260 const struct lp_build_tgsi_action
*action
,
5261 struct lp_build_tgsi_context
*bld_base
,
5262 struct lp_build_emit_data
*emit_data
)
5264 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5265 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5266 LLVMValueRef args
[2];
5269 /* Signal primitive cut */
5270 stream
= si_llvm_get_stream(bld_base
, emit_data
);
5271 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
| (stream
<< 8));
5272 args
[1] = LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
5273 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
5274 ctx
->voidt
, args
, 2, 0);
5277 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
5278 struct lp_build_tgsi_context
*bld_base
,
5279 struct lp_build_emit_data
*emit_data
)
5281 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
5282 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5284 /* The real barrier instruction isn’t needed, because an entire patch
5285 * always fits into a single wave.
5287 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
5288 emit_optimization_barrier(ctx
);
5292 lp_build_intrinsic(gallivm
->builder
,
5293 HAVE_LLVM
>= 0x0309 ? "llvm.amdgcn.s.barrier"
5294 : "llvm.AMDGPU.barrier.local",
5295 ctx
->voidt
, NULL
, 0, 0);
5298 static const struct lp_build_tgsi_action tex_action
= {
5299 .fetch_args
= tex_fetch_args
,
5300 .emit
= build_tex_intrinsic
,
5303 static const struct lp_build_tgsi_action interp_action
= {
5304 .fetch_args
= interp_fetch_args
,
5305 .emit
= build_interp_intrinsic
,
5308 static void si_create_function(struct si_shader_context
*ctx
,
5309 LLVMTypeRef
*returns
, unsigned num_returns
,
5310 LLVMTypeRef
*params
, unsigned num_params
,
5315 radeon_llvm_create_func(&ctx
->radeon_bld
, returns
, num_returns
,
5316 params
, num_params
);
5317 radeon_llvm_shader_type(ctx
->radeon_bld
.main_fn
, ctx
->type
);
5318 ctx
->return_value
= LLVMGetUndef(ctx
->radeon_bld
.return_type
);
5320 for (i
= 0; i
<= last_sgpr
; ++i
) {
5321 LLVMValueRef P
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, i
);
5323 /* The combination of:
5327 * allows the optimization passes to move loads and reduces
5328 * SGPR spilling significantly.
5330 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
5331 LLVMAddAttribute(P
, LLVMByValAttribute
);
5332 lp_add_attr_dereferenceable(P
, UINT64_MAX
);
5334 LLVMAddAttribute(P
, LLVMInRegAttribute
);
5337 if (ctx
->screen
->b
.debug_flags
& DBG_UNSAFE_MATH
) {
5338 /* These were copied from some LLVM test. */
5339 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5340 "less-precise-fpmad",
5342 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5345 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5348 LLVMAddTargetDependentFunctionAttr(ctx
->radeon_bld
.main_fn
,
5354 static void create_meta_data(struct si_shader_context
*ctx
)
5356 struct gallivm_state
*gallivm
= ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5358 ctx
->invariant_load_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5359 "invariant.load", 14);
5360 ctx
->range_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5362 ctx
->uniform_md_kind
= LLVMGetMDKindIDInContext(gallivm
->context
,
5363 "amdgpu.uniform", 14);
5365 ctx
->empty_md
= LLVMMDNodeInContext(gallivm
->context
, NULL
, 0);
5368 static void declare_streamout_params(struct si_shader_context
*ctx
,
5369 struct pipe_stream_output_info
*so
,
5370 LLVMTypeRef
*params
, LLVMTypeRef i32
,
5371 unsigned *num_params
)
5375 /* Streamout SGPRs. */
5376 if (so
->num_outputs
) {
5377 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
5378 params
[ctx
->param_streamout_config
= (*num_params
)++] = i32
;
5380 ctx
->param_streamout_config
= ctx
->param_tess_offchip
;
5382 params
[ctx
->param_streamout_write_index
= (*num_params
)++] = i32
;
5384 /* A streamout buffer offset is loaded if the stride is non-zero. */
5385 for (i
= 0; i
< 4; i
++) {
5389 params
[ctx
->param_streamout_offset
[i
] = (*num_params
)++] = i32
;
5393 static unsigned llvm_get_type_size(LLVMTypeRef type
)
5395 LLVMTypeKind kind
= LLVMGetTypeKind(type
);
5398 case LLVMIntegerTypeKind
:
5399 return LLVMGetIntTypeWidth(type
) / 8;
5400 case LLVMFloatTypeKind
:
5402 case LLVMPointerTypeKind
:
5404 case LLVMVectorTypeKind
:
5405 return LLVMGetVectorSize(type
) *
5406 llvm_get_type_size(LLVMGetElementType(type
));
5413 static void declare_tess_lds(struct si_shader_context
*ctx
)
5415 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5416 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5417 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
5419 unsigned lds_size
= ctx
->screen
->b
.chip_class
>= CIK
? 65536 : 32768;
5420 ctx
->lds
= LLVMBuildIntToPtr(gallivm
->builder
, uint
->zero
,
5421 LLVMPointerType(LLVMArrayType(ctx
->i32
, lds_size
/ 4), LOCAL_ADDR_SPACE
),
5425 static void create_function(struct si_shader_context
*ctx
)
5427 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5428 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5429 struct si_shader
*shader
= ctx
->shader
;
5430 LLVMTypeRef params
[SI_NUM_PARAMS
+ SI_NUM_VERTEX_BUFFERS
], v3i32
;
5431 LLVMTypeRef returns
[16+32*4];
5432 unsigned i
, last_sgpr
, num_params
, num_return_sgprs
;
5433 unsigned num_returns
= 0;
5435 v3i32
= LLVMVectorType(ctx
->i32
, 3);
5437 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_RW_BUFFERS
);
5438 params
[SI_PARAM_CONST_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_CONST_BUFFERS
);
5439 params
[SI_PARAM_SAMPLERS
] = const_array(ctx
->v8i32
, SI_NUM_SAMPLERS
);
5440 params
[SI_PARAM_IMAGES
] = const_array(ctx
->v8i32
, SI_NUM_IMAGES
);
5441 params
[SI_PARAM_SHADER_BUFFERS
] = const_array(ctx
->v4i32
, SI_NUM_SHADER_BUFFERS
);
5443 switch (ctx
->type
) {
5444 case PIPE_SHADER_VERTEX
:
5445 params
[SI_PARAM_VERTEX_BUFFERS
] = const_array(ctx
->v16i8
, SI_NUM_VERTEX_BUFFERS
);
5446 params
[SI_PARAM_BASE_VERTEX
] = ctx
->i32
;
5447 params
[SI_PARAM_START_INSTANCE
] = ctx
->i32
;
5448 params
[SI_PARAM_DRAWID
] = ctx
->i32
;
5449 num_params
= SI_PARAM_DRAWID
+1;
5451 if (shader
->key
.vs
.as_es
) {
5452 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5453 } else if (shader
->key
.vs
.as_ls
) {
5454 params
[SI_PARAM_LS_OUT_LAYOUT
] = ctx
->i32
;
5455 num_params
= SI_PARAM_LS_OUT_LAYOUT
+1;
5457 if (ctx
->is_gs_copy_shader
) {
5458 num_params
= SI_PARAM_RW_BUFFERS
+1;
5460 params
[SI_PARAM_VS_STATE_BITS
] = ctx
->i32
;
5461 num_params
= SI_PARAM_VS_STATE_BITS
+1;
5464 /* The locations of the other parameters are assigned dynamically. */
5465 declare_streamout_params(ctx
, &shader
->selector
->so
,
5466 params
, ctx
->i32
, &num_params
);
5469 last_sgpr
= num_params
-1;
5472 params
[ctx
->param_vertex_id
= num_params
++] = ctx
->i32
;
5473 params
[ctx
->param_rel_auto_id
= num_params
++] = ctx
->i32
;
5474 params
[ctx
->param_vs_prim_id
= num_params
++] = ctx
->i32
;
5475 params
[ctx
->param_instance_id
= num_params
++] = ctx
->i32
;
5477 if (!ctx
->is_monolithic
&&
5478 !ctx
->is_gs_copy_shader
) {
5479 /* Vertex load indices. */
5480 ctx
->param_vertex_index0
= num_params
;
5482 for (i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
5483 params
[num_params
++] = ctx
->i32
;
5485 /* PrimitiveID output. */
5486 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
)
5487 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5488 returns
[num_returns
++] = ctx
->f32
;
5492 case PIPE_SHADER_TESS_CTRL
:
5493 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5494 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
->i32
;
5495 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
->i32
;
5496 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
->i32
;
5497 params
[ctx
->param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
->i32
;
5498 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
->i32
;
5499 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
5502 params
[SI_PARAM_PATCH_ID
] = ctx
->i32
;
5503 params
[SI_PARAM_REL_IDS
] = ctx
->i32
;
5504 num_params
= SI_PARAM_REL_IDS
+1;
5506 if (!ctx
->is_monolithic
) {
5507 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5508 * placed after the user SGPRs.
5510 for (i
= 0; i
< SI_TCS_NUM_USER_SGPR
+ 2; i
++)
5511 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
5513 for (i
= 0; i
< 3; i
++)
5514 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
5518 case PIPE_SHADER_TESS_EVAL
:
5519 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
->i32
;
5520 num_params
= SI_PARAM_TCS_OFFCHIP_LAYOUT
+1;
5522 if (shader
->key
.tes
.as_es
) {
5523 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5524 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5525 params
[ctx
->param_es2gs_offset
= num_params
++] = ctx
->i32
;
5527 params
[ctx
->param_tess_offchip
= num_params
++] = ctx
->i32
;
5528 declare_streamout_params(ctx
, &shader
->selector
->so
,
5529 params
, ctx
->i32
, &num_params
);
5530 params
[ctx
->param_oc_lds
= num_params
++] = ctx
->i32
;
5532 last_sgpr
= num_params
- 1;
5535 params
[ctx
->param_tes_u
= num_params
++] = ctx
->f32
;
5536 params
[ctx
->param_tes_v
= num_params
++] = ctx
->f32
;
5537 params
[ctx
->param_tes_rel_patch_id
= num_params
++] = ctx
->i32
;
5538 params
[ctx
->param_tes_patch_id
= num_params
++] = ctx
->i32
;
5540 /* PrimitiveID output. */
5541 if (!ctx
->is_monolithic
&& !shader
->key
.tes
.as_es
)
5542 for (i
= 0; i
<= VS_EPILOG_PRIMID_LOC
; i
++)
5543 returns
[num_returns
++] = ctx
->f32
;
5546 case PIPE_SHADER_GEOMETRY
:
5547 params
[SI_PARAM_GS2VS_OFFSET
] = ctx
->i32
;
5548 params
[SI_PARAM_GS_WAVE_ID
] = ctx
->i32
;
5549 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
5552 params
[SI_PARAM_VTX0_OFFSET
] = ctx
->i32
;
5553 params
[SI_PARAM_VTX1_OFFSET
] = ctx
->i32
;
5554 params
[SI_PARAM_PRIMITIVE_ID
] = ctx
->i32
;
5555 params
[SI_PARAM_VTX2_OFFSET
] = ctx
->i32
;
5556 params
[SI_PARAM_VTX3_OFFSET
] = ctx
->i32
;
5557 params
[SI_PARAM_VTX4_OFFSET
] = ctx
->i32
;
5558 params
[SI_PARAM_VTX5_OFFSET
] = ctx
->i32
;
5559 params
[SI_PARAM_GS_INSTANCE_ID
] = ctx
->i32
;
5560 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
5563 case PIPE_SHADER_FRAGMENT
:
5564 params
[SI_PARAM_ALPHA_REF
] = ctx
->f32
;
5565 params
[SI_PARAM_PRIM_MASK
] = ctx
->i32
;
5566 last_sgpr
= SI_PARAM_PRIM_MASK
;
5567 params
[SI_PARAM_PERSP_SAMPLE
] = ctx
->v2i32
;
5568 params
[SI_PARAM_PERSP_CENTER
] = ctx
->v2i32
;
5569 params
[SI_PARAM_PERSP_CENTROID
] = ctx
->v2i32
;
5570 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
5571 params
[SI_PARAM_LINEAR_SAMPLE
] = ctx
->v2i32
;
5572 params
[SI_PARAM_LINEAR_CENTER
] = ctx
->v2i32
;
5573 params
[SI_PARAM_LINEAR_CENTROID
] = ctx
->v2i32
;
5574 params
[SI_PARAM_LINE_STIPPLE_TEX
] = ctx
->f32
;
5575 params
[SI_PARAM_POS_X_FLOAT
] = ctx
->f32
;
5576 params
[SI_PARAM_POS_Y_FLOAT
] = ctx
->f32
;
5577 params
[SI_PARAM_POS_Z_FLOAT
] = ctx
->f32
;
5578 params
[SI_PARAM_POS_W_FLOAT
] = ctx
->f32
;
5579 params
[SI_PARAM_FRONT_FACE
] = ctx
->i32
;
5580 params
[SI_PARAM_ANCILLARY
] = ctx
->i32
;
5581 params
[SI_PARAM_SAMPLE_COVERAGE
] = ctx
->f32
;
5582 params
[SI_PARAM_POS_FIXED_PT
] = ctx
->i32
;
5583 num_params
= SI_PARAM_POS_FIXED_PT
+1;
5585 if (!ctx
->is_monolithic
) {
5586 /* Color inputs from the prolog. */
5587 if (shader
->selector
->info
.colors_read
) {
5588 unsigned num_color_elements
=
5589 util_bitcount(shader
->selector
->info
.colors_read
);
5591 assert(num_params
+ num_color_elements
<= ARRAY_SIZE(params
));
5592 for (i
= 0; i
< num_color_elements
; i
++)
5593 params
[num_params
++] = ctx
->f32
;
5596 /* Outputs for the epilog. */
5597 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
5600 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
5601 shader
->selector
->info
.writes_z
+
5602 shader
->selector
->info
.writes_stencil
+
5603 shader
->selector
->info
.writes_samplemask
+
5604 1 /* SampleMaskIn */;
5606 num_returns
= MAX2(num_returns
,
5608 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
5610 for (i
= 0; i
< num_return_sgprs
; i
++)
5611 returns
[i
] = ctx
->i32
;
5612 for (; i
< num_returns
; i
++)
5613 returns
[i
] = ctx
->f32
;
5617 case PIPE_SHADER_COMPUTE
:
5618 params
[SI_PARAM_GRID_SIZE
] = v3i32
;
5619 params
[SI_PARAM_BLOCK_ID
] = v3i32
;
5620 last_sgpr
= SI_PARAM_BLOCK_ID
;
5622 params
[SI_PARAM_THREAD_ID
] = v3i32
;
5623 num_params
= SI_PARAM_THREAD_ID
+ 1;
5626 assert(0 && "unimplemented shader");
5630 assert(num_params
<= ARRAY_SIZE(params
));
5632 si_create_function(ctx
, returns
, num_returns
, params
,
5633 num_params
, last_sgpr
);
5635 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5636 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&&
5637 !ctx
->is_monolithic
) {
5638 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5639 "InitialPSInputAddr",
5640 S_0286D0_PERSP_SAMPLE_ENA(1) |
5641 S_0286D0_PERSP_CENTER_ENA(1) |
5642 S_0286D0_PERSP_CENTROID_ENA(1) |
5643 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5644 S_0286D0_LINEAR_CENTER_ENA(1) |
5645 S_0286D0_LINEAR_CENTROID_ENA(1) |
5646 S_0286D0_FRONT_FACE_ENA(1) |
5647 S_0286D0_POS_FIXED_PT_ENA(1));
5648 } else if (ctx
->type
== PIPE_SHADER_COMPUTE
) {
5649 const unsigned *properties
= shader
->selector
->info
.properties
;
5650 unsigned max_work_group_size
=
5651 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
5652 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
5653 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
5655 assert(max_work_group_size
);
5657 radeon_llvm_add_attribute(ctx
->radeon_bld
.main_fn
,
5658 "amdgpu-max-work-group-size",
5659 max_work_group_size
);
5662 shader
->info
.num_input_sgprs
= 0;
5663 shader
->info
.num_input_vgprs
= 0;
5665 for (i
= 0; i
<= last_sgpr
; ++i
)
5666 shader
->info
.num_input_sgprs
+= llvm_get_type_size(params
[i
]) / 4;
5668 /* Unused fragment shader inputs are eliminated by the compiler,
5669 * so we don't know yet how many there will be.
5671 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
5672 for (; i
< num_params
; ++i
)
5673 shader
->info
.num_input_vgprs
+= llvm_get_type_size(params
[i
]) / 4;
5675 if (bld_base
->info
&&
5676 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
5677 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0 ||
5678 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX_FINE
] > 0 ||
5679 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY_FINE
] > 0 ||
5680 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_OFFSET
] > 0 ||
5681 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
] > 0))
5683 LLVMAddGlobalInAddressSpace(gallivm
->module
,
5684 LLVMArrayType(ctx
->i32
, 64),
5688 if ((ctx
->type
== PIPE_SHADER_VERTEX
&& shader
->key
.vs
.as_ls
) ||
5689 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5690 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
5691 declare_tess_lds(ctx
);
5694 static void preload_constants(struct si_shader_context
*ctx
)
5696 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5697 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5698 const struct tgsi_shader_info
*info
= bld_base
->info
;
5700 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
5702 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
5703 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
5708 /* Allocate space for the constant values */
5709 ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
5711 /* Load the resource descriptor */
5712 ctx
->const_buffers
[buf
] =
5713 build_indexed_load_const(ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5715 /* Load the constants, we rely on the code sinking to do the rest */
5716 for (i
= 0; i
< num_const
* 4; ++i
) {
5717 ctx
->constants
[buf
][i
] =
5718 buffer_load_const(ctx
,
5719 ctx
->const_buffers
[buf
],
5720 lp_build_const_int32(gallivm
, i
* 4));
5725 static void preload_shader_buffers(struct si_shader_context
*ctx
)
5727 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
5728 LLVMValueRef ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_SHADER_BUFFERS
);
5731 maxbuf
= MIN2(ctx
->shader
->selector
->info
.file_max
[TGSI_FILE_BUFFER
],
5732 SI_NUM_SHADER_BUFFERS
- 1);
5733 for (buf
= 0; buf
<= maxbuf
; ++buf
) {
5734 ctx
->shader_buffers
[buf
] =
5735 build_indexed_load_const(
5736 ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
5740 static void preload_samplers(struct si_shader_context
*ctx
)
5742 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5743 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5744 const struct tgsi_shader_info
*info
= bld_base
->info
;
5745 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
5746 LLVMValueRef offset
;
5748 if (num_samplers
== 0)
5751 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5752 for (i
= 0; i
< num_samplers
; ++i
) {
5754 offset
= lp_build_const_int32(gallivm
, i
);
5755 ctx
->sampler_views
[i
] =
5756 get_sampler_desc(ctx
, offset
, DESC_IMAGE
);
5758 /* FMASK resource */
5759 if (info
->is_msaa_sampler
[i
])
5761 get_sampler_desc(ctx
, offset
, DESC_FMASK
);
5763 ctx
->sampler_states
[i
] =
5764 get_sampler_desc(ctx
, offset
, DESC_SAMPLER
);
5765 ctx
->sampler_states
[i
] =
5766 sici_fix_sampler_aniso(ctx
, ctx
->sampler_views
[i
],
5767 ctx
->sampler_states
[i
]);
5772 static void preload_images(struct si_shader_context
*ctx
)
5774 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5775 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
5776 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5777 unsigned num_images
= bld_base
->info
->file_max
[TGSI_FILE_IMAGE
] + 1;
5778 LLVMValueRef res_ptr
;
5781 if (num_images
== 0)
5784 res_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
, SI_PARAM_IMAGES
);
5786 for (i
= 0; i
< num_images
; ++i
) {
5787 /* Rely on LLVM to shrink the load for buffer resources. */
5789 build_indexed_load_const(ctx
, res_ptr
,
5790 lp_build_const_int32(gallivm
, i
));
5792 if (info
->images_writemask
& (1 << i
) &&
5793 !(info
->images_buffers
& (1 << i
)))
5794 rsrc
= force_dcc_off(ctx
, rsrc
);
5796 ctx
->images
[i
] = rsrc
;
5800 static void preload_streamout_buffers(struct si_shader_context
*ctx
)
5802 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
5803 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5806 /* Streamout can only be used if the shader is compiled as VS. */
5807 if (!ctx
->shader
->selector
->so
.num_outputs
||
5808 (ctx
->type
== PIPE_SHADER_VERTEX
&&
5809 (ctx
->shader
->key
.vs
.as_es
||
5810 ctx
->shader
->key
.vs
.as_ls
)) ||
5811 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5812 ctx
->shader
->key
.tes
.as_es
))
5815 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5816 SI_PARAM_RW_BUFFERS
);
5818 /* Load the resources, we rely on the code sinking to do the rest */
5819 for (i
= 0; i
< 4; ++i
) {
5820 if (ctx
->shader
->selector
->so
.stride
[i
]) {
5821 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
5822 SI_VS_STREAMOUT_BUF0
+ i
);
5824 ctx
->so_buffers
[i
] = build_indexed_load_const(ctx
, buf_ptr
, offset
);
5830 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5833 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5835 struct gallivm_state
*gallivm
=
5836 ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
5838 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->radeon_bld
.main_fn
,
5839 SI_PARAM_RW_BUFFERS
);
5841 if ((ctx
->type
== PIPE_SHADER_VERTEX
&&
5842 ctx
->shader
->key
.vs
.as_es
) ||
5843 (ctx
->type
== PIPE_SHADER_TESS_EVAL
&&
5844 ctx
->shader
->key
.tes
.as_es
) ||
5845 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5847 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5849 LLVMValueRef offset
= lp_build_const_int32(gallivm
, ring
);
5852 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5855 if (ctx
->is_gs_copy_shader
) {
5856 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_VS_RING_GSVS
);
5859 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5861 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5863 for (i
= 0; i
< 4; i
++) {
5864 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_GS_RING_GSVS0
+ i
);
5867 build_indexed_load_const(ctx
, buf_ptr
, offset
);
5872 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5873 LLVMValueRef param_rw_buffers
,
5874 unsigned param_pos_fixed_pt
)
5876 struct lp_build_tgsi_context
*bld_base
=
5877 &ctx
->radeon_bld
.soa
.bld_base
;
5878 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
5879 LLVMBuilderRef builder
= gallivm
->builder
;
5880 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5882 /* Use the fixed-point gl_FragCoord input.
5883 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5884 * per coordinate to get the repeating effect.
5886 address
[0] = unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5887 address
[1] = unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5889 /* Load the buffer descriptor. */
5890 slot
= lp_build_const_int32(gallivm
, SI_PS_CONST_POLY_STIPPLE
);
5891 desc
= build_indexed_load_const(ctx
, param_rw_buffers
, slot
);
5893 /* The stipple pattern is 32x32, each row has 32 bits. */
5894 offset
= LLVMBuildMul(builder
, address
[1],
5895 LLVMConstInt(ctx
->i32
, 4, 0), "");
5896 row
= buffer_load_const(ctx
, desc
, offset
);
5897 row
= LLVMBuildBitCast(builder
, row
, ctx
->i32
, "");
5898 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5899 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5901 /* The intrinsic kills the thread if arg < 0. */
5902 bit
= LLVMBuildSelect(builder
, bit
, LLVMConstReal(ctx
->f32
, 0),
5903 LLVMConstReal(ctx
->f32
, -1), "");
5904 lp_build_intrinsic(builder
, "llvm.AMDGPU.kill", ctx
->voidt
, &bit
, 1, 0);
5907 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
5908 struct si_shader_config
*conf
,
5909 unsigned symbol_offset
)
5912 const unsigned char *config
=
5913 radeon_shader_binary_config_start(binary
, symbol_offset
);
5914 bool really_needs_scratch
= false;
5916 /* LLVM adds SGPR spills to the scratch size.
5917 * Find out if we really need the scratch buffer.
5919 for (i
= 0; i
< binary
->reloc_count
; i
++) {
5920 const struct radeon_shader_reloc
*reloc
= &binary
->relocs
[i
];
5922 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
5923 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5924 really_needs_scratch
= true;
5929 /* XXX: We may be able to emit some of these values directly rather than
5930 * extracting fields to be emitted later.
5933 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
5934 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
5935 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
5937 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
5938 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
5939 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
5940 case R_00B848_COMPUTE_PGM_RSRC1
:
5941 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
5942 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
5943 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
5944 conf
->rsrc1
= value
;
5946 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
5947 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
5949 case R_00B84C_COMPUTE_PGM_RSRC2
:
5950 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
5951 conf
->rsrc2
= value
;
5953 case R_0286CC_SPI_PS_INPUT_ENA
:
5954 conf
->spi_ps_input_ena
= value
;
5956 case R_0286D0_SPI_PS_INPUT_ADDR
:
5957 conf
->spi_ps_input_addr
= value
;
5959 case R_0286E8_SPI_TMPRING_SIZE
:
5960 case R_00B860_COMPUTE_TMPRING_SIZE
:
5961 /* WAVESIZE is in units of 256 dwords. */
5962 if (really_needs_scratch
)
5963 conf
->scratch_bytes_per_wave
=
5964 G_00B860_WAVESIZE(value
) * 256 * 4;
5966 case 0x4: /* SPILLED_SGPRS */
5967 conf
->spilled_sgprs
= value
;
5969 case 0x8: /* SPILLED_VGPRS */
5970 conf
->spilled_vgprs
= value
;
5974 static bool printed
;
5977 fprintf(stderr
, "Warning: LLVM emitted unknown "
5978 "config register: 0x%x\n", reg
);
5986 if (!conf
->spi_ps_input_addr
)
5987 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
5990 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
5991 struct si_shader
*shader
,
5992 struct si_shader_config
*config
,
5993 uint64_t scratch_va
)
5996 uint32_t scratch_rsrc_dword0
= scratch_va
;
5997 uint32_t scratch_rsrc_dword1
=
5998 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
6000 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6003 if (HAVE_LLVM
>= 0x0309)
6004 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
6006 scratch_rsrc_dword1
|=
6007 S_008F04_STRIDE(config
->scratch_bytes_per_wave
/ 64);
6009 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
6010 const struct radeon_shader_reloc
*reloc
=
6011 &shader
->binary
.relocs
[i
];
6012 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
6013 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6014 &scratch_rsrc_dword0
, 4);
6015 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
6016 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
6017 &scratch_rsrc_dword1
, 4);
6022 static unsigned si_get_shader_binary_size(struct si_shader
*shader
)
6024 unsigned size
= shader
->binary
.code_size
;
6027 size
+= shader
->prolog
->binary
.code_size
;
6029 size
+= shader
->epilog
->binary
.code_size
;
6033 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
6035 const struct radeon_shader_binary
*prolog
=
6036 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
6037 const struct radeon_shader_binary
*epilog
=
6038 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
6039 const struct radeon_shader_binary
*mainb
= &shader
->binary
;
6040 unsigned bo_size
= si_get_shader_binary_size(shader
) +
6041 (!epilog
? mainb
->rodata_size
: 0);
6044 assert(!prolog
|| !prolog
->rodata_size
);
6045 assert((!prolog
&& !epilog
) || !mainb
->rodata_size
);
6046 assert(!epilog
|| !epilog
->rodata_size
);
6048 r600_resource_reference(&shader
->bo
, NULL
);
6049 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
,
6050 PIPE_USAGE_IMMUTABLE
,
6056 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->buf
, NULL
,
6057 PIPE_TRANSFER_READ_WRITE
);
6060 util_memcpy_cpu_to_le32(ptr
, prolog
->code
, prolog
->code_size
);
6061 ptr
+= prolog
->code_size
;
6064 util_memcpy_cpu_to_le32(ptr
, mainb
->code
, mainb
->code_size
);
6065 ptr
+= mainb
->code_size
;
6068 util_memcpy_cpu_to_le32(ptr
, epilog
->code
, epilog
->code_size
);
6069 else if (mainb
->rodata_size
> 0)
6070 util_memcpy_cpu_to_le32(ptr
, mainb
->rodata
, mainb
->rodata_size
);
6072 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
6076 static void si_shader_dump_disassembly(const struct radeon_shader_binary
*binary
,
6077 struct pipe_debug_callback
*debug
,
6078 const char *name
, FILE *file
)
6083 if (binary
->disasm_string
) {
6084 fprintf(file
, "Shader %s disassembly:\n", name
);
6085 fprintf(file
, "%s", binary
->disasm_string
);
6087 if (debug
&& debug
->debug_message
) {
6088 /* Very long debug messages are cut off, so send the
6089 * disassembly one line at a time. This causes more
6090 * overhead, but on the plus side it simplifies
6091 * parsing of resulting logs.
6093 pipe_debug_message(debug
, SHADER_INFO
,
6094 "Shader Disassembly Begin");
6096 line
= binary
->disasm_string
;
6098 p
= util_strchrnul(line
, '\n');
6102 pipe_debug_message(debug
, SHADER_INFO
,
6103 "%.*s", count
, line
);
6111 pipe_debug_message(debug
, SHADER_INFO
,
6112 "Shader Disassembly End");
6115 fprintf(file
, "Shader %s binary:\n", name
);
6116 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
6117 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
6118 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
6119 binary
->code
[i
+ 1], binary
->code
[i
]);
6124 static void si_shader_dump_stats(struct si_screen
*sscreen
,
6125 struct si_shader_config
*conf
,
6126 unsigned num_inputs
,
6128 struct pipe_debug_callback
*debug
,
6132 unsigned lds_increment
= sscreen
->b
.chip_class
>= CIK
? 512 : 256;
6133 unsigned lds_per_wave
= 0;
6134 unsigned max_simd_waves
= 10;
6136 /* Compute LDS usage for PS. */
6137 if (processor
== PIPE_SHADER_FRAGMENT
) {
6138 /* The minimum usage per wave is (num_inputs * 48). The maximum
6139 * usage is (num_inputs * 48 * 16).
6140 * We can get anything in between and it varies between waves.
6142 * The 48 bytes per input for a single primitive is equal to
6143 * 4 bytes/component * 4 components/input * 3 points.
6145 * Other stages don't know the size at compile time or don't
6146 * allocate LDS per wave, but instead they do it per thread group.
6148 lds_per_wave
= conf
->lds_size
* lds_increment
+
6149 align(num_inputs
* 48, lds_increment
);
6152 /* Compute the per-SIMD wave counts. */
6153 if (conf
->num_sgprs
) {
6154 if (sscreen
->b
.chip_class
>= VI
)
6155 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
6157 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
6160 if (conf
->num_vgprs
)
6161 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
6163 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6167 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
6169 if (file
!= stderr
||
6170 r600_can_dump_shader(&sscreen
->b
, processor
)) {
6171 if (processor
== PIPE_SHADER_FRAGMENT
) {
6172 fprintf(file
, "*** SHADER CONFIG ***\n"
6173 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6174 "SPI_PS_INPUT_ENA = 0x%04x\n",
6175 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
6178 fprintf(file
, "*** SHADER STATS ***\n"
6181 "Spilled SGPRs: %d\n"
6182 "Spilled VGPRs: %d\n"
6183 "Code Size: %d bytes\n"
6185 "Scratch: %d bytes per wave\n"
6187 "********************\n\n\n",
6188 conf
->num_sgprs
, conf
->num_vgprs
,
6189 conf
->spilled_sgprs
, conf
->spilled_vgprs
, code_size
,
6190 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6194 pipe_debug_message(debug
, SHADER_INFO
,
6195 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6196 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6197 "Spilled VGPRs: %d",
6198 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
6199 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
6200 max_simd_waves
, conf
->spilled_sgprs
,
6201 conf
->spilled_vgprs
);
6204 static const char *si_get_shader_name(struct si_shader
*shader
,
6207 switch (processor
) {
6208 case PIPE_SHADER_VERTEX
:
6209 if (shader
->key
.vs
.as_es
)
6210 return "Vertex Shader as ES";
6211 else if (shader
->key
.vs
.as_ls
)
6212 return "Vertex Shader as LS";
6214 return "Vertex Shader as VS";
6215 case PIPE_SHADER_TESS_CTRL
:
6216 return "Tessellation Control Shader";
6217 case PIPE_SHADER_TESS_EVAL
:
6218 if (shader
->key
.tes
.as_es
)
6219 return "Tessellation Evaluation Shader as ES";
6221 return "Tessellation Evaluation Shader as VS";
6222 case PIPE_SHADER_GEOMETRY
:
6223 if (shader
->gs_copy_shader
== NULL
)
6224 return "GS Copy Shader as VS";
6226 return "Geometry Shader";
6227 case PIPE_SHADER_FRAGMENT
:
6228 return "Pixel Shader";
6229 case PIPE_SHADER_COMPUTE
:
6230 return "Compute Shader";
6232 return "Unknown Shader";
6236 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
6237 struct pipe_debug_callback
*debug
, unsigned processor
,
6240 if (file
!= stderr
||
6241 r600_can_dump_shader(&sscreen
->b
, processor
))
6242 si_dump_shader_key(processor
, &shader
->key
, file
);
6244 if (file
!= stderr
&& shader
->binary
.llvm_ir_string
) {
6245 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
6246 si_get_shader_name(shader
, processor
));
6247 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
6250 if (file
!= stderr
||
6251 (r600_can_dump_shader(&sscreen
->b
, processor
) &&
6252 !(sscreen
->b
.debug_flags
& DBG_NO_ASM
))) {
6253 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
6256 si_shader_dump_disassembly(&shader
->prolog
->binary
,
6257 debug
, "prolog", file
);
6259 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
6262 si_shader_dump_disassembly(&shader
->epilog
->binary
,
6263 debug
, "epilog", file
);
6264 fprintf(file
, "\n");
6267 si_shader_dump_stats(sscreen
, &shader
->config
,
6268 shader
->selector
? shader
->selector
->info
.num_inputs
: 0,
6269 si_get_shader_binary_size(shader
), debug
, processor
,
6273 int si_compile_llvm(struct si_screen
*sscreen
,
6274 struct radeon_shader_binary
*binary
,
6275 struct si_shader_config
*conf
,
6276 LLVMTargetMachineRef tm
,
6278 struct pipe_debug_callback
*debug
,
6283 unsigned count
= p_atomic_inc_return(&sscreen
->b
.num_compilations
);
6285 if (r600_can_dump_shader(&sscreen
->b
, processor
)) {
6286 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
6288 if (!(sscreen
->b
.debug_flags
& (DBG_NO_IR
| DBG_PREOPT_IR
))) {
6289 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
6290 LLVMDumpModule(mod
);
6291 fprintf(stderr
, "\n");
6295 if (sscreen
->record_llvm_ir
) {
6296 char *ir
= LLVMPrintModuleToString(mod
);
6297 binary
->llvm_ir_string
= strdup(ir
);
6298 LLVMDisposeMessage(ir
);
6301 if (!si_replace_shader(count
, binary
)) {
6302 r
= radeon_llvm_compile(mod
, binary
, tm
, debug
);
6307 si_shader_binary_read_config(binary
, conf
, 0);
6309 /* Enable 64-bit and 16-bit denormals, because there is no performance
6312 * If denormals are enabled, all floating-point output modifiers are
6315 * Don't enable denormals for 32-bit floats, because:
6316 * - Floating-point output modifiers would be ignored by the hw.
6317 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6318 * have to stop using those.
6319 * - SI & CI would be very slow.
6321 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
6323 FREE(binary
->config
);
6324 FREE(binary
->global_symbol_offsets
);
6325 binary
->config
= NULL
;
6326 binary
->global_symbol_offsets
= NULL
;
6328 /* Some shaders can't have rodata because their binaries can be
6331 if (binary
->rodata_size
&&
6332 (processor
== PIPE_SHADER_VERTEX
||
6333 processor
== PIPE_SHADER_TESS_CTRL
||
6334 processor
== PIPE_SHADER_TESS_EVAL
||
6335 processor
== PIPE_SHADER_FRAGMENT
)) {
6336 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
6343 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
6345 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
6346 LLVMBuildRetVoid(ctx
->radeon_bld
.gallivm
.builder
);
6348 LLVMBuildRet(ctx
->radeon_bld
.gallivm
.builder
, ret
);
6351 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6352 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
6353 struct si_shader_context
*ctx
,
6354 struct si_shader
*gs
,
6355 struct pipe_debug_callback
*debug
)
6357 struct gallivm_state
*gallivm
= &ctx
->radeon_bld
.gallivm
;
6358 struct lp_build_tgsi_context
*bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6359 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
6360 struct si_shader_output_values
*outputs
;
6361 struct tgsi_shader_info
*gsinfo
= &gs
->selector
->info
;
6362 LLVMValueRef args
[9];
6365 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
6367 si_init_shader_ctx(ctx
, sscreen
, ctx
->shader
, ctx
->tm
);
6368 ctx
->type
= PIPE_SHADER_VERTEX
;
6369 ctx
->is_gs_copy_shader
= true;
6371 create_meta_data(ctx
);
6372 create_function(ctx
);
6373 preload_streamout_buffers(ctx
);
6374 preload_ring_buffers(ctx
);
6376 args
[0] = ctx
->gsvs_ring
[0];
6377 args
[1] = lp_build_mul_imm(uint
,
6378 LLVMGetParam(ctx
->radeon_bld
.main_fn
,
6379 ctx
->param_vertex_id
),
6381 args
[3] = uint
->zero
;
6382 args
[4] = uint
->one
; /* OFFEN */
6383 args
[5] = uint
->zero
; /* IDXEN */
6384 args
[6] = uint
->one
; /* GLC */
6385 args
[7] = uint
->one
; /* SLC */
6386 args
[8] = uint
->zero
; /* TFE */
6388 /* Fetch vertex data from GSVS ring */
6389 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
6392 outputs
[i
].name
= gsinfo
->output_semantic_name
[i
];
6393 outputs
[i
].sid
= gsinfo
->output_semantic_index
[i
];
6395 for (chan
= 0; chan
< 4; chan
++) {
6396 args
[2] = lp_build_const_int32(gallivm
,
6398 gs
->selector
->gs_max_out_vertices
* 16 * 4);
6400 outputs
[i
].values
[chan
] =
6401 LLVMBuildBitCast(gallivm
->builder
,
6402 lp_build_intrinsic(gallivm
->builder
,
6403 "llvm.SI.buffer.load.dword.i32.i32",
6405 LLVMReadOnlyAttribute
),
6410 si_llvm_export_vs(bld_base
, outputs
, gsinfo
->num_outputs
);
6412 LLVMBuildRetVoid(gallivm
->builder
);
6414 /* Dump LLVM IR before any optimization passes */
6415 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6416 r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6417 LLVMDumpModule(bld_base
->base
.gallivm
->module
);
6419 radeon_llvm_finalize_module(&ctx
->radeon_bld
);
6421 r
= si_compile_llvm(sscreen
, &ctx
->shader
->binary
,
6422 &ctx
->shader
->config
, ctx
->tm
,
6423 bld_base
->base
.gallivm
->module
,
6424 debug
, PIPE_SHADER_GEOMETRY
,
6427 if (r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_GEOMETRY
))
6428 fprintf(stderr
, "GS Copy Shader:\n");
6429 si_shader_dump(sscreen
, ctx
->shader
, debug
,
6430 PIPE_SHADER_GEOMETRY
, stderr
);
6431 r
= si_shader_binary_upload(sscreen
, ctx
->shader
);
6434 radeon_llvm_dispose(&ctx
->radeon_bld
);
6440 static void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
,
6445 fprintf(f
, "SHADER KEY\n");
6448 case PIPE_SHADER_VERTEX
:
6449 fprintf(f
, " instance_divisors = {");
6450 for (i
= 0; i
< ARRAY_SIZE(key
->vs
.prolog
.instance_divisors
); i
++)
6451 fprintf(f
, !i
? "%u" : ", %u",
6452 key
->vs
.prolog
.instance_divisors
[i
]);
6454 fprintf(f
, " as_es = %u\n", key
->vs
.as_es
);
6455 fprintf(f
, " as_ls = %u\n", key
->vs
.as_ls
);
6456 fprintf(f
, " export_prim_id = %u\n", key
->vs
.epilog
.export_prim_id
);
6459 case PIPE_SHADER_TESS_CTRL
:
6460 fprintf(f
, " prim_mode = %u\n", key
->tcs
.epilog
.prim_mode
);
6463 case PIPE_SHADER_TESS_EVAL
:
6464 fprintf(f
, " as_es = %u\n", key
->tes
.as_es
);
6465 fprintf(f
, " export_prim_id = %u\n", key
->tes
.epilog
.export_prim_id
);
6468 case PIPE_SHADER_GEOMETRY
:
6469 case PIPE_SHADER_COMPUTE
:
6472 case PIPE_SHADER_FRAGMENT
:
6473 fprintf(f
, " prolog.color_two_side = %u\n", key
->ps
.prolog
.color_two_side
);
6474 fprintf(f
, " prolog.flatshade_colors = %u\n", key
->ps
.prolog
.flatshade_colors
);
6475 fprintf(f
, " prolog.poly_stipple = %u\n", key
->ps
.prolog
.poly_stipple
);
6476 fprintf(f
, " prolog.force_persp_sample_interp = %u\n", key
->ps
.prolog
.force_persp_sample_interp
);
6477 fprintf(f
, " prolog.force_linear_sample_interp = %u\n", key
->ps
.prolog
.force_linear_sample_interp
);
6478 fprintf(f
, " prolog.force_persp_center_interp = %u\n", key
->ps
.prolog
.force_persp_center_interp
);
6479 fprintf(f
, " prolog.force_linear_center_interp = %u\n", key
->ps
.prolog
.force_linear_center_interp
);
6480 fprintf(f
, " prolog.bc_optimize_for_persp = %u\n", key
->ps
.prolog
.bc_optimize_for_persp
);
6481 fprintf(f
, " prolog.bc_optimize_for_linear = %u\n", key
->ps
.prolog
.bc_optimize_for_linear
);
6482 fprintf(f
, " epilog.spi_shader_col_format = 0x%x\n", key
->ps
.epilog
.spi_shader_col_format
);
6483 fprintf(f
, " epilog.color_is_int8 = 0x%X\n", key
->ps
.epilog
.color_is_int8
);
6484 fprintf(f
, " epilog.last_cbuf = %u\n", key
->ps
.epilog
.last_cbuf
);
6485 fprintf(f
, " epilog.alpha_func = %u\n", key
->ps
.epilog
.alpha_func
);
6486 fprintf(f
, " epilog.alpha_to_one = %u\n", key
->ps
.epilog
.alpha_to_one
);
6487 fprintf(f
, " epilog.poly_line_smoothing = %u\n", key
->ps
.epilog
.poly_line_smoothing
);
6488 fprintf(f
, " epilog.clamp_color = %u\n", key
->ps
.epilog
.clamp_color
);
6496 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
6497 struct si_screen
*sscreen
,
6498 struct si_shader
*shader
,
6499 LLVMTargetMachineRef tm
)
6501 struct lp_build_tgsi_context
*bld_base
;
6502 struct lp_build_tgsi_action tmpl
= {};
6504 memset(ctx
, 0, sizeof(*ctx
));
6505 radeon_llvm_context_init(
6506 &ctx
->radeon_bld
, "amdgcn--",
6507 (shader
&& shader
->selector
) ? &shader
->selector
->info
: NULL
,
6508 (shader
&& shader
->selector
) ? shader
->selector
->tokens
: NULL
);
6510 ctx
->screen
= sscreen
;
6511 if (shader
&& shader
->selector
)
6512 ctx
->type
= shader
->selector
->info
.processor
;
6515 ctx
->shader
= shader
;
6517 ctx
->voidt
= LLVMVoidTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6518 ctx
->i1
= LLVMInt1TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6519 ctx
->i8
= LLVMInt8TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6520 ctx
->i32
= LLVMInt32TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6521 ctx
->i64
= LLVMInt64TypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6522 ctx
->i128
= LLVMIntTypeInContext(ctx
->radeon_bld
.gallivm
.context
, 128);
6523 ctx
->f32
= LLVMFloatTypeInContext(ctx
->radeon_bld
.gallivm
.context
);
6524 ctx
->v16i8
= LLVMVectorType(ctx
->i8
, 16);
6525 ctx
->v2i32
= LLVMVectorType(ctx
->i32
, 2);
6526 ctx
->v4i32
= LLVMVectorType(ctx
->i32
, 4);
6527 ctx
->v4f32
= LLVMVectorType(ctx
->f32
, 4);
6528 ctx
->v8i32
= LLVMVectorType(ctx
->i32
, 8);
6530 bld_base
= &ctx
->radeon_bld
.soa
.bld_base
;
6531 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
6533 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
6534 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
6535 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
6537 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
6538 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
6539 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
6540 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
6541 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
6542 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
6543 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
6544 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
6545 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
6546 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
6547 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
6548 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
6549 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
6550 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
6552 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
6553 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
6554 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
6555 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
6556 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
6557 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
6559 tmpl
.fetch_args
= atomic_fetch_args
;
6560 tmpl
.emit
= atomic_emit
;
6561 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
6562 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
6563 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
6564 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
6565 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
6566 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
6567 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
6568 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
6569 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
6570 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
6571 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
6572 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
6573 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
6574 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
6575 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
6576 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
6577 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
6578 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
6579 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
6580 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";
6582 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
6584 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
6585 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
6586 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
6587 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
6589 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
6590 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
6591 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6593 bld_base
->op_actions
[TGSI_OPCODE_MAX
].emit
= build_tgsi_intrinsic_nomem
;
6594 bld_base
->op_actions
[TGSI_OPCODE_MAX
].intr_name
= "llvm.maxnum.f32";
6595 bld_base
->op_actions
[TGSI_OPCODE_MIN
].emit
= build_tgsi_intrinsic_nomem
;
6596 bld_base
->op_actions
[TGSI_OPCODE_MIN
].intr_name
= "llvm.minnum.f32";
6599 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6600 LLVMTargetMachineRef tm
,
6601 struct si_shader
*shader
,
6603 struct pipe_debug_callback
*debug
)
6605 struct si_shader_selector
*sel
= shader
->selector
;
6606 struct si_shader_context ctx
;
6607 struct lp_build_tgsi_context
*bld_base
;
6611 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6612 * conversion fails. */
6613 if (r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) &&
6614 !(sscreen
->b
.debug_flags
& DBG_NO_TGSI
)) {
6615 tgsi_dump(sel
->tokens
, 0);
6616 si_dump_streamout(&sel
->so
);
6619 si_init_shader_ctx(&ctx
, sscreen
, shader
, tm
);
6620 ctx
.is_monolithic
= is_monolithic
;
6622 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6624 bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
6625 ctx
.radeon_bld
.load_system_value
= declare_system_value
;
6628 case PIPE_SHADER_VERTEX
:
6629 ctx
.radeon_bld
.load_input
= declare_input_vs
;
6630 if (shader
->key
.vs
.as_ls
)
6631 bld_base
->emit_epilogue
= si_llvm_emit_ls_epilogue
;
6632 else if (shader
->key
.vs
.as_es
)
6633 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6635 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6637 case PIPE_SHADER_TESS_CTRL
:
6638 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6639 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6640 bld_base
->emit_store
= store_output_tcs
;
6641 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
6643 case PIPE_SHADER_TESS_EVAL
:
6644 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6645 if (shader
->key
.tes
.as_es
)
6646 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
6648 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
6650 case PIPE_SHADER_GEOMETRY
:
6651 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6652 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
6654 case PIPE_SHADER_FRAGMENT
:
6655 ctx
.radeon_bld
.load_input
= declare_input_fs
;
6657 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
6659 bld_base
->emit_epilogue
= si_llvm_return_fs_outputs
;
6661 case PIPE_SHADER_COMPUTE
:
6662 ctx
.radeon_bld
.declare_memory_region
= declare_compute_memory
;
6665 assert(!"Unsupported shader type");
6669 create_meta_data(&ctx
);
6670 create_function(&ctx
);
6671 preload_constants(&ctx
);
6672 preload_shader_buffers(&ctx
);
6673 preload_samplers(&ctx
);
6674 preload_images(&ctx
);
6675 preload_streamout_buffers(&ctx
);
6676 preload_ring_buffers(&ctx
);
6678 if (ctx
.is_monolithic
&& sel
->type
== PIPE_SHADER_FRAGMENT
&&
6679 shader
->key
.ps
.prolog
.poly_stipple
) {
6680 LLVMValueRef list
= LLVMGetParam(ctx
.radeon_bld
.main_fn
,
6681 SI_PARAM_RW_BUFFERS
);
6682 si_llvm_emit_polygon_stipple(&ctx
, list
,
6683 SI_PARAM_POS_FIXED_PT
);
6686 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6688 for (i
= 0; i
< 4; i
++) {
6689 ctx
.gs_next_vertex
[i
] =
6690 lp_build_alloca(bld_base
->base
.gallivm
,
6695 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6696 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6700 si_llvm_build_ret(&ctx
, ctx
.return_value
);
6701 mod
= bld_base
->base
.gallivm
->module
;
6703 /* Dump LLVM IR before any optimization passes */
6704 if (sscreen
->b
.debug_flags
& DBG_PREOPT_IR
&&
6705 r600_can_dump_shader(&sscreen
->b
, ctx
.type
))
6706 LLVMDumpModule(mod
);
6708 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6710 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
6711 mod
, debug
, ctx
.type
, "TGSI shader");
6713 fprintf(stderr
, "LLVM failed to compile shader\n");
6717 radeon_llvm_dispose(&ctx
.radeon_bld
);
6719 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6720 * LLVM 3.9svn has this bug.
6722 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6723 unsigned *props
= sel
->info
.properties
;
6724 unsigned wave_size
= 64;
6725 unsigned max_vgprs
= 256;
6726 unsigned max_sgprs
= sscreen
->b
.chip_class
>= VI
? 800 : 512;
6727 unsigned max_sgprs_per_wave
= 128;
6728 unsigned min_waves_per_cu
=
6729 DIV_ROUND_UP(props
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
6730 props
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
6731 props
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
],
6733 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
6735 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
6736 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
6738 if (shader
->config
.num_sgprs
> max_sgprs
||
6739 shader
->config
.num_vgprs
> max_vgprs
) {
6740 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
6741 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6742 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
6743 max_sgprs
, max_vgprs
);
6745 /* Just terminate the process, because dependent
6746 * shaders can hang due to bad input data, but use
6747 * the env var to allow shader-db to work.
6749 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6754 /* Add the scratch offset to input SGPRs. */
6755 if (shader
->config
.scratch_bytes_per_wave
)
6756 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
6758 /* Calculate the number of fragment input VGPRs. */
6759 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6760 shader
->info
.num_input_vgprs
= 0;
6761 shader
->info
.face_vgpr_index
= -1;
6763 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6764 shader
->info
.num_input_vgprs
+= 2;
6765 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6766 shader
->info
.num_input_vgprs
+= 2;
6767 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6768 shader
->info
.num_input_vgprs
+= 2;
6769 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
6770 shader
->info
.num_input_vgprs
+= 3;
6771 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
6772 shader
->info
.num_input_vgprs
+= 2;
6773 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
6774 shader
->info
.num_input_vgprs
+= 2;
6775 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
6776 shader
->info
.num_input_vgprs
+= 2;
6777 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
6778 shader
->info
.num_input_vgprs
+= 1;
6779 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6780 shader
->info
.num_input_vgprs
+= 1;
6781 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6782 shader
->info
.num_input_vgprs
+= 1;
6783 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6784 shader
->info
.num_input_vgprs
+= 1;
6785 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
6786 shader
->info
.num_input_vgprs
+= 1;
6787 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
6788 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
6789 shader
->info
.num_input_vgprs
+= 1;
6791 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
))
6792 shader
->info
.num_input_vgprs
+= 1;
6793 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
6794 shader
->info
.num_input_vgprs
+= 1;
6795 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
6796 shader
->info
.num_input_vgprs
+= 1;
6799 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6800 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
6801 shader
->gs_copy_shader
->selector
= shader
->selector
;
6802 ctx
.shader
= shader
->gs_copy_shader
;
6803 if ((r
= si_generate_gs_copy_shader(sscreen
, &ctx
,
6805 free(shader
->gs_copy_shader
);
6806 shader
->gs_copy_shader
= NULL
;
6812 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
6813 FREE(ctx
.constants
[i
]);
6818 * Create, compile and return a shader part (prolog or epilog).
6820 * \param sscreen screen
6821 * \param list list of shader parts of the same category
6822 * \param key shader part key
6823 * \param tm LLVM target machine
6824 * \param debug debug callback
6825 * \param compile the callback responsible for compilation
6826 * \return non-NULL on success
6828 static struct si_shader_part
*
6829 si_get_shader_part(struct si_screen
*sscreen
,
6830 struct si_shader_part
**list
,
6831 union si_shader_part_key
*key
,
6832 LLVMTargetMachineRef tm
,
6833 struct pipe_debug_callback
*debug
,
6834 bool (*compile
)(struct si_screen
*,
6835 LLVMTargetMachineRef
,
6836 struct pipe_debug_callback
*,
6837 struct si_shader_part
*))
6839 struct si_shader_part
*result
;
6841 pipe_mutex_lock(sscreen
->shader_parts_mutex
);
6843 /* Find existing. */
6844 for (result
= *list
; result
; result
= result
->next
) {
6845 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
6846 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6851 /* Compile a new one. */
6852 result
= CALLOC_STRUCT(si_shader_part
);
6854 if (!compile(sscreen
, tm
, debug
, result
)) {
6856 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6860 result
->next
= *list
;
6862 pipe_mutex_unlock(sscreen
->shader_parts_mutex
);
6867 * Create a vertex shader prolog.
6869 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6870 * All inputs are returned unmodified. The vertex load indices are
6871 * stored after them, which will used by the API VS for fetching inputs.
6873 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6878 * (VertexID + BaseVertex),
6879 * (InstanceID + StartInstance),
6880 * (InstanceID / 2 + StartInstance)
6882 static bool si_compile_vs_prolog(struct si_screen
*sscreen
,
6883 LLVMTargetMachineRef tm
,
6884 struct pipe_debug_callback
*debug
,
6885 struct si_shader_part
*out
)
6887 union si_shader_part_key
*key
= &out
->key
;
6888 struct si_shader shader
= {};
6889 struct si_shader_context ctx
;
6890 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
6891 LLVMTypeRef
*params
, *returns
;
6892 LLVMValueRef ret
, func
;
6893 int last_sgpr
, num_params
, num_returns
, i
;
6896 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
6897 ctx
.type
= PIPE_SHADER_VERTEX
;
6898 ctx
.param_vertex_id
= key
->vs_prolog
.num_input_sgprs
;
6899 ctx
.param_instance_id
= key
->vs_prolog
.num_input_sgprs
+ 3;
6901 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6902 params
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4) *
6903 sizeof(LLVMTypeRef
));
6904 returns
= alloca((key
->vs_prolog
.num_input_sgprs
+ 4 +
6905 key
->vs_prolog
.last_input
+ 1) *
6906 sizeof(LLVMTypeRef
));
6910 /* Declare input and output SGPRs. */
6912 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6913 params
[num_params
++] = ctx
.i32
;
6914 returns
[num_returns
++] = ctx
.i32
;
6916 last_sgpr
= num_params
- 1;
6918 /* 4 preloaded VGPRs (outputs must be floats) */
6919 for (i
= 0; i
< 4; i
++) {
6920 params
[num_params
++] = ctx
.i32
;
6921 returns
[num_returns
++] = ctx
.f32
;
6924 /* Vertex load indices. */
6925 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
6926 returns
[num_returns
++] = ctx
.f32
;
6928 /* Create the function. */
6929 si_create_function(&ctx
, returns
, num_returns
, params
,
6930 num_params
, last_sgpr
);
6931 func
= ctx
.radeon_bld
.main_fn
;
6933 /* Copy inputs to outputs. This should be no-op, as the registers match,
6934 * but it will prevent the compiler from overwriting them unintentionally.
6936 ret
= ctx
.return_value
;
6937 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
6938 LLVMValueRef p
= LLVMGetParam(func
, i
);
6939 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6941 for (i
= num_params
- 4; i
< num_params
; i
++) {
6942 LLVMValueRef p
= LLVMGetParam(func
, i
);
6943 p
= LLVMBuildBitCast(gallivm
->builder
, p
, ctx
.f32
, "");
6944 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
6947 /* Compute vertex load indices from instance divisors. */
6948 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
6949 unsigned divisor
= key
->vs_prolog
.states
.instance_divisors
[i
];
6953 /* InstanceID / Divisor + StartInstance */
6954 index
= get_instance_index_for_fetch(&ctx
.radeon_bld
,
6955 SI_SGPR_START_INSTANCE
,
6958 /* VertexID + BaseVertex */
6959 index
= LLVMBuildAdd(gallivm
->builder
,
6960 LLVMGetParam(func
, ctx
.param_vertex_id
),
6961 LLVMGetParam(func
, SI_SGPR_BASE_VERTEX
), "");
6964 index
= LLVMBuildBitCast(gallivm
->builder
, index
, ctx
.f32
, "");
6965 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, index
,
6970 si_llvm_build_ret(&ctx
, ret
);
6971 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
6973 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
6974 gallivm
->module
, debug
, ctx
.type
,
6975 "Vertex Shader Prolog"))
6978 radeon_llvm_dispose(&ctx
.radeon_bld
);
6983 * Compile the vertex shader epilog. This is also used by the tessellation
6984 * evaluation shader compiled as VS.
6986 * The input is PrimitiveID.
6988 * If PrimitiveID is required by the pixel shader, export it.
6989 * Otherwise, do nothing.
6991 static bool si_compile_vs_epilog(struct si_screen
*sscreen
,
6992 LLVMTargetMachineRef tm
,
6993 struct pipe_debug_callback
*debug
,
6994 struct si_shader_part
*out
)
6996 union si_shader_part_key
*key
= &out
->key
;
6997 struct si_shader_context ctx
;
6998 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
6999 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7000 LLVMTypeRef params
[5];
7004 si_init_shader_ctx(&ctx
, sscreen
, NULL
, tm
);
7005 ctx
.type
= PIPE_SHADER_VERTEX
;
7007 /* Declare input VGPRs. */
7008 num_params
= key
->vs_epilog
.states
.export_prim_id
?
7009 (VS_EPILOG_PRIMID_LOC
+ 1) : 0;
7010 assert(num_params
<= ARRAY_SIZE(params
));
7012 for (i
= 0; i
< num_params
; i
++)
7013 params
[i
] = ctx
.f32
;
7015 /* Create the function. */
7016 si_create_function(&ctx
, NULL
, 0, params
, num_params
, -1);
7019 if (key
->vs_epilog
.states
.export_prim_id
) {
7020 struct lp_build_context
*base
= &bld_base
->base
;
7021 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
7022 LLVMValueRef args
[9];
7024 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
7025 args
[1] = uint
->zero
; /* whether the EXEC mask is valid */
7026 args
[2] = uint
->zero
; /* DONE bit */
7027 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_PARAM
+
7028 key
->vs_epilog
.prim_id_param_offset
);
7029 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
7030 args
[5] = LLVMGetParam(ctx
.radeon_bld
.main_fn
,
7031 VS_EPILOG_PRIMID_LOC
); /* X */
7032 args
[6] = uint
->undef
; /* Y */
7033 args
[7] = uint
->undef
; /* Z */
7034 args
[8] = uint
->undef
; /* W */
7036 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
7037 LLVMVoidTypeInContext(base
->gallivm
->context
),
7042 LLVMBuildRetVoid(gallivm
->builder
);
7043 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7045 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7046 gallivm
->module
, debug
, ctx
.type
,
7047 "Vertex Shader Epilog"))
7050 radeon_llvm_dispose(&ctx
.radeon_bld
);
7055 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7057 static bool si_get_vs_epilog(struct si_screen
*sscreen
,
7058 LLVMTargetMachineRef tm
,
7059 struct si_shader
*shader
,
7060 struct pipe_debug_callback
*debug
,
7061 struct si_vs_epilog_bits
*states
)
7063 union si_shader_part_key epilog_key
;
7065 memset(&epilog_key
, 0, sizeof(epilog_key
));
7066 epilog_key
.vs_epilog
.states
= *states
;
7068 /* Set up the PrimitiveID output. */
7069 if (shader
->key
.vs
.epilog
.export_prim_id
) {
7070 unsigned index
= shader
->selector
->info
.num_outputs
;
7071 unsigned offset
= shader
->info
.nr_param_exports
++;
7073 epilog_key
.vs_epilog
.prim_id_param_offset
= offset
;
7074 assert(index
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
7075 shader
->info
.vs_output_param_offset
[index
] = offset
;
7078 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->vs_epilogs
,
7079 &epilog_key
, tm
, debug
,
7080 si_compile_vs_epilog
);
7081 return shader
->epilog
!= NULL
;
7085 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7087 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7088 LLVMTargetMachineRef tm
,
7089 struct si_shader
*shader
,
7090 struct pipe_debug_callback
*debug
)
7092 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7093 union si_shader_part_key prolog_key
;
7096 /* Get the prolog. */
7097 memset(&prolog_key
, 0, sizeof(prolog_key
));
7098 prolog_key
.vs_prolog
.states
= shader
->key
.vs
.prolog
;
7099 prolog_key
.vs_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7100 prolog_key
.vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
7102 /* The prolog is a no-op if there are no inputs. */
7103 if (info
->num_inputs
) {
7105 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7106 &prolog_key
, tm
, debug
,
7107 si_compile_vs_prolog
);
7108 if (!shader
->prolog
)
7112 /* Get the epilog. */
7113 if (!shader
->key
.vs
.as_es
&& !shader
->key
.vs
.as_ls
&&
7114 !si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7115 &shader
->key
.vs
.epilog
))
7118 /* Set the instanceID flag. */
7119 for (i
= 0; i
< info
->num_inputs
; i
++)
7120 if (prolog_key
.vs_prolog
.states
.instance_divisors
[i
])
7121 shader
->info
.uses_instanceid
= true;
7127 * Select and compile (or reuse) TES parts (epilog).
7129 static bool si_shader_select_tes_parts(struct si_screen
*sscreen
,
7130 LLVMTargetMachineRef tm
,
7131 struct si_shader
*shader
,
7132 struct pipe_debug_callback
*debug
)
7134 if (shader
->key
.tes
.as_es
)
7137 /* TES compiled as VS. */
7138 return si_get_vs_epilog(sscreen
, tm
, shader
, debug
,
7139 &shader
->key
.tes
.epilog
);
7143 * Compile the TCS epilog. This writes tesselation factors to memory based on
7144 * the output primitive type of the tesselator (determined by TES).
7146 static bool si_compile_tcs_epilog(struct si_screen
*sscreen
,
7147 LLVMTargetMachineRef tm
,
7148 struct pipe_debug_callback
*debug
,
7149 struct si_shader_part
*out
)
7151 union si_shader_part_key
*key
= &out
->key
;
7152 struct si_shader shader
= {};
7153 struct si_shader_context ctx
;
7154 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7155 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7156 LLVMTypeRef params
[16];
7158 int last_sgpr
, num_params
;
7161 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7162 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
7163 shader
.key
.tcs
.epilog
= key
->tcs_epilog
.states
;
7165 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7166 params
[SI_PARAM_RW_BUFFERS
] = const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
);
7167 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7168 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7169 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7170 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7171 params
[SI_PARAM_TCS_OFFCHIP_LAYOUT
] = ctx
.i32
;
7172 params
[SI_PARAM_TCS_OUT_OFFSETS
] = ctx
.i32
;
7173 params
[SI_PARAM_TCS_OUT_LAYOUT
] = ctx
.i32
;
7174 params
[SI_PARAM_TCS_IN_LAYOUT
] = ctx
.i32
;
7175 params
[ctx
.param_oc_lds
= SI_PARAM_TCS_OC_LDS
] = ctx
.i32
;
7176 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = ctx
.i32
;
7177 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
7178 num_params
= last_sgpr
+ 1;
7180 params
[num_params
++] = ctx
.i32
; /* patch index within the wave (REL_PATCH_ID) */
7181 params
[num_params
++] = ctx
.i32
; /* invocation ID within the patch */
7182 params
[num_params
++] = ctx
.i32
; /* LDS offset where tess factors should be loaded from */
7184 /* Create the function. */
7185 si_create_function(&ctx
, NULL
, 0, params
, num_params
, last_sgpr
);
7186 declare_tess_lds(&ctx
);
7187 func
= ctx
.radeon_bld
.main_fn
;
7189 si_write_tess_factors(bld_base
,
7190 LLVMGetParam(func
, last_sgpr
+ 1),
7191 LLVMGetParam(func
, last_sgpr
+ 2),
7192 LLVMGetParam(func
, last_sgpr
+ 3));
7195 LLVMBuildRetVoid(gallivm
->builder
);
7196 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7198 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7199 gallivm
->module
, debug
, ctx
.type
,
7200 "Tessellation Control Shader Epilog"))
7203 radeon_llvm_dispose(&ctx
.radeon_bld
);
7208 * Select and compile (or reuse) TCS parts (epilog).
7210 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7211 LLVMTargetMachineRef tm
,
7212 struct si_shader
*shader
,
7213 struct pipe_debug_callback
*debug
)
7215 union si_shader_part_key epilog_key
;
7217 /* Get the epilog. */
7218 memset(&epilog_key
, 0, sizeof(epilog_key
));
7219 epilog_key
.tcs_epilog
.states
= shader
->key
.tcs
.epilog
;
7221 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7222 &epilog_key
, tm
, debug
,
7223 si_compile_tcs_epilog
);
7224 return shader
->epilog
!= NULL
;
7228 * Compile the pixel shader prolog. This handles:
7229 * - two-side color selection and interpolation
7230 * - overriding interpolation parameters for the API PS
7231 * - polygon stippling
7233 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7234 * overriden by other states. (e.g. per-sample interpolation)
7235 * Interpolated colors are stored after the preloaded VGPRs.
7237 static bool si_compile_ps_prolog(struct si_screen
*sscreen
,
7238 LLVMTargetMachineRef tm
,
7239 struct pipe_debug_callback
*debug
,
7240 struct si_shader_part
*out
)
7242 union si_shader_part_key
*key
= &out
->key
;
7243 struct si_shader shader
= {};
7244 struct si_shader_context ctx
;
7245 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7246 LLVMTypeRef
*params
;
7247 LLVMValueRef ret
, func
;
7248 int last_sgpr
, num_params
, num_returns
, i
, num_color_channels
;
7251 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7252 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7253 shader
.key
.ps
.prolog
= key
->ps_prolog
.states
;
7255 /* Number of inputs + 8 color elements. */
7256 params
= alloca((key
->ps_prolog
.num_input_sgprs
+
7257 key
->ps_prolog
.num_input_vgprs
+ 8) *
7258 sizeof(LLVMTypeRef
));
7260 /* Declare inputs. */
7262 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7263 params
[num_params
++] = ctx
.i32
;
7264 last_sgpr
= num_params
- 1;
7266 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7267 params
[num_params
++] = ctx
.f32
;
7269 /* Declare outputs (same as inputs + add colors if needed) */
7270 num_returns
= num_params
;
7271 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7272 for (i
= 0; i
< num_color_channels
; i
++)
7273 params
[num_returns
++] = ctx
.f32
;
7275 /* Create the function. */
7276 si_create_function(&ctx
, params
, num_returns
, params
,
7277 num_params
, last_sgpr
);
7278 func
= ctx
.radeon_bld
.main_fn
;
7280 /* Copy inputs to outputs. This should be no-op, as the registers match,
7281 * but it will prevent the compiler from overwriting them unintentionally.
7283 ret
= ctx
.return_value
;
7284 for (i
= 0; i
< num_params
; i
++) {
7285 LLVMValueRef p
= LLVMGetParam(func
, i
);
7286 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, p
, i
, "");
7289 /* Polygon stippling. */
7290 if (key
->ps_prolog
.states
.poly_stipple
) {
7291 /* POS_FIXED_PT is always last. */
7292 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7293 key
->ps_prolog
.num_input_vgprs
- 1;
7294 LLVMValueRef ptr
[2], list
;
7296 /* Get the pointer to rw buffers. */
7297 ptr
[0] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS
);
7298 ptr
[1] = LLVMGetParam(func
, SI_SGPR_RW_BUFFERS_HI
);
7299 list
= lp_build_gather_values(gallivm
, ptr
, 2);
7300 list
= LLVMBuildBitCast(gallivm
->builder
, list
, ctx
.i64
, "");
7301 list
= LLVMBuildIntToPtr(gallivm
->builder
, list
,
7302 const_array(ctx
.v16i8
, SI_NUM_RW_BUFFERS
), "");
7304 si_llvm_emit_polygon_stipple(&ctx
, list
, pos
);
7307 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7308 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7309 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7310 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7312 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7313 * The hw doesn't compute CENTROID if the whole wave only
7314 * contains fully-covered quads.
7316 * PRIM_MASK is after user SGPRs.
7318 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7319 bc_optimize
= LLVMBuildLShr(gallivm
->builder
, bc_optimize
,
7320 LLVMConstInt(ctx
.i32
, 31, 0), "");
7321 bc_optimize
= LLVMBuildTrunc(gallivm
->builder
, bc_optimize
,
7324 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7325 /* Read PERSP_CENTER. */
7326 for (i
= 0; i
< 2; i
++)
7327 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7328 /* Read PERSP_CENTROID. */
7329 for (i
= 0; i
< 2; i
++)
7330 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7331 /* Select PERSP_CENTROID. */
7332 for (i
= 0; i
< 2; i
++) {
7333 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7334 center
[i
], centroid
[i
], "");
7335 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7336 tmp
, base
+ 4 + i
, "");
7339 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7340 /* Read LINEAR_CENTER. */
7341 for (i
= 0; i
< 2; i
++)
7342 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7343 /* Read LINEAR_CENTROID. */
7344 for (i
= 0; i
< 2; i
++)
7345 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7346 /* Select LINEAR_CENTROID. */
7347 for (i
= 0; i
< 2; i
++) {
7348 tmp
= LLVMBuildSelect(gallivm
->builder
, bc_optimize
,
7349 center
[i
], centroid
[i
], "");
7350 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7351 tmp
, base
+ 10 + i
, "");
7356 /* Interpolate colors. */
7357 for (i
= 0; i
< 2; i
++) {
7358 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7359 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7360 key
->ps_prolog
.face_vgpr_index
;
7361 LLVMValueRef interp
[2], color
[4];
7362 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7367 /* If the interpolation qualifier is not CONSTANT (-1). */
7368 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7369 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7370 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7372 /* Get the (i,j) updated by bc_optimize handling. */
7373 interp
[0] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7375 interp
[1] = LLVMBuildExtractValue(gallivm
->builder
, ret
,
7376 interp_vgpr
+ 1, "");
7377 interp_ij
= lp_build_gather_values(gallivm
, interp
, 2);
7378 interp_ij
= LLVMBuildBitCast(gallivm
->builder
, interp_ij
,
7382 /* Use the absolute location of the input. */
7383 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7385 if (key
->ps_prolog
.states
.color_two_side
) {
7386 face
= LLVMGetParam(func
, face_vgpr
);
7387 face
= LLVMBuildBitCast(gallivm
->builder
, face
, ctx
.i32
, "");
7390 interp_fs_input(&ctx
,
7391 key
->ps_prolog
.color_attr_index
[i
],
7392 TGSI_SEMANTIC_COLOR
, i
,
7393 key
->ps_prolog
.num_interp_inputs
,
7394 key
->ps_prolog
.colors_read
, interp_ij
,
7395 prim_mask
, face
, color
);
7398 unsigned chan
= u_bit_scan(&writemask
);
7399 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
, color
[chan
],
7404 /* Force per-sample interpolation. */
7405 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7406 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7407 LLVMValueRef persp_sample
[2];
7409 /* Read PERSP_SAMPLE. */
7410 for (i
= 0; i
< 2; i
++)
7411 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7412 /* Overwrite PERSP_CENTER. */
7413 for (i
= 0; i
< 2; i
++)
7414 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7415 persp_sample
[i
], base
+ 2 + i
, "");
7416 /* Overwrite PERSP_CENTROID. */
7417 for (i
= 0; i
< 2; i
++)
7418 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7419 persp_sample
[i
], base
+ 4 + i
, "");
7421 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7422 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7423 LLVMValueRef linear_sample
[2];
7425 /* Read LINEAR_SAMPLE. */
7426 for (i
= 0; i
< 2; i
++)
7427 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7428 /* Overwrite LINEAR_CENTER. */
7429 for (i
= 0; i
< 2; i
++)
7430 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7431 linear_sample
[i
], base
+ 8 + i
, "");
7432 /* Overwrite LINEAR_CENTROID. */
7433 for (i
= 0; i
< 2; i
++)
7434 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7435 linear_sample
[i
], base
+ 10 + i
, "");
7438 /* Force center interpolation. */
7439 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7440 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7441 LLVMValueRef persp_center
[2];
7443 /* Read PERSP_CENTER. */
7444 for (i
= 0; i
< 2; i
++)
7445 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7446 /* Overwrite PERSP_SAMPLE. */
7447 for (i
= 0; i
< 2; i
++)
7448 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7449 persp_center
[i
], base
+ i
, "");
7450 /* Overwrite PERSP_CENTROID. */
7451 for (i
= 0; i
< 2; i
++)
7452 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7453 persp_center
[i
], base
+ 4 + i
, "");
7455 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7456 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7457 LLVMValueRef linear_center
[2];
7459 /* Read LINEAR_CENTER. */
7460 for (i
= 0; i
< 2; i
++)
7461 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7462 /* Overwrite LINEAR_SAMPLE. */
7463 for (i
= 0; i
< 2; i
++)
7464 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7465 linear_center
[i
], base
+ 6 + i
, "");
7466 /* Overwrite LINEAR_CENTROID. */
7467 for (i
= 0; i
< 2; i
++)
7468 ret
= LLVMBuildInsertValue(gallivm
->builder
, ret
,
7469 linear_center
[i
], base
+ 10 + i
, "");
7472 /* Tell LLVM to insert WQM instruction sequence when needed. */
7473 if (key
->ps_prolog
.wqm
) {
7474 LLVMAddTargetDependentFunctionAttr(func
,
7475 "amdgpu-ps-wqm-outputs", "");
7479 si_llvm_build_ret(&ctx
, ret
);
7480 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7482 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7483 gallivm
->module
, debug
, ctx
.type
,
7484 "Fragment Shader Prolog"))
7487 radeon_llvm_dispose(&ctx
.radeon_bld
);
7492 * Compile the pixel shader epilog. This handles everything that must be
7493 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7495 static bool si_compile_ps_epilog(struct si_screen
*sscreen
,
7496 LLVMTargetMachineRef tm
,
7497 struct pipe_debug_callback
*debug
,
7498 struct si_shader_part
*out
)
7500 union si_shader_part_key
*key
= &out
->key
;
7501 struct si_shader shader
= {};
7502 struct si_shader_context ctx
;
7503 struct gallivm_state
*gallivm
= &ctx
.radeon_bld
.gallivm
;
7504 struct lp_build_tgsi_context
*bld_base
= &ctx
.radeon_bld
.soa
.bld_base
;
7505 LLVMTypeRef params
[16+8*4+3];
7506 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7507 int last_sgpr
, num_params
, i
;
7509 struct si_ps_exports exp
= {};
7511 si_init_shader_ctx(&ctx
, sscreen
, &shader
, tm
);
7512 ctx
.type
= PIPE_SHADER_FRAGMENT
;
7513 shader
.key
.ps
.epilog
= key
->ps_epilog
.states
;
7515 /* Declare input SGPRs. */
7516 params
[SI_PARAM_RW_BUFFERS
] = ctx
.i64
;
7517 params
[SI_PARAM_CONST_BUFFERS
] = ctx
.i64
;
7518 params
[SI_PARAM_SAMPLERS
] = ctx
.i64
;
7519 params
[SI_PARAM_IMAGES
] = ctx
.i64
;
7520 params
[SI_PARAM_SHADER_BUFFERS
] = ctx
.i64
;
7521 params
[SI_PARAM_ALPHA_REF
] = ctx
.f32
;
7522 last_sgpr
= SI_PARAM_ALPHA_REF
;
7524 /* Declare input VGPRs. */
7525 num_params
= (last_sgpr
+ 1) +
7526 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7527 key
->ps_epilog
.writes_z
+
7528 key
->ps_epilog
.writes_stencil
+
7529 key
->ps_epilog
.writes_samplemask
;
7531 num_params
= MAX2(num_params
,
7532 last_sgpr
+ 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7534 assert(num_params
<= ARRAY_SIZE(params
));
7536 for (i
= last_sgpr
+ 1; i
< num_params
; i
++)
7537 params
[i
] = ctx
.f32
;
7539 /* Create the function. */
7540 si_create_function(&ctx
, NULL
, 0, params
, num_params
, last_sgpr
);
7541 /* Disable elimination of unused inputs. */
7542 radeon_llvm_add_attribute(ctx
.radeon_bld
.main_fn
,
7543 "InitialPSInputAddr", 0xffffff);
7545 /* Process colors. */
7546 unsigned vgpr
= last_sgpr
+ 1;
7547 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7548 int last_color_export
= -1;
7550 /* Find the last color export. */
7551 if (!key
->ps_epilog
.writes_z
&&
7552 !key
->ps_epilog
.writes_stencil
&&
7553 !key
->ps_epilog
.writes_samplemask
) {
7554 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7556 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7557 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7558 /* Just set this if any of the colorbuffers are enabled. */
7560 ((1llu << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7561 last_color_export
= 0;
7563 for (i
= 0; i
< 8; i
++)
7564 if (colors_written
& (1 << i
) &&
7565 (spi_format
>> (i
* 4)) & 0xf)
7566 last_color_export
= i
;
7570 while (colors_written
) {
7571 LLVMValueRef color
[4];
7572 int mrt
= u_bit_scan(&colors_written
);
7574 for (i
= 0; i
< 4; i
++)
7575 color
[i
] = LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7577 si_export_mrt_color(bld_base
, color
, mrt
,
7579 mrt
== last_color_export
, &exp
);
7582 /* Process depth, stencil, samplemask. */
7583 if (key
->ps_epilog
.writes_z
)
7584 depth
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7585 if (key
->ps_epilog
.writes_stencil
)
7586 stencil
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7587 if (key
->ps_epilog
.writes_samplemask
)
7588 samplemask
= LLVMGetParam(ctx
.radeon_bld
.main_fn
, vgpr
++);
7590 if (depth
|| stencil
|| samplemask
)
7591 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7592 else if (last_color_export
== -1)
7593 si_export_null(bld_base
);
7596 si_emit_ps_exports(&ctx
, &exp
);
7599 LLVMBuildRetVoid(gallivm
->builder
);
7600 radeon_llvm_finalize_module(&ctx
.radeon_bld
);
7602 if (si_compile_llvm(sscreen
, &out
->binary
, &out
->config
, tm
,
7603 gallivm
->module
, debug
, ctx
.type
,
7604 "Fragment Shader Epilog"))
7607 radeon_llvm_dispose(&ctx
.radeon_bld
);
7612 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7614 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7615 LLVMTargetMachineRef tm
,
7616 struct si_shader
*shader
,
7617 struct pipe_debug_callback
*debug
)
7619 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
7620 union si_shader_part_key prolog_key
;
7621 union si_shader_part_key epilog_key
;
7624 /* Get the prolog. */
7625 memset(&prolog_key
, 0, sizeof(prolog_key
));
7626 prolog_key
.ps_prolog
.states
= shader
->key
.ps
.prolog
;
7627 prolog_key
.ps_prolog
.colors_read
= info
->colors_read
;
7628 prolog_key
.ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
7629 prolog_key
.ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
7630 prolog_key
.ps_prolog
.wqm
= info
->uses_derivatives
&&
7631 (prolog_key
.ps_prolog
.colors_read
||
7632 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7633 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7634 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7635 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7636 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7637 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
);
7639 if (info
->colors_read
) {
7640 unsigned *color
= shader
->selector
->color_attr_index
;
7642 if (shader
->key
.ps
.prolog
.color_two_side
) {
7643 /* BCOLORs are stored after the last input. */
7644 prolog_key
.ps_prolog
.num_interp_inputs
= info
->num_inputs
;
7645 prolog_key
.ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
7646 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
7649 for (i
= 0; i
< 2; i
++) {
7650 unsigned interp
= info
->input_interpolate
[color
[i
]];
7651 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
7653 if (!(info
->colors_read
& (0xf << i
*4)))
7656 prolog_key
.ps_prolog
.color_attr_index
[i
] = color
[i
];
7658 if (shader
->key
.ps
.prolog
.flatshade_colors
&&
7659 interp
== TGSI_INTERPOLATE_COLOR
)
7660 interp
= TGSI_INTERPOLATE_CONSTANT
;
7663 case TGSI_INTERPOLATE_CONSTANT
:
7664 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = -1;
7666 case TGSI_INTERPOLATE_PERSPECTIVE
:
7667 case TGSI_INTERPOLATE_COLOR
:
7668 /* Force the interpolation location for colors here. */
7669 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
)
7670 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7671 if (shader
->key
.ps
.prolog
.force_persp_center_interp
)
7672 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7675 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7676 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 0;
7677 shader
->config
.spi_ps_input_ena
|=
7678 S_0286CC_PERSP_SAMPLE_ENA(1);
7680 case TGSI_INTERPOLATE_LOC_CENTER
:
7681 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 2;
7682 shader
->config
.spi_ps_input_ena
|=
7683 S_0286CC_PERSP_CENTER_ENA(1);
7685 case TGSI_INTERPOLATE_LOC_CENTROID
:
7686 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 4;
7687 shader
->config
.spi_ps_input_ena
|=
7688 S_0286CC_PERSP_CENTROID_ENA(1);
7694 case TGSI_INTERPOLATE_LINEAR
:
7695 /* Force the interpolation location for colors here. */
7696 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
)
7697 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
7698 if (shader
->key
.ps
.prolog
.force_linear_center_interp
)
7699 location
= TGSI_INTERPOLATE_LOC_CENTER
;
7702 case TGSI_INTERPOLATE_LOC_SAMPLE
:
7703 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 6;
7704 shader
->config
.spi_ps_input_ena
|=
7705 S_0286CC_LINEAR_SAMPLE_ENA(1);
7707 case TGSI_INTERPOLATE_LOC_CENTER
:
7708 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 8;
7709 shader
->config
.spi_ps_input_ena
|=
7710 S_0286CC_LINEAR_CENTER_ENA(1);
7712 case TGSI_INTERPOLATE_LOC_CENTROID
:
7713 prolog_key
.ps_prolog
.color_interp_vgpr_index
[i
] = 10;
7714 shader
->config
.spi_ps_input_ena
|=
7715 S_0286CC_LINEAR_CENTROID_ENA(1);
7727 /* The prolog is a no-op if these aren't set. */
7728 if (prolog_key
.ps_prolog
.colors_read
||
7729 prolog_key
.ps_prolog
.states
.force_persp_sample_interp
||
7730 prolog_key
.ps_prolog
.states
.force_linear_sample_interp
||
7731 prolog_key
.ps_prolog
.states
.force_persp_center_interp
||
7732 prolog_key
.ps_prolog
.states
.force_linear_center_interp
||
7733 prolog_key
.ps_prolog
.states
.bc_optimize_for_persp
||
7734 prolog_key
.ps_prolog
.states
.bc_optimize_for_linear
||
7735 prolog_key
.ps_prolog
.states
.poly_stipple
) {
7737 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7738 &prolog_key
, tm
, debug
,
7739 si_compile_ps_prolog
);
7740 if (!shader
->prolog
)
7744 /* Get the epilog. */
7745 memset(&epilog_key
, 0, sizeof(epilog_key
));
7746 epilog_key
.ps_epilog
.colors_written
= info
->colors_written
;
7747 epilog_key
.ps_epilog
.writes_z
= info
->writes_z
;
7748 epilog_key
.ps_epilog
.writes_stencil
= info
->writes_stencil
;
7749 epilog_key
.ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
7750 epilog_key
.ps_epilog
.states
= shader
->key
.ps
.epilog
;
7753 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7754 &epilog_key
, tm
, debug
,
7755 si_compile_ps_epilog
);
7756 if (!shader
->epilog
)
7759 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7760 if (shader
->key
.ps
.prolog
.poly_stipple
) {
7761 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7762 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7765 /* Set up the enable bits for per-sample shading if needed. */
7766 if (shader
->key
.ps
.prolog
.force_persp_sample_interp
&&
7767 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7768 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7769 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7770 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7771 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7773 if (shader
->key
.ps
.prolog
.force_linear_sample_interp
&&
7774 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7775 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7776 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7777 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7778 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7780 if (shader
->key
.ps
.prolog
.force_persp_center_interp
&&
7781 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7782 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7783 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7784 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7785 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7787 if (shader
->key
.ps
.prolog
.force_linear_center_interp
&&
7788 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7789 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7790 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7791 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7792 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7795 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7796 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7797 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7798 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7799 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7802 /* At least one pair of interpolation weights must be enabled. */
7803 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7804 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7805 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7808 /* The sample mask input is always enabled, because the API shader always
7809 * passes it through to the epilog. Disable it here if it's unused.
7811 if (!shader
->key
.ps
.epilog
.poly_line_smoothing
&&
7812 !shader
->selector
->info
.reads_samplemask
)
7813 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
7818 static void si_fix_num_sgprs(struct si_shader
*shader
)
7820 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
7822 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
7825 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
7826 struct si_shader
*shader
,
7827 struct pipe_debug_callback
*debug
)
7829 struct si_shader
*mainp
= shader
->selector
->main_shader_part
;
7832 /* LS, ES, VS are compiled on demand if the main part hasn't been
7833 * compiled for that stage.
7836 (shader
->selector
->type
== PIPE_SHADER_VERTEX
&&
7837 (shader
->key
.vs
.as_es
!= mainp
->key
.vs
.as_es
||
7838 shader
->key
.vs
.as_ls
!= mainp
->key
.vs
.as_ls
)) ||
7839 (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
&&
7840 shader
->key
.tes
.as_es
!= mainp
->key
.tes
.as_es
) ||
7841 (shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
&&
7842 shader
->key
.tcs
.epilog
.inputs_to_copy
) ||
7843 shader
->selector
->type
== PIPE_SHADER_COMPUTE
) {
7844 /* Monolithic shader (compiled as a whole, has many variants,
7845 * may take a long time to compile).
7847 r
= si_compile_tgsi_shader(sscreen
, tm
, shader
, true, debug
);
7851 /* The shader consists of 2-3 parts:
7853 * - the middle part is the user shader, it has 1 variant only
7854 * and it was compiled during the creation of the shader
7856 * - the prolog part is inserted at the beginning
7857 * - the epilog part is inserted at the end
7859 * The prolog and epilog have many (but simple) variants.
7862 /* Copy the compiled TGSI shader data over. */
7863 shader
->is_binary_shared
= true;
7864 shader
->binary
= mainp
->binary
;
7865 shader
->config
= mainp
->config
;
7866 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
7867 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
7868 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
7869 memcpy(shader
->info
.vs_output_param_offset
,
7870 mainp
->info
.vs_output_param_offset
,
7871 sizeof(mainp
->info
.vs_output_param_offset
));
7872 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
7873 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
7874 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
7876 /* Select prologs and/or epilogs. */
7877 switch (shader
->selector
->type
) {
7878 case PIPE_SHADER_VERTEX
:
7879 if (!si_shader_select_vs_parts(sscreen
, tm
, shader
, debug
))
7882 case PIPE_SHADER_TESS_CTRL
:
7883 if (!si_shader_select_tcs_parts(sscreen
, tm
, shader
, debug
))
7886 case PIPE_SHADER_TESS_EVAL
:
7887 if (!si_shader_select_tes_parts(sscreen
, tm
, shader
, debug
))
7890 case PIPE_SHADER_FRAGMENT
:
7891 if (!si_shader_select_ps_parts(sscreen
, tm
, shader
, debug
))
7894 /* Make sure we have at least as many VGPRs as there
7895 * are allocated inputs.
7897 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7898 shader
->info
.num_input_vgprs
);
7902 /* Update SGPR and VGPR counts. */
7903 if (shader
->prolog
) {
7904 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7905 shader
->prolog
->config
.num_sgprs
);
7906 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7907 shader
->prolog
->config
.num_vgprs
);
7909 if (shader
->epilog
) {
7910 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
7911 shader
->epilog
->config
.num_sgprs
);
7912 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
7913 shader
->epilog
->config
.num_vgprs
);
7917 si_fix_num_sgprs(shader
);
7918 si_shader_dump(sscreen
, shader
, debug
, shader
->selector
->info
.processor
,
7922 r
= si_shader_binary_upload(sscreen
, shader
);
7924 fprintf(stderr
, "LLVM failed to upload shader\n");
7931 void si_shader_destroy(struct si_shader
*shader
)
7933 if (shader
->gs_copy_shader
) {
7934 si_shader_destroy(shader
->gs_copy_shader
);
7935 FREE(shader
->gs_copy_shader
);
7938 if (shader
->scratch_bo
)
7939 r600_resource_reference(&shader
->scratch_bo
, NULL
);
7941 r600_resource_reference(&shader
->bo
, NULL
);
7943 if (!shader
->is_binary_shared
)
7944 radeon_shader_binary_clean(&shader
->binary
);
7946 free(shader
->shader_log
);