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radeonsi: determine DB_SHADER_CONTROL outside of shader compilation
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 if (type == TGSI_TYPE_DOUBLE) {
598 LLVMValueRef value2;
599 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
600 lp_build_const_int32(gallivm, swizzle + 1));
601 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
602 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
603 }
604
605 return LLVMBuildBitCast(gallivm->builder, value,
606 tgsi2llvmtype(bld_base, type), "");
607 }
608
609 /**
610 * Store to LDS.
611 *
612 * \param swizzle offset (typically 0..3)
613 * \param dw_addr address in dwords
614 * \param value value to store
615 */
616 static void lds_store(struct lp_build_tgsi_context * bld_base,
617 unsigned swizzle, LLVMValueRef dw_addr,
618 LLVMValueRef value)
619 {
620 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
621 struct gallivm_state *gallivm = bld_base->base.gallivm;
622
623 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
624 lp_build_const_int32(gallivm, swizzle));
625
626 value = LLVMBuildBitCast(gallivm->builder, value,
627 LLVMInt32TypeInContext(gallivm->context), "");
628 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
629 dw_addr, value);
630 }
631
632 static LLVMValueRef fetch_input_tcs(
633 struct lp_build_tgsi_context *bld_base,
634 const struct tgsi_full_src_register *reg,
635 enum tgsi_opcode_type type, unsigned swizzle)
636 {
637 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
638 LLVMValueRef dw_addr, stride;
639
640 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
641 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
642 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
643
644 return lds_load(bld_base, type, swizzle, dw_addr);
645 }
646
647 static LLVMValueRef fetch_output_tcs(
648 struct lp_build_tgsi_context *bld_base,
649 const struct tgsi_full_src_register *reg,
650 enum tgsi_opcode_type type, unsigned swizzle)
651 {
652 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
653 LLVMValueRef dw_addr, stride;
654
655 if (reg->Register.Dimension) {
656 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
657 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
658 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
659 } else {
660 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
661 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
662 }
663
664 return lds_load(bld_base, type, swizzle, dw_addr);
665 }
666
667 static LLVMValueRef fetch_input_tes(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 if (reg->Register.Dimension) {
676 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
677 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
678 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
679 } else {
680 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
681 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
682 }
683
684 return lds_load(bld_base, type, swizzle, dw_addr);
685 }
686
687 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
688 const struct tgsi_full_instruction * inst,
689 const struct tgsi_opcode_info * info,
690 LLVMValueRef dst[4])
691 {
692 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
693 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
694 unsigned chan_index;
695 LLVMValueRef dw_addr, stride;
696
697 /* Only handle per-patch and per-vertex outputs here.
698 * Vectors will be lowered to scalars and this function will be called again.
699 */
700 if (reg->Register.File != TGSI_FILE_OUTPUT ||
701 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
702 radeon_llvm_emit_store(bld_base, inst, info, dst);
703 return;
704 }
705
706 if (reg->Register.Dimension) {
707 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
708 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
709 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
710 } else {
711 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
712 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
713 }
714
715 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
716 LLVMValueRef value = dst[chan_index];
717
718 if (inst->Instruction.Saturate)
719 value = radeon_llvm_saturate(bld_base, value);
720
721 lds_store(bld_base, chan_index, dw_addr, value);
722 }
723 }
724
725 static LLVMValueRef fetch_input_gs(
726 struct lp_build_tgsi_context *bld_base,
727 const struct tgsi_full_src_register *reg,
728 enum tgsi_opcode_type type,
729 unsigned swizzle)
730 {
731 struct lp_build_context *base = &bld_base->base;
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct si_shader *shader = si_shader_ctx->shader;
734 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
735 struct gallivm_state *gallivm = base->gallivm;
736 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
737 LLVMValueRef vtx_offset;
738 LLVMValueRef args[9];
739 unsigned vtx_offset_param;
740 struct tgsi_shader_info *info = &shader->selector->info;
741 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
742 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
743 unsigned param;
744 LLVMValueRef value;
745
746 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
747 return get_primitive_id(bld_base, swizzle);
748
749 if (!reg->Register.Dimension)
750 return NULL;
751
752 if (swizzle == ~0) {
753 LLVMValueRef values[TGSI_NUM_CHANNELS];
754 unsigned chan;
755 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
756 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
757 }
758 return lp_build_gather_values(bld_base->base.gallivm, values,
759 TGSI_NUM_CHANNELS);
760 }
761
762 /* Get the vertex offset parameter */
763 vtx_offset_param = reg->Dimension.Index;
764 if (vtx_offset_param < 2) {
765 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
766 } else {
767 assert(vtx_offset_param < 6);
768 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
769 }
770 vtx_offset = lp_build_mul_imm(uint,
771 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
772 vtx_offset_param),
773 4);
774
775 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
776 args[0] = si_shader_ctx->esgs_ring;
777 args[1] = vtx_offset;
778 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
779 args[3] = uint->zero;
780 args[4] = uint->one; /* OFFEN */
781 args[5] = uint->zero; /* IDXEN */
782 args[6] = uint->one; /* GLC */
783 args[7] = uint->zero; /* SLC */
784 args[8] = uint->zero; /* TFE */
785
786 value = lp_build_intrinsic(gallivm->builder,
787 "llvm.SI.buffer.load.dword.i32.i32",
788 i32, args, 9,
789 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
790 if (type == TGSI_TYPE_DOUBLE) {
791 LLVMValueRef value2;
792 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
793 value2 = lp_build_intrinsic(gallivm->builder,
794 "llvm.SI.buffer.load.dword.i32.i32",
795 i32, args, 9,
796 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
797 return radeon_llvm_emit_fetch_double(bld_base,
798 value, value2);
799 }
800 return LLVMBuildBitCast(gallivm->builder,
801 value,
802 tgsi2llvmtype(bld_base, type), "");
803 }
804
805 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
806 {
807 switch (interpolate) {
808 case TGSI_INTERPOLATE_CONSTANT:
809 return 0;
810
811 case TGSI_INTERPOLATE_LINEAR:
812 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
813 return SI_PARAM_LINEAR_SAMPLE;
814 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
815 return SI_PARAM_LINEAR_CENTROID;
816 else
817 return SI_PARAM_LINEAR_CENTER;
818 break;
819 case TGSI_INTERPOLATE_COLOR:
820 case TGSI_INTERPOLATE_PERSPECTIVE:
821 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
822 return SI_PARAM_PERSP_SAMPLE;
823 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
824 return SI_PARAM_PERSP_CENTROID;
825 else
826 return SI_PARAM_PERSP_CENTER;
827 break;
828 default:
829 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
830 return -1;
831 }
832 }
833
834 /* This shouldn't be used by explicit INTERP opcodes. */
835 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
836 unsigned param)
837 {
838 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
839 unsigned sample_param = 0;
840 LLVMValueRef default_ij, sample_ij, force_sample;
841
842 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
843
844 /* If the shader doesn't use center/centroid, just return the parameter.
845 *
846 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
847 * switch between center/centroid and sample without shader changes.
848 */
849 switch (param) {
850 case SI_PARAM_PERSP_CENTROID:
851 case SI_PARAM_PERSP_CENTER:
852 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
853 return default_ij;
854
855 sample_param = SI_PARAM_PERSP_SAMPLE;
856 break;
857
858 case SI_PARAM_LINEAR_CENTROID:
859 case SI_PARAM_LINEAR_CENTER:
860 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
861 return default_ij;
862
863 sample_param = SI_PARAM_LINEAR_SAMPLE;
864 break;
865
866 default:
867 return default_ij;
868 }
869
870 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
871 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
872
873 /* TODO: this can be done more efficiently by switching between
874 * 2 prologs.
875 */
876 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
877 SI_PARAM_PS_STATE_BITS);
878 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
879 LLVMInt1TypeInContext(gallivm->context), "");
880 return LLVMBuildSelect(gallivm->builder, force_sample,
881 sample_ij, default_ij, "");
882 }
883
884 static void declare_input_fs(
885 struct radeon_llvm_context *radeon_bld,
886 unsigned input_index,
887 const struct tgsi_full_declaration *decl)
888 {
889 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
890 struct si_shader_context *si_shader_ctx =
891 si_shader_context(&radeon_bld->soa.bld_base);
892 struct si_shader *shader = si_shader_ctx->shader;
893 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
894 struct gallivm_state *gallivm = base->gallivm;
895 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
896 LLVMValueRef main_fn = radeon_bld->main_fn;
897
898 LLVMValueRef interp_param = NULL;
899 int interp_param_idx;
900 const char * intr_name;
901
902 /* This value is:
903 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
904 * quad begins a new primitive. Bit 0 always needs
905 * to be unset)
906 * [32:16] ParamOffset
907 *
908 */
909 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
910 LLVMValueRef attr_number;
911
912 unsigned chan;
913
914 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
915 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
916 unsigned soa_index =
917 radeon_llvm_reg_index_soa(input_index, chan);
918 radeon_bld->inputs[soa_index] =
919 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
920
921 if (chan == 3)
922 /* RCP for fragcoord.w */
923 radeon_bld->inputs[soa_index] =
924 LLVMBuildFDiv(gallivm->builder,
925 lp_build_const_float(gallivm, 1.0f),
926 radeon_bld->inputs[soa_index],
927 "");
928 }
929 return;
930 }
931
932 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
933 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
934 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
935 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
936 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
937 lp_build_const_float(gallivm, 0.0f);
938 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
939 lp_build_const_float(gallivm, 1.0f);
940
941 return;
942 }
943
944 shader->ps_input_param_offset[input_index] = shader->nparam++;
945 attr_number = lp_build_const_int32(gallivm,
946 shader->ps_input_param_offset[input_index]);
947
948 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
949 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
950 decl->Interp.Location);
951 if (interp_param_idx == -1)
952 return;
953 else if (interp_param_idx)
954 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
955
956 /* fs.constant returns the param from the middle vertex, so it's not
957 * really useful for flat shading. It's meant to be used for custom
958 * interpolation (but the intrinsic can't fetch from the other two
959 * vertices).
960 *
961 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
962 * to do the right thing. The only reason we use fs.constant is that
963 * fs.interp cannot be used on integers, because they can be equal
964 * to NaN.
965 */
966 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
967
968 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
969 si_shader_ctx->shader->key.ps.color_two_side) {
970 LLVMValueRef args[4];
971 LLVMValueRef face, is_face_positive;
972 LLVMValueRef back_attr_number =
973 lp_build_const_int32(gallivm,
974 shader->ps_input_param_offset[input_index] + 1);
975
976 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
977
978 is_face_positive = LLVMBuildFCmp(gallivm->builder,
979 LLVMRealOGT, face,
980 lp_build_const_float(gallivm, 0.0f),
981 "");
982
983 args[2] = params;
984 args[3] = interp_param;
985 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
986 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
987 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
988 LLVMValueRef front, back;
989
990 args[0] = llvm_chan;
991 args[1] = attr_number;
992 front = lp_build_intrinsic(gallivm->builder, intr_name,
993 input_type, args, args[3] ? 4 : 3,
994 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
995
996 args[1] = back_attr_number;
997 back = lp_build_intrinsic(gallivm->builder, intr_name,
998 input_type, args, args[3] ? 4 : 3,
999 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1000
1001 radeon_bld->inputs[soa_index] =
1002 LLVMBuildSelect(gallivm->builder,
1003 is_face_positive,
1004 front,
1005 back,
1006 "");
1007 }
1008
1009 shader->nparam++;
1010 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1011 LLVMValueRef args[4];
1012
1013 args[0] = uint->zero;
1014 args[1] = attr_number;
1015 args[2] = params;
1016 args[3] = interp_param;
1017 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1018 lp_build_intrinsic(gallivm->builder, intr_name,
1019 input_type, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1022 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1023 lp_build_const_float(gallivm, 0.0f);
1024 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1025 lp_build_const_float(gallivm, 1.0f);
1026 } else {
1027 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1028 LLVMValueRef args[4];
1029 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1030 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1031 args[0] = llvm_chan;
1032 args[1] = attr_number;
1033 args[2] = params;
1034 args[3] = interp_param;
1035 radeon_bld->inputs[soa_index] =
1036 lp_build_intrinsic(gallivm->builder, intr_name,
1037 input_type, args, args[3] ? 4 : 3,
1038 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1039 }
1040 }
1041 }
1042
1043 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1044 {
1045 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1046 SI_PARAM_ANCILLARY, 8, 4);
1047 }
1048
1049 /**
1050 * Load a dword from a constant buffer.
1051 */
1052 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1053 LLVMValueRef offset, LLVMTypeRef return_type)
1054 {
1055 LLVMValueRef args[2] = {resource, offset};
1056
1057 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1058 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1059 }
1060
1061 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1062 {
1063 struct si_shader_context *si_shader_ctx =
1064 si_shader_context(&radeon_bld->soa.bld_base);
1065 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1066 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1067 LLVMBuilderRef builder = gallivm->builder;
1068 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1069 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1070 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1071
1072 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1073 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1074 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1075
1076 LLVMValueRef pos[4] = {
1077 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1078 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1079 lp_build_const_float(gallivm, 0),
1080 lp_build_const_float(gallivm, 0)
1081 };
1082
1083 return lp_build_gather_values(gallivm, pos, 4);
1084 }
1085
1086 static void declare_system_value(
1087 struct radeon_llvm_context * radeon_bld,
1088 unsigned index,
1089 const struct tgsi_full_declaration *decl)
1090 {
1091 struct si_shader_context *si_shader_ctx =
1092 si_shader_context(&radeon_bld->soa.bld_base);
1093 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1094 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1095 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1096 LLVMValueRef value = 0;
1097
1098 switch (decl->Semantic.Name) {
1099 case TGSI_SEMANTIC_INSTANCEID:
1100 value = LLVMGetParam(radeon_bld->main_fn,
1101 si_shader_ctx->param_instance_id);
1102 break;
1103
1104 case TGSI_SEMANTIC_VERTEXID:
1105 value = LLVMBuildAdd(gallivm->builder,
1106 LLVMGetParam(radeon_bld->main_fn,
1107 si_shader_ctx->param_vertex_id),
1108 LLVMGetParam(radeon_bld->main_fn,
1109 SI_PARAM_BASE_VERTEX), "");
1110 break;
1111
1112 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1113 value = LLVMGetParam(radeon_bld->main_fn,
1114 si_shader_ctx->param_vertex_id);
1115 break;
1116
1117 case TGSI_SEMANTIC_BASEVERTEX:
1118 value = LLVMGetParam(radeon_bld->main_fn,
1119 SI_PARAM_BASE_VERTEX);
1120 break;
1121
1122 case TGSI_SEMANTIC_INVOCATIONID:
1123 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1124 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1125 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1126 value = LLVMGetParam(radeon_bld->main_fn,
1127 SI_PARAM_GS_INSTANCE_ID);
1128 else
1129 assert(!"INVOCATIONID not implemented");
1130 break;
1131
1132 case TGSI_SEMANTIC_SAMPLEID:
1133 value = get_sample_id(radeon_bld);
1134 break;
1135
1136 case TGSI_SEMANTIC_SAMPLEPOS:
1137 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1138 break;
1139
1140 case TGSI_SEMANTIC_SAMPLEMASK:
1141 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1142 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1143 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1144 value = uint_bld->one;
1145 else
1146 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1147 break;
1148
1149 case TGSI_SEMANTIC_TESSCOORD:
1150 {
1151 LLVMValueRef coord[4] = {
1152 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1153 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1154 bld->zero,
1155 bld->zero
1156 };
1157
1158 /* For triangles, the vector should be (u, v, 1-u-v). */
1159 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1160 PIPE_PRIM_TRIANGLES)
1161 coord[2] = lp_build_sub(bld, bld->one,
1162 lp_build_add(bld, coord[0], coord[1]));
1163
1164 value = lp_build_gather_values(gallivm, coord, 4);
1165 break;
1166 }
1167
1168 case TGSI_SEMANTIC_VERTICESIN:
1169 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1170 break;
1171
1172 case TGSI_SEMANTIC_TESSINNER:
1173 case TGSI_SEMANTIC_TESSOUTER:
1174 {
1175 LLVMValueRef dw_addr;
1176 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1177
1178 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1179 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1180 lp_build_const_int32(gallivm, param * 4), "");
1181
1182 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1183 ~0, dw_addr);
1184 break;
1185 }
1186
1187 case TGSI_SEMANTIC_PRIMID:
1188 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1189 break;
1190
1191 default:
1192 assert(!"unknown system value");
1193 return;
1194 }
1195
1196 radeon_bld->system_values[index] = value;
1197 }
1198
1199 static LLVMValueRef fetch_constant(
1200 struct lp_build_tgsi_context * bld_base,
1201 const struct tgsi_full_src_register *reg,
1202 enum tgsi_opcode_type type,
1203 unsigned swizzle)
1204 {
1205 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1206 struct lp_build_context * base = &bld_base->base;
1207 const struct tgsi_ind_register *ireg = &reg->Indirect;
1208 unsigned buf, idx;
1209
1210 LLVMValueRef addr, bufp;
1211 LLVMValueRef result;
1212
1213 if (swizzle == LP_CHAN_ALL) {
1214 unsigned chan;
1215 LLVMValueRef values[4];
1216 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1217 values[chan] = fetch_constant(bld_base, reg, type, chan);
1218
1219 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1220 }
1221
1222 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1223 idx = reg->Register.Index * 4 + swizzle;
1224
1225 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1226 if (type != TGSI_TYPE_DOUBLE)
1227 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1228 else {
1229 return radeon_llvm_emit_fetch_double(bld_base,
1230 si_shader_ctx->constants[buf][idx],
1231 si_shader_ctx->constants[buf][idx + 1]);
1232 }
1233 }
1234
1235 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1236 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1237 LLVMValueRef index;
1238 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1239 reg->Dimension.Index);
1240 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1241 } else
1242 bufp = si_shader_ctx->const_buffers[buf];
1243
1244 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1245 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1246 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1247 addr = lp_build_add(&bld_base->uint_bld, addr,
1248 lp_build_const_int32(base->gallivm, idx * 4));
1249
1250 result = buffer_load_const(base->gallivm->builder, bufp,
1251 addr, bld_base->base.elem_type);
1252
1253 if (type != TGSI_TYPE_DOUBLE)
1254 result = bitcast(bld_base, type, result);
1255 else {
1256 LLVMValueRef addr2, result2;
1257 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1258 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1259 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1260 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1261 lp_build_const_int32(base->gallivm, idx * 4));
1262
1263 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1264 addr2, bld_base->base.elem_type);
1265
1266 result = radeon_llvm_emit_fetch_double(bld_base,
1267 result, result2);
1268 }
1269 return result;
1270 }
1271
1272 /* Initialize arguments for the shader export intrinsic */
1273 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1274 LLVMValueRef *values,
1275 unsigned target,
1276 LLVMValueRef *args)
1277 {
1278 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1279 struct lp_build_context *uint =
1280 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1281 struct lp_build_context *base = &bld_base->base;
1282 unsigned compressed = 0;
1283 unsigned chan;
1284
1285 /* XXX: This controls which components of the output
1286 * registers actually get exported. (e.g bit 0 means export
1287 * X component, bit 1 means export Y component, etc.) I'm
1288 * hard coding this to 0xf for now. In the future, we might
1289 * want to do something else.
1290 */
1291 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1292
1293 /* Specify whether the EXEC mask represents the valid mask */
1294 args[1] = uint->zero;
1295
1296 /* Specify whether this is the last export */
1297 args[2] = uint->zero;
1298
1299 /* Specify the target we are exporting */
1300 args[3] = lp_build_const_int32(base->gallivm, target);
1301
1302 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1303 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1304
1305 if (cbuf >= 0 && cbuf < 8) {
1306 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1307
1308 if (compressed)
1309 si_shader_ctx->shader->spi_shader_col_format |=
1310 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1311 else
1312 si_shader_ctx->shader->spi_shader_col_format |=
1313 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1314
1315 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1316 }
1317 }
1318
1319 /* Set COMPR flag */
1320 args[4] = compressed ? uint->one : uint->zero;
1321
1322 if (compressed) {
1323 /* Pixel shader needs to pack output values before export */
1324 for (chan = 0; chan < 2; chan++) {
1325 LLVMValueRef pack_args[2] = {
1326 values[2 * chan],
1327 values[2 * chan + 1]
1328 };
1329 LLVMValueRef packed;
1330
1331 packed = lp_build_intrinsic(base->gallivm->builder,
1332 "llvm.SI.packf16",
1333 LLVMInt32TypeInContext(base->gallivm->context),
1334 pack_args, 2,
1335 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1336 args[chan + 7] = args[chan + 5] =
1337 LLVMBuildBitCast(base->gallivm->builder,
1338 packed,
1339 LLVMFloatTypeInContext(base->gallivm->context),
1340 "");
1341 }
1342 } else
1343 memcpy(&args[5], values, sizeof(values[0]) * 4);
1344 }
1345
1346 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1347 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1348 LLVMValueRef *out_ptr,
1349 unsigned target,
1350 LLVMValueRef *args)
1351 {
1352 struct gallivm_state *gallivm = bld_base->base.gallivm;
1353 LLVMValueRef values[4];
1354 int i;
1355
1356 for (i = 0; i < 4; i++)
1357 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1358
1359 si_llvm_init_export_args(bld_base, values, target, args);
1360 }
1361
1362 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1363 LLVMValueRef alpha_ptr)
1364 {
1365 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1366 struct gallivm_state *gallivm = bld_base->base.gallivm;
1367
1368 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1369 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1370 SI_PARAM_ALPHA_REF);
1371
1372 LLVMValueRef alpha_pass =
1373 lp_build_cmp(&bld_base->base,
1374 si_shader_ctx->shader->key.ps.alpha_func,
1375 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1376 alpha_ref);
1377 LLVMValueRef arg =
1378 lp_build_select(&bld_base->base,
1379 alpha_pass,
1380 lp_build_const_float(gallivm, 1.0f),
1381 lp_build_const_float(gallivm, -1.0f));
1382
1383 lp_build_intrinsic(gallivm->builder,
1384 "llvm.AMDGPU.kill",
1385 LLVMVoidTypeInContext(gallivm->context),
1386 &arg, 1, 0);
1387 } else {
1388 lp_build_intrinsic(gallivm->builder,
1389 "llvm.AMDGPU.kilp",
1390 LLVMVoidTypeInContext(gallivm->context),
1391 NULL, 0, 0);
1392 }
1393 }
1394
1395 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1396 LLVMValueRef alpha_ptr)
1397 {
1398 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1399 struct gallivm_state *gallivm = bld_base->base.gallivm;
1400 LLVMValueRef coverage, alpha;
1401
1402 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1403 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1404 SI_PARAM_SAMPLE_COVERAGE);
1405 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1406
1407 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1408 bld_base->int_bld.elem_type,
1409 &coverage, 1, LLVMReadNoneAttribute);
1410
1411 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1412 bld_base->base.elem_type, "");
1413
1414 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1415 lp_build_const_float(gallivm,
1416 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1417
1418 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1419 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1420 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1421 }
1422
1423 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1424 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1425 {
1426 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1427 struct lp_build_context *base = &bld_base->base;
1428 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1429 unsigned reg_index;
1430 unsigned chan;
1431 unsigned const_chan;
1432 LLVMValueRef base_elt;
1433 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1434 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1435 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1436
1437 for (reg_index = 0; reg_index < 2; reg_index ++) {
1438 LLVMValueRef *args = pos[2 + reg_index];
1439
1440 args[5] =
1441 args[6] =
1442 args[7] =
1443 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1444
1445 /* Compute dot products of position and user clip plane vectors */
1446 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1447 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1448 args[1] = lp_build_const_int32(base->gallivm,
1449 ((reg_index * 4 + chan) * 4 +
1450 const_chan) * 4);
1451 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1452 args[1], base->elem_type);
1453 args[5 + chan] =
1454 lp_build_add(base, args[5 + chan],
1455 lp_build_mul(base, base_elt,
1456 out_elts[const_chan]));
1457 }
1458 }
1459
1460 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1461 args[1] = uint->zero;
1462 args[2] = uint->zero;
1463 args[3] = lp_build_const_int32(base->gallivm,
1464 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1465 args[4] = uint->zero;
1466 }
1467 }
1468
1469 static void si_dump_streamout(struct pipe_stream_output_info *so)
1470 {
1471 unsigned i;
1472
1473 if (so->num_outputs)
1474 fprintf(stderr, "STREAMOUT\n");
1475
1476 for (i = 0; i < so->num_outputs; i++) {
1477 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1478 so->output[i].start_component;
1479 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1480 i, so->output[i].output_buffer,
1481 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1482 so->output[i].register_index,
1483 mask & 1 ? "x" : "",
1484 mask & 2 ? "y" : "",
1485 mask & 4 ? "z" : "",
1486 mask & 8 ? "w" : "");
1487 }
1488 }
1489
1490 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1491 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1492 * or v4i32 (num_channels=3,4). */
1493 static void build_tbuffer_store(struct si_shader_context *shader,
1494 LLVMValueRef rsrc,
1495 LLVMValueRef vdata,
1496 unsigned num_channels,
1497 LLVMValueRef vaddr,
1498 LLVMValueRef soffset,
1499 unsigned inst_offset,
1500 unsigned dfmt,
1501 unsigned nfmt,
1502 unsigned offen,
1503 unsigned idxen,
1504 unsigned glc,
1505 unsigned slc,
1506 unsigned tfe)
1507 {
1508 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1509 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1510 LLVMValueRef args[] = {
1511 rsrc,
1512 vdata,
1513 LLVMConstInt(i32, num_channels, 0),
1514 vaddr,
1515 soffset,
1516 LLVMConstInt(i32, inst_offset, 0),
1517 LLVMConstInt(i32, dfmt, 0),
1518 LLVMConstInt(i32, nfmt, 0),
1519 LLVMConstInt(i32, offen, 0),
1520 LLVMConstInt(i32, idxen, 0),
1521 LLVMConstInt(i32, glc, 0),
1522 LLVMConstInt(i32, slc, 0),
1523 LLVMConstInt(i32, tfe, 0)
1524 };
1525
1526 /* The instruction offset field has 12 bits */
1527 assert(offen || inst_offset < (1 << 12));
1528
1529 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1530 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1531 const char *types[] = {"i32", "v2i32", "v4i32"};
1532 char name[256];
1533 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1534
1535 lp_build_intrinsic(gallivm->builder, name,
1536 LLVMVoidTypeInContext(gallivm->context),
1537 args, Elements(args), 0);
1538 }
1539
1540 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1541 LLVMValueRef rsrc,
1542 LLVMValueRef vdata,
1543 unsigned num_channels,
1544 LLVMValueRef vaddr,
1545 LLVMValueRef soffset,
1546 unsigned inst_offset)
1547 {
1548 static unsigned dfmt[] = {
1549 V_008F0C_BUF_DATA_FORMAT_32,
1550 V_008F0C_BUF_DATA_FORMAT_32_32,
1551 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1552 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1553 };
1554 assert(num_channels >= 1 && num_channels <= 4);
1555
1556 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1557 inst_offset, dfmt[num_channels-1],
1558 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1559 }
1560
1561 /* On SI, the vertex shader is responsible for writing streamout data
1562 * to buffers. */
1563 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1564 struct si_shader_output_values *outputs,
1565 unsigned noutput)
1566 {
1567 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1568 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1569 LLVMBuilderRef builder = gallivm->builder;
1570 int i, j;
1571 struct lp_build_if_state if_ctx;
1572
1573 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1574
1575 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1576 LLVMValueRef so_vtx_count =
1577 unpack_param(shader, shader->param_streamout_config, 16, 7);
1578
1579 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1580 NULL, 0, LLVMReadNoneAttribute);
1581
1582 /* can_emit = tid < so_vtx_count; */
1583 LLVMValueRef can_emit =
1584 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1585
1586 LLVMValueRef stream_id =
1587 unpack_param(shader, shader->param_streamout_config, 24, 2);
1588
1589 /* Emit the streamout code conditionally. This actually avoids
1590 * out-of-bounds buffer access. The hw tells us via the SGPR
1591 * (so_vtx_count) which threads are allowed to emit streamout data. */
1592 lp_build_if(&if_ctx, gallivm, can_emit);
1593 {
1594 /* The buffer offset is computed as follows:
1595 * ByteOffset = streamout_offset[buffer_id]*4 +
1596 * (streamout_write_index + thread_id)*stride[buffer_id] +
1597 * attrib_offset
1598 */
1599
1600 LLVMValueRef so_write_index =
1601 LLVMGetParam(shader->radeon_bld.main_fn,
1602 shader->param_streamout_write_index);
1603
1604 /* Compute (streamout_write_index + thread_id). */
1605 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1606
1607 /* Compute the write offset for each enabled buffer. */
1608 LLVMValueRef so_write_offset[4] = {};
1609 for (i = 0; i < 4; i++) {
1610 if (!so->stride[i])
1611 continue;
1612
1613 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1614 shader->param_streamout_offset[i]);
1615 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1616
1617 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1618 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1619 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1620 }
1621
1622 /* Write streamout data. */
1623 for (i = 0; i < so->num_outputs; i++) {
1624 unsigned buf_idx = so->output[i].output_buffer;
1625 unsigned reg = so->output[i].register_index;
1626 unsigned start = so->output[i].start_component;
1627 unsigned num_comps = so->output[i].num_components;
1628 unsigned stream = so->output[i].stream;
1629 LLVMValueRef out[4];
1630 struct lp_build_if_state if_ctx_stream;
1631
1632 assert(num_comps && num_comps <= 4);
1633 if (!num_comps || num_comps > 4)
1634 continue;
1635
1636 if (reg >= noutput)
1637 continue;
1638
1639 /* Load the output as int. */
1640 for (j = 0; j < num_comps; j++) {
1641 out[j] = LLVMBuildBitCast(builder,
1642 outputs[reg].values[start+j],
1643 i32, "");
1644 }
1645
1646 /* Pack the output. */
1647 LLVMValueRef vdata = NULL;
1648
1649 switch (num_comps) {
1650 case 1: /* as i32 */
1651 vdata = out[0];
1652 break;
1653 case 2: /* as v2i32 */
1654 case 3: /* as v4i32 (aligned to 4) */
1655 case 4: /* as v4i32 */
1656 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1657 for (j = 0; j < num_comps; j++) {
1658 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1659 LLVMConstInt(i32, j, 0), "");
1660 }
1661 break;
1662 }
1663
1664 LLVMValueRef can_emit_stream =
1665 LLVMBuildICmp(builder, LLVMIntEQ,
1666 stream_id,
1667 lp_build_const_int32(gallivm, stream), "");
1668
1669 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1670 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1671 vdata, num_comps,
1672 so_write_offset[buf_idx],
1673 LLVMConstInt(i32, 0, 0),
1674 so->output[i].dst_offset*4);
1675 lp_build_endif(&if_ctx_stream);
1676 }
1677 }
1678 lp_build_endif(&if_ctx);
1679 }
1680
1681
1682 /* Generate export instructions for hardware VS shader stage */
1683 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1684 struct si_shader_output_values *outputs,
1685 unsigned noutput)
1686 {
1687 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1688 struct si_shader * shader = si_shader_ctx->shader;
1689 struct lp_build_context * base = &bld_base->base;
1690 struct lp_build_context * uint =
1691 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1692 LLVMValueRef args[9];
1693 LLVMValueRef pos_args[4][9] = { { 0 } };
1694 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1695 unsigned semantic_name, semantic_index;
1696 unsigned target;
1697 unsigned param_count = 0;
1698 unsigned pos_idx;
1699 int i;
1700
1701 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1702 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1703 }
1704
1705 for (i = 0; i < noutput; i++) {
1706 semantic_name = outputs[i].name;
1707 semantic_index = outputs[i].sid;
1708
1709 handle_semantic:
1710 /* Select the correct target */
1711 switch(semantic_name) {
1712 case TGSI_SEMANTIC_PSIZE:
1713 psize_value = outputs[i].values[0];
1714 continue;
1715 case TGSI_SEMANTIC_EDGEFLAG:
1716 edgeflag_value = outputs[i].values[0];
1717 continue;
1718 case TGSI_SEMANTIC_LAYER:
1719 layer_value = outputs[i].values[0];
1720 semantic_name = TGSI_SEMANTIC_GENERIC;
1721 goto handle_semantic;
1722 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1723 viewport_index_value = outputs[i].values[0];
1724 semantic_name = TGSI_SEMANTIC_GENERIC;
1725 goto handle_semantic;
1726 case TGSI_SEMANTIC_POSITION:
1727 target = V_008DFC_SQ_EXP_POS;
1728 break;
1729 case TGSI_SEMANTIC_COLOR:
1730 case TGSI_SEMANTIC_BCOLOR:
1731 target = V_008DFC_SQ_EXP_PARAM + param_count;
1732 shader->vs_output_param_offset[i] = param_count;
1733 param_count++;
1734 break;
1735 case TGSI_SEMANTIC_CLIPDIST:
1736 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1737 break;
1738 case TGSI_SEMANTIC_CLIPVERTEX:
1739 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1740 continue;
1741 case TGSI_SEMANTIC_PRIMID:
1742 case TGSI_SEMANTIC_FOG:
1743 case TGSI_SEMANTIC_TEXCOORD:
1744 case TGSI_SEMANTIC_GENERIC:
1745 target = V_008DFC_SQ_EXP_PARAM + param_count;
1746 shader->vs_output_param_offset[i] = param_count;
1747 param_count++;
1748 break;
1749 default:
1750 target = 0;
1751 fprintf(stderr,
1752 "Warning: SI unhandled vs output type:%d\n",
1753 semantic_name);
1754 }
1755
1756 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1757
1758 if (target >= V_008DFC_SQ_EXP_POS &&
1759 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1760 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1761 args, sizeof(args));
1762 } else {
1763 lp_build_intrinsic(base->gallivm->builder,
1764 "llvm.SI.export",
1765 LLVMVoidTypeInContext(base->gallivm->context),
1766 args, 9, 0);
1767 }
1768
1769 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1770 semantic_name = TGSI_SEMANTIC_GENERIC;
1771 goto handle_semantic;
1772 }
1773 }
1774
1775 shader->nr_param_exports = param_count;
1776
1777 /* We need to add the position output manually if it's missing. */
1778 if (!pos_args[0][0]) {
1779 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1780 pos_args[0][1] = uint->zero; /* EXEC mask */
1781 pos_args[0][2] = uint->zero; /* last export? */
1782 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1783 pos_args[0][4] = uint->zero; /* COMPR flag */
1784 pos_args[0][5] = base->zero; /* X */
1785 pos_args[0][6] = base->zero; /* Y */
1786 pos_args[0][7] = base->zero; /* Z */
1787 pos_args[0][8] = base->one; /* W */
1788 }
1789
1790 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1791 if (shader->selector->info.writes_psize ||
1792 shader->selector->info.writes_edgeflag ||
1793 shader->selector->info.writes_viewport_index ||
1794 shader->selector->info.writes_layer) {
1795 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1796 shader->selector->info.writes_psize |
1797 (shader->selector->info.writes_edgeflag << 1) |
1798 (shader->selector->info.writes_layer << 2) |
1799 (shader->selector->info.writes_viewport_index << 3));
1800 pos_args[1][1] = uint->zero; /* EXEC mask */
1801 pos_args[1][2] = uint->zero; /* last export? */
1802 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1803 pos_args[1][4] = uint->zero; /* COMPR flag */
1804 pos_args[1][5] = base->zero; /* X */
1805 pos_args[1][6] = base->zero; /* Y */
1806 pos_args[1][7] = base->zero; /* Z */
1807 pos_args[1][8] = base->zero; /* W */
1808
1809 if (shader->selector->info.writes_psize)
1810 pos_args[1][5] = psize_value;
1811
1812 if (shader->selector->info.writes_edgeflag) {
1813 /* The output is a float, but the hw expects an integer
1814 * with the first bit containing the edge flag. */
1815 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1816 edgeflag_value,
1817 bld_base->uint_bld.elem_type, "");
1818 edgeflag_value = lp_build_min(&bld_base->int_bld,
1819 edgeflag_value,
1820 bld_base->int_bld.one);
1821
1822 /* The LLVM intrinsic expects a float. */
1823 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1824 edgeflag_value,
1825 base->elem_type, "");
1826 }
1827
1828 if (shader->selector->info.writes_layer)
1829 pos_args[1][7] = layer_value;
1830
1831 if (shader->selector->info.writes_viewport_index)
1832 pos_args[1][8] = viewport_index_value;
1833 }
1834
1835 for (i = 0; i < 4; i++)
1836 if (pos_args[i][0])
1837 shader->nr_pos_exports++;
1838
1839 pos_idx = 0;
1840 for (i = 0; i < 4; i++) {
1841 if (!pos_args[i][0])
1842 continue;
1843
1844 /* Specify the target we are exporting */
1845 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1846
1847 if (pos_idx == shader->nr_pos_exports)
1848 /* Specify that this is the last export */
1849 pos_args[i][2] = uint->one;
1850
1851 lp_build_intrinsic(base->gallivm->builder,
1852 "llvm.SI.export",
1853 LLVMVoidTypeInContext(base->gallivm->context),
1854 pos_args[i], 9, 0);
1855 }
1856 }
1857
1858 /* This only writes the tessellation factor levels. */
1859 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1860 {
1861 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1862 struct gallivm_state *gallivm = bld_base->base.gallivm;
1863 struct si_shader *shader = si_shader_ctx->shader;
1864 unsigned tess_inner_index, tess_outer_index;
1865 LLVMValueRef lds_base, lds_inner, lds_outer;
1866 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1867 LLVMValueRef out[6], vec0, vec1, invocation_id;
1868 unsigned stride, outer_comps, inner_comps, i;
1869 struct lp_build_if_state if_ctx;
1870
1871 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1872
1873 /* Do this only for invocation 0, because the tess levels are per-patch,
1874 * not per-vertex.
1875 *
1876 * This can't jump, because invocation 0 executes this. It should
1877 * at least mask out the loads and stores for other invocations.
1878 */
1879 lp_build_if(&if_ctx, gallivm,
1880 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1881 invocation_id, bld_base->uint_bld.zero, ""));
1882
1883 /* Determine the layout of one tess factor element in the buffer. */
1884 switch (shader->key.tcs.prim_mode) {
1885 case PIPE_PRIM_LINES:
1886 stride = 2; /* 2 dwords, 1 vec2 store */
1887 outer_comps = 2;
1888 inner_comps = 0;
1889 break;
1890 case PIPE_PRIM_TRIANGLES:
1891 stride = 4; /* 4 dwords, 1 vec4 store */
1892 outer_comps = 3;
1893 inner_comps = 1;
1894 break;
1895 case PIPE_PRIM_QUADS:
1896 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1897 outer_comps = 4;
1898 inner_comps = 2;
1899 break;
1900 default:
1901 assert(0);
1902 return;
1903 }
1904
1905 /* Load tess_inner and tess_outer from LDS.
1906 * Any invocation can write them, so we can't get them from a temporary.
1907 */
1908 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1909 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1910
1911 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1912 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1913 lp_build_const_int32(gallivm,
1914 tess_inner_index * 4), "");
1915 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1916 lp_build_const_int32(gallivm,
1917 tess_outer_index * 4), "");
1918
1919 for (i = 0; i < outer_comps; i++)
1920 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1921 for (i = 0; i < inner_comps; i++)
1922 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1923
1924 /* Convert the outputs to vectors for stores. */
1925 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1926 vec1 = NULL;
1927
1928 if (stride > 4)
1929 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1930
1931 /* Get the buffer. */
1932 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1933 SI_PARAM_RW_BUFFERS);
1934 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1935 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1936
1937 /* Get the offset. */
1938 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1939 SI_PARAM_TESS_FACTOR_OFFSET);
1940 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1941 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1942 lp_build_const_int32(gallivm, 4 * stride), "");
1943
1944 /* Store the outputs. */
1945 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1946 MIN2(stride, 4), byteoffset, tf_base, 0);
1947 if (vec1)
1948 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1949 stride - 4, byteoffset, tf_base, 16);
1950 lp_build_endif(&if_ctx);
1951 }
1952
1953 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1954 {
1955 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1956 struct si_shader *shader = si_shader_ctx->shader;
1957 struct tgsi_shader_info *info = &shader->selector->info;
1958 struct gallivm_state *gallivm = bld_base->base.gallivm;
1959 unsigned i, chan;
1960 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1961 si_shader_ctx->param_rel_auto_id);
1962 LLVMValueRef vertex_dw_stride =
1963 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1964 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1965 vertex_dw_stride, "");
1966
1967 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1968 * its inputs from it. */
1969 for (i = 0; i < info->num_outputs; i++) {
1970 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1971 unsigned name = info->output_semantic_name[i];
1972 unsigned index = info->output_semantic_index[i];
1973 int param = si_shader_io_get_unique_index(name, index);
1974 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1975 lp_build_const_int32(gallivm, param * 4), "");
1976
1977 for (chan = 0; chan < 4; chan++) {
1978 lds_store(bld_base, chan, dw_addr,
1979 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1980 }
1981 }
1982 }
1983
1984 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1985 {
1986 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1987 struct gallivm_state *gallivm = bld_base->base.gallivm;
1988 struct si_shader *es = si_shader_ctx->shader;
1989 struct tgsi_shader_info *info = &es->selector->info;
1990 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1991 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1992 si_shader_ctx->param_es2gs_offset);
1993 unsigned chan;
1994 int i;
1995
1996 for (i = 0; i < info->num_outputs; i++) {
1997 LLVMValueRef *out_ptr =
1998 si_shader_ctx->radeon_bld.soa.outputs[i];
1999 int param_index;
2000
2001 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2002 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2003 continue;
2004
2005 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2006 info->output_semantic_index[i]);
2007
2008 for (chan = 0; chan < 4; chan++) {
2009 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2010 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2011
2012 build_tbuffer_store(si_shader_ctx,
2013 si_shader_ctx->esgs_ring,
2014 out_val, 1,
2015 LLVMGetUndef(i32), soffset,
2016 (4 * param_index + chan) * 4,
2017 V_008F0C_BUF_DATA_FORMAT_32,
2018 V_008F0C_BUF_NUM_FORMAT_UINT,
2019 0, 0, 1, 1, 0);
2020 }
2021 }
2022 }
2023
2024 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2025 {
2026 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2027 struct gallivm_state *gallivm = bld_base->base.gallivm;
2028 LLVMValueRef args[2];
2029
2030 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2031 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2032 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2033 LLVMVoidTypeInContext(gallivm->context), args, 2,
2034 LLVMNoUnwindAttribute);
2035 }
2036
2037 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2038 {
2039 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2040 struct gallivm_state *gallivm = bld_base->base.gallivm;
2041 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2042 struct si_shader_output_values *outputs = NULL;
2043 int i,j;
2044
2045 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2046
2047 /* Vertex color clamping.
2048 *
2049 * This uses a state constant loaded in a user data SGPR and
2050 * an IF statement is added that clamps all colors if the constant
2051 * is true.
2052 */
2053 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2054 !si_shader_ctx->shader->is_gs_copy_shader) {
2055 struct lp_build_if_state if_ctx;
2056 LLVMValueRef cond = NULL;
2057 LLVMValueRef addr, val;
2058
2059 for (i = 0; i < info->num_outputs; i++) {
2060 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2061 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2062 continue;
2063
2064 /* We've found a color. */
2065 if (!cond) {
2066 /* The state is in the first bit of the user SGPR. */
2067 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2068 SI_PARAM_VS_STATE_BITS);
2069 cond = LLVMBuildTrunc(gallivm->builder, cond,
2070 LLVMInt1TypeInContext(gallivm->context), "");
2071 lp_build_if(&if_ctx, gallivm, cond);
2072 }
2073
2074 for (j = 0; j < 4; j++) {
2075 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2076 val = LLVMBuildLoad(gallivm->builder, addr, "");
2077 val = radeon_llvm_saturate(bld_base, val);
2078 LLVMBuildStore(gallivm->builder, val, addr);
2079 }
2080 }
2081
2082 if (cond)
2083 lp_build_endif(&if_ctx);
2084 }
2085
2086 for (i = 0; i < info->num_outputs; i++) {
2087 outputs[i].name = info->output_semantic_name[i];
2088 outputs[i].sid = info->output_semantic_index[i];
2089
2090 for (j = 0; j < 4; j++)
2091 outputs[i].values[j] =
2092 LLVMBuildLoad(gallivm->builder,
2093 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2094 "");
2095 }
2096
2097 /* Export PrimitiveID when PS needs it. */
2098 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2099 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2100 outputs[i].sid = 0;
2101 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 get_primitive_id(bld_base, 0));
2103 outputs[i].values[1] = bld_base->base.undef;
2104 outputs[i].values[2] = bld_base->base.undef;
2105 outputs[i].values[3] = bld_base->base.undef;
2106 i++;
2107 }
2108
2109 si_llvm_export_vs(bld_base, outputs, i);
2110 FREE(outputs);
2111 }
2112
2113 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2114 {
2115 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2116 struct si_shader * shader = si_shader_ctx->shader;
2117 struct lp_build_context * base = &bld_base->base;
2118 struct lp_build_context * uint = &bld_base->uint_bld;
2119 struct tgsi_shader_info *info = &shader->selector->info;
2120 LLVMBuilderRef builder = base->gallivm->builder;
2121 LLVMValueRef args[9];
2122 LLVMValueRef last_args[9] = { 0 };
2123 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2124 int i;
2125
2126 for (i = 0; i < info->num_outputs; i++) {
2127 unsigned semantic_name = info->output_semantic_name[i];
2128 unsigned semantic_index = info->output_semantic_index[i];
2129 unsigned target;
2130 LLVMValueRef alpha_ptr;
2131
2132 /* Select the correct target */
2133 switch (semantic_name) {
2134 case TGSI_SEMANTIC_POSITION:
2135 depth_index = i;
2136 continue;
2137 case TGSI_SEMANTIC_STENCIL:
2138 stencil_index = i;
2139 continue;
2140 case TGSI_SEMANTIC_SAMPLEMASK:
2141 samplemask_index = i;
2142 continue;
2143 case TGSI_SEMANTIC_COLOR:
2144 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2145 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2146
2147 if (si_shader_ctx->shader->key.ps.clamp_color) {
2148 for (int j = 0; j < 4; j++) {
2149 LLVMValueRef ptr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2150 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2151
2152 result = radeon_llvm_saturate(bld_base, result);
2153 LLVMBuildStore(builder, result, ptr);
2154 }
2155 }
2156
2157 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2158 LLVMBuildStore(base->gallivm->builder,
2159 base->one, alpha_ptr);
2160
2161 if (semantic_index == 0 &&
2162 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2163 si_alpha_test(bld_base, alpha_ptr);
2164
2165 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2166 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2167
2168 break;
2169 default:
2170 target = 0;
2171 fprintf(stderr,
2172 "Warning: SI unhandled fs output type:%d\n",
2173 semantic_name);
2174 }
2175
2176 si_llvm_init_export_args_load(bld_base,
2177 si_shader_ctx->radeon_bld.soa.outputs[i],
2178 target, args);
2179
2180 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2181 /* If there is an export instruction waiting to be emitted, do so now. */
2182 if (last_args[0]) {
2183 lp_build_intrinsic(base->gallivm->builder,
2184 "llvm.SI.export",
2185 LLVMVoidTypeInContext(base->gallivm->context),
2186 last_args, 9, 0);
2187 }
2188
2189 /* This instruction will be emitted at the end of the shader. */
2190 memcpy(last_args, args, sizeof(args));
2191
2192 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2193 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2194 semantic_index == 0 &&
2195 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2196 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2197 si_llvm_init_export_args_load(bld_base,
2198 si_shader_ctx->radeon_bld.soa.outputs[i],
2199 V_008DFC_SQ_EXP_MRT + c, args);
2200 lp_build_intrinsic(base->gallivm->builder,
2201 "llvm.SI.export",
2202 LLVMVoidTypeInContext(base->gallivm->context),
2203 args, 9, 0);
2204 }
2205 }
2206 } else {
2207 lp_build_intrinsic(base->gallivm->builder,
2208 "llvm.SI.export",
2209 LLVMVoidTypeInContext(base->gallivm->context),
2210 args, 9, 0);
2211 }
2212 }
2213
2214 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2215 LLVMValueRef out_ptr;
2216 unsigned mask = 0;
2217
2218 /* Specify the target we are exporting */
2219 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2220
2221 args[5] = base->zero; /* R, depth */
2222 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2223 args[7] = base->zero; /* B, sample mask */
2224 args[8] = base->zero; /* A, alpha to mask */
2225
2226 if (depth_index >= 0) {
2227 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2228 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2229 mask |= 0x1;
2230 }
2231
2232 if (stencil_index >= 0) {
2233 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2234 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2235 mask |= 0x2;
2236 }
2237
2238 if (samplemask_index >= 0) {
2239 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2240 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2241 mask |= 0x4;
2242 }
2243
2244 /* SI (except OLAND) has a bug that it only looks
2245 * at the X writemask component. */
2246 if (si_shader_ctx->screen->b.chip_class == SI &&
2247 si_shader_ctx->screen->b.family != CHIP_OLAND)
2248 mask |= 0x1;
2249
2250 if (samplemask_index >= 0)
2251 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2252 else if (stencil_index >= 0)
2253 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2254 else
2255 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2256
2257 /* Specify which components to enable */
2258 args[0] = lp_build_const_int32(base->gallivm, mask);
2259
2260 args[1] =
2261 args[2] =
2262 args[4] = uint->zero;
2263
2264 if (last_args[0])
2265 lp_build_intrinsic(base->gallivm->builder,
2266 "llvm.SI.export",
2267 LLVMVoidTypeInContext(base->gallivm->context),
2268 args, 9, 0);
2269 else
2270 memcpy(last_args, args, sizeof(args));
2271 }
2272
2273 if (!last_args[0]) {
2274 /* Specify which components to enable */
2275 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2276
2277 /* Specify the target we are exporting */
2278 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2279
2280 /* Set COMPR flag to zero to export data as 32-bit */
2281 last_args[4] = uint->zero;
2282
2283 /* dummy bits */
2284 last_args[5]= uint->zero;
2285 last_args[6]= uint->zero;
2286 last_args[7]= uint->zero;
2287 last_args[8]= uint->zero;
2288 }
2289
2290 /* Specify whether the EXEC mask represents the valid mask */
2291 last_args[1] = uint->one;
2292
2293 /* Specify that this is the last export */
2294 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2295
2296 lp_build_intrinsic(base->gallivm->builder,
2297 "llvm.SI.export",
2298 LLVMVoidTypeInContext(base->gallivm->context),
2299 last_args, 9, 0);
2300 }
2301
2302 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2303 struct lp_build_tgsi_context * bld_base,
2304 struct lp_build_emit_data * emit_data);
2305
2306 static bool tgsi_is_array_sampler(unsigned target)
2307 {
2308 return target == TGSI_TEXTURE_1D_ARRAY ||
2309 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2310 target == TGSI_TEXTURE_2D_ARRAY ||
2311 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2312 target == TGSI_TEXTURE_CUBE_ARRAY ||
2313 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2314 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2315 }
2316
2317 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2318 struct lp_build_emit_data *emit_data,
2319 unsigned opcode, unsigned target,
2320 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2321 LLVMValueRef *param, unsigned count,
2322 unsigned dmask)
2323 {
2324 unsigned num_args;
2325 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2326 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2327
2328 /* Pad to power of two vector */
2329 while (count < util_next_power_of_two(count))
2330 param[count++] = LLVMGetUndef(i32);
2331
2332 /* Texture coordinates. */
2333 if (count > 1)
2334 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2335 else
2336 emit_data->args[0] = param[0];
2337
2338 /* Resource. */
2339 emit_data->args[1] = res_ptr;
2340 num_args = 2;
2341
2342 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2343 emit_data->dst_type = LLVMVectorType(i32, 4);
2344 else {
2345 emit_data->dst_type = LLVMVectorType(
2346 LLVMFloatTypeInContext(gallivm->context), 4);
2347
2348 emit_data->args[num_args++] = samp_ptr;
2349 }
2350
2351 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2352 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2353 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2354 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2355 tgsi_is_array_sampler(target)); /* da */
2356 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2357 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2358 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2359 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2360
2361 emit_data->arg_count = num_args;
2362 }
2363
2364 static const struct lp_build_tgsi_action tex_action;
2365
2366 static void tex_fetch_ptrs(
2367 struct lp_build_tgsi_context * bld_base,
2368 struct lp_build_emit_data * emit_data,
2369 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2370 {
2371 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2372 struct gallivm_state *gallivm = bld_base->base.gallivm;
2373 const struct tgsi_full_instruction * inst = emit_data->inst;
2374 unsigned target = inst->Texture.Texture;
2375 unsigned sampler_src;
2376 unsigned sampler_index;
2377
2378 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2379 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2380
2381 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2382 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2383 LLVMValueRef ind_index;
2384
2385 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2386
2387 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2388 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2389
2390 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2391 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2392
2393 if (target == TGSI_TEXTURE_2D_MSAA ||
2394 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2395 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2396 lp_build_const_int32(gallivm,
2397 SI_FMASK_TEX_OFFSET), "");
2398 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2399 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2400 }
2401 } else {
2402 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2403 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2404 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2405 }
2406 }
2407
2408 static void tex_fetch_args(
2409 struct lp_build_tgsi_context * bld_base,
2410 struct lp_build_emit_data * emit_data)
2411 {
2412 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2413 struct gallivm_state *gallivm = bld_base->base.gallivm;
2414 LLVMBuilderRef builder = gallivm->builder;
2415 const struct tgsi_full_instruction * inst = emit_data->inst;
2416 unsigned opcode = inst->Instruction.Opcode;
2417 unsigned target = inst->Texture.Texture;
2418 LLVMValueRef coords[5], derivs[6];
2419 LLVMValueRef address[16];
2420 int ref_pos;
2421 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2422 unsigned count = 0;
2423 unsigned chan;
2424 unsigned num_deriv_channels = 0;
2425 bool has_offset = inst->Texture.NumOffsets > 0;
2426 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2427 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2428 unsigned dmask = 0xf;
2429
2430 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2431
2432 if (opcode == TGSI_OPCODE_TXQ) {
2433 if (target == TGSI_TEXTURE_BUFFER) {
2434 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2435
2436 /* Read the size from the buffer descriptor directly. */
2437 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2438 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2439 lp_build_const_int32(gallivm, 6), "");
2440
2441 if (si_shader_ctx->screen->b.chip_class >= VI) {
2442 /* On VI, the descriptor contains the size in bytes,
2443 * but TXQ must return the size in elements.
2444 * The stride is always non-zero for resources using TXQ.
2445 */
2446 LLVMValueRef stride =
2447 LLVMBuildExtractElement(builder, res,
2448 lp_build_const_int32(gallivm, 5), "");
2449 stride = LLVMBuildLShr(builder, stride,
2450 lp_build_const_int32(gallivm, 16), "");
2451 stride = LLVMBuildAnd(builder, stride,
2452 lp_build_const_int32(gallivm, 0x3FFF), "");
2453
2454 size = LLVMBuildUDiv(builder, size, stride, "");
2455 }
2456
2457 emit_data->args[0] = size;
2458 return;
2459 }
2460
2461 /* Textures - set the mip level. */
2462 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2463
2464 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2465 NULL, address, count, 0xf);
2466 return;
2467 }
2468
2469 if (target == TGSI_TEXTURE_BUFFER) {
2470 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2471 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2472 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2473 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2474
2475 /* Bitcast and truncate v8i32 to v16i8. */
2476 LLVMValueRef res = res_ptr;
2477 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2478 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2479 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2480
2481 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2482 emit_data->args[0] = res;
2483 emit_data->args[1] = bld_base->uint_bld.zero;
2484 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2485 emit_data->arg_count = 3;
2486 return;
2487 }
2488
2489 /* Fetch and project texture coordinates */
2490 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2491 for (chan = 0; chan < 3; chan++ ) {
2492 coords[chan] = lp_build_emit_fetch(bld_base,
2493 emit_data->inst, 0,
2494 chan);
2495 if (opcode == TGSI_OPCODE_TXP)
2496 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2497 TGSI_OPCODE_DIV,
2498 coords[chan],
2499 coords[3]);
2500 }
2501
2502 if (opcode == TGSI_OPCODE_TXP)
2503 coords[3] = bld_base->base.one;
2504
2505 /* Pack offsets. */
2506 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2507 /* The offsets are six-bit signed integers packed like this:
2508 * X=[5:0], Y=[13:8], and Z=[21:16].
2509 */
2510 LLVMValueRef offset[3], pack;
2511
2512 assert(inst->Texture.NumOffsets == 1);
2513
2514 for (chan = 0; chan < 3; chan++) {
2515 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2516 emit_data->inst, 0, chan);
2517 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2518 lp_build_const_int32(gallivm, 0x3f), "");
2519 if (chan)
2520 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2521 lp_build_const_int32(gallivm, chan*8), "");
2522 }
2523
2524 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2525 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2526 address[count++] = pack;
2527 }
2528
2529 /* Pack LOD bias value */
2530 if (opcode == TGSI_OPCODE_TXB)
2531 address[count++] = coords[3];
2532 if (opcode == TGSI_OPCODE_TXB2)
2533 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2534
2535 /* Pack depth comparison value */
2536 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2537 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2538 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2539 } else {
2540 assert(ref_pos >= 0);
2541 address[count++] = coords[ref_pos];
2542 }
2543 }
2544
2545 /* Pack user derivatives */
2546 if (opcode == TGSI_OPCODE_TXD) {
2547 int param, num_src_deriv_channels;
2548
2549 switch (target) {
2550 case TGSI_TEXTURE_3D:
2551 num_src_deriv_channels = 3;
2552 num_deriv_channels = 3;
2553 break;
2554 case TGSI_TEXTURE_2D:
2555 case TGSI_TEXTURE_SHADOW2D:
2556 case TGSI_TEXTURE_RECT:
2557 case TGSI_TEXTURE_SHADOWRECT:
2558 case TGSI_TEXTURE_2D_ARRAY:
2559 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2560 num_src_deriv_channels = 2;
2561 num_deriv_channels = 2;
2562 break;
2563 case TGSI_TEXTURE_CUBE:
2564 case TGSI_TEXTURE_SHADOWCUBE:
2565 case TGSI_TEXTURE_CUBE_ARRAY:
2566 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2567 /* Cube derivatives will be converted to 2D. */
2568 num_src_deriv_channels = 3;
2569 num_deriv_channels = 2;
2570 break;
2571 case TGSI_TEXTURE_1D:
2572 case TGSI_TEXTURE_SHADOW1D:
2573 case TGSI_TEXTURE_1D_ARRAY:
2574 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2575 num_src_deriv_channels = 1;
2576 num_deriv_channels = 1;
2577 break;
2578 default:
2579 unreachable("invalid target");
2580 }
2581
2582 for (param = 0; param < 2; param++)
2583 for (chan = 0; chan < num_src_deriv_channels; chan++)
2584 derivs[param * num_src_deriv_channels + chan] =
2585 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2586 }
2587
2588 if (target == TGSI_TEXTURE_CUBE ||
2589 target == TGSI_TEXTURE_CUBE_ARRAY ||
2590 target == TGSI_TEXTURE_SHADOWCUBE ||
2591 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2592 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2593
2594 if (opcode == TGSI_OPCODE_TXD)
2595 for (int i = 0; i < num_deriv_channels * 2; i++)
2596 address[count++] = derivs[i];
2597
2598 /* Pack texture coordinates */
2599 address[count++] = coords[0];
2600 if (num_coords > 1)
2601 address[count++] = coords[1];
2602 if (num_coords > 2)
2603 address[count++] = coords[2];
2604
2605 /* Pack LOD or sample index */
2606 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2607 address[count++] = coords[3];
2608 else if (opcode == TGSI_OPCODE_TXL2)
2609 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2610
2611 if (count > 16) {
2612 assert(!"Cannot handle more than 16 texture address parameters");
2613 count = 16;
2614 }
2615
2616 for (chan = 0; chan < count; chan++ ) {
2617 address[chan] = LLVMBuildBitCast(gallivm->builder,
2618 address[chan], i32, "");
2619 }
2620
2621 /* Adjust the sample index according to FMASK.
2622 *
2623 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2624 * which is the identity mapping. Each nibble says which physical sample
2625 * should be fetched to get that sample.
2626 *
2627 * For example, 0x11111100 means there are only 2 samples stored and
2628 * the second sample covers 3/4 of the pixel. When reading samples 0
2629 * and 1, return physical sample 0 (determined by the first two 0s
2630 * in FMASK), otherwise return physical sample 1.
2631 *
2632 * The sample index should be adjusted as follows:
2633 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2634 */
2635 if (target == TGSI_TEXTURE_2D_MSAA ||
2636 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2637 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2638 struct lp_build_emit_data txf_emit_data = *emit_data;
2639 LLVMValueRef txf_address[4];
2640 unsigned txf_count = count;
2641 struct tgsi_full_instruction inst = {};
2642
2643 memcpy(txf_address, address, sizeof(txf_address));
2644
2645 if (target == TGSI_TEXTURE_2D_MSAA) {
2646 txf_address[2] = bld_base->uint_bld.zero;
2647 }
2648 txf_address[3] = bld_base->uint_bld.zero;
2649
2650 /* Read FMASK using TXF. */
2651 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2652 inst.Texture.Texture = target;
2653 txf_emit_data.inst = &inst;
2654 txf_emit_data.chan = 0;
2655 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2656 target, fmask_ptr, NULL,
2657 txf_address, txf_count, 0xf);
2658 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2659
2660 /* Initialize some constants. */
2661 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2662 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2663
2664 /* Apply the formula. */
2665 LLVMValueRef fmask =
2666 LLVMBuildExtractElement(gallivm->builder,
2667 txf_emit_data.output[0],
2668 uint_bld->zero, "");
2669
2670 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2671
2672 LLVMValueRef sample_index4 =
2673 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2674
2675 LLVMValueRef shifted_fmask =
2676 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2677
2678 LLVMValueRef final_sample =
2679 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2680
2681 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2682 * resource descriptor is 0 (invalid),
2683 */
2684 LLVMValueRef fmask_desc =
2685 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2686 LLVMVectorType(uint_bld->elem_type, 8), "");
2687
2688 LLVMValueRef fmask_word1 =
2689 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2690 uint_bld->one, "");
2691
2692 LLVMValueRef word1_is_nonzero =
2693 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2694 fmask_word1, uint_bld->zero, "");
2695
2696 /* Replace the MSAA sample index. */
2697 address[sample_chan] =
2698 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2699 final_sample, address[sample_chan], "");
2700 }
2701
2702 if (opcode == TGSI_OPCODE_TXF) {
2703 /* add tex offsets */
2704 if (inst->Texture.NumOffsets) {
2705 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2706 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2707 const struct tgsi_texture_offset * off = inst->TexOffsets;
2708
2709 assert(inst->Texture.NumOffsets == 1);
2710
2711 switch (target) {
2712 case TGSI_TEXTURE_3D:
2713 address[2] = lp_build_add(uint_bld, address[2],
2714 bld->immediates[off->Index][off->SwizzleZ]);
2715 /* fall through */
2716 case TGSI_TEXTURE_2D:
2717 case TGSI_TEXTURE_SHADOW2D:
2718 case TGSI_TEXTURE_RECT:
2719 case TGSI_TEXTURE_SHADOWRECT:
2720 case TGSI_TEXTURE_2D_ARRAY:
2721 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2722 address[1] =
2723 lp_build_add(uint_bld, address[1],
2724 bld->immediates[off->Index][off->SwizzleY]);
2725 /* fall through */
2726 case TGSI_TEXTURE_1D:
2727 case TGSI_TEXTURE_SHADOW1D:
2728 case TGSI_TEXTURE_1D_ARRAY:
2729 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2730 address[0] =
2731 lp_build_add(uint_bld, address[0],
2732 bld->immediates[off->Index][off->SwizzleX]);
2733 break;
2734 /* texture offsets do not apply to other texture targets */
2735 }
2736 }
2737 }
2738
2739 if (opcode == TGSI_OPCODE_TG4) {
2740 unsigned gather_comp = 0;
2741
2742 /* DMASK was repurposed for GATHER4. 4 components are always
2743 * returned and DMASK works like a swizzle - it selects
2744 * the component to fetch. The only valid DMASK values are
2745 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2746 * (red,red,red,red) etc.) The ISA document doesn't mention
2747 * this.
2748 */
2749
2750 /* Get the component index from src1.x for Gather4. */
2751 if (!tgsi_is_shadow_target(target)) {
2752 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2753 LLVMValueRef comp_imm;
2754 struct tgsi_src_register src1 = inst->Src[1].Register;
2755
2756 assert(src1.File == TGSI_FILE_IMMEDIATE);
2757
2758 comp_imm = imms[src1.Index][src1.SwizzleX];
2759 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2760 gather_comp = CLAMP(gather_comp, 0, 3);
2761 }
2762
2763 dmask = 1 << gather_comp;
2764 }
2765
2766 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2767 samp_ptr, address, count, dmask);
2768 }
2769
2770 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2771 struct lp_build_tgsi_context * bld_base,
2772 struct lp_build_emit_data * emit_data)
2773 {
2774 struct lp_build_context * base = &bld_base->base;
2775 unsigned opcode = emit_data->inst->Instruction.Opcode;
2776 unsigned target = emit_data->inst->Texture.Texture;
2777 char intr_name[127];
2778 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2779 bool is_shadow = tgsi_is_shadow_target(target);
2780 char type[64];
2781 const char *name = "llvm.SI.image.sample";
2782 const char *infix = "";
2783
2784 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2785 /* Just return the buffer size. */
2786 emit_data->output[emit_data->chan] = emit_data->args[0];
2787 return;
2788 }
2789
2790 if (target == TGSI_TEXTURE_BUFFER) {
2791 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2792 base->gallivm->builder,
2793 "llvm.SI.vs.load.input", emit_data->dst_type,
2794 emit_data->args, emit_data->arg_count,
2795 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2796 return;
2797 }
2798
2799 switch (opcode) {
2800 case TGSI_OPCODE_TXF:
2801 name = target == TGSI_TEXTURE_2D_MSAA ||
2802 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2803 "llvm.SI.image.load" :
2804 "llvm.SI.image.load.mip";
2805 is_shadow = false;
2806 has_offset = false;
2807 break;
2808 case TGSI_OPCODE_TXQ:
2809 name = "llvm.SI.getresinfo";
2810 is_shadow = false;
2811 has_offset = false;
2812 break;
2813 case TGSI_OPCODE_LODQ:
2814 name = "llvm.SI.getlod";
2815 is_shadow = false;
2816 has_offset = false;
2817 break;
2818 case TGSI_OPCODE_TEX:
2819 case TGSI_OPCODE_TEX2:
2820 case TGSI_OPCODE_TXP:
2821 break;
2822 case TGSI_OPCODE_TXB:
2823 case TGSI_OPCODE_TXB2:
2824 infix = ".b";
2825 break;
2826 case TGSI_OPCODE_TXL:
2827 case TGSI_OPCODE_TXL2:
2828 infix = ".l";
2829 break;
2830 case TGSI_OPCODE_TXD:
2831 infix = ".d";
2832 break;
2833 case TGSI_OPCODE_TG4:
2834 name = "llvm.SI.gather4";
2835 break;
2836 default:
2837 assert(0);
2838 return;
2839 }
2840
2841 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2842 sprintf(type, ".v%ui32",
2843 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2844 else
2845 strcpy(type, ".i32");
2846
2847 /* Add the type and suffixes .c, .o if needed. */
2848 sprintf(intr_name, "%s%s%s%s%s",
2849 name, is_shadow ? ".c" : "", infix,
2850 has_offset ? ".o" : "", type);
2851
2852 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2853 base->gallivm->builder, intr_name, emit_data->dst_type,
2854 emit_data->args, emit_data->arg_count,
2855 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2856
2857 /* Divide the number of layers by 6 to get the number of cubes. */
2858 if (opcode == TGSI_OPCODE_TXQ &&
2859 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2860 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2861 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2862 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2863 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2864
2865 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2866 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2867 z = LLVMBuildSDiv(builder, z, six, "");
2868
2869 emit_data->output[emit_data->chan] =
2870 LLVMBuildInsertElement(builder, v4, z, two, "");
2871 }
2872 }
2873
2874 static void si_llvm_emit_txqs(
2875 const struct lp_build_tgsi_action * action,
2876 struct lp_build_tgsi_context * bld_base,
2877 struct lp_build_emit_data * emit_data)
2878 {
2879 struct gallivm_state *gallivm = bld_base->base.gallivm;
2880 LLVMBuilderRef builder = gallivm->builder;
2881 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2882 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2883 LLVMValueRef res, samples;
2884 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2885
2886 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2887
2888
2889 /* Read the samples from the descriptor directly. */
2890 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2891 samples = LLVMBuildExtractElement(
2892 builder, res,
2893 lp_build_const_int32(gallivm, 3), "");
2894 samples = LLVMBuildLShr(builder, samples,
2895 lp_build_const_int32(gallivm, 16), "");
2896 samples = LLVMBuildAnd(builder, samples,
2897 lp_build_const_int32(gallivm, 0xf), "");
2898 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2899 samples, "");
2900
2901 emit_data->output[emit_data->chan] = samples;
2902 }
2903
2904 /*
2905 * SI implements derivatives using the local data store (LDS)
2906 * All writes to the LDS happen in all executing threads at
2907 * the same time. TID is the Thread ID for the current
2908 * thread and is a value between 0 and 63, representing
2909 * the thread's position in the wavefront.
2910 *
2911 * For the pixel shader threads are grouped into quads of four pixels.
2912 * The TIDs of the pixels of a quad are:
2913 *
2914 * +------+------+
2915 * |4n + 0|4n + 1|
2916 * +------+------+
2917 * |4n + 2|4n + 3|
2918 * +------+------+
2919 *
2920 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2921 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2922 * the current pixel's column, and masking with 0xfffffffe yields the TID
2923 * of the left pixel of the current pixel's row.
2924 *
2925 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2926 * adding 2 yields the TID of the pixel below the top pixel.
2927 */
2928 /* masks for thread ID. */
2929 #define TID_MASK_TOP_LEFT 0xfffffffc
2930 #define TID_MASK_TOP 0xfffffffd
2931 #define TID_MASK_LEFT 0xfffffffe
2932
2933 static void si_llvm_emit_ddxy(
2934 const struct lp_build_tgsi_action * action,
2935 struct lp_build_tgsi_context * bld_base,
2936 struct lp_build_emit_data * emit_data)
2937 {
2938 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2939 struct gallivm_state *gallivm = bld_base->base.gallivm;
2940 struct lp_build_context * base = &bld_base->base;
2941 const struct tgsi_full_instruction *inst = emit_data->inst;
2942 unsigned opcode = inst->Instruction.Opcode;
2943 LLVMValueRef indices[2];
2944 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2945 LLVMValueRef tl, trbl, result[4];
2946 LLVMTypeRef i32;
2947 unsigned swizzle[4];
2948 unsigned c;
2949 int idx;
2950 unsigned mask;
2951
2952 i32 = LLVMInt32TypeInContext(gallivm->context);
2953
2954 indices[0] = bld_base->uint_bld.zero;
2955 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2956 NULL, 0, LLVMReadNoneAttribute);
2957 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2958 indices, 2, "");
2959
2960 if (opcode == TGSI_OPCODE_DDX_FINE)
2961 mask = TID_MASK_LEFT;
2962 else if (opcode == TGSI_OPCODE_DDY_FINE)
2963 mask = TID_MASK_TOP;
2964 else
2965 mask = TID_MASK_TOP_LEFT;
2966
2967 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2968 lp_build_const_int32(gallivm, mask), "");
2969 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2970 indices, 2, "");
2971
2972 /* for DDX we want to next X pixel, DDY next Y pixel. */
2973 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2974 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2975 lp_build_const_int32(gallivm, idx), "");
2976 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2977 indices, 2, "");
2978
2979 for (c = 0; c < 4; ++c) {
2980 unsigned i;
2981
2982 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2983 for (i = 0; i < c; ++i) {
2984 if (swizzle[i] == swizzle[c]) {
2985 result[c] = result[i];
2986 break;
2987 }
2988 }
2989 if (i != c)
2990 continue;
2991
2992 LLVMBuildStore(gallivm->builder,
2993 LLVMBuildBitCast(gallivm->builder,
2994 lp_build_emit_fetch(bld_base, inst, 0, c),
2995 i32, ""),
2996 store_ptr);
2997
2998 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2999 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3000
3001 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3002 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3003
3004 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3005 }
3006
3007 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3008 }
3009
3010 /*
3011 * this takes an I,J coordinate pair,
3012 * and works out the X and Y derivatives.
3013 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3014 */
3015 static LLVMValueRef si_llvm_emit_ddxy_interp(
3016 struct lp_build_tgsi_context *bld_base,
3017 LLVMValueRef interp_ij)
3018 {
3019 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3020 struct gallivm_state *gallivm = bld_base->base.gallivm;
3021 struct lp_build_context *base = &bld_base->base;
3022 LLVMValueRef indices[2];
3023 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3024 LLVMValueRef tl, tr, bl, result[4];
3025 LLVMTypeRef i32;
3026 unsigned c;
3027
3028 i32 = LLVMInt32TypeInContext(gallivm->context);
3029
3030 indices[0] = bld_base->uint_bld.zero;
3031 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3032 NULL, 0, LLVMReadNoneAttribute);
3033 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3034 indices, 2, "");
3035
3036 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3037 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3038
3039 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3040 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3041
3042 indices[1] = temp;
3043 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3044 indices, 2, "");
3045
3046 indices[1] = temp2;
3047 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3048 indices, 2, "");
3049
3050 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3051 lp_build_const_int32(gallivm, 1), "");
3052 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3053 indices, 2, "");
3054
3055 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3056 lp_build_const_int32(gallivm, 2), "");
3057 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3058 indices, 2, "");
3059
3060 for (c = 0; c < 2; ++c) {
3061 LLVMValueRef store_val;
3062 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3063
3064 store_val = LLVMBuildExtractElement(gallivm->builder,
3065 interp_ij, c_ll, "");
3066 LLVMBuildStore(gallivm->builder,
3067 store_val,
3068 store_ptr);
3069
3070 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3071 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3072
3073 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3074 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3075
3076 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3077
3078 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3079 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3080
3081 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3082 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3083
3084 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3085 }
3086
3087 return lp_build_gather_values(gallivm, result, 4);
3088 }
3089
3090 static void interp_fetch_args(
3091 struct lp_build_tgsi_context *bld_base,
3092 struct lp_build_emit_data *emit_data)
3093 {
3094 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3095 struct gallivm_state *gallivm = bld_base->base.gallivm;
3096 const struct tgsi_full_instruction *inst = emit_data->inst;
3097
3098 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3099 /* offset is in second src, first two channels */
3100 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3101 emit_data->inst, 1,
3102 0);
3103 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3104 emit_data->inst, 1,
3105 1);
3106 emit_data->arg_count = 2;
3107 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3108 LLVMValueRef sample_position;
3109 LLVMValueRef sample_id;
3110 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3111
3112 /* fetch sample ID, then fetch its sample position,
3113 * and place into first two channels.
3114 */
3115 sample_id = lp_build_emit_fetch(bld_base,
3116 emit_data->inst, 1, 0);
3117 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3118 LLVMInt32TypeInContext(gallivm->context),
3119 "");
3120 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3121
3122 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3123 sample_position,
3124 lp_build_const_int32(gallivm, 0), "");
3125
3126 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3127 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3128 sample_position,
3129 lp_build_const_int32(gallivm, 1), "");
3130 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3131 emit_data->arg_count = 2;
3132 }
3133 }
3134
3135 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3136 struct lp_build_tgsi_context *bld_base,
3137 struct lp_build_emit_data *emit_data)
3138 {
3139 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3140 struct si_shader *shader = si_shader_ctx->shader;
3141 struct gallivm_state *gallivm = bld_base->base.gallivm;
3142 LLVMValueRef interp_param;
3143 const struct tgsi_full_instruction *inst = emit_data->inst;
3144 const char *intr_name;
3145 int input_index;
3146 int chan;
3147 int i;
3148 LLVMValueRef attr_number;
3149 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3150 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3151 int interp_param_idx;
3152 unsigned location;
3153
3154 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3155 input_index = inst->Src[0].Register.Index;
3156
3157 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3158 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3159 location = TGSI_INTERPOLATE_LOC_CENTER;
3160 else
3161 location = TGSI_INTERPOLATE_LOC_CENTROID;
3162
3163 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3164 location);
3165 if (interp_param_idx == -1)
3166 return;
3167 else if (interp_param_idx)
3168 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3169 else
3170 interp_param = NULL;
3171
3172 attr_number = lp_build_const_int32(gallivm,
3173 shader->ps_input_param_offset[input_index]);
3174
3175 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3176 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3177 LLVMValueRef ij_out[2];
3178 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3179
3180 /*
3181 * take the I then J parameters, and the DDX/Y for it, and
3182 * calculate the IJ inputs for the interpolator.
3183 * temp1 = ddx * offset/sample.x + I;
3184 * interp_param.I = ddy * offset/sample.y + temp1;
3185 * temp1 = ddx * offset/sample.x + J;
3186 * interp_param.J = ddy * offset/sample.y + temp1;
3187 */
3188 for (i = 0; i < 2; i++) {
3189 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3190 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3191 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3192 ddxy_out, ix_ll, "");
3193 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3194 ddxy_out, iy_ll, "");
3195 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3196 interp_param, ix_ll, "");
3197 LLVMValueRef temp1, temp2;
3198
3199 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3200 LLVMFloatTypeInContext(gallivm->context), "");
3201
3202 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3203
3204 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3205
3206 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3207
3208 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3209
3210 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3211 temp2,
3212 LLVMIntTypeInContext(gallivm->context, 32), "");
3213 }
3214 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3215 }
3216
3217 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3218 for (chan = 0; chan < 2; chan++) {
3219 LLVMValueRef args[4];
3220 LLVMValueRef llvm_chan;
3221 unsigned schan;
3222
3223 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3224 llvm_chan = lp_build_const_int32(gallivm, schan);
3225
3226 args[0] = llvm_chan;
3227 args[1] = attr_number;
3228 args[2] = params;
3229 args[3] = interp_param;
3230
3231 emit_data->output[chan] =
3232 lp_build_intrinsic(gallivm->builder, intr_name,
3233 input_type, args, args[3] ? 4 : 3,
3234 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3235 }
3236 }
3237
3238 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3239 struct lp_build_emit_data *emit_data)
3240 {
3241 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3242 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3243 unsigned stream;
3244
3245 assert(src0.File == TGSI_FILE_IMMEDIATE);
3246
3247 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3248 return stream;
3249 }
3250
3251 /* Emit one vertex from the geometry shader */
3252 static void si_llvm_emit_vertex(
3253 const struct lp_build_tgsi_action *action,
3254 struct lp_build_tgsi_context *bld_base,
3255 struct lp_build_emit_data *emit_data)
3256 {
3257 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3258 struct lp_build_context *uint = &bld_base->uint_bld;
3259 struct si_shader *shader = si_shader_ctx->shader;
3260 struct tgsi_shader_info *info = &shader->selector->info;
3261 struct gallivm_state *gallivm = bld_base->base.gallivm;
3262 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3263 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3264 SI_PARAM_GS2VS_OFFSET);
3265 LLVMValueRef gs_next_vertex;
3266 LLVMValueRef can_emit, kill;
3267 LLVMValueRef args[2];
3268 unsigned chan;
3269 int i;
3270 unsigned stream;
3271
3272 stream = si_llvm_get_stream(bld_base, emit_data);
3273
3274 /* Write vertex attribute values to GSVS ring */
3275 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3276 si_shader_ctx->gs_next_vertex[stream],
3277 "");
3278
3279 /* If this thread has already emitted the declared maximum number of
3280 * vertices, kill it: excessive vertex emissions are not supposed to
3281 * have any effect, and GS threads have no externally observable
3282 * effects other than emitting vertices.
3283 */
3284 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3285 lp_build_const_int32(gallivm,
3286 shader->selector->gs_max_out_vertices), "");
3287 kill = lp_build_select(&bld_base->base, can_emit,
3288 lp_build_const_float(gallivm, 1.0f),
3289 lp_build_const_float(gallivm, -1.0f));
3290
3291 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3292 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3293
3294 for (i = 0; i < info->num_outputs; i++) {
3295 LLVMValueRef *out_ptr =
3296 si_shader_ctx->radeon_bld.soa.outputs[i];
3297
3298 for (chan = 0; chan < 4; chan++) {
3299 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3300 LLVMValueRef voffset =
3301 lp_build_const_int32(gallivm, (i * 4 + chan) *
3302 shader->selector->gs_max_out_vertices);
3303
3304 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3305 voffset = lp_build_mul_imm(uint, voffset, 4);
3306
3307 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3308
3309 build_tbuffer_store(si_shader_ctx,
3310 si_shader_ctx->gsvs_ring[stream],
3311 out_val, 1,
3312 voffset, soffset, 0,
3313 V_008F0C_BUF_DATA_FORMAT_32,
3314 V_008F0C_BUF_NUM_FORMAT_UINT,
3315 1, 0, 1, 1, 0);
3316 }
3317 }
3318 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3319 lp_build_const_int32(gallivm, 1));
3320
3321 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3322
3323 /* Signal vertex emission */
3324 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3325 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3326 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3327 LLVMVoidTypeInContext(gallivm->context), args, 2,
3328 LLVMNoUnwindAttribute);
3329 }
3330
3331 /* Cut one primitive from the geometry shader */
3332 static void si_llvm_emit_primitive(
3333 const struct lp_build_tgsi_action *action,
3334 struct lp_build_tgsi_context *bld_base,
3335 struct lp_build_emit_data *emit_data)
3336 {
3337 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3338 struct gallivm_state *gallivm = bld_base->base.gallivm;
3339 LLVMValueRef args[2];
3340 unsigned stream;
3341
3342 /* Signal primitive cut */
3343 stream = si_llvm_get_stream(bld_base, emit_data);
3344 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3345 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3346 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3347 LLVMVoidTypeInContext(gallivm->context), args, 2,
3348 LLVMNoUnwindAttribute);
3349 }
3350
3351 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3352 struct lp_build_tgsi_context *bld_base,
3353 struct lp_build_emit_data *emit_data)
3354 {
3355 struct gallivm_state *gallivm = bld_base->base.gallivm;
3356
3357 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3358 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3359 LLVMNoUnwindAttribute);
3360 }
3361
3362 static const struct lp_build_tgsi_action tex_action = {
3363 .fetch_args = tex_fetch_args,
3364 .emit = build_tex_intrinsic,
3365 };
3366
3367 static const struct lp_build_tgsi_action interp_action = {
3368 .fetch_args = interp_fetch_args,
3369 .emit = build_interp_intrinsic,
3370 };
3371
3372 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3373 {
3374 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3375 LLVMValueRef args[3];
3376
3377 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3378 args[1] = 0;
3379 args[2] = lp_build_const_int32(gallivm, 1);
3380
3381 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3382 }
3383
3384 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3385 {
3386 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3387 CONST_ADDR_SPACE);
3388 }
3389
3390 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3391 struct pipe_stream_output_info *so,
3392 LLVMTypeRef *params, LLVMTypeRef i32,
3393 unsigned *num_params)
3394 {
3395 int i;
3396
3397 /* Streamout SGPRs. */
3398 if (so->num_outputs) {
3399 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3400 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3401 }
3402 /* A streamout buffer offset is loaded if the stride is non-zero. */
3403 for (i = 0; i < 4; i++) {
3404 if (!so->stride[i])
3405 continue;
3406
3407 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3408 }
3409 }
3410
3411 static void create_function(struct si_shader_context *si_shader_ctx)
3412 {
3413 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3414 struct gallivm_state *gallivm = bld_base->base.gallivm;
3415 struct si_shader *shader = si_shader_ctx->shader;
3416 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3417 unsigned i, last_array_pointer, last_sgpr, num_params;
3418
3419 i8 = LLVMInt8TypeInContext(gallivm->context);
3420 i32 = LLVMInt32TypeInContext(gallivm->context);
3421 f32 = LLVMFloatTypeInContext(gallivm->context);
3422 v2i32 = LLVMVectorType(i32, 2);
3423 v3i32 = LLVMVectorType(i32, 3);
3424 v4i32 = LLVMVectorType(i32, 4);
3425 v8i32 = LLVMVectorType(i32, 8);
3426 v16i8 = LLVMVectorType(i8, 16);
3427
3428 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3429 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3430 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3431 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3432 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3433
3434 switch (si_shader_ctx->type) {
3435 case TGSI_PROCESSOR_VERTEX:
3436 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3437 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3438 params[SI_PARAM_BASE_VERTEX] = i32;
3439 params[SI_PARAM_START_INSTANCE] = i32;
3440 num_params = SI_PARAM_START_INSTANCE+1;
3441
3442 if (shader->key.vs.as_es) {
3443 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3444 } else if (shader->key.vs.as_ls) {
3445 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3446 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3447 } else {
3448 if (shader->is_gs_copy_shader) {
3449 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3450 num_params = SI_PARAM_CONST_BUFFERS+1;
3451 } else {
3452 params[SI_PARAM_VS_STATE_BITS] = i32;
3453 num_params = SI_PARAM_VS_STATE_BITS+1;
3454 }
3455
3456 /* The locations of the other parameters are assigned dynamically. */
3457 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3458 params, i32, &num_params);
3459 }
3460
3461 last_sgpr = num_params-1;
3462
3463 /* VGPRs */
3464 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3465 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3466 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3467 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3468 break;
3469
3470 case TGSI_PROCESSOR_TESS_CTRL:
3471 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3472 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3473 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3474 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3475 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3476
3477 /* VGPRs */
3478 params[SI_PARAM_PATCH_ID] = i32;
3479 params[SI_PARAM_REL_IDS] = i32;
3480 num_params = SI_PARAM_REL_IDS+1;
3481 break;
3482
3483 case TGSI_PROCESSOR_TESS_EVAL:
3484 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3485 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3486 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3487
3488 if (shader->key.tes.as_es) {
3489 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3490 } else {
3491 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3492 params, i32, &num_params);
3493 }
3494 last_sgpr = num_params - 1;
3495
3496 /* VGPRs */
3497 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3498 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3499 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3500 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3501 break;
3502
3503 case TGSI_PROCESSOR_GEOMETRY:
3504 params[SI_PARAM_GS2VS_OFFSET] = i32;
3505 params[SI_PARAM_GS_WAVE_ID] = i32;
3506 last_sgpr = SI_PARAM_GS_WAVE_ID;
3507
3508 /* VGPRs */
3509 params[SI_PARAM_VTX0_OFFSET] = i32;
3510 params[SI_PARAM_VTX1_OFFSET] = i32;
3511 params[SI_PARAM_PRIMITIVE_ID] = i32;
3512 params[SI_PARAM_VTX2_OFFSET] = i32;
3513 params[SI_PARAM_VTX3_OFFSET] = i32;
3514 params[SI_PARAM_VTX4_OFFSET] = i32;
3515 params[SI_PARAM_VTX5_OFFSET] = i32;
3516 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3517 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3518 break;
3519
3520 case TGSI_PROCESSOR_FRAGMENT:
3521 params[SI_PARAM_ALPHA_REF] = f32;
3522 params[SI_PARAM_PS_STATE_BITS] = i32;
3523 params[SI_PARAM_PRIM_MASK] = i32;
3524 last_sgpr = SI_PARAM_PRIM_MASK;
3525 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3526 params[SI_PARAM_PERSP_CENTER] = v2i32;
3527 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3528 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3529 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3530 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3531 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3532 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3533 params[SI_PARAM_POS_X_FLOAT] = f32;
3534 params[SI_PARAM_POS_Y_FLOAT] = f32;
3535 params[SI_PARAM_POS_Z_FLOAT] = f32;
3536 params[SI_PARAM_POS_W_FLOAT] = f32;
3537 params[SI_PARAM_FRONT_FACE] = f32;
3538 params[SI_PARAM_ANCILLARY] = i32;
3539 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3540 params[SI_PARAM_POS_FIXED_PT] = f32;
3541 num_params = SI_PARAM_POS_FIXED_PT+1;
3542 break;
3543
3544 default:
3545 assert(0 && "unimplemented shader");
3546 return;
3547 }
3548
3549 assert(num_params <= Elements(params));
3550 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3551 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3552
3553 if (shader->dx10_clamp_mode)
3554 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3555 "enable-no-nans-fp-math", "true");
3556
3557 for (i = 0; i <= last_sgpr; ++i) {
3558 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3559
3560 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3561 * to move load. Inputs are constant so this is fine. */
3562 if (i <= last_array_pointer)
3563 LLVMAddAttribute(P, LLVMByValAttribute);
3564 else
3565 LLVMAddAttribute(P, LLVMInRegAttribute);
3566 }
3567
3568 if (bld_base->info &&
3569 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3570 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3571 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3572 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3573 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3574 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3575 si_shader_ctx->lds =
3576 LLVMAddGlobalInAddressSpace(gallivm->module,
3577 LLVMArrayType(i32, 64),
3578 "ddxy_lds",
3579 LOCAL_ADDR_SPACE);
3580
3581 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3582 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3583 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3584 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3585 unsigned vertex_data_dw_size = 32*32*4;
3586 unsigned patch_data_dw_size = 32*4;
3587 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3588 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3589 unsigned lds_dwords = patch_dw_size;
3590
3591 /* The actual size is computed outside of the shader to reduce
3592 * the number of shader variants. */
3593 si_shader_ctx->lds =
3594 LLVMAddGlobalInAddressSpace(gallivm->module,
3595 LLVMArrayType(i32, lds_dwords),
3596 "tess_lds",
3597 LOCAL_ADDR_SPACE);
3598 }
3599 }
3600
3601 static void preload_constants(struct si_shader_context *si_shader_ctx)
3602 {
3603 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3604 struct gallivm_state * gallivm = bld_base->base.gallivm;
3605 const struct tgsi_shader_info * info = bld_base->info;
3606 unsigned buf;
3607 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3608
3609 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3610 unsigned i, num_const = info->const_file_max[buf] + 1;
3611
3612 if (num_const == 0)
3613 continue;
3614
3615 /* Allocate space for the constant values */
3616 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3617
3618 /* Load the resource descriptor */
3619 si_shader_ctx->const_buffers[buf] =
3620 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3621
3622 /* Load the constants, we rely on the code sinking to do the rest */
3623 for (i = 0; i < num_const * 4; ++i) {
3624 si_shader_ctx->constants[buf][i] =
3625 buffer_load_const(gallivm->builder,
3626 si_shader_ctx->const_buffers[buf],
3627 lp_build_const_int32(gallivm, i * 4),
3628 bld_base->base.elem_type);
3629 }
3630 }
3631 }
3632
3633 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3634 {
3635 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3636 struct gallivm_state * gallivm = bld_base->base.gallivm;
3637 const struct tgsi_shader_info * info = bld_base->info;
3638
3639 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3640
3641 LLVMValueRef res_ptr, samp_ptr;
3642 LLVMValueRef offset;
3643
3644 if (num_samplers == 0)
3645 return;
3646
3647 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3648 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3649
3650 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3651 for (i = 0; i < num_samplers; ++i) {
3652 /* Resource */
3653 offset = lp_build_const_int32(gallivm, i);
3654 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3655
3656 /* Sampler */
3657 offset = lp_build_const_int32(gallivm, i);
3658 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3659
3660 /* FMASK resource */
3661 if (info->is_msaa_sampler[i]) {
3662 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3663 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3664 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3665 }
3666 }
3667 }
3668
3669 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3670 {
3671 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3672 struct gallivm_state * gallivm = bld_base->base.gallivm;
3673 unsigned i;
3674
3675 /* Streamout can only be used if the shader is compiled as VS. */
3676 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3677 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3678 (si_shader_ctx->shader->key.vs.as_es ||
3679 si_shader_ctx->shader->key.vs.as_ls)) ||
3680 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3681 si_shader_ctx->shader->key.tes.as_es))
3682 return;
3683
3684 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3685 SI_PARAM_RW_BUFFERS);
3686
3687 /* Load the resources, we rely on the code sinking to do the rest */
3688 for (i = 0; i < 4; ++i) {
3689 if (si_shader_ctx->shader->selector->so.stride[i]) {
3690 LLVMValueRef offset = lp_build_const_int32(gallivm,
3691 SI_SO_BUF_OFFSET + i);
3692
3693 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3694 }
3695 }
3696 }
3697
3698 /**
3699 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3700 * for later use.
3701 */
3702 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3703 {
3704 struct gallivm_state *gallivm =
3705 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3706
3707 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3708 SI_PARAM_RW_BUFFERS);
3709
3710 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3711 si_shader_ctx->shader->key.vs.as_es) ||
3712 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3713 si_shader_ctx->shader->key.tes.as_es) ||
3714 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3715 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3716
3717 si_shader_ctx->esgs_ring =
3718 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3719 }
3720
3721 if (si_shader_ctx->shader->is_gs_copy_shader) {
3722 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3723
3724 si_shader_ctx->gsvs_ring[0] =
3725 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3726 }
3727 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3728 int i;
3729 for (i = 0; i < 4; i++) {
3730 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3731
3732 si_shader_ctx->gsvs_ring[i] =
3733 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3734 }
3735 }
3736 }
3737
3738 void si_shader_binary_read_config(struct si_shader *shader,
3739 unsigned symbol_offset)
3740 {
3741 unsigned i;
3742 const unsigned char *config =
3743 radeon_shader_binary_config_start(&shader->binary,
3744 symbol_offset);
3745
3746 /* XXX: We may be able to emit some of these values directly rather than
3747 * extracting fields to be emitted later.
3748 */
3749
3750 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3751 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3752 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3753 switch (reg) {
3754 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3755 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3756 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3757 case R_00B848_COMPUTE_PGM_RSRC1:
3758 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3759 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3760 shader->float_mode = G_00B028_FLOAT_MODE(value);
3761 shader->rsrc1 = value;
3762 break;
3763 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3764 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3765 break;
3766 case R_00B84C_COMPUTE_PGM_RSRC2:
3767 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3768 shader->rsrc2 = value;
3769 break;
3770 case R_0286CC_SPI_PS_INPUT_ENA:
3771 shader->spi_ps_input_ena = value;
3772 break;
3773 case R_0286E8_SPI_TMPRING_SIZE:
3774 case R_00B860_COMPUTE_TMPRING_SIZE:
3775 /* WAVESIZE is in units of 256 dwords. */
3776 shader->scratch_bytes_per_wave =
3777 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3778 break;
3779 default:
3780 fprintf(stderr, "Warning: Compiler emitted unknown "
3781 "config register: 0x%x\n", reg);
3782 break;
3783 }
3784 }
3785 }
3786
3787 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3788 struct si_shader *shader,
3789 uint64_t scratch_va)
3790 {
3791 unsigned i;
3792 uint32_t scratch_rsrc_dword0 = scratch_va;
3793 uint32_t scratch_rsrc_dword1 =
3794 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3795 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3796
3797 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3798 const struct radeon_shader_reloc *reloc =
3799 &shader->binary.relocs[i];
3800 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3801 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3802 &scratch_rsrc_dword0, 4);
3803 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3804 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3805 &scratch_rsrc_dword1, 4);
3806 }
3807 }
3808 }
3809
3810 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3811 {
3812 const struct radeon_shader_binary *binary = &shader->binary;
3813 unsigned code_size = binary->code_size + binary->rodata_size;
3814 unsigned char *ptr;
3815
3816 r600_resource_reference(&shader->bo, NULL);
3817 shader->bo = si_resource_create_custom(&sscreen->b.b,
3818 PIPE_USAGE_IMMUTABLE,
3819 code_size);
3820 if (!shader->bo)
3821 return -ENOMEM;
3822
3823 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3824 PIPE_TRANSFER_READ_WRITE);
3825 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3826 if (binary->rodata_size > 0) {
3827 ptr += binary->code_size;
3828 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3829 binary->rodata_size);
3830 }
3831
3832 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3833 return 0;
3834 }
3835
3836 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3837 struct pipe_debug_callback *debug)
3838 {
3839 char *line, *p;
3840 unsigned i, count;
3841
3842 if (binary->disasm_string) {
3843 fprintf(stderr, "\nShader Disassembly:\n\n");
3844 fprintf(stderr, "%s\n", binary->disasm_string);
3845
3846 if (debug && debug->debug_message) {
3847 /* Very long debug messages are cut off, so send the
3848 * disassembly one line at a time. This causes more
3849 * overhead, but on the plus side it simplifies
3850 * parsing of resulting logs.
3851 */
3852 pipe_debug_message(debug, SHADER_INFO,
3853 "Shader Disassembly Begin");
3854
3855 line = binary->disasm_string;
3856 while (*line) {
3857 p = strchrnul(line, '\n');
3858 count = p - line;
3859
3860 if (count) {
3861 pipe_debug_message(debug, SHADER_INFO,
3862 "%.*s", count, line);
3863 }
3864
3865 if (!*p)
3866 break;
3867 line = p + 1;
3868 }
3869
3870 pipe_debug_message(debug, SHADER_INFO,
3871 "Shader Disassembly End");
3872 }
3873 } else {
3874 fprintf(stderr, "SI CODE:\n");
3875 for (i = 0; i < binary->code_size; i += 4) {
3876 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3877 binary->code[i + 3], binary->code[i + 2],
3878 binary->code[i + 1], binary->code[i]);
3879 }
3880 }
3881 }
3882
3883 void si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
3884 struct pipe_debug_callback *debug, unsigned processor)
3885 {
3886 const struct radeon_shader_binary *binary = &shader->binary;
3887
3888 si_shader_binary_read_config(shader, 0);
3889
3890 if (r600_can_dump_shader(&sscreen->b, processor)) {
3891 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
3892 si_shader_dump_disassembly(binary, debug);
3893
3894 fprintf(stderr, "*** SHADER STATS ***\n"
3895 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3896 "Scratch: %d bytes per wave\n********************\n",
3897 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3898 shader->lds_size, shader->scratch_bytes_per_wave);
3899 }
3900
3901 pipe_debug_message(debug, SHADER_INFO,
3902 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
3903 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3904 shader->lds_size, shader->scratch_bytes_per_wave);
3905 }
3906
3907 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3908 LLVMTargetMachineRef tm, LLVMModuleRef mod,
3909 struct pipe_debug_callback *debug, unsigned processor)
3910 {
3911 int r = 0;
3912 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
3913
3914 if (r600_can_dump_shader(&sscreen->b, processor)) {
3915 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
3916
3917 if (!(sscreen->b.debug_flags & DBG_NO_IR))
3918 LLVMDumpModule(mod);
3919 }
3920
3921 if (!si_replace_shader(count, &shader->binary)) {
3922 r = radeon_llvm_compile(mod, &shader->binary,
3923 r600_get_llvm_processor_name(sscreen->b.family), tm,
3924 debug);
3925 if (r)
3926 return r;
3927 }
3928
3929 si_shader_binary_read(sscreen, shader, debug, processor);
3930
3931 r = si_shader_binary_upload(sscreen, shader);
3932 if (r)
3933 return r;
3934
3935 FREE(shader->binary.config);
3936 FREE(shader->binary.rodata);
3937 FREE(shader->binary.global_symbol_offsets);
3938 if (shader->scratch_bytes_per_wave == 0) {
3939 FREE(shader->binary.code);
3940 FREE(shader->binary.relocs);
3941 memset(&shader->binary, 0,
3942 offsetof(struct radeon_shader_binary, disasm_string));
3943 }
3944 return r;
3945 }
3946
3947 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3948 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3949 struct si_shader_context *si_shader_ctx,
3950 struct si_shader *gs, bool dump,
3951 struct pipe_debug_callback *debug)
3952 {
3953 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3954 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3955 struct lp_build_context *base = &bld_base->base;
3956 struct lp_build_context *uint = &bld_base->uint_bld;
3957 struct si_shader *shader = si_shader_ctx->shader;
3958 struct si_shader_output_values *outputs;
3959 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3960 LLVMValueRef args[9];
3961 int i, r;
3962
3963 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3964
3965 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3966 shader->is_gs_copy_shader = true;
3967
3968 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3969
3970 create_meta_data(si_shader_ctx);
3971 create_function(si_shader_ctx);
3972 preload_streamout_buffers(si_shader_ctx);
3973 preload_ring_buffers(si_shader_ctx);
3974
3975 args[0] = si_shader_ctx->gsvs_ring[0];
3976 args[1] = lp_build_mul_imm(uint,
3977 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3978 si_shader_ctx->param_vertex_id),
3979 4);
3980 args[3] = uint->zero;
3981 args[4] = uint->one; /* OFFEN */
3982 args[5] = uint->zero; /* IDXEN */
3983 args[6] = uint->one; /* GLC */
3984 args[7] = uint->one; /* SLC */
3985 args[8] = uint->zero; /* TFE */
3986
3987 /* Fetch vertex data from GSVS ring */
3988 for (i = 0; i < gsinfo->num_outputs; ++i) {
3989 unsigned chan;
3990
3991 outputs[i].name = gsinfo->output_semantic_name[i];
3992 outputs[i].sid = gsinfo->output_semantic_index[i];
3993
3994 for (chan = 0; chan < 4; chan++) {
3995 args[2] = lp_build_const_int32(gallivm,
3996 (i * 4 + chan) *
3997 gs->selector->gs_max_out_vertices * 16 * 4);
3998
3999 outputs[i].values[chan] =
4000 LLVMBuildBitCast(gallivm->builder,
4001 lp_build_intrinsic(gallivm->builder,
4002 "llvm.SI.buffer.load.dword.i32.i32",
4003 LLVMInt32TypeInContext(gallivm->context),
4004 args, 9,
4005 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4006 base->elem_type, "");
4007 }
4008 }
4009
4010 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4011
4012 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4013
4014 if (dump)
4015 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4016
4017 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
4018 si_shader_ctx->tm, bld_base->base.gallivm->module,
4019 debug, TGSI_PROCESSOR_GEOMETRY);
4020
4021 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4022
4023 FREE(outputs);
4024 return r;
4025 }
4026
4027 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4028 {
4029 int i;
4030
4031 fprintf(f, "SHADER KEY\n");
4032
4033 switch (shader) {
4034 case PIPE_SHADER_VERTEX:
4035 fprintf(f, " instance_divisors = {");
4036 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4037 fprintf(f, !i ? "%u" : ", %u",
4038 key->vs.instance_divisors[i]);
4039 fprintf(f, "}\n");
4040 fprintf(f, " as_es = %u\n", key->vs.as_es);
4041 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4042 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4043 break;
4044
4045 case PIPE_SHADER_TESS_CTRL:
4046 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4047 break;
4048
4049 case PIPE_SHADER_TESS_EVAL:
4050 fprintf(f, " as_es = %u\n", key->tes.as_es);
4051 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4052 break;
4053
4054 case PIPE_SHADER_GEOMETRY:
4055 break;
4056
4057 case PIPE_SHADER_FRAGMENT:
4058 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4059 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4060 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4061 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4062 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4063 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4064 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4065 break;
4066
4067 default:
4068 assert(0);
4069 }
4070 }
4071
4072 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4073 struct si_shader *shader,
4074 struct pipe_debug_callback *debug)
4075 {
4076 struct si_shader_selector *sel = shader->selector;
4077 struct tgsi_token *tokens = sel->tokens;
4078 struct si_shader_context si_shader_ctx;
4079 struct lp_build_tgsi_context * bld_base;
4080 struct tgsi_shader_info stipple_shader_info;
4081 LLVMModuleRef mod;
4082 int r = 0;
4083 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4084 shader->key.ps.poly_stipple;
4085 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4086
4087 if (poly_stipple) {
4088 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4089 SI_POLY_STIPPLE_SAMPLER);
4090 tgsi_scan_shader(tokens, &stipple_shader_info);
4091 }
4092
4093 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4094 * conversion fails. */
4095 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4096 si_dump_shader_key(sel->type, &shader->key, stderr);
4097 tgsi_dump(tokens, 0);
4098 si_dump_streamout(&sel->so);
4099 }
4100
4101 assert(shader->nparam == 0);
4102
4103 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4104 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4105 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4106
4107 if (sel->type != PIPE_SHADER_COMPUTE)
4108 shader->dx10_clamp_mode = true;
4109
4110 shader->uses_instanceid = sel->info.uses_instanceid;
4111 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4112 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4113
4114 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4115 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4116 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4117
4118 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4119 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4120 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4121 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4122 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4123 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4124 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4125 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4126 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4127 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4128 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4129 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4130 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4131
4132 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4133 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4134 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4135 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4136
4137 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4138 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4139 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4140
4141 if (HAVE_LLVM >= 0x0306) {
4142 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4143 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4144 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4145 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4146 }
4147
4148 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4149 si_shader_ctx.shader = shader;
4150 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4151 si_shader_ctx.screen = sscreen;
4152 si_shader_ctx.tm = tm;
4153
4154 switch (si_shader_ctx.type) {
4155 case TGSI_PROCESSOR_VERTEX:
4156 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4157 if (shader->key.vs.as_ls)
4158 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4159 else if (shader->key.vs.as_es)
4160 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4161 else
4162 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4163 break;
4164 case TGSI_PROCESSOR_TESS_CTRL:
4165 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4166 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4167 bld_base->emit_store = store_output_tcs;
4168 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4169 break;
4170 case TGSI_PROCESSOR_TESS_EVAL:
4171 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4172 if (shader->key.tes.as_es)
4173 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4174 else
4175 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4176 break;
4177 case TGSI_PROCESSOR_GEOMETRY:
4178 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4179 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4180 break;
4181 case TGSI_PROCESSOR_FRAGMENT:
4182 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4183 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4184 break;
4185 default:
4186 assert(!"Unsupported shader type");
4187 return -1;
4188 }
4189
4190 create_meta_data(&si_shader_ctx);
4191 create_function(&si_shader_ctx);
4192 preload_constants(&si_shader_ctx);
4193 preload_samplers(&si_shader_ctx);
4194 preload_streamout_buffers(&si_shader_ctx);
4195 preload_ring_buffers(&si_shader_ctx);
4196
4197 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4198 int i;
4199 for (i = 0; i < 4; i++) {
4200 si_shader_ctx.gs_next_vertex[i] =
4201 lp_build_alloca(bld_base->base.gallivm,
4202 bld_base->uint_bld.elem_type, "");
4203 }
4204 }
4205
4206 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4207 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4208 goto out;
4209 }
4210
4211 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4212
4213 mod = bld_base->base.gallivm->module;
4214 r = si_compile_llvm(sscreen, shader, tm, mod, debug, si_shader_ctx.type);
4215 if (r) {
4216 fprintf(stderr, "LLVM failed to compile shader\n");
4217 goto out;
4218 }
4219
4220 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4221
4222 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4223 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4224 shader->gs_copy_shader->selector = shader->selector;
4225 shader->gs_copy_shader->key = shader->key;
4226 si_shader_ctx.shader = shader->gs_copy_shader;
4227 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4228 shader, dump, debug))) {
4229 free(shader->gs_copy_shader);
4230 shader->gs_copy_shader = NULL;
4231 goto out;
4232 }
4233 }
4234
4235 out:
4236 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4237 FREE(si_shader_ctx.constants[i]);
4238 if (poly_stipple)
4239 tgsi_free_tokens(tokens);
4240 return r;
4241 }
4242
4243 void si_shader_destroy(struct si_shader *shader)
4244 {
4245 if (shader->gs_copy_shader) {
4246 si_shader_destroy(shader->gs_copy_shader);
4247 FREE(shader->gs_copy_shader);
4248 }
4249
4250 if (shader->scratch_bo)
4251 r600_resource_reference(&shader->scratch_bo, NULL);
4252
4253 r600_resource_reference(&shader->bo, NULL);
4254
4255 FREE(shader->binary.code);
4256 FREE(shader->binary.relocs);
4257 FREE(shader->binary.disasm_string);
4258 }