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radeonsi: move sample positions constant buffer to RW buffers
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94
95 LLVMTargetMachineRef tm;
96
97 LLVMValueRef const_md;
98 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
99 LLVMValueRef lds;
100 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
101 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
102 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
103 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
104 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
105 LLVMValueRef images[SI_NUM_IMAGES];
106 LLVMValueRef so_buffers[4];
107 LLVMValueRef esgs_ring;
108 LLVMValueRef gsvs_ring[4];
109 LLVMValueRef gs_next_vertex[4];
110 LLVMValueRef return_value;
111
112 LLVMTypeRef voidt;
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i32;
116 LLVMTypeRef i64;
117 LLVMTypeRef i128;
118 LLVMTypeRef f32;
119 LLVMTypeRef v16i8;
120 LLVMTypeRef v2i32;
121 LLVMTypeRef v4i32;
122 LLVMTypeRef v4f32;
123 LLVMTypeRef v8i32;
124
125 LLVMValueRef shared_memory;
126 };
127
128 static struct si_shader_context *si_shader_context(
129 struct lp_build_tgsi_context *bld_base)
130 {
131 return (struct si_shader_context *)bld_base;
132 }
133
134 static void si_init_shader_ctx(struct si_shader_context *ctx,
135 struct si_screen *sscreen,
136 struct si_shader *shader,
137 LLVMTargetMachineRef tm);
138
139 /* Ideally pass the sample mask input to the PS epilog as v13, which
140 * is its usual location, so that the shader doesn't have to add v_mov.
141 */
142 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
143
144 /* The VS location of the PrimitiveID input is the same in the epilog,
145 * so that the main shader part doesn't have to move it.
146 */
147 #define VS_EPILOG_PRIMID_LOC 2
148
149 #define PERSPECTIVE_BASE 0
150 #define LINEAR_BASE 9
151
152 #define SAMPLE_OFFSET 0
153 #define CENTER_OFFSET 2
154 #define CENTROID_OFSET 4
155
156 #define USE_SGPR_MAX_SUFFIX_LEN 5
157 #define CONST_ADDR_SPACE 2
158 #define LOCAL_ADDR_SPACE 3
159 #define USER_SGPR_ADDR_SPACE 8
160
161
162 #define SENDMSG_GS 2
163 #define SENDMSG_GS_DONE 3
164
165 #define SENDMSG_GS_OP_NOP (0 << 4)
166 #define SENDMSG_GS_OP_CUT (1 << 4)
167 #define SENDMSG_GS_OP_EMIT (2 << 4)
168 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
169
170 /**
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
173 * calculated.
174 */
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
176 {
177 switch (semantic_name) {
178 case TGSI_SEMANTIC_POSITION:
179 return 0;
180 case TGSI_SEMANTIC_PSIZE:
181 return 1;
182 case TGSI_SEMANTIC_CLIPDIST:
183 assert(index <= 1);
184 return 2 + index;
185 case TGSI_SEMANTIC_GENERIC:
186 if (index <= 63-4)
187 return 4 + index;
188 else
189 /* same explanation as in the default statement,
190 * the only user hitting this is st/nine.
191 */
192 return 0;
193
194 /* patch indices are completely separate and thus start from 0 */
195 case TGSI_SEMANTIC_TESSOUTER:
196 return 0;
197 case TGSI_SEMANTIC_TESSINNER:
198 return 1;
199 case TGSI_SEMANTIC_PATCH:
200 return 2 + index;
201
202 default:
203 /* Don't fail here. The result of this function is only used
204 * for LS, TCS, TES, and GS, where legacy GL semantics can't
205 * occur, but this function is called for all vertex shaders
206 * before it's known whether LS will be compiled or not.
207 */
208 return 0;
209 }
210 }
211
212 /**
213 * Get the value of a shader input parameter and extract a bitfield.
214 */
215 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
216 unsigned param, unsigned rshift,
217 unsigned bitwidth)
218 {
219 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
220 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
221 param);
222
223 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
224 value = bitcast(&ctx->radeon_bld.soa.bld_base,
225 TGSI_TYPE_UNSIGNED, value);
226
227 if (rshift)
228 value = LLVMBuildLShr(gallivm->builder, value,
229 lp_build_const_int32(gallivm, rshift), "");
230
231 if (rshift + bitwidth < 32) {
232 unsigned mask = (1 << bitwidth) - 1;
233 value = LLVMBuildAnd(gallivm->builder, value,
234 lp_build_const_int32(gallivm, mask), "");
235 }
236
237 return value;
238 }
239
240 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
241 {
242 switch (ctx->type) {
243 case TGSI_PROCESSOR_TESS_CTRL:
244 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
245
246 case TGSI_PROCESSOR_TESS_EVAL:
247 return LLVMGetParam(ctx->radeon_bld.main_fn,
248 ctx->param_tes_rel_patch_id);
249
250 default:
251 assert(0);
252 return NULL;
253 }
254 }
255
256 /* Tessellation shaders pass outputs to the next shader using LDS.
257 *
258 * LS outputs = TCS inputs
259 * TCS outputs = TES inputs
260 *
261 * The LDS layout is:
262 * - TCS inputs for patch 0
263 * - TCS inputs for patch 1
264 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
265 * - ...
266 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
267 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
268 * - TCS outputs for patch 1
269 * - Per-patch TCS outputs for patch 1
270 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
271 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
272 * - ...
273 *
274 * All three shaders VS(LS), TCS, TES share the same LDS space.
275 */
276
277 static LLVMValueRef
278 get_tcs_in_patch_stride(struct si_shader_context *ctx)
279 {
280 if (ctx->type == TGSI_PROCESSOR_VERTEX)
281 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
282 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
283 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
284 else {
285 assert(0);
286 return NULL;
287 }
288 }
289
290 static LLVMValueRef
291 get_tcs_out_patch_stride(struct si_shader_context *ctx)
292 {
293 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
294 }
295
296 static LLVMValueRef
297 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
298 {
299 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
300 unpack_param(ctx,
301 SI_PARAM_TCS_OUT_OFFSETS,
302 0, 16),
303 4);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
308 {
309 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
310 unpack_param(ctx,
311 SI_PARAM_TCS_OUT_OFFSETS,
312 16, 16),
313 4);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
318 {
319 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
320 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
321 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
322
323 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
324 }
325
326 static LLVMValueRef
327 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
328 {
329 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
330 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
331 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
332 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
333
334 return LLVMBuildAdd(gallivm->builder, patch0_offset,
335 LLVMBuildMul(gallivm->builder, patch_stride,
336 rel_patch_id, ""),
337 "");
338 }
339
340 static LLVMValueRef
341 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
342 {
343 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
344 LLVMValueRef patch0_patch_data_offset =
345 get_tcs_out_patch0_patch_data_offset(ctx);
346 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
350 LLVMBuildMul(gallivm->builder, patch_stride,
351 rel_patch_id, ""),
352 "");
353 }
354
355 static void build_indexed_store(struct si_shader_context *ctx,
356 LLVMValueRef base_ptr, LLVMValueRef index,
357 LLVMValueRef value)
358 {
359 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
360 struct gallivm_state *gallivm = bld_base->base.gallivm;
361 LLVMValueRef indices[2], pointer;
362
363 indices[0] = bld_base->uint_bld.zero;
364 indices[1] = index;
365
366 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
367 LLVMBuildStore(gallivm->builder, value, pointer);
368 }
369
370 /**
371 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
372 * It's equivalent to doing a load from &base_ptr[index].
373 *
374 * \param base_ptr Where the array starts.
375 * \param index The element index into the array.
376 */
377 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
378 LLVMValueRef base_ptr, LLVMValueRef index)
379 {
380 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
381 struct gallivm_state *gallivm = bld_base->base.gallivm;
382 LLVMValueRef indices[2], pointer;
383
384 indices[0] = bld_base->uint_bld.zero;
385 indices[1] = index;
386
387 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
388 return LLVMBuildLoad(gallivm->builder, pointer, "");
389 }
390
391 /**
392 * Do a load from &base_ptr[index], but also add a flag that it's loading
393 * a constant.
394 */
395 static LLVMValueRef build_indexed_load_const(
396 struct si_shader_context *ctx,
397 LLVMValueRef base_ptr, LLVMValueRef index)
398 {
399 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
400 LLVMSetMetadata(result, 1, ctx->const_md);
401 return result;
402 }
403
404 static LLVMValueRef get_instance_index_for_fetch(
405 struct radeon_llvm_context *radeon_bld,
406 unsigned param_start_instance, unsigned divisor)
407 {
408 struct si_shader_context *ctx =
409 si_shader_context(&radeon_bld->soa.bld_base);
410 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
411
412 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
413 ctx->param_instance_id);
414
415 /* The division must be done before START_INSTANCE is added. */
416 if (divisor > 1)
417 result = LLVMBuildUDiv(gallivm->builder, result,
418 lp_build_const_int32(gallivm, divisor), "");
419
420 return LLVMBuildAdd(gallivm->builder, result,
421 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
422 }
423
424 static void declare_input_vs(
425 struct radeon_llvm_context *radeon_bld,
426 unsigned input_index,
427 const struct tgsi_full_declaration *decl)
428 {
429 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
430 struct gallivm_state *gallivm = base->gallivm;
431 struct si_shader_context *ctx =
432 si_shader_context(&radeon_bld->soa.bld_base);
433 unsigned divisor =
434 ctx->shader->key.vs.prolog.instance_divisors[input_index];
435
436 unsigned chan;
437
438 LLVMValueRef t_list_ptr;
439 LLVMValueRef t_offset;
440 LLVMValueRef t_list;
441 LLVMValueRef attribute_offset;
442 LLVMValueRef buffer_index;
443 LLVMValueRef args[3];
444 LLVMValueRef input;
445
446 /* Load the T list */
447 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
448
449 t_offset = lp_build_const_int32(gallivm, input_index);
450
451 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
452
453 /* Build the attribute offset */
454 attribute_offset = lp_build_const_int32(gallivm, 0);
455
456 if (!ctx->is_monolithic) {
457 buffer_index = LLVMGetParam(radeon_bld->main_fn,
458 ctx->param_vertex_index0 +
459 input_index);
460 } else if (divisor) {
461 /* Build index from instance ID, start instance and divisor */
462 ctx->shader->info.uses_instanceid = true;
463 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
464 SI_PARAM_START_INSTANCE,
465 divisor);
466 } else {
467 /* Load the buffer index for vertices. */
468 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
469 ctx->param_vertex_id);
470 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
471 SI_PARAM_BASE_VERTEX);
472 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
473 }
474
475 args[0] = t_list;
476 args[1] = attribute_offset;
477 args[2] = buffer_index;
478 input = lp_build_intrinsic(gallivm->builder,
479 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
480 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
481
482 /* Break up the vec4 into individual components */
483 for (chan = 0; chan < 4; chan++) {
484 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
485 /* XXX: Use a helper function for this. There is one in
486 * tgsi_llvm.c. */
487 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
488 LLVMBuildExtractElement(gallivm->builder,
489 input, llvm_chan, "");
490 }
491 }
492
493 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
494 unsigned swizzle)
495 {
496 struct si_shader_context *ctx = si_shader_context(bld_base);
497
498 if (swizzle > 0)
499 return bld_base->uint_bld.zero;
500
501 switch (ctx->type) {
502 case TGSI_PROCESSOR_VERTEX:
503 return LLVMGetParam(ctx->radeon_bld.main_fn,
504 ctx->param_vs_prim_id);
505 case TGSI_PROCESSOR_TESS_CTRL:
506 return LLVMGetParam(ctx->radeon_bld.main_fn,
507 SI_PARAM_PATCH_ID);
508 case TGSI_PROCESSOR_TESS_EVAL:
509 return LLVMGetParam(ctx->radeon_bld.main_fn,
510 ctx->param_tes_patch_id);
511 case TGSI_PROCESSOR_GEOMETRY:
512 return LLVMGetParam(ctx->radeon_bld.main_fn,
513 SI_PARAM_PRIMITIVE_ID);
514 default:
515 assert(0);
516 return bld_base->uint_bld.zero;
517 }
518 }
519
520 /**
521 * Return the value of tgsi_ind_register for indexing.
522 * This is the indirect index with the constant offset added to it.
523 */
524 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index)
527 {
528 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
529 LLVMValueRef result;
530
531 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
532 result = LLVMBuildLoad(gallivm->builder, result, "");
533 result = LLVMBuildAdd(gallivm->builder, result,
534 lp_build_const_int32(gallivm, rel_index), "");
535 return result;
536 }
537
538 /**
539 * Like get_indirect_index, but restricts the return value to a (possibly
540 * undefined) value inside [0..num).
541 */
542 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
543 const struct tgsi_ind_register *ind,
544 int rel_index, unsigned num)
545 {
546 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
547 LLVMBuilderRef builder = gallivm->builder;
548 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
549 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
550 LLVMValueRef cc;
551
552 if (util_is_power_of_two(num)) {
553 result = LLVMBuildAnd(builder, result, c_max, "");
554 } else {
555 /* In theory, this MAX pattern should result in code that is
556 * as good as the bit-wise AND above.
557 *
558 * In practice, LLVM generates worse code (at the time of
559 * writing), because its value tracking is not strong enough.
560 */
561 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
562 result = LLVMBuildSelect(builder, cc, result, c_max, "");
563 }
564
565 return result;
566 }
567
568
569 /**
570 * Calculate a dword address given an input or output register and a stride.
571 */
572 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
573 const struct tgsi_full_dst_register *dst,
574 const struct tgsi_full_src_register *src,
575 LLVMValueRef vertex_dw_stride,
576 LLVMValueRef base_addr)
577 {
578 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
579 struct tgsi_shader_info *info = &ctx->shader->selector->info;
580 ubyte *name, *index, *array_first;
581 int first, param;
582 struct tgsi_full_dst_register reg;
583
584 /* Set the register description. The address computation is the same
585 * for sources and destinations. */
586 if (src) {
587 reg.Register.File = src->Register.File;
588 reg.Register.Index = src->Register.Index;
589 reg.Register.Indirect = src->Register.Indirect;
590 reg.Register.Dimension = src->Register.Dimension;
591 reg.Indirect = src->Indirect;
592 reg.Dimension = src->Dimension;
593 reg.DimIndirect = src->DimIndirect;
594 } else
595 reg = *dst;
596
597 /* If the register is 2-dimensional (e.g. an array of vertices
598 * in a primitive), calculate the base address of the vertex. */
599 if (reg.Register.Dimension) {
600 LLVMValueRef index;
601
602 if (reg.Dimension.Indirect)
603 index = get_indirect_index(ctx, &reg.DimIndirect,
604 reg.Dimension.Index);
605 else
606 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
607
608 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
609 LLVMBuildMul(gallivm->builder, index,
610 vertex_dw_stride, ""), "");
611 }
612
613 /* Get information about the register. */
614 if (reg.Register.File == TGSI_FILE_INPUT) {
615 name = info->input_semantic_name;
616 index = info->input_semantic_index;
617 array_first = info->input_array_first;
618 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
619 name = info->output_semantic_name;
620 index = info->output_semantic_index;
621 array_first = info->output_array_first;
622 } else {
623 assert(0);
624 return NULL;
625 }
626
627 if (reg.Register.Indirect) {
628 /* Add the relative address of the element. */
629 LLVMValueRef ind_index;
630
631 if (reg.Indirect.ArrayID)
632 first = array_first[reg.Indirect.ArrayID];
633 else
634 first = reg.Register.Index;
635
636 ind_index = get_indirect_index(ctx, &reg.Indirect,
637 reg.Register.Index - first);
638
639 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
640 LLVMBuildMul(gallivm->builder, ind_index,
641 lp_build_const_int32(gallivm, 4), ""), "");
642
643 param = si_shader_io_get_unique_index(name[first], index[first]);
644 } else {
645 param = si_shader_io_get_unique_index(name[reg.Register.Index],
646 index[reg.Register.Index]);
647 }
648
649 /* Add the base address of the element. */
650 return LLVMBuildAdd(gallivm->builder, base_addr,
651 lp_build_const_int32(gallivm, param * 4), "");
652 }
653
654 /**
655 * Load from LDS.
656 *
657 * \param type output value type
658 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
659 * \param dw_addr address in dwords
660 */
661 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
662 enum tgsi_opcode_type type, unsigned swizzle,
663 LLVMValueRef dw_addr)
664 {
665 struct si_shader_context *ctx = si_shader_context(bld_base);
666 struct gallivm_state *gallivm = bld_base->base.gallivm;
667 LLVMValueRef value;
668
669 if (swizzle == ~0) {
670 LLVMValueRef values[TGSI_NUM_CHANNELS];
671
672 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
673 values[chan] = lds_load(bld_base, type, chan, dw_addr);
674
675 return lp_build_gather_values(bld_base->base.gallivm, values,
676 TGSI_NUM_CHANNELS);
677 }
678
679 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
680 lp_build_const_int32(gallivm, swizzle));
681
682 value = build_indexed_load(ctx, ctx->lds, dw_addr);
683 if (type == TGSI_TYPE_DOUBLE) {
684 LLVMValueRef value2;
685 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
686 lp_build_const_int32(gallivm, swizzle + 1));
687 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
688 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
689 }
690
691 return LLVMBuildBitCast(gallivm->builder, value,
692 tgsi2llvmtype(bld_base, type), "");
693 }
694
695 /**
696 * Store to LDS.
697 *
698 * \param swizzle offset (typically 0..3)
699 * \param dw_addr address in dwords
700 * \param value value to store
701 */
702 static void lds_store(struct lp_build_tgsi_context *bld_base,
703 unsigned swizzle, LLVMValueRef dw_addr,
704 LLVMValueRef value)
705 {
706 struct si_shader_context *ctx = si_shader_context(bld_base);
707 struct gallivm_state *gallivm = bld_base->base.gallivm;
708
709 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
710 lp_build_const_int32(gallivm, swizzle));
711
712 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
713 build_indexed_store(ctx, ctx->lds,
714 dw_addr, value);
715 }
716
717 static LLVMValueRef fetch_input_tcs(
718 struct lp_build_tgsi_context *bld_base,
719 const struct tgsi_full_src_register *reg,
720 enum tgsi_opcode_type type, unsigned swizzle)
721 {
722 struct si_shader_context *ctx = si_shader_context(bld_base);
723 LLVMValueRef dw_addr, stride;
724
725 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
726 dw_addr = get_tcs_in_current_patch_offset(ctx);
727 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
728
729 return lds_load(bld_base, type, swizzle, dw_addr);
730 }
731
732 static LLVMValueRef fetch_output_tcs(
733 struct lp_build_tgsi_context *bld_base,
734 const struct tgsi_full_src_register *reg,
735 enum tgsi_opcode_type type, unsigned swizzle)
736 {
737 struct si_shader_context *ctx = si_shader_context(bld_base);
738 LLVMValueRef dw_addr, stride;
739
740 if (reg->Register.Dimension) {
741 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
742 dw_addr = get_tcs_out_current_patch_offset(ctx);
743 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
744 } else {
745 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
746 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
747 }
748
749 return lds_load(bld_base, type, swizzle, dw_addr);
750 }
751
752 static LLVMValueRef fetch_input_tes(
753 struct lp_build_tgsi_context *bld_base,
754 const struct tgsi_full_src_register *reg,
755 enum tgsi_opcode_type type, unsigned swizzle)
756 {
757 struct si_shader_context *ctx = si_shader_context(bld_base);
758 LLVMValueRef dw_addr, stride;
759
760 if (reg->Register.Dimension) {
761 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
762 dw_addr = get_tcs_out_current_patch_offset(ctx);
763 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
764 } else {
765 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
766 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
767 }
768
769 return lds_load(bld_base, type, swizzle, dw_addr);
770 }
771
772 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
773 const struct tgsi_full_instruction *inst,
774 const struct tgsi_opcode_info *info,
775 LLVMValueRef dst[4])
776 {
777 struct si_shader_context *ctx = si_shader_context(bld_base);
778 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
779 unsigned chan_index;
780 LLVMValueRef dw_addr, stride;
781
782 /* Only handle per-patch and per-vertex outputs here.
783 * Vectors will be lowered to scalars and this function will be called again.
784 */
785 if (reg->Register.File != TGSI_FILE_OUTPUT ||
786 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
787 radeon_llvm_emit_store(bld_base, inst, info, dst);
788 return;
789 }
790
791 if (reg->Register.Dimension) {
792 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
793 dw_addr = get_tcs_out_current_patch_offset(ctx);
794 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
795 } else {
796 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
797 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
798 }
799
800 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
801 LLVMValueRef value = dst[chan_index];
802
803 if (inst->Instruction.Saturate)
804 value = radeon_llvm_saturate(bld_base, value);
805
806 lds_store(bld_base, chan_index, dw_addr, value);
807 }
808 }
809
810 static LLVMValueRef fetch_input_gs(
811 struct lp_build_tgsi_context *bld_base,
812 const struct tgsi_full_src_register *reg,
813 enum tgsi_opcode_type type,
814 unsigned swizzle)
815 {
816 struct lp_build_context *base = &bld_base->base;
817 struct si_shader_context *ctx = si_shader_context(bld_base);
818 struct si_shader *shader = ctx->shader;
819 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
820 struct gallivm_state *gallivm = base->gallivm;
821 LLVMValueRef vtx_offset;
822 LLVMValueRef args[9];
823 unsigned vtx_offset_param;
824 struct tgsi_shader_info *info = &shader->selector->info;
825 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
826 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
827 unsigned param;
828 LLVMValueRef value;
829
830 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
831 return get_primitive_id(bld_base, swizzle);
832
833 if (!reg->Register.Dimension)
834 return NULL;
835
836 if (swizzle == ~0) {
837 LLVMValueRef values[TGSI_NUM_CHANNELS];
838 unsigned chan;
839 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
840 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
841 }
842 return lp_build_gather_values(bld_base->base.gallivm, values,
843 TGSI_NUM_CHANNELS);
844 }
845
846 /* Get the vertex offset parameter */
847 vtx_offset_param = reg->Dimension.Index;
848 if (vtx_offset_param < 2) {
849 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
850 } else {
851 assert(vtx_offset_param < 6);
852 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
853 }
854 vtx_offset = lp_build_mul_imm(uint,
855 LLVMGetParam(ctx->radeon_bld.main_fn,
856 vtx_offset_param),
857 4);
858
859 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
860 args[0] = ctx->esgs_ring;
861 args[1] = vtx_offset;
862 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
863 args[3] = uint->zero;
864 args[4] = uint->one; /* OFFEN */
865 args[5] = uint->zero; /* IDXEN */
866 args[6] = uint->one; /* GLC */
867 args[7] = uint->zero; /* SLC */
868 args[8] = uint->zero; /* TFE */
869
870 value = lp_build_intrinsic(gallivm->builder,
871 "llvm.SI.buffer.load.dword.i32.i32",
872 ctx->i32, args, 9,
873 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
874 if (type == TGSI_TYPE_DOUBLE) {
875 LLVMValueRef value2;
876 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
877 value2 = lp_build_intrinsic(gallivm->builder,
878 "llvm.SI.buffer.load.dword.i32.i32",
879 ctx->i32, args, 9,
880 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
881 return radeon_llvm_emit_fetch_double(bld_base,
882 value, value2);
883 }
884 return LLVMBuildBitCast(gallivm->builder,
885 value,
886 tgsi2llvmtype(bld_base, type), "");
887 }
888
889 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
890 {
891 switch (interpolate) {
892 case TGSI_INTERPOLATE_CONSTANT:
893 return 0;
894
895 case TGSI_INTERPOLATE_LINEAR:
896 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
897 return SI_PARAM_LINEAR_SAMPLE;
898 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
899 return SI_PARAM_LINEAR_CENTROID;
900 else
901 return SI_PARAM_LINEAR_CENTER;
902 break;
903 case TGSI_INTERPOLATE_COLOR:
904 case TGSI_INTERPOLATE_PERSPECTIVE:
905 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
906 return SI_PARAM_PERSP_SAMPLE;
907 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
908 return SI_PARAM_PERSP_CENTROID;
909 else
910 return SI_PARAM_PERSP_CENTER;
911 break;
912 default:
913 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
914 return -1;
915 }
916 }
917
918 /* This shouldn't be used by explicit INTERP opcodes. */
919 static unsigned select_interp_param(struct si_shader_context *ctx,
920 unsigned param)
921 {
922 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
923 !ctx->is_monolithic)
924 return param;
925
926 /* If the shader doesn't use center/centroid, just return the parameter.
927 *
928 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
929 * switch between center/centroid and sample without shader changes.
930 */
931 switch (param) {
932 case SI_PARAM_PERSP_CENTROID:
933 case SI_PARAM_PERSP_CENTER:
934 return SI_PARAM_PERSP_SAMPLE;
935
936 case SI_PARAM_LINEAR_CENTROID:
937 case SI_PARAM_LINEAR_CENTER:
938 return SI_PARAM_LINEAR_SAMPLE;
939
940 default:
941 return param;
942 }
943 }
944
945 /**
946 * Interpolate a fragment shader input.
947 *
948 * @param ctx context
949 * @param input_index index of the input in hardware
950 * @param semantic_name TGSI_SEMANTIC_*
951 * @param semantic_index semantic index
952 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
953 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
954 * @param interp_param interpolation weights (i,j)
955 * @param prim_mask SI_PARAM_PRIM_MASK
956 * @param face SI_PARAM_FRONT_FACE
957 * @param result the return value (4 components)
958 */
959 static void interp_fs_input(struct si_shader_context *ctx,
960 unsigned input_index,
961 unsigned semantic_name,
962 unsigned semantic_index,
963 unsigned num_interp_inputs,
964 unsigned colors_read_mask,
965 LLVMValueRef interp_param,
966 LLVMValueRef prim_mask,
967 LLVMValueRef face,
968 LLVMValueRef result[4])
969 {
970 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
971 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
972 struct gallivm_state *gallivm = base->gallivm;
973 const char *intr_name;
974 LLVMValueRef attr_number;
975
976 unsigned chan;
977
978 attr_number = lp_build_const_int32(gallivm, input_index);
979
980 /* fs.constant returns the param from the middle vertex, so it's not
981 * really useful for flat shading. It's meant to be used for custom
982 * interpolation (but the intrinsic can't fetch from the other two
983 * vertices).
984 *
985 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
986 * to do the right thing. The only reason we use fs.constant is that
987 * fs.interp cannot be used on integers, because they can be equal
988 * to NaN.
989 */
990 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
991
992 if (semantic_name == TGSI_SEMANTIC_COLOR &&
993 ctx->shader->key.ps.prolog.color_two_side) {
994 LLVMValueRef args[4];
995 LLVMValueRef is_face_positive;
996 LLVMValueRef back_attr_number;
997
998 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
999 * otherwise it's at offset "num_inputs".
1000 */
1001 unsigned back_attr_offset = num_interp_inputs;
1002 if (semantic_index == 1 && colors_read_mask & 0xf)
1003 back_attr_offset += 1;
1004
1005 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1006
1007 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1008 face, uint->zero, "");
1009
1010 args[2] = prim_mask;
1011 args[3] = interp_param;
1012 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1013 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1014 LLVMValueRef front, back;
1015
1016 args[0] = llvm_chan;
1017 args[1] = attr_number;
1018 front = lp_build_intrinsic(gallivm->builder, intr_name,
1019 ctx->f32, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021
1022 args[1] = back_attr_number;
1023 back = lp_build_intrinsic(gallivm->builder, intr_name,
1024 ctx->f32, args, args[3] ? 4 : 3,
1025 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1026
1027 result[chan] = LLVMBuildSelect(gallivm->builder,
1028 is_face_positive,
1029 front,
1030 back,
1031 "");
1032 }
1033 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1034 LLVMValueRef args[4];
1035
1036 args[0] = uint->zero;
1037 args[1] = attr_number;
1038 args[2] = prim_mask;
1039 args[3] = interp_param;
1040 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1041 ctx->f32, args, args[3] ? 4 : 3,
1042 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1043 result[1] =
1044 result[2] = lp_build_const_float(gallivm, 0.0f);
1045 result[3] = lp_build_const_float(gallivm, 1.0f);
1046 } else {
1047 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1048 LLVMValueRef args[4];
1049 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1050
1051 args[0] = llvm_chan;
1052 args[1] = attr_number;
1053 args[2] = prim_mask;
1054 args[3] = interp_param;
1055 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1056 ctx->f32, args, args[3] ? 4 : 3,
1057 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1058 }
1059 }
1060 }
1061
1062 static void declare_input_fs(
1063 struct radeon_llvm_context *radeon_bld,
1064 unsigned input_index,
1065 const struct tgsi_full_declaration *decl)
1066 {
1067 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1068 struct si_shader_context *ctx =
1069 si_shader_context(&radeon_bld->soa.bld_base);
1070 struct si_shader *shader = ctx->shader;
1071 LLVMValueRef main_fn = radeon_bld->main_fn;
1072 LLVMValueRef interp_param = NULL;
1073 int interp_param_idx;
1074
1075 /* Get colors from input VGPRs (set by the prolog). */
1076 if (!ctx->is_monolithic &&
1077 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1078 unsigned i = decl->Semantic.Index;
1079 unsigned colors_read = shader->selector->info.colors_read;
1080 unsigned mask = colors_read >> (i * 4);
1081 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1082 (i ? util_bitcount(colors_read & 0xf) : 0);
1083
1084 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1085 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1086 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1087 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1088 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1089 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1090 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1091 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1092 return;
1093 }
1094
1095 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1096 decl->Interp.Location);
1097 if (interp_param_idx == -1)
1098 return;
1099 else if (interp_param_idx) {
1100 interp_param_idx = select_interp_param(ctx,
1101 interp_param_idx);
1102 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1103 }
1104
1105 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1106 decl->Semantic.Index, shader->selector->info.num_inputs,
1107 shader->selector->info.colors_read, interp_param,
1108 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1109 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1110 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1111 }
1112
1113 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1114 {
1115 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1116 SI_PARAM_ANCILLARY, 8, 4);
1117 }
1118
1119 /**
1120 * Load a dword from a constant buffer.
1121 */
1122 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1123 LLVMValueRef offset, LLVMTypeRef return_type)
1124 {
1125 LLVMValueRef args[2] = {resource, offset};
1126
1127 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1128 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1129 }
1130
1131 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1132 {
1133 struct si_shader_context *ctx =
1134 si_shader_context(&radeon_bld->soa.bld_base);
1135 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1136 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1137 LLVMBuilderRef builder = gallivm->builder;
1138 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1139 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1140 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1141
1142 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1143 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1144 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1145
1146 LLVMValueRef pos[4] = {
1147 buffer_load_const(builder, resource, offset0, ctx->f32),
1148 buffer_load_const(builder, resource, offset1, ctx->f32),
1149 lp_build_const_float(gallivm, 0),
1150 lp_build_const_float(gallivm, 0)
1151 };
1152
1153 return lp_build_gather_values(gallivm, pos, 4);
1154 }
1155
1156 static void declare_system_value(
1157 struct radeon_llvm_context *radeon_bld,
1158 unsigned index,
1159 const struct tgsi_full_declaration *decl)
1160 {
1161 struct si_shader_context *ctx =
1162 si_shader_context(&radeon_bld->soa.bld_base);
1163 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1164 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1165 LLVMValueRef value = 0;
1166
1167 switch (decl->Semantic.Name) {
1168 case TGSI_SEMANTIC_INSTANCEID:
1169 value = LLVMGetParam(radeon_bld->main_fn,
1170 ctx->param_instance_id);
1171 break;
1172
1173 case TGSI_SEMANTIC_VERTEXID:
1174 value = LLVMBuildAdd(gallivm->builder,
1175 LLVMGetParam(radeon_bld->main_fn,
1176 ctx->param_vertex_id),
1177 LLVMGetParam(radeon_bld->main_fn,
1178 SI_PARAM_BASE_VERTEX), "");
1179 break;
1180
1181 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1182 value = LLVMGetParam(radeon_bld->main_fn,
1183 ctx->param_vertex_id);
1184 break;
1185
1186 case TGSI_SEMANTIC_BASEVERTEX:
1187 value = LLVMGetParam(radeon_bld->main_fn,
1188 SI_PARAM_BASE_VERTEX);
1189 break;
1190
1191 case TGSI_SEMANTIC_INVOCATIONID:
1192 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1193 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1194 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1195 value = LLVMGetParam(radeon_bld->main_fn,
1196 SI_PARAM_GS_INSTANCE_ID);
1197 else
1198 assert(!"INVOCATIONID not implemented");
1199 break;
1200
1201 case TGSI_SEMANTIC_POSITION:
1202 {
1203 LLVMValueRef pos[4] = {
1204 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1205 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1206 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1207 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1208 LLVMGetParam(radeon_bld->main_fn,
1209 SI_PARAM_POS_W_FLOAT)),
1210 };
1211 value = lp_build_gather_values(gallivm, pos, 4);
1212 break;
1213 }
1214
1215 case TGSI_SEMANTIC_FACE:
1216 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1217 break;
1218
1219 case TGSI_SEMANTIC_SAMPLEID:
1220 value = get_sample_id(radeon_bld);
1221 break;
1222
1223 case TGSI_SEMANTIC_SAMPLEPOS: {
1224 LLVMValueRef pos[4] = {
1225 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1226 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1227 lp_build_const_float(gallivm, 0),
1228 lp_build_const_float(gallivm, 0)
1229 };
1230 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1231 TGSI_OPCODE_FRC, pos[0]);
1232 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1233 TGSI_OPCODE_FRC, pos[1]);
1234 value = lp_build_gather_values(gallivm, pos, 4);
1235 break;
1236 }
1237
1238 case TGSI_SEMANTIC_SAMPLEMASK:
1239 /* This can only occur with the OpenGL Core profile, which
1240 * doesn't support smoothing.
1241 */
1242 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1243 break;
1244
1245 case TGSI_SEMANTIC_TESSCOORD:
1246 {
1247 LLVMValueRef coord[4] = {
1248 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1249 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1250 bld->zero,
1251 bld->zero
1252 };
1253
1254 /* For triangles, the vector should be (u, v, 1-u-v). */
1255 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1256 PIPE_PRIM_TRIANGLES)
1257 coord[2] = lp_build_sub(bld, bld->one,
1258 lp_build_add(bld, coord[0], coord[1]));
1259
1260 value = lp_build_gather_values(gallivm, coord, 4);
1261 break;
1262 }
1263
1264 case TGSI_SEMANTIC_VERTICESIN:
1265 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1266 break;
1267
1268 case TGSI_SEMANTIC_TESSINNER:
1269 case TGSI_SEMANTIC_TESSOUTER:
1270 {
1271 LLVMValueRef dw_addr;
1272 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1273
1274 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1275 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1276 lp_build_const_int32(gallivm, param * 4), "");
1277
1278 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1279 ~0, dw_addr);
1280 break;
1281 }
1282
1283 case TGSI_SEMANTIC_PRIMID:
1284 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1285 break;
1286
1287 case TGSI_SEMANTIC_GRID_SIZE:
1288 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1289 break;
1290
1291 case TGSI_SEMANTIC_BLOCK_SIZE:
1292 {
1293 LLVMValueRef values[3];
1294 unsigned i;
1295 unsigned *properties = ctx->shader->selector->info.properties;
1296 unsigned sizes[3] = {
1297 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1298 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1299 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1300 };
1301
1302 for (i = 0; i < 3; ++i)
1303 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1304
1305 value = lp_build_gather_values(gallivm, values, 3);
1306 break;
1307 }
1308
1309 case TGSI_SEMANTIC_BLOCK_ID:
1310 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1311 break;
1312
1313 case TGSI_SEMANTIC_THREAD_ID:
1314 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1315 break;
1316
1317 default:
1318 assert(!"unknown system value");
1319 return;
1320 }
1321
1322 radeon_bld->system_values[index] = value;
1323 }
1324
1325 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1326 const struct tgsi_full_declaration *decl)
1327 {
1328 struct si_shader_context *ctx =
1329 si_shader_context(&radeon_bld->soa.bld_base);
1330 struct si_shader_selector *sel = ctx->shader->selector;
1331 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1332
1333 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1334 LLVMValueRef var;
1335
1336 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1337 assert(decl->Range.First == decl->Range.Last);
1338 assert(!ctx->shared_memory);
1339
1340 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1341 LLVMArrayType(ctx->i8, sel->local_size),
1342 "compute_lds",
1343 LOCAL_ADDR_SPACE);
1344 LLVMSetAlignment(var, 4);
1345
1346 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1347 }
1348
1349 static LLVMValueRef fetch_constant(
1350 struct lp_build_tgsi_context *bld_base,
1351 const struct tgsi_full_src_register *reg,
1352 enum tgsi_opcode_type type,
1353 unsigned swizzle)
1354 {
1355 struct si_shader_context *ctx = si_shader_context(bld_base);
1356 struct lp_build_context *base = &bld_base->base;
1357 const struct tgsi_ind_register *ireg = &reg->Indirect;
1358 unsigned buf, idx;
1359
1360 LLVMValueRef addr, bufp;
1361 LLVMValueRef result;
1362
1363 if (swizzle == LP_CHAN_ALL) {
1364 unsigned chan;
1365 LLVMValueRef values[4];
1366 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1367 values[chan] = fetch_constant(bld_base, reg, type, chan);
1368
1369 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1370 }
1371
1372 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1373 idx = reg->Register.Index * 4 + swizzle;
1374
1375 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1376 if (type != TGSI_TYPE_DOUBLE)
1377 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1378 else {
1379 return radeon_llvm_emit_fetch_double(bld_base,
1380 ctx->constants[buf][idx],
1381 ctx->constants[buf][idx + 1]);
1382 }
1383 }
1384
1385 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1386 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1387 LLVMValueRef index;
1388 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1389 reg->Dimension.Index,
1390 SI_NUM_USER_CONST_BUFFERS);
1391 bufp = build_indexed_load_const(ctx, ptr, index);
1392 } else
1393 bufp = ctx->const_buffers[buf];
1394
1395 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1396 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1397 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1398 addr = lp_build_add(&bld_base->uint_bld, addr,
1399 lp_build_const_int32(base->gallivm, idx * 4));
1400
1401 result = buffer_load_const(base->gallivm->builder, bufp,
1402 addr, ctx->f32);
1403
1404 if (type != TGSI_TYPE_DOUBLE)
1405 result = bitcast(bld_base, type, result);
1406 else {
1407 LLVMValueRef addr2, result2;
1408 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1409 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1410 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1411 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1412 lp_build_const_int32(base->gallivm, idx * 4));
1413
1414 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1415 addr2, ctx->f32);
1416
1417 result = radeon_llvm_emit_fetch_double(bld_base,
1418 result, result2);
1419 }
1420 return result;
1421 }
1422
1423 /* Upper 16 bits must be zero. */
1424 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1425 LLVMValueRef val[2])
1426 {
1427 return LLVMBuildOr(gallivm->builder, val[0],
1428 LLVMBuildShl(gallivm->builder, val[1],
1429 lp_build_const_int32(gallivm, 16),
1430 ""), "");
1431 }
1432
1433 /* Upper 16 bits are ignored and will be dropped. */
1434 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1435 LLVMValueRef val[2])
1436 {
1437 LLVMValueRef v[2] = {
1438 LLVMBuildAnd(gallivm->builder, val[0],
1439 lp_build_const_int32(gallivm, 0xffff), ""),
1440 val[1],
1441 };
1442 return si_llvm_pack_two_int16(gallivm, v);
1443 }
1444
1445 /* Initialize arguments for the shader export intrinsic */
1446 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1447 LLVMValueRef *values,
1448 unsigned target,
1449 LLVMValueRef *args)
1450 {
1451 struct si_shader_context *ctx = si_shader_context(bld_base);
1452 struct lp_build_context *uint =
1453 &ctx->radeon_bld.soa.bld_base.uint_bld;
1454 struct lp_build_context *base = &bld_base->base;
1455 struct gallivm_state *gallivm = base->gallivm;
1456 LLVMBuilderRef builder = base->gallivm->builder;
1457 LLVMValueRef val[4];
1458 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1459 unsigned chan;
1460 bool is_int8;
1461
1462 /* Default is 0xf. Adjusted below depending on the format. */
1463 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1464
1465 /* Specify whether the EXEC mask represents the valid mask */
1466 args[1] = uint->zero;
1467
1468 /* Specify whether this is the last export */
1469 args[2] = uint->zero;
1470
1471 /* Specify the target we are exporting */
1472 args[3] = lp_build_const_int32(base->gallivm, target);
1473
1474 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1475 const union si_shader_key *key = &ctx->shader->key;
1476 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1477 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1478
1479 assert(cbuf >= 0 && cbuf < 8);
1480 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1481 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1482 }
1483
1484 args[4] = uint->zero; /* COMPR flag */
1485 args[5] = base->undef;
1486 args[6] = base->undef;
1487 args[7] = base->undef;
1488 args[8] = base->undef;
1489
1490 switch (spi_shader_col_format) {
1491 case V_028714_SPI_SHADER_ZERO:
1492 args[0] = uint->zero; /* writemask */
1493 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1494 break;
1495
1496 case V_028714_SPI_SHADER_32_R:
1497 args[0] = uint->one; /* writemask */
1498 args[5] = values[0];
1499 break;
1500
1501 case V_028714_SPI_SHADER_32_GR:
1502 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1503 args[5] = values[0];
1504 args[6] = values[1];
1505 break;
1506
1507 case V_028714_SPI_SHADER_32_AR:
1508 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1509 args[5] = values[0];
1510 args[8] = values[3];
1511 break;
1512
1513 case V_028714_SPI_SHADER_FP16_ABGR:
1514 args[4] = uint->one; /* COMPR flag */
1515
1516 for (chan = 0; chan < 2; chan++) {
1517 LLVMValueRef pack_args[2] = {
1518 values[2 * chan],
1519 values[2 * chan + 1]
1520 };
1521 LLVMValueRef packed;
1522
1523 packed = lp_build_intrinsic(base->gallivm->builder,
1524 "llvm.SI.packf16",
1525 ctx->i32, pack_args, 2,
1526 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1527 args[chan + 5] =
1528 LLVMBuildBitCast(base->gallivm->builder,
1529 packed, ctx->f32, "");
1530 }
1531 break;
1532
1533 case V_028714_SPI_SHADER_UNORM16_ABGR:
1534 for (chan = 0; chan < 4; chan++) {
1535 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1536 val[chan] = LLVMBuildFMul(builder, val[chan],
1537 lp_build_const_float(gallivm, 65535), "");
1538 val[chan] = LLVMBuildFAdd(builder, val[chan],
1539 lp_build_const_float(gallivm, 0.5), "");
1540 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1541 ctx->i32, "");
1542 }
1543
1544 args[4] = uint->one; /* COMPR flag */
1545 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1546 si_llvm_pack_two_int16(gallivm, val));
1547 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1548 si_llvm_pack_two_int16(gallivm, val+2));
1549 break;
1550
1551 case V_028714_SPI_SHADER_SNORM16_ABGR:
1552 for (chan = 0; chan < 4; chan++) {
1553 /* Clamp between [-1, 1]. */
1554 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1555 values[chan],
1556 lp_build_const_float(gallivm, 1));
1557 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1558 val[chan],
1559 lp_build_const_float(gallivm, -1));
1560 /* Convert to a signed integer in [-32767, 32767]. */
1561 val[chan] = LLVMBuildFMul(builder, val[chan],
1562 lp_build_const_float(gallivm, 32767), "");
1563 /* If positive, add 0.5, else add -0.5. */
1564 val[chan] = LLVMBuildFAdd(builder, val[chan],
1565 LLVMBuildSelect(builder,
1566 LLVMBuildFCmp(builder, LLVMRealOGE,
1567 val[chan], base->zero, ""),
1568 lp_build_const_float(gallivm, 0.5),
1569 lp_build_const_float(gallivm, -0.5), ""), "");
1570 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1571 }
1572
1573 args[4] = uint->one; /* COMPR flag */
1574 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1575 si_llvm_pack_two_int32_as_int16(gallivm, val));
1576 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1577 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1578 break;
1579
1580 case V_028714_SPI_SHADER_UINT16_ABGR: {
1581 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1582 255 : 65535);
1583 /* Clamp. */
1584 for (chan = 0; chan < 4; chan++) {
1585 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1586 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1587 val[chan], max);
1588 }
1589
1590 args[4] = uint->one; /* COMPR flag */
1591 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1592 si_llvm_pack_two_int16(gallivm, val));
1593 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1594 si_llvm_pack_two_int16(gallivm, val+2));
1595 break;
1596 }
1597
1598 case V_028714_SPI_SHADER_SINT16_ABGR: {
1599 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1600 127 : 32767);
1601 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1602 -128 : -32768);
1603 /* Clamp. */
1604 for (chan = 0; chan < 4; chan++) {
1605 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1606 val[chan] = lp_build_emit_llvm_binary(bld_base,
1607 TGSI_OPCODE_IMIN,
1608 val[chan], max);
1609 val[chan] = lp_build_emit_llvm_binary(bld_base,
1610 TGSI_OPCODE_IMAX,
1611 val[chan], min);
1612 }
1613
1614 args[4] = uint->one; /* COMPR flag */
1615 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1616 si_llvm_pack_two_int32_as_int16(gallivm, val));
1617 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1618 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1619 break;
1620 }
1621
1622 case V_028714_SPI_SHADER_32_ABGR:
1623 memcpy(&args[5], values, sizeof(values[0]) * 4);
1624 break;
1625 }
1626 }
1627
1628 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1629 LLVMValueRef alpha)
1630 {
1631 struct si_shader_context *ctx = si_shader_context(bld_base);
1632 struct gallivm_state *gallivm = bld_base->base.gallivm;
1633
1634 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1635 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1636 SI_PARAM_ALPHA_REF);
1637
1638 LLVMValueRef alpha_pass =
1639 lp_build_cmp(&bld_base->base,
1640 ctx->shader->key.ps.epilog.alpha_func,
1641 alpha, alpha_ref);
1642 LLVMValueRef arg =
1643 lp_build_select(&bld_base->base,
1644 alpha_pass,
1645 lp_build_const_float(gallivm, 1.0f),
1646 lp_build_const_float(gallivm, -1.0f));
1647
1648 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1649 ctx->voidt, &arg, 1, 0);
1650 } else {
1651 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1652 ctx->voidt, NULL, 0, 0);
1653 }
1654 }
1655
1656 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1657 LLVMValueRef alpha,
1658 unsigned samplemask_param)
1659 {
1660 struct si_shader_context *ctx = si_shader_context(bld_base);
1661 struct gallivm_state *gallivm = bld_base->base.gallivm;
1662 LLVMValueRef coverage;
1663
1664 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1665 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1666 samplemask_param);
1667 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1668
1669 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1670 ctx->i32,
1671 &coverage, 1, LLVMReadNoneAttribute);
1672
1673 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1674 ctx->f32, "");
1675
1676 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1677 lp_build_const_float(gallivm,
1678 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1679
1680 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1681 }
1682
1683 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1684 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1685 {
1686 struct si_shader_context *ctx = si_shader_context(bld_base);
1687 struct lp_build_context *base = &bld_base->base;
1688 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1689 unsigned reg_index;
1690 unsigned chan;
1691 unsigned const_chan;
1692 LLVMValueRef base_elt;
1693 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1694 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1695 SI_VS_CONST_CLIP_PLANES);
1696 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1697
1698 for (reg_index = 0; reg_index < 2; reg_index ++) {
1699 LLVMValueRef *args = pos[2 + reg_index];
1700
1701 args[5] =
1702 args[6] =
1703 args[7] =
1704 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1705
1706 /* Compute dot products of position and user clip plane vectors */
1707 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1708 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1709 args[1] = lp_build_const_int32(base->gallivm,
1710 ((reg_index * 4 + chan) * 4 +
1711 const_chan) * 4);
1712 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1713 args[1], ctx->f32);
1714 args[5 + chan] =
1715 lp_build_add(base, args[5 + chan],
1716 lp_build_mul(base, base_elt,
1717 out_elts[const_chan]));
1718 }
1719 }
1720
1721 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1722 args[1] = uint->zero;
1723 args[2] = uint->zero;
1724 args[3] = lp_build_const_int32(base->gallivm,
1725 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1726 args[4] = uint->zero;
1727 }
1728 }
1729
1730 static void si_dump_streamout(struct pipe_stream_output_info *so)
1731 {
1732 unsigned i;
1733
1734 if (so->num_outputs)
1735 fprintf(stderr, "STREAMOUT\n");
1736
1737 for (i = 0; i < so->num_outputs; i++) {
1738 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1739 so->output[i].start_component;
1740 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1741 i, so->output[i].output_buffer,
1742 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1743 so->output[i].register_index,
1744 mask & 1 ? "x" : "",
1745 mask & 2 ? "y" : "",
1746 mask & 4 ? "z" : "",
1747 mask & 8 ? "w" : "");
1748 }
1749 }
1750
1751 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1752 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1753 * or v4i32 (num_channels=3,4). */
1754 static void build_tbuffer_store(struct si_shader_context *ctx,
1755 LLVMValueRef rsrc,
1756 LLVMValueRef vdata,
1757 unsigned num_channels,
1758 LLVMValueRef vaddr,
1759 LLVMValueRef soffset,
1760 unsigned inst_offset,
1761 unsigned dfmt,
1762 unsigned nfmt,
1763 unsigned offen,
1764 unsigned idxen,
1765 unsigned glc,
1766 unsigned slc,
1767 unsigned tfe)
1768 {
1769 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1770 LLVMValueRef args[] = {
1771 rsrc,
1772 vdata,
1773 LLVMConstInt(ctx->i32, num_channels, 0),
1774 vaddr,
1775 soffset,
1776 LLVMConstInt(ctx->i32, inst_offset, 0),
1777 LLVMConstInt(ctx->i32, dfmt, 0),
1778 LLVMConstInt(ctx->i32, nfmt, 0),
1779 LLVMConstInt(ctx->i32, offen, 0),
1780 LLVMConstInt(ctx->i32, idxen, 0),
1781 LLVMConstInt(ctx->i32, glc, 0),
1782 LLVMConstInt(ctx->i32, slc, 0),
1783 LLVMConstInt(ctx->i32, tfe, 0)
1784 };
1785
1786 /* The instruction offset field has 12 bits */
1787 assert(offen || inst_offset < (1 << 12));
1788
1789 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1790 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1791 const char *types[] = {"i32", "v2i32", "v4i32"};
1792 char name[256];
1793 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1794
1795 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1796 args, Elements(args), 0);
1797 }
1798
1799 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1800 LLVMValueRef rsrc,
1801 LLVMValueRef vdata,
1802 unsigned num_channels,
1803 LLVMValueRef vaddr,
1804 LLVMValueRef soffset,
1805 unsigned inst_offset)
1806 {
1807 static unsigned dfmt[] = {
1808 V_008F0C_BUF_DATA_FORMAT_32,
1809 V_008F0C_BUF_DATA_FORMAT_32_32,
1810 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1811 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1812 };
1813 assert(num_channels >= 1 && num_channels <= 4);
1814
1815 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1816 inst_offset, dfmt[num_channels-1],
1817 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1818 }
1819
1820 /* On SI, the vertex shader is responsible for writing streamout data
1821 * to buffers. */
1822 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1823 struct si_shader_output_values *outputs,
1824 unsigned noutput)
1825 {
1826 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1827 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1828 LLVMBuilderRef builder = gallivm->builder;
1829 int i, j;
1830 struct lp_build_if_state if_ctx;
1831
1832 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1833 LLVMValueRef so_vtx_count =
1834 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1835
1836 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1837 NULL, 0, LLVMReadNoneAttribute);
1838
1839 /* can_emit = tid < so_vtx_count; */
1840 LLVMValueRef can_emit =
1841 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1842
1843 LLVMValueRef stream_id =
1844 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1845
1846 /* Emit the streamout code conditionally. This actually avoids
1847 * out-of-bounds buffer access. The hw tells us via the SGPR
1848 * (so_vtx_count) which threads are allowed to emit streamout data. */
1849 lp_build_if(&if_ctx, gallivm, can_emit);
1850 {
1851 /* The buffer offset is computed as follows:
1852 * ByteOffset = streamout_offset[buffer_id]*4 +
1853 * (streamout_write_index + thread_id)*stride[buffer_id] +
1854 * attrib_offset
1855 */
1856
1857 LLVMValueRef so_write_index =
1858 LLVMGetParam(ctx->radeon_bld.main_fn,
1859 ctx->param_streamout_write_index);
1860
1861 /* Compute (streamout_write_index + thread_id). */
1862 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1863
1864 /* Compute the write offset for each enabled buffer. */
1865 LLVMValueRef so_write_offset[4] = {};
1866 for (i = 0; i < 4; i++) {
1867 if (!so->stride[i])
1868 continue;
1869
1870 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1871 ctx->param_streamout_offset[i]);
1872 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1873
1874 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1875 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1876 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1877 }
1878
1879 /* Write streamout data. */
1880 for (i = 0; i < so->num_outputs; i++) {
1881 unsigned buf_idx = so->output[i].output_buffer;
1882 unsigned reg = so->output[i].register_index;
1883 unsigned start = so->output[i].start_component;
1884 unsigned num_comps = so->output[i].num_components;
1885 unsigned stream = so->output[i].stream;
1886 LLVMValueRef out[4];
1887 struct lp_build_if_state if_ctx_stream;
1888
1889 assert(num_comps && num_comps <= 4);
1890 if (!num_comps || num_comps > 4)
1891 continue;
1892
1893 if (reg >= noutput)
1894 continue;
1895
1896 /* Load the output as int. */
1897 for (j = 0; j < num_comps; j++) {
1898 out[j] = LLVMBuildBitCast(builder,
1899 outputs[reg].values[start+j],
1900 ctx->i32, "");
1901 }
1902
1903 /* Pack the output. */
1904 LLVMValueRef vdata = NULL;
1905
1906 switch (num_comps) {
1907 case 1: /* as i32 */
1908 vdata = out[0];
1909 break;
1910 case 2: /* as v2i32 */
1911 case 3: /* as v4i32 (aligned to 4) */
1912 case 4: /* as v4i32 */
1913 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1914 for (j = 0; j < num_comps; j++) {
1915 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1916 LLVMConstInt(ctx->i32, j, 0), "");
1917 }
1918 break;
1919 }
1920
1921 LLVMValueRef can_emit_stream =
1922 LLVMBuildICmp(builder, LLVMIntEQ,
1923 stream_id,
1924 lp_build_const_int32(gallivm, stream), "");
1925
1926 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1927 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1928 vdata, num_comps,
1929 so_write_offset[buf_idx],
1930 LLVMConstInt(ctx->i32, 0, 0),
1931 so->output[i].dst_offset*4);
1932 lp_build_endif(&if_ctx_stream);
1933 }
1934 }
1935 lp_build_endif(&if_ctx);
1936 }
1937
1938
1939 /* Generate export instructions for hardware VS shader stage */
1940 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1941 struct si_shader_output_values *outputs,
1942 unsigned noutput)
1943 {
1944 struct si_shader_context *ctx = si_shader_context(bld_base);
1945 struct si_shader *shader = ctx->shader;
1946 struct lp_build_context *base = &bld_base->base;
1947 struct lp_build_context *uint =
1948 &ctx->radeon_bld.soa.bld_base.uint_bld;
1949 LLVMValueRef args[9];
1950 LLVMValueRef pos_args[4][9] = { { 0 } };
1951 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1952 unsigned semantic_name, semantic_index;
1953 unsigned target;
1954 unsigned param_count = 0;
1955 unsigned pos_idx;
1956 int i;
1957
1958 if (outputs && ctx->shader->selector->so.num_outputs) {
1959 si_llvm_emit_streamout(ctx, outputs, noutput);
1960 }
1961
1962 for (i = 0; i < noutput; i++) {
1963 semantic_name = outputs[i].name;
1964 semantic_index = outputs[i].sid;
1965
1966 handle_semantic:
1967 /* Select the correct target */
1968 switch(semantic_name) {
1969 case TGSI_SEMANTIC_PSIZE:
1970 psize_value = outputs[i].values[0];
1971 continue;
1972 case TGSI_SEMANTIC_EDGEFLAG:
1973 edgeflag_value = outputs[i].values[0];
1974 continue;
1975 case TGSI_SEMANTIC_LAYER:
1976 layer_value = outputs[i].values[0];
1977 semantic_name = TGSI_SEMANTIC_GENERIC;
1978 goto handle_semantic;
1979 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1980 viewport_index_value = outputs[i].values[0];
1981 semantic_name = TGSI_SEMANTIC_GENERIC;
1982 goto handle_semantic;
1983 case TGSI_SEMANTIC_POSITION:
1984 target = V_008DFC_SQ_EXP_POS;
1985 break;
1986 case TGSI_SEMANTIC_COLOR:
1987 case TGSI_SEMANTIC_BCOLOR:
1988 target = V_008DFC_SQ_EXP_PARAM + param_count;
1989 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1990 shader->info.vs_output_param_offset[i] = param_count;
1991 param_count++;
1992 break;
1993 case TGSI_SEMANTIC_CLIPDIST:
1994 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1995 break;
1996 case TGSI_SEMANTIC_CLIPVERTEX:
1997 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1998 continue;
1999 case TGSI_SEMANTIC_PRIMID:
2000 case TGSI_SEMANTIC_FOG:
2001 case TGSI_SEMANTIC_TEXCOORD:
2002 case TGSI_SEMANTIC_GENERIC:
2003 target = V_008DFC_SQ_EXP_PARAM + param_count;
2004 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2005 shader->info.vs_output_param_offset[i] = param_count;
2006 param_count++;
2007 break;
2008 default:
2009 target = 0;
2010 fprintf(stderr,
2011 "Warning: SI unhandled vs output type:%d\n",
2012 semantic_name);
2013 }
2014
2015 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2016
2017 if (target >= V_008DFC_SQ_EXP_POS &&
2018 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2019 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2020 args, sizeof(args));
2021 } else {
2022 lp_build_intrinsic(base->gallivm->builder,
2023 "llvm.SI.export", ctx->voidt,
2024 args, 9, 0);
2025 }
2026
2027 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2028 semantic_name = TGSI_SEMANTIC_GENERIC;
2029 goto handle_semantic;
2030 }
2031 }
2032
2033 shader->info.nr_param_exports = param_count;
2034
2035 /* We need to add the position output manually if it's missing. */
2036 if (!pos_args[0][0]) {
2037 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2038 pos_args[0][1] = uint->zero; /* EXEC mask */
2039 pos_args[0][2] = uint->zero; /* last export? */
2040 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2041 pos_args[0][4] = uint->zero; /* COMPR flag */
2042 pos_args[0][5] = base->zero; /* X */
2043 pos_args[0][6] = base->zero; /* Y */
2044 pos_args[0][7] = base->zero; /* Z */
2045 pos_args[0][8] = base->one; /* W */
2046 }
2047
2048 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2049 if (shader->selector->info.writes_psize ||
2050 shader->selector->info.writes_edgeflag ||
2051 shader->selector->info.writes_viewport_index ||
2052 shader->selector->info.writes_layer) {
2053 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2054 shader->selector->info.writes_psize |
2055 (shader->selector->info.writes_edgeflag << 1) |
2056 (shader->selector->info.writes_layer << 2) |
2057 (shader->selector->info.writes_viewport_index << 3));
2058 pos_args[1][1] = uint->zero; /* EXEC mask */
2059 pos_args[1][2] = uint->zero; /* last export? */
2060 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2061 pos_args[1][4] = uint->zero; /* COMPR flag */
2062 pos_args[1][5] = base->zero; /* X */
2063 pos_args[1][6] = base->zero; /* Y */
2064 pos_args[1][7] = base->zero; /* Z */
2065 pos_args[1][8] = base->zero; /* W */
2066
2067 if (shader->selector->info.writes_psize)
2068 pos_args[1][5] = psize_value;
2069
2070 if (shader->selector->info.writes_edgeflag) {
2071 /* The output is a float, but the hw expects an integer
2072 * with the first bit containing the edge flag. */
2073 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2074 edgeflag_value,
2075 ctx->i32, "");
2076 edgeflag_value = lp_build_min(&bld_base->int_bld,
2077 edgeflag_value,
2078 bld_base->int_bld.one);
2079
2080 /* The LLVM intrinsic expects a float. */
2081 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2082 edgeflag_value,
2083 ctx->f32, "");
2084 }
2085
2086 if (shader->selector->info.writes_layer)
2087 pos_args[1][7] = layer_value;
2088
2089 if (shader->selector->info.writes_viewport_index)
2090 pos_args[1][8] = viewport_index_value;
2091 }
2092
2093 for (i = 0; i < 4; i++)
2094 if (pos_args[i][0])
2095 shader->info.nr_pos_exports++;
2096
2097 pos_idx = 0;
2098 for (i = 0; i < 4; i++) {
2099 if (!pos_args[i][0])
2100 continue;
2101
2102 /* Specify the target we are exporting */
2103 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2104
2105 if (pos_idx == shader->info.nr_pos_exports)
2106 /* Specify that this is the last export */
2107 pos_args[i][2] = uint->one;
2108
2109 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2110 ctx->voidt, pos_args[i], 9, 0);
2111 }
2112 }
2113
2114 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2115 LLVMValueRef rel_patch_id,
2116 LLVMValueRef invocation_id,
2117 LLVMValueRef tcs_out_current_patch_data_offset)
2118 {
2119 struct si_shader_context *ctx = si_shader_context(bld_base);
2120 struct gallivm_state *gallivm = bld_base->base.gallivm;
2121 struct si_shader *shader = ctx->shader;
2122 unsigned tess_inner_index, tess_outer_index;
2123 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2124 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2125 unsigned stride, outer_comps, inner_comps, i;
2126 struct lp_build_if_state if_ctx;
2127
2128 /* Do this only for invocation 0, because the tess levels are per-patch,
2129 * not per-vertex.
2130 *
2131 * This can't jump, because invocation 0 executes this. It should
2132 * at least mask out the loads and stores for other invocations.
2133 */
2134 lp_build_if(&if_ctx, gallivm,
2135 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2136 invocation_id, bld_base->uint_bld.zero, ""));
2137
2138 /* Determine the layout of one tess factor element in the buffer. */
2139 switch (shader->key.tcs.epilog.prim_mode) {
2140 case PIPE_PRIM_LINES:
2141 stride = 2; /* 2 dwords, 1 vec2 store */
2142 outer_comps = 2;
2143 inner_comps = 0;
2144 break;
2145 case PIPE_PRIM_TRIANGLES:
2146 stride = 4; /* 4 dwords, 1 vec4 store */
2147 outer_comps = 3;
2148 inner_comps = 1;
2149 break;
2150 case PIPE_PRIM_QUADS:
2151 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2152 outer_comps = 4;
2153 inner_comps = 2;
2154 break;
2155 default:
2156 assert(0);
2157 return;
2158 }
2159
2160 /* Load tess_inner and tess_outer from LDS.
2161 * Any invocation can write them, so we can't get them from a temporary.
2162 */
2163 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2164 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2165
2166 lds_base = tcs_out_current_patch_data_offset;
2167 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2168 lp_build_const_int32(gallivm,
2169 tess_inner_index * 4), "");
2170 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2171 lp_build_const_int32(gallivm,
2172 tess_outer_index * 4), "");
2173
2174 for (i = 0; i < outer_comps; i++)
2175 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2176 for (i = 0; i < inner_comps; i++)
2177 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2178
2179 /* Convert the outputs to vectors for stores. */
2180 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2181 vec1 = NULL;
2182
2183 if (stride > 4)
2184 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2185
2186 /* Get the buffer. */
2187 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2188 SI_PARAM_RW_BUFFERS);
2189 buffer = build_indexed_load_const(ctx, rw_buffers,
2190 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2191
2192 /* Get the offset. */
2193 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2194 SI_PARAM_TESS_FACTOR_OFFSET);
2195 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2196 lp_build_const_int32(gallivm, 4 * stride), "");
2197
2198 /* Store the outputs. */
2199 build_tbuffer_store_dwords(ctx, buffer, vec0,
2200 MIN2(stride, 4), byteoffset, tf_base, 0);
2201 if (vec1)
2202 build_tbuffer_store_dwords(ctx, buffer, vec1,
2203 stride - 4, byteoffset, tf_base, 16);
2204 lp_build_endif(&if_ctx);
2205 }
2206
2207 /* This only writes the tessellation factor levels. */
2208 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2209 {
2210 struct si_shader_context *ctx = si_shader_context(bld_base);
2211 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2212
2213 rel_patch_id = get_rel_patch_id(ctx);
2214 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2215 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2216
2217 if (!ctx->is_monolithic) {
2218 /* Return epilog parameters from this function. */
2219 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2220 LLVMValueRef ret = ctx->return_value;
2221 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2222 unsigned vgpr;
2223
2224 /* RW_BUFFERS pointer */
2225 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2226 SI_PARAM_RW_BUFFERS);
2227 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2228 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2229 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2230 bld_base->uint_bld.zero, "");
2231 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2232 bld_base->uint_bld.one, "");
2233 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2234 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2235
2236 /* Tess factor buffer soffset is after user SGPRs. */
2237 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2238 SI_PARAM_TESS_FACTOR_OFFSET);
2239 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2240 SI_TCS_NUM_USER_SGPR, "");
2241
2242 /* VGPRs */
2243 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2244 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2245 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2246
2247 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2248 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2249 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2250 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2251 ctx->return_value = ret;
2252 return;
2253 }
2254
2255 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2256 }
2257
2258 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2259 {
2260 struct si_shader_context *ctx = si_shader_context(bld_base);
2261 struct si_shader *shader = ctx->shader;
2262 struct tgsi_shader_info *info = &shader->selector->info;
2263 struct gallivm_state *gallivm = bld_base->base.gallivm;
2264 unsigned i, chan;
2265 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2266 ctx->param_rel_auto_id);
2267 LLVMValueRef vertex_dw_stride =
2268 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2269 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2270 vertex_dw_stride, "");
2271
2272 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2273 * its inputs from it. */
2274 for (i = 0; i < info->num_outputs; i++) {
2275 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2276 unsigned name = info->output_semantic_name[i];
2277 unsigned index = info->output_semantic_index[i];
2278 int param = si_shader_io_get_unique_index(name, index);
2279 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2280 lp_build_const_int32(gallivm, param * 4), "");
2281
2282 for (chan = 0; chan < 4; chan++) {
2283 lds_store(bld_base, chan, dw_addr,
2284 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2285 }
2286 }
2287 }
2288
2289 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2290 {
2291 struct si_shader_context *ctx = si_shader_context(bld_base);
2292 struct gallivm_state *gallivm = bld_base->base.gallivm;
2293 struct si_shader *es = ctx->shader;
2294 struct tgsi_shader_info *info = &es->selector->info;
2295 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2296 ctx->param_es2gs_offset);
2297 unsigned chan;
2298 int i;
2299
2300 for (i = 0; i < info->num_outputs; i++) {
2301 LLVMValueRef *out_ptr =
2302 ctx->radeon_bld.soa.outputs[i];
2303 int param_index;
2304
2305 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2306 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2307 continue;
2308
2309 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2310 info->output_semantic_index[i]);
2311
2312 for (chan = 0; chan < 4; chan++) {
2313 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2314 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2315
2316 build_tbuffer_store(ctx,
2317 ctx->esgs_ring,
2318 out_val, 1,
2319 LLVMGetUndef(ctx->i32), soffset,
2320 (4 * param_index + chan) * 4,
2321 V_008F0C_BUF_DATA_FORMAT_32,
2322 V_008F0C_BUF_NUM_FORMAT_UINT,
2323 0, 0, 1, 1, 0);
2324 }
2325 }
2326 }
2327
2328 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2329 {
2330 struct si_shader_context *ctx = si_shader_context(bld_base);
2331 struct gallivm_state *gallivm = bld_base->base.gallivm;
2332 LLVMValueRef args[2];
2333
2334 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2335 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2336 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2337 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2338 }
2339
2340 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2341 {
2342 struct si_shader_context *ctx = si_shader_context(bld_base);
2343 struct gallivm_state *gallivm = bld_base->base.gallivm;
2344 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2345 struct si_shader_output_values *outputs = NULL;
2346 int i,j;
2347
2348 assert(!ctx->is_gs_copy_shader);
2349
2350 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2351
2352 /* Vertex color clamping.
2353 *
2354 * This uses a state constant loaded in a user data SGPR and
2355 * an IF statement is added that clamps all colors if the constant
2356 * is true.
2357 */
2358 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2359 struct lp_build_if_state if_ctx;
2360 LLVMValueRef cond = NULL;
2361 LLVMValueRef addr, val;
2362
2363 for (i = 0; i < info->num_outputs; i++) {
2364 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2365 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2366 continue;
2367
2368 /* We've found a color. */
2369 if (!cond) {
2370 /* The state is in the first bit of the user SGPR. */
2371 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2372 SI_PARAM_VS_STATE_BITS);
2373 cond = LLVMBuildTrunc(gallivm->builder, cond,
2374 ctx->i1, "");
2375 lp_build_if(&if_ctx, gallivm, cond);
2376 }
2377
2378 for (j = 0; j < 4; j++) {
2379 addr = ctx->radeon_bld.soa.outputs[i][j];
2380 val = LLVMBuildLoad(gallivm->builder, addr, "");
2381 val = radeon_llvm_saturate(bld_base, val);
2382 LLVMBuildStore(gallivm->builder, val, addr);
2383 }
2384 }
2385
2386 if (cond)
2387 lp_build_endif(&if_ctx);
2388 }
2389
2390 for (i = 0; i < info->num_outputs; i++) {
2391 outputs[i].name = info->output_semantic_name[i];
2392 outputs[i].sid = info->output_semantic_index[i];
2393
2394 for (j = 0; j < 4; j++)
2395 outputs[i].values[j] =
2396 LLVMBuildLoad(gallivm->builder,
2397 ctx->radeon_bld.soa.outputs[i][j],
2398 "");
2399 }
2400
2401 if (ctx->is_monolithic) {
2402 /* Export PrimitiveID when PS needs it. */
2403 if (si_vs_exports_prim_id(ctx->shader)) {
2404 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2405 outputs[i].sid = 0;
2406 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2407 get_primitive_id(bld_base, 0));
2408 outputs[i].values[1] = bld_base->base.undef;
2409 outputs[i].values[2] = bld_base->base.undef;
2410 outputs[i].values[3] = bld_base->base.undef;
2411 i++;
2412 }
2413 } else {
2414 /* Return the primitive ID from the LLVM function. */
2415 ctx->return_value =
2416 LLVMBuildInsertValue(gallivm->builder,
2417 ctx->return_value,
2418 bitcast(bld_base, TGSI_TYPE_FLOAT,
2419 get_primitive_id(bld_base, 0)),
2420 VS_EPILOG_PRIMID_LOC, "");
2421 }
2422
2423 si_llvm_export_vs(bld_base, outputs, i);
2424 FREE(outputs);
2425 }
2426
2427 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2428 LLVMValueRef depth, LLVMValueRef stencil,
2429 LLVMValueRef samplemask)
2430 {
2431 struct si_shader_context *ctx = si_shader_context(bld_base);
2432 struct lp_build_context *base = &bld_base->base;
2433 struct lp_build_context *uint = &bld_base->uint_bld;
2434 LLVMValueRef args[9];
2435 unsigned mask = 0;
2436
2437 assert(depth || stencil || samplemask);
2438
2439 args[1] = uint->one; /* whether the EXEC mask is valid */
2440 args[2] = uint->one; /* DONE bit */
2441
2442 /* Specify the target we are exporting */
2443 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2444
2445 args[4] = uint->zero; /* COMP flag */
2446 args[5] = base->undef; /* R, depth */
2447 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2448 args[7] = base->undef; /* B, sample mask */
2449 args[8] = base->undef; /* A, alpha to mask */
2450
2451 if (depth) {
2452 args[5] = depth;
2453 mask |= 0x1;
2454 }
2455
2456 if (stencil) {
2457 args[6] = stencil;
2458 mask |= 0x2;
2459 }
2460
2461 if (samplemask) {
2462 args[7] = samplemask;
2463 mask |= 0x4;
2464 }
2465
2466 /* SI (except OLAND) has a bug that it only looks
2467 * at the X writemask component. */
2468 if (ctx->screen->b.chip_class == SI &&
2469 ctx->screen->b.family != CHIP_OLAND)
2470 mask |= 0x1;
2471
2472 /* Specify which components to enable */
2473 args[0] = lp_build_const_int32(base->gallivm, mask);
2474
2475 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2476 ctx->voidt, args, 9, 0);
2477 }
2478
2479 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2480 LLVMValueRef *color, unsigned index,
2481 unsigned samplemask_param,
2482 bool is_last)
2483 {
2484 struct si_shader_context *ctx = si_shader_context(bld_base);
2485 struct lp_build_context *base = &bld_base->base;
2486 int i;
2487
2488 /* Clamp color */
2489 if (ctx->shader->key.ps.epilog.clamp_color)
2490 for (i = 0; i < 4; i++)
2491 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2492
2493 /* Alpha to one */
2494 if (ctx->shader->key.ps.epilog.alpha_to_one)
2495 color[3] = base->one;
2496
2497 /* Alpha test */
2498 if (index == 0 &&
2499 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2500 si_alpha_test(bld_base, color[3]);
2501
2502 /* Line & polygon smoothing */
2503 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2504 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2505 samplemask_param);
2506
2507 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2508 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2509 LLVMValueRef args[8][9];
2510 int c, last = -1;
2511
2512 /* Get the export arguments, also find out what the last one is. */
2513 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2514 si_llvm_init_export_args(bld_base, color,
2515 V_008DFC_SQ_EXP_MRT + c, args[c]);
2516 if (args[c][0] != bld_base->uint_bld.zero)
2517 last = c;
2518 }
2519
2520 /* Emit all exports. */
2521 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2522 if (is_last && last == c) {
2523 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2524 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2525 } else if (args[c][0] == bld_base->uint_bld.zero)
2526 continue; /* unnecessary NULL export */
2527
2528 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2529 ctx->voidt, args[c], 9, 0);
2530 }
2531 } else {
2532 LLVMValueRef args[9];
2533
2534 /* Export */
2535 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2536 args);
2537 if (is_last) {
2538 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2539 args[2] = bld_base->uint_bld.one; /* DONE bit */
2540 } else if (args[0] == bld_base->uint_bld.zero)
2541 return; /* unnecessary NULL export */
2542
2543 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2544 ctx->voidt, args, 9, 0);
2545 }
2546 }
2547
2548 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2549 {
2550 struct si_shader_context *ctx = si_shader_context(bld_base);
2551 struct lp_build_context *base = &bld_base->base;
2552 struct lp_build_context *uint = &bld_base->uint_bld;
2553 LLVMValueRef args[9];
2554
2555 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2556 args[1] = uint->one; /* whether the EXEC mask is valid */
2557 args[2] = uint->one; /* DONE bit */
2558 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2559 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2560 args[5] = uint->undef; /* R */
2561 args[6] = uint->undef; /* G */
2562 args[7] = uint->undef; /* B */
2563 args[8] = uint->undef; /* A */
2564
2565 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2566 ctx->voidt, args, 9, 0);
2567 }
2568
2569 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2570 {
2571 struct si_shader_context *ctx = si_shader_context(bld_base);
2572 struct si_shader *shader = ctx->shader;
2573 struct lp_build_context *base = &bld_base->base;
2574 struct tgsi_shader_info *info = &shader->selector->info;
2575 LLVMBuilderRef builder = base->gallivm->builder;
2576 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2577 int last_color_export = -1;
2578 int i;
2579
2580 /* Determine the last export. If MRTZ is present, it's always last.
2581 * Otherwise, find the last color export.
2582 */
2583 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2584 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2585
2586 /* Don't export NULL and return if alpha-test is enabled. */
2587 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2588 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2589 (spi_format & 0xf) == 0)
2590 spi_format |= V_028714_SPI_SHADER_32_AR;
2591
2592 for (i = 0; i < info->num_outputs; i++) {
2593 unsigned index = info->output_semantic_index[i];
2594
2595 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2596 continue;
2597
2598 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2599 if (shader->key.ps.epilog.last_cbuf > 0) {
2600 /* Just set this if any of the colorbuffers are enabled. */
2601 if (spi_format &
2602 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2603 last_color_export = i;
2604 continue;
2605 }
2606
2607 if ((spi_format >> (index * 4)) & 0xf)
2608 last_color_export = i;
2609 }
2610
2611 /* If there are no outputs, export NULL. */
2612 if (last_color_export == -1) {
2613 si_export_null(bld_base);
2614 return;
2615 }
2616 }
2617
2618 for (i = 0; i < info->num_outputs; i++) {
2619 unsigned semantic_name = info->output_semantic_name[i];
2620 unsigned semantic_index = info->output_semantic_index[i];
2621 unsigned j;
2622 LLVMValueRef color[4] = {};
2623
2624 /* Select the correct target */
2625 switch (semantic_name) {
2626 case TGSI_SEMANTIC_POSITION:
2627 depth = LLVMBuildLoad(builder,
2628 ctx->radeon_bld.soa.outputs[i][2], "");
2629 break;
2630 case TGSI_SEMANTIC_STENCIL:
2631 stencil = LLVMBuildLoad(builder,
2632 ctx->radeon_bld.soa.outputs[i][1], "");
2633 break;
2634 case TGSI_SEMANTIC_SAMPLEMASK:
2635 samplemask = LLVMBuildLoad(builder,
2636 ctx->radeon_bld.soa.outputs[i][0], "");
2637 break;
2638 case TGSI_SEMANTIC_COLOR:
2639 for (j = 0; j < 4; j++)
2640 color[j] = LLVMBuildLoad(builder,
2641 ctx->radeon_bld.soa.outputs[i][j], "");
2642
2643 si_export_mrt_color(bld_base, color, semantic_index,
2644 SI_PARAM_SAMPLE_COVERAGE,
2645 last_color_export == i);
2646 break;
2647 default:
2648 fprintf(stderr,
2649 "Warning: SI unhandled fs output type:%d\n",
2650 semantic_name);
2651 }
2652 }
2653
2654 if (depth || stencil || samplemask)
2655 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2656 }
2657
2658 /**
2659 * Return PS outputs in this order:
2660 *
2661 * v[0:3] = color0.xyzw
2662 * v[4:7] = color1.xyzw
2663 * ...
2664 * vN+0 = Depth
2665 * vN+1 = Stencil
2666 * vN+2 = SampleMask
2667 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2668 *
2669 * The alpha-ref SGPR is returned via its original location.
2670 */
2671 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2672 {
2673 struct si_shader_context *ctx = si_shader_context(bld_base);
2674 struct si_shader *shader = ctx->shader;
2675 struct lp_build_context *base = &bld_base->base;
2676 struct tgsi_shader_info *info = &shader->selector->info;
2677 LLVMBuilderRef builder = base->gallivm->builder;
2678 unsigned i, j, first_vgpr, vgpr;
2679
2680 LLVMValueRef color[8][4] = {};
2681 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2682 LLVMValueRef ret;
2683
2684 /* Read the output values. */
2685 for (i = 0; i < info->num_outputs; i++) {
2686 unsigned semantic_name = info->output_semantic_name[i];
2687 unsigned semantic_index = info->output_semantic_index[i];
2688
2689 switch (semantic_name) {
2690 case TGSI_SEMANTIC_COLOR:
2691 assert(semantic_index < 8);
2692 for (j = 0; j < 4; j++) {
2693 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2694 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2695 color[semantic_index][j] = result;
2696 }
2697 break;
2698 case TGSI_SEMANTIC_POSITION:
2699 depth = LLVMBuildLoad(builder,
2700 ctx->radeon_bld.soa.outputs[i][2], "");
2701 break;
2702 case TGSI_SEMANTIC_STENCIL:
2703 stencil = LLVMBuildLoad(builder,
2704 ctx->radeon_bld.soa.outputs[i][1], "");
2705 break;
2706 case TGSI_SEMANTIC_SAMPLEMASK:
2707 samplemask = LLVMBuildLoad(builder,
2708 ctx->radeon_bld.soa.outputs[i][0], "");
2709 break;
2710 default:
2711 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2712 semantic_name);
2713 }
2714 }
2715
2716 /* Fill the return structure. */
2717 ret = ctx->return_value;
2718
2719 /* Set SGPRs. */
2720 ret = LLVMBuildInsertValue(builder, ret,
2721 bitcast(bld_base, TGSI_TYPE_SIGNED,
2722 LLVMGetParam(ctx->radeon_bld.main_fn,
2723 SI_PARAM_ALPHA_REF)),
2724 SI_SGPR_ALPHA_REF, "");
2725
2726 /* Set VGPRs */
2727 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2728 for (i = 0; i < ARRAY_SIZE(color); i++) {
2729 if (!color[i][0])
2730 continue;
2731
2732 for (j = 0; j < 4; j++)
2733 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2734 }
2735 if (depth)
2736 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2737 if (stencil)
2738 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2739 if (samplemask)
2740 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2741
2742 /* Add the input sample mask for smoothing at the end. */
2743 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2744 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2745 ret = LLVMBuildInsertValue(builder, ret,
2746 LLVMGetParam(ctx->radeon_bld.main_fn,
2747 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2748
2749 ctx->return_value = ret;
2750 }
2751
2752 /**
2753 * Given a v8i32 resource descriptor for a buffer, extract the size of the
2754 * buffer in number of elements and return it as an i32.
2755 */
2756 static LLVMValueRef get_buffer_size(
2757 struct lp_build_tgsi_context *bld_base,
2758 LLVMValueRef descriptor)
2759 {
2760 struct si_shader_context *ctx = si_shader_context(bld_base);
2761 struct gallivm_state *gallivm = bld_base->base.gallivm;
2762 LLVMBuilderRef builder = gallivm->builder;
2763 LLVMValueRef size =
2764 LLVMBuildExtractElement(builder, descriptor,
2765 lp_build_const_int32(gallivm, 6), "");
2766
2767 if (ctx->screen->b.chip_class >= VI) {
2768 /* On VI, the descriptor contains the size in bytes,
2769 * but TXQ must return the size in elements.
2770 * The stride is always non-zero for resources using TXQ.
2771 */
2772 LLVMValueRef stride =
2773 LLVMBuildExtractElement(builder, descriptor,
2774 lp_build_const_int32(gallivm, 5), "");
2775 stride = LLVMBuildLShr(builder, stride,
2776 lp_build_const_int32(gallivm, 16), "");
2777 stride = LLVMBuildAnd(builder, stride,
2778 lp_build_const_int32(gallivm, 0x3FFF), "");
2779
2780 size = LLVMBuildUDiv(builder, size, stride, "");
2781 }
2782
2783 return size;
2784 }
2785
2786 /**
2787 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2788 * intrinsic names).
2789 */
2790 static void build_int_type_name(
2791 LLVMTypeRef type,
2792 char *buf, unsigned bufsize)
2793 {
2794 assert(bufsize >= 6);
2795
2796 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2797 snprintf(buf, bufsize, "v%ui32",
2798 LLVMGetVectorSize(type));
2799 else
2800 strcpy(buf, "i32");
2801 }
2802
2803 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2804 struct lp_build_tgsi_context *bld_base,
2805 struct lp_build_emit_data *emit_data);
2806
2807 /* Prevent optimizations (at least of memory accesses) across the current
2808 * point in the program by emitting empty inline assembly that is marked as
2809 * having side effects.
2810 */
2811 static void emit_optimization_barrier(struct si_shader_context *ctx)
2812 {
2813 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2814 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
2815 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
2816 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
2817 }
2818
2819 static void membar_emit(
2820 const struct lp_build_tgsi_action *action,
2821 struct lp_build_tgsi_context *bld_base,
2822 struct lp_build_emit_data *emit_data)
2823 {
2824 struct si_shader_context *ctx = si_shader_context(bld_base);
2825
2826 /* Since memoryBarrier only makes guarantees about atomics and
2827 * coherent image accesses (which bypass TC L1), we do not need to emit
2828 * any special cache handling here.
2829 *
2830 * We do have to prevent LLVM from re-ordering loads across
2831 * the barrier though.
2832 */
2833 emit_optimization_barrier(ctx);
2834 }
2835
2836 static LLVMValueRef
2837 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
2838 const struct tgsi_full_src_register *reg)
2839 {
2840 LLVMValueRef ind_index;
2841 LLVMValueRef rsrc_ptr;
2842
2843 if (!reg->Register.Indirect)
2844 return ctx->shader_buffers[reg->Register.Index];
2845
2846 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
2847 reg->Register.Index,
2848 SI_NUM_SHADER_BUFFERS);
2849
2850 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
2851 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2852 }
2853
2854 static bool tgsi_is_array_sampler(unsigned target)
2855 {
2856 return target == TGSI_TEXTURE_1D_ARRAY ||
2857 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2858 target == TGSI_TEXTURE_2D_ARRAY ||
2859 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2860 target == TGSI_TEXTURE_CUBE_ARRAY ||
2861 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2862 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2863 }
2864
2865 static bool tgsi_is_array_image(unsigned target)
2866 {
2867 return target == TGSI_TEXTURE_3D ||
2868 target == TGSI_TEXTURE_CUBE ||
2869 target == TGSI_TEXTURE_1D_ARRAY ||
2870 target == TGSI_TEXTURE_2D_ARRAY ||
2871 target == TGSI_TEXTURE_CUBE_ARRAY ||
2872 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2873 }
2874
2875 /**
2876 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
2877 *
2878 * At least on Tonga, executing image stores on images with DCC enabled and
2879 * non-trivial can eventually lead to lockups. This can occur when an
2880 * application binds an image as read-only but then uses a shader that writes
2881 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
2882 * program termination) in this case, but it doesn't cost much to be a bit
2883 * nicer: disabling DCC in the shader still leads to undefined results but
2884 * avoids the lockup.
2885 */
2886 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
2887 LLVMValueRef rsrc)
2888 {
2889 if (ctx->screen->b.chip_class <= CIK) {
2890 return rsrc;
2891 } else {
2892 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2893 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
2894 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
2895 LLVMValueRef tmp;
2896
2897 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
2898 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
2899 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
2900 }
2901 }
2902
2903 /**
2904 * Load the resource descriptor for \p image.
2905 */
2906 static void
2907 image_fetch_rsrc(
2908 struct lp_build_tgsi_context *bld_base,
2909 const struct tgsi_full_src_register *image,
2910 bool dcc_off,
2911 LLVMValueRef *rsrc)
2912 {
2913 struct si_shader_context *ctx = si_shader_context(bld_base);
2914
2915 assert(image->Register.File == TGSI_FILE_IMAGE);
2916
2917 if (!image->Register.Indirect) {
2918 /* Fast path: use preloaded resources */
2919 *rsrc = ctx->images[image->Register.Index];
2920 } else {
2921 /* Indexing and manual load */
2922 LLVMValueRef ind_index;
2923 LLVMValueRef rsrc_ptr;
2924 LLVMValueRef tmp;
2925
2926 /* From the GL_ARB_shader_image_load_store extension spec:
2927 *
2928 * If a shader performs an image load, store, or atomic
2929 * operation using an image variable declared as an array,
2930 * and if the index used to select an individual element is
2931 * negative or greater than or equal to the size of the
2932 * array, the results of the operation are undefined but may
2933 * not lead to termination.
2934 */
2935 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
2936 image->Register.Index,
2937 SI_NUM_IMAGES);
2938
2939 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
2940 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2941 if (dcc_off)
2942 tmp = force_dcc_off(ctx, tmp);
2943 *rsrc = tmp;
2944 }
2945 }
2946
2947 static LLVMValueRef image_fetch_coords(
2948 struct lp_build_tgsi_context *bld_base,
2949 const struct tgsi_full_instruction *inst,
2950 unsigned src)
2951 {
2952 struct gallivm_state *gallivm = bld_base->base.gallivm;
2953 LLVMBuilderRef builder = gallivm->builder;
2954 unsigned target = inst->Memory.Texture;
2955 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
2956 LLVMValueRef coords[4];
2957 LLVMValueRef tmp;
2958 int chan;
2959
2960 for (chan = 0; chan < num_coords; ++chan) {
2961 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
2962 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
2963 coords[chan] = tmp;
2964 }
2965
2966 if (num_coords == 1)
2967 return coords[0];
2968
2969 if (num_coords == 3) {
2970 /* LLVM has difficulties lowering 3-element vectors. */
2971 coords[3] = bld_base->uint_bld.undef;
2972 num_coords = 4;
2973 }
2974
2975 return lp_build_gather_values(gallivm, coords, num_coords);
2976 }
2977
2978 /**
2979 * Append the extra mode bits that are used by image load and store.
2980 */
2981 static void image_append_args(
2982 struct si_shader_context *ctx,
2983 struct lp_build_emit_data * emit_data,
2984 unsigned target,
2985 bool atomic)
2986 {
2987 const struct tgsi_full_instruction *inst = emit_data->inst;
2988 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2989 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2990
2991 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
2992 emit_data->args[emit_data->arg_count++] =
2993 tgsi_is_array_image(target) ? i1true : i1false; /* da */
2994 if (!atomic) {
2995 emit_data->args[emit_data->arg_count++] =
2996 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
2997 i1true : i1false; /* glc */
2998 }
2999 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3000 }
3001
3002 /**
3003 * Given a 256 bit resource, extract the top half (which stores the buffer
3004 * resource in the case of textures and images).
3005 */
3006 static LLVMValueRef extract_rsrc_top_half(
3007 struct si_shader_context *ctx,
3008 LLVMValueRef rsrc)
3009 {
3010 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3011 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3012 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3013
3014 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3015 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3016 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3017
3018 return rsrc;
3019 }
3020
3021 /**
3022 * Append the resource and indexing arguments for buffer intrinsics.
3023 *
3024 * \param rsrc the v4i32 buffer resource
3025 * \param index index into the buffer (stride-based)
3026 * \param offset byte offset into the buffer
3027 */
3028 static void buffer_append_args(
3029 struct si_shader_context *ctx,
3030 struct lp_build_emit_data *emit_data,
3031 LLVMValueRef rsrc,
3032 LLVMValueRef index,
3033 LLVMValueRef offset,
3034 bool atomic)
3035 {
3036 const struct tgsi_full_instruction *inst = emit_data->inst;
3037 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3038 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3039
3040 emit_data->args[emit_data->arg_count++] = rsrc;
3041 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3042 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3043 if (!atomic) {
3044 emit_data->args[emit_data->arg_count++] =
3045 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3046 i1true : i1false; /* glc */
3047 }
3048 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3049 }
3050
3051 static void load_fetch_args(
3052 struct lp_build_tgsi_context * bld_base,
3053 struct lp_build_emit_data * emit_data)
3054 {
3055 struct si_shader_context *ctx = si_shader_context(bld_base);
3056 struct gallivm_state *gallivm = bld_base->base.gallivm;
3057 const struct tgsi_full_instruction * inst = emit_data->inst;
3058 unsigned target = inst->Memory.Texture;
3059 LLVMValueRef rsrc;
3060
3061 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3062
3063 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3064 LLVMBuilderRef builder = gallivm->builder;
3065 LLVMValueRef offset;
3066 LLVMValueRef tmp;
3067
3068 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3069
3070 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3071 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3072
3073 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3074 offset, false);
3075 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3076 LLVMValueRef coords;
3077
3078 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3079 coords = image_fetch_coords(bld_base, inst, 1);
3080
3081 if (target == TGSI_TEXTURE_BUFFER) {
3082 rsrc = extract_rsrc_top_half(ctx, rsrc);
3083 buffer_append_args(ctx, emit_data, rsrc, coords,
3084 bld_base->uint_bld.zero, false);
3085 } else {
3086 emit_data->args[0] = coords;
3087 emit_data->args[1] = rsrc;
3088 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3089 emit_data->arg_count = 3;
3090
3091 image_append_args(ctx, emit_data, target, false);
3092 }
3093 }
3094 }
3095
3096 static void load_emit_buffer(struct si_shader_context *ctx,
3097 struct lp_build_emit_data *emit_data)
3098 {
3099 const struct tgsi_full_instruction *inst = emit_data->inst;
3100 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3101 LLVMBuilderRef builder = gallivm->builder;
3102 uint writemask = inst->Dst[0].Register.WriteMask;
3103 uint count = util_last_bit(writemask);
3104 const char *intrinsic_name;
3105 LLVMTypeRef dst_type;
3106
3107 switch (count) {
3108 case 1:
3109 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3110 dst_type = ctx->f32;
3111 break;
3112 case 2:
3113 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3114 dst_type = LLVMVectorType(ctx->f32, 2);
3115 break;
3116 default: // 3 & 4
3117 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3118 dst_type = ctx->v4f32;
3119 count = 4;
3120 }
3121
3122 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3123 builder, intrinsic_name, dst_type,
3124 emit_data->args, emit_data->arg_count,
3125 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3126 }
3127
3128 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3129 const struct tgsi_full_instruction *inst,
3130 LLVMTypeRef type, int arg)
3131 {
3132 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3133 LLVMBuilderRef builder = gallivm->builder;
3134 LLVMValueRef offset, ptr;
3135 int addr_space;
3136
3137 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3138 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3139
3140 ptr = ctx->shared_memory;
3141 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3142 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3143 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3144
3145 return ptr;
3146 }
3147
3148 static void load_emit_memory(
3149 struct si_shader_context *ctx,
3150 struct lp_build_emit_data *emit_data)
3151 {
3152 const struct tgsi_full_instruction *inst = emit_data->inst;
3153 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3154 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3155 LLVMBuilderRef builder = gallivm->builder;
3156 unsigned writemask = inst->Dst[0].Register.WriteMask;
3157 LLVMValueRef channels[4], ptr, derived_ptr, index;
3158 int chan;
3159
3160 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3161
3162 for (chan = 0; chan < 4; ++chan) {
3163 if (!(writemask & (1 << chan))) {
3164 channels[chan] = LLVMGetUndef(base->elem_type);
3165 continue;
3166 }
3167
3168 index = lp_build_const_int32(gallivm, chan);
3169 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3170 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3171 }
3172 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3173 }
3174
3175 static void load_emit(
3176 const struct lp_build_tgsi_action *action,
3177 struct lp_build_tgsi_context *bld_base,
3178 struct lp_build_emit_data *emit_data)
3179 {
3180 struct si_shader_context *ctx = si_shader_context(bld_base);
3181 struct gallivm_state *gallivm = bld_base->base.gallivm;
3182 LLVMBuilderRef builder = gallivm->builder;
3183 const struct tgsi_full_instruction * inst = emit_data->inst;
3184 char intrinsic_name[32];
3185 char coords_type[8];
3186
3187 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3188 load_emit_memory(ctx, emit_data);
3189 return;
3190 }
3191
3192 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3193 emit_optimization_barrier(ctx);
3194
3195 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3196 load_emit_buffer(ctx, emit_data);
3197 return;
3198 }
3199
3200 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3201 emit_data->output[emit_data->chan] =
3202 lp_build_intrinsic(
3203 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3204 emit_data->args, emit_data->arg_count,
3205 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3206 } else {
3207 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3208 coords_type, sizeof(coords_type));
3209
3210 snprintf(intrinsic_name, sizeof(intrinsic_name),
3211 "llvm.amdgcn.image.load.%s", coords_type);
3212
3213 emit_data->output[emit_data->chan] =
3214 lp_build_intrinsic(
3215 builder, intrinsic_name, emit_data->dst_type,
3216 emit_data->args, emit_data->arg_count,
3217 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3218 }
3219 }
3220
3221 static void store_fetch_args(
3222 struct lp_build_tgsi_context * bld_base,
3223 struct lp_build_emit_data * emit_data)
3224 {
3225 struct si_shader_context *ctx = si_shader_context(bld_base);
3226 struct gallivm_state *gallivm = bld_base->base.gallivm;
3227 LLVMBuilderRef builder = gallivm->builder;
3228 const struct tgsi_full_instruction * inst = emit_data->inst;
3229 struct tgsi_full_src_register memory;
3230 LLVMValueRef chans[4];
3231 LLVMValueRef data;
3232 LLVMValueRef rsrc;
3233 unsigned chan;
3234
3235 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3236
3237 for (chan = 0; chan < 4; ++chan) {
3238 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3239 }
3240 data = lp_build_gather_values(gallivm, chans, 4);
3241
3242 emit_data->args[emit_data->arg_count++] = data;
3243
3244 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3245
3246 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3247 LLVMValueRef offset;
3248 LLVMValueRef tmp;
3249
3250 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3251
3252 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3253 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3254
3255 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3256 offset, false);
3257 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3258 unsigned target = inst->Memory.Texture;
3259 LLVMValueRef coords;
3260
3261 coords = image_fetch_coords(bld_base, inst, 0);
3262
3263 if (target == TGSI_TEXTURE_BUFFER) {
3264 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3265
3266 rsrc = extract_rsrc_top_half(ctx, rsrc);
3267 buffer_append_args(ctx, emit_data, rsrc, coords,
3268 bld_base->uint_bld.zero, false);
3269 } else {
3270 emit_data->args[1] = coords;
3271 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3272 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3273 emit_data->arg_count = 4;
3274
3275 image_append_args(ctx, emit_data, target, false);
3276 }
3277 }
3278 }
3279
3280 static void store_emit_buffer(
3281 struct si_shader_context *ctx,
3282 struct lp_build_emit_data *emit_data)
3283 {
3284 const struct tgsi_full_instruction *inst = emit_data->inst;
3285 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3286 LLVMBuilderRef builder = gallivm->builder;
3287 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3288 LLVMValueRef base_data = emit_data->args[0];
3289 LLVMValueRef base_offset = emit_data->args[3];
3290 unsigned writemask = inst->Dst[0].Register.WriteMask;
3291
3292 while (writemask) {
3293 int start, count;
3294 const char *intrinsic_name;
3295 LLVMValueRef data;
3296 LLVMValueRef offset;
3297 LLVMValueRef tmp;
3298
3299 u_bit_scan_consecutive_range(&writemask, &start, &count);
3300
3301 /* Due to an LLVM limitation, split 3-element writes
3302 * into a 2-element and a 1-element write. */
3303 if (count == 3) {
3304 writemask |= 1 << (start + 2);
3305 count = 2;
3306 }
3307
3308 if (count == 4) {
3309 data = base_data;
3310 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3311 } else if (count == 2) {
3312 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3313
3314 tmp = LLVMBuildExtractElement(
3315 builder, base_data,
3316 lp_build_const_int32(gallivm, start), "");
3317 data = LLVMBuildInsertElement(
3318 builder, LLVMGetUndef(v2f32), tmp,
3319 uint_bld->zero, "");
3320
3321 tmp = LLVMBuildExtractElement(
3322 builder, base_data,
3323 lp_build_const_int32(gallivm, start + 1), "");
3324 data = LLVMBuildInsertElement(
3325 builder, data, tmp, uint_bld->one, "");
3326
3327 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3328 } else {
3329 assert(count == 1);
3330 data = LLVMBuildExtractElement(
3331 builder, base_data,
3332 lp_build_const_int32(gallivm, start), "");
3333 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3334 }
3335
3336 offset = base_offset;
3337 if (start != 0) {
3338 offset = LLVMBuildAdd(
3339 builder, offset,
3340 lp_build_const_int32(gallivm, start * 4), "");
3341 }
3342
3343 emit_data->args[0] = data;
3344 emit_data->args[3] = offset;
3345
3346 lp_build_intrinsic(
3347 builder, intrinsic_name, emit_data->dst_type,
3348 emit_data->args, emit_data->arg_count,
3349 LLVMNoUnwindAttribute);
3350 }
3351 }
3352
3353 static void store_emit_memory(
3354 struct si_shader_context *ctx,
3355 struct lp_build_emit_data *emit_data)
3356 {
3357 const struct tgsi_full_instruction *inst = emit_data->inst;
3358 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3359 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3360 LLVMBuilderRef builder = gallivm->builder;
3361 unsigned writemask = inst->Dst[0].Register.WriteMask;
3362 LLVMValueRef ptr, derived_ptr, data, index;
3363 int chan;
3364
3365 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3366
3367 for (chan = 0; chan < 4; ++chan) {
3368 if (!(writemask & (1 << chan))) {
3369 continue;
3370 }
3371 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3372 index = lp_build_const_int32(gallivm, chan);
3373 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3374 LLVMBuildStore(builder, data, derived_ptr);
3375 }
3376 }
3377
3378 static void store_emit(
3379 const struct lp_build_tgsi_action *action,
3380 struct lp_build_tgsi_context *bld_base,
3381 struct lp_build_emit_data *emit_data)
3382 {
3383 struct gallivm_state *gallivm = bld_base->base.gallivm;
3384 LLVMBuilderRef builder = gallivm->builder;
3385 const struct tgsi_full_instruction * inst = emit_data->inst;
3386 unsigned target = inst->Memory.Texture;
3387 char intrinsic_name[32];
3388 char coords_type[8];
3389
3390 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3391 store_emit_buffer(si_shader_context(bld_base), emit_data);
3392 return;
3393 } else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3394 store_emit_memory(si_shader_context(bld_base), emit_data);
3395 return;
3396 }
3397
3398 if (target == TGSI_TEXTURE_BUFFER) {
3399 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3400 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3401 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3402 LLVMNoUnwindAttribute);
3403 } else {
3404 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3405 coords_type, sizeof(coords_type));
3406 snprintf(intrinsic_name, sizeof(intrinsic_name),
3407 "llvm.amdgcn.image.store.%s", coords_type);
3408
3409 emit_data->output[emit_data->chan] =
3410 lp_build_intrinsic(
3411 builder, intrinsic_name, emit_data->dst_type,
3412 emit_data->args, emit_data->arg_count,
3413 LLVMNoUnwindAttribute);
3414 }
3415 }
3416
3417 static void atomic_fetch_args(
3418 struct lp_build_tgsi_context * bld_base,
3419 struct lp_build_emit_data * emit_data)
3420 {
3421 struct si_shader_context *ctx = si_shader_context(bld_base);
3422 struct gallivm_state *gallivm = bld_base->base.gallivm;
3423 LLVMBuilderRef builder = gallivm->builder;
3424 const struct tgsi_full_instruction * inst = emit_data->inst;
3425 LLVMValueRef data1, data2;
3426 LLVMValueRef rsrc;
3427 LLVMValueRef tmp;
3428
3429 emit_data->dst_type = bld_base->base.elem_type;
3430
3431 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3432 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3433
3434 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3435 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3436 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3437 }
3438
3439 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3440 * of arguments, which is reversed relative to TGSI (and GLSL)
3441 */
3442 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3443 emit_data->args[emit_data->arg_count++] = data2;
3444 emit_data->args[emit_data->arg_count++] = data1;
3445
3446 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3447 LLVMValueRef offset;
3448
3449 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3450
3451 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3452 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3453
3454 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3455 offset, true);
3456 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3457 unsigned target = inst->Memory.Texture;
3458 LLVMValueRef coords;
3459
3460 image_fetch_rsrc(bld_base, &inst->Src[0],
3461 target != TGSI_TEXTURE_BUFFER, &rsrc);
3462 coords = image_fetch_coords(bld_base, inst, 1);
3463
3464 if (target == TGSI_TEXTURE_BUFFER) {
3465 rsrc = extract_rsrc_top_half(ctx, rsrc);
3466 buffer_append_args(ctx, emit_data, rsrc, coords,
3467 bld_base->uint_bld.zero, true);
3468 } else {
3469 emit_data->args[emit_data->arg_count++] = coords;
3470 emit_data->args[emit_data->arg_count++] = rsrc;
3471
3472 image_append_args(ctx, emit_data, target, true);
3473 }
3474 }
3475 }
3476
3477 static void atomic_emit_memory(struct si_shader_context *ctx,
3478 struct lp_build_emit_data *emit_data) {
3479 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3480 LLVMBuilderRef builder = gallivm->builder;
3481 const struct tgsi_full_instruction * inst = emit_data->inst;
3482 LLVMValueRef ptr, result, arg;
3483
3484 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3485
3486 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3487 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3488
3489 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3490 LLVMValueRef new_data;
3491 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3492 inst, 3, 0);
3493
3494 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3495
3496 #if HAVE_LLVM >= 0x309
3497 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3498 LLVMAtomicOrderingSequentiallyConsistent,
3499 LLVMAtomicOrderingSequentiallyConsistent,
3500 false);
3501 #endif
3502
3503 result = LLVMBuildExtractValue(builder, result, 0, "");
3504 } else {
3505 LLVMAtomicRMWBinOp op;
3506
3507 switch(inst->Instruction.Opcode) {
3508 case TGSI_OPCODE_ATOMUADD:
3509 op = LLVMAtomicRMWBinOpAdd;
3510 break;
3511 case TGSI_OPCODE_ATOMXCHG:
3512 op = LLVMAtomicRMWBinOpXchg;
3513 break;
3514 case TGSI_OPCODE_ATOMAND:
3515 op = LLVMAtomicRMWBinOpAnd;
3516 break;
3517 case TGSI_OPCODE_ATOMOR:
3518 op = LLVMAtomicRMWBinOpOr;
3519 break;
3520 case TGSI_OPCODE_ATOMXOR:
3521 op = LLVMAtomicRMWBinOpXor;
3522 break;
3523 case TGSI_OPCODE_ATOMUMIN:
3524 op = LLVMAtomicRMWBinOpUMin;
3525 break;
3526 case TGSI_OPCODE_ATOMUMAX:
3527 op = LLVMAtomicRMWBinOpUMax;
3528 break;
3529 case TGSI_OPCODE_ATOMIMIN:
3530 op = LLVMAtomicRMWBinOpMin;
3531 break;
3532 case TGSI_OPCODE_ATOMIMAX:
3533 op = LLVMAtomicRMWBinOpMax;
3534 break;
3535 default:
3536 unreachable("unknown atomic opcode");
3537 }
3538
3539 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3540 LLVMAtomicOrderingSequentiallyConsistent,
3541 false);
3542 }
3543 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3544 }
3545
3546 static void atomic_emit(
3547 const struct lp_build_tgsi_action *action,
3548 struct lp_build_tgsi_context *bld_base,
3549 struct lp_build_emit_data *emit_data)
3550 {
3551 struct si_shader_context *ctx = si_shader_context(bld_base);
3552 struct gallivm_state *gallivm = bld_base->base.gallivm;
3553 LLVMBuilderRef builder = gallivm->builder;
3554 const struct tgsi_full_instruction * inst = emit_data->inst;
3555 char intrinsic_name[40];
3556 LLVMValueRef tmp;
3557
3558 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3559 atomic_emit_memory(ctx, emit_data);
3560 return;
3561 }
3562
3563 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3564 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3565 snprintf(intrinsic_name, sizeof(intrinsic_name),
3566 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3567 } else {
3568 char coords_type[8];
3569
3570 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3571 coords_type, sizeof(coords_type));
3572 snprintf(intrinsic_name, sizeof(intrinsic_name),
3573 "llvm.amdgcn.image.atomic.%s.%s",
3574 action->intr_name, coords_type);
3575 }
3576
3577 tmp = lp_build_intrinsic(
3578 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3579 emit_data->args, emit_data->arg_count,
3580 LLVMNoUnwindAttribute);
3581 emit_data->output[emit_data->chan] =
3582 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3583 }
3584
3585 static void resq_fetch_args(
3586 struct lp_build_tgsi_context * bld_base,
3587 struct lp_build_emit_data * emit_data)
3588 {
3589 struct si_shader_context *ctx = si_shader_context(bld_base);
3590 struct gallivm_state *gallivm = bld_base->base.gallivm;
3591 const struct tgsi_full_instruction *inst = emit_data->inst;
3592 const struct tgsi_full_src_register *reg = &inst->Src[0];
3593
3594 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3595
3596 if (reg->Register.File == TGSI_FILE_BUFFER) {
3597 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
3598 emit_data->arg_count = 1;
3599 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3600 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
3601 emit_data->arg_count = 1;
3602 } else {
3603 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3604 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
3605 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3606 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3607 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3608 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
3609 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3610 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3611 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3612 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3613 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3614 emit_data->arg_count = 10;
3615 }
3616 }
3617
3618 static void resq_emit(
3619 const struct lp_build_tgsi_action *action,
3620 struct lp_build_tgsi_context *bld_base,
3621 struct lp_build_emit_data *emit_data)
3622 {
3623 struct gallivm_state *gallivm = bld_base->base.gallivm;
3624 LLVMBuilderRef builder = gallivm->builder;
3625 const struct tgsi_full_instruction *inst = emit_data->inst;
3626 LLVMValueRef out;
3627
3628 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3629 out = LLVMBuildExtractElement(builder, emit_data->args[0],
3630 lp_build_const_int32(gallivm, 2), "");
3631 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3632 out = get_buffer_size(bld_base, emit_data->args[0]);
3633 } else {
3634 out = lp_build_intrinsic(
3635 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
3636 emit_data->args, emit_data->arg_count,
3637 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3638
3639 /* Divide the number of layers by 6 to get the number of cubes. */
3640 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
3641 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
3642 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
3643
3644 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
3645 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
3646 z = LLVMBuildSDiv(builder, z, imm6, "");
3647 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
3648 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
3649 }
3650 }
3651
3652 emit_data->output[emit_data->chan] = out;
3653 }
3654
3655 static void set_tex_fetch_args(struct si_shader_context *ctx,
3656 struct lp_build_emit_data *emit_data,
3657 unsigned opcode, unsigned target,
3658 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3659 LLVMValueRef *param, unsigned count,
3660 unsigned dmask)
3661 {
3662 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3663 unsigned num_args;
3664 unsigned is_rect = target == TGSI_TEXTURE_RECT;
3665
3666 /* Pad to power of two vector */
3667 while (count < util_next_power_of_two(count))
3668 param[count++] = LLVMGetUndef(ctx->i32);
3669
3670 /* Texture coordinates. */
3671 if (count > 1)
3672 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
3673 else
3674 emit_data->args[0] = param[0];
3675
3676 /* Resource. */
3677 emit_data->args[1] = res_ptr;
3678 num_args = 2;
3679
3680 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
3681 emit_data->dst_type = ctx->v4i32;
3682 else {
3683 emit_data->dst_type = ctx->v4f32;
3684
3685 emit_data->args[num_args++] = samp_ptr;
3686 }
3687
3688 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
3689 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
3690 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
3691 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
3692 tgsi_is_array_sampler(target)); /* da */
3693 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
3694 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
3695 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
3696 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
3697
3698 emit_data->arg_count = num_args;
3699 }
3700
3701 static const struct lp_build_tgsi_action tex_action;
3702
3703 enum desc_type {
3704 DESC_IMAGE,
3705 DESC_FMASK,
3706 DESC_SAMPLER
3707 };
3708
3709 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3710 {
3711 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3712 CONST_ADDR_SPACE);
3713 }
3714
3715 /**
3716 * Load an image view, fmask view. or sampler state descriptor.
3717 */
3718 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
3719 LLVMValueRef list, LLVMValueRef index,
3720 enum desc_type type)
3721 {
3722 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3723 LLVMBuilderRef builder = gallivm->builder;
3724
3725 switch (type) {
3726 case DESC_IMAGE:
3727 /* The image is at [0:7]. */
3728 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3729 break;
3730 case DESC_FMASK:
3731 /* The FMASK is at [8:15]. */
3732 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3733 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
3734 break;
3735 case DESC_SAMPLER:
3736 /* The sampler state is at [12:15]. */
3737 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
3738 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
3739 list = LLVMBuildPointerCast(builder, list,
3740 const_array(ctx->v4i32, 0), "");
3741 break;
3742 }
3743
3744 return build_indexed_load_const(ctx, list, index);
3745 }
3746
3747 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
3748 LLVMValueRef index, enum desc_type type)
3749 {
3750 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
3751 SI_PARAM_SAMPLERS);
3752
3753 return get_sampler_desc_custom(ctx, list, index, type);
3754 }
3755
3756 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3757 *
3758 * SI-CI:
3759 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3760 * filtering manually. The driver sets img7 to a mask clearing
3761 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3762 * s_and_b32 samp0, samp0, img7
3763 *
3764 * VI:
3765 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3766 */
3767 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
3768 LLVMValueRef res, LLVMValueRef samp)
3769 {
3770 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3771 LLVMValueRef img7, samp0;
3772
3773 if (ctx->screen->b.chip_class >= VI)
3774 return samp;
3775
3776 img7 = LLVMBuildExtractElement(builder, res,
3777 LLVMConstInt(ctx->i32, 7, 0), "");
3778 samp0 = LLVMBuildExtractElement(builder, samp,
3779 LLVMConstInt(ctx->i32, 0, 0), "");
3780 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3781 return LLVMBuildInsertElement(builder, samp, samp0,
3782 LLVMConstInt(ctx->i32, 0, 0), "");
3783 }
3784
3785 static void tex_fetch_ptrs(
3786 struct lp_build_tgsi_context *bld_base,
3787 struct lp_build_emit_data *emit_data,
3788 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
3789 {
3790 struct si_shader_context *ctx = si_shader_context(bld_base);
3791 const struct tgsi_full_instruction *inst = emit_data->inst;
3792 unsigned target = inst->Texture.Texture;
3793 unsigned sampler_src;
3794 unsigned sampler_index;
3795
3796 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
3797 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
3798
3799 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
3800 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
3801 LLVMValueRef ind_index;
3802
3803 ind_index = get_bounded_indirect_index(ctx,
3804 &reg->Indirect,
3805 reg->Register.Index,
3806 SI_NUM_USER_SAMPLERS);
3807
3808 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
3809
3810 if (target == TGSI_TEXTURE_2D_MSAA ||
3811 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3812 *samp_ptr = NULL;
3813 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
3814 } else {
3815 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
3816 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3817 *fmask_ptr = NULL;
3818 }
3819 } else {
3820 *res_ptr = ctx->sampler_views[sampler_index];
3821 *samp_ptr = ctx->sampler_states[sampler_index];
3822 *fmask_ptr = ctx->fmasks[sampler_index];
3823 }
3824 }
3825
3826 static void tex_fetch_args(
3827 struct lp_build_tgsi_context *bld_base,
3828 struct lp_build_emit_data *emit_data)
3829 {
3830 struct si_shader_context *ctx = si_shader_context(bld_base);
3831 struct gallivm_state *gallivm = bld_base->base.gallivm;
3832 LLVMBuilderRef builder = gallivm->builder;
3833 const struct tgsi_full_instruction *inst = emit_data->inst;
3834 unsigned opcode = inst->Instruction.Opcode;
3835 unsigned target = inst->Texture.Texture;
3836 LLVMValueRef coords[5], derivs[6];
3837 LLVMValueRef address[16];
3838 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3839 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
3840 unsigned count = 0;
3841 unsigned chan;
3842 unsigned num_deriv_channels = 0;
3843 bool has_offset = inst->Texture.NumOffsets > 0;
3844 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3845 unsigned dmask = 0xf;
3846
3847 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3848
3849 if (opcode == TGSI_OPCODE_TXQ) {
3850 if (target == TGSI_TEXTURE_BUFFER) {
3851 /* Read the size from the buffer descriptor directly. */
3852 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3853 emit_data->args[0] = get_buffer_size(bld_base, res);
3854 return;
3855 }
3856
3857 /* Textures - set the mip level. */
3858 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
3859
3860 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3861 NULL, address, count, 0xf);
3862 return;
3863 }
3864
3865 if (target == TGSI_TEXTURE_BUFFER) {
3866 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3867
3868 /* Bitcast and truncate v8i32 to v16i8. */
3869 LLVMValueRef res = res_ptr;
3870 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
3871 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
3872 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
3873
3874 emit_data->dst_type = ctx->v4f32;
3875 emit_data->args[0] = res;
3876 emit_data->args[1] = bld_base->uint_bld.zero;
3877 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3878 emit_data->arg_count = 3;
3879 return;
3880 }
3881
3882 /* Fetch and project texture coordinates */
3883 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
3884 for (chan = 0; chan < 3; chan++ ) {
3885 coords[chan] = lp_build_emit_fetch(bld_base,
3886 emit_data->inst, 0,
3887 chan);
3888 if (opcode == TGSI_OPCODE_TXP)
3889 coords[chan] = lp_build_emit_llvm_binary(bld_base,
3890 TGSI_OPCODE_DIV,
3891 coords[chan],
3892 coords[3]);
3893 }
3894
3895 if (opcode == TGSI_OPCODE_TXP)
3896 coords[3] = bld_base->base.one;
3897
3898 /* Pack offsets. */
3899 if (has_offset && opcode != TGSI_OPCODE_TXF) {
3900 /* The offsets are six-bit signed integers packed like this:
3901 * X=[5:0], Y=[13:8], and Z=[21:16].
3902 */
3903 LLVMValueRef offset[3], pack;
3904
3905 assert(inst->Texture.NumOffsets == 1);
3906
3907 for (chan = 0; chan < 3; chan++) {
3908 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
3909 emit_data->inst, 0, chan);
3910 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
3911 lp_build_const_int32(gallivm, 0x3f), "");
3912 if (chan)
3913 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
3914 lp_build_const_int32(gallivm, chan*8), "");
3915 }
3916
3917 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
3918 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
3919 address[count++] = pack;
3920 }
3921
3922 /* Pack LOD bias value */
3923 if (opcode == TGSI_OPCODE_TXB)
3924 address[count++] = coords[3];
3925 if (opcode == TGSI_OPCODE_TXB2)
3926 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3927
3928 /* Pack depth comparison value */
3929 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
3930 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
3931 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3932 } else {
3933 assert(ref_pos >= 0);
3934 address[count++] = coords[ref_pos];
3935 }
3936 }
3937
3938 /* Pack user derivatives */
3939 if (opcode == TGSI_OPCODE_TXD) {
3940 int param, num_src_deriv_channels;
3941
3942 switch (target) {
3943 case TGSI_TEXTURE_3D:
3944 num_src_deriv_channels = 3;
3945 num_deriv_channels = 3;
3946 break;
3947 case TGSI_TEXTURE_2D:
3948 case TGSI_TEXTURE_SHADOW2D:
3949 case TGSI_TEXTURE_RECT:
3950 case TGSI_TEXTURE_SHADOWRECT:
3951 case TGSI_TEXTURE_2D_ARRAY:
3952 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3953 num_src_deriv_channels = 2;
3954 num_deriv_channels = 2;
3955 break;
3956 case TGSI_TEXTURE_CUBE:
3957 case TGSI_TEXTURE_SHADOWCUBE:
3958 case TGSI_TEXTURE_CUBE_ARRAY:
3959 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
3960 /* Cube derivatives will be converted to 2D. */
3961 num_src_deriv_channels = 3;
3962 num_deriv_channels = 2;
3963 break;
3964 case TGSI_TEXTURE_1D:
3965 case TGSI_TEXTURE_SHADOW1D:
3966 case TGSI_TEXTURE_1D_ARRAY:
3967 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3968 num_src_deriv_channels = 1;
3969 num_deriv_channels = 1;
3970 break;
3971 default:
3972 unreachable("invalid target");
3973 }
3974
3975 for (param = 0; param < 2; param++)
3976 for (chan = 0; chan < num_src_deriv_channels; chan++)
3977 derivs[param * num_src_deriv_channels + chan] =
3978 lp_build_emit_fetch(bld_base, inst, param+1, chan);
3979 }
3980
3981 if (target == TGSI_TEXTURE_CUBE ||
3982 target == TGSI_TEXTURE_CUBE_ARRAY ||
3983 target == TGSI_TEXTURE_SHADOWCUBE ||
3984 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
3985 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
3986
3987 if (opcode == TGSI_OPCODE_TXD)
3988 for (int i = 0; i < num_deriv_channels * 2; i++)
3989 address[count++] = derivs[i];
3990
3991 /* Pack texture coordinates */
3992 address[count++] = coords[0];
3993 if (num_coords > 1)
3994 address[count++] = coords[1];
3995 if (num_coords > 2)
3996 address[count++] = coords[2];
3997
3998 /* Pack LOD or sample index */
3999 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4000 address[count++] = coords[3];
4001 else if (opcode == TGSI_OPCODE_TXL2)
4002 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4003
4004 if (count > 16) {
4005 assert(!"Cannot handle more than 16 texture address parameters");
4006 count = 16;
4007 }
4008
4009 for (chan = 0; chan < count; chan++ ) {
4010 address[chan] = LLVMBuildBitCast(gallivm->builder,
4011 address[chan], ctx->i32, "");
4012 }
4013
4014 /* Adjust the sample index according to FMASK.
4015 *
4016 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4017 * which is the identity mapping. Each nibble says which physical sample
4018 * should be fetched to get that sample.
4019 *
4020 * For example, 0x11111100 means there are only 2 samples stored and
4021 * the second sample covers 3/4 of the pixel. When reading samples 0
4022 * and 1, return physical sample 0 (determined by the first two 0s
4023 * in FMASK), otherwise return physical sample 1.
4024 *
4025 * The sample index should be adjusted as follows:
4026 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4027 */
4028 if (target == TGSI_TEXTURE_2D_MSAA ||
4029 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4030 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4031 struct lp_build_emit_data txf_emit_data = *emit_data;
4032 LLVMValueRef txf_address[4];
4033 unsigned txf_count = count;
4034 struct tgsi_full_instruction inst = {};
4035
4036 memcpy(txf_address, address, sizeof(txf_address));
4037
4038 if (target == TGSI_TEXTURE_2D_MSAA) {
4039 txf_address[2] = bld_base->uint_bld.zero;
4040 }
4041 txf_address[3] = bld_base->uint_bld.zero;
4042
4043 /* Read FMASK using TXF. */
4044 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4045 inst.Texture.Texture = target;
4046 txf_emit_data.inst = &inst;
4047 txf_emit_data.chan = 0;
4048 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4049 target, fmask_ptr, NULL,
4050 txf_address, txf_count, 0xf);
4051 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4052
4053 /* Initialize some constants. */
4054 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4055 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4056
4057 /* Apply the formula. */
4058 LLVMValueRef fmask =
4059 LLVMBuildExtractElement(gallivm->builder,
4060 txf_emit_data.output[0],
4061 uint_bld->zero, "");
4062
4063 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4064
4065 LLVMValueRef sample_index4 =
4066 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4067
4068 LLVMValueRef shifted_fmask =
4069 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4070
4071 LLVMValueRef final_sample =
4072 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4073
4074 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4075 * resource descriptor is 0 (invalid),
4076 */
4077 LLVMValueRef fmask_desc =
4078 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4079 ctx->v8i32, "");
4080
4081 LLVMValueRef fmask_word1 =
4082 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4083 uint_bld->one, "");
4084
4085 LLVMValueRef word1_is_nonzero =
4086 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4087 fmask_word1, uint_bld->zero, "");
4088
4089 /* Replace the MSAA sample index. */
4090 address[sample_chan] =
4091 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4092 final_sample, address[sample_chan], "");
4093 }
4094
4095 if (opcode == TGSI_OPCODE_TXF) {
4096 /* add tex offsets */
4097 if (inst->Texture.NumOffsets) {
4098 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4099 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4100 const struct tgsi_texture_offset *off = inst->TexOffsets;
4101
4102 assert(inst->Texture.NumOffsets == 1);
4103
4104 switch (target) {
4105 case TGSI_TEXTURE_3D:
4106 address[2] = lp_build_add(uint_bld, address[2],
4107 bld->immediates[off->Index][off->SwizzleZ]);
4108 /* fall through */
4109 case TGSI_TEXTURE_2D:
4110 case TGSI_TEXTURE_SHADOW2D:
4111 case TGSI_TEXTURE_RECT:
4112 case TGSI_TEXTURE_SHADOWRECT:
4113 case TGSI_TEXTURE_2D_ARRAY:
4114 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4115 address[1] =
4116 lp_build_add(uint_bld, address[1],
4117 bld->immediates[off->Index][off->SwizzleY]);
4118 /* fall through */
4119 case TGSI_TEXTURE_1D:
4120 case TGSI_TEXTURE_SHADOW1D:
4121 case TGSI_TEXTURE_1D_ARRAY:
4122 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4123 address[0] =
4124 lp_build_add(uint_bld, address[0],
4125 bld->immediates[off->Index][off->SwizzleX]);
4126 break;
4127 /* texture offsets do not apply to other texture targets */
4128 }
4129 }
4130 }
4131
4132 if (opcode == TGSI_OPCODE_TG4) {
4133 unsigned gather_comp = 0;
4134
4135 /* DMASK was repurposed for GATHER4. 4 components are always
4136 * returned and DMASK works like a swizzle - it selects
4137 * the component to fetch. The only valid DMASK values are
4138 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4139 * (red,red,red,red) etc.) The ISA document doesn't mention
4140 * this.
4141 */
4142
4143 /* Get the component index from src1.x for Gather4. */
4144 if (!tgsi_is_shadow_target(target)) {
4145 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4146 LLVMValueRef comp_imm;
4147 struct tgsi_src_register src1 = inst->Src[1].Register;
4148
4149 assert(src1.File == TGSI_FILE_IMMEDIATE);
4150
4151 comp_imm = imms[src1.Index][src1.SwizzleX];
4152 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4153 gather_comp = CLAMP(gather_comp, 0, 3);
4154 }
4155
4156 dmask = 1 << gather_comp;
4157 }
4158
4159 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4160 samp_ptr, address, count, dmask);
4161 }
4162
4163 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4164 struct lp_build_tgsi_context *bld_base,
4165 struct lp_build_emit_data *emit_data)
4166 {
4167 struct lp_build_context *base = &bld_base->base;
4168 unsigned opcode = emit_data->inst->Instruction.Opcode;
4169 unsigned target = emit_data->inst->Texture.Texture;
4170 char intr_name[127];
4171 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4172 bool is_shadow = tgsi_is_shadow_target(target);
4173 char type[64];
4174 const char *name = "llvm.SI.image.sample";
4175 const char *infix = "";
4176
4177 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
4178 /* Just return the buffer size. */
4179 emit_data->output[emit_data->chan] = emit_data->args[0];
4180 return;
4181 }
4182
4183 if (target == TGSI_TEXTURE_BUFFER) {
4184 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4185 base->gallivm->builder,
4186 "llvm.SI.vs.load.input", emit_data->dst_type,
4187 emit_data->args, emit_data->arg_count,
4188 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4189 return;
4190 }
4191
4192 switch (opcode) {
4193 case TGSI_OPCODE_TXF:
4194 name = target == TGSI_TEXTURE_2D_MSAA ||
4195 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4196 "llvm.SI.image.load" :
4197 "llvm.SI.image.load.mip";
4198 is_shadow = false;
4199 has_offset = false;
4200 break;
4201 case TGSI_OPCODE_TXQ:
4202 name = "llvm.SI.getresinfo";
4203 is_shadow = false;
4204 has_offset = false;
4205 break;
4206 case TGSI_OPCODE_LODQ:
4207 name = "llvm.SI.getlod";
4208 is_shadow = false;
4209 has_offset = false;
4210 break;
4211 case TGSI_OPCODE_TEX:
4212 case TGSI_OPCODE_TEX2:
4213 case TGSI_OPCODE_TXP:
4214 break;
4215 case TGSI_OPCODE_TXB:
4216 case TGSI_OPCODE_TXB2:
4217 infix = ".b";
4218 break;
4219 case TGSI_OPCODE_TXL:
4220 case TGSI_OPCODE_TXL2:
4221 infix = ".l";
4222 break;
4223 case TGSI_OPCODE_TXD:
4224 infix = ".d";
4225 break;
4226 case TGSI_OPCODE_TG4:
4227 name = "llvm.SI.gather4";
4228 break;
4229 default:
4230 assert(0);
4231 return;
4232 }
4233
4234 /* Add the type and suffixes .c, .o if needed. */
4235 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4236 sprintf(intr_name, "%s%s%s%s.%s",
4237 name, is_shadow ? ".c" : "", infix,
4238 has_offset ? ".o" : "", type);
4239
4240 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4241 base->gallivm->builder, intr_name, emit_data->dst_type,
4242 emit_data->args, emit_data->arg_count,
4243 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4244
4245 /* Divide the number of layers by 6 to get the number of cubes. */
4246 if (opcode == TGSI_OPCODE_TXQ &&
4247 (target == TGSI_TEXTURE_CUBE_ARRAY ||
4248 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
4249 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4250 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4251 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4252
4253 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4254 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4255 z = LLVMBuildSDiv(builder, z, six, "");
4256
4257 emit_data->output[emit_data->chan] =
4258 LLVMBuildInsertElement(builder, v4, z, two, "");
4259 }
4260 }
4261
4262 static void si_llvm_emit_txqs(
4263 const struct lp_build_tgsi_action *action,
4264 struct lp_build_tgsi_context *bld_base,
4265 struct lp_build_emit_data *emit_data)
4266 {
4267 struct si_shader_context *ctx = si_shader_context(bld_base);
4268 struct gallivm_state *gallivm = bld_base->base.gallivm;
4269 LLVMBuilderRef builder = gallivm->builder;
4270 LLVMValueRef res, samples;
4271 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4272
4273 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4274
4275
4276 /* Read the samples from the descriptor directly. */
4277 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4278 samples = LLVMBuildExtractElement(
4279 builder, res,
4280 lp_build_const_int32(gallivm, 3), "");
4281 samples = LLVMBuildLShr(builder, samples,
4282 lp_build_const_int32(gallivm, 16), "");
4283 samples = LLVMBuildAnd(builder, samples,
4284 lp_build_const_int32(gallivm, 0xf), "");
4285 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4286 samples, "");
4287
4288 emit_data->output[emit_data->chan] = samples;
4289 }
4290
4291 /*
4292 * SI implements derivatives using the local data store (LDS)
4293 * All writes to the LDS happen in all executing threads at
4294 * the same time. TID is the Thread ID for the current
4295 * thread and is a value between 0 and 63, representing
4296 * the thread's position in the wavefront.
4297 *
4298 * For the pixel shader threads are grouped into quads of four pixels.
4299 * The TIDs of the pixels of a quad are:
4300 *
4301 * +------+------+
4302 * |4n + 0|4n + 1|
4303 * +------+------+
4304 * |4n + 2|4n + 3|
4305 * +------+------+
4306 *
4307 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4308 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4309 * the current pixel's column, and masking with 0xfffffffe yields the TID
4310 * of the left pixel of the current pixel's row.
4311 *
4312 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4313 * adding 2 yields the TID of the pixel below the top pixel.
4314 */
4315 /* masks for thread ID. */
4316 #define TID_MASK_TOP_LEFT 0xfffffffc
4317 #define TID_MASK_TOP 0xfffffffd
4318 #define TID_MASK_LEFT 0xfffffffe
4319
4320 static void si_llvm_emit_ddxy(
4321 const struct lp_build_tgsi_action *action,
4322 struct lp_build_tgsi_context *bld_base,
4323 struct lp_build_emit_data *emit_data)
4324 {
4325 struct si_shader_context *ctx = si_shader_context(bld_base);
4326 struct gallivm_state *gallivm = bld_base->base.gallivm;
4327 const struct tgsi_full_instruction *inst = emit_data->inst;
4328 unsigned opcode = inst->Instruction.Opcode;
4329 LLVMValueRef indices[2];
4330 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4331 LLVMValueRef tl, trbl, result[4];
4332 unsigned swizzle[4];
4333 unsigned c;
4334 int idx;
4335 unsigned mask;
4336
4337 indices[0] = bld_base->uint_bld.zero;
4338 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
4339 NULL, 0, LLVMReadNoneAttribute);
4340 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4341 indices, 2, "");
4342
4343 if (opcode == TGSI_OPCODE_DDX_FINE)
4344 mask = TID_MASK_LEFT;
4345 else if (opcode == TGSI_OPCODE_DDY_FINE)
4346 mask = TID_MASK_TOP;
4347 else
4348 mask = TID_MASK_TOP_LEFT;
4349
4350 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
4351 lp_build_const_int32(gallivm, mask), "");
4352 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4353 indices, 2, "");
4354
4355 /* for DDX we want to next X pixel, DDY next Y pixel. */
4356 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4357 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
4358 lp_build_const_int32(gallivm, idx), "");
4359 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4360 indices, 2, "");
4361
4362 for (c = 0; c < 4; ++c) {
4363 unsigned i;
4364
4365 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4366 for (i = 0; i < c; ++i) {
4367 if (swizzle[i] == swizzle[c]) {
4368 result[c] = result[i];
4369 break;
4370 }
4371 }
4372 if (i != c)
4373 continue;
4374
4375 LLVMBuildStore(gallivm->builder,
4376 LLVMBuildBitCast(gallivm->builder,
4377 lp_build_emit_fetch(bld_base, inst, 0, c),
4378 ctx->i32, ""),
4379 store_ptr);
4380
4381 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4382 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4383
4384 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4385 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4386
4387 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4388 }
4389
4390 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4391 }
4392
4393 /*
4394 * this takes an I,J coordinate pair,
4395 * and works out the X and Y derivatives.
4396 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4397 */
4398 static LLVMValueRef si_llvm_emit_ddxy_interp(
4399 struct lp_build_tgsi_context *bld_base,
4400 LLVMValueRef interp_ij)
4401 {
4402 struct si_shader_context *ctx = si_shader_context(bld_base);
4403 struct gallivm_state *gallivm = bld_base->base.gallivm;
4404 LLVMValueRef indices[2];
4405 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4406 LLVMValueRef tl, tr, bl, result[4];
4407 unsigned c;
4408
4409 indices[0] = bld_base->uint_bld.zero;
4410 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
4411 NULL, 0, LLVMReadNoneAttribute);
4412 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4413 indices, 2, "");
4414
4415 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4416 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4417
4418 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4419 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4420
4421 indices[1] = temp;
4422 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4423 indices, 2, "");
4424
4425 indices[1] = temp2;
4426 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4427 indices, 2, "");
4428
4429 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4430 lp_build_const_int32(gallivm, 1), "");
4431 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4432 indices, 2, "");
4433
4434 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4435 lp_build_const_int32(gallivm, 2), "");
4436 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4437 indices, 2, "");
4438
4439 for (c = 0; c < 2; ++c) {
4440 LLVMValueRef store_val;
4441 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4442
4443 store_val = LLVMBuildExtractElement(gallivm->builder,
4444 interp_ij, c_ll, "");
4445 LLVMBuildStore(gallivm->builder,
4446 store_val,
4447 store_ptr);
4448
4449 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4450 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4451
4452 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
4453 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
4454
4455 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
4456
4457 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
4458 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4459
4460 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
4461 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
4462
4463 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
4464 }
4465
4466 return lp_build_gather_values(gallivm, result, 4);
4467 }
4468
4469 static void interp_fetch_args(
4470 struct lp_build_tgsi_context *bld_base,
4471 struct lp_build_emit_data *emit_data)
4472 {
4473 struct si_shader_context *ctx = si_shader_context(bld_base);
4474 struct gallivm_state *gallivm = bld_base->base.gallivm;
4475 const struct tgsi_full_instruction *inst = emit_data->inst;
4476
4477 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4478 /* offset is in second src, first two channels */
4479 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4480 emit_data->inst, 1,
4481 TGSI_CHAN_X);
4482 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4483 emit_data->inst, 1,
4484 TGSI_CHAN_Y);
4485 emit_data->arg_count = 2;
4486 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4487 LLVMValueRef sample_position;
4488 LLVMValueRef sample_id;
4489 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4490
4491 /* fetch sample ID, then fetch its sample position,
4492 * and place into first two channels.
4493 */
4494 sample_id = lp_build_emit_fetch(bld_base,
4495 emit_data->inst, 1, TGSI_CHAN_X);
4496 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4497 ctx->i32, "");
4498 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4499
4500 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4501 sample_position,
4502 lp_build_const_int32(gallivm, 0), "");
4503
4504 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4505 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4506 sample_position,
4507 lp_build_const_int32(gallivm, 1), "");
4508 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4509 emit_data->arg_count = 2;
4510 }
4511 }
4512
4513 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4514 struct lp_build_tgsi_context *bld_base,
4515 struct lp_build_emit_data *emit_data)
4516 {
4517 struct si_shader_context *ctx = si_shader_context(bld_base);
4518 struct si_shader *shader = ctx->shader;
4519 struct gallivm_state *gallivm = bld_base->base.gallivm;
4520 LLVMValueRef interp_param;
4521 const struct tgsi_full_instruction *inst = emit_data->inst;
4522 const char *intr_name;
4523 int input_index = inst->Src[0].Register.Index;
4524 int chan;
4525 int i;
4526 LLVMValueRef attr_number;
4527 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
4528 int interp_param_idx;
4529 unsigned interp = shader->selector->info.input_interpolate[input_index];
4530 unsigned location;
4531
4532 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4533
4534 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4535 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4536 location = TGSI_INTERPOLATE_LOC_CENTER;
4537 else
4538 location = TGSI_INTERPOLATE_LOC_CENTROID;
4539
4540 interp_param_idx = lookup_interp_param_index(interp, location);
4541 if (interp_param_idx == -1)
4542 return;
4543 else if (interp_param_idx)
4544 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
4545 else
4546 interp_param = NULL;
4547
4548 attr_number = lp_build_const_int32(gallivm, input_index);
4549
4550 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4551 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4552 LLVMValueRef ij_out[2];
4553 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4554
4555 /*
4556 * take the I then J parameters, and the DDX/Y for it, and
4557 * calculate the IJ inputs for the interpolator.
4558 * temp1 = ddx * offset/sample.x + I;
4559 * interp_param.I = ddy * offset/sample.y + temp1;
4560 * temp1 = ddx * offset/sample.x + J;
4561 * interp_param.J = ddy * offset/sample.y + temp1;
4562 */
4563 for (i = 0; i < 2; i++) {
4564 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4565 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4566 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4567 ddxy_out, ix_ll, "");
4568 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4569 ddxy_out, iy_ll, "");
4570 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4571 interp_param, ix_ll, "");
4572 LLVMValueRef temp1, temp2;
4573
4574 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4575 ctx->f32, "");
4576
4577 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4578
4579 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4580
4581 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4582
4583 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4584
4585 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
4586 temp2, ctx->i32, "");
4587 }
4588 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4589 }
4590
4591 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4592 for (chan = 0; chan < 2; chan++) {
4593 LLVMValueRef args[4];
4594 LLVMValueRef llvm_chan;
4595 unsigned schan;
4596
4597 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4598 llvm_chan = lp_build_const_int32(gallivm, schan);
4599
4600 args[0] = llvm_chan;
4601 args[1] = attr_number;
4602 args[2] = params;
4603 args[3] = interp_param;
4604
4605 emit_data->output[chan] =
4606 lp_build_intrinsic(gallivm->builder, intr_name,
4607 ctx->f32, args, args[3] ? 4 : 3,
4608 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4609 }
4610 }
4611
4612 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4613 struct lp_build_emit_data *emit_data)
4614 {
4615 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4616 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4617 unsigned stream;
4618
4619 assert(src0.File == TGSI_FILE_IMMEDIATE);
4620
4621 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
4622 return stream;
4623 }
4624
4625 /* Emit one vertex from the geometry shader */
4626 static void si_llvm_emit_vertex(
4627 const struct lp_build_tgsi_action *action,
4628 struct lp_build_tgsi_context *bld_base,
4629 struct lp_build_emit_data *emit_data)
4630 {
4631 struct si_shader_context *ctx = si_shader_context(bld_base);
4632 struct lp_build_context *uint = &bld_base->uint_bld;
4633 struct si_shader *shader = ctx->shader;
4634 struct tgsi_shader_info *info = &shader->selector->info;
4635 struct gallivm_state *gallivm = bld_base->base.gallivm;
4636 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
4637 SI_PARAM_GS2VS_OFFSET);
4638 LLVMValueRef gs_next_vertex;
4639 LLVMValueRef can_emit, kill;
4640 LLVMValueRef args[2];
4641 unsigned chan;
4642 int i;
4643 unsigned stream;
4644
4645 stream = si_llvm_get_stream(bld_base, emit_data);
4646
4647 /* Write vertex attribute values to GSVS ring */
4648 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
4649 ctx->gs_next_vertex[stream],
4650 "");
4651
4652 /* If this thread has already emitted the declared maximum number of
4653 * vertices, kill it: excessive vertex emissions are not supposed to
4654 * have any effect, and GS threads have no externally observable
4655 * effects other than emitting vertices.
4656 */
4657 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
4658 lp_build_const_int32(gallivm,
4659 shader->selector->gs_max_out_vertices), "");
4660 kill = lp_build_select(&bld_base->base, can_emit,
4661 lp_build_const_float(gallivm, 1.0f),
4662 lp_build_const_float(gallivm, -1.0f));
4663
4664 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4665 ctx->voidt, &kill, 1, 0);
4666
4667 for (i = 0; i < info->num_outputs; i++) {
4668 LLVMValueRef *out_ptr =
4669 ctx->radeon_bld.soa.outputs[i];
4670
4671 for (chan = 0; chan < 4; chan++) {
4672 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
4673 LLVMValueRef voffset =
4674 lp_build_const_int32(gallivm, (i * 4 + chan) *
4675 shader->selector->gs_max_out_vertices);
4676
4677 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4678 voffset = lp_build_mul_imm(uint, voffset, 4);
4679
4680 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
4681
4682 build_tbuffer_store(ctx,
4683 ctx->gsvs_ring[stream],
4684 out_val, 1,
4685 voffset, soffset, 0,
4686 V_008F0C_BUF_DATA_FORMAT_32,
4687 V_008F0C_BUF_NUM_FORMAT_UINT,
4688 1, 0, 1, 1, 0);
4689 }
4690 }
4691 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4692 lp_build_const_int32(gallivm, 1));
4693
4694 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4695
4696 /* Signal vertex emission */
4697 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
4698 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4699 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4700 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4701 }
4702
4703 /* Cut one primitive from the geometry shader */
4704 static void si_llvm_emit_primitive(
4705 const struct lp_build_tgsi_action *action,
4706 struct lp_build_tgsi_context *bld_base,
4707 struct lp_build_emit_data *emit_data)
4708 {
4709 struct si_shader_context *ctx = si_shader_context(bld_base);
4710 struct gallivm_state *gallivm = bld_base->base.gallivm;
4711 LLVMValueRef args[2];
4712 unsigned stream;
4713
4714 /* Signal primitive cut */
4715 stream = si_llvm_get_stream(bld_base, emit_data);
4716 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
4717 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4718 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4719 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4720 }
4721
4722 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4723 struct lp_build_tgsi_context *bld_base,
4724 struct lp_build_emit_data *emit_data)
4725 {
4726 struct si_shader_context *ctx = si_shader_context(bld_base);
4727 struct gallivm_state *gallivm = bld_base->base.gallivm;
4728
4729 /* The real barrier instruction isn’t needed, because an entire patch
4730 * always fits into a single wave.
4731 */
4732 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
4733 emit_optimization_barrier(ctx);
4734 return;
4735 }
4736
4737 lp_build_intrinsic(gallivm->builder,
4738 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
4739 : "llvm.AMDGPU.barrier.local",
4740 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
4741 }
4742
4743 static const struct lp_build_tgsi_action tex_action = {
4744 .fetch_args = tex_fetch_args,
4745 .emit = build_tex_intrinsic,
4746 };
4747
4748 static const struct lp_build_tgsi_action interp_action = {
4749 .fetch_args = interp_fetch_args,
4750 .emit = build_interp_intrinsic,
4751 };
4752
4753 static void si_create_function(struct si_shader_context *ctx,
4754 LLVMTypeRef *returns, unsigned num_returns,
4755 LLVMTypeRef *params, unsigned num_params,
4756 int last_array_pointer, int last_sgpr)
4757 {
4758 int i;
4759
4760 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
4761 params, num_params);
4762 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
4763 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
4764
4765 for (i = 0; i <= last_sgpr; ++i) {
4766 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
4767
4768 /* We tell llvm that array inputs are passed by value to allow Sinking pass
4769 * to move load. Inputs are constant so this is fine. */
4770 if (i <= last_array_pointer)
4771 LLVMAddAttribute(P, LLVMByValAttribute);
4772 else
4773 LLVMAddAttribute(P, LLVMInRegAttribute);
4774 }
4775 }
4776
4777 static void create_meta_data(struct si_shader_context *ctx)
4778 {
4779 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
4780 LLVMValueRef args[3];
4781
4782 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
4783 args[1] = 0;
4784 args[2] = lp_build_const_int32(gallivm, 1);
4785
4786 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
4787 }
4788
4789 static void declare_streamout_params(struct si_shader_context *ctx,
4790 struct pipe_stream_output_info *so,
4791 LLVMTypeRef *params, LLVMTypeRef i32,
4792 unsigned *num_params)
4793 {
4794 int i;
4795
4796 /* Streamout SGPRs. */
4797 if (so->num_outputs) {
4798 params[ctx->param_streamout_config = (*num_params)++] = i32;
4799 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
4800 }
4801 /* A streamout buffer offset is loaded if the stride is non-zero. */
4802 for (i = 0; i < 4; i++) {
4803 if (!so->stride[i])
4804 continue;
4805
4806 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
4807 }
4808 }
4809
4810 static unsigned llvm_get_type_size(LLVMTypeRef type)
4811 {
4812 LLVMTypeKind kind = LLVMGetTypeKind(type);
4813
4814 switch (kind) {
4815 case LLVMIntegerTypeKind:
4816 return LLVMGetIntTypeWidth(type) / 8;
4817 case LLVMFloatTypeKind:
4818 return 4;
4819 case LLVMPointerTypeKind:
4820 return 8;
4821 case LLVMVectorTypeKind:
4822 return LLVMGetVectorSize(type) *
4823 llvm_get_type_size(LLVMGetElementType(type));
4824 default:
4825 assert(0);
4826 return 0;
4827 }
4828 }
4829
4830 static void declare_tess_lds(struct si_shader_context *ctx)
4831 {
4832 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4833 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
4834
4835 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
4836 unsigned vertex_data_dw_size = 32*32*4;
4837 unsigned patch_data_dw_size = 32*4;
4838 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
4839 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
4840 unsigned lds_dwords = patch_dw_size;
4841
4842 /* The actual size is computed outside of the shader to reduce
4843 * the number of shader variants. */
4844 ctx->lds =
4845 LLVMAddGlobalInAddressSpace(gallivm->module,
4846 LLVMArrayType(i32, lds_dwords),
4847 "tess_lds",
4848 LOCAL_ADDR_SPACE);
4849 }
4850
4851 static void create_function(struct si_shader_context *ctx)
4852 {
4853 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4854 struct gallivm_state *gallivm = bld_base->base.gallivm;
4855 struct si_shader *shader = ctx->shader;
4856 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
4857 LLVMTypeRef returns[16+32*4];
4858 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
4859 unsigned num_returns = 0;
4860
4861 v3i32 = LLVMVectorType(ctx->i32, 3);
4862
4863 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
4864 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
4865 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
4866 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
4867 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
4868 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
4869
4870 switch (ctx->type) {
4871 case TGSI_PROCESSOR_VERTEX:
4872 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
4873 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
4874 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
4875 params[SI_PARAM_START_INSTANCE] = ctx->i32;
4876 num_params = SI_PARAM_START_INSTANCE+1;
4877
4878 if (shader->key.vs.as_es) {
4879 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4880 } else if (shader->key.vs.as_ls) {
4881 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
4882 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
4883 } else {
4884 if (ctx->is_gs_copy_shader) {
4885 last_array_pointer = SI_PARAM_CONST_BUFFERS;
4886 num_params = SI_PARAM_CONST_BUFFERS+1;
4887 } else {
4888 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
4889 num_params = SI_PARAM_VS_STATE_BITS+1;
4890 }
4891
4892 /* The locations of the other parameters are assigned dynamically. */
4893 declare_streamout_params(ctx, &shader->selector->so,
4894 params, ctx->i32, &num_params);
4895 }
4896
4897 last_sgpr = num_params-1;
4898
4899 /* VGPRs */
4900 params[ctx->param_vertex_id = num_params++] = ctx->i32;
4901 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
4902 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
4903 params[ctx->param_instance_id = num_params++] = ctx->i32;
4904
4905 if (!ctx->is_monolithic &&
4906 !ctx->is_gs_copy_shader) {
4907 /* Vertex load indices. */
4908 ctx->param_vertex_index0 = num_params;
4909
4910 for (i = 0; i < shader->selector->info.num_inputs; i++)
4911 params[num_params++] = ctx->i32;
4912
4913 /* PrimitiveID output. */
4914 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
4915 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4916 returns[num_returns++] = ctx->f32;
4917 }
4918 break;
4919
4920 case TGSI_PROCESSOR_TESS_CTRL:
4921 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4922 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4923 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
4924 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
4925 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
4926
4927 /* VGPRs */
4928 params[SI_PARAM_PATCH_ID] = ctx->i32;
4929 params[SI_PARAM_REL_IDS] = ctx->i32;
4930 num_params = SI_PARAM_REL_IDS+1;
4931
4932 if (!ctx->is_monolithic) {
4933 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
4934 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
4935 returns[num_returns++] = ctx->i32; /* SGPRs */
4936
4937 for (i = 0; i < 3; i++)
4938 returns[num_returns++] = ctx->f32; /* VGPRs */
4939 }
4940 break;
4941
4942 case TGSI_PROCESSOR_TESS_EVAL:
4943 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4944 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4945 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
4946
4947 if (shader->key.tes.as_es) {
4948 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4949 } else {
4950 declare_streamout_params(ctx, &shader->selector->so,
4951 params, ctx->i32, &num_params);
4952 }
4953 last_sgpr = num_params - 1;
4954
4955 /* VGPRs */
4956 params[ctx->param_tes_u = num_params++] = ctx->f32;
4957 params[ctx->param_tes_v = num_params++] = ctx->f32;
4958 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
4959 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
4960
4961 /* PrimitiveID output. */
4962 if (!ctx->is_monolithic && !shader->key.tes.as_es)
4963 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4964 returns[num_returns++] = ctx->f32;
4965 break;
4966
4967 case TGSI_PROCESSOR_GEOMETRY:
4968 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
4969 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
4970 last_sgpr = SI_PARAM_GS_WAVE_ID;
4971
4972 /* VGPRs */
4973 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
4974 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
4975 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
4976 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
4977 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
4978 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
4979 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
4980 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
4981 num_params = SI_PARAM_GS_INSTANCE_ID+1;
4982 break;
4983
4984 case TGSI_PROCESSOR_FRAGMENT:
4985 params[SI_PARAM_ALPHA_REF] = ctx->f32;
4986 params[SI_PARAM_PRIM_MASK] = ctx->i32;
4987 last_sgpr = SI_PARAM_PRIM_MASK;
4988 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
4989 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
4990 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
4991 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
4992 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
4993 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
4994 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
4995 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
4996 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
4997 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
4998 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
4999 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5000 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5001 params[SI_PARAM_ANCILLARY] = ctx->i32;
5002 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5003 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5004 num_params = SI_PARAM_POS_FIXED_PT+1;
5005
5006 if (!ctx->is_monolithic) {
5007 /* Color inputs from the prolog. */
5008 if (shader->selector->info.colors_read) {
5009 unsigned num_color_elements =
5010 util_bitcount(shader->selector->info.colors_read);
5011
5012 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5013 for (i = 0; i < num_color_elements; i++)
5014 params[num_params++] = ctx->f32;
5015 }
5016
5017 /* Outputs for the epilog. */
5018 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5019 num_returns =
5020 num_return_sgprs +
5021 util_bitcount(shader->selector->info.colors_written) * 4 +
5022 shader->selector->info.writes_z +
5023 shader->selector->info.writes_stencil +
5024 shader->selector->info.writes_samplemask +
5025 1 /* SampleMaskIn */;
5026
5027 num_returns = MAX2(num_returns,
5028 num_return_sgprs +
5029 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5030
5031 for (i = 0; i < num_return_sgprs; i++)
5032 returns[i] = ctx->i32;
5033 for (; i < num_returns; i++)
5034 returns[i] = ctx->f32;
5035 }
5036 break;
5037
5038 case TGSI_PROCESSOR_COMPUTE:
5039 params[SI_PARAM_GRID_SIZE] = v3i32;
5040 params[SI_PARAM_BLOCK_ID] = v3i32;
5041 last_sgpr = SI_PARAM_BLOCK_ID;
5042
5043 params[SI_PARAM_THREAD_ID] = v3i32;
5044 num_params = SI_PARAM_THREAD_ID + 1;
5045 break;
5046 default:
5047 assert(0 && "unimplemented shader");
5048 return;
5049 }
5050
5051 assert(num_params <= Elements(params));
5052
5053 si_create_function(ctx, returns, num_returns, params,
5054 num_params, last_array_pointer, last_sgpr);
5055
5056 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5057 if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
5058 !ctx->is_monolithic) {
5059 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5060 "InitialPSInputAddr",
5061 S_0286D0_PERSP_SAMPLE_ENA(1) |
5062 S_0286D0_PERSP_CENTER_ENA(1) |
5063 S_0286D0_PERSP_CENTROID_ENA(1) |
5064 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5065 S_0286D0_LINEAR_CENTER_ENA(1) |
5066 S_0286D0_LINEAR_CENTROID_ENA(1) |
5067 S_0286D0_FRONT_FACE_ENA(1) |
5068 S_0286D0_POS_FIXED_PT_ENA(1));
5069 } else if (ctx->type == TGSI_PROCESSOR_COMPUTE) {
5070 const unsigned *properties = shader->selector->info.properties;
5071 unsigned max_work_group_size =
5072 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5073 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5074 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5075
5076 assert(max_work_group_size);
5077
5078 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5079 "amdgpu-max-work-group-size",
5080 max_work_group_size);
5081 }
5082
5083 shader->info.num_input_sgprs = 0;
5084 shader->info.num_input_vgprs = 0;
5085
5086 for (i = 0; i <= last_sgpr; ++i)
5087 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5088
5089 /* Unused fragment shader inputs are eliminated by the compiler,
5090 * so we don't know yet how many there will be.
5091 */
5092 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
5093 for (; i < num_params; ++i)
5094 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5095
5096 if (bld_base->info &&
5097 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5098 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5099 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5100 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5101 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5102 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5103 ctx->lds =
5104 LLVMAddGlobalInAddressSpace(gallivm->module,
5105 LLVMArrayType(ctx->i32, 64),
5106 "ddxy_lds",
5107 LOCAL_ADDR_SPACE);
5108
5109 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
5110 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
5111 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
5112 declare_tess_lds(ctx);
5113 }
5114
5115 static void preload_constants(struct si_shader_context *ctx)
5116 {
5117 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5118 struct gallivm_state *gallivm = bld_base->base.gallivm;
5119 const struct tgsi_shader_info *info = bld_base->info;
5120 unsigned buf;
5121 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5122
5123 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5124 unsigned i, num_const = info->const_file_max[buf] + 1;
5125
5126 if (num_const == 0)
5127 continue;
5128
5129 /* Allocate space for the constant values */
5130 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5131
5132 /* Load the resource descriptor */
5133 ctx->const_buffers[buf] =
5134 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5135
5136 /* Load the constants, we rely on the code sinking to do the rest */
5137 for (i = 0; i < num_const * 4; ++i) {
5138 ctx->constants[buf][i] =
5139 buffer_load_const(gallivm->builder,
5140 ctx->const_buffers[buf],
5141 lp_build_const_int32(gallivm, i * 4),
5142 ctx->f32);
5143 }
5144 }
5145 }
5146
5147 static void preload_shader_buffers(struct si_shader_context *ctx)
5148 {
5149 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5150 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5151 int buf, maxbuf;
5152
5153 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5154 SI_NUM_SHADER_BUFFERS - 1);
5155 for (buf = 0; buf <= maxbuf; ++buf) {
5156 ctx->shader_buffers[buf] =
5157 build_indexed_load_const(
5158 ctx, ptr, lp_build_const_int32(gallivm, buf));
5159 }
5160 }
5161
5162 static void preload_samplers(struct si_shader_context *ctx)
5163 {
5164 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5165 struct gallivm_state *gallivm = bld_base->base.gallivm;
5166 const struct tgsi_shader_info *info = bld_base->info;
5167 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5168 LLVMValueRef offset;
5169
5170 if (num_samplers == 0)
5171 return;
5172
5173 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5174 for (i = 0; i < num_samplers; ++i) {
5175 /* Resource */
5176 offset = lp_build_const_int32(gallivm, i);
5177 ctx->sampler_views[i] =
5178 get_sampler_desc(ctx, offset, DESC_IMAGE);
5179
5180 /* FMASK resource */
5181 if (info->is_msaa_sampler[i])
5182 ctx->fmasks[i] =
5183 get_sampler_desc(ctx, offset, DESC_FMASK);
5184 else {
5185 ctx->sampler_states[i] =
5186 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5187 ctx->sampler_states[i] =
5188 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5189 ctx->sampler_states[i]);
5190 }
5191 }
5192 }
5193
5194 static void preload_images(struct si_shader_context *ctx)
5195 {
5196 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5197 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5198 struct gallivm_state *gallivm = bld_base->base.gallivm;
5199 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5200 LLVMValueRef res_ptr;
5201 unsigned i;
5202
5203 if (num_images == 0)
5204 return;
5205
5206 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5207
5208 for (i = 0; i < num_images; ++i) {
5209 /* Rely on LLVM to shrink the load for buffer resources. */
5210 LLVMValueRef rsrc =
5211 build_indexed_load_const(ctx, res_ptr,
5212 lp_build_const_int32(gallivm, i));
5213
5214 if (info->images_writemask & (1 << i) &&
5215 !(info->images_buffers & (1 << i)))
5216 rsrc = force_dcc_off(ctx, rsrc);
5217
5218 ctx->images[i] = rsrc;
5219 }
5220 }
5221
5222 static void preload_streamout_buffers(struct si_shader_context *ctx)
5223 {
5224 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5225 struct gallivm_state *gallivm = bld_base->base.gallivm;
5226 unsigned i;
5227
5228 /* Streamout can only be used if the shader is compiled as VS. */
5229 if (!ctx->shader->selector->so.num_outputs ||
5230 (ctx->type == TGSI_PROCESSOR_VERTEX &&
5231 (ctx->shader->key.vs.as_es ||
5232 ctx->shader->key.vs.as_ls)) ||
5233 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
5234 ctx->shader->key.tes.as_es))
5235 return;
5236
5237 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5238 SI_PARAM_RW_BUFFERS);
5239
5240 /* Load the resources, we rely on the code sinking to do the rest */
5241 for (i = 0; i < 4; ++i) {
5242 if (ctx->shader->selector->so.stride[i]) {
5243 LLVMValueRef offset = lp_build_const_int32(gallivm,
5244 SI_VS_STREAMOUT_BUF0 + i);
5245
5246 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5247 }
5248 }
5249 }
5250
5251 /**
5252 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5253 * for later use.
5254 */
5255 static void preload_ring_buffers(struct si_shader_context *ctx)
5256 {
5257 struct gallivm_state *gallivm =
5258 ctx->radeon_bld.soa.bld_base.base.gallivm;
5259
5260 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5261 SI_PARAM_RW_BUFFERS);
5262
5263 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
5264 ctx->shader->key.vs.as_es) ||
5265 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
5266 ctx->shader->key.tes.as_es) ||
5267 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
5268 unsigned ring =
5269 ctx->type == TGSI_PROCESSOR_GEOMETRY ? SI_GS_RING_ESGS
5270 : SI_ES_RING_ESGS;
5271 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5272
5273 ctx->esgs_ring =
5274 build_indexed_load_const(ctx, buf_ptr, offset);
5275 }
5276
5277 if (ctx->is_gs_copy_shader) {
5278 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5279
5280 ctx->gsvs_ring[0] =
5281 build_indexed_load_const(ctx, buf_ptr, offset);
5282 }
5283 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
5284 int i;
5285 for (i = 0; i < 4; i++) {
5286 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5287
5288 ctx->gsvs_ring[i] =
5289 build_indexed_load_const(ctx, buf_ptr, offset);
5290 }
5291 }
5292 }
5293
5294 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5295 LLVMValueRef param_rw_buffers,
5296 unsigned param_pos_fixed_pt)
5297 {
5298 struct lp_build_tgsi_context *bld_base =
5299 &ctx->radeon_bld.soa.bld_base;
5300 struct gallivm_state *gallivm = bld_base->base.gallivm;
5301 LLVMBuilderRef builder = gallivm->builder;
5302 LLVMValueRef slot, desc, offset, row, bit, address[2];
5303
5304 /* Use the fixed-point gl_FragCoord input.
5305 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5306 * per coordinate to get the repeating effect.
5307 */
5308 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5309 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5310
5311 /* Load the buffer descriptor. */
5312 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5313 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5314
5315 /* The stipple pattern is 32x32, each row has 32 bits. */
5316 offset = LLVMBuildMul(builder, address[1],
5317 LLVMConstInt(ctx->i32, 4, 0), "");
5318 row = buffer_load_const(builder, desc, offset, ctx->i32);
5319 bit = LLVMBuildLShr(builder, row, address[0], "");
5320 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5321
5322 /* The intrinsic kills the thread if arg < 0. */
5323 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5324 LLVMConstReal(ctx->f32, -1), "");
5325 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5326 }
5327
5328 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5329 struct si_shader_config *conf,
5330 unsigned symbol_offset)
5331 {
5332 unsigned i;
5333 const unsigned char *config =
5334 radeon_shader_binary_config_start(binary, symbol_offset);
5335
5336 /* XXX: We may be able to emit some of these values directly rather than
5337 * extracting fields to be emitted later.
5338 */
5339
5340 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5341 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5342 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5343 switch (reg) {
5344 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5345 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5346 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5347 case R_00B848_COMPUTE_PGM_RSRC1:
5348 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5349 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5350 conf->float_mode = G_00B028_FLOAT_MODE(value);
5351 conf->rsrc1 = value;
5352 break;
5353 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5354 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5355 break;
5356 case R_00B84C_COMPUTE_PGM_RSRC2:
5357 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5358 conf->rsrc2 = value;
5359 break;
5360 case R_0286CC_SPI_PS_INPUT_ENA:
5361 conf->spi_ps_input_ena = value;
5362 break;
5363 case R_0286D0_SPI_PS_INPUT_ADDR:
5364 conf->spi_ps_input_addr = value;
5365 break;
5366 case R_0286E8_SPI_TMPRING_SIZE:
5367 case R_00B860_COMPUTE_TMPRING_SIZE:
5368 /* WAVESIZE is in units of 256 dwords. */
5369 conf->scratch_bytes_per_wave =
5370 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
5371 break;
5372 default:
5373 {
5374 static bool printed;
5375
5376 if (!printed) {
5377 fprintf(stderr, "Warning: LLVM emitted unknown "
5378 "config register: 0x%x\n", reg);
5379 printed = true;
5380 }
5381 }
5382 break;
5383 }
5384
5385 if (!conf->spi_ps_input_addr)
5386 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5387 }
5388 }
5389
5390 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5391 struct si_shader *shader,
5392 struct si_shader_config *config,
5393 uint64_t scratch_va)
5394 {
5395 unsigned i;
5396 uint32_t scratch_rsrc_dword0 = scratch_va;
5397 uint32_t scratch_rsrc_dword1 =
5398 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
5399 | S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5400
5401 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5402 const struct radeon_shader_reloc *reloc =
5403 &shader->binary.relocs[i];
5404 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5405 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5406 &scratch_rsrc_dword0, 4);
5407 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5408 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5409 &scratch_rsrc_dword1, 4);
5410 }
5411 }
5412 }
5413
5414 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5415 {
5416 unsigned size = shader->binary.code_size;
5417
5418 if (shader->prolog)
5419 size += shader->prolog->binary.code_size;
5420 if (shader->epilog)
5421 size += shader->epilog->binary.code_size;
5422 return size;
5423 }
5424
5425 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5426 {
5427 const struct radeon_shader_binary *prolog =
5428 shader->prolog ? &shader->prolog->binary : NULL;
5429 const struct radeon_shader_binary *epilog =
5430 shader->epilog ? &shader->epilog->binary : NULL;
5431 const struct radeon_shader_binary *mainb = &shader->binary;
5432 unsigned bo_size = si_get_shader_binary_size(shader) +
5433 (!epilog ? mainb->rodata_size : 0);
5434 unsigned char *ptr;
5435
5436 assert(!prolog || !prolog->rodata_size);
5437 assert((!prolog && !epilog) || !mainb->rodata_size);
5438 assert(!epilog || !epilog->rodata_size);
5439
5440 r600_resource_reference(&shader->bo, NULL);
5441 shader->bo = si_resource_create_custom(&sscreen->b.b,
5442 PIPE_USAGE_IMMUTABLE,
5443 bo_size);
5444 if (!shader->bo)
5445 return -ENOMEM;
5446
5447 /* Upload. */
5448 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5449 PIPE_TRANSFER_READ_WRITE);
5450
5451 if (prolog) {
5452 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5453 ptr += prolog->code_size;
5454 }
5455
5456 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5457 ptr += mainb->code_size;
5458
5459 if (epilog)
5460 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5461 else if (mainb->rodata_size > 0)
5462 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5463
5464 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5465 return 0;
5466 }
5467
5468 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5469 struct pipe_debug_callback *debug,
5470 const char *name, FILE *file)
5471 {
5472 char *line, *p;
5473 unsigned i, count;
5474
5475 if (binary->disasm_string) {
5476 fprintf(file, "Shader %s disassembly:\n", name);
5477 fprintf(file, "%s", binary->disasm_string);
5478
5479 if (debug && debug->debug_message) {
5480 /* Very long debug messages are cut off, so send the
5481 * disassembly one line at a time. This causes more
5482 * overhead, but on the plus side it simplifies
5483 * parsing of resulting logs.
5484 */
5485 pipe_debug_message(debug, SHADER_INFO,
5486 "Shader Disassembly Begin");
5487
5488 line = binary->disasm_string;
5489 while (*line) {
5490 p = util_strchrnul(line, '\n');
5491 count = p - line;
5492
5493 if (count) {
5494 pipe_debug_message(debug, SHADER_INFO,
5495 "%.*s", count, line);
5496 }
5497
5498 if (!*p)
5499 break;
5500 line = p + 1;
5501 }
5502
5503 pipe_debug_message(debug, SHADER_INFO,
5504 "Shader Disassembly End");
5505 }
5506 } else {
5507 fprintf(file, "Shader %s binary:\n", name);
5508 for (i = 0; i < binary->code_size; i += 4) {
5509 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5510 binary->code[i + 3], binary->code[i + 2],
5511 binary->code[i + 1], binary->code[i]);
5512 }
5513 }
5514 }
5515
5516 static void si_shader_dump_stats(struct si_screen *sscreen,
5517 struct si_shader_config *conf,
5518 unsigned num_inputs,
5519 unsigned code_size,
5520 struct pipe_debug_callback *debug,
5521 unsigned processor,
5522 FILE *file)
5523 {
5524 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5525 unsigned lds_per_wave = 0;
5526 unsigned max_simd_waves = 10;
5527
5528 /* Compute LDS usage for PS. */
5529 if (processor == TGSI_PROCESSOR_FRAGMENT) {
5530 /* The minimum usage per wave is (num_inputs * 36). The maximum
5531 * usage is (num_inputs * 36 * 16).
5532 * We can get anything in between and it varies between waves.
5533 *
5534 * Other stages don't know the size at compile time or don't
5535 * allocate LDS per wave, but instead they do it per thread group.
5536 */
5537 lds_per_wave = conf->lds_size * lds_increment +
5538 align(num_inputs * 36, lds_increment);
5539 }
5540
5541 /* Compute the per-SIMD wave counts. */
5542 if (conf->num_sgprs) {
5543 if (sscreen->b.chip_class >= VI)
5544 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5545 else
5546 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5547 }
5548
5549 if (conf->num_vgprs)
5550 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5551
5552 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5553 * that PS can use.
5554 */
5555 if (lds_per_wave)
5556 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5557
5558 if (file != stderr ||
5559 r600_can_dump_shader(&sscreen->b, processor)) {
5560 if (processor == TGSI_PROCESSOR_FRAGMENT) {
5561 fprintf(file, "*** SHADER CONFIG ***\n"
5562 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5563 "SPI_PS_INPUT_ENA = 0x%04x\n",
5564 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5565 }
5566
5567 fprintf(file, "*** SHADER STATS ***\n"
5568 "SGPRS: %d\n"
5569 "VGPRS: %d\n"
5570 "Code Size: %d bytes\n"
5571 "LDS: %d blocks\n"
5572 "Scratch: %d bytes per wave\n"
5573 "Max Waves: %d\n"
5574 "********************\n",
5575 conf->num_sgprs, conf->num_vgprs, code_size,
5576 conf->lds_size, conf->scratch_bytes_per_wave,
5577 max_simd_waves);
5578 }
5579
5580 pipe_debug_message(debug, SHADER_INFO,
5581 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5582 "LDS: %d Scratch: %d Max Waves: %d",
5583 conf->num_sgprs, conf->num_vgprs, code_size,
5584 conf->lds_size, conf->scratch_bytes_per_wave,
5585 max_simd_waves);
5586 }
5587
5588 static const char *si_get_shader_name(struct si_shader *shader,
5589 unsigned processor)
5590 {
5591 switch (processor) {
5592 case TGSI_PROCESSOR_VERTEX:
5593 if (shader->key.vs.as_es)
5594 return "Vertex Shader as ES";
5595 else if (shader->key.vs.as_ls)
5596 return "Vertex Shader as LS";
5597 else
5598 return "Vertex Shader as VS";
5599 case TGSI_PROCESSOR_TESS_CTRL:
5600 return "Tessellation Control Shader";
5601 case TGSI_PROCESSOR_TESS_EVAL:
5602 if (shader->key.tes.as_es)
5603 return "Tessellation Evaluation Shader as ES";
5604 else
5605 return "Tessellation Evaluation Shader as VS";
5606 case TGSI_PROCESSOR_GEOMETRY:
5607 if (shader->gs_copy_shader == NULL)
5608 return "GS Copy Shader as VS";
5609 else
5610 return "Geometry Shader";
5611 case TGSI_PROCESSOR_FRAGMENT:
5612 return "Pixel Shader";
5613 case TGSI_PROCESSOR_COMPUTE:
5614 return "Compute Shader";
5615 default:
5616 return "Unknown Shader";
5617 }
5618 }
5619
5620 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5621 struct pipe_debug_callback *debug, unsigned processor,
5622 FILE *file)
5623 {
5624 if (file != stderr ||
5625 (r600_can_dump_shader(&sscreen->b, processor) &&
5626 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5627 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5628
5629 if (shader->prolog)
5630 si_shader_dump_disassembly(&shader->prolog->binary,
5631 debug, "prolog", file);
5632
5633 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5634
5635 if (shader->epilog)
5636 si_shader_dump_disassembly(&shader->epilog->binary,
5637 debug, "epilog", file);
5638 fprintf(file, "\n");
5639 }
5640
5641 si_shader_dump_stats(sscreen, &shader->config,
5642 shader->selector ? shader->selector->info.num_inputs : 0,
5643 si_get_shader_binary_size(shader), debug, processor,
5644 file);
5645 }
5646
5647 int si_compile_llvm(struct si_screen *sscreen,
5648 struct radeon_shader_binary *binary,
5649 struct si_shader_config *conf,
5650 LLVMTargetMachineRef tm,
5651 LLVMModuleRef mod,
5652 struct pipe_debug_callback *debug,
5653 unsigned processor,
5654 const char *name)
5655 {
5656 int r = 0;
5657 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5658
5659 if (r600_can_dump_shader(&sscreen->b, processor)) {
5660 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5661
5662 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5663 fprintf(stderr, "%s LLVM IR:\n\n", name);
5664 LLVMDumpModule(mod);
5665 fprintf(stderr, "\n");
5666 }
5667 }
5668
5669 if (!si_replace_shader(count, binary)) {
5670 r = radeon_llvm_compile(mod, binary,
5671 r600_get_llvm_processor_name(sscreen->b.family), tm,
5672 debug);
5673 if (r)
5674 return r;
5675 }
5676
5677 si_shader_binary_read_config(binary, conf, 0);
5678
5679 /* Enable 64-bit and 16-bit denormals, because there is no performance
5680 * cost.
5681 *
5682 * If denormals are enabled, all floating-point output modifiers are
5683 * ignored.
5684 *
5685 * Don't enable denormals for 32-bit floats, because:
5686 * - Floating-point output modifiers would be ignored by the hw.
5687 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5688 * have to stop using those.
5689 * - SI & CI would be very slow.
5690 */
5691 conf->float_mode |= V_00B028_FP_64_DENORMS;
5692
5693 FREE(binary->config);
5694 FREE(binary->global_symbol_offsets);
5695 binary->config = NULL;
5696 binary->global_symbol_offsets = NULL;
5697
5698 /* Some shaders can't have rodata because their binaries can be
5699 * concatenated.
5700 */
5701 if (binary->rodata_size &&
5702 (processor == TGSI_PROCESSOR_VERTEX ||
5703 processor == TGSI_PROCESSOR_TESS_CTRL ||
5704 processor == TGSI_PROCESSOR_TESS_EVAL ||
5705 processor == TGSI_PROCESSOR_FRAGMENT)) {
5706 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5707 return -EINVAL;
5708 }
5709
5710 return r;
5711 }
5712
5713 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5714 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
5715 struct si_shader_context *ctx,
5716 struct si_shader *gs,
5717 struct pipe_debug_callback *debug)
5718 {
5719 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5720 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5721 struct lp_build_context *uint = &bld_base->uint_bld;
5722 struct si_shader_output_values *outputs;
5723 struct tgsi_shader_info *gsinfo = &gs->selector->info;
5724 LLVMValueRef args[9];
5725 int i, r;
5726
5727 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5728
5729 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
5730 ctx->type = TGSI_PROCESSOR_VERTEX;
5731 ctx->is_gs_copy_shader = true;
5732
5733 create_meta_data(ctx);
5734 create_function(ctx);
5735 preload_streamout_buffers(ctx);
5736 preload_ring_buffers(ctx);
5737
5738 args[0] = ctx->gsvs_ring[0];
5739 args[1] = lp_build_mul_imm(uint,
5740 LLVMGetParam(ctx->radeon_bld.main_fn,
5741 ctx->param_vertex_id),
5742 4);
5743 args[3] = uint->zero;
5744 args[4] = uint->one; /* OFFEN */
5745 args[5] = uint->zero; /* IDXEN */
5746 args[6] = uint->one; /* GLC */
5747 args[7] = uint->one; /* SLC */
5748 args[8] = uint->zero; /* TFE */
5749
5750 /* Fetch vertex data from GSVS ring */
5751 for (i = 0; i < gsinfo->num_outputs; ++i) {
5752 unsigned chan;
5753
5754 outputs[i].name = gsinfo->output_semantic_name[i];
5755 outputs[i].sid = gsinfo->output_semantic_index[i];
5756
5757 for (chan = 0; chan < 4; chan++) {
5758 args[2] = lp_build_const_int32(gallivm,
5759 (i * 4 + chan) *
5760 gs->selector->gs_max_out_vertices * 16 * 4);
5761
5762 outputs[i].values[chan] =
5763 LLVMBuildBitCast(gallivm->builder,
5764 lp_build_intrinsic(gallivm->builder,
5765 "llvm.SI.buffer.load.dword.i32.i32",
5766 ctx->i32, args, 9,
5767 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
5768 ctx->f32, "");
5769 }
5770 }
5771
5772 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5773
5774 LLVMBuildRet(gallivm->builder, ctx->return_value);
5775
5776 /* Dump LLVM IR before any optimization passes */
5777 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5778 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5779 LLVMDumpModule(bld_base->base.gallivm->module);
5780
5781 radeon_llvm_finalize_module(&ctx->radeon_bld);
5782
5783 r = si_compile_llvm(sscreen, &ctx->shader->binary,
5784 &ctx->shader->config, ctx->tm,
5785 bld_base->base.gallivm->module,
5786 debug, TGSI_PROCESSOR_GEOMETRY,
5787 "GS Copy Shader");
5788 if (!r) {
5789 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5790 fprintf(stderr, "GS Copy Shader:\n");
5791 si_shader_dump(sscreen, ctx->shader, debug,
5792 TGSI_PROCESSOR_GEOMETRY, stderr);
5793 r = si_shader_binary_upload(sscreen, ctx->shader);
5794 }
5795
5796 radeon_llvm_dispose(&ctx->radeon_bld);
5797
5798 FREE(outputs);
5799 return r;
5800 }
5801
5802 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
5803 {
5804 int i;
5805
5806 fprintf(f, "SHADER KEY\n");
5807
5808 switch (shader) {
5809 case PIPE_SHADER_VERTEX:
5810 fprintf(f, " instance_divisors = {");
5811 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
5812 fprintf(f, !i ? "%u" : ", %u",
5813 key->vs.prolog.instance_divisors[i]);
5814 fprintf(f, "}\n");
5815 fprintf(f, " as_es = %u\n", key->vs.as_es);
5816 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
5817 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
5818 break;
5819
5820 case PIPE_SHADER_TESS_CTRL:
5821 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
5822 break;
5823
5824 case PIPE_SHADER_TESS_EVAL:
5825 fprintf(f, " as_es = %u\n", key->tes.as_es);
5826 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
5827 break;
5828
5829 case PIPE_SHADER_GEOMETRY:
5830 case PIPE_SHADER_COMPUTE:
5831 break;
5832
5833 case PIPE_SHADER_FRAGMENT:
5834 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
5835 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
5836 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
5837 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
5838 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
5839 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
5840 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
5841 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
5842 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
5843 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
5844 break;
5845
5846 default:
5847 assert(0);
5848 }
5849 }
5850
5851 static void si_init_shader_ctx(struct si_shader_context *ctx,
5852 struct si_screen *sscreen,
5853 struct si_shader *shader,
5854 LLVMTargetMachineRef tm)
5855 {
5856 struct lp_build_tgsi_context *bld_base;
5857 struct lp_build_tgsi_action tmpl = {};
5858
5859 memset(ctx, 0, sizeof(*ctx));
5860 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
5861 ctx->tm = tm;
5862 ctx->screen = sscreen;
5863 if (shader && shader->selector)
5864 ctx->type = shader->selector->info.processor;
5865 else
5866 ctx->type = -1;
5867 ctx->shader = shader;
5868
5869 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
5870 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
5871 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
5872 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
5873 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
5874 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
5875 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
5876 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
5877 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
5878 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
5879 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
5880 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
5881
5882 bld_base = &ctx->radeon_bld.soa.bld_base;
5883 if (shader && shader->selector)
5884 bld_base->info = &shader->selector->info;
5885 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5886
5887 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5888 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5889 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5890
5891 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
5892 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
5893 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
5894 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
5895 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
5896 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
5897 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
5898 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
5899 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
5900 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
5901 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
5902 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
5903 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
5904
5905 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
5906 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
5907 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
5908 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
5909 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
5910 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
5911
5912 tmpl.fetch_args = atomic_fetch_args;
5913 tmpl.emit = atomic_emit;
5914 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5915 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
5916 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
5917 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
5918 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
5919 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
5920 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
5921 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
5922 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
5923 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
5924 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
5925 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
5926 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
5927 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
5928 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
5929 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
5930 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
5931 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
5932 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
5933 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
5934
5935 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5936
5937 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5938 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5939 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5940 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5941
5942 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5943 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5944 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5945
5946 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
5947 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
5948 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
5949 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
5950 }
5951
5952 int si_compile_tgsi_shader(struct si_screen *sscreen,
5953 LLVMTargetMachineRef tm,
5954 struct si_shader *shader,
5955 bool is_monolithic,
5956 struct pipe_debug_callback *debug)
5957 {
5958 struct si_shader_selector *sel = shader->selector;
5959 struct si_shader_context ctx;
5960 struct lp_build_tgsi_context *bld_base;
5961 LLVMModuleRef mod;
5962 int r = 0;
5963
5964 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
5965 * conversion fails. */
5966 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
5967 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
5968 si_dump_shader_key(sel->type, &shader->key, stderr);
5969 tgsi_dump(sel->tokens, 0);
5970 si_dump_streamout(&sel->so);
5971 }
5972
5973 si_init_shader_ctx(&ctx, sscreen, shader, tm);
5974 ctx.is_monolithic = is_monolithic;
5975
5976 shader->info.uses_instanceid = sel->info.uses_instanceid;
5977
5978 bld_base = &ctx.radeon_bld.soa.bld_base;
5979 ctx.radeon_bld.load_system_value = declare_system_value;
5980
5981 switch (ctx.type) {
5982 case TGSI_PROCESSOR_VERTEX:
5983 ctx.radeon_bld.load_input = declare_input_vs;
5984 if (shader->key.vs.as_ls)
5985 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5986 else if (shader->key.vs.as_es)
5987 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5988 else
5989 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5990 break;
5991 case TGSI_PROCESSOR_TESS_CTRL:
5992 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5993 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5994 bld_base->emit_store = store_output_tcs;
5995 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5996 break;
5997 case TGSI_PROCESSOR_TESS_EVAL:
5998 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5999 if (shader->key.tes.as_es)
6000 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6001 else
6002 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6003 break;
6004 case TGSI_PROCESSOR_GEOMETRY:
6005 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6006 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6007 break;
6008 case TGSI_PROCESSOR_FRAGMENT:
6009 ctx.radeon_bld.load_input = declare_input_fs;
6010 if (is_monolithic)
6011 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6012 else
6013 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6014 break;
6015 case TGSI_PROCESSOR_COMPUTE:
6016 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6017 break;
6018 default:
6019 assert(!"Unsupported shader type");
6020 return -1;
6021 }
6022
6023 create_meta_data(&ctx);
6024 create_function(&ctx);
6025 preload_constants(&ctx);
6026 preload_shader_buffers(&ctx);
6027 preload_samplers(&ctx);
6028 preload_images(&ctx);
6029 preload_streamout_buffers(&ctx);
6030 preload_ring_buffers(&ctx);
6031
6032 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6033 shader->key.ps.prolog.poly_stipple) {
6034 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6035 SI_PARAM_RW_BUFFERS);
6036 si_llvm_emit_polygon_stipple(&ctx, list,
6037 SI_PARAM_POS_FIXED_PT);
6038 }
6039
6040 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
6041 int i;
6042 for (i = 0; i < 4; i++) {
6043 ctx.gs_next_vertex[i] =
6044 lp_build_alloca(bld_base->base.gallivm,
6045 ctx.i32, "");
6046 }
6047 }
6048
6049 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6050 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6051 goto out;
6052 }
6053
6054 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
6055 mod = bld_base->base.gallivm->module;
6056
6057 /* Dump LLVM IR before any optimization passes */
6058 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6059 r600_can_dump_shader(&sscreen->b, ctx.type))
6060 LLVMDumpModule(mod);
6061
6062 radeon_llvm_finalize_module(&ctx.radeon_bld);
6063
6064 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6065 mod, debug, ctx.type, "TGSI shader");
6066 if (r) {
6067 fprintf(stderr, "LLVM failed to compile shader\n");
6068 goto out;
6069 }
6070
6071 radeon_llvm_dispose(&ctx.radeon_bld);
6072
6073 /* Add the scratch offset to input SGPRs. */
6074 if (shader->config.scratch_bytes_per_wave)
6075 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6076
6077 /* Calculate the number of fragment input VGPRs. */
6078 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
6079 shader->info.num_input_vgprs = 0;
6080 shader->info.face_vgpr_index = -1;
6081
6082 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6083 shader->info.num_input_vgprs += 2;
6084 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6085 shader->info.num_input_vgprs += 2;
6086 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6087 shader->info.num_input_vgprs += 2;
6088 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6089 shader->info.num_input_vgprs += 3;
6090 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6091 shader->info.num_input_vgprs += 2;
6092 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6093 shader->info.num_input_vgprs += 2;
6094 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6095 shader->info.num_input_vgprs += 2;
6096 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6097 shader->info.num_input_vgprs += 1;
6098 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6099 shader->info.num_input_vgprs += 1;
6100 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6101 shader->info.num_input_vgprs += 1;
6102 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6103 shader->info.num_input_vgprs += 1;
6104 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6105 shader->info.num_input_vgprs += 1;
6106 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6107 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6108 shader->info.num_input_vgprs += 1;
6109 }
6110 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6111 shader->info.num_input_vgprs += 1;
6112 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6113 shader->info.num_input_vgprs += 1;
6114 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6115 shader->info.num_input_vgprs += 1;
6116 }
6117
6118 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
6119 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6120 shader->gs_copy_shader->selector = shader->selector;
6121 ctx.shader = shader->gs_copy_shader;
6122 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6123 shader, debug))) {
6124 free(shader->gs_copy_shader);
6125 shader->gs_copy_shader = NULL;
6126 goto out;
6127 }
6128 }
6129
6130 out:
6131 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6132 FREE(ctx.constants[i]);
6133 return r;
6134 }
6135
6136 /**
6137 * Create, compile and return a shader part (prolog or epilog).
6138 *
6139 * \param sscreen screen
6140 * \param list list of shader parts of the same category
6141 * \param key shader part key
6142 * \param tm LLVM target machine
6143 * \param debug debug callback
6144 * \param compile the callback responsible for compilation
6145 * \return non-NULL on success
6146 */
6147 static struct si_shader_part *
6148 si_get_shader_part(struct si_screen *sscreen,
6149 struct si_shader_part **list,
6150 union si_shader_part_key *key,
6151 LLVMTargetMachineRef tm,
6152 struct pipe_debug_callback *debug,
6153 bool (*compile)(struct si_screen *,
6154 LLVMTargetMachineRef,
6155 struct pipe_debug_callback *,
6156 struct si_shader_part *))
6157 {
6158 struct si_shader_part *result;
6159
6160 pipe_mutex_lock(sscreen->shader_parts_mutex);
6161
6162 /* Find existing. */
6163 for (result = *list; result; result = result->next) {
6164 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6165 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6166 return result;
6167 }
6168 }
6169
6170 /* Compile a new one. */
6171 result = CALLOC_STRUCT(si_shader_part);
6172 result->key = *key;
6173 if (!compile(sscreen, tm, debug, result)) {
6174 FREE(result);
6175 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6176 return NULL;
6177 }
6178
6179 result->next = *list;
6180 *list = result;
6181 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6182 return result;
6183 }
6184
6185 /**
6186 * Create a vertex shader prolog.
6187 *
6188 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6189 * All inputs are returned unmodified. The vertex load indices are
6190 * stored after them, which will used by the API VS for fetching inputs.
6191 *
6192 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6193 * input_v0,
6194 * input_v1,
6195 * input_v2,
6196 * input_v3,
6197 * (VertexID + BaseVertex),
6198 * (InstanceID + StartInstance),
6199 * (InstanceID / 2 + StartInstance)
6200 */
6201 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6202 LLVMTargetMachineRef tm,
6203 struct pipe_debug_callback *debug,
6204 struct si_shader_part *out)
6205 {
6206 union si_shader_part_key *key = &out->key;
6207 struct si_shader shader = {};
6208 struct si_shader_context ctx;
6209 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6210 LLVMTypeRef *params, *returns;
6211 LLVMValueRef ret, func;
6212 int last_sgpr, num_params, num_returns, i;
6213 bool status = true;
6214
6215 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6216 ctx.type = TGSI_PROCESSOR_VERTEX;
6217 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6218 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6219
6220 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6221 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6222 sizeof(LLVMTypeRef));
6223 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6224 key->vs_prolog.last_input + 1) *
6225 sizeof(LLVMTypeRef));
6226 num_params = 0;
6227 num_returns = 0;
6228
6229 /* Declare input and output SGPRs. */
6230 num_params = 0;
6231 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6232 params[num_params++] = ctx.i32;
6233 returns[num_returns++] = ctx.i32;
6234 }
6235 last_sgpr = num_params - 1;
6236
6237 /* 4 preloaded VGPRs (outputs must be floats) */
6238 for (i = 0; i < 4; i++) {
6239 params[num_params++] = ctx.i32;
6240 returns[num_returns++] = ctx.f32;
6241 }
6242
6243 /* Vertex load indices. */
6244 for (i = 0; i <= key->vs_prolog.last_input; i++)
6245 returns[num_returns++] = ctx.f32;
6246
6247 /* Create the function. */
6248 si_create_function(&ctx, returns, num_returns, params,
6249 num_params, -1, last_sgpr);
6250 func = ctx.radeon_bld.main_fn;
6251
6252 /* Copy inputs to outputs. This should be no-op, as the registers match,
6253 * but it will prevent the compiler from overwriting them unintentionally.
6254 */
6255 ret = ctx.return_value;
6256 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6257 LLVMValueRef p = LLVMGetParam(func, i);
6258 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6259 }
6260 for (i = num_params - 4; i < num_params; i++) {
6261 LLVMValueRef p = LLVMGetParam(func, i);
6262 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6263 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6264 }
6265
6266 /* Compute vertex load indices from instance divisors. */
6267 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6268 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6269 LLVMValueRef index;
6270
6271 if (divisor) {
6272 /* InstanceID / Divisor + StartInstance */
6273 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6274 SI_SGPR_START_INSTANCE,
6275 divisor);
6276 } else {
6277 /* VertexID + BaseVertex */
6278 index = LLVMBuildAdd(gallivm->builder,
6279 LLVMGetParam(func, ctx.param_vertex_id),
6280 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6281 }
6282
6283 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6284 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6285 num_params++, "");
6286 }
6287
6288 /* Compile. */
6289 LLVMBuildRet(gallivm->builder, ret);
6290 radeon_llvm_finalize_module(&ctx.radeon_bld);
6291
6292 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6293 gallivm->module, debug, ctx.type,
6294 "Vertex Shader Prolog"))
6295 status = false;
6296
6297 radeon_llvm_dispose(&ctx.radeon_bld);
6298 return status;
6299 }
6300
6301 /**
6302 * Compile the vertex shader epilog. This is also used by the tessellation
6303 * evaluation shader compiled as VS.
6304 *
6305 * The input is PrimitiveID.
6306 *
6307 * If PrimitiveID is required by the pixel shader, export it.
6308 * Otherwise, do nothing.
6309 */
6310 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6311 LLVMTargetMachineRef tm,
6312 struct pipe_debug_callback *debug,
6313 struct si_shader_part *out)
6314 {
6315 union si_shader_part_key *key = &out->key;
6316 struct si_shader_context ctx;
6317 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6318 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6319 LLVMTypeRef params[5];
6320 int num_params, i;
6321 bool status = true;
6322
6323 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6324 ctx.type = TGSI_PROCESSOR_VERTEX;
6325
6326 /* Declare input VGPRs. */
6327 num_params = key->vs_epilog.states.export_prim_id ?
6328 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6329 assert(num_params <= ARRAY_SIZE(params));
6330
6331 for (i = 0; i < num_params; i++)
6332 params[i] = ctx.f32;
6333
6334 /* Create the function. */
6335 si_create_function(&ctx, NULL, 0, params, num_params,
6336 -1, -1);
6337
6338 /* Emit exports. */
6339 if (key->vs_epilog.states.export_prim_id) {
6340 struct lp_build_context *base = &bld_base->base;
6341 struct lp_build_context *uint = &bld_base->uint_bld;
6342 LLVMValueRef args[9];
6343
6344 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6345 args[1] = uint->zero; /* whether the EXEC mask is valid */
6346 args[2] = uint->zero; /* DONE bit */
6347 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6348 key->vs_epilog.prim_id_param_offset);
6349 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6350 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6351 VS_EPILOG_PRIMID_LOC); /* X */
6352 args[6] = uint->undef; /* Y */
6353 args[7] = uint->undef; /* Z */
6354 args[8] = uint->undef; /* W */
6355
6356 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6357 LLVMVoidTypeInContext(base->gallivm->context),
6358 args, 9, 0);
6359 }
6360
6361 /* Compile. */
6362 LLVMBuildRet(gallivm->builder, ctx.return_value);
6363 radeon_llvm_finalize_module(&ctx.radeon_bld);
6364
6365 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6366 gallivm->module, debug, ctx.type,
6367 "Vertex Shader Epilog"))
6368 status = false;
6369
6370 radeon_llvm_dispose(&ctx.radeon_bld);
6371 return status;
6372 }
6373
6374 /**
6375 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6376 */
6377 static bool si_get_vs_epilog(struct si_screen *sscreen,
6378 LLVMTargetMachineRef tm,
6379 struct si_shader *shader,
6380 struct pipe_debug_callback *debug,
6381 struct si_vs_epilog_bits *states)
6382 {
6383 union si_shader_part_key epilog_key;
6384
6385 memset(&epilog_key, 0, sizeof(epilog_key));
6386 epilog_key.vs_epilog.states = *states;
6387
6388 /* Set up the PrimitiveID output. */
6389 if (shader->key.vs.epilog.export_prim_id) {
6390 unsigned index = shader->selector->info.num_outputs;
6391 unsigned offset = shader->info.nr_param_exports++;
6392
6393 epilog_key.vs_epilog.prim_id_param_offset = offset;
6394 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6395 shader->info.vs_output_param_offset[index] = offset;
6396 }
6397
6398 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
6399 &epilog_key, tm, debug,
6400 si_compile_vs_epilog);
6401 return shader->epilog != NULL;
6402 }
6403
6404 /**
6405 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6406 */
6407 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6408 LLVMTargetMachineRef tm,
6409 struct si_shader *shader,
6410 struct pipe_debug_callback *debug)
6411 {
6412 struct tgsi_shader_info *info = &shader->selector->info;
6413 union si_shader_part_key prolog_key;
6414 unsigned i;
6415
6416 /* Get the prolog. */
6417 memset(&prolog_key, 0, sizeof(prolog_key));
6418 prolog_key.vs_prolog.states = shader->key.vs.prolog;
6419 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6420 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6421
6422 /* The prolog is a no-op if there are no inputs. */
6423 if (info->num_inputs) {
6424 shader->prolog =
6425 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6426 &prolog_key, tm, debug,
6427 si_compile_vs_prolog);
6428 if (!shader->prolog)
6429 return false;
6430 }
6431
6432 /* Get the epilog. */
6433 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
6434 !si_get_vs_epilog(sscreen, tm, shader, debug,
6435 &shader->key.vs.epilog))
6436 return false;
6437
6438 /* Set the instanceID flag. */
6439 for (i = 0; i < info->num_inputs; i++)
6440 if (prolog_key.vs_prolog.states.instance_divisors[i])
6441 shader->info.uses_instanceid = true;
6442
6443 return true;
6444 }
6445
6446 /**
6447 * Select and compile (or reuse) TES parts (epilog).
6448 */
6449 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
6450 LLVMTargetMachineRef tm,
6451 struct si_shader *shader,
6452 struct pipe_debug_callback *debug)
6453 {
6454 if (shader->key.tes.as_es)
6455 return true;
6456
6457 /* TES compiled as VS. */
6458 return si_get_vs_epilog(sscreen, tm, shader, debug,
6459 &shader->key.tes.epilog);
6460 }
6461
6462 /**
6463 * Compile the TCS epilog. This writes tesselation factors to memory based on
6464 * the output primitive type of the tesselator (determined by TES).
6465 */
6466 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
6467 LLVMTargetMachineRef tm,
6468 struct pipe_debug_callback *debug,
6469 struct si_shader_part *out)
6470 {
6471 union si_shader_part_key *key = &out->key;
6472 struct si_shader shader = {};
6473 struct si_shader_context ctx;
6474 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6475 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6476 LLVMTypeRef params[16];
6477 LLVMValueRef func;
6478 int last_array_pointer, last_sgpr, num_params;
6479 bool status = true;
6480
6481 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6482 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
6483 shader.key.tcs.epilog = key->tcs_epilog.states;
6484
6485 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
6486 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
6487 last_array_pointer = SI_PARAM_RW_BUFFERS;
6488 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6489 params[SI_PARAM_SAMPLERS] = ctx.i64;
6490 params[SI_PARAM_IMAGES] = ctx.i64;
6491 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6492 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
6493 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
6494 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
6495 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
6496 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
6497 num_params = last_sgpr + 1;
6498
6499 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
6500 params[num_params++] = ctx.i32; /* invocation ID within the patch */
6501 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
6502
6503 /* Create the function. */
6504 si_create_function(&ctx, NULL, 0, params, num_params,
6505 last_array_pointer, last_sgpr);
6506 declare_tess_lds(&ctx);
6507 func = ctx.radeon_bld.main_fn;
6508
6509 si_write_tess_factors(bld_base,
6510 LLVMGetParam(func, last_sgpr + 1),
6511 LLVMGetParam(func, last_sgpr + 2),
6512 LLVMGetParam(func, last_sgpr + 3));
6513
6514 /* Compile. */
6515 LLVMBuildRet(gallivm->builder, ctx.return_value);
6516 radeon_llvm_finalize_module(&ctx.radeon_bld);
6517
6518 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6519 gallivm->module, debug, ctx.type,
6520 "Tessellation Control Shader Epilog"))
6521 status = false;
6522
6523 radeon_llvm_dispose(&ctx.radeon_bld);
6524 return status;
6525 }
6526
6527 /**
6528 * Select and compile (or reuse) TCS parts (epilog).
6529 */
6530 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6531 LLVMTargetMachineRef tm,
6532 struct si_shader *shader,
6533 struct pipe_debug_callback *debug)
6534 {
6535 union si_shader_part_key epilog_key;
6536
6537 /* Get the epilog. */
6538 memset(&epilog_key, 0, sizeof(epilog_key));
6539 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
6540
6541 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6542 &epilog_key, tm, debug,
6543 si_compile_tcs_epilog);
6544 return shader->epilog != NULL;
6545 }
6546
6547 /**
6548 * Compile the pixel shader prolog. This handles:
6549 * - two-side color selection and interpolation
6550 * - overriding interpolation parameters for the API PS
6551 * - polygon stippling
6552 *
6553 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6554 * overriden by other states. (e.g. per-sample interpolation)
6555 * Interpolated colors are stored after the preloaded VGPRs.
6556 */
6557 static bool si_compile_ps_prolog(struct si_screen *sscreen,
6558 LLVMTargetMachineRef tm,
6559 struct pipe_debug_callback *debug,
6560 struct si_shader_part *out)
6561 {
6562 union si_shader_part_key *key = &out->key;
6563 struct si_shader shader = {};
6564 struct si_shader_context ctx;
6565 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6566 LLVMTypeRef *params;
6567 LLVMValueRef ret, func;
6568 int last_sgpr, num_params, num_returns, i, num_color_channels;
6569 bool status = true;
6570
6571 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6572 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6573 shader.key.ps.prolog = key->ps_prolog.states;
6574
6575 /* Number of inputs + 8 color elements. */
6576 params = alloca((key->ps_prolog.num_input_sgprs +
6577 key->ps_prolog.num_input_vgprs + 8) *
6578 sizeof(LLVMTypeRef));
6579
6580 /* Declare inputs. */
6581 num_params = 0;
6582 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
6583 params[num_params++] = ctx.i32;
6584 last_sgpr = num_params - 1;
6585
6586 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
6587 params[num_params++] = ctx.f32;
6588
6589 /* Declare outputs (same as inputs + add colors if needed) */
6590 num_returns = num_params;
6591 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6592 for (i = 0; i < num_color_channels; i++)
6593 params[num_returns++] = ctx.f32;
6594
6595 /* Create the function. */
6596 si_create_function(&ctx, params, num_returns, params,
6597 num_params, -1, last_sgpr);
6598 func = ctx.radeon_bld.main_fn;
6599
6600 /* Copy inputs to outputs. This should be no-op, as the registers match,
6601 * but it will prevent the compiler from overwriting them unintentionally.
6602 */
6603 ret = ctx.return_value;
6604 for (i = 0; i < num_params; i++) {
6605 LLVMValueRef p = LLVMGetParam(func, i);
6606 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6607 }
6608
6609 /* Polygon stippling. */
6610 if (key->ps_prolog.states.poly_stipple) {
6611 /* POS_FIXED_PT is always last. */
6612 unsigned pos = key->ps_prolog.num_input_sgprs +
6613 key->ps_prolog.num_input_vgprs - 1;
6614 LLVMValueRef ptr[2], list;
6615
6616 /* Get the pointer to rw buffers. */
6617 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
6618 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
6619 list = lp_build_gather_values(gallivm, ptr, 2);
6620 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
6621 list = LLVMBuildIntToPtr(gallivm->builder, list,
6622 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
6623
6624 si_llvm_emit_polygon_stipple(&ctx, list, pos);
6625 }
6626
6627 /* Interpolate colors. */
6628 for (i = 0; i < 2; i++) {
6629 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6630 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6631 key->ps_prolog.face_vgpr_index;
6632 LLVMValueRef interp[2], color[4];
6633 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6634
6635 if (!writemask)
6636 continue;
6637
6638 /* If the interpolation qualifier is not CONSTANT (-1). */
6639 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6640 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6641 key->ps_prolog.color_interp_vgpr_index[i];
6642
6643 interp[0] = LLVMGetParam(func, interp_vgpr);
6644 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
6645 interp_ij = lp_build_gather_values(gallivm, interp, 2);
6646 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
6647 ctx.v2i32, "");
6648 }
6649
6650 /* Use the absolute location of the input. */
6651 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6652
6653 if (key->ps_prolog.states.color_two_side) {
6654 face = LLVMGetParam(func, face_vgpr);
6655 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
6656 }
6657
6658 interp_fs_input(&ctx,
6659 key->ps_prolog.color_attr_index[i],
6660 TGSI_SEMANTIC_COLOR, i,
6661 key->ps_prolog.num_interp_inputs,
6662 key->ps_prolog.colors_read, interp_ij,
6663 prim_mask, face, color);
6664
6665 while (writemask) {
6666 unsigned chan = u_bit_scan(&writemask);
6667 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
6668 num_params++, "");
6669 }
6670 }
6671
6672 /* Force per-sample interpolation. */
6673 if (key->ps_prolog.states.force_persample_interp) {
6674 unsigned i, base = key->ps_prolog.num_input_sgprs;
6675 LLVMValueRef persp_sample[2], linear_sample[2];
6676
6677 /* Read PERSP_SAMPLE. */
6678 for (i = 0; i < 2; i++)
6679 persp_sample[i] = LLVMGetParam(func, base + i);
6680 /* Overwrite PERSP_CENTER. */
6681 for (i = 0; i < 2; i++)
6682 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6683 persp_sample[i], base + 2 + i, "");
6684 /* Overwrite PERSP_CENTROID. */
6685 for (i = 0; i < 2; i++)
6686 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6687 persp_sample[i], base + 4 + i, "");
6688 /* Read LINEAR_SAMPLE. */
6689 for (i = 0; i < 2; i++)
6690 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6691 /* Overwrite LINEAR_CENTER. */
6692 for (i = 0; i < 2; i++)
6693 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6694 linear_sample[i], base + 8 + i, "");
6695 /* Overwrite LINEAR_CENTROID. */
6696 for (i = 0; i < 2; i++)
6697 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6698 linear_sample[i], base + 10 + i, "");
6699 }
6700
6701 /* Compile. */
6702 LLVMBuildRet(gallivm->builder, ret);
6703 radeon_llvm_finalize_module(&ctx.radeon_bld);
6704
6705 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6706 gallivm->module, debug, ctx.type,
6707 "Fragment Shader Prolog"))
6708 status = false;
6709
6710 radeon_llvm_dispose(&ctx.radeon_bld);
6711 return status;
6712 }
6713
6714 /**
6715 * Compile the pixel shader epilog. This handles everything that must be
6716 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6717 */
6718 static bool si_compile_ps_epilog(struct si_screen *sscreen,
6719 LLVMTargetMachineRef tm,
6720 struct pipe_debug_callback *debug,
6721 struct si_shader_part *out)
6722 {
6723 union si_shader_part_key *key = &out->key;
6724 struct si_shader shader = {};
6725 struct si_shader_context ctx;
6726 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6727 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6728 LLVMTypeRef params[16+8*4+3];
6729 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6730 int last_array_pointer, last_sgpr, num_params, i;
6731 bool status = true;
6732
6733 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6734 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6735 shader.key.ps.epilog = key->ps_epilog.states;
6736
6737 /* Declare input SGPRs. */
6738 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
6739 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6740 params[SI_PARAM_SAMPLERS] = ctx.i64;
6741 params[SI_PARAM_IMAGES] = ctx.i64;
6742 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6743 params[SI_PARAM_ALPHA_REF] = ctx.f32;
6744 last_array_pointer = -1;
6745 last_sgpr = SI_PARAM_ALPHA_REF;
6746
6747 /* Declare input VGPRs. */
6748 num_params = (last_sgpr + 1) +
6749 util_bitcount(key->ps_epilog.colors_written) * 4 +
6750 key->ps_epilog.writes_z +
6751 key->ps_epilog.writes_stencil +
6752 key->ps_epilog.writes_samplemask;
6753
6754 num_params = MAX2(num_params,
6755 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6756
6757 assert(num_params <= ARRAY_SIZE(params));
6758
6759 for (i = last_sgpr + 1; i < num_params; i++)
6760 params[i] = ctx.f32;
6761
6762 /* Create the function. */
6763 si_create_function(&ctx, NULL, 0, params, num_params,
6764 last_array_pointer, last_sgpr);
6765 /* Disable elimination of unused inputs. */
6766 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
6767 "InitialPSInputAddr", 0xffffff);
6768
6769 /* Process colors. */
6770 unsigned vgpr = last_sgpr + 1;
6771 unsigned colors_written = key->ps_epilog.colors_written;
6772 int last_color_export = -1;
6773
6774 /* Find the last color export. */
6775 if (!key->ps_epilog.writes_z &&
6776 !key->ps_epilog.writes_stencil &&
6777 !key->ps_epilog.writes_samplemask) {
6778 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6779
6780 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6781 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6782 /* Just set this if any of the colorbuffers are enabled. */
6783 if (spi_format &
6784 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6785 last_color_export = 0;
6786 } else {
6787 for (i = 0; i < 8; i++)
6788 if (colors_written & (1 << i) &&
6789 (spi_format >> (i * 4)) & 0xf)
6790 last_color_export = i;
6791 }
6792 }
6793
6794 while (colors_written) {
6795 LLVMValueRef color[4];
6796 int mrt = u_bit_scan(&colors_written);
6797
6798 for (i = 0; i < 4; i++)
6799 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6800
6801 si_export_mrt_color(bld_base, color, mrt,
6802 num_params - 1,
6803 mrt == last_color_export);
6804 }
6805
6806 /* Process depth, stencil, samplemask. */
6807 if (key->ps_epilog.writes_z)
6808 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6809 if (key->ps_epilog.writes_stencil)
6810 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6811 if (key->ps_epilog.writes_samplemask)
6812 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6813
6814 if (depth || stencil || samplemask)
6815 si_export_mrt_z(bld_base, depth, stencil, samplemask);
6816 else if (last_color_export == -1)
6817 si_export_null(bld_base);
6818
6819 /* Compile. */
6820 LLVMBuildRetVoid(gallivm->builder);
6821 radeon_llvm_finalize_module(&ctx.radeon_bld);
6822
6823 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6824 gallivm->module, debug, ctx.type,
6825 "Fragment Shader Epilog"))
6826 status = false;
6827
6828 radeon_llvm_dispose(&ctx.radeon_bld);
6829 return status;
6830 }
6831
6832 /**
6833 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6834 */
6835 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6836 LLVMTargetMachineRef tm,
6837 struct si_shader *shader,
6838 struct pipe_debug_callback *debug)
6839 {
6840 struct tgsi_shader_info *info = &shader->selector->info;
6841 union si_shader_part_key prolog_key;
6842 union si_shader_part_key epilog_key;
6843 unsigned i;
6844
6845 /* Get the prolog. */
6846 memset(&prolog_key, 0, sizeof(prolog_key));
6847 prolog_key.ps_prolog.states = shader->key.ps.prolog;
6848 prolog_key.ps_prolog.colors_read = info->colors_read;
6849 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6850 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6851
6852 if (info->colors_read) {
6853 unsigned *color = shader->selector->color_attr_index;
6854
6855 if (shader->key.ps.prolog.color_two_side) {
6856 /* BCOLORs are stored after the last input. */
6857 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
6858 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6859 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6860 }
6861
6862 for (i = 0; i < 2; i++) {
6863 unsigned location = info->input_interpolate_loc[color[i]];
6864
6865 if (!(info->colors_read & (0xf << i*4)))
6866 continue;
6867
6868 prolog_key.ps_prolog.color_attr_index[i] = color[i];
6869
6870 /* Force per-sample interpolation for the colors here. */
6871 if (shader->key.ps.prolog.force_persample_interp)
6872 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6873
6874 switch (info->input_interpolate[color[i]]) {
6875 case TGSI_INTERPOLATE_CONSTANT:
6876 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
6877 break;
6878 case TGSI_INTERPOLATE_PERSPECTIVE:
6879 case TGSI_INTERPOLATE_COLOR:
6880 switch (location) {
6881 case TGSI_INTERPOLATE_LOC_SAMPLE:
6882 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
6883 shader->config.spi_ps_input_ena |=
6884 S_0286CC_PERSP_SAMPLE_ENA(1);
6885 break;
6886 case TGSI_INTERPOLATE_LOC_CENTER:
6887 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
6888 shader->config.spi_ps_input_ena |=
6889 S_0286CC_PERSP_CENTER_ENA(1);
6890 break;
6891 case TGSI_INTERPOLATE_LOC_CENTROID:
6892 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
6893 shader->config.spi_ps_input_ena |=
6894 S_0286CC_PERSP_CENTROID_ENA(1);
6895 break;
6896 default:
6897 assert(0);
6898 }
6899 break;
6900 case TGSI_INTERPOLATE_LINEAR:
6901 switch (location) {
6902 case TGSI_INTERPOLATE_LOC_SAMPLE:
6903 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
6904 shader->config.spi_ps_input_ena |=
6905 S_0286CC_LINEAR_SAMPLE_ENA(1);
6906 break;
6907 case TGSI_INTERPOLATE_LOC_CENTER:
6908 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
6909 shader->config.spi_ps_input_ena |=
6910 S_0286CC_LINEAR_CENTER_ENA(1);
6911 break;
6912 case TGSI_INTERPOLATE_LOC_CENTROID:
6913 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
6914 shader->config.spi_ps_input_ena |=
6915 S_0286CC_LINEAR_CENTROID_ENA(1);
6916 break;
6917 default:
6918 assert(0);
6919 }
6920 break;
6921 default:
6922 assert(0);
6923 }
6924 }
6925 }
6926
6927 /* The prolog is a no-op if these aren't set. */
6928 if (prolog_key.ps_prolog.colors_read ||
6929 prolog_key.ps_prolog.states.force_persample_interp ||
6930 prolog_key.ps_prolog.states.poly_stipple) {
6931 shader->prolog =
6932 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6933 &prolog_key, tm, debug,
6934 si_compile_ps_prolog);
6935 if (!shader->prolog)
6936 return false;
6937 }
6938
6939 /* Get the epilog. */
6940 memset(&epilog_key, 0, sizeof(epilog_key));
6941 epilog_key.ps_epilog.colors_written = info->colors_written;
6942 epilog_key.ps_epilog.writes_z = info->writes_z;
6943 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
6944 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
6945 epilog_key.ps_epilog.states = shader->key.ps.epilog;
6946
6947 shader->epilog =
6948 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6949 &epilog_key, tm, debug,
6950 si_compile_ps_epilog);
6951 if (!shader->epilog)
6952 return false;
6953
6954 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6955 if (shader->key.ps.prolog.poly_stipple) {
6956 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6957 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6958 }
6959
6960 /* Set up the enable bits for per-sample shading if needed. */
6961 if (shader->key.ps.prolog.force_persample_interp) {
6962 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6963 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6964 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
6965 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6966 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
6967 }
6968 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6969 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6970 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
6971 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6972 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
6973 }
6974 }
6975
6976 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
6977 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
6978 !(shader->config.spi_ps_input_ena & 0xf)) {
6979 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6980 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
6981 }
6982
6983 /* At least one pair of interpolation weights must be enabled. */
6984 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
6985 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6986 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
6987 }
6988
6989 /* The sample mask input is always enabled, because the API shader always
6990 * passes it through to the epilog. Disable it here if it's unused.
6991 */
6992 if (!shader->key.ps.epilog.poly_line_smoothing &&
6993 !shader->selector->info.reads_samplemask)
6994 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
6995
6996 return true;
6997 }
6998
6999 static void si_fix_num_sgprs(struct si_shader *shader)
7000 {
7001 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7002
7003 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7004 }
7005
7006 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7007 struct si_shader *shader,
7008 struct pipe_debug_callback *debug)
7009 {
7010 struct si_shader *mainp = shader->selector->main_shader_part;
7011 int r;
7012
7013 /* LS, ES, VS are compiled on demand if the main part hasn't been
7014 * compiled for that stage.
7015 */
7016 if (!mainp ||
7017 (shader->selector->type == PIPE_SHADER_VERTEX &&
7018 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7019 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7020 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7021 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7022 shader->selector->type == PIPE_SHADER_COMPUTE) {
7023 /* Monolithic shader (compiled as a whole, has many variants,
7024 * may take a long time to compile).
7025 */
7026 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7027 if (r)
7028 return r;
7029 } else {
7030 /* The shader consists of 2-3 parts:
7031 *
7032 * - the middle part is the user shader, it has 1 variant only
7033 * and it was compiled during the creation of the shader
7034 * selector
7035 * - the prolog part is inserted at the beginning
7036 * - the epilog part is inserted at the end
7037 *
7038 * The prolog and epilog have many (but simple) variants.
7039 */
7040
7041 /* Copy the compiled TGSI shader data over. */
7042 shader->is_binary_shared = true;
7043 shader->binary = mainp->binary;
7044 shader->config = mainp->config;
7045 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7046 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7047 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7048 memcpy(shader->info.vs_output_param_offset,
7049 mainp->info.vs_output_param_offset,
7050 sizeof(mainp->info.vs_output_param_offset));
7051 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7052 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7053 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7054
7055 /* Select prologs and/or epilogs. */
7056 switch (shader->selector->type) {
7057 case PIPE_SHADER_VERTEX:
7058 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7059 return -1;
7060 break;
7061 case PIPE_SHADER_TESS_CTRL:
7062 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7063 return -1;
7064 break;
7065 case PIPE_SHADER_TESS_EVAL:
7066 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7067 return -1;
7068 break;
7069 case PIPE_SHADER_FRAGMENT:
7070 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7071 return -1;
7072
7073 /* Make sure we have at least as many VGPRs as there
7074 * are allocated inputs.
7075 */
7076 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7077 shader->info.num_input_vgprs);
7078 break;
7079 }
7080
7081 /* Update SGPR and VGPR counts. */
7082 if (shader->prolog) {
7083 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7084 shader->prolog->config.num_sgprs);
7085 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7086 shader->prolog->config.num_vgprs);
7087 }
7088 if (shader->epilog) {
7089 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7090 shader->epilog->config.num_sgprs);
7091 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7092 shader->epilog->config.num_vgprs);
7093 }
7094 }
7095
7096 si_fix_num_sgprs(shader);
7097 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7098 stderr);
7099
7100 /* Upload. */
7101 r = si_shader_binary_upload(sscreen, shader);
7102 if (r) {
7103 fprintf(stderr, "LLVM failed to upload shader\n");
7104 return r;
7105 }
7106
7107 return 0;
7108 }
7109
7110 void si_shader_destroy(struct si_shader *shader)
7111 {
7112 if (shader->gs_copy_shader) {
7113 si_shader_destroy(shader->gs_copy_shader);
7114 FREE(shader->gs_copy_shader);
7115 }
7116
7117 if (shader->scratch_bo)
7118 r600_resource_reference(&shader->scratch_bo, NULL);
7119
7120 r600_resource_reference(&shader->bo, NULL);
7121
7122 if (!shader->is_binary_shared)
7123 radeon_shader_binary_clean(&shader->binary);
7124 }