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radeonsi: remove dead code after ES-GS linkage change
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 return LLVMBuildBitCast(gallivm->builder, value,
598 tgsi2llvmtype(bld_base, type), "");
599 }
600
601 /**
602 * Store to LDS.
603 *
604 * \param swizzle offset (typically 0..3)
605 * \param dw_addr address in dwords
606 * \param value value to store
607 */
608 static void lds_store(struct lp_build_tgsi_context * bld_base,
609 unsigned swizzle, LLVMValueRef dw_addr,
610 LLVMValueRef value)
611 {
612 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
613 struct gallivm_state *gallivm = bld_base->base.gallivm;
614
615 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
616 lp_build_const_int32(gallivm, swizzle));
617
618 value = LLVMBuildBitCast(gallivm->builder, value,
619 LLVMInt32TypeInContext(gallivm->context), "");
620 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
621 dw_addr, value);
622 }
623
624 static LLVMValueRef fetch_input_tcs(
625 struct lp_build_tgsi_context *bld_base,
626 const struct tgsi_full_src_register *reg,
627 enum tgsi_opcode_type type, unsigned swizzle)
628 {
629 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
630 LLVMValueRef dw_addr, stride;
631
632 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
633 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
634 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
635
636 return lds_load(bld_base, type, swizzle, dw_addr);
637 }
638
639 static LLVMValueRef fetch_output_tcs(
640 struct lp_build_tgsi_context *bld_base,
641 const struct tgsi_full_src_register *reg,
642 enum tgsi_opcode_type type, unsigned swizzle)
643 {
644 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
645 LLVMValueRef dw_addr, stride;
646
647 if (reg->Register.Dimension) {
648 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
649 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
650 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
651 } else {
652 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
653 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
654 }
655
656 return lds_load(bld_base, type, swizzle, dw_addr);
657 }
658
659 static LLVMValueRef fetch_input_tes(
660 struct lp_build_tgsi_context *bld_base,
661 const struct tgsi_full_src_register *reg,
662 enum tgsi_opcode_type type, unsigned swizzle)
663 {
664 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
665 LLVMValueRef dw_addr, stride;
666
667 if (reg->Register.Dimension) {
668 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
669 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
670 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
671 } else {
672 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
673 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
674 }
675
676 return lds_load(bld_base, type, swizzle, dw_addr);
677 }
678
679 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
680 const struct tgsi_full_instruction * inst,
681 const struct tgsi_opcode_info * info,
682 LLVMValueRef dst[4])
683 {
684 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
685 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
686 unsigned chan_index;
687 LLVMValueRef dw_addr, stride;
688
689 /* Only handle per-patch and per-vertex outputs here.
690 * Vectors will be lowered to scalars and this function will be called again.
691 */
692 if (reg->Register.File != TGSI_FILE_OUTPUT ||
693 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
694 radeon_llvm_emit_store(bld_base, inst, info, dst);
695 return;
696 }
697
698 if (reg->Register.Dimension) {
699 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
700 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
701 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
702 } else {
703 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
704 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
705 }
706
707 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
708 LLVMValueRef value = dst[chan_index];
709
710 if (inst->Instruction.Saturate)
711 value = radeon_llvm_saturate(bld_base, value);
712
713 lds_store(bld_base, chan_index, dw_addr, value);
714 }
715 }
716
717 static LLVMValueRef fetch_input_gs(
718 struct lp_build_tgsi_context *bld_base,
719 const struct tgsi_full_src_register *reg,
720 enum tgsi_opcode_type type,
721 unsigned swizzle)
722 {
723 struct lp_build_context *base = &bld_base->base;
724 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
725 struct si_shader *shader = si_shader_ctx->shader;
726 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
727 struct gallivm_state *gallivm = base->gallivm;
728 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
729 LLVMValueRef vtx_offset;
730 LLVMValueRef args[9];
731 unsigned vtx_offset_param;
732 struct tgsi_shader_info *info = &shader->selector->info;
733 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
734 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
735 unsigned param;
736
737 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
738 return get_primitive_id(bld_base, swizzle);
739
740 if (!reg->Register.Dimension)
741 return NULL;
742
743 if (swizzle == ~0) {
744 LLVMValueRef values[TGSI_NUM_CHANNELS];
745 unsigned chan;
746 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
747 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
748 }
749 return lp_build_gather_values(bld_base->base.gallivm, values,
750 TGSI_NUM_CHANNELS);
751 }
752
753 /* Get the vertex offset parameter */
754 vtx_offset_param = reg->Dimension.Index;
755 if (vtx_offset_param < 2) {
756 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
757 } else {
758 assert(vtx_offset_param < 6);
759 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
760 }
761 vtx_offset = lp_build_mul_imm(uint,
762 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
763 vtx_offset_param),
764 4);
765
766 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
767 args[0] = si_shader_ctx->esgs_ring;
768 args[1] = vtx_offset;
769 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
770 args[3] = uint->zero;
771 args[4] = uint->one; /* OFFEN */
772 args[5] = uint->zero; /* IDXEN */
773 args[6] = uint->one; /* GLC */
774 args[7] = uint->zero; /* SLC */
775 args[8] = uint->zero; /* TFE */
776
777 return LLVMBuildBitCast(gallivm->builder,
778 lp_build_intrinsic(gallivm->builder,
779 "llvm.SI.buffer.load.dword.i32.i32",
780 i32, args, 9,
781 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
782 tgsi2llvmtype(bld_base, type), "");
783 }
784
785 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
786 {
787 switch (interpolate) {
788 case TGSI_INTERPOLATE_CONSTANT:
789 return 0;
790
791 case TGSI_INTERPOLATE_LINEAR:
792 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
793 return SI_PARAM_LINEAR_SAMPLE;
794 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
795 return SI_PARAM_LINEAR_CENTROID;
796 else
797 return SI_PARAM_LINEAR_CENTER;
798 break;
799 case TGSI_INTERPOLATE_COLOR:
800 case TGSI_INTERPOLATE_PERSPECTIVE:
801 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
802 return SI_PARAM_PERSP_SAMPLE;
803 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
804 return SI_PARAM_PERSP_CENTROID;
805 else
806 return SI_PARAM_PERSP_CENTER;
807 break;
808 default:
809 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
810 return -1;
811 }
812 }
813
814 /* This shouldn't be used by explicit INTERP opcodes. */
815 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
816 unsigned param)
817 {
818 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
819 unsigned sample_param = 0;
820 LLVMValueRef default_ij, sample_ij, force_sample;
821
822 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
823
824 /* If the shader doesn't use center/centroid, just return the parameter.
825 *
826 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
827 * switch between center/centroid and sample without shader changes.
828 */
829 switch (param) {
830 case SI_PARAM_PERSP_CENTROID:
831 case SI_PARAM_PERSP_CENTER:
832 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
833 return default_ij;
834
835 sample_param = SI_PARAM_PERSP_SAMPLE;
836 break;
837
838 case SI_PARAM_LINEAR_CENTROID:
839 case SI_PARAM_LINEAR_CENTER:
840 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
841 return default_ij;
842
843 sample_param = SI_PARAM_LINEAR_SAMPLE;
844 break;
845
846 default:
847 return default_ij;
848 }
849
850 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
851 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
852
853 /* TODO: this can be done more efficiently by switching between
854 * 2 prologs.
855 */
856 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
857 SI_PARAM_PS_STATE_BITS);
858 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
859 LLVMInt1TypeInContext(gallivm->context), "");
860 return LLVMBuildSelect(gallivm->builder, force_sample,
861 sample_ij, default_ij, "");
862 }
863
864 static void declare_input_fs(
865 struct radeon_llvm_context *radeon_bld,
866 unsigned input_index,
867 const struct tgsi_full_declaration *decl)
868 {
869 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
870 struct si_shader_context *si_shader_ctx =
871 si_shader_context(&radeon_bld->soa.bld_base);
872 struct si_shader *shader = si_shader_ctx->shader;
873 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
874 struct gallivm_state *gallivm = base->gallivm;
875 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
876 LLVMValueRef main_fn = radeon_bld->main_fn;
877
878 LLVMValueRef interp_param = NULL;
879 int interp_param_idx;
880 const char * intr_name;
881
882 /* This value is:
883 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
884 * quad begins a new primitive. Bit 0 always needs
885 * to be unset)
886 * [32:16] ParamOffset
887 *
888 */
889 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
890 LLVMValueRef attr_number;
891
892 unsigned chan;
893
894 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
895 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
896 unsigned soa_index =
897 radeon_llvm_reg_index_soa(input_index, chan);
898 radeon_bld->inputs[soa_index] =
899 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
900
901 if (chan == 3)
902 /* RCP for fragcoord.w */
903 radeon_bld->inputs[soa_index] =
904 LLVMBuildFDiv(gallivm->builder,
905 lp_build_const_float(gallivm, 1.0f),
906 radeon_bld->inputs[soa_index],
907 "");
908 }
909 return;
910 }
911
912 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
913 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
914 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
915 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
916 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
917 lp_build_const_float(gallivm, 0.0f);
918 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
919 lp_build_const_float(gallivm, 1.0f);
920
921 return;
922 }
923
924 shader->ps_input_param_offset[input_index] = shader->nparam++;
925 attr_number = lp_build_const_int32(gallivm,
926 shader->ps_input_param_offset[input_index]);
927
928 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
929 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
930 decl->Interp.Location);
931 if (interp_param_idx == -1)
932 return;
933 else if (interp_param_idx)
934 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
935
936 /* fs.constant returns the param from the middle vertex, so it's not
937 * really useful for flat shading. It's meant to be used for custom
938 * interpolation (but the intrinsic can't fetch from the other two
939 * vertices).
940 *
941 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
942 * to do the right thing. The only reason we use fs.constant is that
943 * fs.interp cannot be used on integers, because they can be equal
944 * to NaN.
945 */
946 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
947
948 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
949 si_shader_ctx->shader->key.ps.color_two_side) {
950 LLVMValueRef args[4];
951 LLVMValueRef face, is_face_positive;
952 LLVMValueRef back_attr_number =
953 lp_build_const_int32(gallivm,
954 shader->ps_input_param_offset[input_index] + 1);
955
956 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
957
958 is_face_positive = LLVMBuildFCmp(gallivm->builder,
959 LLVMRealOGT, face,
960 lp_build_const_float(gallivm, 0.0f),
961 "");
962
963 args[2] = params;
964 args[3] = interp_param;
965 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
966 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
967 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
968 LLVMValueRef front, back;
969
970 args[0] = llvm_chan;
971 args[1] = attr_number;
972 front = lp_build_intrinsic(gallivm->builder, intr_name,
973 input_type, args, args[3] ? 4 : 3,
974 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
975
976 args[1] = back_attr_number;
977 back = lp_build_intrinsic(gallivm->builder, intr_name,
978 input_type, args, args[3] ? 4 : 3,
979 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
980
981 radeon_bld->inputs[soa_index] =
982 LLVMBuildSelect(gallivm->builder,
983 is_face_positive,
984 front,
985 back,
986 "");
987 }
988
989 shader->nparam++;
990 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
991 LLVMValueRef args[4];
992
993 args[0] = uint->zero;
994 args[1] = attr_number;
995 args[2] = params;
996 args[3] = interp_param;
997 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
998 lp_build_intrinsic(gallivm->builder, intr_name,
999 input_type, args, args[3] ? 4 : 3,
1000 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1001 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1002 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1003 lp_build_const_float(gallivm, 0.0f);
1004 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1005 lp_build_const_float(gallivm, 1.0f);
1006 } else {
1007 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1008 LLVMValueRef args[4];
1009 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1010 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1011 args[0] = llvm_chan;
1012 args[1] = attr_number;
1013 args[2] = params;
1014 args[3] = interp_param;
1015 radeon_bld->inputs[soa_index] =
1016 lp_build_intrinsic(gallivm->builder, intr_name,
1017 input_type, args, args[3] ? 4 : 3,
1018 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1019 }
1020 }
1021 }
1022
1023 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1024 {
1025 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1026 SI_PARAM_ANCILLARY, 8, 4);
1027 }
1028
1029 /**
1030 * Load a dword from a constant buffer.
1031 */
1032 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1033 LLVMValueRef offset, LLVMTypeRef return_type)
1034 {
1035 LLVMValueRef args[2] = {resource, offset};
1036
1037 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1038 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1039 }
1040
1041 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1042 {
1043 struct si_shader_context *si_shader_ctx =
1044 si_shader_context(&radeon_bld->soa.bld_base);
1045 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1046 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1047 LLVMBuilderRef builder = gallivm->builder;
1048 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1049 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1050 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1051
1052 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1053 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1054 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1055
1056 LLVMValueRef pos[4] = {
1057 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1058 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1059 lp_build_const_float(gallivm, 0),
1060 lp_build_const_float(gallivm, 0)
1061 };
1062
1063 return lp_build_gather_values(gallivm, pos, 4);
1064 }
1065
1066 static void declare_system_value(
1067 struct radeon_llvm_context * radeon_bld,
1068 unsigned index,
1069 const struct tgsi_full_declaration *decl)
1070 {
1071 struct si_shader_context *si_shader_ctx =
1072 si_shader_context(&radeon_bld->soa.bld_base);
1073 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1074 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1075 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1076 LLVMValueRef value = 0;
1077
1078 switch (decl->Semantic.Name) {
1079 case TGSI_SEMANTIC_INSTANCEID:
1080 value = LLVMGetParam(radeon_bld->main_fn,
1081 si_shader_ctx->param_instance_id);
1082 break;
1083
1084 case TGSI_SEMANTIC_VERTEXID:
1085 value = LLVMBuildAdd(gallivm->builder,
1086 LLVMGetParam(radeon_bld->main_fn,
1087 si_shader_ctx->param_vertex_id),
1088 LLVMGetParam(radeon_bld->main_fn,
1089 SI_PARAM_BASE_VERTEX), "");
1090 break;
1091
1092 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1093 value = LLVMGetParam(radeon_bld->main_fn,
1094 si_shader_ctx->param_vertex_id);
1095 break;
1096
1097 case TGSI_SEMANTIC_BASEVERTEX:
1098 value = LLVMGetParam(radeon_bld->main_fn,
1099 SI_PARAM_BASE_VERTEX);
1100 break;
1101
1102 case TGSI_SEMANTIC_INVOCATIONID:
1103 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1104 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1105 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1106 value = LLVMGetParam(radeon_bld->main_fn,
1107 SI_PARAM_GS_INSTANCE_ID);
1108 else
1109 assert(!"INVOCATIONID not implemented");
1110 break;
1111
1112 case TGSI_SEMANTIC_SAMPLEID:
1113 value = get_sample_id(radeon_bld);
1114 break;
1115
1116 case TGSI_SEMANTIC_SAMPLEPOS:
1117 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1118 break;
1119
1120 case TGSI_SEMANTIC_SAMPLEMASK:
1121 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1122 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1123 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1124 value = uint_bld->one;
1125 else
1126 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1127 break;
1128
1129 case TGSI_SEMANTIC_TESSCOORD:
1130 {
1131 LLVMValueRef coord[4] = {
1132 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1133 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1134 bld->zero,
1135 bld->zero
1136 };
1137
1138 /* For triangles, the vector should be (u, v, 1-u-v). */
1139 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1140 PIPE_PRIM_TRIANGLES)
1141 coord[2] = lp_build_sub(bld, bld->one,
1142 lp_build_add(bld, coord[0], coord[1]));
1143
1144 value = lp_build_gather_values(gallivm, coord, 4);
1145 break;
1146 }
1147
1148 case TGSI_SEMANTIC_VERTICESIN:
1149 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1150 break;
1151
1152 case TGSI_SEMANTIC_TESSINNER:
1153 case TGSI_SEMANTIC_TESSOUTER:
1154 {
1155 LLVMValueRef dw_addr;
1156 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1157
1158 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1159 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1160 lp_build_const_int32(gallivm, param * 4), "");
1161
1162 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1163 ~0, dw_addr);
1164 break;
1165 }
1166
1167 case TGSI_SEMANTIC_PRIMID:
1168 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1169 break;
1170
1171 default:
1172 assert(!"unknown system value");
1173 return;
1174 }
1175
1176 radeon_bld->system_values[index] = value;
1177 }
1178
1179 static LLVMValueRef fetch_constant(
1180 struct lp_build_tgsi_context * bld_base,
1181 const struct tgsi_full_src_register *reg,
1182 enum tgsi_opcode_type type,
1183 unsigned swizzle)
1184 {
1185 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1186 struct lp_build_context * base = &bld_base->base;
1187 const struct tgsi_ind_register *ireg = &reg->Indirect;
1188 unsigned buf, idx;
1189
1190 LLVMValueRef addr, bufp;
1191 LLVMValueRef result;
1192
1193 if (swizzle == LP_CHAN_ALL) {
1194 unsigned chan;
1195 LLVMValueRef values[4];
1196 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1197 values[chan] = fetch_constant(bld_base, reg, type, chan);
1198
1199 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1200 }
1201
1202 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1203 idx = reg->Register.Index * 4 + swizzle;
1204
1205 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1206 if (type != TGSI_TYPE_DOUBLE)
1207 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1208 else {
1209 return radeon_llvm_emit_fetch_double(bld_base,
1210 si_shader_ctx->constants[buf][idx],
1211 si_shader_ctx->constants[buf][idx + 1]);
1212 }
1213 }
1214
1215 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1216 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1217 LLVMValueRef index;
1218 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1219 reg->Dimension.Index);
1220 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1221 } else
1222 bufp = si_shader_ctx->const_resource[buf];
1223
1224 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1225 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1226 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1227 addr = lp_build_add(&bld_base->uint_bld, addr,
1228 lp_build_const_int32(base->gallivm, idx * 4));
1229
1230 result = buffer_load_const(base->gallivm->builder, bufp,
1231 addr, bld_base->base.elem_type);
1232
1233 if (type != TGSI_TYPE_DOUBLE)
1234 result = bitcast(bld_base, type, result);
1235 else {
1236 LLVMValueRef addr2, result2;
1237 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1238 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1239 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1240 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1241 lp_build_const_int32(base->gallivm, idx * 4));
1242
1243 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1244 addr2, bld_base->base.elem_type);
1245
1246 result = radeon_llvm_emit_fetch_double(bld_base,
1247 result, result2);
1248 }
1249 return result;
1250 }
1251
1252 /* Initialize arguments for the shader export intrinsic */
1253 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1254 LLVMValueRef *values,
1255 unsigned target,
1256 LLVMValueRef *args)
1257 {
1258 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1259 struct lp_build_context *uint =
1260 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1261 struct lp_build_context *base = &bld_base->base;
1262 unsigned compressed = 0;
1263 unsigned chan;
1264
1265 /* XXX: This controls which components of the output
1266 * registers actually get exported. (e.g bit 0 means export
1267 * X component, bit 1 means export Y component, etc.) I'm
1268 * hard coding this to 0xf for now. In the future, we might
1269 * want to do something else.
1270 */
1271 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1272
1273 /* Specify whether the EXEC mask represents the valid mask */
1274 args[1] = uint->zero;
1275
1276 /* Specify whether this is the last export */
1277 args[2] = uint->zero;
1278
1279 /* Specify the target we are exporting */
1280 args[3] = lp_build_const_int32(base->gallivm, target);
1281
1282 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1283 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1284
1285 if (cbuf >= 0 && cbuf < 8) {
1286 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1287
1288 if (compressed)
1289 si_shader_ctx->shader->spi_shader_col_format |=
1290 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1291 else
1292 si_shader_ctx->shader->spi_shader_col_format |=
1293 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1294
1295 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1296 }
1297 }
1298
1299 /* Set COMPR flag */
1300 args[4] = compressed ? uint->one : uint->zero;
1301
1302 if (compressed) {
1303 /* Pixel shader needs to pack output values before export */
1304 for (chan = 0; chan < 2; chan++) {
1305 LLVMValueRef pack_args[2] = {
1306 values[2 * chan],
1307 values[2 * chan + 1]
1308 };
1309 LLVMValueRef packed;
1310
1311 packed = lp_build_intrinsic(base->gallivm->builder,
1312 "llvm.SI.packf16",
1313 LLVMInt32TypeInContext(base->gallivm->context),
1314 pack_args, 2,
1315 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1316 args[chan + 7] = args[chan + 5] =
1317 LLVMBuildBitCast(base->gallivm->builder,
1318 packed,
1319 LLVMFloatTypeInContext(base->gallivm->context),
1320 "");
1321 }
1322 } else
1323 memcpy(&args[5], values, sizeof(values[0]) * 4);
1324 }
1325
1326 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1327 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1328 LLVMValueRef *out_ptr,
1329 unsigned target,
1330 LLVMValueRef *args)
1331 {
1332 struct gallivm_state *gallivm = bld_base->base.gallivm;
1333 LLVMValueRef values[4];
1334 int i;
1335
1336 for (i = 0; i < 4; i++)
1337 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1338
1339 si_llvm_init_export_args(bld_base, values, target, args);
1340 }
1341
1342 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1343 LLVMValueRef alpha_ptr)
1344 {
1345 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1346 struct gallivm_state *gallivm = bld_base->base.gallivm;
1347
1348 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1349 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1350 SI_PARAM_ALPHA_REF);
1351
1352 LLVMValueRef alpha_pass =
1353 lp_build_cmp(&bld_base->base,
1354 si_shader_ctx->shader->key.ps.alpha_func,
1355 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1356 alpha_ref);
1357 LLVMValueRef arg =
1358 lp_build_select(&bld_base->base,
1359 alpha_pass,
1360 lp_build_const_float(gallivm, 1.0f),
1361 lp_build_const_float(gallivm, -1.0f));
1362
1363 lp_build_intrinsic(gallivm->builder,
1364 "llvm.AMDGPU.kill",
1365 LLVMVoidTypeInContext(gallivm->context),
1366 &arg, 1, 0);
1367 } else {
1368 lp_build_intrinsic(gallivm->builder,
1369 "llvm.AMDGPU.kilp",
1370 LLVMVoidTypeInContext(gallivm->context),
1371 NULL, 0, 0);
1372 }
1373
1374 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1375 }
1376
1377 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1378 LLVMValueRef alpha_ptr)
1379 {
1380 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1381 struct gallivm_state *gallivm = bld_base->base.gallivm;
1382 LLVMValueRef coverage, alpha;
1383
1384 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1385 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1386 SI_PARAM_SAMPLE_COVERAGE);
1387 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1388
1389 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1390 bld_base->int_bld.elem_type,
1391 &coverage, 1, LLVMReadNoneAttribute);
1392
1393 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1394 bld_base->base.elem_type, "");
1395
1396 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1397 lp_build_const_float(gallivm,
1398 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1399
1400 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1401 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1402 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1403 }
1404
1405 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1406 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1407 {
1408 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1409 struct lp_build_context *base = &bld_base->base;
1410 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1411 unsigned reg_index;
1412 unsigned chan;
1413 unsigned const_chan;
1414 LLVMValueRef base_elt;
1415 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1416 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1417 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1418
1419 for (reg_index = 0; reg_index < 2; reg_index ++) {
1420 LLVMValueRef *args = pos[2 + reg_index];
1421
1422 args[5] =
1423 args[6] =
1424 args[7] =
1425 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1426
1427 /* Compute dot products of position and user clip plane vectors */
1428 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1429 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1430 args[1] = lp_build_const_int32(base->gallivm,
1431 ((reg_index * 4 + chan) * 4 +
1432 const_chan) * 4);
1433 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1434 args[1], base->elem_type);
1435 args[5 + chan] =
1436 lp_build_add(base, args[5 + chan],
1437 lp_build_mul(base, base_elt,
1438 out_elts[const_chan]));
1439 }
1440 }
1441
1442 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1443 args[1] = uint->zero;
1444 args[2] = uint->zero;
1445 args[3] = lp_build_const_int32(base->gallivm,
1446 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1447 args[4] = uint->zero;
1448 }
1449 }
1450
1451 static void si_dump_streamout(struct pipe_stream_output_info *so)
1452 {
1453 unsigned i;
1454
1455 if (so->num_outputs)
1456 fprintf(stderr, "STREAMOUT\n");
1457
1458 for (i = 0; i < so->num_outputs; i++) {
1459 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1460 so->output[i].start_component;
1461 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1462 i, so->output[i].output_buffer,
1463 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1464 so->output[i].register_index,
1465 mask & 1 ? "x" : "",
1466 mask & 2 ? "y" : "",
1467 mask & 4 ? "z" : "",
1468 mask & 8 ? "w" : "");
1469 }
1470 }
1471
1472 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1473 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1474 * or v4i32 (num_channels=3,4). */
1475 static void build_tbuffer_store(struct si_shader_context *shader,
1476 LLVMValueRef rsrc,
1477 LLVMValueRef vdata,
1478 unsigned num_channels,
1479 LLVMValueRef vaddr,
1480 LLVMValueRef soffset,
1481 unsigned inst_offset,
1482 unsigned dfmt,
1483 unsigned nfmt,
1484 unsigned offen,
1485 unsigned idxen,
1486 unsigned glc,
1487 unsigned slc,
1488 unsigned tfe)
1489 {
1490 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1491 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1492 LLVMValueRef args[] = {
1493 rsrc,
1494 vdata,
1495 LLVMConstInt(i32, num_channels, 0),
1496 vaddr,
1497 soffset,
1498 LLVMConstInt(i32, inst_offset, 0),
1499 LLVMConstInt(i32, dfmt, 0),
1500 LLVMConstInt(i32, nfmt, 0),
1501 LLVMConstInt(i32, offen, 0),
1502 LLVMConstInt(i32, idxen, 0),
1503 LLVMConstInt(i32, glc, 0),
1504 LLVMConstInt(i32, slc, 0),
1505 LLVMConstInt(i32, tfe, 0)
1506 };
1507
1508 /* The instruction offset field has 12 bits */
1509 assert(offen || inst_offset < (1 << 12));
1510
1511 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1512 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1513 const char *types[] = {"i32", "v2i32", "v4i32"};
1514 char name[256];
1515 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1516
1517 lp_build_intrinsic(gallivm->builder, name,
1518 LLVMVoidTypeInContext(gallivm->context),
1519 args, Elements(args), 0);
1520 }
1521
1522 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1523 LLVMValueRef rsrc,
1524 LLVMValueRef vdata,
1525 unsigned num_channels,
1526 LLVMValueRef vaddr,
1527 LLVMValueRef soffset,
1528 unsigned inst_offset)
1529 {
1530 static unsigned dfmt[] = {
1531 V_008F0C_BUF_DATA_FORMAT_32,
1532 V_008F0C_BUF_DATA_FORMAT_32_32,
1533 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1534 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1535 };
1536 assert(num_channels >= 1 && num_channels <= 4);
1537
1538 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1539 inst_offset, dfmt[num_channels-1],
1540 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1541 }
1542
1543 /* On SI, the vertex shader is responsible for writing streamout data
1544 * to buffers. */
1545 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1546 struct si_shader_output_values *outputs,
1547 unsigned noutput)
1548 {
1549 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1550 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1551 LLVMBuilderRef builder = gallivm->builder;
1552 int i, j;
1553 struct lp_build_if_state if_ctx;
1554
1555 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1556
1557 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1558 LLVMValueRef so_vtx_count =
1559 unpack_param(shader, shader->param_streamout_config, 16, 7);
1560
1561 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1562 NULL, 0, LLVMReadNoneAttribute);
1563
1564 /* can_emit = tid < so_vtx_count; */
1565 LLVMValueRef can_emit =
1566 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1567
1568 LLVMValueRef stream_id =
1569 unpack_param(shader, shader->param_streamout_config, 24, 2);
1570
1571 /* Emit the streamout code conditionally. This actually avoids
1572 * out-of-bounds buffer access. The hw tells us via the SGPR
1573 * (so_vtx_count) which threads are allowed to emit streamout data. */
1574 lp_build_if(&if_ctx, gallivm, can_emit);
1575 {
1576 /* The buffer offset is computed as follows:
1577 * ByteOffset = streamout_offset[buffer_id]*4 +
1578 * (streamout_write_index + thread_id)*stride[buffer_id] +
1579 * attrib_offset
1580 */
1581
1582 LLVMValueRef so_write_index =
1583 LLVMGetParam(shader->radeon_bld.main_fn,
1584 shader->param_streamout_write_index);
1585
1586 /* Compute (streamout_write_index + thread_id). */
1587 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1588
1589 /* Compute the write offset for each enabled buffer. */
1590 LLVMValueRef so_write_offset[4] = {};
1591 for (i = 0; i < 4; i++) {
1592 if (!so->stride[i])
1593 continue;
1594
1595 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1596 shader->param_streamout_offset[i]);
1597 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1598
1599 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1600 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1601 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1602 }
1603
1604 /* Write streamout data. */
1605 for (i = 0; i < so->num_outputs; i++) {
1606 unsigned buf_idx = so->output[i].output_buffer;
1607 unsigned reg = so->output[i].register_index;
1608 unsigned start = so->output[i].start_component;
1609 unsigned num_comps = so->output[i].num_components;
1610 unsigned stream = so->output[i].stream;
1611 LLVMValueRef out[4];
1612 struct lp_build_if_state if_ctx_stream;
1613
1614 assert(num_comps && num_comps <= 4);
1615 if (!num_comps || num_comps > 4)
1616 continue;
1617
1618 if (reg >= noutput)
1619 continue;
1620
1621 /* Load the output as int. */
1622 for (j = 0; j < num_comps; j++) {
1623 out[j] = LLVMBuildBitCast(builder,
1624 outputs[reg].values[start+j],
1625 i32, "");
1626 }
1627
1628 /* Pack the output. */
1629 LLVMValueRef vdata = NULL;
1630
1631 switch (num_comps) {
1632 case 1: /* as i32 */
1633 vdata = out[0];
1634 break;
1635 case 2: /* as v2i32 */
1636 case 3: /* as v4i32 (aligned to 4) */
1637 case 4: /* as v4i32 */
1638 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1639 for (j = 0; j < num_comps; j++) {
1640 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1641 LLVMConstInt(i32, j, 0), "");
1642 }
1643 break;
1644 }
1645
1646 LLVMValueRef can_emit_stream =
1647 LLVMBuildICmp(builder, LLVMIntEQ,
1648 stream_id,
1649 lp_build_const_int32(gallivm, stream), "");
1650
1651 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1652 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1653 vdata, num_comps,
1654 so_write_offset[buf_idx],
1655 LLVMConstInt(i32, 0, 0),
1656 so->output[i].dst_offset*4);
1657 lp_build_endif(&if_ctx_stream);
1658 }
1659 }
1660 lp_build_endif(&if_ctx);
1661 }
1662
1663
1664 /* Generate export instructions for hardware VS shader stage */
1665 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1666 struct si_shader_output_values *outputs,
1667 unsigned noutput)
1668 {
1669 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1670 struct si_shader * shader = si_shader_ctx->shader;
1671 struct lp_build_context * base = &bld_base->base;
1672 struct lp_build_context * uint =
1673 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1674 LLVMValueRef args[9];
1675 LLVMValueRef pos_args[4][9] = { { 0 } };
1676 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1677 unsigned semantic_name, semantic_index;
1678 unsigned target;
1679 unsigned param_count = 0;
1680 unsigned pos_idx;
1681 int i;
1682
1683 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1684 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1685 }
1686
1687 for (i = 0; i < noutput; i++) {
1688 semantic_name = outputs[i].name;
1689 semantic_index = outputs[i].sid;
1690
1691 handle_semantic:
1692 /* Select the correct target */
1693 switch(semantic_name) {
1694 case TGSI_SEMANTIC_PSIZE:
1695 psize_value = outputs[i].values[0];
1696 continue;
1697 case TGSI_SEMANTIC_EDGEFLAG:
1698 edgeflag_value = outputs[i].values[0];
1699 continue;
1700 case TGSI_SEMANTIC_LAYER:
1701 layer_value = outputs[i].values[0];
1702 semantic_name = TGSI_SEMANTIC_GENERIC;
1703 goto handle_semantic;
1704 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1705 viewport_index_value = outputs[i].values[0];
1706 semantic_name = TGSI_SEMANTIC_GENERIC;
1707 goto handle_semantic;
1708 case TGSI_SEMANTIC_POSITION:
1709 target = V_008DFC_SQ_EXP_POS;
1710 break;
1711 case TGSI_SEMANTIC_COLOR:
1712 case TGSI_SEMANTIC_BCOLOR:
1713 target = V_008DFC_SQ_EXP_PARAM + param_count;
1714 shader->vs_output_param_offset[i] = param_count;
1715 param_count++;
1716 break;
1717 case TGSI_SEMANTIC_CLIPDIST:
1718 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1719 break;
1720 case TGSI_SEMANTIC_CLIPVERTEX:
1721 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1722 continue;
1723 case TGSI_SEMANTIC_PRIMID:
1724 case TGSI_SEMANTIC_FOG:
1725 case TGSI_SEMANTIC_TEXCOORD:
1726 case TGSI_SEMANTIC_GENERIC:
1727 target = V_008DFC_SQ_EXP_PARAM + param_count;
1728 shader->vs_output_param_offset[i] = param_count;
1729 param_count++;
1730 break;
1731 default:
1732 target = 0;
1733 fprintf(stderr,
1734 "Warning: SI unhandled vs output type:%d\n",
1735 semantic_name);
1736 }
1737
1738 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1739
1740 if (target >= V_008DFC_SQ_EXP_POS &&
1741 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1742 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1743 args, sizeof(args));
1744 } else {
1745 lp_build_intrinsic(base->gallivm->builder,
1746 "llvm.SI.export",
1747 LLVMVoidTypeInContext(base->gallivm->context),
1748 args, 9, 0);
1749 }
1750
1751 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1752 semantic_name = TGSI_SEMANTIC_GENERIC;
1753 goto handle_semantic;
1754 }
1755 }
1756
1757 shader->nr_param_exports = param_count;
1758
1759 /* We need to add the position output manually if it's missing. */
1760 if (!pos_args[0][0]) {
1761 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1762 pos_args[0][1] = uint->zero; /* EXEC mask */
1763 pos_args[0][2] = uint->zero; /* last export? */
1764 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1765 pos_args[0][4] = uint->zero; /* COMPR flag */
1766 pos_args[0][5] = base->zero; /* X */
1767 pos_args[0][6] = base->zero; /* Y */
1768 pos_args[0][7] = base->zero; /* Z */
1769 pos_args[0][8] = base->one; /* W */
1770 }
1771
1772 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1773 if (shader->selector->info.writes_psize ||
1774 shader->selector->info.writes_edgeflag ||
1775 shader->selector->info.writes_viewport_index ||
1776 shader->selector->info.writes_layer) {
1777 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1778 shader->selector->info.writes_psize |
1779 (shader->selector->info.writes_edgeflag << 1) |
1780 (shader->selector->info.writes_layer << 2) |
1781 (shader->selector->info.writes_viewport_index << 3));
1782 pos_args[1][1] = uint->zero; /* EXEC mask */
1783 pos_args[1][2] = uint->zero; /* last export? */
1784 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1785 pos_args[1][4] = uint->zero; /* COMPR flag */
1786 pos_args[1][5] = base->zero; /* X */
1787 pos_args[1][6] = base->zero; /* Y */
1788 pos_args[1][7] = base->zero; /* Z */
1789 pos_args[1][8] = base->zero; /* W */
1790
1791 if (shader->selector->info.writes_psize)
1792 pos_args[1][5] = psize_value;
1793
1794 if (shader->selector->info.writes_edgeflag) {
1795 /* The output is a float, but the hw expects an integer
1796 * with the first bit containing the edge flag. */
1797 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1798 edgeflag_value,
1799 bld_base->uint_bld.elem_type, "");
1800 edgeflag_value = lp_build_min(&bld_base->int_bld,
1801 edgeflag_value,
1802 bld_base->int_bld.one);
1803
1804 /* The LLVM intrinsic expects a float. */
1805 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1806 edgeflag_value,
1807 base->elem_type, "");
1808 }
1809
1810 if (shader->selector->info.writes_layer)
1811 pos_args[1][7] = layer_value;
1812
1813 if (shader->selector->info.writes_viewport_index)
1814 pos_args[1][8] = viewport_index_value;
1815 }
1816
1817 for (i = 0; i < 4; i++)
1818 if (pos_args[i][0])
1819 shader->nr_pos_exports++;
1820
1821 pos_idx = 0;
1822 for (i = 0; i < 4; i++) {
1823 if (!pos_args[i][0])
1824 continue;
1825
1826 /* Specify the target we are exporting */
1827 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1828
1829 if (pos_idx == shader->nr_pos_exports)
1830 /* Specify that this is the last export */
1831 pos_args[i][2] = uint->one;
1832
1833 lp_build_intrinsic(base->gallivm->builder,
1834 "llvm.SI.export",
1835 LLVMVoidTypeInContext(base->gallivm->context),
1836 pos_args[i], 9, 0);
1837 }
1838 }
1839
1840 /* This only writes the tessellation factor levels. */
1841 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1842 {
1843 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1844 struct gallivm_state *gallivm = bld_base->base.gallivm;
1845 struct si_shader *shader = si_shader_ctx->shader;
1846 unsigned tess_inner_index, tess_outer_index;
1847 LLVMValueRef lds_base, lds_inner, lds_outer;
1848 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1849 LLVMValueRef out[6], vec0, vec1, invocation_id;
1850 unsigned stride, outer_comps, inner_comps, i;
1851 struct lp_build_if_state if_ctx;
1852
1853 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1854
1855 /* Do this only for invocation 0, because the tess levels are per-patch,
1856 * not per-vertex.
1857 *
1858 * This can't jump, because invocation 0 executes this. It should
1859 * at least mask out the loads and stores for other invocations.
1860 */
1861 lp_build_if(&if_ctx, gallivm,
1862 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1863 invocation_id, bld_base->uint_bld.zero, ""));
1864
1865 /* Determine the layout of one tess factor element in the buffer. */
1866 switch (shader->key.tcs.prim_mode) {
1867 case PIPE_PRIM_LINES:
1868 stride = 2; /* 2 dwords, 1 vec2 store */
1869 outer_comps = 2;
1870 inner_comps = 0;
1871 break;
1872 case PIPE_PRIM_TRIANGLES:
1873 stride = 4; /* 4 dwords, 1 vec4 store */
1874 outer_comps = 3;
1875 inner_comps = 1;
1876 break;
1877 case PIPE_PRIM_QUADS:
1878 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1879 outer_comps = 4;
1880 inner_comps = 2;
1881 break;
1882 default:
1883 assert(0);
1884 return;
1885 }
1886
1887 /* Load tess_inner and tess_outer from LDS.
1888 * Any invocation can write them, so we can't get them from a temporary.
1889 */
1890 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1891 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1892
1893 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1894 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1895 lp_build_const_int32(gallivm,
1896 tess_inner_index * 4), "");
1897 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1898 lp_build_const_int32(gallivm,
1899 tess_outer_index * 4), "");
1900
1901 for (i = 0; i < outer_comps; i++)
1902 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1903 for (i = 0; i < inner_comps; i++)
1904 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1905
1906 /* Convert the outputs to vectors for stores. */
1907 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1908 vec1 = NULL;
1909
1910 if (stride > 4)
1911 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1912
1913 /* Get the buffer. */
1914 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1915 SI_PARAM_RW_BUFFERS);
1916 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1917 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1918
1919 /* Get the offset. */
1920 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1921 SI_PARAM_TESS_FACTOR_OFFSET);
1922 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1923 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1924 lp_build_const_int32(gallivm, 4 * stride), "");
1925
1926 /* Store the outputs. */
1927 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1928 MIN2(stride, 4), byteoffset, tf_base, 0);
1929 if (vec1)
1930 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1931 stride - 4, byteoffset, tf_base, 16);
1932 lp_build_endif(&if_ctx);
1933 }
1934
1935 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1936 {
1937 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1938 struct si_shader *shader = si_shader_ctx->shader;
1939 struct tgsi_shader_info *info = &shader->selector->info;
1940 struct gallivm_state *gallivm = bld_base->base.gallivm;
1941 unsigned i, chan;
1942 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1943 si_shader_ctx->param_rel_auto_id);
1944 LLVMValueRef vertex_dw_stride =
1945 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1946 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1947 vertex_dw_stride, "");
1948
1949 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1950 * its inputs from it. */
1951 for (i = 0; i < info->num_outputs; i++) {
1952 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1953 unsigned name = info->output_semantic_name[i];
1954 unsigned index = info->output_semantic_index[i];
1955 int param = si_shader_io_get_unique_index(name, index);
1956 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1957 lp_build_const_int32(gallivm, param * 4), "");
1958
1959 for (chan = 0; chan < 4; chan++) {
1960 lds_store(bld_base, chan, dw_addr,
1961 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1962 }
1963 }
1964 }
1965
1966 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1967 {
1968 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1969 struct gallivm_state *gallivm = bld_base->base.gallivm;
1970 struct si_shader *es = si_shader_ctx->shader;
1971 struct tgsi_shader_info *info = &es->selector->info;
1972 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1973 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1974 si_shader_ctx->param_es2gs_offset);
1975 unsigned chan;
1976 int i;
1977
1978 for (i = 0; i < info->num_outputs; i++) {
1979 LLVMValueRef *out_ptr =
1980 si_shader_ctx->radeon_bld.soa.outputs[i];
1981 int param_index;
1982
1983 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1984 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1985 continue;
1986
1987 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
1988 info->output_semantic_index[i]);
1989
1990 for (chan = 0; chan < 4; chan++) {
1991 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1992 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1993
1994 build_tbuffer_store(si_shader_ctx,
1995 si_shader_ctx->esgs_ring,
1996 out_val, 1,
1997 LLVMGetUndef(i32), soffset,
1998 (4 * param_index + chan) * 4,
1999 V_008F0C_BUF_DATA_FORMAT_32,
2000 V_008F0C_BUF_NUM_FORMAT_UINT,
2001 0, 0, 1, 1, 0);
2002 }
2003 }
2004 }
2005
2006 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2007 {
2008 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2009 struct gallivm_state *gallivm = bld_base->base.gallivm;
2010 LLVMValueRef args[2];
2011
2012 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2013 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2014 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2015 LLVMVoidTypeInContext(gallivm->context), args, 2,
2016 LLVMNoUnwindAttribute);
2017 }
2018
2019 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2020 {
2021 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2022 struct gallivm_state *gallivm = bld_base->base.gallivm;
2023 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2024 struct si_shader_output_values *outputs = NULL;
2025 int i,j;
2026
2027 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2028
2029 /* Vertex color clamping.
2030 *
2031 * This uses a state constant loaded in a user data SGPR and
2032 * an IF statement is added that clamps all colors if the constant
2033 * is true.
2034 */
2035 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2036 !si_shader_ctx->shader->is_gs_copy_shader) {
2037 struct lp_build_if_state if_ctx;
2038 LLVMValueRef cond = NULL;
2039 LLVMValueRef addr, val;
2040
2041 for (i = 0; i < info->num_outputs; i++) {
2042 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2043 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2044 continue;
2045
2046 /* We've found a color. */
2047 if (!cond) {
2048 /* The state is in the first bit of the user SGPR. */
2049 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2050 SI_PARAM_VS_STATE_BITS);
2051 cond = LLVMBuildTrunc(gallivm->builder, cond,
2052 LLVMInt1TypeInContext(gallivm->context), "");
2053 lp_build_if(&if_ctx, gallivm, cond);
2054 }
2055
2056 for (j = 0; j < 4; j++) {
2057 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2058 val = LLVMBuildLoad(gallivm->builder, addr, "");
2059 val = radeon_llvm_saturate(bld_base, val);
2060 LLVMBuildStore(gallivm->builder, val, addr);
2061 }
2062 }
2063
2064 if (cond)
2065 lp_build_endif(&if_ctx);
2066 }
2067
2068 for (i = 0; i < info->num_outputs; i++) {
2069 outputs[i].name = info->output_semantic_name[i];
2070 outputs[i].sid = info->output_semantic_index[i];
2071
2072 for (j = 0; j < 4; j++)
2073 outputs[i].values[j] =
2074 LLVMBuildLoad(gallivm->builder,
2075 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2076 "");
2077 }
2078
2079 /* Export PrimitiveID when PS needs it. */
2080 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2081 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2082 outputs[i].sid = 0;
2083 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2084 get_primitive_id(bld_base, 0));
2085 outputs[i].values[1] = bld_base->base.undef;
2086 outputs[i].values[2] = bld_base->base.undef;
2087 outputs[i].values[3] = bld_base->base.undef;
2088 i++;
2089 }
2090
2091 si_llvm_export_vs(bld_base, outputs, i);
2092 FREE(outputs);
2093 }
2094
2095 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2096 {
2097 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2098 struct si_shader * shader = si_shader_ctx->shader;
2099 struct lp_build_context * base = &bld_base->base;
2100 struct lp_build_context * uint = &bld_base->uint_bld;
2101 struct tgsi_shader_info *info = &shader->selector->info;
2102 LLVMBuilderRef builder = base->gallivm->builder;
2103 LLVMValueRef args[9];
2104 LLVMValueRef last_args[9] = { 0 };
2105 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2106 int i;
2107
2108 for (i = 0; i < info->num_outputs; i++) {
2109 unsigned semantic_name = info->output_semantic_name[i];
2110 unsigned semantic_index = info->output_semantic_index[i];
2111 unsigned target;
2112 LLVMValueRef alpha_ptr;
2113
2114 /* Select the correct target */
2115 switch (semantic_name) {
2116 case TGSI_SEMANTIC_POSITION:
2117 depth_index = i;
2118 continue;
2119 case TGSI_SEMANTIC_STENCIL:
2120 stencil_index = i;
2121 continue;
2122 case TGSI_SEMANTIC_SAMPLEMASK:
2123 samplemask_index = i;
2124 continue;
2125 case TGSI_SEMANTIC_COLOR:
2126 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2127 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2128
2129 if (si_shader_ctx->shader->key.ps.clamp_color) {
2130 for (int j = 0; j < 4; j++) {
2131 LLVMValueRef ptr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2132 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2133
2134 result = radeon_llvm_saturate(bld_base, result);
2135 LLVMBuildStore(builder, result, ptr);
2136 }
2137 }
2138
2139 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2140 LLVMBuildStore(base->gallivm->builder,
2141 base->one, alpha_ptr);
2142
2143 if (semantic_index == 0 &&
2144 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2145 si_alpha_test(bld_base, alpha_ptr);
2146
2147 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2148 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2149
2150 break;
2151 default:
2152 target = 0;
2153 fprintf(stderr,
2154 "Warning: SI unhandled fs output type:%d\n",
2155 semantic_name);
2156 }
2157
2158 si_llvm_init_export_args_load(bld_base,
2159 si_shader_ctx->radeon_bld.soa.outputs[i],
2160 target, args);
2161
2162 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2163 /* If there is an export instruction waiting to be emitted, do so now. */
2164 if (last_args[0]) {
2165 lp_build_intrinsic(base->gallivm->builder,
2166 "llvm.SI.export",
2167 LLVMVoidTypeInContext(base->gallivm->context),
2168 last_args, 9, 0);
2169 }
2170
2171 /* This instruction will be emitted at the end of the shader. */
2172 memcpy(last_args, args, sizeof(args));
2173
2174 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2175 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2176 semantic_index == 0 &&
2177 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2178 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2179 si_llvm_init_export_args_load(bld_base,
2180 si_shader_ctx->radeon_bld.soa.outputs[i],
2181 V_008DFC_SQ_EXP_MRT + c, args);
2182 lp_build_intrinsic(base->gallivm->builder,
2183 "llvm.SI.export",
2184 LLVMVoidTypeInContext(base->gallivm->context),
2185 args, 9, 0);
2186 }
2187 }
2188 } else {
2189 lp_build_intrinsic(base->gallivm->builder,
2190 "llvm.SI.export",
2191 LLVMVoidTypeInContext(base->gallivm->context),
2192 args, 9, 0);
2193 }
2194 }
2195
2196 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2197 LLVMValueRef out_ptr;
2198 unsigned mask = 0;
2199
2200 /* Specify the target we are exporting */
2201 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2202
2203 args[5] = base->zero; /* R, depth */
2204 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2205 args[7] = base->zero; /* B, sample mask */
2206 args[8] = base->zero; /* A, alpha to mask */
2207
2208 if (depth_index >= 0) {
2209 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2210 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2211 mask |= 0x1;
2212 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2213 }
2214
2215 if (stencil_index >= 0) {
2216 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2217 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2218 mask |= 0x2;
2219 si_shader_ctx->shader->db_shader_control |=
2220 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2221 }
2222
2223 if (samplemask_index >= 0) {
2224 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2225 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2226 mask |= 0x4;
2227 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2228 }
2229
2230 /* SI (except OLAND) has a bug that it only looks
2231 * at the X writemask component. */
2232 if (si_shader_ctx->screen->b.chip_class == SI &&
2233 si_shader_ctx->screen->b.family != CHIP_OLAND)
2234 mask |= 0x1;
2235
2236 if (samplemask_index >= 0)
2237 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2238 else if (stencil_index >= 0)
2239 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2240 else
2241 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2242
2243 /* Specify which components to enable */
2244 args[0] = lp_build_const_int32(base->gallivm, mask);
2245
2246 args[1] =
2247 args[2] =
2248 args[4] = uint->zero;
2249
2250 if (last_args[0])
2251 lp_build_intrinsic(base->gallivm->builder,
2252 "llvm.SI.export",
2253 LLVMVoidTypeInContext(base->gallivm->context),
2254 args, 9, 0);
2255 else
2256 memcpy(last_args, args, sizeof(args));
2257 }
2258
2259 if (!last_args[0]) {
2260 /* Specify which components to enable */
2261 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2262
2263 /* Specify the target we are exporting */
2264 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2265
2266 /* Set COMPR flag to zero to export data as 32-bit */
2267 last_args[4] = uint->zero;
2268
2269 /* dummy bits */
2270 last_args[5]= uint->zero;
2271 last_args[6]= uint->zero;
2272 last_args[7]= uint->zero;
2273 last_args[8]= uint->zero;
2274 }
2275
2276 /* Specify whether the EXEC mask represents the valid mask */
2277 last_args[1] = uint->one;
2278
2279 /* Specify that this is the last export */
2280 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2281
2282 lp_build_intrinsic(base->gallivm->builder,
2283 "llvm.SI.export",
2284 LLVMVoidTypeInContext(base->gallivm->context),
2285 last_args, 9, 0);
2286 }
2287
2288 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2289 struct lp_build_tgsi_context * bld_base,
2290 struct lp_build_emit_data * emit_data);
2291
2292 static bool tgsi_is_array_sampler(unsigned target)
2293 {
2294 return target == TGSI_TEXTURE_1D_ARRAY ||
2295 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2296 target == TGSI_TEXTURE_2D_ARRAY ||
2297 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2298 target == TGSI_TEXTURE_CUBE_ARRAY ||
2299 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2300 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2301 }
2302
2303 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2304 struct lp_build_emit_data *emit_data,
2305 unsigned opcode, unsigned target,
2306 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2307 LLVMValueRef *param, unsigned count,
2308 unsigned dmask)
2309 {
2310 unsigned num_args;
2311 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2312 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2313
2314 /* Pad to power of two vector */
2315 while (count < util_next_power_of_two(count))
2316 param[count++] = LLVMGetUndef(i32);
2317
2318 /* Texture coordinates. */
2319 if (count > 1)
2320 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2321 else
2322 emit_data->args[0] = param[0];
2323
2324 /* Resource. */
2325 emit_data->args[1] = res_ptr;
2326 num_args = 2;
2327
2328 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2329 emit_data->dst_type = LLVMVectorType(i32, 4);
2330 else {
2331 emit_data->dst_type = LLVMVectorType(
2332 LLVMFloatTypeInContext(gallivm->context), 4);
2333
2334 emit_data->args[num_args++] = samp_ptr;
2335 }
2336
2337 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2338 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2339 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2340 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2341 tgsi_is_array_sampler(target)); /* da */
2342 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2343 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2344 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2345 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2346
2347 emit_data->arg_count = num_args;
2348 }
2349
2350 static const struct lp_build_tgsi_action tex_action;
2351
2352 static void tex_fetch_ptrs(
2353 struct lp_build_tgsi_context * bld_base,
2354 struct lp_build_emit_data * emit_data,
2355 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2356 {
2357 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2358 struct gallivm_state *gallivm = bld_base->base.gallivm;
2359 const struct tgsi_full_instruction * inst = emit_data->inst;
2360 unsigned target = inst->Texture.Texture;
2361 unsigned sampler_src;
2362 unsigned sampler_index;
2363
2364 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2365 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2366
2367 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2368 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2369 LLVMValueRef ind_index;
2370
2371 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2372
2373 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2374 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2375
2376 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2377 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2378
2379 if (target == TGSI_TEXTURE_2D_MSAA ||
2380 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2381 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2382 lp_build_const_int32(gallivm,
2383 SI_FMASK_TEX_OFFSET), "");
2384 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2385 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2386 }
2387 } else {
2388 *res_ptr = si_shader_ctx->resources[sampler_index];
2389 *samp_ptr = si_shader_ctx->samplers[sampler_index];
2390 *fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2391 }
2392 }
2393
2394 static void tex_fetch_args(
2395 struct lp_build_tgsi_context * bld_base,
2396 struct lp_build_emit_data * emit_data)
2397 {
2398 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2399 struct gallivm_state *gallivm = bld_base->base.gallivm;
2400 LLVMBuilderRef builder = gallivm->builder;
2401 const struct tgsi_full_instruction * inst = emit_data->inst;
2402 unsigned opcode = inst->Instruction.Opcode;
2403 unsigned target = inst->Texture.Texture;
2404 LLVMValueRef coords[5], derivs[6];
2405 LLVMValueRef address[16];
2406 int ref_pos;
2407 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2408 unsigned count = 0;
2409 unsigned chan;
2410 unsigned num_deriv_channels = 0;
2411 bool has_offset = inst->Texture.NumOffsets > 0;
2412 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2413 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2414 unsigned dmask = 0xf;
2415
2416 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2417
2418 if (opcode == TGSI_OPCODE_TXQ) {
2419 if (target == TGSI_TEXTURE_BUFFER) {
2420 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2421
2422 /* Read the size from the buffer descriptor directly. */
2423 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2424 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2425 lp_build_const_int32(gallivm, 6), "");
2426
2427 if (si_shader_ctx->screen->b.chip_class >= VI) {
2428 /* On VI, the descriptor contains the size in bytes,
2429 * but TXQ must return the size in elements.
2430 * The stride is always non-zero for resources using TXQ.
2431 */
2432 LLVMValueRef stride =
2433 LLVMBuildExtractElement(builder, res,
2434 lp_build_const_int32(gallivm, 5), "");
2435 stride = LLVMBuildLShr(builder, stride,
2436 lp_build_const_int32(gallivm, 16), "");
2437 stride = LLVMBuildAnd(builder, stride,
2438 lp_build_const_int32(gallivm, 0x3FFF), "");
2439
2440 size = LLVMBuildUDiv(builder, size, stride, "");
2441 }
2442
2443 emit_data->args[0] = size;
2444 return;
2445 }
2446
2447 /* Textures - set the mip level. */
2448 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2449
2450 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2451 NULL, address, count, 0xf);
2452 return;
2453 }
2454
2455 if (target == TGSI_TEXTURE_BUFFER) {
2456 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2457 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2458 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2459 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2460
2461 /* Bitcast and truncate v8i32 to v16i8. */
2462 LLVMValueRef res = res_ptr;
2463 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2464 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2465 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2466
2467 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2468 emit_data->args[0] = res;
2469 emit_data->args[1] = bld_base->uint_bld.zero;
2470 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2471 emit_data->arg_count = 3;
2472 return;
2473 }
2474
2475 /* Fetch and project texture coordinates */
2476 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2477 for (chan = 0; chan < 3; chan++ ) {
2478 coords[chan] = lp_build_emit_fetch(bld_base,
2479 emit_data->inst, 0,
2480 chan);
2481 if (opcode == TGSI_OPCODE_TXP)
2482 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2483 TGSI_OPCODE_DIV,
2484 coords[chan],
2485 coords[3]);
2486 }
2487
2488 if (opcode == TGSI_OPCODE_TXP)
2489 coords[3] = bld_base->base.one;
2490
2491 /* Pack offsets. */
2492 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2493 /* The offsets are six-bit signed integers packed like this:
2494 * X=[5:0], Y=[13:8], and Z=[21:16].
2495 */
2496 LLVMValueRef offset[3], pack;
2497
2498 assert(inst->Texture.NumOffsets == 1);
2499
2500 for (chan = 0; chan < 3; chan++) {
2501 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2502 emit_data->inst, 0, chan);
2503 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2504 lp_build_const_int32(gallivm, 0x3f), "");
2505 if (chan)
2506 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2507 lp_build_const_int32(gallivm, chan*8), "");
2508 }
2509
2510 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2511 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2512 address[count++] = pack;
2513 }
2514
2515 /* Pack LOD bias value */
2516 if (opcode == TGSI_OPCODE_TXB)
2517 address[count++] = coords[3];
2518 if (opcode == TGSI_OPCODE_TXB2)
2519 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2520
2521 /* Pack depth comparison value */
2522 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2523 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2524 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2525 } else {
2526 assert(ref_pos >= 0);
2527 address[count++] = coords[ref_pos];
2528 }
2529 }
2530
2531 /* Pack user derivatives */
2532 if (opcode == TGSI_OPCODE_TXD) {
2533 int param, num_src_deriv_channels;
2534
2535 switch (target) {
2536 case TGSI_TEXTURE_3D:
2537 num_src_deriv_channels = 3;
2538 num_deriv_channels = 3;
2539 break;
2540 case TGSI_TEXTURE_2D:
2541 case TGSI_TEXTURE_SHADOW2D:
2542 case TGSI_TEXTURE_RECT:
2543 case TGSI_TEXTURE_SHADOWRECT:
2544 case TGSI_TEXTURE_2D_ARRAY:
2545 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2546 num_src_deriv_channels = 2;
2547 num_deriv_channels = 2;
2548 break;
2549 case TGSI_TEXTURE_CUBE:
2550 case TGSI_TEXTURE_SHADOWCUBE:
2551 case TGSI_TEXTURE_CUBE_ARRAY:
2552 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2553 /* Cube derivatives will be converted to 2D. */
2554 num_src_deriv_channels = 3;
2555 num_deriv_channels = 2;
2556 break;
2557 case TGSI_TEXTURE_1D:
2558 case TGSI_TEXTURE_SHADOW1D:
2559 case TGSI_TEXTURE_1D_ARRAY:
2560 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2561 num_src_deriv_channels = 1;
2562 num_deriv_channels = 1;
2563 break;
2564 default:
2565 unreachable("invalid target");
2566 }
2567
2568 for (param = 0; param < 2; param++)
2569 for (chan = 0; chan < num_src_deriv_channels; chan++)
2570 derivs[param * num_src_deriv_channels + chan] =
2571 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2572 }
2573
2574 if (target == TGSI_TEXTURE_CUBE ||
2575 target == TGSI_TEXTURE_CUBE_ARRAY ||
2576 target == TGSI_TEXTURE_SHADOWCUBE ||
2577 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2578 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2579
2580 if (opcode == TGSI_OPCODE_TXD)
2581 for (int i = 0; i < num_deriv_channels * 2; i++)
2582 address[count++] = derivs[i];
2583
2584 /* Pack texture coordinates */
2585 address[count++] = coords[0];
2586 if (num_coords > 1)
2587 address[count++] = coords[1];
2588 if (num_coords > 2)
2589 address[count++] = coords[2];
2590
2591 /* Pack LOD or sample index */
2592 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2593 address[count++] = coords[3];
2594 else if (opcode == TGSI_OPCODE_TXL2)
2595 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2596
2597 if (count > 16) {
2598 assert(!"Cannot handle more than 16 texture address parameters");
2599 count = 16;
2600 }
2601
2602 for (chan = 0; chan < count; chan++ ) {
2603 address[chan] = LLVMBuildBitCast(gallivm->builder,
2604 address[chan], i32, "");
2605 }
2606
2607 /* Adjust the sample index according to FMASK.
2608 *
2609 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2610 * which is the identity mapping. Each nibble says which physical sample
2611 * should be fetched to get that sample.
2612 *
2613 * For example, 0x11111100 means there are only 2 samples stored and
2614 * the second sample covers 3/4 of the pixel. When reading samples 0
2615 * and 1, return physical sample 0 (determined by the first two 0s
2616 * in FMASK), otherwise return physical sample 1.
2617 *
2618 * The sample index should be adjusted as follows:
2619 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2620 */
2621 if (target == TGSI_TEXTURE_2D_MSAA ||
2622 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2623 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2624 struct lp_build_emit_data txf_emit_data = *emit_data;
2625 LLVMValueRef txf_address[4];
2626 unsigned txf_count = count;
2627 struct tgsi_full_instruction inst = {};
2628
2629 memcpy(txf_address, address, sizeof(txf_address));
2630
2631 if (target == TGSI_TEXTURE_2D_MSAA) {
2632 txf_address[2] = bld_base->uint_bld.zero;
2633 }
2634 txf_address[3] = bld_base->uint_bld.zero;
2635
2636 /* Read FMASK using TXF. */
2637 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2638 inst.Texture.Texture = target;
2639 txf_emit_data.inst = &inst;
2640 txf_emit_data.chan = 0;
2641 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2642 target, fmask_ptr, NULL,
2643 txf_address, txf_count, 0xf);
2644 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2645
2646 /* Initialize some constants. */
2647 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2648 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2649
2650 /* Apply the formula. */
2651 LLVMValueRef fmask =
2652 LLVMBuildExtractElement(gallivm->builder,
2653 txf_emit_data.output[0],
2654 uint_bld->zero, "");
2655
2656 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2657
2658 LLVMValueRef sample_index4 =
2659 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2660
2661 LLVMValueRef shifted_fmask =
2662 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2663
2664 LLVMValueRef final_sample =
2665 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2666
2667 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2668 * resource descriptor is 0 (invalid),
2669 */
2670 LLVMValueRef fmask_desc =
2671 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2672 LLVMVectorType(uint_bld->elem_type, 8), "");
2673
2674 LLVMValueRef fmask_word1 =
2675 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2676 uint_bld->one, "");
2677
2678 LLVMValueRef word1_is_nonzero =
2679 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2680 fmask_word1, uint_bld->zero, "");
2681
2682 /* Replace the MSAA sample index. */
2683 address[sample_chan] =
2684 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2685 final_sample, address[sample_chan], "");
2686 }
2687
2688 if (opcode == TGSI_OPCODE_TXF) {
2689 /* add tex offsets */
2690 if (inst->Texture.NumOffsets) {
2691 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2692 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2693 const struct tgsi_texture_offset * off = inst->TexOffsets;
2694
2695 assert(inst->Texture.NumOffsets == 1);
2696
2697 switch (target) {
2698 case TGSI_TEXTURE_3D:
2699 address[2] = lp_build_add(uint_bld, address[2],
2700 bld->immediates[off->Index][off->SwizzleZ]);
2701 /* fall through */
2702 case TGSI_TEXTURE_2D:
2703 case TGSI_TEXTURE_SHADOW2D:
2704 case TGSI_TEXTURE_RECT:
2705 case TGSI_TEXTURE_SHADOWRECT:
2706 case TGSI_TEXTURE_2D_ARRAY:
2707 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2708 address[1] =
2709 lp_build_add(uint_bld, address[1],
2710 bld->immediates[off->Index][off->SwizzleY]);
2711 /* fall through */
2712 case TGSI_TEXTURE_1D:
2713 case TGSI_TEXTURE_SHADOW1D:
2714 case TGSI_TEXTURE_1D_ARRAY:
2715 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2716 address[0] =
2717 lp_build_add(uint_bld, address[0],
2718 bld->immediates[off->Index][off->SwizzleX]);
2719 break;
2720 /* texture offsets do not apply to other texture targets */
2721 }
2722 }
2723 }
2724
2725 if (opcode == TGSI_OPCODE_TG4) {
2726 unsigned gather_comp = 0;
2727
2728 /* DMASK was repurposed for GATHER4. 4 components are always
2729 * returned and DMASK works like a swizzle - it selects
2730 * the component to fetch. The only valid DMASK values are
2731 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2732 * (red,red,red,red) etc.) The ISA document doesn't mention
2733 * this.
2734 */
2735
2736 /* Get the component index from src1.x for Gather4. */
2737 if (!tgsi_is_shadow_target(target)) {
2738 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2739 LLVMValueRef comp_imm;
2740 struct tgsi_src_register src1 = inst->Src[1].Register;
2741
2742 assert(src1.File == TGSI_FILE_IMMEDIATE);
2743
2744 comp_imm = imms[src1.Index][src1.SwizzleX];
2745 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2746 gather_comp = CLAMP(gather_comp, 0, 3);
2747 }
2748
2749 dmask = 1 << gather_comp;
2750 }
2751
2752 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2753 samp_ptr, address, count, dmask);
2754 }
2755
2756 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2757 struct lp_build_tgsi_context * bld_base,
2758 struct lp_build_emit_data * emit_data)
2759 {
2760 struct lp_build_context * base = &bld_base->base;
2761 unsigned opcode = emit_data->inst->Instruction.Opcode;
2762 unsigned target = emit_data->inst->Texture.Texture;
2763 char intr_name[127];
2764 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2765 bool is_shadow = tgsi_is_shadow_target(target);
2766 char type[64];
2767 const char *name = "llvm.SI.image.sample";
2768 const char *infix = "";
2769
2770 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2771 /* Just return the buffer size. */
2772 emit_data->output[emit_data->chan] = emit_data->args[0];
2773 return;
2774 }
2775
2776 if (target == TGSI_TEXTURE_BUFFER) {
2777 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2778 base->gallivm->builder,
2779 "llvm.SI.vs.load.input", emit_data->dst_type,
2780 emit_data->args, emit_data->arg_count,
2781 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2782 return;
2783 }
2784
2785 switch (opcode) {
2786 case TGSI_OPCODE_TXF:
2787 name = target == TGSI_TEXTURE_2D_MSAA ||
2788 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2789 "llvm.SI.image.load" :
2790 "llvm.SI.image.load.mip";
2791 is_shadow = false;
2792 has_offset = false;
2793 break;
2794 case TGSI_OPCODE_TXQ:
2795 name = "llvm.SI.getresinfo";
2796 is_shadow = false;
2797 has_offset = false;
2798 break;
2799 case TGSI_OPCODE_LODQ:
2800 name = "llvm.SI.getlod";
2801 is_shadow = false;
2802 has_offset = false;
2803 break;
2804 case TGSI_OPCODE_TEX:
2805 case TGSI_OPCODE_TEX2:
2806 case TGSI_OPCODE_TXP:
2807 break;
2808 case TGSI_OPCODE_TXB:
2809 case TGSI_OPCODE_TXB2:
2810 infix = ".b";
2811 break;
2812 case TGSI_OPCODE_TXL:
2813 case TGSI_OPCODE_TXL2:
2814 infix = ".l";
2815 break;
2816 case TGSI_OPCODE_TXD:
2817 infix = ".d";
2818 break;
2819 case TGSI_OPCODE_TG4:
2820 name = "llvm.SI.gather4";
2821 break;
2822 default:
2823 assert(0);
2824 return;
2825 }
2826
2827 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2828 sprintf(type, ".v%ui32",
2829 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2830 else
2831 strcpy(type, ".i32");
2832
2833 /* Add the type and suffixes .c, .o if needed. */
2834 sprintf(intr_name, "%s%s%s%s%s",
2835 name, is_shadow ? ".c" : "", infix,
2836 has_offset ? ".o" : "", type);
2837
2838 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2839 base->gallivm->builder, intr_name, emit_data->dst_type,
2840 emit_data->args, emit_data->arg_count,
2841 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2842
2843 /* Divide the number of layers by 6 to get the number of cubes. */
2844 if (opcode == TGSI_OPCODE_TXQ &&
2845 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2846 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2847 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2848 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2849 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2850
2851 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2852 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2853 z = LLVMBuildSDiv(builder, z, six, "");
2854
2855 emit_data->output[emit_data->chan] =
2856 LLVMBuildInsertElement(builder, v4, z, two, "");
2857 }
2858 }
2859
2860 static void si_llvm_emit_txqs(
2861 const struct lp_build_tgsi_action * action,
2862 struct lp_build_tgsi_context * bld_base,
2863 struct lp_build_emit_data * emit_data)
2864 {
2865 struct gallivm_state *gallivm = bld_base->base.gallivm;
2866 LLVMBuilderRef builder = gallivm->builder;
2867 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2868 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2869 LLVMValueRef res, samples;
2870 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2871
2872 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2873
2874
2875 /* Read the samples from the descriptor directly. */
2876 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2877 samples = LLVMBuildExtractElement(
2878 builder, res,
2879 lp_build_const_int32(gallivm, 3), "");
2880 samples = LLVMBuildLShr(builder, samples,
2881 lp_build_const_int32(gallivm, 16), "");
2882 samples = LLVMBuildAnd(builder, samples,
2883 lp_build_const_int32(gallivm, 0xf), "");
2884 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2885 samples, "");
2886
2887 emit_data->output[emit_data->chan] = samples;
2888 }
2889
2890 /*
2891 * SI implements derivatives using the local data store (LDS)
2892 * All writes to the LDS happen in all executing threads at
2893 * the same time. TID is the Thread ID for the current
2894 * thread and is a value between 0 and 63, representing
2895 * the thread's position in the wavefront.
2896 *
2897 * For the pixel shader threads are grouped into quads of four pixels.
2898 * The TIDs of the pixels of a quad are:
2899 *
2900 * +------+------+
2901 * |4n + 0|4n + 1|
2902 * +------+------+
2903 * |4n + 2|4n + 3|
2904 * +------+------+
2905 *
2906 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2907 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2908 * the current pixel's column, and masking with 0xfffffffe yields the TID
2909 * of the left pixel of the current pixel's row.
2910 *
2911 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2912 * adding 2 yields the TID of the pixel below the top pixel.
2913 */
2914 /* masks for thread ID. */
2915 #define TID_MASK_TOP_LEFT 0xfffffffc
2916 #define TID_MASK_TOP 0xfffffffd
2917 #define TID_MASK_LEFT 0xfffffffe
2918
2919 static void si_llvm_emit_ddxy(
2920 const struct lp_build_tgsi_action * action,
2921 struct lp_build_tgsi_context * bld_base,
2922 struct lp_build_emit_data * emit_data)
2923 {
2924 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2925 struct gallivm_state *gallivm = bld_base->base.gallivm;
2926 struct lp_build_context * base = &bld_base->base;
2927 const struct tgsi_full_instruction *inst = emit_data->inst;
2928 unsigned opcode = inst->Instruction.Opcode;
2929 LLVMValueRef indices[2];
2930 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2931 LLVMValueRef tl, trbl, result[4];
2932 LLVMTypeRef i32;
2933 unsigned swizzle[4];
2934 unsigned c;
2935 int idx;
2936 unsigned mask;
2937
2938 i32 = LLVMInt32TypeInContext(gallivm->context);
2939
2940 indices[0] = bld_base->uint_bld.zero;
2941 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2942 NULL, 0, LLVMReadNoneAttribute);
2943 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2944 indices, 2, "");
2945
2946 if (opcode == TGSI_OPCODE_DDX_FINE)
2947 mask = TID_MASK_LEFT;
2948 else if (opcode == TGSI_OPCODE_DDY_FINE)
2949 mask = TID_MASK_TOP;
2950 else
2951 mask = TID_MASK_TOP_LEFT;
2952
2953 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2954 lp_build_const_int32(gallivm, mask), "");
2955 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2956 indices, 2, "");
2957
2958 /* for DDX we want to next X pixel, DDY next Y pixel. */
2959 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2960 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2961 lp_build_const_int32(gallivm, idx), "");
2962 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2963 indices, 2, "");
2964
2965 for (c = 0; c < 4; ++c) {
2966 unsigned i;
2967
2968 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2969 for (i = 0; i < c; ++i) {
2970 if (swizzle[i] == swizzle[c]) {
2971 result[c] = result[i];
2972 break;
2973 }
2974 }
2975 if (i != c)
2976 continue;
2977
2978 LLVMBuildStore(gallivm->builder,
2979 LLVMBuildBitCast(gallivm->builder,
2980 lp_build_emit_fetch(bld_base, inst, 0, c),
2981 i32, ""),
2982 store_ptr);
2983
2984 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2985 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2986
2987 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2988 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2989
2990 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2991 }
2992
2993 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2994 }
2995
2996 /*
2997 * this takes an I,J coordinate pair,
2998 * and works out the X and Y derivatives.
2999 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3000 */
3001 static LLVMValueRef si_llvm_emit_ddxy_interp(
3002 struct lp_build_tgsi_context *bld_base,
3003 LLVMValueRef interp_ij)
3004 {
3005 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3006 struct gallivm_state *gallivm = bld_base->base.gallivm;
3007 struct lp_build_context *base = &bld_base->base;
3008 LLVMValueRef indices[2];
3009 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3010 LLVMValueRef tl, tr, bl, result[4];
3011 LLVMTypeRef i32;
3012 unsigned c;
3013
3014 i32 = LLVMInt32TypeInContext(gallivm->context);
3015
3016 indices[0] = bld_base->uint_bld.zero;
3017 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3018 NULL, 0, LLVMReadNoneAttribute);
3019 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3020 indices, 2, "");
3021
3022 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3023 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3024
3025 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3026 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3027
3028 indices[1] = temp;
3029 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3030 indices, 2, "");
3031
3032 indices[1] = temp2;
3033 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3034 indices, 2, "");
3035
3036 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3037 lp_build_const_int32(gallivm, 1), "");
3038 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3039 indices, 2, "");
3040
3041 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3042 lp_build_const_int32(gallivm, 2), "");
3043 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3044 indices, 2, "");
3045
3046 for (c = 0; c < 2; ++c) {
3047 LLVMValueRef store_val;
3048 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3049
3050 store_val = LLVMBuildExtractElement(gallivm->builder,
3051 interp_ij, c_ll, "");
3052 LLVMBuildStore(gallivm->builder,
3053 store_val,
3054 store_ptr);
3055
3056 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3057 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3058
3059 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3060 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3061
3062 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3063
3064 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3065 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3066
3067 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3068 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3069
3070 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3071 }
3072
3073 return lp_build_gather_values(gallivm, result, 4);
3074 }
3075
3076 static void interp_fetch_args(
3077 struct lp_build_tgsi_context *bld_base,
3078 struct lp_build_emit_data *emit_data)
3079 {
3080 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3081 struct gallivm_state *gallivm = bld_base->base.gallivm;
3082 const struct tgsi_full_instruction *inst = emit_data->inst;
3083
3084 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3085 /* offset is in second src, first two channels */
3086 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3087 emit_data->inst, 1,
3088 0);
3089 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3090 emit_data->inst, 1,
3091 1);
3092 emit_data->arg_count = 2;
3093 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3094 LLVMValueRef sample_position;
3095 LLVMValueRef sample_id;
3096 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3097
3098 /* fetch sample ID, then fetch its sample position,
3099 * and place into first two channels.
3100 */
3101 sample_id = lp_build_emit_fetch(bld_base,
3102 emit_data->inst, 1, 0);
3103 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3104 LLVMInt32TypeInContext(gallivm->context),
3105 "");
3106 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3107
3108 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3109 sample_position,
3110 lp_build_const_int32(gallivm, 0), "");
3111
3112 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3113 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3114 sample_position,
3115 lp_build_const_int32(gallivm, 1), "");
3116 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3117 emit_data->arg_count = 2;
3118 }
3119 }
3120
3121 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3122 struct lp_build_tgsi_context *bld_base,
3123 struct lp_build_emit_data *emit_data)
3124 {
3125 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3126 struct si_shader *shader = si_shader_ctx->shader;
3127 struct gallivm_state *gallivm = bld_base->base.gallivm;
3128 LLVMValueRef interp_param;
3129 const struct tgsi_full_instruction *inst = emit_data->inst;
3130 const char *intr_name;
3131 int input_index;
3132 int chan;
3133 int i;
3134 LLVMValueRef attr_number;
3135 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3136 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3137 int interp_param_idx;
3138 unsigned location;
3139
3140 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3141 input_index = inst->Src[0].Register.Index;
3142
3143 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3144 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3145 location = TGSI_INTERPOLATE_LOC_CENTER;
3146 else
3147 location = TGSI_INTERPOLATE_LOC_CENTROID;
3148
3149 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3150 location);
3151 if (interp_param_idx == -1)
3152 return;
3153 else if (interp_param_idx)
3154 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3155 else
3156 interp_param = NULL;
3157
3158 attr_number = lp_build_const_int32(gallivm,
3159 shader->ps_input_param_offset[input_index]);
3160
3161 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3162 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3163 LLVMValueRef ij_out[2];
3164 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3165
3166 /*
3167 * take the I then J parameters, and the DDX/Y for it, and
3168 * calculate the IJ inputs for the interpolator.
3169 * temp1 = ddx * offset/sample.x + I;
3170 * interp_param.I = ddy * offset/sample.y + temp1;
3171 * temp1 = ddx * offset/sample.x + J;
3172 * interp_param.J = ddy * offset/sample.y + temp1;
3173 */
3174 for (i = 0; i < 2; i++) {
3175 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3176 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3177 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3178 ddxy_out, ix_ll, "");
3179 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3180 ddxy_out, iy_ll, "");
3181 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3182 interp_param, ix_ll, "");
3183 LLVMValueRef temp1, temp2;
3184
3185 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3186 LLVMFloatTypeInContext(gallivm->context), "");
3187
3188 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3189
3190 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3191
3192 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3193
3194 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3195
3196 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3197 temp2,
3198 LLVMIntTypeInContext(gallivm->context, 32), "");
3199 }
3200 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3201 }
3202
3203 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3204 for (chan = 0; chan < 2; chan++) {
3205 LLVMValueRef args[4];
3206 LLVMValueRef llvm_chan;
3207 unsigned schan;
3208
3209 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3210 llvm_chan = lp_build_const_int32(gallivm, schan);
3211
3212 args[0] = llvm_chan;
3213 args[1] = attr_number;
3214 args[2] = params;
3215 args[3] = interp_param;
3216
3217 emit_data->output[chan] =
3218 lp_build_intrinsic(gallivm->builder, intr_name,
3219 input_type, args, args[3] ? 4 : 3,
3220 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3221 }
3222 }
3223
3224 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3225 struct lp_build_emit_data *emit_data)
3226 {
3227 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3228 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3229 unsigned stream;
3230
3231 assert(src0.File == TGSI_FILE_IMMEDIATE);
3232
3233 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3234 return stream;
3235 }
3236
3237 /* Emit one vertex from the geometry shader */
3238 static void si_llvm_emit_vertex(
3239 const struct lp_build_tgsi_action *action,
3240 struct lp_build_tgsi_context *bld_base,
3241 struct lp_build_emit_data *emit_data)
3242 {
3243 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3244 struct lp_build_context *uint = &bld_base->uint_bld;
3245 struct si_shader *shader = si_shader_ctx->shader;
3246 struct tgsi_shader_info *info = &shader->selector->info;
3247 struct gallivm_state *gallivm = bld_base->base.gallivm;
3248 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3249 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3250 SI_PARAM_GS2VS_OFFSET);
3251 LLVMValueRef gs_next_vertex;
3252 LLVMValueRef can_emit, kill;
3253 LLVMValueRef args[2];
3254 unsigned chan;
3255 int i;
3256 unsigned stream;
3257
3258 stream = si_llvm_get_stream(bld_base, emit_data);
3259
3260 /* Write vertex attribute values to GSVS ring */
3261 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3262 si_shader_ctx->gs_next_vertex[stream],
3263 "");
3264
3265 /* If this thread has already emitted the declared maximum number of
3266 * vertices, kill it: excessive vertex emissions are not supposed to
3267 * have any effect, and GS threads have no externally observable
3268 * effects other than emitting vertices.
3269 */
3270 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3271 lp_build_const_int32(gallivm,
3272 shader->selector->gs_max_out_vertices), "");
3273 kill = lp_build_select(&bld_base->base, can_emit,
3274 lp_build_const_float(gallivm, 1.0f),
3275 lp_build_const_float(gallivm, -1.0f));
3276
3277 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3278 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3279
3280 for (i = 0; i < info->num_outputs; i++) {
3281 LLVMValueRef *out_ptr =
3282 si_shader_ctx->radeon_bld.soa.outputs[i];
3283
3284 for (chan = 0; chan < 4; chan++) {
3285 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3286 LLVMValueRef voffset =
3287 lp_build_const_int32(gallivm, (i * 4 + chan) *
3288 shader->selector->gs_max_out_vertices);
3289
3290 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3291 voffset = lp_build_mul_imm(uint, voffset, 4);
3292
3293 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3294
3295 build_tbuffer_store(si_shader_ctx,
3296 si_shader_ctx->gsvs_ring[stream],
3297 out_val, 1,
3298 voffset, soffset, 0,
3299 V_008F0C_BUF_DATA_FORMAT_32,
3300 V_008F0C_BUF_NUM_FORMAT_UINT,
3301 1, 0, 1, 1, 0);
3302 }
3303 }
3304 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3305 lp_build_const_int32(gallivm, 1));
3306
3307 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3308
3309 /* Signal vertex emission */
3310 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3311 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3312 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3313 LLVMVoidTypeInContext(gallivm->context), args, 2,
3314 LLVMNoUnwindAttribute);
3315 }
3316
3317 /* Cut one primitive from the geometry shader */
3318 static void si_llvm_emit_primitive(
3319 const struct lp_build_tgsi_action *action,
3320 struct lp_build_tgsi_context *bld_base,
3321 struct lp_build_emit_data *emit_data)
3322 {
3323 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3324 struct gallivm_state *gallivm = bld_base->base.gallivm;
3325 LLVMValueRef args[2];
3326 unsigned stream;
3327
3328 /* Signal primitive cut */
3329 stream = si_llvm_get_stream(bld_base, emit_data);
3330 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3331 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3332 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3333 LLVMVoidTypeInContext(gallivm->context), args, 2,
3334 LLVMNoUnwindAttribute);
3335 }
3336
3337 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3338 struct lp_build_tgsi_context *bld_base,
3339 struct lp_build_emit_data *emit_data)
3340 {
3341 struct gallivm_state *gallivm = bld_base->base.gallivm;
3342
3343 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3344 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3345 LLVMNoUnwindAttribute);
3346 }
3347
3348 static const struct lp_build_tgsi_action tex_action = {
3349 .fetch_args = tex_fetch_args,
3350 .emit = build_tex_intrinsic,
3351 };
3352
3353 static const struct lp_build_tgsi_action interp_action = {
3354 .fetch_args = interp_fetch_args,
3355 .emit = build_interp_intrinsic,
3356 };
3357
3358 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3359 {
3360 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3361 LLVMValueRef args[3];
3362
3363 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3364 args[1] = 0;
3365 args[2] = lp_build_const_int32(gallivm, 1);
3366
3367 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3368 }
3369
3370 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3371 {
3372 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3373 CONST_ADDR_SPACE);
3374 }
3375
3376 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3377 struct pipe_stream_output_info *so,
3378 LLVMTypeRef *params, LLVMTypeRef i32,
3379 unsigned *num_params)
3380 {
3381 int i;
3382
3383 /* Streamout SGPRs. */
3384 if (so->num_outputs) {
3385 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3386 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3387 }
3388 /* A streamout buffer offset is loaded if the stride is non-zero. */
3389 for (i = 0; i < 4; i++) {
3390 if (!so->stride[i])
3391 continue;
3392
3393 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3394 }
3395 }
3396
3397 static void create_function(struct si_shader_context *si_shader_ctx)
3398 {
3399 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3400 struct gallivm_state *gallivm = bld_base->base.gallivm;
3401 struct si_shader *shader = si_shader_ctx->shader;
3402 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3403 unsigned i, last_array_pointer, last_sgpr, num_params;
3404
3405 i8 = LLVMInt8TypeInContext(gallivm->context);
3406 i32 = LLVMInt32TypeInContext(gallivm->context);
3407 f32 = LLVMFloatTypeInContext(gallivm->context);
3408 v2i32 = LLVMVectorType(i32, 2);
3409 v3i32 = LLVMVectorType(i32, 3);
3410 v4i32 = LLVMVectorType(i32, 4);
3411 v8i32 = LLVMVectorType(i32, 8);
3412 v16i8 = LLVMVectorType(i8, 16);
3413
3414 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3415 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3416 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3417 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3418 last_array_pointer = SI_PARAM_RESOURCE;
3419
3420 switch (si_shader_ctx->type) {
3421 case TGSI_PROCESSOR_VERTEX:
3422 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3423 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3424 params[SI_PARAM_BASE_VERTEX] = i32;
3425 params[SI_PARAM_START_INSTANCE] = i32;
3426 num_params = SI_PARAM_START_INSTANCE+1;
3427
3428 if (shader->key.vs.as_es) {
3429 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3430 } else if (shader->key.vs.as_ls) {
3431 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3432 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3433 } else {
3434 if (shader->is_gs_copy_shader) {
3435 last_array_pointer = SI_PARAM_CONST;
3436 num_params = SI_PARAM_CONST+1;
3437 } else {
3438 params[SI_PARAM_VS_STATE_BITS] = i32;
3439 num_params = SI_PARAM_VS_STATE_BITS+1;
3440 }
3441
3442 /* The locations of the other parameters are assigned dynamically. */
3443 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3444 params, i32, &num_params);
3445 }
3446
3447 last_sgpr = num_params-1;
3448
3449 /* VGPRs */
3450 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3451 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3452 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3453 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3454 break;
3455
3456 case TGSI_PROCESSOR_TESS_CTRL:
3457 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3458 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3459 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3460 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3461 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3462
3463 /* VGPRs */
3464 params[SI_PARAM_PATCH_ID] = i32;
3465 params[SI_PARAM_REL_IDS] = i32;
3466 num_params = SI_PARAM_REL_IDS+1;
3467 break;
3468
3469 case TGSI_PROCESSOR_TESS_EVAL:
3470 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3471 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3472 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3473
3474 if (shader->key.tes.as_es) {
3475 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3476 } else {
3477 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3478 params, i32, &num_params);
3479 }
3480 last_sgpr = num_params - 1;
3481
3482 /* VGPRs */
3483 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3484 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3485 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3486 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3487 break;
3488
3489 case TGSI_PROCESSOR_GEOMETRY:
3490 params[SI_PARAM_GS2VS_OFFSET] = i32;
3491 params[SI_PARAM_GS_WAVE_ID] = i32;
3492 last_sgpr = SI_PARAM_GS_WAVE_ID;
3493
3494 /* VGPRs */
3495 params[SI_PARAM_VTX0_OFFSET] = i32;
3496 params[SI_PARAM_VTX1_OFFSET] = i32;
3497 params[SI_PARAM_PRIMITIVE_ID] = i32;
3498 params[SI_PARAM_VTX2_OFFSET] = i32;
3499 params[SI_PARAM_VTX3_OFFSET] = i32;
3500 params[SI_PARAM_VTX4_OFFSET] = i32;
3501 params[SI_PARAM_VTX5_OFFSET] = i32;
3502 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3503 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3504 break;
3505
3506 case TGSI_PROCESSOR_FRAGMENT:
3507 params[SI_PARAM_ALPHA_REF] = f32;
3508 params[SI_PARAM_PS_STATE_BITS] = i32;
3509 params[SI_PARAM_PRIM_MASK] = i32;
3510 last_sgpr = SI_PARAM_PRIM_MASK;
3511 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3512 params[SI_PARAM_PERSP_CENTER] = v2i32;
3513 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3514 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3515 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3516 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3517 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3518 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3519 params[SI_PARAM_POS_X_FLOAT] = f32;
3520 params[SI_PARAM_POS_Y_FLOAT] = f32;
3521 params[SI_PARAM_POS_Z_FLOAT] = f32;
3522 params[SI_PARAM_POS_W_FLOAT] = f32;
3523 params[SI_PARAM_FRONT_FACE] = f32;
3524 params[SI_PARAM_ANCILLARY] = i32;
3525 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3526 params[SI_PARAM_POS_FIXED_PT] = f32;
3527 num_params = SI_PARAM_POS_FIXED_PT+1;
3528 break;
3529
3530 default:
3531 assert(0 && "unimplemented shader");
3532 return;
3533 }
3534
3535 assert(num_params <= Elements(params));
3536 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3537 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3538
3539 if (shader->dx10_clamp_mode)
3540 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3541 "enable-no-nans-fp-math", "true");
3542
3543 for (i = 0; i <= last_sgpr; ++i) {
3544 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3545
3546 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3547 * to move load. Inputs are constant so this is fine. */
3548 if (i <= last_array_pointer)
3549 LLVMAddAttribute(P, LLVMByValAttribute);
3550 else
3551 LLVMAddAttribute(P, LLVMInRegAttribute);
3552 }
3553
3554 if (bld_base->info &&
3555 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3556 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3557 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3558 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3559 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3560 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3561 si_shader_ctx->lds =
3562 LLVMAddGlobalInAddressSpace(gallivm->module,
3563 LLVMArrayType(i32, 64),
3564 "ddxy_lds",
3565 LOCAL_ADDR_SPACE);
3566
3567 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3568 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3569 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3570 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3571 unsigned vertex_data_dw_size = 32*32*4;
3572 unsigned patch_data_dw_size = 32*4;
3573 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3574 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3575 unsigned lds_dwords = patch_dw_size;
3576
3577 /* The actual size is computed outside of the shader to reduce
3578 * the number of shader variants. */
3579 si_shader_ctx->lds =
3580 LLVMAddGlobalInAddressSpace(gallivm->module,
3581 LLVMArrayType(i32, lds_dwords),
3582 "tess_lds",
3583 LOCAL_ADDR_SPACE);
3584 }
3585 }
3586
3587 static void preload_constants(struct si_shader_context *si_shader_ctx)
3588 {
3589 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3590 struct gallivm_state * gallivm = bld_base->base.gallivm;
3591 const struct tgsi_shader_info * info = bld_base->info;
3592 unsigned buf;
3593 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3594
3595 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3596 unsigned i, num_const = info->const_file_max[buf] + 1;
3597
3598 if (num_const == 0)
3599 continue;
3600
3601 /* Allocate space for the constant values */
3602 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3603
3604 /* Load the resource descriptor */
3605 si_shader_ctx->const_resource[buf] =
3606 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3607
3608 /* Load the constants, we rely on the code sinking to do the rest */
3609 for (i = 0; i < num_const * 4; ++i) {
3610 si_shader_ctx->constants[buf][i] =
3611 buffer_load_const(gallivm->builder,
3612 si_shader_ctx->const_resource[buf],
3613 lp_build_const_int32(gallivm, i * 4),
3614 bld_base->base.elem_type);
3615 }
3616 }
3617 }
3618
3619 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3620 {
3621 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3622 struct gallivm_state * gallivm = bld_base->base.gallivm;
3623 const struct tgsi_shader_info * info = bld_base->info;
3624
3625 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3626
3627 LLVMValueRef res_ptr, samp_ptr;
3628 LLVMValueRef offset;
3629
3630 if (num_samplers == 0)
3631 return;
3632
3633 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3634 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3635
3636 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3637 for (i = 0; i < num_samplers; ++i) {
3638 /* Resource */
3639 offset = lp_build_const_int32(gallivm, i);
3640 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3641
3642 /* Sampler */
3643 offset = lp_build_const_int32(gallivm, i);
3644 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3645
3646 /* FMASK resource */
3647 if (info->is_msaa_sampler[i]) {
3648 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3649 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3650 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3651 }
3652 }
3653 }
3654
3655 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3656 {
3657 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3658 struct gallivm_state * gallivm = bld_base->base.gallivm;
3659 unsigned i;
3660
3661 /* Streamout can only be used if the shader is compiled as VS. */
3662 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3663 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3664 (si_shader_ctx->shader->key.vs.as_es ||
3665 si_shader_ctx->shader->key.vs.as_ls)) ||
3666 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3667 si_shader_ctx->shader->key.tes.as_es))
3668 return;
3669
3670 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3671 SI_PARAM_RW_BUFFERS);
3672
3673 /* Load the resources, we rely on the code sinking to do the rest */
3674 for (i = 0; i < 4; ++i) {
3675 if (si_shader_ctx->shader->selector->so.stride[i]) {
3676 LLVMValueRef offset = lp_build_const_int32(gallivm,
3677 SI_SO_BUF_OFFSET + i);
3678
3679 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3680 }
3681 }
3682 }
3683
3684 /**
3685 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3686 * for later use.
3687 */
3688 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3689 {
3690 struct gallivm_state *gallivm =
3691 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3692
3693 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3694 SI_PARAM_RW_BUFFERS);
3695
3696 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3697 si_shader_ctx->shader->key.vs.as_es) ||
3698 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3699 si_shader_ctx->shader->key.tes.as_es) ||
3700 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3701 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3702
3703 si_shader_ctx->esgs_ring =
3704 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3705 }
3706
3707 if (si_shader_ctx->shader->is_gs_copy_shader) {
3708 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3709
3710 si_shader_ctx->gsvs_ring[0] =
3711 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3712 }
3713 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3714 int i;
3715 for (i = 0; i < 4; i++) {
3716 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3717
3718 si_shader_ctx->gsvs_ring[i] =
3719 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3720 }
3721 }
3722 }
3723
3724 void si_shader_binary_read_config(const struct si_screen *sscreen,
3725 struct si_shader *shader,
3726 unsigned symbol_offset)
3727 {
3728 unsigned i;
3729 const unsigned char *config =
3730 radeon_shader_binary_config_start(&shader->binary,
3731 symbol_offset);
3732
3733 /* XXX: We may be able to emit some of these values directly rather than
3734 * extracting fields to be emitted later.
3735 */
3736
3737 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3738 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3739 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3740 switch (reg) {
3741 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3742 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3743 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3744 case R_00B848_COMPUTE_PGM_RSRC1:
3745 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3746 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3747 shader->float_mode = G_00B028_FLOAT_MODE(value);
3748 break;
3749 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3750 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3751 break;
3752 case R_00B84C_COMPUTE_PGM_RSRC2:
3753 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3754 break;
3755 case R_0286CC_SPI_PS_INPUT_ENA:
3756 shader->spi_ps_input_ena = value;
3757 break;
3758 case R_0286E8_SPI_TMPRING_SIZE:
3759 case R_00B860_COMPUTE_TMPRING_SIZE:
3760 /* WAVESIZE is in units of 256 dwords. */
3761 shader->scratch_bytes_per_wave =
3762 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3763 break;
3764 default:
3765 fprintf(stderr, "Warning: Compiler emitted unknown "
3766 "config register: 0x%x\n", reg);
3767 break;
3768 }
3769 }
3770 }
3771
3772 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3773 struct si_shader *shader,
3774 uint64_t scratch_va)
3775 {
3776 unsigned i;
3777 uint32_t scratch_rsrc_dword0 = scratch_va;
3778 uint32_t scratch_rsrc_dword1 =
3779 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3780 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3781
3782 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3783 const struct radeon_shader_reloc *reloc =
3784 &shader->binary.relocs[i];
3785 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3786 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3787 &scratch_rsrc_dword0, 4);
3788 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3789 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3790 &scratch_rsrc_dword1, 4);
3791 }
3792 }
3793 }
3794
3795 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3796 {
3797 const struct radeon_shader_binary *binary = &shader->binary;
3798 unsigned code_size = binary->code_size + binary->rodata_size;
3799 unsigned char *ptr;
3800
3801 r600_resource_reference(&shader->bo, NULL);
3802 shader->bo = si_resource_create_custom(&sscreen->b.b,
3803 PIPE_USAGE_IMMUTABLE,
3804 code_size);
3805 if (!shader->bo)
3806 return -ENOMEM;
3807
3808 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3809 PIPE_TRANSFER_READ_WRITE);
3810 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3811 if (binary->rodata_size > 0) {
3812 ptr += binary->code_size;
3813 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3814 binary->rodata_size);
3815 }
3816
3817 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3818 return 0;
3819 }
3820
3821 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3822 {
3823 const struct radeon_shader_binary *binary = &shader->binary;
3824 unsigned i;
3825 int r;
3826 bool dump = r600_can_dump_shader(&sscreen->b,
3827 shader->selector ? shader->selector->tokens : NULL);
3828
3829 si_shader_binary_read_config(sscreen, shader, 0);
3830 r = si_shader_binary_upload(sscreen, shader);
3831 if (r)
3832 return r;
3833
3834 if (dump) {
3835 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3836 if (binary->disasm_string) {
3837 fprintf(stderr, "\nShader Disassembly:\n\n");
3838 fprintf(stderr, "%s\n", binary->disasm_string);
3839 } else {
3840 fprintf(stderr, "SI CODE:\n");
3841 for (i = 0; i < binary->code_size; i+=4 ) {
3842 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3843 binary->code[i + 2], binary->code[i + 1],
3844 binary->code[i]);
3845 }
3846 }
3847 }
3848
3849 fprintf(stderr, "*** SHADER STATS ***\n"
3850 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3851 "Scratch: %d bytes per wave\n********************\n",
3852 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3853 shader->lds_size, shader->scratch_bytes_per_wave);
3854 }
3855 return 0;
3856 }
3857
3858 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3859 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3860 {
3861 int r = 0;
3862 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3863 shader->selector ? shader->selector->tokens : NULL);
3864 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3865
3866 r = radeon_llvm_compile(mod, &shader->binary,
3867 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3868 if (r)
3869 return r;
3870
3871 r = si_shader_binary_read(sscreen, shader);
3872
3873 FREE(shader->binary.config);
3874 FREE(shader->binary.rodata);
3875 FREE(shader->binary.global_symbol_offsets);
3876 if (shader->scratch_bytes_per_wave == 0) {
3877 FREE(shader->binary.code);
3878 FREE(shader->binary.relocs);
3879 memset(&shader->binary, 0,
3880 offsetof(struct radeon_shader_binary, disasm_string));
3881 }
3882 return r;
3883 }
3884
3885 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3886 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3887 struct si_shader_context *si_shader_ctx,
3888 struct si_shader *gs, bool dump)
3889 {
3890 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3891 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3892 struct lp_build_context *base = &bld_base->base;
3893 struct lp_build_context *uint = &bld_base->uint_bld;
3894 struct si_shader *shader = si_shader_ctx->shader;
3895 struct si_shader_output_values *outputs;
3896 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3897 LLVMValueRef args[9];
3898 int i, r;
3899
3900 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3901
3902 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3903 shader->is_gs_copy_shader = true;
3904
3905 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3906
3907 create_meta_data(si_shader_ctx);
3908 create_function(si_shader_ctx);
3909 preload_streamout_buffers(si_shader_ctx);
3910 preload_ring_buffers(si_shader_ctx);
3911
3912 args[0] = si_shader_ctx->gsvs_ring[0];
3913 args[1] = lp_build_mul_imm(uint,
3914 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3915 si_shader_ctx->param_vertex_id),
3916 4);
3917 args[3] = uint->zero;
3918 args[4] = uint->one; /* OFFEN */
3919 args[5] = uint->zero; /* IDXEN */
3920 args[6] = uint->one; /* GLC */
3921 args[7] = uint->one; /* SLC */
3922 args[8] = uint->zero; /* TFE */
3923
3924 /* Fetch vertex data from GSVS ring */
3925 for (i = 0; i < gsinfo->num_outputs; ++i) {
3926 unsigned chan;
3927
3928 outputs[i].name = gsinfo->output_semantic_name[i];
3929 outputs[i].sid = gsinfo->output_semantic_index[i];
3930
3931 for (chan = 0; chan < 4; chan++) {
3932 args[2] = lp_build_const_int32(gallivm,
3933 (i * 4 + chan) *
3934 gs->selector->gs_max_out_vertices * 16 * 4);
3935
3936 outputs[i].values[chan] =
3937 LLVMBuildBitCast(gallivm->builder,
3938 lp_build_intrinsic(gallivm->builder,
3939 "llvm.SI.buffer.load.dword.i32.i32",
3940 LLVMInt32TypeInContext(gallivm->context),
3941 args, 9,
3942 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3943 base->elem_type, "");
3944 }
3945 }
3946
3947 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3948
3949 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3950
3951 if (dump)
3952 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3953
3954 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3955 si_shader_ctx->tm, bld_base->base.gallivm->module);
3956
3957 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3958
3959 FREE(outputs);
3960 return r;
3961 }
3962
3963 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
3964 {
3965 int i;
3966
3967 fprintf(f, "SHADER KEY\n");
3968
3969 switch (shader) {
3970 case PIPE_SHADER_VERTEX:
3971 fprintf(f, " instance_divisors = {");
3972 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
3973 fprintf(f, !i ? "%u" : ", %u",
3974 key->vs.instance_divisors[i]);
3975 fprintf(f, "}\n");
3976 fprintf(f, " as_es = %u\n", key->vs.as_es);
3977 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
3978 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
3979 break;
3980
3981 case PIPE_SHADER_TESS_CTRL:
3982 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
3983 break;
3984
3985 case PIPE_SHADER_TESS_EVAL:
3986 fprintf(f, " as_es = %u\n", key->tes.as_es);
3987 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
3988 break;
3989
3990 case PIPE_SHADER_GEOMETRY:
3991 break;
3992
3993 case PIPE_SHADER_FRAGMENT:
3994 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
3995 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
3996 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
3997 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
3998 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
3999 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4000 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4001 break;
4002
4003 default:
4004 assert(0);
4005 }
4006 }
4007
4008 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4009 struct si_shader *shader)
4010 {
4011 struct si_shader_selector *sel = shader->selector;
4012 struct tgsi_token *tokens = sel->tokens;
4013 struct si_shader_context si_shader_ctx;
4014 struct lp_build_tgsi_context * bld_base;
4015 struct tgsi_shader_info stipple_shader_info;
4016 LLVMModuleRef mod;
4017 int r = 0;
4018 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4019 shader->key.ps.poly_stipple;
4020 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
4021
4022 if (poly_stipple) {
4023 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4024 SI_POLY_STIPPLE_SAMPLER);
4025 tgsi_scan_shader(tokens, &stipple_shader_info);
4026 }
4027
4028 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4029 * conversion fails. */
4030 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4031 si_dump_shader_key(sel->type, &shader->key, stderr);
4032 tgsi_dump(tokens, 0);
4033 si_dump_streamout(&sel->so);
4034 }
4035
4036 assert(shader->nparam == 0);
4037
4038 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4039 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4040 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4041
4042 if (sel->type != PIPE_SHADER_COMPUTE)
4043 shader->dx10_clamp_mode = true;
4044
4045 if (sel->info.uses_kill)
4046 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4047
4048 shader->uses_instanceid = sel->info.uses_instanceid;
4049 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4050 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4051
4052 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4053 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4054 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4055
4056 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4057 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4058 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4059 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4060 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4061 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4062 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4063 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4064 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4065 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4066 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4067 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4068 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4069
4070 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4071 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4072 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4073 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4074
4075 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4076 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4077 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4078
4079 if (HAVE_LLVM >= 0x0306) {
4080 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4081 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4082 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4083 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4084 }
4085
4086 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4087 si_shader_ctx.shader = shader;
4088 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4089 si_shader_ctx.screen = sscreen;
4090 si_shader_ctx.tm = tm;
4091
4092 switch (si_shader_ctx.type) {
4093 case TGSI_PROCESSOR_VERTEX:
4094 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4095 if (shader->key.vs.as_ls)
4096 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4097 else if (shader->key.vs.as_es)
4098 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4099 else
4100 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4101 break;
4102 case TGSI_PROCESSOR_TESS_CTRL:
4103 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4104 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4105 bld_base->emit_store = store_output_tcs;
4106 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4107 break;
4108 case TGSI_PROCESSOR_TESS_EVAL:
4109 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4110 if (shader->key.tes.as_es)
4111 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4112 else
4113 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4114 break;
4115 case TGSI_PROCESSOR_GEOMETRY:
4116 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4117 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4118 break;
4119 case TGSI_PROCESSOR_FRAGMENT:
4120 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4121 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4122
4123 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4124 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4125 shader->db_shader_control |=
4126 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4127 break;
4128 case TGSI_FS_DEPTH_LAYOUT_LESS:
4129 shader->db_shader_control |=
4130 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4131 break;
4132 }
4133 break;
4134 default:
4135 assert(!"Unsupported shader type");
4136 return -1;
4137 }
4138
4139 create_meta_data(&si_shader_ctx);
4140 create_function(&si_shader_ctx);
4141 preload_constants(&si_shader_ctx);
4142 preload_samplers(&si_shader_ctx);
4143 preload_streamout_buffers(&si_shader_ctx);
4144 preload_ring_buffers(&si_shader_ctx);
4145
4146 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4147 int i;
4148 for (i = 0; i < 4; i++) {
4149 si_shader_ctx.gs_next_vertex[i] =
4150 lp_build_alloca(bld_base->base.gallivm,
4151 bld_base->uint_bld.elem_type, "");
4152 }
4153 }
4154
4155 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4156 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4157 goto out;
4158 }
4159
4160 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4161
4162 mod = bld_base->base.gallivm->module;
4163 r = si_compile_llvm(sscreen, shader, tm, mod);
4164 if (r) {
4165 fprintf(stderr, "LLVM failed to compile shader\n");
4166 goto out;
4167 }
4168
4169 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4170
4171 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4172 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4173 shader->gs_copy_shader->selector = shader->selector;
4174 shader->gs_copy_shader->key = shader->key;
4175 si_shader_ctx.shader = shader->gs_copy_shader;
4176 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4177 shader, dump))) {
4178 free(shader->gs_copy_shader);
4179 shader->gs_copy_shader = NULL;
4180 goto out;
4181 }
4182 }
4183
4184 out:
4185 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4186 FREE(si_shader_ctx.constants[i]);
4187 if (poly_stipple)
4188 tgsi_free_tokens(tokens);
4189 return r;
4190 }
4191
4192 void si_shader_destroy(struct si_shader *shader)
4193 {
4194 if (shader->gs_copy_shader) {
4195 si_shader_destroy(shader->gs_copy_shader);
4196 FREE(shader->gs_copy_shader);
4197 }
4198
4199 if (shader->scratch_bo)
4200 r600_resource_reference(&shader->scratch_bo, NULL);
4201
4202 r600_resource_reference(&shader->bo, NULL);
4203
4204 FREE(shader->binary.code);
4205 FREE(shader->binary.relocs);
4206 FREE(shader->binary.disasm_string);
4207 }