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radeonsi: skip ES output stores for undefined output components
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "gallivm/lp_bld_const.h"
26 #include "gallivm/lp_bld_gather.h"
27 #include "gallivm/lp_bld_intr.h"
28 #include "gallivm/lp_bld_logic.h"
29 #include "gallivm/lp_bld_arit.h"
30 #include "gallivm/lp_bld_flow.h"
31 #include "gallivm/lp_bld_misc.h"
32 #include "util/u_memory.h"
33 #include "util/u_string.h"
34 #include "tgsi/tgsi_build.h"
35 #include "tgsi/tgsi_util.h"
36 #include "tgsi/tgsi_dump.h"
37
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_exp_param.h"
41 #include "ac_shader_util.h"
42 #include "si_shader_internal.h"
43 #include "si_pipe.h"
44 #include "sid.h"
45
46 #include "compiler/nir/nir.h"
47
48 static const char *scratch_rsrc_dword0_symbol =
49 "SCRATCH_RSRC_DWORD0";
50
51 static const char *scratch_rsrc_dword1_symbol =
52 "SCRATCH_RSRC_DWORD1";
53
54 struct si_shader_output_values
55 {
56 LLVMValueRef values[4];
57 unsigned semantic_name;
58 unsigned semantic_index;
59 ubyte vertex_stream[4];
60 };
61
62 /**
63 * Used to collect types and other info about arguments of the LLVM function
64 * before the function is created.
65 */
66 struct si_function_info {
67 LLVMTypeRef types[100];
68 LLVMValueRef *assign[100];
69 unsigned num_sgpr_params;
70 unsigned num_params;
71 };
72
73 enum si_arg_regfile {
74 ARG_SGPR,
75 ARG_VGPR
76 };
77
78 static void si_init_shader_ctx(struct si_shader_context *ctx,
79 struct si_screen *sscreen,
80 struct si_compiler *compiler);
81
82 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
83 struct lp_build_tgsi_context *bld_base,
84 struct lp_build_emit_data *emit_data);
85
86 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
87 FILE *f);
88
89 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
90 union si_shader_part_key *key);
91 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
92 union si_shader_part_key *key);
93 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
94 union si_shader_part_key *key);
95 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
96 union si_shader_part_key *key);
97
98 /* Ideally pass the sample mask input to the PS epilog as v14, which
99 * is its usual location, so that the shader doesn't have to add v_mov.
100 */
101 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
102
103 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
104 LLVMTypeRef type)
105 {
106 if (type == ctx->ac.i64 || type == ctx->ac.f64)
107 return true;
108
109 return false;
110 }
111
112 static bool is_merged_shader(struct si_shader *shader)
113 {
114 if (shader->selector->screen->info.chip_class <= VI)
115 return false;
116
117 return shader->key.as_ls ||
118 shader->key.as_es ||
119 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
120 shader->selector->type == PIPE_SHADER_GEOMETRY;
121 }
122
123 static void si_init_function_info(struct si_function_info *fninfo)
124 {
125 fninfo->num_params = 0;
126 fninfo->num_sgpr_params = 0;
127 }
128
129 static unsigned add_arg_assign(struct si_function_info *fninfo,
130 enum si_arg_regfile regfile, LLVMTypeRef type,
131 LLVMValueRef *assign)
132 {
133 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
134
135 unsigned idx = fninfo->num_params++;
136 assert(idx < ARRAY_SIZE(fninfo->types));
137
138 if (regfile == ARG_SGPR)
139 fninfo->num_sgpr_params = fninfo->num_params;
140
141 fninfo->types[idx] = type;
142 fninfo->assign[idx] = assign;
143 return idx;
144 }
145
146 static unsigned add_arg(struct si_function_info *fninfo,
147 enum si_arg_regfile regfile, LLVMTypeRef type)
148 {
149 return add_arg_assign(fninfo, regfile, type, NULL);
150 }
151
152 static void add_arg_assign_checked(struct si_function_info *fninfo,
153 enum si_arg_regfile regfile, LLVMTypeRef type,
154 LLVMValueRef *assign, unsigned idx)
155 {
156 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
157 assert(actual == idx);
158 }
159
160 static void add_arg_checked(struct si_function_info *fninfo,
161 enum si_arg_regfile regfile, LLVMTypeRef type,
162 unsigned idx)
163 {
164 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
165 }
166
167 /**
168 * Returns a unique index for a per-patch semantic name and index. The index
169 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
170 * can be calculated.
171 */
172 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
173 {
174 switch (semantic_name) {
175 case TGSI_SEMANTIC_TESSOUTER:
176 return 0;
177 case TGSI_SEMANTIC_TESSINNER:
178 return 1;
179 case TGSI_SEMANTIC_PATCH:
180 assert(index < 30);
181 return 2 + index;
182
183 default:
184 assert(!"invalid semantic name");
185 return 0;
186 }
187 }
188
189 /**
190 * Returns a unique index for a semantic name and index. The index must be
191 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
192 * calculated.
193 */
194 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
195 {
196 switch (semantic_name) {
197 case TGSI_SEMANTIC_POSITION:
198 return 0;
199 case TGSI_SEMANTIC_GENERIC:
200 /* Since some shader stages use the the highest used IO index
201 * to determine the size to allocate for inputs/outputs
202 * (in LDS, tess and GS rings). GENERIC should be placed right
203 * after POSITION to make that size as small as possible.
204 */
205 if (index < SI_MAX_IO_GENERIC)
206 return 1 + index;
207
208 assert(!"invalid generic index");
209 return 0;
210 case TGSI_SEMANTIC_PSIZE:
211 return SI_MAX_IO_GENERIC + 1;
212 case TGSI_SEMANTIC_CLIPDIST:
213 assert(index <= 1);
214 return SI_MAX_IO_GENERIC + 2 + index;
215 case TGSI_SEMANTIC_FOG:
216 return SI_MAX_IO_GENERIC + 4;
217 case TGSI_SEMANTIC_LAYER:
218 return SI_MAX_IO_GENERIC + 5;
219 case TGSI_SEMANTIC_VIEWPORT_INDEX:
220 return SI_MAX_IO_GENERIC + 6;
221 case TGSI_SEMANTIC_PRIMID:
222 return SI_MAX_IO_GENERIC + 7;
223 case TGSI_SEMANTIC_COLOR: /* these alias */
224 case TGSI_SEMANTIC_BCOLOR:
225 assert(index < 2);
226 return SI_MAX_IO_GENERIC + 8 + index;
227 case TGSI_SEMANTIC_TEXCOORD:
228 assert(index < 8);
229 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
230 return SI_MAX_IO_GENERIC + 10 + index;
231 default:
232 assert(!"invalid semantic name");
233 return 0;
234 }
235 }
236
237 /**
238 * Get the value of a shader input parameter and extract a bitfield.
239 */
240 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
241 LLVMValueRef value, unsigned rshift,
242 unsigned bitwidth)
243 {
244 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
245 value = ac_to_integer(&ctx->ac, value);
246
247 if (rshift)
248 value = LLVMBuildLShr(ctx->ac.builder, value,
249 LLVMConstInt(ctx->i32, rshift, 0), "");
250
251 if (rshift + bitwidth < 32) {
252 unsigned mask = (1 << bitwidth) - 1;
253 value = LLVMBuildAnd(ctx->ac.builder, value,
254 LLVMConstInt(ctx->i32, mask, 0), "");
255 }
256
257 return value;
258 }
259
260 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
261 unsigned param, unsigned rshift,
262 unsigned bitwidth)
263 {
264 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
265
266 return unpack_llvm_param(ctx, value, rshift, bitwidth);
267 }
268
269 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
270 {
271 switch (ctx->type) {
272 case PIPE_SHADER_TESS_CTRL:
273 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
274
275 case PIPE_SHADER_TESS_EVAL:
276 return LLVMGetParam(ctx->main_fn,
277 ctx->param_tes_rel_patch_id);
278
279 default:
280 assert(0);
281 return NULL;
282 }
283 }
284
285 /* Tessellation shaders pass outputs to the next shader using LDS.
286 *
287 * LS outputs = TCS inputs
288 * TCS outputs = TES inputs
289 *
290 * The LDS layout is:
291 * - TCS inputs for patch 0
292 * - TCS inputs for patch 1
293 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
294 * - ...
295 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
296 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
297 * - TCS outputs for patch 1
298 * - Per-patch TCS outputs for patch 1
299 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
300 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
301 * - ...
302 *
303 * All three shaders VS(LS), TCS, TES share the same LDS space.
304 */
305
306 static LLVMValueRef
307 get_tcs_in_patch_stride(struct si_shader_context *ctx)
308 {
309 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
310 }
311
312 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
313 {
314 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
315
316 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
317 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
318
319 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
320 }
321
322 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
323 {
324 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
325
326 return LLVMConstInt(ctx->i32, stride, 0);
327 }
328
329 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
330 {
331 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
332 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
333
334 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
335 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
336 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
337 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
338 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
339 num_patch_outputs * 4;
340 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
341 }
342
343 static LLVMValueRef
344 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
345 {
346 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
347 si_unpack_param(ctx,
348 ctx->param_tcs_out_lds_offsets,
349 0, 16),
350 4);
351 }
352
353 static LLVMValueRef
354 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
355 {
356 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
357 si_unpack_param(ctx,
358 ctx->param_tcs_out_lds_offsets,
359 16, 16),
360 4);
361 }
362
363 static LLVMValueRef
364 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
365 {
366 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
367 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
368
369 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
370 }
371
372 static LLVMValueRef
373 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
374 {
375 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
376 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
377 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
378
379 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
380 LLVMBuildMul(ctx->ac.builder, patch_stride,
381 rel_patch_id, ""),
382 "");
383 }
384
385 static LLVMValueRef
386 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
387 {
388 LLVMValueRef patch0_patch_data_offset =
389 get_tcs_out_patch0_patch_data_offset(ctx);
390 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
391 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
392
393 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
394 LLVMBuildMul(ctx->ac.builder, patch_stride,
395 rel_patch_id, ""),
396 "");
397 }
398
399 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
400 {
401 unsigned tcs_out_vertices =
402 ctx->shader->selector ?
403 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
404
405 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
406 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
407 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
408
409 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
410 }
411
412 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
413 {
414 unsigned stride;
415
416 switch (ctx->type) {
417 case PIPE_SHADER_VERTEX:
418 stride = util_last_bit64(ctx->shader->selector->outputs_written);
419 return LLVMConstInt(ctx->i32, stride * 4, 0);
420
421 case PIPE_SHADER_TESS_CTRL:
422 if (ctx->screen->info.chip_class >= GFX9 &&
423 ctx->shader->is_monolithic) {
424 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
425 return LLVMConstInt(ctx->i32, stride * 4, 0);
426 }
427 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
428
429 default:
430 assert(0);
431 return NULL;
432 }
433 }
434
435 static LLVMValueRef get_instance_index_for_fetch(
436 struct si_shader_context *ctx,
437 unsigned param_start_instance, LLVMValueRef divisor)
438 {
439 LLVMValueRef result = ctx->abi.instance_id;
440
441 /* The division must be done before START_INSTANCE is added. */
442 if (divisor != ctx->i32_1)
443 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
444
445 return LLVMBuildAdd(ctx->ac.builder, result,
446 LLVMGetParam(ctx->main_fn, param_start_instance), "");
447 }
448
449 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
450 * to float. */
451 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
452 LLVMValueRef vec4,
453 unsigned double_index)
454 {
455 LLVMBuilderRef builder = ctx->ac.builder;
456 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
457 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
458 LLVMVectorType(f64, 2), "");
459 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
460 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
461 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
462 }
463
464 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
465 LLVMValueRef i32, unsigned index)
466 {
467 assert(index <= 1);
468
469 if (index == 1)
470 return LLVMBuildAShr(ctx->ac.builder, i32,
471 LLVMConstInt(ctx->i32, 16, 0), "");
472
473 return LLVMBuildSExt(ctx->ac.builder,
474 LLVMBuildTrunc(ctx->ac.builder, i32,
475 ctx->ac.i16, ""),
476 ctx->i32, "");
477 }
478
479 void si_llvm_load_input_vs(
480 struct si_shader_context *ctx,
481 unsigned input_index,
482 LLVMValueRef out[4])
483 {
484 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
485 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
486
487 if (vs_blit_property) {
488 LLVMValueRef vertex_id = ctx->abi.vertex_id;
489 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
490 LLVMIntULE, vertex_id,
491 ctx->i32_1, "");
492 /* Use LLVMIntNE, because we have 3 vertices and only
493 * the middle one should use y2.
494 */
495 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
496 LLVMIntNE, vertex_id,
497 ctx->i32_1, "");
498
499 if (input_index == 0) {
500 /* Position: */
501 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs);
503 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
504 ctx->param_vs_blit_inputs + 1);
505
506 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
507 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
508 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
509 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
510
511 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
512 x1, x2, "");
513 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
514 y1, y2, "");
515
516 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
517 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
518 out[2] = LLVMGetParam(ctx->main_fn,
519 ctx->param_vs_blit_inputs + 2);
520 out[3] = ctx->ac.f32_1;
521 return;
522 }
523
524 /* Color or texture coordinates: */
525 assert(input_index == 1);
526
527 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
528 for (int i = 0; i < 4; i++) {
529 out[i] = LLVMGetParam(ctx->main_fn,
530 ctx->param_vs_blit_inputs + 3 + i);
531 }
532 } else {
533 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
534 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
535 ctx->param_vs_blit_inputs + 3);
536 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
537 ctx->param_vs_blit_inputs + 4);
538 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
539 ctx->param_vs_blit_inputs + 5);
540 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
541 ctx->param_vs_blit_inputs + 6);
542
543 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
544 x1, x2, "");
545 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
546 y1, y2, "");
547 out[2] = LLVMGetParam(ctx->main_fn,
548 ctx->param_vs_blit_inputs + 7);
549 out[3] = LLVMGetParam(ctx->main_fn,
550 ctx->param_vs_blit_inputs + 8);
551 }
552 return;
553 }
554
555 unsigned chan;
556 unsigned fix_fetch;
557 unsigned num_fetches;
558 unsigned fetch_stride;
559 unsigned num_channels;
560
561 LLVMValueRef t_list_ptr;
562 LLVMValueRef t_offset;
563 LLVMValueRef t_list;
564 LLVMValueRef vertex_index;
565 LLVMValueRef input[3];
566
567 /* Load the T list */
568 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
569
570 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
571
572 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
573
574 vertex_index = LLVMGetParam(ctx->main_fn,
575 ctx->param_vertex_index0 +
576 input_index);
577
578 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
579
580 /* Do multiple loads for special formats. */
581 switch (fix_fetch) {
582 case SI_FIX_FETCH_RGB_64_FLOAT:
583 num_fetches = 3; /* 3 2-dword loads */
584 fetch_stride = 8;
585 num_channels = 2;
586 break;
587 case SI_FIX_FETCH_RGBA_64_FLOAT:
588 num_fetches = 2; /* 2 4-dword loads */
589 fetch_stride = 16;
590 num_channels = 4;
591 break;
592 case SI_FIX_FETCH_RGB_8:
593 case SI_FIX_FETCH_RGB_8_INT:
594 num_fetches = 3;
595 fetch_stride = 1;
596 num_channels = 1;
597 break;
598 case SI_FIX_FETCH_RGB_16:
599 case SI_FIX_FETCH_RGB_16_INT:
600 num_fetches = 3;
601 fetch_stride = 2;
602 num_channels = 1;
603 break;
604 default:
605 num_fetches = 1;
606 fetch_stride = 0;
607 num_channels = util_last_bit(info->input_usage_mask[input_index]);
608 }
609
610 for (unsigned i = 0; i < num_fetches; i++) {
611 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
612
613 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
614 vertex_index, voffset,
615 num_channels, false, true);
616 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
617 }
618
619 /* Break up the vec4 into individual components */
620 for (chan = 0; chan < 4; chan++) {
621 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
622 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
623 input[0], llvm_chan, "");
624 }
625
626 switch (fix_fetch) {
627 case SI_FIX_FETCH_A2_SNORM:
628 case SI_FIX_FETCH_A2_SSCALED:
629 case SI_FIX_FETCH_A2_SINT: {
630 /* The hardware returns an unsigned value; convert it to a
631 * signed one.
632 */
633 LLVMValueRef tmp = out[3];
634 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
635
636 /* First, recover the sign-extended signed integer value. */
637 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
638 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
639 else
640 tmp = ac_to_integer(&ctx->ac, tmp);
641
642 /* For the integer-like cases, do a natural sign extension.
643 *
644 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
645 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
646 * exponent.
647 */
648 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
649 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
650 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
651 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
652
653 /* Convert back to the right type. */
654 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
655 LLVMValueRef clamp;
656 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
657 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
658 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
659 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
660 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
661 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
662 }
663
664 out[3] = tmp;
665 break;
666 }
667 case SI_FIX_FETCH_RGBA_32_UNORM:
668 case SI_FIX_FETCH_RGBX_32_UNORM:
669 for (chan = 0; chan < 4; chan++) {
670 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
671 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
672 out[chan], ctx->f32, "");
673 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
674 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
675 }
676 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
677 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
678 out[3] = LLVMConstReal(ctx->f32, 1);
679 break;
680 case SI_FIX_FETCH_RGBA_32_SNORM:
681 case SI_FIX_FETCH_RGBX_32_SNORM:
682 case SI_FIX_FETCH_RGBA_32_FIXED:
683 case SI_FIX_FETCH_RGBX_32_FIXED: {
684 double scale;
685 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
686 scale = 1.0 / 0x10000;
687 else
688 scale = 1.0 / INT_MAX;
689
690 for (chan = 0; chan < 4; chan++) {
691 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
692 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
693 out[chan], ctx->f32, "");
694 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
695 LLVMConstReal(ctx->f32, scale), "");
696 }
697 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
698 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
699 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
700 out[3] = LLVMConstReal(ctx->f32, 1);
701 break;
702 }
703 case SI_FIX_FETCH_RGBA_32_USCALED:
704 for (chan = 0; chan < 4; chan++) {
705 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
706 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
707 out[chan], ctx->f32, "");
708 }
709 break;
710 case SI_FIX_FETCH_RGBA_32_SSCALED:
711 for (chan = 0; chan < 4; chan++) {
712 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
713 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
714 out[chan], ctx->f32, "");
715 }
716 break;
717 case SI_FIX_FETCH_RG_64_FLOAT:
718 for (chan = 0; chan < 2; chan++)
719 out[chan] = extract_double_to_float(ctx, input[0], chan);
720
721 out[2] = LLVMConstReal(ctx->f32, 0);
722 out[3] = LLVMConstReal(ctx->f32, 1);
723 break;
724 case SI_FIX_FETCH_RGB_64_FLOAT:
725 for (chan = 0; chan < 3; chan++)
726 out[chan] = extract_double_to_float(ctx, input[chan], 0);
727
728 out[3] = LLVMConstReal(ctx->f32, 1);
729 break;
730 case SI_FIX_FETCH_RGBA_64_FLOAT:
731 for (chan = 0; chan < 4; chan++) {
732 out[chan] = extract_double_to_float(ctx, input[chan / 2],
733 chan % 2);
734 }
735 break;
736 case SI_FIX_FETCH_RGB_8:
737 case SI_FIX_FETCH_RGB_8_INT:
738 case SI_FIX_FETCH_RGB_16:
739 case SI_FIX_FETCH_RGB_16_INT:
740 for (chan = 0; chan < 3; chan++) {
741 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
742 input[chan],
743 ctx->i32_0, "");
744 }
745 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
746 fix_fetch == SI_FIX_FETCH_RGB_16) {
747 out[3] = LLVMConstReal(ctx->f32, 1);
748 } else {
749 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
750 }
751 break;
752 }
753 }
754
755 static void declare_input_vs(
756 struct si_shader_context *ctx,
757 unsigned input_index,
758 const struct tgsi_full_declaration *decl,
759 LLVMValueRef out[4])
760 {
761 si_llvm_load_input_vs(ctx, input_index, out);
762 }
763
764 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
765 unsigned swizzle)
766 {
767 if (swizzle > 0)
768 return ctx->i32_0;
769
770 switch (ctx->type) {
771 case PIPE_SHADER_VERTEX:
772 return LLVMGetParam(ctx->main_fn,
773 ctx->param_vs_prim_id);
774 case PIPE_SHADER_TESS_CTRL:
775 return ctx->abi.tcs_patch_id;
776 case PIPE_SHADER_TESS_EVAL:
777 return ctx->abi.tes_patch_id;
778 case PIPE_SHADER_GEOMETRY:
779 return ctx->abi.gs_prim_id;
780 default:
781 assert(0);
782 return ctx->i32_0;
783 }
784 }
785
786 /**
787 * Return the value of tgsi_ind_register for indexing.
788 * This is the indirect index with the constant offset added to it.
789 */
790 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
791 const struct tgsi_ind_register *ind,
792 unsigned addr_mul,
793 int rel_index)
794 {
795 LLVMValueRef result;
796
797 if (ind->File == TGSI_FILE_ADDRESS) {
798 result = ctx->addrs[ind->Index][ind->Swizzle];
799 result = LLVMBuildLoad(ctx->ac.builder, result, "");
800 } else {
801 struct tgsi_full_src_register src = {};
802
803 src.Register.File = ind->File;
804 src.Register.Index = ind->Index;
805
806 /* Set the second index to 0 for constants. */
807 if (ind->File == TGSI_FILE_CONSTANT)
808 src.Register.Dimension = 1;
809
810 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
811 TGSI_TYPE_SIGNED,
812 ind->Swizzle);
813 result = ac_to_integer(&ctx->ac, result);
814 }
815
816 if (addr_mul != 1)
817 result = LLVMBuildMul(ctx->ac.builder, result,
818 LLVMConstInt(ctx->i32, addr_mul, 0), "");
819 result = LLVMBuildAdd(ctx->ac.builder, result,
820 LLVMConstInt(ctx->i32, rel_index, 0), "");
821 return result;
822 }
823
824 /**
825 * Like si_get_indirect_index, but restricts the return value to a (possibly
826 * undefined) value inside [0..num).
827 */
828 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
829 const struct tgsi_ind_register *ind,
830 int rel_index, unsigned num)
831 {
832 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
833
834 return si_llvm_bound_index(ctx, result, num);
835 }
836
837 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
838 LLVMValueRef vertex_dw_stride,
839 LLVMValueRef base_addr,
840 LLVMValueRef vertex_index,
841 LLVMValueRef param_index,
842 unsigned input_index,
843 ubyte *name,
844 ubyte *index,
845 bool is_patch)
846 {
847 if (vertex_dw_stride) {
848 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
849 LLVMBuildMul(ctx->ac.builder, vertex_index,
850 vertex_dw_stride, ""), "");
851 }
852
853 if (param_index) {
854 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
855 LLVMBuildMul(ctx->ac.builder, param_index,
856 LLVMConstInt(ctx->i32, 4, 0), ""), "");
857 }
858
859 int param = is_patch ?
860 si_shader_io_get_unique_index_patch(name[input_index],
861 index[input_index]) :
862 si_shader_io_get_unique_index(name[input_index],
863 index[input_index]);
864
865 /* Add the base address of the element. */
866 return LLVMBuildAdd(ctx->ac.builder, base_addr,
867 LLVMConstInt(ctx->i32, param * 4, 0), "");
868 }
869
870 /**
871 * Calculate a dword address given an input or output register and a stride.
872 */
873 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
874 const struct tgsi_full_dst_register *dst,
875 const struct tgsi_full_src_register *src,
876 LLVMValueRef vertex_dw_stride,
877 LLVMValueRef base_addr)
878 {
879 struct tgsi_shader_info *info = &ctx->shader->selector->info;
880 ubyte *name, *index, *array_first;
881 int input_index;
882 struct tgsi_full_dst_register reg;
883 LLVMValueRef vertex_index = NULL;
884 LLVMValueRef ind_index = NULL;
885
886 /* Set the register description. The address computation is the same
887 * for sources and destinations. */
888 if (src) {
889 reg.Register.File = src->Register.File;
890 reg.Register.Index = src->Register.Index;
891 reg.Register.Indirect = src->Register.Indirect;
892 reg.Register.Dimension = src->Register.Dimension;
893 reg.Indirect = src->Indirect;
894 reg.Dimension = src->Dimension;
895 reg.DimIndirect = src->DimIndirect;
896 } else
897 reg = *dst;
898
899 /* If the register is 2-dimensional (e.g. an array of vertices
900 * in a primitive), calculate the base address of the vertex. */
901 if (reg.Register.Dimension) {
902 if (reg.Dimension.Indirect)
903 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
904 1, reg.Dimension.Index);
905 else
906 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
907 }
908
909 /* Get information about the register. */
910 if (reg.Register.File == TGSI_FILE_INPUT) {
911 name = info->input_semantic_name;
912 index = info->input_semantic_index;
913 array_first = info->input_array_first;
914 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
915 name = info->output_semantic_name;
916 index = info->output_semantic_index;
917 array_first = info->output_array_first;
918 } else {
919 assert(0);
920 return NULL;
921 }
922
923 if (reg.Register.Indirect) {
924 /* Add the relative address of the element. */
925 if (reg.Indirect.ArrayID)
926 input_index = array_first[reg.Indirect.ArrayID];
927 else
928 input_index = reg.Register.Index;
929
930 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
931 1, reg.Register.Index - input_index);
932 } else {
933 input_index = reg.Register.Index;
934 }
935
936 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
937 base_addr, vertex_index,
938 ind_index, input_index,
939 name, index,
940 !reg.Register.Dimension);
941 }
942
943 /* The offchip buffer layout for TCS->TES is
944 *
945 * - attribute 0 of patch 0 vertex 0
946 * - attribute 0 of patch 0 vertex 1
947 * - attribute 0 of patch 0 vertex 2
948 * ...
949 * - attribute 0 of patch 1 vertex 0
950 * - attribute 0 of patch 1 vertex 1
951 * ...
952 * - attribute 1 of patch 0 vertex 0
953 * - attribute 1 of patch 0 vertex 1
954 * ...
955 * - per patch attribute 0 of patch 0
956 * - per patch attribute 0 of patch 1
957 * ...
958 *
959 * Note that every attribute has 4 components.
960 */
961 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
962 LLVMValueRef rel_patch_id,
963 LLVMValueRef vertex_index,
964 LLVMValueRef param_index)
965 {
966 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
967 LLVMValueRef param_stride, constant16;
968
969 vertices_per_patch = get_num_tcs_out_vertices(ctx);
970 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
971 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
972 num_patches, "");
973
974 constant16 = LLVMConstInt(ctx->i32, 16, 0);
975 if (vertex_index) {
976 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
977 vertices_per_patch, "");
978
979 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
980 vertex_index, "");
981
982 param_stride = total_vertices;
983 } else {
984 base_addr = rel_patch_id;
985 param_stride = num_patches;
986 }
987
988 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
989 LLVMBuildMul(ctx->ac.builder, param_index,
990 param_stride, ""), "");
991
992 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
993
994 if (!vertex_index) {
995 LLVMValueRef patch_data_offset =
996 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
997
998 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
999 patch_data_offset, "");
1000 }
1001 return base_addr;
1002 }
1003
1004 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1005 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1006 struct si_shader_context *ctx,
1007 LLVMValueRef vertex_index,
1008 LLVMValueRef param_index,
1009 unsigned param_base,
1010 ubyte *name,
1011 ubyte *index,
1012 bool is_patch)
1013 {
1014 unsigned param_index_base;
1015
1016 param_index_base = is_patch ?
1017 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1018 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1019
1020 if (param_index) {
1021 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1022 LLVMConstInt(ctx->i32, param_index_base, 0),
1023 "");
1024 } else {
1025 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1026 }
1027
1028 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1029 vertex_index, param_index);
1030 }
1031
1032 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1033 struct si_shader_context *ctx,
1034 const struct tgsi_full_dst_register *dst,
1035 const struct tgsi_full_src_register *src)
1036 {
1037 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1038 ubyte *name, *index, *array_first;
1039 struct tgsi_full_src_register reg;
1040 LLVMValueRef vertex_index = NULL;
1041 LLVMValueRef param_index = NULL;
1042 unsigned param_base;
1043
1044 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1045
1046 if (reg.Register.Dimension) {
1047
1048 if (reg.Dimension.Indirect)
1049 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1050 1, reg.Dimension.Index);
1051 else
1052 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1053 }
1054
1055 /* Get information about the register. */
1056 if (reg.Register.File == TGSI_FILE_INPUT) {
1057 name = info->input_semantic_name;
1058 index = info->input_semantic_index;
1059 array_first = info->input_array_first;
1060 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1061 name = info->output_semantic_name;
1062 index = info->output_semantic_index;
1063 array_first = info->output_array_first;
1064 } else {
1065 assert(0);
1066 return NULL;
1067 }
1068
1069 if (reg.Register.Indirect) {
1070 if (reg.Indirect.ArrayID)
1071 param_base = array_first[reg.Indirect.ArrayID];
1072 else
1073 param_base = reg.Register.Index;
1074
1075 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1076 1, reg.Register.Index - param_base);
1077
1078 } else {
1079 param_base = reg.Register.Index;
1080 }
1081
1082 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1083 param_index, param_base,
1084 name, index, !reg.Register.Dimension);
1085 }
1086
1087 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1088 LLVMTypeRef type, unsigned swizzle,
1089 LLVMValueRef buffer, LLVMValueRef offset,
1090 LLVMValueRef base, bool can_speculate)
1091 {
1092 struct si_shader_context *ctx = si_shader_context(bld_base);
1093 LLVMValueRef value, value2;
1094 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1095
1096 if (swizzle == ~0) {
1097 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1098 0, 1, 0, can_speculate, false);
1099
1100 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1101 }
1102
1103 if (!llvm_type_is_64bit(ctx, type)) {
1104 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1105 0, 1, 0, can_speculate, false);
1106
1107 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1108 return LLVMBuildExtractElement(ctx->ac.builder, value,
1109 LLVMConstInt(ctx->i32, swizzle, 0), "");
1110 }
1111
1112 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1113 swizzle * 4, 1, 0, can_speculate, false);
1114
1115 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1116 swizzle * 4 + 4, 1, 0, can_speculate, false);
1117
1118 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1119 }
1120
1121 /**
1122 * Load from LDS.
1123 *
1124 * \param type output value type
1125 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1126 * \param dw_addr address in dwords
1127 */
1128 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1129 LLVMTypeRef type, unsigned swizzle,
1130 LLVMValueRef dw_addr)
1131 {
1132 struct si_shader_context *ctx = si_shader_context(bld_base);
1133 LLVMValueRef value;
1134
1135 if (swizzle == ~0) {
1136 LLVMValueRef values[TGSI_NUM_CHANNELS];
1137
1138 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1139 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1140
1141 return lp_build_gather_values(&ctx->gallivm, values,
1142 TGSI_NUM_CHANNELS);
1143 }
1144
1145 /* Split 64-bit loads. */
1146 if (llvm_type_is_64bit(ctx, type)) {
1147 LLVMValueRef lo, hi;
1148
1149 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1150 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1151 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1152 }
1153
1154 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1155 LLVMConstInt(ctx->i32, swizzle, 0));
1156
1157 value = ac_lds_load(&ctx->ac, dw_addr);
1158
1159 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1160 }
1161
1162 /**
1163 * Store to LDS.
1164 *
1165 * \param swizzle offset (typically 0..3)
1166 * \param dw_addr address in dwords
1167 * \param value value to store
1168 */
1169 static void lds_store(struct si_shader_context *ctx,
1170 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1171 LLVMValueRef value)
1172 {
1173 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1174 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1175
1176 ac_lds_store(&ctx->ac, dw_addr, value);
1177 }
1178
1179 enum si_tess_ring {
1180 TCS_FACTOR_RING,
1181 TESS_OFFCHIP_RING_TCS,
1182 TESS_OFFCHIP_RING_TES,
1183 };
1184
1185 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1186 enum si_tess_ring ring)
1187 {
1188 LLVMBuilderRef builder = ctx->ac.builder;
1189 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1190 ctx->param_tcs_out_lds_layout;
1191 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1192
1193 /* TCS only receives high 13 bits of the address. */
1194 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1195 addr = LLVMBuildAnd(builder, addr,
1196 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1197 }
1198
1199 if (ring == TCS_FACTOR_RING) {
1200 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1201 addr = LLVMBuildAdd(builder, addr,
1202 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1203 }
1204
1205 LLVMValueRef desc[4];
1206 desc[0] = addr;
1207 desc[1] = LLVMConstInt(ctx->i32,
1208 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1209 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1210 desc[3] = LLVMConstInt(ctx->i32,
1211 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1212 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1213 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1214 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1215 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1216 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1217
1218 return ac_build_gather_values(&ctx->ac, desc, 4);
1219 }
1220
1221 static LLVMValueRef fetch_input_tcs(
1222 struct lp_build_tgsi_context *bld_base,
1223 const struct tgsi_full_src_register *reg,
1224 enum tgsi_opcode_type type, unsigned swizzle)
1225 {
1226 struct si_shader_context *ctx = si_shader_context(bld_base);
1227 LLVMValueRef dw_addr, stride;
1228
1229 stride = get_tcs_in_vertex_dw_stride(ctx);
1230 dw_addr = get_tcs_in_current_patch_offset(ctx);
1231 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1232
1233 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1234 }
1235
1236 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1237 LLVMTypeRef type,
1238 LLVMValueRef vertex_index,
1239 LLVMValueRef param_index,
1240 unsigned const_index,
1241 unsigned location,
1242 unsigned driver_location,
1243 unsigned component,
1244 unsigned num_components,
1245 bool is_patch,
1246 bool is_compact,
1247 bool load_input)
1248 {
1249 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1250 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1251 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1252 LLVMValueRef dw_addr, stride;
1253
1254 driver_location = driver_location / 4;
1255
1256 if (load_input) {
1257 stride = get_tcs_in_vertex_dw_stride(ctx);
1258 dw_addr = get_tcs_in_current_patch_offset(ctx);
1259 } else {
1260 if (is_patch) {
1261 stride = NULL;
1262 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1263 } else {
1264 stride = get_tcs_out_vertex_dw_stride(ctx);
1265 dw_addr = get_tcs_out_current_patch_offset(ctx);
1266 }
1267 }
1268
1269 if (param_index) {
1270 /* Add the constant index to the indirect index */
1271 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1272 LLVMConstInt(ctx->i32, const_index, 0), "");
1273 } else {
1274 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1275 }
1276
1277 ubyte *names;
1278 ubyte *indices;
1279 if (load_input) {
1280 names = info->input_semantic_name;
1281 indices = info->input_semantic_index;
1282 } else {
1283 names = info->output_semantic_name;
1284 indices = info->output_semantic_index;
1285 }
1286
1287 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1288 vertex_index, param_index,
1289 driver_location,
1290 names, indices,
1291 is_patch);
1292
1293 LLVMValueRef value[4];
1294 for (unsigned i = 0; i < num_components; i++) {
1295 unsigned offset = i;
1296 if (llvm_type_is_64bit(ctx, type))
1297 offset *= 2;
1298
1299 offset += component;
1300 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1301 }
1302
1303 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1304 }
1305
1306 static LLVMValueRef fetch_output_tcs(
1307 struct lp_build_tgsi_context *bld_base,
1308 const struct tgsi_full_src_register *reg,
1309 enum tgsi_opcode_type type, unsigned swizzle)
1310 {
1311 struct si_shader_context *ctx = si_shader_context(bld_base);
1312 LLVMValueRef dw_addr, stride;
1313
1314 if (reg->Register.Dimension) {
1315 stride = get_tcs_out_vertex_dw_stride(ctx);
1316 dw_addr = get_tcs_out_current_patch_offset(ctx);
1317 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1318 } else {
1319 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1320 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1321 }
1322
1323 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1324 }
1325
1326 static LLVMValueRef fetch_input_tes(
1327 struct lp_build_tgsi_context *bld_base,
1328 const struct tgsi_full_src_register *reg,
1329 enum tgsi_opcode_type type, unsigned swizzle)
1330 {
1331 struct si_shader_context *ctx = si_shader_context(bld_base);
1332 LLVMValueRef base, addr;
1333
1334 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1335 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1336
1337 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1338 ctx->tess_offchip_ring, base, addr, true);
1339 }
1340
1341 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1342 LLVMTypeRef type,
1343 LLVMValueRef vertex_index,
1344 LLVMValueRef param_index,
1345 unsigned const_index,
1346 unsigned location,
1347 unsigned driver_location,
1348 unsigned component,
1349 unsigned num_components,
1350 bool is_patch,
1351 bool is_compact,
1352 bool load_input)
1353 {
1354 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1355 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1356 LLVMValueRef base, addr;
1357
1358 driver_location = driver_location / 4;
1359
1360 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1361
1362 if (param_index) {
1363 /* Add the constant index to the indirect index */
1364 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1365 LLVMConstInt(ctx->i32, const_index, 0), "");
1366 } else {
1367 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1368 }
1369
1370 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1371 param_index, driver_location,
1372 info->input_semantic_name,
1373 info->input_semantic_index,
1374 is_patch);
1375
1376 /* TODO: This will generate rather ordinary llvm code, although it
1377 * should be easy for the optimiser to fix up. In future we might want
1378 * to refactor buffer_load(), but for now this maximises code sharing
1379 * between the NIR and TGSI backends.
1380 */
1381 LLVMValueRef value[4];
1382 for (unsigned i = 0; i < num_components; i++) {
1383 unsigned offset = i;
1384 if (llvm_type_is_64bit(ctx, type))
1385 offset *= 2;
1386
1387 offset += component;
1388 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1389 ctx->tess_offchip_ring, base, addr, true);
1390 }
1391
1392 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1393 }
1394
1395 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1396 const struct tgsi_full_instruction *inst,
1397 const struct tgsi_opcode_info *info,
1398 unsigned index,
1399 LLVMValueRef dst[4])
1400 {
1401 struct si_shader_context *ctx = si_shader_context(bld_base);
1402 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1403 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1404 unsigned chan_index;
1405 LLVMValueRef dw_addr, stride;
1406 LLVMValueRef buffer, base, buf_addr;
1407 LLVMValueRef values[4];
1408 bool skip_lds_store;
1409 bool is_tess_factor = false, is_tess_inner = false;
1410
1411 /* Only handle per-patch and per-vertex outputs here.
1412 * Vectors will be lowered to scalars and this function will be called again.
1413 */
1414 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1415 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1416 si_llvm_emit_store(bld_base, inst, info, index, dst);
1417 return;
1418 }
1419
1420 if (reg->Register.Dimension) {
1421 stride = get_tcs_out_vertex_dw_stride(ctx);
1422 dw_addr = get_tcs_out_current_patch_offset(ctx);
1423 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1424 skip_lds_store = !sh_info->reads_pervertex_outputs;
1425 } else {
1426 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1427 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1428 skip_lds_store = !sh_info->reads_perpatch_outputs;
1429
1430 if (!reg->Register.Indirect) {
1431 int name = sh_info->output_semantic_name[reg->Register.Index];
1432
1433 /* Always write tess factors into LDS for the TCS epilog. */
1434 if (name == TGSI_SEMANTIC_TESSINNER ||
1435 name == TGSI_SEMANTIC_TESSOUTER) {
1436 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1437 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1438 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1439 is_tess_factor = true;
1440 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1441 }
1442 }
1443 }
1444
1445 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1446
1447 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1448 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1449
1450 uint32_t writemask = reg->Register.WriteMask;
1451 while (writemask) {
1452 chan_index = u_bit_scan(&writemask);
1453 LLVMValueRef value = dst[chan_index];
1454
1455 if (inst->Instruction.Saturate)
1456 value = ac_build_clamp(&ctx->ac, value);
1457
1458 /* Skip LDS stores if there is no LDS read of this output. */
1459 if (!skip_lds_store)
1460 lds_store(ctx, chan_index, dw_addr, value);
1461
1462 value = ac_to_integer(&ctx->ac, value);
1463 values[chan_index] = value;
1464
1465 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1466 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1467 buf_addr, base,
1468 4 * chan_index, 1, 0, true, false);
1469 }
1470
1471 /* Write tess factors into VGPRs for the epilog. */
1472 if (is_tess_factor &&
1473 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1474 if (!is_tess_inner) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1476 ctx->invoc0_tess_factors[chan_index]);
1477 } else if (chan_index < 2) {
1478 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1479 ctx->invoc0_tess_factors[4 + chan_index]);
1480 }
1481 }
1482 }
1483
1484 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1485 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1486 values, 4);
1487 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1488 base, 0, 1, 0, true, false);
1489 }
1490 }
1491
1492 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1493 const struct nir_variable *var,
1494 LLVMValueRef vertex_index,
1495 LLVMValueRef param_index,
1496 unsigned const_index,
1497 LLVMValueRef src,
1498 unsigned writemask)
1499 {
1500 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1501 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1502 const unsigned component = var->data.location_frac;
1503 const bool is_patch = var->data.patch;
1504 unsigned driver_location = var->data.driver_location;
1505 LLVMValueRef dw_addr, stride;
1506 LLVMValueRef buffer, base, addr;
1507 LLVMValueRef values[4];
1508 bool skip_lds_store;
1509 bool is_tess_factor = false, is_tess_inner = false;
1510
1511 driver_location = driver_location / 4;
1512
1513 if (param_index) {
1514 /* Add the constant index to the indirect index */
1515 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1516 LLVMConstInt(ctx->i32, const_index, 0), "");
1517 } else {
1518 if (const_index != 0)
1519 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1520 }
1521
1522 if (!is_patch) {
1523 stride = get_tcs_out_vertex_dw_stride(ctx);
1524 dw_addr = get_tcs_out_current_patch_offset(ctx);
1525 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1526 vertex_index, param_index,
1527 driver_location,
1528 info->output_semantic_name,
1529 info->output_semantic_index,
1530 is_patch);
1531
1532 skip_lds_store = !info->reads_pervertex_outputs;
1533 } else {
1534 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1535 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1536 vertex_index, param_index,
1537 driver_location,
1538 info->output_semantic_name,
1539 info->output_semantic_index,
1540 is_patch);
1541
1542 skip_lds_store = !info->reads_perpatch_outputs;
1543
1544 if (!param_index) {
1545 int name = info->output_semantic_name[driver_location];
1546
1547 /* Always write tess factors into LDS for the TCS epilog. */
1548 if (name == TGSI_SEMANTIC_TESSINNER ||
1549 name == TGSI_SEMANTIC_TESSOUTER) {
1550 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1551 skip_lds_store = !info->reads_tessfactor_outputs &&
1552 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1553 is_tess_factor = true;
1554 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1555 }
1556 }
1557 }
1558
1559 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1560
1561 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1562
1563 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1564 param_index, driver_location,
1565 info->output_semantic_name,
1566 info->output_semantic_index,
1567 is_patch);
1568
1569 for (unsigned chan = 0; chan < 4; chan++) {
1570 if (!(writemask & (1 << chan)))
1571 continue;
1572 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1573
1574 /* Skip LDS stores if there is no LDS read of this output. */
1575 if (!skip_lds_store)
1576 lds_store(ctx, chan, dw_addr, value);
1577
1578 value = ac_to_integer(&ctx->ac, value);
1579 values[chan] = value;
1580
1581 if (writemask != 0xF && !is_tess_factor) {
1582 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1583 addr, base,
1584 4 * chan, 1, 0, true, false);
1585 }
1586
1587 /* Write tess factors into VGPRs for the epilog. */
1588 if (is_tess_factor &&
1589 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1590 if (!is_tess_inner) {
1591 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1592 ctx->invoc0_tess_factors[chan]);
1593 } else if (chan < 2) {
1594 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1595 ctx->invoc0_tess_factors[4 + chan]);
1596 }
1597 }
1598 }
1599
1600 if (writemask == 0xF && !is_tess_factor) {
1601 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1602 values, 4);
1603 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1604 base, 0, 1, 0, true, false);
1605 }
1606 }
1607
1608 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1609 unsigned input_index,
1610 unsigned vtx_offset_param,
1611 LLVMTypeRef type,
1612 unsigned swizzle)
1613 {
1614 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1615 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1616 struct si_shader *shader = ctx->shader;
1617 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1618 LLVMValueRef vtx_offset, soffset;
1619 struct tgsi_shader_info *info = &shader->selector->info;
1620 unsigned semantic_name = info->input_semantic_name[input_index];
1621 unsigned semantic_index = info->input_semantic_index[input_index];
1622 unsigned param;
1623 LLVMValueRef value;
1624
1625 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1626
1627 /* GFX9 has the ESGS ring in LDS. */
1628 if (ctx->screen->info.chip_class >= GFX9) {
1629 unsigned index = vtx_offset_param;
1630
1631 switch (index / 2) {
1632 case 0:
1633 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1634 index % 2 ? 16 : 0, 16);
1635 break;
1636 case 1:
1637 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1638 index % 2 ? 16 : 0, 16);
1639 break;
1640 case 2:
1641 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1642 index % 2 ? 16 : 0, 16);
1643 break;
1644 default:
1645 assert(0);
1646 return NULL;
1647 }
1648
1649 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1650 LLVMConstInt(ctx->i32, param * 4, 0), "");
1651 return lds_load(bld_base, type, swizzle, vtx_offset);
1652 }
1653
1654 /* GFX6: input load from the ESGS ring in memory. */
1655 if (swizzle == ~0) {
1656 LLVMValueRef values[TGSI_NUM_CHANNELS];
1657 unsigned chan;
1658 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1659 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1660 type, chan);
1661 }
1662 return lp_build_gather_values(&ctx->gallivm, values,
1663 TGSI_NUM_CHANNELS);
1664 }
1665
1666 /* Get the vertex offset parameter on GFX6. */
1667 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1668
1669 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1670
1671 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1672
1673 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1674 vtx_offset, soffset, 0, 1, 0, true, false);
1675 if (llvm_type_is_64bit(ctx, type)) {
1676 LLVMValueRef value2;
1677 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1678
1679 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1680 ctx->i32_0, vtx_offset, soffset,
1681 0, 1, 0, true, false);
1682 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1683 }
1684 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1685 }
1686
1687 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1688 unsigned location,
1689 unsigned driver_location,
1690 unsigned component,
1691 unsigned num_components,
1692 unsigned vertex_index,
1693 unsigned const_index,
1694 LLVMTypeRef type)
1695 {
1696 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1697
1698 LLVMValueRef value[4];
1699 for (unsigned i = 0; i < num_components; i++) {
1700 unsigned offset = i;
1701 if (llvm_type_is_64bit(ctx, type))
1702 offset *= 2;
1703
1704 offset += component;
1705 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1706 vertex_index, type, offset);
1707 }
1708
1709 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1710 }
1711
1712 static LLVMValueRef fetch_input_gs(
1713 struct lp_build_tgsi_context *bld_base,
1714 const struct tgsi_full_src_register *reg,
1715 enum tgsi_opcode_type type,
1716 unsigned swizzle)
1717 {
1718 struct si_shader_context *ctx = si_shader_context(bld_base);
1719 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1720
1721 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1722 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1723 return get_primitive_id(ctx, swizzle);
1724
1725 if (!reg->Register.Dimension)
1726 return NULL;
1727
1728 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1729 reg->Dimension.Index,
1730 tgsi2llvmtype(bld_base, type),
1731 swizzle);
1732 }
1733
1734 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1735 {
1736 switch (interpolate) {
1737 case TGSI_INTERPOLATE_CONSTANT:
1738 return 0;
1739
1740 case TGSI_INTERPOLATE_LINEAR:
1741 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1742 return SI_PARAM_LINEAR_SAMPLE;
1743 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1744 return SI_PARAM_LINEAR_CENTROID;
1745 else
1746 return SI_PARAM_LINEAR_CENTER;
1747 break;
1748 case TGSI_INTERPOLATE_COLOR:
1749 case TGSI_INTERPOLATE_PERSPECTIVE:
1750 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1751 return SI_PARAM_PERSP_SAMPLE;
1752 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1753 return SI_PARAM_PERSP_CENTROID;
1754 else
1755 return SI_PARAM_PERSP_CENTER;
1756 break;
1757 default:
1758 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1759 return -1;
1760 }
1761 }
1762
1763 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1764 unsigned attr_index, unsigned chan,
1765 LLVMValueRef prim_mask,
1766 LLVMValueRef i, LLVMValueRef j)
1767 {
1768 if (i || j) {
1769 return ac_build_fs_interp(&ctx->ac,
1770 LLVMConstInt(ctx->i32, chan, 0),
1771 LLVMConstInt(ctx->i32, attr_index, 0),
1772 prim_mask, i, j);
1773 }
1774 return ac_build_fs_interp_mov(&ctx->ac,
1775 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1776 LLVMConstInt(ctx->i32, chan, 0),
1777 LLVMConstInt(ctx->i32, attr_index, 0),
1778 prim_mask);
1779 }
1780
1781 /**
1782 * Interpolate a fragment shader input.
1783 *
1784 * @param ctx context
1785 * @param input_index index of the input in hardware
1786 * @param semantic_name TGSI_SEMANTIC_*
1787 * @param semantic_index semantic index
1788 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1789 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1790 * @param interp_param interpolation weights (i,j)
1791 * @param prim_mask SI_PARAM_PRIM_MASK
1792 * @param face SI_PARAM_FRONT_FACE
1793 * @param result the return value (4 components)
1794 */
1795 static void interp_fs_input(struct si_shader_context *ctx,
1796 unsigned input_index,
1797 unsigned semantic_name,
1798 unsigned semantic_index,
1799 unsigned num_interp_inputs,
1800 unsigned colors_read_mask,
1801 LLVMValueRef interp_param,
1802 LLVMValueRef prim_mask,
1803 LLVMValueRef face,
1804 LLVMValueRef result[4])
1805 {
1806 LLVMValueRef i = NULL, j = NULL;
1807 unsigned chan;
1808
1809 /* fs.constant returns the param from the middle vertex, so it's not
1810 * really useful for flat shading. It's meant to be used for custom
1811 * interpolation (but the intrinsic can't fetch from the other two
1812 * vertices).
1813 *
1814 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1815 * to do the right thing. The only reason we use fs.constant is that
1816 * fs.interp cannot be used on integers, because they can be equal
1817 * to NaN.
1818 *
1819 * When interp is false we will use fs.constant or for newer llvm,
1820 * amdgcn.interp.mov.
1821 */
1822 bool interp = interp_param != NULL;
1823
1824 if (interp) {
1825 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1826 LLVMVectorType(ctx->f32, 2), "");
1827
1828 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1829 ctx->i32_0, "");
1830 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1831 ctx->i32_1, "");
1832 }
1833
1834 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1835 ctx->shader->key.part.ps.prolog.color_two_side) {
1836 LLVMValueRef is_face_positive;
1837
1838 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1839 * otherwise it's at offset "num_inputs".
1840 */
1841 unsigned back_attr_offset = num_interp_inputs;
1842 if (semantic_index == 1 && colors_read_mask & 0xf)
1843 back_attr_offset += 1;
1844
1845 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1846 face, ctx->i32_0, "");
1847
1848 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1849 LLVMValueRef front, back;
1850
1851 front = si_build_fs_interp(ctx,
1852 input_index, chan,
1853 prim_mask, i, j);
1854 back = si_build_fs_interp(ctx,
1855 back_attr_offset, chan,
1856 prim_mask, i, j);
1857
1858 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1859 is_face_positive,
1860 front,
1861 back,
1862 "");
1863 }
1864 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1865 result[0] = si_build_fs_interp(ctx, input_index,
1866 0, prim_mask, i, j);
1867 result[1] =
1868 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1869 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1870 } else {
1871 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1872 result[chan] = si_build_fs_interp(ctx,
1873 input_index, chan,
1874 prim_mask, i, j);
1875 }
1876 }
1877 }
1878
1879 void si_llvm_load_input_fs(
1880 struct si_shader_context *ctx,
1881 unsigned input_index,
1882 LLVMValueRef out[4])
1883 {
1884 struct lp_build_context *base = &ctx->bld_base.base;
1885 struct si_shader *shader = ctx->shader;
1886 struct tgsi_shader_info *info = &shader->selector->info;
1887 LLVMValueRef main_fn = ctx->main_fn;
1888 LLVMValueRef interp_param = NULL;
1889 int interp_param_idx;
1890 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1891 unsigned semantic_index = info->input_semantic_index[input_index];
1892 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1893 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1894
1895 /* Get colors from input VGPRs (set by the prolog). */
1896 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1897 unsigned colors_read = shader->selector->info.colors_read;
1898 unsigned mask = colors_read >> (semantic_index * 4);
1899 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1900 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1901
1902 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1903 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1904 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1905 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1906 return;
1907 }
1908
1909 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1910 if (interp_param_idx == -1)
1911 return;
1912 else if (interp_param_idx) {
1913 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1914 }
1915
1916 interp_fs_input(ctx, input_index, semantic_name,
1917 semantic_index, 0, /* this param is unused */
1918 shader->selector->info.colors_read, interp_param,
1919 ctx->abi.prim_mask,
1920 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1921 &out[0]);
1922 }
1923
1924 static void declare_input_fs(
1925 struct si_shader_context *ctx,
1926 unsigned input_index,
1927 const struct tgsi_full_declaration *decl,
1928 LLVMValueRef out[4])
1929 {
1930 si_llvm_load_input_fs(ctx, input_index, out);
1931 }
1932
1933 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1934 {
1935 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1936 }
1937
1938 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1939 {
1940 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1941
1942 /* For non-indexed draws, the base vertex set by the driver
1943 * (for direct draws) or the CP (for indirect draws) is the
1944 * first vertex ID, but GLSL expects 0 to be returned.
1945 */
1946 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1947 ctx->param_vs_state_bits);
1948 LLVMValueRef indexed;
1949
1950 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1951 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1952
1953 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1954 ctx->i32_0, "");
1955 }
1956
1957 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1958 {
1959 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1960
1961 LLVMValueRef values[3];
1962 LLVMValueRef result;
1963 unsigned i;
1964 unsigned *properties = ctx->shader->selector->info.properties;
1965
1966 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1967 unsigned sizes[3] = {
1968 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1969 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1970 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1971 };
1972
1973 for (i = 0; i < 3; ++i)
1974 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1975
1976 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1977 } else {
1978 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1979 }
1980
1981 return result;
1982 }
1983
1984 /**
1985 * Load a dword from a constant buffer.
1986 */
1987 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1988 LLVMValueRef resource,
1989 LLVMValueRef offset)
1990 {
1991 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1992 0, 0, 0, true, true);
1993 }
1994
1995 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1996 {
1997 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1998 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1999 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2000 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
2001 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
2002
2003 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2004 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
2005 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
2006
2007 LLVMValueRef pos[4] = {
2008 buffer_load_const(ctx, resource, offset0),
2009 buffer_load_const(ctx, resource, offset1),
2010 LLVMConstReal(ctx->f32, 0),
2011 LLVMConstReal(ctx->f32, 0)
2012 };
2013
2014 return lp_build_gather_values(&ctx->gallivm, pos, 4);
2015 }
2016
2017 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
2018 {
2019 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2020 return ac_to_integer(&ctx->ac, abi->sample_coverage);
2021 }
2022
2023 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2024 {
2025 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2026 struct lp_build_context *bld = &ctx->bld_base.base;
2027
2028 LLVMValueRef coord[4] = {
2029 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2030 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2031 ctx->ac.f32_0,
2032 ctx->ac.f32_0
2033 };
2034
2035 /* For triangles, the vector should be (u, v, 1-u-v). */
2036 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2037 PIPE_PRIM_TRIANGLES)
2038 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
2039 lp_build_add(bld, coord[0], coord[1]));
2040
2041 return lp_build_gather_values(&ctx->gallivm, coord, 4);
2042 }
2043
2044 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2045 unsigned semantic_name)
2046 {
2047 LLVMValueRef base, addr;
2048
2049 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2050
2051 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2052 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2053 LLVMConstInt(ctx->i32, param, 0));
2054
2055 return buffer_load(&ctx->bld_base, ctx->f32,
2056 ~0, ctx->tess_offchip_ring, base, addr, true);
2057
2058 }
2059
2060 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2061 unsigned varying_id)
2062 {
2063 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2064 unsigned semantic_name;
2065
2066 switch (varying_id) {
2067 case VARYING_SLOT_TESS_LEVEL_INNER:
2068 semantic_name = TGSI_SEMANTIC_TESSINNER;
2069 break;
2070 case VARYING_SLOT_TESS_LEVEL_OUTER:
2071 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2072 break;
2073 default:
2074 unreachable("unknown tess level");
2075 }
2076
2077 return load_tess_level(ctx, semantic_name);
2078
2079 }
2080
2081 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2082 {
2083 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2084 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2085 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2086 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2087 return get_num_tcs_out_vertices(ctx);
2088 else
2089 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2090 }
2091
2092 void si_load_system_value(struct si_shader_context *ctx,
2093 unsigned index,
2094 const struct tgsi_full_declaration *decl)
2095 {
2096 LLVMValueRef value = 0;
2097
2098 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2099
2100 switch (decl->Semantic.Name) {
2101 case TGSI_SEMANTIC_INSTANCEID:
2102 value = ctx->abi.instance_id;
2103 break;
2104
2105 case TGSI_SEMANTIC_VERTEXID:
2106 value = LLVMBuildAdd(ctx->ac.builder,
2107 ctx->abi.vertex_id,
2108 ctx->abi.base_vertex, "");
2109 break;
2110
2111 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2112 /* Unused. Clarify the meaning in indexed vs. non-indexed
2113 * draws if this is ever used again. */
2114 assert(false);
2115 break;
2116
2117 case TGSI_SEMANTIC_BASEVERTEX:
2118 value = get_base_vertex(&ctx->abi);
2119 break;
2120
2121 case TGSI_SEMANTIC_BASEINSTANCE:
2122 value = ctx->abi.start_instance;
2123 break;
2124
2125 case TGSI_SEMANTIC_DRAWID:
2126 value = ctx->abi.draw_id;
2127 break;
2128
2129 case TGSI_SEMANTIC_INVOCATIONID:
2130 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2131 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2132 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2133 value = ctx->abi.gs_invocation_id;
2134 else
2135 assert(!"INVOCATIONID not implemented");
2136 break;
2137
2138 case TGSI_SEMANTIC_POSITION:
2139 {
2140 LLVMValueRef pos[4] = {
2141 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2142 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2143 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2144 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2145 LLVMGetParam(ctx->main_fn,
2146 SI_PARAM_POS_W_FLOAT)),
2147 };
2148 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2149 break;
2150 }
2151
2152 case TGSI_SEMANTIC_FACE:
2153 value = ctx->abi.front_face;
2154 break;
2155
2156 case TGSI_SEMANTIC_SAMPLEID:
2157 value = si_get_sample_id(ctx);
2158 break;
2159
2160 case TGSI_SEMANTIC_SAMPLEPOS: {
2161 LLVMValueRef pos[4] = {
2162 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2163 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2164 LLVMConstReal(ctx->f32, 0),
2165 LLVMConstReal(ctx->f32, 0)
2166 };
2167 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2168 TGSI_OPCODE_FRC, pos[0]);
2169 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2170 TGSI_OPCODE_FRC, pos[1]);
2171 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2172 break;
2173 }
2174
2175 case TGSI_SEMANTIC_SAMPLEMASK:
2176 /* This can only occur with the OpenGL Core profile, which
2177 * doesn't support smoothing.
2178 */
2179 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2180 break;
2181
2182 case TGSI_SEMANTIC_TESSCOORD:
2183 value = si_load_tess_coord(&ctx->abi);
2184 break;
2185
2186 case TGSI_SEMANTIC_VERTICESIN:
2187 value = si_load_patch_vertices_in(&ctx->abi);
2188 break;
2189
2190 case TGSI_SEMANTIC_TESSINNER:
2191 case TGSI_SEMANTIC_TESSOUTER:
2192 value = load_tess_level(ctx, decl->Semantic.Name);
2193 break;
2194
2195 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2196 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2197 {
2198 LLVMValueRef buf, slot, val[4];
2199 int i, offset;
2200
2201 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2202 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2203 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2204 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2205
2206 for (i = 0; i < 4; i++)
2207 val[i] = buffer_load_const(ctx, buf,
2208 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2209 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2210 break;
2211 }
2212
2213 case TGSI_SEMANTIC_PRIMID:
2214 value = get_primitive_id(ctx, 0);
2215 break;
2216
2217 case TGSI_SEMANTIC_GRID_SIZE:
2218 value = ctx->abi.num_work_groups;
2219 break;
2220
2221 case TGSI_SEMANTIC_BLOCK_SIZE:
2222 value = get_block_size(&ctx->abi);
2223 break;
2224
2225 case TGSI_SEMANTIC_BLOCK_ID:
2226 {
2227 LLVMValueRef values[3];
2228
2229 for (int i = 0; i < 3; i++) {
2230 values[i] = ctx->i32_0;
2231 if (ctx->abi.workgroup_ids[i]) {
2232 values[i] = ctx->abi.workgroup_ids[i];
2233 }
2234 }
2235 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2236 break;
2237 }
2238
2239 case TGSI_SEMANTIC_THREAD_ID:
2240 value = ctx->abi.local_invocation_ids;
2241 break;
2242
2243 case TGSI_SEMANTIC_HELPER_INVOCATION:
2244 value = lp_build_intrinsic(ctx->ac.builder,
2245 "llvm.amdgcn.ps.live",
2246 ctx->i1, NULL, 0,
2247 LP_FUNC_ATTR_READNONE);
2248 value = LLVMBuildNot(ctx->ac.builder, value, "");
2249 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2250 break;
2251
2252 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2253 value = LLVMConstInt(ctx->i32, 64, 0);
2254 break;
2255
2256 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2257 value = ac_get_thread_id(&ctx->ac);
2258 break;
2259
2260 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2261 {
2262 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2263 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2264 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2265 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2266 break;
2267 }
2268
2269 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2270 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2271 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2272 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2273 {
2274 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2275 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2276 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2277 /* All bits set except LSB */
2278 value = LLVMConstInt(ctx->i64, -2, 0);
2279 } else {
2280 /* All bits set */
2281 value = LLVMConstInt(ctx->i64, -1, 0);
2282 }
2283 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2284 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2285 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2286 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2287 value = LLVMBuildNot(ctx->ac.builder, value, "");
2288 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2289 break;
2290 }
2291
2292 default:
2293 assert(!"unknown system value");
2294 return;
2295 }
2296
2297 ctx->system_values[index] = value;
2298 }
2299
2300 void si_declare_compute_memory(struct si_shader_context *ctx)
2301 {
2302 struct si_shader_selector *sel = ctx->shader->selector;
2303
2304 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2305 LLVMValueRef var;
2306
2307 assert(!ctx->ac.lds);
2308
2309 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2310 LLVMArrayType(ctx->i8, sel->local_size),
2311 "compute_lds",
2312 AC_LOCAL_ADDR_SPACE);
2313 LLVMSetAlignment(var, 4);
2314
2315 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2316 }
2317
2318 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2319 const struct tgsi_full_declaration *decl)
2320 {
2321 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2322 assert(decl->Range.First == decl->Range.Last);
2323
2324 si_declare_compute_memory(ctx);
2325 }
2326
2327 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2328 {
2329 LLVMValueRef ptr =
2330 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2331 struct si_shader_selector *sel = ctx->shader->selector;
2332
2333 /* Do the bounds checking with a descriptor, because
2334 * doing computation and manual bounds checking of 64-bit
2335 * addresses generates horrible VALU code with very high
2336 * VGPR usage and very low SIMD occupancy.
2337 */
2338 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2339
2340 LLVMValueRef desc0, desc1;
2341 if (HAVE_32BIT_POINTERS) {
2342 desc0 = ptr;
2343 desc1 = LLVMConstInt(ctx->i32,
2344 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2345 } else {
2346 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2347 desc0 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, "");
2348 desc1 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, "");
2349 /* Mask out all bits except BASE_ADDRESS_HI. */
2350 desc1 = LLVMBuildAnd(ctx->ac.builder, desc1,
2351 LLVMConstInt(ctx->i32, ~C_008F04_BASE_ADDRESS_HI, 0), "");
2352 }
2353
2354 LLVMValueRef desc_elems[] = {
2355 desc0,
2356 desc1,
2357 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2358 LLVMConstInt(ctx->i32,
2359 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2360 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2361 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2362 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2363 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2364 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2365 };
2366
2367 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2368 }
2369
2370 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2371 {
2372 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2373 ctx->param_const_and_shader_buffers);
2374
2375 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2376 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2377 }
2378
2379 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2380 {
2381 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2382 struct si_shader_selector *sel = ctx->shader->selector;
2383
2384 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2385
2386 if (sel->info.const_buffers_declared == 1 &&
2387 sel->info.shader_buffers_declared == 0) {
2388 return load_const_buffer_desc_fast_path(ctx);
2389 }
2390
2391 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2392 index = LLVMBuildAdd(ctx->ac.builder, index,
2393 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2394
2395 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2396 }
2397
2398 static LLVMValueRef
2399 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2400 {
2401 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2402 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2403 ctx->param_const_and_shader_buffers);
2404
2405 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2406 index = LLVMBuildSub(ctx->ac.builder,
2407 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2408 index, "");
2409
2410 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2411 }
2412
2413 static LLVMValueRef fetch_constant(
2414 struct lp_build_tgsi_context *bld_base,
2415 const struct tgsi_full_src_register *reg,
2416 enum tgsi_opcode_type type,
2417 unsigned swizzle)
2418 {
2419 struct si_shader_context *ctx = si_shader_context(bld_base);
2420 struct si_shader_selector *sel = ctx->shader->selector;
2421 const struct tgsi_ind_register *ireg = &reg->Indirect;
2422 unsigned buf, idx;
2423
2424 LLVMValueRef addr, bufp;
2425
2426 if (swizzle == LP_CHAN_ALL) {
2427 unsigned chan;
2428 LLVMValueRef values[4];
2429 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2430 values[chan] = fetch_constant(bld_base, reg, type, chan);
2431
2432 return lp_build_gather_values(&ctx->gallivm, values, 4);
2433 }
2434
2435 /* Split 64-bit loads. */
2436 if (tgsi_type_is_64bit(type)) {
2437 LLVMValueRef lo, hi;
2438
2439 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2440 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2441 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2442 lo, hi);
2443 }
2444
2445 idx = reg->Register.Index * 4 + swizzle;
2446 if (reg->Register.Indirect) {
2447 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2448 } else {
2449 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2450 }
2451
2452 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2453 if (sel->info.const_buffers_declared == 1 &&
2454 sel->info.shader_buffers_declared == 0) {
2455
2456 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2457 * loads, and up to x4 load opcode merging. However, it leads to horrible
2458 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2459 *
2460 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2461 *
2462 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2463 * a descriptor and s_buffer_load_dword using it, so we can't expand
2464 * the pointer into a full descriptor like below. We have to use
2465 * s_load_dword instead. The only case when LLVM 5.0 would select
2466 * s_buffer_load_dword (that we have to prevent) is when we use use
2467 * a literal offset where we don't need bounds checking.
2468 */
2469 if (ctx->screen->info.chip_class == SI && HAVE_LLVM < 0x0600 &&
2470 !reg->Register.Indirect) {
2471 LLVMValueRef ptr =
2472 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2473
2474 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2475 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2476 return bitcast(bld_base, type, result);
2477 }
2478
2479 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2480 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2481 return bitcast(bld_base, type, result);
2482 }
2483
2484 assert(reg->Register.Dimension);
2485 buf = reg->Dimension.Index;
2486
2487 if (reg->Dimension.Indirect) {
2488 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2489 LLVMValueRef index;
2490 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2491 reg->Dimension.Index,
2492 ctx->num_const_buffers);
2493 index = LLVMBuildAdd(ctx->ac.builder, index,
2494 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2495 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2496 } else
2497 bufp = load_const_buffer_desc(ctx, buf);
2498
2499 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2500 }
2501
2502 /* Initialize arguments for the shader export intrinsic */
2503 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2504 LLVMValueRef *values,
2505 unsigned target,
2506 struct ac_export_args *args)
2507 {
2508 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2509 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2510 unsigned chan;
2511 bool is_int8, is_int10;
2512
2513 /* Default is 0xf. Adjusted below depending on the format. */
2514 args->enabled_channels = 0xf; /* writemask */
2515
2516 /* Specify whether the EXEC mask represents the valid mask */
2517 args->valid_mask = 0;
2518
2519 /* Specify whether this is the last export */
2520 args->done = 0;
2521
2522 /* Specify the target we are exporting */
2523 args->target = target;
2524
2525 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2526 const struct si_shader_key *key = &ctx->shader->key;
2527 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2528 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2529
2530 assert(cbuf >= 0 && cbuf < 8);
2531 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2532 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2533 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2534 }
2535
2536 args->compr = false;
2537 args->out[0] = f32undef;
2538 args->out[1] = f32undef;
2539 args->out[2] = f32undef;
2540 args->out[3] = f32undef;
2541
2542 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2543 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2544 unsigned bits, bool hi) = NULL;
2545
2546 switch (spi_shader_col_format) {
2547 case V_028714_SPI_SHADER_ZERO:
2548 args->enabled_channels = 0; /* writemask */
2549 args->target = V_008DFC_SQ_EXP_NULL;
2550 break;
2551
2552 case V_028714_SPI_SHADER_32_R:
2553 args->enabled_channels = 1; /* writemask */
2554 args->out[0] = values[0];
2555 break;
2556
2557 case V_028714_SPI_SHADER_32_GR:
2558 args->enabled_channels = 0x3; /* writemask */
2559 args->out[0] = values[0];
2560 args->out[1] = values[1];
2561 break;
2562
2563 case V_028714_SPI_SHADER_32_AR:
2564 args->enabled_channels = 0x9; /* writemask */
2565 args->out[0] = values[0];
2566 args->out[3] = values[3];
2567 break;
2568
2569 case V_028714_SPI_SHADER_FP16_ABGR:
2570 packf = ac_build_cvt_pkrtz_f16;
2571 break;
2572
2573 case V_028714_SPI_SHADER_UNORM16_ABGR:
2574 packf = ac_build_cvt_pknorm_u16;
2575 break;
2576
2577 case V_028714_SPI_SHADER_SNORM16_ABGR:
2578 packf = ac_build_cvt_pknorm_i16;
2579 break;
2580
2581 case V_028714_SPI_SHADER_UINT16_ABGR:
2582 packi = ac_build_cvt_pk_u16;
2583 break;
2584
2585 case V_028714_SPI_SHADER_SINT16_ABGR:
2586 packi = ac_build_cvt_pk_i16;
2587 break;
2588
2589 case V_028714_SPI_SHADER_32_ABGR:
2590 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2591 break;
2592 }
2593
2594 /* Pack f16 or norm_i16/u16. */
2595 if (packf) {
2596 for (chan = 0; chan < 2; chan++) {
2597 LLVMValueRef pack_args[2] = {
2598 values[2 * chan],
2599 values[2 * chan + 1]
2600 };
2601 LLVMValueRef packed;
2602
2603 packed = packf(&ctx->ac, pack_args);
2604 args->out[chan] = ac_to_float(&ctx->ac, packed);
2605 }
2606 args->compr = 1; /* COMPR flag */
2607 }
2608 /* Pack i16/u16. */
2609 if (packi) {
2610 for (chan = 0; chan < 2; chan++) {
2611 LLVMValueRef pack_args[2] = {
2612 ac_to_integer(&ctx->ac, values[2 * chan]),
2613 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2614 };
2615 LLVMValueRef packed;
2616
2617 packed = packi(&ctx->ac, pack_args,
2618 is_int8 ? 8 : is_int10 ? 10 : 16,
2619 chan == 1);
2620 args->out[chan] = ac_to_float(&ctx->ac, packed);
2621 }
2622 args->compr = 1; /* COMPR flag */
2623 }
2624 }
2625
2626 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2627 LLVMValueRef alpha)
2628 {
2629 struct si_shader_context *ctx = si_shader_context(bld_base);
2630
2631 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2632 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2633 [PIPE_FUNC_LESS] = LLVMRealOLT,
2634 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2635 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2636 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2637 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2638 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2639 };
2640 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2641 assert(cond);
2642
2643 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2644 SI_PARAM_ALPHA_REF);
2645 LLVMValueRef alpha_pass =
2646 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2647 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2648 } else {
2649 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2650 }
2651 }
2652
2653 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2654 LLVMValueRef alpha,
2655 unsigned samplemask_param)
2656 {
2657 struct si_shader_context *ctx = si_shader_context(bld_base);
2658 LLVMValueRef coverage;
2659
2660 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2661 coverage = LLVMGetParam(ctx->main_fn,
2662 samplemask_param);
2663 coverage = ac_to_integer(&ctx->ac, coverage);
2664
2665 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2666 ctx->i32,
2667 &coverage, 1, LP_FUNC_ATTR_READNONE);
2668
2669 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2670 ctx->f32, "");
2671
2672 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2673 LLVMConstReal(ctx->f32,
2674 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2675
2676 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2677 }
2678
2679 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2680 struct ac_export_args *pos, LLVMValueRef *out_elts)
2681 {
2682 unsigned reg_index;
2683 unsigned chan;
2684 unsigned const_chan;
2685 LLVMValueRef base_elt;
2686 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2687 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2688 SI_VS_CONST_CLIP_PLANES, 0);
2689 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2690
2691 for (reg_index = 0; reg_index < 2; reg_index ++) {
2692 struct ac_export_args *args = &pos[2 + reg_index];
2693
2694 args->out[0] =
2695 args->out[1] =
2696 args->out[2] =
2697 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2698
2699 /* Compute dot products of position and user clip plane vectors */
2700 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2701 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2702 LLVMValueRef addr =
2703 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2704 const_chan) * 4, 0);
2705 base_elt = buffer_load_const(ctx, const_resource,
2706 addr);
2707 args->out[chan] =
2708 lp_build_add(&ctx->bld_base.base, args->out[chan],
2709 lp_build_mul(&ctx->bld_base.base, base_elt,
2710 out_elts[const_chan]));
2711 }
2712 }
2713
2714 args->enabled_channels = 0xf;
2715 args->valid_mask = 0;
2716 args->done = 0;
2717 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2718 args->compr = 0;
2719 }
2720 }
2721
2722 static void si_dump_streamout(struct pipe_stream_output_info *so)
2723 {
2724 unsigned i;
2725
2726 if (so->num_outputs)
2727 fprintf(stderr, "STREAMOUT\n");
2728
2729 for (i = 0; i < so->num_outputs; i++) {
2730 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2731 so->output[i].start_component;
2732 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2733 i, so->output[i].output_buffer,
2734 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2735 so->output[i].register_index,
2736 mask & 1 ? "x" : "",
2737 mask & 2 ? "y" : "",
2738 mask & 4 ? "z" : "",
2739 mask & 8 ? "w" : "");
2740 }
2741 }
2742
2743 static void emit_streamout_output(struct si_shader_context *ctx,
2744 LLVMValueRef const *so_buffers,
2745 LLVMValueRef const *so_write_offsets,
2746 struct pipe_stream_output *stream_out,
2747 struct si_shader_output_values *shader_out)
2748 {
2749 unsigned buf_idx = stream_out->output_buffer;
2750 unsigned start = stream_out->start_component;
2751 unsigned num_comps = stream_out->num_components;
2752 LLVMValueRef out[4];
2753
2754 assert(num_comps && num_comps <= 4);
2755 if (!num_comps || num_comps > 4)
2756 return;
2757
2758 /* Load the output as int. */
2759 for (int j = 0; j < num_comps; j++) {
2760 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2761
2762 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2763 }
2764
2765 /* Pack the output. */
2766 LLVMValueRef vdata = NULL;
2767
2768 switch (num_comps) {
2769 case 1: /* as i32 */
2770 vdata = out[0];
2771 break;
2772 case 2: /* as v2i32 */
2773 case 3: /* as v4i32 (aligned to 4) */
2774 case 4: /* as v4i32 */
2775 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2776 for (int j = 0; j < num_comps; j++) {
2777 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2778 LLVMConstInt(ctx->i32, j, 0), "");
2779 }
2780 break;
2781 }
2782
2783 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2784 vdata, num_comps,
2785 so_write_offsets[buf_idx],
2786 ctx->i32_0,
2787 stream_out->dst_offset * 4, 1, 1, true, false);
2788 }
2789
2790 /**
2791 * Write streamout data to buffers for vertex stream @p stream (different
2792 * vertex streams can occur for GS copy shaders).
2793 */
2794 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2795 struct si_shader_output_values *outputs,
2796 unsigned noutput, unsigned stream)
2797 {
2798 struct si_shader_selector *sel = ctx->shader->selector;
2799 struct pipe_stream_output_info *so = &sel->so;
2800 LLVMBuilderRef builder = ctx->ac.builder;
2801 int i;
2802 struct lp_build_if_state if_ctx;
2803
2804 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2805 LLVMValueRef so_vtx_count =
2806 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2807
2808 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2809
2810 /* can_emit = tid < so_vtx_count; */
2811 LLVMValueRef can_emit =
2812 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2813
2814 /* Emit the streamout code conditionally. This actually avoids
2815 * out-of-bounds buffer access. The hw tells us via the SGPR
2816 * (so_vtx_count) which threads are allowed to emit streamout data. */
2817 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2818 {
2819 /* The buffer offset is computed as follows:
2820 * ByteOffset = streamout_offset[buffer_id]*4 +
2821 * (streamout_write_index + thread_id)*stride[buffer_id] +
2822 * attrib_offset
2823 */
2824
2825 LLVMValueRef so_write_index =
2826 LLVMGetParam(ctx->main_fn,
2827 ctx->param_streamout_write_index);
2828
2829 /* Compute (streamout_write_index + thread_id). */
2830 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2831
2832 /* Load the descriptor and compute the write offset for each
2833 * enabled buffer. */
2834 LLVMValueRef so_write_offset[4] = {};
2835 LLVMValueRef so_buffers[4];
2836 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2837 ctx->param_rw_buffers);
2838
2839 for (i = 0; i < 4; i++) {
2840 if (!so->stride[i])
2841 continue;
2842
2843 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2844 SI_VS_STREAMOUT_BUF0 + i, 0);
2845
2846 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2847
2848 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2849 ctx->param_streamout_offset[i]);
2850 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2851
2852 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2853 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2854 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2855 }
2856
2857 /* Write streamout data. */
2858 for (i = 0; i < so->num_outputs; i++) {
2859 unsigned reg = so->output[i].register_index;
2860
2861 if (reg >= noutput)
2862 continue;
2863
2864 if (stream != so->output[i].stream)
2865 continue;
2866
2867 emit_streamout_output(ctx, so_buffers, so_write_offset,
2868 &so->output[i], &outputs[reg]);
2869 }
2870 }
2871 lp_build_endif(&if_ctx);
2872 }
2873
2874 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2875 LLVMValueRef *values)
2876 {
2877 struct ac_export_args args;
2878
2879 si_llvm_init_export_args(ctx, values,
2880 V_008DFC_SQ_EXP_PARAM + index, &args);
2881 ac_build_export(&ctx->ac, &args);
2882 }
2883
2884 static void si_build_param_exports(struct si_shader_context *ctx,
2885 struct si_shader_output_values *outputs,
2886 unsigned noutput)
2887 {
2888 struct si_shader *shader = ctx->shader;
2889 unsigned param_count = 0;
2890
2891 for (unsigned i = 0; i < noutput; i++) {
2892 unsigned semantic_name = outputs[i].semantic_name;
2893 unsigned semantic_index = outputs[i].semantic_index;
2894
2895 if (outputs[i].vertex_stream[0] != 0 &&
2896 outputs[i].vertex_stream[1] != 0 &&
2897 outputs[i].vertex_stream[2] != 0 &&
2898 outputs[i].vertex_stream[3] != 0)
2899 continue;
2900
2901 switch (semantic_name) {
2902 case TGSI_SEMANTIC_LAYER:
2903 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2904 case TGSI_SEMANTIC_CLIPDIST:
2905 case TGSI_SEMANTIC_COLOR:
2906 case TGSI_SEMANTIC_BCOLOR:
2907 case TGSI_SEMANTIC_PRIMID:
2908 case TGSI_SEMANTIC_FOG:
2909 case TGSI_SEMANTIC_TEXCOORD:
2910 case TGSI_SEMANTIC_GENERIC:
2911 break;
2912 default:
2913 continue;
2914 }
2915
2916 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2917 semantic_index < SI_MAX_IO_GENERIC) &&
2918 shader->key.opt.kill_outputs &
2919 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2920 continue;
2921
2922 si_export_param(ctx, param_count, outputs[i].values);
2923
2924 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2925 shader->info.vs_output_param_offset[i] = param_count++;
2926 }
2927
2928 shader->info.nr_param_exports = param_count;
2929 }
2930
2931 /* Generate export instructions for hardware VS shader stage */
2932 static void si_llvm_export_vs(struct si_shader_context *ctx,
2933 struct si_shader_output_values *outputs,
2934 unsigned noutput)
2935 {
2936 struct si_shader *shader = ctx->shader;
2937 struct ac_export_args pos_args[4] = {};
2938 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2939 unsigned pos_idx;
2940 int i;
2941
2942 /* Build position exports. */
2943 for (i = 0; i < noutput; i++) {
2944 switch (outputs[i].semantic_name) {
2945 case TGSI_SEMANTIC_POSITION:
2946 si_llvm_init_export_args(ctx, outputs[i].values,
2947 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2948 break;
2949 case TGSI_SEMANTIC_PSIZE:
2950 psize_value = outputs[i].values[0];
2951 break;
2952 case TGSI_SEMANTIC_LAYER:
2953 layer_value = outputs[i].values[0];
2954 break;
2955 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2956 viewport_index_value = outputs[i].values[0];
2957 break;
2958 case TGSI_SEMANTIC_EDGEFLAG:
2959 edgeflag_value = outputs[i].values[0];
2960 break;
2961 case TGSI_SEMANTIC_CLIPDIST:
2962 if (!shader->key.opt.clip_disable) {
2963 unsigned index = 2 + outputs[i].semantic_index;
2964 si_llvm_init_export_args(ctx, outputs[i].values,
2965 V_008DFC_SQ_EXP_POS + index,
2966 &pos_args[index]);
2967 }
2968 break;
2969 case TGSI_SEMANTIC_CLIPVERTEX:
2970 if (!shader->key.opt.clip_disable) {
2971 si_llvm_emit_clipvertex(ctx, pos_args,
2972 outputs[i].values);
2973 }
2974 break;
2975 }
2976 }
2977
2978 /* We need to add the position output manually if it's missing. */
2979 if (!pos_args[0].out[0]) {
2980 pos_args[0].enabled_channels = 0xf; /* writemask */
2981 pos_args[0].valid_mask = 0; /* EXEC mask */
2982 pos_args[0].done = 0; /* last export? */
2983 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2984 pos_args[0].compr = 0; /* COMPR flag */
2985 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2986 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2987 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2988 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2989 }
2990
2991 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2992 if (shader->selector->info.writes_psize ||
2993 shader->selector->info.writes_edgeflag ||
2994 shader->selector->info.writes_viewport_index ||
2995 shader->selector->info.writes_layer) {
2996 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2997 (shader->selector->info.writes_edgeflag << 1) |
2998 (shader->selector->info.writes_layer << 2);
2999
3000 pos_args[1].valid_mask = 0; /* EXEC mask */
3001 pos_args[1].done = 0; /* last export? */
3002 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
3003 pos_args[1].compr = 0; /* COMPR flag */
3004 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
3005 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
3006 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
3007 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
3008
3009 if (shader->selector->info.writes_psize)
3010 pos_args[1].out[0] = psize_value;
3011
3012 if (shader->selector->info.writes_edgeflag) {
3013 /* The output is a float, but the hw expects an integer
3014 * with the first bit containing the edge flag. */
3015 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
3016 edgeflag_value,
3017 ctx->i32, "");
3018 edgeflag_value = ac_build_umin(&ctx->ac,
3019 edgeflag_value,
3020 ctx->i32_1);
3021
3022 /* The LLVM intrinsic expects a float. */
3023 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3024 }
3025
3026 if (ctx->screen->info.chip_class >= GFX9) {
3027 /* GFX9 has the layer in out.z[10:0] and the viewport
3028 * index in out.z[19:16].
3029 */
3030 if (shader->selector->info.writes_layer)
3031 pos_args[1].out[2] = layer_value;
3032
3033 if (shader->selector->info.writes_viewport_index) {
3034 LLVMValueRef v = viewport_index_value;
3035
3036 v = ac_to_integer(&ctx->ac, v);
3037 v = LLVMBuildShl(ctx->ac.builder, v,
3038 LLVMConstInt(ctx->i32, 16, 0), "");
3039 v = LLVMBuildOr(ctx->ac.builder, v,
3040 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3041 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3042 pos_args[1].enabled_channels |= 1 << 2;
3043 }
3044 } else {
3045 if (shader->selector->info.writes_layer)
3046 pos_args[1].out[2] = layer_value;
3047
3048 if (shader->selector->info.writes_viewport_index) {
3049 pos_args[1].out[3] = viewport_index_value;
3050 pos_args[1].enabled_channels |= 1 << 3;
3051 }
3052 }
3053 }
3054
3055 for (i = 0; i < 4; i++)
3056 if (pos_args[i].out[0])
3057 shader->info.nr_pos_exports++;
3058
3059 pos_idx = 0;
3060 for (i = 0; i < 4; i++) {
3061 if (!pos_args[i].out[0])
3062 continue;
3063
3064 /* Specify the target we are exporting */
3065 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3066
3067 if (pos_idx == shader->info.nr_pos_exports)
3068 /* Specify that this is the last export */
3069 pos_args[i].done = 1;
3070
3071 ac_build_export(&ctx->ac, &pos_args[i]);
3072 }
3073
3074 /* Build parameter exports. */
3075 si_build_param_exports(ctx, outputs, noutput);
3076 }
3077
3078 /**
3079 * Forward all outputs from the vertex shader to the TES. This is only used
3080 * for the fixed function TCS.
3081 */
3082 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3083 {
3084 struct si_shader_context *ctx = si_shader_context(bld_base);
3085 LLVMValueRef invocation_id, buffer, buffer_offset;
3086 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3087 uint64_t inputs;
3088
3089 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3090 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3091 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3092
3093 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3094 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3095 lds_vertex_stride, "");
3096 lds_base = get_tcs_in_current_patch_offset(ctx);
3097 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3098
3099 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3100 while (inputs) {
3101 unsigned i = u_bit_scan64(&inputs);
3102
3103 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3104 LLVMConstInt(ctx->i32, 4 * i, 0),
3105 "");
3106
3107 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3108 get_rel_patch_id(ctx),
3109 invocation_id,
3110 LLVMConstInt(ctx->i32, i, 0));
3111
3112 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3113 lds_ptr);
3114
3115 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3116 buffer_offset, 0, 1, 0, true, false);
3117 }
3118 }
3119
3120 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3121 LLVMValueRef rel_patch_id,
3122 LLVMValueRef invocation_id,
3123 LLVMValueRef tcs_out_current_patch_data_offset,
3124 LLVMValueRef invoc0_tf_outer[4],
3125 LLVMValueRef invoc0_tf_inner[2])
3126 {
3127 struct si_shader_context *ctx = si_shader_context(bld_base);
3128 struct si_shader *shader = ctx->shader;
3129 unsigned tess_inner_index, tess_outer_index;
3130 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3131 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3132 unsigned stride, outer_comps, inner_comps, i, offset;
3133 struct lp_build_if_state if_ctx, inner_if_ctx;
3134
3135 /* Add a barrier before loading tess factors from LDS. */
3136 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3137 si_llvm_emit_barrier(NULL, bld_base, NULL);
3138
3139 /* Do this only for invocation 0, because the tess levels are per-patch,
3140 * not per-vertex.
3141 *
3142 * This can't jump, because invocation 0 executes this. It should
3143 * at least mask out the loads and stores for other invocations.
3144 */
3145 lp_build_if(&if_ctx, &ctx->gallivm,
3146 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3147 invocation_id, ctx->i32_0, ""));
3148
3149 /* Determine the layout of one tess factor element in the buffer. */
3150 switch (shader->key.part.tcs.epilog.prim_mode) {
3151 case PIPE_PRIM_LINES:
3152 stride = 2; /* 2 dwords, 1 vec2 store */
3153 outer_comps = 2;
3154 inner_comps = 0;
3155 break;
3156 case PIPE_PRIM_TRIANGLES:
3157 stride = 4; /* 4 dwords, 1 vec4 store */
3158 outer_comps = 3;
3159 inner_comps = 1;
3160 break;
3161 case PIPE_PRIM_QUADS:
3162 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3163 outer_comps = 4;
3164 inner_comps = 2;
3165 break;
3166 default:
3167 assert(0);
3168 return;
3169 }
3170
3171 for (i = 0; i < 4; i++) {
3172 inner[i] = LLVMGetUndef(ctx->i32);
3173 outer[i] = LLVMGetUndef(ctx->i32);
3174 }
3175
3176 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3177 /* Tess factors are in VGPRs. */
3178 for (i = 0; i < outer_comps; i++)
3179 outer[i] = out[i] = invoc0_tf_outer[i];
3180 for (i = 0; i < inner_comps; i++)
3181 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3182 } else {
3183 /* Load tess_inner and tess_outer from LDS.
3184 * Any invocation can write them, so we can't get them from a temporary.
3185 */
3186 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3187 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3188
3189 lds_base = tcs_out_current_patch_data_offset;
3190 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3191 LLVMConstInt(ctx->i32,
3192 tess_inner_index * 4, 0), "");
3193 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3194 LLVMConstInt(ctx->i32,
3195 tess_outer_index * 4, 0), "");
3196
3197 for (i = 0; i < outer_comps; i++) {
3198 outer[i] = out[i] =
3199 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3200 }
3201 for (i = 0; i < inner_comps; i++) {
3202 inner[i] = out[outer_comps+i] =
3203 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3204 }
3205 }
3206
3207 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3208 /* For isolines, the hardware expects tess factors in the
3209 * reverse order from what GLSL / TGSI specify.
3210 */
3211 LLVMValueRef tmp = out[0];
3212 out[0] = out[1];
3213 out[1] = tmp;
3214 }
3215
3216 /* Convert the outputs to vectors for stores. */
3217 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3218 vec1 = NULL;
3219
3220 if (stride > 4)
3221 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3222
3223 /* Get the buffer. */
3224 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3225
3226 /* Get the offset. */
3227 tf_base = LLVMGetParam(ctx->main_fn,
3228 ctx->param_tcs_factor_offset);
3229 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3230 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3231
3232 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3233 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3234 rel_patch_id, ctx->i32_0, ""));
3235
3236 /* Store the dynamic HS control word. */
3237 offset = 0;
3238 if (ctx->screen->info.chip_class <= VI) {
3239 ac_build_buffer_store_dword(&ctx->ac, buffer,
3240 LLVMConstInt(ctx->i32, 0x80000000, 0),
3241 1, ctx->i32_0, tf_base,
3242 offset, 1, 0, true, false);
3243 offset += 4;
3244 }
3245
3246 lp_build_endif(&inner_if_ctx);
3247
3248 /* Store the tessellation factors. */
3249 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3250 MIN2(stride, 4), byteoffset, tf_base,
3251 offset, 1, 0, true, false);
3252 offset += 16;
3253 if (vec1)
3254 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3255 stride - 4, byteoffset, tf_base,
3256 offset, 1, 0, true, false);
3257
3258 /* Store the tess factors into the offchip buffer if TES reads them. */
3259 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3260 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3261 LLVMValueRef tf_inner_offset;
3262 unsigned param_outer, param_inner;
3263
3264 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3265 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3266
3267 param_outer = si_shader_io_get_unique_index_patch(
3268 TGSI_SEMANTIC_TESSOUTER, 0);
3269 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3270 LLVMConstInt(ctx->i32, param_outer, 0));
3271
3272 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3273 util_next_power_of_two(outer_comps));
3274
3275 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3276 outer_comps, tf_outer_offset,
3277 base, 0, 1, 0, true, false);
3278 if (inner_comps) {
3279 param_inner = si_shader_io_get_unique_index_patch(
3280 TGSI_SEMANTIC_TESSINNER, 0);
3281 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3282 LLVMConstInt(ctx->i32, param_inner, 0));
3283
3284 inner_vec = inner_comps == 1 ? inner[0] :
3285 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3286 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3287 inner_comps, tf_inner_offset,
3288 base, 0, 1, 0, true, false);
3289 }
3290 }
3291
3292 lp_build_endif(&if_ctx);
3293 }
3294
3295 static LLVMValueRef
3296 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3297 unsigned param, unsigned return_index)
3298 {
3299 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3300 LLVMGetParam(ctx->main_fn, param),
3301 return_index, "");
3302 }
3303
3304 static LLVMValueRef
3305 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3306 unsigned param, unsigned return_index)
3307 {
3308 LLVMBuilderRef builder = ctx->ac.builder;
3309 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3310
3311 return LLVMBuildInsertValue(builder, ret,
3312 ac_to_float(&ctx->ac, p),
3313 return_index, "");
3314 }
3315
3316 static LLVMValueRef
3317 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3318 unsigned param, unsigned return_index)
3319 {
3320 LLVMBuilderRef builder = ctx->ac.builder;
3321 LLVMValueRef ptr, lo, hi;
3322
3323 if (HAVE_32BIT_POINTERS) {
3324 ptr = LLVMGetParam(ctx->main_fn, param);
3325 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3326 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3327 }
3328
3329 ptr = LLVMGetParam(ctx->main_fn, param);
3330 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3331 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3332 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3333 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3334 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3335 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3336 }
3337
3338 /* This only writes the tessellation factor levels. */
3339 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3340 unsigned max_outputs,
3341 LLVMValueRef *addrs)
3342 {
3343 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3344 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3345 LLVMBuilderRef builder = ctx->ac.builder;
3346 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3347
3348 si_copy_tcs_inputs(bld_base);
3349
3350 rel_patch_id = get_rel_patch_id(ctx);
3351 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3352 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3353
3354 if (ctx->screen->info.chip_class >= GFX9) {
3355 LLVMBasicBlockRef blocks[2] = {
3356 LLVMGetInsertBlock(builder),
3357 ctx->merged_wrap_if_state.entry_block
3358 };
3359 LLVMValueRef values[2];
3360
3361 lp_build_endif(&ctx->merged_wrap_if_state);
3362
3363 values[0] = rel_patch_id;
3364 values[1] = LLVMGetUndef(ctx->i32);
3365 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3366
3367 values[0] = tf_lds_offset;
3368 values[1] = LLVMGetUndef(ctx->i32);
3369 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3370
3371 values[0] = invocation_id;
3372 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3373 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3374 }
3375
3376 /* Return epilog parameters from this function. */
3377 LLVMValueRef ret = ctx->return_value;
3378 unsigned vgpr;
3379
3380 if (ctx->screen->info.chip_class >= GFX9) {
3381 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3382 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3383 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3384 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3385 /* Tess offchip and tess factor offsets are at the beginning. */
3386 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3387 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3388 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3389 } else {
3390 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3391 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3392 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3393 GFX6_SGPR_TCS_OUT_LAYOUT);
3394 /* Tess offchip and tess factor offsets are after user SGPRs. */
3395 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3396 GFX6_TCS_NUM_USER_SGPR);
3397 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3398 GFX6_TCS_NUM_USER_SGPR + 1);
3399 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3400 }
3401
3402 /* VGPRs */
3403 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3404 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3405 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3406
3407 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3408 * the invocation_id output does not alias the tcs_rel_ids input,
3409 * which saves a V_MOV on gfx9.
3410 */
3411 vgpr += 2;
3412
3413 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3414 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3415
3416 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3417 vgpr++; /* skip the tess factor LDS offset */
3418 for (unsigned i = 0; i < 6; i++) {
3419 LLVMValueRef value =
3420 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3421 value = ac_to_float(&ctx->ac, value);
3422 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3423 }
3424 } else {
3425 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3426 }
3427 ctx->return_value = ret;
3428 }
3429
3430 /* Pass TCS inputs from LS to TCS on GFX9. */
3431 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3432 {
3433 LLVMValueRef ret = ctx->return_value;
3434
3435 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3436 if (HAVE_32BIT_POINTERS)
3437 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3438 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3439 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3440 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3441 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3442
3443 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3444 8 + SI_SGPR_RW_BUFFERS);
3445 ret = si_insert_input_ptr(ctx, ret,
3446 ctx->param_bindless_samplers_and_images,
3447 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3448
3449 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3450 8 + SI_SGPR_VS_STATE_BITS);
3451
3452 #if !HAVE_32BIT_POINTERS
3453 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3454 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3455 #endif
3456
3457 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3458 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3459 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3460 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3461 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3462 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3463
3464 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3465 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3466 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3467 vgpr++, "");
3468 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3469 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3470 vgpr++, "");
3471 ctx->return_value = ret;
3472 }
3473
3474 /* Pass GS inputs from ES to GS on GFX9. */
3475 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3476 {
3477 LLVMValueRef ret = ctx->return_value;
3478
3479 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3480 if (HAVE_32BIT_POINTERS)
3481 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3482 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3483 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3484 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3485
3486 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3487 8 + SI_SGPR_RW_BUFFERS);
3488 ret = si_insert_input_ptr(ctx, ret,
3489 ctx->param_bindless_samplers_and_images,
3490 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3491
3492 #if !HAVE_32BIT_POINTERS
3493 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3494 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3495 #endif
3496
3497 unsigned vgpr;
3498 if (ctx->type == PIPE_SHADER_VERTEX)
3499 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3500 else
3501 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3502
3503 for (unsigned i = 0; i < 5; i++) {
3504 unsigned param = ctx->param_gs_vtx01_offset + i;
3505 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3506 }
3507 ctx->return_value = ret;
3508 }
3509
3510 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3511 unsigned max_outputs,
3512 LLVMValueRef *addrs)
3513 {
3514 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3515 struct si_shader *shader = ctx->shader;
3516 struct tgsi_shader_info *info = &shader->selector->info;
3517 unsigned i, chan;
3518 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3519 ctx->param_rel_auto_id);
3520 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3521 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3522 vertex_dw_stride, "");
3523
3524 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3525 * its inputs from it. */
3526 for (i = 0; i < info->num_outputs; i++) {
3527 unsigned name = info->output_semantic_name[i];
3528 unsigned index = info->output_semantic_index[i];
3529
3530 /* The ARB_shader_viewport_layer_array spec contains the
3531 * following issue:
3532 *
3533 * 2) What happens if gl_ViewportIndex or gl_Layer is
3534 * written in the vertex shader and a geometry shader is
3535 * present?
3536 *
3537 * RESOLVED: The value written by the last vertex processing
3538 * stage is used. If the last vertex processing stage
3539 * (vertex, tessellation evaluation or geometry) does not
3540 * statically assign to gl_ViewportIndex or gl_Layer, index
3541 * or layer zero is assumed.
3542 *
3543 * So writes to those outputs in VS-as-LS are simply ignored.
3544 */
3545 if (name == TGSI_SEMANTIC_LAYER ||
3546 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3547 continue;
3548
3549 int param = si_shader_io_get_unique_index(name, index);
3550 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3551 LLVMConstInt(ctx->i32, param * 4, 0), "");
3552
3553 for (chan = 0; chan < 4; chan++) {
3554 if (!(info->output_usagemask[i] & (1 << chan)))
3555 continue;
3556
3557 lds_store(ctx, chan, dw_addr,
3558 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3559 }
3560 }
3561
3562 if (ctx->screen->info.chip_class >= GFX9)
3563 si_set_ls_return_value_for_tcs(ctx);
3564 }
3565
3566 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3567 unsigned max_outputs,
3568 LLVMValueRef *addrs)
3569 {
3570 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3571 struct si_shader *es = ctx->shader;
3572 struct tgsi_shader_info *info = &es->selector->info;
3573 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3574 ctx->param_es2gs_offset);
3575 LLVMValueRef lds_base = NULL;
3576 unsigned chan;
3577 int i;
3578
3579 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3580 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3581 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3582 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3583 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3584 LLVMBuildMul(ctx->ac.builder, wave_idx,
3585 LLVMConstInt(ctx->i32, 64, false), ""), "");
3586 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3587 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3588 }
3589
3590 for (i = 0; i < info->num_outputs; i++) {
3591 int param;
3592
3593 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3594 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3595 continue;
3596
3597 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3598 info->output_semantic_index[i]);
3599
3600 for (chan = 0; chan < 4; chan++) {
3601 if (!(info->output_usagemask[i] & (1 << chan)))
3602 continue;
3603
3604 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3605 out_val = ac_to_integer(&ctx->ac, out_val);
3606
3607 /* GFX9 has the ESGS ring in LDS. */
3608 if (ctx->screen->info.chip_class >= GFX9) {
3609 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3610 continue;
3611 }
3612
3613 ac_build_buffer_store_dword(&ctx->ac,
3614 ctx->esgs_ring,
3615 out_val, 1, NULL, soffset,
3616 (4 * param + chan) * 4,
3617 1, 1, true, true);
3618 }
3619 }
3620
3621 if (ctx->screen->info.chip_class >= GFX9)
3622 si_set_es_return_value_for_gs(ctx);
3623 }
3624
3625 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3626 {
3627 if (ctx->screen->info.chip_class >= GFX9)
3628 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3629 else
3630 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3631 }
3632
3633 static void emit_gs_epilogue(struct si_shader_context *ctx)
3634 {
3635 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3636 si_get_gs_wave_id(ctx));
3637
3638 if (ctx->screen->info.chip_class >= GFX9)
3639 lp_build_endif(&ctx->merged_wrap_if_state);
3640 }
3641
3642 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3643 unsigned max_outputs,
3644 LLVMValueRef *addrs)
3645 {
3646 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3647 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3648
3649 assert(info->num_outputs <= max_outputs);
3650
3651 emit_gs_epilogue(ctx);
3652 }
3653
3654 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3655 {
3656 struct si_shader_context *ctx = si_shader_context(bld_base);
3657 emit_gs_epilogue(ctx);
3658 }
3659
3660 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3661 unsigned max_outputs,
3662 LLVMValueRef *addrs)
3663 {
3664 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3665 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3666 struct si_shader_output_values *outputs = NULL;
3667 int i,j;
3668
3669 assert(!ctx->shader->is_gs_copy_shader);
3670 assert(info->num_outputs <= max_outputs);
3671
3672 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3673
3674 /* Vertex color clamping.
3675 *
3676 * This uses a state constant loaded in a user data SGPR and
3677 * an IF statement is added that clamps all colors if the constant
3678 * is true.
3679 */
3680 if (ctx->type == PIPE_SHADER_VERTEX) {
3681 struct lp_build_if_state if_ctx;
3682 LLVMValueRef cond = NULL;
3683 LLVMValueRef addr, val;
3684
3685 for (i = 0; i < info->num_outputs; i++) {
3686 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3687 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3688 continue;
3689
3690 /* We've found a color. */
3691 if (!cond) {
3692 /* The state is in the first bit of the user SGPR. */
3693 cond = LLVMGetParam(ctx->main_fn,
3694 ctx->param_vs_state_bits);
3695 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3696 ctx->i1, "");
3697 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3698 }
3699
3700 for (j = 0; j < 4; j++) {
3701 addr = addrs[4 * i + j];
3702 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3703 val = ac_build_clamp(&ctx->ac, val);
3704 LLVMBuildStore(ctx->ac.builder, val, addr);
3705 }
3706 }
3707
3708 if (cond)
3709 lp_build_endif(&if_ctx);
3710 }
3711
3712 for (i = 0; i < info->num_outputs; i++) {
3713 outputs[i].semantic_name = info->output_semantic_name[i];
3714 outputs[i].semantic_index = info->output_semantic_index[i];
3715
3716 for (j = 0; j < 4; j++) {
3717 outputs[i].values[j] =
3718 LLVMBuildLoad(ctx->ac.builder,
3719 addrs[4 * i + j],
3720 "");
3721 outputs[i].vertex_stream[j] =
3722 (info->output_streams[i] >> (2 * j)) & 3;
3723 }
3724 }
3725
3726 if (ctx->shader->selector->so.num_outputs)
3727 si_llvm_emit_streamout(ctx, outputs, i, 0);
3728
3729 /* Export PrimitiveID. */
3730 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3731 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3732 outputs[i].semantic_index = 0;
3733 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3734 for (j = 1; j < 4; j++)
3735 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3736
3737 memset(outputs[i].vertex_stream, 0,
3738 sizeof(outputs[i].vertex_stream));
3739 i++;
3740 }
3741
3742 si_llvm_export_vs(ctx, outputs, i);
3743 FREE(outputs);
3744 }
3745
3746 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3747 {
3748 struct si_shader_context *ctx = si_shader_context(bld_base);
3749
3750 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3751 &ctx->outputs[0][0]);
3752 }
3753
3754 struct si_ps_exports {
3755 unsigned num;
3756 struct ac_export_args args[10];
3757 };
3758
3759 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3760 LLVMValueRef depth, LLVMValueRef stencil,
3761 LLVMValueRef samplemask, struct si_ps_exports *exp)
3762 {
3763 struct si_shader_context *ctx = si_shader_context(bld_base);
3764 struct ac_export_args args;
3765
3766 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3767
3768 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3769 }
3770
3771 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3772 LLVMValueRef *color, unsigned index,
3773 unsigned samplemask_param,
3774 bool is_last, struct si_ps_exports *exp)
3775 {
3776 struct si_shader_context *ctx = si_shader_context(bld_base);
3777 int i;
3778
3779 /* Clamp color */
3780 if (ctx->shader->key.part.ps.epilog.clamp_color)
3781 for (i = 0; i < 4; i++)
3782 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3783
3784 /* Alpha to one */
3785 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3786 color[3] = ctx->ac.f32_1;
3787
3788 /* Alpha test */
3789 if (index == 0 &&
3790 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3791 si_alpha_test(bld_base, color[3]);
3792
3793 /* Line & polygon smoothing */
3794 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3795 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3796 samplemask_param);
3797
3798 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3799 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3800 struct ac_export_args args[8];
3801 int c, last = -1;
3802
3803 /* Get the export arguments, also find out what the last one is. */
3804 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3805 si_llvm_init_export_args(ctx, color,
3806 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3807 if (args[c].enabled_channels)
3808 last = c;
3809 }
3810
3811 /* Emit all exports. */
3812 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3813 if (is_last && last == c) {
3814 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3815 args[c].done = 1; /* DONE bit */
3816 } else if (!args[c].enabled_channels)
3817 continue; /* unnecessary NULL export */
3818
3819 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3820 }
3821 } else {
3822 struct ac_export_args args;
3823
3824 /* Export */
3825 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3826 &args);
3827 if (is_last) {
3828 args.valid_mask = 1; /* whether the EXEC mask is valid */
3829 args.done = 1; /* DONE bit */
3830 } else if (!args.enabled_channels)
3831 return; /* unnecessary NULL export */
3832
3833 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3834 }
3835 }
3836
3837 static void si_emit_ps_exports(struct si_shader_context *ctx,
3838 struct si_ps_exports *exp)
3839 {
3840 for (unsigned i = 0; i < exp->num; i++)
3841 ac_build_export(&ctx->ac, &exp->args[i]);
3842 }
3843
3844 /**
3845 * Return PS outputs in this order:
3846 *
3847 * v[0:3] = color0.xyzw
3848 * v[4:7] = color1.xyzw
3849 * ...
3850 * vN+0 = Depth
3851 * vN+1 = Stencil
3852 * vN+2 = SampleMask
3853 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3854 *
3855 * The alpha-ref SGPR is returned via its original location.
3856 */
3857 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3858 unsigned max_outputs,
3859 LLVMValueRef *addrs)
3860 {
3861 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3862 struct si_shader *shader = ctx->shader;
3863 struct tgsi_shader_info *info = &shader->selector->info;
3864 LLVMBuilderRef builder = ctx->ac.builder;
3865 unsigned i, j, first_vgpr, vgpr;
3866
3867 LLVMValueRef color[8][4] = {};
3868 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3869 LLVMValueRef ret;
3870
3871 if (ctx->postponed_kill)
3872 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3873
3874 /* Read the output values. */
3875 for (i = 0; i < info->num_outputs; i++) {
3876 unsigned semantic_name = info->output_semantic_name[i];
3877 unsigned semantic_index = info->output_semantic_index[i];
3878
3879 switch (semantic_name) {
3880 case TGSI_SEMANTIC_COLOR:
3881 assert(semantic_index < 8);
3882 for (j = 0; j < 4; j++) {
3883 LLVMValueRef ptr = addrs[4 * i + j];
3884 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3885 color[semantic_index][j] = result;
3886 }
3887 break;
3888 case TGSI_SEMANTIC_POSITION:
3889 depth = LLVMBuildLoad(builder,
3890 addrs[4 * i + 2], "");
3891 break;
3892 case TGSI_SEMANTIC_STENCIL:
3893 stencil = LLVMBuildLoad(builder,
3894 addrs[4 * i + 1], "");
3895 break;
3896 case TGSI_SEMANTIC_SAMPLEMASK:
3897 samplemask = LLVMBuildLoad(builder,
3898 addrs[4 * i + 0], "");
3899 break;
3900 default:
3901 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3902 semantic_name);
3903 }
3904 }
3905
3906 /* Fill the return structure. */
3907 ret = ctx->return_value;
3908
3909 /* Set SGPRs. */
3910 ret = LLVMBuildInsertValue(builder, ret,
3911 ac_to_integer(&ctx->ac,
3912 LLVMGetParam(ctx->main_fn,
3913 SI_PARAM_ALPHA_REF)),
3914 SI_SGPR_ALPHA_REF, "");
3915
3916 /* Set VGPRs */
3917 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3918 for (i = 0; i < ARRAY_SIZE(color); i++) {
3919 if (!color[i][0])
3920 continue;
3921
3922 for (j = 0; j < 4; j++)
3923 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3924 }
3925 if (depth)
3926 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3927 if (stencil)
3928 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3929 if (samplemask)
3930 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3931
3932 /* Add the input sample mask for smoothing at the end. */
3933 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3934 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3935 ret = LLVMBuildInsertValue(builder, ret,
3936 LLVMGetParam(ctx->main_fn,
3937 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3938
3939 ctx->return_value = ret;
3940 }
3941
3942 static void membar_emit(
3943 const struct lp_build_tgsi_action *action,
3944 struct lp_build_tgsi_context *bld_base,
3945 struct lp_build_emit_data *emit_data)
3946 {
3947 struct si_shader_context *ctx = si_shader_context(bld_base);
3948 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3949 unsigned flags = LLVMConstIntGetZExtValue(src0);
3950 unsigned waitcnt = NOOP_WAITCNT;
3951
3952 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3953 waitcnt &= VM_CNT & LGKM_CNT;
3954
3955 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3956 TGSI_MEMBAR_SHADER_BUFFER |
3957 TGSI_MEMBAR_SHADER_IMAGE))
3958 waitcnt &= VM_CNT;
3959
3960 if (flags & TGSI_MEMBAR_SHARED)
3961 waitcnt &= LGKM_CNT;
3962
3963 if (waitcnt != NOOP_WAITCNT)
3964 ac_build_waitcnt(&ctx->ac, waitcnt);
3965 }
3966
3967 static void clock_emit(
3968 const struct lp_build_tgsi_action *action,
3969 struct lp_build_tgsi_context *bld_base,
3970 struct lp_build_emit_data *emit_data)
3971 {
3972 struct si_shader_context *ctx = si_shader_context(bld_base);
3973 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3974
3975 emit_data->output[0] =
3976 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3977 emit_data->output[1] =
3978 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3979 }
3980
3981 static void si_llvm_emit_ddxy(
3982 const struct lp_build_tgsi_action *action,
3983 struct lp_build_tgsi_context *bld_base,
3984 struct lp_build_emit_data *emit_data)
3985 {
3986 struct si_shader_context *ctx = si_shader_context(bld_base);
3987 unsigned opcode = emit_data->info->opcode;
3988 LLVMValueRef val;
3989 int idx;
3990 unsigned mask;
3991
3992 if (opcode == TGSI_OPCODE_DDX_FINE)
3993 mask = AC_TID_MASK_LEFT;
3994 else if (opcode == TGSI_OPCODE_DDY_FINE)
3995 mask = AC_TID_MASK_TOP;
3996 else
3997 mask = AC_TID_MASK_TOP_LEFT;
3998
3999 /* for DDX we want to next X pixel, DDY next Y pixel. */
4000 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4001
4002 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
4003 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
4004 emit_data->output[emit_data->chan] = val;
4005 }
4006
4007 /*
4008 * this takes an I,J coordinate pair,
4009 * and works out the X and Y derivatives.
4010 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4011 */
4012 static LLVMValueRef si_llvm_emit_ddxy_interp(
4013 struct lp_build_tgsi_context *bld_base,
4014 LLVMValueRef interp_ij)
4015 {
4016 struct si_shader_context *ctx = si_shader_context(bld_base);
4017 LLVMValueRef result[4], a;
4018 unsigned i;
4019
4020 for (i = 0; i < 2; i++) {
4021 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
4022 LLVMConstInt(ctx->i32, i, 0), "");
4023 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4024 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4025 }
4026
4027 return lp_build_gather_values(&ctx->gallivm, result, 4);
4028 }
4029
4030 static void interp_fetch_args(
4031 struct lp_build_tgsi_context *bld_base,
4032 struct lp_build_emit_data *emit_data)
4033 {
4034 struct si_shader_context *ctx = si_shader_context(bld_base);
4035 const struct tgsi_full_instruction *inst = emit_data->inst;
4036
4037 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4038 /* offset is in second src, first two channels */
4039 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4040 emit_data->inst, 1,
4041 TGSI_CHAN_X);
4042 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4043 emit_data->inst, 1,
4044 TGSI_CHAN_Y);
4045 emit_data->arg_count = 2;
4046 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4047 LLVMValueRef sample_position;
4048 LLVMValueRef sample_id;
4049 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4050
4051 /* fetch sample ID, then fetch its sample position,
4052 * and place into first two channels.
4053 */
4054 sample_id = lp_build_emit_fetch(bld_base,
4055 emit_data->inst, 1, TGSI_CHAN_X);
4056 sample_id = ac_to_integer(&ctx->ac, sample_id);
4057
4058 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4059 * Language 4.50 spec says about interpolateAtSample:
4060 *
4061 * "Returns the value of the input interpolant variable at
4062 * the location of sample number sample. If multisample
4063 * buffers are not available, the input variable will be
4064 * evaluated at the center of the pixel. If sample sample
4065 * does not exist, the position used to interpolate the
4066 * input variable is undefined."
4067 *
4068 * This means that sample_id values outside of the valid are
4069 * in fact valid input, and the usual mechanism for loading the
4070 * sample position doesn't work.
4071 */
4072 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4073 LLVMValueRef center[4] = {
4074 LLVMConstReal(ctx->f32, 0.5),
4075 LLVMConstReal(ctx->f32, 0.5),
4076 ctx->ac.f32_0,
4077 ctx->ac.f32_0,
4078 };
4079
4080 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4081 } else {
4082 sample_position = load_sample_position(&ctx->abi, sample_id);
4083 }
4084
4085 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4086 sample_position,
4087 ctx->i32_0, "");
4088
4089 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4090 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4091 sample_position,
4092 ctx->i32_1, "");
4093 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4094 emit_data->arg_count = 2;
4095 }
4096 }
4097
4098 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4099 struct lp_build_tgsi_context *bld_base,
4100 struct lp_build_emit_data *emit_data)
4101 {
4102 struct si_shader_context *ctx = si_shader_context(bld_base);
4103 struct si_shader *shader = ctx->shader;
4104 const struct tgsi_shader_info *info = &shader->selector->info;
4105 LLVMValueRef interp_param;
4106 const struct tgsi_full_instruction *inst = emit_data->inst;
4107 const struct tgsi_full_src_register *input = &inst->Src[0];
4108 int input_base, input_array_size;
4109 int chan;
4110 int i;
4111 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4112 LLVMValueRef array_idx;
4113 int interp_param_idx;
4114 unsigned interp;
4115 unsigned location;
4116
4117 assert(input->Register.File == TGSI_FILE_INPUT);
4118
4119 if (input->Register.Indirect) {
4120 unsigned array_id = input->Indirect.ArrayID;
4121
4122 if (array_id) {
4123 input_base = info->input_array_first[array_id];
4124 input_array_size = info->input_array_last[array_id] - input_base + 1;
4125 } else {
4126 input_base = inst->Src[0].Register.Index;
4127 input_array_size = info->num_inputs - input_base;
4128 }
4129
4130 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4131 1, input->Register.Index - input_base);
4132 } else {
4133 input_base = inst->Src[0].Register.Index;
4134 input_array_size = 1;
4135 array_idx = ctx->i32_0;
4136 }
4137
4138 interp = shader->selector->info.input_interpolate[input_base];
4139
4140 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4141 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4142 location = TGSI_INTERPOLATE_LOC_CENTER;
4143 else
4144 location = TGSI_INTERPOLATE_LOC_CENTROID;
4145
4146 interp_param_idx = lookup_interp_param_index(interp, location);
4147 if (interp_param_idx == -1)
4148 return;
4149 else if (interp_param_idx)
4150 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4151 else
4152 interp_param = NULL;
4153
4154 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4155 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4156 LLVMValueRef ij_out[2];
4157 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4158
4159 /*
4160 * take the I then J parameters, and the DDX/Y for it, and
4161 * calculate the IJ inputs for the interpolator.
4162 * temp1 = ddx * offset/sample.x + I;
4163 * interp_param.I = ddy * offset/sample.y + temp1;
4164 * temp1 = ddx * offset/sample.x + J;
4165 * interp_param.J = ddy * offset/sample.y + temp1;
4166 */
4167 for (i = 0; i < 2; i++) {
4168 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4169 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4170 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4171 ddxy_out, ix_ll, "");
4172 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4173 ddxy_out, iy_ll, "");
4174 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4175 interp_param, ix_ll, "");
4176 LLVMValueRef temp1, temp2;
4177
4178 interp_el = ac_to_float(&ctx->ac, interp_el);
4179
4180 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4181
4182 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4183
4184 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4185
4186 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4187 }
4188 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4189 }
4190
4191 if (interp_param)
4192 interp_param = ac_to_float(&ctx->ac, interp_param);
4193
4194 for (chan = 0; chan < 4; chan++) {
4195 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4196 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4197
4198 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4199 LLVMValueRef v, i = NULL, j = NULL;
4200
4201 if (interp_param) {
4202 i = LLVMBuildExtractElement(
4203 ctx->ac.builder, interp_param, ctx->i32_0, "");
4204 j = LLVMBuildExtractElement(
4205 ctx->ac.builder, interp_param, ctx->i32_1, "");
4206 }
4207 v = si_build_fs_interp(ctx, input_base + idx, schan,
4208 prim_mask, i, j);
4209
4210 gather = LLVMBuildInsertElement(ctx->ac.builder,
4211 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4212 }
4213
4214 emit_data->output[chan] = LLVMBuildExtractElement(
4215 ctx->ac.builder, gather, array_idx, "");
4216 }
4217 }
4218
4219 static void vote_all_emit(
4220 const struct lp_build_tgsi_action *action,
4221 struct lp_build_tgsi_context *bld_base,
4222 struct lp_build_emit_data *emit_data)
4223 {
4224 struct si_shader_context *ctx = si_shader_context(bld_base);
4225
4226 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4227 emit_data->output[emit_data->chan] =
4228 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4229 }
4230
4231 static void vote_any_emit(
4232 const struct lp_build_tgsi_action *action,
4233 struct lp_build_tgsi_context *bld_base,
4234 struct lp_build_emit_data *emit_data)
4235 {
4236 struct si_shader_context *ctx = si_shader_context(bld_base);
4237
4238 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4239 emit_data->output[emit_data->chan] =
4240 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4241 }
4242
4243 static void vote_eq_emit(
4244 const struct lp_build_tgsi_action *action,
4245 struct lp_build_tgsi_context *bld_base,
4246 struct lp_build_emit_data *emit_data)
4247 {
4248 struct si_shader_context *ctx = si_shader_context(bld_base);
4249
4250 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4251 emit_data->output[emit_data->chan] =
4252 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4253 }
4254
4255 static void ballot_emit(
4256 const struct lp_build_tgsi_action *action,
4257 struct lp_build_tgsi_context *bld_base,
4258 struct lp_build_emit_data *emit_data)
4259 {
4260 struct si_shader_context *ctx = si_shader_context(bld_base);
4261 LLVMBuilderRef builder = ctx->ac.builder;
4262 LLVMValueRef tmp;
4263
4264 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4265 tmp = ac_build_ballot(&ctx->ac, tmp);
4266 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4267
4268 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4269 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4270 }
4271
4272 static void read_invoc_fetch_args(
4273 struct lp_build_tgsi_context *bld_base,
4274 struct lp_build_emit_data *emit_data)
4275 {
4276 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4277 0, emit_data->src_chan);
4278
4279 /* Always read the source invocation (= lane) from the X channel. */
4280 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4281 1, TGSI_CHAN_X);
4282 emit_data->arg_count = 2;
4283 }
4284
4285 static void read_lane_emit(
4286 const struct lp_build_tgsi_action *action,
4287 struct lp_build_tgsi_context *bld_base,
4288 struct lp_build_emit_data *emit_data)
4289 {
4290 struct si_shader_context *ctx = si_shader_context(bld_base);
4291
4292 /* We currently have no other way to prevent LLVM from lifting the icmp
4293 * calls to a dominating basic block.
4294 */
4295 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4296
4297 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4298 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4299
4300 emit_data->output[emit_data->chan] =
4301 ac_build_intrinsic(&ctx->ac, action->intr_name,
4302 ctx->i32, emit_data->args, emit_data->arg_count,
4303 AC_FUNC_ATTR_READNONE |
4304 AC_FUNC_ATTR_CONVERGENT);
4305 }
4306
4307 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4308 struct lp_build_emit_data *emit_data)
4309 {
4310 struct si_shader_context *ctx = si_shader_context(bld_base);
4311 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4312 LLVMValueRef imm;
4313 unsigned stream;
4314
4315 assert(src0.File == TGSI_FILE_IMMEDIATE);
4316
4317 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4318 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4319 return stream;
4320 }
4321
4322 /* Emit one vertex from the geometry shader */
4323 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4324 unsigned stream,
4325 LLVMValueRef *addrs)
4326 {
4327 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4328 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4329 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4330 struct si_shader *shader = ctx->shader;
4331 struct lp_build_if_state if_state;
4332 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4333 ctx->param_gs2vs_offset);
4334 LLVMValueRef gs_next_vertex;
4335 LLVMValueRef can_emit;
4336 unsigned chan, offset;
4337 int i;
4338
4339 /* Write vertex attribute values to GSVS ring */
4340 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4341 ctx->gs_next_vertex[stream],
4342 "");
4343
4344 /* If this thread has already emitted the declared maximum number of
4345 * vertices, skip the write: excessive vertex emissions are not
4346 * supposed to have any effect.
4347 *
4348 * If the shader has no writes to memory, kill it instead. This skips
4349 * further memory loads and may allow LLVM to skip to the end
4350 * altogether.
4351 */
4352 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4353 LLVMConstInt(ctx->i32,
4354 shader->selector->gs_max_out_vertices, 0), "");
4355
4356 bool use_kill = !info->writes_memory;
4357 if (use_kill) {
4358 ac_build_kill_if_false(&ctx->ac, can_emit);
4359 } else {
4360 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4361 }
4362
4363 offset = 0;
4364 for (i = 0; i < info->num_outputs; i++) {
4365 for (chan = 0; chan < 4; chan++) {
4366 if (!(info->output_usagemask[i] & (1 << chan)) ||
4367 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4368 continue;
4369
4370 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4371 LLVMValueRef voffset =
4372 LLVMConstInt(ctx->i32, offset *
4373 shader->selector->gs_max_out_vertices, 0);
4374 offset++;
4375
4376 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4377 voffset = lp_build_mul_imm(uint, voffset, 4);
4378
4379 out_val = ac_to_integer(&ctx->ac, out_val);
4380
4381 ac_build_buffer_store_dword(&ctx->ac,
4382 ctx->gsvs_ring[stream],
4383 out_val, 1,
4384 voffset, soffset, 0,
4385 1, 1, true, true);
4386 }
4387 }
4388
4389 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4390 ctx->i32_1);
4391
4392 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4393
4394 /* Signal vertex emission */
4395 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4396 si_get_gs_wave_id(ctx));
4397 if (!use_kill)
4398 lp_build_endif(&if_state);
4399 }
4400
4401 /* Emit one vertex from the geometry shader */
4402 static void si_tgsi_emit_vertex(
4403 const struct lp_build_tgsi_action *action,
4404 struct lp_build_tgsi_context *bld_base,
4405 struct lp_build_emit_data *emit_data)
4406 {
4407 struct si_shader_context *ctx = si_shader_context(bld_base);
4408 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4409
4410 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4411 }
4412
4413 /* Cut one primitive from the geometry shader */
4414 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4415 unsigned stream)
4416 {
4417 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4418
4419 /* Signal primitive cut */
4420 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4421 si_get_gs_wave_id(ctx));
4422 }
4423
4424 /* Cut one primitive from the geometry shader */
4425 static void si_tgsi_emit_primitive(
4426 const struct lp_build_tgsi_action *action,
4427 struct lp_build_tgsi_context *bld_base,
4428 struct lp_build_emit_data *emit_data)
4429 {
4430 struct si_shader_context *ctx = si_shader_context(bld_base);
4431
4432 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4433 }
4434
4435 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4436 struct lp_build_tgsi_context *bld_base,
4437 struct lp_build_emit_data *emit_data)
4438 {
4439 struct si_shader_context *ctx = si_shader_context(bld_base);
4440
4441 /* SI only (thanks to a hw bug workaround):
4442 * The real barrier instruction isn’t needed, because an entire patch
4443 * always fits into a single wave.
4444 */
4445 if (ctx->screen->info.chip_class == SI &&
4446 ctx->type == PIPE_SHADER_TESS_CTRL) {
4447 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4448 return;
4449 }
4450
4451 lp_build_intrinsic(ctx->ac.builder,
4452 "llvm.amdgcn.s.barrier",
4453 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4454 }
4455
4456 static const struct lp_build_tgsi_action interp_action = {
4457 .fetch_args = interp_fetch_args,
4458 .emit = build_interp_intrinsic,
4459 };
4460
4461 static void si_create_function(struct si_shader_context *ctx,
4462 const char *name,
4463 LLVMTypeRef *returns, unsigned num_returns,
4464 struct si_function_info *fninfo,
4465 unsigned max_workgroup_size)
4466 {
4467 int i;
4468
4469 si_llvm_create_func(ctx, name, returns, num_returns,
4470 fninfo->types, fninfo->num_params);
4471 ctx->return_value = LLVMGetUndef(ctx->return_type);
4472
4473 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4474 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4475
4476 /* The combination of:
4477 * - noalias
4478 * - dereferenceable
4479 * - invariant.load
4480 * allows the optimization passes to move loads and reduces
4481 * SGPR spilling significantly.
4482 */
4483 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4484
4485 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4486 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4487 ac_add_attr_dereferenceable(P, UINT64_MAX);
4488 }
4489 }
4490
4491 for (i = 0; i < fninfo->num_params; ++i) {
4492 if (fninfo->assign[i])
4493 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4494 }
4495
4496 if (ctx->screen->info.address32_hi) {
4497 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4498 "amdgpu-32bit-address-high-bits",
4499 ctx->screen->info.address32_hi);
4500 }
4501
4502 if (max_workgroup_size) {
4503 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4504 "amdgpu-max-work-group-size",
4505 max_workgroup_size);
4506 }
4507 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4508 "no-signed-zeros-fp-math",
4509 "true");
4510
4511 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4512 /* These were copied from some LLVM test. */
4513 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4514 "less-precise-fpmad",
4515 "true");
4516 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4517 "no-infs-fp-math",
4518 "true");
4519 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4520 "no-nans-fp-math",
4521 "true");
4522 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4523 "unsafe-fp-math",
4524 "true");
4525 }
4526 }
4527
4528 static void declare_streamout_params(struct si_shader_context *ctx,
4529 struct pipe_stream_output_info *so,
4530 struct si_function_info *fninfo)
4531 {
4532 int i;
4533
4534 /* Streamout SGPRs. */
4535 if (so->num_outputs) {
4536 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4537 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4538 else
4539 ctx->param_streamout_config = fninfo->num_params - 1;
4540
4541 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4542 }
4543 /* A streamout buffer offset is loaded if the stride is non-zero. */
4544 for (i = 0; i < 4; i++) {
4545 if (!so->stride[i])
4546 continue;
4547
4548 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4549 }
4550 }
4551
4552 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4553 {
4554 switch (shader->selector->type) {
4555 case PIPE_SHADER_TESS_CTRL:
4556 /* Return this so that LLVM doesn't remove s_barrier
4557 * instructions on chips where we use s_barrier. */
4558 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4559
4560 case PIPE_SHADER_GEOMETRY:
4561 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4562
4563 case PIPE_SHADER_COMPUTE:
4564 break; /* see below */
4565
4566 default:
4567 return 0;
4568 }
4569
4570 const unsigned *properties = shader->selector->info.properties;
4571 unsigned max_work_group_size =
4572 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4573 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4574 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4575
4576 if (!max_work_group_size) {
4577 /* This is a variable group size compute shader,
4578 * compile it for the maximum possible group size.
4579 */
4580 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4581 }
4582 return max_work_group_size;
4583 }
4584
4585 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4586 struct si_function_info *fninfo,
4587 bool assign_params)
4588 {
4589 LLVMTypeRef const_shader_buf_type;
4590
4591 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4592 ctx->shader->selector->info.shader_buffers_declared == 0)
4593 const_shader_buf_type = ctx->f32;
4594 else
4595 const_shader_buf_type = ctx->v4i32;
4596
4597 unsigned const_and_shader_buffers =
4598 add_arg(fninfo, ARG_SGPR,
4599 ac_array_in_const32_addr_space(const_shader_buf_type));
4600
4601 if (assign_params)
4602 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4603 }
4604
4605 static void declare_samplers_and_images(struct si_shader_context *ctx,
4606 struct si_function_info *fninfo,
4607 bool assign_params)
4608 {
4609 unsigned samplers_and_images =
4610 add_arg(fninfo, ARG_SGPR,
4611 ac_array_in_const32_addr_space(ctx->v8i32));
4612
4613 if (assign_params)
4614 ctx->param_samplers_and_images = samplers_and_images;
4615 }
4616
4617 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4618 struct si_function_info *fninfo,
4619 bool assign_params)
4620 {
4621 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4622 declare_samplers_and_images(ctx, fninfo, assign_params);
4623 }
4624
4625 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4626 struct si_function_info *fninfo)
4627 {
4628 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4629 ac_array_in_const32_addr_space(ctx->v4i32));
4630 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4631 ac_array_in_const32_addr_space(ctx->v8i32));
4632 }
4633
4634 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4635 struct si_function_info *fninfo)
4636 {
4637 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4638 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4639 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4640 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4641 }
4642
4643 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4644 struct si_function_info *fninfo,
4645 unsigned *num_prolog_vgprs)
4646 {
4647 struct si_shader *shader = ctx->shader;
4648
4649 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4650 if (shader->key.as_ls) {
4651 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4652 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4653 } else {
4654 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4655 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4656 }
4657 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4658
4659 if (!shader->is_gs_copy_shader) {
4660 /* Vertex load indices. */
4661 ctx->param_vertex_index0 = fninfo->num_params;
4662 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4663 add_arg(fninfo, ARG_VGPR, ctx->i32);
4664 *num_prolog_vgprs += shader->selector->info.num_inputs;
4665 }
4666 }
4667
4668 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4669 struct si_function_info *fninfo)
4670 {
4671 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4672 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4673 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4674 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4675 }
4676
4677 enum {
4678 /* Convenient merged shader definitions. */
4679 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4680 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4681 };
4682
4683 static void create_function(struct si_shader_context *ctx)
4684 {
4685 struct si_shader *shader = ctx->shader;
4686 struct si_function_info fninfo;
4687 LLVMTypeRef returns[16+32*4];
4688 unsigned i, num_return_sgprs;
4689 unsigned num_returns = 0;
4690 unsigned num_prolog_vgprs = 0;
4691 unsigned type = ctx->type;
4692 unsigned vs_blit_property =
4693 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4694
4695 si_init_function_info(&fninfo);
4696
4697 /* Set MERGED shaders. */
4698 if (ctx->screen->info.chip_class >= GFX9) {
4699 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4700 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4701 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4702 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4703 }
4704
4705 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4706
4707 switch (type) {
4708 case PIPE_SHADER_VERTEX:
4709 declare_global_desc_pointers(ctx, &fninfo);
4710
4711 if (vs_blit_property) {
4712 ctx->param_vs_blit_inputs = fninfo.num_params;
4713 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4714 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4715 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4716
4717 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4718 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4719 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4720 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4721 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4722 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4723 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4724 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4725 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4726 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4727 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4728 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4729 }
4730
4731 /* VGPRs */
4732 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4733 break;
4734 }
4735
4736 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4737 declare_vs_specific_input_sgprs(ctx, &fninfo);
4738 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4739 ac_array_in_const32_addr_space(ctx->v4i32));
4740
4741 if (shader->key.as_es) {
4742 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 } else if (shader->key.as_ls) {
4744 /* no extra parameters */
4745 } else {
4746 if (shader->is_gs_copy_shader) {
4747 fninfo.num_params = ctx->param_rw_buffers + 1;
4748 fninfo.num_sgpr_params = fninfo.num_params;
4749 }
4750
4751 /* The locations of the other parameters are assigned dynamically. */
4752 declare_streamout_params(ctx, &shader->selector->so,
4753 &fninfo);
4754 }
4755
4756 /* VGPRs */
4757 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4758 break;
4759
4760 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4761 declare_global_desc_pointers(ctx, &fninfo);
4762 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4763 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4764 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4765 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4766 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4767 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4768 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4769
4770 /* VGPRs */
4771 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4772 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4773
4774 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4775 * placed after the user SGPRs.
4776 */
4777 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4778 returns[num_returns++] = ctx->i32; /* SGPRs */
4779 for (i = 0; i < 11; i++)
4780 returns[num_returns++] = ctx->f32; /* VGPRs */
4781 break;
4782
4783 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4784 /* Merged stages have 8 system SGPRs at the beginning. */
4785 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4786 if (HAVE_32BIT_POINTERS) {
4787 declare_per_stage_desc_pointers(ctx, &fninfo,
4788 ctx->type == PIPE_SHADER_TESS_CTRL);
4789 } else {
4790 declare_const_and_shader_buffers(ctx, &fninfo,
4791 ctx->type == PIPE_SHADER_TESS_CTRL);
4792 }
4793 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4794 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4795 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4796 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4797 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4798 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4799
4800 declare_global_desc_pointers(ctx, &fninfo);
4801 declare_per_stage_desc_pointers(ctx, &fninfo,
4802 ctx->type == PIPE_SHADER_VERTEX);
4803 declare_vs_specific_input_sgprs(ctx, &fninfo);
4804
4805 if (!HAVE_32BIT_POINTERS) {
4806 declare_samplers_and_images(ctx, &fninfo,
4807 ctx->type == PIPE_SHADER_TESS_CTRL);
4808 }
4809 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4810 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4811 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4812 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4813 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4814 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4815 ac_array_in_const32_addr_space(ctx->v4i32));
4816
4817 /* VGPRs (first TCS, then VS) */
4818 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4819 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4820
4821 if (ctx->type == PIPE_SHADER_VERTEX) {
4822 declare_vs_input_vgprs(ctx, &fninfo,
4823 &num_prolog_vgprs);
4824
4825 /* LS return values are inputs to the TCS main shader part. */
4826 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4827 returns[num_returns++] = ctx->i32; /* SGPRs */
4828 for (i = 0; i < 2; i++)
4829 returns[num_returns++] = ctx->f32; /* VGPRs */
4830 } else {
4831 /* TCS return values are inputs to the TCS epilog.
4832 *
4833 * param_tcs_offchip_offset, param_tcs_factor_offset,
4834 * param_tcs_offchip_layout, and param_rw_buffers
4835 * should be passed to the epilog.
4836 */
4837 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4838 returns[num_returns++] = ctx->i32; /* SGPRs */
4839 for (i = 0; i < 11; i++)
4840 returns[num_returns++] = ctx->f32; /* VGPRs */
4841 }
4842 break;
4843
4844 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4845 /* Merged stages have 8 system SGPRs at the beginning. */
4846 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4847 if (HAVE_32BIT_POINTERS) {
4848 declare_per_stage_desc_pointers(ctx, &fninfo,
4849 ctx->type == PIPE_SHADER_GEOMETRY);
4850 } else {
4851 declare_const_and_shader_buffers(ctx, &fninfo,
4852 ctx->type == PIPE_SHADER_GEOMETRY);
4853 }
4854 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4855 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4856 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4857 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4858 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4859 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4860
4861 declare_global_desc_pointers(ctx, &fninfo);
4862 declare_per_stage_desc_pointers(ctx, &fninfo,
4863 (ctx->type == PIPE_SHADER_VERTEX ||
4864 ctx->type == PIPE_SHADER_TESS_EVAL));
4865 if (ctx->type == PIPE_SHADER_VERTEX) {
4866 declare_vs_specific_input_sgprs(ctx, &fninfo);
4867 } else {
4868 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4869 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4870 if (!HAVE_32BIT_POINTERS) {
4871 /* Declare as many input SGPRs as the VS has. */
4872 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4873 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4874 }
4875 }
4876
4877 if (!HAVE_32BIT_POINTERS) {
4878 declare_samplers_and_images(ctx, &fninfo,
4879 ctx->type == PIPE_SHADER_GEOMETRY);
4880 }
4881 if (ctx->type == PIPE_SHADER_VERTEX) {
4882 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4883 ac_array_in_const32_addr_space(ctx->v4i32));
4884 }
4885
4886 /* VGPRs (first GS, then VS/TES) */
4887 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4888 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4889 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4890 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4891 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4892
4893 if (ctx->type == PIPE_SHADER_VERTEX) {
4894 declare_vs_input_vgprs(ctx, &fninfo,
4895 &num_prolog_vgprs);
4896 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4897 declare_tes_input_vgprs(ctx, &fninfo);
4898 }
4899
4900 if (ctx->type == PIPE_SHADER_VERTEX ||
4901 ctx->type == PIPE_SHADER_TESS_EVAL) {
4902 unsigned num_user_sgprs;
4903
4904 if (ctx->type == PIPE_SHADER_VERTEX)
4905 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4906 else
4907 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4908
4909 /* ES return values are inputs to GS. */
4910 for (i = 0; i < 8 + num_user_sgprs; i++)
4911 returns[num_returns++] = ctx->i32; /* SGPRs */
4912 for (i = 0; i < 5; i++)
4913 returns[num_returns++] = ctx->f32; /* VGPRs */
4914 }
4915 break;
4916
4917 case PIPE_SHADER_TESS_EVAL:
4918 declare_global_desc_pointers(ctx, &fninfo);
4919 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4920 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4921 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4922
4923 if (shader->key.as_es) {
4924 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4925 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4926 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4927 } else {
4928 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4929 declare_streamout_params(ctx, &shader->selector->so,
4930 &fninfo);
4931 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4932 }
4933
4934 /* VGPRs */
4935 declare_tes_input_vgprs(ctx, &fninfo);
4936 break;
4937
4938 case PIPE_SHADER_GEOMETRY:
4939 declare_global_desc_pointers(ctx, &fninfo);
4940 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4941 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4942 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4943
4944 /* VGPRs */
4945 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4946 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4947 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4948 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4949 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4950 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4951 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4952 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4953 break;
4954
4955 case PIPE_SHADER_FRAGMENT:
4956 declare_global_desc_pointers(ctx, &fninfo);
4957 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4958 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4959 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4960 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4961
4962 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4963 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4964 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4965 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4966 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4967 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4968 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4969 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4970 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4971 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4972 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4973 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4974 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4975 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4976 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4977 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4978 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4979 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4980 shader->info.face_vgpr_index = 20;
4981 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4982 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4983 shader->info.ancillary_vgpr_index = 21;
4984 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4985 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4986 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4987
4988 /* Color inputs from the prolog. */
4989 if (shader->selector->info.colors_read) {
4990 unsigned num_color_elements =
4991 util_bitcount(shader->selector->info.colors_read);
4992
4993 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4994 for (i = 0; i < num_color_elements; i++)
4995 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4996
4997 num_prolog_vgprs += num_color_elements;
4998 }
4999
5000 /* Outputs for the epilog. */
5001 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5002 num_returns =
5003 num_return_sgprs +
5004 util_bitcount(shader->selector->info.colors_written) * 4 +
5005 shader->selector->info.writes_z +
5006 shader->selector->info.writes_stencil +
5007 shader->selector->info.writes_samplemask +
5008 1 /* SampleMaskIn */;
5009
5010 num_returns = MAX2(num_returns,
5011 num_return_sgprs +
5012 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5013
5014 for (i = 0; i < num_return_sgprs; i++)
5015 returns[i] = ctx->i32;
5016 for (; i < num_returns; i++)
5017 returns[i] = ctx->f32;
5018 break;
5019
5020 case PIPE_SHADER_COMPUTE:
5021 declare_global_desc_pointers(ctx, &fninfo);
5022 declare_per_stage_desc_pointers(ctx, &fninfo, true);
5023 if (shader->selector->info.uses_grid_size)
5024 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
5025 if (shader->selector->info.uses_block_size)
5026 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
5027
5028 for (i = 0; i < 3; i++) {
5029 ctx->abi.workgroup_ids[i] = NULL;
5030 if (shader->selector->info.uses_block_id[i])
5031 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
5032 }
5033
5034 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
5035 break;
5036 default:
5037 assert(0 && "unimplemented shader");
5038 return;
5039 }
5040
5041 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5042 si_get_max_workgroup_size(shader));
5043
5044 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5045 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5046 ctx->separate_prolog) {
5047 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5048 "InitialPSInputAddr",
5049 S_0286D0_PERSP_SAMPLE_ENA(1) |
5050 S_0286D0_PERSP_CENTER_ENA(1) |
5051 S_0286D0_PERSP_CENTROID_ENA(1) |
5052 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5053 S_0286D0_LINEAR_CENTER_ENA(1) |
5054 S_0286D0_LINEAR_CENTROID_ENA(1) |
5055 S_0286D0_FRONT_FACE_ENA(1) |
5056 S_0286D0_ANCILLARY_ENA(1) |
5057 S_0286D0_POS_FIXED_PT_ENA(1));
5058 }
5059
5060 shader->info.num_input_sgprs = 0;
5061 shader->info.num_input_vgprs = 0;
5062
5063 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5064 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5065
5066 for (; i < fninfo.num_params; ++i)
5067 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5068
5069 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5070 shader->info.num_input_vgprs -= num_prolog_vgprs;
5071
5072 if (shader->key.as_ls ||
5073 ctx->type == PIPE_SHADER_TESS_CTRL ||
5074 /* GFX9 has the ESGS ring buffer in LDS. */
5075 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5076 ac_declare_lds_as_pointer(&ctx->ac);
5077 }
5078
5079 /**
5080 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5081 * for later use.
5082 */
5083 static void preload_ring_buffers(struct si_shader_context *ctx)
5084 {
5085 LLVMBuilderRef builder = ctx->ac.builder;
5086
5087 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5088 ctx->param_rw_buffers);
5089
5090 if (ctx->screen->info.chip_class <= VI &&
5091 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5092 unsigned ring =
5093 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5094 : SI_ES_RING_ESGS;
5095 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5096
5097 ctx->esgs_ring =
5098 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5099 }
5100
5101 if (ctx->shader->is_gs_copy_shader) {
5102 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5103
5104 ctx->gsvs_ring[0] =
5105 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5106 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5107 const struct si_shader_selector *sel = ctx->shader->selector;
5108 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5109 LLVMValueRef base_ring;
5110
5111 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5112
5113 /* The conceptual layout of the GSVS ring is
5114 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5115 * but the real memory layout is swizzled across
5116 * threads:
5117 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5118 * t16v0c0 ..
5119 * Override the buffer descriptor accordingly.
5120 */
5121 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5122 uint64_t stream_offset = 0;
5123
5124 for (unsigned stream = 0; stream < 4; ++stream) {
5125 unsigned num_components;
5126 unsigned stride;
5127 unsigned num_records;
5128 LLVMValueRef ring, tmp;
5129
5130 num_components = sel->info.num_stream_output_components[stream];
5131 if (!num_components)
5132 continue;
5133
5134 stride = 4 * num_components * sel->gs_max_out_vertices;
5135
5136 /* Limit on the stride field for <= CIK. */
5137 assert(stride < (1 << 14));
5138
5139 num_records = 64;
5140
5141 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5142 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5143 tmp = LLVMBuildAdd(builder, tmp,
5144 LLVMConstInt(ctx->i64,
5145 stream_offset, 0), "");
5146 stream_offset += stride * 64;
5147
5148 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5149 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5150 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5151 tmp = LLVMBuildOr(builder, tmp,
5152 LLVMConstInt(ctx->i32,
5153 S_008F04_STRIDE(stride) |
5154 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5155 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5156 ring = LLVMBuildInsertElement(builder, ring,
5157 LLVMConstInt(ctx->i32, num_records, 0),
5158 LLVMConstInt(ctx->i32, 2, 0), "");
5159 ring = LLVMBuildInsertElement(builder, ring,
5160 LLVMConstInt(ctx->i32,
5161 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5165 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5167 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5168 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5169 S_008F0C_ADD_TID_ENABLE(1),
5170 0),
5171 LLVMConstInt(ctx->i32, 3, 0), "");
5172
5173 ctx->gsvs_ring[stream] = ring;
5174 }
5175 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5176 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5177 }
5178 }
5179
5180 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5181 LLVMValueRef param_rw_buffers,
5182 unsigned param_pos_fixed_pt)
5183 {
5184 LLVMBuilderRef builder = ctx->ac.builder;
5185 LLVMValueRef slot, desc, offset, row, bit, address[2];
5186
5187 /* Use the fixed-point gl_FragCoord input.
5188 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5189 * per coordinate to get the repeating effect.
5190 */
5191 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5192 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5193
5194 /* Load the buffer descriptor. */
5195 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5196 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5197
5198 /* The stipple pattern is 32x32, each row has 32 bits. */
5199 offset = LLVMBuildMul(builder, address[1],
5200 LLVMConstInt(ctx->i32, 4, 0), "");
5201 row = buffer_load_const(ctx, desc, offset);
5202 row = ac_to_integer(&ctx->ac, row);
5203 bit = LLVMBuildLShr(builder, row, address[0], "");
5204 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5205 ac_build_kill_if_false(&ctx->ac, bit);
5206 }
5207
5208 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5209 struct si_shader_config *conf,
5210 unsigned symbol_offset)
5211 {
5212 unsigned i;
5213 const unsigned char *config =
5214 ac_shader_binary_config_start(binary, symbol_offset);
5215 bool really_needs_scratch = false;
5216
5217 /* LLVM adds SGPR spills to the scratch size.
5218 * Find out if we really need the scratch buffer.
5219 */
5220 for (i = 0; i < binary->reloc_count; i++) {
5221 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5222
5223 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5224 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5225 really_needs_scratch = true;
5226 break;
5227 }
5228 }
5229
5230 /* XXX: We may be able to emit some of these values directly rather than
5231 * extracting fields to be emitted later.
5232 */
5233
5234 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5235 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5236 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5237 switch (reg) {
5238 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5239 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5240 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5241 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5242 case R_00B848_COMPUTE_PGM_RSRC1:
5243 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5244 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5245 conf->float_mode = G_00B028_FLOAT_MODE(value);
5246 conf->rsrc1 = value;
5247 break;
5248 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5249 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5250 break;
5251 case R_00B84C_COMPUTE_PGM_RSRC2:
5252 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5253 conf->rsrc2 = value;
5254 break;
5255 case R_0286CC_SPI_PS_INPUT_ENA:
5256 conf->spi_ps_input_ena = value;
5257 break;
5258 case R_0286D0_SPI_PS_INPUT_ADDR:
5259 conf->spi_ps_input_addr = value;
5260 break;
5261 case R_0286E8_SPI_TMPRING_SIZE:
5262 case R_00B860_COMPUTE_TMPRING_SIZE:
5263 /* WAVESIZE is in units of 256 dwords. */
5264 if (really_needs_scratch)
5265 conf->scratch_bytes_per_wave =
5266 G_00B860_WAVESIZE(value) * 256 * 4;
5267 break;
5268 case 0x4: /* SPILLED_SGPRS */
5269 conf->spilled_sgprs = value;
5270 break;
5271 case 0x8: /* SPILLED_VGPRS */
5272 conf->spilled_vgprs = value;
5273 break;
5274 default:
5275 {
5276 static bool printed;
5277
5278 if (!printed) {
5279 fprintf(stderr, "Warning: LLVM emitted unknown "
5280 "config register: 0x%x\n", reg);
5281 printed = true;
5282 }
5283 }
5284 break;
5285 }
5286 }
5287
5288 if (!conf->spi_ps_input_addr)
5289 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5290 }
5291
5292 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5293 uint64_t scratch_va)
5294 {
5295 unsigned i;
5296 uint32_t scratch_rsrc_dword0 = scratch_va;
5297 uint32_t scratch_rsrc_dword1 =
5298 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5299
5300 /* Enable scratch coalescing. */
5301 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5302
5303 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5304 const struct ac_shader_reloc *reloc =
5305 &shader->binary.relocs[i];
5306 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5307 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5308 &scratch_rsrc_dword0, 4);
5309 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5310 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5311 &scratch_rsrc_dword1, 4);
5312 }
5313 }
5314 }
5315
5316 /* For the UMR disassembler. */
5317 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5318 #define DEBUGGER_NUM_MARKERS 5
5319
5320 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5321 {
5322 unsigned size = shader->binary.code_size;
5323
5324 if (shader->prolog)
5325 size += shader->prolog->binary.code_size;
5326 if (shader->previous_stage)
5327 size += shader->previous_stage->binary.code_size;
5328 if (shader->prolog2)
5329 size += shader->prolog2->binary.code_size;
5330 if (shader->epilog)
5331 size += shader->epilog->binary.code_size;
5332 return size + DEBUGGER_NUM_MARKERS * 4;
5333 }
5334
5335 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5336 {
5337 const struct ac_shader_binary *prolog =
5338 shader->prolog ? &shader->prolog->binary : NULL;
5339 const struct ac_shader_binary *previous_stage =
5340 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5341 const struct ac_shader_binary *prolog2 =
5342 shader->prolog2 ? &shader->prolog2->binary : NULL;
5343 const struct ac_shader_binary *epilog =
5344 shader->epilog ? &shader->epilog->binary : NULL;
5345 const struct ac_shader_binary *mainb = &shader->binary;
5346 unsigned bo_size = si_get_shader_binary_size(shader) +
5347 (!epilog ? mainb->rodata_size : 0);
5348 unsigned char *ptr;
5349
5350 assert(!prolog || !prolog->rodata_size);
5351 assert(!previous_stage || !previous_stage->rodata_size);
5352 assert(!prolog2 || !prolog2->rodata_size);
5353 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5354 !mainb->rodata_size);
5355 assert(!epilog || !epilog->rodata_size);
5356
5357 r600_resource_reference(&shader->bo, NULL);
5358 shader->bo = si_aligned_buffer_create(&sscreen->b,
5359 sscreen->cpdma_prefetch_writes_memory ?
5360 0 : SI_RESOURCE_FLAG_READ_ONLY,
5361 PIPE_USAGE_IMMUTABLE,
5362 align(bo_size, SI_CPDMA_ALIGNMENT),
5363 256);
5364 if (!shader->bo)
5365 return -ENOMEM;
5366
5367 /* Upload. */
5368 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5369 PIPE_TRANSFER_READ_WRITE |
5370 PIPE_TRANSFER_UNSYNCHRONIZED);
5371
5372 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5373 * endian-independent. */
5374 if (prolog) {
5375 memcpy(ptr, prolog->code, prolog->code_size);
5376 ptr += prolog->code_size;
5377 }
5378 if (previous_stage) {
5379 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5380 ptr += previous_stage->code_size;
5381 }
5382 if (prolog2) {
5383 memcpy(ptr, prolog2->code, prolog2->code_size);
5384 ptr += prolog2->code_size;
5385 }
5386
5387 memcpy(ptr, mainb->code, mainb->code_size);
5388 ptr += mainb->code_size;
5389
5390 if (epilog) {
5391 memcpy(ptr, epilog->code, epilog->code_size);
5392 ptr += epilog->code_size;
5393 } else if (mainb->rodata_size > 0) {
5394 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5395 ptr += mainb->rodata_size;
5396 }
5397
5398 /* Add end-of-code markers for the UMR disassembler. */
5399 uint32_t *ptr32 = (uint32_t*)ptr;
5400 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5401 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5402
5403 sscreen->ws->buffer_unmap(shader->bo->buf);
5404 return 0;
5405 }
5406
5407 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5408 struct pipe_debug_callback *debug,
5409 const char *name, FILE *file)
5410 {
5411 char *line, *p;
5412 unsigned i, count;
5413
5414 if (binary->disasm_string) {
5415 fprintf(file, "Shader %s disassembly:\n", name);
5416 fprintf(file, "%s", binary->disasm_string);
5417
5418 if (debug && debug->debug_message) {
5419 /* Very long debug messages are cut off, so send the
5420 * disassembly one line at a time. This causes more
5421 * overhead, but on the plus side it simplifies
5422 * parsing of resulting logs.
5423 */
5424 pipe_debug_message(debug, SHADER_INFO,
5425 "Shader Disassembly Begin");
5426
5427 line = binary->disasm_string;
5428 while (*line) {
5429 p = util_strchrnul(line, '\n');
5430 count = p - line;
5431
5432 if (count) {
5433 pipe_debug_message(debug, SHADER_INFO,
5434 "%.*s", count, line);
5435 }
5436
5437 if (!*p)
5438 break;
5439 line = p + 1;
5440 }
5441
5442 pipe_debug_message(debug, SHADER_INFO,
5443 "Shader Disassembly End");
5444 }
5445 } else {
5446 fprintf(file, "Shader %s binary:\n", name);
5447 for (i = 0; i < binary->code_size; i += 4) {
5448 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5449 binary->code[i + 3], binary->code[i + 2],
5450 binary->code[i + 1], binary->code[i]);
5451 }
5452 }
5453 }
5454
5455 static void si_calculate_max_simd_waves(struct si_shader *shader)
5456 {
5457 struct si_screen *sscreen = shader->selector->screen;
5458 struct si_shader_config *conf = &shader->config;
5459 unsigned num_inputs = shader->selector->info.num_inputs;
5460 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5461 unsigned lds_per_wave = 0;
5462 unsigned max_simd_waves;
5463
5464 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5465
5466 /* Compute LDS usage for PS. */
5467 switch (shader->selector->type) {
5468 case PIPE_SHADER_FRAGMENT:
5469 /* The minimum usage per wave is (num_inputs * 48). The maximum
5470 * usage is (num_inputs * 48 * 16).
5471 * We can get anything in between and it varies between waves.
5472 *
5473 * The 48 bytes per input for a single primitive is equal to
5474 * 4 bytes/component * 4 components/input * 3 points.
5475 *
5476 * Other stages don't know the size at compile time or don't
5477 * allocate LDS per wave, but instead they do it per thread group.
5478 */
5479 lds_per_wave = conf->lds_size * lds_increment +
5480 align(num_inputs * 48, lds_increment);
5481 break;
5482 case PIPE_SHADER_COMPUTE:
5483 if (shader->selector) {
5484 unsigned max_workgroup_size =
5485 si_get_max_workgroup_size(shader);
5486 lds_per_wave = (conf->lds_size * lds_increment) /
5487 DIV_ROUND_UP(max_workgroup_size, 64);
5488 }
5489 break;
5490 }
5491
5492 /* Compute the per-SIMD wave counts. */
5493 if (conf->num_sgprs) {
5494 if (sscreen->info.chip_class >= VI)
5495 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5496 else
5497 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5498 }
5499
5500 if (conf->num_vgprs)
5501 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5502
5503 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5504 * 16KB makes some SIMDs unoccupied). */
5505 if (lds_per_wave)
5506 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5507
5508 conf->max_simd_waves = max_simd_waves;
5509 }
5510
5511 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5512 struct pipe_debug_callback *debug)
5513 {
5514 const struct si_shader_config *conf = &shader->config;
5515
5516 pipe_debug_message(debug, SHADER_INFO,
5517 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5518 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5519 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5520 conf->num_sgprs, conf->num_vgprs,
5521 si_get_shader_binary_size(shader),
5522 conf->lds_size, conf->scratch_bytes_per_wave,
5523 conf->max_simd_waves, conf->spilled_sgprs,
5524 conf->spilled_vgprs, conf->private_mem_vgprs);
5525 }
5526
5527 static void si_shader_dump_stats(struct si_screen *sscreen,
5528 const struct si_shader *shader,
5529 unsigned processor,
5530 FILE *file,
5531 bool check_debug_option)
5532 {
5533 const struct si_shader_config *conf = &shader->config;
5534
5535 if (!check_debug_option ||
5536 si_can_dump_shader(sscreen, processor)) {
5537 if (processor == PIPE_SHADER_FRAGMENT) {
5538 fprintf(file, "*** SHADER CONFIG ***\n"
5539 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5540 "SPI_PS_INPUT_ENA = 0x%04x\n",
5541 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5542 }
5543
5544 fprintf(file, "*** SHADER STATS ***\n"
5545 "SGPRS: %d\n"
5546 "VGPRS: %d\n"
5547 "Spilled SGPRs: %d\n"
5548 "Spilled VGPRs: %d\n"
5549 "Private memory VGPRs: %d\n"
5550 "Code Size: %d bytes\n"
5551 "LDS: %d blocks\n"
5552 "Scratch: %d bytes per wave\n"
5553 "Max Waves: %d\n"
5554 "********************\n\n\n",
5555 conf->num_sgprs, conf->num_vgprs,
5556 conf->spilled_sgprs, conf->spilled_vgprs,
5557 conf->private_mem_vgprs,
5558 si_get_shader_binary_size(shader),
5559 conf->lds_size, conf->scratch_bytes_per_wave,
5560 conf->max_simd_waves);
5561 }
5562 }
5563
5564 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5565 {
5566 switch (processor) {
5567 case PIPE_SHADER_VERTEX:
5568 if (shader->key.as_es)
5569 return "Vertex Shader as ES";
5570 else if (shader->key.as_ls)
5571 return "Vertex Shader as LS";
5572 else
5573 return "Vertex Shader as VS";
5574 case PIPE_SHADER_TESS_CTRL:
5575 return "Tessellation Control Shader";
5576 case PIPE_SHADER_TESS_EVAL:
5577 if (shader->key.as_es)
5578 return "Tessellation Evaluation Shader as ES";
5579 else
5580 return "Tessellation Evaluation Shader as VS";
5581 case PIPE_SHADER_GEOMETRY:
5582 if (shader->is_gs_copy_shader)
5583 return "GS Copy Shader as VS";
5584 else
5585 return "Geometry Shader";
5586 case PIPE_SHADER_FRAGMENT:
5587 return "Pixel Shader";
5588 case PIPE_SHADER_COMPUTE:
5589 return "Compute Shader";
5590 default:
5591 return "Unknown Shader";
5592 }
5593 }
5594
5595 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5596 struct pipe_debug_callback *debug, unsigned processor,
5597 FILE *file, bool check_debug_option)
5598 {
5599 if (!check_debug_option ||
5600 si_can_dump_shader(sscreen, processor))
5601 si_dump_shader_key(processor, shader, file);
5602
5603 if (!check_debug_option && shader->binary.llvm_ir_string) {
5604 if (shader->previous_stage &&
5605 shader->previous_stage->binary.llvm_ir_string) {
5606 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5607 si_get_shader_name(shader, processor));
5608 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5609 }
5610
5611 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5612 si_get_shader_name(shader, processor));
5613 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5614 }
5615
5616 if (!check_debug_option ||
5617 (si_can_dump_shader(sscreen, processor) &&
5618 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5619 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5620
5621 if (shader->prolog)
5622 si_shader_dump_disassembly(&shader->prolog->binary,
5623 debug, "prolog", file);
5624 if (shader->previous_stage)
5625 si_shader_dump_disassembly(&shader->previous_stage->binary,
5626 debug, "previous stage", file);
5627 if (shader->prolog2)
5628 si_shader_dump_disassembly(&shader->prolog2->binary,
5629 debug, "prolog2", file);
5630
5631 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5632
5633 if (shader->epilog)
5634 si_shader_dump_disassembly(&shader->epilog->binary,
5635 debug, "epilog", file);
5636 fprintf(file, "\n");
5637 }
5638
5639 si_shader_dump_stats(sscreen, shader, processor, file,
5640 check_debug_option);
5641 }
5642
5643 static int si_compile_llvm(struct si_screen *sscreen,
5644 struct ac_shader_binary *binary,
5645 struct si_shader_config *conf,
5646 struct si_compiler *compiler,
5647 LLVMModuleRef mod,
5648 struct pipe_debug_callback *debug,
5649 unsigned processor,
5650 const char *name)
5651 {
5652 int r = 0;
5653 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5654
5655 if (si_can_dump_shader(sscreen, processor)) {
5656 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5657
5658 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5659 fprintf(stderr, "%s LLVM IR:\n\n", name);
5660 ac_dump_module(mod);
5661 fprintf(stderr, "\n");
5662 }
5663 }
5664
5665 if (sscreen->record_llvm_ir) {
5666 char *ir = LLVMPrintModuleToString(mod);
5667 binary->llvm_ir_string = strdup(ir);
5668 LLVMDisposeMessage(ir);
5669 }
5670
5671 if (!si_replace_shader(count, binary)) {
5672 r = si_llvm_compile(mod, binary, compiler, debug);
5673 if (r)
5674 return r;
5675 }
5676
5677 si_shader_binary_read_config(binary, conf, 0);
5678
5679 /* Enable 64-bit and 16-bit denormals, because there is no performance
5680 * cost.
5681 *
5682 * If denormals are enabled, all floating-point output modifiers are
5683 * ignored.
5684 *
5685 * Don't enable denormals for 32-bit floats, because:
5686 * - Floating-point output modifiers would be ignored by the hw.
5687 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5688 * have to stop using those.
5689 * - SI & CI would be very slow.
5690 */
5691 conf->float_mode |= V_00B028_FP_64_DENORMS;
5692
5693 FREE(binary->config);
5694 FREE(binary->global_symbol_offsets);
5695 binary->config = NULL;
5696 binary->global_symbol_offsets = NULL;
5697
5698 /* Some shaders can't have rodata because their binaries can be
5699 * concatenated.
5700 */
5701 if (binary->rodata_size &&
5702 (processor == PIPE_SHADER_VERTEX ||
5703 processor == PIPE_SHADER_TESS_CTRL ||
5704 processor == PIPE_SHADER_TESS_EVAL ||
5705 processor == PIPE_SHADER_FRAGMENT)) {
5706 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5707 return -EINVAL;
5708 }
5709
5710 return r;
5711 }
5712
5713 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5714 {
5715 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5716 LLVMBuildRetVoid(ctx->ac.builder);
5717 else
5718 LLVMBuildRet(ctx->ac.builder, ret);
5719 }
5720
5721 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5722 struct si_shader *
5723 si_generate_gs_copy_shader(struct si_screen *sscreen,
5724 struct si_compiler *compiler,
5725 struct si_shader_selector *gs_selector,
5726 struct pipe_debug_callback *debug)
5727 {
5728 struct si_shader_context ctx;
5729 struct si_shader *shader;
5730 LLVMBuilderRef builder;
5731 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5732 struct lp_build_context *uint = &bld_base->uint_bld;
5733 struct si_shader_output_values *outputs;
5734 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5735 int i, r;
5736
5737 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5738
5739 if (!outputs)
5740 return NULL;
5741
5742 shader = CALLOC_STRUCT(si_shader);
5743 if (!shader) {
5744 FREE(outputs);
5745 return NULL;
5746 }
5747
5748 /* We can leave the fence as permanently signaled because the GS copy
5749 * shader only becomes visible globally after it has been compiled. */
5750 util_queue_fence_init(&shader->ready);
5751
5752 shader->selector = gs_selector;
5753 shader->is_gs_copy_shader = true;
5754
5755 si_init_shader_ctx(&ctx, sscreen, compiler);
5756 ctx.shader = shader;
5757 ctx.type = PIPE_SHADER_VERTEX;
5758
5759 builder = ctx.ac.builder;
5760
5761 create_function(&ctx);
5762 preload_ring_buffers(&ctx);
5763
5764 LLVMValueRef voffset =
5765 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5766
5767 /* Fetch the vertex stream ID.*/
5768 LLVMValueRef stream_id;
5769
5770 if (gs_selector->so.num_outputs)
5771 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5772 else
5773 stream_id = ctx.i32_0;
5774
5775 /* Fill in output information. */
5776 for (i = 0; i < gsinfo->num_outputs; ++i) {
5777 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5778 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5779
5780 for (int chan = 0; chan < 4; chan++) {
5781 outputs[i].vertex_stream[chan] =
5782 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5783 }
5784 }
5785
5786 LLVMBasicBlockRef end_bb;
5787 LLVMValueRef switch_inst;
5788
5789 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5790 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5791
5792 for (int stream = 0; stream < 4; stream++) {
5793 LLVMBasicBlockRef bb;
5794 unsigned offset;
5795
5796 if (!gsinfo->num_stream_output_components[stream])
5797 continue;
5798
5799 if (stream > 0 && !gs_selector->so.num_outputs)
5800 continue;
5801
5802 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5803 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5804 LLVMPositionBuilderAtEnd(builder, bb);
5805
5806 /* Fetch vertex data from GSVS ring */
5807 offset = 0;
5808 for (i = 0; i < gsinfo->num_outputs; ++i) {
5809 for (unsigned chan = 0; chan < 4; chan++) {
5810 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5811 outputs[i].vertex_stream[chan] != stream) {
5812 outputs[i].values[chan] = ctx.bld_base.base.undef;
5813 continue;
5814 }
5815
5816 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5817 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5818 offset++;
5819
5820 outputs[i].values[chan] =
5821 ac_build_buffer_load(&ctx.ac,
5822 ctx.gsvs_ring[0], 1,
5823 ctx.i32_0, voffset,
5824 soffset, 0, 1, 1,
5825 true, false);
5826 }
5827 }
5828
5829 /* Streamout and exports. */
5830 if (gs_selector->so.num_outputs) {
5831 si_llvm_emit_streamout(&ctx, outputs,
5832 gsinfo->num_outputs,
5833 stream);
5834 }
5835
5836 if (stream == 0)
5837 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5838
5839 LLVMBuildBr(builder, end_bb);
5840 }
5841
5842 LLVMPositionBuilderAtEnd(builder, end_bb);
5843
5844 LLVMBuildRetVoid(ctx.ac.builder);
5845
5846 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5847 si_llvm_optimize_module(&ctx);
5848
5849 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5850 &ctx.shader->config, ctx.compiler,
5851 ctx.gallivm.module,
5852 debug, PIPE_SHADER_GEOMETRY,
5853 "GS Copy Shader");
5854 if (!r) {
5855 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5856 fprintf(stderr, "GS Copy Shader:\n");
5857 si_shader_dump(sscreen, ctx.shader, debug,
5858 PIPE_SHADER_GEOMETRY, stderr, true);
5859 r = si_shader_binary_upload(sscreen, ctx.shader);
5860 }
5861
5862 si_llvm_dispose(&ctx);
5863
5864 FREE(outputs);
5865
5866 if (r != 0) {
5867 FREE(shader);
5868 shader = NULL;
5869 }
5870 return shader;
5871 }
5872
5873 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5874 const struct si_vs_prolog_bits *prolog,
5875 const char *prefix, FILE *f)
5876 {
5877 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5878 prefix, prolog->instance_divisor_is_one);
5879 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5880 prefix, prolog->instance_divisor_is_fetched);
5881 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5882 prefix, prolog->ls_vgpr_fix);
5883
5884 fprintf(f, " mono.vs.fix_fetch = {");
5885 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5886 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5887 fprintf(f, "}\n");
5888 }
5889
5890 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5891 FILE *f)
5892 {
5893 const struct si_shader_key *key = &shader->key;
5894
5895 fprintf(f, "SHADER KEY\n");
5896
5897 switch (processor) {
5898 case PIPE_SHADER_VERTEX:
5899 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5900 "part.vs.prolog", f);
5901 fprintf(f, " as_es = %u\n", key->as_es);
5902 fprintf(f, " as_ls = %u\n", key->as_ls);
5903 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5904 key->mono.u.vs_export_prim_id);
5905 break;
5906
5907 case PIPE_SHADER_TESS_CTRL:
5908 if (shader->selector->screen->info.chip_class >= GFX9) {
5909 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5910 "part.tcs.ls_prolog", f);
5911 }
5912 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5913 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5914 break;
5915
5916 case PIPE_SHADER_TESS_EVAL:
5917 fprintf(f, " as_es = %u\n", key->as_es);
5918 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5919 key->mono.u.vs_export_prim_id);
5920 break;
5921
5922 case PIPE_SHADER_GEOMETRY:
5923 if (shader->is_gs_copy_shader)
5924 break;
5925
5926 if (shader->selector->screen->info.chip_class >= GFX9 &&
5927 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5928 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5929 "part.gs.vs_prolog", f);
5930 }
5931 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5932 break;
5933
5934 case PIPE_SHADER_COMPUTE:
5935 break;
5936
5937 case PIPE_SHADER_FRAGMENT:
5938 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5939 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5940 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5941 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5942 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5943 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5944 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5945 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5946 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5947 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5948 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5949 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5950 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5951 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5952 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5953 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5954 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5955 break;
5956
5957 default:
5958 assert(0);
5959 }
5960
5961 if ((processor == PIPE_SHADER_GEOMETRY ||
5962 processor == PIPE_SHADER_TESS_EVAL ||
5963 processor == PIPE_SHADER_VERTEX) &&
5964 !key->as_es && !key->as_ls) {
5965 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5966 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5967 }
5968 }
5969
5970 static void si_init_shader_ctx(struct si_shader_context *ctx,
5971 struct si_screen *sscreen,
5972 struct si_compiler *compiler)
5973 {
5974 struct lp_build_tgsi_context *bld_base;
5975
5976 si_llvm_context_init(ctx, sscreen, compiler);
5977
5978 bld_base = &ctx->bld_base;
5979 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5980
5981 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5982 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5983 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5984
5985 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5986
5987 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5988
5989 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5990 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5991 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5992 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5993
5994 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5995 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5996 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5997 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5998 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5999 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6000 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6001 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
6002 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6003
6004 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
6005 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
6006 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6007 }
6008
6009 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
6010 {
6011 struct si_shader *shader = ctx->shader;
6012 struct tgsi_shader_info *info = &shader->selector->info;
6013
6014 if ((ctx->type != PIPE_SHADER_VERTEX &&
6015 ctx->type != PIPE_SHADER_TESS_EVAL) ||
6016 shader->key.as_ls ||
6017 shader->key.as_es)
6018 return;
6019
6020 ac_optimize_vs_outputs(&ctx->ac,
6021 ctx->main_fn,
6022 shader->info.vs_output_param_offset,
6023 info->num_outputs,
6024 &shader->info.nr_param_exports);
6025 }
6026
6027 static void si_init_exec_from_input(struct si_shader_context *ctx,
6028 unsigned param, unsigned bitoffset)
6029 {
6030 LLVMValueRef args[] = {
6031 LLVMGetParam(ctx->main_fn, param),
6032 LLVMConstInt(ctx->i32, bitoffset, 0),
6033 };
6034 lp_build_intrinsic(ctx->ac.builder,
6035 "llvm.amdgcn.init.exec.from.input",
6036 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
6037 }
6038
6039 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6040 const struct si_vs_prolog_bits *key)
6041 {
6042 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6043 * VS prolog. */
6044 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6045 }
6046
6047 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6048 bool is_monolithic)
6049 {
6050 struct si_shader *shader = ctx->shader;
6051 struct si_shader_selector *sel = shader->selector;
6052 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6053
6054 // TODO clean all this up!
6055 switch (ctx->type) {
6056 case PIPE_SHADER_VERTEX:
6057 ctx->load_input = declare_input_vs;
6058 if (shader->key.as_ls)
6059 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6060 else if (shader->key.as_es)
6061 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6062 else
6063 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6064 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6065 ctx->abi.load_base_vertex = get_base_vertex;
6066 break;
6067 case PIPE_SHADER_TESS_CTRL:
6068 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6069 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6070 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6071 bld_base->emit_store = store_output_tcs;
6072 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6073 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6074 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6075 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6076 break;
6077 case PIPE_SHADER_TESS_EVAL:
6078 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6079 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6080 ctx->abi.load_tess_coord = si_load_tess_coord;
6081 ctx->abi.load_tess_level = si_load_tess_level;
6082 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6083 if (shader->key.as_es)
6084 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6085 else
6086 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6087 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6088 break;
6089 case PIPE_SHADER_GEOMETRY:
6090 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6091 ctx->abi.load_inputs = si_nir_load_input_gs;
6092 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6093 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6094 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6095 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6096 break;
6097 case PIPE_SHADER_FRAGMENT:
6098 ctx->load_input = declare_input_fs;
6099 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6100 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6101 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6102 ctx->abi.load_sample_position = load_sample_position;
6103 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6104 ctx->abi.emit_kill = si_llvm_emit_kill;
6105 break;
6106 case PIPE_SHADER_COMPUTE:
6107 ctx->abi.load_local_group_size = get_block_size;
6108 break;
6109 default:
6110 assert(!"Unsupported shader type");
6111 return false;
6112 }
6113
6114 ctx->abi.load_ubo = load_ubo;
6115 ctx->abi.load_ssbo = load_ssbo;
6116
6117 create_function(ctx);
6118 preload_ring_buffers(ctx);
6119
6120 /* For GFX9 merged shaders:
6121 * - Set EXEC for the first shader. If the prolog is present, set
6122 * EXEC there instead.
6123 * - Add a barrier before the second shader.
6124 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6125 * an if-statement. This is required for correctness in geometry
6126 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6127 * GS_CUT messages.
6128 *
6129 * For monolithic merged shaders, the first shader is wrapped in an
6130 * if-block together with its prolog in si_build_wrapper_function.
6131 */
6132 if (ctx->screen->info.chip_class >= GFX9) {
6133 if (!is_monolithic &&
6134 sel->info.num_instructions > 1 && /* not empty shader */
6135 (shader->key.as_es || shader->key.as_ls) &&
6136 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6137 (ctx->type == PIPE_SHADER_VERTEX &&
6138 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6139 si_init_exec_from_input(ctx,
6140 ctx->param_merged_wave_info, 0);
6141 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6142 ctx->type == PIPE_SHADER_GEOMETRY) {
6143 if (!is_monolithic)
6144 ac_init_exec_full_mask(&ctx->ac);
6145
6146 /* The barrier must execute for all shaders in a
6147 * threadgroup.
6148 */
6149 si_llvm_emit_barrier(NULL, bld_base, NULL);
6150
6151 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6152 LLVMValueRef ena =
6153 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6154 ac_get_thread_id(&ctx->ac), num_threads, "");
6155 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6156 }
6157 }
6158
6159 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6160 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6161 for (unsigned i = 0; i < 6; i++) {
6162 ctx->invoc0_tess_factors[i] =
6163 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6164 }
6165 }
6166
6167 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6168 int i;
6169 for (i = 0; i < 4; i++) {
6170 ctx->gs_next_vertex[i] =
6171 lp_build_alloca(&ctx->gallivm,
6172 ctx->i32, "");
6173 }
6174 }
6175
6176 if (sel->force_correct_derivs_after_kill) {
6177 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6178 /* true = don't kill. */
6179 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6180 ctx->postponed_kill);
6181 }
6182
6183 if (sel->tokens) {
6184 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6185 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6186 return false;
6187 }
6188 } else {
6189 if (!si_nir_build_llvm(ctx, sel->nir)) {
6190 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6191 return false;
6192 }
6193 }
6194
6195 si_llvm_build_ret(ctx, ctx->return_value);
6196 return true;
6197 }
6198
6199 /**
6200 * Compute the VS prolog key, which contains all the information needed to
6201 * build the VS prolog function, and set shader->info bits where needed.
6202 *
6203 * \param info Shader info of the vertex shader.
6204 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6205 * \param prolog_key Key of the VS prolog
6206 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6207 * \param key Output shader part key.
6208 */
6209 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6210 unsigned num_input_sgprs,
6211 const struct si_vs_prolog_bits *prolog_key,
6212 struct si_shader *shader_out,
6213 union si_shader_part_key *key)
6214 {
6215 memset(key, 0, sizeof(*key));
6216 key->vs_prolog.states = *prolog_key;
6217 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6218 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6219 key->vs_prolog.as_ls = shader_out->key.as_ls;
6220 key->vs_prolog.as_es = shader_out->key.as_es;
6221
6222 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6223 key->vs_prolog.as_ls = 1;
6224 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6225 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6226 key->vs_prolog.as_es = 1;
6227 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6228 }
6229
6230 /* Enable loading the InstanceID VGPR. */
6231 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6232
6233 if ((key->vs_prolog.states.instance_divisor_is_one |
6234 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6235 shader_out->info.uses_instanceid = true;
6236 }
6237
6238 /**
6239 * Compute the PS prolog key, which contains all the information needed to
6240 * build the PS prolog function, and set related bits in shader->config.
6241 */
6242 static void si_get_ps_prolog_key(struct si_shader *shader,
6243 union si_shader_part_key *key,
6244 bool separate_prolog)
6245 {
6246 struct tgsi_shader_info *info = &shader->selector->info;
6247
6248 memset(key, 0, sizeof(*key));
6249 key->ps_prolog.states = shader->key.part.ps.prolog;
6250 key->ps_prolog.colors_read = info->colors_read;
6251 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6252 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6253 key->ps_prolog.wqm = info->uses_derivatives &&
6254 (key->ps_prolog.colors_read ||
6255 key->ps_prolog.states.force_persp_sample_interp ||
6256 key->ps_prolog.states.force_linear_sample_interp ||
6257 key->ps_prolog.states.force_persp_center_interp ||
6258 key->ps_prolog.states.force_linear_center_interp ||
6259 key->ps_prolog.states.bc_optimize_for_persp ||
6260 key->ps_prolog.states.bc_optimize_for_linear);
6261 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6262
6263 if (info->colors_read) {
6264 unsigned *color = shader->selector->color_attr_index;
6265
6266 if (shader->key.part.ps.prolog.color_two_side) {
6267 /* BCOLORs are stored after the last input. */
6268 key->ps_prolog.num_interp_inputs = info->num_inputs;
6269 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6270 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6271 }
6272
6273 for (unsigned i = 0; i < 2; i++) {
6274 unsigned interp = info->input_interpolate[color[i]];
6275 unsigned location = info->input_interpolate_loc[color[i]];
6276
6277 if (!(info->colors_read & (0xf << i*4)))
6278 continue;
6279
6280 key->ps_prolog.color_attr_index[i] = color[i];
6281
6282 if (shader->key.part.ps.prolog.flatshade_colors &&
6283 interp == TGSI_INTERPOLATE_COLOR)
6284 interp = TGSI_INTERPOLATE_CONSTANT;
6285
6286 switch (interp) {
6287 case TGSI_INTERPOLATE_CONSTANT:
6288 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6289 break;
6290 case TGSI_INTERPOLATE_PERSPECTIVE:
6291 case TGSI_INTERPOLATE_COLOR:
6292 /* Force the interpolation location for colors here. */
6293 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6294 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6295 if (shader->key.part.ps.prolog.force_persp_center_interp)
6296 location = TGSI_INTERPOLATE_LOC_CENTER;
6297
6298 switch (location) {
6299 case TGSI_INTERPOLATE_LOC_SAMPLE:
6300 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6301 shader->config.spi_ps_input_ena |=
6302 S_0286CC_PERSP_SAMPLE_ENA(1);
6303 break;
6304 case TGSI_INTERPOLATE_LOC_CENTER:
6305 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6306 shader->config.spi_ps_input_ena |=
6307 S_0286CC_PERSP_CENTER_ENA(1);
6308 break;
6309 case TGSI_INTERPOLATE_LOC_CENTROID:
6310 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6311 shader->config.spi_ps_input_ena |=
6312 S_0286CC_PERSP_CENTROID_ENA(1);
6313 break;
6314 default:
6315 assert(0);
6316 }
6317 break;
6318 case TGSI_INTERPOLATE_LINEAR:
6319 /* Force the interpolation location for colors here. */
6320 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6321 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6322 if (shader->key.part.ps.prolog.force_linear_center_interp)
6323 location = TGSI_INTERPOLATE_LOC_CENTER;
6324
6325 /* The VGPR assignment for non-monolithic shaders
6326 * works because InitialPSInputAddr is set on the
6327 * main shader and PERSP_PULL_MODEL is never used.
6328 */
6329 switch (location) {
6330 case TGSI_INTERPOLATE_LOC_SAMPLE:
6331 key->ps_prolog.color_interp_vgpr_index[i] =
6332 separate_prolog ? 6 : 9;
6333 shader->config.spi_ps_input_ena |=
6334 S_0286CC_LINEAR_SAMPLE_ENA(1);
6335 break;
6336 case TGSI_INTERPOLATE_LOC_CENTER:
6337 key->ps_prolog.color_interp_vgpr_index[i] =
6338 separate_prolog ? 8 : 11;
6339 shader->config.spi_ps_input_ena |=
6340 S_0286CC_LINEAR_CENTER_ENA(1);
6341 break;
6342 case TGSI_INTERPOLATE_LOC_CENTROID:
6343 key->ps_prolog.color_interp_vgpr_index[i] =
6344 separate_prolog ? 10 : 13;
6345 shader->config.spi_ps_input_ena |=
6346 S_0286CC_LINEAR_CENTROID_ENA(1);
6347 break;
6348 default:
6349 assert(0);
6350 }
6351 break;
6352 default:
6353 assert(0);
6354 }
6355 }
6356 }
6357 }
6358
6359 /**
6360 * Check whether a PS prolog is required based on the key.
6361 */
6362 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6363 {
6364 return key->ps_prolog.colors_read ||
6365 key->ps_prolog.states.force_persp_sample_interp ||
6366 key->ps_prolog.states.force_linear_sample_interp ||
6367 key->ps_prolog.states.force_persp_center_interp ||
6368 key->ps_prolog.states.force_linear_center_interp ||
6369 key->ps_prolog.states.bc_optimize_for_persp ||
6370 key->ps_prolog.states.bc_optimize_for_linear ||
6371 key->ps_prolog.states.poly_stipple ||
6372 key->ps_prolog.states.samplemask_log_ps_iter;
6373 }
6374
6375 /**
6376 * Compute the PS epilog key, which contains all the information needed to
6377 * build the PS epilog function.
6378 */
6379 static void si_get_ps_epilog_key(struct si_shader *shader,
6380 union si_shader_part_key *key)
6381 {
6382 struct tgsi_shader_info *info = &shader->selector->info;
6383 memset(key, 0, sizeof(*key));
6384 key->ps_epilog.colors_written = info->colors_written;
6385 key->ps_epilog.writes_z = info->writes_z;
6386 key->ps_epilog.writes_stencil = info->writes_stencil;
6387 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6388 key->ps_epilog.states = shader->key.part.ps.epilog;
6389 }
6390
6391 /**
6392 * Build the GS prolog function. Rotate the input vertices for triangle strips
6393 * with adjacency.
6394 */
6395 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6396 union si_shader_part_key *key)
6397 {
6398 unsigned num_sgprs, num_vgprs;
6399 struct si_function_info fninfo;
6400 LLVMBuilderRef builder = ctx->ac.builder;
6401 LLVMTypeRef returns[48];
6402 LLVMValueRef func, ret;
6403
6404 si_init_function_info(&fninfo);
6405
6406 if (ctx->screen->info.chip_class >= GFX9) {
6407 if (key->gs_prolog.states.gfx9_prev_is_vs)
6408 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6409 else
6410 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6411 num_vgprs = 5; /* ES inputs are not needed by GS */
6412 } else {
6413 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6414 num_vgprs = 8;
6415 }
6416
6417 for (unsigned i = 0; i < num_sgprs; ++i) {
6418 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6419 returns[i] = ctx->i32;
6420 }
6421
6422 for (unsigned i = 0; i < num_vgprs; ++i) {
6423 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6424 returns[num_sgprs + i] = ctx->f32;
6425 }
6426
6427 /* Create the function. */
6428 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6429 &fninfo, 0);
6430 func = ctx->main_fn;
6431
6432 /* Set the full EXEC mask for the prolog, because we are only fiddling
6433 * with registers here. The main shader part will set the correct EXEC
6434 * mask.
6435 */
6436 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6437 ac_init_exec_full_mask(&ctx->ac);
6438
6439 /* Copy inputs to outputs. This should be no-op, as the registers match,
6440 * but it will prevent the compiler from overwriting them unintentionally.
6441 */
6442 ret = ctx->return_value;
6443 for (unsigned i = 0; i < num_sgprs; i++) {
6444 LLVMValueRef p = LLVMGetParam(func, i);
6445 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6446 }
6447 for (unsigned i = 0; i < num_vgprs; i++) {
6448 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6449 p = ac_to_float(&ctx->ac, p);
6450 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6451 }
6452
6453 if (key->gs_prolog.states.tri_strip_adj_fix) {
6454 /* Remap the input vertices for every other primitive. */
6455 const unsigned gfx6_vtx_params[6] = {
6456 num_sgprs,
6457 num_sgprs + 1,
6458 num_sgprs + 3,
6459 num_sgprs + 4,
6460 num_sgprs + 5,
6461 num_sgprs + 6
6462 };
6463 const unsigned gfx9_vtx_params[3] = {
6464 num_sgprs,
6465 num_sgprs + 1,
6466 num_sgprs + 4,
6467 };
6468 LLVMValueRef vtx_in[6], vtx_out[6];
6469 LLVMValueRef prim_id, rotate;
6470
6471 if (ctx->screen->info.chip_class >= GFX9) {
6472 for (unsigned i = 0; i < 3; i++) {
6473 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6474 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6475 }
6476 } else {
6477 for (unsigned i = 0; i < 6; i++)
6478 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6479 }
6480
6481 prim_id = LLVMGetParam(func, num_sgprs + 2);
6482 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6483
6484 for (unsigned i = 0; i < 6; ++i) {
6485 LLVMValueRef base, rotated;
6486 base = vtx_in[i];
6487 rotated = vtx_in[(i + 4) % 6];
6488 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6489 }
6490
6491 if (ctx->screen->info.chip_class >= GFX9) {
6492 for (unsigned i = 0; i < 3; i++) {
6493 LLVMValueRef hi, out;
6494
6495 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6496 LLVMConstInt(ctx->i32, 16, 0), "");
6497 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6498 out = ac_to_float(&ctx->ac, out);
6499 ret = LLVMBuildInsertValue(builder, ret, out,
6500 gfx9_vtx_params[i], "");
6501 }
6502 } else {
6503 for (unsigned i = 0; i < 6; i++) {
6504 LLVMValueRef out;
6505
6506 out = ac_to_float(&ctx->ac, vtx_out[i]);
6507 ret = LLVMBuildInsertValue(builder, ret, out,
6508 gfx6_vtx_params[i], "");
6509 }
6510 }
6511 }
6512
6513 LLVMBuildRet(builder, ret);
6514 }
6515
6516 /**
6517 * Given a list of shader part functions, build a wrapper function that
6518 * runs them in sequence to form a monolithic shader.
6519 */
6520 static void si_build_wrapper_function(struct si_shader_context *ctx,
6521 LLVMValueRef *parts,
6522 unsigned num_parts,
6523 unsigned main_part,
6524 unsigned next_shader_first_part)
6525 {
6526 LLVMBuilderRef builder = ctx->ac.builder;
6527 /* PS epilog has one arg per color component; gfx9 merged shader
6528 * prologs need to forward 32 user SGPRs.
6529 */
6530 struct si_function_info fninfo;
6531 LLVMValueRef initial[64], out[64];
6532 LLVMTypeRef function_type;
6533 unsigned num_first_params;
6534 unsigned num_out, initial_num_out;
6535 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6536 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6537 unsigned num_sgprs, num_vgprs;
6538 unsigned gprs;
6539 struct lp_build_if_state if_state;
6540
6541 si_init_function_info(&fninfo);
6542
6543 for (unsigned i = 0; i < num_parts; ++i) {
6544 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6545 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6546 }
6547
6548 /* The parameters of the wrapper function correspond to those of the
6549 * first part in terms of SGPRs and VGPRs, but we use the types of the
6550 * main part to get the right types. This is relevant for the
6551 * dereferenceable attribute on descriptor table pointers.
6552 */
6553 num_sgprs = 0;
6554 num_vgprs = 0;
6555
6556 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6557 num_first_params = LLVMCountParamTypes(function_type);
6558
6559 for (unsigned i = 0; i < num_first_params; ++i) {
6560 LLVMValueRef param = LLVMGetParam(parts[0], i);
6561
6562 if (ac_is_sgpr_param(param)) {
6563 assert(num_vgprs == 0);
6564 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6565 } else {
6566 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6567 }
6568 }
6569
6570 gprs = 0;
6571 while (gprs < num_sgprs + num_vgprs) {
6572 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6573 LLVMTypeRef type = LLVMTypeOf(param);
6574 unsigned size = ac_get_type_size(type) / 4;
6575
6576 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6577
6578 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6579 assert(gprs + size <= num_sgprs + num_vgprs &&
6580 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6581
6582 gprs += size;
6583 }
6584
6585 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6586 si_get_max_workgroup_size(ctx->shader));
6587
6588 if (is_merged_shader(ctx->shader))
6589 ac_init_exec_full_mask(&ctx->ac);
6590
6591 /* Record the arguments of the function as if they were an output of
6592 * a previous part.
6593 */
6594 num_out = 0;
6595 num_out_sgpr = 0;
6596
6597 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6598 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6599 LLVMTypeRef param_type = LLVMTypeOf(param);
6600 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6601 unsigned size = ac_get_type_size(param_type) / 4;
6602
6603 if (size == 1) {
6604 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6605 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6606 param_type = ctx->i32;
6607 }
6608
6609 if (param_type != out_type)
6610 param = LLVMBuildBitCast(builder, param, out_type, "");
6611 out[num_out++] = param;
6612 } else {
6613 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6614
6615 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6616 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6617 param_type = ctx->i64;
6618 }
6619
6620 if (param_type != vector_type)
6621 param = LLVMBuildBitCast(builder, param, vector_type, "");
6622
6623 for (unsigned j = 0; j < size; ++j)
6624 out[num_out++] = LLVMBuildExtractElement(
6625 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6626 }
6627
6628 if (i < fninfo.num_sgpr_params)
6629 num_out_sgpr = num_out;
6630 }
6631
6632 memcpy(initial, out, sizeof(out));
6633 initial_num_out = num_out;
6634 initial_num_out_sgpr = num_out_sgpr;
6635
6636 /* Now chain the parts. */
6637 for (unsigned part = 0; part < num_parts; ++part) {
6638 LLVMValueRef in[48];
6639 LLVMValueRef ret;
6640 LLVMTypeRef ret_type;
6641 unsigned out_idx = 0;
6642 unsigned num_params = LLVMCountParams(parts[part]);
6643
6644 /* Merged shaders are executed conditionally depending
6645 * on the number of enabled threads passed in the input SGPRs. */
6646 if (is_merged_shader(ctx->shader) && part == 0) {
6647 LLVMValueRef ena, count = initial[3];
6648
6649 count = LLVMBuildAnd(builder, count,
6650 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6651 ena = LLVMBuildICmp(builder, LLVMIntULT,
6652 ac_get_thread_id(&ctx->ac), count, "");
6653 lp_build_if(&if_state, &ctx->gallivm, ena);
6654 }
6655
6656 /* Derive arguments for the next part from outputs of the
6657 * previous one.
6658 */
6659 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6660 LLVMValueRef param;
6661 LLVMTypeRef param_type;
6662 bool is_sgpr;
6663 unsigned param_size;
6664 LLVMValueRef arg = NULL;
6665
6666 param = LLVMGetParam(parts[part], param_idx);
6667 param_type = LLVMTypeOf(param);
6668 param_size = ac_get_type_size(param_type) / 4;
6669 is_sgpr = ac_is_sgpr_param(param);
6670
6671 if (is_sgpr)
6672 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6673 else if (out_idx < num_out_sgpr) {
6674 /* Skip returned SGPRs the current part doesn't
6675 * declare on the input. */
6676 out_idx = num_out_sgpr;
6677 }
6678
6679 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6680
6681 if (param_size == 1)
6682 arg = out[out_idx];
6683 else
6684 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6685
6686 if (LLVMTypeOf(arg) != param_type) {
6687 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6688 if (LLVMGetPointerAddressSpace(param_type) ==
6689 AC_CONST_32BIT_ADDR_SPACE) {
6690 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6691 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6692 } else {
6693 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6694 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6695 }
6696 } else {
6697 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6698 }
6699 }
6700
6701 in[param_idx] = arg;
6702 out_idx += param_size;
6703 }
6704
6705 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6706
6707 if (is_merged_shader(ctx->shader) &&
6708 part + 1 == next_shader_first_part) {
6709 lp_build_endif(&if_state);
6710
6711 /* The second half of the merged shader should use
6712 * the inputs from the toplevel (wrapper) function,
6713 * not the return value from the last call.
6714 *
6715 * That's because the last call was executed condi-
6716 * tionally, so we can't consume it in the main
6717 * block.
6718 */
6719 memcpy(out, initial, sizeof(initial));
6720 num_out = initial_num_out;
6721 num_out_sgpr = initial_num_out_sgpr;
6722 continue;
6723 }
6724
6725 /* Extract the returned GPRs. */
6726 ret_type = LLVMTypeOf(ret);
6727 num_out = 0;
6728 num_out_sgpr = 0;
6729
6730 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6731 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6732
6733 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6734
6735 for (unsigned i = 0; i < ret_size; ++i) {
6736 LLVMValueRef val =
6737 LLVMBuildExtractValue(builder, ret, i, "");
6738
6739 assert(num_out < ARRAY_SIZE(out));
6740 out[num_out++] = val;
6741
6742 if (LLVMTypeOf(val) == ctx->i32) {
6743 assert(num_out_sgpr + 1 == num_out);
6744 num_out_sgpr = num_out;
6745 }
6746 }
6747 }
6748 }
6749
6750 LLVMBuildRetVoid(builder);
6751 }
6752
6753 int si_compile_tgsi_shader(struct si_screen *sscreen,
6754 struct si_compiler *compiler,
6755 struct si_shader *shader,
6756 bool is_monolithic,
6757 struct pipe_debug_callback *debug)
6758 {
6759 struct si_shader_selector *sel = shader->selector;
6760 struct si_shader_context ctx;
6761 int r = -1;
6762
6763 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6764 * conversion fails. */
6765 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6766 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6767 if (sel->tokens)
6768 tgsi_dump(sel->tokens, 0);
6769 else
6770 nir_print_shader(sel->nir, stderr);
6771 si_dump_streamout(&sel->so);
6772 }
6773
6774 si_init_shader_ctx(&ctx, sscreen, compiler);
6775 si_llvm_context_set_tgsi(&ctx, shader);
6776 ctx.separate_prolog = !is_monolithic;
6777
6778 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6779 sizeof(shader->info.vs_output_param_offset));
6780
6781 shader->info.uses_instanceid = sel->info.uses_instanceid;
6782
6783 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6784 si_llvm_dispose(&ctx);
6785 return -1;
6786 }
6787
6788 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6789 LLVMValueRef parts[2];
6790 bool need_prolog = sel->vs_needs_prolog;
6791
6792 parts[1] = ctx.main_fn;
6793
6794 if (need_prolog) {
6795 union si_shader_part_key prolog_key;
6796 si_get_vs_prolog_key(&sel->info,
6797 shader->info.num_input_sgprs,
6798 &shader->key.part.vs.prolog,
6799 shader, &prolog_key);
6800 si_build_vs_prolog_function(&ctx, &prolog_key);
6801 parts[0] = ctx.main_fn;
6802 }
6803
6804 si_build_wrapper_function(&ctx, parts + !need_prolog,
6805 1 + need_prolog, need_prolog, 0);
6806 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6807 if (sscreen->info.chip_class >= GFX9) {
6808 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6809 LLVMValueRef parts[4];
6810 bool vs_needs_prolog =
6811 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6812
6813 /* TCS main part */
6814 parts[2] = ctx.main_fn;
6815
6816 /* TCS epilog */
6817 union si_shader_part_key tcs_epilog_key;
6818 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6819 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6820 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6821 parts[3] = ctx.main_fn;
6822
6823 /* VS as LS main part */
6824 struct si_shader shader_ls = {};
6825 shader_ls.selector = ls;
6826 shader_ls.key.as_ls = 1;
6827 shader_ls.key.mono = shader->key.mono;
6828 shader_ls.key.opt = shader->key.opt;
6829 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6830
6831 if (!si_compile_tgsi_main(&ctx, true)) {
6832 si_llvm_dispose(&ctx);
6833 return -1;
6834 }
6835 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6836 parts[1] = ctx.main_fn;
6837
6838 /* LS prolog */
6839 if (vs_needs_prolog) {
6840 union si_shader_part_key vs_prolog_key;
6841 si_get_vs_prolog_key(&ls->info,
6842 shader_ls.info.num_input_sgprs,
6843 &shader->key.part.tcs.ls_prolog,
6844 shader, &vs_prolog_key);
6845 vs_prolog_key.vs_prolog.is_monolithic = true;
6846 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6847 parts[0] = ctx.main_fn;
6848 }
6849
6850 /* Reset the shader context. */
6851 ctx.shader = shader;
6852 ctx.type = PIPE_SHADER_TESS_CTRL;
6853
6854 si_build_wrapper_function(&ctx,
6855 parts + !vs_needs_prolog,
6856 4 - !vs_needs_prolog, vs_needs_prolog,
6857 vs_needs_prolog ? 2 : 1);
6858 } else {
6859 LLVMValueRef parts[2];
6860 union si_shader_part_key epilog_key;
6861
6862 parts[0] = ctx.main_fn;
6863
6864 memset(&epilog_key, 0, sizeof(epilog_key));
6865 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6866 si_build_tcs_epilog_function(&ctx, &epilog_key);
6867 parts[1] = ctx.main_fn;
6868
6869 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6870 }
6871 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6872 if (ctx.screen->info.chip_class >= GFX9) {
6873 struct si_shader_selector *es = shader->key.part.gs.es;
6874 LLVMValueRef es_prolog = NULL;
6875 LLVMValueRef es_main = NULL;
6876 LLVMValueRef gs_prolog = NULL;
6877 LLVMValueRef gs_main = ctx.main_fn;
6878
6879 /* GS prolog */
6880 union si_shader_part_key gs_prolog_key;
6881 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6882 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6883 gs_prolog_key.gs_prolog.is_monolithic = true;
6884 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6885 gs_prolog = ctx.main_fn;
6886
6887 /* ES main part */
6888 struct si_shader shader_es = {};
6889 shader_es.selector = es;
6890 shader_es.key.as_es = 1;
6891 shader_es.key.mono = shader->key.mono;
6892 shader_es.key.opt = shader->key.opt;
6893 si_llvm_context_set_tgsi(&ctx, &shader_es);
6894
6895 if (!si_compile_tgsi_main(&ctx, true)) {
6896 si_llvm_dispose(&ctx);
6897 return -1;
6898 }
6899 shader->info.uses_instanceid |= es->info.uses_instanceid;
6900 es_main = ctx.main_fn;
6901
6902 /* ES prolog */
6903 if (es->vs_needs_prolog) {
6904 union si_shader_part_key vs_prolog_key;
6905 si_get_vs_prolog_key(&es->info,
6906 shader_es.info.num_input_sgprs,
6907 &shader->key.part.gs.vs_prolog,
6908 shader, &vs_prolog_key);
6909 vs_prolog_key.vs_prolog.is_monolithic = true;
6910 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6911 es_prolog = ctx.main_fn;
6912 }
6913
6914 /* Reset the shader context. */
6915 ctx.shader = shader;
6916 ctx.type = PIPE_SHADER_GEOMETRY;
6917
6918 /* Prepare the array of shader parts. */
6919 LLVMValueRef parts[4];
6920 unsigned num_parts = 0, main_part, next_first_part;
6921
6922 if (es_prolog)
6923 parts[num_parts++] = es_prolog;
6924
6925 parts[main_part = num_parts++] = es_main;
6926 parts[next_first_part = num_parts++] = gs_prolog;
6927 parts[num_parts++] = gs_main;
6928
6929 si_build_wrapper_function(&ctx, parts, num_parts,
6930 main_part, next_first_part);
6931 } else {
6932 LLVMValueRef parts[2];
6933 union si_shader_part_key prolog_key;
6934
6935 parts[1] = ctx.main_fn;
6936
6937 memset(&prolog_key, 0, sizeof(prolog_key));
6938 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6939 si_build_gs_prolog_function(&ctx, &prolog_key);
6940 parts[0] = ctx.main_fn;
6941
6942 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6943 }
6944 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6945 LLVMValueRef parts[3];
6946 union si_shader_part_key prolog_key;
6947 union si_shader_part_key epilog_key;
6948 bool need_prolog;
6949
6950 si_get_ps_prolog_key(shader, &prolog_key, false);
6951 need_prolog = si_need_ps_prolog(&prolog_key);
6952
6953 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6954
6955 if (need_prolog) {
6956 si_build_ps_prolog_function(&ctx, &prolog_key);
6957 parts[0] = ctx.main_fn;
6958 }
6959
6960 si_get_ps_epilog_key(shader, &epilog_key);
6961 si_build_ps_epilog_function(&ctx, &epilog_key);
6962 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6963
6964 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6965 need_prolog ? 1 : 0, 0);
6966 }
6967
6968 si_llvm_optimize_module(&ctx);
6969
6970 /* Post-optimization transformations and analysis. */
6971 si_optimize_vs_outputs(&ctx);
6972
6973 if ((debug && debug->debug_message) ||
6974 si_can_dump_shader(sscreen, ctx.type)) {
6975 ctx.shader->config.private_mem_vgprs =
6976 ac_count_scratch_private_memory(ctx.main_fn);
6977 }
6978
6979 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6980 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6981 LLVMPointerTypeKind);
6982
6983 /* Compile to bytecode. */
6984 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6985 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6986 si_llvm_dispose(&ctx);
6987 if (r) {
6988 fprintf(stderr, "LLVM failed to compile shader\n");
6989 return r;
6990 }
6991
6992 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6993 * LLVM 3.9svn has this bug.
6994 */
6995 if (sel->type == PIPE_SHADER_COMPUTE) {
6996 unsigned wave_size = 64;
6997 unsigned max_vgprs = 256;
6998 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6999 unsigned max_sgprs_per_wave = 128;
7000 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7001 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7002 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7003
7004 max_vgprs = max_vgprs / min_waves_per_simd;
7005 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7006
7007 if (shader->config.num_sgprs > max_sgprs ||
7008 shader->config.num_vgprs > max_vgprs) {
7009 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7010 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7011 shader->config.num_sgprs, shader->config.num_vgprs,
7012 max_sgprs, max_vgprs);
7013
7014 /* Just terminate the process, because dependent
7015 * shaders can hang due to bad input data, but use
7016 * the env var to allow shader-db to work.
7017 */
7018 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7019 abort();
7020 }
7021 }
7022
7023 /* Add the scratch offset to input SGPRs. */
7024 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
7025 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7026
7027 /* Calculate the number of fragment input VGPRs. */
7028 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7029 shader->info.num_input_vgprs = 0;
7030 shader->info.face_vgpr_index = -1;
7031 shader->info.ancillary_vgpr_index = -1;
7032
7033 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7034 shader->info.num_input_vgprs += 2;
7035 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7036 shader->info.num_input_vgprs += 2;
7037 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7038 shader->info.num_input_vgprs += 2;
7039 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7040 shader->info.num_input_vgprs += 3;
7041 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7042 shader->info.num_input_vgprs += 2;
7043 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7044 shader->info.num_input_vgprs += 2;
7045 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7046 shader->info.num_input_vgprs += 2;
7047 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7048 shader->info.num_input_vgprs += 1;
7049 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7050 shader->info.num_input_vgprs += 1;
7051 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7052 shader->info.num_input_vgprs += 1;
7053 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7054 shader->info.num_input_vgprs += 1;
7055 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7056 shader->info.num_input_vgprs += 1;
7057 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7058 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7059 shader->info.num_input_vgprs += 1;
7060 }
7061 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7062 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7063 shader->info.num_input_vgprs += 1;
7064 }
7065 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7066 shader->info.num_input_vgprs += 1;
7067 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7068 shader->info.num_input_vgprs += 1;
7069 }
7070
7071 si_calculate_max_simd_waves(shader);
7072 si_shader_dump_stats_for_shader_db(shader, debug);
7073 return 0;
7074 }
7075
7076 /**
7077 * Create, compile and return a shader part (prolog or epilog).
7078 *
7079 * \param sscreen screen
7080 * \param list list of shader parts of the same category
7081 * \param type shader type
7082 * \param key shader part key
7083 * \param prolog whether the part being requested is a prolog
7084 * \param tm LLVM target machine
7085 * \param debug debug callback
7086 * \param build the callback responsible for building the main function
7087 * \return non-NULL on success
7088 */
7089 static struct si_shader_part *
7090 si_get_shader_part(struct si_screen *sscreen,
7091 struct si_shader_part **list,
7092 enum pipe_shader_type type,
7093 bool prolog,
7094 union si_shader_part_key *key,
7095 struct si_compiler *compiler,
7096 struct pipe_debug_callback *debug,
7097 void (*build)(struct si_shader_context *,
7098 union si_shader_part_key *),
7099 const char *name)
7100 {
7101 struct si_shader_part *result;
7102
7103 mtx_lock(&sscreen->shader_parts_mutex);
7104
7105 /* Find existing. */
7106 for (result = *list; result; result = result->next) {
7107 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7108 mtx_unlock(&sscreen->shader_parts_mutex);
7109 return result;
7110 }
7111 }
7112
7113 /* Compile a new one. */
7114 result = CALLOC_STRUCT(si_shader_part);
7115 result->key = *key;
7116
7117 struct si_shader shader = {};
7118 struct si_shader_context ctx;
7119
7120 si_init_shader_ctx(&ctx, sscreen, compiler);
7121 ctx.shader = &shader;
7122 ctx.type = type;
7123
7124 switch (type) {
7125 case PIPE_SHADER_VERTEX:
7126 shader.key.as_ls = key->vs_prolog.as_ls;
7127 shader.key.as_es = key->vs_prolog.as_es;
7128 break;
7129 case PIPE_SHADER_TESS_CTRL:
7130 assert(!prolog);
7131 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7132 break;
7133 case PIPE_SHADER_GEOMETRY:
7134 assert(prolog);
7135 break;
7136 case PIPE_SHADER_FRAGMENT:
7137 if (prolog)
7138 shader.key.part.ps.prolog = key->ps_prolog.states;
7139 else
7140 shader.key.part.ps.epilog = key->ps_epilog.states;
7141 break;
7142 default:
7143 unreachable("bad shader part");
7144 }
7145
7146 build(&ctx, key);
7147
7148 /* Compile. */
7149 si_llvm_optimize_module(&ctx);
7150
7151 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7152 ctx.ac.module, debug, ctx.type, name)) {
7153 FREE(result);
7154 result = NULL;
7155 goto out;
7156 }
7157
7158 result->next = *list;
7159 *list = result;
7160
7161 out:
7162 si_llvm_dispose(&ctx);
7163 mtx_unlock(&sscreen->shader_parts_mutex);
7164 return result;
7165 }
7166
7167 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7168 {
7169 LLVMValueRef ptr[2], list;
7170 bool is_merged_shader =
7171 ctx->screen->info.chip_class >= GFX9 &&
7172 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7173 ctx->type == PIPE_SHADER_GEOMETRY ||
7174 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7175
7176 if (HAVE_32BIT_POINTERS) {
7177 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7178 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7179 ac_array_in_const32_addr_space(ctx->v4i32), "");
7180 return list;
7181 }
7182
7183 /* Get the pointer to rw buffers. */
7184 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7185 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7186 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7187 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7188 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7189 ac_array_in_const_addr_space(ctx->v4i32), "");
7190 return list;
7191 }
7192
7193 /**
7194 * Build the vertex shader prolog function.
7195 *
7196 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7197 * All inputs are returned unmodified. The vertex load indices are
7198 * stored after them, which will be used by the API VS for fetching inputs.
7199 *
7200 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7201 * input_v0,
7202 * input_v1,
7203 * input_v2,
7204 * input_v3,
7205 * (VertexID + BaseVertex),
7206 * (InstanceID + StartInstance),
7207 * (InstanceID / 2 + StartInstance)
7208 */
7209 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7210 union si_shader_part_key *key)
7211 {
7212 struct si_function_info fninfo;
7213 LLVMTypeRef *returns;
7214 LLVMValueRef ret, func;
7215 int num_returns, i;
7216 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7217 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7218 LLVMValueRef input_vgprs[9];
7219 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7220 num_input_vgprs;
7221 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7222
7223 si_init_function_info(&fninfo);
7224
7225 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7226 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7227 sizeof(LLVMTypeRef));
7228 num_returns = 0;
7229
7230 /* Declare input and output SGPRs. */
7231 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7232 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7233 returns[num_returns++] = ctx->i32;
7234 }
7235
7236 /* Preloaded VGPRs (outputs must be floats) */
7237 for (i = 0; i < num_input_vgprs; i++) {
7238 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7239 returns[num_returns++] = ctx->f32;
7240 }
7241
7242 /* Vertex load indices. */
7243 for (i = 0; i <= key->vs_prolog.last_input; i++)
7244 returns[num_returns++] = ctx->f32;
7245
7246 /* Create the function. */
7247 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7248 func = ctx->main_fn;
7249
7250 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7251 if (!key->vs_prolog.is_monolithic)
7252 si_init_exec_from_input(ctx, 3, 0);
7253
7254 if (key->vs_prolog.as_ls &&
7255 ctx->screen->has_ls_vgpr_init_bug) {
7256 /* If there are no HS threads, SPI loads the LS VGPRs
7257 * starting at VGPR 0. Shift them back to where they
7258 * belong.
7259 */
7260 LLVMValueRef has_hs_threads =
7261 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7262 si_unpack_param(ctx, 3, 8, 8),
7263 ctx->i32_0, "");
7264
7265 for (i = 4; i > 0; --i) {
7266 input_vgprs[i + 1] =
7267 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7268 input_vgprs[i + 1],
7269 input_vgprs[i - 1], "");
7270 }
7271 }
7272 }
7273
7274 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7275 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7276
7277 /* Copy inputs to outputs. This should be no-op, as the registers match,
7278 * but it will prevent the compiler from overwriting them unintentionally.
7279 */
7280 ret = ctx->return_value;
7281 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7282 LLVMValueRef p = LLVMGetParam(func, i);
7283 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7284 }
7285 for (i = 0; i < num_input_vgprs; i++) {
7286 LLVMValueRef p = input_vgprs[i];
7287 p = ac_to_float(&ctx->ac, p);
7288 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7289 key->vs_prolog.num_input_sgprs + i, "");
7290 }
7291
7292 /* Compute vertex load indices from instance divisors. */
7293 LLVMValueRef instance_divisor_constbuf = NULL;
7294
7295 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7296 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7297 LLVMValueRef buf_index =
7298 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7299 instance_divisor_constbuf =
7300 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7301 }
7302
7303 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7304 bool divisor_is_one =
7305 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7306 bool divisor_is_fetched =
7307 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7308 LLVMValueRef index;
7309
7310 if (divisor_is_one || divisor_is_fetched) {
7311 LLVMValueRef divisor = ctx->i32_1;
7312
7313 if (divisor_is_fetched) {
7314 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7315 LLVMConstInt(ctx->i32, i * 4, 0));
7316 divisor = ac_to_integer(&ctx->ac, divisor);
7317 }
7318
7319 /* InstanceID / Divisor + StartInstance */
7320 index = get_instance_index_for_fetch(ctx,
7321 user_sgpr_base +
7322 SI_SGPR_START_INSTANCE,
7323 divisor);
7324 } else {
7325 /* VertexID + BaseVertex */
7326 index = LLVMBuildAdd(ctx->ac.builder,
7327 ctx->abi.vertex_id,
7328 LLVMGetParam(func, user_sgpr_base +
7329 SI_SGPR_BASE_VERTEX), "");
7330 }
7331
7332 index = ac_to_float(&ctx->ac, index);
7333 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7334 fninfo.num_params + i, "");
7335 }
7336
7337 si_llvm_build_ret(ctx, ret);
7338 }
7339
7340 static bool si_get_vs_prolog(struct si_screen *sscreen,
7341 struct si_compiler *compiler,
7342 struct si_shader *shader,
7343 struct pipe_debug_callback *debug,
7344 struct si_shader *main_part,
7345 const struct si_vs_prolog_bits *key)
7346 {
7347 struct si_shader_selector *vs = main_part->selector;
7348
7349 if (!si_vs_needs_prolog(vs, key))
7350 return true;
7351
7352 /* Get the prolog. */
7353 union si_shader_part_key prolog_key;
7354 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7355 key, shader, &prolog_key);
7356
7357 shader->prolog =
7358 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7359 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7360 debug, si_build_vs_prolog_function,
7361 "Vertex Shader Prolog");
7362 return shader->prolog != NULL;
7363 }
7364
7365 /**
7366 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7367 */
7368 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7369 struct si_compiler *compiler,
7370 struct si_shader *shader,
7371 struct pipe_debug_callback *debug)
7372 {
7373 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7374 &shader->key.part.vs.prolog);
7375 }
7376
7377 /**
7378 * Compile the TCS epilog function. This writes tesselation factors to memory
7379 * based on the output primitive type of the tesselator (determined by TES).
7380 */
7381 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7382 union si_shader_part_key *key)
7383 {
7384 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7385 struct si_function_info fninfo;
7386 LLVMValueRef func;
7387
7388 si_init_function_info(&fninfo);
7389
7390 if (ctx->screen->info.chip_class >= GFX9) {
7391 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7392 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7393 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7394 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7395 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7396 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7397 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7398 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7399 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7400 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7401 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7402 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7403 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7404 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7405 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7406 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7407 if (!HAVE_32BIT_POINTERS)
7408 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7409 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7410 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7411 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7412 } else {
7413 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7414 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7415 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7416 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7417 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7418 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7419 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7420 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7421 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7422 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7423 }
7424
7425 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7426 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7427 unsigned tess_factors_idx =
7428 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7429 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7430 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7431
7432 for (unsigned i = 0; i < 6; i++)
7433 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7434
7435 /* Create the function. */
7436 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7437 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7438 ac_declare_lds_as_pointer(&ctx->ac);
7439 func = ctx->main_fn;
7440
7441 LLVMValueRef invoc0_tess_factors[6];
7442 for (unsigned i = 0; i < 6; i++)
7443 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7444
7445 si_write_tess_factors(bld_base,
7446 LLVMGetParam(func, tess_factors_idx),
7447 LLVMGetParam(func, tess_factors_idx + 1),
7448 LLVMGetParam(func, tess_factors_idx + 2),
7449 invoc0_tess_factors, invoc0_tess_factors + 4);
7450
7451 LLVMBuildRetVoid(ctx->ac.builder);
7452 }
7453
7454 /**
7455 * Select and compile (or reuse) TCS parts (epilog).
7456 */
7457 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7458 struct si_compiler *compiler,
7459 struct si_shader *shader,
7460 struct pipe_debug_callback *debug)
7461 {
7462 if (sscreen->info.chip_class >= GFX9) {
7463 struct si_shader *ls_main_part =
7464 shader->key.part.tcs.ls->main_shader_part_ls;
7465
7466 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7467 &shader->key.part.tcs.ls_prolog))
7468 return false;
7469
7470 shader->previous_stage = ls_main_part;
7471 }
7472
7473 /* Get the epilog. */
7474 union si_shader_part_key epilog_key;
7475 memset(&epilog_key, 0, sizeof(epilog_key));
7476 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7477
7478 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7479 PIPE_SHADER_TESS_CTRL, false,
7480 &epilog_key, compiler, debug,
7481 si_build_tcs_epilog_function,
7482 "Tessellation Control Shader Epilog");
7483 return shader->epilog != NULL;
7484 }
7485
7486 /**
7487 * Select and compile (or reuse) GS parts (prolog).
7488 */
7489 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7490 struct si_compiler *compiler,
7491 struct si_shader *shader,
7492 struct pipe_debug_callback *debug)
7493 {
7494 if (sscreen->info.chip_class >= GFX9) {
7495 struct si_shader *es_main_part =
7496 shader->key.part.gs.es->main_shader_part_es;
7497
7498 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7499 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7500 &shader->key.part.gs.vs_prolog))
7501 return false;
7502
7503 shader->previous_stage = es_main_part;
7504 }
7505
7506 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7507 return true;
7508
7509 union si_shader_part_key prolog_key;
7510 memset(&prolog_key, 0, sizeof(prolog_key));
7511 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7512
7513 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7514 PIPE_SHADER_GEOMETRY, true,
7515 &prolog_key, compiler, debug,
7516 si_build_gs_prolog_function,
7517 "Geometry Shader Prolog");
7518 return shader->prolog2 != NULL;
7519 }
7520
7521 /**
7522 * Build the pixel shader prolog function. This handles:
7523 * - two-side color selection and interpolation
7524 * - overriding interpolation parameters for the API PS
7525 * - polygon stippling
7526 *
7527 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7528 * overriden by other states. (e.g. per-sample interpolation)
7529 * Interpolated colors are stored after the preloaded VGPRs.
7530 */
7531 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7532 union si_shader_part_key *key)
7533 {
7534 struct si_function_info fninfo;
7535 LLVMValueRef ret, func;
7536 int num_returns, i, num_color_channels;
7537
7538 assert(si_need_ps_prolog(key));
7539
7540 si_init_function_info(&fninfo);
7541
7542 /* Declare inputs. */
7543 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7544 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7545
7546 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7547 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7548
7549 /* Declare outputs (same as inputs + add colors if needed) */
7550 num_returns = fninfo.num_params;
7551 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7552 for (i = 0; i < num_color_channels; i++)
7553 fninfo.types[num_returns++] = ctx->f32;
7554
7555 /* Create the function. */
7556 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7557 &fninfo, 0);
7558 func = ctx->main_fn;
7559
7560 /* Copy inputs to outputs. This should be no-op, as the registers match,
7561 * but it will prevent the compiler from overwriting them unintentionally.
7562 */
7563 ret = ctx->return_value;
7564 for (i = 0; i < fninfo.num_params; i++) {
7565 LLVMValueRef p = LLVMGetParam(func, i);
7566 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7567 }
7568
7569 /* Polygon stippling. */
7570 if (key->ps_prolog.states.poly_stipple) {
7571 /* POS_FIXED_PT is always last. */
7572 unsigned pos = key->ps_prolog.num_input_sgprs +
7573 key->ps_prolog.num_input_vgprs - 1;
7574 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7575
7576 si_llvm_emit_polygon_stipple(ctx, list, pos);
7577 }
7578
7579 if (key->ps_prolog.states.bc_optimize_for_persp ||
7580 key->ps_prolog.states.bc_optimize_for_linear) {
7581 unsigned i, base = key->ps_prolog.num_input_sgprs;
7582 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7583
7584 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7585 * The hw doesn't compute CENTROID if the whole wave only
7586 * contains fully-covered quads.
7587 *
7588 * PRIM_MASK is after user SGPRs.
7589 */
7590 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7591 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7592 LLVMConstInt(ctx->i32, 31, 0), "");
7593 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7594 ctx->i1, "");
7595
7596 if (key->ps_prolog.states.bc_optimize_for_persp) {
7597 /* Read PERSP_CENTER. */
7598 for (i = 0; i < 2; i++)
7599 center[i] = LLVMGetParam(func, base + 2 + i);
7600 /* Read PERSP_CENTROID. */
7601 for (i = 0; i < 2; i++)
7602 centroid[i] = LLVMGetParam(func, base + 4 + i);
7603 /* Select PERSP_CENTROID. */
7604 for (i = 0; i < 2; i++) {
7605 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7606 center[i], centroid[i], "");
7607 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7608 tmp, base + 4 + i, "");
7609 }
7610 }
7611 if (key->ps_prolog.states.bc_optimize_for_linear) {
7612 /* Read LINEAR_CENTER. */
7613 for (i = 0; i < 2; i++)
7614 center[i] = LLVMGetParam(func, base + 8 + i);
7615 /* Read LINEAR_CENTROID. */
7616 for (i = 0; i < 2; i++)
7617 centroid[i] = LLVMGetParam(func, base + 10 + i);
7618 /* Select LINEAR_CENTROID. */
7619 for (i = 0; i < 2; i++) {
7620 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7621 center[i], centroid[i], "");
7622 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7623 tmp, base + 10 + i, "");
7624 }
7625 }
7626 }
7627
7628 /* Force per-sample interpolation. */
7629 if (key->ps_prolog.states.force_persp_sample_interp) {
7630 unsigned i, base = key->ps_prolog.num_input_sgprs;
7631 LLVMValueRef persp_sample[2];
7632
7633 /* Read PERSP_SAMPLE. */
7634 for (i = 0; i < 2; i++)
7635 persp_sample[i] = LLVMGetParam(func, base + i);
7636 /* Overwrite PERSP_CENTER. */
7637 for (i = 0; i < 2; i++)
7638 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7639 persp_sample[i], base + 2 + i, "");
7640 /* Overwrite PERSP_CENTROID. */
7641 for (i = 0; i < 2; i++)
7642 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7643 persp_sample[i], base + 4 + i, "");
7644 }
7645 if (key->ps_prolog.states.force_linear_sample_interp) {
7646 unsigned i, base = key->ps_prolog.num_input_sgprs;
7647 LLVMValueRef linear_sample[2];
7648
7649 /* Read LINEAR_SAMPLE. */
7650 for (i = 0; i < 2; i++)
7651 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7652 /* Overwrite LINEAR_CENTER. */
7653 for (i = 0; i < 2; i++)
7654 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7655 linear_sample[i], base + 8 + i, "");
7656 /* Overwrite LINEAR_CENTROID. */
7657 for (i = 0; i < 2; i++)
7658 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7659 linear_sample[i], base + 10 + i, "");
7660 }
7661
7662 /* Force center interpolation. */
7663 if (key->ps_prolog.states.force_persp_center_interp) {
7664 unsigned i, base = key->ps_prolog.num_input_sgprs;
7665 LLVMValueRef persp_center[2];
7666
7667 /* Read PERSP_CENTER. */
7668 for (i = 0; i < 2; i++)
7669 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7670 /* Overwrite PERSP_SAMPLE. */
7671 for (i = 0; i < 2; i++)
7672 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7673 persp_center[i], base + i, "");
7674 /* Overwrite PERSP_CENTROID. */
7675 for (i = 0; i < 2; i++)
7676 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7677 persp_center[i], base + 4 + i, "");
7678 }
7679 if (key->ps_prolog.states.force_linear_center_interp) {
7680 unsigned i, base = key->ps_prolog.num_input_sgprs;
7681 LLVMValueRef linear_center[2];
7682
7683 /* Read LINEAR_CENTER. */
7684 for (i = 0; i < 2; i++)
7685 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7686 /* Overwrite LINEAR_SAMPLE. */
7687 for (i = 0; i < 2; i++)
7688 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7689 linear_center[i], base + 6 + i, "");
7690 /* Overwrite LINEAR_CENTROID. */
7691 for (i = 0; i < 2; i++)
7692 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7693 linear_center[i], base + 10 + i, "");
7694 }
7695
7696 /* Interpolate colors. */
7697 unsigned color_out_idx = 0;
7698 for (i = 0; i < 2; i++) {
7699 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7700 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7701 key->ps_prolog.face_vgpr_index;
7702 LLVMValueRef interp[2], color[4];
7703 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7704
7705 if (!writemask)
7706 continue;
7707
7708 /* If the interpolation qualifier is not CONSTANT (-1). */
7709 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7710 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7711 key->ps_prolog.color_interp_vgpr_index[i];
7712
7713 /* Get the (i,j) updated by bc_optimize handling. */
7714 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7715 interp_vgpr, "");
7716 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7717 interp_vgpr + 1, "");
7718 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7719 }
7720
7721 /* Use the absolute location of the input. */
7722 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7723
7724 if (key->ps_prolog.states.color_two_side) {
7725 face = LLVMGetParam(func, face_vgpr);
7726 face = ac_to_integer(&ctx->ac, face);
7727 }
7728
7729 interp_fs_input(ctx,
7730 key->ps_prolog.color_attr_index[i],
7731 TGSI_SEMANTIC_COLOR, i,
7732 key->ps_prolog.num_interp_inputs,
7733 key->ps_prolog.colors_read, interp_ij,
7734 prim_mask, face, color);
7735
7736 while (writemask) {
7737 unsigned chan = u_bit_scan(&writemask);
7738 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7739 fninfo.num_params + color_out_idx++, "");
7740 }
7741 }
7742
7743 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7744 * says:
7745 *
7746 * "When per-sample shading is active due to the use of a fragment
7747 * input qualified by sample or due to the use of the gl_SampleID
7748 * or gl_SamplePosition variables, only the bit for the current
7749 * sample is set in gl_SampleMaskIn. When state specifies multiple
7750 * fragment shader invocations for a given fragment, the sample
7751 * mask for any single fragment shader invocation may specify a
7752 * subset of the covered samples for the fragment. In this case,
7753 * the bit corresponding to each covered sample will be set in
7754 * exactly one fragment shader invocation."
7755 *
7756 * The samplemask loaded by hardware is always the coverage of the
7757 * entire pixel/fragment, so mask bits out based on the sample ID.
7758 */
7759 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7760 /* The bit pattern matches that used by fixed function fragment
7761 * processing. */
7762 static const uint16_t ps_iter_masks[] = {
7763 0xffff, /* not used */
7764 0x5555,
7765 0x1111,
7766 0x0101,
7767 0x0001,
7768 };
7769 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7770
7771 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7772 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7773 key->ps_prolog.ancillary_vgpr_index;
7774 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7775 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7776
7777 samplemask = ac_to_integer(&ctx->ac, samplemask);
7778 samplemask = LLVMBuildAnd(
7779 ctx->ac.builder,
7780 samplemask,
7781 LLVMBuildShl(ctx->ac.builder,
7782 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7783 sampleid, ""),
7784 "");
7785 samplemask = ac_to_float(&ctx->ac, samplemask);
7786
7787 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7788 ancillary_vgpr + 1, "");
7789 }
7790
7791 /* Tell LLVM to insert WQM instruction sequence when needed. */
7792 if (key->ps_prolog.wqm) {
7793 LLVMAddTargetDependentFunctionAttr(func,
7794 "amdgpu-ps-wqm-outputs", "");
7795 }
7796
7797 si_llvm_build_ret(ctx, ret);
7798 }
7799
7800 /**
7801 * Build the pixel shader epilog function. This handles everything that must be
7802 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7803 */
7804 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7805 union si_shader_part_key *key)
7806 {
7807 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7808 struct si_function_info fninfo;
7809 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7810 int i;
7811 struct si_ps_exports exp = {};
7812
7813 si_init_function_info(&fninfo);
7814
7815 /* Declare input SGPRs. */
7816 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7817 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7818 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7819 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7820 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7821
7822 /* Declare input VGPRs. */
7823 unsigned required_num_params =
7824 fninfo.num_sgpr_params +
7825 util_bitcount(key->ps_epilog.colors_written) * 4 +
7826 key->ps_epilog.writes_z +
7827 key->ps_epilog.writes_stencil +
7828 key->ps_epilog.writes_samplemask;
7829
7830 required_num_params = MAX2(required_num_params,
7831 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7832
7833 while (fninfo.num_params < required_num_params)
7834 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7835
7836 /* Create the function. */
7837 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7838 /* Disable elimination of unused inputs. */
7839 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7840 "InitialPSInputAddr", 0xffffff);
7841
7842 /* Process colors. */
7843 unsigned vgpr = fninfo.num_sgpr_params;
7844 unsigned colors_written = key->ps_epilog.colors_written;
7845 int last_color_export = -1;
7846
7847 /* Find the last color export. */
7848 if (!key->ps_epilog.writes_z &&
7849 !key->ps_epilog.writes_stencil &&
7850 !key->ps_epilog.writes_samplemask) {
7851 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7852
7853 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7854 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7855 /* Just set this if any of the colorbuffers are enabled. */
7856 if (spi_format &
7857 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7858 last_color_export = 0;
7859 } else {
7860 for (i = 0; i < 8; i++)
7861 if (colors_written & (1 << i) &&
7862 (spi_format >> (i * 4)) & 0xf)
7863 last_color_export = i;
7864 }
7865 }
7866
7867 while (colors_written) {
7868 LLVMValueRef color[4];
7869 int mrt = u_bit_scan(&colors_written);
7870
7871 for (i = 0; i < 4; i++)
7872 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7873
7874 si_export_mrt_color(bld_base, color, mrt,
7875 fninfo.num_params - 1,
7876 mrt == last_color_export, &exp);
7877 }
7878
7879 /* Process depth, stencil, samplemask. */
7880 if (key->ps_epilog.writes_z)
7881 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7882 if (key->ps_epilog.writes_stencil)
7883 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7884 if (key->ps_epilog.writes_samplemask)
7885 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7886
7887 if (depth || stencil || samplemask)
7888 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7889 else if (last_color_export == -1)
7890 ac_build_export_null(&ctx->ac);
7891
7892 if (exp.num)
7893 si_emit_ps_exports(ctx, &exp);
7894
7895 /* Compile. */
7896 LLVMBuildRetVoid(ctx->ac.builder);
7897 }
7898
7899 /**
7900 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7901 */
7902 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7903 struct si_compiler *compiler,
7904 struct si_shader *shader,
7905 struct pipe_debug_callback *debug)
7906 {
7907 union si_shader_part_key prolog_key;
7908 union si_shader_part_key epilog_key;
7909
7910 /* Get the prolog. */
7911 si_get_ps_prolog_key(shader, &prolog_key, true);
7912
7913 /* The prolog is a no-op if these aren't set. */
7914 if (si_need_ps_prolog(&prolog_key)) {
7915 shader->prolog =
7916 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7917 PIPE_SHADER_FRAGMENT, true,
7918 &prolog_key, compiler, debug,
7919 si_build_ps_prolog_function,
7920 "Fragment Shader Prolog");
7921 if (!shader->prolog)
7922 return false;
7923 }
7924
7925 /* Get the epilog. */
7926 si_get_ps_epilog_key(shader, &epilog_key);
7927
7928 shader->epilog =
7929 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7930 PIPE_SHADER_FRAGMENT, false,
7931 &epilog_key, compiler, debug,
7932 si_build_ps_epilog_function,
7933 "Fragment Shader Epilog");
7934 if (!shader->epilog)
7935 return false;
7936
7937 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7938 if (shader->key.part.ps.prolog.poly_stipple) {
7939 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7940 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7941 }
7942
7943 /* Set up the enable bits for per-sample shading if needed. */
7944 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7945 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7946 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7947 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7948 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7949 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7950 }
7951 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7952 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7953 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7954 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7955 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7956 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7957 }
7958 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7959 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7960 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7961 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7962 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7963 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7964 }
7965 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7966 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7967 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7968 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7969 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7970 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7971 }
7972
7973 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7974 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7975 !(shader->config.spi_ps_input_ena & 0xf)) {
7976 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7977 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7978 }
7979
7980 /* At least one pair of interpolation weights must be enabled. */
7981 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7982 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7983 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7984 }
7985
7986 /* Samplemask fixup requires the sample ID. */
7987 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7988 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7989 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7990 }
7991
7992 /* The sample mask input is always enabled, because the API shader always
7993 * passes it through to the epilog. Disable it here if it's unused.
7994 */
7995 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7996 !shader->selector->info.reads_samplemask)
7997 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7998
7999 return true;
8000 }
8001
8002 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8003 unsigned *lds_size)
8004 {
8005 /* If tessellation is all offchip and on-chip GS isn't used, this
8006 * workaround is not needed.
8007 */
8008 return;
8009
8010 /* SPI barrier management bug:
8011 * Make sure we have at least 4k of LDS in use to avoid the bug.
8012 * It applies to workgroup sizes of more than one wavefront.
8013 */
8014 if (sscreen->info.family == CHIP_BONAIRE ||
8015 sscreen->info.family == CHIP_KABINI ||
8016 sscreen->info.family == CHIP_MULLINS)
8017 *lds_size = MAX2(*lds_size, 8);
8018 }
8019
8020 static void si_fix_resource_usage(struct si_screen *sscreen,
8021 struct si_shader *shader)
8022 {
8023 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8024
8025 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8026
8027 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8028 si_get_max_workgroup_size(shader) > 64) {
8029 si_multiwave_lds_size_workaround(sscreen,
8030 &shader->config.lds_size);
8031 }
8032 }
8033
8034 int si_shader_create(struct si_screen *sscreen, struct si_compiler *compiler,
8035 struct si_shader *shader,
8036 struct pipe_debug_callback *debug)
8037 {
8038 struct si_shader_selector *sel = shader->selector;
8039 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8040 int r;
8041
8042 /* LS, ES, VS are compiled on demand if the main part hasn't been
8043 * compiled for that stage.
8044 *
8045 * Vertex shaders are compiled on demand when a vertex fetch
8046 * workaround must be applied.
8047 */
8048 if (shader->is_monolithic) {
8049 /* Monolithic shader (compiled as a whole, has many variants,
8050 * may take a long time to compile).
8051 */
8052 r = si_compile_tgsi_shader(sscreen, compiler, shader, true, debug);
8053 if (r)
8054 return r;
8055 } else {
8056 /* The shader consists of several parts:
8057 *
8058 * - the middle part is the user shader, it has 1 variant only
8059 * and it was compiled during the creation of the shader
8060 * selector
8061 * - the prolog part is inserted at the beginning
8062 * - the epilog part is inserted at the end
8063 *
8064 * The prolog and epilog have many (but simple) variants.
8065 *
8066 * Starting with gfx9, geometry and tessellation control
8067 * shaders also contain the prolog and user shader parts of
8068 * the previous shader stage.
8069 */
8070
8071 if (!mainp)
8072 return -1;
8073
8074 /* Copy the compiled TGSI shader data over. */
8075 shader->is_binary_shared = true;
8076 shader->binary = mainp->binary;
8077 shader->config = mainp->config;
8078 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8079 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8080 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8081 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8082 memcpy(shader->info.vs_output_param_offset,
8083 mainp->info.vs_output_param_offset,
8084 sizeof(mainp->info.vs_output_param_offset));
8085 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8086 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8087 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8088
8089 /* Select prologs and/or epilogs. */
8090 switch (sel->type) {
8091 case PIPE_SHADER_VERTEX:
8092 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8093 return -1;
8094 break;
8095 case PIPE_SHADER_TESS_CTRL:
8096 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8097 return -1;
8098 break;
8099 case PIPE_SHADER_TESS_EVAL:
8100 break;
8101 case PIPE_SHADER_GEOMETRY:
8102 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8103 return -1;
8104 break;
8105 case PIPE_SHADER_FRAGMENT:
8106 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8107 return -1;
8108
8109 /* Make sure we have at least as many VGPRs as there
8110 * are allocated inputs.
8111 */
8112 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8113 shader->info.num_input_vgprs);
8114 break;
8115 }
8116
8117 /* Update SGPR and VGPR counts. */
8118 if (shader->prolog) {
8119 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8120 shader->prolog->config.num_sgprs);
8121 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8122 shader->prolog->config.num_vgprs);
8123 }
8124 if (shader->previous_stage) {
8125 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8126 shader->previous_stage->config.num_sgprs);
8127 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8128 shader->previous_stage->config.num_vgprs);
8129 shader->config.spilled_sgprs =
8130 MAX2(shader->config.spilled_sgprs,
8131 shader->previous_stage->config.spilled_sgprs);
8132 shader->config.spilled_vgprs =
8133 MAX2(shader->config.spilled_vgprs,
8134 shader->previous_stage->config.spilled_vgprs);
8135 shader->config.private_mem_vgprs =
8136 MAX2(shader->config.private_mem_vgprs,
8137 shader->previous_stage->config.private_mem_vgprs);
8138 shader->config.scratch_bytes_per_wave =
8139 MAX2(shader->config.scratch_bytes_per_wave,
8140 shader->previous_stage->config.scratch_bytes_per_wave);
8141 shader->info.uses_instanceid |=
8142 shader->previous_stage->info.uses_instanceid;
8143 }
8144 if (shader->prolog2) {
8145 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8146 shader->prolog2->config.num_sgprs);
8147 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8148 shader->prolog2->config.num_vgprs);
8149 }
8150 if (shader->epilog) {
8151 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8152 shader->epilog->config.num_sgprs);
8153 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8154 shader->epilog->config.num_vgprs);
8155 }
8156 si_calculate_max_simd_waves(shader);
8157 }
8158
8159 si_fix_resource_usage(sscreen, shader);
8160 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8161 stderr, true);
8162
8163 /* Upload. */
8164 r = si_shader_binary_upload(sscreen, shader);
8165 if (r) {
8166 fprintf(stderr, "LLVM failed to upload shader\n");
8167 return r;
8168 }
8169
8170 return 0;
8171 }
8172
8173 void si_shader_destroy(struct si_shader *shader)
8174 {
8175 if (shader->scratch_bo)
8176 r600_resource_reference(&shader->scratch_bo, NULL);
8177
8178 r600_resource_reference(&shader->bo, NULL);
8179
8180 if (!shader->is_binary_shared)
8181 ac_shader_binary_clean(&shader->binary);
8182
8183 free(shader->shader_log);
8184 }