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amd: remove support for LLVM 6.0
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_util.h"
29 #include "tgsi/tgsi_dump.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_llvm_util.h"
34 #include "si_shader_internal.h"
35 #include "si_pipe.h"
36 #include "sid.h"
37
38 #include "compiler/nir/nir.h"
39
40 static const char *scratch_rsrc_dword0_symbol =
41 "SCRATCH_RSRC_DWORD0";
42
43 static const char *scratch_rsrc_dword1_symbol =
44 "SCRATCH_RSRC_DWORD1";
45
46 struct si_shader_output_values
47 {
48 LLVMValueRef values[4];
49 unsigned semantic_name;
50 unsigned semantic_index;
51 ubyte vertex_stream[4];
52 };
53
54 /**
55 * Used to collect types and other info about arguments of the LLVM function
56 * before the function is created.
57 */
58 struct si_function_info {
59 LLVMTypeRef types[100];
60 LLVMValueRef *assign[100];
61 unsigned num_sgpr_params;
62 unsigned num_params;
63 };
64
65 enum si_arg_regfile {
66 ARG_SGPR,
67 ARG_VGPR
68 };
69
70 static void si_init_shader_ctx(struct si_shader_context *ctx,
71 struct si_screen *sscreen,
72 struct ac_llvm_compiler *compiler);
73
74 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
75 struct lp_build_tgsi_context *bld_base,
76 struct lp_build_emit_data *emit_data);
77
78 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
79 FILE *f);
80
81 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89
90 /* Ideally pass the sample mask input to the PS epilog as v14, which
91 * is its usual location, so that the shader doesn't have to add v_mov.
92 */
93 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
94
95 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
96 LLVMTypeRef type)
97 {
98 if (type == ctx->ac.i64 || type == ctx->ac.f64)
99 return true;
100
101 return false;
102 }
103
104 static bool is_merged_shader(struct si_shader_context *ctx)
105 {
106 if (ctx->screen->info.chip_class <= VI)
107 return false;
108
109 return ctx->shader->key.as_ls ||
110 ctx->shader->key.as_es ||
111 ctx->type == PIPE_SHADER_TESS_CTRL ||
112 ctx->type == PIPE_SHADER_GEOMETRY;
113 }
114
115 static void si_init_function_info(struct si_function_info *fninfo)
116 {
117 fninfo->num_params = 0;
118 fninfo->num_sgpr_params = 0;
119 }
120
121 static unsigned add_arg_assign(struct si_function_info *fninfo,
122 enum si_arg_regfile regfile, LLVMTypeRef type,
123 LLVMValueRef *assign)
124 {
125 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
126
127 unsigned idx = fninfo->num_params++;
128 assert(idx < ARRAY_SIZE(fninfo->types));
129
130 if (regfile == ARG_SGPR)
131 fninfo->num_sgpr_params = fninfo->num_params;
132
133 fninfo->types[idx] = type;
134 fninfo->assign[idx] = assign;
135 return idx;
136 }
137
138 static unsigned add_arg(struct si_function_info *fninfo,
139 enum si_arg_regfile regfile, LLVMTypeRef type)
140 {
141 return add_arg_assign(fninfo, regfile, type, NULL);
142 }
143
144 static void add_arg_assign_checked(struct si_function_info *fninfo,
145 enum si_arg_regfile regfile, LLVMTypeRef type,
146 LLVMValueRef *assign, unsigned idx)
147 {
148 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
149 assert(actual == idx);
150 }
151
152 static void add_arg_checked(struct si_function_info *fninfo,
153 enum si_arg_regfile regfile, LLVMTypeRef type,
154 unsigned idx)
155 {
156 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
157 }
158
159 /**
160 * Returns a unique index for a per-patch semantic name and index. The index
161 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
162 * can be calculated.
163 */
164 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
165 {
166 switch (semantic_name) {
167 case TGSI_SEMANTIC_TESSOUTER:
168 return 0;
169 case TGSI_SEMANTIC_TESSINNER:
170 return 1;
171 case TGSI_SEMANTIC_PATCH:
172 assert(index < 30);
173 return 2 + index;
174
175 default:
176 assert(!"invalid semantic name");
177 return 0;
178 }
179 }
180
181 /**
182 * Returns a unique index for a semantic name and index. The index must be
183 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
184 * calculated.
185 */
186 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
187 unsigned is_varying)
188 {
189 switch (semantic_name) {
190 case TGSI_SEMANTIC_POSITION:
191 return 0;
192 case TGSI_SEMANTIC_GENERIC:
193 /* Since some shader stages use the the highest used IO index
194 * to determine the size to allocate for inputs/outputs
195 * (in LDS, tess and GS rings). GENERIC should be placed right
196 * after POSITION to make that size as small as possible.
197 */
198 if (index < SI_MAX_IO_GENERIC)
199 return 1 + index;
200
201 assert(!"invalid generic index");
202 return 0;
203 case TGSI_SEMANTIC_PSIZE:
204 return SI_MAX_IO_GENERIC + 1;
205 case TGSI_SEMANTIC_CLIPDIST:
206 assert(index <= 1);
207 return SI_MAX_IO_GENERIC + 2 + index;
208 case TGSI_SEMANTIC_FOG:
209 return SI_MAX_IO_GENERIC + 4;
210 case TGSI_SEMANTIC_LAYER:
211 return SI_MAX_IO_GENERIC + 5;
212 case TGSI_SEMANTIC_VIEWPORT_INDEX:
213 return SI_MAX_IO_GENERIC + 6;
214 case TGSI_SEMANTIC_PRIMID:
215 return SI_MAX_IO_GENERIC + 7;
216 case TGSI_SEMANTIC_COLOR:
217 assert(index < 2);
218 return SI_MAX_IO_GENERIC + 8 + index;
219 case TGSI_SEMANTIC_BCOLOR:
220 assert(index < 2);
221 /* If it's a varying, COLOR and BCOLOR alias. */
222 if (is_varying)
223 return SI_MAX_IO_GENERIC + 8 + index;
224 else
225 return SI_MAX_IO_GENERIC + 10 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
229 return SI_MAX_IO_GENERIC + 12 + index;
230 case TGSI_SEMANTIC_CLIPVERTEX:
231 return 63;
232 default:
233 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
234 assert(!"invalid semantic name");
235 return 0;
236 }
237 }
238
239 /**
240 * Get the value of a shader input parameter and extract a bitfield.
241 */
242 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
243 LLVMValueRef value, unsigned rshift,
244 unsigned bitwidth)
245 {
246 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
247 value = ac_to_integer(&ctx->ac, value);
248
249 if (rshift)
250 value = LLVMBuildLShr(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, rshift, 0), "");
252
253 if (rshift + bitwidth < 32) {
254 unsigned mask = (1 << bitwidth) - 1;
255 value = LLVMBuildAnd(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, mask, 0), "");
257 }
258
259 return value;
260 }
261
262 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
263 unsigned param, unsigned rshift,
264 unsigned bitwidth)
265 {
266 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
267
268 return unpack_llvm_param(ctx, value, rshift, bitwidth);
269 }
270
271 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
272 {
273 switch (ctx->type) {
274 case PIPE_SHADER_TESS_CTRL:
275 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
276
277 case PIPE_SHADER_TESS_EVAL:
278 return LLVMGetParam(ctx->main_fn,
279 ctx->param_tes_rel_patch_id);
280
281 default:
282 assert(0);
283 return NULL;
284 }
285 }
286
287 /* Tessellation shaders pass outputs to the next shader using LDS.
288 *
289 * LS outputs = TCS inputs
290 * TCS outputs = TES inputs
291 *
292 * The LDS layout is:
293 * - TCS inputs for patch 0
294 * - TCS inputs for patch 1
295 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
296 * - ...
297 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
298 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
299 * - TCS outputs for patch 1
300 * - Per-patch TCS outputs for patch 1
301 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
302 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
303 * - ...
304 *
305 * All three shaders VS(LS), TCS, TES share the same LDS space.
306 */
307
308 static LLVMValueRef
309 get_tcs_in_patch_stride(struct si_shader_context *ctx)
310 {
311 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
312 }
313
314 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
315 {
316 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
317
318 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
319 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
320
321 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
322 }
323
324 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
325 {
326 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
327
328 return LLVMConstInt(ctx->i32, stride, 0);
329 }
330
331 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
332 {
333 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
334 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
335
336 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
337 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
338 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
339 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
340 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
341 num_patch_outputs * 4;
342 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
343 }
344
345 static LLVMValueRef
346 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
347 {
348 return LLVMBuildMul(ctx->ac.builder,
349 si_unpack_param(ctx,
350 ctx->param_tcs_out_lds_offsets,
351 0, 16),
352 LLVMConstInt(ctx->i32, 4, 0), "");
353 }
354
355 static LLVMValueRef
356 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
357 {
358 return LLVMBuildMul(ctx->ac.builder,
359 si_unpack_param(ctx,
360 ctx->param_tcs_out_lds_offsets,
361 16, 16),
362 LLVMConstInt(ctx->i32, 4, 0), "");
363 }
364
365 static LLVMValueRef
366 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
367 {
368 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
369 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
370
371 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
372 }
373
374 static LLVMValueRef
375 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
376 {
377 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
393 }
394
395 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
396 {
397 unsigned tcs_out_vertices =
398 ctx->shader->selector ?
399 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
400
401 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
402 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
403 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
404
405 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
406 }
407
408 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
409 {
410 unsigned stride;
411
412 switch (ctx->type) {
413 case PIPE_SHADER_VERTEX:
414 stride = ctx->shader->selector->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416
417 case PIPE_SHADER_TESS_CTRL:
418 if (ctx->screen->info.chip_class >= GFX9 &&
419 ctx->shader->is_monolithic) {
420 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
421 return LLVMConstInt(ctx->i32, stride, 0);
422 }
423 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
424
425 default:
426 assert(0);
427 return NULL;
428 }
429 }
430
431 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
432 * to float. */
433 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
434 LLVMValueRef vec4,
435 unsigned double_index)
436 {
437 LLVMBuilderRef builder = ctx->ac.builder;
438 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
439 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
440 LLVMVectorType(f64, 2), "");
441 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
442 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
443 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
444 }
445
446 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
447 LLVMValueRef i32, unsigned index)
448 {
449 assert(index <= 1);
450
451 if (index == 1)
452 return LLVMBuildAShr(ctx->ac.builder, i32,
453 LLVMConstInt(ctx->i32, 16, 0), "");
454
455 return LLVMBuildSExt(ctx->ac.builder,
456 LLVMBuildTrunc(ctx->ac.builder, i32,
457 ctx->ac.i16, ""),
458 ctx->i32, "");
459 }
460
461 void si_llvm_load_input_vs(
462 struct si_shader_context *ctx,
463 unsigned input_index,
464 LLVMValueRef out[4])
465 {
466 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
467 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
468
469 if (vs_blit_property) {
470 LLVMValueRef vertex_id = ctx->abi.vertex_id;
471 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
472 LLVMIntULE, vertex_id,
473 ctx->i32_1, "");
474 /* Use LLVMIntNE, because we have 3 vertices and only
475 * the middle one should use y2.
476 */
477 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
478 LLVMIntNE, vertex_id,
479 ctx->i32_1, "");
480
481 if (input_index == 0) {
482 /* Position: */
483 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
484 ctx->param_vs_blit_inputs);
485 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_blit_inputs + 1);
487
488 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
489 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
490 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
491 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
492
493 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
494 x1, x2, "");
495 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
496 y1, y2, "");
497
498 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
499 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
500 out[2] = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs + 2);
502 out[3] = ctx->ac.f32_1;
503 return;
504 }
505
506 /* Color or texture coordinates: */
507 assert(input_index == 1);
508
509 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
510 for (int i = 0; i < 4; i++) {
511 out[i] = LLVMGetParam(ctx->main_fn,
512 ctx->param_vs_blit_inputs + 3 + i);
513 }
514 } else {
515 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
516 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
517 ctx->param_vs_blit_inputs + 3);
518 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
519 ctx->param_vs_blit_inputs + 4);
520 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
521 ctx->param_vs_blit_inputs + 5);
522 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 6);
524
525 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
526 x1, x2, "");
527 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
528 y1, y2, "");
529 out[2] = LLVMGetParam(ctx->main_fn,
530 ctx->param_vs_blit_inputs + 7);
531 out[3] = LLVMGetParam(ctx->main_fn,
532 ctx->param_vs_blit_inputs + 8);
533 }
534 return;
535 }
536
537 unsigned chan;
538 unsigned fix_fetch;
539 unsigned num_fetches;
540 unsigned fetch_stride;
541 unsigned num_channels;
542
543 LLVMValueRef t_list_ptr;
544 LLVMValueRef t_offset;
545 LLVMValueRef t_list;
546 LLVMValueRef vertex_index;
547 LLVMValueRef input[3];
548
549 /* Load the T list */
550 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
551
552 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
553
554 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
555
556 vertex_index = LLVMGetParam(ctx->main_fn,
557 ctx->param_vertex_index0 +
558 input_index);
559
560 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
561
562 /* Do multiple loads for special formats. */
563 switch (fix_fetch) {
564 case SI_FIX_FETCH_RGB_64_FLOAT:
565 num_fetches = 3; /* 3 2-dword loads */
566 fetch_stride = 8;
567 num_channels = 2;
568 break;
569 case SI_FIX_FETCH_RGBA_64_FLOAT:
570 num_fetches = 2; /* 2 4-dword loads */
571 fetch_stride = 16;
572 num_channels = 4;
573 break;
574 case SI_FIX_FETCH_RGB_8:
575 case SI_FIX_FETCH_RGB_8_INT:
576 num_fetches = 3;
577 fetch_stride = 1;
578 num_channels = 1;
579 break;
580 case SI_FIX_FETCH_RGB_16:
581 case SI_FIX_FETCH_RGB_16_INT:
582 num_fetches = 3;
583 fetch_stride = 2;
584 num_channels = 1;
585 break;
586 default:
587 num_fetches = 1;
588 fetch_stride = 0;
589 num_channels = util_last_bit(info->input_usage_mask[input_index]);
590 }
591
592 for (unsigned i = 0; i < num_fetches; i++) {
593 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
594
595 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
596 vertex_index, voffset,
597 num_channels, false, true);
598 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
599 }
600
601 /* Break up the vec4 into individual components */
602 for (chan = 0; chan < 4; chan++) {
603 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
604 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
605 input[0], llvm_chan, "");
606 }
607
608 switch (fix_fetch) {
609 case SI_FIX_FETCH_A2_SNORM:
610 case SI_FIX_FETCH_A2_SSCALED:
611 case SI_FIX_FETCH_A2_SINT: {
612 /* The hardware returns an unsigned value; convert it to a
613 * signed one.
614 */
615 LLVMValueRef tmp = out[3];
616 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
617
618 /* First, recover the sign-extended signed integer value. */
619 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
620 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
621 else
622 tmp = ac_to_integer(&ctx->ac, tmp);
623
624 /* For the integer-like cases, do a natural sign extension.
625 *
626 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
627 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
628 * exponent.
629 */
630 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
631 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
632 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
633 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
634
635 /* Convert back to the right type. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
637 LLVMValueRef clamp;
638 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
639 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
640 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
641 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
642 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
643 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
644 }
645
646 out[3] = tmp;
647 break;
648 }
649 case SI_FIX_FETCH_RGBA_32_UNORM:
650 case SI_FIX_FETCH_RGBX_32_UNORM:
651 for (chan = 0; chan < 4; chan++) {
652 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
653 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
654 out[chan], ctx->f32, "");
655 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
656 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
657 }
658 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
659 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
660 out[3] = LLVMConstReal(ctx->f32, 1);
661 break;
662 case SI_FIX_FETCH_RGBA_32_SNORM:
663 case SI_FIX_FETCH_RGBX_32_SNORM:
664 case SI_FIX_FETCH_RGBA_32_FIXED:
665 case SI_FIX_FETCH_RGBX_32_FIXED: {
666 double scale;
667 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
668 scale = 1.0 / 0x10000;
669 else
670 scale = 1.0 / INT_MAX;
671
672 for (chan = 0; chan < 4; chan++) {
673 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
674 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
675 out[chan], ctx->f32, "");
676 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
677 LLVMConstReal(ctx->f32, scale), "");
678 }
679 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
680 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
681 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
682 out[3] = LLVMConstReal(ctx->f32, 1);
683 break;
684 }
685 case SI_FIX_FETCH_RGBA_32_USCALED:
686 for (chan = 0; chan < 4; chan++) {
687 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
688 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
689 out[chan], ctx->f32, "");
690 }
691 break;
692 case SI_FIX_FETCH_RGBA_32_SSCALED:
693 for (chan = 0; chan < 4; chan++) {
694 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
695 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
696 out[chan], ctx->f32, "");
697 }
698 break;
699 case SI_FIX_FETCH_RG_64_FLOAT:
700 for (chan = 0; chan < 2; chan++)
701 out[chan] = extract_double_to_float(ctx, input[0], chan);
702
703 out[2] = LLVMConstReal(ctx->f32, 0);
704 out[3] = LLVMConstReal(ctx->f32, 1);
705 break;
706 case SI_FIX_FETCH_RGB_64_FLOAT:
707 for (chan = 0; chan < 3; chan++)
708 out[chan] = extract_double_to_float(ctx, input[chan], 0);
709
710 out[3] = LLVMConstReal(ctx->f32, 1);
711 break;
712 case SI_FIX_FETCH_RGBA_64_FLOAT:
713 for (chan = 0; chan < 4; chan++) {
714 out[chan] = extract_double_to_float(ctx, input[chan / 2],
715 chan % 2);
716 }
717 break;
718 case SI_FIX_FETCH_RGB_8:
719 case SI_FIX_FETCH_RGB_8_INT:
720 case SI_FIX_FETCH_RGB_16:
721 case SI_FIX_FETCH_RGB_16_INT:
722 for (chan = 0; chan < 3; chan++) {
723 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
724 input[chan],
725 ctx->i32_0, "");
726 }
727 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
728 fix_fetch == SI_FIX_FETCH_RGB_16) {
729 out[3] = LLVMConstReal(ctx->f32, 1);
730 } else {
731 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
732 }
733 break;
734 }
735 }
736
737 static void declare_input_vs(
738 struct si_shader_context *ctx,
739 unsigned input_index,
740 const struct tgsi_full_declaration *decl,
741 LLVMValueRef out[4])
742 {
743 si_llvm_load_input_vs(ctx, input_index, out);
744 }
745
746 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
747 unsigned swizzle)
748 {
749 if (swizzle > 0)
750 return ctx->i32_0;
751
752 switch (ctx->type) {
753 case PIPE_SHADER_VERTEX:
754 return LLVMGetParam(ctx->main_fn,
755 ctx->param_vs_prim_id);
756 case PIPE_SHADER_TESS_CTRL:
757 return ctx->abi.tcs_patch_id;
758 case PIPE_SHADER_TESS_EVAL:
759 return ctx->abi.tes_patch_id;
760 case PIPE_SHADER_GEOMETRY:
761 return ctx->abi.gs_prim_id;
762 default:
763 assert(0);
764 return ctx->i32_0;
765 }
766 }
767
768 /**
769 * Return the value of tgsi_ind_register for indexing.
770 * This is the indirect index with the constant offset added to it.
771 */
772 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
773 const struct tgsi_ind_register *ind,
774 unsigned addr_mul,
775 int rel_index)
776 {
777 LLVMValueRef result;
778
779 if (ind->File == TGSI_FILE_ADDRESS) {
780 result = ctx->addrs[ind->Index][ind->Swizzle];
781 result = LLVMBuildLoad(ctx->ac.builder, result, "");
782 } else {
783 struct tgsi_full_src_register src = {};
784
785 src.Register.File = ind->File;
786 src.Register.Index = ind->Index;
787
788 /* Set the second index to 0 for constants. */
789 if (ind->File == TGSI_FILE_CONSTANT)
790 src.Register.Dimension = 1;
791
792 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
793 TGSI_TYPE_SIGNED,
794 ind->Swizzle);
795 result = ac_to_integer(&ctx->ac, result);
796 }
797
798 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
799 LLVMConstInt(ctx->i32, rel_index, 0));
800 }
801
802 /**
803 * Like si_get_indirect_index, but restricts the return value to a (possibly
804 * undefined) value inside [0..num).
805 */
806 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
807 const struct tgsi_ind_register *ind,
808 int rel_index, unsigned num)
809 {
810 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
811
812 return si_llvm_bound_index(ctx, result, num);
813 }
814
815 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
816 LLVMValueRef vertex_dw_stride,
817 LLVMValueRef base_addr,
818 LLVMValueRef vertex_index,
819 LLVMValueRef param_index,
820 unsigned input_index,
821 ubyte *name,
822 ubyte *index,
823 bool is_patch)
824 {
825 if (vertex_dw_stride) {
826 base_addr = ac_build_imad(&ctx->ac, vertex_index,
827 vertex_dw_stride, base_addr);
828 }
829
830 if (param_index) {
831 base_addr = ac_build_imad(&ctx->ac, param_index,
832 LLVMConstInt(ctx->i32, 4, 0), base_addr);
833 }
834
835 int param = is_patch ?
836 si_shader_io_get_unique_index_patch(name[input_index],
837 index[input_index]) :
838 si_shader_io_get_unique_index(name[input_index],
839 index[input_index], false);
840
841 /* Add the base address of the element. */
842 return LLVMBuildAdd(ctx->ac.builder, base_addr,
843 LLVMConstInt(ctx->i32, param * 4, 0), "");
844 }
845
846 /**
847 * Calculate a dword address given an input or output register and a stride.
848 */
849 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
850 const struct tgsi_full_dst_register *dst,
851 const struct tgsi_full_src_register *src,
852 LLVMValueRef vertex_dw_stride,
853 LLVMValueRef base_addr)
854 {
855 struct tgsi_shader_info *info = &ctx->shader->selector->info;
856 ubyte *name, *index, *array_first;
857 int input_index;
858 struct tgsi_full_dst_register reg;
859 LLVMValueRef vertex_index = NULL;
860 LLVMValueRef ind_index = NULL;
861
862 /* Set the register description. The address computation is the same
863 * for sources and destinations. */
864 if (src) {
865 reg.Register.File = src->Register.File;
866 reg.Register.Index = src->Register.Index;
867 reg.Register.Indirect = src->Register.Indirect;
868 reg.Register.Dimension = src->Register.Dimension;
869 reg.Indirect = src->Indirect;
870 reg.Dimension = src->Dimension;
871 reg.DimIndirect = src->DimIndirect;
872 } else
873 reg = *dst;
874
875 /* If the register is 2-dimensional (e.g. an array of vertices
876 * in a primitive), calculate the base address of the vertex. */
877 if (reg.Register.Dimension) {
878 if (reg.Dimension.Indirect)
879 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
880 1, reg.Dimension.Index);
881 else
882 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
883 }
884
885 /* Get information about the register. */
886 if (reg.Register.File == TGSI_FILE_INPUT) {
887 name = info->input_semantic_name;
888 index = info->input_semantic_index;
889 array_first = info->input_array_first;
890 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
891 name = info->output_semantic_name;
892 index = info->output_semantic_index;
893 array_first = info->output_array_first;
894 } else {
895 assert(0);
896 return NULL;
897 }
898
899 if (reg.Register.Indirect) {
900 /* Add the relative address of the element. */
901 if (reg.Indirect.ArrayID)
902 input_index = array_first[reg.Indirect.ArrayID];
903 else
904 input_index = reg.Register.Index;
905
906 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
907 1, reg.Register.Index - input_index);
908 } else {
909 input_index = reg.Register.Index;
910 }
911
912 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
913 base_addr, vertex_index,
914 ind_index, input_index,
915 name, index,
916 !reg.Register.Dimension);
917 }
918
919 /* The offchip buffer layout for TCS->TES is
920 *
921 * - attribute 0 of patch 0 vertex 0
922 * - attribute 0 of patch 0 vertex 1
923 * - attribute 0 of patch 0 vertex 2
924 * ...
925 * - attribute 0 of patch 1 vertex 0
926 * - attribute 0 of patch 1 vertex 1
927 * ...
928 * - attribute 1 of patch 0 vertex 0
929 * - attribute 1 of patch 0 vertex 1
930 * ...
931 * - per patch attribute 0 of patch 0
932 * - per patch attribute 0 of patch 1
933 * ...
934 *
935 * Note that every attribute has 4 components.
936 */
937 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
938 LLVMValueRef rel_patch_id,
939 LLVMValueRef vertex_index,
940 LLVMValueRef param_index)
941 {
942 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
943 LLVMValueRef param_stride, constant16;
944
945 vertices_per_patch = get_num_tcs_out_vertices(ctx);
946 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
947 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
948 num_patches, "");
949
950 constant16 = LLVMConstInt(ctx->i32, 16, 0);
951 if (vertex_index) {
952 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
953 vertices_per_patch, vertex_index);
954 param_stride = total_vertices;
955 } else {
956 base_addr = rel_patch_id;
957 param_stride = num_patches;
958 }
959
960 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
961 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
962
963 if (!vertex_index) {
964 LLVMValueRef patch_data_offset =
965 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
966
967 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
968 patch_data_offset, "");
969 }
970 return base_addr;
971 }
972
973 /* This is a generic helper that can be shared by the NIR and TGSI backends */
974 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
975 struct si_shader_context *ctx,
976 LLVMValueRef vertex_index,
977 LLVMValueRef param_index,
978 unsigned param_base,
979 ubyte *name,
980 ubyte *index,
981 bool is_patch)
982 {
983 unsigned param_index_base;
984
985 param_index_base = is_patch ?
986 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
987 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
988
989 if (param_index) {
990 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
991 LLVMConstInt(ctx->i32, param_index_base, 0),
992 "");
993 } else {
994 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
995 }
996
997 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
998 vertex_index, param_index);
999 }
1000
1001 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1002 struct si_shader_context *ctx,
1003 const struct tgsi_full_dst_register *dst,
1004 const struct tgsi_full_src_register *src)
1005 {
1006 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1007 ubyte *name, *index, *array_first;
1008 struct tgsi_full_src_register reg;
1009 LLVMValueRef vertex_index = NULL;
1010 LLVMValueRef param_index = NULL;
1011 unsigned param_base;
1012
1013 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1014
1015 if (reg.Register.Dimension) {
1016
1017 if (reg.Dimension.Indirect)
1018 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1019 1, reg.Dimension.Index);
1020 else
1021 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1022 }
1023
1024 /* Get information about the register. */
1025 if (reg.Register.File == TGSI_FILE_INPUT) {
1026 name = info->input_semantic_name;
1027 index = info->input_semantic_index;
1028 array_first = info->input_array_first;
1029 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1030 name = info->output_semantic_name;
1031 index = info->output_semantic_index;
1032 array_first = info->output_array_first;
1033 } else {
1034 assert(0);
1035 return NULL;
1036 }
1037
1038 if (reg.Register.Indirect) {
1039 if (reg.Indirect.ArrayID)
1040 param_base = array_first[reg.Indirect.ArrayID];
1041 else
1042 param_base = reg.Register.Index;
1043
1044 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1045 1, reg.Register.Index - param_base);
1046
1047 } else {
1048 param_base = reg.Register.Index;
1049 }
1050
1051 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1052 param_index, param_base,
1053 name, index, !reg.Register.Dimension);
1054 }
1055
1056 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1057 LLVMTypeRef type, unsigned swizzle,
1058 LLVMValueRef buffer, LLVMValueRef offset,
1059 LLVMValueRef base, bool can_speculate)
1060 {
1061 struct si_shader_context *ctx = si_shader_context(bld_base);
1062 LLVMValueRef value, value2;
1063 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1064
1065 if (swizzle == ~0) {
1066 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1067 0, 1, 0, can_speculate, false);
1068
1069 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1070 }
1071
1072 if (!llvm_type_is_64bit(ctx, type)) {
1073 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1074 0, 1, 0, can_speculate, false);
1075
1076 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1077 return LLVMBuildExtractElement(ctx->ac.builder, value,
1078 LLVMConstInt(ctx->i32, swizzle, 0), "");
1079 }
1080
1081 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1082 swizzle * 4, 1, 0, can_speculate, false);
1083
1084 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1085 swizzle * 4 + 4, 1, 0, can_speculate, false);
1086
1087 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1088 }
1089
1090 /**
1091 * Load from LDS.
1092 *
1093 * \param type output value type
1094 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1095 * \param dw_addr address in dwords
1096 */
1097 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1098 LLVMTypeRef type, unsigned swizzle,
1099 LLVMValueRef dw_addr)
1100 {
1101 struct si_shader_context *ctx = si_shader_context(bld_base);
1102 LLVMValueRef value;
1103
1104 if (swizzle == ~0) {
1105 LLVMValueRef values[TGSI_NUM_CHANNELS];
1106
1107 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1108 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1109
1110 return ac_build_gather_values(&ctx->ac, values,
1111 TGSI_NUM_CHANNELS);
1112 }
1113
1114 /* Split 64-bit loads. */
1115 if (llvm_type_is_64bit(ctx, type)) {
1116 LLVMValueRef lo, hi;
1117
1118 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1119 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1120 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1121 }
1122
1123 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1124 LLVMConstInt(ctx->i32, swizzle, 0), "");
1125
1126 value = ac_lds_load(&ctx->ac, dw_addr);
1127
1128 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1129 }
1130
1131 /**
1132 * Store to LDS.
1133 *
1134 * \param swizzle offset (typically 0..3)
1135 * \param dw_addr address in dwords
1136 * \param value value to store
1137 */
1138 static void lds_store(struct si_shader_context *ctx,
1139 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1140 LLVMValueRef value)
1141 {
1142 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1143 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1144
1145 ac_lds_store(&ctx->ac, dw_addr, value);
1146 }
1147
1148 enum si_tess_ring {
1149 TCS_FACTOR_RING,
1150 TESS_OFFCHIP_RING_TCS,
1151 TESS_OFFCHIP_RING_TES,
1152 };
1153
1154 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1155 enum si_tess_ring ring)
1156 {
1157 LLVMBuilderRef builder = ctx->ac.builder;
1158 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1159 ctx->param_tcs_out_lds_layout;
1160 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1161
1162 /* TCS only receives high 13 bits of the address. */
1163 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1164 addr = LLVMBuildAnd(builder, addr,
1165 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1166 }
1167
1168 if (ring == TCS_FACTOR_RING) {
1169 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1170 addr = LLVMBuildAdd(builder, addr,
1171 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1172 }
1173
1174 LLVMValueRef desc[4];
1175 desc[0] = addr;
1176 desc[1] = LLVMConstInt(ctx->i32,
1177 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1178 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1179 desc[3] = LLVMConstInt(ctx->i32,
1180 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1181 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1182 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1183 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1184 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1185 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1186
1187 return ac_build_gather_values(&ctx->ac, desc, 4);
1188 }
1189
1190 static LLVMValueRef fetch_input_tcs(
1191 struct lp_build_tgsi_context *bld_base,
1192 const struct tgsi_full_src_register *reg,
1193 enum tgsi_opcode_type type, unsigned swizzle_in)
1194 {
1195 struct si_shader_context *ctx = si_shader_context(bld_base);
1196 LLVMValueRef dw_addr, stride;
1197 unsigned swizzle = swizzle_in & 0xffff;
1198 stride = get_tcs_in_vertex_dw_stride(ctx);
1199 dw_addr = get_tcs_in_current_patch_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1201
1202 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1203 }
1204
1205 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1206 LLVMTypeRef type,
1207 LLVMValueRef vertex_index,
1208 LLVMValueRef param_index,
1209 unsigned const_index,
1210 unsigned location,
1211 unsigned driver_location,
1212 unsigned component,
1213 unsigned num_components,
1214 bool is_patch,
1215 bool is_compact,
1216 bool load_input)
1217 {
1218 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1219 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1220 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1221 LLVMValueRef dw_addr, stride;
1222
1223 driver_location = driver_location / 4;
1224
1225 if (load_input) {
1226 stride = get_tcs_in_vertex_dw_stride(ctx);
1227 dw_addr = get_tcs_in_current_patch_offset(ctx);
1228 } else {
1229 if (is_patch) {
1230 stride = NULL;
1231 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1232 } else {
1233 stride = get_tcs_out_vertex_dw_stride(ctx);
1234 dw_addr = get_tcs_out_current_patch_offset(ctx);
1235 }
1236 }
1237
1238 if (param_index) {
1239 /* Add the constant index to the indirect index */
1240 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1241 LLVMConstInt(ctx->i32, const_index, 0), "");
1242 } else {
1243 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1244 }
1245
1246 ubyte *names;
1247 ubyte *indices;
1248 if (load_input) {
1249 names = info->input_semantic_name;
1250 indices = info->input_semantic_index;
1251 } else {
1252 names = info->output_semantic_name;
1253 indices = info->output_semantic_index;
1254 }
1255
1256 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1257 vertex_index, param_index,
1258 driver_location,
1259 names, indices,
1260 is_patch);
1261
1262 LLVMValueRef value[4];
1263 for (unsigned i = 0; i < num_components; i++) {
1264 unsigned offset = i;
1265 if (llvm_type_is_64bit(ctx, type))
1266 offset *= 2;
1267
1268 offset += component;
1269 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1270 }
1271
1272 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1273 }
1274
1275 static LLVMValueRef fetch_output_tcs(
1276 struct lp_build_tgsi_context *bld_base,
1277 const struct tgsi_full_src_register *reg,
1278 enum tgsi_opcode_type type, unsigned swizzle_in)
1279 {
1280 struct si_shader_context *ctx = si_shader_context(bld_base);
1281 LLVMValueRef dw_addr, stride;
1282 unsigned swizzle = (swizzle_in & 0xffff);
1283
1284 if (reg->Register.Dimension) {
1285 stride = get_tcs_out_vertex_dw_stride(ctx);
1286 dw_addr = get_tcs_out_current_patch_offset(ctx);
1287 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1288 } else {
1289 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1290 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1291 }
1292
1293 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1294 }
1295
1296 static LLVMValueRef fetch_input_tes(
1297 struct lp_build_tgsi_context *bld_base,
1298 const struct tgsi_full_src_register *reg,
1299 enum tgsi_opcode_type type, unsigned swizzle_in)
1300 {
1301 struct si_shader_context *ctx = si_shader_context(bld_base);
1302 LLVMValueRef base, addr;
1303 unsigned swizzle = (swizzle_in & 0xffff);
1304
1305 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1306 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1307
1308 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1309 ctx->tess_offchip_ring, base, addr, true);
1310 }
1311
1312 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1313 LLVMTypeRef type,
1314 LLVMValueRef vertex_index,
1315 LLVMValueRef param_index,
1316 unsigned const_index,
1317 unsigned location,
1318 unsigned driver_location,
1319 unsigned component,
1320 unsigned num_components,
1321 bool is_patch,
1322 bool is_compact,
1323 bool load_input)
1324 {
1325 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1326 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1327 LLVMValueRef base, addr;
1328
1329 driver_location = driver_location / 4;
1330
1331 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1332
1333 if (param_index) {
1334 /* Add the constant index to the indirect index */
1335 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1336 LLVMConstInt(ctx->i32, const_index, 0), "");
1337 } else {
1338 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1339 }
1340
1341 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1342 param_index, driver_location,
1343 info->input_semantic_name,
1344 info->input_semantic_index,
1345 is_patch);
1346
1347 /* TODO: This will generate rather ordinary llvm code, although it
1348 * should be easy for the optimiser to fix up. In future we might want
1349 * to refactor buffer_load(), but for now this maximises code sharing
1350 * between the NIR and TGSI backends.
1351 */
1352 LLVMValueRef value[4];
1353 for (unsigned i = 0; i < num_components; i++) {
1354 unsigned offset = i;
1355 if (llvm_type_is_64bit(ctx, type))
1356 offset *= 2;
1357
1358 offset += component;
1359 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1360 ctx->tess_offchip_ring, base, addr, true);
1361 }
1362
1363 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1364 }
1365
1366 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1367 const struct tgsi_full_instruction *inst,
1368 const struct tgsi_opcode_info *info,
1369 unsigned index,
1370 LLVMValueRef dst[4])
1371 {
1372 struct si_shader_context *ctx = si_shader_context(bld_base);
1373 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1374 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1375 unsigned chan_index;
1376 LLVMValueRef dw_addr, stride;
1377 LLVMValueRef buffer, base, buf_addr;
1378 LLVMValueRef values[4];
1379 bool skip_lds_store;
1380 bool is_tess_factor = false, is_tess_inner = false;
1381
1382 /* Only handle per-patch and per-vertex outputs here.
1383 * Vectors will be lowered to scalars and this function will be called again.
1384 */
1385 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1386 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1387 si_llvm_emit_store(bld_base, inst, info, index, dst);
1388 return;
1389 }
1390
1391 if (reg->Register.Dimension) {
1392 stride = get_tcs_out_vertex_dw_stride(ctx);
1393 dw_addr = get_tcs_out_current_patch_offset(ctx);
1394 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1395 skip_lds_store = !sh_info->reads_pervertex_outputs;
1396 } else {
1397 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1398 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1399 skip_lds_store = !sh_info->reads_perpatch_outputs;
1400
1401 if (!reg->Register.Indirect) {
1402 int name = sh_info->output_semantic_name[reg->Register.Index];
1403
1404 /* Always write tess factors into LDS for the TCS epilog. */
1405 if (name == TGSI_SEMANTIC_TESSINNER ||
1406 name == TGSI_SEMANTIC_TESSOUTER) {
1407 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1408 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1409 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1410 is_tess_factor = true;
1411 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1412 }
1413 }
1414 }
1415
1416 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1417
1418 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1419 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1420
1421 uint32_t writemask = reg->Register.WriteMask;
1422 while (writemask) {
1423 chan_index = u_bit_scan(&writemask);
1424 LLVMValueRef value = dst[chan_index];
1425
1426 if (inst->Instruction.Saturate)
1427 value = ac_build_clamp(&ctx->ac, value);
1428
1429 /* Skip LDS stores if there is no LDS read of this output. */
1430 if (!skip_lds_store)
1431 lds_store(ctx, chan_index, dw_addr, value);
1432
1433 value = ac_to_integer(&ctx->ac, value);
1434 values[chan_index] = value;
1435
1436 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1437 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1438 buf_addr, base,
1439 4 * chan_index, 1, 0, true, false);
1440 }
1441
1442 /* Write tess factors into VGPRs for the epilog. */
1443 if (is_tess_factor &&
1444 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1445 if (!is_tess_inner) {
1446 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1447 ctx->invoc0_tess_factors[chan_index]);
1448 } else if (chan_index < 2) {
1449 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1450 ctx->invoc0_tess_factors[4 + chan_index]);
1451 }
1452 }
1453 }
1454
1455 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1456 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1457 values, 4);
1458 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1459 base, 0, 1, 0, true, false);
1460 }
1461 }
1462
1463 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1464 const struct nir_variable *var,
1465 LLVMValueRef vertex_index,
1466 LLVMValueRef param_index,
1467 unsigned const_index,
1468 LLVMValueRef src,
1469 unsigned writemask)
1470 {
1471 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1472 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1473 const unsigned component = var->data.location_frac;
1474 const bool is_patch = var->data.patch;
1475 unsigned driver_location = var->data.driver_location;
1476 LLVMValueRef dw_addr, stride;
1477 LLVMValueRef buffer, base, addr;
1478 LLVMValueRef values[4];
1479 bool skip_lds_store;
1480 bool is_tess_factor = false, is_tess_inner = false;
1481
1482 driver_location = driver_location / 4;
1483
1484 if (param_index) {
1485 /* Add the constant index to the indirect index */
1486 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1487 LLVMConstInt(ctx->i32, const_index, 0), "");
1488 } else {
1489 if (const_index != 0)
1490 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1491 }
1492
1493 if (!is_patch) {
1494 stride = get_tcs_out_vertex_dw_stride(ctx);
1495 dw_addr = get_tcs_out_current_patch_offset(ctx);
1496 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1497 vertex_index, param_index,
1498 driver_location,
1499 info->output_semantic_name,
1500 info->output_semantic_index,
1501 is_patch);
1502
1503 skip_lds_store = !info->reads_pervertex_outputs;
1504 } else {
1505 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1506 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1507 vertex_index, param_index,
1508 driver_location,
1509 info->output_semantic_name,
1510 info->output_semantic_index,
1511 is_patch);
1512
1513 skip_lds_store = !info->reads_perpatch_outputs;
1514
1515 if (!param_index) {
1516 int name = info->output_semantic_name[driver_location];
1517
1518 /* Always write tess factors into LDS for the TCS epilog. */
1519 if (name == TGSI_SEMANTIC_TESSINNER ||
1520 name == TGSI_SEMANTIC_TESSOUTER) {
1521 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1522 skip_lds_store = !info->reads_tessfactor_outputs &&
1523 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1524 is_tess_factor = true;
1525 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1526 }
1527 }
1528 }
1529
1530 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1531
1532 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1533
1534 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1535 param_index, driver_location,
1536 info->output_semantic_name,
1537 info->output_semantic_index,
1538 is_patch);
1539
1540 for (unsigned chan = 0; chan < 4; chan++) {
1541 if (!(writemask & (1 << chan)))
1542 continue;
1543 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1544
1545 /* Skip LDS stores if there is no LDS read of this output. */
1546 if (!skip_lds_store)
1547 lds_store(ctx, chan, dw_addr, value);
1548
1549 value = ac_to_integer(&ctx->ac, value);
1550 values[chan] = value;
1551
1552 if (writemask != 0xF && !is_tess_factor) {
1553 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1554 addr, base,
1555 4 * chan, 1, 0, true, false);
1556 }
1557
1558 /* Write tess factors into VGPRs for the epilog. */
1559 if (is_tess_factor &&
1560 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1561 if (!is_tess_inner) {
1562 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1563 ctx->invoc0_tess_factors[chan]);
1564 } else if (chan < 2) {
1565 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1566 ctx->invoc0_tess_factors[4 + chan]);
1567 }
1568 }
1569 }
1570
1571 if (writemask == 0xF && !is_tess_factor) {
1572 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1573 values, 4);
1574 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1575 base, 0, 1, 0, true, false);
1576 }
1577 }
1578
1579 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1580 unsigned input_index,
1581 unsigned vtx_offset_param,
1582 LLVMTypeRef type,
1583 unsigned swizzle)
1584 {
1585 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1586 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1587 struct si_shader *shader = ctx->shader;
1588 LLVMValueRef vtx_offset, soffset;
1589 struct tgsi_shader_info *info = &shader->selector->info;
1590 unsigned semantic_name = info->input_semantic_name[input_index];
1591 unsigned semantic_index = info->input_semantic_index[input_index];
1592 unsigned param;
1593 LLVMValueRef value;
1594
1595 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1596
1597 /* GFX9 has the ESGS ring in LDS. */
1598 if (ctx->screen->info.chip_class >= GFX9) {
1599 unsigned index = vtx_offset_param;
1600
1601 switch (index / 2) {
1602 case 0:
1603 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1604 index % 2 ? 16 : 0, 16);
1605 break;
1606 case 1:
1607 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1608 index % 2 ? 16 : 0, 16);
1609 break;
1610 case 2:
1611 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1612 index % 2 ? 16 : 0, 16);
1613 break;
1614 default:
1615 assert(0);
1616 return NULL;
1617 }
1618
1619 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1620 LLVMConstInt(ctx->i32, param * 4, 0), "");
1621 return lds_load(bld_base, type, swizzle, vtx_offset);
1622 }
1623
1624 /* GFX6: input load from the ESGS ring in memory. */
1625 if (swizzle == ~0) {
1626 LLVMValueRef values[TGSI_NUM_CHANNELS];
1627 unsigned chan;
1628 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1629 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1630 type, chan);
1631 }
1632 return ac_build_gather_values(&ctx->ac, values,
1633 TGSI_NUM_CHANNELS);
1634 }
1635
1636 /* Get the vertex offset parameter on GFX6. */
1637 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1638
1639 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1640 LLVMConstInt(ctx->i32, 4, 0), "");
1641
1642 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1643
1644 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1645 vtx_offset, soffset, 0, 1, 0, true, false);
1646 if (llvm_type_is_64bit(ctx, type)) {
1647 LLVMValueRef value2;
1648 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1649
1650 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1651 ctx->i32_0, vtx_offset, soffset,
1652 0, 1, 0, true, false);
1653 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1654 }
1655 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1656 }
1657
1658 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1659 unsigned location,
1660 unsigned driver_location,
1661 unsigned component,
1662 unsigned num_components,
1663 unsigned vertex_index,
1664 unsigned const_index,
1665 LLVMTypeRef type)
1666 {
1667 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1668
1669 LLVMValueRef value[4];
1670 for (unsigned i = 0; i < num_components; i++) {
1671 unsigned offset = i;
1672 if (llvm_type_is_64bit(ctx, type))
1673 offset *= 2;
1674
1675 offset += component;
1676 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1677 vertex_index, type, offset);
1678 }
1679
1680 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1681 }
1682
1683 static LLVMValueRef fetch_input_gs(
1684 struct lp_build_tgsi_context *bld_base,
1685 const struct tgsi_full_src_register *reg,
1686 enum tgsi_opcode_type type,
1687 unsigned swizzle_in)
1688 {
1689 struct si_shader_context *ctx = si_shader_context(bld_base);
1690 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1691 unsigned swizzle = swizzle_in & 0xffff;
1692
1693 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1694 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1695 return get_primitive_id(ctx, swizzle);
1696
1697 if (!reg->Register.Dimension)
1698 return NULL;
1699
1700 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1701 reg->Dimension.Index,
1702 tgsi2llvmtype(bld_base, type),
1703 swizzle);
1704 }
1705
1706 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1707 {
1708 switch (interpolate) {
1709 case TGSI_INTERPOLATE_CONSTANT:
1710 return 0;
1711
1712 case TGSI_INTERPOLATE_LINEAR:
1713 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1714 return SI_PARAM_LINEAR_SAMPLE;
1715 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1716 return SI_PARAM_LINEAR_CENTROID;
1717 else
1718 return SI_PARAM_LINEAR_CENTER;
1719 break;
1720 case TGSI_INTERPOLATE_COLOR:
1721 case TGSI_INTERPOLATE_PERSPECTIVE:
1722 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1723 return SI_PARAM_PERSP_SAMPLE;
1724 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1725 return SI_PARAM_PERSP_CENTROID;
1726 else
1727 return SI_PARAM_PERSP_CENTER;
1728 break;
1729 default:
1730 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1731 return -1;
1732 }
1733 }
1734
1735 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1736 unsigned attr_index, unsigned chan,
1737 LLVMValueRef prim_mask,
1738 LLVMValueRef i, LLVMValueRef j)
1739 {
1740 if (i || j) {
1741 return ac_build_fs_interp(&ctx->ac,
1742 LLVMConstInt(ctx->i32, chan, 0),
1743 LLVMConstInt(ctx->i32, attr_index, 0),
1744 prim_mask, i, j);
1745 }
1746 return ac_build_fs_interp_mov(&ctx->ac,
1747 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1748 LLVMConstInt(ctx->i32, chan, 0),
1749 LLVMConstInt(ctx->i32, attr_index, 0),
1750 prim_mask);
1751 }
1752
1753 /**
1754 * Interpolate a fragment shader input.
1755 *
1756 * @param ctx context
1757 * @param input_index index of the input in hardware
1758 * @param semantic_name TGSI_SEMANTIC_*
1759 * @param semantic_index semantic index
1760 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1761 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1762 * @param interp_param interpolation weights (i,j)
1763 * @param prim_mask SI_PARAM_PRIM_MASK
1764 * @param face SI_PARAM_FRONT_FACE
1765 * @param result the return value (4 components)
1766 */
1767 static void interp_fs_input(struct si_shader_context *ctx,
1768 unsigned input_index,
1769 unsigned semantic_name,
1770 unsigned semantic_index,
1771 unsigned num_interp_inputs,
1772 unsigned colors_read_mask,
1773 LLVMValueRef interp_param,
1774 LLVMValueRef prim_mask,
1775 LLVMValueRef face,
1776 LLVMValueRef result[4])
1777 {
1778 LLVMValueRef i = NULL, j = NULL;
1779 unsigned chan;
1780
1781 /* fs.constant returns the param from the middle vertex, so it's not
1782 * really useful for flat shading. It's meant to be used for custom
1783 * interpolation (but the intrinsic can't fetch from the other two
1784 * vertices).
1785 *
1786 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1787 * to do the right thing. The only reason we use fs.constant is that
1788 * fs.interp cannot be used on integers, because they can be equal
1789 * to NaN.
1790 *
1791 * When interp is false we will use fs.constant or for newer llvm,
1792 * amdgcn.interp.mov.
1793 */
1794 bool interp = interp_param != NULL;
1795
1796 if (interp) {
1797 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1798 LLVMVectorType(ctx->f32, 2), "");
1799
1800 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1801 ctx->i32_0, "");
1802 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1803 ctx->i32_1, "");
1804 }
1805
1806 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1807 ctx->shader->key.part.ps.prolog.color_two_side) {
1808 LLVMValueRef is_face_positive;
1809
1810 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1811 * otherwise it's at offset "num_inputs".
1812 */
1813 unsigned back_attr_offset = num_interp_inputs;
1814 if (semantic_index == 1 && colors_read_mask & 0xf)
1815 back_attr_offset += 1;
1816
1817 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1818 face, ctx->i32_0, "");
1819
1820 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1821 LLVMValueRef front, back;
1822
1823 front = si_build_fs_interp(ctx,
1824 input_index, chan,
1825 prim_mask, i, j);
1826 back = si_build_fs_interp(ctx,
1827 back_attr_offset, chan,
1828 prim_mask, i, j);
1829
1830 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1831 is_face_positive,
1832 front,
1833 back,
1834 "");
1835 }
1836 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1837 result[0] = si_build_fs_interp(ctx, input_index,
1838 0, prim_mask, i, j);
1839 result[1] =
1840 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1841 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1842 } else {
1843 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1844 result[chan] = si_build_fs_interp(ctx,
1845 input_index, chan,
1846 prim_mask, i, j);
1847 }
1848 }
1849 }
1850
1851 void si_llvm_load_input_fs(
1852 struct si_shader_context *ctx,
1853 unsigned input_index,
1854 LLVMValueRef out[4])
1855 {
1856 struct si_shader *shader = ctx->shader;
1857 struct tgsi_shader_info *info = &shader->selector->info;
1858 LLVMValueRef main_fn = ctx->main_fn;
1859 LLVMValueRef interp_param = NULL;
1860 int interp_param_idx;
1861 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1862 unsigned semantic_index = info->input_semantic_index[input_index];
1863 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1864 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1865
1866 /* Get colors from input VGPRs (set by the prolog). */
1867 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1868 unsigned colors_read = shader->selector->info.colors_read;
1869 unsigned mask = colors_read >> (semantic_index * 4);
1870 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1871 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1872 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1873
1874 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1875 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1876 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1877 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1878 return;
1879 }
1880
1881 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1882 if (interp_param_idx == -1)
1883 return;
1884 else if (interp_param_idx) {
1885 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1886 }
1887
1888 interp_fs_input(ctx, input_index, semantic_name,
1889 semantic_index, 0, /* this param is unused */
1890 shader->selector->info.colors_read, interp_param,
1891 ctx->abi.prim_mask,
1892 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1893 &out[0]);
1894 }
1895
1896 static void declare_input_fs(
1897 struct si_shader_context *ctx,
1898 unsigned input_index,
1899 const struct tgsi_full_declaration *decl,
1900 LLVMValueRef out[4])
1901 {
1902 si_llvm_load_input_fs(ctx, input_index, out);
1903 }
1904
1905 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1906 {
1907 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1908 }
1909
1910 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1911 {
1912 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1913
1914 /* For non-indexed draws, the base vertex set by the driver
1915 * (for direct draws) or the CP (for indirect draws) is the
1916 * first vertex ID, but GLSL expects 0 to be returned.
1917 */
1918 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1919 ctx->param_vs_state_bits);
1920 LLVMValueRef indexed;
1921
1922 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1923 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1924
1925 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1926 ctx->i32_0, "");
1927 }
1928
1929 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1930 {
1931 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1932
1933 LLVMValueRef values[3];
1934 LLVMValueRef result;
1935 unsigned i;
1936 unsigned *properties = ctx->shader->selector->info.properties;
1937
1938 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1939 unsigned sizes[3] = {
1940 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1941 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1942 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1943 };
1944
1945 for (i = 0; i < 3; ++i)
1946 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1947
1948 result = ac_build_gather_values(&ctx->ac, values, 3);
1949 } else {
1950 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1951 }
1952
1953 return result;
1954 }
1955
1956 /**
1957 * Load a dword from a constant buffer.
1958 */
1959 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1960 LLVMValueRef resource,
1961 LLVMValueRef offset)
1962 {
1963 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1964 0, 0, 0, true, true);
1965 }
1966
1967 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1968 {
1969 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1970 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1971 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1972 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1973
1974 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1975 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1976 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1977
1978 LLVMValueRef pos[4] = {
1979 buffer_load_const(ctx, resource, offset0),
1980 buffer_load_const(ctx, resource, offset1),
1981 LLVMConstReal(ctx->f32, 0),
1982 LLVMConstReal(ctx->f32, 0)
1983 };
1984
1985 return ac_build_gather_values(&ctx->ac, pos, 4);
1986 }
1987
1988 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1989 {
1990 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1991 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1992 }
1993
1994 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1995 {
1996 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1997 LLVMValueRef coord[4] = {
1998 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1999 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2000 ctx->ac.f32_0,
2001 ctx->ac.f32_0
2002 };
2003
2004 /* For triangles, the vector should be (u, v, 1-u-v). */
2005 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2006 PIPE_PRIM_TRIANGLES) {
2007 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
2008 LLVMBuildFAdd(ctx->ac.builder,
2009 coord[0], coord[1], ""), "");
2010 }
2011 return ac_build_gather_values(&ctx->ac, coord, 4);
2012 }
2013
2014 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2015 unsigned semantic_name)
2016 {
2017 LLVMValueRef base, addr;
2018
2019 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2020
2021 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2022 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2023 LLVMConstInt(ctx->i32, param, 0));
2024
2025 return buffer_load(&ctx->bld_base, ctx->f32,
2026 ~0, ctx->tess_offchip_ring, base, addr, true);
2027
2028 }
2029
2030 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2031 unsigned varying_id)
2032 {
2033 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2034 unsigned semantic_name;
2035
2036 switch (varying_id) {
2037 case VARYING_SLOT_TESS_LEVEL_INNER:
2038 semantic_name = TGSI_SEMANTIC_TESSINNER;
2039 break;
2040 case VARYING_SLOT_TESS_LEVEL_OUTER:
2041 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2042 break;
2043 default:
2044 unreachable("unknown tess level");
2045 }
2046
2047 return load_tess_level(ctx, semantic_name);
2048
2049 }
2050
2051 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2052 {
2053 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2054 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2055 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2056 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2057 return get_num_tcs_out_vertices(ctx);
2058 else
2059 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2060 }
2061
2062 void si_load_system_value(struct si_shader_context *ctx,
2063 unsigned index,
2064 const struct tgsi_full_declaration *decl)
2065 {
2066 LLVMValueRef value = 0;
2067
2068 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2069
2070 switch (decl->Semantic.Name) {
2071 case TGSI_SEMANTIC_INSTANCEID:
2072 value = ctx->abi.instance_id;
2073 break;
2074
2075 case TGSI_SEMANTIC_VERTEXID:
2076 value = LLVMBuildAdd(ctx->ac.builder,
2077 ctx->abi.vertex_id,
2078 ctx->abi.base_vertex, "");
2079 break;
2080
2081 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2082 /* Unused. Clarify the meaning in indexed vs. non-indexed
2083 * draws if this is ever used again. */
2084 assert(false);
2085 break;
2086
2087 case TGSI_SEMANTIC_BASEVERTEX:
2088 value = get_base_vertex(&ctx->abi);
2089 break;
2090
2091 case TGSI_SEMANTIC_BASEINSTANCE:
2092 value = ctx->abi.start_instance;
2093 break;
2094
2095 case TGSI_SEMANTIC_DRAWID:
2096 value = ctx->abi.draw_id;
2097 break;
2098
2099 case TGSI_SEMANTIC_INVOCATIONID:
2100 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2101 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2102 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2103 value = ctx->abi.gs_invocation_id;
2104 else
2105 assert(!"INVOCATIONID not implemented");
2106 break;
2107
2108 case TGSI_SEMANTIC_POSITION:
2109 {
2110 LLVMValueRef pos[4] = {
2111 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2112 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2113 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2114 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2115 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2116 };
2117 value = ac_build_gather_values(&ctx->ac, pos, 4);
2118 break;
2119 }
2120
2121 case TGSI_SEMANTIC_FACE:
2122 value = ctx->abi.front_face;
2123 break;
2124
2125 case TGSI_SEMANTIC_SAMPLEID:
2126 value = si_get_sample_id(ctx);
2127 break;
2128
2129 case TGSI_SEMANTIC_SAMPLEPOS: {
2130 LLVMValueRef pos[4] = {
2131 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2132 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2133 LLVMConstReal(ctx->f32, 0),
2134 LLVMConstReal(ctx->f32, 0)
2135 };
2136 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2137 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2138 value = ac_build_gather_values(&ctx->ac, pos, 4);
2139 break;
2140 }
2141
2142 case TGSI_SEMANTIC_SAMPLEMASK:
2143 /* This can only occur with the OpenGL Core profile, which
2144 * doesn't support smoothing.
2145 */
2146 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2147 break;
2148
2149 case TGSI_SEMANTIC_TESSCOORD:
2150 value = si_load_tess_coord(&ctx->abi);
2151 break;
2152
2153 case TGSI_SEMANTIC_VERTICESIN:
2154 value = si_load_patch_vertices_in(&ctx->abi);
2155 break;
2156
2157 case TGSI_SEMANTIC_TESSINNER:
2158 case TGSI_SEMANTIC_TESSOUTER:
2159 value = load_tess_level(ctx, decl->Semantic.Name);
2160 break;
2161
2162 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2163 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2164 {
2165 LLVMValueRef buf, slot, val[4];
2166 int i, offset;
2167
2168 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2169 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2170 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2171 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2172
2173 for (i = 0; i < 4; i++)
2174 val[i] = buffer_load_const(ctx, buf,
2175 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2176 value = ac_build_gather_values(&ctx->ac, val, 4);
2177 break;
2178 }
2179
2180 case TGSI_SEMANTIC_PRIMID:
2181 value = get_primitive_id(ctx, 0);
2182 break;
2183
2184 case TGSI_SEMANTIC_GRID_SIZE:
2185 value = ctx->abi.num_work_groups;
2186 break;
2187
2188 case TGSI_SEMANTIC_BLOCK_SIZE:
2189 value = get_block_size(&ctx->abi);
2190 break;
2191
2192 case TGSI_SEMANTIC_BLOCK_ID:
2193 {
2194 LLVMValueRef values[3];
2195
2196 for (int i = 0; i < 3; i++) {
2197 values[i] = ctx->i32_0;
2198 if (ctx->abi.workgroup_ids[i]) {
2199 values[i] = ctx->abi.workgroup_ids[i];
2200 }
2201 }
2202 value = ac_build_gather_values(&ctx->ac, values, 3);
2203 break;
2204 }
2205
2206 case TGSI_SEMANTIC_THREAD_ID:
2207 value = ctx->abi.local_invocation_ids;
2208 break;
2209
2210 case TGSI_SEMANTIC_HELPER_INVOCATION:
2211 value = ac_build_intrinsic(&ctx->ac,
2212 "llvm.amdgcn.ps.live",
2213 ctx->i1, NULL, 0,
2214 AC_FUNC_ATTR_READNONE);
2215 value = LLVMBuildNot(ctx->ac.builder, value, "");
2216 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2217 break;
2218
2219 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2220 value = LLVMConstInt(ctx->i32, 64, 0);
2221 break;
2222
2223 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2224 value = ac_get_thread_id(&ctx->ac);
2225 break;
2226
2227 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2228 {
2229 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2230 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2231 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2232 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2233 break;
2234 }
2235
2236 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2237 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2238 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2239 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2240 {
2241 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2242 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2243 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2244 /* All bits set except LSB */
2245 value = LLVMConstInt(ctx->i64, -2, 0);
2246 } else {
2247 /* All bits set */
2248 value = LLVMConstInt(ctx->i64, -1, 0);
2249 }
2250 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2251 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2252 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2253 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2254 value = LLVMBuildNot(ctx->ac.builder, value, "");
2255 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2256 break;
2257 }
2258
2259 case TGSI_SEMANTIC_CS_USER_DATA:
2260 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2261 break;
2262
2263 default:
2264 assert(!"unknown system value");
2265 return;
2266 }
2267
2268 ctx->system_values[index] = value;
2269 }
2270
2271 void si_declare_compute_memory(struct si_shader_context *ctx)
2272 {
2273 struct si_shader_selector *sel = ctx->shader->selector;
2274 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2275
2276 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2277 LLVMValueRef var;
2278
2279 assert(!ctx->ac.lds);
2280
2281 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2282 LLVMArrayType(ctx->i8, lds_size),
2283 "compute_lds",
2284 AC_ADDR_SPACE_LDS);
2285 LLVMSetAlignment(var, 4);
2286
2287 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2288 }
2289
2290 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2291 const struct tgsi_full_declaration *decl)
2292 {
2293 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2294 assert(decl->Range.First == decl->Range.Last);
2295
2296 si_declare_compute_memory(ctx);
2297 }
2298
2299 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2300 {
2301 LLVMValueRef ptr =
2302 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2303 struct si_shader_selector *sel = ctx->shader->selector;
2304
2305 /* Do the bounds checking with a descriptor, because
2306 * doing computation and manual bounds checking of 64-bit
2307 * addresses generates horrible VALU code with very high
2308 * VGPR usage and very low SIMD occupancy.
2309 */
2310 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2311
2312 LLVMValueRef desc0, desc1;
2313 desc0 = ptr;
2314 desc1 = LLVMConstInt(ctx->i32,
2315 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2316
2317 LLVMValueRef desc_elems[] = {
2318 desc0,
2319 desc1,
2320 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2321 LLVMConstInt(ctx->i32,
2322 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2323 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2324 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2325 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2326 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2327 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2328 };
2329
2330 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2331 }
2332
2333 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2334 {
2335 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2336 ctx->param_const_and_shader_buffers);
2337
2338 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2339 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2340 }
2341
2342 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2343 {
2344 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2345 struct si_shader_selector *sel = ctx->shader->selector;
2346
2347 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2348
2349 if (sel->info.const_buffers_declared == 1 &&
2350 sel->info.shader_buffers_declared == 0) {
2351 return load_const_buffer_desc_fast_path(ctx);
2352 }
2353
2354 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2355 index = LLVMBuildAdd(ctx->ac.builder, index,
2356 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2357
2358 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2359 }
2360
2361 static LLVMValueRef
2362 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2363 {
2364 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2365 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2366 ctx->param_const_and_shader_buffers);
2367
2368 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2369 index = LLVMBuildSub(ctx->ac.builder,
2370 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2371 index, "");
2372
2373 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2374 }
2375
2376 static LLVMValueRef fetch_constant(
2377 struct lp_build_tgsi_context *bld_base,
2378 const struct tgsi_full_src_register *reg,
2379 enum tgsi_opcode_type type,
2380 unsigned swizzle_in)
2381 {
2382 struct si_shader_context *ctx = si_shader_context(bld_base);
2383 struct si_shader_selector *sel = ctx->shader->selector;
2384 const struct tgsi_ind_register *ireg = &reg->Indirect;
2385 unsigned buf, idx;
2386 unsigned swizzle = swizzle_in & 0xffff;
2387
2388 LLVMValueRef addr, bufp;
2389
2390 if (swizzle_in == LP_CHAN_ALL) {
2391 unsigned chan;
2392 LLVMValueRef values[4];
2393 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2394 values[chan] = fetch_constant(bld_base, reg, type, chan);
2395
2396 return ac_build_gather_values(&ctx->ac, values, 4);
2397 }
2398
2399 /* Split 64-bit loads. */
2400 if (tgsi_type_is_64bit(type)) {
2401 LLVMValueRef lo, hi;
2402
2403 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2404 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2405 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2406 lo, hi);
2407 }
2408
2409 idx = reg->Register.Index * 4 + swizzle;
2410 if (reg->Register.Indirect) {
2411 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2412 } else {
2413 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2414 }
2415
2416 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2417 if (sel->info.const_buffers_declared == 1 &&
2418 sel->info.shader_buffers_declared == 0) {
2419 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2420 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2421 return bitcast(bld_base, type, result);
2422 }
2423
2424 assert(reg->Register.Dimension);
2425 buf = reg->Dimension.Index;
2426
2427 if (reg->Dimension.Indirect) {
2428 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2429 LLVMValueRef index;
2430 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2431 reg->Dimension.Index,
2432 ctx->num_const_buffers);
2433 index = LLVMBuildAdd(ctx->ac.builder, index,
2434 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2435 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2436 } else
2437 bufp = load_const_buffer_desc(ctx, buf);
2438
2439 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2440 }
2441
2442 /* Initialize arguments for the shader export intrinsic */
2443 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2444 LLVMValueRef *values,
2445 unsigned target,
2446 struct ac_export_args *args)
2447 {
2448 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2449 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2450 unsigned chan;
2451 bool is_int8, is_int10;
2452
2453 /* Default is 0xf. Adjusted below depending on the format. */
2454 args->enabled_channels = 0xf; /* writemask */
2455
2456 /* Specify whether the EXEC mask represents the valid mask */
2457 args->valid_mask = 0;
2458
2459 /* Specify whether this is the last export */
2460 args->done = 0;
2461
2462 /* Specify the target we are exporting */
2463 args->target = target;
2464
2465 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2466 const struct si_shader_key *key = &ctx->shader->key;
2467 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2468 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2469
2470 assert(cbuf >= 0 && cbuf < 8);
2471 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2472 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2473 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2474 }
2475
2476 args->compr = false;
2477 args->out[0] = f32undef;
2478 args->out[1] = f32undef;
2479 args->out[2] = f32undef;
2480 args->out[3] = f32undef;
2481
2482 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2483 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2484 unsigned bits, bool hi) = NULL;
2485
2486 switch (spi_shader_col_format) {
2487 case V_028714_SPI_SHADER_ZERO:
2488 args->enabled_channels = 0; /* writemask */
2489 args->target = V_008DFC_SQ_EXP_NULL;
2490 break;
2491
2492 case V_028714_SPI_SHADER_32_R:
2493 args->enabled_channels = 1; /* writemask */
2494 args->out[0] = values[0];
2495 break;
2496
2497 case V_028714_SPI_SHADER_32_GR:
2498 args->enabled_channels = 0x3; /* writemask */
2499 args->out[0] = values[0];
2500 args->out[1] = values[1];
2501 break;
2502
2503 case V_028714_SPI_SHADER_32_AR:
2504 args->enabled_channels = 0x9; /* writemask */
2505 args->out[0] = values[0];
2506 args->out[3] = values[3];
2507 break;
2508
2509 case V_028714_SPI_SHADER_FP16_ABGR:
2510 packf = ac_build_cvt_pkrtz_f16;
2511 break;
2512
2513 case V_028714_SPI_SHADER_UNORM16_ABGR:
2514 packf = ac_build_cvt_pknorm_u16;
2515 break;
2516
2517 case V_028714_SPI_SHADER_SNORM16_ABGR:
2518 packf = ac_build_cvt_pknorm_i16;
2519 break;
2520
2521 case V_028714_SPI_SHADER_UINT16_ABGR:
2522 packi = ac_build_cvt_pk_u16;
2523 break;
2524
2525 case V_028714_SPI_SHADER_SINT16_ABGR:
2526 packi = ac_build_cvt_pk_i16;
2527 break;
2528
2529 case V_028714_SPI_SHADER_32_ABGR:
2530 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2531 break;
2532 }
2533
2534 /* Pack f16 or norm_i16/u16. */
2535 if (packf) {
2536 for (chan = 0; chan < 2; chan++) {
2537 LLVMValueRef pack_args[2] = {
2538 values[2 * chan],
2539 values[2 * chan + 1]
2540 };
2541 LLVMValueRef packed;
2542
2543 packed = packf(&ctx->ac, pack_args);
2544 args->out[chan] = ac_to_float(&ctx->ac, packed);
2545 }
2546 args->compr = 1; /* COMPR flag */
2547 }
2548 /* Pack i16/u16. */
2549 if (packi) {
2550 for (chan = 0; chan < 2; chan++) {
2551 LLVMValueRef pack_args[2] = {
2552 ac_to_integer(&ctx->ac, values[2 * chan]),
2553 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2554 };
2555 LLVMValueRef packed;
2556
2557 packed = packi(&ctx->ac, pack_args,
2558 is_int8 ? 8 : is_int10 ? 10 : 16,
2559 chan == 1);
2560 args->out[chan] = ac_to_float(&ctx->ac, packed);
2561 }
2562 args->compr = 1; /* COMPR flag */
2563 }
2564 }
2565
2566 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2567 LLVMValueRef alpha)
2568 {
2569 struct si_shader_context *ctx = si_shader_context(bld_base);
2570
2571 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2572 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2573 [PIPE_FUNC_LESS] = LLVMRealOLT,
2574 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2575 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2576 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2577 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2578 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2579 };
2580 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2581 assert(cond);
2582
2583 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2584 SI_PARAM_ALPHA_REF);
2585 LLVMValueRef alpha_pass =
2586 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2587 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2588 } else {
2589 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2590 }
2591 }
2592
2593 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2594 LLVMValueRef alpha,
2595 unsigned samplemask_param)
2596 {
2597 struct si_shader_context *ctx = si_shader_context(bld_base);
2598 LLVMValueRef coverage;
2599
2600 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2601 coverage = LLVMGetParam(ctx->main_fn,
2602 samplemask_param);
2603 coverage = ac_to_integer(&ctx->ac, coverage);
2604
2605 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2606 ctx->i32,
2607 &coverage, 1, AC_FUNC_ATTR_READNONE);
2608
2609 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2610 ctx->f32, "");
2611
2612 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2613 LLVMConstReal(ctx->f32,
2614 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2615
2616 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2617 }
2618
2619 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2620 struct ac_export_args *pos, LLVMValueRef *out_elts)
2621 {
2622 unsigned reg_index;
2623 unsigned chan;
2624 unsigned const_chan;
2625 LLVMValueRef base_elt;
2626 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2627 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2628 SI_VS_CONST_CLIP_PLANES, 0);
2629 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2630
2631 for (reg_index = 0; reg_index < 2; reg_index ++) {
2632 struct ac_export_args *args = &pos[2 + reg_index];
2633
2634 args->out[0] =
2635 args->out[1] =
2636 args->out[2] =
2637 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2638
2639 /* Compute dot products of position and user clip plane vectors */
2640 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2641 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2642 LLVMValueRef addr =
2643 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2644 const_chan) * 4, 0);
2645 base_elt = buffer_load_const(ctx, const_resource,
2646 addr);
2647 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2648 out_elts[const_chan], args->out[chan]);
2649 }
2650 }
2651
2652 args->enabled_channels = 0xf;
2653 args->valid_mask = 0;
2654 args->done = 0;
2655 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2656 args->compr = 0;
2657 }
2658 }
2659
2660 static void si_dump_streamout(struct pipe_stream_output_info *so)
2661 {
2662 unsigned i;
2663
2664 if (so->num_outputs)
2665 fprintf(stderr, "STREAMOUT\n");
2666
2667 for (i = 0; i < so->num_outputs; i++) {
2668 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2669 so->output[i].start_component;
2670 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2671 i, so->output[i].output_buffer,
2672 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2673 so->output[i].register_index,
2674 mask & 1 ? "x" : "",
2675 mask & 2 ? "y" : "",
2676 mask & 4 ? "z" : "",
2677 mask & 8 ? "w" : "");
2678 }
2679 }
2680
2681 static void emit_streamout_output(struct si_shader_context *ctx,
2682 LLVMValueRef const *so_buffers,
2683 LLVMValueRef const *so_write_offsets,
2684 struct pipe_stream_output *stream_out,
2685 struct si_shader_output_values *shader_out)
2686 {
2687 unsigned buf_idx = stream_out->output_buffer;
2688 unsigned start = stream_out->start_component;
2689 unsigned num_comps = stream_out->num_components;
2690 LLVMValueRef out[4];
2691
2692 assert(num_comps && num_comps <= 4);
2693 if (!num_comps || num_comps > 4)
2694 return;
2695
2696 /* Load the output as int. */
2697 for (int j = 0; j < num_comps; j++) {
2698 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2699
2700 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2701 }
2702
2703 /* Pack the output. */
2704 LLVMValueRef vdata = NULL;
2705
2706 switch (num_comps) {
2707 case 1: /* as i32 */
2708 vdata = out[0];
2709 break;
2710 case 2: /* as v2i32 */
2711 case 3: /* as v4i32 (aligned to 4) */
2712 out[3] = LLVMGetUndef(ctx->i32);
2713 /* fall through */
2714 case 4: /* as v4i32 */
2715 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2716 break;
2717 }
2718
2719 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2720 vdata, num_comps,
2721 so_write_offsets[buf_idx],
2722 ctx->i32_0,
2723 stream_out->dst_offset * 4, 1, 1, true, false);
2724 }
2725
2726 /**
2727 * Write streamout data to buffers for vertex stream @p stream (different
2728 * vertex streams can occur for GS copy shaders).
2729 */
2730 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2731 struct si_shader_output_values *outputs,
2732 unsigned noutput, unsigned stream)
2733 {
2734 struct si_shader_selector *sel = ctx->shader->selector;
2735 struct pipe_stream_output_info *so = &sel->so;
2736 LLVMBuilderRef builder = ctx->ac.builder;
2737 int i;
2738 struct lp_build_if_state if_ctx;
2739
2740 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2741 LLVMValueRef so_vtx_count =
2742 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2743
2744 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2745
2746 /* can_emit = tid < so_vtx_count; */
2747 LLVMValueRef can_emit =
2748 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2749
2750 /* Emit the streamout code conditionally. This actually avoids
2751 * out-of-bounds buffer access. The hw tells us via the SGPR
2752 * (so_vtx_count) which threads are allowed to emit streamout data. */
2753 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2754 {
2755 /* The buffer offset is computed as follows:
2756 * ByteOffset = streamout_offset[buffer_id]*4 +
2757 * (streamout_write_index + thread_id)*stride[buffer_id] +
2758 * attrib_offset
2759 */
2760
2761 LLVMValueRef so_write_index =
2762 LLVMGetParam(ctx->main_fn,
2763 ctx->param_streamout_write_index);
2764
2765 /* Compute (streamout_write_index + thread_id). */
2766 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2767
2768 /* Load the descriptor and compute the write offset for each
2769 * enabled buffer. */
2770 LLVMValueRef so_write_offset[4] = {};
2771 LLVMValueRef so_buffers[4];
2772 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2773 ctx->param_rw_buffers);
2774
2775 for (i = 0; i < 4; i++) {
2776 if (!so->stride[i])
2777 continue;
2778
2779 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2780 SI_VS_STREAMOUT_BUF0 + i, 0);
2781
2782 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2783
2784 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2785 ctx->param_streamout_offset[i]);
2786 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2787
2788 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2789 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2790 so_offset);
2791 }
2792
2793 /* Write streamout data. */
2794 for (i = 0; i < so->num_outputs; i++) {
2795 unsigned reg = so->output[i].register_index;
2796
2797 if (reg >= noutput)
2798 continue;
2799
2800 if (stream != so->output[i].stream)
2801 continue;
2802
2803 emit_streamout_output(ctx, so_buffers, so_write_offset,
2804 &so->output[i], &outputs[reg]);
2805 }
2806 }
2807 lp_build_endif(&if_ctx);
2808 }
2809
2810 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2811 LLVMValueRef *values)
2812 {
2813 struct ac_export_args args;
2814
2815 si_llvm_init_export_args(ctx, values,
2816 V_008DFC_SQ_EXP_PARAM + index, &args);
2817 ac_build_export(&ctx->ac, &args);
2818 }
2819
2820 static void si_build_param_exports(struct si_shader_context *ctx,
2821 struct si_shader_output_values *outputs,
2822 unsigned noutput)
2823 {
2824 struct si_shader *shader = ctx->shader;
2825 unsigned param_count = 0;
2826
2827 for (unsigned i = 0; i < noutput; i++) {
2828 unsigned semantic_name = outputs[i].semantic_name;
2829 unsigned semantic_index = outputs[i].semantic_index;
2830
2831 if (outputs[i].vertex_stream[0] != 0 &&
2832 outputs[i].vertex_stream[1] != 0 &&
2833 outputs[i].vertex_stream[2] != 0 &&
2834 outputs[i].vertex_stream[3] != 0)
2835 continue;
2836
2837 switch (semantic_name) {
2838 case TGSI_SEMANTIC_LAYER:
2839 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2840 case TGSI_SEMANTIC_CLIPDIST:
2841 case TGSI_SEMANTIC_COLOR:
2842 case TGSI_SEMANTIC_BCOLOR:
2843 case TGSI_SEMANTIC_PRIMID:
2844 case TGSI_SEMANTIC_FOG:
2845 case TGSI_SEMANTIC_TEXCOORD:
2846 case TGSI_SEMANTIC_GENERIC:
2847 break;
2848 default:
2849 continue;
2850 }
2851
2852 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2853 semantic_index < SI_MAX_IO_GENERIC) &&
2854 shader->key.opt.kill_outputs &
2855 (1ull << si_shader_io_get_unique_index(semantic_name,
2856 semantic_index, true)))
2857 continue;
2858
2859 si_export_param(ctx, param_count, outputs[i].values);
2860
2861 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2862 shader->info.vs_output_param_offset[i] = param_count++;
2863 }
2864
2865 shader->info.nr_param_exports = param_count;
2866 }
2867
2868 /* Generate export instructions for hardware VS shader stage */
2869 static void si_llvm_export_vs(struct si_shader_context *ctx,
2870 struct si_shader_output_values *outputs,
2871 unsigned noutput)
2872 {
2873 struct si_shader *shader = ctx->shader;
2874 struct ac_export_args pos_args[4] = {};
2875 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2876 unsigned pos_idx;
2877 int i;
2878
2879 /* Build position exports. */
2880 for (i = 0; i < noutput; i++) {
2881 switch (outputs[i].semantic_name) {
2882 case TGSI_SEMANTIC_POSITION:
2883 si_llvm_init_export_args(ctx, outputs[i].values,
2884 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2885 break;
2886 case TGSI_SEMANTIC_PSIZE:
2887 psize_value = outputs[i].values[0];
2888 break;
2889 case TGSI_SEMANTIC_LAYER:
2890 layer_value = outputs[i].values[0];
2891 break;
2892 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2893 viewport_index_value = outputs[i].values[0];
2894 break;
2895 case TGSI_SEMANTIC_EDGEFLAG:
2896 edgeflag_value = outputs[i].values[0];
2897 break;
2898 case TGSI_SEMANTIC_CLIPDIST:
2899 if (!shader->key.opt.clip_disable) {
2900 unsigned index = 2 + outputs[i].semantic_index;
2901 si_llvm_init_export_args(ctx, outputs[i].values,
2902 V_008DFC_SQ_EXP_POS + index,
2903 &pos_args[index]);
2904 }
2905 break;
2906 case TGSI_SEMANTIC_CLIPVERTEX:
2907 if (!shader->key.opt.clip_disable) {
2908 si_llvm_emit_clipvertex(ctx, pos_args,
2909 outputs[i].values);
2910 }
2911 break;
2912 }
2913 }
2914
2915 /* We need to add the position output manually if it's missing. */
2916 if (!pos_args[0].out[0]) {
2917 pos_args[0].enabled_channels = 0xf; /* writemask */
2918 pos_args[0].valid_mask = 0; /* EXEC mask */
2919 pos_args[0].done = 0; /* last export? */
2920 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2921 pos_args[0].compr = 0; /* COMPR flag */
2922 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2923 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2924 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2925 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2926 }
2927
2928 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2929 if (shader->selector->info.writes_psize ||
2930 shader->selector->info.writes_edgeflag ||
2931 shader->selector->info.writes_viewport_index ||
2932 shader->selector->info.writes_layer) {
2933 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2934 (shader->selector->info.writes_edgeflag << 1) |
2935 (shader->selector->info.writes_layer << 2);
2936
2937 pos_args[1].valid_mask = 0; /* EXEC mask */
2938 pos_args[1].done = 0; /* last export? */
2939 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2940 pos_args[1].compr = 0; /* COMPR flag */
2941 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2942 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2943 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2944 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2945
2946 if (shader->selector->info.writes_psize)
2947 pos_args[1].out[0] = psize_value;
2948
2949 if (shader->selector->info.writes_edgeflag) {
2950 /* The output is a float, but the hw expects an integer
2951 * with the first bit containing the edge flag. */
2952 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2953 edgeflag_value,
2954 ctx->i32, "");
2955 edgeflag_value = ac_build_umin(&ctx->ac,
2956 edgeflag_value,
2957 ctx->i32_1);
2958
2959 /* The LLVM intrinsic expects a float. */
2960 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2961 }
2962
2963 if (ctx->screen->info.chip_class >= GFX9) {
2964 /* GFX9 has the layer in out.z[10:0] and the viewport
2965 * index in out.z[19:16].
2966 */
2967 if (shader->selector->info.writes_layer)
2968 pos_args[1].out[2] = layer_value;
2969
2970 if (shader->selector->info.writes_viewport_index) {
2971 LLVMValueRef v = viewport_index_value;
2972
2973 v = ac_to_integer(&ctx->ac, v);
2974 v = LLVMBuildShl(ctx->ac.builder, v,
2975 LLVMConstInt(ctx->i32, 16, 0), "");
2976 v = LLVMBuildOr(ctx->ac.builder, v,
2977 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2978 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2979 pos_args[1].enabled_channels |= 1 << 2;
2980 }
2981 } else {
2982 if (shader->selector->info.writes_layer)
2983 pos_args[1].out[2] = layer_value;
2984
2985 if (shader->selector->info.writes_viewport_index) {
2986 pos_args[1].out[3] = viewport_index_value;
2987 pos_args[1].enabled_channels |= 1 << 3;
2988 }
2989 }
2990 }
2991
2992 for (i = 0; i < 4; i++)
2993 if (pos_args[i].out[0])
2994 shader->info.nr_pos_exports++;
2995
2996 pos_idx = 0;
2997 for (i = 0; i < 4; i++) {
2998 if (!pos_args[i].out[0])
2999 continue;
3000
3001 /* Specify the target we are exporting */
3002 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3003
3004 if (pos_idx == shader->info.nr_pos_exports)
3005 /* Specify that this is the last export */
3006 pos_args[i].done = 1;
3007
3008 ac_build_export(&ctx->ac, &pos_args[i]);
3009 }
3010
3011 /* Build parameter exports. */
3012 si_build_param_exports(ctx, outputs, noutput);
3013 }
3014
3015 /**
3016 * Forward all outputs from the vertex shader to the TES. This is only used
3017 * for the fixed function TCS.
3018 */
3019 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3020 {
3021 struct si_shader_context *ctx = si_shader_context(bld_base);
3022 LLVMValueRef invocation_id, buffer, buffer_offset;
3023 LLVMValueRef lds_vertex_stride, lds_base;
3024 uint64_t inputs;
3025
3026 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3027 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3028 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3029
3030 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3031 lds_base = get_tcs_in_current_patch_offset(ctx);
3032 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3033 lds_base);
3034
3035 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3036 while (inputs) {
3037 unsigned i = u_bit_scan64(&inputs);
3038
3039 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3040 LLVMConstInt(ctx->i32, 4 * i, 0),
3041 "");
3042
3043 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3044 get_rel_patch_id(ctx),
3045 invocation_id,
3046 LLVMConstInt(ctx->i32, i, 0));
3047
3048 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3049 lds_ptr);
3050
3051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3052 buffer_offset, 0, 1, 0, true, false);
3053 }
3054 }
3055
3056 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3057 LLVMValueRef rel_patch_id,
3058 LLVMValueRef invocation_id,
3059 LLVMValueRef tcs_out_current_patch_data_offset,
3060 LLVMValueRef invoc0_tf_outer[4],
3061 LLVMValueRef invoc0_tf_inner[2])
3062 {
3063 struct si_shader_context *ctx = si_shader_context(bld_base);
3064 struct si_shader *shader = ctx->shader;
3065 unsigned tess_inner_index, tess_outer_index;
3066 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3067 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3068 unsigned stride, outer_comps, inner_comps, i, offset;
3069 struct lp_build_if_state if_ctx, inner_if_ctx;
3070
3071 /* Add a barrier before loading tess factors from LDS. */
3072 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3073 si_llvm_emit_barrier(NULL, bld_base, NULL);
3074
3075 /* Do this only for invocation 0, because the tess levels are per-patch,
3076 * not per-vertex.
3077 *
3078 * This can't jump, because invocation 0 executes this. It should
3079 * at least mask out the loads and stores for other invocations.
3080 */
3081 lp_build_if(&if_ctx, &ctx->gallivm,
3082 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3083 invocation_id, ctx->i32_0, ""));
3084
3085 /* Determine the layout of one tess factor element in the buffer. */
3086 switch (shader->key.part.tcs.epilog.prim_mode) {
3087 case PIPE_PRIM_LINES:
3088 stride = 2; /* 2 dwords, 1 vec2 store */
3089 outer_comps = 2;
3090 inner_comps = 0;
3091 break;
3092 case PIPE_PRIM_TRIANGLES:
3093 stride = 4; /* 4 dwords, 1 vec4 store */
3094 outer_comps = 3;
3095 inner_comps = 1;
3096 break;
3097 case PIPE_PRIM_QUADS:
3098 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3099 outer_comps = 4;
3100 inner_comps = 2;
3101 break;
3102 default:
3103 assert(0);
3104 return;
3105 }
3106
3107 for (i = 0; i < 4; i++) {
3108 inner[i] = LLVMGetUndef(ctx->i32);
3109 outer[i] = LLVMGetUndef(ctx->i32);
3110 }
3111
3112 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3113 /* Tess factors are in VGPRs. */
3114 for (i = 0; i < outer_comps; i++)
3115 outer[i] = out[i] = invoc0_tf_outer[i];
3116 for (i = 0; i < inner_comps; i++)
3117 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3118 } else {
3119 /* Load tess_inner and tess_outer from LDS.
3120 * Any invocation can write them, so we can't get them from a temporary.
3121 */
3122 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3123 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3124
3125 lds_base = tcs_out_current_patch_data_offset;
3126 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3127 LLVMConstInt(ctx->i32,
3128 tess_inner_index * 4, 0), "");
3129 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3130 LLVMConstInt(ctx->i32,
3131 tess_outer_index * 4, 0), "");
3132
3133 for (i = 0; i < outer_comps; i++) {
3134 outer[i] = out[i] =
3135 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3136 }
3137 for (i = 0; i < inner_comps; i++) {
3138 inner[i] = out[outer_comps+i] =
3139 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3140 }
3141 }
3142
3143 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3144 /* For isolines, the hardware expects tess factors in the
3145 * reverse order from what GLSL / TGSI specify.
3146 */
3147 LLVMValueRef tmp = out[0];
3148 out[0] = out[1];
3149 out[1] = tmp;
3150 }
3151
3152 /* Convert the outputs to vectors for stores. */
3153 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3154 vec1 = NULL;
3155
3156 if (stride > 4)
3157 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3158
3159 /* Get the buffer. */
3160 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3161
3162 /* Get the offset. */
3163 tf_base = LLVMGetParam(ctx->main_fn,
3164 ctx->param_tcs_factor_offset);
3165 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3166 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3167
3168 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3169 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3170 rel_patch_id, ctx->i32_0, ""));
3171
3172 /* Store the dynamic HS control word. */
3173 offset = 0;
3174 if (ctx->screen->info.chip_class <= VI) {
3175 ac_build_buffer_store_dword(&ctx->ac, buffer,
3176 LLVMConstInt(ctx->i32, 0x80000000, 0),
3177 1, ctx->i32_0, tf_base,
3178 offset, 1, 0, true, false);
3179 offset += 4;
3180 }
3181
3182 lp_build_endif(&inner_if_ctx);
3183
3184 /* Store the tessellation factors. */
3185 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3186 MIN2(stride, 4), byteoffset, tf_base,
3187 offset, 1, 0, true, false);
3188 offset += 16;
3189 if (vec1)
3190 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3191 stride - 4, byteoffset, tf_base,
3192 offset, 1, 0, true, false);
3193
3194 /* Store the tess factors into the offchip buffer if TES reads them. */
3195 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3196 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3197 LLVMValueRef tf_inner_offset;
3198 unsigned param_outer, param_inner;
3199
3200 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3201 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3202
3203 param_outer = si_shader_io_get_unique_index_patch(
3204 TGSI_SEMANTIC_TESSOUTER, 0);
3205 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3206 LLVMConstInt(ctx->i32, param_outer, 0));
3207
3208 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3209 util_next_power_of_two(outer_comps));
3210
3211 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3212 outer_comps, tf_outer_offset,
3213 base, 0, 1, 0, true, false);
3214 if (inner_comps) {
3215 param_inner = si_shader_io_get_unique_index_patch(
3216 TGSI_SEMANTIC_TESSINNER, 0);
3217 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3218 LLVMConstInt(ctx->i32, param_inner, 0));
3219
3220 inner_vec = inner_comps == 1 ? inner[0] :
3221 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3222 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3223 inner_comps, tf_inner_offset,
3224 base, 0, 1, 0, true, false);
3225 }
3226 }
3227
3228 lp_build_endif(&if_ctx);
3229 }
3230
3231 static LLVMValueRef
3232 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3233 unsigned param, unsigned return_index)
3234 {
3235 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3236 LLVMGetParam(ctx->main_fn, param),
3237 return_index, "");
3238 }
3239
3240 static LLVMValueRef
3241 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3242 unsigned param, unsigned return_index)
3243 {
3244 LLVMBuilderRef builder = ctx->ac.builder;
3245 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3246
3247 return LLVMBuildInsertValue(builder, ret,
3248 ac_to_float(&ctx->ac, p),
3249 return_index, "");
3250 }
3251
3252 static LLVMValueRef
3253 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3254 unsigned param, unsigned return_index)
3255 {
3256 LLVMBuilderRef builder = ctx->ac.builder;
3257 LLVMValueRef ptr, lo, hi;
3258
3259 ptr = LLVMGetParam(ctx->main_fn, param);
3260 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3261 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3262 }
3263
3264 /* This only writes the tessellation factor levels. */
3265 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3266 unsigned max_outputs,
3267 LLVMValueRef *addrs)
3268 {
3269 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3270 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3271 LLVMBuilderRef builder = ctx->ac.builder;
3272 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3273
3274 si_copy_tcs_inputs(bld_base);
3275
3276 rel_patch_id = get_rel_patch_id(ctx);
3277 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3278 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3279
3280 if (ctx->screen->info.chip_class >= GFX9) {
3281 LLVMBasicBlockRef blocks[2] = {
3282 LLVMGetInsertBlock(builder),
3283 ctx->merged_wrap_if_state.entry_block
3284 };
3285 LLVMValueRef values[2];
3286
3287 lp_build_endif(&ctx->merged_wrap_if_state);
3288
3289 values[0] = rel_patch_id;
3290 values[1] = LLVMGetUndef(ctx->i32);
3291 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3292
3293 values[0] = tf_lds_offset;
3294 values[1] = LLVMGetUndef(ctx->i32);
3295 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3296
3297 values[0] = invocation_id;
3298 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3299 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3300 }
3301
3302 /* Return epilog parameters from this function. */
3303 LLVMValueRef ret = ctx->return_value;
3304 unsigned vgpr;
3305
3306 if (ctx->screen->info.chip_class >= GFX9) {
3307 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3308 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3309 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3310 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3311 /* Tess offchip and tess factor offsets are at the beginning. */
3312 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3313 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3314 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3315 } else {
3316 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3317 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3318 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3319 GFX6_SGPR_TCS_OUT_LAYOUT);
3320 /* Tess offchip and tess factor offsets are after user SGPRs. */
3321 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3322 GFX6_TCS_NUM_USER_SGPR);
3323 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3324 GFX6_TCS_NUM_USER_SGPR + 1);
3325 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3326 }
3327
3328 /* VGPRs */
3329 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3330 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3331 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3332
3333 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3334 * the invocation_id output does not alias the tcs_rel_ids input,
3335 * which saves a V_MOV on gfx9.
3336 */
3337 vgpr += 2;
3338
3339 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3340 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3341
3342 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3343 vgpr++; /* skip the tess factor LDS offset */
3344 for (unsigned i = 0; i < 6; i++) {
3345 LLVMValueRef value =
3346 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3347 value = ac_to_float(&ctx->ac, value);
3348 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3349 }
3350 } else {
3351 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3352 }
3353 ctx->return_value = ret;
3354 }
3355
3356 /* Pass TCS inputs from LS to TCS on GFX9. */
3357 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3358 {
3359 LLVMValueRef ret = ctx->return_value;
3360
3361 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3362 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3363 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3364 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3365 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3366 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3367
3368 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3369 8 + SI_SGPR_RW_BUFFERS);
3370 ret = si_insert_input_ptr(ctx, ret,
3371 ctx->param_bindless_samplers_and_images,
3372 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3373
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3375 8 + SI_SGPR_VS_STATE_BITS);
3376
3377 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3378 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3379 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3380 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3381 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3382 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3383
3384 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3385 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3386 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3387 vgpr++, "");
3388 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3389 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3390 vgpr++, "");
3391 ctx->return_value = ret;
3392 }
3393
3394 /* Pass GS inputs from ES to GS on GFX9. */
3395 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3396 {
3397 LLVMValueRef ret = ctx->return_value;
3398
3399 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3400 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3401 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3402 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3403 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3404
3405 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3406 8 + SI_SGPR_RW_BUFFERS);
3407 ret = si_insert_input_ptr(ctx, ret,
3408 ctx->param_bindless_samplers_and_images,
3409 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3410
3411 unsigned vgpr;
3412 if (ctx->type == PIPE_SHADER_VERTEX)
3413 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3414 else
3415 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3416
3417 for (unsigned i = 0; i < 5; i++) {
3418 unsigned param = ctx->param_gs_vtx01_offset + i;
3419 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3420 }
3421 ctx->return_value = ret;
3422 }
3423
3424 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3425 unsigned max_outputs,
3426 LLVMValueRef *addrs)
3427 {
3428 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3429 struct si_shader *shader = ctx->shader;
3430 struct tgsi_shader_info *info = &shader->selector->info;
3431 unsigned i, chan;
3432 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3433 ctx->param_rel_auto_id);
3434 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3435 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3436 vertex_dw_stride, "");
3437
3438 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3439 * its inputs from it. */
3440 for (i = 0; i < info->num_outputs; i++) {
3441 unsigned name = info->output_semantic_name[i];
3442 unsigned index = info->output_semantic_index[i];
3443
3444 /* The ARB_shader_viewport_layer_array spec contains the
3445 * following issue:
3446 *
3447 * 2) What happens if gl_ViewportIndex or gl_Layer is
3448 * written in the vertex shader and a geometry shader is
3449 * present?
3450 *
3451 * RESOLVED: The value written by the last vertex processing
3452 * stage is used. If the last vertex processing stage
3453 * (vertex, tessellation evaluation or geometry) does not
3454 * statically assign to gl_ViewportIndex or gl_Layer, index
3455 * or layer zero is assumed.
3456 *
3457 * So writes to those outputs in VS-as-LS are simply ignored.
3458 */
3459 if (name == TGSI_SEMANTIC_LAYER ||
3460 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3461 continue;
3462
3463 int param = si_shader_io_get_unique_index(name, index, false);
3464 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3465 LLVMConstInt(ctx->i32, param * 4, 0), "");
3466
3467 for (chan = 0; chan < 4; chan++) {
3468 if (!(info->output_usagemask[i] & (1 << chan)))
3469 continue;
3470
3471 lds_store(ctx, chan, dw_addr,
3472 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3473 }
3474 }
3475
3476 if (ctx->screen->info.chip_class >= GFX9)
3477 si_set_ls_return_value_for_tcs(ctx);
3478 }
3479
3480 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3481 unsigned max_outputs,
3482 LLVMValueRef *addrs)
3483 {
3484 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3485 struct si_shader *es = ctx->shader;
3486 struct tgsi_shader_info *info = &es->selector->info;
3487 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3488 ctx->param_es2gs_offset);
3489 LLVMValueRef lds_base = NULL;
3490 unsigned chan;
3491 int i;
3492
3493 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3494 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3495 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3496 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3497 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3498 LLVMBuildMul(ctx->ac.builder, wave_idx,
3499 LLVMConstInt(ctx->i32, 64, false), ""), "");
3500 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3501 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3502 }
3503
3504 for (i = 0; i < info->num_outputs; i++) {
3505 int param;
3506
3507 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3508 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3509 continue;
3510
3511 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3512 info->output_semantic_index[i], false);
3513
3514 for (chan = 0; chan < 4; chan++) {
3515 if (!(info->output_usagemask[i] & (1 << chan)))
3516 continue;
3517
3518 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3519 out_val = ac_to_integer(&ctx->ac, out_val);
3520
3521 /* GFX9 has the ESGS ring in LDS. */
3522 if (ctx->screen->info.chip_class >= GFX9) {
3523 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3524 continue;
3525 }
3526
3527 ac_build_buffer_store_dword(&ctx->ac,
3528 ctx->esgs_ring,
3529 out_val, 1, NULL, soffset,
3530 (4 * param + chan) * 4,
3531 1, 1, true, true);
3532 }
3533 }
3534
3535 if (ctx->screen->info.chip_class >= GFX9)
3536 si_set_es_return_value_for_gs(ctx);
3537 }
3538
3539 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3540 {
3541 if (ctx->screen->info.chip_class >= GFX9)
3542 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3543 else
3544 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3545 }
3546
3547 static void emit_gs_epilogue(struct si_shader_context *ctx)
3548 {
3549 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3550 si_get_gs_wave_id(ctx));
3551
3552 if (ctx->screen->info.chip_class >= GFX9)
3553 lp_build_endif(&ctx->merged_wrap_if_state);
3554 }
3555
3556 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3557 unsigned max_outputs,
3558 LLVMValueRef *addrs)
3559 {
3560 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3561 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3562
3563 assert(info->num_outputs <= max_outputs);
3564
3565 emit_gs_epilogue(ctx);
3566 }
3567
3568 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3569 {
3570 struct si_shader_context *ctx = si_shader_context(bld_base);
3571 emit_gs_epilogue(ctx);
3572 }
3573
3574 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3575 unsigned max_outputs,
3576 LLVMValueRef *addrs)
3577 {
3578 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3579 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3580 struct si_shader_output_values *outputs = NULL;
3581 int i,j;
3582
3583 assert(!ctx->shader->is_gs_copy_shader);
3584 assert(info->num_outputs <= max_outputs);
3585
3586 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3587
3588 /* Vertex color clamping.
3589 *
3590 * This uses a state constant loaded in a user data SGPR and
3591 * an IF statement is added that clamps all colors if the constant
3592 * is true.
3593 */
3594 struct lp_build_if_state if_ctx;
3595 LLVMValueRef cond = NULL;
3596 LLVMValueRef addr, val;
3597
3598 for (i = 0; i < info->num_outputs; i++) {
3599 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3600 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3601 continue;
3602
3603 /* We've found a color. */
3604 if (!cond) {
3605 /* The state is in the first bit of the user SGPR. */
3606 cond = LLVMGetParam(ctx->main_fn,
3607 ctx->param_vs_state_bits);
3608 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3609 ctx->i1, "");
3610 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3611 }
3612
3613 for (j = 0; j < 4; j++) {
3614 addr = addrs[4 * i + j];
3615 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3616 val = ac_build_clamp(&ctx->ac, val);
3617 LLVMBuildStore(ctx->ac.builder, val, addr);
3618 }
3619 }
3620
3621 if (cond)
3622 lp_build_endif(&if_ctx);
3623
3624 for (i = 0; i < info->num_outputs; i++) {
3625 outputs[i].semantic_name = info->output_semantic_name[i];
3626 outputs[i].semantic_index = info->output_semantic_index[i];
3627
3628 for (j = 0; j < 4; j++) {
3629 outputs[i].values[j] =
3630 LLVMBuildLoad(ctx->ac.builder,
3631 addrs[4 * i + j],
3632 "");
3633 outputs[i].vertex_stream[j] =
3634 (info->output_streams[i] >> (2 * j)) & 3;
3635 }
3636 }
3637
3638 if (ctx->shader->selector->so.num_outputs)
3639 si_llvm_emit_streamout(ctx, outputs, i, 0);
3640
3641 /* Export PrimitiveID. */
3642 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3643 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3644 outputs[i].semantic_index = 0;
3645 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3646 for (j = 1; j < 4; j++)
3647 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3648
3649 memset(outputs[i].vertex_stream, 0,
3650 sizeof(outputs[i].vertex_stream));
3651 i++;
3652 }
3653
3654 si_llvm_export_vs(ctx, outputs, i);
3655 FREE(outputs);
3656 }
3657
3658 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3659 {
3660 struct si_shader_context *ctx = si_shader_context(bld_base);
3661
3662 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3663 &ctx->outputs[0][0]);
3664 }
3665
3666 struct si_ps_exports {
3667 unsigned num;
3668 struct ac_export_args args[10];
3669 };
3670
3671 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3672 LLVMValueRef depth, LLVMValueRef stencil,
3673 LLVMValueRef samplemask, struct si_ps_exports *exp)
3674 {
3675 struct si_shader_context *ctx = si_shader_context(bld_base);
3676 struct ac_export_args args;
3677
3678 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3679
3680 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3681 }
3682
3683 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3684 LLVMValueRef *color, unsigned index,
3685 unsigned samplemask_param,
3686 bool is_last, struct si_ps_exports *exp)
3687 {
3688 struct si_shader_context *ctx = si_shader_context(bld_base);
3689 int i;
3690
3691 /* Clamp color */
3692 if (ctx->shader->key.part.ps.epilog.clamp_color)
3693 for (i = 0; i < 4; i++)
3694 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3695
3696 /* Alpha to one */
3697 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3698 color[3] = ctx->ac.f32_1;
3699
3700 /* Alpha test */
3701 if (index == 0 &&
3702 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3703 si_alpha_test(bld_base, color[3]);
3704
3705 /* Line & polygon smoothing */
3706 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3707 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3708 samplemask_param);
3709
3710 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3711 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3712 struct ac_export_args args[8];
3713 int c, last = -1;
3714
3715 /* Get the export arguments, also find out what the last one is. */
3716 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3717 si_llvm_init_export_args(ctx, color,
3718 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3719 if (args[c].enabled_channels)
3720 last = c;
3721 }
3722
3723 /* Emit all exports. */
3724 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3725 if (is_last && last == c) {
3726 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3727 args[c].done = 1; /* DONE bit */
3728 } else if (!args[c].enabled_channels)
3729 continue; /* unnecessary NULL export */
3730
3731 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3732 }
3733 } else {
3734 struct ac_export_args args;
3735
3736 /* Export */
3737 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3738 &args);
3739 if (is_last) {
3740 args.valid_mask = 1; /* whether the EXEC mask is valid */
3741 args.done = 1; /* DONE bit */
3742 } else if (!args.enabled_channels)
3743 return; /* unnecessary NULL export */
3744
3745 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3746 }
3747 }
3748
3749 static void si_emit_ps_exports(struct si_shader_context *ctx,
3750 struct si_ps_exports *exp)
3751 {
3752 for (unsigned i = 0; i < exp->num; i++)
3753 ac_build_export(&ctx->ac, &exp->args[i]);
3754 }
3755
3756 /**
3757 * Return PS outputs in this order:
3758 *
3759 * v[0:3] = color0.xyzw
3760 * v[4:7] = color1.xyzw
3761 * ...
3762 * vN+0 = Depth
3763 * vN+1 = Stencil
3764 * vN+2 = SampleMask
3765 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3766 *
3767 * The alpha-ref SGPR is returned via its original location.
3768 */
3769 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3770 unsigned max_outputs,
3771 LLVMValueRef *addrs)
3772 {
3773 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3774 struct si_shader *shader = ctx->shader;
3775 struct tgsi_shader_info *info = &shader->selector->info;
3776 LLVMBuilderRef builder = ctx->ac.builder;
3777 unsigned i, j, first_vgpr, vgpr;
3778
3779 LLVMValueRef color[8][4] = {};
3780 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3781 LLVMValueRef ret;
3782
3783 if (ctx->postponed_kill)
3784 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3785
3786 /* Read the output values. */
3787 for (i = 0; i < info->num_outputs; i++) {
3788 unsigned semantic_name = info->output_semantic_name[i];
3789 unsigned semantic_index = info->output_semantic_index[i];
3790
3791 switch (semantic_name) {
3792 case TGSI_SEMANTIC_COLOR:
3793 assert(semantic_index < 8);
3794 for (j = 0; j < 4; j++) {
3795 LLVMValueRef ptr = addrs[4 * i + j];
3796 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3797 color[semantic_index][j] = result;
3798 }
3799 break;
3800 case TGSI_SEMANTIC_POSITION:
3801 depth = LLVMBuildLoad(builder,
3802 addrs[4 * i + 2], "");
3803 break;
3804 case TGSI_SEMANTIC_STENCIL:
3805 stencil = LLVMBuildLoad(builder,
3806 addrs[4 * i + 1], "");
3807 break;
3808 case TGSI_SEMANTIC_SAMPLEMASK:
3809 samplemask = LLVMBuildLoad(builder,
3810 addrs[4 * i + 0], "");
3811 break;
3812 default:
3813 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3814 semantic_name);
3815 }
3816 }
3817
3818 /* Fill the return structure. */
3819 ret = ctx->return_value;
3820
3821 /* Set SGPRs. */
3822 ret = LLVMBuildInsertValue(builder, ret,
3823 ac_to_integer(&ctx->ac,
3824 LLVMGetParam(ctx->main_fn,
3825 SI_PARAM_ALPHA_REF)),
3826 SI_SGPR_ALPHA_REF, "");
3827
3828 /* Set VGPRs */
3829 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3830 for (i = 0; i < ARRAY_SIZE(color); i++) {
3831 if (!color[i][0])
3832 continue;
3833
3834 for (j = 0; j < 4; j++)
3835 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3836 }
3837 if (depth)
3838 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3839 if (stencil)
3840 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3841 if (samplemask)
3842 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3843
3844 /* Add the input sample mask for smoothing at the end. */
3845 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3846 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3847 ret = LLVMBuildInsertValue(builder, ret,
3848 LLVMGetParam(ctx->main_fn,
3849 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3850
3851 ctx->return_value = ret;
3852 }
3853
3854 static void membar_emit(
3855 const struct lp_build_tgsi_action *action,
3856 struct lp_build_tgsi_context *bld_base,
3857 struct lp_build_emit_data *emit_data)
3858 {
3859 struct si_shader_context *ctx = si_shader_context(bld_base);
3860 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3861 unsigned flags = LLVMConstIntGetZExtValue(src0);
3862 unsigned waitcnt = NOOP_WAITCNT;
3863
3864 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3865 waitcnt &= VM_CNT & LGKM_CNT;
3866
3867 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3868 TGSI_MEMBAR_SHADER_BUFFER |
3869 TGSI_MEMBAR_SHADER_IMAGE))
3870 waitcnt &= VM_CNT;
3871
3872 if (flags & TGSI_MEMBAR_SHARED)
3873 waitcnt &= LGKM_CNT;
3874
3875 if (waitcnt != NOOP_WAITCNT)
3876 ac_build_waitcnt(&ctx->ac, waitcnt);
3877 }
3878
3879 static void clock_emit(
3880 const struct lp_build_tgsi_action *action,
3881 struct lp_build_tgsi_context *bld_base,
3882 struct lp_build_emit_data *emit_data)
3883 {
3884 struct si_shader_context *ctx = si_shader_context(bld_base);
3885 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3886
3887 emit_data->output[0] =
3888 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3889 emit_data->output[1] =
3890 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3891 }
3892
3893 static void si_llvm_emit_ddxy(
3894 const struct lp_build_tgsi_action *action,
3895 struct lp_build_tgsi_context *bld_base,
3896 struct lp_build_emit_data *emit_data)
3897 {
3898 struct si_shader_context *ctx = si_shader_context(bld_base);
3899 unsigned opcode = emit_data->info->opcode;
3900 LLVMValueRef val;
3901 int idx;
3902 unsigned mask;
3903
3904 if (opcode == TGSI_OPCODE_DDX_FINE)
3905 mask = AC_TID_MASK_LEFT;
3906 else if (opcode == TGSI_OPCODE_DDY_FINE)
3907 mask = AC_TID_MASK_TOP;
3908 else
3909 mask = AC_TID_MASK_TOP_LEFT;
3910
3911 /* for DDX we want to next X pixel, DDY next Y pixel. */
3912 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3913
3914 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3915 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3916 emit_data->output[emit_data->chan] = val;
3917 }
3918
3919 /*
3920 * this takes an I,J coordinate pair,
3921 * and works out the X and Y derivatives.
3922 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3923 */
3924 static LLVMValueRef si_llvm_emit_ddxy_interp(
3925 struct lp_build_tgsi_context *bld_base,
3926 LLVMValueRef interp_ij)
3927 {
3928 struct si_shader_context *ctx = si_shader_context(bld_base);
3929 LLVMValueRef result[4], a;
3930 unsigned i;
3931
3932 for (i = 0; i < 2; i++) {
3933 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3934 LLVMConstInt(ctx->i32, i, 0), "");
3935 result[i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 1,
3936 ac_to_integer(&ctx->ac, a)); /* DDX */
3937 result[2+i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 2,
3938 ac_to_integer(&ctx->ac, a)); /* DDY */
3939 }
3940
3941 return ac_build_gather_values(&ctx->ac, result, 4);
3942 }
3943
3944 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3945 struct lp_build_tgsi_context *bld_base,
3946 struct lp_build_emit_data *emit_data)
3947 {
3948 struct si_shader_context *ctx = si_shader_context(bld_base);
3949 struct si_shader *shader = ctx->shader;
3950 const struct tgsi_shader_info *info = &shader->selector->info;
3951 LLVMValueRef interp_param;
3952 const struct tgsi_full_instruction *inst = emit_data->inst;
3953 const struct tgsi_full_src_register *input = &inst->Src[0];
3954 int input_base, input_array_size;
3955 int chan;
3956 int i;
3957 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3958 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3959 int interp_param_idx;
3960 unsigned interp;
3961 unsigned location;
3962
3963 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3964 /* offset is in second src, first two channels */
3965 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3966 TGSI_CHAN_X);
3967 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3968 TGSI_CHAN_Y);
3969 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3970 LLVMValueRef sample_position;
3971 LLVMValueRef sample_id;
3972 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3973
3974 /* fetch sample ID, then fetch its sample position,
3975 * and place into first two channels.
3976 */
3977 sample_id = lp_build_emit_fetch(bld_base,
3978 emit_data->inst, 1, TGSI_CHAN_X);
3979 sample_id = ac_to_integer(&ctx->ac, sample_id);
3980
3981 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3982 * Language 4.50 spec says about interpolateAtSample:
3983 *
3984 * "Returns the value of the input interpolant variable at
3985 * the location of sample number sample. If multisample
3986 * buffers are not available, the input variable will be
3987 * evaluated at the center of the pixel. If sample sample
3988 * does not exist, the position used to interpolate the
3989 * input variable is undefined."
3990 *
3991 * This means that sample_id values outside of the valid are
3992 * in fact valid input, and the usual mechanism for loading the
3993 * sample position doesn't work.
3994 */
3995 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3996 LLVMValueRef center[4] = {
3997 LLVMConstReal(ctx->f32, 0.5),
3998 LLVMConstReal(ctx->f32, 0.5),
3999 ctx->ac.f32_0,
4000 ctx->ac.f32_0,
4001 };
4002
4003 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4004 } else {
4005 sample_position = load_sample_position(&ctx->abi, sample_id);
4006 }
4007
4008 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4009 ctx->i32_0, "");
4010
4011 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4012 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4013 ctx->i32_1, "");
4014 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4015 }
4016
4017 assert(input->Register.File == TGSI_FILE_INPUT);
4018
4019 if (input->Register.Indirect) {
4020 unsigned array_id = input->Indirect.ArrayID;
4021
4022 if (array_id) {
4023 input_base = info->input_array_first[array_id];
4024 input_array_size = info->input_array_last[array_id] - input_base + 1;
4025 } else {
4026 input_base = inst->Src[0].Register.Index;
4027 input_array_size = info->num_inputs - input_base;
4028 }
4029
4030 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4031 1, input->Register.Index - input_base);
4032 } else {
4033 input_base = inst->Src[0].Register.Index;
4034 input_array_size = 1;
4035 array_idx = ctx->i32_0;
4036 }
4037
4038 interp = shader->selector->info.input_interpolate[input_base];
4039
4040 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4041 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4042 location = TGSI_INTERPOLATE_LOC_CENTER;
4043 else
4044 location = TGSI_INTERPOLATE_LOC_CENTROID;
4045
4046 interp_param_idx = lookup_interp_param_index(interp, location);
4047 if (interp_param_idx == -1)
4048 return;
4049 else if (interp_param_idx)
4050 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4051 else
4052 interp_param = NULL;
4053
4054 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4055 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4056 LLVMValueRef ij_out[2];
4057 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4058
4059 /*
4060 * take the I then J parameters, and the DDX/Y for it, and
4061 * calculate the IJ inputs for the interpolator.
4062 * temp1 = ddx * offset/sample.x + I;
4063 * interp_param.I = ddy * offset/sample.y + temp1;
4064 * temp1 = ddx * offset/sample.x + J;
4065 * interp_param.J = ddy * offset/sample.y + temp1;
4066 */
4067 for (i = 0; i < 2; i++) {
4068 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4069 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4070 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4071 ddxy_out, ix_ll, "");
4072 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4073 ddxy_out, iy_ll, "");
4074 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4075 interp_param, ix_ll, "");
4076 LLVMValueRef temp;
4077
4078 interp_el = ac_to_float(&ctx->ac, interp_el);
4079
4080 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4081 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4082 }
4083 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4084 }
4085
4086 if (interp_param)
4087 interp_param = ac_to_float(&ctx->ac, interp_param);
4088
4089 for (chan = 0; chan < 4; chan++) {
4090 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4091 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4092
4093 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4094 LLVMValueRef v, i = NULL, j = NULL;
4095
4096 if (interp_param) {
4097 i = LLVMBuildExtractElement(
4098 ctx->ac.builder, interp_param, ctx->i32_0, "");
4099 j = LLVMBuildExtractElement(
4100 ctx->ac.builder, interp_param, ctx->i32_1, "");
4101 }
4102 v = si_build_fs_interp(ctx, input_base + idx, schan,
4103 prim_mask, i, j);
4104
4105 gather = LLVMBuildInsertElement(ctx->ac.builder,
4106 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4107 }
4108
4109 emit_data->output[chan] = LLVMBuildExtractElement(
4110 ctx->ac.builder, gather, array_idx, "");
4111 }
4112 }
4113
4114 static void vote_all_emit(
4115 const struct lp_build_tgsi_action *action,
4116 struct lp_build_tgsi_context *bld_base,
4117 struct lp_build_emit_data *emit_data)
4118 {
4119 struct si_shader_context *ctx = si_shader_context(bld_base);
4120
4121 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4122 emit_data->output[emit_data->chan] =
4123 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4124 }
4125
4126 static void vote_any_emit(
4127 const struct lp_build_tgsi_action *action,
4128 struct lp_build_tgsi_context *bld_base,
4129 struct lp_build_emit_data *emit_data)
4130 {
4131 struct si_shader_context *ctx = si_shader_context(bld_base);
4132
4133 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4134 emit_data->output[emit_data->chan] =
4135 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4136 }
4137
4138 static void vote_eq_emit(
4139 const struct lp_build_tgsi_action *action,
4140 struct lp_build_tgsi_context *bld_base,
4141 struct lp_build_emit_data *emit_data)
4142 {
4143 struct si_shader_context *ctx = si_shader_context(bld_base);
4144
4145 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4146 emit_data->output[emit_data->chan] =
4147 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4148 }
4149
4150 static void ballot_emit(
4151 const struct lp_build_tgsi_action *action,
4152 struct lp_build_tgsi_context *bld_base,
4153 struct lp_build_emit_data *emit_data)
4154 {
4155 struct si_shader_context *ctx = si_shader_context(bld_base);
4156 LLVMBuilderRef builder = ctx->ac.builder;
4157 LLVMValueRef tmp;
4158
4159 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4160 tmp = ac_build_ballot(&ctx->ac, tmp);
4161 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4162
4163 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4164 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4165 }
4166
4167 static void read_lane_emit(
4168 const struct lp_build_tgsi_action *action,
4169 struct lp_build_tgsi_context *bld_base,
4170 struct lp_build_emit_data *emit_data)
4171 {
4172 struct si_shader_context *ctx = si_shader_context(bld_base);
4173
4174 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4175 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4176 0, emit_data->src_chan);
4177
4178 /* Always read the source invocation (= lane) from the X channel. */
4179 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4180 1, TGSI_CHAN_X);
4181 emit_data->arg_count = 2;
4182 }
4183
4184 /* We currently have no other way to prevent LLVM from lifting the icmp
4185 * calls to a dominating basic block.
4186 */
4187 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4188
4189 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4190 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4191
4192 emit_data->output[emit_data->chan] =
4193 ac_build_intrinsic(&ctx->ac, action->intr_name,
4194 ctx->i32, emit_data->args, emit_data->arg_count,
4195 AC_FUNC_ATTR_READNONE |
4196 AC_FUNC_ATTR_CONVERGENT);
4197 }
4198
4199 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4200 struct lp_build_emit_data *emit_data)
4201 {
4202 struct si_shader_context *ctx = si_shader_context(bld_base);
4203 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4204 LLVMValueRef imm;
4205 unsigned stream;
4206
4207 assert(src0.File == TGSI_FILE_IMMEDIATE);
4208
4209 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4210 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4211 return stream;
4212 }
4213
4214 /* Emit one vertex from the geometry shader */
4215 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4216 unsigned stream,
4217 LLVMValueRef *addrs)
4218 {
4219 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4220 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4221 struct si_shader *shader = ctx->shader;
4222 struct lp_build_if_state if_state;
4223 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4224 ctx->param_gs2vs_offset);
4225 LLVMValueRef gs_next_vertex;
4226 LLVMValueRef can_emit;
4227 unsigned chan, offset;
4228 int i;
4229
4230 /* Write vertex attribute values to GSVS ring */
4231 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4232 ctx->gs_next_vertex[stream],
4233 "");
4234
4235 /* If this thread has already emitted the declared maximum number of
4236 * vertices, skip the write: excessive vertex emissions are not
4237 * supposed to have any effect.
4238 *
4239 * If the shader has no writes to memory, kill it instead. This skips
4240 * further memory loads and may allow LLVM to skip to the end
4241 * altogether.
4242 */
4243 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4244 LLVMConstInt(ctx->i32,
4245 shader->selector->gs_max_out_vertices, 0), "");
4246
4247 bool use_kill = !info->writes_memory;
4248 if (use_kill) {
4249 ac_build_kill_if_false(&ctx->ac, can_emit);
4250 } else {
4251 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4252 }
4253
4254 offset = 0;
4255 for (i = 0; i < info->num_outputs; i++) {
4256 for (chan = 0; chan < 4; chan++) {
4257 if (!(info->output_usagemask[i] & (1 << chan)) ||
4258 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4259 continue;
4260
4261 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4262 LLVMValueRef voffset =
4263 LLVMConstInt(ctx->i32, offset *
4264 shader->selector->gs_max_out_vertices, 0);
4265 offset++;
4266
4267 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4268 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4269 LLVMConstInt(ctx->i32, 4, 0), "");
4270
4271 out_val = ac_to_integer(&ctx->ac, out_val);
4272
4273 ac_build_buffer_store_dword(&ctx->ac,
4274 ctx->gsvs_ring[stream],
4275 out_val, 1,
4276 voffset, soffset, 0,
4277 1, 1, true, true);
4278 }
4279 }
4280
4281 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4282 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4283
4284 /* Signal vertex emission if vertex data was written. */
4285 if (offset) {
4286 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4287 si_get_gs_wave_id(ctx));
4288 }
4289
4290 if (!use_kill)
4291 lp_build_endif(&if_state);
4292 }
4293
4294 /* Emit one vertex from the geometry shader */
4295 static void si_tgsi_emit_vertex(
4296 const struct lp_build_tgsi_action *action,
4297 struct lp_build_tgsi_context *bld_base,
4298 struct lp_build_emit_data *emit_data)
4299 {
4300 struct si_shader_context *ctx = si_shader_context(bld_base);
4301 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4302
4303 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4304 }
4305
4306 /* Cut one primitive from the geometry shader */
4307 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4308 unsigned stream)
4309 {
4310 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4311
4312 /* Signal primitive cut */
4313 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4314 si_get_gs_wave_id(ctx));
4315 }
4316
4317 /* Cut one primitive from the geometry shader */
4318 static void si_tgsi_emit_primitive(
4319 const struct lp_build_tgsi_action *action,
4320 struct lp_build_tgsi_context *bld_base,
4321 struct lp_build_emit_data *emit_data)
4322 {
4323 struct si_shader_context *ctx = si_shader_context(bld_base);
4324
4325 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4326 }
4327
4328 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4329 struct lp_build_tgsi_context *bld_base,
4330 struct lp_build_emit_data *emit_data)
4331 {
4332 struct si_shader_context *ctx = si_shader_context(bld_base);
4333
4334 /* SI only (thanks to a hw bug workaround):
4335 * The real barrier instruction isn’t needed, because an entire patch
4336 * always fits into a single wave.
4337 */
4338 if (ctx->screen->info.chip_class == SI &&
4339 ctx->type == PIPE_SHADER_TESS_CTRL) {
4340 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4341 return;
4342 }
4343
4344 ac_build_s_barrier(&ctx->ac);
4345 }
4346
4347 static void si_create_function(struct si_shader_context *ctx,
4348 const char *name,
4349 LLVMTypeRef *returns, unsigned num_returns,
4350 struct si_function_info *fninfo,
4351 unsigned max_workgroup_size)
4352 {
4353 int i;
4354
4355 si_llvm_create_func(ctx, name, returns, num_returns,
4356 fninfo->types, fninfo->num_params);
4357 ctx->return_value = LLVMGetUndef(ctx->return_type);
4358
4359 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4360 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4361
4362 /* The combination of:
4363 * - noalias
4364 * - dereferenceable
4365 * - invariant.load
4366 * allows the optimization passes to move loads and reduces
4367 * SGPR spilling significantly.
4368 */
4369 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4370 AC_FUNC_ATTR_INREG);
4371
4372 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4373 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4374 AC_FUNC_ATTR_NOALIAS);
4375 ac_add_attr_dereferenceable(P, UINT64_MAX);
4376 }
4377 }
4378
4379 for (i = 0; i < fninfo->num_params; ++i) {
4380 if (fninfo->assign[i])
4381 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4382 }
4383
4384 if (ctx->screen->info.address32_hi) {
4385 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4386 "amdgpu-32bit-address-high-bits",
4387 ctx->screen->info.address32_hi);
4388 }
4389
4390 if (max_workgroup_size) {
4391 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4392 "amdgpu-max-work-group-size",
4393 max_workgroup_size);
4394 }
4395 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4396 "no-signed-zeros-fp-math",
4397 "true");
4398
4399 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4400 /* These were copied from some LLVM test. */
4401 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4402 "less-precise-fpmad",
4403 "true");
4404 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4405 "no-infs-fp-math",
4406 "true");
4407 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4408 "no-nans-fp-math",
4409 "true");
4410 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4411 "unsafe-fp-math",
4412 "true");
4413 }
4414 }
4415
4416 static void declare_streamout_params(struct si_shader_context *ctx,
4417 struct pipe_stream_output_info *so,
4418 struct si_function_info *fninfo)
4419 {
4420 int i;
4421
4422 /* Streamout SGPRs. */
4423 if (so->num_outputs) {
4424 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4425 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4426 else
4427 ctx->param_streamout_config = fninfo->num_params - 1;
4428
4429 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4430 }
4431 /* A streamout buffer offset is loaded if the stride is non-zero. */
4432 for (i = 0; i < 4; i++) {
4433 if (!so->stride[i])
4434 continue;
4435
4436 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4437 }
4438 }
4439
4440 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4441 {
4442 switch (shader->selector->type) {
4443 case PIPE_SHADER_TESS_CTRL:
4444 /* Return this so that LLVM doesn't remove s_barrier
4445 * instructions on chips where we use s_barrier. */
4446 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4447
4448 case PIPE_SHADER_GEOMETRY:
4449 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4450
4451 case PIPE_SHADER_COMPUTE:
4452 break; /* see below */
4453
4454 default:
4455 return 0;
4456 }
4457
4458 const unsigned *properties = shader->selector->info.properties;
4459 unsigned max_work_group_size =
4460 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4461 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4462 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4463
4464 if (!max_work_group_size) {
4465 /* This is a variable group size compute shader,
4466 * compile it for the maximum possible group size.
4467 */
4468 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4469 }
4470 return max_work_group_size;
4471 }
4472
4473 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4474 struct si_function_info *fninfo,
4475 bool assign_params)
4476 {
4477 LLVMTypeRef const_shader_buf_type;
4478
4479 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4480 ctx->shader->selector->info.shader_buffers_declared == 0)
4481 const_shader_buf_type = ctx->f32;
4482 else
4483 const_shader_buf_type = ctx->v4i32;
4484
4485 unsigned const_and_shader_buffers =
4486 add_arg(fninfo, ARG_SGPR,
4487 ac_array_in_const32_addr_space(const_shader_buf_type));
4488
4489 if (assign_params)
4490 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4491 }
4492
4493 static void declare_samplers_and_images(struct si_shader_context *ctx,
4494 struct si_function_info *fninfo,
4495 bool assign_params)
4496 {
4497 unsigned samplers_and_images =
4498 add_arg(fninfo, ARG_SGPR,
4499 ac_array_in_const32_addr_space(ctx->v8i32));
4500
4501 if (assign_params)
4502 ctx->param_samplers_and_images = samplers_and_images;
4503 }
4504
4505 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4506 struct si_function_info *fninfo,
4507 bool assign_params)
4508 {
4509 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4510 declare_samplers_and_images(ctx, fninfo, assign_params);
4511 }
4512
4513 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4514 struct si_function_info *fninfo)
4515 {
4516 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4517 ac_array_in_const32_addr_space(ctx->v4i32));
4518 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4519 ac_array_in_const32_addr_space(ctx->v8i32));
4520 }
4521
4522 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4523 struct si_function_info *fninfo)
4524 {
4525 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4526 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4527 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4528 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4529 }
4530
4531 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4532 struct si_function_info *fninfo,
4533 unsigned *num_prolog_vgprs)
4534 {
4535 struct si_shader *shader = ctx->shader;
4536
4537 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4538 if (shader->key.as_ls) {
4539 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4540 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4541 } else {
4542 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4543 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4544 }
4545 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4546
4547 if (!shader->is_gs_copy_shader) {
4548 /* Vertex load indices. */
4549 ctx->param_vertex_index0 = fninfo->num_params;
4550 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4551 add_arg(fninfo, ARG_VGPR, ctx->i32);
4552 *num_prolog_vgprs += shader->selector->info.num_inputs;
4553 }
4554 }
4555
4556 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4557 struct si_function_info *fninfo)
4558 {
4559 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4560 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4561 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4562 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4563 }
4564
4565 enum {
4566 /* Convenient merged shader definitions. */
4567 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4568 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4569 };
4570
4571 static void create_function(struct si_shader_context *ctx)
4572 {
4573 struct si_shader *shader = ctx->shader;
4574 struct si_function_info fninfo;
4575 LLVMTypeRef returns[16+32*4];
4576 unsigned i, num_return_sgprs;
4577 unsigned num_returns = 0;
4578 unsigned num_prolog_vgprs = 0;
4579 unsigned type = ctx->type;
4580 unsigned vs_blit_property =
4581 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4582
4583 si_init_function_info(&fninfo);
4584
4585 /* Set MERGED shaders. */
4586 if (ctx->screen->info.chip_class >= GFX9) {
4587 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4588 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4589 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4590 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4591 }
4592
4593 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4594
4595 switch (type) {
4596 case PIPE_SHADER_VERTEX:
4597 declare_global_desc_pointers(ctx, &fninfo);
4598
4599 if (vs_blit_property) {
4600 ctx->param_vs_blit_inputs = fninfo.num_params;
4601 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4602 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4603 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4604
4605 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4606 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4607 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4608 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4609 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4610 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4611 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4612 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4613 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4614 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4615 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4616 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4617 }
4618
4619 /* VGPRs */
4620 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4621 break;
4622 }
4623
4624 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4625 declare_vs_specific_input_sgprs(ctx, &fninfo);
4626 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4627 ac_array_in_const32_addr_space(ctx->v4i32));
4628
4629 if (shader->key.as_es) {
4630 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4631 } else if (shader->key.as_ls) {
4632 /* no extra parameters */
4633 } else {
4634 if (shader->is_gs_copy_shader) {
4635 fninfo.num_params = ctx->param_vs_state_bits + 1;
4636 fninfo.num_sgpr_params = fninfo.num_params;
4637 }
4638
4639 /* The locations of the other parameters are assigned dynamically. */
4640 declare_streamout_params(ctx, &shader->selector->so,
4641 &fninfo);
4642 }
4643
4644 /* VGPRs */
4645 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4646 break;
4647
4648 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4649 declare_global_desc_pointers(ctx, &fninfo);
4650 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4651 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4652 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4653 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4654 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4655 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4656 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4657
4658 /* VGPRs */
4659 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4660 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4661
4662 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4663 * placed after the user SGPRs.
4664 */
4665 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4666 returns[num_returns++] = ctx->i32; /* SGPRs */
4667 for (i = 0; i < 11; i++)
4668 returns[num_returns++] = ctx->f32; /* VGPRs */
4669 break;
4670
4671 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4672 /* Merged stages have 8 system SGPRs at the beginning. */
4673 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4674 declare_per_stage_desc_pointers(ctx, &fninfo,
4675 ctx->type == PIPE_SHADER_TESS_CTRL);
4676 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4677 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4678 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4679 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4680 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4681 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4682
4683 declare_global_desc_pointers(ctx, &fninfo);
4684 declare_per_stage_desc_pointers(ctx, &fninfo,
4685 ctx->type == PIPE_SHADER_VERTEX);
4686 declare_vs_specific_input_sgprs(ctx, &fninfo);
4687
4688 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4689 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4690 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4691 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4692 ac_array_in_const32_addr_space(ctx->v4i32));
4693
4694 /* VGPRs (first TCS, then VS) */
4695 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4696 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4697
4698 if (ctx->type == PIPE_SHADER_VERTEX) {
4699 declare_vs_input_vgprs(ctx, &fninfo,
4700 &num_prolog_vgprs);
4701
4702 /* LS return values are inputs to the TCS main shader part. */
4703 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4704 returns[num_returns++] = ctx->i32; /* SGPRs */
4705 for (i = 0; i < 2; i++)
4706 returns[num_returns++] = ctx->f32; /* VGPRs */
4707 } else {
4708 /* TCS return values are inputs to the TCS epilog.
4709 *
4710 * param_tcs_offchip_offset, param_tcs_factor_offset,
4711 * param_tcs_offchip_layout, and param_rw_buffers
4712 * should be passed to the epilog.
4713 */
4714 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4715 returns[num_returns++] = ctx->i32; /* SGPRs */
4716 for (i = 0; i < 11; i++)
4717 returns[num_returns++] = ctx->f32; /* VGPRs */
4718 }
4719 break;
4720
4721 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4722 /* Merged stages have 8 system SGPRs at the beginning. */
4723 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4724 declare_per_stage_desc_pointers(ctx, &fninfo,
4725 ctx->type == PIPE_SHADER_GEOMETRY);
4726 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4727 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4731 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4732
4733 declare_global_desc_pointers(ctx, &fninfo);
4734 declare_per_stage_desc_pointers(ctx, &fninfo,
4735 (ctx->type == PIPE_SHADER_VERTEX ||
4736 ctx->type == PIPE_SHADER_TESS_EVAL));
4737 if (ctx->type == PIPE_SHADER_VERTEX) {
4738 declare_vs_specific_input_sgprs(ctx, &fninfo);
4739 } else {
4740 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4741 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4742 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 /* Declare as many input SGPRs as the VS has. */
4744 }
4745
4746 if (ctx->type == PIPE_SHADER_VERTEX) {
4747 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4748 ac_array_in_const32_addr_space(ctx->v4i32));
4749 }
4750
4751 /* VGPRs (first GS, then VS/TES) */
4752 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4753 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4754 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4755 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4756 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4757
4758 if (ctx->type == PIPE_SHADER_VERTEX) {
4759 declare_vs_input_vgprs(ctx, &fninfo,
4760 &num_prolog_vgprs);
4761 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4762 declare_tes_input_vgprs(ctx, &fninfo);
4763 }
4764
4765 if (ctx->type == PIPE_SHADER_VERTEX ||
4766 ctx->type == PIPE_SHADER_TESS_EVAL) {
4767 unsigned num_user_sgprs;
4768
4769 if (ctx->type == PIPE_SHADER_VERTEX)
4770 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4771 else
4772 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4773
4774 /* ES return values are inputs to GS. */
4775 for (i = 0; i < 8 + num_user_sgprs; i++)
4776 returns[num_returns++] = ctx->i32; /* SGPRs */
4777 for (i = 0; i < 5; i++)
4778 returns[num_returns++] = ctx->f32; /* VGPRs */
4779 }
4780 break;
4781
4782 case PIPE_SHADER_TESS_EVAL:
4783 declare_global_desc_pointers(ctx, &fninfo);
4784 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4785 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4786 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4787 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4788
4789 if (shader->key.as_es) {
4790 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4791 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4792 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4793 } else {
4794 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4795 declare_streamout_params(ctx, &shader->selector->so,
4796 &fninfo);
4797 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798 }
4799
4800 /* VGPRs */
4801 declare_tes_input_vgprs(ctx, &fninfo);
4802 break;
4803
4804 case PIPE_SHADER_GEOMETRY:
4805 declare_global_desc_pointers(ctx, &fninfo);
4806 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4807 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4808 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4809
4810 /* VGPRs */
4811 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4812 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4813 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4814 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4815 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4816 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4817 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4818 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4819 break;
4820
4821 case PIPE_SHADER_FRAGMENT:
4822 declare_global_desc_pointers(ctx, &fninfo);
4823 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4824 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4825 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4826 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4827
4828 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4829 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4830 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4831 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4832 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4833 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4834 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4835 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4836 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4837 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4838 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4839 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4840 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4841 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4842 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4843 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4844 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4845 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4846 shader->info.face_vgpr_index = 20;
4847 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4848 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4849 shader->info.ancillary_vgpr_index = 21;
4850 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4851 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4852 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4853
4854 /* Color inputs from the prolog. */
4855 if (shader->selector->info.colors_read) {
4856 unsigned num_color_elements =
4857 util_bitcount(shader->selector->info.colors_read);
4858
4859 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4860 for (i = 0; i < num_color_elements; i++)
4861 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4862
4863 num_prolog_vgprs += num_color_elements;
4864 }
4865
4866 /* Outputs for the epilog. */
4867 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4868 num_returns =
4869 num_return_sgprs +
4870 util_bitcount(shader->selector->info.colors_written) * 4 +
4871 shader->selector->info.writes_z +
4872 shader->selector->info.writes_stencil +
4873 shader->selector->info.writes_samplemask +
4874 1 /* SampleMaskIn */;
4875
4876 num_returns = MAX2(num_returns,
4877 num_return_sgprs +
4878 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4879
4880 for (i = 0; i < num_return_sgprs; i++)
4881 returns[i] = ctx->i32;
4882 for (; i < num_returns; i++)
4883 returns[i] = ctx->f32;
4884 break;
4885
4886 case PIPE_SHADER_COMPUTE:
4887 declare_global_desc_pointers(ctx, &fninfo);
4888 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4889 if (shader->selector->info.uses_grid_size)
4890 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4891 if (shader->selector->info.uses_block_size &&
4892 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4893 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4894
4895 unsigned cs_user_data_dwords =
4896 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4897 if (cs_user_data_dwords) {
4898 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4899 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4900 }
4901
4902 for (i = 0; i < 3; i++) {
4903 ctx->abi.workgroup_ids[i] = NULL;
4904 if (shader->selector->info.uses_block_id[i])
4905 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4906 }
4907
4908 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4909 break;
4910 default:
4911 assert(0 && "unimplemented shader");
4912 return;
4913 }
4914
4915 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4916 si_get_max_workgroup_size(shader));
4917
4918 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4919 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4920 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4921 "InitialPSInputAddr",
4922 S_0286D0_PERSP_SAMPLE_ENA(1) |
4923 S_0286D0_PERSP_CENTER_ENA(1) |
4924 S_0286D0_PERSP_CENTROID_ENA(1) |
4925 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4926 S_0286D0_LINEAR_CENTER_ENA(1) |
4927 S_0286D0_LINEAR_CENTROID_ENA(1) |
4928 S_0286D0_FRONT_FACE_ENA(1) |
4929 S_0286D0_ANCILLARY_ENA(1) |
4930 S_0286D0_POS_FIXED_PT_ENA(1));
4931 }
4932
4933 shader->info.num_input_sgprs = 0;
4934 shader->info.num_input_vgprs = 0;
4935
4936 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4937 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4938
4939 for (; i < fninfo.num_params; ++i)
4940 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4941
4942 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4943 shader->info.num_input_vgprs -= num_prolog_vgprs;
4944
4945 if (shader->key.as_ls ||
4946 ctx->type == PIPE_SHADER_TESS_CTRL ||
4947 /* GFX9 has the ESGS ring buffer in LDS. */
4948 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4949 ac_declare_lds_as_pointer(&ctx->ac);
4950 }
4951
4952 /**
4953 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4954 * for later use.
4955 */
4956 static void preload_ring_buffers(struct si_shader_context *ctx)
4957 {
4958 LLVMBuilderRef builder = ctx->ac.builder;
4959
4960 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4961 ctx->param_rw_buffers);
4962
4963 if (ctx->screen->info.chip_class <= VI &&
4964 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4965 unsigned ring =
4966 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4967 : SI_ES_RING_ESGS;
4968 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4969
4970 ctx->esgs_ring =
4971 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4972 }
4973
4974 if (ctx->shader->is_gs_copy_shader) {
4975 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4976
4977 ctx->gsvs_ring[0] =
4978 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4979 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4980 const struct si_shader_selector *sel = ctx->shader->selector;
4981 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4982 LLVMValueRef base_ring;
4983
4984 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4985
4986 /* The conceptual layout of the GSVS ring is
4987 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4988 * but the real memory layout is swizzled across
4989 * threads:
4990 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4991 * t16v0c0 ..
4992 * Override the buffer descriptor accordingly.
4993 */
4994 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4995 uint64_t stream_offset = 0;
4996
4997 for (unsigned stream = 0; stream < 4; ++stream) {
4998 unsigned num_components;
4999 unsigned stride;
5000 unsigned num_records;
5001 LLVMValueRef ring, tmp;
5002
5003 num_components = sel->info.num_stream_output_components[stream];
5004 if (!num_components)
5005 continue;
5006
5007 stride = 4 * num_components * sel->gs_max_out_vertices;
5008
5009 /* Limit on the stride field for <= CIK. */
5010 assert(stride < (1 << 14));
5011
5012 num_records = 64;
5013
5014 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5015 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5016 tmp = LLVMBuildAdd(builder, tmp,
5017 LLVMConstInt(ctx->i64,
5018 stream_offset, 0), "");
5019 stream_offset += stride * 64;
5020
5021 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5022 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5023 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5024 tmp = LLVMBuildOr(builder, tmp,
5025 LLVMConstInt(ctx->i32,
5026 S_008F04_STRIDE(stride) |
5027 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5028 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5029 ring = LLVMBuildInsertElement(builder, ring,
5030 LLVMConstInt(ctx->i32, num_records, 0),
5031 LLVMConstInt(ctx->i32, 2, 0), "");
5032 ring = LLVMBuildInsertElement(builder, ring,
5033 LLVMConstInt(ctx->i32,
5034 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5035 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5036 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5037 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5038 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5039 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5040 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5041 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5042 S_008F0C_ADD_TID_ENABLE(1),
5043 0),
5044 LLVMConstInt(ctx->i32, 3, 0), "");
5045
5046 ctx->gsvs_ring[stream] = ring;
5047 }
5048 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5049 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5050 }
5051 }
5052
5053 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5054 LLVMValueRef param_rw_buffers,
5055 unsigned param_pos_fixed_pt)
5056 {
5057 LLVMBuilderRef builder = ctx->ac.builder;
5058 LLVMValueRef slot, desc, offset, row, bit, address[2];
5059
5060 /* Use the fixed-point gl_FragCoord input.
5061 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5062 * per coordinate to get the repeating effect.
5063 */
5064 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5065 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5066
5067 /* Load the buffer descriptor. */
5068 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5069 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5070
5071 /* The stipple pattern is 32x32, each row has 32 bits. */
5072 offset = LLVMBuildMul(builder, address[1],
5073 LLVMConstInt(ctx->i32, 4, 0), "");
5074 row = buffer_load_const(ctx, desc, offset);
5075 row = ac_to_integer(&ctx->ac, row);
5076 bit = LLVMBuildLShr(builder, row, address[0], "");
5077 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5078 ac_build_kill_if_false(&ctx->ac, bit);
5079 }
5080
5081 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5082 struct si_shader_config *conf,
5083 unsigned symbol_offset)
5084 {
5085 unsigned i;
5086 const unsigned char *config =
5087 ac_shader_binary_config_start(binary, symbol_offset);
5088 bool really_needs_scratch = false;
5089
5090 /* LLVM adds SGPR spills to the scratch size.
5091 * Find out if we really need the scratch buffer.
5092 */
5093 for (i = 0; i < binary->reloc_count; i++) {
5094 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5095
5096 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5097 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5098 really_needs_scratch = true;
5099 break;
5100 }
5101 }
5102
5103 /* XXX: We may be able to emit some of these values directly rather than
5104 * extracting fields to be emitted later.
5105 */
5106
5107 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5108 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5109 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5110 switch (reg) {
5111 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5112 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5113 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5114 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5115 case R_00B848_COMPUTE_PGM_RSRC1:
5116 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5117 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5118 conf->float_mode = G_00B028_FLOAT_MODE(value);
5119 conf->rsrc1 = value;
5120 break;
5121 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5122 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5123 break;
5124 case R_00B84C_COMPUTE_PGM_RSRC2:
5125 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5126 conf->rsrc2 = value;
5127 break;
5128 case R_0286CC_SPI_PS_INPUT_ENA:
5129 conf->spi_ps_input_ena = value;
5130 break;
5131 case R_0286D0_SPI_PS_INPUT_ADDR:
5132 conf->spi_ps_input_addr = value;
5133 break;
5134 case R_0286E8_SPI_TMPRING_SIZE:
5135 case R_00B860_COMPUTE_TMPRING_SIZE:
5136 /* WAVESIZE is in units of 256 dwords. */
5137 if (really_needs_scratch)
5138 conf->scratch_bytes_per_wave =
5139 G_00B860_WAVESIZE(value) * 256 * 4;
5140 break;
5141 case 0x4: /* SPILLED_SGPRS */
5142 conf->spilled_sgprs = value;
5143 break;
5144 case 0x8: /* SPILLED_VGPRS */
5145 conf->spilled_vgprs = value;
5146 break;
5147 default:
5148 {
5149 static bool printed;
5150
5151 if (!printed) {
5152 fprintf(stderr, "Warning: LLVM emitted unknown "
5153 "config register: 0x%x\n", reg);
5154 printed = true;
5155 }
5156 }
5157 break;
5158 }
5159 }
5160
5161 if (!conf->spi_ps_input_addr)
5162 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5163 }
5164
5165 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5166 uint64_t scratch_va)
5167 {
5168 unsigned i;
5169 uint32_t scratch_rsrc_dword0 = scratch_va;
5170 uint32_t scratch_rsrc_dword1 =
5171 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5172
5173 /* Enable scratch coalescing. */
5174 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5175
5176 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5177 const struct ac_shader_reloc *reloc =
5178 &shader->binary.relocs[i];
5179 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5180 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5181 &scratch_rsrc_dword0, 4);
5182 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5183 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5184 &scratch_rsrc_dword1, 4);
5185 }
5186 }
5187 }
5188
5189 /* For the UMR disassembler. */
5190 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5191 #define DEBUGGER_NUM_MARKERS 5
5192
5193 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5194 {
5195 unsigned size = shader->binary.code_size;
5196
5197 if (shader->prolog)
5198 size += shader->prolog->binary.code_size;
5199 if (shader->previous_stage)
5200 size += shader->previous_stage->binary.code_size;
5201 if (shader->prolog2)
5202 size += shader->prolog2->binary.code_size;
5203 if (shader->epilog)
5204 size += shader->epilog->binary.code_size;
5205 return size + DEBUGGER_NUM_MARKERS * 4;
5206 }
5207
5208 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5209 {
5210 const struct ac_shader_binary *prolog =
5211 shader->prolog ? &shader->prolog->binary : NULL;
5212 const struct ac_shader_binary *previous_stage =
5213 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5214 const struct ac_shader_binary *prolog2 =
5215 shader->prolog2 ? &shader->prolog2->binary : NULL;
5216 const struct ac_shader_binary *epilog =
5217 shader->epilog ? &shader->epilog->binary : NULL;
5218 const struct ac_shader_binary *mainb = &shader->binary;
5219 unsigned bo_size = si_get_shader_binary_size(shader) +
5220 (!epilog ? mainb->rodata_size : 0);
5221 unsigned char *ptr;
5222
5223 assert(!prolog || !prolog->rodata_size);
5224 assert(!previous_stage || !previous_stage->rodata_size);
5225 assert(!prolog2 || !prolog2->rodata_size);
5226 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5227 !mainb->rodata_size);
5228 assert(!epilog || !epilog->rodata_size);
5229
5230 r600_resource_reference(&shader->bo, NULL);
5231 shader->bo = si_aligned_buffer_create(&sscreen->b,
5232 sscreen->cpdma_prefetch_writes_memory ?
5233 0 : SI_RESOURCE_FLAG_READ_ONLY,
5234 PIPE_USAGE_IMMUTABLE,
5235 align(bo_size, SI_CPDMA_ALIGNMENT),
5236 256);
5237 if (!shader->bo)
5238 return -ENOMEM;
5239
5240 /* Upload. */
5241 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5242 PIPE_TRANSFER_READ_WRITE |
5243 PIPE_TRANSFER_UNSYNCHRONIZED |
5244 RADEON_TRANSFER_TEMPORARY);
5245
5246 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5247 * endian-independent. */
5248 if (prolog) {
5249 memcpy(ptr, prolog->code, prolog->code_size);
5250 ptr += prolog->code_size;
5251 }
5252 if (previous_stage) {
5253 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5254 ptr += previous_stage->code_size;
5255 }
5256 if (prolog2) {
5257 memcpy(ptr, prolog2->code, prolog2->code_size);
5258 ptr += prolog2->code_size;
5259 }
5260
5261 memcpy(ptr, mainb->code, mainb->code_size);
5262 ptr += mainb->code_size;
5263
5264 if (epilog) {
5265 memcpy(ptr, epilog->code, epilog->code_size);
5266 ptr += epilog->code_size;
5267 } else if (mainb->rodata_size > 0) {
5268 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5269 ptr += mainb->rodata_size;
5270 }
5271
5272 /* Add end-of-code markers for the UMR disassembler. */
5273 uint32_t *ptr32 = (uint32_t*)ptr;
5274 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5275 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5276
5277 sscreen->ws->buffer_unmap(shader->bo->buf);
5278 return 0;
5279 }
5280
5281 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5282 struct pipe_debug_callback *debug,
5283 const char *name, FILE *file)
5284 {
5285 char *line, *p;
5286 unsigned i, count;
5287
5288 if (binary->disasm_string) {
5289 fprintf(file, "Shader %s disassembly:\n", name);
5290 fprintf(file, "%s", binary->disasm_string);
5291
5292 if (debug && debug->debug_message) {
5293 /* Very long debug messages are cut off, so send the
5294 * disassembly one line at a time. This causes more
5295 * overhead, but on the plus side it simplifies
5296 * parsing of resulting logs.
5297 */
5298 pipe_debug_message(debug, SHADER_INFO,
5299 "Shader Disassembly Begin");
5300
5301 line = binary->disasm_string;
5302 while (*line) {
5303 p = util_strchrnul(line, '\n');
5304 count = p - line;
5305
5306 if (count) {
5307 pipe_debug_message(debug, SHADER_INFO,
5308 "%.*s", count, line);
5309 }
5310
5311 if (!*p)
5312 break;
5313 line = p + 1;
5314 }
5315
5316 pipe_debug_message(debug, SHADER_INFO,
5317 "Shader Disassembly End");
5318 }
5319 } else {
5320 fprintf(file, "Shader %s binary:\n", name);
5321 for (i = 0; i < binary->code_size; i += 4) {
5322 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5323 binary->code[i + 3], binary->code[i + 2],
5324 binary->code[i + 1], binary->code[i]);
5325 }
5326 }
5327 }
5328
5329 static void si_calculate_max_simd_waves(struct si_shader *shader)
5330 {
5331 struct si_screen *sscreen = shader->selector->screen;
5332 struct si_shader_config *conf = &shader->config;
5333 unsigned num_inputs = shader->selector->info.num_inputs;
5334 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5335 unsigned lds_per_wave = 0;
5336 unsigned max_simd_waves;
5337
5338 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5339
5340 /* Compute LDS usage for PS. */
5341 switch (shader->selector->type) {
5342 case PIPE_SHADER_FRAGMENT:
5343 /* The minimum usage per wave is (num_inputs * 48). The maximum
5344 * usage is (num_inputs * 48 * 16).
5345 * We can get anything in between and it varies between waves.
5346 *
5347 * The 48 bytes per input for a single primitive is equal to
5348 * 4 bytes/component * 4 components/input * 3 points.
5349 *
5350 * Other stages don't know the size at compile time or don't
5351 * allocate LDS per wave, but instead they do it per thread group.
5352 */
5353 lds_per_wave = conf->lds_size * lds_increment +
5354 align(num_inputs * 48, lds_increment);
5355 break;
5356 case PIPE_SHADER_COMPUTE:
5357 if (shader->selector) {
5358 unsigned max_workgroup_size =
5359 si_get_max_workgroup_size(shader);
5360 lds_per_wave = (conf->lds_size * lds_increment) /
5361 DIV_ROUND_UP(max_workgroup_size, 64);
5362 }
5363 break;
5364 }
5365
5366 /* Compute the per-SIMD wave counts. */
5367 if (conf->num_sgprs) {
5368 if (sscreen->info.chip_class >= VI)
5369 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5370 else
5371 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5372 }
5373
5374 if (conf->num_vgprs)
5375 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5376
5377 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5378 * 16KB makes some SIMDs unoccupied). */
5379 if (lds_per_wave)
5380 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5381
5382 conf->max_simd_waves = max_simd_waves;
5383 }
5384
5385 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5386 struct pipe_debug_callback *debug)
5387 {
5388 const struct si_shader_config *conf = &shader->config;
5389
5390 pipe_debug_message(debug, SHADER_INFO,
5391 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5392 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5393 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5394 conf->num_sgprs, conf->num_vgprs,
5395 si_get_shader_binary_size(shader),
5396 conf->lds_size, conf->scratch_bytes_per_wave,
5397 conf->max_simd_waves, conf->spilled_sgprs,
5398 conf->spilled_vgprs, conf->private_mem_vgprs);
5399 }
5400
5401 static void si_shader_dump_stats(struct si_screen *sscreen,
5402 const struct si_shader *shader,
5403 unsigned processor,
5404 FILE *file,
5405 bool check_debug_option)
5406 {
5407 const struct si_shader_config *conf = &shader->config;
5408
5409 if (!check_debug_option ||
5410 si_can_dump_shader(sscreen, processor)) {
5411 if (processor == PIPE_SHADER_FRAGMENT) {
5412 fprintf(file, "*** SHADER CONFIG ***\n"
5413 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5414 "SPI_PS_INPUT_ENA = 0x%04x\n",
5415 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5416 }
5417
5418 fprintf(file, "*** SHADER STATS ***\n"
5419 "SGPRS: %d\n"
5420 "VGPRS: %d\n"
5421 "Spilled SGPRs: %d\n"
5422 "Spilled VGPRs: %d\n"
5423 "Private memory VGPRs: %d\n"
5424 "Code Size: %d bytes\n"
5425 "LDS: %d blocks\n"
5426 "Scratch: %d bytes per wave\n"
5427 "Max Waves: %d\n"
5428 "********************\n\n\n",
5429 conf->num_sgprs, conf->num_vgprs,
5430 conf->spilled_sgprs, conf->spilled_vgprs,
5431 conf->private_mem_vgprs,
5432 si_get_shader_binary_size(shader),
5433 conf->lds_size, conf->scratch_bytes_per_wave,
5434 conf->max_simd_waves);
5435 }
5436 }
5437
5438 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5439 {
5440 switch (processor) {
5441 case PIPE_SHADER_VERTEX:
5442 if (shader->key.as_es)
5443 return "Vertex Shader as ES";
5444 else if (shader->key.as_ls)
5445 return "Vertex Shader as LS";
5446 else
5447 return "Vertex Shader as VS";
5448 case PIPE_SHADER_TESS_CTRL:
5449 return "Tessellation Control Shader";
5450 case PIPE_SHADER_TESS_EVAL:
5451 if (shader->key.as_es)
5452 return "Tessellation Evaluation Shader as ES";
5453 else
5454 return "Tessellation Evaluation Shader as VS";
5455 case PIPE_SHADER_GEOMETRY:
5456 if (shader->is_gs_copy_shader)
5457 return "GS Copy Shader as VS";
5458 else
5459 return "Geometry Shader";
5460 case PIPE_SHADER_FRAGMENT:
5461 return "Pixel Shader";
5462 case PIPE_SHADER_COMPUTE:
5463 return "Compute Shader";
5464 default:
5465 return "Unknown Shader";
5466 }
5467 }
5468
5469 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5470 struct pipe_debug_callback *debug, unsigned processor,
5471 FILE *file, bool check_debug_option)
5472 {
5473 if (!check_debug_option ||
5474 si_can_dump_shader(sscreen, processor))
5475 si_dump_shader_key(processor, shader, file);
5476
5477 if (!check_debug_option && shader->binary.llvm_ir_string) {
5478 if (shader->previous_stage &&
5479 shader->previous_stage->binary.llvm_ir_string) {
5480 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5481 si_get_shader_name(shader, processor));
5482 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5483 }
5484
5485 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5486 si_get_shader_name(shader, processor));
5487 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5488 }
5489
5490 if (!check_debug_option ||
5491 (si_can_dump_shader(sscreen, processor) &&
5492 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5493 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5494
5495 if (shader->prolog)
5496 si_shader_dump_disassembly(&shader->prolog->binary,
5497 debug, "prolog", file);
5498 if (shader->previous_stage)
5499 si_shader_dump_disassembly(&shader->previous_stage->binary,
5500 debug, "previous stage", file);
5501 if (shader->prolog2)
5502 si_shader_dump_disassembly(&shader->prolog2->binary,
5503 debug, "prolog2", file);
5504
5505 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5506
5507 if (shader->epilog)
5508 si_shader_dump_disassembly(&shader->epilog->binary,
5509 debug, "epilog", file);
5510 fprintf(file, "\n");
5511 }
5512
5513 si_shader_dump_stats(sscreen, shader, processor, file,
5514 check_debug_option);
5515 }
5516
5517 static int si_compile_llvm(struct si_screen *sscreen,
5518 struct ac_shader_binary *binary,
5519 struct si_shader_config *conf,
5520 struct ac_llvm_compiler *compiler,
5521 LLVMModuleRef mod,
5522 struct pipe_debug_callback *debug,
5523 unsigned processor,
5524 const char *name,
5525 bool less_optimized)
5526 {
5527 int r = 0;
5528 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5529
5530 if (si_can_dump_shader(sscreen, processor)) {
5531 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5532
5533 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5534 fprintf(stderr, "%s LLVM IR:\n\n", name);
5535 ac_dump_module(mod);
5536 fprintf(stderr, "\n");
5537 }
5538 }
5539
5540 if (sscreen->record_llvm_ir) {
5541 char *ir = LLVMPrintModuleToString(mod);
5542 binary->llvm_ir_string = strdup(ir);
5543 LLVMDisposeMessage(ir);
5544 }
5545
5546 if (!si_replace_shader(count, binary)) {
5547 r = si_llvm_compile(mod, binary, compiler, debug,
5548 less_optimized);
5549 if (r)
5550 return r;
5551 }
5552
5553 si_shader_binary_read_config(binary, conf, 0);
5554
5555 /* Enable 64-bit and 16-bit denormals, because there is no performance
5556 * cost.
5557 *
5558 * If denormals are enabled, all floating-point output modifiers are
5559 * ignored.
5560 *
5561 * Don't enable denormals for 32-bit floats, because:
5562 * - Floating-point output modifiers would be ignored by the hw.
5563 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5564 * have to stop using those.
5565 * - SI & CI would be very slow.
5566 */
5567 conf->float_mode |= V_00B028_FP_64_DENORMS;
5568
5569 FREE(binary->config);
5570 FREE(binary->global_symbol_offsets);
5571 binary->config = NULL;
5572 binary->global_symbol_offsets = NULL;
5573
5574 /* Some shaders can't have rodata because their binaries can be
5575 * concatenated.
5576 */
5577 if (binary->rodata_size &&
5578 (processor == PIPE_SHADER_VERTEX ||
5579 processor == PIPE_SHADER_TESS_CTRL ||
5580 processor == PIPE_SHADER_TESS_EVAL ||
5581 processor == PIPE_SHADER_FRAGMENT)) {
5582 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5583 return -EINVAL;
5584 }
5585
5586 return r;
5587 }
5588
5589 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5590 {
5591 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5592 LLVMBuildRetVoid(ctx->ac.builder);
5593 else
5594 LLVMBuildRet(ctx->ac.builder, ret);
5595 }
5596
5597 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5598 struct si_shader *
5599 si_generate_gs_copy_shader(struct si_screen *sscreen,
5600 struct ac_llvm_compiler *compiler,
5601 struct si_shader_selector *gs_selector,
5602 struct pipe_debug_callback *debug)
5603 {
5604 struct si_shader_context ctx;
5605 struct si_shader *shader;
5606 LLVMBuilderRef builder;
5607 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5608 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5609 int i, r;
5610
5611
5612 shader = CALLOC_STRUCT(si_shader);
5613 if (!shader)
5614 return NULL;
5615
5616 /* We can leave the fence as permanently signaled because the GS copy
5617 * shader only becomes visible globally after it has been compiled. */
5618 util_queue_fence_init(&shader->ready);
5619
5620 shader->selector = gs_selector;
5621 shader->is_gs_copy_shader = true;
5622
5623 si_init_shader_ctx(&ctx, sscreen, compiler);
5624 ctx.shader = shader;
5625 ctx.type = PIPE_SHADER_VERTEX;
5626
5627 builder = ctx.ac.builder;
5628
5629 create_function(&ctx);
5630 preload_ring_buffers(&ctx);
5631
5632 LLVMValueRef voffset =
5633 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5634 LLVMConstInt(ctx.i32, 4, 0), "");
5635
5636 /* Fetch the vertex stream ID.*/
5637 LLVMValueRef stream_id;
5638
5639 if (gs_selector->so.num_outputs)
5640 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5641 else
5642 stream_id = ctx.i32_0;
5643
5644 /* Fill in output information. */
5645 for (i = 0; i < gsinfo->num_outputs; ++i) {
5646 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5647 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5648
5649 for (int chan = 0; chan < 4; chan++) {
5650 outputs[i].vertex_stream[chan] =
5651 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5652 }
5653 }
5654
5655 LLVMBasicBlockRef end_bb;
5656 LLVMValueRef switch_inst;
5657
5658 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5659 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5660
5661 for (int stream = 0; stream < 4; stream++) {
5662 LLVMBasicBlockRef bb;
5663 unsigned offset;
5664
5665 if (!gsinfo->num_stream_output_components[stream])
5666 continue;
5667
5668 if (stream > 0 && !gs_selector->so.num_outputs)
5669 continue;
5670
5671 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5672 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5673 LLVMPositionBuilderAtEnd(builder, bb);
5674
5675 /* Fetch vertex data from GSVS ring */
5676 offset = 0;
5677 for (i = 0; i < gsinfo->num_outputs; ++i) {
5678 for (unsigned chan = 0; chan < 4; chan++) {
5679 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5680 outputs[i].vertex_stream[chan] != stream) {
5681 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5682 continue;
5683 }
5684
5685 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5686 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5687 offset++;
5688
5689 outputs[i].values[chan] =
5690 ac_build_buffer_load(&ctx.ac,
5691 ctx.gsvs_ring[0], 1,
5692 ctx.i32_0, voffset,
5693 soffset, 0, 1, 1,
5694 true, false);
5695 }
5696 }
5697
5698 /* Streamout and exports. */
5699 if (gs_selector->so.num_outputs) {
5700 si_llvm_emit_streamout(&ctx, outputs,
5701 gsinfo->num_outputs,
5702 stream);
5703 }
5704
5705 if (stream == 0) {
5706 /* Vertex color clamping.
5707 *
5708 * This uses a state constant loaded in a user data SGPR and
5709 * an IF statement is added that clamps all colors if the constant
5710 * is true.
5711 */
5712 struct lp_build_if_state if_ctx;
5713 LLVMValueRef v[2], cond = NULL;
5714 LLVMBasicBlockRef blocks[2];
5715
5716 for (unsigned i = 0; i < gsinfo->num_outputs; i++) {
5717 if (gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
5718 gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
5719 continue;
5720
5721 /* We've found a color. */
5722 if (!cond) {
5723 /* The state is in the first bit of the user SGPR. */
5724 cond = LLVMGetParam(ctx.main_fn,
5725 ctx.param_vs_state_bits);
5726 cond = LLVMBuildTrunc(ctx.ac.builder, cond,
5727 ctx.i1, "");
5728 lp_build_if(&if_ctx, &ctx.gallivm, cond);
5729 /* Remember blocks for Phi. */
5730 blocks[0] = if_ctx.true_block;
5731 blocks[1] = if_ctx.entry_block;
5732 }
5733
5734 for (unsigned j = 0; j < 4; j++) {
5735 /* Insert clamp into the true block. */
5736 v[0] = ac_build_clamp(&ctx.ac, outputs[i].values[j]);
5737 v[1] = outputs[i].values[j];
5738
5739 /* Insert Phi into the endif block. */
5740 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.merge_block);
5741 outputs[i].values[j] = ac_build_phi(&ctx.ac, ctx.f32, 2, v, blocks);
5742 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.true_block);
5743 }
5744 }
5745 if (cond)
5746 lp_build_endif(&if_ctx);
5747
5748 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5749 }
5750
5751 LLVMBuildBr(builder, end_bb);
5752 }
5753
5754 LLVMPositionBuilderAtEnd(builder, end_bb);
5755
5756 LLVMBuildRetVoid(ctx.ac.builder);
5757
5758 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5759 si_llvm_optimize_module(&ctx);
5760
5761 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5762 &ctx.shader->config, ctx.compiler,
5763 ctx.ac.module,
5764 debug, PIPE_SHADER_GEOMETRY,
5765 "GS Copy Shader", false);
5766 if (!r) {
5767 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5768 fprintf(stderr, "GS Copy Shader:\n");
5769 si_shader_dump(sscreen, ctx.shader, debug,
5770 PIPE_SHADER_GEOMETRY, stderr, true);
5771 r = si_shader_binary_upload(sscreen, ctx.shader);
5772 }
5773
5774 si_llvm_dispose(&ctx);
5775
5776 if (r != 0) {
5777 FREE(shader);
5778 shader = NULL;
5779 }
5780 return shader;
5781 }
5782
5783 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5784 const struct si_vs_prolog_bits *prolog,
5785 const char *prefix, FILE *f)
5786 {
5787 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5788 prefix, prolog->instance_divisor_is_one);
5789 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5790 prefix, prolog->instance_divisor_is_fetched);
5791 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5792 prefix, prolog->ls_vgpr_fix);
5793
5794 fprintf(f, " mono.vs.fix_fetch = {");
5795 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5796 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5797 fprintf(f, "}\n");
5798 }
5799
5800 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5801 FILE *f)
5802 {
5803 const struct si_shader_key *key = &shader->key;
5804
5805 fprintf(f, "SHADER KEY\n");
5806
5807 switch (processor) {
5808 case PIPE_SHADER_VERTEX:
5809 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5810 "part.vs.prolog", f);
5811 fprintf(f, " as_es = %u\n", key->as_es);
5812 fprintf(f, " as_ls = %u\n", key->as_ls);
5813 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5814 key->mono.u.vs_export_prim_id);
5815 break;
5816
5817 case PIPE_SHADER_TESS_CTRL:
5818 if (shader->selector->screen->info.chip_class >= GFX9) {
5819 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5820 "part.tcs.ls_prolog", f);
5821 }
5822 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5823 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5824 break;
5825
5826 case PIPE_SHADER_TESS_EVAL:
5827 fprintf(f, " as_es = %u\n", key->as_es);
5828 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5829 key->mono.u.vs_export_prim_id);
5830 break;
5831
5832 case PIPE_SHADER_GEOMETRY:
5833 if (shader->is_gs_copy_shader)
5834 break;
5835
5836 if (shader->selector->screen->info.chip_class >= GFX9 &&
5837 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5838 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5839 "part.gs.vs_prolog", f);
5840 }
5841 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5842 break;
5843
5844 case PIPE_SHADER_COMPUTE:
5845 break;
5846
5847 case PIPE_SHADER_FRAGMENT:
5848 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5849 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5850 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5851 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5852 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5853 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5854 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5855 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5856 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5857 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5858 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5859 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5860 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5861 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5862 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5863 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5864 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5865 break;
5866
5867 default:
5868 assert(0);
5869 }
5870
5871 if ((processor == PIPE_SHADER_GEOMETRY ||
5872 processor == PIPE_SHADER_TESS_EVAL ||
5873 processor == PIPE_SHADER_VERTEX) &&
5874 !key->as_es && !key->as_ls) {
5875 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5876 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5877 }
5878 }
5879
5880 static void si_init_shader_ctx(struct si_shader_context *ctx,
5881 struct si_screen *sscreen,
5882 struct ac_llvm_compiler *compiler)
5883 {
5884 struct lp_build_tgsi_context *bld_base;
5885
5886 si_llvm_context_init(ctx, sscreen, compiler);
5887
5888 bld_base = &ctx->bld_base;
5889 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5890
5891 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5892 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5893 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5894
5895 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5896
5897 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5898
5899 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5900 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5901 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5902 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5903
5904 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5905 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5906 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5907 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5908 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5909 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5910 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5911 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5912
5913 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5914 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5915 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5916 }
5917
5918 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5919 {
5920 struct si_shader *shader = ctx->shader;
5921 struct tgsi_shader_info *info = &shader->selector->info;
5922
5923 if ((ctx->type != PIPE_SHADER_VERTEX &&
5924 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5925 shader->key.as_ls ||
5926 shader->key.as_es)
5927 return;
5928
5929 ac_optimize_vs_outputs(&ctx->ac,
5930 ctx->main_fn,
5931 shader->info.vs_output_param_offset,
5932 info->num_outputs,
5933 &shader->info.nr_param_exports);
5934 }
5935
5936 static void si_init_exec_from_input(struct si_shader_context *ctx,
5937 unsigned param, unsigned bitoffset)
5938 {
5939 LLVMValueRef args[] = {
5940 LLVMGetParam(ctx->main_fn, param),
5941 LLVMConstInt(ctx->i32, bitoffset, 0),
5942 };
5943 ac_build_intrinsic(&ctx->ac,
5944 "llvm.amdgcn.init.exec.from.input",
5945 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5946 }
5947
5948 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5949 const struct si_vs_prolog_bits *key)
5950 {
5951 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5952 * VS prolog. */
5953 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5954 }
5955
5956 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5957 {
5958 struct si_shader *shader = ctx->shader;
5959 struct si_shader_selector *sel = shader->selector;
5960 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5961
5962 // TODO clean all this up!
5963 switch (ctx->type) {
5964 case PIPE_SHADER_VERTEX:
5965 ctx->load_input = declare_input_vs;
5966 if (shader->key.as_ls)
5967 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5968 else if (shader->key.as_es)
5969 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5970 else
5971 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5972 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5973 ctx->abi.load_base_vertex = get_base_vertex;
5974 break;
5975 case PIPE_SHADER_TESS_CTRL:
5976 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5977 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5978 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5979 bld_base->emit_store = store_output_tcs;
5980 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5981 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5982 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5983 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5984 break;
5985 case PIPE_SHADER_TESS_EVAL:
5986 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5987 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5988 ctx->abi.load_tess_coord = si_load_tess_coord;
5989 ctx->abi.load_tess_level = si_load_tess_level;
5990 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5991 if (shader->key.as_es)
5992 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5993 else
5994 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5995 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5996 break;
5997 case PIPE_SHADER_GEOMETRY:
5998 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5999 ctx->abi.load_inputs = si_nir_load_input_gs;
6000 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6001 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6002 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6003 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6004 break;
6005 case PIPE_SHADER_FRAGMENT:
6006 ctx->load_input = declare_input_fs;
6007 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6008 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6009 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6010 ctx->abi.load_sample_position = load_sample_position;
6011 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6012 ctx->abi.emit_kill = si_llvm_emit_kill;
6013 break;
6014 case PIPE_SHADER_COMPUTE:
6015 ctx->abi.load_local_group_size = get_block_size;
6016 break;
6017 default:
6018 assert(!"Unsupported shader type");
6019 return false;
6020 }
6021
6022 ctx->abi.load_ubo = load_ubo;
6023 ctx->abi.load_ssbo = load_ssbo;
6024
6025 create_function(ctx);
6026 preload_ring_buffers(ctx);
6027
6028 /* For GFX9 merged shaders:
6029 * - Set EXEC for the first shader. If the prolog is present, set
6030 * EXEC there instead.
6031 * - Add a barrier before the second shader.
6032 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6033 * an if-statement. This is required for correctness in geometry
6034 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6035 * GS_CUT messages.
6036 *
6037 * For monolithic merged shaders, the first shader is wrapped in an
6038 * if-block together with its prolog in si_build_wrapper_function.
6039 */
6040 if (ctx->screen->info.chip_class >= GFX9) {
6041 if (!shader->is_monolithic &&
6042 sel->info.num_instructions > 1 && /* not empty shader */
6043 (shader->key.as_es || shader->key.as_ls) &&
6044 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6045 (ctx->type == PIPE_SHADER_VERTEX &&
6046 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6047 si_init_exec_from_input(ctx,
6048 ctx->param_merged_wave_info, 0);
6049 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6050 ctx->type == PIPE_SHADER_GEOMETRY) {
6051 if (!shader->is_monolithic)
6052 ac_init_exec_full_mask(&ctx->ac);
6053
6054 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6055 LLVMValueRef ena =
6056 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6057 ac_get_thread_id(&ctx->ac), num_threads, "");
6058 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6059
6060 /* The barrier must execute for all shaders in a
6061 * threadgroup.
6062 *
6063 * Execute the barrier inside the conditional block,
6064 * so that empty waves can jump directly to s_endpgm,
6065 * which will also signal the barrier.
6066 *
6067 * If the shader is TCS and the TCS epilog is present
6068 * and contains a barrier, it will wait there and then
6069 * reach s_endpgm.
6070 */
6071 si_llvm_emit_barrier(NULL, bld_base, NULL);
6072 }
6073 }
6074
6075 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6076 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6077 for (unsigned i = 0; i < 6; i++) {
6078 ctx->invoc0_tess_factors[i] =
6079 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6080 }
6081 }
6082
6083 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6084 int i;
6085 for (i = 0; i < 4; i++) {
6086 ctx->gs_next_vertex[i] =
6087 ac_build_alloca(&ctx->ac, ctx->i32, "");
6088 }
6089 }
6090
6091 if (sel->force_correct_derivs_after_kill) {
6092 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6093 /* true = don't kill. */
6094 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6095 ctx->postponed_kill);
6096 }
6097
6098 if (sel->tokens) {
6099 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6100 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6101 return false;
6102 }
6103 } else {
6104 if (!si_nir_build_llvm(ctx, sel->nir)) {
6105 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6106 return false;
6107 }
6108 }
6109
6110 si_llvm_build_ret(ctx, ctx->return_value);
6111 return true;
6112 }
6113
6114 /**
6115 * Compute the VS prolog key, which contains all the information needed to
6116 * build the VS prolog function, and set shader->info bits where needed.
6117 *
6118 * \param info Shader info of the vertex shader.
6119 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6120 * \param prolog_key Key of the VS prolog
6121 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6122 * \param key Output shader part key.
6123 */
6124 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6125 unsigned num_input_sgprs,
6126 const struct si_vs_prolog_bits *prolog_key,
6127 struct si_shader *shader_out,
6128 union si_shader_part_key *key)
6129 {
6130 memset(key, 0, sizeof(*key));
6131 key->vs_prolog.states = *prolog_key;
6132 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6133 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6134 key->vs_prolog.as_ls = shader_out->key.as_ls;
6135 key->vs_prolog.as_es = shader_out->key.as_es;
6136
6137 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6138 key->vs_prolog.as_ls = 1;
6139 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6140 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6141 key->vs_prolog.as_es = 1;
6142 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6143 }
6144
6145 /* Enable loading the InstanceID VGPR. */
6146 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6147
6148 if ((key->vs_prolog.states.instance_divisor_is_one |
6149 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6150 shader_out->info.uses_instanceid = true;
6151 }
6152
6153 /**
6154 * Compute the PS prolog key, which contains all the information needed to
6155 * build the PS prolog function, and set related bits in shader->config.
6156 */
6157 static void si_get_ps_prolog_key(struct si_shader *shader,
6158 union si_shader_part_key *key,
6159 bool separate_prolog)
6160 {
6161 struct tgsi_shader_info *info = &shader->selector->info;
6162
6163 memset(key, 0, sizeof(*key));
6164 key->ps_prolog.states = shader->key.part.ps.prolog;
6165 key->ps_prolog.colors_read = info->colors_read;
6166 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6167 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6168 key->ps_prolog.wqm = info->uses_derivatives &&
6169 (key->ps_prolog.colors_read ||
6170 key->ps_prolog.states.force_persp_sample_interp ||
6171 key->ps_prolog.states.force_linear_sample_interp ||
6172 key->ps_prolog.states.force_persp_center_interp ||
6173 key->ps_prolog.states.force_linear_center_interp ||
6174 key->ps_prolog.states.bc_optimize_for_persp ||
6175 key->ps_prolog.states.bc_optimize_for_linear);
6176 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6177
6178 if (info->colors_read) {
6179 unsigned *color = shader->selector->color_attr_index;
6180
6181 if (shader->key.part.ps.prolog.color_two_side) {
6182 /* BCOLORs are stored after the last input. */
6183 key->ps_prolog.num_interp_inputs = info->num_inputs;
6184 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6185 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6186 }
6187
6188 for (unsigned i = 0; i < 2; i++) {
6189 unsigned interp = info->input_interpolate[color[i]];
6190 unsigned location = info->input_interpolate_loc[color[i]];
6191
6192 if (!(info->colors_read & (0xf << i*4)))
6193 continue;
6194
6195 key->ps_prolog.color_attr_index[i] = color[i];
6196
6197 if (shader->key.part.ps.prolog.flatshade_colors &&
6198 interp == TGSI_INTERPOLATE_COLOR)
6199 interp = TGSI_INTERPOLATE_CONSTANT;
6200
6201 switch (interp) {
6202 case TGSI_INTERPOLATE_CONSTANT:
6203 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6204 break;
6205 case TGSI_INTERPOLATE_PERSPECTIVE:
6206 case TGSI_INTERPOLATE_COLOR:
6207 /* Force the interpolation location for colors here. */
6208 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6209 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6210 if (shader->key.part.ps.prolog.force_persp_center_interp)
6211 location = TGSI_INTERPOLATE_LOC_CENTER;
6212
6213 switch (location) {
6214 case TGSI_INTERPOLATE_LOC_SAMPLE:
6215 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6216 shader->config.spi_ps_input_ena |=
6217 S_0286CC_PERSP_SAMPLE_ENA(1);
6218 break;
6219 case TGSI_INTERPOLATE_LOC_CENTER:
6220 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6221 shader->config.spi_ps_input_ena |=
6222 S_0286CC_PERSP_CENTER_ENA(1);
6223 break;
6224 case TGSI_INTERPOLATE_LOC_CENTROID:
6225 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6226 shader->config.spi_ps_input_ena |=
6227 S_0286CC_PERSP_CENTROID_ENA(1);
6228 break;
6229 default:
6230 assert(0);
6231 }
6232 break;
6233 case TGSI_INTERPOLATE_LINEAR:
6234 /* Force the interpolation location for colors here. */
6235 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6236 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6237 if (shader->key.part.ps.prolog.force_linear_center_interp)
6238 location = TGSI_INTERPOLATE_LOC_CENTER;
6239
6240 /* The VGPR assignment for non-monolithic shaders
6241 * works because InitialPSInputAddr is set on the
6242 * main shader and PERSP_PULL_MODEL is never used.
6243 */
6244 switch (location) {
6245 case TGSI_INTERPOLATE_LOC_SAMPLE:
6246 key->ps_prolog.color_interp_vgpr_index[i] =
6247 separate_prolog ? 6 : 9;
6248 shader->config.spi_ps_input_ena |=
6249 S_0286CC_LINEAR_SAMPLE_ENA(1);
6250 break;
6251 case TGSI_INTERPOLATE_LOC_CENTER:
6252 key->ps_prolog.color_interp_vgpr_index[i] =
6253 separate_prolog ? 8 : 11;
6254 shader->config.spi_ps_input_ena |=
6255 S_0286CC_LINEAR_CENTER_ENA(1);
6256 break;
6257 case TGSI_INTERPOLATE_LOC_CENTROID:
6258 key->ps_prolog.color_interp_vgpr_index[i] =
6259 separate_prolog ? 10 : 13;
6260 shader->config.spi_ps_input_ena |=
6261 S_0286CC_LINEAR_CENTROID_ENA(1);
6262 break;
6263 default:
6264 assert(0);
6265 }
6266 break;
6267 default:
6268 assert(0);
6269 }
6270 }
6271 }
6272 }
6273
6274 /**
6275 * Check whether a PS prolog is required based on the key.
6276 */
6277 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6278 {
6279 return key->ps_prolog.colors_read ||
6280 key->ps_prolog.states.force_persp_sample_interp ||
6281 key->ps_prolog.states.force_linear_sample_interp ||
6282 key->ps_prolog.states.force_persp_center_interp ||
6283 key->ps_prolog.states.force_linear_center_interp ||
6284 key->ps_prolog.states.bc_optimize_for_persp ||
6285 key->ps_prolog.states.bc_optimize_for_linear ||
6286 key->ps_prolog.states.poly_stipple ||
6287 key->ps_prolog.states.samplemask_log_ps_iter;
6288 }
6289
6290 /**
6291 * Compute the PS epilog key, which contains all the information needed to
6292 * build the PS epilog function.
6293 */
6294 static void si_get_ps_epilog_key(struct si_shader *shader,
6295 union si_shader_part_key *key)
6296 {
6297 struct tgsi_shader_info *info = &shader->selector->info;
6298 memset(key, 0, sizeof(*key));
6299 key->ps_epilog.colors_written = info->colors_written;
6300 key->ps_epilog.writes_z = info->writes_z;
6301 key->ps_epilog.writes_stencil = info->writes_stencil;
6302 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6303 key->ps_epilog.states = shader->key.part.ps.epilog;
6304 }
6305
6306 /**
6307 * Build the GS prolog function. Rotate the input vertices for triangle strips
6308 * with adjacency.
6309 */
6310 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6311 union si_shader_part_key *key)
6312 {
6313 unsigned num_sgprs, num_vgprs;
6314 struct si_function_info fninfo;
6315 LLVMBuilderRef builder = ctx->ac.builder;
6316 LLVMTypeRef returns[48];
6317 LLVMValueRef func, ret;
6318
6319 si_init_function_info(&fninfo);
6320
6321 if (ctx->screen->info.chip_class >= GFX9) {
6322 if (key->gs_prolog.states.gfx9_prev_is_vs)
6323 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6324 else
6325 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6326 num_vgprs = 5; /* ES inputs are not needed by GS */
6327 } else {
6328 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6329 num_vgprs = 8;
6330 }
6331
6332 for (unsigned i = 0; i < num_sgprs; ++i) {
6333 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6334 returns[i] = ctx->i32;
6335 }
6336
6337 for (unsigned i = 0; i < num_vgprs; ++i) {
6338 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6339 returns[num_sgprs + i] = ctx->f32;
6340 }
6341
6342 /* Create the function. */
6343 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6344 &fninfo, 0);
6345 func = ctx->main_fn;
6346
6347 /* Set the full EXEC mask for the prolog, because we are only fiddling
6348 * with registers here. The main shader part will set the correct EXEC
6349 * mask.
6350 */
6351 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6352 ac_init_exec_full_mask(&ctx->ac);
6353
6354 /* Copy inputs to outputs. This should be no-op, as the registers match,
6355 * but it will prevent the compiler from overwriting them unintentionally.
6356 */
6357 ret = ctx->return_value;
6358 for (unsigned i = 0; i < num_sgprs; i++) {
6359 LLVMValueRef p = LLVMGetParam(func, i);
6360 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6361 }
6362 for (unsigned i = 0; i < num_vgprs; i++) {
6363 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6364 p = ac_to_float(&ctx->ac, p);
6365 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6366 }
6367
6368 if (key->gs_prolog.states.tri_strip_adj_fix) {
6369 /* Remap the input vertices for every other primitive. */
6370 const unsigned gfx6_vtx_params[6] = {
6371 num_sgprs,
6372 num_sgprs + 1,
6373 num_sgprs + 3,
6374 num_sgprs + 4,
6375 num_sgprs + 5,
6376 num_sgprs + 6
6377 };
6378 const unsigned gfx9_vtx_params[3] = {
6379 num_sgprs,
6380 num_sgprs + 1,
6381 num_sgprs + 4,
6382 };
6383 LLVMValueRef vtx_in[6], vtx_out[6];
6384 LLVMValueRef prim_id, rotate;
6385
6386 if (ctx->screen->info.chip_class >= GFX9) {
6387 for (unsigned i = 0; i < 3; i++) {
6388 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6389 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6390 }
6391 } else {
6392 for (unsigned i = 0; i < 6; i++)
6393 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6394 }
6395
6396 prim_id = LLVMGetParam(func, num_sgprs + 2);
6397 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6398
6399 for (unsigned i = 0; i < 6; ++i) {
6400 LLVMValueRef base, rotated;
6401 base = vtx_in[i];
6402 rotated = vtx_in[(i + 4) % 6];
6403 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6404 }
6405
6406 if (ctx->screen->info.chip_class >= GFX9) {
6407 for (unsigned i = 0; i < 3; i++) {
6408 LLVMValueRef hi, out;
6409
6410 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6411 LLVMConstInt(ctx->i32, 16, 0), "");
6412 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6413 out = ac_to_float(&ctx->ac, out);
6414 ret = LLVMBuildInsertValue(builder, ret, out,
6415 gfx9_vtx_params[i], "");
6416 }
6417 } else {
6418 for (unsigned i = 0; i < 6; i++) {
6419 LLVMValueRef out;
6420
6421 out = ac_to_float(&ctx->ac, vtx_out[i]);
6422 ret = LLVMBuildInsertValue(builder, ret, out,
6423 gfx6_vtx_params[i], "");
6424 }
6425 }
6426 }
6427
6428 LLVMBuildRet(builder, ret);
6429 }
6430
6431 /**
6432 * Given a list of shader part functions, build a wrapper function that
6433 * runs them in sequence to form a monolithic shader.
6434 */
6435 static void si_build_wrapper_function(struct si_shader_context *ctx,
6436 LLVMValueRef *parts,
6437 unsigned num_parts,
6438 unsigned main_part,
6439 unsigned next_shader_first_part)
6440 {
6441 LLVMBuilderRef builder = ctx->ac.builder;
6442 /* PS epilog has one arg per color component; gfx9 merged shader
6443 * prologs need to forward 32 user SGPRs.
6444 */
6445 struct si_function_info fninfo;
6446 LLVMValueRef initial[64], out[64];
6447 LLVMTypeRef function_type;
6448 unsigned num_first_params;
6449 unsigned num_out, initial_num_out;
6450 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6451 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6452 unsigned num_sgprs, num_vgprs;
6453 unsigned gprs;
6454 struct lp_build_if_state if_state;
6455
6456 si_init_function_info(&fninfo);
6457
6458 for (unsigned i = 0; i < num_parts; ++i) {
6459 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6460 AC_FUNC_ATTR_ALWAYSINLINE);
6461 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6462 }
6463
6464 /* The parameters of the wrapper function correspond to those of the
6465 * first part in terms of SGPRs and VGPRs, but we use the types of the
6466 * main part to get the right types. This is relevant for the
6467 * dereferenceable attribute on descriptor table pointers.
6468 */
6469 num_sgprs = 0;
6470 num_vgprs = 0;
6471
6472 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6473 num_first_params = LLVMCountParamTypes(function_type);
6474
6475 for (unsigned i = 0; i < num_first_params; ++i) {
6476 LLVMValueRef param = LLVMGetParam(parts[0], i);
6477
6478 if (ac_is_sgpr_param(param)) {
6479 assert(num_vgprs == 0);
6480 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6481 } else {
6482 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6483 }
6484 }
6485
6486 gprs = 0;
6487 while (gprs < num_sgprs + num_vgprs) {
6488 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6489 LLVMTypeRef type = LLVMTypeOf(param);
6490 unsigned size = ac_get_type_size(type) / 4;
6491
6492 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6493
6494 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6495 assert(gprs + size <= num_sgprs + num_vgprs &&
6496 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6497
6498 gprs += size;
6499 }
6500
6501 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6502 si_get_max_workgroup_size(ctx->shader));
6503
6504 if (is_merged_shader(ctx))
6505 ac_init_exec_full_mask(&ctx->ac);
6506
6507 /* Record the arguments of the function as if they were an output of
6508 * a previous part.
6509 */
6510 num_out = 0;
6511 num_out_sgpr = 0;
6512
6513 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6514 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6515 LLVMTypeRef param_type = LLVMTypeOf(param);
6516 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6517 unsigned size = ac_get_type_size(param_type) / 4;
6518
6519 if (size == 1) {
6520 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6521 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6522 param_type = ctx->i32;
6523 }
6524
6525 if (param_type != out_type)
6526 param = LLVMBuildBitCast(builder, param, out_type, "");
6527 out[num_out++] = param;
6528 } else {
6529 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6530
6531 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6532 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6533 param_type = ctx->i64;
6534 }
6535
6536 if (param_type != vector_type)
6537 param = LLVMBuildBitCast(builder, param, vector_type, "");
6538
6539 for (unsigned j = 0; j < size; ++j)
6540 out[num_out++] = LLVMBuildExtractElement(
6541 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6542 }
6543
6544 if (i < fninfo.num_sgpr_params)
6545 num_out_sgpr = num_out;
6546 }
6547
6548 memcpy(initial, out, sizeof(out));
6549 initial_num_out = num_out;
6550 initial_num_out_sgpr = num_out_sgpr;
6551
6552 /* Now chain the parts. */
6553 for (unsigned part = 0; part < num_parts; ++part) {
6554 LLVMValueRef in[48];
6555 LLVMValueRef ret;
6556 LLVMTypeRef ret_type;
6557 unsigned out_idx = 0;
6558 unsigned num_params = LLVMCountParams(parts[part]);
6559
6560 /* Merged shaders are executed conditionally depending
6561 * on the number of enabled threads passed in the input SGPRs. */
6562 if (is_merged_shader(ctx) && part == 0) {
6563 LLVMValueRef ena, count = initial[3];
6564
6565 count = LLVMBuildAnd(builder, count,
6566 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6567 ena = LLVMBuildICmp(builder, LLVMIntULT,
6568 ac_get_thread_id(&ctx->ac), count, "");
6569 lp_build_if(&if_state, &ctx->gallivm, ena);
6570 }
6571
6572 /* Derive arguments for the next part from outputs of the
6573 * previous one.
6574 */
6575 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6576 LLVMValueRef param;
6577 LLVMTypeRef param_type;
6578 bool is_sgpr;
6579 unsigned param_size;
6580 LLVMValueRef arg = NULL;
6581
6582 param = LLVMGetParam(parts[part], param_idx);
6583 param_type = LLVMTypeOf(param);
6584 param_size = ac_get_type_size(param_type) / 4;
6585 is_sgpr = ac_is_sgpr_param(param);
6586
6587 if (is_sgpr) {
6588 ac_add_function_attr(ctx->ac.context, parts[part],
6589 param_idx + 1, AC_FUNC_ATTR_INREG);
6590 } else if (out_idx < num_out_sgpr) {
6591 /* Skip returned SGPRs the current part doesn't
6592 * declare on the input. */
6593 out_idx = num_out_sgpr;
6594 }
6595
6596 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6597
6598 if (param_size == 1)
6599 arg = out[out_idx];
6600 else
6601 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6602
6603 if (LLVMTypeOf(arg) != param_type) {
6604 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6605 if (LLVMGetPointerAddressSpace(param_type) ==
6606 AC_ADDR_SPACE_CONST_32BIT) {
6607 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6608 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6609 } else {
6610 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6611 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6612 }
6613 } else {
6614 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6615 }
6616 }
6617
6618 in[param_idx] = arg;
6619 out_idx += param_size;
6620 }
6621
6622 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6623
6624 if (is_merged_shader(ctx) &&
6625 part + 1 == next_shader_first_part) {
6626 lp_build_endif(&if_state);
6627
6628 /* The second half of the merged shader should use
6629 * the inputs from the toplevel (wrapper) function,
6630 * not the return value from the last call.
6631 *
6632 * That's because the last call was executed condi-
6633 * tionally, so we can't consume it in the main
6634 * block.
6635 */
6636 memcpy(out, initial, sizeof(initial));
6637 num_out = initial_num_out;
6638 num_out_sgpr = initial_num_out_sgpr;
6639 continue;
6640 }
6641
6642 /* Extract the returned GPRs. */
6643 ret_type = LLVMTypeOf(ret);
6644 num_out = 0;
6645 num_out_sgpr = 0;
6646
6647 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6648 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6649
6650 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6651
6652 for (unsigned i = 0; i < ret_size; ++i) {
6653 LLVMValueRef val =
6654 LLVMBuildExtractValue(builder, ret, i, "");
6655
6656 assert(num_out < ARRAY_SIZE(out));
6657 out[num_out++] = val;
6658
6659 if (LLVMTypeOf(val) == ctx->i32) {
6660 assert(num_out_sgpr + 1 == num_out);
6661 num_out_sgpr = num_out;
6662 }
6663 }
6664 }
6665 }
6666
6667 LLVMBuildRetVoid(builder);
6668 }
6669
6670 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6671 struct si_shader_selector *sel)
6672 {
6673 if (!compiler->low_opt_passes)
6674 return false;
6675
6676 /* Assume a slow CPU. */
6677 assert(!sel->screen->info.has_dedicated_vram &&
6678 sel->screen->info.chip_class <= VI);
6679
6680 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6681 * buffer stores. */
6682 return sel->type == PIPE_SHADER_COMPUTE &&
6683 sel->info.num_memory_instructions > 1000;
6684 }
6685
6686 int si_compile_tgsi_shader(struct si_screen *sscreen,
6687 struct ac_llvm_compiler *compiler,
6688 struct si_shader *shader,
6689 struct pipe_debug_callback *debug)
6690 {
6691 struct si_shader_selector *sel = shader->selector;
6692 struct si_shader_context ctx;
6693 int r = -1;
6694
6695 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6696 * conversion fails. */
6697 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6698 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6699 if (sel->tokens)
6700 tgsi_dump(sel->tokens, 0);
6701 else
6702 nir_print_shader(sel->nir, stderr);
6703 si_dump_streamout(&sel->so);
6704 }
6705
6706 si_init_shader_ctx(&ctx, sscreen, compiler);
6707 si_llvm_context_set_tgsi(&ctx, shader);
6708
6709 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6710 sizeof(shader->info.vs_output_param_offset));
6711
6712 shader->info.uses_instanceid = sel->info.uses_instanceid;
6713
6714 if (!si_compile_tgsi_main(&ctx)) {
6715 si_llvm_dispose(&ctx);
6716 return -1;
6717 }
6718
6719 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6720 LLVMValueRef parts[2];
6721 bool need_prolog = sel->vs_needs_prolog;
6722
6723 parts[1] = ctx.main_fn;
6724
6725 if (need_prolog) {
6726 union si_shader_part_key prolog_key;
6727 si_get_vs_prolog_key(&sel->info,
6728 shader->info.num_input_sgprs,
6729 &shader->key.part.vs.prolog,
6730 shader, &prolog_key);
6731 si_build_vs_prolog_function(&ctx, &prolog_key);
6732 parts[0] = ctx.main_fn;
6733 }
6734
6735 si_build_wrapper_function(&ctx, parts + !need_prolog,
6736 1 + need_prolog, need_prolog, 0);
6737 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6738 if (sscreen->info.chip_class >= GFX9) {
6739 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6740 LLVMValueRef parts[4];
6741 bool vs_needs_prolog =
6742 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6743
6744 /* TCS main part */
6745 parts[2] = ctx.main_fn;
6746
6747 /* TCS epilog */
6748 union si_shader_part_key tcs_epilog_key;
6749 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6750 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6751 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6752 parts[3] = ctx.main_fn;
6753
6754 /* VS as LS main part */
6755 struct si_shader shader_ls = {};
6756 shader_ls.selector = ls;
6757 shader_ls.key.as_ls = 1;
6758 shader_ls.key.mono = shader->key.mono;
6759 shader_ls.key.opt = shader->key.opt;
6760 shader_ls.is_monolithic = true;
6761 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6762
6763 if (!si_compile_tgsi_main(&ctx)) {
6764 si_llvm_dispose(&ctx);
6765 return -1;
6766 }
6767 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6768 parts[1] = ctx.main_fn;
6769
6770 /* LS prolog */
6771 if (vs_needs_prolog) {
6772 union si_shader_part_key vs_prolog_key;
6773 si_get_vs_prolog_key(&ls->info,
6774 shader_ls.info.num_input_sgprs,
6775 &shader->key.part.tcs.ls_prolog,
6776 shader, &vs_prolog_key);
6777 vs_prolog_key.vs_prolog.is_monolithic = true;
6778 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6779 parts[0] = ctx.main_fn;
6780 }
6781
6782 /* Reset the shader context. */
6783 ctx.shader = shader;
6784 ctx.type = PIPE_SHADER_TESS_CTRL;
6785
6786 si_build_wrapper_function(&ctx,
6787 parts + !vs_needs_prolog,
6788 4 - !vs_needs_prolog, vs_needs_prolog,
6789 vs_needs_prolog ? 2 : 1);
6790 } else {
6791 LLVMValueRef parts[2];
6792 union si_shader_part_key epilog_key;
6793
6794 parts[0] = ctx.main_fn;
6795
6796 memset(&epilog_key, 0, sizeof(epilog_key));
6797 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6798 si_build_tcs_epilog_function(&ctx, &epilog_key);
6799 parts[1] = ctx.main_fn;
6800
6801 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6802 }
6803 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6804 if (ctx.screen->info.chip_class >= GFX9) {
6805 struct si_shader_selector *es = shader->key.part.gs.es;
6806 LLVMValueRef es_prolog = NULL;
6807 LLVMValueRef es_main = NULL;
6808 LLVMValueRef gs_prolog = NULL;
6809 LLVMValueRef gs_main = ctx.main_fn;
6810
6811 /* GS prolog */
6812 union si_shader_part_key gs_prolog_key;
6813 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6814 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6815 gs_prolog_key.gs_prolog.is_monolithic = true;
6816 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6817 gs_prolog = ctx.main_fn;
6818
6819 /* ES main part */
6820 struct si_shader shader_es = {};
6821 shader_es.selector = es;
6822 shader_es.key.as_es = 1;
6823 shader_es.key.mono = shader->key.mono;
6824 shader_es.key.opt = shader->key.opt;
6825 shader_es.is_monolithic = true;
6826 si_llvm_context_set_tgsi(&ctx, &shader_es);
6827
6828 if (!si_compile_tgsi_main(&ctx)) {
6829 si_llvm_dispose(&ctx);
6830 return -1;
6831 }
6832 shader->info.uses_instanceid |= es->info.uses_instanceid;
6833 es_main = ctx.main_fn;
6834
6835 /* ES prolog */
6836 if (es->vs_needs_prolog) {
6837 union si_shader_part_key vs_prolog_key;
6838 si_get_vs_prolog_key(&es->info,
6839 shader_es.info.num_input_sgprs,
6840 &shader->key.part.gs.vs_prolog,
6841 shader, &vs_prolog_key);
6842 vs_prolog_key.vs_prolog.is_monolithic = true;
6843 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6844 es_prolog = ctx.main_fn;
6845 }
6846
6847 /* Reset the shader context. */
6848 ctx.shader = shader;
6849 ctx.type = PIPE_SHADER_GEOMETRY;
6850
6851 /* Prepare the array of shader parts. */
6852 LLVMValueRef parts[4];
6853 unsigned num_parts = 0, main_part, next_first_part;
6854
6855 if (es_prolog)
6856 parts[num_parts++] = es_prolog;
6857
6858 parts[main_part = num_parts++] = es_main;
6859 parts[next_first_part = num_parts++] = gs_prolog;
6860 parts[num_parts++] = gs_main;
6861
6862 si_build_wrapper_function(&ctx, parts, num_parts,
6863 main_part, next_first_part);
6864 } else {
6865 LLVMValueRef parts[2];
6866 union si_shader_part_key prolog_key;
6867
6868 parts[1] = ctx.main_fn;
6869
6870 memset(&prolog_key, 0, sizeof(prolog_key));
6871 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6872 si_build_gs_prolog_function(&ctx, &prolog_key);
6873 parts[0] = ctx.main_fn;
6874
6875 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6876 }
6877 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6878 LLVMValueRef parts[3];
6879 union si_shader_part_key prolog_key;
6880 union si_shader_part_key epilog_key;
6881 bool need_prolog;
6882
6883 si_get_ps_prolog_key(shader, &prolog_key, false);
6884 need_prolog = si_need_ps_prolog(&prolog_key);
6885
6886 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6887
6888 if (need_prolog) {
6889 si_build_ps_prolog_function(&ctx, &prolog_key);
6890 parts[0] = ctx.main_fn;
6891 }
6892
6893 si_get_ps_epilog_key(shader, &epilog_key);
6894 si_build_ps_epilog_function(&ctx, &epilog_key);
6895 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6896
6897 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6898 need_prolog ? 1 : 0, 0);
6899 }
6900
6901 si_llvm_optimize_module(&ctx);
6902
6903 /* Post-optimization transformations and analysis. */
6904 si_optimize_vs_outputs(&ctx);
6905
6906 if ((debug && debug->debug_message) ||
6907 si_can_dump_shader(sscreen, ctx.type)) {
6908 ctx.shader->config.private_mem_vgprs =
6909 ac_count_scratch_private_memory(ctx.main_fn);
6910 }
6911
6912 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6913 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6914 LLVMPointerTypeKind);
6915
6916 /* Compile to bytecode. */
6917 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6918 ctx.ac.module, debug, ctx.type,
6919 si_get_shader_name(shader, ctx.type),
6920 si_should_optimize_less(compiler, shader->selector));
6921 si_llvm_dispose(&ctx);
6922 if (r) {
6923 fprintf(stderr, "LLVM failed to compile shader\n");
6924 return r;
6925 }
6926
6927 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6928 * LLVM 3.9svn has this bug.
6929 */
6930 if (sel->type == PIPE_SHADER_COMPUTE) {
6931 unsigned wave_size = 64;
6932 unsigned max_vgprs = 256;
6933 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6934 unsigned max_sgprs_per_wave = 128;
6935 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6936 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6937 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6938
6939 max_vgprs = max_vgprs / min_waves_per_simd;
6940 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6941
6942 if (shader->config.num_sgprs > max_sgprs ||
6943 shader->config.num_vgprs > max_vgprs) {
6944 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6945 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6946 shader->config.num_sgprs, shader->config.num_vgprs,
6947 max_sgprs, max_vgprs);
6948
6949 /* Just terminate the process, because dependent
6950 * shaders can hang due to bad input data, but use
6951 * the env var to allow shader-db to work.
6952 */
6953 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6954 abort();
6955 }
6956 }
6957
6958 /* Add the scratch offset to input SGPRs. */
6959 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6960 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6961
6962 /* Calculate the number of fragment input VGPRs. */
6963 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6964 shader->info.num_input_vgprs = 0;
6965 shader->info.face_vgpr_index = -1;
6966 shader->info.ancillary_vgpr_index = -1;
6967
6968 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6969 shader->info.num_input_vgprs += 2;
6970 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6971 shader->info.num_input_vgprs += 2;
6972 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6973 shader->info.num_input_vgprs += 2;
6974 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6975 shader->info.num_input_vgprs += 3;
6976 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6977 shader->info.num_input_vgprs += 2;
6978 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6979 shader->info.num_input_vgprs += 2;
6980 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6981 shader->info.num_input_vgprs += 2;
6982 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6983 shader->info.num_input_vgprs += 1;
6984 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6985 shader->info.num_input_vgprs += 1;
6986 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6987 shader->info.num_input_vgprs += 1;
6988 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6989 shader->info.num_input_vgprs += 1;
6990 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6991 shader->info.num_input_vgprs += 1;
6992 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6993 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6994 shader->info.num_input_vgprs += 1;
6995 }
6996 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6997 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6998 shader->info.num_input_vgprs += 1;
6999 }
7000 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7001 shader->info.num_input_vgprs += 1;
7002 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7003 shader->info.num_input_vgprs += 1;
7004 }
7005
7006 si_calculate_max_simd_waves(shader);
7007 si_shader_dump_stats_for_shader_db(shader, debug);
7008 return 0;
7009 }
7010
7011 /**
7012 * Create, compile and return a shader part (prolog or epilog).
7013 *
7014 * \param sscreen screen
7015 * \param list list of shader parts of the same category
7016 * \param type shader type
7017 * \param key shader part key
7018 * \param prolog whether the part being requested is a prolog
7019 * \param tm LLVM target machine
7020 * \param debug debug callback
7021 * \param build the callback responsible for building the main function
7022 * \return non-NULL on success
7023 */
7024 static struct si_shader_part *
7025 si_get_shader_part(struct si_screen *sscreen,
7026 struct si_shader_part **list,
7027 enum pipe_shader_type type,
7028 bool prolog,
7029 union si_shader_part_key *key,
7030 struct ac_llvm_compiler *compiler,
7031 struct pipe_debug_callback *debug,
7032 void (*build)(struct si_shader_context *,
7033 union si_shader_part_key *),
7034 const char *name)
7035 {
7036 struct si_shader_part *result;
7037
7038 mtx_lock(&sscreen->shader_parts_mutex);
7039
7040 /* Find existing. */
7041 for (result = *list; result; result = result->next) {
7042 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7043 mtx_unlock(&sscreen->shader_parts_mutex);
7044 return result;
7045 }
7046 }
7047
7048 /* Compile a new one. */
7049 result = CALLOC_STRUCT(si_shader_part);
7050 result->key = *key;
7051
7052 struct si_shader shader = {};
7053 struct si_shader_context ctx;
7054
7055 si_init_shader_ctx(&ctx, sscreen, compiler);
7056 ctx.shader = &shader;
7057 ctx.type = type;
7058
7059 switch (type) {
7060 case PIPE_SHADER_VERTEX:
7061 shader.key.as_ls = key->vs_prolog.as_ls;
7062 shader.key.as_es = key->vs_prolog.as_es;
7063 break;
7064 case PIPE_SHADER_TESS_CTRL:
7065 assert(!prolog);
7066 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7067 break;
7068 case PIPE_SHADER_GEOMETRY:
7069 assert(prolog);
7070 break;
7071 case PIPE_SHADER_FRAGMENT:
7072 if (prolog)
7073 shader.key.part.ps.prolog = key->ps_prolog.states;
7074 else
7075 shader.key.part.ps.epilog = key->ps_epilog.states;
7076 break;
7077 default:
7078 unreachable("bad shader part");
7079 }
7080
7081 build(&ctx, key);
7082
7083 /* Compile. */
7084 si_llvm_optimize_module(&ctx);
7085
7086 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7087 ctx.ac.module, debug, ctx.type, name, false)) {
7088 FREE(result);
7089 result = NULL;
7090 goto out;
7091 }
7092
7093 result->next = *list;
7094 *list = result;
7095
7096 out:
7097 si_llvm_dispose(&ctx);
7098 mtx_unlock(&sscreen->shader_parts_mutex);
7099 return result;
7100 }
7101
7102 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7103 {
7104 LLVMValueRef ptr[2], list;
7105 bool merged_shader = is_merged_shader(ctx);
7106
7107 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7108 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7109 ac_array_in_const32_addr_space(ctx->v4i32), "");
7110 return list;
7111 }
7112
7113 /**
7114 * Build the vertex shader prolog function.
7115 *
7116 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7117 * All inputs are returned unmodified. The vertex load indices are
7118 * stored after them, which will be used by the API VS for fetching inputs.
7119 *
7120 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7121 * input_v0,
7122 * input_v1,
7123 * input_v2,
7124 * input_v3,
7125 * (VertexID + BaseVertex),
7126 * (InstanceID + StartInstance),
7127 * (InstanceID / 2 + StartInstance)
7128 */
7129 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7130 union si_shader_part_key *key)
7131 {
7132 struct si_function_info fninfo;
7133 LLVMTypeRef *returns;
7134 LLVMValueRef ret, func;
7135 int num_returns, i;
7136 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7137 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7138 LLVMValueRef input_vgprs[9];
7139 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7140 num_input_vgprs;
7141 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7142
7143 si_init_function_info(&fninfo);
7144
7145 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7146 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7147 sizeof(LLVMTypeRef));
7148 num_returns = 0;
7149
7150 /* Declare input and output SGPRs. */
7151 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7152 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7153 returns[num_returns++] = ctx->i32;
7154 }
7155
7156 /* Preloaded VGPRs (outputs must be floats) */
7157 for (i = 0; i < num_input_vgprs; i++) {
7158 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7159 returns[num_returns++] = ctx->f32;
7160 }
7161
7162 /* Vertex load indices. */
7163 for (i = 0; i <= key->vs_prolog.last_input; i++)
7164 returns[num_returns++] = ctx->f32;
7165
7166 /* Create the function. */
7167 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7168 func = ctx->main_fn;
7169
7170 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7171 if (!key->vs_prolog.is_monolithic)
7172 si_init_exec_from_input(ctx, 3, 0);
7173
7174 if (key->vs_prolog.as_ls &&
7175 ctx->screen->has_ls_vgpr_init_bug) {
7176 /* If there are no HS threads, SPI loads the LS VGPRs
7177 * starting at VGPR 0. Shift them back to where they
7178 * belong.
7179 */
7180 LLVMValueRef has_hs_threads =
7181 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7182 si_unpack_param(ctx, 3, 8, 8),
7183 ctx->i32_0, "");
7184
7185 for (i = 4; i > 0; --i) {
7186 input_vgprs[i + 1] =
7187 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7188 input_vgprs[i + 1],
7189 input_vgprs[i - 1], "");
7190 }
7191 }
7192 }
7193
7194 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7195 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7196
7197 /* Copy inputs to outputs. This should be no-op, as the registers match,
7198 * but it will prevent the compiler from overwriting them unintentionally.
7199 */
7200 ret = ctx->return_value;
7201 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7202 LLVMValueRef p = LLVMGetParam(func, i);
7203 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7204 }
7205 for (i = 0; i < num_input_vgprs; i++) {
7206 LLVMValueRef p = input_vgprs[i];
7207 p = ac_to_float(&ctx->ac, p);
7208 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7209 key->vs_prolog.num_input_sgprs + i, "");
7210 }
7211
7212 /* Compute vertex load indices from instance divisors. */
7213 LLVMValueRef instance_divisor_constbuf = NULL;
7214
7215 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7216 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7217 LLVMValueRef buf_index =
7218 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7219 instance_divisor_constbuf =
7220 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7221 }
7222
7223 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7224 bool divisor_is_one =
7225 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7226 bool divisor_is_fetched =
7227 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7228 LLVMValueRef index = NULL;
7229
7230 if (divisor_is_one) {
7231 index = ctx->abi.instance_id;
7232 } else if (divisor_is_fetched) {
7233 LLVMValueRef udiv_factors[4];
7234
7235 for (unsigned j = 0; j < 4; j++) {
7236 udiv_factors[j] =
7237 buffer_load_const(ctx, instance_divisor_constbuf,
7238 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7239 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7240 }
7241 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7242 * Such InstanceID might not be achievable in a reasonable time though.
7243 */
7244 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7245 udiv_factors[0], udiv_factors[1],
7246 udiv_factors[2], udiv_factors[3]);
7247 }
7248
7249 if (divisor_is_one || divisor_is_fetched) {
7250 /* Add StartInstance. */
7251 index = LLVMBuildAdd(ctx->ac.builder, index,
7252 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7253 SI_SGPR_START_INSTANCE), "");
7254 } else {
7255 /* VertexID + BaseVertex */
7256 index = LLVMBuildAdd(ctx->ac.builder,
7257 ctx->abi.vertex_id,
7258 LLVMGetParam(func, user_sgpr_base +
7259 SI_SGPR_BASE_VERTEX), "");
7260 }
7261
7262 index = ac_to_float(&ctx->ac, index);
7263 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7264 fninfo.num_params + i, "");
7265 }
7266
7267 si_llvm_build_ret(ctx, ret);
7268 }
7269
7270 static bool si_get_vs_prolog(struct si_screen *sscreen,
7271 struct ac_llvm_compiler *compiler,
7272 struct si_shader *shader,
7273 struct pipe_debug_callback *debug,
7274 struct si_shader *main_part,
7275 const struct si_vs_prolog_bits *key)
7276 {
7277 struct si_shader_selector *vs = main_part->selector;
7278
7279 if (!si_vs_needs_prolog(vs, key))
7280 return true;
7281
7282 /* Get the prolog. */
7283 union si_shader_part_key prolog_key;
7284 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7285 key, shader, &prolog_key);
7286
7287 shader->prolog =
7288 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7289 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7290 debug, si_build_vs_prolog_function,
7291 "Vertex Shader Prolog");
7292 return shader->prolog != NULL;
7293 }
7294
7295 /**
7296 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7297 */
7298 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7299 struct ac_llvm_compiler *compiler,
7300 struct si_shader *shader,
7301 struct pipe_debug_callback *debug)
7302 {
7303 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7304 &shader->key.part.vs.prolog);
7305 }
7306
7307 /**
7308 * Compile the TCS epilog function. This writes tesselation factors to memory
7309 * based on the output primitive type of the tesselator (determined by TES).
7310 */
7311 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7312 union si_shader_part_key *key)
7313 {
7314 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7315 struct si_function_info fninfo;
7316 LLVMValueRef func;
7317
7318 si_init_function_info(&fninfo);
7319
7320 if (ctx->screen->info.chip_class >= GFX9) {
7321 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7322 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7323 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7324 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7325 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7326 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7327 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7328 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7329 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7330 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7331 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7332 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7333 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7334 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7340 } else {
7341 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7342 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7343 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7344 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7345 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7346 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7347 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7348 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7349 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7351 }
7352
7353 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7354 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7355 unsigned tess_factors_idx =
7356 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7357 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7358 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7359
7360 for (unsigned i = 0; i < 6; i++)
7361 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7362
7363 /* Create the function. */
7364 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7365 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7366 ac_declare_lds_as_pointer(&ctx->ac);
7367 func = ctx->main_fn;
7368
7369 LLVMValueRef invoc0_tess_factors[6];
7370 for (unsigned i = 0; i < 6; i++)
7371 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7372
7373 si_write_tess_factors(bld_base,
7374 LLVMGetParam(func, tess_factors_idx),
7375 LLVMGetParam(func, tess_factors_idx + 1),
7376 LLVMGetParam(func, tess_factors_idx + 2),
7377 invoc0_tess_factors, invoc0_tess_factors + 4);
7378
7379 LLVMBuildRetVoid(ctx->ac.builder);
7380 }
7381
7382 /**
7383 * Select and compile (or reuse) TCS parts (epilog).
7384 */
7385 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7386 struct ac_llvm_compiler *compiler,
7387 struct si_shader *shader,
7388 struct pipe_debug_callback *debug)
7389 {
7390 if (sscreen->info.chip_class >= GFX9) {
7391 struct si_shader *ls_main_part =
7392 shader->key.part.tcs.ls->main_shader_part_ls;
7393
7394 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7395 &shader->key.part.tcs.ls_prolog))
7396 return false;
7397
7398 shader->previous_stage = ls_main_part;
7399 }
7400
7401 /* Get the epilog. */
7402 union si_shader_part_key epilog_key;
7403 memset(&epilog_key, 0, sizeof(epilog_key));
7404 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7405
7406 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7407 PIPE_SHADER_TESS_CTRL, false,
7408 &epilog_key, compiler, debug,
7409 si_build_tcs_epilog_function,
7410 "Tessellation Control Shader Epilog");
7411 return shader->epilog != NULL;
7412 }
7413
7414 /**
7415 * Select and compile (or reuse) GS parts (prolog).
7416 */
7417 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7418 struct ac_llvm_compiler *compiler,
7419 struct si_shader *shader,
7420 struct pipe_debug_callback *debug)
7421 {
7422 if (sscreen->info.chip_class >= GFX9) {
7423 struct si_shader *es_main_part =
7424 shader->key.part.gs.es->main_shader_part_es;
7425
7426 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7427 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7428 &shader->key.part.gs.vs_prolog))
7429 return false;
7430
7431 shader->previous_stage = es_main_part;
7432 }
7433
7434 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7435 return true;
7436
7437 union si_shader_part_key prolog_key;
7438 memset(&prolog_key, 0, sizeof(prolog_key));
7439 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7440
7441 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7442 PIPE_SHADER_GEOMETRY, true,
7443 &prolog_key, compiler, debug,
7444 si_build_gs_prolog_function,
7445 "Geometry Shader Prolog");
7446 return shader->prolog2 != NULL;
7447 }
7448
7449 /**
7450 * Build the pixel shader prolog function. This handles:
7451 * - two-side color selection and interpolation
7452 * - overriding interpolation parameters for the API PS
7453 * - polygon stippling
7454 *
7455 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7456 * overriden by other states. (e.g. per-sample interpolation)
7457 * Interpolated colors are stored after the preloaded VGPRs.
7458 */
7459 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7460 union si_shader_part_key *key)
7461 {
7462 struct si_function_info fninfo;
7463 LLVMValueRef ret, func;
7464 int num_returns, i, num_color_channels;
7465
7466 assert(si_need_ps_prolog(key));
7467
7468 si_init_function_info(&fninfo);
7469
7470 /* Declare inputs. */
7471 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7472 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7473
7474 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7475 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7476
7477 /* Declare outputs (same as inputs + add colors if needed) */
7478 num_returns = fninfo.num_params;
7479 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7480 for (i = 0; i < num_color_channels; i++)
7481 fninfo.types[num_returns++] = ctx->f32;
7482
7483 /* Create the function. */
7484 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7485 &fninfo, 0);
7486 func = ctx->main_fn;
7487
7488 /* Copy inputs to outputs. This should be no-op, as the registers match,
7489 * but it will prevent the compiler from overwriting them unintentionally.
7490 */
7491 ret = ctx->return_value;
7492 for (i = 0; i < fninfo.num_params; i++) {
7493 LLVMValueRef p = LLVMGetParam(func, i);
7494 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7495 }
7496
7497 /* Polygon stippling. */
7498 if (key->ps_prolog.states.poly_stipple) {
7499 /* POS_FIXED_PT is always last. */
7500 unsigned pos = key->ps_prolog.num_input_sgprs +
7501 key->ps_prolog.num_input_vgprs - 1;
7502 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7503
7504 si_llvm_emit_polygon_stipple(ctx, list, pos);
7505 }
7506
7507 if (key->ps_prolog.states.bc_optimize_for_persp ||
7508 key->ps_prolog.states.bc_optimize_for_linear) {
7509 unsigned i, base = key->ps_prolog.num_input_sgprs;
7510 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7511
7512 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7513 * The hw doesn't compute CENTROID if the whole wave only
7514 * contains fully-covered quads.
7515 *
7516 * PRIM_MASK is after user SGPRs.
7517 */
7518 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7519 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7520 LLVMConstInt(ctx->i32, 31, 0), "");
7521 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7522 ctx->i1, "");
7523
7524 if (key->ps_prolog.states.bc_optimize_for_persp) {
7525 /* Read PERSP_CENTER. */
7526 for (i = 0; i < 2; i++)
7527 center[i] = LLVMGetParam(func, base + 2 + i);
7528 /* Read PERSP_CENTROID. */
7529 for (i = 0; i < 2; i++)
7530 centroid[i] = LLVMGetParam(func, base + 4 + i);
7531 /* Select PERSP_CENTROID. */
7532 for (i = 0; i < 2; i++) {
7533 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7534 center[i], centroid[i], "");
7535 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7536 tmp, base + 4 + i, "");
7537 }
7538 }
7539 if (key->ps_prolog.states.bc_optimize_for_linear) {
7540 /* Read LINEAR_CENTER. */
7541 for (i = 0; i < 2; i++)
7542 center[i] = LLVMGetParam(func, base + 8 + i);
7543 /* Read LINEAR_CENTROID. */
7544 for (i = 0; i < 2; i++)
7545 centroid[i] = LLVMGetParam(func, base + 10 + i);
7546 /* Select LINEAR_CENTROID. */
7547 for (i = 0; i < 2; i++) {
7548 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7549 center[i], centroid[i], "");
7550 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7551 tmp, base + 10 + i, "");
7552 }
7553 }
7554 }
7555
7556 /* Force per-sample interpolation. */
7557 if (key->ps_prolog.states.force_persp_sample_interp) {
7558 unsigned i, base = key->ps_prolog.num_input_sgprs;
7559 LLVMValueRef persp_sample[2];
7560
7561 /* Read PERSP_SAMPLE. */
7562 for (i = 0; i < 2; i++)
7563 persp_sample[i] = LLVMGetParam(func, base + i);
7564 /* Overwrite PERSP_CENTER. */
7565 for (i = 0; i < 2; i++)
7566 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7567 persp_sample[i], base + 2 + i, "");
7568 /* Overwrite PERSP_CENTROID. */
7569 for (i = 0; i < 2; i++)
7570 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7571 persp_sample[i], base + 4 + i, "");
7572 }
7573 if (key->ps_prolog.states.force_linear_sample_interp) {
7574 unsigned i, base = key->ps_prolog.num_input_sgprs;
7575 LLVMValueRef linear_sample[2];
7576
7577 /* Read LINEAR_SAMPLE. */
7578 for (i = 0; i < 2; i++)
7579 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7580 /* Overwrite LINEAR_CENTER. */
7581 for (i = 0; i < 2; i++)
7582 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7583 linear_sample[i], base + 8 + i, "");
7584 /* Overwrite LINEAR_CENTROID. */
7585 for (i = 0; i < 2; i++)
7586 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7587 linear_sample[i], base + 10 + i, "");
7588 }
7589
7590 /* Force center interpolation. */
7591 if (key->ps_prolog.states.force_persp_center_interp) {
7592 unsigned i, base = key->ps_prolog.num_input_sgprs;
7593 LLVMValueRef persp_center[2];
7594
7595 /* Read PERSP_CENTER. */
7596 for (i = 0; i < 2; i++)
7597 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7598 /* Overwrite PERSP_SAMPLE. */
7599 for (i = 0; i < 2; i++)
7600 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7601 persp_center[i], base + i, "");
7602 /* Overwrite PERSP_CENTROID. */
7603 for (i = 0; i < 2; i++)
7604 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7605 persp_center[i], base + 4 + i, "");
7606 }
7607 if (key->ps_prolog.states.force_linear_center_interp) {
7608 unsigned i, base = key->ps_prolog.num_input_sgprs;
7609 LLVMValueRef linear_center[2];
7610
7611 /* Read LINEAR_CENTER. */
7612 for (i = 0; i < 2; i++)
7613 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7614 /* Overwrite LINEAR_SAMPLE. */
7615 for (i = 0; i < 2; i++)
7616 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7617 linear_center[i], base + 6 + i, "");
7618 /* Overwrite LINEAR_CENTROID. */
7619 for (i = 0; i < 2; i++)
7620 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7621 linear_center[i], base + 10 + i, "");
7622 }
7623
7624 /* Interpolate colors. */
7625 unsigned color_out_idx = 0;
7626 for (i = 0; i < 2; i++) {
7627 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7628 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7629 key->ps_prolog.face_vgpr_index;
7630 LLVMValueRef interp[2], color[4];
7631 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7632
7633 if (!writemask)
7634 continue;
7635
7636 /* If the interpolation qualifier is not CONSTANT (-1). */
7637 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7638 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7639 key->ps_prolog.color_interp_vgpr_index[i];
7640
7641 /* Get the (i,j) updated by bc_optimize handling. */
7642 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7643 interp_vgpr, "");
7644 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7645 interp_vgpr + 1, "");
7646 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7647 }
7648
7649 /* Use the absolute location of the input. */
7650 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7651
7652 if (key->ps_prolog.states.color_two_side) {
7653 face = LLVMGetParam(func, face_vgpr);
7654 face = ac_to_integer(&ctx->ac, face);
7655 }
7656
7657 interp_fs_input(ctx,
7658 key->ps_prolog.color_attr_index[i],
7659 TGSI_SEMANTIC_COLOR, i,
7660 key->ps_prolog.num_interp_inputs,
7661 key->ps_prolog.colors_read, interp_ij,
7662 prim_mask, face, color);
7663
7664 while (writemask) {
7665 unsigned chan = u_bit_scan(&writemask);
7666 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7667 fninfo.num_params + color_out_idx++, "");
7668 }
7669 }
7670
7671 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7672 * says:
7673 *
7674 * "When per-sample shading is active due to the use of a fragment
7675 * input qualified by sample or due to the use of the gl_SampleID
7676 * or gl_SamplePosition variables, only the bit for the current
7677 * sample is set in gl_SampleMaskIn. When state specifies multiple
7678 * fragment shader invocations for a given fragment, the sample
7679 * mask for any single fragment shader invocation may specify a
7680 * subset of the covered samples for the fragment. In this case,
7681 * the bit corresponding to each covered sample will be set in
7682 * exactly one fragment shader invocation."
7683 *
7684 * The samplemask loaded by hardware is always the coverage of the
7685 * entire pixel/fragment, so mask bits out based on the sample ID.
7686 */
7687 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7688 /* The bit pattern matches that used by fixed function fragment
7689 * processing. */
7690 static const uint16_t ps_iter_masks[] = {
7691 0xffff, /* not used */
7692 0x5555,
7693 0x1111,
7694 0x0101,
7695 0x0001,
7696 };
7697 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7698
7699 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7700 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7701 key->ps_prolog.ancillary_vgpr_index;
7702 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7703 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7704
7705 samplemask = ac_to_integer(&ctx->ac, samplemask);
7706 samplemask = LLVMBuildAnd(
7707 ctx->ac.builder,
7708 samplemask,
7709 LLVMBuildShl(ctx->ac.builder,
7710 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7711 sampleid, ""),
7712 "");
7713 samplemask = ac_to_float(&ctx->ac, samplemask);
7714
7715 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7716 ancillary_vgpr + 1, "");
7717 }
7718
7719 /* Tell LLVM to insert WQM instruction sequence when needed. */
7720 if (key->ps_prolog.wqm) {
7721 LLVMAddTargetDependentFunctionAttr(func,
7722 "amdgpu-ps-wqm-outputs", "");
7723 }
7724
7725 si_llvm_build_ret(ctx, ret);
7726 }
7727
7728 /**
7729 * Build the pixel shader epilog function. This handles everything that must be
7730 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7731 */
7732 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7733 union si_shader_part_key *key)
7734 {
7735 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7736 struct si_function_info fninfo;
7737 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7738 int i;
7739 struct si_ps_exports exp = {};
7740
7741 si_init_function_info(&fninfo);
7742
7743 /* Declare input SGPRs. */
7744 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7745 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7746 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7747 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7748 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7749
7750 /* Declare input VGPRs. */
7751 unsigned required_num_params =
7752 fninfo.num_sgpr_params +
7753 util_bitcount(key->ps_epilog.colors_written) * 4 +
7754 key->ps_epilog.writes_z +
7755 key->ps_epilog.writes_stencil +
7756 key->ps_epilog.writes_samplemask;
7757
7758 required_num_params = MAX2(required_num_params,
7759 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7760
7761 while (fninfo.num_params < required_num_params)
7762 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7763
7764 /* Create the function. */
7765 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7766 /* Disable elimination of unused inputs. */
7767 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7768 "InitialPSInputAddr", 0xffffff);
7769
7770 /* Process colors. */
7771 unsigned vgpr = fninfo.num_sgpr_params;
7772 unsigned colors_written = key->ps_epilog.colors_written;
7773 int last_color_export = -1;
7774
7775 /* Find the last color export. */
7776 if (!key->ps_epilog.writes_z &&
7777 !key->ps_epilog.writes_stencil &&
7778 !key->ps_epilog.writes_samplemask) {
7779 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7780
7781 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7782 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7783 /* Just set this if any of the colorbuffers are enabled. */
7784 if (spi_format &
7785 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7786 last_color_export = 0;
7787 } else {
7788 for (i = 0; i < 8; i++)
7789 if (colors_written & (1 << i) &&
7790 (spi_format >> (i * 4)) & 0xf)
7791 last_color_export = i;
7792 }
7793 }
7794
7795 while (colors_written) {
7796 LLVMValueRef color[4];
7797 int mrt = u_bit_scan(&colors_written);
7798
7799 for (i = 0; i < 4; i++)
7800 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7801
7802 si_export_mrt_color(bld_base, color, mrt,
7803 fninfo.num_params - 1,
7804 mrt == last_color_export, &exp);
7805 }
7806
7807 /* Process depth, stencil, samplemask. */
7808 if (key->ps_epilog.writes_z)
7809 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7810 if (key->ps_epilog.writes_stencil)
7811 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7812 if (key->ps_epilog.writes_samplemask)
7813 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7814
7815 if (depth || stencil || samplemask)
7816 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7817 else if (last_color_export == -1)
7818 ac_build_export_null(&ctx->ac);
7819
7820 if (exp.num)
7821 si_emit_ps_exports(ctx, &exp);
7822
7823 /* Compile. */
7824 LLVMBuildRetVoid(ctx->ac.builder);
7825 }
7826
7827 /**
7828 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7829 */
7830 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7831 struct ac_llvm_compiler *compiler,
7832 struct si_shader *shader,
7833 struct pipe_debug_callback *debug)
7834 {
7835 union si_shader_part_key prolog_key;
7836 union si_shader_part_key epilog_key;
7837
7838 /* Get the prolog. */
7839 si_get_ps_prolog_key(shader, &prolog_key, true);
7840
7841 /* The prolog is a no-op if these aren't set. */
7842 if (si_need_ps_prolog(&prolog_key)) {
7843 shader->prolog =
7844 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7845 PIPE_SHADER_FRAGMENT, true,
7846 &prolog_key, compiler, debug,
7847 si_build_ps_prolog_function,
7848 "Fragment Shader Prolog");
7849 if (!shader->prolog)
7850 return false;
7851 }
7852
7853 /* Get the epilog. */
7854 si_get_ps_epilog_key(shader, &epilog_key);
7855
7856 shader->epilog =
7857 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7858 PIPE_SHADER_FRAGMENT, false,
7859 &epilog_key, compiler, debug,
7860 si_build_ps_epilog_function,
7861 "Fragment Shader Epilog");
7862 if (!shader->epilog)
7863 return false;
7864
7865 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7866 if (shader->key.part.ps.prolog.poly_stipple) {
7867 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7868 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7869 }
7870
7871 /* Set up the enable bits for per-sample shading if needed. */
7872 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7873 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7874 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7875 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7876 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7877 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7878 }
7879 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7880 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7881 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7882 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7883 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7884 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7885 }
7886 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7887 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7888 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7889 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7890 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7891 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7892 }
7893 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7894 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7895 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7896 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7897 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7898 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7899 }
7900
7901 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7902 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7903 !(shader->config.spi_ps_input_ena & 0xf)) {
7904 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7905 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7906 }
7907
7908 /* At least one pair of interpolation weights must be enabled. */
7909 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7910 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7911 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7912 }
7913
7914 /* Samplemask fixup requires the sample ID. */
7915 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7916 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7917 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7918 }
7919
7920 /* The sample mask input is always enabled, because the API shader always
7921 * passes it through to the epilog. Disable it here if it's unused.
7922 */
7923 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7924 !shader->selector->info.reads_samplemask)
7925 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7926
7927 return true;
7928 }
7929
7930 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7931 unsigned *lds_size)
7932 {
7933 /* If tessellation is all offchip and on-chip GS isn't used, this
7934 * workaround is not needed.
7935 */
7936 return;
7937
7938 /* SPI barrier management bug:
7939 * Make sure we have at least 4k of LDS in use to avoid the bug.
7940 * It applies to workgroup sizes of more than one wavefront.
7941 */
7942 if (sscreen->info.family == CHIP_BONAIRE ||
7943 sscreen->info.family == CHIP_KABINI ||
7944 sscreen->info.family == CHIP_MULLINS)
7945 *lds_size = MAX2(*lds_size, 8);
7946 }
7947
7948 static void si_fix_resource_usage(struct si_screen *sscreen,
7949 struct si_shader *shader)
7950 {
7951 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7952
7953 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7954
7955 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7956 si_get_max_workgroup_size(shader) > 64) {
7957 si_multiwave_lds_size_workaround(sscreen,
7958 &shader->config.lds_size);
7959 }
7960 }
7961
7962 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7963 struct si_shader *shader,
7964 struct pipe_debug_callback *debug)
7965 {
7966 struct si_shader_selector *sel = shader->selector;
7967 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7968 int r;
7969
7970 /* LS, ES, VS are compiled on demand if the main part hasn't been
7971 * compiled for that stage.
7972 *
7973 * Vertex shaders are compiled on demand when a vertex fetch
7974 * workaround must be applied.
7975 */
7976 if (shader->is_monolithic) {
7977 /* Monolithic shader (compiled as a whole, has many variants,
7978 * may take a long time to compile).
7979 */
7980 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7981 if (r)
7982 return r;
7983 } else {
7984 /* The shader consists of several parts:
7985 *
7986 * - the middle part is the user shader, it has 1 variant only
7987 * and it was compiled during the creation of the shader
7988 * selector
7989 * - the prolog part is inserted at the beginning
7990 * - the epilog part is inserted at the end
7991 *
7992 * The prolog and epilog have many (but simple) variants.
7993 *
7994 * Starting with gfx9, geometry and tessellation control
7995 * shaders also contain the prolog and user shader parts of
7996 * the previous shader stage.
7997 */
7998
7999 if (!mainp)
8000 return -1;
8001
8002 /* Copy the compiled TGSI shader data over. */
8003 shader->is_binary_shared = true;
8004 shader->binary = mainp->binary;
8005 shader->config = mainp->config;
8006 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8007 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8008 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8009 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8010 memcpy(shader->info.vs_output_param_offset,
8011 mainp->info.vs_output_param_offset,
8012 sizeof(mainp->info.vs_output_param_offset));
8013 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8014 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8015 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8016
8017 /* Select prologs and/or epilogs. */
8018 switch (sel->type) {
8019 case PIPE_SHADER_VERTEX:
8020 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8021 return -1;
8022 break;
8023 case PIPE_SHADER_TESS_CTRL:
8024 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8025 return -1;
8026 break;
8027 case PIPE_SHADER_TESS_EVAL:
8028 break;
8029 case PIPE_SHADER_GEOMETRY:
8030 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8031 return -1;
8032 break;
8033 case PIPE_SHADER_FRAGMENT:
8034 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8035 return -1;
8036
8037 /* Make sure we have at least as many VGPRs as there
8038 * are allocated inputs.
8039 */
8040 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8041 shader->info.num_input_vgprs);
8042 break;
8043 }
8044
8045 /* Update SGPR and VGPR counts. */
8046 if (shader->prolog) {
8047 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8048 shader->prolog->config.num_sgprs);
8049 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8050 shader->prolog->config.num_vgprs);
8051 }
8052 if (shader->previous_stage) {
8053 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8054 shader->previous_stage->config.num_sgprs);
8055 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8056 shader->previous_stage->config.num_vgprs);
8057 shader->config.spilled_sgprs =
8058 MAX2(shader->config.spilled_sgprs,
8059 shader->previous_stage->config.spilled_sgprs);
8060 shader->config.spilled_vgprs =
8061 MAX2(shader->config.spilled_vgprs,
8062 shader->previous_stage->config.spilled_vgprs);
8063 shader->config.private_mem_vgprs =
8064 MAX2(shader->config.private_mem_vgprs,
8065 shader->previous_stage->config.private_mem_vgprs);
8066 shader->config.scratch_bytes_per_wave =
8067 MAX2(shader->config.scratch_bytes_per_wave,
8068 shader->previous_stage->config.scratch_bytes_per_wave);
8069 shader->info.uses_instanceid |=
8070 shader->previous_stage->info.uses_instanceid;
8071 }
8072 if (shader->prolog2) {
8073 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8074 shader->prolog2->config.num_sgprs);
8075 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8076 shader->prolog2->config.num_vgprs);
8077 }
8078 if (shader->epilog) {
8079 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8080 shader->epilog->config.num_sgprs);
8081 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8082 shader->epilog->config.num_vgprs);
8083 }
8084 si_calculate_max_simd_waves(shader);
8085 }
8086
8087 si_fix_resource_usage(sscreen, shader);
8088 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8089 stderr, true);
8090
8091 /* Upload. */
8092 r = si_shader_binary_upload(sscreen, shader);
8093 if (r) {
8094 fprintf(stderr, "LLVM failed to upload shader\n");
8095 return r;
8096 }
8097
8098 return 0;
8099 }
8100
8101 void si_shader_destroy(struct si_shader *shader)
8102 {
8103 if (shader->scratch_bo)
8104 r600_resource_reference(&shader->scratch_bo, NULL);
8105
8106 r600_resource_reference(&shader->bo, NULL);
8107
8108 if (!shader->is_binary_shared)
8109 ac_shader_binary_clean(&shader->binary);
8110
8111 free(shader->shader_log);
8112 }