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radeonsi: compute only one set of interpolation (i,j) when MSAA is disabled
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94 int param_oc_lds;
95
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
98 */
99 int param_tess_offchip;
100
101 LLVMTargetMachineRef tm;
102
103 unsigned uniform_md_kind;
104 LLVMValueRef const_md;
105 LLVMValueRef empty_md;
106 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
107 LLVMValueRef lds;
108 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
109 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
110 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
111 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
112 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
113 LLVMValueRef images[SI_NUM_IMAGES];
114 LLVMValueRef so_buffers[4];
115 LLVMValueRef esgs_ring;
116 LLVMValueRef gsvs_ring[4];
117 LLVMValueRef gs_next_vertex[4];
118 LLVMValueRef return_value;
119
120 LLVMTypeRef voidt;
121 LLVMTypeRef i1;
122 LLVMTypeRef i8;
123 LLVMTypeRef i32;
124 LLVMTypeRef i64;
125 LLVMTypeRef i128;
126 LLVMTypeRef f32;
127 LLVMTypeRef v16i8;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v4i32;
130 LLVMTypeRef v4f32;
131 LLVMTypeRef v8i32;
132
133 LLVMValueRef shared_memory;
134 };
135
136 static struct si_shader_context *si_shader_context(
137 struct lp_build_tgsi_context *bld_base)
138 {
139 return (struct si_shader_context *)bld_base;
140 }
141
142 static void si_init_shader_ctx(struct si_shader_context *ctx,
143 struct si_screen *sscreen,
144 struct si_shader *shader,
145 LLVMTargetMachineRef tm);
146
147 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
148 struct lp_build_tgsi_context *bld_base,
149 struct lp_build_emit_data *emit_data);
150
151 /* Ideally pass the sample mask input to the PS epilog as v13, which
152 * is its usual location, so that the shader doesn't have to add v_mov.
153 */
154 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
155
156 /* The VS location of the PrimitiveID input is the same in the epilog,
157 * so that the main shader part doesn't have to move it.
158 */
159 #define VS_EPILOG_PRIMID_LOC 2
160
161 #define PERSPECTIVE_BASE 0
162 #define LINEAR_BASE 9
163
164 #define SAMPLE_OFFSET 0
165 #define CENTER_OFFSET 2
166 #define CENTROID_OFSET 4
167
168 #define USE_SGPR_MAX_SUFFIX_LEN 5
169 #define CONST_ADDR_SPACE 2
170 #define LOCAL_ADDR_SPACE 3
171 #define USER_SGPR_ADDR_SPACE 8
172
173
174 #define SENDMSG_GS 2
175 #define SENDMSG_GS_DONE 3
176
177 #define SENDMSG_GS_OP_NOP (0 << 4)
178 #define SENDMSG_GS_OP_CUT (1 << 4)
179 #define SENDMSG_GS_OP_EMIT (2 << 4)
180 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
181
182 /**
183 * Returns a unique index for a semantic name and index. The index must be
184 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
185 * calculated.
186 */
187 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
188 {
189 switch (semantic_name) {
190 case TGSI_SEMANTIC_POSITION:
191 return 0;
192 case TGSI_SEMANTIC_PSIZE:
193 return 1;
194 case TGSI_SEMANTIC_CLIPDIST:
195 assert(index <= 1);
196 return 2 + index;
197 case TGSI_SEMANTIC_GENERIC:
198 if (index <= 63-4)
199 return 4 + index;
200 else
201 /* same explanation as in the default statement,
202 * the only user hitting this is st/nine.
203 */
204 return 0;
205
206 /* patch indices are completely separate and thus start from 0 */
207 case TGSI_SEMANTIC_TESSOUTER:
208 return 0;
209 case TGSI_SEMANTIC_TESSINNER:
210 return 1;
211 case TGSI_SEMANTIC_PATCH:
212 return 2 + index;
213
214 default:
215 /* Don't fail here. The result of this function is only used
216 * for LS, TCS, TES, and GS, where legacy GL semantics can't
217 * occur, but this function is called for all vertex shaders
218 * before it's known whether LS will be compiled or not.
219 */
220 return 0;
221 }
222 }
223
224 /**
225 * Get the value of a shader input parameter and extract a bitfield.
226 */
227 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
228 unsigned param, unsigned rshift,
229 unsigned bitwidth)
230 {
231 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
232 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
233 param);
234
235 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
236 value = bitcast(&ctx->radeon_bld.soa.bld_base,
237 TGSI_TYPE_UNSIGNED, value);
238
239 if (rshift)
240 value = LLVMBuildLShr(gallivm->builder, value,
241 lp_build_const_int32(gallivm, rshift), "");
242
243 if (rshift + bitwidth < 32) {
244 unsigned mask = (1 << bitwidth) - 1;
245 value = LLVMBuildAnd(gallivm->builder, value,
246 lp_build_const_int32(gallivm, mask), "");
247 }
248
249 return value;
250 }
251
252 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
253 {
254 switch (ctx->type) {
255 case PIPE_SHADER_TESS_CTRL:
256 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
257
258 case PIPE_SHADER_TESS_EVAL:
259 return LLVMGetParam(ctx->radeon_bld.main_fn,
260 ctx->param_tes_rel_patch_id);
261
262 default:
263 assert(0);
264 return NULL;
265 }
266 }
267
268 /* Tessellation shaders pass outputs to the next shader using LDS.
269 *
270 * LS outputs = TCS inputs
271 * TCS outputs = TES inputs
272 *
273 * The LDS layout is:
274 * - TCS inputs for patch 0
275 * - TCS inputs for patch 1
276 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
277 * - ...
278 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
279 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
280 * - TCS outputs for patch 1
281 * - Per-patch TCS outputs for patch 1
282 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
283 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
284 * - ...
285 *
286 * All three shaders VS(LS), TCS, TES share the same LDS space.
287 */
288
289 static LLVMValueRef
290 get_tcs_in_patch_stride(struct si_shader_context *ctx)
291 {
292 if (ctx->type == PIPE_SHADER_VERTEX)
293 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
294 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
295 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
296 else {
297 assert(0);
298 return NULL;
299 }
300 }
301
302 static LLVMValueRef
303 get_tcs_out_patch_stride(struct si_shader_context *ctx)
304 {
305 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
306 }
307
308 static LLVMValueRef
309 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
310 {
311 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
312 unpack_param(ctx,
313 SI_PARAM_TCS_OUT_OFFSETS,
314 0, 16),
315 4);
316 }
317
318 static LLVMValueRef
319 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
320 {
321 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
322 unpack_param(ctx,
323 SI_PARAM_TCS_OUT_OFFSETS,
324 16, 16),
325 4);
326 }
327
328 static LLVMValueRef
329 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
330 {
331 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
332 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
333 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
334
335 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
343 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
344 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
345
346 return LLVMBuildAdd(gallivm->builder, patch0_offset,
347 LLVMBuildMul(gallivm->builder, patch_stride,
348 rel_patch_id, ""),
349 "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
354 {
355 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
356 LLVMValueRef patch0_patch_data_offset =
357 get_tcs_out_patch0_patch_data_offset(ctx);
358 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
359 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
360
361 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
362 LLVMBuildMul(gallivm->builder, patch_stride,
363 rel_patch_id, ""),
364 "");
365 }
366
367 static void build_indexed_store(struct si_shader_context *ctx,
368 LLVMValueRef base_ptr, LLVMValueRef index,
369 LLVMValueRef value)
370 {
371 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
372 struct gallivm_state *gallivm = bld_base->base.gallivm;
373 LLVMValueRef indices[2], pointer;
374
375 indices[0] = bld_base->uint_bld.zero;
376 indices[1] = index;
377
378 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
379 LLVMBuildStore(gallivm->builder, value, pointer);
380 }
381
382 /**
383 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
384 * It's equivalent to doing a load from &base_ptr[index].
385 *
386 * \param base_ptr Where the array starts.
387 * \param index The element index into the array.
388 * \param uniform Whether the base_ptr and index can be assumed to be
389 * dynamically uniform
390 */
391 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
392 LLVMValueRef base_ptr, LLVMValueRef index,
393 bool uniform)
394 {
395 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
396 struct gallivm_state *gallivm = bld_base->base.gallivm;
397 LLVMValueRef indices[2], pointer;
398
399 indices[0] = bld_base->uint_bld.zero;
400 indices[1] = index;
401
402 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
403 if (uniform)
404 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
405 return LLVMBuildLoad(gallivm->builder, pointer, "");
406 }
407
408 /**
409 * Do a load from &base_ptr[index], but also add a flag that it's loading
410 * a constant from a dynamically uniform index.
411 */
412 static LLVMValueRef build_indexed_load_const(
413 struct si_shader_context *ctx,
414 LLVMValueRef base_ptr, LLVMValueRef index)
415 {
416 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
417 LLVMSetMetadata(result, 1, ctx->const_md);
418 return result;
419 }
420
421 static LLVMValueRef get_instance_index_for_fetch(
422 struct radeon_llvm_context *radeon_bld,
423 unsigned param_start_instance, unsigned divisor)
424 {
425 struct si_shader_context *ctx =
426 si_shader_context(&radeon_bld->soa.bld_base);
427 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
428
429 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
430 ctx->param_instance_id);
431
432 /* The division must be done before START_INSTANCE is added. */
433 if (divisor > 1)
434 result = LLVMBuildUDiv(gallivm->builder, result,
435 lp_build_const_int32(gallivm, divisor), "");
436
437 return LLVMBuildAdd(gallivm->builder, result,
438 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
439 }
440
441 static void declare_input_vs(
442 struct radeon_llvm_context *radeon_bld,
443 unsigned input_index,
444 const struct tgsi_full_declaration *decl)
445 {
446 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
447 struct gallivm_state *gallivm = base->gallivm;
448 struct si_shader_context *ctx =
449 si_shader_context(&radeon_bld->soa.bld_base);
450 unsigned divisor =
451 ctx->shader->key.vs.prolog.instance_divisors[input_index];
452
453 unsigned chan;
454
455 LLVMValueRef t_list_ptr;
456 LLVMValueRef t_offset;
457 LLVMValueRef t_list;
458 LLVMValueRef attribute_offset;
459 LLVMValueRef buffer_index;
460 LLVMValueRef args[3];
461 LLVMValueRef input;
462
463 /* Load the T list */
464 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
465
466 t_offset = lp_build_const_int32(gallivm, input_index);
467
468 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
469
470 /* Build the attribute offset */
471 attribute_offset = lp_build_const_int32(gallivm, 0);
472
473 if (!ctx->is_monolithic) {
474 buffer_index = LLVMGetParam(radeon_bld->main_fn,
475 ctx->param_vertex_index0 +
476 input_index);
477 } else if (divisor) {
478 /* Build index from instance ID, start instance and divisor */
479 ctx->shader->info.uses_instanceid = true;
480 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
481 SI_PARAM_START_INSTANCE,
482 divisor);
483 } else {
484 /* Load the buffer index for vertices. */
485 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
486 ctx->param_vertex_id);
487 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
488 SI_PARAM_BASE_VERTEX);
489 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
490 }
491
492 args[0] = t_list;
493 args[1] = attribute_offset;
494 args[2] = buffer_index;
495 input = lp_build_intrinsic(gallivm->builder,
496 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
497 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
498
499 /* Break up the vec4 into individual components */
500 for (chan = 0; chan < 4; chan++) {
501 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
502 /* XXX: Use a helper function for this. There is one in
503 * tgsi_llvm.c. */
504 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
505 LLVMBuildExtractElement(gallivm->builder,
506 input, llvm_chan, "");
507 }
508 }
509
510 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
511 unsigned swizzle)
512 {
513 struct si_shader_context *ctx = si_shader_context(bld_base);
514
515 if (swizzle > 0)
516 return bld_base->uint_bld.zero;
517
518 switch (ctx->type) {
519 case PIPE_SHADER_VERTEX:
520 return LLVMGetParam(ctx->radeon_bld.main_fn,
521 ctx->param_vs_prim_id);
522 case PIPE_SHADER_TESS_CTRL:
523 return LLVMGetParam(ctx->radeon_bld.main_fn,
524 SI_PARAM_PATCH_ID);
525 case PIPE_SHADER_TESS_EVAL:
526 return LLVMGetParam(ctx->radeon_bld.main_fn,
527 ctx->param_tes_patch_id);
528 case PIPE_SHADER_GEOMETRY:
529 return LLVMGetParam(ctx->radeon_bld.main_fn,
530 SI_PARAM_PRIMITIVE_ID);
531 default:
532 assert(0);
533 return bld_base->uint_bld.zero;
534 }
535 }
536
537 /**
538 * Return the value of tgsi_ind_register for indexing.
539 * This is the indirect index with the constant offset added to it.
540 */
541 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
542 const struct tgsi_ind_register *ind,
543 int rel_index)
544 {
545 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
546 LLVMValueRef result;
547
548 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
549 result = LLVMBuildLoad(gallivm->builder, result, "");
550 result = LLVMBuildAdd(gallivm->builder, result,
551 lp_build_const_int32(gallivm, rel_index), "");
552 return result;
553 }
554
555 /**
556 * Like get_indirect_index, but restricts the return value to a (possibly
557 * undefined) value inside [0..num).
558 */
559 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
560 const struct tgsi_ind_register *ind,
561 int rel_index, unsigned num)
562 {
563 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
564 LLVMBuilderRef builder = gallivm->builder;
565 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
566 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
567 LLVMValueRef cc;
568
569 /* LLVM 3.8: If indirect resource indexing is used:
570 * - SI & CIK hang
571 * - VI crashes
572 */
573 if (HAVE_LLVM <= 0x0308)
574 return LLVMGetUndef(ctx->i32);
575
576 if (util_is_power_of_two(num)) {
577 result = LLVMBuildAnd(builder, result, c_max, "");
578 } else {
579 /* In theory, this MAX pattern should result in code that is
580 * as good as the bit-wise AND above.
581 *
582 * In practice, LLVM generates worse code (at the time of
583 * writing), because its value tracking is not strong enough.
584 */
585 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
586 result = LLVMBuildSelect(builder, cc, result, c_max, "");
587 }
588
589 return result;
590 }
591
592
593 /**
594 * Calculate a dword address given an input or output register and a stride.
595 */
596 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
597 const struct tgsi_full_dst_register *dst,
598 const struct tgsi_full_src_register *src,
599 LLVMValueRef vertex_dw_stride,
600 LLVMValueRef base_addr)
601 {
602 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
603 struct tgsi_shader_info *info = &ctx->shader->selector->info;
604 ubyte *name, *index, *array_first;
605 int first, param;
606 struct tgsi_full_dst_register reg;
607
608 /* Set the register description. The address computation is the same
609 * for sources and destinations. */
610 if (src) {
611 reg.Register.File = src->Register.File;
612 reg.Register.Index = src->Register.Index;
613 reg.Register.Indirect = src->Register.Indirect;
614 reg.Register.Dimension = src->Register.Dimension;
615 reg.Indirect = src->Indirect;
616 reg.Dimension = src->Dimension;
617 reg.DimIndirect = src->DimIndirect;
618 } else
619 reg = *dst;
620
621 /* If the register is 2-dimensional (e.g. an array of vertices
622 * in a primitive), calculate the base address of the vertex. */
623 if (reg.Register.Dimension) {
624 LLVMValueRef index;
625
626 if (reg.Dimension.Indirect)
627 index = get_indirect_index(ctx, &reg.DimIndirect,
628 reg.Dimension.Index);
629 else
630 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
631
632 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
633 LLVMBuildMul(gallivm->builder, index,
634 vertex_dw_stride, ""), "");
635 }
636
637 /* Get information about the register. */
638 if (reg.Register.File == TGSI_FILE_INPUT) {
639 name = info->input_semantic_name;
640 index = info->input_semantic_index;
641 array_first = info->input_array_first;
642 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
643 name = info->output_semantic_name;
644 index = info->output_semantic_index;
645 array_first = info->output_array_first;
646 } else {
647 assert(0);
648 return NULL;
649 }
650
651 if (reg.Register.Indirect) {
652 /* Add the relative address of the element. */
653 LLVMValueRef ind_index;
654
655 if (reg.Indirect.ArrayID)
656 first = array_first[reg.Indirect.ArrayID];
657 else
658 first = reg.Register.Index;
659
660 ind_index = get_indirect_index(ctx, &reg.Indirect,
661 reg.Register.Index - first);
662
663 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
664 LLVMBuildMul(gallivm->builder, ind_index,
665 lp_build_const_int32(gallivm, 4), ""), "");
666
667 param = si_shader_io_get_unique_index(name[first], index[first]);
668 } else {
669 param = si_shader_io_get_unique_index(name[reg.Register.Index],
670 index[reg.Register.Index]);
671 }
672
673 /* Add the base address of the element. */
674 return LLVMBuildAdd(gallivm->builder, base_addr,
675 lp_build_const_int32(gallivm, param * 4), "");
676 }
677
678 /* The offchip buffer layout for TCS->TES is
679 *
680 * - attribute 0 of patch 0 vertex 0
681 * - attribute 0 of patch 0 vertex 1
682 * - attribute 0 of patch 0 vertex 2
683 * ...
684 * - attribute 0 of patch 1 vertex 0
685 * - attribute 0 of patch 1 vertex 1
686 * ...
687 * - attribute 1 of patch 0 vertex 0
688 * - attribute 1 of patch 0 vertex 1
689 * ...
690 * - per patch attribute 0 of patch 0
691 * - per patch attribute 0 of patch 1
692 * ...
693 *
694 * Note that every attribute has 4 components.
695 */
696 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
697 LLVMValueRef vertex_index,
698 LLVMValueRef param_index)
699 {
700 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
701 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
702 LLVMValueRef param_stride, constant16;
703
704 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
705 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
706 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
707 num_patches, "");
708
709 constant16 = lp_build_const_int32(gallivm, 16);
710 if (vertex_index) {
711 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
712 vertices_per_patch, "");
713
714 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
715 vertex_index, "");
716
717 param_stride = total_vertices;
718 } else {
719 base_addr = get_rel_patch_id(ctx);
720 param_stride = num_patches;
721 }
722
723 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
724 LLVMBuildMul(gallivm->builder, param_index,
725 param_stride, ""), "");
726
727 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
728
729 if (!vertex_index) {
730 LLVMValueRef patch_data_offset =
731 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
732
733 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
734 patch_data_offset, "");
735 }
736 return base_addr;
737 }
738
739 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
740 struct si_shader_context *ctx,
741 const struct tgsi_full_dst_register *dst,
742 const struct tgsi_full_src_register *src)
743 {
744 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
745 struct tgsi_shader_info *info = &ctx->shader->selector->info;
746 ubyte *name, *index, *array_first;
747 struct tgsi_full_src_register reg;
748 LLVMValueRef vertex_index = NULL;
749 LLVMValueRef param_index = NULL;
750 unsigned param_index_base, param_base;
751
752 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
753
754 if (reg.Register.Dimension) {
755
756 if (reg.Dimension.Indirect)
757 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
758 reg.Dimension.Index);
759 else
760 vertex_index = lp_build_const_int32(gallivm,
761 reg.Dimension.Index);
762 }
763
764 /* Get information about the register. */
765 if (reg.Register.File == TGSI_FILE_INPUT) {
766 name = info->input_semantic_name;
767 index = info->input_semantic_index;
768 array_first = info->input_array_first;
769 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
770 name = info->output_semantic_name;
771 index = info->output_semantic_index;
772 array_first = info->output_array_first;
773 } else {
774 assert(0);
775 return NULL;
776 }
777
778 if (reg.Register.Indirect) {
779 if (reg.Indirect.ArrayID)
780 param_base = array_first[reg.Indirect.ArrayID];
781 else
782 param_base = reg.Register.Index;
783
784 param_index = get_indirect_index(ctx, &reg.Indirect,
785 reg.Register.Index - param_base);
786
787 } else {
788 param_base = reg.Register.Index;
789 param_index = lp_build_const_int32(gallivm, 0);
790 }
791
792 param_index_base = si_shader_io_get_unique_index(name[param_base],
793 index[param_base]);
794
795 param_index = LLVMBuildAdd(gallivm->builder, param_index,
796 lp_build_const_int32(gallivm, param_index_base),
797 "");
798
799 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
800 }
801
802 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
803 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
804 * or v4i32 (num_channels=3,4). */
805 static void build_tbuffer_store(struct si_shader_context *ctx,
806 LLVMValueRef rsrc,
807 LLVMValueRef vdata,
808 unsigned num_channels,
809 LLVMValueRef vaddr,
810 LLVMValueRef soffset,
811 unsigned inst_offset,
812 unsigned dfmt,
813 unsigned nfmt,
814 unsigned offen,
815 unsigned idxen,
816 unsigned glc,
817 unsigned slc,
818 unsigned tfe)
819 {
820 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
821 LLVMValueRef args[] = {
822 rsrc,
823 vdata,
824 LLVMConstInt(ctx->i32, num_channels, 0),
825 vaddr,
826 soffset,
827 LLVMConstInt(ctx->i32, inst_offset, 0),
828 LLVMConstInt(ctx->i32, dfmt, 0),
829 LLVMConstInt(ctx->i32, nfmt, 0),
830 LLVMConstInt(ctx->i32, offen, 0),
831 LLVMConstInt(ctx->i32, idxen, 0),
832 LLVMConstInt(ctx->i32, glc, 0),
833 LLVMConstInt(ctx->i32, slc, 0),
834 LLVMConstInt(ctx->i32, tfe, 0)
835 };
836
837 /* The instruction offset field has 12 bits */
838 assert(offen || inst_offset < (1 << 12));
839
840 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
841 unsigned func = CLAMP(num_channels, 1, 3) - 1;
842 const char *types[] = {"i32", "v2i32", "v4i32"};
843 char name[256];
844 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
845
846 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
847 args, ARRAY_SIZE(args), 0);
848 }
849
850 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
851 LLVMValueRef rsrc,
852 LLVMValueRef vdata,
853 unsigned num_channels,
854 LLVMValueRef vaddr,
855 LLVMValueRef soffset,
856 unsigned inst_offset)
857 {
858 static unsigned dfmt[] = {
859 V_008F0C_BUF_DATA_FORMAT_32,
860 V_008F0C_BUF_DATA_FORMAT_32_32,
861 V_008F0C_BUF_DATA_FORMAT_32_32_32,
862 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
863 };
864 assert(num_channels >= 1 && num_channels <= 4);
865
866 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
867 inst_offset, dfmt[num_channels-1],
868 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
869 }
870
871 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
872 LLVMValueRef rsrc,
873 int num_channels,
874 LLVMValueRef vindex,
875 LLVMValueRef voffset,
876 LLVMValueRef soffset,
877 unsigned inst_offset,
878 unsigned glc,
879 unsigned slc)
880 {
881 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
882 unsigned func = CLAMP(num_channels, 1, 3) - 1;
883
884 if (HAVE_LLVM >= 0x309) {
885 LLVMValueRef args[] = {
886 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
887 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
888 LLVMConstInt(ctx->i32, inst_offset, 0),
889 LLVMConstInt(ctx->i1, glc, 0),
890 LLVMConstInt(ctx->i1, slc, 0)
891 };
892
893 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
894 ctx->v4f32};
895 const char *type_names[] = {"f32", "v2f32", "v4f32"};
896 char name[256];
897
898 if (voffset) {
899 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
900 "");
901 }
902
903 if (soffset) {
904 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
905 "");
906 }
907
908 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
909 type_names[func]);
910
911 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
912 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
913 LLVMNoUnwindAttribute);
914 } else {
915 LLVMValueRef args[] = {
916 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
917 voffset ? voffset : vindex,
918 soffset,
919 LLVMConstInt(ctx->i32, inst_offset, 0),
920 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
921 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
922 LLVMConstInt(ctx->i32, glc, 0),
923 LLVMConstInt(ctx->i32, slc, 0),
924 LLVMConstInt(ctx->i32, 0, 0), // TFE
925 };
926
927 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
928 ctx->v4i32};
929 const char *type_names[] = {"i32", "v2i32", "v4i32"};
930 const char *arg_type = "i32";
931 char name[256];
932
933 if (voffset && vindex) {
934 LLVMValueRef vaddr[] = {vindex, voffset};
935
936 arg_type = "v2i32";
937 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
938 }
939
940 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
941 type_names[func], arg_type);
942
943 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
944 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
945 LLVMNoUnwindAttribute);
946 }
947 }
948
949 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
950 enum tgsi_opcode_type type, unsigned swizzle,
951 LLVMValueRef buffer, LLVMValueRef offset,
952 LLVMValueRef base)
953 {
954 struct si_shader_context *ctx = si_shader_context(bld_base);
955 struct gallivm_state *gallivm = bld_base->base.gallivm;
956 LLVMValueRef value, value2;
957 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
958 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
959
960 if (swizzle == ~0) {
961 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
962 0, 1, 0);
963
964 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
965 }
966
967 if (!tgsi_type_is_64bit(type)) {
968 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
969 0, 1, 0);
970
971 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
972 return LLVMBuildExtractElement(gallivm->builder, value,
973 lp_build_const_int32(gallivm, swizzle), "");
974 }
975
976 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
977 swizzle * 4, 1, 0);
978
979 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
980 swizzle * 4 + 4, 1, 0);
981
982 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
983 }
984
985 /**
986 * Load from LDS.
987 *
988 * \param type output value type
989 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
990 * \param dw_addr address in dwords
991 */
992 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
993 enum tgsi_opcode_type type, unsigned swizzle,
994 LLVMValueRef dw_addr)
995 {
996 struct si_shader_context *ctx = si_shader_context(bld_base);
997 struct gallivm_state *gallivm = bld_base->base.gallivm;
998 LLVMValueRef value;
999
1000 if (swizzle == ~0) {
1001 LLVMValueRef values[TGSI_NUM_CHANNELS];
1002
1003 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1004 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1005
1006 return lp_build_gather_values(bld_base->base.gallivm, values,
1007 TGSI_NUM_CHANNELS);
1008 }
1009
1010 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1011 lp_build_const_int32(gallivm, swizzle));
1012
1013 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1014 if (tgsi_type_is_64bit(type)) {
1015 LLVMValueRef value2;
1016 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1017 lp_build_const_int32(gallivm, swizzle + 1));
1018 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1019 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1020 }
1021
1022 return LLVMBuildBitCast(gallivm->builder, value,
1023 tgsi2llvmtype(bld_base, type), "");
1024 }
1025
1026 /**
1027 * Store to LDS.
1028 *
1029 * \param swizzle offset (typically 0..3)
1030 * \param dw_addr address in dwords
1031 * \param value value to store
1032 */
1033 static void lds_store(struct lp_build_tgsi_context *bld_base,
1034 unsigned swizzle, LLVMValueRef dw_addr,
1035 LLVMValueRef value)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 struct gallivm_state *gallivm = bld_base->base.gallivm;
1039
1040 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1041 lp_build_const_int32(gallivm, swizzle));
1042
1043 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1044 build_indexed_store(ctx, ctx->lds,
1045 dw_addr, value);
1046 }
1047
1048 static LLVMValueRef fetch_input_tcs(
1049 struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_src_register *reg,
1051 enum tgsi_opcode_type type, unsigned swizzle)
1052 {
1053 struct si_shader_context *ctx = si_shader_context(bld_base);
1054 LLVMValueRef dw_addr, stride;
1055
1056 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1057 dw_addr = get_tcs_in_current_patch_offset(ctx);
1058 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1059
1060 return lds_load(bld_base, type, swizzle, dw_addr);
1061 }
1062
1063 static LLVMValueRef fetch_output_tcs(
1064 struct lp_build_tgsi_context *bld_base,
1065 const struct tgsi_full_src_register *reg,
1066 enum tgsi_opcode_type type, unsigned swizzle)
1067 {
1068 struct si_shader_context *ctx = si_shader_context(bld_base);
1069 LLVMValueRef dw_addr, stride;
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1078 }
1079
1080 return lds_load(bld_base, type, swizzle, dw_addr);
1081 }
1082
1083 static LLVMValueRef fetch_input_tes(
1084 struct lp_build_tgsi_context *bld_base,
1085 const struct tgsi_full_src_register *reg,
1086 enum tgsi_opcode_type type, unsigned swizzle)
1087 {
1088 struct si_shader_context *ctx = si_shader_context(bld_base);
1089 struct gallivm_state *gallivm = bld_base->base.gallivm;
1090 LLVMValueRef rw_buffers, buffer, base, addr;
1091
1092 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1093 SI_PARAM_RW_BUFFERS);
1094 buffer = build_indexed_load_const(ctx, rw_buffers,
1095 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1096
1097 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1098 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1099
1100 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1101 }
1102
1103 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1104 const struct tgsi_full_instruction *inst,
1105 const struct tgsi_opcode_info *info,
1106 LLVMValueRef dst[4])
1107 {
1108 struct si_shader_context *ctx = si_shader_context(bld_base);
1109 struct gallivm_state *gallivm = bld_base->base.gallivm;
1110 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1111 unsigned chan_index;
1112 LLVMValueRef dw_addr, stride;
1113 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1114 LLVMValueRef values[4];
1115
1116 /* Only handle per-patch and per-vertex outputs here.
1117 * Vectors will be lowered to scalars and this function will be called again.
1118 */
1119 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1120 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1121 radeon_llvm_emit_store(bld_base, inst, info, dst);
1122 return;
1123 }
1124
1125 if (reg->Register.Dimension) {
1126 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1127 dw_addr = get_tcs_out_current_patch_offset(ctx);
1128 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1129 } else {
1130 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1131 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1132 }
1133
1134 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1135 SI_PARAM_RW_BUFFERS);
1136 buffer = build_indexed_load_const(ctx, rw_buffers,
1137 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1138
1139 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1140 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1141
1142
1143 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1144 LLVMValueRef value = dst[chan_index];
1145
1146 if (inst->Instruction.Saturate)
1147 value = radeon_llvm_saturate(bld_base, value);
1148
1149 lds_store(bld_base, chan_index, dw_addr, value);
1150
1151 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1152 values[chan_index] = value;
1153
1154 if (inst->Dst[0].Register.WriteMask != 0xF) {
1155 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1156 buf_addr, base,
1157 4 * chan_index);
1158 }
1159 }
1160
1161 if (inst->Dst[0].Register.WriteMask == 0xF) {
1162 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1163 values, 4);
1164 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1165 base, 0);
1166 }
1167 }
1168
1169 static LLVMValueRef fetch_input_gs(
1170 struct lp_build_tgsi_context *bld_base,
1171 const struct tgsi_full_src_register *reg,
1172 enum tgsi_opcode_type type,
1173 unsigned swizzle)
1174 {
1175 struct lp_build_context *base = &bld_base->base;
1176 struct si_shader_context *ctx = si_shader_context(bld_base);
1177 struct si_shader *shader = ctx->shader;
1178 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1179 struct gallivm_state *gallivm = base->gallivm;
1180 LLVMValueRef vtx_offset;
1181 LLVMValueRef args[9];
1182 unsigned vtx_offset_param;
1183 struct tgsi_shader_info *info = &shader->selector->info;
1184 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1185 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1186 unsigned param;
1187 LLVMValueRef value;
1188
1189 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1190 return get_primitive_id(bld_base, swizzle);
1191
1192 if (!reg->Register.Dimension)
1193 return NULL;
1194
1195 if (swizzle == ~0) {
1196 LLVMValueRef values[TGSI_NUM_CHANNELS];
1197 unsigned chan;
1198 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1199 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1200 }
1201 return lp_build_gather_values(bld_base->base.gallivm, values,
1202 TGSI_NUM_CHANNELS);
1203 }
1204
1205 /* Get the vertex offset parameter */
1206 vtx_offset_param = reg->Dimension.Index;
1207 if (vtx_offset_param < 2) {
1208 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1209 } else {
1210 assert(vtx_offset_param < 6);
1211 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1212 }
1213 vtx_offset = lp_build_mul_imm(uint,
1214 LLVMGetParam(ctx->radeon_bld.main_fn,
1215 vtx_offset_param),
1216 4);
1217
1218 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1219 args[0] = ctx->esgs_ring;
1220 args[1] = vtx_offset;
1221 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1222 args[3] = uint->zero;
1223 args[4] = uint->one; /* OFFEN */
1224 args[5] = uint->zero; /* IDXEN */
1225 args[6] = uint->one; /* GLC */
1226 args[7] = uint->zero; /* SLC */
1227 args[8] = uint->zero; /* TFE */
1228
1229 value = lp_build_intrinsic(gallivm->builder,
1230 "llvm.SI.buffer.load.dword.i32.i32",
1231 ctx->i32, args, 9,
1232 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1233 if (tgsi_type_is_64bit(type)) {
1234 LLVMValueRef value2;
1235 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1236 value2 = lp_build_intrinsic(gallivm->builder,
1237 "llvm.SI.buffer.load.dword.i32.i32",
1238 ctx->i32, args, 9,
1239 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1240 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1241 value, value2);
1242 }
1243 return LLVMBuildBitCast(gallivm->builder,
1244 value,
1245 tgsi2llvmtype(bld_base, type), "");
1246 }
1247
1248 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1249 {
1250 switch (interpolate) {
1251 case TGSI_INTERPOLATE_CONSTANT:
1252 return 0;
1253
1254 case TGSI_INTERPOLATE_LINEAR:
1255 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1256 return SI_PARAM_LINEAR_SAMPLE;
1257 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1258 return SI_PARAM_LINEAR_CENTROID;
1259 else
1260 return SI_PARAM_LINEAR_CENTER;
1261 break;
1262 case TGSI_INTERPOLATE_COLOR:
1263 case TGSI_INTERPOLATE_PERSPECTIVE:
1264 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1265 return SI_PARAM_PERSP_SAMPLE;
1266 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1267 return SI_PARAM_PERSP_CENTROID;
1268 else
1269 return SI_PARAM_PERSP_CENTER;
1270 break;
1271 default:
1272 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1273 return -1;
1274 }
1275 }
1276
1277 /* This shouldn't be used by explicit INTERP opcodes. */
1278 static unsigned select_interp_param(struct si_shader_context *ctx,
1279 unsigned param)
1280 {
1281 if (!ctx->is_monolithic)
1282 return param;
1283
1284 /* If the shader doesn't use center/centroid, just return the parameter.
1285 *
1286 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
1287 * switch between center/centroid and sample without shader changes.
1288 */
1289 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1290 switch (param) {
1291 case SI_PARAM_PERSP_CENTROID:
1292 case SI_PARAM_PERSP_CENTER:
1293 return SI_PARAM_PERSP_SAMPLE;
1294 }
1295 }
1296 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1297 switch (param) {
1298 case SI_PARAM_LINEAR_CENTROID:
1299 case SI_PARAM_LINEAR_CENTER:
1300 return SI_PARAM_LINEAR_SAMPLE;
1301 }
1302 }
1303 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1304 switch (param) {
1305 case SI_PARAM_PERSP_CENTROID:
1306 case SI_PARAM_PERSP_SAMPLE:
1307 return SI_PARAM_PERSP_CENTER;
1308 }
1309 }
1310 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1311 switch (param) {
1312 case SI_PARAM_LINEAR_CENTROID:
1313 case SI_PARAM_LINEAR_SAMPLE:
1314 return SI_PARAM_PERSP_CENTER;
1315 }
1316 }
1317
1318 return param;
1319 }
1320
1321 /**
1322 * Interpolate a fragment shader input.
1323 *
1324 * @param ctx context
1325 * @param input_index index of the input in hardware
1326 * @param semantic_name TGSI_SEMANTIC_*
1327 * @param semantic_index semantic index
1328 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1329 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1330 * @param interp_param interpolation weights (i,j)
1331 * @param prim_mask SI_PARAM_PRIM_MASK
1332 * @param face SI_PARAM_FRONT_FACE
1333 * @param result the return value (4 components)
1334 */
1335 static void interp_fs_input(struct si_shader_context *ctx,
1336 unsigned input_index,
1337 unsigned semantic_name,
1338 unsigned semantic_index,
1339 unsigned num_interp_inputs,
1340 unsigned colors_read_mask,
1341 LLVMValueRef interp_param,
1342 LLVMValueRef prim_mask,
1343 LLVMValueRef face,
1344 LLVMValueRef result[4])
1345 {
1346 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1347 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1348 struct gallivm_state *gallivm = base->gallivm;
1349 const char *intr_name;
1350 LLVMValueRef attr_number;
1351
1352 unsigned chan;
1353
1354 attr_number = lp_build_const_int32(gallivm, input_index);
1355
1356 /* fs.constant returns the param from the middle vertex, so it's not
1357 * really useful for flat shading. It's meant to be used for custom
1358 * interpolation (but the intrinsic can't fetch from the other two
1359 * vertices).
1360 *
1361 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1362 * to do the right thing. The only reason we use fs.constant is that
1363 * fs.interp cannot be used on integers, because they can be equal
1364 * to NaN.
1365 */
1366 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1367
1368 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1369 ctx->shader->key.ps.prolog.color_two_side) {
1370 LLVMValueRef args[4];
1371 LLVMValueRef is_face_positive;
1372 LLVMValueRef back_attr_number;
1373
1374 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1375 * otherwise it's at offset "num_inputs".
1376 */
1377 unsigned back_attr_offset = num_interp_inputs;
1378 if (semantic_index == 1 && colors_read_mask & 0xf)
1379 back_attr_offset += 1;
1380
1381 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1382
1383 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1384 face, uint->zero, "");
1385
1386 args[2] = prim_mask;
1387 args[3] = interp_param;
1388 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1389 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1390 LLVMValueRef front, back;
1391
1392 args[0] = llvm_chan;
1393 args[1] = attr_number;
1394 front = lp_build_intrinsic(gallivm->builder, intr_name,
1395 ctx->f32, args, args[3] ? 4 : 3,
1396 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1397
1398 args[1] = back_attr_number;
1399 back = lp_build_intrinsic(gallivm->builder, intr_name,
1400 ctx->f32, args, args[3] ? 4 : 3,
1401 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1402
1403 result[chan] = LLVMBuildSelect(gallivm->builder,
1404 is_face_positive,
1405 front,
1406 back,
1407 "");
1408 }
1409 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1410 LLVMValueRef args[4];
1411
1412 args[0] = uint->zero;
1413 args[1] = attr_number;
1414 args[2] = prim_mask;
1415 args[3] = interp_param;
1416 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1417 ctx->f32, args, args[3] ? 4 : 3,
1418 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1419 result[1] =
1420 result[2] = lp_build_const_float(gallivm, 0.0f);
1421 result[3] = lp_build_const_float(gallivm, 1.0f);
1422 } else {
1423 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1424 LLVMValueRef args[4];
1425 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1426
1427 args[0] = llvm_chan;
1428 args[1] = attr_number;
1429 args[2] = prim_mask;
1430 args[3] = interp_param;
1431 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1432 ctx->f32, args, args[3] ? 4 : 3,
1433 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1434 }
1435 }
1436 }
1437
1438 static void declare_input_fs(
1439 struct radeon_llvm_context *radeon_bld,
1440 unsigned input_index,
1441 const struct tgsi_full_declaration *decl)
1442 {
1443 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1444 struct si_shader_context *ctx =
1445 si_shader_context(&radeon_bld->soa.bld_base);
1446 struct si_shader *shader = ctx->shader;
1447 LLVMValueRef main_fn = radeon_bld->main_fn;
1448 LLVMValueRef interp_param = NULL;
1449 int interp_param_idx;
1450
1451 /* Get colors from input VGPRs (set by the prolog). */
1452 if (!ctx->is_monolithic &&
1453 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1454 unsigned i = decl->Semantic.Index;
1455 unsigned colors_read = shader->selector->info.colors_read;
1456 unsigned mask = colors_read >> (i * 4);
1457 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1458 (i ? util_bitcount(colors_read & 0xf) : 0);
1459
1460 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1461 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1462 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1463 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1464 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1465 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1466 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1467 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1468 return;
1469 }
1470
1471 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1472 decl->Interp.Location);
1473 if (interp_param_idx == -1)
1474 return;
1475 else if (interp_param_idx) {
1476 interp_param_idx = select_interp_param(ctx,
1477 interp_param_idx);
1478 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1479 }
1480
1481 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1482 decl->Semantic.Index, shader->selector->info.num_inputs,
1483 shader->selector->info.colors_read, interp_param,
1484 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1485 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1486 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1487 }
1488
1489 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1490 {
1491 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1492 SI_PARAM_ANCILLARY, 8, 4);
1493 }
1494
1495 /**
1496 * Set range metadata on an instruction. This can only be used on load and
1497 * call instructions. If you know an instruction can only produce the values
1498 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1499 * \p lo is the minimum value inclusive.
1500 * \p hi is the maximum value exclusive.
1501 */
1502 static void set_range_metadata(LLVMValueRef value, unsigned lo, unsigned hi)
1503 {
1504 const char *range_md_string = "range";
1505 LLVMValueRef range_md, md_args[2];
1506 LLVMTypeRef type = LLVMTypeOf(value);
1507 LLVMContextRef context = LLVMGetTypeContext(type);
1508 unsigned md_range_id = LLVMGetMDKindIDInContext(context,
1509 range_md_string, strlen(range_md_string));
1510
1511 md_args[0] = LLVMConstInt(type, lo, false);
1512 md_args[1] = LLVMConstInt(type, hi, false);
1513 range_md = LLVMMDNodeInContext(context, md_args, 2);
1514 LLVMSetMetadata(value, md_range_id, range_md);
1515 }
1516
1517 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1518 {
1519 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1520 LLVMValueRef tid;
1521
1522 if (HAVE_LLVM < 0x0308) {
1523 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1524 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1525 } else {
1526 LLVMValueRef tid_args[2];
1527 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1528 tid_args[1] = lp_build_const_int32(gallivm, 0);
1529 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1530 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1531 tid_args, 2, LLVMReadNoneAttribute);
1532
1533 tid = lp_build_intrinsic(gallivm->builder,
1534 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1535 tid_args, 2, LLVMReadNoneAttribute);
1536 }
1537 set_range_metadata(tid, 0, 64);
1538 return tid;
1539 }
1540
1541 /**
1542 * Load a dword from a constant buffer.
1543 */
1544 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1545 LLVMValueRef offset, LLVMTypeRef return_type)
1546 {
1547 LLVMValueRef args[2] = {resource, offset};
1548
1549 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1550 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1551 }
1552
1553 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1554 {
1555 struct si_shader_context *ctx =
1556 si_shader_context(&radeon_bld->soa.bld_base);
1557 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1558 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1559 LLVMBuilderRef builder = gallivm->builder;
1560 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1561 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1562 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1563
1564 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1565 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1566 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1567
1568 LLVMValueRef pos[4] = {
1569 buffer_load_const(builder, resource, offset0, ctx->f32),
1570 buffer_load_const(builder, resource, offset1, ctx->f32),
1571 lp_build_const_float(gallivm, 0),
1572 lp_build_const_float(gallivm, 0)
1573 };
1574
1575 return lp_build_gather_values(gallivm, pos, 4);
1576 }
1577
1578 static void declare_system_value(
1579 struct radeon_llvm_context *radeon_bld,
1580 unsigned index,
1581 const struct tgsi_full_declaration *decl)
1582 {
1583 struct si_shader_context *ctx =
1584 si_shader_context(&radeon_bld->soa.bld_base);
1585 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1586 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1587 LLVMValueRef value = 0;
1588
1589 switch (decl->Semantic.Name) {
1590 case TGSI_SEMANTIC_INSTANCEID:
1591 value = LLVMGetParam(radeon_bld->main_fn,
1592 ctx->param_instance_id);
1593 break;
1594
1595 case TGSI_SEMANTIC_VERTEXID:
1596 value = LLVMBuildAdd(gallivm->builder,
1597 LLVMGetParam(radeon_bld->main_fn,
1598 ctx->param_vertex_id),
1599 LLVMGetParam(radeon_bld->main_fn,
1600 SI_PARAM_BASE_VERTEX), "");
1601 break;
1602
1603 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1604 value = LLVMGetParam(radeon_bld->main_fn,
1605 ctx->param_vertex_id);
1606 break;
1607
1608 case TGSI_SEMANTIC_BASEVERTEX:
1609 value = LLVMGetParam(radeon_bld->main_fn,
1610 SI_PARAM_BASE_VERTEX);
1611 break;
1612
1613 case TGSI_SEMANTIC_INVOCATIONID:
1614 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1615 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1616 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1617 value = LLVMGetParam(radeon_bld->main_fn,
1618 SI_PARAM_GS_INSTANCE_ID);
1619 else
1620 assert(!"INVOCATIONID not implemented");
1621 break;
1622
1623 case TGSI_SEMANTIC_POSITION:
1624 {
1625 LLVMValueRef pos[4] = {
1626 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1627 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1628 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1629 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1630 LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_POS_W_FLOAT)),
1632 };
1633 value = lp_build_gather_values(gallivm, pos, 4);
1634 break;
1635 }
1636
1637 case TGSI_SEMANTIC_FACE:
1638 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1639 break;
1640
1641 case TGSI_SEMANTIC_SAMPLEID:
1642 value = get_sample_id(radeon_bld);
1643 break;
1644
1645 case TGSI_SEMANTIC_SAMPLEPOS: {
1646 LLVMValueRef pos[4] = {
1647 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1648 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1649 lp_build_const_float(gallivm, 0),
1650 lp_build_const_float(gallivm, 0)
1651 };
1652 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1653 TGSI_OPCODE_FRC, pos[0]);
1654 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1655 TGSI_OPCODE_FRC, pos[1]);
1656 value = lp_build_gather_values(gallivm, pos, 4);
1657 break;
1658 }
1659
1660 case TGSI_SEMANTIC_SAMPLEMASK:
1661 /* This can only occur with the OpenGL Core profile, which
1662 * doesn't support smoothing.
1663 */
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1665 break;
1666
1667 case TGSI_SEMANTIC_TESSCOORD:
1668 {
1669 LLVMValueRef coord[4] = {
1670 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1671 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1672 bld->zero,
1673 bld->zero
1674 };
1675
1676 /* For triangles, the vector should be (u, v, 1-u-v). */
1677 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1678 PIPE_PRIM_TRIANGLES)
1679 coord[2] = lp_build_sub(bld, bld->one,
1680 lp_build_add(bld, coord[0], coord[1]));
1681
1682 value = lp_build_gather_values(gallivm, coord, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_VERTICESIN:
1687 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1688 break;
1689
1690 case TGSI_SEMANTIC_TESSINNER:
1691 case TGSI_SEMANTIC_TESSOUTER:
1692 {
1693 LLVMValueRef rw_buffers, buffer, base, addr;
1694 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1695
1696 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1697 SI_PARAM_RW_BUFFERS);
1698 buffer = build_indexed_load_const(ctx, rw_buffers,
1699 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1700
1701 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1702 addr = get_tcs_tes_buffer_address(ctx, NULL,
1703 lp_build_const_int32(gallivm, param));
1704
1705 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1706 ~0, buffer, base, addr);
1707
1708 break;
1709 }
1710
1711 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1712 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1713 {
1714 LLVMValueRef buf, slot, val[4];
1715 int i, offset;
1716
1717 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1718 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1719 buf = build_indexed_load_const(ctx, buf, slot);
1720 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1721
1722 for (i = 0; i < 4; i++)
1723 val[i] = buffer_load_const(gallivm->builder, buf,
1724 lp_build_const_int32(gallivm, (offset + i) * 4),
1725 ctx->f32);
1726 value = lp_build_gather_values(gallivm, val, 4);
1727 break;
1728 }
1729
1730 case TGSI_SEMANTIC_PRIMID:
1731 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1732 break;
1733
1734 case TGSI_SEMANTIC_GRID_SIZE:
1735 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1736 break;
1737
1738 case TGSI_SEMANTIC_BLOCK_SIZE:
1739 {
1740 LLVMValueRef values[3];
1741 unsigned i;
1742 unsigned *properties = ctx->shader->selector->info.properties;
1743 unsigned sizes[3] = {
1744 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1745 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1746 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1747 };
1748
1749 for (i = 0; i < 3; ++i)
1750 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1751
1752 value = lp_build_gather_values(gallivm, values, 3);
1753 break;
1754 }
1755
1756 case TGSI_SEMANTIC_BLOCK_ID:
1757 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1758 break;
1759
1760 case TGSI_SEMANTIC_THREAD_ID:
1761 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1762 break;
1763
1764 #if HAVE_LLVM >= 0x0309
1765 case TGSI_SEMANTIC_HELPER_INVOCATION:
1766 value = lp_build_intrinsic(gallivm->builder,
1767 "llvm.amdgcn.ps.live",
1768 ctx->i1, NULL, 0,
1769 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1770 value = LLVMBuildNot(gallivm->builder, value, "");
1771 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1772 break;
1773 #endif
1774
1775 default:
1776 assert(!"unknown system value");
1777 return;
1778 }
1779
1780 radeon_bld->system_values[index] = value;
1781 }
1782
1783 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1784 const struct tgsi_full_declaration *decl)
1785 {
1786 struct si_shader_context *ctx =
1787 si_shader_context(&radeon_bld->soa.bld_base);
1788 struct si_shader_selector *sel = ctx->shader->selector;
1789 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1790
1791 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1792 LLVMValueRef var;
1793
1794 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1795 assert(decl->Range.First == decl->Range.Last);
1796 assert(!ctx->shared_memory);
1797
1798 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1799 LLVMArrayType(ctx->i8, sel->local_size),
1800 "compute_lds",
1801 LOCAL_ADDR_SPACE);
1802 LLVMSetAlignment(var, 4);
1803
1804 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1805 }
1806
1807 static LLVMValueRef fetch_constant(
1808 struct lp_build_tgsi_context *bld_base,
1809 const struct tgsi_full_src_register *reg,
1810 enum tgsi_opcode_type type,
1811 unsigned swizzle)
1812 {
1813 struct si_shader_context *ctx = si_shader_context(bld_base);
1814 struct lp_build_context *base = &bld_base->base;
1815 const struct tgsi_ind_register *ireg = &reg->Indirect;
1816 unsigned buf, idx;
1817
1818 LLVMValueRef addr, bufp;
1819 LLVMValueRef result;
1820
1821 if (swizzle == LP_CHAN_ALL) {
1822 unsigned chan;
1823 LLVMValueRef values[4];
1824 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1825 values[chan] = fetch_constant(bld_base, reg, type, chan);
1826
1827 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1828 }
1829
1830 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1831 idx = reg->Register.Index * 4 + swizzle;
1832
1833 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1834 if (!tgsi_type_is_64bit(type))
1835 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1836 else {
1837 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1838 ctx->constants[buf][idx],
1839 ctx->constants[buf][idx + 1]);
1840 }
1841 }
1842
1843 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1844 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1845 LLVMValueRef index;
1846 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1847 reg->Dimension.Index,
1848 SI_NUM_CONST_BUFFERS);
1849 bufp = build_indexed_load_const(ctx, ptr, index);
1850 } else
1851 bufp = ctx->const_buffers[buf];
1852
1853 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1854 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1855 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1856 addr = lp_build_add(&bld_base->uint_bld, addr,
1857 lp_build_const_int32(base->gallivm, idx * 4));
1858
1859 result = buffer_load_const(base->gallivm->builder, bufp,
1860 addr, ctx->f32);
1861
1862 if (!tgsi_type_is_64bit(type))
1863 result = bitcast(bld_base, type, result);
1864 else {
1865 LLVMValueRef addr2, result2;
1866 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1867 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1868 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1869 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1870 lp_build_const_int32(base->gallivm, idx * 4));
1871
1872 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1873 addr2, ctx->f32);
1874
1875 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1876 result, result2);
1877 }
1878 return result;
1879 }
1880
1881 /* Upper 16 bits must be zero. */
1882 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1883 LLVMValueRef val[2])
1884 {
1885 return LLVMBuildOr(gallivm->builder, val[0],
1886 LLVMBuildShl(gallivm->builder, val[1],
1887 lp_build_const_int32(gallivm, 16),
1888 ""), "");
1889 }
1890
1891 /* Upper 16 bits are ignored and will be dropped. */
1892 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1893 LLVMValueRef val[2])
1894 {
1895 LLVMValueRef v[2] = {
1896 LLVMBuildAnd(gallivm->builder, val[0],
1897 lp_build_const_int32(gallivm, 0xffff), ""),
1898 val[1],
1899 };
1900 return si_llvm_pack_two_int16(gallivm, v);
1901 }
1902
1903 /* Initialize arguments for the shader export intrinsic */
1904 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1905 LLVMValueRef *values,
1906 unsigned target,
1907 LLVMValueRef *args)
1908 {
1909 struct si_shader_context *ctx = si_shader_context(bld_base);
1910 struct lp_build_context *uint =
1911 &ctx->radeon_bld.soa.bld_base.uint_bld;
1912 struct lp_build_context *base = &bld_base->base;
1913 struct gallivm_state *gallivm = base->gallivm;
1914 LLVMBuilderRef builder = base->gallivm->builder;
1915 LLVMValueRef val[4];
1916 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1917 unsigned chan;
1918 bool is_int8;
1919
1920 /* Default is 0xf. Adjusted below depending on the format. */
1921 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1922
1923 /* Specify whether the EXEC mask represents the valid mask */
1924 args[1] = uint->zero;
1925
1926 /* Specify whether this is the last export */
1927 args[2] = uint->zero;
1928
1929 /* Specify the target we are exporting */
1930 args[3] = lp_build_const_int32(base->gallivm, target);
1931
1932 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1933 const union si_shader_key *key = &ctx->shader->key;
1934 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1935 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1936
1937 assert(cbuf >= 0 && cbuf < 8);
1938 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1939 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1940 }
1941
1942 args[4] = uint->zero; /* COMPR flag */
1943 args[5] = base->undef;
1944 args[6] = base->undef;
1945 args[7] = base->undef;
1946 args[8] = base->undef;
1947
1948 switch (spi_shader_col_format) {
1949 case V_028714_SPI_SHADER_ZERO:
1950 args[0] = uint->zero; /* writemask */
1951 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1952 break;
1953
1954 case V_028714_SPI_SHADER_32_R:
1955 args[0] = uint->one; /* writemask */
1956 args[5] = values[0];
1957 break;
1958
1959 case V_028714_SPI_SHADER_32_GR:
1960 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1961 args[5] = values[0];
1962 args[6] = values[1];
1963 break;
1964
1965 case V_028714_SPI_SHADER_32_AR:
1966 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1967 args[5] = values[0];
1968 args[8] = values[3];
1969 break;
1970
1971 case V_028714_SPI_SHADER_FP16_ABGR:
1972 args[4] = uint->one; /* COMPR flag */
1973
1974 for (chan = 0; chan < 2; chan++) {
1975 LLVMValueRef pack_args[2] = {
1976 values[2 * chan],
1977 values[2 * chan + 1]
1978 };
1979 LLVMValueRef packed;
1980
1981 packed = lp_build_intrinsic(base->gallivm->builder,
1982 "llvm.SI.packf16",
1983 ctx->i32, pack_args, 2,
1984 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1985 args[chan + 5] =
1986 LLVMBuildBitCast(base->gallivm->builder,
1987 packed, ctx->f32, "");
1988 }
1989 break;
1990
1991 case V_028714_SPI_SHADER_UNORM16_ABGR:
1992 for (chan = 0; chan < 4; chan++) {
1993 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1994 val[chan] = LLVMBuildFMul(builder, val[chan],
1995 lp_build_const_float(gallivm, 65535), "");
1996 val[chan] = LLVMBuildFAdd(builder, val[chan],
1997 lp_build_const_float(gallivm, 0.5), "");
1998 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1999 ctx->i32, "");
2000 }
2001
2002 args[4] = uint->one; /* COMPR flag */
2003 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2004 si_llvm_pack_two_int16(gallivm, val));
2005 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2006 si_llvm_pack_two_int16(gallivm, val+2));
2007 break;
2008
2009 case V_028714_SPI_SHADER_SNORM16_ABGR:
2010 for (chan = 0; chan < 4; chan++) {
2011 /* Clamp between [-1, 1]. */
2012 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2013 values[chan],
2014 lp_build_const_float(gallivm, 1));
2015 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2016 val[chan],
2017 lp_build_const_float(gallivm, -1));
2018 /* Convert to a signed integer in [-32767, 32767]. */
2019 val[chan] = LLVMBuildFMul(builder, val[chan],
2020 lp_build_const_float(gallivm, 32767), "");
2021 /* If positive, add 0.5, else add -0.5. */
2022 val[chan] = LLVMBuildFAdd(builder, val[chan],
2023 LLVMBuildSelect(builder,
2024 LLVMBuildFCmp(builder, LLVMRealOGE,
2025 val[chan], base->zero, ""),
2026 lp_build_const_float(gallivm, 0.5),
2027 lp_build_const_float(gallivm, -0.5), ""), "");
2028 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2029 }
2030
2031 args[4] = uint->one; /* COMPR flag */
2032 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2033 si_llvm_pack_two_int32_as_int16(gallivm, val));
2034 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2035 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2036 break;
2037
2038 case V_028714_SPI_SHADER_UINT16_ABGR: {
2039 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2040 255 : 65535);
2041 /* Clamp. */
2042 for (chan = 0; chan < 4; chan++) {
2043 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2044 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2045 val[chan], max);
2046 }
2047
2048 args[4] = uint->one; /* COMPR flag */
2049 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2050 si_llvm_pack_two_int16(gallivm, val));
2051 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2052 si_llvm_pack_two_int16(gallivm, val+2));
2053 break;
2054 }
2055
2056 case V_028714_SPI_SHADER_SINT16_ABGR: {
2057 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2058 127 : 32767);
2059 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2060 -128 : -32768);
2061 /* Clamp. */
2062 for (chan = 0; chan < 4; chan++) {
2063 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2064 val[chan] = lp_build_emit_llvm_binary(bld_base,
2065 TGSI_OPCODE_IMIN,
2066 val[chan], max);
2067 val[chan] = lp_build_emit_llvm_binary(bld_base,
2068 TGSI_OPCODE_IMAX,
2069 val[chan], min);
2070 }
2071
2072 args[4] = uint->one; /* COMPR flag */
2073 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2074 si_llvm_pack_two_int32_as_int16(gallivm, val));
2075 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2076 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2077 break;
2078 }
2079
2080 case V_028714_SPI_SHADER_32_ABGR:
2081 memcpy(&args[5], values, sizeof(values[0]) * 4);
2082 break;
2083 }
2084 }
2085
2086 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2087 LLVMValueRef alpha)
2088 {
2089 struct si_shader_context *ctx = si_shader_context(bld_base);
2090 struct gallivm_state *gallivm = bld_base->base.gallivm;
2091
2092 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2093 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2094 SI_PARAM_ALPHA_REF);
2095
2096 LLVMValueRef alpha_pass =
2097 lp_build_cmp(&bld_base->base,
2098 ctx->shader->key.ps.epilog.alpha_func,
2099 alpha, alpha_ref);
2100 LLVMValueRef arg =
2101 lp_build_select(&bld_base->base,
2102 alpha_pass,
2103 lp_build_const_float(gallivm, 1.0f),
2104 lp_build_const_float(gallivm, -1.0f));
2105
2106 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2107 ctx->voidt, &arg, 1, 0);
2108 } else {
2109 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2110 ctx->voidt, NULL, 0, 0);
2111 }
2112 }
2113
2114 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2115 LLVMValueRef alpha,
2116 unsigned samplemask_param)
2117 {
2118 struct si_shader_context *ctx = si_shader_context(bld_base);
2119 struct gallivm_state *gallivm = bld_base->base.gallivm;
2120 LLVMValueRef coverage;
2121
2122 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2123 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2124 samplemask_param);
2125 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2126
2127 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2128 ctx->i32,
2129 &coverage, 1, LLVMReadNoneAttribute);
2130
2131 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2132 ctx->f32, "");
2133
2134 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2135 lp_build_const_float(gallivm,
2136 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2137
2138 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2139 }
2140
2141 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2142 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2143 {
2144 struct si_shader_context *ctx = si_shader_context(bld_base);
2145 struct lp_build_context *base = &bld_base->base;
2146 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2147 unsigned reg_index;
2148 unsigned chan;
2149 unsigned const_chan;
2150 LLVMValueRef base_elt;
2151 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2152 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2153 SI_VS_CONST_CLIP_PLANES);
2154 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2155
2156 for (reg_index = 0; reg_index < 2; reg_index ++) {
2157 LLVMValueRef *args = pos[2 + reg_index];
2158
2159 args[5] =
2160 args[6] =
2161 args[7] =
2162 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2163
2164 /* Compute dot products of position and user clip plane vectors */
2165 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2166 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2167 args[1] = lp_build_const_int32(base->gallivm,
2168 ((reg_index * 4 + chan) * 4 +
2169 const_chan) * 4);
2170 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
2171 args[1], ctx->f32);
2172 args[5 + chan] =
2173 lp_build_add(base, args[5 + chan],
2174 lp_build_mul(base, base_elt,
2175 out_elts[const_chan]));
2176 }
2177 }
2178
2179 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2180 args[1] = uint->zero;
2181 args[2] = uint->zero;
2182 args[3] = lp_build_const_int32(base->gallivm,
2183 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2184 args[4] = uint->zero;
2185 }
2186 }
2187
2188 static void si_dump_streamout(struct pipe_stream_output_info *so)
2189 {
2190 unsigned i;
2191
2192 if (so->num_outputs)
2193 fprintf(stderr, "STREAMOUT\n");
2194
2195 for (i = 0; i < so->num_outputs; i++) {
2196 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2197 so->output[i].start_component;
2198 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2199 i, so->output[i].output_buffer,
2200 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2201 so->output[i].register_index,
2202 mask & 1 ? "x" : "",
2203 mask & 2 ? "y" : "",
2204 mask & 4 ? "z" : "",
2205 mask & 8 ? "w" : "");
2206 }
2207 }
2208
2209 /* On SI, the vertex shader is responsible for writing streamout data
2210 * to buffers. */
2211 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2212 struct si_shader_output_values *outputs,
2213 unsigned noutput)
2214 {
2215 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2216 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2217 LLVMBuilderRef builder = gallivm->builder;
2218 int i, j;
2219 struct lp_build_if_state if_ctx;
2220
2221 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2222 LLVMValueRef so_vtx_count =
2223 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2224
2225 LLVMValueRef tid = get_thread_id(ctx);
2226
2227 /* can_emit = tid < so_vtx_count; */
2228 LLVMValueRef can_emit =
2229 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2230
2231 LLVMValueRef stream_id =
2232 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2233
2234 /* Emit the streamout code conditionally. This actually avoids
2235 * out-of-bounds buffer access. The hw tells us via the SGPR
2236 * (so_vtx_count) which threads are allowed to emit streamout data. */
2237 lp_build_if(&if_ctx, gallivm, can_emit);
2238 {
2239 /* The buffer offset is computed as follows:
2240 * ByteOffset = streamout_offset[buffer_id]*4 +
2241 * (streamout_write_index + thread_id)*stride[buffer_id] +
2242 * attrib_offset
2243 */
2244
2245 LLVMValueRef so_write_index =
2246 LLVMGetParam(ctx->radeon_bld.main_fn,
2247 ctx->param_streamout_write_index);
2248
2249 /* Compute (streamout_write_index + thread_id). */
2250 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2251
2252 /* Compute the write offset for each enabled buffer. */
2253 LLVMValueRef so_write_offset[4] = {};
2254 for (i = 0; i < 4; i++) {
2255 if (!so->stride[i])
2256 continue;
2257
2258 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2259 ctx->param_streamout_offset[i]);
2260 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2261
2262 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2263 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2264 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2265 }
2266
2267 /* Write streamout data. */
2268 for (i = 0; i < so->num_outputs; i++) {
2269 unsigned buf_idx = so->output[i].output_buffer;
2270 unsigned reg = so->output[i].register_index;
2271 unsigned start = so->output[i].start_component;
2272 unsigned num_comps = so->output[i].num_components;
2273 unsigned stream = so->output[i].stream;
2274 LLVMValueRef out[4];
2275 struct lp_build_if_state if_ctx_stream;
2276
2277 assert(num_comps && num_comps <= 4);
2278 if (!num_comps || num_comps > 4)
2279 continue;
2280
2281 if (reg >= noutput)
2282 continue;
2283
2284 /* Load the output as int. */
2285 for (j = 0; j < num_comps; j++) {
2286 out[j] = LLVMBuildBitCast(builder,
2287 outputs[reg].values[start+j],
2288 ctx->i32, "");
2289 }
2290
2291 /* Pack the output. */
2292 LLVMValueRef vdata = NULL;
2293
2294 switch (num_comps) {
2295 case 1: /* as i32 */
2296 vdata = out[0];
2297 break;
2298 case 2: /* as v2i32 */
2299 case 3: /* as v4i32 (aligned to 4) */
2300 case 4: /* as v4i32 */
2301 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2302 for (j = 0; j < num_comps; j++) {
2303 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2304 LLVMConstInt(ctx->i32, j, 0), "");
2305 }
2306 break;
2307 }
2308
2309 LLVMValueRef can_emit_stream =
2310 LLVMBuildICmp(builder, LLVMIntEQ,
2311 stream_id,
2312 lp_build_const_int32(gallivm, stream), "");
2313
2314 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2315 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
2316 vdata, num_comps,
2317 so_write_offset[buf_idx],
2318 LLVMConstInt(ctx->i32, 0, 0),
2319 so->output[i].dst_offset*4);
2320 lp_build_endif(&if_ctx_stream);
2321 }
2322 }
2323 lp_build_endif(&if_ctx);
2324 }
2325
2326
2327 /* Generate export instructions for hardware VS shader stage */
2328 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2329 struct si_shader_output_values *outputs,
2330 unsigned noutput)
2331 {
2332 struct si_shader_context *ctx = si_shader_context(bld_base);
2333 struct si_shader *shader = ctx->shader;
2334 struct lp_build_context *base = &bld_base->base;
2335 struct lp_build_context *uint =
2336 &ctx->radeon_bld.soa.bld_base.uint_bld;
2337 LLVMValueRef args[9];
2338 LLVMValueRef pos_args[4][9] = { { 0 } };
2339 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2340 unsigned semantic_name, semantic_index;
2341 unsigned target;
2342 unsigned param_count = 0;
2343 unsigned pos_idx;
2344 int i;
2345
2346 if (outputs && ctx->shader->selector->so.num_outputs) {
2347 si_llvm_emit_streamout(ctx, outputs, noutput);
2348 }
2349
2350 for (i = 0; i < noutput; i++) {
2351 semantic_name = outputs[i].name;
2352 semantic_index = outputs[i].sid;
2353
2354 handle_semantic:
2355 /* Select the correct target */
2356 switch(semantic_name) {
2357 case TGSI_SEMANTIC_PSIZE:
2358 psize_value = outputs[i].values[0];
2359 continue;
2360 case TGSI_SEMANTIC_EDGEFLAG:
2361 edgeflag_value = outputs[i].values[0];
2362 continue;
2363 case TGSI_SEMANTIC_LAYER:
2364 layer_value = outputs[i].values[0];
2365 semantic_name = TGSI_SEMANTIC_GENERIC;
2366 goto handle_semantic;
2367 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2368 viewport_index_value = outputs[i].values[0];
2369 semantic_name = TGSI_SEMANTIC_GENERIC;
2370 goto handle_semantic;
2371 case TGSI_SEMANTIC_POSITION:
2372 target = V_008DFC_SQ_EXP_POS;
2373 break;
2374 case TGSI_SEMANTIC_COLOR:
2375 case TGSI_SEMANTIC_BCOLOR:
2376 target = V_008DFC_SQ_EXP_PARAM + param_count;
2377 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2378 shader->info.vs_output_param_offset[i] = param_count;
2379 param_count++;
2380 break;
2381 case TGSI_SEMANTIC_CLIPDIST:
2382 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2383 break;
2384 case TGSI_SEMANTIC_CLIPVERTEX:
2385 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2386 continue;
2387 case TGSI_SEMANTIC_PRIMID:
2388 case TGSI_SEMANTIC_FOG:
2389 case TGSI_SEMANTIC_TEXCOORD:
2390 case TGSI_SEMANTIC_GENERIC:
2391 target = V_008DFC_SQ_EXP_PARAM + param_count;
2392 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2393 shader->info.vs_output_param_offset[i] = param_count;
2394 param_count++;
2395 break;
2396 default:
2397 target = 0;
2398 fprintf(stderr,
2399 "Warning: SI unhandled vs output type:%d\n",
2400 semantic_name);
2401 }
2402
2403 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2404
2405 if (target >= V_008DFC_SQ_EXP_POS &&
2406 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2407 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2408 args, sizeof(args));
2409 } else {
2410 lp_build_intrinsic(base->gallivm->builder,
2411 "llvm.SI.export", ctx->voidt,
2412 args, 9, 0);
2413 }
2414
2415 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2416 semantic_name = TGSI_SEMANTIC_GENERIC;
2417 goto handle_semantic;
2418 }
2419 }
2420
2421 shader->info.nr_param_exports = param_count;
2422
2423 /* We need to add the position output manually if it's missing. */
2424 if (!pos_args[0][0]) {
2425 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2426 pos_args[0][1] = uint->zero; /* EXEC mask */
2427 pos_args[0][2] = uint->zero; /* last export? */
2428 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2429 pos_args[0][4] = uint->zero; /* COMPR flag */
2430 pos_args[0][5] = base->zero; /* X */
2431 pos_args[0][6] = base->zero; /* Y */
2432 pos_args[0][7] = base->zero; /* Z */
2433 pos_args[0][8] = base->one; /* W */
2434 }
2435
2436 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2437 if (shader->selector->info.writes_psize ||
2438 shader->selector->info.writes_edgeflag ||
2439 shader->selector->info.writes_viewport_index ||
2440 shader->selector->info.writes_layer) {
2441 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2442 shader->selector->info.writes_psize |
2443 (shader->selector->info.writes_edgeflag << 1) |
2444 (shader->selector->info.writes_layer << 2) |
2445 (shader->selector->info.writes_viewport_index << 3));
2446 pos_args[1][1] = uint->zero; /* EXEC mask */
2447 pos_args[1][2] = uint->zero; /* last export? */
2448 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2449 pos_args[1][4] = uint->zero; /* COMPR flag */
2450 pos_args[1][5] = base->zero; /* X */
2451 pos_args[1][6] = base->zero; /* Y */
2452 pos_args[1][7] = base->zero; /* Z */
2453 pos_args[1][8] = base->zero; /* W */
2454
2455 if (shader->selector->info.writes_psize)
2456 pos_args[1][5] = psize_value;
2457
2458 if (shader->selector->info.writes_edgeflag) {
2459 /* The output is a float, but the hw expects an integer
2460 * with the first bit containing the edge flag. */
2461 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2462 edgeflag_value,
2463 ctx->i32, "");
2464 edgeflag_value = lp_build_min(&bld_base->int_bld,
2465 edgeflag_value,
2466 bld_base->int_bld.one);
2467
2468 /* The LLVM intrinsic expects a float. */
2469 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2470 edgeflag_value,
2471 ctx->f32, "");
2472 }
2473
2474 if (shader->selector->info.writes_layer)
2475 pos_args[1][7] = layer_value;
2476
2477 if (shader->selector->info.writes_viewport_index)
2478 pos_args[1][8] = viewport_index_value;
2479 }
2480
2481 for (i = 0; i < 4; i++)
2482 if (pos_args[i][0])
2483 shader->info.nr_pos_exports++;
2484
2485 pos_idx = 0;
2486 for (i = 0; i < 4; i++) {
2487 if (!pos_args[i][0])
2488 continue;
2489
2490 /* Specify the target we are exporting */
2491 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2492
2493 if (pos_idx == shader->info.nr_pos_exports)
2494 /* Specify that this is the last export */
2495 pos_args[i][2] = uint->one;
2496
2497 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2498 ctx->voidt, pos_args[i], 9, 0);
2499 }
2500 }
2501
2502 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2503 {
2504 struct si_shader_context *ctx = si_shader_context(bld_base);
2505 struct gallivm_state *gallivm = bld_base->base.gallivm;
2506 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2507 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2508 uint64_t inputs;
2509
2510 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2511
2512 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2513 buffer = build_indexed_load_const(ctx, rw_buffers,
2514 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2515
2516 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2517
2518 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2519 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2520 lds_vertex_stride, "");
2521 lds_base = get_tcs_in_current_patch_offset(ctx);
2522 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2523
2524 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2525 while (inputs) {
2526 unsigned i = u_bit_scan64(&inputs);
2527
2528 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2529 lp_build_const_int32(gallivm, 4 * i),
2530 "");
2531
2532 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2533 invocation_id,
2534 lp_build_const_int32(gallivm, i));
2535
2536 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2537 lds_ptr);
2538
2539 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2540 buffer_offset, 0);
2541 }
2542 }
2543
2544 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2545 LLVMValueRef rel_patch_id,
2546 LLVMValueRef invocation_id,
2547 LLVMValueRef tcs_out_current_patch_data_offset)
2548 {
2549 struct si_shader_context *ctx = si_shader_context(bld_base);
2550 struct gallivm_state *gallivm = bld_base->base.gallivm;
2551 struct si_shader *shader = ctx->shader;
2552 unsigned tess_inner_index, tess_outer_index;
2553 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2554 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2555 unsigned stride, outer_comps, inner_comps, i;
2556 struct lp_build_if_state if_ctx, inner_if_ctx;
2557
2558 si_llvm_emit_barrier(NULL, bld_base, NULL);
2559
2560 /* Do this only for invocation 0, because the tess levels are per-patch,
2561 * not per-vertex.
2562 *
2563 * This can't jump, because invocation 0 executes this. It should
2564 * at least mask out the loads and stores for other invocations.
2565 */
2566 lp_build_if(&if_ctx, gallivm,
2567 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2568 invocation_id, bld_base->uint_bld.zero, ""));
2569
2570 /* Determine the layout of one tess factor element in the buffer. */
2571 switch (shader->key.tcs.epilog.prim_mode) {
2572 case PIPE_PRIM_LINES:
2573 stride = 2; /* 2 dwords, 1 vec2 store */
2574 outer_comps = 2;
2575 inner_comps = 0;
2576 break;
2577 case PIPE_PRIM_TRIANGLES:
2578 stride = 4; /* 4 dwords, 1 vec4 store */
2579 outer_comps = 3;
2580 inner_comps = 1;
2581 break;
2582 case PIPE_PRIM_QUADS:
2583 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2584 outer_comps = 4;
2585 inner_comps = 2;
2586 break;
2587 default:
2588 assert(0);
2589 return;
2590 }
2591
2592 /* Load tess_inner and tess_outer from LDS.
2593 * Any invocation can write them, so we can't get them from a temporary.
2594 */
2595 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2596 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2597
2598 lds_base = tcs_out_current_patch_data_offset;
2599 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2600 lp_build_const_int32(gallivm,
2601 tess_inner_index * 4), "");
2602 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2603 lp_build_const_int32(gallivm,
2604 tess_outer_index * 4), "");
2605
2606 for (i = 0; i < outer_comps; i++)
2607 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2608 for (i = 0; i < inner_comps; i++)
2609 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2610
2611 /* Convert the outputs to vectors for stores. */
2612 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2613 vec1 = NULL;
2614
2615 if (stride > 4)
2616 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2617
2618 /* Get the buffer. */
2619 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2620 SI_PARAM_RW_BUFFERS);
2621 buffer = build_indexed_load_const(ctx, rw_buffers,
2622 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2623
2624 /* Get the offset. */
2625 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2626 SI_PARAM_TESS_FACTOR_OFFSET);
2627 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2628 lp_build_const_int32(gallivm, 4 * stride), "");
2629
2630 lp_build_if(&inner_if_ctx, gallivm,
2631 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2632 rel_patch_id, bld_base->uint_bld.zero, ""));
2633
2634 /* Store the dynamic HS control word. */
2635 build_tbuffer_store_dwords(ctx, buffer,
2636 lp_build_const_int32(gallivm, 0x80000000),
2637 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2638
2639 lp_build_endif(&inner_if_ctx);
2640
2641 /* Store the tessellation factors. */
2642 build_tbuffer_store_dwords(ctx, buffer, vec0,
2643 MIN2(stride, 4), byteoffset, tf_base, 4);
2644 if (vec1)
2645 build_tbuffer_store_dwords(ctx, buffer, vec1,
2646 stride - 4, byteoffset, tf_base, 20);
2647 lp_build_endif(&if_ctx);
2648 }
2649
2650 /* This only writes the tessellation factor levels. */
2651 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2652 {
2653 struct si_shader_context *ctx = si_shader_context(bld_base);
2654 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2655
2656 rel_patch_id = get_rel_patch_id(ctx);
2657 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2658 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2659
2660 if (!ctx->is_monolithic) {
2661 /* Return epilog parameters from this function. */
2662 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2663 LLVMValueRef ret = ctx->return_value;
2664 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2665 unsigned vgpr;
2666
2667 /* RW_BUFFERS pointer */
2668 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2669 SI_PARAM_RW_BUFFERS);
2670 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2671 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2672 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2673 bld_base->uint_bld.zero, "");
2674 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2675 bld_base->uint_bld.one, "");
2676 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2677 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2678
2679 /* Tess factor buffer soffset is after user SGPRs. */
2680 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2681 SI_PARAM_TESS_FACTOR_OFFSET);
2682 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2683 SI_TCS_NUM_USER_SGPR + 1, "");
2684
2685 /* VGPRs */
2686 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2687 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2688 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2689
2690 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2691 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2692 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2693 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2694 ctx->return_value = ret;
2695 return;
2696 }
2697
2698 si_copy_tcs_inputs(bld_base);
2699 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2700 }
2701
2702 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2703 {
2704 struct si_shader_context *ctx = si_shader_context(bld_base);
2705 struct si_shader *shader = ctx->shader;
2706 struct tgsi_shader_info *info = &shader->selector->info;
2707 struct gallivm_state *gallivm = bld_base->base.gallivm;
2708 unsigned i, chan;
2709 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2710 ctx->param_rel_auto_id);
2711 LLVMValueRef vertex_dw_stride =
2712 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2713 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2714 vertex_dw_stride, "");
2715
2716 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2717 * its inputs from it. */
2718 for (i = 0; i < info->num_outputs; i++) {
2719 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2720 unsigned name = info->output_semantic_name[i];
2721 unsigned index = info->output_semantic_index[i];
2722 int param = si_shader_io_get_unique_index(name, index);
2723 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2724 lp_build_const_int32(gallivm, param * 4), "");
2725
2726 for (chan = 0; chan < 4; chan++) {
2727 lds_store(bld_base, chan, dw_addr,
2728 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2729 }
2730 }
2731 }
2732
2733 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2734 {
2735 struct si_shader_context *ctx = si_shader_context(bld_base);
2736 struct gallivm_state *gallivm = bld_base->base.gallivm;
2737 struct si_shader *es = ctx->shader;
2738 struct tgsi_shader_info *info = &es->selector->info;
2739 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2740 ctx->param_es2gs_offset);
2741 unsigned chan;
2742 int i;
2743
2744 for (i = 0; i < info->num_outputs; i++) {
2745 LLVMValueRef *out_ptr =
2746 ctx->radeon_bld.soa.outputs[i];
2747 int param_index;
2748
2749 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2750 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2751 continue;
2752
2753 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2754 info->output_semantic_index[i]);
2755
2756 for (chan = 0; chan < 4; chan++) {
2757 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2758 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2759
2760 build_tbuffer_store(ctx,
2761 ctx->esgs_ring,
2762 out_val, 1,
2763 LLVMGetUndef(ctx->i32), soffset,
2764 (4 * param_index + chan) * 4,
2765 V_008F0C_BUF_DATA_FORMAT_32,
2766 V_008F0C_BUF_NUM_FORMAT_UINT,
2767 0, 0, 1, 1, 0);
2768 }
2769 }
2770 }
2771
2772 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2773 {
2774 struct si_shader_context *ctx = si_shader_context(bld_base);
2775 struct gallivm_state *gallivm = bld_base->base.gallivm;
2776 LLVMValueRef args[2];
2777
2778 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2779 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2780 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2781 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2782 }
2783
2784 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2785 {
2786 struct si_shader_context *ctx = si_shader_context(bld_base);
2787 struct gallivm_state *gallivm = bld_base->base.gallivm;
2788 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2789 struct si_shader_output_values *outputs = NULL;
2790 int i,j;
2791
2792 assert(!ctx->is_gs_copy_shader);
2793
2794 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2795
2796 /* Vertex color clamping.
2797 *
2798 * This uses a state constant loaded in a user data SGPR and
2799 * an IF statement is added that clamps all colors if the constant
2800 * is true.
2801 */
2802 if (ctx->type == PIPE_SHADER_VERTEX) {
2803 struct lp_build_if_state if_ctx;
2804 LLVMValueRef cond = NULL;
2805 LLVMValueRef addr, val;
2806
2807 for (i = 0; i < info->num_outputs; i++) {
2808 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2809 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2810 continue;
2811
2812 /* We've found a color. */
2813 if (!cond) {
2814 /* The state is in the first bit of the user SGPR. */
2815 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2816 SI_PARAM_VS_STATE_BITS);
2817 cond = LLVMBuildTrunc(gallivm->builder, cond,
2818 ctx->i1, "");
2819 lp_build_if(&if_ctx, gallivm, cond);
2820 }
2821
2822 for (j = 0; j < 4; j++) {
2823 addr = ctx->radeon_bld.soa.outputs[i][j];
2824 val = LLVMBuildLoad(gallivm->builder, addr, "");
2825 val = radeon_llvm_saturate(bld_base, val);
2826 LLVMBuildStore(gallivm->builder, val, addr);
2827 }
2828 }
2829
2830 if (cond)
2831 lp_build_endif(&if_ctx);
2832 }
2833
2834 for (i = 0; i < info->num_outputs; i++) {
2835 outputs[i].name = info->output_semantic_name[i];
2836 outputs[i].sid = info->output_semantic_index[i];
2837
2838 for (j = 0; j < 4; j++)
2839 outputs[i].values[j] =
2840 LLVMBuildLoad(gallivm->builder,
2841 ctx->radeon_bld.soa.outputs[i][j],
2842 "");
2843 }
2844
2845 if (ctx->is_monolithic) {
2846 /* Export PrimitiveID when PS needs it. */
2847 if (si_vs_exports_prim_id(ctx->shader)) {
2848 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2849 outputs[i].sid = 0;
2850 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2851 get_primitive_id(bld_base, 0));
2852 outputs[i].values[1] = bld_base->base.undef;
2853 outputs[i].values[2] = bld_base->base.undef;
2854 outputs[i].values[3] = bld_base->base.undef;
2855 i++;
2856 }
2857 } else {
2858 /* Return the primitive ID from the LLVM function. */
2859 ctx->return_value =
2860 LLVMBuildInsertValue(gallivm->builder,
2861 ctx->return_value,
2862 bitcast(bld_base, TGSI_TYPE_FLOAT,
2863 get_primitive_id(bld_base, 0)),
2864 VS_EPILOG_PRIMID_LOC, "");
2865 }
2866
2867 si_llvm_export_vs(bld_base, outputs, i);
2868 FREE(outputs);
2869 }
2870
2871 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2872 LLVMValueRef depth, LLVMValueRef stencil,
2873 LLVMValueRef samplemask)
2874 {
2875 struct si_shader_context *ctx = si_shader_context(bld_base);
2876 struct lp_build_context *base = &bld_base->base;
2877 struct lp_build_context *uint = &bld_base->uint_bld;
2878 LLVMValueRef args[9];
2879 unsigned mask = 0;
2880
2881 assert(depth || stencil || samplemask);
2882
2883 args[1] = uint->one; /* whether the EXEC mask is valid */
2884 args[2] = uint->one; /* DONE bit */
2885
2886 /* Specify the target we are exporting */
2887 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2888
2889 args[4] = uint->zero; /* COMP flag */
2890 args[5] = base->undef; /* R, depth */
2891 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2892 args[7] = base->undef; /* B, sample mask */
2893 args[8] = base->undef; /* A, alpha to mask */
2894
2895 if (depth) {
2896 args[5] = depth;
2897 mask |= 0x1;
2898 }
2899
2900 if (stencil) {
2901 args[6] = stencil;
2902 mask |= 0x2;
2903 }
2904
2905 if (samplemask) {
2906 args[7] = samplemask;
2907 mask |= 0x4;
2908 }
2909
2910 /* SI (except OLAND) has a bug that it only looks
2911 * at the X writemask component. */
2912 if (ctx->screen->b.chip_class == SI &&
2913 ctx->screen->b.family != CHIP_OLAND)
2914 mask |= 0x1;
2915
2916 /* Specify which components to enable */
2917 args[0] = lp_build_const_int32(base->gallivm, mask);
2918
2919 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2920 ctx->voidt, args, 9, 0);
2921 }
2922
2923 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2924 LLVMValueRef *color, unsigned index,
2925 unsigned samplemask_param,
2926 bool is_last)
2927 {
2928 struct si_shader_context *ctx = si_shader_context(bld_base);
2929 struct lp_build_context *base = &bld_base->base;
2930 int i;
2931
2932 /* Clamp color */
2933 if (ctx->shader->key.ps.epilog.clamp_color)
2934 for (i = 0; i < 4; i++)
2935 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2936
2937 /* Alpha to one */
2938 if (ctx->shader->key.ps.epilog.alpha_to_one)
2939 color[3] = base->one;
2940
2941 /* Alpha test */
2942 if (index == 0 &&
2943 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2944 si_alpha_test(bld_base, color[3]);
2945
2946 /* Line & polygon smoothing */
2947 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2948 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2949 samplemask_param);
2950
2951 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2952 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2953 LLVMValueRef args[8][9];
2954 int c, last = -1;
2955
2956 /* Get the export arguments, also find out what the last one is. */
2957 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2958 si_llvm_init_export_args(bld_base, color,
2959 V_008DFC_SQ_EXP_MRT + c, args[c]);
2960 if (args[c][0] != bld_base->uint_bld.zero)
2961 last = c;
2962 }
2963
2964 /* Emit all exports. */
2965 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2966 if (is_last && last == c) {
2967 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2968 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2969 } else if (args[c][0] == bld_base->uint_bld.zero)
2970 continue; /* unnecessary NULL export */
2971
2972 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2973 ctx->voidt, args[c], 9, 0);
2974 }
2975 } else {
2976 LLVMValueRef args[9];
2977
2978 /* Export */
2979 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2980 args);
2981 if (is_last) {
2982 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2983 args[2] = bld_base->uint_bld.one; /* DONE bit */
2984 } else if (args[0] == bld_base->uint_bld.zero)
2985 return; /* unnecessary NULL export */
2986
2987 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2988 ctx->voidt, args, 9, 0);
2989 }
2990 }
2991
2992 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2993 {
2994 struct si_shader_context *ctx = si_shader_context(bld_base);
2995 struct lp_build_context *base = &bld_base->base;
2996 struct lp_build_context *uint = &bld_base->uint_bld;
2997 LLVMValueRef args[9];
2998
2999 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3000 args[1] = uint->one; /* whether the EXEC mask is valid */
3001 args[2] = uint->one; /* DONE bit */
3002 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3003 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3004 args[5] = uint->undef; /* R */
3005 args[6] = uint->undef; /* G */
3006 args[7] = uint->undef; /* B */
3007 args[8] = uint->undef; /* A */
3008
3009 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3010 ctx->voidt, args, 9, 0);
3011 }
3012
3013 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3014 {
3015 struct si_shader_context *ctx = si_shader_context(bld_base);
3016 struct si_shader *shader = ctx->shader;
3017 struct lp_build_context *base = &bld_base->base;
3018 struct tgsi_shader_info *info = &shader->selector->info;
3019 LLVMBuilderRef builder = base->gallivm->builder;
3020 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3021 int last_color_export = -1;
3022 int i;
3023
3024 /* Determine the last export. If MRTZ is present, it's always last.
3025 * Otherwise, find the last color export.
3026 */
3027 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3028 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3029
3030 /* Don't export NULL and return if alpha-test is enabled. */
3031 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3032 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3033 (spi_format & 0xf) == 0)
3034 spi_format |= V_028714_SPI_SHADER_32_AR;
3035
3036 for (i = 0; i < info->num_outputs; i++) {
3037 unsigned index = info->output_semantic_index[i];
3038
3039 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3040 continue;
3041
3042 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3043 if (shader->key.ps.epilog.last_cbuf > 0) {
3044 /* Just set this if any of the colorbuffers are enabled. */
3045 if (spi_format &
3046 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3047 last_color_export = i;
3048 continue;
3049 }
3050
3051 if ((spi_format >> (index * 4)) & 0xf)
3052 last_color_export = i;
3053 }
3054
3055 /* If there are no outputs, export NULL. */
3056 if (last_color_export == -1) {
3057 si_export_null(bld_base);
3058 return;
3059 }
3060 }
3061
3062 for (i = 0; i < info->num_outputs; i++) {
3063 unsigned semantic_name = info->output_semantic_name[i];
3064 unsigned semantic_index = info->output_semantic_index[i];
3065 unsigned j;
3066 LLVMValueRef color[4] = {};
3067
3068 /* Select the correct target */
3069 switch (semantic_name) {
3070 case TGSI_SEMANTIC_POSITION:
3071 depth = LLVMBuildLoad(builder,
3072 ctx->radeon_bld.soa.outputs[i][2], "");
3073 break;
3074 case TGSI_SEMANTIC_STENCIL:
3075 stencil = LLVMBuildLoad(builder,
3076 ctx->radeon_bld.soa.outputs[i][1], "");
3077 break;
3078 case TGSI_SEMANTIC_SAMPLEMASK:
3079 samplemask = LLVMBuildLoad(builder,
3080 ctx->radeon_bld.soa.outputs[i][0], "");
3081 break;
3082 case TGSI_SEMANTIC_COLOR:
3083 for (j = 0; j < 4; j++)
3084 color[j] = LLVMBuildLoad(builder,
3085 ctx->radeon_bld.soa.outputs[i][j], "");
3086
3087 si_export_mrt_color(bld_base, color, semantic_index,
3088 SI_PARAM_SAMPLE_COVERAGE,
3089 last_color_export == i);
3090 break;
3091 default:
3092 fprintf(stderr,
3093 "Warning: SI unhandled fs output type:%d\n",
3094 semantic_name);
3095 }
3096 }
3097
3098 if (depth || stencil || samplemask)
3099 si_export_mrt_z(bld_base, depth, stencil, samplemask);
3100 }
3101
3102 /**
3103 * Return PS outputs in this order:
3104 *
3105 * v[0:3] = color0.xyzw
3106 * v[4:7] = color1.xyzw
3107 * ...
3108 * vN+0 = Depth
3109 * vN+1 = Stencil
3110 * vN+2 = SampleMask
3111 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3112 *
3113 * The alpha-ref SGPR is returned via its original location.
3114 */
3115 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3116 {
3117 struct si_shader_context *ctx = si_shader_context(bld_base);
3118 struct si_shader *shader = ctx->shader;
3119 struct lp_build_context *base = &bld_base->base;
3120 struct tgsi_shader_info *info = &shader->selector->info;
3121 LLVMBuilderRef builder = base->gallivm->builder;
3122 unsigned i, j, first_vgpr, vgpr;
3123
3124 LLVMValueRef color[8][4] = {};
3125 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3126 LLVMValueRef ret;
3127
3128 /* Read the output values. */
3129 for (i = 0; i < info->num_outputs; i++) {
3130 unsigned semantic_name = info->output_semantic_name[i];
3131 unsigned semantic_index = info->output_semantic_index[i];
3132
3133 switch (semantic_name) {
3134 case TGSI_SEMANTIC_COLOR:
3135 assert(semantic_index < 8);
3136 for (j = 0; j < 4; j++) {
3137 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3138 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3139 color[semantic_index][j] = result;
3140 }
3141 break;
3142 case TGSI_SEMANTIC_POSITION:
3143 depth = LLVMBuildLoad(builder,
3144 ctx->radeon_bld.soa.outputs[i][2], "");
3145 break;
3146 case TGSI_SEMANTIC_STENCIL:
3147 stencil = LLVMBuildLoad(builder,
3148 ctx->radeon_bld.soa.outputs[i][1], "");
3149 break;
3150 case TGSI_SEMANTIC_SAMPLEMASK:
3151 samplemask = LLVMBuildLoad(builder,
3152 ctx->radeon_bld.soa.outputs[i][0], "");
3153 break;
3154 default:
3155 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3156 semantic_name);
3157 }
3158 }
3159
3160 /* Fill the return structure. */
3161 ret = ctx->return_value;
3162
3163 /* Set SGPRs. */
3164 ret = LLVMBuildInsertValue(builder, ret,
3165 bitcast(bld_base, TGSI_TYPE_SIGNED,
3166 LLVMGetParam(ctx->radeon_bld.main_fn,
3167 SI_PARAM_ALPHA_REF)),
3168 SI_SGPR_ALPHA_REF, "");
3169
3170 /* Set VGPRs */
3171 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3172 for (i = 0; i < ARRAY_SIZE(color); i++) {
3173 if (!color[i][0])
3174 continue;
3175
3176 for (j = 0; j < 4; j++)
3177 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3178 }
3179 if (depth)
3180 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3181 if (stencil)
3182 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3183 if (samplemask)
3184 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3185
3186 /* Add the input sample mask for smoothing at the end. */
3187 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3188 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3189 ret = LLVMBuildInsertValue(builder, ret,
3190 LLVMGetParam(ctx->radeon_bld.main_fn,
3191 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3192
3193 ctx->return_value = ret;
3194 }
3195
3196 /**
3197 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3198 * buffer in number of elements and return it as an i32.
3199 */
3200 static LLVMValueRef get_buffer_size(
3201 struct lp_build_tgsi_context *bld_base,
3202 LLVMValueRef descriptor)
3203 {
3204 struct si_shader_context *ctx = si_shader_context(bld_base);
3205 struct gallivm_state *gallivm = bld_base->base.gallivm;
3206 LLVMBuilderRef builder = gallivm->builder;
3207 LLVMValueRef size =
3208 LLVMBuildExtractElement(builder, descriptor,
3209 lp_build_const_int32(gallivm, 6), "");
3210
3211 if (ctx->screen->b.chip_class >= VI) {
3212 /* On VI, the descriptor contains the size in bytes,
3213 * but TXQ must return the size in elements.
3214 * The stride is always non-zero for resources using TXQ.
3215 */
3216 LLVMValueRef stride =
3217 LLVMBuildExtractElement(builder, descriptor,
3218 lp_build_const_int32(gallivm, 5), "");
3219 stride = LLVMBuildLShr(builder, stride,
3220 lp_build_const_int32(gallivm, 16), "");
3221 stride = LLVMBuildAnd(builder, stride,
3222 lp_build_const_int32(gallivm, 0x3FFF), "");
3223
3224 size = LLVMBuildUDiv(builder, size, stride, "");
3225 }
3226
3227 return size;
3228 }
3229
3230 /**
3231 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3232 * intrinsic names).
3233 */
3234 static void build_int_type_name(
3235 LLVMTypeRef type,
3236 char *buf, unsigned bufsize)
3237 {
3238 assert(bufsize >= 6);
3239
3240 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3241 snprintf(buf, bufsize, "v%ui32",
3242 LLVMGetVectorSize(type));
3243 else
3244 strcpy(buf, "i32");
3245 }
3246
3247 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3248 struct lp_build_tgsi_context *bld_base,
3249 struct lp_build_emit_data *emit_data);
3250
3251 /* Prevent optimizations (at least of memory accesses) across the current
3252 * point in the program by emitting empty inline assembly that is marked as
3253 * having side effects.
3254 */
3255 static void emit_optimization_barrier(struct si_shader_context *ctx)
3256 {
3257 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3258 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3259 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3260 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3261 }
3262
3263 static void emit_waitcnt(struct si_shader_context *ctx)
3264 {
3265 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3266 LLVMBuilderRef builder = gallivm->builder;
3267 LLVMValueRef args[1] = {
3268 lp_build_const_int32(gallivm, 0xf70)
3269 };
3270 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3271 ctx->voidt, args, 1, LLVMNoUnwindAttribute);
3272 }
3273
3274 static void membar_emit(
3275 const struct lp_build_tgsi_action *action,
3276 struct lp_build_tgsi_context *bld_base,
3277 struct lp_build_emit_data *emit_data)
3278 {
3279 struct si_shader_context *ctx = si_shader_context(bld_base);
3280
3281 emit_waitcnt(ctx);
3282 }
3283
3284 static LLVMValueRef
3285 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3286 const struct tgsi_full_src_register *reg)
3287 {
3288 LLVMValueRef ind_index;
3289 LLVMValueRef rsrc_ptr;
3290
3291 if (!reg->Register.Indirect)
3292 return ctx->shader_buffers[reg->Register.Index];
3293
3294 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3295 reg->Register.Index,
3296 SI_NUM_SHADER_BUFFERS);
3297
3298 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3299 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3300 }
3301
3302 static bool tgsi_is_array_sampler(unsigned target)
3303 {
3304 return target == TGSI_TEXTURE_1D_ARRAY ||
3305 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3306 target == TGSI_TEXTURE_2D_ARRAY ||
3307 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3308 target == TGSI_TEXTURE_CUBE_ARRAY ||
3309 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3310 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3311 }
3312
3313 static bool tgsi_is_array_image(unsigned target)
3314 {
3315 return target == TGSI_TEXTURE_3D ||
3316 target == TGSI_TEXTURE_CUBE ||
3317 target == TGSI_TEXTURE_1D_ARRAY ||
3318 target == TGSI_TEXTURE_2D_ARRAY ||
3319 target == TGSI_TEXTURE_CUBE_ARRAY ||
3320 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3321 }
3322
3323 /**
3324 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3325 *
3326 * At least on Tonga, executing image stores on images with DCC enabled and
3327 * non-trivial can eventually lead to lockups. This can occur when an
3328 * application binds an image as read-only but then uses a shader that writes
3329 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3330 * program termination) in this case, but it doesn't cost much to be a bit
3331 * nicer: disabling DCC in the shader still leads to undefined results but
3332 * avoids the lockup.
3333 */
3334 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3335 LLVMValueRef rsrc)
3336 {
3337 if (ctx->screen->b.chip_class <= CIK) {
3338 return rsrc;
3339 } else {
3340 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3341 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3342 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3343 LLVMValueRef tmp;
3344
3345 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3346 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3347 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3348 }
3349 }
3350
3351 /**
3352 * Load the resource descriptor for \p image.
3353 */
3354 static void
3355 image_fetch_rsrc(
3356 struct lp_build_tgsi_context *bld_base,
3357 const struct tgsi_full_src_register *image,
3358 bool dcc_off,
3359 LLVMValueRef *rsrc)
3360 {
3361 struct si_shader_context *ctx = si_shader_context(bld_base);
3362
3363 assert(image->Register.File == TGSI_FILE_IMAGE);
3364
3365 if (!image->Register.Indirect) {
3366 /* Fast path: use preloaded resources */
3367 *rsrc = ctx->images[image->Register.Index];
3368 } else {
3369 /* Indexing and manual load */
3370 LLVMValueRef ind_index;
3371 LLVMValueRef rsrc_ptr;
3372 LLVMValueRef tmp;
3373
3374 /* From the GL_ARB_shader_image_load_store extension spec:
3375 *
3376 * If a shader performs an image load, store, or atomic
3377 * operation using an image variable declared as an array,
3378 * and if the index used to select an individual element is
3379 * negative or greater than or equal to the size of the
3380 * array, the results of the operation are undefined but may
3381 * not lead to termination.
3382 */
3383 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3384 image->Register.Index,
3385 SI_NUM_IMAGES);
3386
3387 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3388 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3389 if (dcc_off)
3390 tmp = force_dcc_off(ctx, tmp);
3391 *rsrc = tmp;
3392 }
3393 }
3394
3395 static LLVMValueRef image_fetch_coords(
3396 struct lp_build_tgsi_context *bld_base,
3397 const struct tgsi_full_instruction *inst,
3398 unsigned src)
3399 {
3400 struct gallivm_state *gallivm = bld_base->base.gallivm;
3401 LLVMBuilderRef builder = gallivm->builder;
3402 unsigned target = inst->Memory.Texture;
3403 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3404 LLVMValueRef coords[4];
3405 LLVMValueRef tmp;
3406 int chan;
3407
3408 for (chan = 0; chan < num_coords; ++chan) {
3409 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3410 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3411 coords[chan] = tmp;
3412 }
3413
3414 if (num_coords == 1)
3415 return coords[0];
3416
3417 if (num_coords == 3) {
3418 /* LLVM has difficulties lowering 3-element vectors. */
3419 coords[3] = bld_base->uint_bld.undef;
3420 num_coords = 4;
3421 }
3422
3423 return lp_build_gather_values(gallivm, coords, num_coords);
3424 }
3425
3426 /**
3427 * Append the extra mode bits that are used by image load and store.
3428 */
3429 static void image_append_args(
3430 struct si_shader_context *ctx,
3431 struct lp_build_emit_data * emit_data,
3432 unsigned target,
3433 bool atomic)
3434 {
3435 const struct tgsi_full_instruction *inst = emit_data->inst;
3436 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3437 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3438
3439 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3440 emit_data->args[emit_data->arg_count++] =
3441 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3442 if (!atomic) {
3443 emit_data->args[emit_data->arg_count++] =
3444 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3445 i1true : i1false; /* glc */
3446 }
3447 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3448 }
3449
3450 /**
3451 * Given a 256 bit resource, extract the top half (which stores the buffer
3452 * resource in the case of textures and images).
3453 */
3454 static LLVMValueRef extract_rsrc_top_half(
3455 struct si_shader_context *ctx,
3456 LLVMValueRef rsrc)
3457 {
3458 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3459 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3460 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3461
3462 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3463 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3464 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3465
3466 return rsrc;
3467 }
3468
3469 /**
3470 * Append the resource and indexing arguments for buffer intrinsics.
3471 *
3472 * \param rsrc the v4i32 buffer resource
3473 * \param index index into the buffer (stride-based)
3474 * \param offset byte offset into the buffer
3475 */
3476 static void buffer_append_args(
3477 struct si_shader_context *ctx,
3478 struct lp_build_emit_data *emit_data,
3479 LLVMValueRef rsrc,
3480 LLVMValueRef index,
3481 LLVMValueRef offset,
3482 bool atomic)
3483 {
3484 const struct tgsi_full_instruction *inst = emit_data->inst;
3485 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3486 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3487
3488 emit_data->args[emit_data->arg_count++] = rsrc;
3489 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3490 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3491 if (!atomic) {
3492 emit_data->args[emit_data->arg_count++] =
3493 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3494 i1true : i1false; /* glc */
3495 }
3496 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3497 }
3498
3499 static void load_fetch_args(
3500 struct lp_build_tgsi_context * bld_base,
3501 struct lp_build_emit_data * emit_data)
3502 {
3503 struct si_shader_context *ctx = si_shader_context(bld_base);
3504 struct gallivm_state *gallivm = bld_base->base.gallivm;
3505 const struct tgsi_full_instruction * inst = emit_data->inst;
3506 unsigned target = inst->Memory.Texture;
3507 LLVMValueRef rsrc;
3508
3509 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3510
3511 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3512 LLVMBuilderRef builder = gallivm->builder;
3513 LLVMValueRef offset;
3514 LLVMValueRef tmp;
3515
3516 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3517
3518 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3519 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3520
3521 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3522 offset, false);
3523 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3524 LLVMValueRef coords;
3525
3526 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3527 coords = image_fetch_coords(bld_base, inst, 1);
3528
3529 if (target == TGSI_TEXTURE_BUFFER) {
3530 rsrc = extract_rsrc_top_half(ctx, rsrc);
3531 buffer_append_args(ctx, emit_data, rsrc, coords,
3532 bld_base->uint_bld.zero, false);
3533 } else {
3534 emit_data->args[0] = coords;
3535 emit_data->args[1] = rsrc;
3536 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3537 emit_data->arg_count = 3;
3538
3539 image_append_args(ctx, emit_data, target, false);
3540 }
3541 }
3542 }
3543
3544 static void load_emit_buffer(struct si_shader_context *ctx,
3545 struct lp_build_emit_data *emit_data)
3546 {
3547 const struct tgsi_full_instruction *inst = emit_data->inst;
3548 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3549 LLVMBuilderRef builder = gallivm->builder;
3550 uint writemask = inst->Dst[0].Register.WriteMask;
3551 uint count = util_last_bit(writemask);
3552 const char *intrinsic_name;
3553 LLVMTypeRef dst_type;
3554
3555 switch (count) {
3556 case 1:
3557 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3558 dst_type = ctx->f32;
3559 break;
3560 case 2:
3561 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3562 dst_type = LLVMVectorType(ctx->f32, 2);
3563 break;
3564 default: // 3 & 4
3565 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3566 dst_type = ctx->v4f32;
3567 count = 4;
3568 }
3569
3570 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3571 builder, intrinsic_name, dst_type,
3572 emit_data->args, emit_data->arg_count,
3573 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3574 }
3575
3576 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3577 const struct tgsi_full_instruction *inst,
3578 LLVMTypeRef type, int arg)
3579 {
3580 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3581 LLVMBuilderRef builder = gallivm->builder;
3582 LLVMValueRef offset, ptr;
3583 int addr_space;
3584
3585 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3586 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3587
3588 ptr = ctx->shared_memory;
3589 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3590 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3591 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3592
3593 return ptr;
3594 }
3595
3596 static void load_emit_memory(
3597 struct si_shader_context *ctx,
3598 struct lp_build_emit_data *emit_data)
3599 {
3600 const struct tgsi_full_instruction *inst = emit_data->inst;
3601 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3602 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3603 LLVMBuilderRef builder = gallivm->builder;
3604 unsigned writemask = inst->Dst[0].Register.WriteMask;
3605 LLVMValueRef channels[4], ptr, derived_ptr, index;
3606 int chan;
3607
3608 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3609
3610 for (chan = 0; chan < 4; ++chan) {
3611 if (!(writemask & (1 << chan))) {
3612 channels[chan] = LLVMGetUndef(base->elem_type);
3613 continue;
3614 }
3615
3616 index = lp_build_const_int32(gallivm, chan);
3617 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3618 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3619 }
3620 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3621 }
3622
3623 static void load_emit(
3624 const struct lp_build_tgsi_action *action,
3625 struct lp_build_tgsi_context *bld_base,
3626 struct lp_build_emit_data *emit_data)
3627 {
3628 struct si_shader_context *ctx = si_shader_context(bld_base);
3629 struct gallivm_state *gallivm = bld_base->base.gallivm;
3630 LLVMBuilderRef builder = gallivm->builder;
3631 const struct tgsi_full_instruction * inst = emit_data->inst;
3632 char intrinsic_name[32];
3633 char coords_type[8];
3634
3635 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3636 load_emit_memory(ctx, emit_data);
3637 return;
3638 }
3639
3640 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3641 emit_waitcnt(ctx);
3642
3643 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3644 load_emit_buffer(ctx, emit_data);
3645 return;
3646 }
3647
3648 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3649 emit_data->output[emit_data->chan] =
3650 lp_build_intrinsic(
3651 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3652 emit_data->args, emit_data->arg_count,
3653 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3654 } else {
3655 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3656 coords_type, sizeof(coords_type));
3657
3658 snprintf(intrinsic_name, sizeof(intrinsic_name),
3659 "llvm.amdgcn.image.load.%s", coords_type);
3660
3661 emit_data->output[emit_data->chan] =
3662 lp_build_intrinsic(
3663 builder, intrinsic_name, emit_data->dst_type,
3664 emit_data->args, emit_data->arg_count,
3665 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3666 }
3667 }
3668
3669 static void store_fetch_args(
3670 struct lp_build_tgsi_context * bld_base,
3671 struct lp_build_emit_data * emit_data)
3672 {
3673 struct si_shader_context *ctx = si_shader_context(bld_base);
3674 struct gallivm_state *gallivm = bld_base->base.gallivm;
3675 LLVMBuilderRef builder = gallivm->builder;
3676 const struct tgsi_full_instruction * inst = emit_data->inst;
3677 struct tgsi_full_src_register memory;
3678 LLVMValueRef chans[4];
3679 LLVMValueRef data;
3680 LLVMValueRef rsrc;
3681 unsigned chan;
3682
3683 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3684
3685 for (chan = 0; chan < 4; ++chan) {
3686 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3687 }
3688 data = lp_build_gather_values(gallivm, chans, 4);
3689
3690 emit_data->args[emit_data->arg_count++] = data;
3691
3692 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3693
3694 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3695 LLVMValueRef offset;
3696 LLVMValueRef tmp;
3697
3698 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3699
3700 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3701 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3702
3703 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3704 offset, false);
3705 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3706 unsigned target = inst->Memory.Texture;
3707 LLVMValueRef coords;
3708
3709 coords = image_fetch_coords(bld_base, inst, 0);
3710
3711 if (target == TGSI_TEXTURE_BUFFER) {
3712 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3713
3714 rsrc = extract_rsrc_top_half(ctx, rsrc);
3715 buffer_append_args(ctx, emit_data, rsrc, coords,
3716 bld_base->uint_bld.zero, false);
3717 } else {
3718 emit_data->args[1] = coords;
3719 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3720 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3721 emit_data->arg_count = 4;
3722
3723 image_append_args(ctx, emit_data, target, false);
3724 }
3725 }
3726 }
3727
3728 static void store_emit_buffer(
3729 struct si_shader_context *ctx,
3730 struct lp_build_emit_data *emit_data)
3731 {
3732 const struct tgsi_full_instruction *inst = emit_data->inst;
3733 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3734 LLVMBuilderRef builder = gallivm->builder;
3735 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3736 LLVMValueRef base_data = emit_data->args[0];
3737 LLVMValueRef base_offset = emit_data->args[3];
3738 unsigned writemask = inst->Dst[0].Register.WriteMask;
3739
3740 while (writemask) {
3741 int start, count;
3742 const char *intrinsic_name;
3743 LLVMValueRef data;
3744 LLVMValueRef offset;
3745 LLVMValueRef tmp;
3746
3747 u_bit_scan_consecutive_range(&writemask, &start, &count);
3748
3749 /* Due to an LLVM limitation, split 3-element writes
3750 * into a 2-element and a 1-element write. */
3751 if (count == 3) {
3752 writemask |= 1 << (start + 2);
3753 count = 2;
3754 }
3755
3756 if (count == 4) {
3757 data = base_data;
3758 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3759 } else if (count == 2) {
3760 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3761
3762 tmp = LLVMBuildExtractElement(
3763 builder, base_data,
3764 lp_build_const_int32(gallivm, start), "");
3765 data = LLVMBuildInsertElement(
3766 builder, LLVMGetUndef(v2f32), tmp,
3767 uint_bld->zero, "");
3768
3769 tmp = LLVMBuildExtractElement(
3770 builder, base_data,
3771 lp_build_const_int32(gallivm, start + 1), "");
3772 data = LLVMBuildInsertElement(
3773 builder, data, tmp, uint_bld->one, "");
3774
3775 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3776 } else {
3777 assert(count == 1);
3778 data = LLVMBuildExtractElement(
3779 builder, base_data,
3780 lp_build_const_int32(gallivm, start), "");
3781 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3782 }
3783
3784 offset = base_offset;
3785 if (start != 0) {
3786 offset = LLVMBuildAdd(
3787 builder, offset,
3788 lp_build_const_int32(gallivm, start * 4), "");
3789 }
3790
3791 emit_data->args[0] = data;
3792 emit_data->args[3] = offset;
3793
3794 lp_build_intrinsic(
3795 builder, intrinsic_name, emit_data->dst_type,
3796 emit_data->args, emit_data->arg_count,
3797 LLVMNoUnwindAttribute);
3798 }
3799 }
3800
3801 static void store_emit_memory(
3802 struct si_shader_context *ctx,
3803 struct lp_build_emit_data *emit_data)
3804 {
3805 const struct tgsi_full_instruction *inst = emit_data->inst;
3806 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3807 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3808 LLVMBuilderRef builder = gallivm->builder;
3809 unsigned writemask = inst->Dst[0].Register.WriteMask;
3810 LLVMValueRef ptr, derived_ptr, data, index;
3811 int chan;
3812
3813 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3814
3815 for (chan = 0; chan < 4; ++chan) {
3816 if (!(writemask & (1 << chan))) {
3817 continue;
3818 }
3819 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3820 index = lp_build_const_int32(gallivm, chan);
3821 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3822 LLVMBuildStore(builder, data, derived_ptr);
3823 }
3824 }
3825
3826 static void store_emit(
3827 const struct lp_build_tgsi_action *action,
3828 struct lp_build_tgsi_context *bld_base,
3829 struct lp_build_emit_data *emit_data)
3830 {
3831 struct si_shader_context *ctx = si_shader_context(bld_base);
3832 struct gallivm_state *gallivm = bld_base->base.gallivm;
3833 LLVMBuilderRef builder = gallivm->builder;
3834 const struct tgsi_full_instruction * inst = emit_data->inst;
3835 unsigned target = inst->Memory.Texture;
3836 char intrinsic_name[32];
3837 char coords_type[8];
3838
3839 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3840 store_emit_memory(ctx, emit_data);
3841 return;
3842 }
3843
3844 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3845 emit_waitcnt(ctx);
3846
3847 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3848 store_emit_buffer(ctx, emit_data);
3849 return;
3850 }
3851
3852 if (target == TGSI_TEXTURE_BUFFER) {
3853 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3854 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3855 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3856 LLVMNoUnwindAttribute);
3857 } else {
3858 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3859 coords_type, sizeof(coords_type));
3860 snprintf(intrinsic_name, sizeof(intrinsic_name),
3861 "llvm.amdgcn.image.store.%s", coords_type);
3862
3863 emit_data->output[emit_data->chan] =
3864 lp_build_intrinsic(
3865 builder, intrinsic_name, emit_data->dst_type,
3866 emit_data->args, emit_data->arg_count,
3867 LLVMNoUnwindAttribute);
3868 }
3869 }
3870
3871 static void atomic_fetch_args(
3872 struct lp_build_tgsi_context * bld_base,
3873 struct lp_build_emit_data * emit_data)
3874 {
3875 struct si_shader_context *ctx = si_shader_context(bld_base);
3876 struct gallivm_state *gallivm = bld_base->base.gallivm;
3877 LLVMBuilderRef builder = gallivm->builder;
3878 const struct tgsi_full_instruction * inst = emit_data->inst;
3879 LLVMValueRef data1, data2;
3880 LLVMValueRef rsrc;
3881 LLVMValueRef tmp;
3882
3883 emit_data->dst_type = bld_base->base.elem_type;
3884
3885 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3886 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3887
3888 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3889 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3890 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3891 }
3892
3893 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3894 * of arguments, which is reversed relative to TGSI (and GLSL)
3895 */
3896 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3897 emit_data->args[emit_data->arg_count++] = data2;
3898 emit_data->args[emit_data->arg_count++] = data1;
3899
3900 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3901 LLVMValueRef offset;
3902
3903 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3904
3905 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3906 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3907
3908 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3909 offset, true);
3910 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3911 unsigned target = inst->Memory.Texture;
3912 LLVMValueRef coords;
3913
3914 image_fetch_rsrc(bld_base, &inst->Src[0],
3915 target != TGSI_TEXTURE_BUFFER, &rsrc);
3916 coords = image_fetch_coords(bld_base, inst, 1);
3917
3918 if (target == TGSI_TEXTURE_BUFFER) {
3919 rsrc = extract_rsrc_top_half(ctx, rsrc);
3920 buffer_append_args(ctx, emit_data, rsrc, coords,
3921 bld_base->uint_bld.zero, true);
3922 } else {
3923 emit_data->args[emit_data->arg_count++] = coords;
3924 emit_data->args[emit_data->arg_count++] = rsrc;
3925
3926 image_append_args(ctx, emit_data, target, true);
3927 }
3928 }
3929 }
3930
3931 static void atomic_emit_memory(struct si_shader_context *ctx,
3932 struct lp_build_emit_data *emit_data) {
3933 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3934 LLVMBuilderRef builder = gallivm->builder;
3935 const struct tgsi_full_instruction * inst = emit_data->inst;
3936 LLVMValueRef ptr, result, arg;
3937
3938 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3939
3940 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3941 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3942
3943 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3944 LLVMValueRef new_data;
3945 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3946 inst, 3, 0);
3947
3948 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3949
3950 #if HAVE_LLVM >= 0x309
3951 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3952 LLVMAtomicOrderingSequentiallyConsistent,
3953 LLVMAtomicOrderingSequentiallyConsistent,
3954 false);
3955 #endif
3956
3957 result = LLVMBuildExtractValue(builder, result, 0, "");
3958 } else {
3959 LLVMAtomicRMWBinOp op;
3960
3961 switch(inst->Instruction.Opcode) {
3962 case TGSI_OPCODE_ATOMUADD:
3963 op = LLVMAtomicRMWBinOpAdd;
3964 break;
3965 case TGSI_OPCODE_ATOMXCHG:
3966 op = LLVMAtomicRMWBinOpXchg;
3967 break;
3968 case TGSI_OPCODE_ATOMAND:
3969 op = LLVMAtomicRMWBinOpAnd;
3970 break;
3971 case TGSI_OPCODE_ATOMOR:
3972 op = LLVMAtomicRMWBinOpOr;
3973 break;
3974 case TGSI_OPCODE_ATOMXOR:
3975 op = LLVMAtomicRMWBinOpXor;
3976 break;
3977 case TGSI_OPCODE_ATOMUMIN:
3978 op = LLVMAtomicRMWBinOpUMin;
3979 break;
3980 case TGSI_OPCODE_ATOMUMAX:
3981 op = LLVMAtomicRMWBinOpUMax;
3982 break;
3983 case TGSI_OPCODE_ATOMIMIN:
3984 op = LLVMAtomicRMWBinOpMin;
3985 break;
3986 case TGSI_OPCODE_ATOMIMAX:
3987 op = LLVMAtomicRMWBinOpMax;
3988 break;
3989 default:
3990 unreachable("unknown atomic opcode");
3991 }
3992
3993 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3994 LLVMAtomicOrderingSequentiallyConsistent,
3995 false);
3996 }
3997 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3998 }
3999
4000 static void atomic_emit(
4001 const struct lp_build_tgsi_action *action,
4002 struct lp_build_tgsi_context *bld_base,
4003 struct lp_build_emit_data *emit_data)
4004 {
4005 struct si_shader_context *ctx = si_shader_context(bld_base);
4006 struct gallivm_state *gallivm = bld_base->base.gallivm;
4007 LLVMBuilderRef builder = gallivm->builder;
4008 const struct tgsi_full_instruction * inst = emit_data->inst;
4009 char intrinsic_name[40];
4010 LLVMValueRef tmp;
4011
4012 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4013 atomic_emit_memory(ctx, emit_data);
4014 return;
4015 }
4016
4017 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4018 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4019 snprintf(intrinsic_name, sizeof(intrinsic_name),
4020 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4021 } else {
4022 char coords_type[8];
4023
4024 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4025 coords_type, sizeof(coords_type));
4026 snprintf(intrinsic_name, sizeof(intrinsic_name),
4027 "llvm.amdgcn.image.atomic.%s.%s",
4028 action->intr_name, coords_type);
4029 }
4030
4031 tmp = lp_build_intrinsic(
4032 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4033 emit_data->args, emit_data->arg_count,
4034 LLVMNoUnwindAttribute);
4035 emit_data->output[emit_data->chan] =
4036 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4037 }
4038
4039 static void resq_fetch_args(
4040 struct lp_build_tgsi_context * bld_base,
4041 struct lp_build_emit_data * emit_data)
4042 {
4043 struct si_shader_context *ctx = si_shader_context(bld_base);
4044 struct gallivm_state *gallivm = bld_base->base.gallivm;
4045 const struct tgsi_full_instruction *inst = emit_data->inst;
4046 const struct tgsi_full_src_register *reg = &inst->Src[0];
4047
4048 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
4049
4050 if (reg->Register.File == TGSI_FILE_BUFFER) {
4051 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4052 emit_data->arg_count = 1;
4053 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4054 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4055 emit_data->arg_count = 1;
4056 } else {
4057 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4058 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4059 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4060 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4061 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4062 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4063 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4064 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4065 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4066 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4067 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4068 emit_data->arg_count = 10;
4069 }
4070 }
4071
4072 static void resq_emit(
4073 const struct lp_build_tgsi_action *action,
4074 struct lp_build_tgsi_context *bld_base,
4075 struct lp_build_emit_data *emit_data)
4076 {
4077 struct gallivm_state *gallivm = bld_base->base.gallivm;
4078 LLVMBuilderRef builder = gallivm->builder;
4079 const struct tgsi_full_instruction *inst = emit_data->inst;
4080 LLVMValueRef out;
4081
4082 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4083 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4084 lp_build_const_int32(gallivm, 2), "");
4085 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4086 out = get_buffer_size(bld_base, emit_data->args[0]);
4087 } else {
4088 out = lp_build_intrinsic(
4089 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4090 emit_data->args, emit_data->arg_count,
4091 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4092
4093 /* Divide the number of layers by 6 to get the number of cubes. */
4094 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4095 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4096 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4097
4098 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4099 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
4100 z = LLVMBuildSDiv(builder, z, imm6, "");
4101 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
4102 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4103 }
4104 }
4105
4106 emit_data->output[emit_data->chan] = out;
4107 }
4108
4109 static void set_tex_fetch_args(struct si_shader_context *ctx,
4110 struct lp_build_emit_data *emit_data,
4111 unsigned opcode, unsigned target,
4112 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4113 LLVMValueRef *param, unsigned count,
4114 unsigned dmask)
4115 {
4116 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4117 unsigned num_args;
4118 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4119
4120 /* Pad to power of two vector */
4121 while (count < util_next_power_of_two(count))
4122 param[count++] = LLVMGetUndef(ctx->i32);
4123
4124 /* Texture coordinates. */
4125 if (count > 1)
4126 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4127 else
4128 emit_data->args[0] = param[0];
4129
4130 /* Resource. */
4131 emit_data->args[1] = res_ptr;
4132 num_args = 2;
4133
4134 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4135 emit_data->dst_type = ctx->v4i32;
4136 else {
4137 emit_data->dst_type = ctx->v4f32;
4138
4139 emit_data->args[num_args++] = samp_ptr;
4140 }
4141
4142 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4143 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4144 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4145 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4146 tgsi_is_array_sampler(target)); /* da */
4147 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4148 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4149 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4150 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4151
4152 emit_data->arg_count = num_args;
4153 }
4154
4155 static const struct lp_build_tgsi_action tex_action;
4156
4157 enum desc_type {
4158 DESC_IMAGE,
4159 DESC_FMASK,
4160 DESC_SAMPLER
4161 };
4162
4163 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4164 {
4165 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4166 CONST_ADDR_SPACE);
4167 }
4168
4169 /**
4170 * Load an image view, fmask view. or sampler state descriptor.
4171 */
4172 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4173 LLVMValueRef list, LLVMValueRef index,
4174 enum desc_type type)
4175 {
4176 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4177 LLVMBuilderRef builder = gallivm->builder;
4178
4179 switch (type) {
4180 case DESC_IMAGE:
4181 /* The image is at [0:7]. */
4182 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4183 break;
4184 case DESC_FMASK:
4185 /* The FMASK is at [8:15]. */
4186 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4187 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4188 break;
4189 case DESC_SAMPLER:
4190 /* The sampler state is at [12:15]. */
4191 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4192 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4193 list = LLVMBuildPointerCast(builder, list,
4194 const_array(ctx->v4i32, 0), "");
4195 break;
4196 }
4197
4198 return build_indexed_load_const(ctx, list, index);
4199 }
4200
4201 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4202 LLVMValueRef index, enum desc_type type)
4203 {
4204 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4205 SI_PARAM_SAMPLERS);
4206
4207 return get_sampler_desc_custom(ctx, list, index, type);
4208 }
4209
4210 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4211 *
4212 * SI-CI:
4213 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4214 * filtering manually. The driver sets img7 to a mask clearing
4215 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4216 * s_and_b32 samp0, samp0, img7
4217 *
4218 * VI:
4219 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4220 */
4221 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4222 LLVMValueRef res, LLVMValueRef samp)
4223 {
4224 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4225 LLVMValueRef img7, samp0;
4226
4227 if (ctx->screen->b.chip_class >= VI)
4228 return samp;
4229
4230 img7 = LLVMBuildExtractElement(builder, res,
4231 LLVMConstInt(ctx->i32, 7, 0), "");
4232 samp0 = LLVMBuildExtractElement(builder, samp,
4233 LLVMConstInt(ctx->i32, 0, 0), "");
4234 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4235 return LLVMBuildInsertElement(builder, samp, samp0,
4236 LLVMConstInt(ctx->i32, 0, 0), "");
4237 }
4238
4239 static void tex_fetch_ptrs(
4240 struct lp_build_tgsi_context *bld_base,
4241 struct lp_build_emit_data *emit_data,
4242 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4243 {
4244 struct si_shader_context *ctx = si_shader_context(bld_base);
4245 const struct tgsi_full_instruction *inst = emit_data->inst;
4246 unsigned target = inst->Texture.Texture;
4247 unsigned sampler_src;
4248 unsigned sampler_index;
4249
4250 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4251 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4252
4253 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4254 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4255 LLVMValueRef ind_index;
4256
4257 ind_index = get_bounded_indirect_index(ctx,
4258 &reg->Indirect,
4259 reg->Register.Index,
4260 SI_NUM_SAMPLERS);
4261
4262 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4263
4264 if (target == TGSI_TEXTURE_2D_MSAA ||
4265 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4266 if (samp_ptr)
4267 *samp_ptr = NULL;
4268 if (fmask_ptr)
4269 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4270 } else {
4271 if (samp_ptr) {
4272 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4273 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4274 }
4275 if (fmask_ptr)
4276 *fmask_ptr = NULL;
4277 }
4278 } else {
4279 *res_ptr = ctx->sampler_views[sampler_index];
4280 if (samp_ptr)
4281 *samp_ptr = ctx->sampler_states[sampler_index];
4282 if (fmask_ptr)
4283 *fmask_ptr = ctx->fmasks[sampler_index];
4284 }
4285 }
4286
4287 static void txq_fetch_args(
4288 struct lp_build_tgsi_context *bld_base,
4289 struct lp_build_emit_data *emit_data)
4290 {
4291 struct si_shader_context *ctx = si_shader_context(bld_base);
4292 struct gallivm_state *gallivm = bld_base->base.gallivm;
4293 LLVMBuilderRef builder = gallivm->builder;
4294 const struct tgsi_full_instruction *inst = emit_data->inst;
4295 unsigned target = inst->Texture.Texture;
4296 LLVMValueRef res_ptr;
4297 LLVMValueRef address;
4298
4299 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4300
4301 if (target == TGSI_TEXTURE_BUFFER) {
4302 /* Read the size from the buffer descriptor directly. */
4303 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4304 emit_data->args[0] = get_buffer_size(bld_base, res);
4305 return;
4306 }
4307
4308 /* Textures - set the mip level. */
4309 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4310
4311 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4312 NULL, &address, 1, 0xf);
4313 }
4314
4315 static void txq_emit(const struct lp_build_tgsi_action *action,
4316 struct lp_build_tgsi_context *bld_base,
4317 struct lp_build_emit_data *emit_data)
4318 {
4319 struct lp_build_context *base = &bld_base->base;
4320 unsigned target = emit_data->inst->Texture.Texture;
4321
4322 if (target == TGSI_TEXTURE_BUFFER) {
4323 /* Just return the buffer size. */
4324 emit_data->output[emit_data->chan] = emit_data->args[0];
4325 return;
4326 }
4327
4328 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4329 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4330 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4331 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4332
4333 /* Divide the number of layers by 6 to get the number of cubes. */
4334 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4335 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4336 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4337 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4338 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4339
4340 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4341 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4342 z = LLVMBuildSDiv(builder, z, six, "");
4343
4344 emit_data->output[emit_data->chan] =
4345 LLVMBuildInsertElement(builder, v4, z, two, "");
4346 }
4347 }
4348
4349 static void tex_fetch_args(
4350 struct lp_build_tgsi_context *bld_base,
4351 struct lp_build_emit_data *emit_data)
4352 {
4353 struct si_shader_context *ctx = si_shader_context(bld_base);
4354 struct gallivm_state *gallivm = bld_base->base.gallivm;
4355 const struct tgsi_full_instruction *inst = emit_data->inst;
4356 unsigned opcode = inst->Instruction.Opcode;
4357 unsigned target = inst->Texture.Texture;
4358 LLVMValueRef coords[5], derivs[6];
4359 LLVMValueRef address[16];
4360 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4361 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4362 unsigned count = 0;
4363 unsigned chan;
4364 unsigned num_deriv_channels = 0;
4365 bool has_offset = inst->Texture.NumOffsets > 0;
4366 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4367 unsigned dmask = 0xf;
4368
4369 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4370
4371 if (target == TGSI_TEXTURE_BUFFER) {
4372 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4373
4374 /* Bitcast and truncate v8i32 to v16i8. */
4375 LLVMValueRef res = res_ptr;
4376 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4377 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4378 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4379
4380 emit_data->dst_type = ctx->v4f32;
4381 emit_data->args[0] = res;
4382 emit_data->args[1] = bld_base->uint_bld.zero;
4383 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4384 emit_data->arg_count = 3;
4385 return;
4386 }
4387
4388 /* Fetch and project texture coordinates */
4389 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4390 for (chan = 0; chan < 3; chan++ ) {
4391 coords[chan] = lp_build_emit_fetch(bld_base,
4392 emit_data->inst, 0,
4393 chan);
4394 if (opcode == TGSI_OPCODE_TXP)
4395 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4396 TGSI_OPCODE_DIV,
4397 coords[chan],
4398 coords[3]);
4399 }
4400
4401 if (opcode == TGSI_OPCODE_TXP)
4402 coords[3] = bld_base->base.one;
4403
4404 /* Pack offsets. */
4405 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4406 /* The offsets are six-bit signed integers packed like this:
4407 * X=[5:0], Y=[13:8], and Z=[21:16].
4408 */
4409 LLVMValueRef offset[3], pack;
4410
4411 assert(inst->Texture.NumOffsets == 1);
4412
4413 for (chan = 0; chan < 3; chan++) {
4414 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4415 emit_data->inst, 0, chan);
4416 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4417 lp_build_const_int32(gallivm, 0x3f), "");
4418 if (chan)
4419 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4420 lp_build_const_int32(gallivm, chan*8), "");
4421 }
4422
4423 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4424 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4425 address[count++] = pack;
4426 }
4427
4428 /* Pack LOD bias value */
4429 if (opcode == TGSI_OPCODE_TXB)
4430 address[count++] = coords[3];
4431 if (opcode == TGSI_OPCODE_TXB2)
4432 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4433
4434 /* Pack depth comparison value */
4435 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4436 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4437 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4438 } else {
4439 assert(ref_pos >= 0);
4440 address[count++] = coords[ref_pos];
4441 }
4442 }
4443
4444 /* Pack user derivatives */
4445 if (opcode == TGSI_OPCODE_TXD) {
4446 int param, num_src_deriv_channels;
4447
4448 switch (target) {
4449 case TGSI_TEXTURE_3D:
4450 num_src_deriv_channels = 3;
4451 num_deriv_channels = 3;
4452 break;
4453 case TGSI_TEXTURE_2D:
4454 case TGSI_TEXTURE_SHADOW2D:
4455 case TGSI_TEXTURE_RECT:
4456 case TGSI_TEXTURE_SHADOWRECT:
4457 case TGSI_TEXTURE_2D_ARRAY:
4458 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4459 num_src_deriv_channels = 2;
4460 num_deriv_channels = 2;
4461 break;
4462 case TGSI_TEXTURE_CUBE:
4463 case TGSI_TEXTURE_SHADOWCUBE:
4464 case TGSI_TEXTURE_CUBE_ARRAY:
4465 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4466 /* Cube derivatives will be converted to 2D. */
4467 num_src_deriv_channels = 3;
4468 num_deriv_channels = 2;
4469 break;
4470 case TGSI_TEXTURE_1D:
4471 case TGSI_TEXTURE_SHADOW1D:
4472 case TGSI_TEXTURE_1D_ARRAY:
4473 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4474 num_src_deriv_channels = 1;
4475 num_deriv_channels = 1;
4476 break;
4477 default:
4478 unreachable("invalid target");
4479 }
4480
4481 for (param = 0; param < 2; param++)
4482 for (chan = 0; chan < num_src_deriv_channels; chan++)
4483 derivs[param * num_src_deriv_channels + chan] =
4484 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4485 }
4486
4487 if (target == TGSI_TEXTURE_CUBE ||
4488 target == TGSI_TEXTURE_CUBE_ARRAY ||
4489 target == TGSI_TEXTURE_SHADOWCUBE ||
4490 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4491 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4492
4493 if (opcode == TGSI_OPCODE_TXD)
4494 for (int i = 0; i < num_deriv_channels * 2; i++)
4495 address[count++] = derivs[i];
4496
4497 /* Pack texture coordinates */
4498 address[count++] = coords[0];
4499 if (num_coords > 1)
4500 address[count++] = coords[1];
4501 if (num_coords > 2)
4502 address[count++] = coords[2];
4503
4504 /* Pack LOD or sample index */
4505 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4506 address[count++] = coords[3];
4507 else if (opcode == TGSI_OPCODE_TXL2)
4508 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4509
4510 if (count > 16) {
4511 assert(!"Cannot handle more than 16 texture address parameters");
4512 count = 16;
4513 }
4514
4515 for (chan = 0; chan < count; chan++ ) {
4516 address[chan] = LLVMBuildBitCast(gallivm->builder,
4517 address[chan], ctx->i32, "");
4518 }
4519
4520 /* Adjust the sample index according to FMASK.
4521 *
4522 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4523 * which is the identity mapping. Each nibble says which physical sample
4524 * should be fetched to get that sample.
4525 *
4526 * For example, 0x11111100 means there are only 2 samples stored and
4527 * the second sample covers 3/4 of the pixel. When reading samples 0
4528 * and 1, return physical sample 0 (determined by the first two 0s
4529 * in FMASK), otherwise return physical sample 1.
4530 *
4531 * The sample index should be adjusted as follows:
4532 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4533 */
4534 if (target == TGSI_TEXTURE_2D_MSAA ||
4535 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4536 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4537 struct lp_build_emit_data txf_emit_data = *emit_data;
4538 LLVMValueRef txf_address[4];
4539 unsigned txf_count = count;
4540 struct tgsi_full_instruction inst = {};
4541
4542 memcpy(txf_address, address, sizeof(txf_address));
4543
4544 if (target == TGSI_TEXTURE_2D_MSAA) {
4545 txf_address[2] = bld_base->uint_bld.zero;
4546 }
4547 txf_address[3] = bld_base->uint_bld.zero;
4548
4549 /* Read FMASK using TXF. */
4550 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4551 inst.Texture.Texture = target;
4552 txf_emit_data.inst = &inst;
4553 txf_emit_data.chan = 0;
4554 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4555 target, fmask_ptr, NULL,
4556 txf_address, txf_count, 0xf);
4557 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4558
4559 /* Initialize some constants. */
4560 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4561 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4562
4563 /* Apply the formula. */
4564 LLVMValueRef fmask =
4565 LLVMBuildExtractElement(gallivm->builder,
4566 txf_emit_data.output[0],
4567 uint_bld->zero, "");
4568
4569 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4570
4571 LLVMValueRef sample_index4 =
4572 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4573
4574 LLVMValueRef shifted_fmask =
4575 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4576
4577 LLVMValueRef final_sample =
4578 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4579
4580 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4581 * resource descriptor is 0 (invalid),
4582 */
4583 LLVMValueRef fmask_desc =
4584 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4585 ctx->v8i32, "");
4586
4587 LLVMValueRef fmask_word1 =
4588 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4589 uint_bld->one, "");
4590
4591 LLVMValueRef word1_is_nonzero =
4592 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4593 fmask_word1, uint_bld->zero, "");
4594
4595 /* Replace the MSAA sample index. */
4596 address[sample_chan] =
4597 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4598 final_sample, address[sample_chan], "");
4599 }
4600
4601 if (opcode == TGSI_OPCODE_TXF) {
4602 /* add tex offsets */
4603 if (inst->Texture.NumOffsets) {
4604 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4605 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4606 const struct tgsi_texture_offset *off = inst->TexOffsets;
4607
4608 assert(inst->Texture.NumOffsets == 1);
4609
4610 switch (target) {
4611 case TGSI_TEXTURE_3D:
4612 address[2] = lp_build_add(uint_bld, address[2],
4613 bld->immediates[off->Index][off->SwizzleZ]);
4614 /* fall through */
4615 case TGSI_TEXTURE_2D:
4616 case TGSI_TEXTURE_SHADOW2D:
4617 case TGSI_TEXTURE_RECT:
4618 case TGSI_TEXTURE_SHADOWRECT:
4619 case TGSI_TEXTURE_2D_ARRAY:
4620 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4621 address[1] =
4622 lp_build_add(uint_bld, address[1],
4623 bld->immediates[off->Index][off->SwizzleY]);
4624 /* fall through */
4625 case TGSI_TEXTURE_1D:
4626 case TGSI_TEXTURE_SHADOW1D:
4627 case TGSI_TEXTURE_1D_ARRAY:
4628 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4629 address[0] =
4630 lp_build_add(uint_bld, address[0],
4631 bld->immediates[off->Index][off->SwizzleX]);
4632 break;
4633 /* texture offsets do not apply to other texture targets */
4634 }
4635 }
4636 }
4637
4638 if (opcode == TGSI_OPCODE_TG4) {
4639 unsigned gather_comp = 0;
4640
4641 /* DMASK was repurposed for GATHER4. 4 components are always
4642 * returned and DMASK works like a swizzle - it selects
4643 * the component to fetch. The only valid DMASK values are
4644 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4645 * (red,red,red,red) etc.) The ISA document doesn't mention
4646 * this.
4647 */
4648
4649 /* Get the component index from src1.x for Gather4. */
4650 if (!tgsi_is_shadow_target(target)) {
4651 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4652 LLVMValueRef comp_imm;
4653 struct tgsi_src_register src1 = inst->Src[1].Register;
4654
4655 assert(src1.File == TGSI_FILE_IMMEDIATE);
4656
4657 comp_imm = imms[src1.Index][src1.SwizzleX];
4658 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4659 gather_comp = CLAMP(gather_comp, 0, 3);
4660 }
4661
4662 dmask = 1 << gather_comp;
4663 }
4664
4665 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4666 samp_ptr, address, count, dmask);
4667 }
4668
4669 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4670 struct lp_build_tgsi_context *bld_base,
4671 struct lp_build_emit_data *emit_data)
4672 {
4673 struct si_shader_context *ctx = si_shader_context(bld_base);
4674 struct lp_build_context *base = &bld_base->base;
4675 unsigned opcode = emit_data->inst->Instruction.Opcode;
4676 unsigned target = emit_data->inst->Texture.Texture;
4677 char intr_name[127];
4678 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4679 bool is_shadow = tgsi_is_shadow_target(target);
4680 char type[64];
4681 const char *name = "llvm.SI.image.sample";
4682 const char *infix = "";
4683
4684 if (target == TGSI_TEXTURE_BUFFER) {
4685 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4686 base->gallivm->builder,
4687 "llvm.SI.vs.load.input", emit_data->dst_type,
4688 emit_data->args, emit_data->arg_count,
4689 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4690 return;
4691 }
4692
4693 switch (opcode) {
4694 case TGSI_OPCODE_TXF:
4695 name = target == TGSI_TEXTURE_2D_MSAA ||
4696 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4697 "llvm.SI.image.load" :
4698 "llvm.SI.image.load.mip";
4699 is_shadow = false;
4700 has_offset = false;
4701 break;
4702 case TGSI_OPCODE_LODQ:
4703 name = "llvm.SI.getlod";
4704 is_shadow = false;
4705 has_offset = false;
4706 break;
4707 case TGSI_OPCODE_TEX:
4708 case TGSI_OPCODE_TEX2:
4709 case TGSI_OPCODE_TXP:
4710 if (ctx->type != PIPE_SHADER_FRAGMENT)
4711 infix = ".lz";
4712 break;
4713 case TGSI_OPCODE_TXB:
4714 case TGSI_OPCODE_TXB2:
4715 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4716 infix = ".b";
4717 break;
4718 case TGSI_OPCODE_TXL:
4719 case TGSI_OPCODE_TXL2:
4720 infix = ".l";
4721 break;
4722 case TGSI_OPCODE_TXD:
4723 infix = ".d";
4724 break;
4725 case TGSI_OPCODE_TG4:
4726 name = "llvm.SI.gather4";
4727 infix = ".lz";
4728 break;
4729 default:
4730 assert(0);
4731 return;
4732 }
4733
4734 /* Add the type and suffixes .c, .o if needed. */
4735 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4736 sprintf(intr_name, "%s%s%s%s.%s",
4737 name, is_shadow ? ".c" : "", infix,
4738 has_offset ? ".o" : "", type);
4739
4740 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4741 base->gallivm->builder, intr_name, emit_data->dst_type,
4742 emit_data->args, emit_data->arg_count,
4743 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4744 }
4745
4746 static void si_llvm_emit_txqs(
4747 const struct lp_build_tgsi_action *action,
4748 struct lp_build_tgsi_context *bld_base,
4749 struct lp_build_emit_data *emit_data)
4750 {
4751 struct si_shader_context *ctx = si_shader_context(bld_base);
4752 struct gallivm_state *gallivm = bld_base->base.gallivm;
4753 LLVMBuilderRef builder = gallivm->builder;
4754 LLVMValueRef res, samples;
4755 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4756
4757 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4758
4759
4760 /* Read the samples from the descriptor directly. */
4761 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4762 samples = LLVMBuildExtractElement(
4763 builder, res,
4764 lp_build_const_int32(gallivm, 3), "");
4765 samples = LLVMBuildLShr(builder, samples,
4766 lp_build_const_int32(gallivm, 16), "");
4767 samples = LLVMBuildAnd(builder, samples,
4768 lp_build_const_int32(gallivm, 0xf), "");
4769 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4770 samples, "");
4771
4772 emit_data->output[emit_data->chan] = samples;
4773 }
4774
4775 /*
4776 * SI implements derivatives using the local data store (LDS)
4777 * All writes to the LDS happen in all executing threads at
4778 * the same time. TID is the Thread ID for the current
4779 * thread and is a value between 0 and 63, representing
4780 * the thread's position in the wavefront.
4781 *
4782 * For the pixel shader threads are grouped into quads of four pixels.
4783 * The TIDs of the pixels of a quad are:
4784 *
4785 * +------+------+
4786 * |4n + 0|4n + 1|
4787 * +------+------+
4788 * |4n + 2|4n + 3|
4789 * +------+------+
4790 *
4791 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4792 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4793 * the current pixel's column, and masking with 0xfffffffe yields the TID
4794 * of the left pixel of the current pixel's row.
4795 *
4796 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4797 * adding 2 yields the TID of the pixel below the top pixel.
4798 */
4799 /* masks for thread ID. */
4800 #define TID_MASK_TOP_LEFT 0xfffffffc
4801 #define TID_MASK_TOP 0xfffffffd
4802 #define TID_MASK_LEFT 0xfffffffe
4803
4804 static void si_llvm_emit_ddxy(
4805 const struct lp_build_tgsi_action *action,
4806 struct lp_build_tgsi_context *bld_base,
4807 struct lp_build_emit_data *emit_data)
4808 {
4809 struct si_shader_context *ctx = si_shader_context(bld_base);
4810 struct gallivm_state *gallivm = bld_base->base.gallivm;
4811 const struct tgsi_full_instruction *inst = emit_data->inst;
4812 unsigned opcode = inst->Instruction.Opcode;
4813 LLVMValueRef indices[2];
4814 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4815 LLVMValueRef tl, trbl, result[4];
4816 LLVMValueRef tl_tid, trbl_tid;
4817 unsigned swizzle[4];
4818 unsigned c;
4819 int idx;
4820 unsigned mask;
4821
4822 indices[0] = bld_base->uint_bld.zero;
4823 indices[1] = get_thread_id(ctx);
4824 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4825 indices, 2, "");
4826
4827 if (opcode == TGSI_OPCODE_DDX_FINE)
4828 mask = TID_MASK_LEFT;
4829 else if (opcode == TGSI_OPCODE_DDY_FINE)
4830 mask = TID_MASK_TOP;
4831 else
4832 mask = TID_MASK_TOP_LEFT;
4833
4834 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
4835 lp_build_const_int32(gallivm, mask), "");
4836 indices[1] = tl_tid;
4837 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4838 indices, 2, "");
4839
4840 /* for DDX we want to next X pixel, DDY next Y pixel. */
4841 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4842 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
4843 lp_build_const_int32(gallivm, idx), "");
4844 indices[1] = trbl_tid;
4845 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4846 indices, 2, "");
4847
4848 for (c = 0; c < 4; ++c) {
4849 unsigned i;
4850 LLVMValueRef val;
4851 LLVMValueRef args[2];
4852
4853 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4854 for (i = 0; i < c; ++i) {
4855 if (swizzle[i] == swizzle[c]) {
4856 result[c] = result[i];
4857 break;
4858 }
4859 }
4860 if (i != c)
4861 continue;
4862
4863 val = LLVMBuildBitCast(gallivm->builder,
4864 lp_build_emit_fetch(bld_base, inst, 0, c),
4865 ctx->i32, "");
4866
4867 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
4868
4869 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4870 lp_build_const_int32(gallivm, 4), "");
4871 args[1] = val;
4872 tl = lp_build_intrinsic(gallivm->builder,
4873 "llvm.amdgcn.ds.bpermute", ctx->i32,
4874 args, 2, LLVMReadNoneAttribute);
4875
4876 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4877 lp_build_const_int32(gallivm, 4), "");
4878 trbl = lp_build_intrinsic(gallivm->builder,
4879 "llvm.amdgcn.ds.bpermute", ctx->i32,
4880 args, 2, LLVMReadNoneAttribute);
4881 } else {
4882 LLVMBuildStore(gallivm->builder, val, store_ptr);
4883 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4884 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4885 }
4886 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4887 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4888 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4889 }
4890
4891 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4892 }
4893
4894 /*
4895 * this takes an I,J coordinate pair,
4896 * and works out the X and Y derivatives.
4897 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4898 */
4899 static LLVMValueRef si_llvm_emit_ddxy_interp(
4900 struct lp_build_tgsi_context *bld_base,
4901 LLVMValueRef interp_ij)
4902 {
4903 struct si_shader_context *ctx = si_shader_context(bld_base);
4904 struct gallivm_state *gallivm = bld_base->base.gallivm;
4905 LLVMValueRef indices[2];
4906 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4907 LLVMValueRef tl, tr, bl, result[4];
4908 unsigned c;
4909
4910 indices[0] = bld_base->uint_bld.zero;
4911 indices[1] = get_thread_id(ctx);
4912 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4913 indices, 2, "");
4914
4915 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4916 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4917
4918 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4919 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4920
4921 indices[1] = temp;
4922 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4923 indices, 2, "");
4924
4925 indices[1] = temp2;
4926 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4927 indices, 2, "");
4928
4929 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4930 lp_build_const_int32(gallivm, 1), "");
4931 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4932 indices, 2, "");
4933
4934 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4935 lp_build_const_int32(gallivm, 2), "");
4936 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4937 indices, 2, "");
4938
4939 for (c = 0; c < 2; ++c) {
4940 LLVMValueRef store_val;
4941 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4942
4943 store_val = LLVMBuildExtractElement(gallivm->builder,
4944 interp_ij, c_ll, "");
4945 LLVMBuildStore(gallivm->builder,
4946 store_val,
4947 store_ptr);
4948
4949 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4950 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4951
4952 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
4953 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
4954
4955 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
4956
4957 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
4958 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4959
4960 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
4961 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
4962
4963 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
4964 }
4965
4966 return lp_build_gather_values(gallivm, result, 4);
4967 }
4968
4969 static void interp_fetch_args(
4970 struct lp_build_tgsi_context *bld_base,
4971 struct lp_build_emit_data *emit_data)
4972 {
4973 struct si_shader_context *ctx = si_shader_context(bld_base);
4974 struct gallivm_state *gallivm = bld_base->base.gallivm;
4975 const struct tgsi_full_instruction *inst = emit_data->inst;
4976
4977 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4978 /* offset is in second src, first two channels */
4979 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4980 emit_data->inst, 1,
4981 TGSI_CHAN_X);
4982 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4983 emit_data->inst, 1,
4984 TGSI_CHAN_Y);
4985 emit_data->arg_count = 2;
4986 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4987 LLVMValueRef sample_position;
4988 LLVMValueRef sample_id;
4989 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4990
4991 /* fetch sample ID, then fetch its sample position,
4992 * and place into first two channels.
4993 */
4994 sample_id = lp_build_emit_fetch(bld_base,
4995 emit_data->inst, 1, TGSI_CHAN_X);
4996 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4997 ctx->i32, "");
4998 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4999
5000 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5001 sample_position,
5002 lp_build_const_int32(gallivm, 0), "");
5003
5004 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5005 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5006 sample_position,
5007 lp_build_const_int32(gallivm, 1), "");
5008 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5009 emit_data->arg_count = 2;
5010 }
5011 }
5012
5013 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5014 struct lp_build_tgsi_context *bld_base,
5015 struct lp_build_emit_data *emit_data)
5016 {
5017 struct si_shader_context *ctx = si_shader_context(bld_base);
5018 struct si_shader *shader = ctx->shader;
5019 struct gallivm_state *gallivm = bld_base->base.gallivm;
5020 LLVMValueRef interp_param;
5021 const struct tgsi_full_instruction *inst = emit_data->inst;
5022 const char *intr_name;
5023 int input_index = inst->Src[0].Register.Index;
5024 int chan;
5025 int i;
5026 LLVMValueRef attr_number;
5027 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5028 int interp_param_idx;
5029 unsigned interp = shader->selector->info.input_interpolate[input_index];
5030 unsigned location;
5031
5032 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5033
5034 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5035 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5036 location = TGSI_INTERPOLATE_LOC_CENTER;
5037 else
5038 location = TGSI_INTERPOLATE_LOC_CENTROID;
5039
5040 interp_param_idx = lookup_interp_param_index(interp, location);
5041 if (interp_param_idx == -1)
5042 return;
5043 else if (interp_param_idx)
5044 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
5045 else
5046 interp_param = NULL;
5047
5048 attr_number = lp_build_const_int32(gallivm, input_index);
5049
5050 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5051 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5052 LLVMValueRef ij_out[2];
5053 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5054
5055 /*
5056 * take the I then J parameters, and the DDX/Y for it, and
5057 * calculate the IJ inputs for the interpolator.
5058 * temp1 = ddx * offset/sample.x + I;
5059 * interp_param.I = ddy * offset/sample.y + temp1;
5060 * temp1 = ddx * offset/sample.x + J;
5061 * interp_param.J = ddy * offset/sample.y + temp1;
5062 */
5063 for (i = 0; i < 2; i++) {
5064 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5065 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5066 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5067 ddxy_out, ix_ll, "");
5068 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5069 ddxy_out, iy_ll, "");
5070 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5071 interp_param, ix_ll, "");
5072 LLVMValueRef temp1, temp2;
5073
5074 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5075 ctx->f32, "");
5076
5077 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5078
5079 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5080
5081 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5082
5083 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5084
5085 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5086 temp2, ctx->i32, "");
5087 }
5088 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5089 }
5090
5091 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5092 for (chan = 0; chan < 2; chan++) {
5093 LLVMValueRef args[4];
5094 LLVMValueRef llvm_chan;
5095 unsigned schan;
5096
5097 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5098 llvm_chan = lp_build_const_int32(gallivm, schan);
5099
5100 args[0] = llvm_chan;
5101 args[1] = attr_number;
5102 args[2] = params;
5103 args[3] = interp_param;
5104
5105 emit_data->output[chan] =
5106 lp_build_intrinsic(gallivm->builder, intr_name,
5107 ctx->f32, args, args[3] ? 4 : 3,
5108 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
5109 }
5110 }
5111
5112 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5113 struct lp_build_emit_data *emit_data)
5114 {
5115 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5116 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5117 unsigned stream;
5118
5119 assert(src0.File == TGSI_FILE_IMMEDIATE);
5120
5121 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5122 return stream;
5123 }
5124
5125 /* Emit one vertex from the geometry shader */
5126 static void si_llvm_emit_vertex(
5127 const struct lp_build_tgsi_action *action,
5128 struct lp_build_tgsi_context *bld_base,
5129 struct lp_build_emit_data *emit_data)
5130 {
5131 struct si_shader_context *ctx = si_shader_context(bld_base);
5132 struct lp_build_context *uint = &bld_base->uint_bld;
5133 struct si_shader *shader = ctx->shader;
5134 struct tgsi_shader_info *info = &shader->selector->info;
5135 struct gallivm_state *gallivm = bld_base->base.gallivm;
5136 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5137 SI_PARAM_GS2VS_OFFSET);
5138 LLVMValueRef gs_next_vertex;
5139 LLVMValueRef can_emit, kill;
5140 LLVMValueRef args[2];
5141 unsigned chan;
5142 int i;
5143 unsigned stream;
5144
5145 stream = si_llvm_get_stream(bld_base, emit_data);
5146
5147 /* Write vertex attribute values to GSVS ring */
5148 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5149 ctx->gs_next_vertex[stream],
5150 "");
5151
5152 /* If this thread has already emitted the declared maximum number of
5153 * vertices, kill it: excessive vertex emissions are not supposed to
5154 * have any effect, and GS threads have no externally observable
5155 * effects other than emitting vertices.
5156 */
5157 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5158 lp_build_const_int32(gallivm,
5159 shader->selector->gs_max_out_vertices), "");
5160 kill = lp_build_select(&bld_base->base, can_emit,
5161 lp_build_const_float(gallivm, 1.0f),
5162 lp_build_const_float(gallivm, -1.0f));
5163
5164 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5165 ctx->voidt, &kill, 1, 0);
5166
5167 for (i = 0; i < info->num_outputs; i++) {
5168 LLVMValueRef *out_ptr =
5169 ctx->radeon_bld.soa.outputs[i];
5170
5171 for (chan = 0; chan < 4; chan++) {
5172 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5173 LLVMValueRef voffset =
5174 lp_build_const_int32(gallivm, (i * 4 + chan) *
5175 shader->selector->gs_max_out_vertices);
5176
5177 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5178 voffset = lp_build_mul_imm(uint, voffset, 4);
5179
5180 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5181
5182 build_tbuffer_store(ctx,
5183 ctx->gsvs_ring[stream],
5184 out_val, 1,
5185 voffset, soffset, 0,
5186 V_008F0C_BUF_DATA_FORMAT_32,
5187 V_008F0C_BUF_NUM_FORMAT_UINT,
5188 1, 0, 1, 1, 0);
5189 }
5190 }
5191 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5192 lp_build_const_int32(gallivm, 1));
5193
5194 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5195
5196 /* Signal vertex emission */
5197 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5198 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5199 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5200 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5201 }
5202
5203 /* Cut one primitive from the geometry shader */
5204 static void si_llvm_emit_primitive(
5205 const struct lp_build_tgsi_action *action,
5206 struct lp_build_tgsi_context *bld_base,
5207 struct lp_build_emit_data *emit_data)
5208 {
5209 struct si_shader_context *ctx = si_shader_context(bld_base);
5210 struct gallivm_state *gallivm = bld_base->base.gallivm;
5211 LLVMValueRef args[2];
5212 unsigned stream;
5213
5214 /* Signal primitive cut */
5215 stream = si_llvm_get_stream(bld_base, emit_data);
5216 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5217 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5218 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5219 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5220 }
5221
5222 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5223 struct lp_build_tgsi_context *bld_base,
5224 struct lp_build_emit_data *emit_data)
5225 {
5226 struct si_shader_context *ctx = si_shader_context(bld_base);
5227 struct gallivm_state *gallivm = bld_base->base.gallivm;
5228
5229 /* The real barrier instruction isn’t needed, because an entire patch
5230 * always fits into a single wave.
5231 */
5232 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5233 emit_optimization_barrier(ctx);
5234 return;
5235 }
5236
5237 lp_build_intrinsic(gallivm->builder,
5238 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5239 : "llvm.AMDGPU.barrier.local",
5240 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
5241 }
5242
5243 static const struct lp_build_tgsi_action tex_action = {
5244 .fetch_args = tex_fetch_args,
5245 .emit = build_tex_intrinsic,
5246 };
5247
5248 static const struct lp_build_tgsi_action interp_action = {
5249 .fetch_args = interp_fetch_args,
5250 .emit = build_interp_intrinsic,
5251 };
5252
5253 static void si_create_function(struct si_shader_context *ctx,
5254 LLVMTypeRef *returns, unsigned num_returns,
5255 LLVMTypeRef *params, unsigned num_params,
5256 int last_array_pointer, int last_sgpr)
5257 {
5258 int i;
5259
5260 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5261 params, num_params);
5262 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5263 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5264
5265 for (i = 0; i <= last_sgpr; ++i) {
5266 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5267
5268 /* We tell llvm that array inputs are passed by value to allow Sinking pass
5269 * to move load. Inputs are constant so this is fine. */
5270 if (i <= last_array_pointer)
5271 LLVMAddAttribute(P, LLVMByValAttribute);
5272 else
5273 LLVMAddAttribute(P, LLVMInRegAttribute);
5274 }
5275
5276 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5277 /* These were copied from some LLVM test. */
5278 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5279 "less-precise-fpmad",
5280 "true");
5281 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5282 "no-infs-fp-math",
5283 "true");
5284 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5285 "no-nans-fp-math",
5286 "true");
5287 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5288 "unsafe-fp-math",
5289 "true");
5290 }
5291 }
5292
5293 static void create_meta_data(struct si_shader_context *ctx)
5294 {
5295 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5296 LLVMValueRef args[3];
5297
5298 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
5299 args[1] = 0;
5300 args[2] = lp_build_const_int32(gallivm, 1);
5301
5302 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
5303
5304 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5305 "amdgpu.uniform", 14);
5306
5307 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5308 }
5309
5310 static void declare_streamout_params(struct si_shader_context *ctx,
5311 struct pipe_stream_output_info *so,
5312 LLVMTypeRef *params, LLVMTypeRef i32,
5313 unsigned *num_params)
5314 {
5315 int i;
5316
5317 /* Streamout SGPRs. */
5318 if (so->num_outputs) {
5319 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5320 params[ctx->param_streamout_config = (*num_params)++] = i32;
5321 else
5322 ctx->param_streamout_config = ctx->param_tess_offchip;
5323
5324 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5325 }
5326 /* A streamout buffer offset is loaded if the stride is non-zero. */
5327 for (i = 0; i < 4; i++) {
5328 if (!so->stride[i])
5329 continue;
5330
5331 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5332 }
5333 }
5334
5335 static unsigned llvm_get_type_size(LLVMTypeRef type)
5336 {
5337 LLVMTypeKind kind = LLVMGetTypeKind(type);
5338
5339 switch (kind) {
5340 case LLVMIntegerTypeKind:
5341 return LLVMGetIntTypeWidth(type) / 8;
5342 case LLVMFloatTypeKind:
5343 return 4;
5344 case LLVMPointerTypeKind:
5345 return 8;
5346 case LLVMVectorTypeKind:
5347 return LLVMGetVectorSize(type) *
5348 llvm_get_type_size(LLVMGetElementType(type));
5349 default:
5350 assert(0);
5351 return 0;
5352 }
5353 }
5354
5355 static void declare_tess_lds(struct si_shader_context *ctx)
5356 {
5357 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5358 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
5359 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5360
5361 /* The actual size is computed outside of the shader to reduce
5362 * the number of shader variants. */
5363 ctx->lds =
5364 LLVMAddGlobalInAddressSpace(gallivm->module,
5365 LLVMArrayType(i32, lds_size / 4),
5366 "tess_lds",
5367 LOCAL_ADDR_SPACE);
5368 }
5369
5370 static void create_function(struct si_shader_context *ctx)
5371 {
5372 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5373 struct gallivm_state *gallivm = bld_base->base.gallivm;
5374 struct si_shader *shader = ctx->shader;
5375 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5376 LLVMTypeRef returns[16+32*4];
5377 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
5378 unsigned num_returns = 0;
5379
5380 v3i32 = LLVMVectorType(ctx->i32, 3);
5381
5382 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5383 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5384 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5385 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5386 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5387 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
5388
5389 switch (ctx->type) {
5390 case PIPE_SHADER_VERTEX:
5391 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5392 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
5393 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5394 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5395 num_params = SI_PARAM_START_INSTANCE+1;
5396
5397 if (shader->key.vs.as_es) {
5398 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5399 } else if (shader->key.vs.as_ls) {
5400 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5401 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5402 } else {
5403 if (ctx->is_gs_copy_shader) {
5404 last_array_pointer = SI_PARAM_RW_BUFFERS;
5405 num_params = SI_PARAM_RW_BUFFERS+1;
5406 } else {
5407 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5408 num_params = SI_PARAM_VS_STATE_BITS+1;
5409 }
5410
5411 /* The locations of the other parameters are assigned dynamically. */
5412 declare_streamout_params(ctx, &shader->selector->so,
5413 params, ctx->i32, &num_params);
5414 }
5415
5416 last_sgpr = num_params-1;
5417
5418 /* VGPRs */
5419 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5420 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5421 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5422 params[ctx->param_instance_id = num_params++] = ctx->i32;
5423
5424 if (!ctx->is_monolithic &&
5425 !ctx->is_gs_copy_shader) {
5426 /* Vertex load indices. */
5427 ctx->param_vertex_index0 = num_params;
5428
5429 for (i = 0; i < shader->selector->info.num_inputs; i++)
5430 params[num_params++] = ctx->i32;
5431
5432 /* PrimitiveID output. */
5433 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5434 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5435 returns[num_returns++] = ctx->f32;
5436 }
5437 break;
5438
5439 case PIPE_SHADER_TESS_CTRL:
5440 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5441 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5442 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5443 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5444 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5445 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5446 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5447
5448 /* VGPRs */
5449 params[SI_PARAM_PATCH_ID] = ctx->i32;
5450 params[SI_PARAM_REL_IDS] = ctx->i32;
5451 num_params = SI_PARAM_REL_IDS+1;
5452
5453 if (!ctx->is_monolithic) {
5454 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5455 * placed after the user SGPRs.
5456 */
5457 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5458 returns[num_returns++] = ctx->i32; /* SGPRs */
5459
5460 for (i = 0; i < 3; i++)
5461 returns[num_returns++] = ctx->f32; /* VGPRs */
5462 }
5463 break;
5464
5465 case PIPE_SHADER_TESS_EVAL:
5466 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5467 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5468
5469 if (shader->key.tes.as_es) {
5470 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5471 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5472 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5473 } else {
5474 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5475 declare_streamout_params(ctx, &shader->selector->so,
5476 params, ctx->i32, &num_params);
5477 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5478 }
5479 last_sgpr = num_params - 1;
5480
5481 /* VGPRs */
5482 params[ctx->param_tes_u = num_params++] = ctx->f32;
5483 params[ctx->param_tes_v = num_params++] = ctx->f32;
5484 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5485 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5486
5487 /* PrimitiveID output. */
5488 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5489 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5490 returns[num_returns++] = ctx->f32;
5491 break;
5492
5493 case PIPE_SHADER_GEOMETRY:
5494 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5495 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5496 last_sgpr = SI_PARAM_GS_WAVE_ID;
5497
5498 /* VGPRs */
5499 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5500 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5501 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5502 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5503 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5504 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5505 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5506 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5507 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5508 break;
5509
5510 case PIPE_SHADER_FRAGMENT:
5511 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5512 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5513 last_sgpr = SI_PARAM_PRIM_MASK;
5514 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5515 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5516 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5517 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5518 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5519 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5520 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5521 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5522 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5523 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5524 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5525 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5526 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5527 params[SI_PARAM_ANCILLARY] = ctx->i32;
5528 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5529 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5530 num_params = SI_PARAM_POS_FIXED_PT+1;
5531
5532 if (!ctx->is_monolithic) {
5533 /* Color inputs from the prolog. */
5534 if (shader->selector->info.colors_read) {
5535 unsigned num_color_elements =
5536 util_bitcount(shader->selector->info.colors_read);
5537
5538 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5539 for (i = 0; i < num_color_elements; i++)
5540 params[num_params++] = ctx->f32;
5541 }
5542
5543 /* Outputs for the epilog. */
5544 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5545 num_returns =
5546 num_return_sgprs +
5547 util_bitcount(shader->selector->info.colors_written) * 4 +
5548 shader->selector->info.writes_z +
5549 shader->selector->info.writes_stencil +
5550 shader->selector->info.writes_samplemask +
5551 1 /* SampleMaskIn */;
5552
5553 num_returns = MAX2(num_returns,
5554 num_return_sgprs +
5555 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5556
5557 for (i = 0; i < num_return_sgprs; i++)
5558 returns[i] = ctx->i32;
5559 for (; i < num_returns; i++)
5560 returns[i] = ctx->f32;
5561 }
5562 break;
5563
5564 case PIPE_SHADER_COMPUTE:
5565 params[SI_PARAM_GRID_SIZE] = v3i32;
5566 params[SI_PARAM_BLOCK_ID] = v3i32;
5567 last_sgpr = SI_PARAM_BLOCK_ID;
5568
5569 params[SI_PARAM_THREAD_ID] = v3i32;
5570 num_params = SI_PARAM_THREAD_ID + 1;
5571 break;
5572 default:
5573 assert(0 && "unimplemented shader");
5574 return;
5575 }
5576
5577 assert(num_params <= ARRAY_SIZE(params));
5578
5579 si_create_function(ctx, returns, num_returns, params,
5580 num_params, last_array_pointer, last_sgpr);
5581
5582 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5583 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5584 !ctx->is_monolithic) {
5585 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5586 "InitialPSInputAddr",
5587 S_0286D0_PERSP_SAMPLE_ENA(1) |
5588 S_0286D0_PERSP_CENTER_ENA(1) |
5589 S_0286D0_PERSP_CENTROID_ENA(1) |
5590 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5591 S_0286D0_LINEAR_CENTER_ENA(1) |
5592 S_0286D0_LINEAR_CENTROID_ENA(1) |
5593 S_0286D0_FRONT_FACE_ENA(1) |
5594 S_0286D0_POS_FIXED_PT_ENA(1));
5595 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5596 const unsigned *properties = shader->selector->info.properties;
5597 unsigned max_work_group_size =
5598 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5599 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5600 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5601
5602 assert(max_work_group_size);
5603
5604 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5605 "amdgpu-max-work-group-size",
5606 max_work_group_size);
5607 }
5608
5609 shader->info.num_input_sgprs = 0;
5610 shader->info.num_input_vgprs = 0;
5611
5612 for (i = 0; i <= last_sgpr; ++i)
5613 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5614
5615 /* Unused fragment shader inputs are eliminated by the compiler,
5616 * so we don't know yet how many there will be.
5617 */
5618 if (ctx->type != PIPE_SHADER_FRAGMENT)
5619 for (; i < num_params; ++i)
5620 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5621
5622 if (bld_base->info &&
5623 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5624 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5625 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5626 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5627 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5628 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5629 ctx->lds =
5630 LLVMAddGlobalInAddressSpace(gallivm->module,
5631 LLVMArrayType(ctx->i32, 64),
5632 "ddxy_lds",
5633 LOCAL_ADDR_SPACE);
5634
5635 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5636 ctx->type == PIPE_SHADER_TESS_CTRL ||
5637 ctx->type == PIPE_SHADER_TESS_EVAL)
5638 declare_tess_lds(ctx);
5639 }
5640
5641 static void preload_constants(struct si_shader_context *ctx)
5642 {
5643 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5644 struct gallivm_state *gallivm = bld_base->base.gallivm;
5645 const struct tgsi_shader_info *info = bld_base->info;
5646 unsigned buf;
5647 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5648
5649 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5650 unsigned i, num_const = info->const_file_max[buf] + 1;
5651
5652 if (num_const == 0)
5653 continue;
5654
5655 /* Allocate space for the constant values */
5656 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5657
5658 /* Load the resource descriptor */
5659 ctx->const_buffers[buf] =
5660 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5661
5662 /* Load the constants, we rely on the code sinking to do the rest */
5663 for (i = 0; i < num_const * 4; ++i) {
5664 ctx->constants[buf][i] =
5665 buffer_load_const(gallivm->builder,
5666 ctx->const_buffers[buf],
5667 lp_build_const_int32(gallivm, i * 4),
5668 ctx->f32);
5669 }
5670 }
5671 }
5672
5673 static void preload_shader_buffers(struct si_shader_context *ctx)
5674 {
5675 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5676 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5677 int buf, maxbuf;
5678
5679 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5680 SI_NUM_SHADER_BUFFERS - 1);
5681 for (buf = 0; buf <= maxbuf; ++buf) {
5682 ctx->shader_buffers[buf] =
5683 build_indexed_load_const(
5684 ctx, ptr, lp_build_const_int32(gallivm, buf));
5685 }
5686 }
5687
5688 static void preload_samplers(struct si_shader_context *ctx)
5689 {
5690 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5691 struct gallivm_state *gallivm = bld_base->base.gallivm;
5692 const struct tgsi_shader_info *info = bld_base->info;
5693 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5694 LLVMValueRef offset;
5695
5696 if (num_samplers == 0)
5697 return;
5698
5699 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5700 for (i = 0; i < num_samplers; ++i) {
5701 /* Resource */
5702 offset = lp_build_const_int32(gallivm, i);
5703 ctx->sampler_views[i] =
5704 get_sampler_desc(ctx, offset, DESC_IMAGE);
5705
5706 /* FMASK resource */
5707 if (info->is_msaa_sampler[i])
5708 ctx->fmasks[i] =
5709 get_sampler_desc(ctx, offset, DESC_FMASK);
5710 else {
5711 ctx->sampler_states[i] =
5712 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5713 ctx->sampler_states[i] =
5714 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5715 ctx->sampler_states[i]);
5716 }
5717 }
5718 }
5719
5720 static void preload_images(struct si_shader_context *ctx)
5721 {
5722 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5723 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5724 struct gallivm_state *gallivm = bld_base->base.gallivm;
5725 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5726 LLVMValueRef res_ptr;
5727 unsigned i;
5728
5729 if (num_images == 0)
5730 return;
5731
5732 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5733
5734 for (i = 0; i < num_images; ++i) {
5735 /* Rely on LLVM to shrink the load for buffer resources. */
5736 LLVMValueRef rsrc =
5737 build_indexed_load_const(ctx, res_ptr,
5738 lp_build_const_int32(gallivm, i));
5739
5740 if (info->images_writemask & (1 << i) &&
5741 !(info->images_buffers & (1 << i)))
5742 rsrc = force_dcc_off(ctx, rsrc);
5743
5744 ctx->images[i] = rsrc;
5745 }
5746 }
5747
5748 static void preload_streamout_buffers(struct si_shader_context *ctx)
5749 {
5750 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5751 struct gallivm_state *gallivm = bld_base->base.gallivm;
5752 unsigned i;
5753
5754 /* Streamout can only be used if the shader is compiled as VS. */
5755 if (!ctx->shader->selector->so.num_outputs ||
5756 (ctx->type == PIPE_SHADER_VERTEX &&
5757 (ctx->shader->key.vs.as_es ||
5758 ctx->shader->key.vs.as_ls)) ||
5759 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5760 ctx->shader->key.tes.as_es))
5761 return;
5762
5763 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5764 SI_PARAM_RW_BUFFERS);
5765
5766 /* Load the resources, we rely on the code sinking to do the rest */
5767 for (i = 0; i < 4; ++i) {
5768 if (ctx->shader->selector->so.stride[i]) {
5769 LLVMValueRef offset = lp_build_const_int32(gallivm,
5770 SI_VS_STREAMOUT_BUF0 + i);
5771
5772 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5773 }
5774 }
5775 }
5776
5777 /**
5778 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5779 * for later use.
5780 */
5781 static void preload_ring_buffers(struct si_shader_context *ctx)
5782 {
5783 struct gallivm_state *gallivm =
5784 ctx->radeon_bld.soa.bld_base.base.gallivm;
5785
5786 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5787 SI_PARAM_RW_BUFFERS);
5788
5789 if ((ctx->type == PIPE_SHADER_VERTEX &&
5790 ctx->shader->key.vs.as_es) ||
5791 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5792 ctx->shader->key.tes.as_es) ||
5793 ctx->type == PIPE_SHADER_GEOMETRY) {
5794 unsigned ring =
5795 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5796 : SI_ES_RING_ESGS;
5797 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5798
5799 ctx->esgs_ring =
5800 build_indexed_load_const(ctx, buf_ptr, offset);
5801 }
5802
5803 if (ctx->is_gs_copy_shader) {
5804 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5805
5806 ctx->gsvs_ring[0] =
5807 build_indexed_load_const(ctx, buf_ptr, offset);
5808 }
5809 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5810 int i;
5811 for (i = 0; i < 4; i++) {
5812 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5813
5814 ctx->gsvs_ring[i] =
5815 build_indexed_load_const(ctx, buf_ptr, offset);
5816 }
5817 }
5818 }
5819
5820 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5821 LLVMValueRef param_rw_buffers,
5822 unsigned param_pos_fixed_pt)
5823 {
5824 struct lp_build_tgsi_context *bld_base =
5825 &ctx->radeon_bld.soa.bld_base;
5826 struct gallivm_state *gallivm = bld_base->base.gallivm;
5827 LLVMBuilderRef builder = gallivm->builder;
5828 LLVMValueRef slot, desc, offset, row, bit, address[2];
5829
5830 /* Use the fixed-point gl_FragCoord input.
5831 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5832 * per coordinate to get the repeating effect.
5833 */
5834 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5835 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5836
5837 /* Load the buffer descriptor. */
5838 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5839 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5840
5841 /* The stipple pattern is 32x32, each row has 32 bits. */
5842 offset = LLVMBuildMul(builder, address[1],
5843 LLVMConstInt(ctx->i32, 4, 0), "");
5844 row = buffer_load_const(builder, desc, offset, ctx->i32);
5845 bit = LLVMBuildLShr(builder, row, address[0], "");
5846 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5847
5848 /* The intrinsic kills the thread if arg < 0. */
5849 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5850 LLVMConstReal(ctx->f32, -1), "");
5851 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5852 }
5853
5854 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5855 struct si_shader_config *conf,
5856 unsigned symbol_offset)
5857 {
5858 unsigned i;
5859 const unsigned char *config =
5860 radeon_shader_binary_config_start(binary, symbol_offset);
5861 bool really_needs_scratch = false;
5862
5863 /* LLVM adds SGPR spills to the scratch size.
5864 * Find out if we really need the scratch buffer.
5865 */
5866 for (i = 0; i < binary->reloc_count; i++) {
5867 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5868
5869 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5870 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5871 really_needs_scratch = true;
5872 break;
5873 }
5874 }
5875
5876 /* XXX: We may be able to emit some of these values directly rather than
5877 * extracting fields to be emitted later.
5878 */
5879
5880 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5881 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5882 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5883 switch (reg) {
5884 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5885 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5886 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5887 case R_00B848_COMPUTE_PGM_RSRC1:
5888 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5889 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5890 conf->float_mode = G_00B028_FLOAT_MODE(value);
5891 conf->rsrc1 = value;
5892 break;
5893 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5894 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5895 break;
5896 case R_00B84C_COMPUTE_PGM_RSRC2:
5897 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5898 conf->rsrc2 = value;
5899 break;
5900 case R_0286CC_SPI_PS_INPUT_ENA:
5901 conf->spi_ps_input_ena = value;
5902 break;
5903 case R_0286D0_SPI_PS_INPUT_ADDR:
5904 conf->spi_ps_input_addr = value;
5905 break;
5906 case R_0286E8_SPI_TMPRING_SIZE:
5907 case R_00B860_COMPUTE_TMPRING_SIZE:
5908 /* WAVESIZE is in units of 256 dwords. */
5909 if (really_needs_scratch)
5910 conf->scratch_bytes_per_wave =
5911 G_00B860_WAVESIZE(value) * 256 * 4;
5912 break;
5913 default:
5914 {
5915 static bool printed;
5916
5917 if (!printed) {
5918 fprintf(stderr, "Warning: LLVM emitted unknown "
5919 "config register: 0x%x\n", reg);
5920 printed = true;
5921 }
5922 }
5923 break;
5924 }
5925
5926 if (!conf->spi_ps_input_addr)
5927 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5928 }
5929 }
5930
5931 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5932 struct si_shader *shader,
5933 struct si_shader_config *config,
5934 uint64_t scratch_va)
5935 {
5936 unsigned i;
5937 uint32_t scratch_rsrc_dword0 = scratch_va;
5938 uint32_t scratch_rsrc_dword1 =
5939 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5940
5941 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5942 * correctly.
5943 */
5944 if (HAVE_LLVM >= 0x0309)
5945 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5946 else
5947 scratch_rsrc_dword1 |=
5948 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5949
5950 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5951 const struct radeon_shader_reloc *reloc =
5952 &shader->binary.relocs[i];
5953 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5954 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5955 &scratch_rsrc_dword0, 4);
5956 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5957 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5958 &scratch_rsrc_dword1, 4);
5959 }
5960 }
5961 }
5962
5963 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5964 {
5965 unsigned size = shader->binary.code_size;
5966
5967 if (shader->prolog)
5968 size += shader->prolog->binary.code_size;
5969 if (shader->epilog)
5970 size += shader->epilog->binary.code_size;
5971 return size;
5972 }
5973
5974 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5975 {
5976 const struct radeon_shader_binary *prolog =
5977 shader->prolog ? &shader->prolog->binary : NULL;
5978 const struct radeon_shader_binary *epilog =
5979 shader->epilog ? &shader->epilog->binary : NULL;
5980 const struct radeon_shader_binary *mainb = &shader->binary;
5981 unsigned bo_size = si_get_shader_binary_size(shader) +
5982 (!epilog ? mainb->rodata_size : 0);
5983 unsigned char *ptr;
5984
5985 assert(!prolog || !prolog->rodata_size);
5986 assert((!prolog && !epilog) || !mainb->rodata_size);
5987 assert(!epilog || !epilog->rodata_size);
5988
5989 r600_resource_reference(&shader->bo, NULL);
5990 shader->bo = si_resource_create_custom(&sscreen->b.b,
5991 PIPE_USAGE_IMMUTABLE,
5992 bo_size);
5993 if (!shader->bo)
5994 return -ENOMEM;
5995
5996 /* Upload. */
5997 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5998 PIPE_TRANSFER_READ_WRITE);
5999
6000 if (prolog) {
6001 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6002 ptr += prolog->code_size;
6003 }
6004
6005 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6006 ptr += mainb->code_size;
6007
6008 if (epilog)
6009 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6010 else if (mainb->rodata_size > 0)
6011 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6012
6013 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6014 return 0;
6015 }
6016
6017 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6018 struct pipe_debug_callback *debug,
6019 const char *name, FILE *file)
6020 {
6021 char *line, *p;
6022 unsigned i, count;
6023
6024 if (binary->disasm_string) {
6025 fprintf(file, "Shader %s disassembly:\n", name);
6026 fprintf(file, "%s", binary->disasm_string);
6027
6028 if (debug && debug->debug_message) {
6029 /* Very long debug messages are cut off, so send the
6030 * disassembly one line at a time. This causes more
6031 * overhead, but on the plus side it simplifies
6032 * parsing of resulting logs.
6033 */
6034 pipe_debug_message(debug, SHADER_INFO,
6035 "Shader Disassembly Begin");
6036
6037 line = binary->disasm_string;
6038 while (*line) {
6039 p = util_strchrnul(line, '\n');
6040 count = p - line;
6041
6042 if (count) {
6043 pipe_debug_message(debug, SHADER_INFO,
6044 "%.*s", count, line);
6045 }
6046
6047 if (!*p)
6048 break;
6049 line = p + 1;
6050 }
6051
6052 pipe_debug_message(debug, SHADER_INFO,
6053 "Shader Disassembly End");
6054 }
6055 } else {
6056 fprintf(file, "Shader %s binary:\n", name);
6057 for (i = 0; i < binary->code_size; i += 4) {
6058 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6059 binary->code[i + 3], binary->code[i + 2],
6060 binary->code[i + 1], binary->code[i]);
6061 }
6062 }
6063 }
6064
6065 static void si_shader_dump_stats(struct si_screen *sscreen,
6066 struct si_shader_config *conf,
6067 unsigned num_inputs,
6068 unsigned code_size,
6069 struct pipe_debug_callback *debug,
6070 unsigned processor,
6071 FILE *file)
6072 {
6073 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6074 unsigned lds_per_wave = 0;
6075 unsigned max_simd_waves = 10;
6076 /* Assuming SGPRs aren't spilled. */
6077 unsigned spilled_vgprs = conf->scratch_bytes_per_wave / 64 / 4;
6078
6079 /* Compute LDS usage for PS. */
6080 if (processor == PIPE_SHADER_FRAGMENT) {
6081 /* The minimum usage per wave is (num_inputs * 48). The maximum
6082 * usage is (num_inputs * 48 * 16).
6083 * We can get anything in between and it varies between waves.
6084 *
6085 * The 48 bytes per input for a single primitive is equal to
6086 * 4 bytes/component * 4 components/input * 3 points.
6087 *
6088 * Other stages don't know the size at compile time or don't
6089 * allocate LDS per wave, but instead they do it per thread group.
6090 */
6091 lds_per_wave = conf->lds_size * lds_increment +
6092 align(num_inputs * 48, lds_increment);
6093 }
6094
6095 /* Compute the per-SIMD wave counts. */
6096 if (conf->num_sgprs) {
6097 if (sscreen->b.chip_class >= VI)
6098 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6099 else
6100 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6101 }
6102
6103 if (conf->num_vgprs)
6104 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6105
6106 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6107 * that PS can use.
6108 */
6109 if (lds_per_wave)
6110 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6111
6112 if (file != stderr ||
6113 r600_can_dump_shader(&sscreen->b, processor)) {
6114 if (processor == PIPE_SHADER_FRAGMENT) {
6115 fprintf(file, "*** SHADER CONFIG ***\n"
6116 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6117 "SPI_PS_INPUT_ENA = 0x%04x\n",
6118 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6119 }
6120
6121 fprintf(file, "*** SHADER STATS ***\n"
6122 "SGPRS: %d\n"
6123 "VGPRS: %d\n"
6124 "Spilled VGPRs: %d\n"
6125 "Code Size: %d bytes\n"
6126 "LDS: %d blocks\n"
6127 "Scratch: %d bytes per wave\n"
6128 "Max Waves: %d\n"
6129 "********************\n",
6130 conf->num_sgprs, conf->num_vgprs, spilled_vgprs, code_size,
6131 conf->lds_size, conf->scratch_bytes_per_wave,
6132 max_simd_waves);
6133 }
6134
6135 pipe_debug_message(debug, SHADER_INFO,
6136 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6137 "LDS: %d Scratch: %d Max Waves: %d Spilled VGPRs: %d",
6138 conf->num_sgprs, conf->num_vgprs, code_size,
6139 conf->lds_size, conf->scratch_bytes_per_wave,
6140 max_simd_waves, spilled_vgprs);
6141 }
6142
6143 static const char *si_get_shader_name(struct si_shader *shader,
6144 unsigned processor)
6145 {
6146 switch (processor) {
6147 case PIPE_SHADER_VERTEX:
6148 if (shader->key.vs.as_es)
6149 return "Vertex Shader as ES";
6150 else if (shader->key.vs.as_ls)
6151 return "Vertex Shader as LS";
6152 else
6153 return "Vertex Shader as VS";
6154 case PIPE_SHADER_TESS_CTRL:
6155 return "Tessellation Control Shader";
6156 case PIPE_SHADER_TESS_EVAL:
6157 if (shader->key.tes.as_es)
6158 return "Tessellation Evaluation Shader as ES";
6159 else
6160 return "Tessellation Evaluation Shader as VS";
6161 case PIPE_SHADER_GEOMETRY:
6162 if (shader->gs_copy_shader == NULL)
6163 return "GS Copy Shader as VS";
6164 else
6165 return "Geometry Shader";
6166 case PIPE_SHADER_FRAGMENT:
6167 return "Pixel Shader";
6168 case PIPE_SHADER_COMPUTE:
6169 return "Compute Shader";
6170 default:
6171 return "Unknown Shader";
6172 }
6173 }
6174
6175 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6176 struct pipe_debug_callback *debug, unsigned processor,
6177 FILE *file)
6178 {
6179 if (file != stderr ||
6180 (r600_can_dump_shader(&sscreen->b, processor) &&
6181 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6182 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6183
6184 if (shader->prolog)
6185 si_shader_dump_disassembly(&shader->prolog->binary,
6186 debug, "prolog", file);
6187
6188 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6189
6190 if (shader->epilog)
6191 si_shader_dump_disassembly(&shader->epilog->binary,
6192 debug, "epilog", file);
6193 fprintf(file, "\n");
6194 }
6195
6196 si_shader_dump_stats(sscreen, &shader->config,
6197 shader->selector ? shader->selector->info.num_inputs : 0,
6198 si_get_shader_binary_size(shader), debug, processor,
6199 file);
6200 }
6201
6202 int si_compile_llvm(struct si_screen *sscreen,
6203 struct radeon_shader_binary *binary,
6204 struct si_shader_config *conf,
6205 LLVMTargetMachineRef tm,
6206 LLVMModuleRef mod,
6207 struct pipe_debug_callback *debug,
6208 unsigned processor,
6209 const char *name)
6210 {
6211 int r = 0;
6212 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6213
6214 if (r600_can_dump_shader(&sscreen->b, processor)) {
6215 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6216
6217 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6218 fprintf(stderr, "%s LLVM IR:\n\n", name);
6219 LLVMDumpModule(mod);
6220 fprintf(stderr, "\n");
6221 }
6222 }
6223
6224 if (!si_replace_shader(count, binary)) {
6225 r = radeon_llvm_compile(mod, binary, tm, debug);
6226 if (r)
6227 return r;
6228 }
6229
6230 si_shader_binary_read_config(binary, conf, 0);
6231
6232 /* Enable 64-bit and 16-bit denormals, because there is no performance
6233 * cost.
6234 *
6235 * If denormals are enabled, all floating-point output modifiers are
6236 * ignored.
6237 *
6238 * Don't enable denormals for 32-bit floats, because:
6239 * - Floating-point output modifiers would be ignored by the hw.
6240 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6241 * have to stop using those.
6242 * - SI & CI would be very slow.
6243 */
6244 conf->float_mode |= V_00B028_FP_64_DENORMS;
6245
6246 FREE(binary->config);
6247 FREE(binary->global_symbol_offsets);
6248 binary->config = NULL;
6249 binary->global_symbol_offsets = NULL;
6250
6251 /* Some shaders can't have rodata because their binaries can be
6252 * concatenated.
6253 */
6254 if (binary->rodata_size &&
6255 (processor == PIPE_SHADER_VERTEX ||
6256 processor == PIPE_SHADER_TESS_CTRL ||
6257 processor == PIPE_SHADER_TESS_EVAL ||
6258 processor == PIPE_SHADER_FRAGMENT)) {
6259 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6260 return -EINVAL;
6261 }
6262
6263 return r;
6264 }
6265
6266 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6267 {
6268 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6269 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6270 else
6271 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6272 }
6273
6274 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6275 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6276 struct si_shader_context *ctx,
6277 struct si_shader *gs,
6278 struct pipe_debug_callback *debug)
6279 {
6280 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6281 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6282 struct lp_build_context *uint = &bld_base->uint_bld;
6283 struct si_shader_output_values *outputs;
6284 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6285 LLVMValueRef args[9];
6286 int i, r;
6287
6288 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6289
6290 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6291 ctx->type = PIPE_SHADER_VERTEX;
6292 ctx->is_gs_copy_shader = true;
6293
6294 create_meta_data(ctx);
6295 create_function(ctx);
6296 preload_streamout_buffers(ctx);
6297 preload_ring_buffers(ctx);
6298
6299 args[0] = ctx->gsvs_ring[0];
6300 args[1] = lp_build_mul_imm(uint,
6301 LLVMGetParam(ctx->radeon_bld.main_fn,
6302 ctx->param_vertex_id),
6303 4);
6304 args[3] = uint->zero;
6305 args[4] = uint->one; /* OFFEN */
6306 args[5] = uint->zero; /* IDXEN */
6307 args[6] = uint->one; /* GLC */
6308 args[7] = uint->one; /* SLC */
6309 args[8] = uint->zero; /* TFE */
6310
6311 /* Fetch vertex data from GSVS ring */
6312 for (i = 0; i < gsinfo->num_outputs; ++i) {
6313 unsigned chan;
6314
6315 outputs[i].name = gsinfo->output_semantic_name[i];
6316 outputs[i].sid = gsinfo->output_semantic_index[i];
6317
6318 for (chan = 0; chan < 4; chan++) {
6319 args[2] = lp_build_const_int32(gallivm,
6320 (i * 4 + chan) *
6321 gs->selector->gs_max_out_vertices * 16 * 4);
6322
6323 outputs[i].values[chan] =
6324 LLVMBuildBitCast(gallivm->builder,
6325 lp_build_intrinsic(gallivm->builder,
6326 "llvm.SI.buffer.load.dword.i32.i32",
6327 ctx->i32, args, 9,
6328 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
6329 ctx->f32, "");
6330 }
6331 }
6332
6333 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6334
6335 LLVMBuildRetVoid(gallivm->builder);
6336
6337 /* Dump LLVM IR before any optimization passes */
6338 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6339 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6340 LLVMDumpModule(bld_base->base.gallivm->module);
6341
6342 radeon_llvm_finalize_module(&ctx->radeon_bld);
6343
6344 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6345 &ctx->shader->config, ctx->tm,
6346 bld_base->base.gallivm->module,
6347 debug, PIPE_SHADER_GEOMETRY,
6348 "GS Copy Shader");
6349 if (!r) {
6350 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6351 fprintf(stderr, "GS Copy Shader:\n");
6352 si_shader_dump(sscreen, ctx->shader, debug,
6353 PIPE_SHADER_GEOMETRY, stderr);
6354 r = si_shader_binary_upload(sscreen, ctx->shader);
6355 }
6356
6357 radeon_llvm_dispose(&ctx->radeon_bld);
6358
6359 FREE(outputs);
6360 return r;
6361 }
6362
6363 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
6364 {
6365 int i;
6366
6367 fprintf(f, "SHADER KEY\n");
6368
6369 switch (shader) {
6370 case PIPE_SHADER_VERTEX:
6371 fprintf(f, " instance_divisors = {");
6372 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6373 fprintf(f, !i ? "%u" : ", %u",
6374 key->vs.prolog.instance_divisors[i]);
6375 fprintf(f, "}\n");
6376 fprintf(f, " as_es = %u\n", key->vs.as_es);
6377 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6378 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6379 break;
6380
6381 case PIPE_SHADER_TESS_CTRL:
6382 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6383 break;
6384
6385 case PIPE_SHADER_TESS_EVAL:
6386 fprintf(f, " as_es = %u\n", key->tes.as_es);
6387 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6388 break;
6389
6390 case PIPE_SHADER_GEOMETRY:
6391 case PIPE_SHADER_COMPUTE:
6392 break;
6393
6394 case PIPE_SHADER_FRAGMENT:
6395 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6396 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6397 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6398 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6399 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6400 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6401 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6402 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6403 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6404 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6405 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6406 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6407 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6408 break;
6409
6410 default:
6411 assert(0);
6412 }
6413 }
6414
6415 static void si_init_shader_ctx(struct si_shader_context *ctx,
6416 struct si_screen *sscreen,
6417 struct si_shader *shader,
6418 LLVMTargetMachineRef tm)
6419 {
6420 struct lp_build_tgsi_context *bld_base;
6421 struct lp_build_tgsi_action tmpl = {};
6422
6423 memset(ctx, 0, sizeof(*ctx));
6424 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
6425 ctx->tm = tm;
6426 ctx->screen = sscreen;
6427 if (shader && shader->selector)
6428 ctx->type = shader->selector->info.processor;
6429 else
6430 ctx->type = -1;
6431 ctx->shader = shader;
6432
6433 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6434 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6435 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6436 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6437 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6438 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6439 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6440 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6441 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6442 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6443 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6444 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6445
6446 bld_base = &ctx->radeon_bld.soa.bld_base;
6447 if (shader && shader->selector)
6448 bld_base->info = &shader->selector->info;
6449 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6450
6451 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6452 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6453 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6454
6455 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6456 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6457 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6458 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6459 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6460 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6461 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6462 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6463 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6464 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6465 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6466 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6467 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6468 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6469
6470 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6471 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6472 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6473 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6474 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6475 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6476
6477 tmpl.fetch_args = atomic_fetch_args;
6478 tmpl.emit = atomic_emit;
6479 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6480 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6481 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6482 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6483 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6484 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6485 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6486 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6487 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6488 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6489 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6490 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6491 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6492 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6493 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6494 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6495 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6496 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6497 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6498 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6499
6500 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6501
6502 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6503 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6504 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6505 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6506
6507 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6508 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6509 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6510
6511 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6512 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6513 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6514 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6515 }
6516
6517 int si_compile_tgsi_shader(struct si_screen *sscreen,
6518 LLVMTargetMachineRef tm,
6519 struct si_shader *shader,
6520 bool is_monolithic,
6521 struct pipe_debug_callback *debug)
6522 {
6523 struct si_shader_selector *sel = shader->selector;
6524 struct si_shader_context ctx;
6525 struct lp_build_tgsi_context *bld_base;
6526 LLVMModuleRef mod;
6527 int r = 0;
6528
6529 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6530 * conversion fails. */
6531 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6532 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6533 if (is_monolithic)
6534 si_dump_shader_key(sel->type, &shader->key, stderr);
6535 tgsi_dump(sel->tokens, 0);
6536 si_dump_streamout(&sel->so);
6537 }
6538
6539 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6540 ctx.is_monolithic = is_monolithic;
6541
6542 shader->info.uses_instanceid = sel->info.uses_instanceid;
6543
6544 bld_base = &ctx.radeon_bld.soa.bld_base;
6545 ctx.radeon_bld.load_system_value = declare_system_value;
6546
6547 switch (ctx.type) {
6548 case PIPE_SHADER_VERTEX:
6549 ctx.radeon_bld.load_input = declare_input_vs;
6550 if (shader->key.vs.as_ls)
6551 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6552 else if (shader->key.vs.as_es)
6553 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6554 else
6555 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6556 break;
6557 case PIPE_SHADER_TESS_CTRL:
6558 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6559 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6560 bld_base->emit_store = store_output_tcs;
6561 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6562 break;
6563 case PIPE_SHADER_TESS_EVAL:
6564 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6565 if (shader->key.tes.as_es)
6566 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6567 else
6568 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6569 break;
6570 case PIPE_SHADER_GEOMETRY:
6571 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6572 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6573 break;
6574 case PIPE_SHADER_FRAGMENT:
6575 ctx.radeon_bld.load_input = declare_input_fs;
6576 if (is_monolithic)
6577 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6578 else
6579 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6580 break;
6581 case PIPE_SHADER_COMPUTE:
6582 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6583 break;
6584 default:
6585 assert(!"Unsupported shader type");
6586 return -1;
6587 }
6588
6589 create_meta_data(&ctx);
6590 create_function(&ctx);
6591 preload_constants(&ctx);
6592 preload_shader_buffers(&ctx);
6593 preload_samplers(&ctx);
6594 preload_images(&ctx);
6595 preload_streamout_buffers(&ctx);
6596 preload_ring_buffers(&ctx);
6597
6598 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6599 shader->key.ps.prolog.poly_stipple) {
6600 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6601 SI_PARAM_RW_BUFFERS);
6602 si_llvm_emit_polygon_stipple(&ctx, list,
6603 SI_PARAM_POS_FIXED_PT);
6604 }
6605
6606 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6607 int i;
6608 for (i = 0; i < 4; i++) {
6609 ctx.gs_next_vertex[i] =
6610 lp_build_alloca(bld_base->base.gallivm,
6611 ctx.i32, "");
6612 }
6613 }
6614
6615 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6616 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6617 goto out;
6618 }
6619
6620 si_llvm_build_ret(&ctx, ctx.return_value);
6621 mod = bld_base->base.gallivm->module;
6622
6623 /* Dump LLVM IR before any optimization passes */
6624 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6625 r600_can_dump_shader(&sscreen->b, ctx.type))
6626 LLVMDumpModule(mod);
6627
6628 radeon_llvm_finalize_module(&ctx.radeon_bld);
6629
6630 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6631 mod, debug, ctx.type, "TGSI shader");
6632 if (r) {
6633 fprintf(stderr, "LLVM failed to compile shader\n");
6634 goto out;
6635 }
6636
6637 radeon_llvm_dispose(&ctx.radeon_bld);
6638
6639 /* Add the scratch offset to input SGPRs. */
6640 if (shader->config.scratch_bytes_per_wave)
6641 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6642
6643 /* Calculate the number of fragment input VGPRs. */
6644 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6645 shader->info.num_input_vgprs = 0;
6646 shader->info.face_vgpr_index = -1;
6647
6648 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6649 shader->info.num_input_vgprs += 2;
6650 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6651 shader->info.num_input_vgprs += 2;
6652 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6653 shader->info.num_input_vgprs += 2;
6654 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6655 shader->info.num_input_vgprs += 3;
6656 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6657 shader->info.num_input_vgprs += 2;
6658 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6659 shader->info.num_input_vgprs += 2;
6660 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6661 shader->info.num_input_vgprs += 2;
6662 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6663 shader->info.num_input_vgprs += 1;
6664 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6665 shader->info.num_input_vgprs += 1;
6666 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6667 shader->info.num_input_vgprs += 1;
6668 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6669 shader->info.num_input_vgprs += 1;
6670 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6671 shader->info.num_input_vgprs += 1;
6672 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6673 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6674 shader->info.num_input_vgprs += 1;
6675 }
6676 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6677 shader->info.num_input_vgprs += 1;
6678 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6679 shader->info.num_input_vgprs += 1;
6680 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6681 shader->info.num_input_vgprs += 1;
6682 }
6683
6684 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6685 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6686 shader->gs_copy_shader->selector = shader->selector;
6687 ctx.shader = shader->gs_copy_shader;
6688 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6689 shader, debug))) {
6690 free(shader->gs_copy_shader);
6691 shader->gs_copy_shader = NULL;
6692 goto out;
6693 }
6694 }
6695
6696 out:
6697 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6698 FREE(ctx.constants[i]);
6699 return r;
6700 }
6701
6702 /**
6703 * Create, compile and return a shader part (prolog or epilog).
6704 *
6705 * \param sscreen screen
6706 * \param list list of shader parts of the same category
6707 * \param key shader part key
6708 * \param tm LLVM target machine
6709 * \param debug debug callback
6710 * \param compile the callback responsible for compilation
6711 * \return non-NULL on success
6712 */
6713 static struct si_shader_part *
6714 si_get_shader_part(struct si_screen *sscreen,
6715 struct si_shader_part **list,
6716 union si_shader_part_key *key,
6717 LLVMTargetMachineRef tm,
6718 struct pipe_debug_callback *debug,
6719 bool (*compile)(struct si_screen *,
6720 LLVMTargetMachineRef,
6721 struct pipe_debug_callback *,
6722 struct si_shader_part *))
6723 {
6724 struct si_shader_part *result;
6725
6726 pipe_mutex_lock(sscreen->shader_parts_mutex);
6727
6728 /* Find existing. */
6729 for (result = *list; result; result = result->next) {
6730 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6731 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6732 return result;
6733 }
6734 }
6735
6736 /* Compile a new one. */
6737 result = CALLOC_STRUCT(si_shader_part);
6738 result->key = *key;
6739 if (!compile(sscreen, tm, debug, result)) {
6740 FREE(result);
6741 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6742 return NULL;
6743 }
6744
6745 result->next = *list;
6746 *list = result;
6747 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6748 return result;
6749 }
6750
6751 /**
6752 * Create a vertex shader prolog.
6753 *
6754 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6755 * All inputs are returned unmodified. The vertex load indices are
6756 * stored after them, which will used by the API VS for fetching inputs.
6757 *
6758 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6759 * input_v0,
6760 * input_v1,
6761 * input_v2,
6762 * input_v3,
6763 * (VertexID + BaseVertex),
6764 * (InstanceID + StartInstance),
6765 * (InstanceID / 2 + StartInstance)
6766 */
6767 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6768 LLVMTargetMachineRef tm,
6769 struct pipe_debug_callback *debug,
6770 struct si_shader_part *out)
6771 {
6772 union si_shader_part_key *key = &out->key;
6773 struct si_shader shader = {};
6774 struct si_shader_context ctx;
6775 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6776 LLVMTypeRef *params, *returns;
6777 LLVMValueRef ret, func;
6778 int last_sgpr, num_params, num_returns, i;
6779 bool status = true;
6780
6781 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6782 ctx.type = PIPE_SHADER_VERTEX;
6783 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6784 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6785
6786 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6787 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6788 sizeof(LLVMTypeRef));
6789 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6790 key->vs_prolog.last_input + 1) *
6791 sizeof(LLVMTypeRef));
6792 num_params = 0;
6793 num_returns = 0;
6794
6795 /* Declare input and output SGPRs. */
6796 num_params = 0;
6797 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6798 params[num_params++] = ctx.i32;
6799 returns[num_returns++] = ctx.i32;
6800 }
6801 last_sgpr = num_params - 1;
6802
6803 /* 4 preloaded VGPRs (outputs must be floats) */
6804 for (i = 0; i < 4; i++) {
6805 params[num_params++] = ctx.i32;
6806 returns[num_returns++] = ctx.f32;
6807 }
6808
6809 /* Vertex load indices. */
6810 for (i = 0; i <= key->vs_prolog.last_input; i++)
6811 returns[num_returns++] = ctx.f32;
6812
6813 /* Create the function. */
6814 si_create_function(&ctx, returns, num_returns, params,
6815 num_params, -1, last_sgpr);
6816 func = ctx.radeon_bld.main_fn;
6817
6818 /* Copy inputs to outputs. This should be no-op, as the registers match,
6819 * but it will prevent the compiler from overwriting them unintentionally.
6820 */
6821 ret = ctx.return_value;
6822 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6823 LLVMValueRef p = LLVMGetParam(func, i);
6824 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6825 }
6826 for (i = num_params - 4; i < num_params; i++) {
6827 LLVMValueRef p = LLVMGetParam(func, i);
6828 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6829 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6830 }
6831
6832 /* Compute vertex load indices from instance divisors. */
6833 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6834 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6835 LLVMValueRef index;
6836
6837 if (divisor) {
6838 /* InstanceID / Divisor + StartInstance */
6839 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6840 SI_SGPR_START_INSTANCE,
6841 divisor);
6842 } else {
6843 /* VertexID + BaseVertex */
6844 index = LLVMBuildAdd(gallivm->builder,
6845 LLVMGetParam(func, ctx.param_vertex_id),
6846 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6847 }
6848
6849 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6850 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6851 num_params++, "");
6852 }
6853
6854 /* Compile. */
6855 si_llvm_build_ret(&ctx, ret);
6856 radeon_llvm_finalize_module(&ctx.radeon_bld);
6857
6858 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6859 gallivm->module, debug, ctx.type,
6860 "Vertex Shader Prolog"))
6861 status = false;
6862
6863 radeon_llvm_dispose(&ctx.radeon_bld);
6864 return status;
6865 }
6866
6867 /**
6868 * Compile the vertex shader epilog. This is also used by the tessellation
6869 * evaluation shader compiled as VS.
6870 *
6871 * The input is PrimitiveID.
6872 *
6873 * If PrimitiveID is required by the pixel shader, export it.
6874 * Otherwise, do nothing.
6875 */
6876 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6877 LLVMTargetMachineRef tm,
6878 struct pipe_debug_callback *debug,
6879 struct si_shader_part *out)
6880 {
6881 union si_shader_part_key *key = &out->key;
6882 struct si_shader_context ctx;
6883 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6884 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6885 LLVMTypeRef params[5];
6886 int num_params, i;
6887 bool status = true;
6888
6889 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6890 ctx.type = PIPE_SHADER_VERTEX;
6891
6892 /* Declare input VGPRs. */
6893 num_params = key->vs_epilog.states.export_prim_id ?
6894 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6895 assert(num_params <= ARRAY_SIZE(params));
6896
6897 for (i = 0; i < num_params; i++)
6898 params[i] = ctx.f32;
6899
6900 /* Create the function. */
6901 si_create_function(&ctx, NULL, 0, params, num_params,
6902 -1, -1);
6903
6904 /* Emit exports. */
6905 if (key->vs_epilog.states.export_prim_id) {
6906 struct lp_build_context *base = &bld_base->base;
6907 struct lp_build_context *uint = &bld_base->uint_bld;
6908 LLVMValueRef args[9];
6909
6910 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6911 args[1] = uint->zero; /* whether the EXEC mask is valid */
6912 args[2] = uint->zero; /* DONE bit */
6913 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6914 key->vs_epilog.prim_id_param_offset);
6915 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6916 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6917 VS_EPILOG_PRIMID_LOC); /* X */
6918 args[6] = uint->undef; /* Y */
6919 args[7] = uint->undef; /* Z */
6920 args[8] = uint->undef; /* W */
6921
6922 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6923 LLVMVoidTypeInContext(base->gallivm->context),
6924 args, 9, 0);
6925 }
6926
6927 /* Compile. */
6928 LLVMBuildRetVoid(gallivm->builder);
6929 radeon_llvm_finalize_module(&ctx.radeon_bld);
6930
6931 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6932 gallivm->module, debug, ctx.type,
6933 "Vertex Shader Epilog"))
6934 status = false;
6935
6936 radeon_llvm_dispose(&ctx.radeon_bld);
6937 return status;
6938 }
6939
6940 /**
6941 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6942 */
6943 static bool si_get_vs_epilog(struct si_screen *sscreen,
6944 LLVMTargetMachineRef tm,
6945 struct si_shader *shader,
6946 struct pipe_debug_callback *debug,
6947 struct si_vs_epilog_bits *states)
6948 {
6949 union si_shader_part_key epilog_key;
6950
6951 memset(&epilog_key, 0, sizeof(epilog_key));
6952 epilog_key.vs_epilog.states = *states;
6953
6954 /* Set up the PrimitiveID output. */
6955 if (shader->key.vs.epilog.export_prim_id) {
6956 unsigned index = shader->selector->info.num_outputs;
6957 unsigned offset = shader->info.nr_param_exports++;
6958
6959 epilog_key.vs_epilog.prim_id_param_offset = offset;
6960 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6961 shader->info.vs_output_param_offset[index] = offset;
6962 }
6963
6964 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
6965 &epilog_key, tm, debug,
6966 si_compile_vs_epilog);
6967 return shader->epilog != NULL;
6968 }
6969
6970 /**
6971 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6972 */
6973 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6974 LLVMTargetMachineRef tm,
6975 struct si_shader *shader,
6976 struct pipe_debug_callback *debug)
6977 {
6978 struct tgsi_shader_info *info = &shader->selector->info;
6979 union si_shader_part_key prolog_key;
6980 unsigned i;
6981
6982 /* Get the prolog. */
6983 memset(&prolog_key, 0, sizeof(prolog_key));
6984 prolog_key.vs_prolog.states = shader->key.vs.prolog;
6985 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6986 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6987
6988 /* The prolog is a no-op if there are no inputs. */
6989 if (info->num_inputs) {
6990 shader->prolog =
6991 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6992 &prolog_key, tm, debug,
6993 si_compile_vs_prolog);
6994 if (!shader->prolog)
6995 return false;
6996 }
6997
6998 /* Get the epilog. */
6999 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7000 !si_get_vs_epilog(sscreen, tm, shader, debug,
7001 &shader->key.vs.epilog))
7002 return false;
7003
7004 /* Set the instanceID flag. */
7005 for (i = 0; i < info->num_inputs; i++)
7006 if (prolog_key.vs_prolog.states.instance_divisors[i])
7007 shader->info.uses_instanceid = true;
7008
7009 return true;
7010 }
7011
7012 /**
7013 * Select and compile (or reuse) TES parts (epilog).
7014 */
7015 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7016 LLVMTargetMachineRef tm,
7017 struct si_shader *shader,
7018 struct pipe_debug_callback *debug)
7019 {
7020 if (shader->key.tes.as_es)
7021 return true;
7022
7023 /* TES compiled as VS. */
7024 return si_get_vs_epilog(sscreen, tm, shader, debug,
7025 &shader->key.tes.epilog);
7026 }
7027
7028 /**
7029 * Compile the TCS epilog. This writes tesselation factors to memory based on
7030 * the output primitive type of the tesselator (determined by TES).
7031 */
7032 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7033 LLVMTargetMachineRef tm,
7034 struct pipe_debug_callback *debug,
7035 struct si_shader_part *out)
7036 {
7037 union si_shader_part_key *key = &out->key;
7038 struct si_shader shader = {};
7039 struct si_shader_context ctx;
7040 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7041 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7042 LLVMTypeRef params[16];
7043 LLVMValueRef func;
7044 int last_array_pointer, last_sgpr, num_params;
7045 bool status = true;
7046
7047 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7048 ctx.type = PIPE_SHADER_TESS_CTRL;
7049 shader.key.tcs.epilog = key->tcs_epilog.states;
7050
7051 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7052 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7053 last_array_pointer = SI_PARAM_RW_BUFFERS;
7054 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7055 params[SI_PARAM_SAMPLERS] = ctx.i64;
7056 params[SI_PARAM_IMAGES] = ctx.i64;
7057 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7058 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7059 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7060 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7061 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7062 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7063 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7064 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7065 num_params = last_sgpr + 1;
7066
7067 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7068 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7069 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7070
7071 /* Create the function. */
7072 si_create_function(&ctx, NULL, 0, params, num_params,
7073 last_array_pointer, last_sgpr);
7074 declare_tess_lds(&ctx);
7075 func = ctx.radeon_bld.main_fn;
7076
7077 si_write_tess_factors(bld_base,
7078 LLVMGetParam(func, last_sgpr + 1),
7079 LLVMGetParam(func, last_sgpr + 2),
7080 LLVMGetParam(func, last_sgpr + 3));
7081
7082 /* Compile. */
7083 LLVMBuildRetVoid(gallivm->builder);
7084 radeon_llvm_finalize_module(&ctx.radeon_bld);
7085
7086 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7087 gallivm->module, debug, ctx.type,
7088 "Tessellation Control Shader Epilog"))
7089 status = false;
7090
7091 radeon_llvm_dispose(&ctx.radeon_bld);
7092 return status;
7093 }
7094
7095 /**
7096 * Select and compile (or reuse) TCS parts (epilog).
7097 */
7098 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7099 LLVMTargetMachineRef tm,
7100 struct si_shader *shader,
7101 struct pipe_debug_callback *debug)
7102 {
7103 union si_shader_part_key epilog_key;
7104
7105 /* Get the epilog. */
7106 memset(&epilog_key, 0, sizeof(epilog_key));
7107 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7108
7109 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7110 &epilog_key, tm, debug,
7111 si_compile_tcs_epilog);
7112 return shader->epilog != NULL;
7113 }
7114
7115 /**
7116 * Compile the pixel shader prolog. This handles:
7117 * - two-side color selection and interpolation
7118 * - overriding interpolation parameters for the API PS
7119 * - polygon stippling
7120 *
7121 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7122 * overriden by other states. (e.g. per-sample interpolation)
7123 * Interpolated colors are stored after the preloaded VGPRs.
7124 */
7125 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7126 LLVMTargetMachineRef tm,
7127 struct pipe_debug_callback *debug,
7128 struct si_shader_part *out)
7129 {
7130 union si_shader_part_key *key = &out->key;
7131 struct si_shader shader = {};
7132 struct si_shader_context ctx;
7133 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7134 LLVMTypeRef *params;
7135 LLVMValueRef ret, func;
7136 int last_sgpr, num_params, num_returns, i, num_color_channels;
7137 bool status = true;
7138
7139 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7140 ctx.type = PIPE_SHADER_FRAGMENT;
7141 shader.key.ps.prolog = key->ps_prolog.states;
7142
7143 /* Number of inputs + 8 color elements. */
7144 params = alloca((key->ps_prolog.num_input_sgprs +
7145 key->ps_prolog.num_input_vgprs + 8) *
7146 sizeof(LLVMTypeRef));
7147
7148 /* Declare inputs. */
7149 num_params = 0;
7150 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7151 params[num_params++] = ctx.i32;
7152 last_sgpr = num_params - 1;
7153
7154 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7155 params[num_params++] = ctx.f32;
7156
7157 /* Declare outputs (same as inputs + add colors if needed) */
7158 num_returns = num_params;
7159 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7160 for (i = 0; i < num_color_channels; i++)
7161 params[num_returns++] = ctx.f32;
7162
7163 /* Create the function. */
7164 si_create_function(&ctx, params, num_returns, params,
7165 num_params, -1, last_sgpr);
7166 func = ctx.radeon_bld.main_fn;
7167
7168 /* Copy inputs to outputs. This should be no-op, as the registers match,
7169 * but it will prevent the compiler from overwriting them unintentionally.
7170 */
7171 ret = ctx.return_value;
7172 for (i = 0; i < num_params; i++) {
7173 LLVMValueRef p = LLVMGetParam(func, i);
7174 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7175 }
7176
7177 /* Polygon stippling. */
7178 if (key->ps_prolog.states.poly_stipple) {
7179 /* POS_FIXED_PT is always last. */
7180 unsigned pos = key->ps_prolog.num_input_sgprs +
7181 key->ps_prolog.num_input_vgprs - 1;
7182 LLVMValueRef ptr[2], list;
7183
7184 /* Get the pointer to rw buffers. */
7185 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7186 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7187 list = lp_build_gather_values(gallivm, ptr, 2);
7188 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7189 list = LLVMBuildIntToPtr(gallivm->builder, list,
7190 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7191
7192 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7193 }
7194
7195 /* Interpolate colors. */
7196 for (i = 0; i < 2; i++) {
7197 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7198 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7199 key->ps_prolog.face_vgpr_index;
7200 LLVMValueRef interp[2], color[4];
7201 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7202
7203 if (!writemask)
7204 continue;
7205
7206 /* If the interpolation qualifier is not CONSTANT (-1). */
7207 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7208 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7209 key->ps_prolog.color_interp_vgpr_index[i];
7210
7211 interp[0] = LLVMGetParam(func, interp_vgpr);
7212 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
7213 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7214 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7215 ctx.v2i32, "");
7216 }
7217
7218 /* Use the absolute location of the input. */
7219 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7220
7221 if (key->ps_prolog.states.color_two_side) {
7222 face = LLVMGetParam(func, face_vgpr);
7223 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7224 }
7225
7226 interp_fs_input(&ctx,
7227 key->ps_prolog.color_attr_index[i],
7228 TGSI_SEMANTIC_COLOR, i,
7229 key->ps_prolog.num_interp_inputs,
7230 key->ps_prolog.colors_read, interp_ij,
7231 prim_mask, face, color);
7232
7233 while (writemask) {
7234 unsigned chan = u_bit_scan(&writemask);
7235 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7236 num_params++, "");
7237 }
7238 }
7239
7240 /* Force per-sample interpolation. */
7241 if (key->ps_prolog.states.force_persp_sample_interp) {
7242 unsigned i, base = key->ps_prolog.num_input_sgprs;
7243 LLVMValueRef persp_sample[2];
7244
7245 /* Read PERSP_SAMPLE. */
7246 for (i = 0; i < 2; i++)
7247 persp_sample[i] = LLVMGetParam(func, base + i);
7248 /* Overwrite PERSP_CENTER. */
7249 for (i = 0; i < 2; i++)
7250 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7251 persp_sample[i], base + 2 + i, "");
7252 /* Overwrite PERSP_CENTROID. */
7253 for (i = 0; i < 2; i++)
7254 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7255 persp_sample[i], base + 4 + i, "");
7256 }
7257 if (key->ps_prolog.states.force_linear_sample_interp) {
7258 unsigned i, base = key->ps_prolog.num_input_sgprs;
7259 LLVMValueRef linear_sample[2];
7260
7261 /* Read LINEAR_SAMPLE. */
7262 for (i = 0; i < 2; i++)
7263 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7264 /* Overwrite LINEAR_CENTER. */
7265 for (i = 0; i < 2; i++)
7266 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7267 linear_sample[i], base + 8 + i, "");
7268 /* Overwrite LINEAR_CENTROID. */
7269 for (i = 0; i < 2; i++)
7270 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7271 linear_sample[i], base + 10 + i, "");
7272 }
7273
7274 /* Force center interpolation. */
7275 if (key->ps_prolog.states.force_persp_center_interp) {
7276 unsigned i, base = key->ps_prolog.num_input_sgprs;
7277 LLVMValueRef persp_center[2];
7278
7279 /* Read PERSP_CENTER. */
7280 for (i = 0; i < 2; i++)
7281 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7282 /* Overwrite PERSP_SAMPLE. */
7283 for (i = 0; i < 2; i++)
7284 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7285 persp_center[i], base + i, "");
7286 /* Overwrite PERSP_CENTROID. */
7287 for (i = 0; i < 2; i++)
7288 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7289 persp_center[i], base + 4 + i, "");
7290 }
7291 if (key->ps_prolog.states.force_linear_center_interp) {
7292 unsigned i, base = key->ps_prolog.num_input_sgprs;
7293 LLVMValueRef linear_center[2];
7294
7295 /* Read LINEAR_CENTER. */
7296 for (i = 0; i < 2; i++)
7297 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7298 /* Overwrite LINEAR_SAMPLE. */
7299 for (i = 0; i < 2; i++)
7300 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7301 linear_center[i], base + 6 + i, "");
7302 /* Overwrite LINEAR_CENTROID. */
7303 for (i = 0; i < 2; i++)
7304 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7305 linear_center[i], base + 10 + i, "");
7306 }
7307
7308 /* Tell LLVM to insert WQM instruction sequence when needed. */
7309 if (key->ps_prolog.wqm) {
7310 LLVMAddTargetDependentFunctionAttr(func,
7311 "amdgpu-ps-wqm-outputs", "");
7312 }
7313
7314 /* Compile. */
7315 si_llvm_build_ret(&ctx, ret);
7316 radeon_llvm_finalize_module(&ctx.radeon_bld);
7317
7318 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7319 gallivm->module, debug, ctx.type,
7320 "Fragment Shader Prolog"))
7321 status = false;
7322
7323 radeon_llvm_dispose(&ctx.radeon_bld);
7324 return status;
7325 }
7326
7327 /**
7328 * Compile the pixel shader epilog. This handles everything that must be
7329 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7330 */
7331 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7332 LLVMTargetMachineRef tm,
7333 struct pipe_debug_callback *debug,
7334 struct si_shader_part *out)
7335 {
7336 union si_shader_part_key *key = &out->key;
7337 struct si_shader shader = {};
7338 struct si_shader_context ctx;
7339 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7340 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7341 LLVMTypeRef params[16+8*4+3];
7342 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7343 int last_array_pointer, last_sgpr, num_params, i;
7344 bool status = true;
7345
7346 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7347 ctx.type = PIPE_SHADER_FRAGMENT;
7348 shader.key.ps.epilog = key->ps_epilog.states;
7349
7350 /* Declare input SGPRs. */
7351 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7352 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7353 params[SI_PARAM_SAMPLERS] = ctx.i64;
7354 params[SI_PARAM_IMAGES] = ctx.i64;
7355 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7356 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7357 last_array_pointer = -1;
7358 last_sgpr = SI_PARAM_ALPHA_REF;
7359
7360 /* Declare input VGPRs. */
7361 num_params = (last_sgpr + 1) +
7362 util_bitcount(key->ps_epilog.colors_written) * 4 +
7363 key->ps_epilog.writes_z +
7364 key->ps_epilog.writes_stencil +
7365 key->ps_epilog.writes_samplemask;
7366
7367 num_params = MAX2(num_params,
7368 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7369
7370 assert(num_params <= ARRAY_SIZE(params));
7371
7372 for (i = last_sgpr + 1; i < num_params; i++)
7373 params[i] = ctx.f32;
7374
7375 /* Create the function. */
7376 si_create_function(&ctx, NULL, 0, params, num_params,
7377 last_array_pointer, last_sgpr);
7378 /* Disable elimination of unused inputs. */
7379 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7380 "InitialPSInputAddr", 0xffffff);
7381
7382 /* Process colors. */
7383 unsigned vgpr = last_sgpr + 1;
7384 unsigned colors_written = key->ps_epilog.colors_written;
7385 int last_color_export = -1;
7386
7387 /* Find the last color export. */
7388 if (!key->ps_epilog.writes_z &&
7389 !key->ps_epilog.writes_stencil &&
7390 !key->ps_epilog.writes_samplemask) {
7391 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7392
7393 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7394 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7395 /* Just set this if any of the colorbuffers are enabled. */
7396 if (spi_format &
7397 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7398 last_color_export = 0;
7399 } else {
7400 for (i = 0; i < 8; i++)
7401 if (colors_written & (1 << i) &&
7402 (spi_format >> (i * 4)) & 0xf)
7403 last_color_export = i;
7404 }
7405 }
7406
7407 while (colors_written) {
7408 LLVMValueRef color[4];
7409 int mrt = u_bit_scan(&colors_written);
7410
7411 for (i = 0; i < 4; i++)
7412 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7413
7414 si_export_mrt_color(bld_base, color, mrt,
7415 num_params - 1,
7416 mrt == last_color_export);
7417 }
7418
7419 /* Process depth, stencil, samplemask. */
7420 if (key->ps_epilog.writes_z)
7421 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7422 if (key->ps_epilog.writes_stencil)
7423 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7424 if (key->ps_epilog.writes_samplemask)
7425 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7426
7427 if (depth || stencil || samplemask)
7428 si_export_mrt_z(bld_base, depth, stencil, samplemask);
7429 else if (last_color_export == -1)
7430 si_export_null(bld_base);
7431
7432 /* Compile. */
7433 LLVMBuildRetVoid(gallivm->builder);
7434 radeon_llvm_finalize_module(&ctx.radeon_bld);
7435
7436 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7437 gallivm->module, debug, ctx.type,
7438 "Fragment Shader Epilog"))
7439 status = false;
7440
7441 radeon_llvm_dispose(&ctx.radeon_bld);
7442 return status;
7443 }
7444
7445 /**
7446 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7447 */
7448 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7449 LLVMTargetMachineRef tm,
7450 struct si_shader *shader,
7451 struct pipe_debug_callback *debug)
7452 {
7453 struct tgsi_shader_info *info = &shader->selector->info;
7454 union si_shader_part_key prolog_key;
7455 union si_shader_part_key epilog_key;
7456 unsigned i;
7457
7458 /* Get the prolog. */
7459 memset(&prolog_key, 0, sizeof(prolog_key));
7460 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7461 prolog_key.ps_prolog.colors_read = info->colors_read;
7462 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7463 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7464 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7465 (prolog_key.ps_prolog.colors_read ||
7466 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7467 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7468 prolog_key.ps_prolog.states.force_persp_center_interp ||
7469 prolog_key.ps_prolog.states.force_linear_center_interp);
7470
7471 if (info->colors_read) {
7472 unsigned *color = shader->selector->color_attr_index;
7473
7474 if (shader->key.ps.prolog.color_two_side) {
7475 /* BCOLORs are stored after the last input. */
7476 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7477 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7478 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7479 }
7480
7481 for (i = 0; i < 2; i++) {
7482 unsigned location = info->input_interpolate_loc[color[i]];
7483
7484 if (!(info->colors_read & (0xf << i*4)))
7485 continue;
7486
7487 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7488
7489 switch (info->input_interpolate[color[i]]) {
7490 case TGSI_INTERPOLATE_CONSTANT:
7491 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7492 break;
7493 case TGSI_INTERPOLATE_PERSPECTIVE:
7494 case TGSI_INTERPOLATE_COLOR:
7495 /* Force the interpolation location for colors here. */
7496 if (shader->key.ps.prolog.force_persp_sample_interp)
7497 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7498 if (shader->key.ps.prolog.force_persp_center_interp)
7499 location = TGSI_INTERPOLATE_LOC_CENTER;
7500
7501 switch (location) {
7502 case TGSI_INTERPOLATE_LOC_SAMPLE:
7503 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7504 shader->config.spi_ps_input_ena |=
7505 S_0286CC_PERSP_SAMPLE_ENA(1);
7506 break;
7507 case TGSI_INTERPOLATE_LOC_CENTER:
7508 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7509 shader->config.spi_ps_input_ena |=
7510 S_0286CC_PERSP_CENTER_ENA(1);
7511 break;
7512 case TGSI_INTERPOLATE_LOC_CENTROID:
7513 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7514 shader->config.spi_ps_input_ena |=
7515 S_0286CC_PERSP_CENTROID_ENA(1);
7516 break;
7517 default:
7518 assert(0);
7519 }
7520 break;
7521 case TGSI_INTERPOLATE_LINEAR:
7522 /* Force the interpolation location for colors here. */
7523 if (shader->key.ps.prolog.force_linear_sample_interp)
7524 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7525 if (shader->key.ps.prolog.force_linear_center_interp)
7526 location = TGSI_INTERPOLATE_LOC_CENTER;
7527
7528 switch (location) {
7529 case TGSI_INTERPOLATE_LOC_SAMPLE:
7530 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7531 shader->config.spi_ps_input_ena |=
7532 S_0286CC_LINEAR_SAMPLE_ENA(1);
7533 break;
7534 case TGSI_INTERPOLATE_LOC_CENTER:
7535 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7536 shader->config.spi_ps_input_ena |=
7537 S_0286CC_LINEAR_CENTER_ENA(1);
7538 break;
7539 case TGSI_INTERPOLATE_LOC_CENTROID:
7540 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7541 shader->config.spi_ps_input_ena |=
7542 S_0286CC_LINEAR_CENTROID_ENA(1);
7543 break;
7544 default:
7545 assert(0);
7546 }
7547 break;
7548 default:
7549 assert(0);
7550 }
7551 }
7552 }
7553
7554 /* The prolog is a no-op if these aren't set. */
7555 if (prolog_key.ps_prolog.colors_read ||
7556 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7557 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7558 prolog_key.ps_prolog.states.force_persp_center_interp ||
7559 prolog_key.ps_prolog.states.force_linear_center_interp ||
7560 prolog_key.ps_prolog.states.poly_stipple) {
7561 shader->prolog =
7562 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7563 &prolog_key, tm, debug,
7564 si_compile_ps_prolog);
7565 if (!shader->prolog)
7566 return false;
7567 }
7568
7569 /* Get the epilog. */
7570 memset(&epilog_key, 0, sizeof(epilog_key));
7571 epilog_key.ps_epilog.colors_written = info->colors_written;
7572 epilog_key.ps_epilog.writes_z = info->writes_z;
7573 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7574 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7575 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7576
7577 shader->epilog =
7578 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7579 &epilog_key, tm, debug,
7580 si_compile_ps_epilog);
7581 if (!shader->epilog)
7582 return false;
7583
7584 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7585 if (shader->key.ps.prolog.poly_stipple) {
7586 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7587 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7588 }
7589
7590 /* Set up the enable bits for per-sample shading if needed. */
7591 if (shader->key.ps.prolog.force_persp_sample_interp &&
7592 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7593 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7594 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7595 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7596 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7597 }
7598 if (shader->key.ps.prolog.force_linear_sample_interp &&
7599 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7600 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7601 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7602 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7603 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7604 }
7605 if (shader->key.ps.prolog.force_persp_center_interp &&
7606 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7607 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7608 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7609 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7610 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7611 }
7612 if (shader->key.ps.prolog.force_linear_center_interp &&
7613 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7614 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7615 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7616 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7617 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7618 }
7619
7620 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7621 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7622 !(shader->config.spi_ps_input_ena & 0xf)) {
7623 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7624 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7625 }
7626
7627 /* At least one pair of interpolation weights must be enabled. */
7628 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7629 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7630 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7631 }
7632
7633 /* The sample mask input is always enabled, because the API shader always
7634 * passes it through to the epilog. Disable it here if it's unused.
7635 */
7636 if (!shader->key.ps.epilog.poly_line_smoothing &&
7637 !shader->selector->info.reads_samplemask)
7638 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7639
7640 return true;
7641 }
7642
7643 static void si_fix_num_sgprs(struct si_shader *shader)
7644 {
7645 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7646
7647 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7648 }
7649
7650 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7651 struct si_shader *shader,
7652 struct pipe_debug_callback *debug)
7653 {
7654 struct si_shader *mainp = shader->selector->main_shader_part;
7655 int r;
7656
7657 /* LS, ES, VS are compiled on demand if the main part hasn't been
7658 * compiled for that stage.
7659 */
7660 if (!mainp ||
7661 (shader->selector->type == PIPE_SHADER_VERTEX &&
7662 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7663 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7664 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7665 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7666 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7667 shader->key.tcs.epilog.inputs_to_copy) ||
7668 shader->selector->type == PIPE_SHADER_COMPUTE) {
7669 /* Monolithic shader (compiled as a whole, has many variants,
7670 * may take a long time to compile).
7671 */
7672 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7673 if (r)
7674 return r;
7675 } else {
7676 /* The shader consists of 2-3 parts:
7677 *
7678 * - the middle part is the user shader, it has 1 variant only
7679 * and it was compiled during the creation of the shader
7680 * selector
7681 * - the prolog part is inserted at the beginning
7682 * - the epilog part is inserted at the end
7683 *
7684 * The prolog and epilog have many (but simple) variants.
7685 */
7686
7687 /* Copy the compiled TGSI shader data over. */
7688 shader->is_binary_shared = true;
7689 shader->binary = mainp->binary;
7690 shader->config = mainp->config;
7691 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7692 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7693 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7694 memcpy(shader->info.vs_output_param_offset,
7695 mainp->info.vs_output_param_offset,
7696 sizeof(mainp->info.vs_output_param_offset));
7697 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7698 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7699 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7700
7701 /* Select prologs and/or epilogs. */
7702 switch (shader->selector->type) {
7703 case PIPE_SHADER_VERTEX:
7704 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7705 return -1;
7706 break;
7707 case PIPE_SHADER_TESS_CTRL:
7708 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7709 return -1;
7710 break;
7711 case PIPE_SHADER_TESS_EVAL:
7712 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7713 return -1;
7714 break;
7715 case PIPE_SHADER_FRAGMENT:
7716 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7717 return -1;
7718
7719 /* Make sure we have at least as many VGPRs as there
7720 * are allocated inputs.
7721 */
7722 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7723 shader->info.num_input_vgprs);
7724 break;
7725 }
7726
7727 /* Update SGPR and VGPR counts. */
7728 if (shader->prolog) {
7729 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7730 shader->prolog->config.num_sgprs);
7731 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7732 shader->prolog->config.num_vgprs);
7733 }
7734 if (shader->epilog) {
7735 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7736 shader->epilog->config.num_sgprs);
7737 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7738 shader->epilog->config.num_vgprs);
7739 }
7740 }
7741
7742 si_fix_num_sgprs(shader);
7743 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7744 stderr);
7745
7746 /* Upload. */
7747 r = si_shader_binary_upload(sscreen, shader);
7748 if (r) {
7749 fprintf(stderr, "LLVM failed to upload shader\n");
7750 return r;
7751 }
7752
7753 return 0;
7754 }
7755
7756 void si_shader_destroy(struct si_shader *shader)
7757 {
7758 if (shader->gs_copy_shader) {
7759 si_shader_destroy(shader->gs_copy_shader);
7760 FREE(shader->gs_copy_shader);
7761 }
7762
7763 if (shader->scratch_bo)
7764 r600_resource_reference(&shader->scratch_bo, NULL);
7765
7766 r600_resource_reference(&shader->bo, NULL);
7767
7768 if (!shader->is_binary_shared)
7769 radeon_shader_binary_clean(&shader->binary);
7770 }