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radeonsi: enable the barycentric optimization in all cases
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94 int param_oc_lds;
95
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
98 */
99 int param_tess_offchip;
100
101 LLVMTargetMachineRef tm;
102
103 unsigned uniform_md_kind;
104 LLVMValueRef const_md;
105 LLVMValueRef empty_md;
106 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
107 LLVMValueRef lds;
108 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
109 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
110 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
111 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
112 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
113 LLVMValueRef images[SI_NUM_IMAGES];
114 LLVMValueRef so_buffers[4];
115 LLVMValueRef esgs_ring;
116 LLVMValueRef gsvs_ring[4];
117 LLVMValueRef gs_next_vertex[4];
118 LLVMValueRef return_value;
119
120 LLVMTypeRef voidt;
121 LLVMTypeRef i1;
122 LLVMTypeRef i8;
123 LLVMTypeRef i32;
124 LLVMTypeRef i64;
125 LLVMTypeRef i128;
126 LLVMTypeRef f32;
127 LLVMTypeRef v16i8;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v4i32;
130 LLVMTypeRef v4f32;
131 LLVMTypeRef v8i32;
132
133 LLVMValueRef shared_memory;
134 };
135
136 static struct si_shader_context *si_shader_context(
137 struct lp_build_tgsi_context *bld_base)
138 {
139 return (struct si_shader_context *)bld_base;
140 }
141
142 static void si_init_shader_ctx(struct si_shader_context *ctx,
143 struct si_screen *sscreen,
144 struct si_shader *shader,
145 LLVMTargetMachineRef tm);
146
147 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
148 struct lp_build_tgsi_context *bld_base,
149 struct lp_build_emit_data *emit_data);
150
151 /* Ideally pass the sample mask input to the PS epilog as v13, which
152 * is its usual location, so that the shader doesn't have to add v_mov.
153 */
154 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
155
156 /* The VS location of the PrimitiveID input is the same in the epilog,
157 * so that the main shader part doesn't have to move it.
158 */
159 #define VS_EPILOG_PRIMID_LOC 2
160
161 #define PERSPECTIVE_BASE 0
162 #define LINEAR_BASE 9
163
164 #define SAMPLE_OFFSET 0
165 #define CENTER_OFFSET 2
166 #define CENTROID_OFSET 4
167
168 #define USE_SGPR_MAX_SUFFIX_LEN 5
169 #define CONST_ADDR_SPACE 2
170 #define LOCAL_ADDR_SPACE 3
171 #define USER_SGPR_ADDR_SPACE 8
172
173
174 #define SENDMSG_GS 2
175 #define SENDMSG_GS_DONE 3
176
177 #define SENDMSG_GS_OP_NOP (0 << 4)
178 #define SENDMSG_GS_OP_CUT (1 << 4)
179 #define SENDMSG_GS_OP_EMIT (2 << 4)
180 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
181
182 /**
183 * Returns a unique index for a semantic name and index. The index must be
184 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
185 * calculated.
186 */
187 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
188 {
189 switch (semantic_name) {
190 case TGSI_SEMANTIC_POSITION:
191 return 0;
192 case TGSI_SEMANTIC_PSIZE:
193 return 1;
194 case TGSI_SEMANTIC_CLIPDIST:
195 assert(index <= 1);
196 return 2 + index;
197 case TGSI_SEMANTIC_GENERIC:
198 if (index <= 63-4)
199 return 4 + index;
200 else
201 /* same explanation as in the default statement,
202 * the only user hitting this is st/nine.
203 */
204 return 0;
205
206 /* patch indices are completely separate and thus start from 0 */
207 case TGSI_SEMANTIC_TESSOUTER:
208 return 0;
209 case TGSI_SEMANTIC_TESSINNER:
210 return 1;
211 case TGSI_SEMANTIC_PATCH:
212 return 2 + index;
213
214 default:
215 /* Don't fail here. The result of this function is only used
216 * for LS, TCS, TES, and GS, where legacy GL semantics can't
217 * occur, but this function is called for all vertex shaders
218 * before it's known whether LS will be compiled or not.
219 */
220 return 0;
221 }
222 }
223
224 /**
225 * Get the value of a shader input parameter and extract a bitfield.
226 */
227 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
228 unsigned param, unsigned rshift,
229 unsigned bitwidth)
230 {
231 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
232 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
233 param);
234
235 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
236 value = bitcast(&ctx->radeon_bld.soa.bld_base,
237 TGSI_TYPE_UNSIGNED, value);
238
239 if (rshift)
240 value = LLVMBuildLShr(gallivm->builder, value,
241 lp_build_const_int32(gallivm, rshift), "");
242
243 if (rshift + bitwidth < 32) {
244 unsigned mask = (1 << bitwidth) - 1;
245 value = LLVMBuildAnd(gallivm->builder, value,
246 lp_build_const_int32(gallivm, mask), "");
247 }
248
249 return value;
250 }
251
252 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
253 {
254 switch (ctx->type) {
255 case PIPE_SHADER_TESS_CTRL:
256 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
257
258 case PIPE_SHADER_TESS_EVAL:
259 return LLVMGetParam(ctx->radeon_bld.main_fn,
260 ctx->param_tes_rel_patch_id);
261
262 default:
263 assert(0);
264 return NULL;
265 }
266 }
267
268 /* Tessellation shaders pass outputs to the next shader using LDS.
269 *
270 * LS outputs = TCS inputs
271 * TCS outputs = TES inputs
272 *
273 * The LDS layout is:
274 * - TCS inputs for patch 0
275 * - TCS inputs for patch 1
276 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
277 * - ...
278 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
279 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
280 * - TCS outputs for patch 1
281 * - Per-patch TCS outputs for patch 1
282 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
283 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
284 * - ...
285 *
286 * All three shaders VS(LS), TCS, TES share the same LDS space.
287 */
288
289 static LLVMValueRef
290 get_tcs_in_patch_stride(struct si_shader_context *ctx)
291 {
292 if (ctx->type == PIPE_SHADER_VERTEX)
293 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
294 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
295 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
296 else {
297 assert(0);
298 return NULL;
299 }
300 }
301
302 static LLVMValueRef
303 get_tcs_out_patch_stride(struct si_shader_context *ctx)
304 {
305 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
306 }
307
308 static LLVMValueRef
309 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
310 {
311 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
312 unpack_param(ctx,
313 SI_PARAM_TCS_OUT_OFFSETS,
314 0, 16),
315 4);
316 }
317
318 static LLVMValueRef
319 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
320 {
321 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
322 unpack_param(ctx,
323 SI_PARAM_TCS_OUT_OFFSETS,
324 16, 16),
325 4);
326 }
327
328 static LLVMValueRef
329 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
330 {
331 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
332 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
333 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
334
335 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
343 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
344 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
345
346 return LLVMBuildAdd(gallivm->builder, patch0_offset,
347 LLVMBuildMul(gallivm->builder, patch_stride,
348 rel_patch_id, ""),
349 "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
354 {
355 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
356 LLVMValueRef patch0_patch_data_offset =
357 get_tcs_out_patch0_patch_data_offset(ctx);
358 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
359 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
360
361 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
362 LLVMBuildMul(gallivm->builder, patch_stride,
363 rel_patch_id, ""),
364 "");
365 }
366
367 static void build_indexed_store(struct si_shader_context *ctx,
368 LLVMValueRef base_ptr, LLVMValueRef index,
369 LLVMValueRef value)
370 {
371 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
372 struct gallivm_state *gallivm = bld_base->base.gallivm;
373 LLVMValueRef indices[2], pointer;
374
375 indices[0] = bld_base->uint_bld.zero;
376 indices[1] = index;
377
378 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
379 LLVMBuildStore(gallivm->builder, value, pointer);
380 }
381
382 /**
383 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
384 * It's equivalent to doing a load from &base_ptr[index].
385 *
386 * \param base_ptr Where the array starts.
387 * \param index The element index into the array.
388 * \param uniform Whether the base_ptr and index can be assumed to be
389 * dynamically uniform
390 */
391 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
392 LLVMValueRef base_ptr, LLVMValueRef index,
393 bool uniform)
394 {
395 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
396 struct gallivm_state *gallivm = bld_base->base.gallivm;
397 LLVMValueRef indices[2], pointer;
398
399 indices[0] = bld_base->uint_bld.zero;
400 indices[1] = index;
401
402 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
403 if (uniform)
404 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
405 return LLVMBuildLoad(gallivm->builder, pointer, "");
406 }
407
408 /**
409 * Do a load from &base_ptr[index], but also add a flag that it's loading
410 * a constant from a dynamically uniform index.
411 */
412 static LLVMValueRef build_indexed_load_const(
413 struct si_shader_context *ctx,
414 LLVMValueRef base_ptr, LLVMValueRef index)
415 {
416 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
417 LLVMSetMetadata(result, 1, ctx->const_md);
418 return result;
419 }
420
421 static LLVMValueRef get_instance_index_for_fetch(
422 struct radeon_llvm_context *radeon_bld,
423 unsigned param_start_instance, unsigned divisor)
424 {
425 struct si_shader_context *ctx =
426 si_shader_context(&radeon_bld->soa.bld_base);
427 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
428
429 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
430 ctx->param_instance_id);
431
432 /* The division must be done before START_INSTANCE is added. */
433 if (divisor > 1)
434 result = LLVMBuildUDiv(gallivm->builder, result,
435 lp_build_const_int32(gallivm, divisor), "");
436
437 return LLVMBuildAdd(gallivm->builder, result,
438 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
439 }
440
441 static void declare_input_vs(
442 struct radeon_llvm_context *radeon_bld,
443 unsigned input_index,
444 const struct tgsi_full_declaration *decl)
445 {
446 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
447 struct gallivm_state *gallivm = base->gallivm;
448 struct si_shader_context *ctx =
449 si_shader_context(&radeon_bld->soa.bld_base);
450 unsigned divisor =
451 ctx->shader->key.vs.prolog.instance_divisors[input_index];
452
453 unsigned chan;
454
455 LLVMValueRef t_list_ptr;
456 LLVMValueRef t_offset;
457 LLVMValueRef t_list;
458 LLVMValueRef attribute_offset;
459 LLVMValueRef buffer_index;
460 LLVMValueRef args[3];
461 LLVMValueRef input;
462
463 /* Load the T list */
464 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
465
466 t_offset = lp_build_const_int32(gallivm, input_index);
467
468 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
469
470 /* Build the attribute offset */
471 attribute_offset = lp_build_const_int32(gallivm, 0);
472
473 if (!ctx->is_monolithic) {
474 buffer_index = LLVMGetParam(radeon_bld->main_fn,
475 ctx->param_vertex_index0 +
476 input_index);
477 } else if (divisor) {
478 /* Build index from instance ID, start instance and divisor */
479 ctx->shader->info.uses_instanceid = true;
480 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
481 SI_PARAM_START_INSTANCE,
482 divisor);
483 } else {
484 /* Load the buffer index for vertices. */
485 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
486 ctx->param_vertex_id);
487 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
488 SI_PARAM_BASE_VERTEX);
489 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
490 }
491
492 args[0] = t_list;
493 args[1] = attribute_offset;
494 args[2] = buffer_index;
495 input = lp_build_intrinsic(gallivm->builder,
496 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
497 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
498
499 /* Break up the vec4 into individual components */
500 for (chan = 0; chan < 4; chan++) {
501 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
502 /* XXX: Use a helper function for this. There is one in
503 * tgsi_llvm.c. */
504 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
505 LLVMBuildExtractElement(gallivm->builder,
506 input, llvm_chan, "");
507 }
508 }
509
510 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
511 unsigned swizzle)
512 {
513 struct si_shader_context *ctx = si_shader_context(bld_base);
514
515 if (swizzle > 0)
516 return bld_base->uint_bld.zero;
517
518 switch (ctx->type) {
519 case PIPE_SHADER_VERTEX:
520 return LLVMGetParam(ctx->radeon_bld.main_fn,
521 ctx->param_vs_prim_id);
522 case PIPE_SHADER_TESS_CTRL:
523 return LLVMGetParam(ctx->radeon_bld.main_fn,
524 SI_PARAM_PATCH_ID);
525 case PIPE_SHADER_TESS_EVAL:
526 return LLVMGetParam(ctx->radeon_bld.main_fn,
527 ctx->param_tes_patch_id);
528 case PIPE_SHADER_GEOMETRY:
529 return LLVMGetParam(ctx->radeon_bld.main_fn,
530 SI_PARAM_PRIMITIVE_ID);
531 default:
532 assert(0);
533 return bld_base->uint_bld.zero;
534 }
535 }
536
537 /**
538 * Return the value of tgsi_ind_register for indexing.
539 * This is the indirect index with the constant offset added to it.
540 */
541 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
542 const struct tgsi_ind_register *ind,
543 int rel_index)
544 {
545 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
546 LLVMValueRef result;
547
548 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
549 result = LLVMBuildLoad(gallivm->builder, result, "");
550 result = LLVMBuildAdd(gallivm->builder, result,
551 lp_build_const_int32(gallivm, rel_index), "");
552 return result;
553 }
554
555 /**
556 * Like get_indirect_index, but restricts the return value to a (possibly
557 * undefined) value inside [0..num).
558 */
559 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
560 const struct tgsi_ind_register *ind,
561 int rel_index, unsigned num)
562 {
563 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
564 LLVMBuilderRef builder = gallivm->builder;
565 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
566 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
567 LLVMValueRef cc;
568
569 /* LLVM 3.8: If indirect resource indexing is used:
570 * - SI & CIK hang
571 * - VI crashes
572 */
573 if (HAVE_LLVM <= 0x0308)
574 return LLVMGetUndef(ctx->i32);
575
576 if (util_is_power_of_two(num)) {
577 result = LLVMBuildAnd(builder, result, c_max, "");
578 } else {
579 /* In theory, this MAX pattern should result in code that is
580 * as good as the bit-wise AND above.
581 *
582 * In practice, LLVM generates worse code (at the time of
583 * writing), because its value tracking is not strong enough.
584 */
585 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
586 result = LLVMBuildSelect(builder, cc, result, c_max, "");
587 }
588
589 return result;
590 }
591
592
593 /**
594 * Calculate a dword address given an input or output register and a stride.
595 */
596 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
597 const struct tgsi_full_dst_register *dst,
598 const struct tgsi_full_src_register *src,
599 LLVMValueRef vertex_dw_stride,
600 LLVMValueRef base_addr)
601 {
602 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
603 struct tgsi_shader_info *info = &ctx->shader->selector->info;
604 ubyte *name, *index, *array_first;
605 int first, param;
606 struct tgsi_full_dst_register reg;
607
608 /* Set the register description. The address computation is the same
609 * for sources and destinations. */
610 if (src) {
611 reg.Register.File = src->Register.File;
612 reg.Register.Index = src->Register.Index;
613 reg.Register.Indirect = src->Register.Indirect;
614 reg.Register.Dimension = src->Register.Dimension;
615 reg.Indirect = src->Indirect;
616 reg.Dimension = src->Dimension;
617 reg.DimIndirect = src->DimIndirect;
618 } else
619 reg = *dst;
620
621 /* If the register is 2-dimensional (e.g. an array of vertices
622 * in a primitive), calculate the base address of the vertex. */
623 if (reg.Register.Dimension) {
624 LLVMValueRef index;
625
626 if (reg.Dimension.Indirect)
627 index = get_indirect_index(ctx, &reg.DimIndirect,
628 reg.Dimension.Index);
629 else
630 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
631
632 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
633 LLVMBuildMul(gallivm->builder, index,
634 vertex_dw_stride, ""), "");
635 }
636
637 /* Get information about the register. */
638 if (reg.Register.File == TGSI_FILE_INPUT) {
639 name = info->input_semantic_name;
640 index = info->input_semantic_index;
641 array_first = info->input_array_first;
642 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
643 name = info->output_semantic_name;
644 index = info->output_semantic_index;
645 array_first = info->output_array_first;
646 } else {
647 assert(0);
648 return NULL;
649 }
650
651 if (reg.Register.Indirect) {
652 /* Add the relative address of the element. */
653 LLVMValueRef ind_index;
654
655 if (reg.Indirect.ArrayID)
656 first = array_first[reg.Indirect.ArrayID];
657 else
658 first = reg.Register.Index;
659
660 ind_index = get_indirect_index(ctx, &reg.Indirect,
661 reg.Register.Index - first);
662
663 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
664 LLVMBuildMul(gallivm->builder, ind_index,
665 lp_build_const_int32(gallivm, 4), ""), "");
666
667 param = si_shader_io_get_unique_index(name[first], index[first]);
668 } else {
669 param = si_shader_io_get_unique_index(name[reg.Register.Index],
670 index[reg.Register.Index]);
671 }
672
673 /* Add the base address of the element. */
674 return LLVMBuildAdd(gallivm->builder, base_addr,
675 lp_build_const_int32(gallivm, param * 4), "");
676 }
677
678 /* The offchip buffer layout for TCS->TES is
679 *
680 * - attribute 0 of patch 0 vertex 0
681 * - attribute 0 of patch 0 vertex 1
682 * - attribute 0 of patch 0 vertex 2
683 * ...
684 * - attribute 0 of patch 1 vertex 0
685 * - attribute 0 of patch 1 vertex 1
686 * ...
687 * - attribute 1 of patch 0 vertex 0
688 * - attribute 1 of patch 0 vertex 1
689 * ...
690 * - per patch attribute 0 of patch 0
691 * - per patch attribute 0 of patch 1
692 * ...
693 *
694 * Note that every attribute has 4 components.
695 */
696 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
697 LLVMValueRef vertex_index,
698 LLVMValueRef param_index)
699 {
700 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
701 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
702 LLVMValueRef param_stride, constant16;
703
704 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
705 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
706 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
707 num_patches, "");
708
709 constant16 = lp_build_const_int32(gallivm, 16);
710 if (vertex_index) {
711 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
712 vertices_per_patch, "");
713
714 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
715 vertex_index, "");
716
717 param_stride = total_vertices;
718 } else {
719 base_addr = get_rel_patch_id(ctx);
720 param_stride = num_patches;
721 }
722
723 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
724 LLVMBuildMul(gallivm->builder, param_index,
725 param_stride, ""), "");
726
727 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
728
729 if (!vertex_index) {
730 LLVMValueRef patch_data_offset =
731 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
732
733 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
734 patch_data_offset, "");
735 }
736 return base_addr;
737 }
738
739 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
740 struct si_shader_context *ctx,
741 const struct tgsi_full_dst_register *dst,
742 const struct tgsi_full_src_register *src)
743 {
744 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
745 struct tgsi_shader_info *info = &ctx->shader->selector->info;
746 ubyte *name, *index, *array_first;
747 struct tgsi_full_src_register reg;
748 LLVMValueRef vertex_index = NULL;
749 LLVMValueRef param_index = NULL;
750 unsigned param_index_base, param_base;
751
752 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
753
754 if (reg.Register.Dimension) {
755
756 if (reg.Dimension.Indirect)
757 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
758 reg.Dimension.Index);
759 else
760 vertex_index = lp_build_const_int32(gallivm,
761 reg.Dimension.Index);
762 }
763
764 /* Get information about the register. */
765 if (reg.Register.File == TGSI_FILE_INPUT) {
766 name = info->input_semantic_name;
767 index = info->input_semantic_index;
768 array_first = info->input_array_first;
769 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
770 name = info->output_semantic_name;
771 index = info->output_semantic_index;
772 array_first = info->output_array_first;
773 } else {
774 assert(0);
775 return NULL;
776 }
777
778 if (reg.Register.Indirect) {
779 if (reg.Indirect.ArrayID)
780 param_base = array_first[reg.Indirect.ArrayID];
781 else
782 param_base = reg.Register.Index;
783
784 param_index = get_indirect_index(ctx, &reg.Indirect,
785 reg.Register.Index - param_base);
786
787 } else {
788 param_base = reg.Register.Index;
789 param_index = lp_build_const_int32(gallivm, 0);
790 }
791
792 param_index_base = si_shader_io_get_unique_index(name[param_base],
793 index[param_base]);
794
795 param_index = LLVMBuildAdd(gallivm->builder, param_index,
796 lp_build_const_int32(gallivm, param_index_base),
797 "");
798
799 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
800 }
801
802 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
803 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
804 * or v4i32 (num_channels=3,4). */
805 static void build_tbuffer_store(struct si_shader_context *ctx,
806 LLVMValueRef rsrc,
807 LLVMValueRef vdata,
808 unsigned num_channels,
809 LLVMValueRef vaddr,
810 LLVMValueRef soffset,
811 unsigned inst_offset,
812 unsigned dfmt,
813 unsigned nfmt,
814 unsigned offen,
815 unsigned idxen,
816 unsigned glc,
817 unsigned slc,
818 unsigned tfe)
819 {
820 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
821 LLVMValueRef args[] = {
822 rsrc,
823 vdata,
824 LLVMConstInt(ctx->i32, num_channels, 0),
825 vaddr,
826 soffset,
827 LLVMConstInt(ctx->i32, inst_offset, 0),
828 LLVMConstInt(ctx->i32, dfmt, 0),
829 LLVMConstInt(ctx->i32, nfmt, 0),
830 LLVMConstInt(ctx->i32, offen, 0),
831 LLVMConstInt(ctx->i32, idxen, 0),
832 LLVMConstInt(ctx->i32, glc, 0),
833 LLVMConstInt(ctx->i32, slc, 0),
834 LLVMConstInt(ctx->i32, tfe, 0)
835 };
836
837 /* The instruction offset field has 12 bits */
838 assert(offen || inst_offset < (1 << 12));
839
840 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
841 unsigned func = CLAMP(num_channels, 1, 3) - 1;
842 const char *types[] = {"i32", "v2i32", "v4i32"};
843 char name[256];
844 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
845
846 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
847 args, ARRAY_SIZE(args), 0);
848 }
849
850 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
851 LLVMValueRef rsrc,
852 LLVMValueRef vdata,
853 unsigned num_channels,
854 LLVMValueRef vaddr,
855 LLVMValueRef soffset,
856 unsigned inst_offset)
857 {
858 static unsigned dfmt[] = {
859 V_008F0C_BUF_DATA_FORMAT_32,
860 V_008F0C_BUF_DATA_FORMAT_32_32,
861 V_008F0C_BUF_DATA_FORMAT_32_32_32,
862 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
863 };
864 assert(num_channels >= 1 && num_channels <= 4);
865
866 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
867 inst_offset, dfmt[num_channels-1],
868 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
869 }
870
871 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
872 LLVMValueRef rsrc,
873 int num_channels,
874 LLVMValueRef vindex,
875 LLVMValueRef voffset,
876 LLVMValueRef soffset,
877 unsigned inst_offset,
878 unsigned glc,
879 unsigned slc)
880 {
881 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
882 unsigned func = CLAMP(num_channels, 1, 3) - 1;
883
884 if (HAVE_LLVM >= 0x309) {
885 LLVMValueRef args[] = {
886 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
887 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
888 LLVMConstInt(ctx->i32, inst_offset, 0),
889 LLVMConstInt(ctx->i1, glc, 0),
890 LLVMConstInt(ctx->i1, slc, 0)
891 };
892
893 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
894 ctx->v4f32};
895 const char *type_names[] = {"f32", "v2f32", "v4f32"};
896 char name[256];
897
898 if (voffset) {
899 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
900 "");
901 }
902
903 if (soffset) {
904 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
905 "");
906 }
907
908 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
909 type_names[func]);
910
911 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
912 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
913 LLVMNoUnwindAttribute);
914 } else {
915 LLVMValueRef args[] = {
916 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
917 voffset ? voffset : vindex,
918 soffset,
919 LLVMConstInt(ctx->i32, inst_offset, 0),
920 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
921 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
922 LLVMConstInt(ctx->i32, glc, 0),
923 LLVMConstInt(ctx->i32, slc, 0),
924 LLVMConstInt(ctx->i32, 0, 0), // TFE
925 };
926
927 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
928 ctx->v4i32};
929 const char *type_names[] = {"i32", "v2i32", "v4i32"};
930 const char *arg_type = "i32";
931 char name[256];
932
933 if (voffset && vindex) {
934 LLVMValueRef vaddr[] = {vindex, voffset};
935
936 arg_type = "v2i32";
937 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
938 }
939
940 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
941 type_names[func], arg_type);
942
943 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
944 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
945 LLVMNoUnwindAttribute);
946 }
947 }
948
949 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
950 enum tgsi_opcode_type type, unsigned swizzle,
951 LLVMValueRef buffer, LLVMValueRef offset,
952 LLVMValueRef base)
953 {
954 struct si_shader_context *ctx = si_shader_context(bld_base);
955 struct gallivm_state *gallivm = bld_base->base.gallivm;
956 LLVMValueRef value, value2;
957 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
958 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
959
960 if (swizzle == ~0) {
961 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
962 0, 1, 0);
963
964 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
965 }
966
967 if (!tgsi_type_is_64bit(type)) {
968 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
969 0, 1, 0);
970
971 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
972 return LLVMBuildExtractElement(gallivm->builder, value,
973 lp_build_const_int32(gallivm, swizzle), "");
974 }
975
976 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
977 swizzle * 4, 1, 0);
978
979 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
980 swizzle * 4 + 4, 1, 0);
981
982 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
983 }
984
985 /**
986 * Load from LDS.
987 *
988 * \param type output value type
989 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
990 * \param dw_addr address in dwords
991 */
992 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
993 enum tgsi_opcode_type type, unsigned swizzle,
994 LLVMValueRef dw_addr)
995 {
996 struct si_shader_context *ctx = si_shader_context(bld_base);
997 struct gallivm_state *gallivm = bld_base->base.gallivm;
998 LLVMValueRef value;
999
1000 if (swizzle == ~0) {
1001 LLVMValueRef values[TGSI_NUM_CHANNELS];
1002
1003 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1004 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1005
1006 return lp_build_gather_values(bld_base->base.gallivm, values,
1007 TGSI_NUM_CHANNELS);
1008 }
1009
1010 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1011 lp_build_const_int32(gallivm, swizzle));
1012
1013 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1014 if (tgsi_type_is_64bit(type)) {
1015 LLVMValueRef value2;
1016 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1017 lp_build_const_int32(gallivm, swizzle + 1));
1018 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1019 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1020 }
1021
1022 return LLVMBuildBitCast(gallivm->builder, value,
1023 tgsi2llvmtype(bld_base, type), "");
1024 }
1025
1026 /**
1027 * Store to LDS.
1028 *
1029 * \param swizzle offset (typically 0..3)
1030 * \param dw_addr address in dwords
1031 * \param value value to store
1032 */
1033 static void lds_store(struct lp_build_tgsi_context *bld_base,
1034 unsigned swizzle, LLVMValueRef dw_addr,
1035 LLVMValueRef value)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 struct gallivm_state *gallivm = bld_base->base.gallivm;
1039
1040 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1041 lp_build_const_int32(gallivm, swizzle));
1042
1043 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1044 build_indexed_store(ctx, ctx->lds,
1045 dw_addr, value);
1046 }
1047
1048 static LLVMValueRef fetch_input_tcs(
1049 struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_src_register *reg,
1051 enum tgsi_opcode_type type, unsigned swizzle)
1052 {
1053 struct si_shader_context *ctx = si_shader_context(bld_base);
1054 LLVMValueRef dw_addr, stride;
1055
1056 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1057 dw_addr = get_tcs_in_current_patch_offset(ctx);
1058 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1059
1060 return lds_load(bld_base, type, swizzle, dw_addr);
1061 }
1062
1063 static LLVMValueRef fetch_output_tcs(
1064 struct lp_build_tgsi_context *bld_base,
1065 const struct tgsi_full_src_register *reg,
1066 enum tgsi_opcode_type type, unsigned swizzle)
1067 {
1068 struct si_shader_context *ctx = si_shader_context(bld_base);
1069 LLVMValueRef dw_addr, stride;
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1078 }
1079
1080 return lds_load(bld_base, type, swizzle, dw_addr);
1081 }
1082
1083 static LLVMValueRef fetch_input_tes(
1084 struct lp_build_tgsi_context *bld_base,
1085 const struct tgsi_full_src_register *reg,
1086 enum tgsi_opcode_type type, unsigned swizzle)
1087 {
1088 struct si_shader_context *ctx = si_shader_context(bld_base);
1089 struct gallivm_state *gallivm = bld_base->base.gallivm;
1090 LLVMValueRef rw_buffers, buffer, base, addr;
1091
1092 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1093 SI_PARAM_RW_BUFFERS);
1094 buffer = build_indexed_load_const(ctx, rw_buffers,
1095 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1096
1097 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1098 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1099
1100 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1101 }
1102
1103 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1104 const struct tgsi_full_instruction *inst,
1105 const struct tgsi_opcode_info *info,
1106 LLVMValueRef dst[4])
1107 {
1108 struct si_shader_context *ctx = si_shader_context(bld_base);
1109 struct gallivm_state *gallivm = bld_base->base.gallivm;
1110 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1111 unsigned chan_index;
1112 LLVMValueRef dw_addr, stride;
1113 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1114 LLVMValueRef values[4];
1115
1116 /* Only handle per-patch and per-vertex outputs here.
1117 * Vectors will be lowered to scalars and this function will be called again.
1118 */
1119 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1120 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1121 radeon_llvm_emit_store(bld_base, inst, info, dst);
1122 return;
1123 }
1124
1125 if (reg->Register.Dimension) {
1126 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1127 dw_addr = get_tcs_out_current_patch_offset(ctx);
1128 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1129 } else {
1130 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1131 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1132 }
1133
1134 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1135 SI_PARAM_RW_BUFFERS);
1136 buffer = build_indexed_load_const(ctx, rw_buffers,
1137 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1138
1139 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1140 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1141
1142
1143 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1144 LLVMValueRef value = dst[chan_index];
1145
1146 if (inst->Instruction.Saturate)
1147 value = radeon_llvm_saturate(bld_base, value);
1148
1149 lds_store(bld_base, chan_index, dw_addr, value);
1150
1151 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1152 values[chan_index] = value;
1153
1154 if (inst->Dst[0].Register.WriteMask != 0xF) {
1155 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1156 buf_addr, base,
1157 4 * chan_index);
1158 }
1159 }
1160
1161 if (inst->Dst[0].Register.WriteMask == 0xF) {
1162 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1163 values, 4);
1164 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1165 base, 0);
1166 }
1167 }
1168
1169 static LLVMValueRef fetch_input_gs(
1170 struct lp_build_tgsi_context *bld_base,
1171 const struct tgsi_full_src_register *reg,
1172 enum tgsi_opcode_type type,
1173 unsigned swizzle)
1174 {
1175 struct lp_build_context *base = &bld_base->base;
1176 struct si_shader_context *ctx = si_shader_context(bld_base);
1177 struct si_shader *shader = ctx->shader;
1178 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1179 struct gallivm_state *gallivm = base->gallivm;
1180 LLVMValueRef vtx_offset;
1181 LLVMValueRef args[9];
1182 unsigned vtx_offset_param;
1183 struct tgsi_shader_info *info = &shader->selector->info;
1184 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1185 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1186 unsigned param;
1187 LLVMValueRef value;
1188
1189 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1190 return get_primitive_id(bld_base, swizzle);
1191
1192 if (!reg->Register.Dimension)
1193 return NULL;
1194
1195 if (swizzle == ~0) {
1196 LLVMValueRef values[TGSI_NUM_CHANNELS];
1197 unsigned chan;
1198 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1199 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1200 }
1201 return lp_build_gather_values(bld_base->base.gallivm, values,
1202 TGSI_NUM_CHANNELS);
1203 }
1204
1205 /* Get the vertex offset parameter */
1206 vtx_offset_param = reg->Dimension.Index;
1207 if (vtx_offset_param < 2) {
1208 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1209 } else {
1210 assert(vtx_offset_param < 6);
1211 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1212 }
1213 vtx_offset = lp_build_mul_imm(uint,
1214 LLVMGetParam(ctx->radeon_bld.main_fn,
1215 vtx_offset_param),
1216 4);
1217
1218 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1219 args[0] = ctx->esgs_ring;
1220 args[1] = vtx_offset;
1221 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1222 args[3] = uint->zero;
1223 args[4] = uint->one; /* OFFEN */
1224 args[5] = uint->zero; /* IDXEN */
1225 args[6] = uint->one; /* GLC */
1226 args[7] = uint->zero; /* SLC */
1227 args[8] = uint->zero; /* TFE */
1228
1229 value = lp_build_intrinsic(gallivm->builder,
1230 "llvm.SI.buffer.load.dword.i32.i32",
1231 ctx->i32, args, 9,
1232 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1233 if (tgsi_type_is_64bit(type)) {
1234 LLVMValueRef value2;
1235 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1236 value2 = lp_build_intrinsic(gallivm->builder,
1237 "llvm.SI.buffer.load.dword.i32.i32",
1238 ctx->i32, args, 9,
1239 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1240 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1241 value, value2);
1242 }
1243 return LLVMBuildBitCast(gallivm->builder,
1244 value,
1245 tgsi2llvmtype(bld_base, type), "");
1246 }
1247
1248 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1249 {
1250 switch (interpolate) {
1251 case TGSI_INTERPOLATE_CONSTANT:
1252 return 0;
1253
1254 case TGSI_INTERPOLATE_LINEAR:
1255 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1256 return SI_PARAM_LINEAR_SAMPLE;
1257 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1258 return SI_PARAM_LINEAR_CENTROID;
1259 else
1260 return SI_PARAM_LINEAR_CENTER;
1261 break;
1262 case TGSI_INTERPOLATE_COLOR:
1263 case TGSI_INTERPOLATE_PERSPECTIVE:
1264 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1265 return SI_PARAM_PERSP_SAMPLE;
1266 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1267 return SI_PARAM_PERSP_CENTROID;
1268 else
1269 return SI_PARAM_PERSP_CENTER;
1270 break;
1271 default:
1272 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1273 return -1;
1274 }
1275 }
1276
1277 /* This shouldn't be used by explicit INTERP opcodes. */
1278 static unsigned select_interp_param(struct si_shader_context *ctx,
1279 unsigned param)
1280 {
1281 if (!ctx->is_monolithic)
1282 return param;
1283
1284 /* If the shader doesn't use center/centroid, just return the parameter.
1285 *
1286 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
1287 * switch between center/centroid and sample without shader changes.
1288 */
1289 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1290 switch (param) {
1291 case SI_PARAM_PERSP_CENTROID:
1292 case SI_PARAM_PERSP_CENTER:
1293 return SI_PARAM_PERSP_SAMPLE;
1294 }
1295 }
1296 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1297 switch (param) {
1298 case SI_PARAM_LINEAR_CENTROID:
1299 case SI_PARAM_LINEAR_CENTER:
1300 return SI_PARAM_LINEAR_SAMPLE;
1301 }
1302 }
1303 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1304 switch (param) {
1305 case SI_PARAM_PERSP_CENTROID:
1306 case SI_PARAM_PERSP_SAMPLE:
1307 return SI_PARAM_PERSP_CENTER;
1308 }
1309 }
1310 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1311 switch (param) {
1312 case SI_PARAM_LINEAR_CENTROID:
1313 case SI_PARAM_LINEAR_SAMPLE:
1314 return SI_PARAM_PERSP_CENTER;
1315 }
1316 }
1317
1318 return param;
1319 }
1320
1321 /**
1322 * Interpolate a fragment shader input.
1323 *
1324 * @param ctx context
1325 * @param input_index index of the input in hardware
1326 * @param semantic_name TGSI_SEMANTIC_*
1327 * @param semantic_index semantic index
1328 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1329 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1330 * @param interp_param interpolation weights (i,j)
1331 * @param prim_mask SI_PARAM_PRIM_MASK
1332 * @param face SI_PARAM_FRONT_FACE
1333 * @param result the return value (4 components)
1334 */
1335 static void interp_fs_input(struct si_shader_context *ctx,
1336 unsigned input_index,
1337 unsigned semantic_name,
1338 unsigned semantic_index,
1339 unsigned num_interp_inputs,
1340 unsigned colors_read_mask,
1341 LLVMValueRef interp_param,
1342 LLVMValueRef prim_mask,
1343 LLVMValueRef face,
1344 LLVMValueRef result[4])
1345 {
1346 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1347 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1348 struct gallivm_state *gallivm = base->gallivm;
1349 const char *intr_name;
1350 LLVMValueRef attr_number;
1351
1352 unsigned chan;
1353
1354 attr_number = lp_build_const_int32(gallivm, input_index);
1355
1356 /* fs.constant returns the param from the middle vertex, so it's not
1357 * really useful for flat shading. It's meant to be used for custom
1358 * interpolation (but the intrinsic can't fetch from the other two
1359 * vertices).
1360 *
1361 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1362 * to do the right thing. The only reason we use fs.constant is that
1363 * fs.interp cannot be used on integers, because they can be equal
1364 * to NaN.
1365 */
1366 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1367
1368 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1369 ctx->shader->key.ps.prolog.color_two_side) {
1370 LLVMValueRef args[4];
1371 LLVMValueRef is_face_positive;
1372 LLVMValueRef back_attr_number;
1373
1374 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1375 * otherwise it's at offset "num_inputs".
1376 */
1377 unsigned back_attr_offset = num_interp_inputs;
1378 if (semantic_index == 1 && colors_read_mask & 0xf)
1379 back_attr_offset += 1;
1380
1381 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1382
1383 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1384 face, uint->zero, "");
1385
1386 args[2] = prim_mask;
1387 args[3] = interp_param;
1388 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1389 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1390 LLVMValueRef front, back;
1391
1392 args[0] = llvm_chan;
1393 args[1] = attr_number;
1394 front = lp_build_intrinsic(gallivm->builder, intr_name,
1395 ctx->f32, args, args[3] ? 4 : 3,
1396 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1397
1398 args[1] = back_attr_number;
1399 back = lp_build_intrinsic(gallivm->builder, intr_name,
1400 ctx->f32, args, args[3] ? 4 : 3,
1401 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1402
1403 result[chan] = LLVMBuildSelect(gallivm->builder,
1404 is_face_positive,
1405 front,
1406 back,
1407 "");
1408 }
1409 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1410 LLVMValueRef args[4];
1411
1412 args[0] = uint->zero;
1413 args[1] = attr_number;
1414 args[2] = prim_mask;
1415 args[3] = interp_param;
1416 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1417 ctx->f32, args, args[3] ? 4 : 3,
1418 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1419 result[1] =
1420 result[2] = lp_build_const_float(gallivm, 0.0f);
1421 result[3] = lp_build_const_float(gallivm, 1.0f);
1422 } else {
1423 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1424 LLVMValueRef args[4];
1425 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1426
1427 args[0] = llvm_chan;
1428 args[1] = attr_number;
1429 args[2] = prim_mask;
1430 args[3] = interp_param;
1431 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1432 ctx->f32, args, args[3] ? 4 : 3,
1433 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1434 }
1435 }
1436 }
1437
1438 /* LLVMGetParam with bc_optimize resolved. */
1439 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1440 int interp_param_idx)
1441 {
1442 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1443 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1444 LLVMValueRef param = NULL;
1445
1446 /* Handle PRIM_MASK[31] (bc_optimize). */
1447 if (ctx->is_monolithic &&
1448 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1449 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1450 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1451 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1452 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1453 * The hw doesn't compute CENTROID if the whole wave only
1454 * contains fully-covered quads.
1455 */
1456 LLVMValueRef bc_optimize =
1457 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1458 bc_optimize = LLVMBuildLShr(builder,
1459 bc_optimize,
1460 LLVMConstInt(ctx->i32, 31, 0), "");
1461 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1462
1463 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1464 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1465 param = LLVMBuildSelect(builder, bc_optimize,
1466 LLVMGetParam(main_fn,
1467 SI_PARAM_PERSP_CENTER),
1468 LLVMGetParam(main_fn,
1469 SI_PARAM_PERSP_CENTROID),
1470 "");
1471 }
1472 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1473 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1474 param = LLVMBuildSelect(builder, bc_optimize,
1475 LLVMGetParam(main_fn,
1476 SI_PARAM_LINEAR_CENTER),
1477 LLVMGetParam(main_fn,
1478 SI_PARAM_LINEAR_CENTROID),
1479 "");
1480 }
1481 }
1482
1483 if (!param)
1484 param = LLVMGetParam(main_fn, interp_param_idx);
1485 return param;
1486 }
1487
1488 static void declare_input_fs(
1489 struct radeon_llvm_context *radeon_bld,
1490 unsigned input_index,
1491 const struct tgsi_full_declaration *decl)
1492 {
1493 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1494 struct si_shader_context *ctx =
1495 si_shader_context(&radeon_bld->soa.bld_base);
1496 struct si_shader *shader = ctx->shader;
1497 LLVMValueRef main_fn = radeon_bld->main_fn;
1498 LLVMValueRef interp_param = NULL;
1499 int interp_param_idx;
1500
1501 /* Get colors from input VGPRs (set by the prolog). */
1502 if (!ctx->is_monolithic &&
1503 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1504 unsigned i = decl->Semantic.Index;
1505 unsigned colors_read = shader->selector->info.colors_read;
1506 unsigned mask = colors_read >> (i * 4);
1507 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1508 (i ? util_bitcount(colors_read & 0xf) : 0);
1509
1510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1511 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1512 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1513 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1514 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1515 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1516 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1517 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1518 return;
1519 }
1520
1521 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1522 decl->Interp.Location);
1523 if (interp_param_idx == -1)
1524 return;
1525 else if (interp_param_idx) {
1526 interp_param_idx = select_interp_param(ctx,
1527 interp_param_idx);
1528 interp_param = get_interp_param(ctx, interp_param_idx);
1529 }
1530
1531 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1532 decl->Semantic.Index, shader->selector->info.num_inputs,
1533 shader->selector->info.colors_read, interp_param,
1534 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1535 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1536 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1537 }
1538
1539 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1540 {
1541 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1542 SI_PARAM_ANCILLARY, 8, 4);
1543 }
1544
1545 /**
1546 * Set range metadata on an instruction. This can only be used on load and
1547 * call instructions. If you know an instruction can only produce the values
1548 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1549 * \p lo is the minimum value inclusive.
1550 * \p hi is the maximum value exclusive.
1551 */
1552 static void set_range_metadata(LLVMValueRef value, unsigned lo, unsigned hi)
1553 {
1554 const char *range_md_string = "range";
1555 LLVMValueRef range_md, md_args[2];
1556 LLVMTypeRef type = LLVMTypeOf(value);
1557 LLVMContextRef context = LLVMGetTypeContext(type);
1558 unsigned md_range_id = LLVMGetMDKindIDInContext(context,
1559 range_md_string, strlen(range_md_string));
1560
1561 md_args[0] = LLVMConstInt(type, lo, false);
1562 md_args[1] = LLVMConstInt(type, hi, false);
1563 range_md = LLVMMDNodeInContext(context, md_args, 2);
1564 LLVMSetMetadata(value, md_range_id, range_md);
1565 }
1566
1567 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1568 {
1569 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1570 LLVMValueRef tid;
1571
1572 if (HAVE_LLVM < 0x0308) {
1573 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1574 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1575 } else {
1576 LLVMValueRef tid_args[2];
1577 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1578 tid_args[1] = lp_build_const_int32(gallivm, 0);
1579 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1580 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1581 tid_args, 2, LLVMReadNoneAttribute);
1582
1583 tid = lp_build_intrinsic(gallivm->builder,
1584 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1585 tid_args, 2, LLVMReadNoneAttribute);
1586 }
1587 set_range_metadata(tid, 0, 64);
1588 return tid;
1589 }
1590
1591 /**
1592 * Load a dword from a constant buffer.
1593 */
1594 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1595 LLVMValueRef offset, LLVMTypeRef return_type)
1596 {
1597 LLVMValueRef args[2] = {resource, offset};
1598
1599 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1600 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1601 }
1602
1603 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1604 {
1605 struct si_shader_context *ctx =
1606 si_shader_context(&radeon_bld->soa.bld_base);
1607 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1608 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1609 LLVMBuilderRef builder = gallivm->builder;
1610 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1611 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1612 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1613
1614 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1615 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1616 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1617
1618 LLVMValueRef pos[4] = {
1619 buffer_load_const(builder, resource, offset0, ctx->f32),
1620 buffer_load_const(builder, resource, offset1, ctx->f32),
1621 lp_build_const_float(gallivm, 0),
1622 lp_build_const_float(gallivm, 0)
1623 };
1624
1625 return lp_build_gather_values(gallivm, pos, 4);
1626 }
1627
1628 static void declare_system_value(
1629 struct radeon_llvm_context *radeon_bld,
1630 unsigned index,
1631 const struct tgsi_full_declaration *decl)
1632 {
1633 struct si_shader_context *ctx =
1634 si_shader_context(&radeon_bld->soa.bld_base);
1635 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1636 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1637 LLVMValueRef value = 0;
1638
1639 switch (decl->Semantic.Name) {
1640 case TGSI_SEMANTIC_INSTANCEID:
1641 value = LLVMGetParam(radeon_bld->main_fn,
1642 ctx->param_instance_id);
1643 break;
1644
1645 case TGSI_SEMANTIC_VERTEXID:
1646 value = LLVMBuildAdd(gallivm->builder,
1647 LLVMGetParam(radeon_bld->main_fn,
1648 ctx->param_vertex_id),
1649 LLVMGetParam(radeon_bld->main_fn,
1650 SI_PARAM_BASE_VERTEX), "");
1651 break;
1652
1653 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1654 value = LLVMGetParam(radeon_bld->main_fn,
1655 ctx->param_vertex_id);
1656 break;
1657
1658 case TGSI_SEMANTIC_BASEVERTEX:
1659 value = LLVMGetParam(radeon_bld->main_fn,
1660 SI_PARAM_BASE_VERTEX);
1661 break;
1662
1663 case TGSI_SEMANTIC_INVOCATIONID:
1664 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1665 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1666 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1667 value = LLVMGetParam(radeon_bld->main_fn,
1668 SI_PARAM_GS_INSTANCE_ID);
1669 else
1670 assert(!"INVOCATIONID not implemented");
1671 break;
1672
1673 case TGSI_SEMANTIC_POSITION:
1674 {
1675 LLVMValueRef pos[4] = {
1676 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1677 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1678 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1679 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1680 LLVMGetParam(radeon_bld->main_fn,
1681 SI_PARAM_POS_W_FLOAT)),
1682 };
1683 value = lp_build_gather_values(gallivm, pos, 4);
1684 break;
1685 }
1686
1687 case TGSI_SEMANTIC_FACE:
1688 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1689 break;
1690
1691 case TGSI_SEMANTIC_SAMPLEID:
1692 value = get_sample_id(radeon_bld);
1693 break;
1694
1695 case TGSI_SEMANTIC_SAMPLEPOS: {
1696 LLVMValueRef pos[4] = {
1697 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1698 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1699 lp_build_const_float(gallivm, 0),
1700 lp_build_const_float(gallivm, 0)
1701 };
1702 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1703 TGSI_OPCODE_FRC, pos[0]);
1704 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1705 TGSI_OPCODE_FRC, pos[1]);
1706 value = lp_build_gather_values(gallivm, pos, 4);
1707 break;
1708 }
1709
1710 case TGSI_SEMANTIC_SAMPLEMASK:
1711 /* This can only occur with the OpenGL Core profile, which
1712 * doesn't support smoothing.
1713 */
1714 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1715 break;
1716
1717 case TGSI_SEMANTIC_TESSCOORD:
1718 {
1719 LLVMValueRef coord[4] = {
1720 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1721 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1722 bld->zero,
1723 bld->zero
1724 };
1725
1726 /* For triangles, the vector should be (u, v, 1-u-v). */
1727 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1728 PIPE_PRIM_TRIANGLES)
1729 coord[2] = lp_build_sub(bld, bld->one,
1730 lp_build_add(bld, coord[0], coord[1]));
1731
1732 value = lp_build_gather_values(gallivm, coord, 4);
1733 break;
1734 }
1735
1736 case TGSI_SEMANTIC_VERTICESIN:
1737 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1738 break;
1739
1740 case TGSI_SEMANTIC_TESSINNER:
1741 case TGSI_SEMANTIC_TESSOUTER:
1742 {
1743 LLVMValueRef rw_buffers, buffer, base, addr;
1744 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1745
1746 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1747 SI_PARAM_RW_BUFFERS);
1748 buffer = build_indexed_load_const(ctx, rw_buffers,
1749 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1750
1751 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1752 addr = get_tcs_tes_buffer_address(ctx, NULL,
1753 lp_build_const_int32(gallivm, param));
1754
1755 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1756 ~0, buffer, base, addr);
1757
1758 break;
1759 }
1760
1761 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1762 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1763 {
1764 LLVMValueRef buf, slot, val[4];
1765 int i, offset;
1766
1767 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1768 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1769 buf = build_indexed_load_const(ctx, buf, slot);
1770 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1771
1772 for (i = 0; i < 4; i++)
1773 val[i] = buffer_load_const(gallivm->builder, buf,
1774 lp_build_const_int32(gallivm, (offset + i) * 4),
1775 ctx->f32);
1776 value = lp_build_gather_values(gallivm, val, 4);
1777 break;
1778 }
1779
1780 case TGSI_SEMANTIC_PRIMID:
1781 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1782 break;
1783
1784 case TGSI_SEMANTIC_GRID_SIZE:
1785 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1786 break;
1787
1788 case TGSI_SEMANTIC_BLOCK_SIZE:
1789 {
1790 LLVMValueRef values[3];
1791 unsigned i;
1792 unsigned *properties = ctx->shader->selector->info.properties;
1793 unsigned sizes[3] = {
1794 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1795 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1796 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1797 };
1798
1799 for (i = 0; i < 3; ++i)
1800 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1801
1802 value = lp_build_gather_values(gallivm, values, 3);
1803 break;
1804 }
1805
1806 case TGSI_SEMANTIC_BLOCK_ID:
1807 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1808 break;
1809
1810 case TGSI_SEMANTIC_THREAD_ID:
1811 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1812 break;
1813
1814 #if HAVE_LLVM >= 0x0309
1815 case TGSI_SEMANTIC_HELPER_INVOCATION:
1816 value = lp_build_intrinsic(gallivm->builder,
1817 "llvm.amdgcn.ps.live",
1818 ctx->i1, NULL, 0,
1819 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1820 value = LLVMBuildNot(gallivm->builder, value, "");
1821 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1822 break;
1823 #endif
1824
1825 default:
1826 assert(!"unknown system value");
1827 return;
1828 }
1829
1830 radeon_bld->system_values[index] = value;
1831 }
1832
1833 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1834 const struct tgsi_full_declaration *decl)
1835 {
1836 struct si_shader_context *ctx =
1837 si_shader_context(&radeon_bld->soa.bld_base);
1838 struct si_shader_selector *sel = ctx->shader->selector;
1839 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1840
1841 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1842 LLVMValueRef var;
1843
1844 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1845 assert(decl->Range.First == decl->Range.Last);
1846 assert(!ctx->shared_memory);
1847
1848 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1849 LLVMArrayType(ctx->i8, sel->local_size),
1850 "compute_lds",
1851 LOCAL_ADDR_SPACE);
1852 LLVMSetAlignment(var, 4);
1853
1854 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1855 }
1856
1857 static LLVMValueRef fetch_constant(
1858 struct lp_build_tgsi_context *bld_base,
1859 const struct tgsi_full_src_register *reg,
1860 enum tgsi_opcode_type type,
1861 unsigned swizzle)
1862 {
1863 struct si_shader_context *ctx = si_shader_context(bld_base);
1864 struct lp_build_context *base = &bld_base->base;
1865 const struct tgsi_ind_register *ireg = &reg->Indirect;
1866 unsigned buf, idx;
1867
1868 LLVMValueRef addr, bufp;
1869 LLVMValueRef result;
1870
1871 if (swizzle == LP_CHAN_ALL) {
1872 unsigned chan;
1873 LLVMValueRef values[4];
1874 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1875 values[chan] = fetch_constant(bld_base, reg, type, chan);
1876
1877 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1878 }
1879
1880 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1881 idx = reg->Register.Index * 4 + swizzle;
1882
1883 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1884 if (!tgsi_type_is_64bit(type))
1885 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1886 else {
1887 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1888 ctx->constants[buf][idx],
1889 ctx->constants[buf][idx + 1]);
1890 }
1891 }
1892
1893 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1894 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1895 LLVMValueRef index;
1896 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1897 reg->Dimension.Index,
1898 SI_NUM_CONST_BUFFERS);
1899 bufp = build_indexed_load_const(ctx, ptr, index);
1900 } else
1901 bufp = ctx->const_buffers[buf];
1902
1903 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1904 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1905 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1906 addr = lp_build_add(&bld_base->uint_bld, addr,
1907 lp_build_const_int32(base->gallivm, idx * 4));
1908
1909 result = buffer_load_const(base->gallivm->builder, bufp,
1910 addr, ctx->f32);
1911
1912 if (!tgsi_type_is_64bit(type))
1913 result = bitcast(bld_base, type, result);
1914 else {
1915 LLVMValueRef addr2, result2;
1916 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1917 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1918 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1919 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1920 lp_build_const_int32(base->gallivm, idx * 4));
1921
1922 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1923 addr2, ctx->f32);
1924
1925 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1926 result, result2);
1927 }
1928 return result;
1929 }
1930
1931 /* Upper 16 bits must be zero. */
1932 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1933 LLVMValueRef val[2])
1934 {
1935 return LLVMBuildOr(gallivm->builder, val[0],
1936 LLVMBuildShl(gallivm->builder, val[1],
1937 lp_build_const_int32(gallivm, 16),
1938 ""), "");
1939 }
1940
1941 /* Upper 16 bits are ignored and will be dropped. */
1942 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1943 LLVMValueRef val[2])
1944 {
1945 LLVMValueRef v[2] = {
1946 LLVMBuildAnd(gallivm->builder, val[0],
1947 lp_build_const_int32(gallivm, 0xffff), ""),
1948 val[1],
1949 };
1950 return si_llvm_pack_two_int16(gallivm, v);
1951 }
1952
1953 /* Initialize arguments for the shader export intrinsic */
1954 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1955 LLVMValueRef *values,
1956 unsigned target,
1957 LLVMValueRef *args)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960 struct lp_build_context *uint =
1961 &ctx->radeon_bld.soa.bld_base.uint_bld;
1962 struct lp_build_context *base = &bld_base->base;
1963 struct gallivm_state *gallivm = base->gallivm;
1964 LLVMBuilderRef builder = base->gallivm->builder;
1965 LLVMValueRef val[4];
1966 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1967 unsigned chan;
1968 bool is_int8;
1969
1970 /* Default is 0xf. Adjusted below depending on the format. */
1971 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1972
1973 /* Specify whether the EXEC mask represents the valid mask */
1974 args[1] = uint->zero;
1975
1976 /* Specify whether this is the last export */
1977 args[2] = uint->zero;
1978
1979 /* Specify the target we are exporting */
1980 args[3] = lp_build_const_int32(base->gallivm, target);
1981
1982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1983 const union si_shader_key *key = &ctx->shader->key;
1984 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1985 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1986
1987 assert(cbuf >= 0 && cbuf < 8);
1988 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1989 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1990 }
1991
1992 args[4] = uint->zero; /* COMPR flag */
1993 args[5] = base->undef;
1994 args[6] = base->undef;
1995 args[7] = base->undef;
1996 args[8] = base->undef;
1997
1998 switch (spi_shader_col_format) {
1999 case V_028714_SPI_SHADER_ZERO:
2000 args[0] = uint->zero; /* writemask */
2001 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2002 break;
2003
2004 case V_028714_SPI_SHADER_32_R:
2005 args[0] = uint->one; /* writemask */
2006 args[5] = values[0];
2007 break;
2008
2009 case V_028714_SPI_SHADER_32_GR:
2010 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2011 args[5] = values[0];
2012 args[6] = values[1];
2013 break;
2014
2015 case V_028714_SPI_SHADER_32_AR:
2016 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2017 args[5] = values[0];
2018 args[8] = values[3];
2019 break;
2020
2021 case V_028714_SPI_SHADER_FP16_ABGR:
2022 args[4] = uint->one; /* COMPR flag */
2023
2024 for (chan = 0; chan < 2; chan++) {
2025 LLVMValueRef pack_args[2] = {
2026 values[2 * chan],
2027 values[2 * chan + 1]
2028 };
2029 LLVMValueRef packed;
2030
2031 packed = lp_build_intrinsic(base->gallivm->builder,
2032 "llvm.SI.packf16",
2033 ctx->i32, pack_args, 2,
2034 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2035 args[chan + 5] =
2036 LLVMBuildBitCast(base->gallivm->builder,
2037 packed, ctx->f32, "");
2038 }
2039 break;
2040
2041 case V_028714_SPI_SHADER_UNORM16_ABGR:
2042 for (chan = 0; chan < 4; chan++) {
2043 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2044 val[chan] = LLVMBuildFMul(builder, val[chan],
2045 lp_build_const_float(gallivm, 65535), "");
2046 val[chan] = LLVMBuildFAdd(builder, val[chan],
2047 lp_build_const_float(gallivm, 0.5), "");
2048 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2049 ctx->i32, "");
2050 }
2051
2052 args[4] = uint->one; /* COMPR flag */
2053 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2054 si_llvm_pack_two_int16(gallivm, val));
2055 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2056 si_llvm_pack_two_int16(gallivm, val+2));
2057 break;
2058
2059 case V_028714_SPI_SHADER_SNORM16_ABGR:
2060 for (chan = 0; chan < 4; chan++) {
2061 /* Clamp between [-1, 1]. */
2062 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2063 values[chan],
2064 lp_build_const_float(gallivm, 1));
2065 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2066 val[chan],
2067 lp_build_const_float(gallivm, -1));
2068 /* Convert to a signed integer in [-32767, 32767]. */
2069 val[chan] = LLVMBuildFMul(builder, val[chan],
2070 lp_build_const_float(gallivm, 32767), "");
2071 /* If positive, add 0.5, else add -0.5. */
2072 val[chan] = LLVMBuildFAdd(builder, val[chan],
2073 LLVMBuildSelect(builder,
2074 LLVMBuildFCmp(builder, LLVMRealOGE,
2075 val[chan], base->zero, ""),
2076 lp_build_const_float(gallivm, 0.5),
2077 lp_build_const_float(gallivm, -0.5), ""), "");
2078 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2079 }
2080
2081 args[4] = uint->one; /* COMPR flag */
2082 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val));
2084 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2085 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2086 break;
2087
2088 case V_028714_SPI_SHADER_UINT16_ABGR: {
2089 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2090 255 : 65535);
2091 /* Clamp. */
2092 for (chan = 0; chan < 4; chan++) {
2093 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2094 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2095 val[chan], max);
2096 }
2097
2098 args[4] = uint->one; /* COMPR flag */
2099 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2100 si_llvm_pack_two_int16(gallivm, val));
2101 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 si_llvm_pack_two_int16(gallivm, val+2));
2103 break;
2104 }
2105
2106 case V_028714_SPI_SHADER_SINT16_ABGR: {
2107 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2108 127 : 32767);
2109 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2110 -128 : -32768);
2111 /* Clamp. */
2112 for (chan = 0; chan < 4; chan++) {
2113 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2114 val[chan] = lp_build_emit_llvm_binary(bld_base,
2115 TGSI_OPCODE_IMIN,
2116 val[chan], max);
2117 val[chan] = lp_build_emit_llvm_binary(bld_base,
2118 TGSI_OPCODE_IMAX,
2119 val[chan], min);
2120 }
2121
2122 args[4] = uint->one; /* COMPR flag */
2123 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2124 si_llvm_pack_two_int32_as_int16(gallivm, val));
2125 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2126 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2127 break;
2128 }
2129
2130 case V_028714_SPI_SHADER_32_ABGR:
2131 memcpy(&args[5], values, sizeof(values[0]) * 4);
2132 break;
2133 }
2134 }
2135
2136 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2137 LLVMValueRef alpha)
2138 {
2139 struct si_shader_context *ctx = si_shader_context(bld_base);
2140 struct gallivm_state *gallivm = bld_base->base.gallivm;
2141
2142 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2143 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2144 SI_PARAM_ALPHA_REF);
2145
2146 LLVMValueRef alpha_pass =
2147 lp_build_cmp(&bld_base->base,
2148 ctx->shader->key.ps.epilog.alpha_func,
2149 alpha, alpha_ref);
2150 LLVMValueRef arg =
2151 lp_build_select(&bld_base->base,
2152 alpha_pass,
2153 lp_build_const_float(gallivm, 1.0f),
2154 lp_build_const_float(gallivm, -1.0f));
2155
2156 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2157 ctx->voidt, &arg, 1, 0);
2158 } else {
2159 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2160 ctx->voidt, NULL, 0, 0);
2161 }
2162 }
2163
2164 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2165 LLVMValueRef alpha,
2166 unsigned samplemask_param)
2167 {
2168 struct si_shader_context *ctx = si_shader_context(bld_base);
2169 struct gallivm_state *gallivm = bld_base->base.gallivm;
2170 LLVMValueRef coverage;
2171
2172 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2173 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2174 samplemask_param);
2175 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2176
2177 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2178 ctx->i32,
2179 &coverage, 1, LLVMReadNoneAttribute);
2180
2181 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2182 ctx->f32, "");
2183
2184 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2185 lp_build_const_float(gallivm,
2186 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2187
2188 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2189 }
2190
2191 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2192 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2193 {
2194 struct si_shader_context *ctx = si_shader_context(bld_base);
2195 struct lp_build_context *base = &bld_base->base;
2196 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2197 unsigned reg_index;
2198 unsigned chan;
2199 unsigned const_chan;
2200 LLVMValueRef base_elt;
2201 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2202 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2203 SI_VS_CONST_CLIP_PLANES);
2204 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2205
2206 for (reg_index = 0; reg_index < 2; reg_index ++) {
2207 LLVMValueRef *args = pos[2 + reg_index];
2208
2209 args[5] =
2210 args[6] =
2211 args[7] =
2212 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2213
2214 /* Compute dot products of position and user clip plane vectors */
2215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2216 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2217 args[1] = lp_build_const_int32(base->gallivm,
2218 ((reg_index * 4 + chan) * 4 +
2219 const_chan) * 4);
2220 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
2221 args[1], ctx->f32);
2222 args[5 + chan] =
2223 lp_build_add(base, args[5 + chan],
2224 lp_build_mul(base, base_elt,
2225 out_elts[const_chan]));
2226 }
2227 }
2228
2229 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2230 args[1] = uint->zero;
2231 args[2] = uint->zero;
2232 args[3] = lp_build_const_int32(base->gallivm,
2233 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2234 args[4] = uint->zero;
2235 }
2236 }
2237
2238 static void si_dump_streamout(struct pipe_stream_output_info *so)
2239 {
2240 unsigned i;
2241
2242 if (so->num_outputs)
2243 fprintf(stderr, "STREAMOUT\n");
2244
2245 for (i = 0; i < so->num_outputs; i++) {
2246 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2247 so->output[i].start_component;
2248 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2249 i, so->output[i].output_buffer,
2250 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2251 so->output[i].register_index,
2252 mask & 1 ? "x" : "",
2253 mask & 2 ? "y" : "",
2254 mask & 4 ? "z" : "",
2255 mask & 8 ? "w" : "");
2256 }
2257 }
2258
2259 /* On SI, the vertex shader is responsible for writing streamout data
2260 * to buffers. */
2261 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2262 struct si_shader_output_values *outputs,
2263 unsigned noutput)
2264 {
2265 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2266 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2267 LLVMBuilderRef builder = gallivm->builder;
2268 int i, j;
2269 struct lp_build_if_state if_ctx;
2270
2271 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2272 LLVMValueRef so_vtx_count =
2273 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2274
2275 LLVMValueRef tid = get_thread_id(ctx);
2276
2277 /* can_emit = tid < so_vtx_count; */
2278 LLVMValueRef can_emit =
2279 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2280
2281 LLVMValueRef stream_id =
2282 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2283
2284 /* Emit the streamout code conditionally. This actually avoids
2285 * out-of-bounds buffer access. The hw tells us via the SGPR
2286 * (so_vtx_count) which threads are allowed to emit streamout data. */
2287 lp_build_if(&if_ctx, gallivm, can_emit);
2288 {
2289 /* The buffer offset is computed as follows:
2290 * ByteOffset = streamout_offset[buffer_id]*4 +
2291 * (streamout_write_index + thread_id)*stride[buffer_id] +
2292 * attrib_offset
2293 */
2294
2295 LLVMValueRef so_write_index =
2296 LLVMGetParam(ctx->radeon_bld.main_fn,
2297 ctx->param_streamout_write_index);
2298
2299 /* Compute (streamout_write_index + thread_id). */
2300 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2301
2302 /* Compute the write offset for each enabled buffer. */
2303 LLVMValueRef so_write_offset[4] = {};
2304 for (i = 0; i < 4; i++) {
2305 if (!so->stride[i])
2306 continue;
2307
2308 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2309 ctx->param_streamout_offset[i]);
2310 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2311
2312 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2313 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2314 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2315 }
2316
2317 /* Write streamout data. */
2318 for (i = 0; i < so->num_outputs; i++) {
2319 unsigned buf_idx = so->output[i].output_buffer;
2320 unsigned reg = so->output[i].register_index;
2321 unsigned start = so->output[i].start_component;
2322 unsigned num_comps = so->output[i].num_components;
2323 unsigned stream = so->output[i].stream;
2324 LLVMValueRef out[4];
2325 struct lp_build_if_state if_ctx_stream;
2326
2327 assert(num_comps && num_comps <= 4);
2328 if (!num_comps || num_comps > 4)
2329 continue;
2330
2331 if (reg >= noutput)
2332 continue;
2333
2334 /* Load the output as int. */
2335 for (j = 0; j < num_comps; j++) {
2336 out[j] = LLVMBuildBitCast(builder,
2337 outputs[reg].values[start+j],
2338 ctx->i32, "");
2339 }
2340
2341 /* Pack the output. */
2342 LLVMValueRef vdata = NULL;
2343
2344 switch (num_comps) {
2345 case 1: /* as i32 */
2346 vdata = out[0];
2347 break;
2348 case 2: /* as v2i32 */
2349 case 3: /* as v4i32 (aligned to 4) */
2350 case 4: /* as v4i32 */
2351 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2352 for (j = 0; j < num_comps; j++) {
2353 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2354 LLVMConstInt(ctx->i32, j, 0), "");
2355 }
2356 break;
2357 }
2358
2359 LLVMValueRef can_emit_stream =
2360 LLVMBuildICmp(builder, LLVMIntEQ,
2361 stream_id,
2362 lp_build_const_int32(gallivm, stream), "");
2363
2364 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2365 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
2366 vdata, num_comps,
2367 so_write_offset[buf_idx],
2368 LLVMConstInt(ctx->i32, 0, 0),
2369 so->output[i].dst_offset*4);
2370 lp_build_endif(&if_ctx_stream);
2371 }
2372 }
2373 lp_build_endif(&if_ctx);
2374 }
2375
2376
2377 /* Generate export instructions for hardware VS shader stage */
2378 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2379 struct si_shader_output_values *outputs,
2380 unsigned noutput)
2381 {
2382 struct si_shader_context *ctx = si_shader_context(bld_base);
2383 struct si_shader *shader = ctx->shader;
2384 struct lp_build_context *base = &bld_base->base;
2385 struct lp_build_context *uint =
2386 &ctx->radeon_bld.soa.bld_base.uint_bld;
2387 LLVMValueRef args[9];
2388 LLVMValueRef pos_args[4][9] = { { 0 } };
2389 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2390 unsigned semantic_name, semantic_index;
2391 unsigned target;
2392 unsigned param_count = 0;
2393 unsigned pos_idx;
2394 int i;
2395
2396 if (outputs && ctx->shader->selector->so.num_outputs) {
2397 si_llvm_emit_streamout(ctx, outputs, noutput);
2398 }
2399
2400 for (i = 0; i < noutput; i++) {
2401 semantic_name = outputs[i].name;
2402 semantic_index = outputs[i].sid;
2403
2404 handle_semantic:
2405 /* Select the correct target */
2406 switch(semantic_name) {
2407 case TGSI_SEMANTIC_PSIZE:
2408 psize_value = outputs[i].values[0];
2409 continue;
2410 case TGSI_SEMANTIC_EDGEFLAG:
2411 edgeflag_value = outputs[i].values[0];
2412 continue;
2413 case TGSI_SEMANTIC_LAYER:
2414 layer_value = outputs[i].values[0];
2415 semantic_name = TGSI_SEMANTIC_GENERIC;
2416 goto handle_semantic;
2417 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2418 viewport_index_value = outputs[i].values[0];
2419 semantic_name = TGSI_SEMANTIC_GENERIC;
2420 goto handle_semantic;
2421 case TGSI_SEMANTIC_POSITION:
2422 target = V_008DFC_SQ_EXP_POS;
2423 break;
2424 case TGSI_SEMANTIC_COLOR:
2425 case TGSI_SEMANTIC_BCOLOR:
2426 target = V_008DFC_SQ_EXP_PARAM + param_count;
2427 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2428 shader->info.vs_output_param_offset[i] = param_count;
2429 param_count++;
2430 break;
2431 case TGSI_SEMANTIC_CLIPDIST:
2432 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2433 break;
2434 case TGSI_SEMANTIC_CLIPVERTEX:
2435 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2436 continue;
2437 case TGSI_SEMANTIC_PRIMID:
2438 case TGSI_SEMANTIC_FOG:
2439 case TGSI_SEMANTIC_TEXCOORD:
2440 case TGSI_SEMANTIC_GENERIC:
2441 target = V_008DFC_SQ_EXP_PARAM + param_count;
2442 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2443 shader->info.vs_output_param_offset[i] = param_count;
2444 param_count++;
2445 break;
2446 default:
2447 target = 0;
2448 fprintf(stderr,
2449 "Warning: SI unhandled vs output type:%d\n",
2450 semantic_name);
2451 }
2452
2453 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2454
2455 if (target >= V_008DFC_SQ_EXP_POS &&
2456 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2457 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2458 args, sizeof(args));
2459 } else {
2460 lp_build_intrinsic(base->gallivm->builder,
2461 "llvm.SI.export", ctx->voidt,
2462 args, 9, 0);
2463 }
2464
2465 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2466 semantic_name = TGSI_SEMANTIC_GENERIC;
2467 goto handle_semantic;
2468 }
2469 }
2470
2471 shader->info.nr_param_exports = param_count;
2472
2473 /* We need to add the position output manually if it's missing. */
2474 if (!pos_args[0][0]) {
2475 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2476 pos_args[0][1] = uint->zero; /* EXEC mask */
2477 pos_args[0][2] = uint->zero; /* last export? */
2478 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2479 pos_args[0][4] = uint->zero; /* COMPR flag */
2480 pos_args[0][5] = base->zero; /* X */
2481 pos_args[0][6] = base->zero; /* Y */
2482 pos_args[0][7] = base->zero; /* Z */
2483 pos_args[0][8] = base->one; /* W */
2484 }
2485
2486 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2487 if (shader->selector->info.writes_psize ||
2488 shader->selector->info.writes_edgeflag ||
2489 shader->selector->info.writes_viewport_index ||
2490 shader->selector->info.writes_layer) {
2491 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2492 shader->selector->info.writes_psize |
2493 (shader->selector->info.writes_edgeflag << 1) |
2494 (shader->selector->info.writes_layer << 2) |
2495 (shader->selector->info.writes_viewport_index << 3));
2496 pos_args[1][1] = uint->zero; /* EXEC mask */
2497 pos_args[1][2] = uint->zero; /* last export? */
2498 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2499 pos_args[1][4] = uint->zero; /* COMPR flag */
2500 pos_args[1][5] = base->zero; /* X */
2501 pos_args[1][6] = base->zero; /* Y */
2502 pos_args[1][7] = base->zero; /* Z */
2503 pos_args[1][8] = base->zero; /* W */
2504
2505 if (shader->selector->info.writes_psize)
2506 pos_args[1][5] = psize_value;
2507
2508 if (shader->selector->info.writes_edgeflag) {
2509 /* The output is a float, but the hw expects an integer
2510 * with the first bit containing the edge flag. */
2511 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2512 edgeflag_value,
2513 ctx->i32, "");
2514 edgeflag_value = lp_build_min(&bld_base->int_bld,
2515 edgeflag_value,
2516 bld_base->int_bld.one);
2517
2518 /* The LLVM intrinsic expects a float. */
2519 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2520 edgeflag_value,
2521 ctx->f32, "");
2522 }
2523
2524 if (shader->selector->info.writes_layer)
2525 pos_args[1][7] = layer_value;
2526
2527 if (shader->selector->info.writes_viewport_index)
2528 pos_args[1][8] = viewport_index_value;
2529 }
2530
2531 for (i = 0; i < 4; i++)
2532 if (pos_args[i][0])
2533 shader->info.nr_pos_exports++;
2534
2535 pos_idx = 0;
2536 for (i = 0; i < 4; i++) {
2537 if (!pos_args[i][0])
2538 continue;
2539
2540 /* Specify the target we are exporting */
2541 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2542
2543 if (pos_idx == shader->info.nr_pos_exports)
2544 /* Specify that this is the last export */
2545 pos_args[i][2] = uint->one;
2546
2547 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2548 ctx->voidt, pos_args[i], 9, 0);
2549 }
2550 }
2551
2552 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2553 {
2554 struct si_shader_context *ctx = si_shader_context(bld_base);
2555 struct gallivm_state *gallivm = bld_base->base.gallivm;
2556 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2557 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2558 uint64_t inputs;
2559
2560 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2561
2562 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2563 buffer = build_indexed_load_const(ctx, rw_buffers,
2564 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2565
2566 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2567
2568 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2569 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2570 lds_vertex_stride, "");
2571 lds_base = get_tcs_in_current_patch_offset(ctx);
2572 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2573
2574 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2575 while (inputs) {
2576 unsigned i = u_bit_scan64(&inputs);
2577
2578 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2579 lp_build_const_int32(gallivm, 4 * i),
2580 "");
2581
2582 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2583 invocation_id,
2584 lp_build_const_int32(gallivm, i));
2585
2586 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2587 lds_ptr);
2588
2589 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2590 buffer_offset, 0);
2591 }
2592 }
2593
2594 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2595 LLVMValueRef rel_patch_id,
2596 LLVMValueRef invocation_id,
2597 LLVMValueRef tcs_out_current_patch_data_offset)
2598 {
2599 struct si_shader_context *ctx = si_shader_context(bld_base);
2600 struct gallivm_state *gallivm = bld_base->base.gallivm;
2601 struct si_shader *shader = ctx->shader;
2602 unsigned tess_inner_index, tess_outer_index;
2603 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2604 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2605 unsigned stride, outer_comps, inner_comps, i;
2606 struct lp_build_if_state if_ctx, inner_if_ctx;
2607
2608 si_llvm_emit_barrier(NULL, bld_base, NULL);
2609
2610 /* Do this only for invocation 0, because the tess levels are per-patch,
2611 * not per-vertex.
2612 *
2613 * This can't jump, because invocation 0 executes this. It should
2614 * at least mask out the loads and stores for other invocations.
2615 */
2616 lp_build_if(&if_ctx, gallivm,
2617 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2618 invocation_id, bld_base->uint_bld.zero, ""));
2619
2620 /* Determine the layout of one tess factor element in the buffer. */
2621 switch (shader->key.tcs.epilog.prim_mode) {
2622 case PIPE_PRIM_LINES:
2623 stride = 2; /* 2 dwords, 1 vec2 store */
2624 outer_comps = 2;
2625 inner_comps = 0;
2626 break;
2627 case PIPE_PRIM_TRIANGLES:
2628 stride = 4; /* 4 dwords, 1 vec4 store */
2629 outer_comps = 3;
2630 inner_comps = 1;
2631 break;
2632 case PIPE_PRIM_QUADS:
2633 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2634 outer_comps = 4;
2635 inner_comps = 2;
2636 break;
2637 default:
2638 assert(0);
2639 return;
2640 }
2641
2642 /* Load tess_inner and tess_outer from LDS.
2643 * Any invocation can write them, so we can't get them from a temporary.
2644 */
2645 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2646 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2647
2648 lds_base = tcs_out_current_patch_data_offset;
2649 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2650 lp_build_const_int32(gallivm,
2651 tess_inner_index * 4), "");
2652 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2653 lp_build_const_int32(gallivm,
2654 tess_outer_index * 4), "");
2655
2656 for (i = 0; i < outer_comps; i++)
2657 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2658 for (i = 0; i < inner_comps; i++)
2659 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2660
2661 /* Convert the outputs to vectors for stores. */
2662 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2663 vec1 = NULL;
2664
2665 if (stride > 4)
2666 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2667
2668 /* Get the buffer. */
2669 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2670 SI_PARAM_RW_BUFFERS);
2671 buffer = build_indexed_load_const(ctx, rw_buffers,
2672 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2673
2674 /* Get the offset. */
2675 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2676 SI_PARAM_TESS_FACTOR_OFFSET);
2677 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2678 lp_build_const_int32(gallivm, 4 * stride), "");
2679
2680 lp_build_if(&inner_if_ctx, gallivm,
2681 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2682 rel_patch_id, bld_base->uint_bld.zero, ""));
2683
2684 /* Store the dynamic HS control word. */
2685 build_tbuffer_store_dwords(ctx, buffer,
2686 lp_build_const_int32(gallivm, 0x80000000),
2687 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2688
2689 lp_build_endif(&inner_if_ctx);
2690
2691 /* Store the tessellation factors. */
2692 build_tbuffer_store_dwords(ctx, buffer, vec0,
2693 MIN2(stride, 4), byteoffset, tf_base, 4);
2694 if (vec1)
2695 build_tbuffer_store_dwords(ctx, buffer, vec1,
2696 stride - 4, byteoffset, tf_base, 20);
2697 lp_build_endif(&if_ctx);
2698 }
2699
2700 /* This only writes the tessellation factor levels. */
2701 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2702 {
2703 struct si_shader_context *ctx = si_shader_context(bld_base);
2704 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2705
2706 rel_patch_id = get_rel_patch_id(ctx);
2707 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2708 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2709
2710 if (!ctx->is_monolithic) {
2711 /* Return epilog parameters from this function. */
2712 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2713 LLVMValueRef ret = ctx->return_value;
2714 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2715 unsigned vgpr;
2716
2717 /* RW_BUFFERS pointer */
2718 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2719 SI_PARAM_RW_BUFFERS);
2720 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2721 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2722 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2723 bld_base->uint_bld.zero, "");
2724 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2725 bld_base->uint_bld.one, "");
2726 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2727 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2728
2729 /* Tess factor buffer soffset is after user SGPRs. */
2730 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2731 SI_PARAM_TESS_FACTOR_OFFSET);
2732 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2733 SI_TCS_NUM_USER_SGPR + 1, "");
2734
2735 /* VGPRs */
2736 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2737 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2738 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2739
2740 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2741 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2742 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2743 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2744 ctx->return_value = ret;
2745 return;
2746 }
2747
2748 si_copy_tcs_inputs(bld_base);
2749 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2750 }
2751
2752 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2753 {
2754 struct si_shader_context *ctx = si_shader_context(bld_base);
2755 struct si_shader *shader = ctx->shader;
2756 struct tgsi_shader_info *info = &shader->selector->info;
2757 struct gallivm_state *gallivm = bld_base->base.gallivm;
2758 unsigned i, chan;
2759 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2760 ctx->param_rel_auto_id);
2761 LLVMValueRef vertex_dw_stride =
2762 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2763 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2764 vertex_dw_stride, "");
2765
2766 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2767 * its inputs from it. */
2768 for (i = 0; i < info->num_outputs; i++) {
2769 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2770 unsigned name = info->output_semantic_name[i];
2771 unsigned index = info->output_semantic_index[i];
2772 int param = si_shader_io_get_unique_index(name, index);
2773 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2774 lp_build_const_int32(gallivm, param * 4), "");
2775
2776 for (chan = 0; chan < 4; chan++) {
2777 lds_store(bld_base, chan, dw_addr,
2778 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2779 }
2780 }
2781 }
2782
2783 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2784 {
2785 struct si_shader_context *ctx = si_shader_context(bld_base);
2786 struct gallivm_state *gallivm = bld_base->base.gallivm;
2787 struct si_shader *es = ctx->shader;
2788 struct tgsi_shader_info *info = &es->selector->info;
2789 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2790 ctx->param_es2gs_offset);
2791 unsigned chan;
2792 int i;
2793
2794 for (i = 0; i < info->num_outputs; i++) {
2795 LLVMValueRef *out_ptr =
2796 ctx->radeon_bld.soa.outputs[i];
2797 int param_index;
2798
2799 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2800 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2801 continue;
2802
2803 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2804 info->output_semantic_index[i]);
2805
2806 for (chan = 0; chan < 4; chan++) {
2807 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2808 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2809
2810 build_tbuffer_store(ctx,
2811 ctx->esgs_ring,
2812 out_val, 1,
2813 LLVMGetUndef(ctx->i32), soffset,
2814 (4 * param_index + chan) * 4,
2815 V_008F0C_BUF_DATA_FORMAT_32,
2816 V_008F0C_BUF_NUM_FORMAT_UINT,
2817 0, 0, 1, 1, 0);
2818 }
2819 }
2820 }
2821
2822 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2823 {
2824 struct si_shader_context *ctx = si_shader_context(bld_base);
2825 struct gallivm_state *gallivm = bld_base->base.gallivm;
2826 LLVMValueRef args[2];
2827
2828 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2829 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2830 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2831 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2832 }
2833
2834 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2835 {
2836 struct si_shader_context *ctx = si_shader_context(bld_base);
2837 struct gallivm_state *gallivm = bld_base->base.gallivm;
2838 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2839 struct si_shader_output_values *outputs = NULL;
2840 int i,j;
2841
2842 assert(!ctx->is_gs_copy_shader);
2843
2844 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2845
2846 /* Vertex color clamping.
2847 *
2848 * This uses a state constant loaded in a user data SGPR and
2849 * an IF statement is added that clamps all colors if the constant
2850 * is true.
2851 */
2852 if (ctx->type == PIPE_SHADER_VERTEX) {
2853 struct lp_build_if_state if_ctx;
2854 LLVMValueRef cond = NULL;
2855 LLVMValueRef addr, val;
2856
2857 for (i = 0; i < info->num_outputs; i++) {
2858 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2859 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2860 continue;
2861
2862 /* We've found a color. */
2863 if (!cond) {
2864 /* The state is in the first bit of the user SGPR. */
2865 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2866 SI_PARAM_VS_STATE_BITS);
2867 cond = LLVMBuildTrunc(gallivm->builder, cond,
2868 ctx->i1, "");
2869 lp_build_if(&if_ctx, gallivm, cond);
2870 }
2871
2872 for (j = 0; j < 4; j++) {
2873 addr = ctx->radeon_bld.soa.outputs[i][j];
2874 val = LLVMBuildLoad(gallivm->builder, addr, "");
2875 val = radeon_llvm_saturate(bld_base, val);
2876 LLVMBuildStore(gallivm->builder, val, addr);
2877 }
2878 }
2879
2880 if (cond)
2881 lp_build_endif(&if_ctx);
2882 }
2883
2884 for (i = 0; i < info->num_outputs; i++) {
2885 outputs[i].name = info->output_semantic_name[i];
2886 outputs[i].sid = info->output_semantic_index[i];
2887
2888 for (j = 0; j < 4; j++)
2889 outputs[i].values[j] =
2890 LLVMBuildLoad(gallivm->builder,
2891 ctx->radeon_bld.soa.outputs[i][j],
2892 "");
2893 }
2894
2895 if (ctx->is_monolithic) {
2896 /* Export PrimitiveID when PS needs it. */
2897 if (si_vs_exports_prim_id(ctx->shader)) {
2898 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2899 outputs[i].sid = 0;
2900 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2901 get_primitive_id(bld_base, 0));
2902 outputs[i].values[1] = bld_base->base.undef;
2903 outputs[i].values[2] = bld_base->base.undef;
2904 outputs[i].values[3] = bld_base->base.undef;
2905 i++;
2906 }
2907 } else {
2908 /* Return the primitive ID from the LLVM function. */
2909 ctx->return_value =
2910 LLVMBuildInsertValue(gallivm->builder,
2911 ctx->return_value,
2912 bitcast(bld_base, TGSI_TYPE_FLOAT,
2913 get_primitive_id(bld_base, 0)),
2914 VS_EPILOG_PRIMID_LOC, "");
2915 }
2916
2917 si_llvm_export_vs(bld_base, outputs, i);
2918 FREE(outputs);
2919 }
2920
2921 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2922 LLVMValueRef depth, LLVMValueRef stencil,
2923 LLVMValueRef samplemask)
2924 {
2925 struct si_shader_context *ctx = si_shader_context(bld_base);
2926 struct lp_build_context *base = &bld_base->base;
2927 struct lp_build_context *uint = &bld_base->uint_bld;
2928 LLVMValueRef args[9];
2929 unsigned mask = 0;
2930
2931 assert(depth || stencil || samplemask);
2932
2933 args[1] = uint->one; /* whether the EXEC mask is valid */
2934 args[2] = uint->one; /* DONE bit */
2935
2936 /* Specify the target we are exporting */
2937 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2938
2939 args[4] = uint->zero; /* COMP flag */
2940 args[5] = base->undef; /* R, depth */
2941 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2942 args[7] = base->undef; /* B, sample mask */
2943 args[8] = base->undef; /* A, alpha to mask */
2944
2945 if (depth) {
2946 args[5] = depth;
2947 mask |= 0x1;
2948 }
2949
2950 if (stencil) {
2951 args[6] = stencil;
2952 mask |= 0x2;
2953 }
2954
2955 if (samplemask) {
2956 args[7] = samplemask;
2957 mask |= 0x4;
2958 }
2959
2960 /* SI (except OLAND) has a bug that it only looks
2961 * at the X writemask component. */
2962 if (ctx->screen->b.chip_class == SI &&
2963 ctx->screen->b.family != CHIP_OLAND)
2964 mask |= 0x1;
2965
2966 /* Specify which components to enable */
2967 args[0] = lp_build_const_int32(base->gallivm, mask);
2968
2969 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2970 ctx->voidt, args, 9, 0);
2971 }
2972
2973 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2974 LLVMValueRef *color, unsigned index,
2975 unsigned samplemask_param,
2976 bool is_last)
2977 {
2978 struct si_shader_context *ctx = si_shader_context(bld_base);
2979 struct lp_build_context *base = &bld_base->base;
2980 int i;
2981
2982 /* Clamp color */
2983 if (ctx->shader->key.ps.epilog.clamp_color)
2984 for (i = 0; i < 4; i++)
2985 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2986
2987 /* Alpha to one */
2988 if (ctx->shader->key.ps.epilog.alpha_to_one)
2989 color[3] = base->one;
2990
2991 /* Alpha test */
2992 if (index == 0 &&
2993 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2994 si_alpha_test(bld_base, color[3]);
2995
2996 /* Line & polygon smoothing */
2997 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2998 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2999 samplemask_param);
3000
3001 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3002 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3003 LLVMValueRef args[8][9];
3004 int c, last = -1;
3005
3006 /* Get the export arguments, also find out what the last one is. */
3007 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3008 si_llvm_init_export_args(bld_base, color,
3009 V_008DFC_SQ_EXP_MRT + c, args[c]);
3010 if (args[c][0] != bld_base->uint_bld.zero)
3011 last = c;
3012 }
3013
3014 /* Emit all exports. */
3015 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3016 if (is_last && last == c) {
3017 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3018 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3019 } else if (args[c][0] == bld_base->uint_bld.zero)
3020 continue; /* unnecessary NULL export */
3021
3022 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3023 ctx->voidt, args[c], 9, 0);
3024 }
3025 } else {
3026 LLVMValueRef args[9];
3027
3028 /* Export */
3029 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3030 args);
3031 if (is_last) {
3032 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3033 args[2] = bld_base->uint_bld.one; /* DONE bit */
3034 } else if (args[0] == bld_base->uint_bld.zero)
3035 return; /* unnecessary NULL export */
3036
3037 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3038 ctx->voidt, args, 9, 0);
3039 }
3040 }
3041
3042 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3043 {
3044 struct si_shader_context *ctx = si_shader_context(bld_base);
3045 struct lp_build_context *base = &bld_base->base;
3046 struct lp_build_context *uint = &bld_base->uint_bld;
3047 LLVMValueRef args[9];
3048
3049 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3050 args[1] = uint->one; /* whether the EXEC mask is valid */
3051 args[2] = uint->one; /* DONE bit */
3052 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3053 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3054 args[5] = uint->undef; /* R */
3055 args[6] = uint->undef; /* G */
3056 args[7] = uint->undef; /* B */
3057 args[8] = uint->undef; /* A */
3058
3059 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3060 ctx->voidt, args, 9, 0);
3061 }
3062
3063 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3064 {
3065 struct si_shader_context *ctx = si_shader_context(bld_base);
3066 struct si_shader *shader = ctx->shader;
3067 struct lp_build_context *base = &bld_base->base;
3068 struct tgsi_shader_info *info = &shader->selector->info;
3069 LLVMBuilderRef builder = base->gallivm->builder;
3070 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3071 int last_color_export = -1;
3072 int i;
3073
3074 /* Determine the last export. If MRTZ is present, it's always last.
3075 * Otherwise, find the last color export.
3076 */
3077 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3078 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3079
3080 /* Don't export NULL and return if alpha-test is enabled. */
3081 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3082 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3083 (spi_format & 0xf) == 0)
3084 spi_format |= V_028714_SPI_SHADER_32_AR;
3085
3086 for (i = 0; i < info->num_outputs; i++) {
3087 unsigned index = info->output_semantic_index[i];
3088
3089 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3090 continue;
3091
3092 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3093 if (shader->key.ps.epilog.last_cbuf > 0) {
3094 /* Just set this if any of the colorbuffers are enabled. */
3095 if (spi_format &
3096 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3097 last_color_export = i;
3098 continue;
3099 }
3100
3101 if ((spi_format >> (index * 4)) & 0xf)
3102 last_color_export = i;
3103 }
3104
3105 /* If there are no outputs, export NULL. */
3106 if (last_color_export == -1) {
3107 si_export_null(bld_base);
3108 return;
3109 }
3110 }
3111
3112 for (i = 0; i < info->num_outputs; i++) {
3113 unsigned semantic_name = info->output_semantic_name[i];
3114 unsigned semantic_index = info->output_semantic_index[i];
3115 unsigned j;
3116 LLVMValueRef color[4] = {};
3117
3118 /* Select the correct target */
3119 switch (semantic_name) {
3120 case TGSI_SEMANTIC_POSITION:
3121 depth = LLVMBuildLoad(builder,
3122 ctx->radeon_bld.soa.outputs[i][2], "");
3123 break;
3124 case TGSI_SEMANTIC_STENCIL:
3125 stencil = LLVMBuildLoad(builder,
3126 ctx->radeon_bld.soa.outputs[i][1], "");
3127 break;
3128 case TGSI_SEMANTIC_SAMPLEMASK:
3129 samplemask = LLVMBuildLoad(builder,
3130 ctx->radeon_bld.soa.outputs[i][0], "");
3131 break;
3132 case TGSI_SEMANTIC_COLOR:
3133 for (j = 0; j < 4; j++)
3134 color[j] = LLVMBuildLoad(builder,
3135 ctx->radeon_bld.soa.outputs[i][j], "");
3136
3137 si_export_mrt_color(bld_base, color, semantic_index,
3138 SI_PARAM_SAMPLE_COVERAGE,
3139 last_color_export == i);
3140 break;
3141 default:
3142 fprintf(stderr,
3143 "Warning: SI unhandled fs output type:%d\n",
3144 semantic_name);
3145 }
3146 }
3147
3148 if (depth || stencil || samplemask)
3149 si_export_mrt_z(bld_base, depth, stencil, samplemask);
3150 }
3151
3152 /**
3153 * Return PS outputs in this order:
3154 *
3155 * v[0:3] = color0.xyzw
3156 * v[4:7] = color1.xyzw
3157 * ...
3158 * vN+0 = Depth
3159 * vN+1 = Stencil
3160 * vN+2 = SampleMask
3161 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3162 *
3163 * The alpha-ref SGPR is returned via its original location.
3164 */
3165 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3166 {
3167 struct si_shader_context *ctx = si_shader_context(bld_base);
3168 struct si_shader *shader = ctx->shader;
3169 struct lp_build_context *base = &bld_base->base;
3170 struct tgsi_shader_info *info = &shader->selector->info;
3171 LLVMBuilderRef builder = base->gallivm->builder;
3172 unsigned i, j, first_vgpr, vgpr;
3173
3174 LLVMValueRef color[8][4] = {};
3175 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3176 LLVMValueRef ret;
3177
3178 /* Read the output values. */
3179 for (i = 0; i < info->num_outputs; i++) {
3180 unsigned semantic_name = info->output_semantic_name[i];
3181 unsigned semantic_index = info->output_semantic_index[i];
3182
3183 switch (semantic_name) {
3184 case TGSI_SEMANTIC_COLOR:
3185 assert(semantic_index < 8);
3186 for (j = 0; j < 4; j++) {
3187 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3188 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3189 color[semantic_index][j] = result;
3190 }
3191 break;
3192 case TGSI_SEMANTIC_POSITION:
3193 depth = LLVMBuildLoad(builder,
3194 ctx->radeon_bld.soa.outputs[i][2], "");
3195 break;
3196 case TGSI_SEMANTIC_STENCIL:
3197 stencil = LLVMBuildLoad(builder,
3198 ctx->radeon_bld.soa.outputs[i][1], "");
3199 break;
3200 case TGSI_SEMANTIC_SAMPLEMASK:
3201 samplemask = LLVMBuildLoad(builder,
3202 ctx->radeon_bld.soa.outputs[i][0], "");
3203 break;
3204 default:
3205 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3206 semantic_name);
3207 }
3208 }
3209
3210 /* Fill the return structure. */
3211 ret = ctx->return_value;
3212
3213 /* Set SGPRs. */
3214 ret = LLVMBuildInsertValue(builder, ret,
3215 bitcast(bld_base, TGSI_TYPE_SIGNED,
3216 LLVMGetParam(ctx->radeon_bld.main_fn,
3217 SI_PARAM_ALPHA_REF)),
3218 SI_SGPR_ALPHA_REF, "");
3219
3220 /* Set VGPRs */
3221 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3222 for (i = 0; i < ARRAY_SIZE(color); i++) {
3223 if (!color[i][0])
3224 continue;
3225
3226 for (j = 0; j < 4; j++)
3227 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3228 }
3229 if (depth)
3230 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3231 if (stencil)
3232 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3233 if (samplemask)
3234 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3235
3236 /* Add the input sample mask for smoothing at the end. */
3237 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3238 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3239 ret = LLVMBuildInsertValue(builder, ret,
3240 LLVMGetParam(ctx->radeon_bld.main_fn,
3241 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3242
3243 ctx->return_value = ret;
3244 }
3245
3246 /**
3247 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3248 * buffer in number of elements and return it as an i32.
3249 */
3250 static LLVMValueRef get_buffer_size(
3251 struct lp_build_tgsi_context *bld_base,
3252 LLVMValueRef descriptor)
3253 {
3254 struct si_shader_context *ctx = si_shader_context(bld_base);
3255 struct gallivm_state *gallivm = bld_base->base.gallivm;
3256 LLVMBuilderRef builder = gallivm->builder;
3257 LLVMValueRef size =
3258 LLVMBuildExtractElement(builder, descriptor,
3259 lp_build_const_int32(gallivm, 6), "");
3260
3261 if (ctx->screen->b.chip_class >= VI) {
3262 /* On VI, the descriptor contains the size in bytes,
3263 * but TXQ must return the size in elements.
3264 * The stride is always non-zero for resources using TXQ.
3265 */
3266 LLVMValueRef stride =
3267 LLVMBuildExtractElement(builder, descriptor,
3268 lp_build_const_int32(gallivm, 5), "");
3269 stride = LLVMBuildLShr(builder, stride,
3270 lp_build_const_int32(gallivm, 16), "");
3271 stride = LLVMBuildAnd(builder, stride,
3272 lp_build_const_int32(gallivm, 0x3FFF), "");
3273
3274 size = LLVMBuildUDiv(builder, size, stride, "");
3275 }
3276
3277 return size;
3278 }
3279
3280 /**
3281 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3282 * intrinsic names).
3283 */
3284 static void build_int_type_name(
3285 LLVMTypeRef type,
3286 char *buf, unsigned bufsize)
3287 {
3288 assert(bufsize >= 6);
3289
3290 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3291 snprintf(buf, bufsize, "v%ui32",
3292 LLVMGetVectorSize(type));
3293 else
3294 strcpy(buf, "i32");
3295 }
3296
3297 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3298 struct lp_build_tgsi_context *bld_base,
3299 struct lp_build_emit_data *emit_data);
3300
3301 /* Prevent optimizations (at least of memory accesses) across the current
3302 * point in the program by emitting empty inline assembly that is marked as
3303 * having side effects.
3304 */
3305 static void emit_optimization_barrier(struct si_shader_context *ctx)
3306 {
3307 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3308 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3309 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3310 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3311 }
3312
3313 static void emit_waitcnt(struct si_shader_context *ctx)
3314 {
3315 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3316 LLVMBuilderRef builder = gallivm->builder;
3317 LLVMValueRef args[1] = {
3318 lp_build_const_int32(gallivm, 0xf70)
3319 };
3320 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3321 ctx->voidt, args, 1, LLVMNoUnwindAttribute);
3322 }
3323
3324 static void membar_emit(
3325 const struct lp_build_tgsi_action *action,
3326 struct lp_build_tgsi_context *bld_base,
3327 struct lp_build_emit_data *emit_data)
3328 {
3329 struct si_shader_context *ctx = si_shader_context(bld_base);
3330
3331 emit_waitcnt(ctx);
3332 }
3333
3334 static LLVMValueRef
3335 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3336 const struct tgsi_full_src_register *reg)
3337 {
3338 LLVMValueRef ind_index;
3339 LLVMValueRef rsrc_ptr;
3340
3341 if (!reg->Register.Indirect)
3342 return ctx->shader_buffers[reg->Register.Index];
3343
3344 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3345 reg->Register.Index,
3346 SI_NUM_SHADER_BUFFERS);
3347
3348 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3349 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3350 }
3351
3352 static bool tgsi_is_array_sampler(unsigned target)
3353 {
3354 return target == TGSI_TEXTURE_1D_ARRAY ||
3355 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3356 target == TGSI_TEXTURE_2D_ARRAY ||
3357 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3358 target == TGSI_TEXTURE_CUBE_ARRAY ||
3359 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3360 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3361 }
3362
3363 static bool tgsi_is_array_image(unsigned target)
3364 {
3365 return target == TGSI_TEXTURE_3D ||
3366 target == TGSI_TEXTURE_CUBE ||
3367 target == TGSI_TEXTURE_1D_ARRAY ||
3368 target == TGSI_TEXTURE_2D_ARRAY ||
3369 target == TGSI_TEXTURE_CUBE_ARRAY ||
3370 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3371 }
3372
3373 /**
3374 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3375 *
3376 * At least on Tonga, executing image stores on images with DCC enabled and
3377 * non-trivial can eventually lead to lockups. This can occur when an
3378 * application binds an image as read-only but then uses a shader that writes
3379 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3380 * program termination) in this case, but it doesn't cost much to be a bit
3381 * nicer: disabling DCC in the shader still leads to undefined results but
3382 * avoids the lockup.
3383 */
3384 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3385 LLVMValueRef rsrc)
3386 {
3387 if (ctx->screen->b.chip_class <= CIK) {
3388 return rsrc;
3389 } else {
3390 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3391 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3392 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3393 LLVMValueRef tmp;
3394
3395 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3396 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3397 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3398 }
3399 }
3400
3401 /**
3402 * Load the resource descriptor for \p image.
3403 */
3404 static void
3405 image_fetch_rsrc(
3406 struct lp_build_tgsi_context *bld_base,
3407 const struct tgsi_full_src_register *image,
3408 bool dcc_off,
3409 LLVMValueRef *rsrc)
3410 {
3411 struct si_shader_context *ctx = si_shader_context(bld_base);
3412
3413 assert(image->Register.File == TGSI_FILE_IMAGE);
3414
3415 if (!image->Register.Indirect) {
3416 /* Fast path: use preloaded resources */
3417 *rsrc = ctx->images[image->Register.Index];
3418 } else {
3419 /* Indexing and manual load */
3420 LLVMValueRef ind_index;
3421 LLVMValueRef rsrc_ptr;
3422 LLVMValueRef tmp;
3423
3424 /* From the GL_ARB_shader_image_load_store extension spec:
3425 *
3426 * If a shader performs an image load, store, or atomic
3427 * operation using an image variable declared as an array,
3428 * and if the index used to select an individual element is
3429 * negative or greater than or equal to the size of the
3430 * array, the results of the operation are undefined but may
3431 * not lead to termination.
3432 */
3433 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3434 image->Register.Index,
3435 SI_NUM_IMAGES);
3436
3437 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3438 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3439 if (dcc_off)
3440 tmp = force_dcc_off(ctx, tmp);
3441 *rsrc = tmp;
3442 }
3443 }
3444
3445 static LLVMValueRef image_fetch_coords(
3446 struct lp_build_tgsi_context *bld_base,
3447 const struct tgsi_full_instruction *inst,
3448 unsigned src)
3449 {
3450 struct gallivm_state *gallivm = bld_base->base.gallivm;
3451 LLVMBuilderRef builder = gallivm->builder;
3452 unsigned target = inst->Memory.Texture;
3453 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3454 LLVMValueRef coords[4];
3455 LLVMValueRef tmp;
3456 int chan;
3457
3458 for (chan = 0; chan < num_coords; ++chan) {
3459 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3460 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3461 coords[chan] = tmp;
3462 }
3463
3464 if (num_coords == 1)
3465 return coords[0];
3466
3467 if (num_coords == 3) {
3468 /* LLVM has difficulties lowering 3-element vectors. */
3469 coords[3] = bld_base->uint_bld.undef;
3470 num_coords = 4;
3471 }
3472
3473 return lp_build_gather_values(gallivm, coords, num_coords);
3474 }
3475
3476 /**
3477 * Append the extra mode bits that are used by image load and store.
3478 */
3479 static void image_append_args(
3480 struct si_shader_context *ctx,
3481 struct lp_build_emit_data * emit_data,
3482 unsigned target,
3483 bool atomic)
3484 {
3485 const struct tgsi_full_instruction *inst = emit_data->inst;
3486 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3487 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3488
3489 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3490 emit_data->args[emit_data->arg_count++] =
3491 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3492 if (!atomic) {
3493 emit_data->args[emit_data->arg_count++] =
3494 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3495 i1true : i1false; /* glc */
3496 }
3497 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3498 }
3499
3500 /**
3501 * Given a 256 bit resource, extract the top half (which stores the buffer
3502 * resource in the case of textures and images).
3503 */
3504 static LLVMValueRef extract_rsrc_top_half(
3505 struct si_shader_context *ctx,
3506 LLVMValueRef rsrc)
3507 {
3508 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3509 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3510 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3511
3512 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3513 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3514 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3515
3516 return rsrc;
3517 }
3518
3519 /**
3520 * Append the resource and indexing arguments for buffer intrinsics.
3521 *
3522 * \param rsrc the v4i32 buffer resource
3523 * \param index index into the buffer (stride-based)
3524 * \param offset byte offset into the buffer
3525 */
3526 static void buffer_append_args(
3527 struct si_shader_context *ctx,
3528 struct lp_build_emit_data *emit_data,
3529 LLVMValueRef rsrc,
3530 LLVMValueRef index,
3531 LLVMValueRef offset,
3532 bool atomic)
3533 {
3534 const struct tgsi_full_instruction *inst = emit_data->inst;
3535 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3536 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3537
3538 emit_data->args[emit_data->arg_count++] = rsrc;
3539 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3540 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3541 if (!atomic) {
3542 emit_data->args[emit_data->arg_count++] =
3543 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3544 i1true : i1false; /* glc */
3545 }
3546 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3547 }
3548
3549 static void load_fetch_args(
3550 struct lp_build_tgsi_context * bld_base,
3551 struct lp_build_emit_data * emit_data)
3552 {
3553 struct si_shader_context *ctx = si_shader_context(bld_base);
3554 struct gallivm_state *gallivm = bld_base->base.gallivm;
3555 const struct tgsi_full_instruction * inst = emit_data->inst;
3556 unsigned target = inst->Memory.Texture;
3557 LLVMValueRef rsrc;
3558
3559 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3560
3561 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3562 LLVMBuilderRef builder = gallivm->builder;
3563 LLVMValueRef offset;
3564 LLVMValueRef tmp;
3565
3566 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3567
3568 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3569 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3570
3571 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3572 offset, false);
3573 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3574 LLVMValueRef coords;
3575
3576 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3577 coords = image_fetch_coords(bld_base, inst, 1);
3578
3579 if (target == TGSI_TEXTURE_BUFFER) {
3580 rsrc = extract_rsrc_top_half(ctx, rsrc);
3581 buffer_append_args(ctx, emit_data, rsrc, coords,
3582 bld_base->uint_bld.zero, false);
3583 } else {
3584 emit_data->args[0] = coords;
3585 emit_data->args[1] = rsrc;
3586 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3587 emit_data->arg_count = 3;
3588
3589 image_append_args(ctx, emit_data, target, false);
3590 }
3591 }
3592 }
3593
3594 static void load_emit_buffer(struct si_shader_context *ctx,
3595 struct lp_build_emit_data *emit_data)
3596 {
3597 const struct tgsi_full_instruction *inst = emit_data->inst;
3598 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3599 LLVMBuilderRef builder = gallivm->builder;
3600 uint writemask = inst->Dst[0].Register.WriteMask;
3601 uint count = util_last_bit(writemask);
3602 const char *intrinsic_name;
3603 LLVMTypeRef dst_type;
3604
3605 switch (count) {
3606 case 1:
3607 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3608 dst_type = ctx->f32;
3609 break;
3610 case 2:
3611 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3612 dst_type = LLVMVectorType(ctx->f32, 2);
3613 break;
3614 default: // 3 & 4
3615 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3616 dst_type = ctx->v4f32;
3617 count = 4;
3618 }
3619
3620 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3621 builder, intrinsic_name, dst_type,
3622 emit_data->args, emit_data->arg_count,
3623 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3624 }
3625
3626 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3627 const struct tgsi_full_instruction *inst,
3628 LLVMTypeRef type, int arg)
3629 {
3630 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3631 LLVMBuilderRef builder = gallivm->builder;
3632 LLVMValueRef offset, ptr;
3633 int addr_space;
3634
3635 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3636 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3637
3638 ptr = ctx->shared_memory;
3639 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3640 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3641 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3642
3643 return ptr;
3644 }
3645
3646 static void load_emit_memory(
3647 struct si_shader_context *ctx,
3648 struct lp_build_emit_data *emit_data)
3649 {
3650 const struct tgsi_full_instruction *inst = emit_data->inst;
3651 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3652 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3653 LLVMBuilderRef builder = gallivm->builder;
3654 unsigned writemask = inst->Dst[0].Register.WriteMask;
3655 LLVMValueRef channels[4], ptr, derived_ptr, index;
3656 int chan;
3657
3658 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3659
3660 for (chan = 0; chan < 4; ++chan) {
3661 if (!(writemask & (1 << chan))) {
3662 channels[chan] = LLVMGetUndef(base->elem_type);
3663 continue;
3664 }
3665
3666 index = lp_build_const_int32(gallivm, chan);
3667 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3668 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3669 }
3670 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3671 }
3672
3673 static void load_emit(
3674 const struct lp_build_tgsi_action *action,
3675 struct lp_build_tgsi_context *bld_base,
3676 struct lp_build_emit_data *emit_data)
3677 {
3678 struct si_shader_context *ctx = si_shader_context(bld_base);
3679 struct gallivm_state *gallivm = bld_base->base.gallivm;
3680 LLVMBuilderRef builder = gallivm->builder;
3681 const struct tgsi_full_instruction * inst = emit_data->inst;
3682 char intrinsic_name[32];
3683 char coords_type[8];
3684
3685 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3686 load_emit_memory(ctx, emit_data);
3687 return;
3688 }
3689
3690 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3691 emit_waitcnt(ctx);
3692
3693 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3694 load_emit_buffer(ctx, emit_data);
3695 return;
3696 }
3697
3698 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3699 emit_data->output[emit_data->chan] =
3700 lp_build_intrinsic(
3701 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3702 emit_data->args, emit_data->arg_count,
3703 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3704 } else {
3705 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3706 coords_type, sizeof(coords_type));
3707
3708 snprintf(intrinsic_name, sizeof(intrinsic_name),
3709 "llvm.amdgcn.image.load.%s", coords_type);
3710
3711 emit_data->output[emit_data->chan] =
3712 lp_build_intrinsic(
3713 builder, intrinsic_name, emit_data->dst_type,
3714 emit_data->args, emit_data->arg_count,
3715 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3716 }
3717 }
3718
3719 static void store_fetch_args(
3720 struct lp_build_tgsi_context * bld_base,
3721 struct lp_build_emit_data * emit_data)
3722 {
3723 struct si_shader_context *ctx = si_shader_context(bld_base);
3724 struct gallivm_state *gallivm = bld_base->base.gallivm;
3725 LLVMBuilderRef builder = gallivm->builder;
3726 const struct tgsi_full_instruction * inst = emit_data->inst;
3727 struct tgsi_full_src_register memory;
3728 LLVMValueRef chans[4];
3729 LLVMValueRef data;
3730 LLVMValueRef rsrc;
3731 unsigned chan;
3732
3733 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3734
3735 for (chan = 0; chan < 4; ++chan) {
3736 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3737 }
3738 data = lp_build_gather_values(gallivm, chans, 4);
3739
3740 emit_data->args[emit_data->arg_count++] = data;
3741
3742 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3743
3744 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3745 LLVMValueRef offset;
3746 LLVMValueRef tmp;
3747
3748 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3749
3750 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3751 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3752
3753 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3754 offset, false);
3755 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3756 unsigned target = inst->Memory.Texture;
3757 LLVMValueRef coords;
3758
3759 coords = image_fetch_coords(bld_base, inst, 0);
3760
3761 if (target == TGSI_TEXTURE_BUFFER) {
3762 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3763
3764 rsrc = extract_rsrc_top_half(ctx, rsrc);
3765 buffer_append_args(ctx, emit_data, rsrc, coords,
3766 bld_base->uint_bld.zero, false);
3767 } else {
3768 emit_data->args[1] = coords;
3769 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3770 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3771 emit_data->arg_count = 4;
3772
3773 image_append_args(ctx, emit_data, target, false);
3774 }
3775 }
3776 }
3777
3778 static void store_emit_buffer(
3779 struct si_shader_context *ctx,
3780 struct lp_build_emit_data *emit_data)
3781 {
3782 const struct tgsi_full_instruction *inst = emit_data->inst;
3783 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3784 LLVMBuilderRef builder = gallivm->builder;
3785 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3786 LLVMValueRef base_data = emit_data->args[0];
3787 LLVMValueRef base_offset = emit_data->args[3];
3788 unsigned writemask = inst->Dst[0].Register.WriteMask;
3789
3790 while (writemask) {
3791 int start, count;
3792 const char *intrinsic_name;
3793 LLVMValueRef data;
3794 LLVMValueRef offset;
3795 LLVMValueRef tmp;
3796
3797 u_bit_scan_consecutive_range(&writemask, &start, &count);
3798
3799 /* Due to an LLVM limitation, split 3-element writes
3800 * into a 2-element and a 1-element write. */
3801 if (count == 3) {
3802 writemask |= 1 << (start + 2);
3803 count = 2;
3804 }
3805
3806 if (count == 4) {
3807 data = base_data;
3808 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3809 } else if (count == 2) {
3810 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3811
3812 tmp = LLVMBuildExtractElement(
3813 builder, base_data,
3814 lp_build_const_int32(gallivm, start), "");
3815 data = LLVMBuildInsertElement(
3816 builder, LLVMGetUndef(v2f32), tmp,
3817 uint_bld->zero, "");
3818
3819 tmp = LLVMBuildExtractElement(
3820 builder, base_data,
3821 lp_build_const_int32(gallivm, start + 1), "");
3822 data = LLVMBuildInsertElement(
3823 builder, data, tmp, uint_bld->one, "");
3824
3825 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3826 } else {
3827 assert(count == 1);
3828 data = LLVMBuildExtractElement(
3829 builder, base_data,
3830 lp_build_const_int32(gallivm, start), "");
3831 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3832 }
3833
3834 offset = base_offset;
3835 if (start != 0) {
3836 offset = LLVMBuildAdd(
3837 builder, offset,
3838 lp_build_const_int32(gallivm, start * 4), "");
3839 }
3840
3841 emit_data->args[0] = data;
3842 emit_data->args[3] = offset;
3843
3844 lp_build_intrinsic(
3845 builder, intrinsic_name, emit_data->dst_type,
3846 emit_data->args, emit_data->arg_count,
3847 LLVMNoUnwindAttribute);
3848 }
3849 }
3850
3851 static void store_emit_memory(
3852 struct si_shader_context *ctx,
3853 struct lp_build_emit_data *emit_data)
3854 {
3855 const struct tgsi_full_instruction *inst = emit_data->inst;
3856 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3857 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3858 LLVMBuilderRef builder = gallivm->builder;
3859 unsigned writemask = inst->Dst[0].Register.WriteMask;
3860 LLVMValueRef ptr, derived_ptr, data, index;
3861 int chan;
3862
3863 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3864
3865 for (chan = 0; chan < 4; ++chan) {
3866 if (!(writemask & (1 << chan))) {
3867 continue;
3868 }
3869 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3870 index = lp_build_const_int32(gallivm, chan);
3871 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3872 LLVMBuildStore(builder, data, derived_ptr);
3873 }
3874 }
3875
3876 static void store_emit(
3877 const struct lp_build_tgsi_action *action,
3878 struct lp_build_tgsi_context *bld_base,
3879 struct lp_build_emit_data *emit_data)
3880 {
3881 struct si_shader_context *ctx = si_shader_context(bld_base);
3882 struct gallivm_state *gallivm = bld_base->base.gallivm;
3883 LLVMBuilderRef builder = gallivm->builder;
3884 const struct tgsi_full_instruction * inst = emit_data->inst;
3885 unsigned target = inst->Memory.Texture;
3886 char intrinsic_name[32];
3887 char coords_type[8];
3888
3889 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3890 store_emit_memory(ctx, emit_data);
3891 return;
3892 }
3893
3894 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3895 emit_waitcnt(ctx);
3896
3897 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3898 store_emit_buffer(ctx, emit_data);
3899 return;
3900 }
3901
3902 if (target == TGSI_TEXTURE_BUFFER) {
3903 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3904 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3905 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3906 LLVMNoUnwindAttribute);
3907 } else {
3908 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3909 coords_type, sizeof(coords_type));
3910 snprintf(intrinsic_name, sizeof(intrinsic_name),
3911 "llvm.amdgcn.image.store.%s", coords_type);
3912
3913 emit_data->output[emit_data->chan] =
3914 lp_build_intrinsic(
3915 builder, intrinsic_name, emit_data->dst_type,
3916 emit_data->args, emit_data->arg_count,
3917 LLVMNoUnwindAttribute);
3918 }
3919 }
3920
3921 static void atomic_fetch_args(
3922 struct lp_build_tgsi_context * bld_base,
3923 struct lp_build_emit_data * emit_data)
3924 {
3925 struct si_shader_context *ctx = si_shader_context(bld_base);
3926 struct gallivm_state *gallivm = bld_base->base.gallivm;
3927 LLVMBuilderRef builder = gallivm->builder;
3928 const struct tgsi_full_instruction * inst = emit_data->inst;
3929 LLVMValueRef data1, data2;
3930 LLVMValueRef rsrc;
3931 LLVMValueRef tmp;
3932
3933 emit_data->dst_type = bld_base->base.elem_type;
3934
3935 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3936 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3937
3938 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3939 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3940 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3941 }
3942
3943 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3944 * of arguments, which is reversed relative to TGSI (and GLSL)
3945 */
3946 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3947 emit_data->args[emit_data->arg_count++] = data2;
3948 emit_data->args[emit_data->arg_count++] = data1;
3949
3950 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3951 LLVMValueRef offset;
3952
3953 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3954
3955 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3956 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3957
3958 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3959 offset, true);
3960 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3961 unsigned target = inst->Memory.Texture;
3962 LLVMValueRef coords;
3963
3964 image_fetch_rsrc(bld_base, &inst->Src[0],
3965 target != TGSI_TEXTURE_BUFFER, &rsrc);
3966 coords = image_fetch_coords(bld_base, inst, 1);
3967
3968 if (target == TGSI_TEXTURE_BUFFER) {
3969 rsrc = extract_rsrc_top_half(ctx, rsrc);
3970 buffer_append_args(ctx, emit_data, rsrc, coords,
3971 bld_base->uint_bld.zero, true);
3972 } else {
3973 emit_data->args[emit_data->arg_count++] = coords;
3974 emit_data->args[emit_data->arg_count++] = rsrc;
3975
3976 image_append_args(ctx, emit_data, target, true);
3977 }
3978 }
3979 }
3980
3981 static void atomic_emit_memory(struct si_shader_context *ctx,
3982 struct lp_build_emit_data *emit_data) {
3983 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3984 LLVMBuilderRef builder = gallivm->builder;
3985 const struct tgsi_full_instruction * inst = emit_data->inst;
3986 LLVMValueRef ptr, result, arg;
3987
3988 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3989
3990 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3991 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3992
3993 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3994 LLVMValueRef new_data;
3995 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3996 inst, 3, 0);
3997
3998 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3999
4000 #if HAVE_LLVM >= 0x309
4001 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4002 LLVMAtomicOrderingSequentiallyConsistent,
4003 LLVMAtomicOrderingSequentiallyConsistent,
4004 false);
4005 #endif
4006
4007 result = LLVMBuildExtractValue(builder, result, 0, "");
4008 } else {
4009 LLVMAtomicRMWBinOp op;
4010
4011 switch(inst->Instruction.Opcode) {
4012 case TGSI_OPCODE_ATOMUADD:
4013 op = LLVMAtomicRMWBinOpAdd;
4014 break;
4015 case TGSI_OPCODE_ATOMXCHG:
4016 op = LLVMAtomicRMWBinOpXchg;
4017 break;
4018 case TGSI_OPCODE_ATOMAND:
4019 op = LLVMAtomicRMWBinOpAnd;
4020 break;
4021 case TGSI_OPCODE_ATOMOR:
4022 op = LLVMAtomicRMWBinOpOr;
4023 break;
4024 case TGSI_OPCODE_ATOMXOR:
4025 op = LLVMAtomicRMWBinOpXor;
4026 break;
4027 case TGSI_OPCODE_ATOMUMIN:
4028 op = LLVMAtomicRMWBinOpUMin;
4029 break;
4030 case TGSI_OPCODE_ATOMUMAX:
4031 op = LLVMAtomicRMWBinOpUMax;
4032 break;
4033 case TGSI_OPCODE_ATOMIMIN:
4034 op = LLVMAtomicRMWBinOpMin;
4035 break;
4036 case TGSI_OPCODE_ATOMIMAX:
4037 op = LLVMAtomicRMWBinOpMax;
4038 break;
4039 default:
4040 unreachable("unknown atomic opcode");
4041 }
4042
4043 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4044 LLVMAtomicOrderingSequentiallyConsistent,
4045 false);
4046 }
4047 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4048 }
4049
4050 static void atomic_emit(
4051 const struct lp_build_tgsi_action *action,
4052 struct lp_build_tgsi_context *bld_base,
4053 struct lp_build_emit_data *emit_data)
4054 {
4055 struct si_shader_context *ctx = si_shader_context(bld_base);
4056 struct gallivm_state *gallivm = bld_base->base.gallivm;
4057 LLVMBuilderRef builder = gallivm->builder;
4058 const struct tgsi_full_instruction * inst = emit_data->inst;
4059 char intrinsic_name[40];
4060 LLVMValueRef tmp;
4061
4062 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4063 atomic_emit_memory(ctx, emit_data);
4064 return;
4065 }
4066
4067 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4068 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4069 snprintf(intrinsic_name, sizeof(intrinsic_name),
4070 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4071 } else {
4072 char coords_type[8];
4073
4074 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4075 coords_type, sizeof(coords_type));
4076 snprintf(intrinsic_name, sizeof(intrinsic_name),
4077 "llvm.amdgcn.image.atomic.%s.%s",
4078 action->intr_name, coords_type);
4079 }
4080
4081 tmp = lp_build_intrinsic(
4082 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4083 emit_data->args, emit_data->arg_count,
4084 LLVMNoUnwindAttribute);
4085 emit_data->output[emit_data->chan] =
4086 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4087 }
4088
4089 static void resq_fetch_args(
4090 struct lp_build_tgsi_context * bld_base,
4091 struct lp_build_emit_data * emit_data)
4092 {
4093 struct si_shader_context *ctx = si_shader_context(bld_base);
4094 struct gallivm_state *gallivm = bld_base->base.gallivm;
4095 const struct tgsi_full_instruction *inst = emit_data->inst;
4096 const struct tgsi_full_src_register *reg = &inst->Src[0];
4097
4098 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
4099
4100 if (reg->Register.File == TGSI_FILE_BUFFER) {
4101 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4102 emit_data->arg_count = 1;
4103 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4104 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4105 emit_data->arg_count = 1;
4106 } else {
4107 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4108 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4109 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4110 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4111 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4112 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4113 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4114 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4115 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4116 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4117 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4118 emit_data->arg_count = 10;
4119 }
4120 }
4121
4122 static void resq_emit(
4123 const struct lp_build_tgsi_action *action,
4124 struct lp_build_tgsi_context *bld_base,
4125 struct lp_build_emit_data *emit_data)
4126 {
4127 struct gallivm_state *gallivm = bld_base->base.gallivm;
4128 LLVMBuilderRef builder = gallivm->builder;
4129 const struct tgsi_full_instruction *inst = emit_data->inst;
4130 LLVMValueRef out;
4131
4132 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4133 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4134 lp_build_const_int32(gallivm, 2), "");
4135 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4136 out = get_buffer_size(bld_base, emit_data->args[0]);
4137 } else {
4138 out = lp_build_intrinsic(
4139 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4140 emit_data->args, emit_data->arg_count,
4141 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4142
4143 /* Divide the number of layers by 6 to get the number of cubes. */
4144 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4145 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4146 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4147
4148 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4149 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
4150 z = LLVMBuildSDiv(builder, z, imm6, "");
4151 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
4152 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4153 }
4154 }
4155
4156 emit_data->output[emit_data->chan] = out;
4157 }
4158
4159 static void set_tex_fetch_args(struct si_shader_context *ctx,
4160 struct lp_build_emit_data *emit_data,
4161 unsigned opcode, unsigned target,
4162 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4163 LLVMValueRef *param, unsigned count,
4164 unsigned dmask)
4165 {
4166 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4167 unsigned num_args;
4168 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4169
4170 /* Pad to power of two vector */
4171 while (count < util_next_power_of_two(count))
4172 param[count++] = LLVMGetUndef(ctx->i32);
4173
4174 /* Texture coordinates. */
4175 if (count > 1)
4176 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4177 else
4178 emit_data->args[0] = param[0];
4179
4180 /* Resource. */
4181 emit_data->args[1] = res_ptr;
4182 num_args = 2;
4183
4184 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4185 emit_data->dst_type = ctx->v4i32;
4186 else {
4187 emit_data->dst_type = ctx->v4f32;
4188
4189 emit_data->args[num_args++] = samp_ptr;
4190 }
4191
4192 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4193 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4194 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4195 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4196 tgsi_is_array_sampler(target)); /* da */
4197 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4198 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4199 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4200 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4201
4202 emit_data->arg_count = num_args;
4203 }
4204
4205 static const struct lp_build_tgsi_action tex_action;
4206
4207 enum desc_type {
4208 DESC_IMAGE,
4209 DESC_FMASK,
4210 DESC_SAMPLER
4211 };
4212
4213 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4214 {
4215 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4216 CONST_ADDR_SPACE);
4217 }
4218
4219 /**
4220 * Load an image view, fmask view. or sampler state descriptor.
4221 */
4222 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4223 LLVMValueRef list, LLVMValueRef index,
4224 enum desc_type type)
4225 {
4226 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4227 LLVMBuilderRef builder = gallivm->builder;
4228
4229 switch (type) {
4230 case DESC_IMAGE:
4231 /* The image is at [0:7]. */
4232 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4233 break;
4234 case DESC_FMASK:
4235 /* The FMASK is at [8:15]. */
4236 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4237 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4238 break;
4239 case DESC_SAMPLER:
4240 /* The sampler state is at [12:15]. */
4241 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4242 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4243 list = LLVMBuildPointerCast(builder, list,
4244 const_array(ctx->v4i32, 0), "");
4245 break;
4246 }
4247
4248 return build_indexed_load_const(ctx, list, index);
4249 }
4250
4251 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4252 LLVMValueRef index, enum desc_type type)
4253 {
4254 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4255 SI_PARAM_SAMPLERS);
4256
4257 return get_sampler_desc_custom(ctx, list, index, type);
4258 }
4259
4260 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4261 *
4262 * SI-CI:
4263 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4264 * filtering manually. The driver sets img7 to a mask clearing
4265 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4266 * s_and_b32 samp0, samp0, img7
4267 *
4268 * VI:
4269 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4270 */
4271 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4272 LLVMValueRef res, LLVMValueRef samp)
4273 {
4274 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4275 LLVMValueRef img7, samp0;
4276
4277 if (ctx->screen->b.chip_class >= VI)
4278 return samp;
4279
4280 img7 = LLVMBuildExtractElement(builder, res,
4281 LLVMConstInt(ctx->i32, 7, 0), "");
4282 samp0 = LLVMBuildExtractElement(builder, samp,
4283 LLVMConstInt(ctx->i32, 0, 0), "");
4284 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4285 return LLVMBuildInsertElement(builder, samp, samp0,
4286 LLVMConstInt(ctx->i32, 0, 0), "");
4287 }
4288
4289 static void tex_fetch_ptrs(
4290 struct lp_build_tgsi_context *bld_base,
4291 struct lp_build_emit_data *emit_data,
4292 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4293 {
4294 struct si_shader_context *ctx = si_shader_context(bld_base);
4295 const struct tgsi_full_instruction *inst = emit_data->inst;
4296 unsigned target = inst->Texture.Texture;
4297 unsigned sampler_src;
4298 unsigned sampler_index;
4299
4300 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4301 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4302
4303 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4304 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4305 LLVMValueRef ind_index;
4306
4307 ind_index = get_bounded_indirect_index(ctx,
4308 &reg->Indirect,
4309 reg->Register.Index,
4310 SI_NUM_SAMPLERS);
4311
4312 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4313
4314 if (target == TGSI_TEXTURE_2D_MSAA ||
4315 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4316 if (samp_ptr)
4317 *samp_ptr = NULL;
4318 if (fmask_ptr)
4319 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4320 } else {
4321 if (samp_ptr) {
4322 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4323 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4324 }
4325 if (fmask_ptr)
4326 *fmask_ptr = NULL;
4327 }
4328 } else {
4329 *res_ptr = ctx->sampler_views[sampler_index];
4330 if (samp_ptr)
4331 *samp_ptr = ctx->sampler_states[sampler_index];
4332 if (fmask_ptr)
4333 *fmask_ptr = ctx->fmasks[sampler_index];
4334 }
4335 }
4336
4337 static void txq_fetch_args(
4338 struct lp_build_tgsi_context *bld_base,
4339 struct lp_build_emit_data *emit_data)
4340 {
4341 struct si_shader_context *ctx = si_shader_context(bld_base);
4342 struct gallivm_state *gallivm = bld_base->base.gallivm;
4343 LLVMBuilderRef builder = gallivm->builder;
4344 const struct tgsi_full_instruction *inst = emit_data->inst;
4345 unsigned target = inst->Texture.Texture;
4346 LLVMValueRef res_ptr;
4347 LLVMValueRef address;
4348
4349 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4350
4351 if (target == TGSI_TEXTURE_BUFFER) {
4352 /* Read the size from the buffer descriptor directly. */
4353 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4354 emit_data->args[0] = get_buffer_size(bld_base, res);
4355 return;
4356 }
4357
4358 /* Textures - set the mip level. */
4359 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4360
4361 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4362 NULL, &address, 1, 0xf);
4363 }
4364
4365 static void txq_emit(const struct lp_build_tgsi_action *action,
4366 struct lp_build_tgsi_context *bld_base,
4367 struct lp_build_emit_data *emit_data)
4368 {
4369 struct lp_build_context *base = &bld_base->base;
4370 unsigned target = emit_data->inst->Texture.Texture;
4371
4372 if (target == TGSI_TEXTURE_BUFFER) {
4373 /* Just return the buffer size. */
4374 emit_data->output[emit_data->chan] = emit_data->args[0];
4375 return;
4376 }
4377
4378 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4379 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4380 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4381 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4382
4383 /* Divide the number of layers by 6 to get the number of cubes. */
4384 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4385 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4386 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4387 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4388 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4389
4390 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4391 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4392 z = LLVMBuildSDiv(builder, z, six, "");
4393
4394 emit_data->output[emit_data->chan] =
4395 LLVMBuildInsertElement(builder, v4, z, two, "");
4396 }
4397 }
4398
4399 static void tex_fetch_args(
4400 struct lp_build_tgsi_context *bld_base,
4401 struct lp_build_emit_data *emit_data)
4402 {
4403 struct si_shader_context *ctx = si_shader_context(bld_base);
4404 struct gallivm_state *gallivm = bld_base->base.gallivm;
4405 const struct tgsi_full_instruction *inst = emit_data->inst;
4406 unsigned opcode = inst->Instruction.Opcode;
4407 unsigned target = inst->Texture.Texture;
4408 LLVMValueRef coords[5], derivs[6];
4409 LLVMValueRef address[16];
4410 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4411 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4412 unsigned count = 0;
4413 unsigned chan;
4414 unsigned num_deriv_channels = 0;
4415 bool has_offset = inst->Texture.NumOffsets > 0;
4416 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4417 unsigned dmask = 0xf;
4418
4419 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4420
4421 if (target == TGSI_TEXTURE_BUFFER) {
4422 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4423
4424 /* Bitcast and truncate v8i32 to v16i8. */
4425 LLVMValueRef res = res_ptr;
4426 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4427 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4428 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4429
4430 emit_data->dst_type = ctx->v4f32;
4431 emit_data->args[0] = res;
4432 emit_data->args[1] = bld_base->uint_bld.zero;
4433 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4434 emit_data->arg_count = 3;
4435 return;
4436 }
4437
4438 /* Fetch and project texture coordinates */
4439 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4440 for (chan = 0; chan < 3; chan++ ) {
4441 coords[chan] = lp_build_emit_fetch(bld_base,
4442 emit_data->inst, 0,
4443 chan);
4444 if (opcode == TGSI_OPCODE_TXP)
4445 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4446 TGSI_OPCODE_DIV,
4447 coords[chan],
4448 coords[3]);
4449 }
4450
4451 if (opcode == TGSI_OPCODE_TXP)
4452 coords[3] = bld_base->base.one;
4453
4454 /* Pack offsets. */
4455 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4456 /* The offsets are six-bit signed integers packed like this:
4457 * X=[5:0], Y=[13:8], and Z=[21:16].
4458 */
4459 LLVMValueRef offset[3], pack;
4460
4461 assert(inst->Texture.NumOffsets == 1);
4462
4463 for (chan = 0; chan < 3; chan++) {
4464 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4465 emit_data->inst, 0, chan);
4466 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4467 lp_build_const_int32(gallivm, 0x3f), "");
4468 if (chan)
4469 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4470 lp_build_const_int32(gallivm, chan*8), "");
4471 }
4472
4473 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4474 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4475 address[count++] = pack;
4476 }
4477
4478 /* Pack LOD bias value */
4479 if (opcode == TGSI_OPCODE_TXB)
4480 address[count++] = coords[3];
4481 if (opcode == TGSI_OPCODE_TXB2)
4482 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4483
4484 /* Pack depth comparison value */
4485 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4486 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4487 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4488 } else {
4489 assert(ref_pos >= 0);
4490 address[count++] = coords[ref_pos];
4491 }
4492 }
4493
4494 /* Pack user derivatives */
4495 if (opcode == TGSI_OPCODE_TXD) {
4496 int param, num_src_deriv_channels;
4497
4498 switch (target) {
4499 case TGSI_TEXTURE_3D:
4500 num_src_deriv_channels = 3;
4501 num_deriv_channels = 3;
4502 break;
4503 case TGSI_TEXTURE_2D:
4504 case TGSI_TEXTURE_SHADOW2D:
4505 case TGSI_TEXTURE_RECT:
4506 case TGSI_TEXTURE_SHADOWRECT:
4507 case TGSI_TEXTURE_2D_ARRAY:
4508 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4509 num_src_deriv_channels = 2;
4510 num_deriv_channels = 2;
4511 break;
4512 case TGSI_TEXTURE_CUBE:
4513 case TGSI_TEXTURE_SHADOWCUBE:
4514 case TGSI_TEXTURE_CUBE_ARRAY:
4515 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4516 /* Cube derivatives will be converted to 2D. */
4517 num_src_deriv_channels = 3;
4518 num_deriv_channels = 2;
4519 break;
4520 case TGSI_TEXTURE_1D:
4521 case TGSI_TEXTURE_SHADOW1D:
4522 case TGSI_TEXTURE_1D_ARRAY:
4523 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4524 num_src_deriv_channels = 1;
4525 num_deriv_channels = 1;
4526 break;
4527 default:
4528 unreachable("invalid target");
4529 }
4530
4531 for (param = 0; param < 2; param++)
4532 for (chan = 0; chan < num_src_deriv_channels; chan++)
4533 derivs[param * num_src_deriv_channels + chan] =
4534 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4535 }
4536
4537 if (target == TGSI_TEXTURE_CUBE ||
4538 target == TGSI_TEXTURE_CUBE_ARRAY ||
4539 target == TGSI_TEXTURE_SHADOWCUBE ||
4540 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4541 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4542
4543 if (opcode == TGSI_OPCODE_TXD)
4544 for (int i = 0; i < num_deriv_channels * 2; i++)
4545 address[count++] = derivs[i];
4546
4547 /* Pack texture coordinates */
4548 address[count++] = coords[0];
4549 if (num_coords > 1)
4550 address[count++] = coords[1];
4551 if (num_coords > 2)
4552 address[count++] = coords[2];
4553
4554 /* Pack LOD or sample index */
4555 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4556 address[count++] = coords[3];
4557 else if (opcode == TGSI_OPCODE_TXL2)
4558 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4559
4560 if (count > 16) {
4561 assert(!"Cannot handle more than 16 texture address parameters");
4562 count = 16;
4563 }
4564
4565 for (chan = 0; chan < count; chan++ ) {
4566 address[chan] = LLVMBuildBitCast(gallivm->builder,
4567 address[chan], ctx->i32, "");
4568 }
4569
4570 /* Adjust the sample index according to FMASK.
4571 *
4572 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4573 * which is the identity mapping. Each nibble says which physical sample
4574 * should be fetched to get that sample.
4575 *
4576 * For example, 0x11111100 means there are only 2 samples stored and
4577 * the second sample covers 3/4 of the pixel. When reading samples 0
4578 * and 1, return physical sample 0 (determined by the first two 0s
4579 * in FMASK), otherwise return physical sample 1.
4580 *
4581 * The sample index should be adjusted as follows:
4582 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4583 */
4584 if (target == TGSI_TEXTURE_2D_MSAA ||
4585 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4586 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4587 struct lp_build_emit_data txf_emit_data = *emit_data;
4588 LLVMValueRef txf_address[4];
4589 unsigned txf_count = count;
4590 struct tgsi_full_instruction inst = {};
4591
4592 memcpy(txf_address, address, sizeof(txf_address));
4593
4594 if (target == TGSI_TEXTURE_2D_MSAA) {
4595 txf_address[2] = bld_base->uint_bld.zero;
4596 }
4597 txf_address[3] = bld_base->uint_bld.zero;
4598
4599 /* Read FMASK using TXF. */
4600 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4601 inst.Texture.Texture = target;
4602 txf_emit_data.inst = &inst;
4603 txf_emit_data.chan = 0;
4604 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4605 target, fmask_ptr, NULL,
4606 txf_address, txf_count, 0xf);
4607 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4608
4609 /* Initialize some constants. */
4610 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4611 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4612
4613 /* Apply the formula. */
4614 LLVMValueRef fmask =
4615 LLVMBuildExtractElement(gallivm->builder,
4616 txf_emit_data.output[0],
4617 uint_bld->zero, "");
4618
4619 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4620
4621 LLVMValueRef sample_index4 =
4622 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4623
4624 LLVMValueRef shifted_fmask =
4625 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4626
4627 LLVMValueRef final_sample =
4628 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4629
4630 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4631 * resource descriptor is 0 (invalid),
4632 */
4633 LLVMValueRef fmask_desc =
4634 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4635 ctx->v8i32, "");
4636
4637 LLVMValueRef fmask_word1 =
4638 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4639 uint_bld->one, "");
4640
4641 LLVMValueRef word1_is_nonzero =
4642 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4643 fmask_word1, uint_bld->zero, "");
4644
4645 /* Replace the MSAA sample index. */
4646 address[sample_chan] =
4647 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4648 final_sample, address[sample_chan], "");
4649 }
4650
4651 if (opcode == TGSI_OPCODE_TXF) {
4652 /* add tex offsets */
4653 if (inst->Texture.NumOffsets) {
4654 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4655 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4656 const struct tgsi_texture_offset *off = inst->TexOffsets;
4657
4658 assert(inst->Texture.NumOffsets == 1);
4659
4660 switch (target) {
4661 case TGSI_TEXTURE_3D:
4662 address[2] = lp_build_add(uint_bld, address[2],
4663 bld->immediates[off->Index][off->SwizzleZ]);
4664 /* fall through */
4665 case TGSI_TEXTURE_2D:
4666 case TGSI_TEXTURE_SHADOW2D:
4667 case TGSI_TEXTURE_RECT:
4668 case TGSI_TEXTURE_SHADOWRECT:
4669 case TGSI_TEXTURE_2D_ARRAY:
4670 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4671 address[1] =
4672 lp_build_add(uint_bld, address[1],
4673 bld->immediates[off->Index][off->SwizzleY]);
4674 /* fall through */
4675 case TGSI_TEXTURE_1D:
4676 case TGSI_TEXTURE_SHADOW1D:
4677 case TGSI_TEXTURE_1D_ARRAY:
4678 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4679 address[0] =
4680 lp_build_add(uint_bld, address[0],
4681 bld->immediates[off->Index][off->SwizzleX]);
4682 break;
4683 /* texture offsets do not apply to other texture targets */
4684 }
4685 }
4686 }
4687
4688 if (opcode == TGSI_OPCODE_TG4) {
4689 unsigned gather_comp = 0;
4690
4691 /* DMASK was repurposed for GATHER4. 4 components are always
4692 * returned and DMASK works like a swizzle - it selects
4693 * the component to fetch. The only valid DMASK values are
4694 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4695 * (red,red,red,red) etc.) The ISA document doesn't mention
4696 * this.
4697 */
4698
4699 /* Get the component index from src1.x for Gather4. */
4700 if (!tgsi_is_shadow_target(target)) {
4701 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4702 LLVMValueRef comp_imm;
4703 struct tgsi_src_register src1 = inst->Src[1].Register;
4704
4705 assert(src1.File == TGSI_FILE_IMMEDIATE);
4706
4707 comp_imm = imms[src1.Index][src1.SwizzleX];
4708 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4709 gather_comp = CLAMP(gather_comp, 0, 3);
4710 }
4711
4712 dmask = 1 << gather_comp;
4713 }
4714
4715 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4716 samp_ptr, address, count, dmask);
4717 }
4718
4719 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4720 struct lp_build_tgsi_context *bld_base,
4721 struct lp_build_emit_data *emit_data)
4722 {
4723 struct si_shader_context *ctx = si_shader_context(bld_base);
4724 struct lp_build_context *base = &bld_base->base;
4725 unsigned opcode = emit_data->inst->Instruction.Opcode;
4726 unsigned target = emit_data->inst->Texture.Texture;
4727 char intr_name[127];
4728 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4729 bool is_shadow = tgsi_is_shadow_target(target);
4730 char type[64];
4731 const char *name = "llvm.SI.image.sample";
4732 const char *infix = "";
4733
4734 if (target == TGSI_TEXTURE_BUFFER) {
4735 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4736 base->gallivm->builder,
4737 "llvm.SI.vs.load.input", emit_data->dst_type,
4738 emit_data->args, emit_data->arg_count,
4739 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4740 return;
4741 }
4742
4743 switch (opcode) {
4744 case TGSI_OPCODE_TXF:
4745 name = target == TGSI_TEXTURE_2D_MSAA ||
4746 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4747 "llvm.SI.image.load" :
4748 "llvm.SI.image.load.mip";
4749 is_shadow = false;
4750 has_offset = false;
4751 break;
4752 case TGSI_OPCODE_LODQ:
4753 name = "llvm.SI.getlod";
4754 is_shadow = false;
4755 has_offset = false;
4756 break;
4757 case TGSI_OPCODE_TEX:
4758 case TGSI_OPCODE_TEX2:
4759 case TGSI_OPCODE_TXP:
4760 if (ctx->type != PIPE_SHADER_FRAGMENT)
4761 infix = ".lz";
4762 break;
4763 case TGSI_OPCODE_TXB:
4764 case TGSI_OPCODE_TXB2:
4765 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4766 infix = ".b";
4767 break;
4768 case TGSI_OPCODE_TXL:
4769 case TGSI_OPCODE_TXL2:
4770 infix = ".l";
4771 break;
4772 case TGSI_OPCODE_TXD:
4773 infix = ".d";
4774 break;
4775 case TGSI_OPCODE_TG4:
4776 name = "llvm.SI.gather4";
4777 infix = ".lz";
4778 break;
4779 default:
4780 assert(0);
4781 return;
4782 }
4783
4784 /* Add the type and suffixes .c, .o if needed. */
4785 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4786 sprintf(intr_name, "%s%s%s%s.%s",
4787 name, is_shadow ? ".c" : "", infix,
4788 has_offset ? ".o" : "", type);
4789
4790 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4791 base->gallivm->builder, intr_name, emit_data->dst_type,
4792 emit_data->args, emit_data->arg_count,
4793 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4794 }
4795
4796 static void si_llvm_emit_txqs(
4797 const struct lp_build_tgsi_action *action,
4798 struct lp_build_tgsi_context *bld_base,
4799 struct lp_build_emit_data *emit_data)
4800 {
4801 struct si_shader_context *ctx = si_shader_context(bld_base);
4802 struct gallivm_state *gallivm = bld_base->base.gallivm;
4803 LLVMBuilderRef builder = gallivm->builder;
4804 LLVMValueRef res, samples;
4805 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4806
4807 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4808
4809
4810 /* Read the samples from the descriptor directly. */
4811 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4812 samples = LLVMBuildExtractElement(
4813 builder, res,
4814 lp_build_const_int32(gallivm, 3), "");
4815 samples = LLVMBuildLShr(builder, samples,
4816 lp_build_const_int32(gallivm, 16), "");
4817 samples = LLVMBuildAnd(builder, samples,
4818 lp_build_const_int32(gallivm, 0xf), "");
4819 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4820 samples, "");
4821
4822 emit_data->output[emit_data->chan] = samples;
4823 }
4824
4825 /*
4826 * SI implements derivatives using the local data store (LDS)
4827 * All writes to the LDS happen in all executing threads at
4828 * the same time. TID is the Thread ID for the current
4829 * thread and is a value between 0 and 63, representing
4830 * the thread's position in the wavefront.
4831 *
4832 * For the pixel shader threads are grouped into quads of four pixels.
4833 * The TIDs of the pixels of a quad are:
4834 *
4835 * +------+------+
4836 * |4n + 0|4n + 1|
4837 * +------+------+
4838 * |4n + 2|4n + 3|
4839 * +------+------+
4840 *
4841 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4842 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4843 * the current pixel's column, and masking with 0xfffffffe yields the TID
4844 * of the left pixel of the current pixel's row.
4845 *
4846 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4847 * adding 2 yields the TID of the pixel below the top pixel.
4848 */
4849 /* masks for thread ID. */
4850 #define TID_MASK_TOP_LEFT 0xfffffffc
4851 #define TID_MASK_TOP 0xfffffffd
4852 #define TID_MASK_LEFT 0xfffffffe
4853
4854 static void si_llvm_emit_ddxy(
4855 const struct lp_build_tgsi_action *action,
4856 struct lp_build_tgsi_context *bld_base,
4857 struct lp_build_emit_data *emit_data)
4858 {
4859 struct si_shader_context *ctx = si_shader_context(bld_base);
4860 struct gallivm_state *gallivm = bld_base->base.gallivm;
4861 const struct tgsi_full_instruction *inst = emit_data->inst;
4862 unsigned opcode = inst->Instruction.Opcode;
4863 LLVMValueRef indices[2];
4864 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4865 LLVMValueRef tl, trbl, result[4];
4866 LLVMValueRef tl_tid, trbl_tid;
4867 unsigned swizzle[4];
4868 unsigned c;
4869 int idx;
4870 unsigned mask;
4871
4872 indices[0] = bld_base->uint_bld.zero;
4873 indices[1] = get_thread_id(ctx);
4874 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4875 indices, 2, "");
4876
4877 if (opcode == TGSI_OPCODE_DDX_FINE)
4878 mask = TID_MASK_LEFT;
4879 else if (opcode == TGSI_OPCODE_DDY_FINE)
4880 mask = TID_MASK_TOP;
4881 else
4882 mask = TID_MASK_TOP_LEFT;
4883
4884 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
4885 lp_build_const_int32(gallivm, mask), "");
4886 indices[1] = tl_tid;
4887 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4888 indices, 2, "");
4889
4890 /* for DDX we want to next X pixel, DDY next Y pixel. */
4891 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4892 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
4893 lp_build_const_int32(gallivm, idx), "");
4894 indices[1] = trbl_tid;
4895 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4896 indices, 2, "");
4897
4898 for (c = 0; c < 4; ++c) {
4899 unsigned i;
4900 LLVMValueRef val;
4901 LLVMValueRef args[2];
4902
4903 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4904 for (i = 0; i < c; ++i) {
4905 if (swizzle[i] == swizzle[c]) {
4906 result[c] = result[i];
4907 break;
4908 }
4909 }
4910 if (i != c)
4911 continue;
4912
4913 val = LLVMBuildBitCast(gallivm->builder,
4914 lp_build_emit_fetch(bld_base, inst, 0, c),
4915 ctx->i32, "");
4916
4917 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
4918
4919 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4920 lp_build_const_int32(gallivm, 4), "");
4921 args[1] = val;
4922 tl = lp_build_intrinsic(gallivm->builder,
4923 "llvm.amdgcn.ds.bpermute", ctx->i32,
4924 args, 2, LLVMReadNoneAttribute);
4925
4926 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4927 lp_build_const_int32(gallivm, 4), "");
4928 trbl = lp_build_intrinsic(gallivm->builder,
4929 "llvm.amdgcn.ds.bpermute", ctx->i32,
4930 args, 2, LLVMReadNoneAttribute);
4931 } else {
4932 LLVMBuildStore(gallivm->builder, val, store_ptr);
4933 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4934 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4935 }
4936 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4937 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4938 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4939 }
4940
4941 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4942 }
4943
4944 /*
4945 * this takes an I,J coordinate pair,
4946 * and works out the X and Y derivatives.
4947 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4948 */
4949 static LLVMValueRef si_llvm_emit_ddxy_interp(
4950 struct lp_build_tgsi_context *bld_base,
4951 LLVMValueRef interp_ij)
4952 {
4953 struct si_shader_context *ctx = si_shader_context(bld_base);
4954 struct gallivm_state *gallivm = bld_base->base.gallivm;
4955 LLVMValueRef indices[2];
4956 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4957 LLVMValueRef tl, tr, bl, result[4];
4958 unsigned c;
4959
4960 indices[0] = bld_base->uint_bld.zero;
4961 indices[1] = get_thread_id(ctx);
4962 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4963 indices, 2, "");
4964
4965 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4966 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4967
4968 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4969 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4970
4971 indices[1] = temp;
4972 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4973 indices, 2, "");
4974
4975 indices[1] = temp2;
4976 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4977 indices, 2, "");
4978
4979 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4980 lp_build_const_int32(gallivm, 1), "");
4981 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4982 indices, 2, "");
4983
4984 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4985 lp_build_const_int32(gallivm, 2), "");
4986 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4987 indices, 2, "");
4988
4989 for (c = 0; c < 2; ++c) {
4990 LLVMValueRef store_val;
4991 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4992
4993 store_val = LLVMBuildExtractElement(gallivm->builder,
4994 interp_ij, c_ll, "");
4995 LLVMBuildStore(gallivm->builder,
4996 store_val,
4997 store_ptr);
4998
4999 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
5000 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5001
5002 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
5003 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
5004
5005 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
5006
5007 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
5008 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5009
5010 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
5011 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
5012
5013 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
5014 }
5015
5016 return lp_build_gather_values(gallivm, result, 4);
5017 }
5018
5019 static void interp_fetch_args(
5020 struct lp_build_tgsi_context *bld_base,
5021 struct lp_build_emit_data *emit_data)
5022 {
5023 struct si_shader_context *ctx = si_shader_context(bld_base);
5024 struct gallivm_state *gallivm = bld_base->base.gallivm;
5025 const struct tgsi_full_instruction *inst = emit_data->inst;
5026
5027 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5028 /* offset is in second src, first two channels */
5029 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5030 emit_data->inst, 1,
5031 TGSI_CHAN_X);
5032 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5033 emit_data->inst, 1,
5034 TGSI_CHAN_Y);
5035 emit_data->arg_count = 2;
5036 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5037 LLVMValueRef sample_position;
5038 LLVMValueRef sample_id;
5039 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5040
5041 /* fetch sample ID, then fetch its sample position,
5042 * and place into first two channels.
5043 */
5044 sample_id = lp_build_emit_fetch(bld_base,
5045 emit_data->inst, 1, TGSI_CHAN_X);
5046 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5047 ctx->i32, "");
5048 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5049
5050 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5051 sample_position,
5052 lp_build_const_int32(gallivm, 0), "");
5053
5054 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5055 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5056 sample_position,
5057 lp_build_const_int32(gallivm, 1), "");
5058 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5059 emit_data->arg_count = 2;
5060 }
5061 }
5062
5063 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5064 struct lp_build_tgsi_context *bld_base,
5065 struct lp_build_emit_data *emit_data)
5066 {
5067 struct si_shader_context *ctx = si_shader_context(bld_base);
5068 struct si_shader *shader = ctx->shader;
5069 struct gallivm_state *gallivm = bld_base->base.gallivm;
5070 LLVMValueRef interp_param;
5071 const struct tgsi_full_instruction *inst = emit_data->inst;
5072 const char *intr_name;
5073 int input_index = inst->Src[0].Register.Index;
5074 int chan;
5075 int i;
5076 LLVMValueRef attr_number;
5077 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5078 int interp_param_idx;
5079 unsigned interp = shader->selector->info.input_interpolate[input_index];
5080 unsigned location;
5081
5082 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5083
5084 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5085 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5086 location = TGSI_INTERPOLATE_LOC_CENTER;
5087 else
5088 location = TGSI_INTERPOLATE_LOC_CENTROID;
5089
5090 interp_param_idx = lookup_interp_param_index(interp, location);
5091 if (interp_param_idx == -1)
5092 return;
5093 else if (interp_param_idx)
5094 interp_param = get_interp_param(ctx, interp_param_idx);
5095 else
5096 interp_param = NULL;
5097
5098 attr_number = lp_build_const_int32(gallivm, input_index);
5099
5100 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5101 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5102 LLVMValueRef ij_out[2];
5103 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5104
5105 /*
5106 * take the I then J parameters, and the DDX/Y for it, and
5107 * calculate the IJ inputs for the interpolator.
5108 * temp1 = ddx * offset/sample.x + I;
5109 * interp_param.I = ddy * offset/sample.y + temp1;
5110 * temp1 = ddx * offset/sample.x + J;
5111 * interp_param.J = ddy * offset/sample.y + temp1;
5112 */
5113 for (i = 0; i < 2; i++) {
5114 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5115 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5116 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5117 ddxy_out, ix_ll, "");
5118 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5119 ddxy_out, iy_ll, "");
5120 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5121 interp_param, ix_ll, "");
5122 LLVMValueRef temp1, temp2;
5123
5124 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5125 ctx->f32, "");
5126
5127 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5128
5129 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5130
5131 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5132
5133 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5134
5135 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5136 temp2, ctx->i32, "");
5137 }
5138 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5139 }
5140
5141 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5142 for (chan = 0; chan < 2; chan++) {
5143 LLVMValueRef args[4];
5144 LLVMValueRef llvm_chan;
5145 unsigned schan;
5146
5147 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5148 llvm_chan = lp_build_const_int32(gallivm, schan);
5149
5150 args[0] = llvm_chan;
5151 args[1] = attr_number;
5152 args[2] = params;
5153 args[3] = interp_param;
5154
5155 emit_data->output[chan] =
5156 lp_build_intrinsic(gallivm->builder, intr_name,
5157 ctx->f32, args, args[3] ? 4 : 3,
5158 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
5159 }
5160 }
5161
5162 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5163 struct lp_build_emit_data *emit_data)
5164 {
5165 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5166 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5167 unsigned stream;
5168
5169 assert(src0.File == TGSI_FILE_IMMEDIATE);
5170
5171 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5172 return stream;
5173 }
5174
5175 /* Emit one vertex from the geometry shader */
5176 static void si_llvm_emit_vertex(
5177 const struct lp_build_tgsi_action *action,
5178 struct lp_build_tgsi_context *bld_base,
5179 struct lp_build_emit_data *emit_data)
5180 {
5181 struct si_shader_context *ctx = si_shader_context(bld_base);
5182 struct lp_build_context *uint = &bld_base->uint_bld;
5183 struct si_shader *shader = ctx->shader;
5184 struct tgsi_shader_info *info = &shader->selector->info;
5185 struct gallivm_state *gallivm = bld_base->base.gallivm;
5186 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5187 SI_PARAM_GS2VS_OFFSET);
5188 LLVMValueRef gs_next_vertex;
5189 LLVMValueRef can_emit, kill;
5190 LLVMValueRef args[2];
5191 unsigned chan;
5192 int i;
5193 unsigned stream;
5194
5195 stream = si_llvm_get_stream(bld_base, emit_data);
5196
5197 /* Write vertex attribute values to GSVS ring */
5198 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5199 ctx->gs_next_vertex[stream],
5200 "");
5201
5202 /* If this thread has already emitted the declared maximum number of
5203 * vertices, kill it: excessive vertex emissions are not supposed to
5204 * have any effect, and GS threads have no externally observable
5205 * effects other than emitting vertices.
5206 */
5207 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5208 lp_build_const_int32(gallivm,
5209 shader->selector->gs_max_out_vertices), "");
5210 kill = lp_build_select(&bld_base->base, can_emit,
5211 lp_build_const_float(gallivm, 1.0f),
5212 lp_build_const_float(gallivm, -1.0f));
5213
5214 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5215 ctx->voidt, &kill, 1, 0);
5216
5217 for (i = 0; i < info->num_outputs; i++) {
5218 LLVMValueRef *out_ptr =
5219 ctx->radeon_bld.soa.outputs[i];
5220
5221 for (chan = 0; chan < 4; chan++) {
5222 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5223 LLVMValueRef voffset =
5224 lp_build_const_int32(gallivm, (i * 4 + chan) *
5225 shader->selector->gs_max_out_vertices);
5226
5227 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5228 voffset = lp_build_mul_imm(uint, voffset, 4);
5229
5230 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5231
5232 build_tbuffer_store(ctx,
5233 ctx->gsvs_ring[stream],
5234 out_val, 1,
5235 voffset, soffset, 0,
5236 V_008F0C_BUF_DATA_FORMAT_32,
5237 V_008F0C_BUF_NUM_FORMAT_UINT,
5238 1, 0, 1, 1, 0);
5239 }
5240 }
5241 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5242 lp_build_const_int32(gallivm, 1));
5243
5244 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5245
5246 /* Signal vertex emission */
5247 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5248 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5249 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5250 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5251 }
5252
5253 /* Cut one primitive from the geometry shader */
5254 static void si_llvm_emit_primitive(
5255 const struct lp_build_tgsi_action *action,
5256 struct lp_build_tgsi_context *bld_base,
5257 struct lp_build_emit_data *emit_data)
5258 {
5259 struct si_shader_context *ctx = si_shader_context(bld_base);
5260 struct gallivm_state *gallivm = bld_base->base.gallivm;
5261 LLVMValueRef args[2];
5262 unsigned stream;
5263
5264 /* Signal primitive cut */
5265 stream = si_llvm_get_stream(bld_base, emit_data);
5266 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5267 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5268 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5269 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5270 }
5271
5272 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5273 struct lp_build_tgsi_context *bld_base,
5274 struct lp_build_emit_data *emit_data)
5275 {
5276 struct si_shader_context *ctx = si_shader_context(bld_base);
5277 struct gallivm_state *gallivm = bld_base->base.gallivm;
5278
5279 /* The real barrier instruction isn’t needed, because an entire patch
5280 * always fits into a single wave.
5281 */
5282 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5283 emit_optimization_barrier(ctx);
5284 return;
5285 }
5286
5287 lp_build_intrinsic(gallivm->builder,
5288 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5289 : "llvm.AMDGPU.barrier.local",
5290 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
5291 }
5292
5293 static const struct lp_build_tgsi_action tex_action = {
5294 .fetch_args = tex_fetch_args,
5295 .emit = build_tex_intrinsic,
5296 };
5297
5298 static const struct lp_build_tgsi_action interp_action = {
5299 .fetch_args = interp_fetch_args,
5300 .emit = build_interp_intrinsic,
5301 };
5302
5303 static void si_create_function(struct si_shader_context *ctx,
5304 LLVMTypeRef *returns, unsigned num_returns,
5305 LLVMTypeRef *params, unsigned num_params,
5306 int last_array_pointer, int last_sgpr)
5307 {
5308 int i;
5309
5310 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5311 params, num_params);
5312 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5313 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5314
5315 for (i = 0; i <= last_sgpr; ++i) {
5316 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5317
5318 /* We tell llvm that array inputs are passed by value to allow Sinking pass
5319 * to move load. Inputs are constant so this is fine. */
5320 if (i <= last_array_pointer)
5321 LLVMAddAttribute(P, LLVMByValAttribute);
5322 else
5323 LLVMAddAttribute(P, LLVMInRegAttribute);
5324 }
5325
5326 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5327 /* These were copied from some LLVM test. */
5328 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5329 "less-precise-fpmad",
5330 "true");
5331 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5332 "no-infs-fp-math",
5333 "true");
5334 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5335 "no-nans-fp-math",
5336 "true");
5337 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5338 "unsafe-fp-math",
5339 "true");
5340 }
5341 }
5342
5343 static void create_meta_data(struct si_shader_context *ctx)
5344 {
5345 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5346 LLVMValueRef args[3];
5347
5348 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
5349 args[1] = 0;
5350 args[2] = lp_build_const_int32(gallivm, 1);
5351
5352 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
5353
5354 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5355 "amdgpu.uniform", 14);
5356
5357 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5358 }
5359
5360 static void declare_streamout_params(struct si_shader_context *ctx,
5361 struct pipe_stream_output_info *so,
5362 LLVMTypeRef *params, LLVMTypeRef i32,
5363 unsigned *num_params)
5364 {
5365 int i;
5366
5367 /* Streamout SGPRs. */
5368 if (so->num_outputs) {
5369 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5370 params[ctx->param_streamout_config = (*num_params)++] = i32;
5371 else
5372 ctx->param_streamout_config = ctx->param_tess_offchip;
5373
5374 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5375 }
5376 /* A streamout buffer offset is loaded if the stride is non-zero. */
5377 for (i = 0; i < 4; i++) {
5378 if (!so->stride[i])
5379 continue;
5380
5381 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5382 }
5383 }
5384
5385 static unsigned llvm_get_type_size(LLVMTypeRef type)
5386 {
5387 LLVMTypeKind kind = LLVMGetTypeKind(type);
5388
5389 switch (kind) {
5390 case LLVMIntegerTypeKind:
5391 return LLVMGetIntTypeWidth(type) / 8;
5392 case LLVMFloatTypeKind:
5393 return 4;
5394 case LLVMPointerTypeKind:
5395 return 8;
5396 case LLVMVectorTypeKind:
5397 return LLVMGetVectorSize(type) *
5398 llvm_get_type_size(LLVMGetElementType(type));
5399 default:
5400 assert(0);
5401 return 0;
5402 }
5403 }
5404
5405 static void declare_tess_lds(struct si_shader_context *ctx)
5406 {
5407 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5408 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
5409 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5410
5411 /* The actual size is computed outside of the shader to reduce
5412 * the number of shader variants. */
5413 ctx->lds =
5414 LLVMAddGlobalInAddressSpace(gallivm->module,
5415 LLVMArrayType(i32, lds_size / 4),
5416 "tess_lds",
5417 LOCAL_ADDR_SPACE);
5418 }
5419
5420 static void create_function(struct si_shader_context *ctx)
5421 {
5422 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5423 struct gallivm_state *gallivm = bld_base->base.gallivm;
5424 struct si_shader *shader = ctx->shader;
5425 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5426 LLVMTypeRef returns[16+32*4];
5427 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
5428 unsigned num_returns = 0;
5429
5430 v3i32 = LLVMVectorType(ctx->i32, 3);
5431
5432 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5433 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5434 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5435 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5436 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5437 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
5438
5439 switch (ctx->type) {
5440 case PIPE_SHADER_VERTEX:
5441 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5442 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
5443 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5444 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5445 num_params = SI_PARAM_START_INSTANCE+1;
5446
5447 if (shader->key.vs.as_es) {
5448 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5449 } else if (shader->key.vs.as_ls) {
5450 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5451 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5452 } else {
5453 if (ctx->is_gs_copy_shader) {
5454 last_array_pointer = SI_PARAM_RW_BUFFERS;
5455 num_params = SI_PARAM_RW_BUFFERS+1;
5456 } else {
5457 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5458 num_params = SI_PARAM_VS_STATE_BITS+1;
5459 }
5460
5461 /* The locations of the other parameters are assigned dynamically. */
5462 declare_streamout_params(ctx, &shader->selector->so,
5463 params, ctx->i32, &num_params);
5464 }
5465
5466 last_sgpr = num_params-1;
5467
5468 /* VGPRs */
5469 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5470 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5471 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5472 params[ctx->param_instance_id = num_params++] = ctx->i32;
5473
5474 if (!ctx->is_monolithic &&
5475 !ctx->is_gs_copy_shader) {
5476 /* Vertex load indices. */
5477 ctx->param_vertex_index0 = num_params;
5478
5479 for (i = 0; i < shader->selector->info.num_inputs; i++)
5480 params[num_params++] = ctx->i32;
5481
5482 /* PrimitiveID output. */
5483 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5484 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5485 returns[num_returns++] = ctx->f32;
5486 }
5487 break;
5488
5489 case PIPE_SHADER_TESS_CTRL:
5490 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5491 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5492 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5493 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5494 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5495 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5496 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5497
5498 /* VGPRs */
5499 params[SI_PARAM_PATCH_ID] = ctx->i32;
5500 params[SI_PARAM_REL_IDS] = ctx->i32;
5501 num_params = SI_PARAM_REL_IDS+1;
5502
5503 if (!ctx->is_monolithic) {
5504 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5505 * placed after the user SGPRs.
5506 */
5507 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5508 returns[num_returns++] = ctx->i32; /* SGPRs */
5509
5510 for (i = 0; i < 3; i++)
5511 returns[num_returns++] = ctx->f32; /* VGPRs */
5512 }
5513 break;
5514
5515 case PIPE_SHADER_TESS_EVAL:
5516 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5517 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5518
5519 if (shader->key.tes.as_es) {
5520 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5521 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5522 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5523 } else {
5524 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5525 declare_streamout_params(ctx, &shader->selector->so,
5526 params, ctx->i32, &num_params);
5527 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5528 }
5529 last_sgpr = num_params - 1;
5530
5531 /* VGPRs */
5532 params[ctx->param_tes_u = num_params++] = ctx->f32;
5533 params[ctx->param_tes_v = num_params++] = ctx->f32;
5534 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5535 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5536
5537 /* PrimitiveID output. */
5538 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5539 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5540 returns[num_returns++] = ctx->f32;
5541 break;
5542
5543 case PIPE_SHADER_GEOMETRY:
5544 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5545 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5546 last_sgpr = SI_PARAM_GS_WAVE_ID;
5547
5548 /* VGPRs */
5549 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5550 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5551 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5552 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5553 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5554 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5555 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5556 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5557 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5558 break;
5559
5560 case PIPE_SHADER_FRAGMENT:
5561 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5562 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5563 last_sgpr = SI_PARAM_PRIM_MASK;
5564 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5565 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5566 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5567 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5568 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5569 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5570 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5571 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5572 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5573 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5574 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5575 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5576 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5577 params[SI_PARAM_ANCILLARY] = ctx->i32;
5578 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5579 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5580 num_params = SI_PARAM_POS_FIXED_PT+1;
5581
5582 if (!ctx->is_monolithic) {
5583 /* Color inputs from the prolog. */
5584 if (shader->selector->info.colors_read) {
5585 unsigned num_color_elements =
5586 util_bitcount(shader->selector->info.colors_read);
5587
5588 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5589 for (i = 0; i < num_color_elements; i++)
5590 params[num_params++] = ctx->f32;
5591 }
5592
5593 /* Outputs for the epilog. */
5594 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5595 num_returns =
5596 num_return_sgprs +
5597 util_bitcount(shader->selector->info.colors_written) * 4 +
5598 shader->selector->info.writes_z +
5599 shader->selector->info.writes_stencil +
5600 shader->selector->info.writes_samplemask +
5601 1 /* SampleMaskIn */;
5602
5603 num_returns = MAX2(num_returns,
5604 num_return_sgprs +
5605 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5606
5607 for (i = 0; i < num_return_sgprs; i++)
5608 returns[i] = ctx->i32;
5609 for (; i < num_returns; i++)
5610 returns[i] = ctx->f32;
5611 }
5612 break;
5613
5614 case PIPE_SHADER_COMPUTE:
5615 params[SI_PARAM_GRID_SIZE] = v3i32;
5616 params[SI_PARAM_BLOCK_ID] = v3i32;
5617 last_sgpr = SI_PARAM_BLOCK_ID;
5618
5619 params[SI_PARAM_THREAD_ID] = v3i32;
5620 num_params = SI_PARAM_THREAD_ID + 1;
5621 break;
5622 default:
5623 assert(0 && "unimplemented shader");
5624 return;
5625 }
5626
5627 assert(num_params <= ARRAY_SIZE(params));
5628
5629 si_create_function(ctx, returns, num_returns, params,
5630 num_params, last_array_pointer, last_sgpr);
5631
5632 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5633 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5634 !ctx->is_monolithic) {
5635 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5636 "InitialPSInputAddr",
5637 S_0286D0_PERSP_SAMPLE_ENA(1) |
5638 S_0286D0_PERSP_CENTER_ENA(1) |
5639 S_0286D0_PERSP_CENTROID_ENA(1) |
5640 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5641 S_0286D0_LINEAR_CENTER_ENA(1) |
5642 S_0286D0_LINEAR_CENTROID_ENA(1) |
5643 S_0286D0_FRONT_FACE_ENA(1) |
5644 S_0286D0_POS_FIXED_PT_ENA(1));
5645 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5646 const unsigned *properties = shader->selector->info.properties;
5647 unsigned max_work_group_size =
5648 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5649 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5650 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5651
5652 assert(max_work_group_size);
5653
5654 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5655 "amdgpu-max-work-group-size",
5656 max_work_group_size);
5657 }
5658
5659 shader->info.num_input_sgprs = 0;
5660 shader->info.num_input_vgprs = 0;
5661
5662 for (i = 0; i <= last_sgpr; ++i)
5663 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5664
5665 /* Unused fragment shader inputs are eliminated by the compiler,
5666 * so we don't know yet how many there will be.
5667 */
5668 if (ctx->type != PIPE_SHADER_FRAGMENT)
5669 for (; i < num_params; ++i)
5670 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5671
5672 if (bld_base->info &&
5673 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5674 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5675 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5676 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5677 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5678 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5679 ctx->lds =
5680 LLVMAddGlobalInAddressSpace(gallivm->module,
5681 LLVMArrayType(ctx->i32, 64),
5682 "ddxy_lds",
5683 LOCAL_ADDR_SPACE);
5684
5685 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5686 ctx->type == PIPE_SHADER_TESS_CTRL ||
5687 ctx->type == PIPE_SHADER_TESS_EVAL)
5688 declare_tess_lds(ctx);
5689 }
5690
5691 static void preload_constants(struct si_shader_context *ctx)
5692 {
5693 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5694 struct gallivm_state *gallivm = bld_base->base.gallivm;
5695 const struct tgsi_shader_info *info = bld_base->info;
5696 unsigned buf;
5697 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5698
5699 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5700 unsigned i, num_const = info->const_file_max[buf] + 1;
5701
5702 if (num_const == 0)
5703 continue;
5704
5705 /* Allocate space for the constant values */
5706 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5707
5708 /* Load the resource descriptor */
5709 ctx->const_buffers[buf] =
5710 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5711
5712 /* Load the constants, we rely on the code sinking to do the rest */
5713 for (i = 0; i < num_const * 4; ++i) {
5714 ctx->constants[buf][i] =
5715 buffer_load_const(gallivm->builder,
5716 ctx->const_buffers[buf],
5717 lp_build_const_int32(gallivm, i * 4),
5718 ctx->f32);
5719 }
5720 }
5721 }
5722
5723 static void preload_shader_buffers(struct si_shader_context *ctx)
5724 {
5725 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5726 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5727 int buf, maxbuf;
5728
5729 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5730 SI_NUM_SHADER_BUFFERS - 1);
5731 for (buf = 0; buf <= maxbuf; ++buf) {
5732 ctx->shader_buffers[buf] =
5733 build_indexed_load_const(
5734 ctx, ptr, lp_build_const_int32(gallivm, buf));
5735 }
5736 }
5737
5738 static void preload_samplers(struct si_shader_context *ctx)
5739 {
5740 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5741 struct gallivm_state *gallivm = bld_base->base.gallivm;
5742 const struct tgsi_shader_info *info = bld_base->info;
5743 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5744 LLVMValueRef offset;
5745
5746 if (num_samplers == 0)
5747 return;
5748
5749 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5750 for (i = 0; i < num_samplers; ++i) {
5751 /* Resource */
5752 offset = lp_build_const_int32(gallivm, i);
5753 ctx->sampler_views[i] =
5754 get_sampler_desc(ctx, offset, DESC_IMAGE);
5755
5756 /* FMASK resource */
5757 if (info->is_msaa_sampler[i])
5758 ctx->fmasks[i] =
5759 get_sampler_desc(ctx, offset, DESC_FMASK);
5760 else {
5761 ctx->sampler_states[i] =
5762 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5763 ctx->sampler_states[i] =
5764 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5765 ctx->sampler_states[i]);
5766 }
5767 }
5768 }
5769
5770 static void preload_images(struct si_shader_context *ctx)
5771 {
5772 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5773 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5774 struct gallivm_state *gallivm = bld_base->base.gallivm;
5775 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5776 LLVMValueRef res_ptr;
5777 unsigned i;
5778
5779 if (num_images == 0)
5780 return;
5781
5782 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5783
5784 for (i = 0; i < num_images; ++i) {
5785 /* Rely on LLVM to shrink the load for buffer resources. */
5786 LLVMValueRef rsrc =
5787 build_indexed_load_const(ctx, res_ptr,
5788 lp_build_const_int32(gallivm, i));
5789
5790 if (info->images_writemask & (1 << i) &&
5791 !(info->images_buffers & (1 << i)))
5792 rsrc = force_dcc_off(ctx, rsrc);
5793
5794 ctx->images[i] = rsrc;
5795 }
5796 }
5797
5798 static void preload_streamout_buffers(struct si_shader_context *ctx)
5799 {
5800 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5801 struct gallivm_state *gallivm = bld_base->base.gallivm;
5802 unsigned i;
5803
5804 /* Streamout can only be used if the shader is compiled as VS. */
5805 if (!ctx->shader->selector->so.num_outputs ||
5806 (ctx->type == PIPE_SHADER_VERTEX &&
5807 (ctx->shader->key.vs.as_es ||
5808 ctx->shader->key.vs.as_ls)) ||
5809 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5810 ctx->shader->key.tes.as_es))
5811 return;
5812
5813 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5814 SI_PARAM_RW_BUFFERS);
5815
5816 /* Load the resources, we rely on the code sinking to do the rest */
5817 for (i = 0; i < 4; ++i) {
5818 if (ctx->shader->selector->so.stride[i]) {
5819 LLVMValueRef offset = lp_build_const_int32(gallivm,
5820 SI_VS_STREAMOUT_BUF0 + i);
5821
5822 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5823 }
5824 }
5825 }
5826
5827 /**
5828 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5829 * for later use.
5830 */
5831 static void preload_ring_buffers(struct si_shader_context *ctx)
5832 {
5833 struct gallivm_state *gallivm =
5834 ctx->radeon_bld.soa.bld_base.base.gallivm;
5835
5836 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5837 SI_PARAM_RW_BUFFERS);
5838
5839 if ((ctx->type == PIPE_SHADER_VERTEX &&
5840 ctx->shader->key.vs.as_es) ||
5841 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5842 ctx->shader->key.tes.as_es) ||
5843 ctx->type == PIPE_SHADER_GEOMETRY) {
5844 unsigned ring =
5845 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5846 : SI_ES_RING_ESGS;
5847 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5848
5849 ctx->esgs_ring =
5850 build_indexed_load_const(ctx, buf_ptr, offset);
5851 }
5852
5853 if (ctx->is_gs_copy_shader) {
5854 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5855
5856 ctx->gsvs_ring[0] =
5857 build_indexed_load_const(ctx, buf_ptr, offset);
5858 }
5859 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5860 int i;
5861 for (i = 0; i < 4; i++) {
5862 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5863
5864 ctx->gsvs_ring[i] =
5865 build_indexed_load_const(ctx, buf_ptr, offset);
5866 }
5867 }
5868 }
5869
5870 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5871 LLVMValueRef param_rw_buffers,
5872 unsigned param_pos_fixed_pt)
5873 {
5874 struct lp_build_tgsi_context *bld_base =
5875 &ctx->radeon_bld.soa.bld_base;
5876 struct gallivm_state *gallivm = bld_base->base.gallivm;
5877 LLVMBuilderRef builder = gallivm->builder;
5878 LLVMValueRef slot, desc, offset, row, bit, address[2];
5879
5880 /* Use the fixed-point gl_FragCoord input.
5881 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5882 * per coordinate to get the repeating effect.
5883 */
5884 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5885 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5886
5887 /* Load the buffer descriptor. */
5888 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5889 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5890
5891 /* The stipple pattern is 32x32, each row has 32 bits. */
5892 offset = LLVMBuildMul(builder, address[1],
5893 LLVMConstInt(ctx->i32, 4, 0), "");
5894 row = buffer_load_const(builder, desc, offset, ctx->i32);
5895 bit = LLVMBuildLShr(builder, row, address[0], "");
5896 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5897
5898 /* The intrinsic kills the thread if arg < 0. */
5899 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5900 LLVMConstReal(ctx->f32, -1), "");
5901 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5902 }
5903
5904 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5905 struct si_shader_config *conf,
5906 unsigned symbol_offset)
5907 {
5908 unsigned i;
5909 const unsigned char *config =
5910 radeon_shader_binary_config_start(binary, symbol_offset);
5911 bool really_needs_scratch = false;
5912
5913 /* LLVM adds SGPR spills to the scratch size.
5914 * Find out if we really need the scratch buffer.
5915 */
5916 for (i = 0; i < binary->reloc_count; i++) {
5917 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5918
5919 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5920 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5921 really_needs_scratch = true;
5922 break;
5923 }
5924 }
5925
5926 /* XXX: We may be able to emit some of these values directly rather than
5927 * extracting fields to be emitted later.
5928 */
5929
5930 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5931 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5932 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5933 switch (reg) {
5934 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5935 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5936 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5937 case R_00B848_COMPUTE_PGM_RSRC1:
5938 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5939 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5940 conf->float_mode = G_00B028_FLOAT_MODE(value);
5941 conf->rsrc1 = value;
5942 break;
5943 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5944 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5945 break;
5946 case R_00B84C_COMPUTE_PGM_RSRC2:
5947 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5948 conf->rsrc2 = value;
5949 break;
5950 case R_0286CC_SPI_PS_INPUT_ENA:
5951 conf->spi_ps_input_ena = value;
5952 break;
5953 case R_0286D0_SPI_PS_INPUT_ADDR:
5954 conf->spi_ps_input_addr = value;
5955 break;
5956 case R_0286E8_SPI_TMPRING_SIZE:
5957 case R_00B860_COMPUTE_TMPRING_SIZE:
5958 /* WAVESIZE is in units of 256 dwords. */
5959 if (really_needs_scratch)
5960 conf->scratch_bytes_per_wave =
5961 G_00B860_WAVESIZE(value) * 256 * 4;
5962 break;
5963 default:
5964 {
5965 static bool printed;
5966
5967 if (!printed) {
5968 fprintf(stderr, "Warning: LLVM emitted unknown "
5969 "config register: 0x%x\n", reg);
5970 printed = true;
5971 }
5972 }
5973 break;
5974 }
5975
5976 if (!conf->spi_ps_input_addr)
5977 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5978 }
5979 }
5980
5981 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5982 struct si_shader *shader,
5983 struct si_shader_config *config,
5984 uint64_t scratch_va)
5985 {
5986 unsigned i;
5987 uint32_t scratch_rsrc_dword0 = scratch_va;
5988 uint32_t scratch_rsrc_dword1 =
5989 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5990
5991 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5992 * correctly.
5993 */
5994 if (HAVE_LLVM >= 0x0309)
5995 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5996 else
5997 scratch_rsrc_dword1 |=
5998 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5999
6000 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6001 const struct radeon_shader_reloc *reloc =
6002 &shader->binary.relocs[i];
6003 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6004 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6005 &scratch_rsrc_dword0, 4);
6006 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6007 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6008 &scratch_rsrc_dword1, 4);
6009 }
6010 }
6011 }
6012
6013 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6014 {
6015 unsigned size = shader->binary.code_size;
6016
6017 if (shader->prolog)
6018 size += shader->prolog->binary.code_size;
6019 if (shader->epilog)
6020 size += shader->epilog->binary.code_size;
6021 return size;
6022 }
6023
6024 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6025 {
6026 const struct radeon_shader_binary *prolog =
6027 shader->prolog ? &shader->prolog->binary : NULL;
6028 const struct radeon_shader_binary *epilog =
6029 shader->epilog ? &shader->epilog->binary : NULL;
6030 const struct radeon_shader_binary *mainb = &shader->binary;
6031 unsigned bo_size = si_get_shader_binary_size(shader) +
6032 (!epilog ? mainb->rodata_size : 0);
6033 unsigned char *ptr;
6034
6035 assert(!prolog || !prolog->rodata_size);
6036 assert((!prolog && !epilog) || !mainb->rodata_size);
6037 assert(!epilog || !epilog->rodata_size);
6038
6039 r600_resource_reference(&shader->bo, NULL);
6040 shader->bo = si_resource_create_custom(&sscreen->b.b,
6041 PIPE_USAGE_IMMUTABLE,
6042 bo_size);
6043 if (!shader->bo)
6044 return -ENOMEM;
6045
6046 /* Upload. */
6047 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6048 PIPE_TRANSFER_READ_WRITE);
6049
6050 if (prolog) {
6051 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6052 ptr += prolog->code_size;
6053 }
6054
6055 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6056 ptr += mainb->code_size;
6057
6058 if (epilog)
6059 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6060 else if (mainb->rodata_size > 0)
6061 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6062
6063 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6064 return 0;
6065 }
6066
6067 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6068 struct pipe_debug_callback *debug,
6069 const char *name, FILE *file)
6070 {
6071 char *line, *p;
6072 unsigned i, count;
6073
6074 if (binary->disasm_string) {
6075 fprintf(file, "Shader %s disassembly:\n", name);
6076 fprintf(file, "%s", binary->disasm_string);
6077
6078 if (debug && debug->debug_message) {
6079 /* Very long debug messages are cut off, so send the
6080 * disassembly one line at a time. This causes more
6081 * overhead, but on the plus side it simplifies
6082 * parsing of resulting logs.
6083 */
6084 pipe_debug_message(debug, SHADER_INFO,
6085 "Shader Disassembly Begin");
6086
6087 line = binary->disasm_string;
6088 while (*line) {
6089 p = util_strchrnul(line, '\n');
6090 count = p - line;
6091
6092 if (count) {
6093 pipe_debug_message(debug, SHADER_INFO,
6094 "%.*s", count, line);
6095 }
6096
6097 if (!*p)
6098 break;
6099 line = p + 1;
6100 }
6101
6102 pipe_debug_message(debug, SHADER_INFO,
6103 "Shader Disassembly End");
6104 }
6105 } else {
6106 fprintf(file, "Shader %s binary:\n", name);
6107 for (i = 0; i < binary->code_size; i += 4) {
6108 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6109 binary->code[i + 3], binary->code[i + 2],
6110 binary->code[i + 1], binary->code[i]);
6111 }
6112 }
6113 }
6114
6115 static void si_shader_dump_stats(struct si_screen *sscreen,
6116 struct si_shader_config *conf,
6117 unsigned num_inputs,
6118 unsigned code_size,
6119 struct pipe_debug_callback *debug,
6120 unsigned processor,
6121 FILE *file)
6122 {
6123 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6124 unsigned lds_per_wave = 0;
6125 unsigned max_simd_waves = 10;
6126 /* Assuming SGPRs aren't spilled. */
6127 unsigned spilled_vgprs = conf->scratch_bytes_per_wave / 64 / 4;
6128
6129 /* Compute LDS usage for PS. */
6130 if (processor == PIPE_SHADER_FRAGMENT) {
6131 /* The minimum usage per wave is (num_inputs * 48). The maximum
6132 * usage is (num_inputs * 48 * 16).
6133 * We can get anything in between and it varies between waves.
6134 *
6135 * The 48 bytes per input for a single primitive is equal to
6136 * 4 bytes/component * 4 components/input * 3 points.
6137 *
6138 * Other stages don't know the size at compile time or don't
6139 * allocate LDS per wave, but instead they do it per thread group.
6140 */
6141 lds_per_wave = conf->lds_size * lds_increment +
6142 align(num_inputs * 48, lds_increment);
6143 }
6144
6145 /* Compute the per-SIMD wave counts. */
6146 if (conf->num_sgprs) {
6147 if (sscreen->b.chip_class >= VI)
6148 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6149 else
6150 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6151 }
6152
6153 if (conf->num_vgprs)
6154 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6155
6156 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6157 * that PS can use.
6158 */
6159 if (lds_per_wave)
6160 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6161
6162 if (file != stderr ||
6163 r600_can_dump_shader(&sscreen->b, processor)) {
6164 if (processor == PIPE_SHADER_FRAGMENT) {
6165 fprintf(file, "*** SHADER CONFIG ***\n"
6166 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6167 "SPI_PS_INPUT_ENA = 0x%04x\n",
6168 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6169 }
6170
6171 fprintf(file, "*** SHADER STATS ***\n"
6172 "SGPRS: %d\n"
6173 "VGPRS: %d\n"
6174 "Spilled VGPRs: %d\n"
6175 "Code Size: %d bytes\n"
6176 "LDS: %d blocks\n"
6177 "Scratch: %d bytes per wave\n"
6178 "Max Waves: %d\n"
6179 "********************\n",
6180 conf->num_sgprs, conf->num_vgprs, spilled_vgprs, code_size,
6181 conf->lds_size, conf->scratch_bytes_per_wave,
6182 max_simd_waves);
6183 }
6184
6185 pipe_debug_message(debug, SHADER_INFO,
6186 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6187 "LDS: %d Scratch: %d Max Waves: %d Spilled VGPRs: %d",
6188 conf->num_sgprs, conf->num_vgprs, code_size,
6189 conf->lds_size, conf->scratch_bytes_per_wave,
6190 max_simd_waves, spilled_vgprs);
6191 }
6192
6193 static const char *si_get_shader_name(struct si_shader *shader,
6194 unsigned processor)
6195 {
6196 switch (processor) {
6197 case PIPE_SHADER_VERTEX:
6198 if (shader->key.vs.as_es)
6199 return "Vertex Shader as ES";
6200 else if (shader->key.vs.as_ls)
6201 return "Vertex Shader as LS";
6202 else
6203 return "Vertex Shader as VS";
6204 case PIPE_SHADER_TESS_CTRL:
6205 return "Tessellation Control Shader";
6206 case PIPE_SHADER_TESS_EVAL:
6207 if (shader->key.tes.as_es)
6208 return "Tessellation Evaluation Shader as ES";
6209 else
6210 return "Tessellation Evaluation Shader as VS";
6211 case PIPE_SHADER_GEOMETRY:
6212 if (shader->gs_copy_shader == NULL)
6213 return "GS Copy Shader as VS";
6214 else
6215 return "Geometry Shader";
6216 case PIPE_SHADER_FRAGMENT:
6217 return "Pixel Shader";
6218 case PIPE_SHADER_COMPUTE:
6219 return "Compute Shader";
6220 default:
6221 return "Unknown Shader";
6222 }
6223 }
6224
6225 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6226 struct pipe_debug_callback *debug, unsigned processor,
6227 FILE *file)
6228 {
6229 if (file != stderr ||
6230 (r600_can_dump_shader(&sscreen->b, processor) &&
6231 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6232 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6233
6234 if (shader->prolog)
6235 si_shader_dump_disassembly(&shader->prolog->binary,
6236 debug, "prolog", file);
6237
6238 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6239
6240 if (shader->epilog)
6241 si_shader_dump_disassembly(&shader->epilog->binary,
6242 debug, "epilog", file);
6243 fprintf(file, "\n");
6244 }
6245
6246 si_shader_dump_stats(sscreen, &shader->config,
6247 shader->selector ? shader->selector->info.num_inputs : 0,
6248 si_get_shader_binary_size(shader), debug, processor,
6249 file);
6250 }
6251
6252 int si_compile_llvm(struct si_screen *sscreen,
6253 struct radeon_shader_binary *binary,
6254 struct si_shader_config *conf,
6255 LLVMTargetMachineRef tm,
6256 LLVMModuleRef mod,
6257 struct pipe_debug_callback *debug,
6258 unsigned processor,
6259 const char *name)
6260 {
6261 int r = 0;
6262 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6263
6264 if (r600_can_dump_shader(&sscreen->b, processor)) {
6265 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6266
6267 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6268 fprintf(stderr, "%s LLVM IR:\n\n", name);
6269 LLVMDumpModule(mod);
6270 fprintf(stderr, "\n");
6271 }
6272 }
6273
6274 if (!si_replace_shader(count, binary)) {
6275 r = radeon_llvm_compile(mod, binary, tm, debug);
6276 if (r)
6277 return r;
6278 }
6279
6280 si_shader_binary_read_config(binary, conf, 0);
6281
6282 /* Enable 64-bit and 16-bit denormals, because there is no performance
6283 * cost.
6284 *
6285 * If denormals are enabled, all floating-point output modifiers are
6286 * ignored.
6287 *
6288 * Don't enable denormals for 32-bit floats, because:
6289 * - Floating-point output modifiers would be ignored by the hw.
6290 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6291 * have to stop using those.
6292 * - SI & CI would be very slow.
6293 */
6294 conf->float_mode |= V_00B028_FP_64_DENORMS;
6295
6296 FREE(binary->config);
6297 FREE(binary->global_symbol_offsets);
6298 binary->config = NULL;
6299 binary->global_symbol_offsets = NULL;
6300
6301 /* Some shaders can't have rodata because their binaries can be
6302 * concatenated.
6303 */
6304 if (binary->rodata_size &&
6305 (processor == PIPE_SHADER_VERTEX ||
6306 processor == PIPE_SHADER_TESS_CTRL ||
6307 processor == PIPE_SHADER_TESS_EVAL ||
6308 processor == PIPE_SHADER_FRAGMENT)) {
6309 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6310 return -EINVAL;
6311 }
6312
6313 return r;
6314 }
6315
6316 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6317 {
6318 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6319 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6320 else
6321 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6322 }
6323
6324 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6325 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6326 struct si_shader_context *ctx,
6327 struct si_shader *gs,
6328 struct pipe_debug_callback *debug)
6329 {
6330 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6331 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6332 struct lp_build_context *uint = &bld_base->uint_bld;
6333 struct si_shader_output_values *outputs;
6334 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6335 LLVMValueRef args[9];
6336 int i, r;
6337
6338 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6339
6340 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6341 ctx->type = PIPE_SHADER_VERTEX;
6342 ctx->is_gs_copy_shader = true;
6343
6344 create_meta_data(ctx);
6345 create_function(ctx);
6346 preload_streamout_buffers(ctx);
6347 preload_ring_buffers(ctx);
6348
6349 args[0] = ctx->gsvs_ring[0];
6350 args[1] = lp_build_mul_imm(uint,
6351 LLVMGetParam(ctx->radeon_bld.main_fn,
6352 ctx->param_vertex_id),
6353 4);
6354 args[3] = uint->zero;
6355 args[4] = uint->one; /* OFFEN */
6356 args[5] = uint->zero; /* IDXEN */
6357 args[6] = uint->one; /* GLC */
6358 args[7] = uint->one; /* SLC */
6359 args[8] = uint->zero; /* TFE */
6360
6361 /* Fetch vertex data from GSVS ring */
6362 for (i = 0; i < gsinfo->num_outputs; ++i) {
6363 unsigned chan;
6364
6365 outputs[i].name = gsinfo->output_semantic_name[i];
6366 outputs[i].sid = gsinfo->output_semantic_index[i];
6367
6368 for (chan = 0; chan < 4; chan++) {
6369 args[2] = lp_build_const_int32(gallivm,
6370 (i * 4 + chan) *
6371 gs->selector->gs_max_out_vertices * 16 * 4);
6372
6373 outputs[i].values[chan] =
6374 LLVMBuildBitCast(gallivm->builder,
6375 lp_build_intrinsic(gallivm->builder,
6376 "llvm.SI.buffer.load.dword.i32.i32",
6377 ctx->i32, args, 9,
6378 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
6379 ctx->f32, "");
6380 }
6381 }
6382
6383 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6384
6385 LLVMBuildRetVoid(gallivm->builder);
6386
6387 /* Dump LLVM IR before any optimization passes */
6388 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6389 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6390 LLVMDumpModule(bld_base->base.gallivm->module);
6391
6392 radeon_llvm_finalize_module(&ctx->radeon_bld);
6393
6394 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6395 &ctx->shader->config, ctx->tm,
6396 bld_base->base.gallivm->module,
6397 debug, PIPE_SHADER_GEOMETRY,
6398 "GS Copy Shader");
6399 if (!r) {
6400 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6401 fprintf(stderr, "GS Copy Shader:\n");
6402 si_shader_dump(sscreen, ctx->shader, debug,
6403 PIPE_SHADER_GEOMETRY, stderr);
6404 r = si_shader_binary_upload(sscreen, ctx->shader);
6405 }
6406
6407 radeon_llvm_dispose(&ctx->radeon_bld);
6408
6409 FREE(outputs);
6410 return r;
6411 }
6412
6413 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
6414 {
6415 int i;
6416
6417 fprintf(f, "SHADER KEY\n");
6418
6419 switch (shader) {
6420 case PIPE_SHADER_VERTEX:
6421 fprintf(f, " instance_divisors = {");
6422 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6423 fprintf(f, !i ? "%u" : ", %u",
6424 key->vs.prolog.instance_divisors[i]);
6425 fprintf(f, "}\n");
6426 fprintf(f, " as_es = %u\n", key->vs.as_es);
6427 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6428 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6429 break;
6430
6431 case PIPE_SHADER_TESS_CTRL:
6432 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6433 break;
6434
6435 case PIPE_SHADER_TESS_EVAL:
6436 fprintf(f, " as_es = %u\n", key->tes.as_es);
6437 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6438 break;
6439
6440 case PIPE_SHADER_GEOMETRY:
6441 case PIPE_SHADER_COMPUTE:
6442 break;
6443
6444 case PIPE_SHADER_FRAGMENT:
6445 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6446 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6447 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6448 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6449 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6450 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6451 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6452 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6453 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6454 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6455 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6456 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6457 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6458 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6459 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6460 break;
6461
6462 default:
6463 assert(0);
6464 }
6465 }
6466
6467 static void si_init_shader_ctx(struct si_shader_context *ctx,
6468 struct si_screen *sscreen,
6469 struct si_shader *shader,
6470 LLVMTargetMachineRef tm)
6471 {
6472 struct lp_build_tgsi_context *bld_base;
6473 struct lp_build_tgsi_action tmpl = {};
6474
6475 memset(ctx, 0, sizeof(*ctx));
6476 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
6477 ctx->tm = tm;
6478 ctx->screen = sscreen;
6479 if (shader && shader->selector)
6480 ctx->type = shader->selector->info.processor;
6481 else
6482 ctx->type = -1;
6483 ctx->shader = shader;
6484
6485 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6486 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6487 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6488 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6489 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6490 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6491 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6492 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6493 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6494 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6495 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6496 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6497
6498 bld_base = &ctx->radeon_bld.soa.bld_base;
6499 if (shader && shader->selector)
6500 bld_base->info = &shader->selector->info;
6501 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6502
6503 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6504 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6505 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6506
6507 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6508 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6509 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6510 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6511 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6512 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6513 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6514 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6515 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6516 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6517 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6518 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6519 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6520 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6521
6522 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6523 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6524 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6525 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6526 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6527 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6528
6529 tmpl.fetch_args = atomic_fetch_args;
6530 tmpl.emit = atomic_emit;
6531 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6532 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6533 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6534 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6535 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6536 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6537 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6538 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6539 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6540 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6541 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6542 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6543 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6544 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6545 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6546 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6547 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6548 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6549 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6550 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6551
6552 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6553
6554 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6555 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6556 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6557 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6558
6559 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6560 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6561 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6562
6563 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6564 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6565 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6566 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6567 }
6568
6569 int si_compile_tgsi_shader(struct si_screen *sscreen,
6570 LLVMTargetMachineRef tm,
6571 struct si_shader *shader,
6572 bool is_monolithic,
6573 struct pipe_debug_callback *debug)
6574 {
6575 struct si_shader_selector *sel = shader->selector;
6576 struct si_shader_context ctx;
6577 struct lp_build_tgsi_context *bld_base;
6578 LLVMModuleRef mod;
6579 int r = 0;
6580
6581 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6582 * conversion fails. */
6583 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6584 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6585 if (is_monolithic)
6586 si_dump_shader_key(sel->type, &shader->key, stderr);
6587 tgsi_dump(sel->tokens, 0);
6588 si_dump_streamout(&sel->so);
6589 }
6590
6591 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6592 ctx.is_monolithic = is_monolithic;
6593
6594 shader->info.uses_instanceid = sel->info.uses_instanceid;
6595
6596 bld_base = &ctx.radeon_bld.soa.bld_base;
6597 ctx.radeon_bld.load_system_value = declare_system_value;
6598
6599 switch (ctx.type) {
6600 case PIPE_SHADER_VERTEX:
6601 ctx.radeon_bld.load_input = declare_input_vs;
6602 if (shader->key.vs.as_ls)
6603 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6604 else if (shader->key.vs.as_es)
6605 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6606 else
6607 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6608 break;
6609 case PIPE_SHADER_TESS_CTRL:
6610 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6611 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6612 bld_base->emit_store = store_output_tcs;
6613 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6614 break;
6615 case PIPE_SHADER_TESS_EVAL:
6616 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6617 if (shader->key.tes.as_es)
6618 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6619 else
6620 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6621 break;
6622 case PIPE_SHADER_GEOMETRY:
6623 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6624 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6625 break;
6626 case PIPE_SHADER_FRAGMENT:
6627 ctx.radeon_bld.load_input = declare_input_fs;
6628 if (is_monolithic)
6629 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6630 else
6631 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6632 break;
6633 case PIPE_SHADER_COMPUTE:
6634 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6635 break;
6636 default:
6637 assert(!"Unsupported shader type");
6638 return -1;
6639 }
6640
6641 create_meta_data(&ctx);
6642 create_function(&ctx);
6643 preload_constants(&ctx);
6644 preload_shader_buffers(&ctx);
6645 preload_samplers(&ctx);
6646 preload_images(&ctx);
6647 preload_streamout_buffers(&ctx);
6648 preload_ring_buffers(&ctx);
6649
6650 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6651 shader->key.ps.prolog.poly_stipple) {
6652 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6653 SI_PARAM_RW_BUFFERS);
6654 si_llvm_emit_polygon_stipple(&ctx, list,
6655 SI_PARAM_POS_FIXED_PT);
6656 }
6657
6658 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6659 int i;
6660 for (i = 0; i < 4; i++) {
6661 ctx.gs_next_vertex[i] =
6662 lp_build_alloca(bld_base->base.gallivm,
6663 ctx.i32, "");
6664 }
6665 }
6666
6667 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6668 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6669 goto out;
6670 }
6671
6672 si_llvm_build_ret(&ctx, ctx.return_value);
6673 mod = bld_base->base.gallivm->module;
6674
6675 /* Dump LLVM IR before any optimization passes */
6676 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6677 r600_can_dump_shader(&sscreen->b, ctx.type))
6678 LLVMDumpModule(mod);
6679
6680 radeon_llvm_finalize_module(&ctx.radeon_bld);
6681
6682 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6683 mod, debug, ctx.type, "TGSI shader");
6684 if (r) {
6685 fprintf(stderr, "LLVM failed to compile shader\n");
6686 goto out;
6687 }
6688
6689 radeon_llvm_dispose(&ctx.radeon_bld);
6690
6691 /* Add the scratch offset to input SGPRs. */
6692 if (shader->config.scratch_bytes_per_wave)
6693 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6694
6695 /* Calculate the number of fragment input VGPRs. */
6696 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6697 shader->info.num_input_vgprs = 0;
6698 shader->info.face_vgpr_index = -1;
6699
6700 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6701 shader->info.num_input_vgprs += 2;
6702 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6703 shader->info.num_input_vgprs += 2;
6704 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6705 shader->info.num_input_vgprs += 2;
6706 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6707 shader->info.num_input_vgprs += 3;
6708 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6709 shader->info.num_input_vgprs += 2;
6710 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6711 shader->info.num_input_vgprs += 2;
6712 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6713 shader->info.num_input_vgprs += 2;
6714 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6715 shader->info.num_input_vgprs += 1;
6716 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6717 shader->info.num_input_vgprs += 1;
6718 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6719 shader->info.num_input_vgprs += 1;
6720 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6721 shader->info.num_input_vgprs += 1;
6722 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6723 shader->info.num_input_vgprs += 1;
6724 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6725 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6726 shader->info.num_input_vgprs += 1;
6727 }
6728 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6729 shader->info.num_input_vgprs += 1;
6730 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6731 shader->info.num_input_vgprs += 1;
6732 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6733 shader->info.num_input_vgprs += 1;
6734 }
6735
6736 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6737 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6738 shader->gs_copy_shader->selector = shader->selector;
6739 ctx.shader = shader->gs_copy_shader;
6740 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6741 shader, debug))) {
6742 free(shader->gs_copy_shader);
6743 shader->gs_copy_shader = NULL;
6744 goto out;
6745 }
6746 }
6747
6748 out:
6749 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6750 FREE(ctx.constants[i]);
6751 return r;
6752 }
6753
6754 /**
6755 * Create, compile and return a shader part (prolog or epilog).
6756 *
6757 * \param sscreen screen
6758 * \param list list of shader parts of the same category
6759 * \param key shader part key
6760 * \param tm LLVM target machine
6761 * \param debug debug callback
6762 * \param compile the callback responsible for compilation
6763 * \return non-NULL on success
6764 */
6765 static struct si_shader_part *
6766 si_get_shader_part(struct si_screen *sscreen,
6767 struct si_shader_part **list,
6768 union si_shader_part_key *key,
6769 LLVMTargetMachineRef tm,
6770 struct pipe_debug_callback *debug,
6771 bool (*compile)(struct si_screen *,
6772 LLVMTargetMachineRef,
6773 struct pipe_debug_callback *,
6774 struct si_shader_part *))
6775 {
6776 struct si_shader_part *result;
6777
6778 pipe_mutex_lock(sscreen->shader_parts_mutex);
6779
6780 /* Find existing. */
6781 for (result = *list; result; result = result->next) {
6782 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6783 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6784 return result;
6785 }
6786 }
6787
6788 /* Compile a new one. */
6789 result = CALLOC_STRUCT(si_shader_part);
6790 result->key = *key;
6791 if (!compile(sscreen, tm, debug, result)) {
6792 FREE(result);
6793 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6794 return NULL;
6795 }
6796
6797 result->next = *list;
6798 *list = result;
6799 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6800 return result;
6801 }
6802
6803 /**
6804 * Create a vertex shader prolog.
6805 *
6806 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6807 * All inputs are returned unmodified. The vertex load indices are
6808 * stored after them, which will used by the API VS for fetching inputs.
6809 *
6810 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6811 * input_v0,
6812 * input_v1,
6813 * input_v2,
6814 * input_v3,
6815 * (VertexID + BaseVertex),
6816 * (InstanceID + StartInstance),
6817 * (InstanceID / 2 + StartInstance)
6818 */
6819 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6820 LLVMTargetMachineRef tm,
6821 struct pipe_debug_callback *debug,
6822 struct si_shader_part *out)
6823 {
6824 union si_shader_part_key *key = &out->key;
6825 struct si_shader shader = {};
6826 struct si_shader_context ctx;
6827 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6828 LLVMTypeRef *params, *returns;
6829 LLVMValueRef ret, func;
6830 int last_sgpr, num_params, num_returns, i;
6831 bool status = true;
6832
6833 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6834 ctx.type = PIPE_SHADER_VERTEX;
6835 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6836 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6837
6838 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6839 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6840 sizeof(LLVMTypeRef));
6841 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6842 key->vs_prolog.last_input + 1) *
6843 sizeof(LLVMTypeRef));
6844 num_params = 0;
6845 num_returns = 0;
6846
6847 /* Declare input and output SGPRs. */
6848 num_params = 0;
6849 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6850 params[num_params++] = ctx.i32;
6851 returns[num_returns++] = ctx.i32;
6852 }
6853 last_sgpr = num_params - 1;
6854
6855 /* 4 preloaded VGPRs (outputs must be floats) */
6856 for (i = 0; i < 4; i++) {
6857 params[num_params++] = ctx.i32;
6858 returns[num_returns++] = ctx.f32;
6859 }
6860
6861 /* Vertex load indices. */
6862 for (i = 0; i <= key->vs_prolog.last_input; i++)
6863 returns[num_returns++] = ctx.f32;
6864
6865 /* Create the function. */
6866 si_create_function(&ctx, returns, num_returns, params,
6867 num_params, -1, last_sgpr);
6868 func = ctx.radeon_bld.main_fn;
6869
6870 /* Copy inputs to outputs. This should be no-op, as the registers match,
6871 * but it will prevent the compiler from overwriting them unintentionally.
6872 */
6873 ret = ctx.return_value;
6874 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6875 LLVMValueRef p = LLVMGetParam(func, i);
6876 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6877 }
6878 for (i = num_params - 4; i < num_params; i++) {
6879 LLVMValueRef p = LLVMGetParam(func, i);
6880 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6881 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6882 }
6883
6884 /* Compute vertex load indices from instance divisors. */
6885 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6886 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6887 LLVMValueRef index;
6888
6889 if (divisor) {
6890 /* InstanceID / Divisor + StartInstance */
6891 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6892 SI_SGPR_START_INSTANCE,
6893 divisor);
6894 } else {
6895 /* VertexID + BaseVertex */
6896 index = LLVMBuildAdd(gallivm->builder,
6897 LLVMGetParam(func, ctx.param_vertex_id),
6898 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6899 }
6900
6901 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6902 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6903 num_params++, "");
6904 }
6905
6906 /* Compile. */
6907 si_llvm_build_ret(&ctx, ret);
6908 radeon_llvm_finalize_module(&ctx.radeon_bld);
6909
6910 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6911 gallivm->module, debug, ctx.type,
6912 "Vertex Shader Prolog"))
6913 status = false;
6914
6915 radeon_llvm_dispose(&ctx.radeon_bld);
6916 return status;
6917 }
6918
6919 /**
6920 * Compile the vertex shader epilog. This is also used by the tessellation
6921 * evaluation shader compiled as VS.
6922 *
6923 * The input is PrimitiveID.
6924 *
6925 * If PrimitiveID is required by the pixel shader, export it.
6926 * Otherwise, do nothing.
6927 */
6928 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6929 LLVMTargetMachineRef tm,
6930 struct pipe_debug_callback *debug,
6931 struct si_shader_part *out)
6932 {
6933 union si_shader_part_key *key = &out->key;
6934 struct si_shader_context ctx;
6935 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6936 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6937 LLVMTypeRef params[5];
6938 int num_params, i;
6939 bool status = true;
6940
6941 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6942 ctx.type = PIPE_SHADER_VERTEX;
6943
6944 /* Declare input VGPRs. */
6945 num_params = key->vs_epilog.states.export_prim_id ?
6946 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6947 assert(num_params <= ARRAY_SIZE(params));
6948
6949 for (i = 0; i < num_params; i++)
6950 params[i] = ctx.f32;
6951
6952 /* Create the function. */
6953 si_create_function(&ctx, NULL, 0, params, num_params,
6954 -1, -1);
6955
6956 /* Emit exports. */
6957 if (key->vs_epilog.states.export_prim_id) {
6958 struct lp_build_context *base = &bld_base->base;
6959 struct lp_build_context *uint = &bld_base->uint_bld;
6960 LLVMValueRef args[9];
6961
6962 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6963 args[1] = uint->zero; /* whether the EXEC mask is valid */
6964 args[2] = uint->zero; /* DONE bit */
6965 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6966 key->vs_epilog.prim_id_param_offset);
6967 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6968 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6969 VS_EPILOG_PRIMID_LOC); /* X */
6970 args[6] = uint->undef; /* Y */
6971 args[7] = uint->undef; /* Z */
6972 args[8] = uint->undef; /* W */
6973
6974 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6975 LLVMVoidTypeInContext(base->gallivm->context),
6976 args, 9, 0);
6977 }
6978
6979 /* Compile. */
6980 LLVMBuildRetVoid(gallivm->builder);
6981 radeon_llvm_finalize_module(&ctx.radeon_bld);
6982
6983 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6984 gallivm->module, debug, ctx.type,
6985 "Vertex Shader Epilog"))
6986 status = false;
6987
6988 radeon_llvm_dispose(&ctx.radeon_bld);
6989 return status;
6990 }
6991
6992 /**
6993 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6994 */
6995 static bool si_get_vs_epilog(struct si_screen *sscreen,
6996 LLVMTargetMachineRef tm,
6997 struct si_shader *shader,
6998 struct pipe_debug_callback *debug,
6999 struct si_vs_epilog_bits *states)
7000 {
7001 union si_shader_part_key epilog_key;
7002
7003 memset(&epilog_key, 0, sizeof(epilog_key));
7004 epilog_key.vs_epilog.states = *states;
7005
7006 /* Set up the PrimitiveID output. */
7007 if (shader->key.vs.epilog.export_prim_id) {
7008 unsigned index = shader->selector->info.num_outputs;
7009 unsigned offset = shader->info.nr_param_exports++;
7010
7011 epilog_key.vs_epilog.prim_id_param_offset = offset;
7012 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7013 shader->info.vs_output_param_offset[index] = offset;
7014 }
7015
7016 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7017 &epilog_key, tm, debug,
7018 si_compile_vs_epilog);
7019 return shader->epilog != NULL;
7020 }
7021
7022 /**
7023 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7024 */
7025 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7026 LLVMTargetMachineRef tm,
7027 struct si_shader *shader,
7028 struct pipe_debug_callback *debug)
7029 {
7030 struct tgsi_shader_info *info = &shader->selector->info;
7031 union si_shader_part_key prolog_key;
7032 unsigned i;
7033
7034 /* Get the prolog. */
7035 memset(&prolog_key, 0, sizeof(prolog_key));
7036 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7037 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7038 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7039
7040 /* The prolog is a no-op if there are no inputs. */
7041 if (info->num_inputs) {
7042 shader->prolog =
7043 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7044 &prolog_key, tm, debug,
7045 si_compile_vs_prolog);
7046 if (!shader->prolog)
7047 return false;
7048 }
7049
7050 /* Get the epilog. */
7051 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7052 !si_get_vs_epilog(sscreen, tm, shader, debug,
7053 &shader->key.vs.epilog))
7054 return false;
7055
7056 /* Set the instanceID flag. */
7057 for (i = 0; i < info->num_inputs; i++)
7058 if (prolog_key.vs_prolog.states.instance_divisors[i])
7059 shader->info.uses_instanceid = true;
7060
7061 return true;
7062 }
7063
7064 /**
7065 * Select and compile (or reuse) TES parts (epilog).
7066 */
7067 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7068 LLVMTargetMachineRef tm,
7069 struct si_shader *shader,
7070 struct pipe_debug_callback *debug)
7071 {
7072 if (shader->key.tes.as_es)
7073 return true;
7074
7075 /* TES compiled as VS. */
7076 return si_get_vs_epilog(sscreen, tm, shader, debug,
7077 &shader->key.tes.epilog);
7078 }
7079
7080 /**
7081 * Compile the TCS epilog. This writes tesselation factors to memory based on
7082 * the output primitive type of the tesselator (determined by TES).
7083 */
7084 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7085 LLVMTargetMachineRef tm,
7086 struct pipe_debug_callback *debug,
7087 struct si_shader_part *out)
7088 {
7089 union si_shader_part_key *key = &out->key;
7090 struct si_shader shader = {};
7091 struct si_shader_context ctx;
7092 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7093 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7094 LLVMTypeRef params[16];
7095 LLVMValueRef func;
7096 int last_array_pointer, last_sgpr, num_params;
7097 bool status = true;
7098
7099 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7100 ctx.type = PIPE_SHADER_TESS_CTRL;
7101 shader.key.tcs.epilog = key->tcs_epilog.states;
7102
7103 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7104 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7105 last_array_pointer = SI_PARAM_RW_BUFFERS;
7106 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7107 params[SI_PARAM_SAMPLERS] = ctx.i64;
7108 params[SI_PARAM_IMAGES] = ctx.i64;
7109 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7110 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7111 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7112 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7113 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7114 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7115 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7116 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7117 num_params = last_sgpr + 1;
7118
7119 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7120 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7121 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7122
7123 /* Create the function. */
7124 si_create_function(&ctx, NULL, 0, params, num_params,
7125 last_array_pointer, last_sgpr);
7126 declare_tess_lds(&ctx);
7127 func = ctx.radeon_bld.main_fn;
7128
7129 si_write_tess_factors(bld_base,
7130 LLVMGetParam(func, last_sgpr + 1),
7131 LLVMGetParam(func, last_sgpr + 2),
7132 LLVMGetParam(func, last_sgpr + 3));
7133
7134 /* Compile. */
7135 LLVMBuildRetVoid(gallivm->builder);
7136 radeon_llvm_finalize_module(&ctx.radeon_bld);
7137
7138 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7139 gallivm->module, debug, ctx.type,
7140 "Tessellation Control Shader Epilog"))
7141 status = false;
7142
7143 radeon_llvm_dispose(&ctx.radeon_bld);
7144 return status;
7145 }
7146
7147 /**
7148 * Select and compile (or reuse) TCS parts (epilog).
7149 */
7150 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7151 LLVMTargetMachineRef tm,
7152 struct si_shader *shader,
7153 struct pipe_debug_callback *debug)
7154 {
7155 union si_shader_part_key epilog_key;
7156
7157 /* Get the epilog. */
7158 memset(&epilog_key, 0, sizeof(epilog_key));
7159 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7160
7161 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7162 &epilog_key, tm, debug,
7163 si_compile_tcs_epilog);
7164 return shader->epilog != NULL;
7165 }
7166
7167 /**
7168 * Compile the pixel shader prolog. This handles:
7169 * - two-side color selection and interpolation
7170 * - overriding interpolation parameters for the API PS
7171 * - polygon stippling
7172 *
7173 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7174 * overriden by other states. (e.g. per-sample interpolation)
7175 * Interpolated colors are stored after the preloaded VGPRs.
7176 */
7177 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7178 LLVMTargetMachineRef tm,
7179 struct pipe_debug_callback *debug,
7180 struct si_shader_part *out)
7181 {
7182 union si_shader_part_key *key = &out->key;
7183 struct si_shader shader = {};
7184 struct si_shader_context ctx;
7185 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7186 LLVMTypeRef *params;
7187 LLVMValueRef ret, func;
7188 int last_sgpr, num_params, num_returns, i, num_color_channels;
7189 bool status = true;
7190
7191 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7192 ctx.type = PIPE_SHADER_FRAGMENT;
7193 shader.key.ps.prolog = key->ps_prolog.states;
7194
7195 /* Number of inputs + 8 color elements. */
7196 params = alloca((key->ps_prolog.num_input_sgprs +
7197 key->ps_prolog.num_input_vgprs + 8) *
7198 sizeof(LLVMTypeRef));
7199
7200 /* Declare inputs. */
7201 num_params = 0;
7202 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7203 params[num_params++] = ctx.i32;
7204 last_sgpr = num_params - 1;
7205
7206 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7207 params[num_params++] = ctx.f32;
7208
7209 /* Declare outputs (same as inputs + add colors if needed) */
7210 num_returns = num_params;
7211 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7212 for (i = 0; i < num_color_channels; i++)
7213 params[num_returns++] = ctx.f32;
7214
7215 /* Create the function. */
7216 si_create_function(&ctx, params, num_returns, params,
7217 num_params, -1, last_sgpr);
7218 func = ctx.radeon_bld.main_fn;
7219
7220 /* Copy inputs to outputs. This should be no-op, as the registers match,
7221 * but it will prevent the compiler from overwriting them unintentionally.
7222 */
7223 ret = ctx.return_value;
7224 for (i = 0; i < num_params; i++) {
7225 LLVMValueRef p = LLVMGetParam(func, i);
7226 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7227 }
7228
7229 /* Polygon stippling. */
7230 if (key->ps_prolog.states.poly_stipple) {
7231 /* POS_FIXED_PT is always last. */
7232 unsigned pos = key->ps_prolog.num_input_sgprs +
7233 key->ps_prolog.num_input_vgprs - 1;
7234 LLVMValueRef ptr[2], list;
7235
7236 /* Get the pointer to rw buffers. */
7237 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7238 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7239 list = lp_build_gather_values(gallivm, ptr, 2);
7240 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7241 list = LLVMBuildIntToPtr(gallivm->builder, list,
7242 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7243
7244 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7245 }
7246
7247 if (key->ps_prolog.states.bc_optimize_for_persp ||
7248 key->ps_prolog.states.bc_optimize_for_linear) {
7249 unsigned i, base = key->ps_prolog.num_input_sgprs;
7250 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7251
7252 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7253 * The hw doesn't compute CENTROID if the whole wave only
7254 * contains fully-covered quads.
7255 *
7256 * PRIM_MASK is after user SGPRs.
7257 */
7258 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7259 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7260 LLVMConstInt(ctx.i32, 31, 0), "");
7261 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7262 ctx.i1, "");
7263
7264 if (key->ps_prolog.states.bc_optimize_for_persp) {
7265 /* Read PERSP_CENTER. */
7266 for (i = 0; i < 2; i++)
7267 center[i] = LLVMGetParam(func, base + 2 + i);
7268 /* Read PERSP_CENTROID. */
7269 for (i = 0; i < 2; i++)
7270 centroid[i] = LLVMGetParam(func, base + 4 + i);
7271 /* Select PERSP_CENTROID. */
7272 for (i = 0; i < 2; i++) {
7273 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7274 center[i], centroid[i], "");
7275 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7276 tmp, base + 4 + i, "");
7277 }
7278 }
7279 if (key->ps_prolog.states.bc_optimize_for_linear) {
7280 /* Read LINEAR_CENTER. */
7281 for (i = 0; i < 2; i++)
7282 center[i] = LLVMGetParam(func, base + 8 + i);
7283 /* Read LINEAR_CENTROID. */
7284 for (i = 0; i < 2; i++)
7285 centroid[i] = LLVMGetParam(func, base + 10 + i);
7286 /* Select LINEAR_CENTROID. */
7287 for (i = 0; i < 2; i++) {
7288 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7289 center[i], centroid[i], "");
7290 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7291 tmp, base + 10 + i, "");
7292 }
7293 }
7294 }
7295
7296 /* Interpolate colors. */
7297 for (i = 0; i < 2; i++) {
7298 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7299 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7300 key->ps_prolog.face_vgpr_index;
7301 LLVMValueRef interp[2], color[4];
7302 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7303
7304 if (!writemask)
7305 continue;
7306
7307 /* If the interpolation qualifier is not CONSTANT (-1). */
7308 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7309 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7310 key->ps_prolog.color_interp_vgpr_index[i];
7311
7312 /* Get the (i,j) updated by bc_optimize handling. */
7313 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7314 interp_vgpr, "");
7315 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7316 interp_vgpr + 1, "");
7317 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7318 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7319 ctx.v2i32, "");
7320 }
7321
7322 /* Use the absolute location of the input. */
7323 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7324
7325 if (key->ps_prolog.states.color_two_side) {
7326 face = LLVMGetParam(func, face_vgpr);
7327 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7328 }
7329
7330 interp_fs_input(&ctx,
7331 key->ps_prolog.color_attr_index[i],
7332 TGSI_SEMANTIC_COLOR, i,
7333 key->ps_prolog.num_interp_inputs,
7334 key->ps_prolog.colors_read, interp_ij,
7335 prim_mask, face, color);
7336
7337 while (writemask) {
7338 unsigned chan = u_bit_scan(&writemask);
7339 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7340 num_params++, "");
7341 }
7342 }
7343
7344 /* Force per-sample interpolation. */
7345 if (key->ps_prolog.states.force_persp_sample_interp) {
7346 unsigned i, base = key->ps_prolog.num_input_sgprs;
7347 LLVMValueRef persp_sample[2];
7348
7349 /* Read PERSP_SAMPLE. */
7350 for (i = 0; i < 2; i++)
7351 persp_sample[i] = LLVMGetParam(func, base + i);
7352 /* Overwrite PERSP_CENTER. */
7353 for (i = 0; i < 2; i++)
7354 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7355 persp_sample[i], base + 2 + i, "");
7356 /* Overwrite PERSP_CENTROID. */
7357 for (i = 0; i < 2; i++)
7358 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7359 persp_sample[i], base + 4 + i, "");
7360 }
7361 if (key->ps_prolog.states.force_linear_sample_interp) {
7362 unsigned i, base = key->ps_prolog.num_input_sgprs;
7363 LLVMValueRef linear_sample[2];
7364
7365 /* Read LINEAR_SAMPLE. */
7366 for (i = 0; i < 2; i++)
7367 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7368 /* Overwrite LINEAR_CENTER. */
7369 for (i = 0; i < 2; i++)
7370 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7371 linear_sample[i], base + 8 + i, "");
7372 /* Overwrite LINEAR_CENTROID. */
7373 for (i = 0; i < 2; i++)
7374 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7375 linear_sample[i], base + 10 + i, "");
7376 }
7377
7378 /* Force center interpolation. */
7379 if (key->ps_prolog.states.force_persp_center_interp) {
7380 unsigned i, base = key->ps_prolog.num_input_sgprs;
7381 LLVMValueRef persp_center[2];
7382
7383 /* Read PERSP_CENTER. */
7384 for (i = 0; i < 2; i++)
7385 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7386 /* Overwrite PERSP_SAMPLE. */
7387 for (i = 0; i < 2; i++)
7388 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7389 persp_center[i], base + i, "");
7390 /* Overwrite PERSP_CENTROID. */
7391 for (i = 0; i < 2; i++)
7392 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7393 persp_center[i], base + 4 + i, "");
7394 }
7395 if (key->ps_prolog.states.force_linear_center_interp) {
7396 unsigned i, base = key->ps_prolog.num_input_sgprs;
7397 LLVMValueRef linear_center[2];
7398
7399 /* Read LINEAR_CENTER. */
7400 for (i = 0; i < 2; i++)
7401 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7402 /* Overwrite LINEAR_SAMPLE. */
7403 for (i = 0; i < 2; i++)
7404 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7405 linear_center[i], base + 6 + i, "");
7406 /* Overwrite LINEAR_CENTROID. */
7407 for (i = 0; i < 2; i++)
7408 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7409 linear_center[i], base + 10 + i, "");
7410 }
7411
7412 /* Tell LLVM to insert WQM instruction sequence when needed. */
7413 if (key->ps_prolog.wqm) {
7414 LLVMAddTargetDependentFunctionAttr(func,
7415 "amdgpu-ps-wqm-outputs", "");
7416 }
7417
7418 /* Compile. */
7419 si_llvm_build_ret(&ctx, ret);
7420 radeon_llvm_finalize_module(&ctx.radeon_bld);
7421
7422 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7423 gallivm->module, debug, ctx.type,
7424 "Fragment Shader Prolog"))
7425 status = false;
7426
7427 radeon_llvm_dispose(&ctx.radeon_bld);
7428 return status;
7429 }
7430
7431 /**
7432 * Compile the pixel shader epilog. This handles everything that must be
7433 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7434 */
7435 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7436 LLVMTargetMachineRef tm,
7437 struct pipe_debug_callback *debug,
7438 struct si_shader_part *out)
7439 {
7440 union si_shader_part_key *key = &out->key;
7441 struct si_shader shader = {};
7442 struct si_shader_context ctx;
7443 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7444 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7445 LLVMTypeRef params[16+8*4+3];
7446 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7447 int last_array_pointer, last_sgpr, num_params, i;
7448 bool status = true;
7449
7450 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7451 ctx.type = PIPE_SHADER_FRAGMENT;
7452 shader.key.ps.epilog = key->ps_epilog.states;
7453
7454 /* Declare input SGPRs. */
7455 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7456 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7457 params[SI_PARAM_SAMPLERS] = ctx.i64;
7458 params[SI_PARAM_IMAGES] = ctx.i64;
7459 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7460 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7461 last_array_pointer = -1;
7462 last_sgpr = SI_PARAM_ALPHA_REF;
7463
7464 /* Declare input VGPRs. */
7465 num_params = (last_sgpr + 1) +
7466 util_bitcount(key->ps_epilog.colors_written) * 4 +
7467 key->ps_epilog.writes_z +
7468 key->ps_epilog.writes_stencil +
7469 key->ps_epilog.writes_samplemask;
7470
7471 num_params = MAX2(num_params,
7472 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7473
7474 assert(num_params <= ARRAY_SIZE(params));
7475
7476 for (i = last_sgpr + 1; i < num_params; i++)
7477 params[i] = ctx.f32;
7478
7479 /* Create the function. */
7480 si_create_function(&ctx, NULL, 0, params, num_params,
7481 last_array_pointer, last_sgpr);
7482 /* Disable elimination of unused inputs. */
7483 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7484 "InitialPSInputAddr", 0xffffff);
7485
7486 /* Process colors. */
7487 unsigned vgpr = last_sgpr + 1;
7488 unsigned colors_written = key->ps_epilog.colors_written;
7489 int last_color_export = -1;
7490
7491 /* Find the last color export. */
7492 if (!key->ps_epilog.writes_z &&
7493 !key->ps_epilog.writes_stencil &&
7494 !key->ps_epilog.writes_samplemask) {
7495 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7496
7497 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7498 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7499 /* Just set this if any of the colorbuffers are enabled. */
7500 if (spi_format &
7501 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7502 last_color_export = 0;
7503 } else {
7504 for (i = 0; i < 8; i++)
7505 if (colors_written & (1 << i) &&
7506 (spi_format >> (i * 4)) & 0xf)
7507 last_color_export = i;
7508 }
7509 }
7510
7511 while (colors_written) {
7512 LLVMValueRef color[4];
7513 int mrt = u_bit_scan(&colors_written);
7514
7515 for (i = 0; i < 4; i++)
7516 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7517
7518 si_export_mrt_color(bld_base, color, mrt,
7519 num_params - 1,
7520 mrt == last_color_export);
7521 }
7522
7523 /* Process depth, stencil, samplemask. */
7524 if (key->ps_epilog.writes_z)
7525 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7526 if (key->ps_epilog.writes_stencil)
7527 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7528 if (key->ps_epilog.writes_samplemask)
7529 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7530
7531 if (depth || stencil || samplemask)
7532 si_export_mrt_z(bld_base, depth, stencil, samplemask);
7533 else if (last_color_export == -1)
7534 si_export_null(bld_base);
7535
7536 /* Compile. */
7537 LLVMBuildRetVoid(gallivm->builder);
7538 radeon_llvm_finalize_module(&ctx.radeon_bld);
7539
7540 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7541 gallivm->module, debug, ctx.type,
7542 "Fragment Shader Epilog"))
7543 status = false;
7544
7545 radeon_llvm_dispose(&ctx.radeon_bld);
7546 return status;
7547 }
7548
7549 /**
7550 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7551 */
7552 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7553 LLVMTargetMachineRef tm,
7554 struct si_shader *shader,
7555 struct pipe_debug_callback *debug)
7556 {
7557 struct tgsi_shader_info *info = &shader->selector->info;
7558 union si_shader_part_key prolog_key;
7559 union si_shader_part_key epilog_key;
7560 unsigned i;
7561
7562 /* Get the prolog. */
7563 memset(&prolog_key, 0, sizeof(prolog_key));
7564 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7565 prolog_key.ps_prolog.colors_read = info->colors_read;
7566 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7567 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7568 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7569 (prolog_key.ps_prolog.colors_read ||
7570 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7571 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7572 prolog_key.ps_prolog.states.force_persp_center_interp ||
7573 prolog_key.ps_prolog.states.force_linear_center_interp ||
7574 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7575 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7576
7577 if (info->colors_read) {
7578 unsigned *color = shader->selector->color_attr_index;
7579
7580 if (shader->key.ps.prolog.color_two_side) {
7581 /* BCOLORs are stored after the last input. */
7582 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7583 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7584 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7585 }
7586
7587 for (i = 0; i < 2; i++) {
7588 unsigned location = info->input_interpolate_loc[color[i]];
7589
7590 if (!(info->colors_read & (0xf << i*4)))
7591 continue;
7592
7593 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7594
7595 switch (info->input_interpolate[color[i]]) {
7596 case TGSI_INTERPOLATE_CONSTANT:
7597 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7598 break;
7599 case TGSI_INTERPOLATE_PERSPECTIVE:
7600 case TGSI_INTERPOLATE_COLOR:
7601 /* Force the interpolation location for colors here. */
7602 if (shader->key.ps.prolog.force_persp_sample_interp)
7603 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7604 if (shader->key.ps.prolog.force_persp_center_interp)
7605 location = TGSI_INTERPOLATE_LOC_CENTER;
7606
7607 switch (location) {
7608 case TGSI_INTERPOLATE_LOC_SAMPLE:
7609 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7610 shader->config.spi_ps_input_ena |=
7611 S_0286CC_PERSP_SAMPLE_ENA(1);
7612 break;
7613 case TGSI_INTERPOLATE_LOC_CENTER:
7614 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7615 shader->config.spi_ps_input_ena |=
7616 S_0286CC_PERSP_CENTER_ENA(1);
7617 break;
7618 case TGSI_INTERPOLATE_LOC_CENTROID:
7619 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7620 shader->config.spi_ps_input_ena |=
7621 S_0286CC_PERSP_CENTROID_ENA(1);
7622 break;
7623 default:
7624 assert(0);
7625 }
7626 break;
7627 case TGSI_INTERPOLATE_LINEAR:
7628 /* Force the interpolation location for colors here. */
7629 if (shader->key.ps.prolog.force_linear_sample_interp)
7630 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7631 if (shader->key.ps.prolog.force_linear_center_interp)
7632 location = TGSI_INTERPOLATE_LOC_CENTER;
7633
7634 switch (location) {
7635 case TGSI_INTERPOLATE_LOC_SAMPLE:
7636 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7637 shader->config.spi_ps_input_ena |=
7638 S_0286CC_LINEAR_SAMPLE_ENA(1);
7639 break;
7640 case TGSI_INTERPOLATE_LOC_CENTER:
7641 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7642 shader->config.spi_ps_input_ena |=
7643 S_0286CC_LINEAR_CENTER_ENA(1);
7644 break;
7645 case TGSI_INTERPOLATE_LOC_CENTROID:
7646 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7647 shader->config.spi_ps_input_ena |=
7648 S_0286CC_LINEAR_CENTROID_ENA(1);
7649 break;
7650 default:
7651 assert(0);
7652 }
7653 break;
7654 default:
7655 assert(0);
7656 }
7657 }
7658 }
7659
7660 /* The prolog is a no-op if these aren't set. */
7661 if (prolog_key.ps_prolog.colors_read ||
7662 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7663 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7664 prolog_key.ps_prolog.states.force_persp_center_interp ||
7665 prolog_key.ps_prolog.states.force_linear_center_interp ||
7666 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7667 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7668 prolog_key.ps_prolog.states.poly_stipple) {
7669 shader->prolog =
7670 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7671 &prolog_key, tm, debug,
7672 si_compile_ps_prolog);
7673 if (!shader->prolog)
7674 return false;
7675 }
7676
7677 /* Get the epilog. */
7678 memset(&epilog_key, 0, sizeof(epilog_key));
7679 epilog_key.ps_epilog.colors_written = info->colors_written;
7680 epilog_key.ps_epilog.writes_z = info->writes_z;
7681 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7682 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7683 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7684
7685 shader->epilog =
7686 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7687 &epilog_key, tm, debug,
7688 si_compile_ps_epilog);
7689 if (!shader->epilog)
7690 return false;
7691
7692 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7693 if (shader->key.ps.prolog.poly_stipple) {
7694 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7695 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7696 }
7697
7698 /* Set up the enable bits for per-sample shading if needed. */
7699 if (shader->key.ps.prolog.force_persp_sample_interp &&
7700 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7701 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7702 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7703 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7704 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7705 }
7706 if (shader->key.ps.prolog.force_linear_sample_interp &&
7707 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7708 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7709 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7710 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7711 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7712 }
7713 if (shader->key.ps.prolog.force_persp_center_interp &&
7714 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7715 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7716 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7717 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7718 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7719 }
7720 if (shader->key.ps.prolog.force_linear_center_interp &&
7721 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7722 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7723 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7724 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7725 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7726 }
7727
7728 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7729 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7730 !(shader->config.spi_ps_input_ena & 0xf)) {
7731 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7732 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7733 }
7734
7735 /* At least one pair of interpolation weights must be enabled. */
7736 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7737 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7738 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7739 }
7740
7741 /* The sample mask input is always enabled, because the API shader always
7742 * passes it through to the epilog. Disable it here if it's unused.
7743 */
7744 if (!shader->key.ps.epilog.poly_line_smoothing &&
7745 !shader->selector->info.reads_samplemask)
7746 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7747
7748 return true;
7749 }
7750
7751 static void si_fix_num_sgprs(struct si_shader *shader)
7752 {
7753 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7754
7755 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7756 }
7757
7758 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7759 struct si_shader *shader,
7760 struct pipe_debug_callback *debug)
7761 {
7762 struct si_shader *mainp = shader->selector->main_shader_part;
7763 int r;
7764
7765 /* LS, ES, VS are compiled on demand if the main part hasn't been
7766 * compiled for that stage.
7767 */
7768 if (!mainp ||
7769 (shader->selector->type == PIPE_SHADER_VERTEX &&
7770 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7771 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7772 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7773 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7774 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7775 shader->key.tcs.epilog.inputs_to_copy) ||
7776 shader->selector->type == PIPE_SHADER_COMPUTE) {
7777 /* Monolithic shader (compiled as a whole, has many variants,
7778 * may take a long time to compile).
7779 */
7780 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7781 if (r)
7782 return r;
7783 } else {
7784 /* The shader consists of 2-3 parts:
7785 *
7786 * - the middle part is the user shader, it has 1 variant only
7787 * and it was compiled during the creation of the shader
7788 * selector
7789 * - the prolog part is inserted at the beginning
7790 * - the epilog part is inserted at the end
7791 *
7792 * The prolog and epilog have many (but simple) variants.
7793 */
7794
7795 /* Copy the compiled TGSI shader data over. */
7796 shader->is_binary_shared = true;
7797 shader->binary = mainp->binary;
7798 shader->config = mainp->config;
7799 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7800 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7801 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7802 memcpy(shader->info.vs_output_param_offset,
7803 mainp->info.vs_output_param_offset,
7804 sizeof(mainp->info.vs_output_param_offset));
7805 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7806 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7807 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7808
7809 /* Select prologs and/or epilogs. */
7810 switch (shader->selector->type) {
7811 case PIPE_SHADER_VERTEX:
7812 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7813 return -1;
7814 break;
7815 case PIPE_SHADER_TESS_CTRL:
7816 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7817 return -1;
7818 break;
7819 case PIPE_SHADER_TESS_EVAL:
7820 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7821 return -1;
7822 break;
7823 case PIPE_SHADER_FRAGMENT:
7824 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7825 return -1;
7826
7827 /* Make sure we have at least as many VGPRs as there
7828 * are allocated inputs.
7829 */
7830 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7831 shader->info.num_input_vgprs);
7832 break;
7833 }
7834
7835 /* Update SGPR and VGPR counts. */
7836 if (shader->prolog) {
7837 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7838 shader->prolog->config.num_sgprs);
7839 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7840 shader->prolog->config.num_vgprs);
7841 }
7842 if (shader->epilog) {
7843 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7844 shader->epilog->config.num_sgprs);
7845 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7846 shader->epilog->config.num_vgprs);
7847 }
7848 }
7849
7850 si_fix_num_sgprs(shader);
7851 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7852 stderr);
7853
7854 /* Upload. */
7855 r = si_shader_binary_upload(sscreen, shader);
7856 if (r) {
7857 fprintf(stderr, "LLVM failed to upload shader\n");
7858 return r;
7859 }
7860
7861 return 0;
7862 }
7863
7864 void si_shader_destroy(struct si_shader *shader)
7865 {
7866 if (shader->gs_copy_shader) {
7867 si_shader_destroy(shader->gs_copy_shader);
7868 FREE(shader->gs_copy_shader);
7869 }
7870
7871 if (shader->scratch_bo)
7872 r600_resource_reference(&shader->scratch_bo, NULL);
7873
7874 r600_resource_reference(&shader->bo, NULL);
7875
7876 if (!shader->is_binary_shared)
7877 radeon_shader_binary_clean(&shader->binary);
7878 }