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ac/nir: pass the nir variable through tcs loading.
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 unsigned offset = i;
1295 if (llvm_type_is_64bit(ctx, type))
1296 offset *= 2;
1297
1298 value[i] = lds_load(bld_base, type, offset, dw_addr);
1299 }
1300
1301 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1302 }
1303
1304 static LLVMValueRef fetch_output_tcs(
1305 struct lp_build_tgsi_context *bld_base,
1306 const struct tgsi_full_src_register *reg,
1307 enum tgsi_opcode_type type, unsigned swizzle)
1308 {
1309 struct si_shader_context *ctx = si_shader_context(bld_base);
1310 LLVMValueRef dw_addr, stride;
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1316 } else {
1317 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1318 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1319 }
1320
1321 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1322 }
1323
1324 static LLVMValueRef fetch_input_tes(
1325 struct lp_build_tgsi_context *bld_base,
1326 const struct tgsi_full_src_register *reg,
1327 enum tgsi_opcode_type type, unsigned swizzle)
1328 {
1329 struct si_shader_context *ctx = si_shader_context(bld_base);
1330 LLVMValueRef base, addr;
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1334
1335 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1336 ctx->tess_offchip_ring, base, addr, true);
1337 }
1338
1339 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1340 LLVMTypeRef type,
1341 LLVMValueRef vertex_index,
1342 LLVMValueRef param_index,
1343 unsigned const_index,
1344 unsigned location,
1345 unsigned driver_location,
1346 unsigned component,
1347 unsigned num_components,
1348 bool is_patch,
1349 bool is_compact,
1350 bool load_input)
1351 {
1352 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1353 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1354 LLVMValueRef base, addr;
1355
1356 driver_location = driver_location / 4;
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 unsigned offset = i;
1382 if (llvm_type_is_64bit(ctx, type))
1383 offset *= 2;
1384
1385 value[i] = buffer_load(&ctx->bld_base, type, offset,
1386 ctx->tess_offchip_ring, base, addr, true);
1387 }
1388
1389 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1390 }
1391
1392 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1393 const struct tgsi_full_instruction *inst,
1394 const struct tgsi_opcode_info *info,
1395 unsigned index,
1396 LLVMValueRef dst[4])
1397 {
1398 struct si_shader_context *ctx = si_shader_context(bld_base);
1399 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1400 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1401 unsigned chan_index;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, buf_addr;
1404 LLVMValueRef values[4];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 /* Only handle per-patch and per-vertex outputs here.
1409 * Vectors will be lowered to scalars and this function will be called again.
1410 */
1411 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1412 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1413 si_llvm_emit_store(bld_base, inst, info, index, dst);
1414 return;
1415 }
1416
1417 if (reg->Register.Dimension) {
1418 stride = get_tcs_out_vertex_dw_stride(ctx);
1419 dw_addr = get_tcs_out_current_patch_offset(ctx);
1420 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1421 skip_lds_store = !sh_info->reads_pervertex_outputs;
1422 } else {
1423 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1424 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1425 skip_lds_store = !sh_info->reads_perpatch_outputs;
1426
1427 if (!reg->Register.Indirect) {
1428 int name = sh_info->output_semantic_name[reg->Register.Index];
1429
1430 /* Always write tess factors into LDS for the TCS epilog. */
1431 if (name == TGSI_SEMANTIC_TESSINNER ||
1432 name == TGSI_SEMANTIC_TESSOUTER) {
1433 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1434 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1435 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1436 is_tess_factor = true;
1437 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1438 }
1439 }
1440 }
1441
1442 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1443
1444 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1445 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1446
1447 uint32_t writemask = reg->Register.WriteMask;
1448 while (writemask) {
1449 chan_index = u_bit_scan(&writemask);
1450 LLVMValueRef value = dst[chan_index];
1451
1452 if (inst->Instruction.Saturate)
1453 value = ac_build_clamp(&ctx->ac, value);
1454
1455 /* Skip LDS stores if there is no LDS read of this output. */
1456 if (!skip_lds_store)
1457 lds_store(ctx, chan_index, dw_addr, value);
1458
1459 value = ac_to_integer(&ctx->ac, value);
1460 values[chan_index] = value;
1461
1462 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1463 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1464 buf_addr, base,
1465 4 * chan_index, 1, 0, true, false);
1466 }
1467
1468 /* Write tess factors into VGPRs for the epilog. */
1469 if (is_tess_factor &&
1470 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1471 if (!is_tess_inner) {
1472 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1473 ctx->invoc0_tess_factors[chan_index]);
1474 } else if (chan_index < 2) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1476 ctx->invoc0_tess_factors[4 + chan_index]);
1477 }
1478 }
1479 }
1480
1481 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1482 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1483 values, 4);
1484 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1485 base, 0, 1, 0, true, false);
1486 }
1487 }
1488
1489 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1490 const struct nir_variable *var,
1491 LLVMValueRef vertex_index,
1492 LLVMValueRef param_index,
1493 unsigned const_index,
1494 LLVMValueRef src,
1495 unsigned writemask)
1496 {
1497 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1498 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1499 const unsigned component = var->data.location_frac;
1500 const bool is_patch = var->data.patch;
1501 unsigned driver_location = var->data.driver_location;
1502 LLVMValueRef dw_addr, stride;
1503 LLVMValueRef buffer, base, addr;
1504 LLVMValueRef values[4];
1505 bool skip_lds_store;
1506 bool is_tess_factor = false, is_tess_inner = false;
1507
1508 driver_location = driver_location / 4;
1509
1510 if (param_index) {
1511 /* Add the constant index to the indirect index */
1512 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1513 LLVMConstInt(ctx->i32, const_index, 0), "");
1514 } else {
1515 if (const_index != 0)
1516 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1517 }
1518
1519 if (!is_patch) {
1520 stride = get_tcs_out_vertex_dw_stride(ctx);
1521 dw_addr = get_tcs_out_current_patch_offset(ctx);
1522 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1523 vertex_index, param_index,
1524 driver_location,
1525 info->output_semantic_name,
1526 info->output_semantic_index,
1527 is_patch);
1528
1529 skip_lds_store = !info->reads_pervertex_outputs;
1530 } else {
1531 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1532 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1533 vertex_index, param_index,
1534 driver_location,
1535 info->output_semantic_name,
1536 info->output_semantic_index,
1537 is_patch);
1538
1539 skip_lds_store = !info->reads_perpatch_outputs;
1540
1541 if (!param_index) {
1542 int name = info->output_semantic_name[driver_location];
1543
1544 /* Always write tess factors into LDS for the TCS epilog. */
1545 if (name == TGSI_SEMANTIC_TESSINNER ||
1546 name == TGSI_SEMANTIC_TESSOUTER) {
1547 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1548 skip_lds_store = !info->reads_tessfactor_outputs &&
1549 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1550 is_tess_factor = true;
1551 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1552 }
1553 }
1554 }
1555
1556 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1557
1558 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1559
1560 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1561 param_index, driver_location,
1562 info->output_semantic_name,
1563 info->output_semantic_index,
1564 is_patch);
1565
1566 for (unsigned chan = 0; chan < 4; chan++) {
1567 if (!(writemask & (1 << chan)))
1568 continue;
1569 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1570
1571 /* Skip LDS stores if there is no LDS read of this output. */
1572 if (!skip_lds_store)
1573 lds_store(ctx, chan, dw_addr, value);
1574
1575 value = ac_to_integer(&ctx->ac, value);
1576 values[chan] = value;
1577
1578 if (writemask != 0xF && !is_tess_factor) {
1579 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1580 addr, base,
1581 4 * chan, 1, 0, true, false);
1582 }
1583
1584 /* Write tess factors into VGPRs for the epilog. */
1585 if (is_tess_factor &&
1586 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1587 if (!is_tess_inner) {
1588 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1589 ctx->invoc0_tess_factors[chan]);
1590 } else if (chan < 2) {
1591 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1592 ctx->invoc0_tess_factors[4 + chan]);
1593 }
1594 }
1595 }
1596
1597 if (writemask == 0xF && !is_tess_factor) {
1598 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1599 values, 4);
1600 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1601 base, 0, 1, 0, true, false);
1602 }
1603 }
1604
1605 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1606 unsigned input_index,
1607 unsigned vtx_offset_param,
1608 LLVMTypeRef type,
1609 unsigned swizzle)
1610 {
1611 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1612 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1613 struct si_shader *shader = ctx->shader;
1614 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1615 LLVMValueRef vtx_offset, soffset;
1616 struct tgsi_shader_info *info = &shader->selector->info;
1617 unsigned semantic_name = info->input_semantic_name[input_index];
1618 unsigned semantic_index = info->input_semantic_index[input_index];
1619 unsigned param;
1620 LLVMValueRef value;
1621
1622 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1623
1624 /* GFX9 has the ESGS ring in LDS. */
1625 if (ctx->screen->info.chip_class >= GFX9) {
1626 unsigned index = vtx_offset_param;
1627
1628 switch (index / 2) {
1629 case 0:
1630 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1631 index % 2 ? 16 : 0, 16);
1632 break;
1633 case 1:
1634 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1635 index % 2 ? 16 : 0, 16);
1636 break;
1637 case 2:
1638 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1639 index % 2 ? 16 : 0, 16);
1640 break;
1641 default:
1642 assert(0);
1643 return NULL;
1644 }
1645
1646 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1647 LLVMConstInt(ctx->i32, param * 4, 0), "");
1648 return lds_load(bld_base, type, swizzle, vtx_offset);
1649 }
1650
1651 /* GFX6: input load from the ESGS ring in memory. */
1652 if (swizzle == ~0) {
1653 LLVMValueRef values[TGSI_NUM_CHANNELS];
1654 unsigned chan;
1655 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1656 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1657 type, chan);
1658 }
1659 return lp_build_gather_values(&ctx->gallivm, values,
1660 TGSI_NUM_CHANNELS);
1661 }
1662
1663 /* Get the vertex offset parameter on GFX6. */
1664 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1665
1666 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1667
1668 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1669
1670 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1671 vtx_offset, soffset, 0, 1, 0, true, false);
1672 if (llvm_type_is_64bit(ctx, type)) {
1673 LLVMValueRef value2;
1674 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1675
1676 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1677 ctx->i32_0, vtx_offset, soffset,
1678 0, 1, 0, true, false);
1679 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1680 }
1681 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1682 }
1683
1684 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1685 unsigned location,
1686 unsigned driver_location,
1687 unsigned component,
1688 unsigned num_components,
1689 unsigned vertex_index,
1690 unsigned const_index,
1691 LLVMTypeRef type)
1692 {
1693 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1694
1695 LLVMValueRef value[4];
1696 for (unsigned i = component; i < num_components + component; i++) {
1697 unsigned offset = i;
1698 if (llvm_type_is_64bit(ctx, type))
1699 offset *= 2;
1700
1701 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1702 vertex_index, type, offset);
1703 }
1704
1705 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1706 }
1707
1708 static LLVMValueRef fetch_input_gs(
1709 struct lp_build_tgsi_context *bld_base,
1710 const struct tgsi_full_src_register *reg,
1711 enum tgsi_opcode_type type,
1712 unsigned swizzle)
1713 {
1714 struct si_shader_context *ctx = si_shader_context(bld_base);
1715 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1716
1717 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1718 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1719 return get_primitive_id(ctx, swizzle);
1720
1721 if (!reg->Register.Dimension)
1722 return NULL;
1723
1724 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1725 reg->Dimension.Index,
1726 tgsi2llvmtype(bld_base, type),
1727 swizzle);
1728 }
1729
1730 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1731 {
1732 switch (interpolate) {
1733 case TGSI_INTERPOLATE_CONSTANT:
1734 return 0;
1735
1736 case TGSI_INTERPOLATE_LINEAR:
1737 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1738 return SI_PARAM_LINEAR_SAMPLE;
1739 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1740 return SI_PARAM_LINEAR_CENTROID;
1741 else
1742 return SI_PARAM_LINEAR_CENTER;
1743 break;
1744 case TGSI_INTERPOLATE_COLOR:
1745 case TGSI_INTERPOLATE_PERSPECTIVE:
1746 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1747 return SI_PARAM_PERSP_SAMPLE;
1748 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1749 return SI_PARAM_PERSP_CENTROID;
1750 else
1751 return SI_PARAM_PERSP_CENTER;
1752 break;
1753 default:
1754 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1755 return -1;
1756 }
1757 }
1758
1759 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1760 unsigned attr_index, unsigned chan,
1761 LLVMValueRef prim_mask,
1762 LLVMValueRef i, LLVMValueRef j)
1763 {
1764 if (i || j) {
1765 return ac_build_fs_interp(&ctx->ac,
1766 LLVMConstInt(ctx->i32, chan, 0),
1767 LLVMConstInt(ctx->i32, attr_index, 0),
1768 prim_mask, i, j);
1769 }
1770 return ac_build_fs_interp_mov(&ctx->ac,
1771 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1772 LLVMConstInt(ctx->i32, chan, 0),
1773 LLVMConstInt(ctx->i32, attr_index, 0),
1774 prim_mask);
1775 }
1776
1777 /**
1778 * Interpolate a fragment shader input.
1779 *
1780 * @param ctx context
1781 * @param input_index index of the input in hardware
1782 * @param semantic_name TGSI_SEMANTIC_*
1783 * @param semantic_index semantic index
1784 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1785 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1786 * @param interp_param interpolation weights (i,j)
1787 * @param prim_mask SI_PARAM_PRIM_MASK
1788 * @param face SI_PARAM_FRONT_FACE
1789 * @param result the return value (4 components)
1790 */
1791 static void interp_fs_input(struct si_shader_context *ctx,
1792 unsigned input_index,
1793 unsigned semantic_name,
1794 unsigned semantic_index,
1795 unsigned num_interp_inputs,
1796 unsigned colors_read_mask,
1797 LLVMValueRef interp_param,
1798 LLVMValueRef prim_mask,
1799 LLVMValueRef face,
1800 LLVMValueRef result[4])
1801 {
1802 LLVMValueRef i = NULL, j = NULL;
1803 unsigned chan;
1804
1805 /* fs.constant returns the param from the middle vertex, so it's not
1806 * really useful for flat shading. It's meant to be used for custom
1807 * interpolation (but the intrinsic can't fetch from the other two
1808 * vertices).
1809 *
1810 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1811 * to do the right thing. The only reason we use fs.constant is that
1812 * fs.interp cannot be used on integers, because they can be equal
1813 * to NaN.
1814 *
1815 * When interp is false we will use fs.constant or for newer llvm,
1816 * amdgcn.interp.mov.
1817 */
1818 bool interp = interp_param != NULL;
1819
1820 if (interp) {
1821 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1822 LLVMVectorType(ctx->f32, 2), "");
1823
1824 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1825 ctx->i32_0, "");
1826 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1827 ctx->i32_1, "");
1828 }
1829
1830 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1831 ctx->shader->key.part.ps.prolog.color_two_side) {
1832 LLVMValueRef is_face_positive;
1833
1834 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1835 * otherwise it's at offset "num_inputs".
1836 */
1837 unsigned back_attr_offset = num_interp_inputs;
1838 if (semantic_index == 1 && colors_read_mask & 0xf)
1839 back_attr_offset += 1;
1840
1841 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1842 face, ctx->i32_0, "");
1843
1844 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1845 LLVMValueRef front, back;
1846
1847 front = si_build_fs_interp(ctx,
1848 input_index, chan,
1849 prim_mask, i, j);
1850 back = si_build_fs_interp(ctx,
1851 back_attr_offset, chan,
1852 prim_mask, i, j);
1853
1854 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1855 is_face_positive,
1856 front,
1857 back,
1858 "");
1859 }
1860 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1861 result[0] = si_build_fs_interp(ctx, input_index,
1862 0, prim_mask, i, j);
1863 result[1] =
1864 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1865 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1866 } else {
1867 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1868 result[chan] = si_build_fs_interp(ctx,
1869 input_index, chan,
1870 prim_mask, i, j);
1871 }
1872 }
1873 }
1874
1875 void si_llvm_load_input_fs(
1876 struct si_shader_context *ctx,
1877 unsigned input_index,
1878 LLVMValueRef out[4])
1879 {
1880 struct lp_build_context *base = &ctx->bld_base.base;
1881 struct si_shader *shader = ctx->shader;
1882 struct tgsi_shader_info *info = &shader->selector->info;
1883 LLVMValueRef main_fn = ctx->main_fn;
1884 LLVMValueRef interp_param = NULL;
1885 int interp_param_idx;
1886 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1887 unsigned semantic_index = info->input_semantic_index[input_index];
1888 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1889 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1890
1891 /* Get colors from input VGPRs (set by the prolog). */
1892 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1893 unsigned colors_read = shader->selector->info.colors_read;
1894 unsigned mask = colors_read >> (semantic_index * 4);
1895 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1896 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1897
1898 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1899 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1900 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1901 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1902 return;
1903 }
1904
1905 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1906 if (interp_param_idx == -1)
1907 return;
1908 else if (interp_param_idx) {
1909 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1910 }
1911
1912 interp_fs_input(ctx, input_index, semantic_name,
1913 semantic_index, 0, /* this param is unused */
1914 shader->selector->info.colors_read, interp_param,
1915 ctx->abi.prim_mask,
1916 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1917 &out[0]);
1918 }
1919
1920 static void declare_input_fs(
1921 struct si_shader_context *ctx,
1922 unsigned input_index,
1923 const struct tgsi_full_declaration *decl,
1924 LLVMValueRef out[4])
1925 {
1926 si_llvm_load_input_fs(ctx, input_index, out);
1927 }
1928
1929 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1930 {
1931 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1932 }
1933
1934 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1935 {
1936 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1937
1938 /* For non-indexed draws, the base vertex set by the driver
1939 * (for direct draws) or the CP (for indirect draws) is the
1940 * first vertex ID, but GLSL expects 0 to be returned.
1941 */
1942 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1943 ctx->param_vs_state_bits);
1944 LLVMValueRef indexed;
1945
1946 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1947 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1948
1949 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1950 ctx->i32_0, "");
1951 }
1952
1953 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1954 {
1955 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1956
1957 LLVMValueRef values[3];
1958 LLVMValueRef result;
1959 unsigned i;
1960 unsigned *properties = ctx->shader->selector->info.properties;
1961
1962 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1963 unsigned sizes[3] = {
1964 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1965 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1966 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1967 };
1968
1969 for (i = 0; i < 3; ++i)
1970 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1971
1972 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1973 } else {
1974 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1975 }
1976
1977 return result;
1978 }
1979
1980 /**
1981 * Load a dword from a constant buffer.
1982 */
1983 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1984 LLVMValueRef resource,
1985 LLVMValueRef offset)
1986 {
1987 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1988 0, 0, 0, true, true);
1989 }
1990
1991 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1992 {
1993 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1994 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1995 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1996 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1997 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1998
1999 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2000 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
2001 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
2002
2003 LLVMValueRef pos[4] = {
2004 buffer_load_const(ctx, resource, offset0),
2005 buffer_load_const(ctx, resource, offset1),
2006 LLVMConstReal(ctx->f32, 0),
2007 LLVMConstReal(ctx->f32, 0)
2008 };
2009
2010 return lp_build_gather_values(&ctx->gallivm, pos, 4);
2011 }
2012
2013 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
2014 {
2015 return abi->sample_coverage;
2016 }
2017
2018 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2019 {
2020 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2021 struct lp_build_context *bld = &ctx->bld_base.base;
2022
2023 LLVMValueRef coord[4] = {
2024 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2025 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2026 ctx->ac.f32_0,
2027 ctx->ac.f32_0
2028 };
2029
2030 /* For triangles, the vector should be (u, v, 1-u-v). */
2031 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2032 PIPE_PRIM_TRIANGLES)
2033 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
2034 lp_build_add(bld, coord[0], coord[1]));
2035
2036 return lp_build_gather_values(&ctx->gallivm, coord, 4);
2037 }
2038
2039 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2040 unsigned semantic_name)
2041 {
2042 LLVMValueRef base, addr;
2043
2044 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2045
2046 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2047 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2048 LLVMConstInt(ctx->i32, param, 0));
2049
2050 return buffer_load(&ctx->bld_base, ctx->f32,
2051 ~0, ctx->tess_offchip_ring, base, addr, true);
2052
2053 }
2054
2055 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2056 unsigned varying_id)
2057 {
2058 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2059 unsigned semantic_name;
2060
2061 switch (varying_id) {
2062 case VARYING_SLOT_TESS_LEVEL_INNER:
2063 semantic_name = TGSI_SEMANTIC_TESSINNER;
2064 break;
2065 case VARYING_SLOT_TESS_LEVEL_OUTER:
2066 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2067 break;
2068 default:
2069 unreachable("unknown tess level");
2070 }
2071
2072 return load_tess_level(ctx, semantic_name);
2073
2074 }
2075
2076 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2077 {
2078 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2079 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2080 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2081 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2082 return get_num_tcs_out_vertices(ctx);
2083 else
2084 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2085 }
2086
2087 void si_load_system_value(struct si_shader_context *ctx,
2088 unsigned index,
2089 const struct tgsi_full_declaration *decl)
2090 {
2091 LLVMValueRef value = 0;
2092
2093 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2094
2095 switch (decl->Semantic.Name) {
2096 case TGSI_SEMANTIC_INSTANCEID:
2097 value = ctx->abi.instance_id;
2098 break;
2099
2100 case TGSI_SEMANTIC_VERTEXID:
2101 value = LLVMBuildAdd(ctx->ac.builder,
2102 ctx->abi.vertex_id,
2103 ctx->abi.base_vertex, "");
2104 break;
2105
2106 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2107 /* Unused. Clarify the meaning in indexed vs. non-indexed
2108 * draws if this is ever used again. */
2109 assert(false);
2110 break;
2111
2112 case TGSI_SEMANTIC_BASEVERTEX:
2113 value = get_base_vertex(&ctx->abi);
2114 break;
2115
2116 case TGSI_SEMANTIC_BASEINSTANCE:
2117 value = ctx->abi.start_instance;
2118 break;
2119
2120 case TGSI_SEMANTIC_DRAWID:
2121 value = ctx->abi.draw_id;
2122 break;
2123
2124 case TGSI_SEMANTIC_INVOCATIONID:
2125 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2126 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2127 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2128 value = ctx->abi.gs_invocation_id;
2129 else
2130 assert(!"INVOCATIONID not implemented");
2131 break;
2132
2133 case TGSI_SEMANTIC_POSITION:
2134 {
2135 LLVMValueRef pos[4] = {
2136 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2137 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2138 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2139 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2140 LLVMGetParam(ctx->main_fn,
2141 SI_PARAM_POS_W_FLOAT)),
2142 };
2143 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2144 break;
2145 }
2146
2147 case TGSI_SEMANTIC_FACE:
2148 value = ctx->abi.front_face;
2149 break;
2150
2151 case TGSI_SEMANTIC_SAMPLEID:
2152 value = get_sample_id(ctx);
2153 break;
2154
2155 case TGSI_SEMANTIC_SAMPLEPOS: {
2156 LLVMValueRef pos[4] = {
2157 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2158 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2159 LLVMConstReal(ctx->f32, 0),
2160 LLVMConstReal(ctx->f32, 0)
2161 };
2162 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2163 TGSI_OPCODE_FRC, pos[0]);
2164 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2165 TGSI_OPCODE_FRC, pos[1]);
2166 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2167 break;
2168 }
2169
2170 case TGSI_SEMANTIC_SAMPLEMASK:
2171 /* This can only occur with the OpenGL Core profile, which
2172 * doesn't support smoothing.
2173 */
2174 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2175 break;
2176
2177 case TGSI_SEMANTIC_TESSCOORD:
2178 value = si_load_tess_coord(&ctx->abi);
2179 break;
2180
2181 case TGSI_SEMANTIC_VERTICESIN:
2182 value = si_load_patch_vertices_in(&ctx->abi);
2183 break;
2184
2185 case TGSI_SEMANTIC_TESSINNER:
2186 case TGSI_SEMANTIC_TESSOUTER:
2187 value = load_tess_level(ctx, decl->Semantic.Name);
2188 break;
2189
2190 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2191 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2192 {
2193 LLVMValueRef buf, slot, val[4];
2194 int i, offset;
2195
2196 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2197 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2198 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2199 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2200
2201 for (i = 0; i < 4; i++)
2202 val[i] = buffer_load_const(ctx, buf,
2203 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2204 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2205 break;
2206 }
2207
2208 case TGSI_SEMANTIC_PRIMID:
2209 value = get_primitive_id(ctx, 0);
2210 break;
2211
2212 case TGSI_SEMANTIC_GRID_SIZE:
2213 value = ctx->abi.num_work_groups;
2214 break;
2215
2216 case TGSI_SEMANTIC_BLOCK_SIZE:
2217 value = get_block_size(&ctx->abi);
2218 break;
2219
2220 case TGSI_SEMANTIC_BLOCK_ID:
2221 {
2222 LLVMValueRef values[3];
2223
2224 for (int i = 0; i < 3; i++) {
2225 values[i] = ctx->i32_0;
2226 if (ctx->abi.workgroup_ids[i]) {
2227 values[i] = ctx->abi.workgroup_ids[i];
2228 }
2229 }
2230 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2231 break;
2232 }
2233
2234 case TGSI_SEMANTIC_THREAD_ID:
2235 value = ctx->abi.local_invocation_ids;
2236 break;
2237
2238 case TGSI_SEMANTIC_HELPER_INVOCATION:
2239 value = lp_build_intrinsic(ctx->ac.builder,
2240 "llvm.amdgcn.ps.live",
2241 ctx->i1, NULL, 0,
2242 LP_FUNC_ATTR_READNONE);
2243 value = LLVMBuildNot(ctx->ac.builder, value, "");
2244 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2245 break;
2246
2247 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2248 value = LLVMConstInt(ctx->i32, 64, 0);
2249 break;
2250
2251 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2252 value = ac_get_thread_id(&ctx->ac);
2253 break;
2254
2255 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2256 {
2257 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2258 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2259 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2260 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2261 break;
2262 }
2263
2264 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2265 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2266 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2267 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2268 {
2269 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2270 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2271 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2272 /* All bits set except LSB */
2273 value = LLVMConstInt(ctx->i64, -2, 0);
2274 } else {
2275 /* All bits set */
2276 value = LLVMConstInt(ctx->i64, -1, 0);
2277 }
2278 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2279 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2280 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2281 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2282 value = LLVMBuildNot(ctx->ac.builder, value, "");
2283 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2284 break;
2285 }
2286
2287 default:
2288 assert(!"unknown system value");
2289 return;
2290 }
2291
2292 ctx->system_values[index] = value;
2293 }
2294
2295 void si_declare_compute_memory(struct si_shader_context *ctx)
2296 {
2297 struct si_shader_selector *sel = ctx->shader->selector;
2298
2299 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2300 LLVMValueRef var;
2301
2302 assert(!ctx->ac.lds);
2303
2304 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2305 LLVMArrayType(ctx->i8, sel->local_size),
2306 "compute_lds",
2307 AC_LOCAL_ADDR_SPACE);
2308 LLVMSetAlignment(var, 4);
2309
2310 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2311 }
2312
2313 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2314 const struct tgsi_full_declaration *decl)
2315 {
2316 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2317 assert(decl->Range.First == decl->Range.Last);
2318
2319 si_declare_compute_memory(ctx);
2320 }
2321
2322 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2323 {
2324 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2325 ctx->param_const_and_shader_buffers);
2326
2327 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2328 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2329 }
2330
2331 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2332 {
2333 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2334 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2335
2336 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2337 index = LLVMBuildAdd(ctx->ac.builder, index,
2338 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2339
2340 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2341 }
2342
2343 static LLVMValueRef
2344 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2345 {
2346 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2347 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2348 ctx->param_const_and_shader_buffers);
2349
2350 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2351 index = LLVMBuildSub(ctx->ac.builder,
2352 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2353 index, "");
2354
2355 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2356 }
2357
2358 static LLVMValueRef fetch_constant(
2359 struct lp_build_tgsi_context *bld_base,
2360 const struct tgsi_full_src_register *reg,
2361 enum tgsi_opcode_type type,
2362 unsigned swizzle)
2363 {
2364 struct si_shader_context *ctx = si_shader_context(bld_base);
2365 struct si_shader_selector *sel = ctx->shader->selector;
2366 const struct tgsi_ind_register *ireg = &reg->Indirect;
2367 unsigned buf, idx;
2368
2369 LLVMValueRef addr, bufp;
2370
2371 if (swizzle == LP_CHAN_ALL) {
2372 unsigned chan;
2373 LLVMValueRef values[4];
2374 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2375 values[chan] = fetch_constant(bld_base, reg, type, chan);
2376
2377 return lp_build_gather_values(&ctx->gallivm, values, 4);
2378 }
2379
2380 /* Split 64-bit loads. */
2381 if (tgsi_type_is_64bit(type)) {
2382 LLVMValueRef lo, hi;
2383
2384 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2385 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2386 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2387 lo, hi);
2388 }
2389
2390 idx = reg->Register.Index * 4 + swizzle;
2391 if (reg->Register.Indirect) {
2392 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2393 } else {
2394 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2395 }
2396
2397 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2398 if (sel->info.const_buffers_declared == 1 &&
2399 sel->info.shader_buffers_declared == 0) {
2400 LLVMValueRef ptr =
2401 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2402
2403 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2404 * loads, and up to x4 load opcode merging. However, it leads to horrible
2405 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2406 *
2407 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2408 *
2409 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2410 * a descriptor and s_buffer_load_dword using it, so we can't expand
2411 * the pointer into a full descriptor like below. We have to use
2412 * s_load_dword instead. The only case when LLVM 5.0 would select
2413 * s_buffer_load_dword (that we have to prevent) is when we use use
2414 * a literal offset where we don't need bounds checking.
2415 */
2416 if (ctx->screen->info.chip_class == SI &&
2417 HAVE_LLVM < 0x0600 &&
2418 !reg->Register.Indirect) {
2419 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2420 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2421 return bitcast(bld_base, type, result);
2422 }
2423
2424 /* Do the bounds checking with a descriptor, because
2425 * doing computation and manual bounds checking of 64-bit
2426 * addresses generates horrible VALU code with very high
2427 * VGPR usage and very low SIMD occupancy.
2428 */
2429 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2430
2431 LLVMValueRef desc0, desc1;
2432 if (HAVE_32BIT_POINTERS) {
2433 desc0 = ptr;
2434 desc1 = LLVMConstInt(ctx->i32,
2435 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2436 } else {
2437 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2438 desc0 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, "");
2439 desc1 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, "");
2440 /* Mask out all bits except BASE_ADDRESS_HI. */
2441 desc1 = LLVMBuildAnd(ctx->ac.builder, desc1,
2442 LLVMConstInt(ctx->i32, ~C_008F04_BASE_ADDRESS_HI, 0), "");
2443 }
2444
2445 LLVMValueRef desc_elems[] = {
2446 desc0,
2447 desc1,
2448 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2449 LLVMConstInt(ctx->i32,
2450 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2451 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2452 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2453 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2454 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2455 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2456 };
2457 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2458 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2459 return bitcast(bld_base, type, result);
2460 }
2461
2462 assert(reg->Register.Dimension);
2463 buf = reg->Dimension.Index;
2464
2465 if (reg->Dimension.Indirect) {
2466 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2467 LLVMValueRef index;
2468 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2469 reg->Dimension.Index,
2470 ctx->num_const_buffers);
2471 index = LLVMBuildAdd(ctx->ac.builder, index,
2472 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2473 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2474 } else
2475 bufp = load_const_buffer_desc(ctx, buf);
2476
2477 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2478 }
2479
2480 /* Initialize arguments for the shader export intrinsic */
2481 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2482 LLVMValueRef *values,
2483 unsigned target,
2484 struct ac_export_args *args)
2485 {
2486 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2487 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2488 unsigned chan;
2489 bool is_int8, is_int10;
2490
2491 /* Default is 0xf. Adjusted below depending on the format. */
2492 args->enabled_channels = 0xf; /* writemask */
2493
2494 /* Specify whether the EXEC mask represents the valid mask */
2495 args->valid_mask = 0;
2496
2497 /* Specify whether this is the last export */
2498 args->done = 0;
2499
2500 /* Specify the target we are exporting */
2501 args->target = target;
2502
2503 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2504 const struct si_shader_key *key = &ctx->shader->key;
2505 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2506 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2507
2508 assert(cbuf >= 0 && cbuf < 8);
2509 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2510 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2511 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2512 }
2513
2514 args->compr = false;
2515 args->out[0] = f32undef;
2516 args->out[1] = f32undef;
2517 args->out[2] = f32undef;
2518 args->out[3] = f32undef;
2519
2520 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2521 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2522 unsigned bits, bool hi) = NULL;
2523
2524 switch (spi_shader_col_format) {
2525 case V_028714_SPI_SHADER_ZERO:
2526 args->enabled_channels = 0; /* writemask */
2527 args->target = V_008DFC_SQ_EXP_NULL;
2528 break;
2529
2530 case V_028714_SPI_SHADER_32_R:
2531 args->enabled_channels = 1; /* writemask */
2532 args->out[0] = values[0];
2533 break;
2534
2535 case V_028714_SPI_SHADER_32_GR:
2536 args->enabled_channels = 0x3; /* writemask */
2537 args->out[0] = values[0];
2538 args->out[1] = values[1];
2539 break;
2540
2541 case V_028714_SPI_SHADER_32_AR:
2542 args->enabled_channels = 0x9; /* writemask */
2543 args->out[0] = values[0];
2544 args->out[3] = values[3];
2545 break;
2546
2547 case V_028714_SPI_SHADER_FP16_ABGR:
2548 packf = ac_build_cvt_pkrtz_f16;
2549 break;
2550
2551 case V_028714_SPI_SHADER_UNORM16_ABGR:
2552 packf = ac_build_cvt_pknorm_u16;
2553 break;
2554
2555 case V_028714_SPI_SHADER_SNORM16_ABGR:
2556 packf = ac_build_cvt_pknorm_i16;
2557 break;
2558
2559 case V_028714_SPI_SHADER_UINT16_ABGR:
2560 packi = ac_build_cvt_pk_u16;
2561 break;
2562
2563 case V_028714_SPI_SHADER_SINT16_ABGR:
2564 packi = ac_build_cvt_pk_i16;
2565 break;
2566
2567 case V_028714_SPI_SHADER_32_ABGR:
2568 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2569 break;
2570 }
2571
2572 /* Pack f16 or norm_i16/u16. */
2573 if (packf) {
2574 for (chan = 0; chan < 2; chan++) {
2575 LLVMValueRef pack_args[2] = {
2576 values[2 * chan],
2577 values[2 * chan + 1]
2578 };
2579 LLVMValueRef packed;
2580
2581 packed = packf(&ctx->ac, pack_args);
2582 args->out[chan] = ac_to_float(&ctx->ac, packed);
2583 }
2584 args->compr = 1; /* COMPR flag */
2585 }
2586 /* Pack i16/u16. */
2587 if (packi) {
2588 for (chan = 0; chan < 2; chan++) {
2589 LLVMValueRef pack_args[2] = {
2590 ac_to_integer(&ctx->ac, values[2 * chan]),
2591 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2592 };
2593 LLVMValueRef packed;
2594
2595 packed = packi(&ctx->ac, pack_args,
2596 is_int8 ? 8 : is_int10 ? 10 : 16,
2597 chan == 1);
2598 args->out[chan] = ac_to_float(&ctx->ac, packed);
2599 }
2600 args->compr = 1; /* COMPR flag */
2601 }
2602 }
2603
2604 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2605 LLVMValueRef alpha)
2606 {
2607 struct si_shader_context *ctx = si_shader_context(bld_base);
2608
2609 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2610 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2611 [PIPE_FUNC_LESS] = LLVMRealOLT,
2612 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2613 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2614 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2615 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2616 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2617 };
2618 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2619 assert(cond);
2620
2621 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2622 SI_PARAM_ALPHA_REF);
2623 LLVMValueRef alpha_pass =
2624 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2625 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2626 } else {
2627 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2628 }
2629 }
2630
2631 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2632 LLVMValueRef alpha,
2633 unsigned samplemask_param)
2634 {
2635 struct si_shader_context *ctx = si_shader_context(bld_base);
2636 LLVMValueRef coverage;
2637
2638 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2639 coverage = LLVMGetParam(ctx->main_fn,
2640 samplemask_param);
2641 coverage = ac_to_integer(&ctx->ac, coverage);
2642
2643 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2644 ctx->i32,
2645 &coverage, 1, LP_FUNC_ATTR_READNONE);
2646
2647 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2648 ctx->f32, "");
2649
2650 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2651 LLVMConstReal(ctx->f32,
2652 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2653
2654 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2655 }
2656
2657 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2658 struct ac_export_args *pos, LLVMValueRef *out_elts)
2659 {
2660 unsigned reg_index;
2661 unsigned chan;
2662 unsigned const_chan;
2663 LLVMValueRef base_elt;
2664 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2665 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2666 SI_VS_CONST_CLIP_PLANES, 0);
2667 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2668
2669 for (reg_index = 0; reg_index < 2; reg_index ++) {
2670 struct ac_export_args *args = &pos[2 + reg_index];
2671
2672 args->out[0] =
2673 args->out[1] =
2674 args->out[2] =
2675 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2676
2677 /* Compute dot products of position and user clip plane vectors */
2678 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2679 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2680 LLVMValueRef addr =
2681 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2682 const_chan) * 4, 0);
2683 base_elt = buffer_load_const(ctx, const_resource,
2684 addr);
2685 args->out[chan] =
2686 lp_build_add(&ctx->bld_base.base, args->out[chan],
2687 lp_build_mul(&ctx->bld_base.base, base_elt,
2688 out_elts[const_chan]));
2689 }
2690 }
2691
2692 args->enabled_channels = 0xf;
2693 args->valid_mask = 0;
2694 args->done = 0;
2695 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2696 args->compr = 0;
2697 }
2698 }
2699
2700 static void si_dump_streamout(struct pipe_stream_output_info *so)
2701 {
2702 unsigned i;
2703
2704 if (so->num_outputs)
2705 fprintf(stderr, "STREAMOUT\n");
2706
2707 for (i = 0; i < so->num_outputs; i++) {
2708 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2709 so->output[i].start_component;
2710 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2711 i, so->output[i].output_buffer,
2712 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2713 so->output[i].register_index,
2714 mask & 1 ? "x" : "",
2715 mask & 2 ? "y" : "",
2716 mask & 4 ? "z" : "",
2717 mask & 8 ? "w" : "");
2718 }
2719 }
2720
2721 static void emit_streamout_output(struct si_shader_context *ctx,
2722 LLVMValueRef const *so_buffers,
2723 LLVMValueRef const *so_write_offsets,
2724 struct pipe_stream_output *stream_out,
2725 struct si_shader_output_values *shader_out)
2726 {
2727 unsigned buf_idx = stream_out->output_buffer;
2728 unsigned start = stream_out->start_component;
2729 unsigned num_comps = stream_out->num_components;
2730 LLVMValueRef out[4];
2731
2732 assert(num_comps && num_comps <= 4);
2733 if (!num_comps || num_comps > 4)
2734 return;
2735
2736 /* Load the output as int. */
2737 for (int j = 0; j < num_comps; j++) {
2738 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2739
2740 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2741 }
2742
2743 /* Pack the output. */
2744 LLVMValueRef vdata = NULL;
2745
2746 switch (num_comps) {
2747 case 1: /* as i32 */
2748 vdata = out[0];
2749 break;
2750 case 2: /* as v2i32 */
2751 case 3: /* as v4i32 (aligned to 4) */
2752 case 4: /* as v4i32 */
2753 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2754 for (int j = 0; j < num_comps; j++) {
2755 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2756 LLVMConstInt(ctx->i32, j, 0), "");
2757 }
2758 break;
2759 }
2760
2761 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2762 vdata, num_comps,
2763 so_write_offsets[buf_idx],
2764 ctx->i32_0,
2765 stream_out->dst_offset * 4, 1, 1, true, false);
2766 }
2767
2768 /**
2769 * Write streamout data to buffers for vertex stream @p stream (different
2770 * vertex streams can occur for GS copy shaders).
2771 */
2772 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2773 struct si_shader_output_values *outputs,
2774 unsigned noutput, unsigned stream)
2775 {
2776 struct si_shader_selector *sel = ctx->shader->selector;
2777 struct pipe_stream_output_info *so = &sel->so;
2778 LLVMBuilderRef builder = ctx->ac.builder;
2779 int i;
2780 struct lp_build_if_state if_ctx;
2781
2782 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2783 LLVMValueRef so_vtx_count =
2784 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2785
2786 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2787
2788 /* can_emit = tid < so_vtx_count; */
2789 LLVMValueRef can_emit =
2790 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2791
2792 /* Emit the streamout code conditionally. This actually avoids
2793 * out-of-bounds buffer access. The hw tells us via the SGPR
2794 * (so_vtx_count) which threads are allowed to emit streamout data. */
2795 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2796 {
2797 /* The buffer offset is computed as follows:
2798 * ByteOffset = streamout_offset[buffer_id]*4 +
2799 * (streamout_write_index + thread_id)*stride[buffer_id] +
2800 * attrib_offset
2801 */
2802
2803 LLVMValueRef so_write_index =
2804 LLVMGetParam(ctx->main_fn,
2805 ctx->param_streamout_write_index);
2806
2807 /* Compute (streamout_write_index + thread_id). */
2808 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2809
2810 /* Load the descriptor and compute the write offset for each
2811 * enabled buffer. */
2812 LLVMValueRef so_write_offset[4] = {};
2813 LLVMValueRef so_buffers[4];
2814 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2815 ctx->param_rw_buffers);
2816
2817 for (i = 0; i < 4; i++) {
2818 if (!so->stride[i])
2819 continue;
2820
2821 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2822 SI_VS_STREAMOUT_BUF0 + i, 0);
2823
2824 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2825
2826 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2827 ctx->param_streamout_offset[i]);
2828 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2829
2830 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2831 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2832 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2833 }
2834
2835 /* Write streamout data. */
2836 for (i = 0; i < so->num_outputs; i++) {
2837 unsigned reg = so->output[i].register_index;
2838
2839 if (reg >= noutput)
2840 continue;
2841
2842 if (stream != so->output[i].stream)
2843 continue;
2844
2845 emit_streamout_output(ctx, so_buffers, so_write_offset,
2846 &so->output[i], &outputs[reg]);
2847 }
2848 }
2849 lp_build_endif(&if_ctx);
2850 }
2851
2852 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2853 LLVMValueRef *values)
2854 {
2855 struct ac_export_args args;
2856
2857 si_llvm_init_export_args(ctx, values,
2858 V_008DFC_SQ_EXP_PARAM + index, &args);
2859 ac_build_export(&ctx->ac, &args);
2860 }
2861
2862 static void si_build_param_exports(struct si_shader_context *ctx,
2863 struct si_shader_output_values *outputs,
2864 unsigned noutput)
2865 {
2866 struct si_shader *shader = ctx->shader;
2867 unsigned param_count = 0;
2868
2869 for (unsigned i = 0; i < noutput; i++) {
2870 unsigned semantic_name = outputs[i].semantic_name;
2871 unsigned semantic_index = outputs[i].semantic_index;
2872
2873 if (outputs[i].vertex_stream[0] != 0 &&
2874 outputs[i].vertex_stream[1] != 0 &&
2875 outputs[i].vertex_stream[2] != 0 &&
2876 outputs[i].vertex_stream[3] != 0)
2877 continue;
2878
2879 switch (semantic_name) {
2880 case TGSI_SEMANTIC_LAYER:
2881 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2882 case TGSI_SEMANTIC_CLIPDIST:
2883 case TGSI_SEMANTIC_COLOR:
2884 case TGSI_SEMANTIC_BCOLOR:
2885 case TGSI_SEMANTIC_PRIMID:
2886 case TGSI_SEMANTIC_FOG:
2887 case TGSI_SEMANTIC_TEXCOORD:
2888 case TGSI_SEMANTIC_GENERIC:
2889 break;
2890 default:
2891 continue;
2892 }
2893
2894 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2895 semantic_index < SI_MAX_IO_GENERIC) &&
2896 shader->key.opt.kill_outputs &
2897 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2898 continue;
2899
2900 si_export_param(ctx, param_count, outputs[i].values);
2901
2902 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2903 shader->info.vs_output_param_offset[i] = param_count++;
2904 }
2905
2906 shader->info.nr_param_exports = param_count;
2907 }
2908
2909 /* Generate export instructions for hardware VS shader stage */
2910 static void si_llvm_export_vs(struct si_shader_context *ctx,
2911 struct si_shader_output_values *outputs,
2912 unsigned noutput)
2913 {
2914 struct si_shader *shader = ctx->shader;
2915 struct ac_export_args pos_args[4] = {};
2916 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2917 unsigned pos_idx;
2918 int i;
2919
2920 /* Build position exports. */
2921 for (i = 0; i < noutput; i++) {
2922 switch (outputs[i].semantic_name) {
2923 case TGSI_SEMANTIC_POSITION:
2924 si_llvm_init_export_args(ctx, outputs[i].values,
2925 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2926 break;
2927 case TGSI_SEMANTIC_PSIZE:
2928 psize_value = outputs[i].values[0];
2929 break;
2930 case TGSI_SEMANTIC_LAYER:
2931 layer_value = outputs[i].values[0];
2932 break;
2933 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2934 viewport_index_value = outputs[i].values[0];
2935 break;
2936 case TGSI_SEMANTIC_EDGEFLAG:
2937 edgeflag_value = outputs[i].values[0];
2938 break;
2939 case TGSI_SEMANTIC_CLIPDIST:
2940 if (!shader->key.opt.clip_disable) {
2941 unsigned index = 2 + outputs[i].semantic_index;
2942 si_llvm_init_export_args(ctx, outputs[i].values,
2943 V_008DFC_SQ_EXP_POS + index,
2944 &pos_args[index]);
2945 }
2946 break;
2947 case TGSI_SEMANTIC_CLIPVERTEX:
2948 if (!shader->key.opt.clip_disable) {
2949 si_llvm_emit_clipvertex(ctx, pos_args,
2950 outputs[i].values);
2951 }
2952 break;
2953 }
2954 }
2955
2956 /* We need to add the position output manually if it's missing. */
2957 if (!pos_args[0].out[0]) {
2958 pos_args[0].enabled_channels = 0xf; /* writemask */
2959 pos_args[0].valid_mask = 0; /* EXEC mask */
2960 pos_args[0].done = 0; /* last export? */
2961 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2962 pos_args[0].compr = 0; /* COMPR flag */
2963 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2964 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2965 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2966 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2967 }
2968
2969 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2970 if (shader->selector->info.writes_psize ||
2971 shader->selector->info.writes_edgeflag ||
2972 shader->selector->info.writes_viewport_index ||
2973 shader->selector->info.writes_layer) {
2974 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2975 (shader->selector->info.writes_edgeflag << 1) |
2976 (shader->selector->info.writes_layer << 2);
2977
2978 pos_args[1].valid_mask = 0; /* EXEC mask */
2979 pos_args[1].done = 0; /* last export? */
2980 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2981 pos_args[1].compr = 0; /* COMPR flag */
2982 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2983 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2984 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2985 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2986
2987 if (shader->selector->info.writes_psize)
2988 pos_args[1].out[0] = psize_value;
2989
2990 if (shader->selector->info.writes_edgeflag) {
2991 /* The output is a float, but the hw expects an integer
2992 * with the first bit containing the edge flag. */
2993 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2994 edgeflag_value,
2995 ctx->i32, "");
2996 edgeflag_value = ac_build_umin(&ctx->ac,
2997 edgeflag_value,
2998 ctx->i32_1);
2999
3000 /* The LLVM intrinsic expects a float. */
3001 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3002 }
3003
3004 if (ctx->screen->info.chip_class >= GFX9) {
3005 /* GFX9 has the layer in out.z[10:0] and the viewport
3006 * index in out.z[19:16].
3007 */
3008 if (shader->selector->info.writes_layer)
3009 pos_args[1].out[2] = layer_value;
3010
3011 if (shader->selector->info.writes_viewport_index) {
3012 LLVMValueRef v = viewport_index_value;
3013
3014 v = ac_to_integer(&ctx->ac, v);
3015 v = LLVMBuildShl(ctx->ac.builder, v,
3016 LLVMConstInt(ctx->i32, 16, 0), "");
3017 v = LLVMBuildOr(ctx->ac.builder, v,
3018 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3019 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3020 pos_args[1].enabled_channels |= 1 << 2;
3021 }
3022 } else {
3023 if (shader->selector->info.writes_layer)
3024 pos_args[1].out[2] = layer_value;
3025
3026 if (shader->selector->info.writes_viewport_index) {
3027 pos_args[1].out[3] = viewport_index_value;
3028 pos_args[1].enabled_channels |= 1 << 3;
3029 }
3030 }
3031 }
3032
3033 for (i = 0; i < 4; i++)
3034 if (pos_args[i].out[0])
3035 shader->info.nr_pos_exports++;
3036
3037 pos_idx = 0;
3038 for (i = 0; i < 4; i++) {
3039 if (!pos_args[i].out[0])
3040 continue;
3041
3042 /* Specify the target we are exporting */
3043 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3044
3045 if (pos_idx == shader->info.nr_pos_exports)
3046 /* Specify that this is the last export */
3047 pos_args[i].done = 1;
3048
3049 ac_build_export(&ctx->ac, &pos_args[i]);
3050 }
3051
3052 /* Build parameter exports. */
3053 si_build_param_exports(ctx, outputs, noutput);
3054 }
3055
3056 /**
3057 * Forward all outputs from the vertex shader to the TES. This is only used
3058 * for the fixed function TCS.
3059 */
3060 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3061 {
3062 struct si_shader_context *ctx = si_shader_context(bld_base);
3063 LLVMValueRef invocation_id, buffer, buffer_offset;
3064 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3065 uint64_t inputs;
3066
3067 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3068 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3069 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3070
3071 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3072 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3073 lds_vertex_stride, "");
3074 lds_base = get_tcs_in_current_patch_offset(ctx);
3075 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3076
3077 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3078 while (inputs) {
3079 unsigned i = u_bit_scan64(&inputs);
3080
3081 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3082 LLVMConstInt(ctx->i32, 4 * i, 0),
3083 "");
3084
3085 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3086 get_rel_patch_id(ctx),
3087 invocation_id,
3088 LLVMConstInt(ctx->i32, i, 0));
3089
3090 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3091 lds_ptr);
3092
3093 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3094 buffer_offset, 0, 1, 0, true, false);
3095 }
3096 }
3097
3098 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3099 LLVMValueRef rel_patch_id,
3100 LLVMValueRef invocation_id,
3101 LLVMValueRef tcs_out_current_patch_data_offset,
3102 LLVMValueRef invoc0_tf_outer[4],
3103 LLVMValueRef invoc0_tf_inner[2])
3104 {
3105 struct si_shader_context *ctx = si_shader_context(bld_base);
3106 struct si_shader *shader = ctx->shader;
3107 unsigned tess_inner_index, tess_outer_index;
3108 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3109 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3110 unsigned stride, outer_comps, inner_comps, i, offset;
3111 struct lp_build_if_state if_ctx, inner_if_ctx;
3112
3113 /* Add a barrier before loading tess factors from LDS. */
3114 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3115 si_llvm_emit_barrier(NULL, bld_base, NULL);
3116
3117 /* Do this only for invocation 0, because the tess levels are per-patch,
3118 * not per-vertex.
3119 *
3120 * This can't jump, because invocation 0 executes this. It should
3121 * at least mask out the loads and stores for other invocations.
3122 */
3123 lp_build_if(&if_ctx, &ctx->gallivm,
3124 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3125 invocation_id, ctx->i32_0, ""));
3126
3127 /* Determine the layout of one tess factor element in the buffer. */
3128 switch (shader->key.part.tcs.epilog.prim_mode) {
3129 case PIPE_PRIM_LINES:
3130 stride = 2; /* 2 dwords, 1 vec2 store */
3131 outer_comps = 2;
3132 inner_comps = 0;
3133 break;
3134 case PIPE_PRIM_TRIANGLES:
3135 stride = 4; /* 4 dwords, 1 vec4 store */
3136 outer_comps = 3;
3137 inner_comps = 1;
3138 break;
3139 case PIPE_PRIM_QUADS:
3140 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3141 outer_comps = 4;
3142 inner_comps = 2;
3143 break;
3144 default:
3145 assert(0);
3146 return;
3147 }
3148
3149 for (i = 0; i < 4; i++) {
3150 inner[i] = LLVMGetUndef(ctx->i32);
3151 outer[i] = LLVMGetUndef(ctx->i32);
3152 }
3153
3154 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3155 /* Tess factors are in VGPRs. */
3156 for (i = 0; i < outer_comps; i++)
3157 outer[i] = out[i] = invoc0_tf_outer[i];
3158 for (i = 0; i < inner_comps; i++)
3159 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3160 } else {
3161 /* Load tess_inner and tess_outer from LDS.
3162 * Any invocation can write them, so we can't get them from a temporary.
3163 */
3164 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3165 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3166
3167 lds_base = tcs_out_current_patch_data_offset;
3168 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3169 LLVMConstInt(ctx->i32,
3170 tess_inner_index * 4, 0), "");
3171 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3172 LLVMConstInt(ctx->i32,
3173 tess_outer_index * 4, 0), "");
3174
3175 for (i = 0; i < outer_comps; i++) {
3176 outer[i] = out[i] =
3177 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3178 }
3179 for (i = 0; i < inner_comps; i++) {
3180 inner[i] = out[outer_comps+i] =
3181 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3182 }
3183 }
3184
3185 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3186 /* For isolines, the hardware expects tess factors in the
3187 * reverse order from what GLSL / TGSI specify.
3188 */
3189 LLVMValueRef tmp = out[0];
3190 out[0] = out[1];
3191 out[1] = tmp;
3192 }
3193
3194 /* Convert the outputs to vectors for stores. */
3195 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3196 vec1 = NULL;
3197
3198 if (stride > 4)
3199 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3200
3201 /* Get the buffer. */
3202 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3203
3204 /* Get the offset. */
3205 tf_base = LLVMGetParam(ctx->main_fn,
3206 ctx->param_tcs_factor_offset);
3207 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3208 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3209
3210 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3211 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3212 rel_patch_id, ctx->i32_0, ""));
3213
3214 /* Store the dynamic HS control word. */
3215 offset = 0;
3216 if (ctx->screen->info.chip_class <= VI) {
3217 ac_build_buffer_store_dword(&ctx->ac, buffer,
3218 LLVMConstInt(ctx->i32, 0x80000000, 0),
3219 1, ctx->i32_0, tf_base,
3220 offset, 1, 0, true, false);
3221 offset += 4;
3222 }
3223
3224 lp_build_endif(&inner_if_ctx);
3225
3226 /* Store the tessellation factors. */
3227 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3228 MIN2(stride, 4), byteoffset, tf_base,
3229 offset, 1, 0, true, false);
3230 offset += 16;
3231 if (vec1)
3232 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3233 stride - 4, byteoffset, tf_base,
3234 offset, 1, 0, true, false);
3235
3236 /* Store the tess factors into the offchip buffer if TES reads them. */
3237 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3238 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3239 LLVMValueRef tf_inner_offset;
3240 unsigned param_outer, param_inner;
3241
3242 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3243 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3244
3245 param_outer = si_shader_io_get_unique_index_patch(
3246 TGSI_SEMANTIC_TESSOUTER, 0);
3247 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3248 LLVMConstInt(ctx->i32, param_outer, 0));
3249
3250 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3251 util_next_power_of_two(outer_comps));
3252
3253 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3254 outer_comps, tf_outer_offset,
3255 base, 0, 1, 0, true, false);
3256 if (inner_comps) {
3257 param_inner = si_shader_io_get_unique_index_patch(
3258 TGSI_SEMANTIC_TESSINNER, 0);
3259 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3260 LLVMConstInt(ctx->i32, param_inner, 0));
3261
3262 inner_vec = inner_comps == 1 ? inner[0] :
3263 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3264 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3265 inner_comps, tf_inner_offset,
3266 base, 0, 1, 0, true, false);
3267 }
3268 }
3269
3270 lp_build_endif(&if_ctx);
3271 }
3272
3273 static LLVMValueRef
3274 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3275 unsigned param, unsigned return_index)
3276 {
3277 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3278 LLVMGetParam(ctx->main_fn, param),
3279 return_index, "");
3280 }
3281
3282 static LLVMValueRef
3283 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3284 unsigned param, unsigned return_index)
3285 {
3286 LLVMBuilderRef builder = ctx->ac.builder;
3287 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3288
3289 return LLVMBuildInsertValue(builder, ret,
3290 ac_to_float(&ctx->ac, p),
3291 return_index, "");
3292 }
3293
3294 static LLVMValueRef
3295 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3296 unsigned param, unsigned return_index)
3297 {
3298 LLVMBuilderRef builder = ctx->ac.builder;
3299 LLVMValueRef ptr, lo, hi;
3300
3301 if (HAVE_32BIT_POINTERS) {
3302 ptr = LLVMGetParam(ctx->main_fn, param);
3303 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3304 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3305 }
3306
3307 ptr = LLVMGetParam(ctx->main_fn, param);
3308 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3309 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3310 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3311 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3312 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3313 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3314 }
3315
3316 /* This only writes the tessellation factor levels. */
3317 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3318 unsigned max_outputs,
3319 LLVMValueRef *addrs)
3320 {
3321 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3322 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3323 LLVMBuilderRef builder = ctx->ac.builder;
3324 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3325
3326 si_copy_tcs_inputs(bld_base);
3327
3328 rel_patch_id = get_rel_patch_id(ctx);
3329 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3330 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3331
3332 if (ctx->screen->info.chip_class >= GFX9) {
3333 LLVMBasicBlockRef blocks[2] = {
3334 LLVMGetInsertBlock(builder),
3335 ctx->merged_wrap_if_state.entry_block
3336 };
3337 LLVMValueRef values[2];
3338
3339 lp_build_endif(&ctx->merged_wrap_if_state);
3340
3341 values[0] = rel_patch_id;
3342 values[1] = LLVMGetUndef(ctx->i32);
3343 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3344
3345 values[0] = tf_lds_offset;
3346 values[1] = LLVMGetUndef(ctx->i32);
3347 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3348
3349 values[0] = invocation_id;
3350 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3351 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3352 }
3353
3354 /* Return epilog parameters from this function. */
3355 LLVMValueRef ret = ctx->return_value;
3356 unsigned vgpr;
3357
3358 if (ctx->screen->info.chip_class >= GFX9) {
3359 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3360 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3361 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3362 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3363 /* Tess offchip and tess factor offsets are at the beginning. */
3364 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3365 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3366 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3367 } else {
3368 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3369 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3370 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3371 GFX6_SGPR_TCS_OUT_LAYOUT);
3372 /* Tess offchip and tess factor offsets are after user SGPRs. */
3373 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3374 GFX6_TCS_NUM_USER_SGPR);
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3376 GFX6_TCS_NUM_USER_SGPR + 1);
3377 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3378 }
3379
3380 /* VGPRs */
3381 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3382 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3383 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3384
3385 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3386 * the invocation_id output does not alias the tcs_rel_ids input,
3387 * which saves a V_MOV on gfx9.
3388 */
3389 vgpr += 2;
3390
3391 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3392 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3393
3394 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3395 vgpr++; /* skip the tess factor LDS offset */
3396 for (unsigned i = 0; i < 6; i++) {
3397 LLVMValueRef value =
3398 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3399 value = ac_to_float(&ctx->ac, value);
3400 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3401 }
3402 } else {
3403 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3404 }
3405 ctx->return_value = ret;
3406 }
3407
3408 /* Pass TCS inputs from LS to TCS on GFX9. */
3409 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3410 {
3411 LLVMValueRef ret = ctx->return_value;
3412
3413 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3414 if (HAVE_32BIT_POINTERS)
3415 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3416 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3417 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3418 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3419 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3420
3421 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3422 8 + SI_SGPR_RW_BUFFERS);
3423 ret = si_insert_input_ptr(ctx, ret,
3424 ctx->param_bindless_samplers_and_images,
3425 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3426
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3428 8 + SI_SGPR_VS_STATE_BITS);
3429
3430 #if !HAVE_32BIT_POINTERS
3431 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3432 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3433 #endif
3434
3435 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3436 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3437 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3438 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3439 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3440 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3441
3442 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3443 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3444 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3445 vgpr++, "");
3446 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3447 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3448 vgpr++, "");
3449 ctx->return_value = ret;
3450 }
3451
3452 /* Pass GS inputs from ES to GS on GFX9. */
3453 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3454 {
3455 LLVMValueRef ret = ctx->return_value;
3456
3457 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3458 if (HAVE_32BIT_POINTERS)
3459 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3460 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3461 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3462 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3463
3464 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3465 8 + SI_SGPR_RW_BUFFERS);
3466 ret = si_insert_input_ptr(ctx, ret,
3467 ctx->param_bindless_samplers_and_images,
3468 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3469
3470 #if !HAVE_32BIT_POINTERS
3471 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3472 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3473 #endif
3474
3475 unsigned vgpr;
3476 if (ctx->type == PIPE_SHADER_VERTEX)
3477 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3478 else
3479 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3480
3481 for (unsigned i = 0; i < 5; i++) {
3482 unsigned param = ctx->param_gs_vtx01_offset + i;
3483 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3484 }
3485 ctx->return_value = ret;
3486 }
3487
3488 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3489 unsigned max_outputs,
3490 LLVMValueRef *addrs)
3491 {
3492 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3493 struct si_shader *shader = ctx->shader;
3494 struct tgsi_shader_info *info = &shader->selector->info;
3495 unsigned i, chan;
3496 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3497 ctx->param_rel_auto_id);
3498 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3499 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3500 vertex_dw_stride, "");
3501
3502 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3503 * its inputs from it. */
3504 for (i = 0; i < info->num_outputs; i++) {
3505 unsigned name = info->output_semantic_name[i];
3506 unsigned index = info->output_semantic_index[i];
3507
3508 /* The ARB_shader_viewport_layer_array spec contains the
3509 * following issue:
3510 *
3511 * 2) What happens if gl_ViewportIndex or gl_Layer is
3512 * written in the vertex shader and a geometry shader is
3513 * present?
3514 *
3515 * RESOLVED: The value written by the last vertex processing
3516 * stage is used. If the last vertex processing stage
3517 * (vertex, tessellation evaluation or geometry) does not
3518 * statically assign to gl_ViewportIndex or gl_Layer, index
3519 * or layer zero is assumed.
3520 *
3521 * So writes to those outputs in VS-as-LS are simply ignored.
3522 */
3523 if (name == TGSI_SEMANTIC_LAYER ||
3524 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3525 continue;
3526
3527 int param = si_shader_io_get_unique_index(name, index);
3528 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3529 LLVMConstInt(ctx->i32, param * 4, 0), "");
3530
3531 for (chan = 0; chan < 4; chan++) {
3532 if (!(info->output_usagemask[i] & (1 << chan)))
3533 continue;
3534
3535 lds_store(ctx, chan, dw_addr,
3536 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3537 }
3538 }
3539
3540 if (ctx->screen->info.chip_class >= GFX9)
3541 si_set_ls_return_value_for_tcs(ctx);
3542 }
3543
3544 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3545 unsigned max_outputs,
3546 LLVMValueRef *addrs)
3547 {
3548 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3549 struct si_shader *es = ctx->shader;
3550 struct tgsi_shader_info *info = &es->selector->info;
3551 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3552 ctx->param_es2gs_offset);
3553 LLVMValueRef lds_base = NULL;
3554 unsigned chan;
3555 int i;
3556
3557 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3558 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3559 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3560 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3561 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3562 LLVMBuildMul(ctx->ac.builder, wave_idx,
3563 LLVMConstInt(ctx->i32, 64, false), ""), "");
3564 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3565 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3566 }
3567
3568 for (i = 0; i < info->num_outputs; i++) {
3569 int param;
3570
3571 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3572 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3573 continue;
3574
3575 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3576 info->output_semantic_index[i]);
3577
3578 for (chan = 0; chan < 4; chan++) {
3579 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3580 out_val = ac_to_integer(&ctx->ac, out_val);
3581
3582 /* GFX9 has the ESGS ring in LDS. */
3583 if (ctx->screen->info.chip_class >= GFX9) {
3584 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3585 continue;
3586 }
3587
3588 ac_build_buffer_store_dword(&ctx->ac,
3589 ctx->esgs_ring,
3590 out_val, 1, NULL, soffset,
3591 (4 * param + chan) * 4,
3592 1, 1, true, true);
3593 }
3594 }
3595
3596 if (ctx->screen->info.chip_class >= GFX9)
3597 si_set_es_return_value_for_gs(ctx);
3598 }
3599
3600 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3601 {
3602 if (ctx->screen->info.chip_class >= GFX9)
3603 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3604 else
3605 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3606 }
3607
3608 static void emit_gs_epilogue(struct si_shader_context *ctx)
3609 {
3610 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3611 si_get_gs_wave_id(ctx));
3612
3613 if (ctx->screen->info.chip_class >= GFX9)
3614 lp_build_endif(&ctx->merged_wrap_if_state);
3615 }
3616
3617 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3618 unsigned max_outputs,
3619 LLVMValueRef *addrs)
3620 {
3621 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3622 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3623
3624 assert(info->num_outputs <= max_outputs);
3625
3626 emit_gs_epilogue(ctx);
3627 }
3628
3629 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3630 {
3631 struct si_shader_context *ctx = si_shader_context(bld_base);
3632 emit_gs_epilogue(ctx);
3633 }
3634
3635 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3636 unsigned max_outputs,
3637 LLVMValueRef *addrs)
3638 {
3639 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3640 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3641 struct si_shader_output_values *outputs = NULL;
3642 int i,j;
3643
3644 assert(!ctx->shader->is_gs_copy_shader);
3645 assert(info->num_outputs <= max_outputs);
3646
3647 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3648
3649 /* Vertex color clamping.
3650 *
3651 * This uses a state constant loaded in a user data SGPR and
3652 * an IF statement is added that clamps all colors if the constant
3653 * is true.
3654 */
3655 if (ctx->type == PIPE_SHADER_VERTEX) {
3656 struct lp_build_if_state if_ctx;
3657 LLVMValueRef cond = NULL;
3658 LLVMValueRef addr, val;
3659
3660 for (i = 0; i < info->num_outputs; i++) {
3661 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3662 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3663 continue;
3664
3665 /* We've found a color. */
3666 if (!cond) {
3667 /* The state is in the first bit of the user SGPR. */
3668 cond = LLVMGetParam(ctx->main_fn,
3669 ctx->param_vs_state_bits);
3670 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3671 ctx->i1, "");
3672 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3673 }
3674
3675 for (j = 0; j < 4; j++) {
3676 addr = addrs[4 * i + j];
3677 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3678 val = ac_build_clamp(&ctx->ac, val);
3679 LLVMBuildStore(ctx->ac.builder, val, addr);
3680 }
3681 }
3682
3683 if (cond)
3684 lp_build_endif(&if_ctx);
3685 }
3686
3687 for (i = 0; i < info->num_outputs; i++) {
3688 outputs[i].semantic_name = info->output_semantic_name[i];
3689 outputs[i].semantic_index = info->output_semantic_index[i];
3690
3691 for (j = 0; j < 4; j++) {
3692 outputs[i].values[j] =
3693 LLVMBuildLoad(ctx->ac.builder,
3694 addrs[4 * i + j],
3695 "");
3696 outputs[i].vertex_stream[j] =
3697 (info->output_streams[i] >> (2 * j)) & 3;
3698 }
3699 }
3700
3701 if (ctx->shader->selector->so.num_outputs)
3702 si_llvm_emit_streamout(ctx, outputs, i, 0);
3703
3704 /* Export PrimitiveID. */
3705 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3706 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3707 outputs[i].semantic_index = 0;
3708 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3709 for (j = 1; j < 4; j++)
3710 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3711
3712 memset(outputs[i].vertex_stream, 0,
3713 sizeof(outputs[i].vertex_stream));
3714 i++;
3715 }
3716
3717 si_llvm_export_vs(ctx, outputs, i);
3718 FREE(outputs);
3719 }
3720
3721 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3722 {
3723 struct si_shader_context *ctx = si_shader_context(bld_base);
3724
3725 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3726 &ctx->outputs[0][0]);
3727 }
3728
3729 struct si_ps_exports {
3730 unsigned num;
3731 struct ac_export_args args[10];
3732 };
3733
3734 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3735 LLVMValueRef depth, LLVMValueRef stencil,
3736 LLVMValueRef samplemask, struct si_ps_exports *exp)
3737 {
3738 struct si_shader_context *ctx = si_shader_context(bld_base);
3739 struct ac_export_args args;
3740
3741 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3742
3743 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3744 }
3745
3746 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3747 LLVMValueRef *color, unsigned index,
3748 unsigned samplemask_param,
3749 bool is_last, struct si_ps_exports *exp)
3750 {
3751 struct si_shader_context *ctx = si_shader_context(bld_base);
3752 int i;
3753
3754 /* Clamp color */
3755 if (ctx->shader->key.part.ps.epilog.clamp_color)
3756 for (i = 0; i < 4; i++)
3757 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3758
3759 /* Alpha to one */
3760 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3761 color[3] = ctx->ac.f32_1;
3762
3763 /* Alpha test */
3764 if (index == 0 &&
3765 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3766 si_alpha_test(bld_base, color[3]);
3767
3768 /* Line & polygon smoothing */
3769 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3770 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3771 samplemask_param);
3772
3773 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3774 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3775 struct ac_export_args args[8];
3776 int c, last = -1;
3777
3778 /* Get the export arguments, also find out what the last one is. */
3779 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3780 si_llvm_init_export_args(ctx, color,
3781 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3782 if (args[c].enabled_channels)
3783 last = c;
3784 }
3785
3786 /* Emit all exports. */
3787 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3788 if (is_last && last == c) {
3789 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3790 args[c].done = 1; /* DONE bit */
3791 } else if (!args[c].enabled_channels)
3792 continue; /* unnecessary NULL export */
3793
3794 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3795 }
3796 } else {
3797 struct ac_export_args args;
3798
3799 /* Export */
3800 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3801 &args);
3802 if (is_last) {
3803 args.valid_mask = 1; /* whether the EXEC mask is valid */
3804 args.done = 1; /* DONE bit */
3805 } else if (!args.enabled_channels)
3806 return; /* unnecessary NULL export */
3807
3808 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3809 }
3810 }
3811
3812 static void si_emit_ps_exports(struct si_shader_context *ctx,
3813 struct si_ps_exports *exp)
3814 {
3815 for (unsigned i = 0; i < exp->num; i++)
3816 ac_build_export(&ctx->ac, &exp->args[i]);
3817 }
3818
3819 /**
3820 * Return PS outputs in this order:
3821 *
3822 * v[0:3] = color0.xyzw
3823 * v[4:7] = color1.xyzw
3824 * ...
3825 * vN+0 = Depth
3826 * vN+1 = Stencil
3827 * vN+2 = SampleMask
3828 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3829 *
3830 * The alpha-ref SGPR is returned via its original location.
3831 */
3832 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3833 unsigned max_outputs,
3834 LLVMValueRef *addrs)
3835 {
3836 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3837 struct si_shader *shader = ctx->shader;
3838 struct tgsi_shader_info *info = &shader->selector->info;
3839 LLVMBuilderRef builder = ctx->ac.builder;
3840 unsigned i, j, first_vgpr, vgpr;
3841
3842 LLVMValueRef color[8][4] = {};
3843 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3844 LLVMValueRef ret;
3845
3846 if (ctx->postponed_kill)
3847 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3848
3849 /* Read the output values. */
3850 for (i = 0; i < info->num_outputs; i++) {
3851 unsigned semantic_name = info->output_semantic_name[i];
3852 unsigned semantic_index = info->output_semantic_index[i];
3853
3854 switch (semantic_name) {
3855 case TGSI_SEMANTIC_COLOR:
3856 assert(semantic_index < 8);
3857 for (j = 0; j < 4; j++) {
3858 LLVMValueRef ptr = addrs[4 * i + j];
3859 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3860 color[semantic_index][j] = result;
3861 }
3862 break;
3863 case TGSI_SEMANTIC_POSITION:
3864 depth = LLVMBuildLoad(builder,
3865 addrs[4 * i + 2], "");
3866 break;
3867 case TGSI_SEMANTIC_STENCIL:
3868 stencil = LLVMBuildLoad(builder,
3869 addrs[4 * i + 1], "");
3870 break;
3871 case TGSI_SEMANTIC_SAMPLEMASK:
3872 samplemask = LLVMBuildLoad(builder,
3873 addrs[4 * i + 0], "");
3874 break;
3875 default:
3876 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3877 semantic_name);
3878 }
3879 }
3880
3881 /* Fill the return structure. */
3882 ret = ctx->return_value;
3883
3884 /* Set SGPRs. */
3885 ret = LLVMBuildInsertValue(builder, ret,
3886 ac_to_integer(&ctx->ac,
3887 LLVMGetParam(ctx->main_fn,
3888 SI_PARAM_ALPHA_REF)),
3889 SI_SGPR_ALPHA_REF, "");
3890
3891 /* Set VGPRs */
3892 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3893 for (i = 0; i < ARRAY_SIZE(color); i++) {
3894 if (!color[i][0])
3895 continue;
3896
3897 for (j = 0; j < 4; j++)
3898 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3899 }
3900 if (depth)
3901 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3902 if (stencil)
3903 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3904 if (samplemask)
3905 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3906
3907 /* Add the input sample mask for smoothing at the end. */
3908 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3909 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3910 ret = LLVMBuildInsertValue(builder, ret,
3911 LLVMGetParam(ctx->main_fn,
3912 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3913
3914 ctx->return_value = ret;
3915 }
3916
3917 static void membar_emit(
3918 const struct lp_build_tgsi_action *action,
3919 struct lp_build_tgsi_context *bld_base,
3920 struct lp_build_emit_data *emit_data)
3921 {
3922 struct si_shader_context *ctx = si_shader_context(bld_base);
3923 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3924 unsigned flags = LLVMConstIntGetZExtValue(src0);
3925 unsigned waitcnt = NOOP_WAITCNT;
3926
3927 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3928 waitcnt &= VM_CNT & LGKM_CNT;
3929
3930 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3931 TGSI_MEMBAR_SHADER_BUFFER |
3932 TGSI_MEMBAR_SHADER_IMAGE))
3933 waitcnt &= VM_CNT;
3934
3935 if (flags & TGSI_MEMBAR_SHARED)
3936 waitcnt &= LGKM_CNT;
3937
3938 if (waitcnt != NOOP_WAITCNT)
3939 ac_build_waitcnt(&ctx->ac, waitcnt);
3940 }
3941
3942 static void clock_emit(
3943 const struct lp_build_tgsi_action *action,
3944 struct lp_build_tgsi_context *bld_base,
3945 struct lp_build_emit_data *emit_data)
3946 {
3947 struct si_shader_context *ctx = si_shader_context(bld_base);
3948 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3949
3950 emit_data->output[0] =
3951 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3952 emit_data->output[1] =
3953 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3954 }
3955
3956 static void si_llvm_emit_ddxy(
3957 const struct lp_build_tgsi_action *action,
3958 struct lp_build_tgsi_context *bld_base,
3959 struct lp_build_emit_data *emit_data)
3960 {
3961 struct si_shader_context *ctx = si_shader_context(bld_base);
3962 unsigned opcode = emit_data->info->opcode;
3963 LLVMValueRef val;
3964 int idx;
3965 unsigned mask;
3966
3967 if (opcode == TGSI_OPCODE_DDX_FINE)
3968 mask = AC_TID_MASK_LEFT;
3969 else if (opcode == TGSI_OPCODE_DDY_FINE)
3970 mask = AC_TID_MASK_TOP;
3971 else
3972 mask = AC_TID_MASK_TOP_LEFT;
3973
3974 /* for DDX we want to next X pixel, DDY next Y pixel. */
3975 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3976
3977 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3978 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3979 emit_data->output[emit_data->chan] = val;
3980 }
3981
3982 /*
3983 * this takes an I,J coordinate pair,
3984 * and works out the X and Y derivatives.
3985 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3986 */
3987 static LLVMValueRef si_llvm_emit_ddxy_interp(
3988 struct lp_build_tgsi_context *bld_base,
3989 LLVMValueRef interp_ij)
3990 {
3991 struct si_shader_context *ctx = si_shader_context(bld_base);
3992 LLVMValueRef result[4], a;
3993 unsigned i;
3994
3995 for (i = 0; i < 2; i++) {
3996 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3997 LLVMConstInt(ctx->i32, i, 0), "");
3998 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3999 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4000 }
4001
4002 return lp_build_gather_values(&ctx->gallivm, result, 4);
4003 }
4004
4005 static void interp_fetch_args(
4006 struct lp_build_tgsi_context *bld_base,
4007 struct lp_build_emit_data *emit_data)
4008 {
4009 struct si_shader_context *ctx = si_shader_context(bld_base);
4010 const struct tgsi_full_instruction *inst = emit_data->inst;
4011
4012 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4013 /* offset is in second src, first two channels */
4014 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4015 emit_data->inst, 1,
4016 TGSI_CHAN_X);
4017 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4018 emit_data->inst, 1,
4019 TGSI_CHAN_Y);
4020 emit_data->arg_count = 2;
4021 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4022 LLVMValueRef sample_position;
4023 LLVMValueRef sample_id;
4024 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4025
4026 /* fetch sample ID, then fetch its sample position,
4027 * and place into first two channels.
4028 */
4029 sample_id = lp_build_emit_fetch(bld_base,
4030 emit_data->inst, 1, TGSI_CHAN_X);
4031 sample_id = ac_to_integer(&ctx->ac, sample_id);
4032
4033 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4034 * Language 4.50 spec says about interpolateAtSample:
4035 *
4036 * "Returns the value of the input interpolant variable at
4037 * the location of sample number sample. If multisample
4038 * buffers are not available, the input variable will be
4039 * evaluated at the center of the pixel. If sample sample
4040 * does not exist, the position used to interpolate the
4041 * input variable is undefined."
4042 *
4043 * This means that sample_id values outside of the valid are
4044 * in fact valid input, and the usual mechanism for loading the
4045 * sample position doesn't work.
4046 */
4047 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4048 LLVMValueRef center[4] = {
4049 LLVMConstReal(ctx->f32, 0.5),
4050 LLVMConstReal(ctx->f32, 0.5),
4051 ctx->ac.f32_0,
4052 ctx->ac.f32_0,
4053 };
4054
4055 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4056 } else {
4057 sample_position = load_sample_position(&ctx->abi, sample_id);
4058 }
4059
4060 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4061 sample_position,
4062 ctx->i32_0, "");
4063
4064 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4065 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4066 sample_position,
4067 ctx->i32_1, "");
4068 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4069 emit_data->arg_count = 2;
4070 }
4071 }
4072
4073 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4074 struct lp_build_tgsi_context *bld_base,
4075 struct lp_build_emit_data *emit_data)
4076 {
4077 struct si_shader_context *ctx = si_shader_context(bld_base);
4078 struct si_shader *shader = ctx->shader;
4079 const struct tgsi_shader_info *info = &shader->selector->info;
4080 LLVMValueRef interp_param;
4081 const struct tgsi_full_instruction *inst = emit_data->inst;
4082 const struct tgsi_full_src_register *input = &inst->Src[0];
4083 int input_base, input_array_size;
4084 int chan;
4085 int i;
4086 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4087 LLVMValueRef array_idx;
4088 int interp_param_idx;
4089 unsigned interp;
4090 unsigned location;
4091
4092 assert(input->Register.File == TGSI_FILE_INPUT);
4093
4094 if (input->Register.Indirect) {
4095 unsigned array_id = input->Indirect.ArrayID;
4096
4097 if (array_id) {
4098 input_base = info->input_array_first[array_id];
4099 input_array_size = info->input_array_last[array_id] - input_base + 1;
4100 } else {
4101 input_base = inst->Src[0].Register.Index;
4102 input_array_size = info->num_inputs - input_base;
4103 }
4104
4105 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4106 1, input->Register.Index - input_base);
4107 } else {
4108 input_base = inst->Src[0].Register.Index;
4109 input_array_size = 1;
4110 array_idx = ctx->i32_0;
4111 }
4112
4113 interp = shader->selector->info.input_interpolate[input_base];
4114
4115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4116 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4117 location = TGSI_INTERPOLATE_LOC_CENTER;
4118 else
4119 location = TGSI_INTERPOLATE_LOC_CENTROID;
4120
4121 interp_param_idx = lookup_interp_param_index(interp, location);
4122 if (interp_param_idx == -1)
4123 return;
4124 else if (interp_param_idx)
4125 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4126 else
4127 interp_param = NULL;
4128
4129 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4130 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4131 LLVMValueRef ij_out[2];
4132 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4133
4134 /*
4135 * take the I then J parameters, and the DDX/Y for it, and
4136 * calculate the IJ inputs for the interpolator.
4137 * temp1 = ddx * offset/sample.x + I;
4138 * interp_param.I = ddy * offset/sample.y + temp1;
4139 * temp1 = ddx * offset/sample.x + J;
4140 * interp_param.J = ddy * offset/sample.y + temp1;
4141 */
4142 for (i = 0; i < 2; i++) {
4143 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4144 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4145 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4146 ddxy_out, ix_ll, "");
4147 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4148 ddxy_out, iy_ll, "");
4149 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4150 interp_param, ix_ll, "");
4151 LLVMValueRef temp1, temp2;
4152
4153 interp_el = ac_to_float(&ctx->ac, interp_el);
4154
4155 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4156
4157 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4158
4159 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4160
4161 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4162 }
4163 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4164 }
4165
4166 if (interp_param)
4167 interp_param = ac_to_float(&ctx->ac, interp_param);
4168
4169 for (chan = 0; chan < 4; chan++) {
4170 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4171 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4172
4173 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4174 LLVMValueRef v, i = NULL, j = NULL;
4175
4176 if (interp_param) {
4177 i = LLVMBuildExtractElement(
4178 ctx->ac.builder, interp_param, ctx->i32_0, "");
4179 j = LLVMBuildExtractElement(
4180 ctx->ac.builder, interp_param, ctx->i32_1, "");
4181 }
4182 v = si_build_fs_interp(ctx, input_base + idx, schan,
4183 prim_mask, i, j);
4184
4185 gather = LLVMBuildInsertElement(ctx->ac.builder,
4186 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4187 }
4188
4189 emit_data->output[chan] = LLVMBuildExtractElement(
4190 ctx->ac.builder, gather, array_idx, "");
4191 }
4192 }
4193
4194 static void vote_all_emit(
4195 const struct lp_build_tgsi_action *action,
4196 struct lp_build_tgsi_context *bld_base,
4197 struct lp_build_emit_data *emit_data)
4198 {
4199 struct si_shader_context *ctx = si_shader_context(bld_base);
4200
4201 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4202 emit_data->output[emit_data->chan] =
4203 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4204 }
4205
4206 static void vote_any_emit(
4207 const struct lp_build_tgsi_action *action,
4208 struct lp_build_tgsi_context *bld_base,
4209 struct lp_build_emit_data *emit_data)
4210 {
4211 struct si_shader_context *ctx = si_shader_context(bld_base);
4212
4213 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4214 emit_data->output[emit_data->chan] =
4215 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4216 }
4217
4218 static void vote_eq_emit(
4219 const struct lp_build_tgsi_action *action,
4220 struct lp_build_tgsi_context *bld_base,
4221 struct lp_build_emit_data *emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224
4225 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4226 emit_data->output[emit_data->chan] =
4227 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4228 }
4229
4230 static void ballot_emit(
4231 const struct lp_build_tgsi_action *action,
4232 struct lp_build_tgsi_context *bld_base,
4233 struct lp_build_emit_data *emit_data)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 LLVMBuilderRef builder = ctx->ac.builder;
4237 LLVMValueRef tmp;
4238
4239 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4240 tmp = ac_build_ballot(&ctx->ac, tmp);
4241 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4242
4243 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4244 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4245 }
4246
4247 static void read_invoc_fetch_args(
4248 struct lp_build_tgsi_context *bld_base,
4249 struct lp_build_emit_data *emit_data)
4250 {
4251 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4252 0, emit_data->src_chan);
4253
4254 /* Always read the source invocation (= lane) from the X channel. */
4255 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4256 1, TGSI_CHAN_X);
4257 emit_data->arg_count = 2;
4258 }
4259
4260 static void read_lane_emit(
4261 const struct lp_build_tgsi_action *action,
4262 struct lp_build_tgsi_context *bld_base,
4263 struct lp_build_emit_data *emit_data)
4264 {
4265 struct si_shader_context *ctx = si_shader_context(bld_base);
4266
4267 /* We currently have no other way to prevent LLVM from lifting the icmp
4268 * calls to a dominating basic block.
4269 */
4270 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4271
4272 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4273 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4274
4275 emit_data->output[emit_data->chan] =
4276 ac_build_intrinsic(&ctx->ac, action->intr_name,
4277 ctx->i32, emit_data->args, emit_data->arg_count,
4278 AC_FUNC_ATTR_READNONE |
4279 AC_FUNC_ATTR_CONVERGENT);
4280 }
4281
4282 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4283 struct lp_build_emit_data *emit_data)
4284 {
4285 struct si_shader_context *ctx = si_shader_context(bld_base);
4286 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4287 LLVMValueRef imm;
4288 unsigned stream;
4289
4290 assert(src0.File == TGSI_FILE_IMMEDIATE);
4291
4292 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4293 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4294 return stream;
4295 }
4296
4297 /* Emit one vertex from the geometry shader */
4298 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4299 unsigned stream,
4300 LLVMValueRef *addrs)
4301 {
4302 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4303 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4304 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4305 struct si_shader *shader = ctx->shader;
4306 struct lp_build_if_state if_state;
4307 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4308 ctx->param_gs2vs_offset);
4309 LLVMValueRef gs_next_vertex;
4310 LLVMValueRef can_emit;
4311 unsigned chan, offset;
4312 int i;
4313
4314 /* Write vertex attribute values to GSVS ring */
4315 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4316 ctx->gs_next_vertex[stream],
4317 "");
4318
4319 /* If this thread has already emitted the declared maximum number of
4320 * vertices, skip the write: excessive vertex emissions are not
4321 * supposed to have any effect.
4322 *
4323 * If the shader has no writes to memory, kill it instead. This skips
4324 * further memory loads and may allow LLVM to skip to the end
4325 * altogether.
4326 */
4327 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4328 LLVMConstInt(ctx->i32,
4329 shader->selector->gs_max_out_vertices, 0), "");
4330
4331 bool use_kill = !info->writes_memory;
4332 if (use_kill) {
4333 ac_build_kill_if_false(&ctx->ac, can_emit);
4334 } else {
4335 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4336 }
4337
4338 offset = 0;
4339 for (i = 0; i < info->num_outputs; i++) {
4340 for (chan = 0; chan < 4; chan++) {
4341 if (!(info->output_usagemask[i] & (1 << chan)) ||
4342 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4343 continue;
4344
4345 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4346 LLVMValueRef voffset =
4347 LLVMConstInt(ctx->i32, offset *
4348 shader->selector->gs_max_out_vertices, 0);
4349 offset++;
4350
4351 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4352 voffset = lp_build_mul_imm(uint, voffset, 4);
4353
4354 out_val = ac_to_integer(&ctx->ac, out_val);
4355
4356 ac_build_buffer_store_dword(&ctx->ac,
4357 ctx->gsvs_ring[stream],
4358 out_val, 1,
4359 voffset, soffset, 0,
4360 1, 1, true, true);
4361 }
4362 }
4363
4364 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4365 ctx->i32_1);
4366
4367 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4368
4369 /* Signal vertex emission */
4370 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4371 si_get_gs_wave_id(ctx));
4372 if (!use_kill)
4373 lp_build_endif(&if_state);
4374 }
4375
4376 /* Emit one vertex from the geometry shader */
4377 static void si_tgsi_emit_vertex(
4378 const struct lp_build_tgsi_action *action,
4379 struct lp_build_tgsi_context *bld_base,
4380 struct lp_build_emit_data *emit_data)
4381 {
4382 struct si_shader_context *ctx = si_shader_context(bld_base);
4383 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4384
4385 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4386 }
4387
4388 /* Cut one primitive from the geometry shader */
4389 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4390 unsigned stream)
4391 {
4392 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4393
4394 /* Signal primitive cut */
4395 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4396 si_get_gs_wave_id(ctx));
4397 }
4398
4399 /* Cut one primitive from the geometry shader */
4400 static void si_tgsi_emit_primitive(
4401 const struct lp_build_tgsi_action *action,
4402 struct lp_build_tgsi_context *bld_base,
4403 struct lp_build_emit_data *emit_data)
4404 {
4405 struct si_shader_context *ctx = si_shader_context(bld_base);
4406
4407 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4408 }
4409
4410 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4411 struct lp_build_tgsi_context *bld_base,
4412 struct lp_build_emit_data *emit_data)
4413 {
4414 struct si_shader_context *ctx = si_shader_context(bld_base);
4415
4416 /* SI only (thanks to a hw bug workaround):
4417 * The real barrier instruction isn’t needed, because an entire patch
4418 * always fits into a single wave.
4419 */
4420 if (ctx->screen->info.chip_class == SI &&
4421 ctx->type == PIPE_SHADER_TESS_CTRL) {
4422 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4423 return;
4424 }
4425
4426 lp_build_intrinsic(ctx->ac.builder,
4427 "llvm.amdgcn.s.barrier",
4428 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4429 }
4430
4431 static const struct lp_build_tgsi_action interp_action = {
4432 .fetch_args = interp_fetch_args,
4433 .emit = build_interp_intrinsic,
4434 };
4435
4436 static void si_create_function(struct si_shader_context *ctx,
4437 const char *name,
4438 LLVMTypeRef *returns, unsigned num_returns,
4439 struct si_function_info *fninfo,
4440 unsigned max_workgroup_size)
4441 {
4442 int i;
4443
4444 si_llvm_create_func(ctx, name, returns, num_returns,
4445 fninfo->types, fninfo->num_params);
4446 ctx->return_value = LLVMGetUndef(ctx->return_type);
4447
4448 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4449 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4450
4451 /* The combination of:
4452 * - noalias
4453 * - dereferenceable
4454 * - invariant.load
4455 * allows the optimization passes to move loads and reduces
4456 * SGPR spilling significantly.
4457 */
4458 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4459
4460 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4461 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4462 ac_add_attr_dereferenceable(P, UINT64_MAX);
4463 }
4464 }
4465
4466 for (i = 0; i < fninfo->num_params; ++i) {
4467 if (fninfo->assign[i])
4468 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4469 }
4470
4471 if (ctx->screen->info.address32_hi) {
4472 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4473 "amdgpu-32bit-address-high-bits",
4474 ctx->screen->info.address32_hi);
4475 }
4476
4477 if (max_workgroup_size) {
4478 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4479 "amdgpu-max-work-group-size",
4480 max_workgroup_size);
4481 }
4482 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4483 "no-signed-zeros-fp-math",
4484 "true");
4485
4486 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4487 /* These were copied from some LLVM test. */
4488 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4489 "less-precise-fpmad",
4490 "true");
4491 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4492 "no-infs-fp-math",
4493 "true");
4494 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4495 "no-nans-fp-math",
4496 "true");
4497 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4498 "unsafe-fp-math",
4499 "true");
4500 }
4501 }
4502
4503 static void declare_streamout_params(struct si_shader_context *ctx,
4504 struct pipe_stream_output_info *so,
4505 struct si_function_info *fninfo)
4506 {
4507 int i;
4508
4509 /* Streamout SGPRs. */
4510 if (so->num_outputs) {
4511 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4512 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4513 else
4514 ctx->param_streamout_config = fninfo->num_params - 1;
4515
4516 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4517 }
4518 /* A streamout buffer offset is loaded if the stride is non-zero. */
4519 for (i = 0; i < 4; i++) {
4520 if (!so->stride[i])
4521 continue;
4522
4523 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4524 }
4525 }
4526
4527 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4528 {
4529 switch (shader->selector->type) {
4530 case PIPE_SHADER_TESS_CTRL:
4531 /* Return this so that LLVM doesn't remove s_barrier
4532 * instructions on chips where we use s_barrier. */
4533 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4534
4535 case PIPE_SHADER_GEOMETRY:
4536 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4537
4538 case PIPE_SHADER_COMPUTE:
4539 break; /* see below */
4540
4541 default:
4542 return 0;
4543 }
4544
4545 const unsigned *properties = shader->selector->info.properties;
4546 unsigned max_work_group_size =
4547 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4548 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4549 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4550
4551 if (!max_work_group_size) {
4552 /* This is a variable group size compute shader,
4553 * compile it for the maximum possible group size.
4554 */
4555 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4556 }
4557 return max_work_group_size;
4558 }
4559
4560 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4561 struct si_function_info *fninfo,
4562 bool assign_params)
4563 {
4564 LLVMTypeRef const_shader_buf_type;
4565
4566 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4567 ctx->shader->selector->info.shader_buffers_declared == 0)
4568 const_shader_buf_type = ctx->f32;
4569 else
4570 const_shader_buf_type = ctx->v4i32;
4571
4572 unsigned const_and_shader_buffers =
4573 add_arg(fninfo, ARG_SGPR,
4574 ac_array_in_const32_addr_space(const_shader_buf_type));
4575
4576 if (assign_params)
4577 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4578 }
4579
4580 static void declare_samplers_and_images(struct si_shader_context *ctx,
4581 struct si_function_info *fninfo,
4582 bool assign_params)
4583 {
4584 unsigned samplers_and_images =
4585 add_arg(fninfo, ARG_SGPR,
4586 ac_array_in_const32_addr_space(ctx->v8i32));
4587
4588 if (assign_params)
4589 ctx->param_samplers_and_images = samplers_and_images;
4590 }
4591
4592 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4593 struct si_function_info *fninfo,
4594 bool assign_params)
4595 {
4596 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4597 declare_samplers_and_images(ctx, fninfo, assign_params);
4598 }
4599
4600 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4601 struct si_function_info *fninfo)
4602 {
4603 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4604 ac_array_in_const32_addr_space(ctx->v4i32));
4605 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4606 ac_array_in_const32_addr_space(ctx->v8i32));
4607 }
4608
4609 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4610 struct si_function_info *fninfo)
4611 {
4612 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4613 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4614 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4615 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4616 }
4617
4618 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4619 struct si_function_info *fninfo,
4620 unsigned *num_prolog_vgprs)
4621 {
4622 struct si_shader *shader = ctx->shader;
4623
4624 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4625 if (shader->key.as_ls) {
4626 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4627 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4628 } else {
4629 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4630 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4631 }
4632 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4633
4634 if (!shader->is_gs_copy_shader) {
4635 /* Vertex load indices. */
4636 ctx->param_vertex_index0 = fninfo->num_params;
4637 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4638 add_arg(fninfo, ARG_VGPR, ctx->i32);
4639 *num_prolog_vgprs += shader->selector->info.num_inputs;
4640 }
4641 }
4642
4643 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4644 struct si_function_info *fninfo)
4645 {
4646 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4647 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4648 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4649 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4650 }
4651
4652 enum {
4653 /* Convenient merged shader definitions. */
4654 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4655 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4656 };
4657
4658 static void create_function(struct si_shader_context *ctx)
4659 {
4660 struct si_shader *shader = ctx->shader;
4661 struct si_function_info fninfo;
4662 LLVMTypeRef returns[16+32*4];
4663 unsigned i, num_return_sgprs;
4664 unsigned num_returns = 0;
4665 unsigned num_prolog_vgprs = 0;
4666 unsigned type = ctx->type;
4667 unsigned vs_blit_property =
4668 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4669
4670 si_init_function_info(&fninfo);
4671
4672 /* Set MERGED shaders. */
4673 if (ctx->screen->info.chip_class >= GFX9) {
4674 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4675 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4676 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4677 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4678 }
4679
4680 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4681
4682 switch (type) {
4683 case PIPE_SHADER_VERTEX:
4684 declare_global_desc_pointers(ctx, &fninfo);
4685
4686 if (vs_blit_property) {
4687 ctx->param_vs_blit_inputs = fninfo.num_params;
4688 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4689 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4690 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4691
4692 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4693 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4694 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4695 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4696 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4697 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4698 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4699 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4700 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4701 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4702 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4703 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4704 }
4705
4706 /* VGPRs */
4707 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4708 break;
4709 }
4710
4711 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4712 declare_vs_specific_input_sgprs(ctx, &fninfo);
4713 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4714 ac_array_in_const32_addr_space(ctx->v4i32));
4715
4716 if (shader->key.as_es) {
4717 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4718 } else if (shader->key.as_ls) {
4719 /* no extra parameters */
4720 } else {
4721 if (shader->is_gs_copy_shader) {
4722 fninfo.num_params = ctx->param_rw_buffers + 1;
4723 fninfo.num_sgpr_params = fninfo.num_params;
4724 }
4725
4726 /* The locations of the other parameters are assigned dynamically. */
4727 declare_streamout_params(ctx, &shader->selector->so,
4728 &fninfo);
4729 }
4730
4731 /* VGPRs */
4732 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4733 break;
4734
4735 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4736 declare_global_desc_pointers(ctx, &fninfo);
4737 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4738 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4739 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4740 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4741 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4742 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744
4745 /* VGPRs */
4746 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4747 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4748
4749 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4750 * placed after the user SGPRs.
4751 */
4752 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4753 returns[num_returns++] = ctx->i32; /* SGPRs */
4754 for (i = 0; i < 11; i++)
4755 returns[num_returns++] = ctx->f32; /* VGPRs */
4756 break;
4757
4758 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4759 /* Merged stages have 8 system SGPRs at the beginning. */
4760 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4761 if (HAVE_32BIT_POINTERS) {
4762 declare_per_stage_desc_pointers(ctx, &fninfo,
4763 ctx->type == PIPE_SHADER_TESS_CTRL);
4764 } else {
4765 declare_const_and_shader_buffers(ctx, &fninfo,
4766 ctx->type == PIPE_SHADER_TESS_CTRL);
4767 }
4768 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4769 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4770 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4771 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4772 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4773 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4774
4775 declare_global_desc_pointers(ctx, &fninfo);
4776 declare_per_stage_desc_pointers(ctx, &fninfo,
4777 ctx->type == PIPE_SHADER_VERTEX);
4778 declare_vs_specific_input_sgprs(ctx, &fninfo);
4779
4780 if (!HAVE_32BIT_POINTERS) {
4781 declare_samplers_and_images(ctx, &fninfo,
4782 ctx->type == PIPE_SHADER_TESS_CTRL);
4783 }
4784 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4785 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4786 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4787 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4788 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4789 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4790 ac_array_in_const32_addr_space(ctx->v4i32));
4791
4792 /* VGPRs (first TCS, then VS) */
4793 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4794 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4795
4796 if (ctx->type == PIPE_SHADER_VERTEX) {
4797 declare_vs_input_vgprs(ctx, &fninfo,
4798 &num_prolog_vgprs);
4799
4800 /* LS return values are inputs to the TCS main shader part. */
4801 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4802 returns[num_returns++] = ctx->i32; /* SGPRs */
4803 for (i = 0; i < 2; i++)
4804 returns[num_returns++] = ctx->f32; /* VGPRs */
4805 } else {
4806 /* TCS return values are inputs to the TCS epilog.
4807 *
4808 * param_tcs_offchip_offset, param_tcs_factor_offset,
4809 * param_tcs_offchip_layout, and param_rw_buffers
4810 * should be passed to the epilog.
4811 */
4812 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4813 returns[num_returns++] = ctx->i32; /* SGPRs */
4814 for (i = 0; i < 11; i++)
4815 returns[num_returns++] = ctx->f32; /* VGPRs */
4816 }
4817 break;
4818
4819 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4820 /* Merged stages have 8 system SGPRs at the beginning. */
4821 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4822 if (HAVE_32BIT_POINTERS) {
4823 declare_per_stage_desc_pointers(ctx, &fninfo,
4824 ctx->type == PIPE_SHADER_GEOMETRY);
4825 } else {
4826 declare_const_and_shader_buffers(ctx, &fninfo,
4827 ctx->type == PIPE_SHADER_GEOMETRY);
4828 }
4829 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4830 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4831 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4832 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4833 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4834 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4835
4836 declare_global_desc_pointers(ctx, &fninfo);
4837 declare_per_stage_desc_pointers(ctx, &fninfo,
4838 (ctx->type == PIPE_SHADER_VERTEX ||
4839 ctx->type == PIPE_SHADER_TESS_EVAL));
4840 if (ctx->type == PIPE_SHADER_VERTEX) {
4841 declare_vs_specific_input_sgprs(ctx, &fninfo);
4842 } else {
4843 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4844 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4845 if (!HAVE_32BIT_POINTERS) {
4846 /* Declare as many input SGPRs as the VS has. */
4847 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4848 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4849 }
4850 }
4851
4852 if (!HAVE_32BIT_POINTERS) {
4853 declare_samplers_and_images(ctx, &fninfo,
4854 ctx->type == PIPE_SHADER_GEOMETRY);
4855 }
4856 if (ctx->type == PIPE_SHADER_VERTEX) {
4857 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4858 ac_array_in_const32_addr_space(ctx->v4i32));
4859 }
4860
4861 /* VGPRs (first GS, then VS/TES) */
4862 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4863 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4864 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4865 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4866 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4867
4868 if (ctx->type == PIPE_SHADER_VERTEX) {
4869 declare_vs_input_vgprs(ctx, &fninfo,
4870 &num_prolog_vgprs);
4871 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4872 declare_tes_input_vgprs(ctx, &fninfo);
4873 }
4874
4875 if (ctx->type == PIPE_SHADER_VERTEX ||
4876 ctx->type == PIPE_SHADER_TESS_EVAL) {
4877 unsigned num_user_sgprs;
4878
4879 if (ctx->type == PIPE_SHADER_VERTEX)
4880 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4881 else
4882 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4883
4884 /* ES return values are inputs to GS. */
4885 for (i = 0; i < 8 + num_user_sgprs; i++)
4886 returns[num_returns++] = ctx->i32; /* SGPRs */
4887 for (i = 0; i < 5; i++)
4888 returns[num_returns++] = ctx->f32; /* VGPRs */
4889 }
4890 break;
4891
4892 case PIPE_SHADER_TESS_EVAL:
4893 declare_global_desc_pointers(ctx, &fninfo);
4894 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4895 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4896 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4897
4898 if (shader->key.as_es) {
4899 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4900 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4901 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4902 } else {
4903 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4904 declare_streamout_params(ctx, &shader->selector->so,
4905 &fninfo);
4906 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4907 }
4908
4909 /* VGPRs */
4910 declare_tes_input_vgprs(ctx, &fninfo);
4911 break;
4912
4913 case PIPE_SHADER_GEOMETRY:
4914 declare_global_desc_pointers(ctx, &fninfo);
4915 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4916 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4917 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4918
4919 /* VGPRs */
4920 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4921 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4922 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4923 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4924 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4925 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4926 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4927 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4928 break;
4929
4930 case PIPE_SHADER_FRAGMENT:
4931 declare_global_desc_pointers(ctx, &fninfo);
4932 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4933 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4934 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4935 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4936
4937 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4938 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4939 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4940 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4941 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4942 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4943 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4944 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4945 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4946 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4947 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4948 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4949 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4950 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4951 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4952 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4953 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4954 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4955 shader->info.face_vgpr_index = 20;
4956 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4957 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4958 shader->info.ancillary_vgpr_index = 21;
4959 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4960 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4961 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4962
4963 /* Color inputs from the prolog. */
4964 if (shader->selector->info.colors_read) {
4965 unsigned num_color_elements =
4966 util_bitcount(shader->selector->info.colors_read);
4967
4968 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4969 for (i = 0; i < num_color_elements; i++)
4970 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4971
4972 num_prolog_vgprs += num_color_elements;
4973 }
4974
4975 /* Outputs for the epilog. */
4976 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4977 num_returns =
4978 num_return_sgprs +
4979 util_bitcount(shader->selector->info.colors_written) * 4 +
4980 shader->selector->info.writes_z +
4981 shader->selector->info.writes_stencil +
4982 shader->selector->info.writes_samplemask +
4983 1 /* SampleMaskIn */;
4984
4985 num_returns = MAX2(num_returns,
4986 num_return_sgprs +
4987 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4988
4989 for (i = 0; i < num_return_sgprs; i++)
4990 returns[i] = ctx->i32;
4991 for (; i < num_returns; i++)
4992 returns[i] = ctx->f32;
4993 break;
4994
4995 case PIPE_SHADER_COMPUTE:
4996 declare_global_desc_pointers(ctx, &fninfo);
4997 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4998 if (shader->selector->info.uses_grid_size)
4999 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
5000 if (shader->selector->info.uses_block_size)
5001 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
5002
5003 for (i = 0; i < 3; i++) {
5004 ctx->abi.workgroup_ids[i] = NULL;
5005 if (shader->selector->info.uses_block_id[i])
5006 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
5007 }
5008
5009 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
5010 break;
5011 default:
5012 assert(0 && "unimplemented shader");
5013 return;
5014 }
5015
5016 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5017 si_get_max_workgroup_size(shader));
5018
5019 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5020 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5021 ctx->separate_prolog) {
5022 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5023 "InitialPSInputAddr",
5024 S_0286D0_PERSP_SAMPLE_ENA(1) |
5025 S_0286D0_PERSP_CENTER_ENA(1) |
5026 S_0286D0_PERSP_CENTROID_ENA(1) |
5027 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5028 S_0286D0_LINEAR_CENTER_ENA(1) |
5029 S_0286D0_LINEAR_CENTROID_ENA(1) |
5030 S_0286D0_FRONT_FACE_ENA(1) |
5031 S_0286D0_ANCILLARY_ENA(1) |
5032 S_0286D0_POS_FIXED_PT_ENA(1));
5033 }
5034
5035 shader->info.num_input_sgprs = 0;
5036 shader->info.num_input_vgprs = 0;
5037
5038 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5039 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5040
5041 for (; i < fninfo.num_params; ++i)
5042 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5043
5044 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5045 shader->info.num_input_vgprs -= num_prolog_vgprs;
5046
5047 if (shader->key.as_ls ||
5048 ctx->type == PIPE_SHADER_TESS_CTRL ||
5049 /* GFX9 has the ESGS ring buffer in LDS. */
5050 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5051 ac_declare_lds_as_pointer(&ctx->ac);
5052 }
5053
5054 /**
5055 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5056 * for later use.
5057 */
5058 static void preload_ring_buffers(struct si_shader_context *ctx)
5059 {
5060 LLVMBuilderRef builder = ctx->ac.builder;
5061
5062 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5063 ctx->param_rw_buffers);
5064
5065 if (ctx->screen->info.chip_class <= VI &&
5066 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5067 unsigned ring =
5068 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5069 : SI_ES_RING_ESGS;
5070 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5071
5072 ctx->esgs_ring =
5073 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5074 }
5075
5076 if (ctx->shader->is_gs_copy_shader) {
5077 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5078
5079 ctx->gsvs_ring[0] =
5080 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5081 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5082 const struct si_shader_selector *sel = ctx->shader->selector;
5083 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5084 LLVMValueRef base_ring;
5085
5086 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5087
5088 /* The conceptual layout of the GSVS ring is
5089 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5090 * but the real memory layout is swizzled across
5091 * threads:
5092 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5093 * t16v0c0 ..
5094 * Override the buffer descriptor accordingly.
5095 */
5096 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5097 uint64_t stream_offset = 0;
5098
5099 for (unsigned stream = 0; stream < 4; ++stream) {
5100 unsigned num_components;
5101 unsigned stride;
5102 unsigned num_records;
5103 LLVMValueRef ring, tmp;
5104
5105 num_components = sel->info.num_stream_output_components[stream];
5106 if (!num_components)
5107 continue;
5108
5109 stride = 4 * num_components * sel->gs_max_out_vertices;
5110
5111 /* Limit on the stride field for <= CIK. */
5112 assert(stride < (1 << 14));
5113
5114 num_records = 64;
5115
5116 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5117 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5118 tmp = LLVMBuildAdd(builder, tmp,
5119 LLVMConstInt(ctx->i64,
5120 stream_offset, 0), "");
5121 stream_offset += stride * 64;
5122
5123 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5124 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5125 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5126 tmp = LLVMBuildOr(builder, tmp,
5127 LLVMConstInt(ctx->i32,
5128 S_008F04_STRIDE(stride) |
5129 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5130 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5131 ring = LLVMBuildInsertElement(builder, ring,
5132 LLVMConstInt(ctx->i32, num_records, 0),
5133 LLVMConstInt(ctx->i32, 2, 0), "");
5134 ring = LLVMBuildInsertElement(builder, ring,
5135 LLVMConstInt(ctx->i32,
5136 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5137 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5138 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5139 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5140 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5141 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5142 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5143 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5144 S_008F0C_ADD_TID_ENABLE(1),
5145 0),
5146 LLVMConstInt(ctx->i32, 3, 0), "");
5147
5148 ctx->gsvs_ring[stream] = ring;
5149 }
5150 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5151 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5152 }
5153 }
5154
5155 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5156 LLVMValueRef param_rw_buffers,
5157 unsigned param_pos_fixed_pt)
5158 {
5159 LLVMBuilderRef builder = ctx->ac.builder;
5160 LLVMValueRef slot, desc, offset, row, bit, address[2];
5161
5162 /* Use the fixed-point gl_FragCoord input.
5163 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5164 * per coordinate to get the repeating effect.
5165 */
5166 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5167 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5168
5169 /* Load the buffer descriptor. */
5170 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5171 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5172
5173 /* The stipple pattern is 32x32, each row has 32 bits. */
5174 offset = LLVMBuildMul(builder, address[1],
5175 LLVMConstInt(ctx->i32, 4, 0), "");
5176 row = buffer_load_const(ctx, desc, offset);
5177 row = ac_to_integer(&ctx->ac, row);
5178 bit = LLVMBuildLShr(builder, row, address[0], "");
5179 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5180 ac_build_kill_if_false(&ctx->ac, bit);
5181 }
5182
5183 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5184 struct si_shader_config *conf,
5185 unsigned symbol_offset)
5186 {
5187 unsigned i;
5188 const unsigned char *config =
5189 ac_shader_binary_config_start(binary, symbol_offset);
5190 bool really_needs_scratch = false;
5191
5192 /* LLVM adds SGPR spills to the scratch size.
5193 * Find out if we really need the scratch buffer.
5194 */
5195 for (i = 0; i < binary->reloc_count; i++) {
5196 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5197
5198 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5199 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5200 really_needs_scratch = true;
5201 break;
5202 }
5203 }
5204
5205 /* XXX: We may be able to emit some of these values directly rather than
5206 * extracting fields to be emitted later.
5207 */
5208
5209 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5210 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5211 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5212 switch (reg) {
5213 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5214 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5215 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5216 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5217 case R_00B848_COMPUTE_PGM_RSRC1:
5218 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5219 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5220 conf->float_mode = G_00B028_FLOAT_MODE(value);
5221 conf->rsrc1 = value;
5222 break;
5223 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5224 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5225 break;
5226 case R_00B84C_COMPUTE_PGM_RSRC2:
5227 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5228 conf->rsrc2 = value;
5229 break;
5230 case R_0286CC_SPI_PS_INPUT_ENA:
5231 conf->spi_ps_input_ena = value;
5232 break;
5233 case R_0286D0_SPI_PS_INPUT_ADDR:
5234 conf->spi_ps_input_addr = value;
5235 break;
5236 case R_0286E8_SPI_TMPRING_SIZE:
5237 case R_00B860_COMPUTE_TMPRING_SIZE:
5238 /* WAVESIZE is in units of 256 dwords. */
5239 if (really_needs_scratch)
5240 conf->scratch_bytes_per_wave =
5241 G_00B860_WAVESIZE(value) * 256 * 4;
5242 break;
5243 case 0x4: /* SPILLED_SGPRS */
5244 conf->spilled_sgprs = value;
5245 break;
5246 case 0x8: /* SPILLED_VGPRS */
5247 conf->spilled_vgprs = value;
5248 break;
5249 default:
5250 {
5251 static bool printed;
5252
5253 if (!printed) {
5254 fprintf(stderr, "Warning: LLVM emitted unknown "
5255 "config register: 0x%x\n", reg);
5256 printed = true;
5257 }
5258 }
5259 break;
5260 }
5261 }
5262
5263 if (!conf->spi_ps_input_addr)
5264 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5265 }
5266
5267 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5268 uint64_t scratch_va)
5269 {
5270 unsigned i;
5271 uint32_t scratch_rsrc_dword0 = scratch_va;
5272 uint32_t scratch_rsrc_dword1 =
5273 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5274
5275 /* Enable scratch coalescing. */
5276 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5277
5278 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5279 const struct ac_shader_reloc *reloc =
5280 &shader->binary.relocs[i];
5281 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5282 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5283 &scratch_rsrc_dword0, 4);
5284 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5285 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5286 &scratch_rsrc_dword1, 4);
5287 }
5288 }
5289 }
5290
5291 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5292 {
5293 unsigned size = shader->binary.code_size;
5294
5295 if (shader->prolog)
5296 size += shader->prolog->binary.code_size;
5297 if (shader->previous_stage)
5298 size += shader->previous_stage->binary.code_size;
5299 if (shader->prolog2)
5300 size += shader->prolog2->binary.code_size;
5301 if (shader->epilog)
5302 size += shader->epilog->binary.code_size;
5303 return size;
5304 }
5305
5306 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5307 {
5308 const struct ac_shader_binary *prolog =
5309 shader->prolog ? &shader->prolog->binary : NULL;
5310 const struct ac_shader_binary *previous_stage =
5311 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5312 const struct ac_shader_binary *prolog2 =
5313 shader->prolog2 ? &shader->prolog2->binary : NULL;
5314 const struct ac_shader_binary *epilog =
5315 shader->epilog ? &shader->epilog->binary : NULL;
5316 const struct ac_shader_binary *mainb = &shader->binary;
5317 unsigned bo_size = si_get_shader_binary_size(shader) +
5318 (!epilog ? mainb->rodata_size : 0);
5319 unsigned char *ptr;
5320
5321 assert(!prolog || !prolog->rodata_size);
5322 assert(!previous_stage || !previous_stage->rodata_size);
5323 assert(!prolog2 || !prolog2->rodata_size);
5324 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5325 !mainb->rodata_size);
5326 assert(!epilog || !epilog->rodata_size);
5327
5328 r600_resource_reference(&shader->bo, NULL);
5329 shader->bo = (struct r600_resource*)
5330 si_aligned_buffer_create(&sscreen->b,
5331 sscreen->cpdma_prefetch_writes_memory ?
5332 0 : R600_RESOURCE_FLAG_READ_ONLY,
5333 PIPE_USAGE_IMMUTABLE,
5334 align(bo_size, SI_CPDMA_ALIGNMENT),
5335 256);
5336 if (!shader->bo)
5337 return -ENOMEM;
5338
5339 /* Upload. */
5340 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5341 PIPE_TRANSFER_READ_WRITE |
5342 PIPE_TRANSFER_UNSYNCHRONIZED);
5343
5344 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5345 * endian-independent. */
5346 if (prolog) {
5347 memcpy(ptr, prolog->code, prolog->code_size);
5348 ptr += prolog->code_size;
5349 }
5350 if (previous_stage) {
5351 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5352 ptr += previous_stage->code_size;
5353 }
5354 if (prolog2) {
5355 memcpy(ptr, prolog2->code, prolog2->code_size);
5356 ptr += prolog2->code_size;
5357 }
5358
5359 memcpy(ptr, mainb->code, mainb->code_size);
5360 ptr += mainb->code_size;
5361
5362 if (epilog)
5363 memcpy(ptr, epilog->code, epilog->code_size);
5364 else if (mainb->rodata_size > 0)
5365 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5366
5367 sscreen->ws->buffer_unmap(shader->bo->buf);
5368 return 0;
5369 }
5370
5371 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5372 struct pipe_debug_callback *debug,
5373 const char *name, FILE *file)
5374 {
5375 char *line, *p;
5376 unsigned i, count;
5377
5378 if (binary->disasm_string) {
5379 fprintf(file, "Shader %s disassembly:\n", name);
5380 fprintf(file, "%s", binary->disasm_string);
5381
5382 if (debug && debug->debug_message) {
5383 /* Very long debug messages are cut off, so send the
5384 * disassembly one line at a time. This causes more
5385 * overhead, but on the plus side it simplifies
5386 * parsing of resulting logs.
5387 */
5388 pipe_debug_message(debug, SHADER_INFO,
5389 "Shader Disassembly Begin");
5390
5391 line = binary->disasm_string;
5392 while (*line) {
5393 p = util_strchrnul(line, '\n');
5394 count = p - line;
5395
5396 if (count) {
5397 pipe_debug_message(debug, SHADER_INFO,
5398 "%.*s", count, line);
5399 }
5400
5401 if (!*p)
5402 break;
5403 line = p + 1;
5404 }
5405
5406 pipe_debug_message(debug, SHADER_INFO,
5407 "Shader Disassembly End");
5408 }
5409 } else {
5410 fprintf(file, "Shader %s binary:\n", name);
5411 for (i = 0; i < binary->code_size; i += 4) {
5412 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5413 binary->code[i + 3], binary->code[i + 2],
5414 binary->code[i + 1], binary->code[i]);
5415 }
5416 }
5417 }
5418
5419 static void si_calculate_max_simd_waves(struct si_shader *shader)
5420 {
5421 struct si_screen *sscreen = shader->selector->screen;
5422 struct si_shader_config *conf = &shader->config;
5423 unsigned num_inputs = shader->selector->info.num_inputs;
5424 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5425 unsigned lds_per_wave = 0;
5426 unsigned max_simd_waves;
5427
5428 switch (sscreen->info.family) {
5429 /* These always have 8 waves: */
5430 case CHIP_POLARIS10:
5431 case CHIP_POLARIS11:
5432 case CHIP_POLARIS12:
5433 max_simd_waves = 8;
5434 break;
5435 default:
5436 max_simd_waves = 10;
5437 }
5438
5439 /* Compute LDS usage for PS. */
5440 switch (shader->selector->type) {
5441 case PIPE_SHADER_FRAGMENT:
5442 /* The minimum usage per wave is (num_inputs * 48). The maximum
5443 * usage is (num_inputs * 48 * 16).
5444 * We can get anything in between and it varies between waves.
5445 *
5446 * The 48 bytes per input for a single primitive is equal to
5447 * 4 bytes/component * 4 components/input * 3 points.
5448 *
5449 * Other stages don't know the size at compile time or don't
5450 * allocate LDS per wave, but instead they do it per thread group.
5451 */
5452 lds_per_wave = conf->lds_size * lds_increment +
5453 align(num_inputs * 48, lds_increment);
5454 break;
5455 case PIPE_SHADER_COMPUTE:
5456 if (shader->selector) {
5457 unsigned max_workgroup_size =
5458 si_get_max_workgroup_size(shader);
5459 lds_per_wave = (conf->lds_size * lds_increment) /
5460 DIV_ROUND_UP(max_workgroup_size, 64);
5461 }
5462 break;
5463 }
5464
5465 /* Compute the per-SIMD wave counts. */
5466 if (conf->num_sgprs) {
5467 if (sscreen->info.chip_class >= VI)
5468 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5469 else
5470 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5471 }
5472
5473 if (conf->num_vgprs)
5474 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5475
5476 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5477 * 16KB makes some SIMDs unoccupied). */
5478 if (lds_per_wave)
5479 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5480
5481 conf->max_simd_waves = max_simd_waves;
5482 }
5483
5484 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5485 struct pipe_debug_callback *debug)
5486 {
5487 const struct si_shader_config *conf = &shader->config;
5488
5489 pipe_debug_message(debug, SHADER_INFO,
5490 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5491 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5492 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5493 conf->num_sgprs, conf->num_vgprs,
5494 si_get_shader_binary_size(shader),
5495 conf->lds_size, conf->scratch_bytes_per_wave,
5496 conf->max_simd_waves, conf->spilled_sgprs,
5497 conf->spilled_vgprs, conf->private_mem_vgprs);
5498 }
5499
5500 static void si_shader_dump_stats(struct si_screen *sscreen,
5501 const struct si_shader *shader,
5502 unsigned processor,
5503 FILE *file,
5504 bool check_debug_option)
5505 {
5506 const struct si_shader_config *conf = &shader->config;
5507
5508 if (!check_debug_option ||
5509 si_can_dump_shader(sscreen, processor)) {
5510 if (processor == PIPE_SHADER_FRAGMENT) {
5511 fprintf(file, "*** SHADER CONFIG ***\n"
5512 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5513 "SPI_PS_INPUT_ENA = 0x%04x\n",
5514 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5515 }
5516
5517 fprintf(file, "*** SHADER STATS ***\n"
5518 "SGPRS: %d\n"
5519 "VGPRS: %d\n"
5520 "Spilled SGPRs: %d\n"
5521 "Spilled VGPRs: %d\n"
5522 "Private memory VGPRs: %d\n"
5523 "Code Size: %d bytes\n"
5524 "LDS: %d blocks\n"
5525 "Scratch: %d bytes per wave\n"
5526 "Max Waves: %d\n"
5527 "********************\n\n\n",
5528 conf->num_sgprs, conf->num_vgprs,
5529 conf->spilled_sgprs, conf->spilled_vgprs,
5530 conf->private_mem_vgprs,
5531 si_get_shader_binary_size(shader),
5532 conf->lds_size, conf->scratch_bytes_per_wave,
5533 conf->max_simd_waves);
5534 }
5535 }
5536
5537 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5538 {
5539 switch (processor) {
5540 case PIPE_SHADER_VERTEX:
5541 if (shader->key.as_es)
5542 return "Vertex Shader as ES";
5543 else if (shader->key.as_ls)
5544 return "Vertex Shader as LS";
5545 else
5546 return "Vertex Shader as VS";
5547 case PIPE_SHADER_TESS_CTRL:
5548 return "Tessellation Control Shader";
5549 case PIPE_SHADER_TESS_EVAL:
5550 if (shader->key.as_es)
5551 return "Tessellation Evaluation Shader as ES";
5552 else
5553 return "Tessellation Evaluation Shader as VS";
5554 case PIPE_SHADER_GEOMETRY:
5555 if (shader->is_gs_copy_shader)
5556 return "GS Copy Shader as VS";
5557 else
5558 return "Geometry Shader";
5559 case PIPE_SHADER_FRAGMENT:
5560 return "Pixel Shader";
5561 case PIPE_SHADER_COMPUTE:
5562 return "Compute Shader";
5563 default:
5564 return "Unknown Shader";
5565 }
5566 }
5567
5568 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5569 struct pipe_debug_callback *debug, unsigned processor,
5570 FILE *file, bool check_debug_option)
5571 {
5572 if (!check_debug_option ||
5573 si_can_dump_shader(sscreen, processor))
5574 si_dump_shader_key(processor, shader, file);
5575
5576 if (!check_debug_option && shader->binary.llvm_ir_string) {
5577 if (shader->previous_stage &&
5578 shader->previous_stage->binary.llvm_ir_string) {
5579 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5580 si_get_shader_name(shader, processor));
5581 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5582 }
5583
5584 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5585 si_get_shader_name(shader, processor));
5586 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5587 }
5588
5589 if (!check_debug_option ||
5590 (si_can_dump_shader(sscreen, processor) &&
5591 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5592 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5593
5594 if (shader->prolog)
5595 si_shader_dump_disassembly(&shader->prolog->binary,
5596 debug, "prolog", file);
5597 if (shader->previous_stage)
5598 si_shader_dump_disassembly(&shader->previous_stage->binary,
5599 debug, "previous stage", file);
5600 if (shader->prolog2)
5601 si_shader_dump_disassembly(&shader->prolog2->binary,
5602 debug, "prolog2", file);
5603
5604 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5605
5606 if (shader->epilog)
5607 si_shader_dump_disassembly(&shader->epilog->binary,
5608 debug, "epilog", file);
5609 fprintf(file, "\n");
5610 }
5611
5612 si_shader_dump_stats(sscreen, shader, processor, file,
5613 check_debug_option);
5614 }
5615
5616 static int si_compile_llvm(struct si_screen *sscreen,
5617 struct ac_shader_binary *binary,
5618 struct si_shader_config *conf,
5619 LLVMTargetMachineRef tm,
5620 LLVMModuleRef mod,
5621 struct pipe_debug_callback *debug,
5622 unsigned processor,
5623 const char *name)
5624 {
5625 int r = 0;
5626 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5627
5628 if (si_can_dump_shader(sscreen, processor)) {
5629 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5630
5631 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5632 fprintf(stderr, "%s LLVM IR:\n\n", name);
5633 ac_dump_module(mod);
5634 fprintf(stderr, "\n");
5635 }
5636 }
5637
5638 if (sscreen->record_llvm_ir) {
5639 char *ir = LLVMPrintModuleToString(mod);
5640 binary->llvm_ir_string = strdup(ir);
5641 LLVMDisposeMessage(ir);
5642 }
5643
5644 if (!si_replace_shader(count, binary)) {
5645 r = si_llvm_compile(mod, binary, tm, debug);
5646 if (r)
5647 return r;
5648 }
5649
5650 si_shader_binary_read_config(binary, conf, 0);
5651
5652 /* Enable 64-bit and 16-bit denormals, because there is no performance
5653 * cost.
5654 *
5655 * If denormals are enabled, all floating-point output modifiers are
5656 * ignored.
5657 *
5658 * Don't enable denormals for 32-bit floats, because:
5659 * - Floating-point output modifiers would be ignored by the hw.
5660 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5661 * have to stop using those.
5662 * - SI & CI would be very slow.
5663 */
5664 conf->float_mode |= V_00B028_FP_64_DENORMS;
5665
5666 FREE(binary->config);
5667 FREE(binary->global_symbol_offsets);
5668 binary->config = NULL;
5669 binary->global_symbol_offsets = NULL;
5670
5671 /* Some shaders can't have rodata because their binaries can be
5672 * concatenated.
5673 */
5674 if (binary->rodata_size &&
5675 (processor == PIPE_SHADER_VERTEX ||
5676 processor == PIPE_SHADER_TESS_CTRL ||
5677 processor == PIPE_SHADER_TESS_EVAL ||
5678 processor == PIPE_SHADER_FRAGMENT)) {
5679 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5680 return -EINVAL;
5681 }
5682
5683 return r;
5684 }
5685
5686 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5687 {
5688 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5689 LLVMBuildRetVoid(ctx->ac.builder);
5690 else
5691 LLVMBuildRet(ctx->ac.builder, ret);
5692 }
5693
5694 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5695 struct si_shader *
5696 si_generate_gs_copy_shader(struct si_screen *sscreen,
5697 LLVMTargetMachineRef tm,
5698 struct si_shader_selector *gs_selector,
5699 struct pipe_debug_callback *debug)
5700 {
5701 struct si_shader_context ctx;
5702 struct si_shader *shader;
5703 LLVMBuilderRef builder;
5704 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5705 struct lp_build_context *uint = &bld_base->uint_bld;
5706 struct si_shader_output_values *outputs;
5707 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5708 int i, r;
5709
5710 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5711
5712 if (!outputs)
5713 return NULL;
5714
5715 shader = CALLOC_STRUCT(si_shader);
5716 if (!shader) {
5717 FREE(outputs);
5718 return NULL;
5719 }
5720
5721 /* We can leave the fence as permanently signaled because the GS copy
5722 * shader only becomes visible globally after it has been compiled. */
5723 util_queue_fence_init(&shader->ready);
5724
5725 shader->selector = gs_selector;
5726 shader->is_gs_copy_shader = true;
5727
5728 si_init_shader_ctx(&ctx, sscreen, tm);
5729 ctx.shader = shader;
5730 ctx.type = PIPE_SHADER_VERTEX;
5731
5732 builder = ctx.ac.builder;
5733
5734 create_function(&ctx);
5735 preload_ring_buffers(&ctx);
5736
5737 LLVMValueRef voffset =
5738 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5739
5740 /* Fetch the vertex stream ID.*/
5741 LLVMValueRef stream_id;
5742
5743 if (gs_selector->so.num_outputs)
5744 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5745 else
5746 stream_id = ctx.i32_0;
5747
5748 /* Fill in output information. */
5749 for (i = 0; i < gsinfo->num_outputs; ++i) {
5750 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5751 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5752
5753 for (int chan = 0; chan < 4; chan++) {
5754 outputs[i].vertex_stream[chan] =
5755 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5756 }
5757 }
5758
5759 LLVMBasicBlockRef end_bb;
5760 LLVMValueRef switch_inst;
5761
5762 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5763 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5764
5765 for (int stream = 0; stream < 4; stream++) {
5766 LLVMBasicBlockRef bb;
5767 unsigned offset;
5768
5769 if (!gsinfo->num_stream_output_components[stream])
5770 continue;
5771
5772 if (stream > 0 && !gs_selector->so.num_outputs)
5773 continue;
5774
5775 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5776 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5777 LLVMPositionBuilderAtEnd(builder, bb);
5778
5779 /* Fetch vertex data from GSVS ring */
5780 offset = 0;
5781 for (i = 0; i < gsinfo->num_outputs; ++i) {
5782 for (unsigned chan = 0; chan < 4; chan++) {
5783 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5784 outputs[i].vertex_stream[chan] != stream) {
5785 outputs[i].values[chan] = ctx.bld_base.base.undef;
5786 continue;
5787 }
5788
5789 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5790 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5791 offset++;
5792
5793 outputs[i].values[chan] =
5794 ac_build_buffer_load(&ctx.ac,
5795 ctx.gsvs_ring[0], 1,
5796 ctx.i32_0, voffset,
5797 soffset, 0, 1, 1,
5798 true, false);
5799 }
5800 }
5801
5802 /* Streamout and exports. */
5803 if (gs_selector->so.num_outputs) {
5804 si_llvm_emit_streamout(&ctx, outputs,
5805 gsinfo->num_outputs,
5806 stream);
5807 }
5808
5809 if (stream == 0)
5810 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5811
5812 LLVMBuildBr(builder, end_bb);
5813 }
5814
5815 LLVMPositionBuilderAtEnd(builder, end_bb);
5816
5817 LLVMBuildRetVoid(ctx.ac.builder);
5818
5819 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5820 si_llvm_optimize_module(&ctx);
5821
5822 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5823 &ctx.shader->config, ctx.tm,
5824 ctx.gallivm.module,
5825 debug, PIPE_SHADER_GEOMETRY,
5826 "GS Copy Shader");
5827 if (!r) {
5828 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5829 fprintf(stderr, "GS Copy Shader:\n");
5830 si_shader_dump(sscreen, ctx.shader, debug,
5831 PIPE_SHADER_GEOMETRY, stderr, true);
5832 r = si_shader_binary_upload(sscreen, ctx.shader);
5833 }
5834
5835 si_llvm_dispose(&ctx);
5836
5837 FREE(outputs);
5838
5839 if (r != 0) {
5840 FREE(shader);
5841 shader = NULL;
5842 }
5843 return shader;
5844 }
5845
5846 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5847 const struct si_vs_prolog_bits *prolog,
5848 const char *prefix, FILE *f)
5849 {
5850 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5851 prefix, prolog->instance_divisor_is_one);
5852 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5853 prefix, prolog->instance_divisor_is_fetched);
5854 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5855 prefix, prolog->ls_vgpr_fix);
5856
5857 fprintf(f, " mono.vs.fix_fetch = {");
5858 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5859 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5860 fprintf(f, "}\n");
5861 }
5862
5863 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5864 FILE *f)
5865 {
5866 const struct si_shader_key *key = &shader->key;
5867
5868 fprintf(f, "SHADER KEY\n");
5869
5870 switch (processor) {
5871 case PIPE_SHADER_VERTEX:
5872 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5873 "part.vs.prolog", f);
5874 fprintf(f, " as_es = %u\n", key->as_es);
5875 fprintf(f, " as_ls = %u\n", key->as_ls);
5876 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5877 key->mono.u.vs_export_prim_id);
5878 break;
5879
5880 case PIPE_SHADER_TESS_CTRL:
5881 if (shader->selector->screen->info.chip_class >= GFX9) {
5882 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5883 "part.tcs.ls_prolog", f);
5884 }
5885 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5886 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5887 break;
5888
5889 case PIPE_SHADER_TESS_EVAL:
5890 fprintf(f, " as_es = %u\n", key->as_es);
5891 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5892 key->mono.u.vs_export_prim_id);
5893 break;
5894
5895 case PIPE_SHADER_GEOMETRY:
5896 if (shader->is_gs_copy_shader)
5897 break;
5898
5899 if (shader->selector->screen->info.chip_class >= GFX9 &&
5900 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5901 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5902 "part.gs.vs_prolog", f);
5903 }
5904 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5905 break;
5906
5907 case PIPE_SHADER_COMPUTE:
5908 break;
5909
5910 case PIPE_SHADER_FRAGMENT:
5911 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5912 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5913 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5914 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5915 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5916 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5917 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5918 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5919 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5920 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5921 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5922 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5923 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5924 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5925 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5926 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5927 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5928 break;
5929
5930 default:
5931 assert(0);
5932 }
5933
5934 if ((processor == PIPE_SHADER_GEOMETRY ||
5935 processor == PIPE_SHADER_TESS_EVAL ||
5936 processor == PIPE_SHADER_VERTEX) &&
5937 !key->as_es && !key->as_ls) {
5938 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5939 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5940 }
5941 }
5942
5943 static void si_init_shader_ctx(struct si_shader_context *ctx,
5944 struct si_screen *sscreen,
5945 LLVMTargetMachineRef tm)
5946 {
5947 struct lp_build_tgsi_context *bld_base;
5948
5949 si_llvm_context_init(ctx, sscreen, tm);
5950
5951 bld_base = &ctx->bld_base;
5952 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5953
5954 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5955 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5956 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5957
5958 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5959
5960 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5961
5962 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5963 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5964 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5965 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5966
5967 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5968 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5969 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5970 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5971 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5972 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5973 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5974 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5975 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5976
5977 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5978 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5979 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5980 }
5981
5982 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5983 {
5984 struct si_shader *shader = ctx->shader;
5985 struct tgsi_shader_info *info = &shader->selector->info;
5986
5987 if ((ctx->type != PIPE_SHADER_VERTEX &&
5988 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5989 shader->key.as_ls ||
5990 shader->key.as_es)
5991 return;
5992
5993 ac_optimize_vs_outputs(&ctx->ac,
5994 ctx->main_fn,
5995 shader->info.vs_output_param_offset,
5996 info->num_outputs,
5997 &shader->info.nr_param_exports);
5998 }
5999
6000 static void si_init_exec_from_input(struct si_shader_context *ctx,
6001 unsigned param, unsigned bitoffset)
6002 {
6003 LLVMValueRef args[] = {
6004 LLVMGetParam(ctx->main_fn, param),
6005 LLVMConstInt(ctx->i32, bitoffset, 0),
6006 };
6007 lp_build_intrinsic(ctx->ac.builder,
6008 "llvm.amdgcn.init.exec.from.input",
6009 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
6010 }
6011
6012 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6013 const struct si_vs_prolog_bits *key)
6014 {
6015 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6016 * VS prolog. */
6017 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6018 }
6019
6020 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6021 bool is_monolithic)
6022 {
6023 struct si_shader *shader = ctx->shader;
6024 struct si_shader_selector *sel = shader->selector;
6025 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6026
6027 // TODO clean all this up!
6028 switch (ctx->type) {
6029 case PIPE_SHADER_VERTEX:
6030 ctx->load_input = declare_input_vs;
6031 if (shader->key.as_ls)
6032 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6033 else if (shader->key.as_es)
6034 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6035 else
6036 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6037 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6038 ctx->abi.load_base_vertex = get_base_vertex;
6039 break;
6040 case PIPE_SHADER_TESS_CTRL:
6041 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6042 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6043 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6044 bld_base->emit_store = store_output_tcs;
6045 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6046 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6047 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6048 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6049 break;
6050 case PIPE_SHADER_TESS_EVAL:
6051 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6052 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6053 ctx->abi.load_tess_coord = si_load_tess_coord;
6054 ctx->abi.load_tess_level = si_load_tess_level;
6055 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6056 if (shader->key.as_es)
6057 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6058 else
6059 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6060 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6061 break;
6062 case PIPE_SHADER_GEOMETRY:
6063 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6064 ctx->abi.load_inputs = si_nir_load_input_gs;
6065 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6066 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6067 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6068 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6069 break;
6070 case PIPE_SHADER_FRAGMENT:
6071 ctx->load_input = declare_input_fs;
6072 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6073 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6074 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6075 ctx->abi.load_sample_position = load_sample_position;
6076 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6077 ctx->abi.emit_kill = si_llvm_emit_kill;
6078 break;
6079 case PIPE_SHADER_COMPUTE:
6080 ctx->abi.load_local_group_size = get_block_size;
6081 break;
6082 default:
6083 assert(!"Unsupported shader type");
6084 return false;
6085 }
6086
6087 ctx->abi.load_ubo = load_ubo;
6088 ctx->abi.load_ssbo = load_ssbo;
6089
6090 create_function(ctx);
6091 preload_ring_buffers(ctx);
6092
6093 /* For GFX9 merged shaders:
6094 * - Set EXEC for the first shader. If the prolog is present, set
6095 * EXEC there instead.
6096 * - Add a barrier before the second shader.
6097 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6098 * an if-statement. This is required for correctness in geometry
6099 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6100 * GS_CUT messages.
6101 *
6102 * For monolithic merged shaders, the first shader is wrapped in an
6103 * if-block together with its prolog in si_build_wrapper_function.
6104 */
6105 if (ctx->screen->info.chip_class >= GFX9) {
6106 if (!is_monolithic &&
6107 sel->info.num_instructions > 1 && /* not empty shader */
6108 (shader->key.as_es || shader->key.as_ls) &&
6109 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6110 (ctx->type == PIPE_SHADER_VERTEX &&
6111 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6112 si_init_exec_from_input(ctx,
6113 ctx->param_merged_wave_info, 0);
6114 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6115 ctx->type == PIPE_SHADER_GEOMETRY) {
6116 if (!is_monolithic)
6117 ac_init_exec_full_mask(&ctx->ac);
6118
6119 /* The barrier must execute for all shaders in a
6120 * threadgroup.
6121 */
6122 si_llvm_emit_barrier(NULL, bld_base, NULL);
6123
6124 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6125 LLVMValueRef ena =
6126 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6127 ac_get_thread_id(&ctx->ac), num_threads, "");
6128 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6129 }
6130 }
6131
6132 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6133 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6134 for (unsigned i = 0; i < 6; i++) {
6135 ctx->invoc0_tess_factors[i] =
6136 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6137 }
6138 }
6139
6140 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6141 int i;
6142 for (i = 0; i < 4; i++) {
6143 ctx->gs_next_vertex[i] =
6144 lp_build_alloca(&ctx->gallivm,
6145 ctx->i32, "");
6146 }
6147 }
6148
6149 if (sel->force_correct_derivs_after_kill) {
6150 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6151 /* true = don't kill. */
6152 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6153 ctx->postponed_kill);
6154 }
6155
6156 if (sel->tokens) {
6157 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6158 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6159 return false;
6160 }
6161 } else {
6162 if (!si_nir_build_llvm(ctx, sel->nir)) {
6163 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6164 return false;
6165 }
6166 }
6167
6168 si_llvm_build_ret(ctx, ctx->return_value);
6169 return true;
6170 }
6171
6172 /**
6173 * Compute the VS prolog key, which contains all the information needed to
6174 * build the VS prolog function, and set shader->info bits where needed.
6175 *
6176 * \param info Shader info of the vertex shader.
6177 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6178 * \param prolog_key Key of the VS prolog
6179 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6180 * \param key Output shader part key.
6181 */
6182 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6183 unsigned num_input_sgprs,
6184 const struct si_vs_prolog_bits *prolog_key,
6185 struct si_shader *shader_out,
6186 union si_shader_part_key *key)
6187 {
6188 memset(key, 0, sizeof(*key));
6189 key->vs_prolog.states = *prolog_key;
6190 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6191 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6192 key->vs_prolog.as_ls = shader_out->key.as_ls;
6193 key->vs_prolog.as_es = shader_out->key.as_es;
6194
6195 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6196 key->vs_prolog.as_ls = 1;
6197 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6198 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6199 key->vs_prolog.as_es = 1;
6200 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6201 }
6202
6203 /* Enable loading the InstanceID VGPR. */
6204 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6205
6206 if ((key->vs_prolog.states.instance_divisor_is_one |
6207 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6208 shader_out->info.uses_instanceid = true;
6209 }
6210
6211 /**
6212 * Compute the PS prolog key, which contains all the information needed to
6213 * build the PS prolog function, and set related bits in shader->config.
6214 */
6215 static void si_get_ps_prolog_key(struct si_shader *shader,
6216 union si_shader_part_key *key,
6217 bool separate_prolog)
6218 {
6219 struct tgsi_shader_info *info = &shader->selector->info;
6220
6221 memset(key, 0, sizeof(*key));
6222 key->ps_prolog.states = shader->key.part.ps.prolog;
6223 key->ps_prolog.colors_read = info->colors_read;
6224 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6225 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6226 key->ps_prolog.wqm = info->uses_derivatives &&
6227 (key->ps_prolog.colors_read ||
6228 key->ps_prolog.states.force_persp_sample_interp ||
6229 key->ps_prolog.states.force_linear_sample_interp ||
6230 key->ps_prolog.states.force_persp_center_interp ||
6231 key->ps_prolog.states.force_linear_center_interp ||
6232 key->ps_prolog.states.bc_optimize_for_persp ||
6233 key->ps_prolog.states.bc_optimize_for_linear);
6234 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6235
6236 if (info->colors_read) {
6237 unsigned *color = shader->selector->color_attr_index;
6238
6239 if (shader->key.part.ps.prolog.color_two_side) {
6240 /* BCOLORs are stored after the last input. */
6241 key->ps_prolog.num_interp_inputs = info->num_inputs;
6242 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6243 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6244 }
6245
6246 for (unsigned i = 0; i < 2; i++) {
6247 unsigned interp = info->input_interpolate[color[i]];
6248 unsigned location = info->input_interpolate_loc[color[i]];
6249
6250 if (!(info->colors_read & (0xf << i*4)))
6251 continue;
6252
6253 key->ps_prolog.color_attr_index[i] = color[i];
6254
6255 if (shader->key.part.ps.prolog.flatshade_colors &&
6256 interp == TGSI_INTERPOLATE_COLOR)
6257 interp = TGSI_INTERPOLATE_CONSTANT;
6258
6259 switch (interp) {
6260 case TGSI_INTERPOLATE_CONSTANT:
6261 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6262 break;
6263 case TGSI_INTERPOLATE_PERSPECTIVE:
6264 case TGSI_INTERPOLATE_COLOR:
6265 /* Force the interpolation location for colors here. */
6266 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6267 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6268 if (shader->key.part.ps.prolog.force_persp_center_interp)
6269 location = TGSI_INTERPOLATE_LOC_CENTER;
6270
6271 switch (location) {
6272 case TGSI_INTERPOLATE_LOC_SAMPLE:
6273 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6274 shader->config.spi_ps_input_ena |=
6275 S_0286CC_PERSP_SAMPLE_ENA(1);
6276 break;
6277 case TGSI_INTERPOLATE_LOC_CENTER:
6278 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6279 shader->config.spi_ps_input_ena |=
6280 S_0286CC_PERSP_CENTER_ENA(1);
6281 break;
6282 case TGSI_INTERPOLATE_LOC_CENTROID:
6283 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6284 shader->config.spi_ps_input_ena |=
6285 S_0286CC_PERSP_CENTROID_ENA(1);
6286 break;
6287 default:
6288 assert(0);
6289 }
6290 break;
6291 case TGSI_INTERPOLATE_LINEAR:
6292 /* Force the interpolation location for colors here. */
6293 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6294 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6295 if (shader->key.part.ps.prolog.force_linear_center_interp)
6296 location = TGSI_INTERPOLATE_LOC_CENTER;
6297
6298 /* The VGPR assignment for non-monolithic shaders
6299 * works because InitialPSInputAddr is set on the
6300 * main shader and PERSP_PULL_MODEL is never used.
6301 */
6302 switch (location) {
6303 case TGSI_INTERPOLATE_LOC_SAMPLE:
6304 key->ps_prolog.color_interp_vgpr_index[i] =
6305 separate_prolog ? 6 : 9;
6306 shader->config.spi_ps_input_ena |=
6307 S_0286CC_LINEAR_SAMPLE_ENA(1);
6308 break;
6309 case TGSI_INTERPOLATE_LOC_CENTER:
6310 key->ps_prolog.color_interp_vgpr_index[i] =
6311 separate_prolog ? 8 : 11;
6312 shader->config.spi_ps_input_ena |=
6313 S_0286CC_LINEAR_CENTER_ENA(1);
6314 break;
6315 case TGSI_INTERPOLATE_LOC_CENTROID:
6316 key->ps_prolog.color_interp_vgpr_index[i] =
6317 separate_prolog ? 10 : 13;
6318 shader->config.spi_ps_input_ena |=
6319 S_0286CC_LINEAR_CENTROID_ENA(1);
6320 break;
6321 default:
6322 assert(0);
6323 }
6324 break;
6325 default:
6326 assert(0);
6327 }
6328 }
6329 }
6330 }
6331
6332 /**
6333 * Check whether a PS prolog is required based on the key.
6334 */
6335 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6336 {
6337 return key->ps_prolog.colors_read ||
6338 key->ps_prolog.states.force_persp_sample_interp ||
6339 key->ps_prolog.states.force_linear_sample_interp ||
6340 key->ps_prolog.states.force_persp_center_interp ||
6341 key->ps_prolog.states.force_linear_center_interp ||
6342 key->ps_prolog.states.bc_optimize_for_persp ||
6343 key->ps_prolog.states.bc_optimize_for_linear ||
6344 key->ps_prolog.states.poly_stipple ||
6345 key->ps_prolog.states.samplemask_log_ps_iter;
6346 }
6347
6348 /**
6349 * Compute the PS epilog key, which contains all the information needed to
6350 * build the PS epilog function.
6351 */
6352 static void si_get_ps_epilog_key(struct si_shader *shader,
6353 union si_shader_part_key *key)
6354 {
6355 struct tgsi_shader_info *info = &shader->selector->info;
6356 memset(key, 0, sizeof(*key));
6357 key->ps_epilog.colors_written = info->colors_written;
6358 key->ps_epilog.writes_z = info->writes_z;
6359 key->ps_epilog.writes_stencil = info->writes_stencil;
6360 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6361 key->ps_epilog.states = shader->key.part.ps.epilog;
6362 }
6363
6364 /**
6365 * Build the GS prolog function. Rotate the input vertices for triangle strips
6366 * with adjacency.
6367 */
6368 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6369 union si_shader_part_key *key)
6370 {
6371 unsigned num_sgprs, num_vgprs;
6372 struct si_function_info fninfo;
6373 LLVMBuilderRef builder = ctx->ac.builder;
6374 LLVMTypeRef returns[48];
6375 LLVMValueRef func, ret;
6376
6377 si_init_function_info(&fninfo);
6378
6379 if (ctx->screen->info.chip_class >= GFX9) {
6380 if (key->gs_prolog.states.gfx9_prev_is_vs)
6381 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6382 else
6383 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6384 num_vgprs = 5; /* ES inputs are not needed by GS */
6385 } else {
6386 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6387 num_vgprs = 8;
6388 }
6389
6390 for (unsigned i = 0; i < num_sgprs; ++i) {
6391 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6392 returns[i] = ctx->i32;
6393 }
6394
6395 for (unsigned i = 0; i < num_vgprs; ++i) {
6396 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6397 returns[num_sgprs + i] = ctx->f32;
6398 }
6399
6400 /* Create the function. */
6401 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6402 &fninfo, 0);
6403 func = ctx->main_fn;
6404
6405 /* Set the full EXEC mask for the prolog, because we are only fiddling
6406 * with registers here. The main shader part will set the correct EXEC
6407 * mask.
6408 */
6409 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6410 ac_init_exec_full_mask(&ctx->ac);
6411
6412 /* Copy inputs to outputs. This should be no-op, as the registers match,
6413 * but it will prevent the compiler from overwriting them unintentionally.
6414 */
6415 ret = ctx->return_value;
6416 for (unsigned i = 0; i < num_sgprs; i++) {
6417 LLVMValueRef p = LLVMGetParam(func, i);
6418 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6419 }
6420 for (unsigned i = 0; i < num_vgprs; i++) {
6421 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6422 p = ac_to_float(&ctx->ac, p);
6423 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6424 }
6425
6426 if (key->gs_prolog.states.tri_strip_adj_fix) {
6427 /* Remap the input vertices for every other primitive. */
6428 const unsigned gfx6_vtx_params[6] = {
6429 num_sgprs,
6430 num_sgprs + 1,
6431 num_sgprs + 3,
6432 num_sgprs + 4,
6433 num_sgprs + 5,
6434 num_sgprs + 6
6435 };
6436 const unsigned gfx9_vtx_params[3] = {
6437 num_sgprs,
6438 num_sgprs + 1,
6439 num_sgprs + 4,
6440 };
6441 LLVMValueRef vtx_in[6], vtx_out[6];
6442 LLVMValueRef prim_id, rotate;
6443
6444 if (ctx->screen->info.chip_class >= GFX9) {
6445 for (unsigned i = 0; i < 3; i++) {
6446 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6447 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6448 }
6449 } else {
6450 for (unsigned i = 0; i < 6; i++)
6451 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6452 }
6453
6454 prim_id = LLVMGetParam(func, num_sgprs + 2);
6455 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6456
6457 for (unsigned i = 0; i < 6; ++i) {
6458 LLVMValueRef base, rotated;
6459 base = vtx_in[i];
6460 rotated = vtx_in[(i + 4) % 6];
6461 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6462 }
6463
6464 if (ctx->screen->info.chip_class >= GFX9) {
6465 for (unsigned i = 0; i < 3; i++) {
6466 LLVMValueRef hi, out;
6467
6468 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6469 LLVMConstInt(ctx->i32, 16, 0), "");
6470 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6471 out = ac_to_float(&ctx->ac, out);
6472 ret = LLVMBuildInsertValue(builder, ret, out,
6473 gfx9_vtx_params[i], "");
6474 }
6475 } else {
6476 for (unsigned i = 0; i < 6; i++) {
6477 LLVMValueRef out;
6478
6479 out = ac_to_float(&ctx->ac, vtx_out[i]);
6480 ret = LLVMBuildInsertValue(builder, ret, out,
6481 gfx6_vtx_params[i], "");
6482 }
6483 }
6484 }
6485
6486 LLVMBuildRet(builder, ret);
6487 }
6488
6489 /**
6490 * Given a list of shader part functions, build a wrapper function that
6491 * runs them in sequence to form a monolithic shader.
6492 */
6493 static void si_build_wrapper_function(struct si_shader_context *ctx,
6494 LLVMValueRef *parts,
6495 unsigned num_parts,
6496 unsigned main_part,
6497 unsigned next_shader_first_part)
6498 {
6499 LLVMBuilderRef builder = ctx->ac.builder;
6500 /* PS epilog has one arg per color component; gfx9 merged shader
6501 * prologs need to forward 32 user SGPRs.
6502 */
6503 struct si_function_info fninfo;
6504 LLVMValueRef initial[64], out[64];
6505 LLVMTypeRef function_type;
6506 unsigned num_first_params;
6507 unsigned num_out, initial_num_out;
6508 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6509 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6510 unsigned num_sgprs, num_vgprs;
6511 unsigned gprs;
6512 struct lp_build_if_state if_state;
6513
6514 si_init_function_info(&fninfo);
6515
6516 for (unsigned i = 0; i < num_parts; ++i) {
6517 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6518 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6519 }
6520
6521 /* The parameters of the wrapper function correspond to those of the
6522 * first part in terms of SGPRs and VGPRs, but we use the types of the
6523 * main part to get the right types. This is relevant for the
6524 * dereferenceable attribute on descriptor table pointers.
6525 */
6526 num_sgprs = 0;
6527 num_vgprs = 0;
6528
6529 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6530 num_first_params = LLVMCountParamTypes(function_type);
6531
6532 for (unsigned i = 0; i < num_first_params; ++i) {
6533 LLVMValueRef param = LLVMGetParam(parts[0], i);
6534
6535 if (ac_is_sgpr_param(param)) {
6536 assert(num_vgprs == 0);
6537 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6538 } else {
6539 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6540 }
6541 }
6542
6543 gprs = 0;
6544 while (gprs < num_sgprs + num_vgprs) {
6545 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6546 LLVMTypeRef type = LLVMTypeOf(param);
6547 unsigned size = ac_get_type_size(type) / 4;
6548
6549 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6550
6551 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6552 assert(gprs + size <= num_sgprs + num_vgprs &&
6553 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6554
6555 gprs += size;
6556 }
6557
6558 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6559 si_get_max_workgroup_size(ctx->shader));
6560
6561 if (is_merged_shader(ctx->shader))
6562 ac_init_exec_full_mask(&ctx->ac);
6563
6564 /* Record the arguments of the function as if they were an output of
6565 * a previous part.
6566 */
6567 num_out = 0;
6568 num_out_sgpr = 0;
6569
6570 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6571 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6572 LLVMTypeRef param_type = LLVMTypeOf(param);
6573 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6574 unsigned size = ac_get_type_size(param_type) / 4;
6575
6576 if (size == 1) {
6577 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6578 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6579 param_type = ctx->i32;
6580 }
6581
6582 if (param_type != out_type)
6583 param = LLVMBuildBitCast(builder, param, out_type, "");
6584 out[num_out++] = param;
6585 } else {
6586 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6587
6588 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6589 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6590 param_type = ctx->i64;
6591 }
6592
6593 if (param_type != vector_type)
6594 param = LLVMBuildBitCast(builder, param, vector_type, "");
6595
6596 for (unsigned j = 0; j < size; ++j)
6597 out[num_out++] = LLVMBuildExtractElement(
6598 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6599 }
6600
6601 if (i < fninfo.num_sgpr_params)
6602 num_out_sgpr = num_out;
6603 }
6604
6605 memcpy(initial, out, sizeof(out));
6606 initial_num_out = num_out;
6607 initial_num_out_sgpr = num_out_sgpr;
6608
6609 /* Now chain the parts. */
6610 for (unsigned part = 0; part < num_parts; ++part) {
6611 LLVMValueRef in[48];
6612 LLVMValueRef ret;
6613 LLVMTypeRef ret_type;
6614 unsigned out_idx = 0;
6615 unsigned num_params = LLVMCountParams(parts[part]);
6616
6617 /* Merged shaders are executed conditionally depending
6618 * on the number of enabled threads passed in the input SGPRs. */
6619 if (is_merged_shader(ctx->shader) && part == 0) {
6620 LLVMValueRef ena, count = initial[3];
6621
6622 count = LLVMBuildAnd(builder, count,
6623 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6624 ena = LLVMBuildICmp(builder, LLVMIntULT,
6625 ac_get_thread_id(&ctx->ac), count, "");
6626 lp_build_if(&if_state, &ctx->gallivm, ena);
6627 }
6628
6629 /* Derive arguments for the next part from outputs of the
6630 * previous one.
6631 */
6632 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6633 LLVMValueRef param;
6634 LLVMTypeRef param_type;
6635 bool is_sgpr;
6636 unsigned param_size;
6637 LLVMValueRef arg = NULL;
6638
6639 param = LLVMGetParam(parts[part], param_idx);
6640 param_type = LLVMTypeOf(param);
6641 param_size = ac_get_type_size(param_type) / 4;
6642 is_sgpr = ac_is_sgpr_param(param);
6643
6644 if (is_sgpr)
6645 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6646 else if (out_idx < num_out_sgpr) {
6647 /* Skip returned SGPRs the current part doesn't
6648 * declare on the input. */
6649 out_idx = num_out_sgpr;
6650 }
6651
6652 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6653
6654 if (param_size == 1)
6655 arg = out[out_idx];
6656 else
6657 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6658
6659 if (LLVMTypeOf(arg) != param_type) {
6660 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6661 if (LLVMGetPointerAddressSpace(param_type) ==
6662 AC_CONST_32BIT_ADDR_SPACE) {
6663 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6664 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6665 } else {
6666 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6667 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6668 }
6669 } else {
6670 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6671 }
6672 }
6673
6674 in[param_idx] = arg;
6675 out_idx += param_size;
6676 }
6677
6678 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6679
6680 if (is_merged_shader(ctx->shader) &&
6681 part + 1 == next_shader_first_part) {
6682 lp_build_endif(&if_state);
6683
6684 /* The second half of the merged shader should use
6685 * the inputs from the toplevel (wrapper) function,
6686 * not the return value from the last call.
6687 *
6688 * That's because the last call was executed condi-
6689 * tionally, so we can't consume it in the main
6690 * block.
6691 */
6692 memcpy(out, initial, sizeof(initial));
6693 num_out = initial_num_out;
6694 num_out_sgpr = initial_num_out_sgpr;
6695 continue;
6696 }
6697
6698 /* Extract the returned GPRs. */
6699 ret_type = LLVMTypeOf(ret);
6700 num_out = 0;
6701 num_out_sgpr = 0;
6702
6703 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6704 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6705
6706 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6707
6708 for (unsigned i = 0; i < ret_size; ++i) {
6709 LLVMValueRef val =
6710 LLVMBuildExtractValue(builder, ret, i, "");
6711
6712 assert(num_out < ARRAY_SIZE(out));
6713 out[num_out++] = val;
6714
6715 if (LLVMTypeOf(val) == ctx->i32) {
6716 assert(num_out_sgpr + 1 == num_out);
6717 num_out_sgpr = num_out;
6718 }
6719 }
6720 }
6721 }
6722
6723 LLVMBuildRetVoid(builder);
6724 }
6725
6726 int si_compile_tgsi_shader(struct si_screen *sscreen,
6727 LLVMTargetMachineRef tm,
6728 struct si_shader *shader,
6729 bool is_monolithic,
6730 struct pipe_debug_callback *debug)
6731 {
6732 struct si_shader_selector *sel = shader->selector;
6733 struct si_shader_context ctx;
6734 int r = -1;
6735
6736 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6737 * conversion fails. */
6738 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6739 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6740 if (sel->tokens)
6741 tgsi_dump(sel->tokens, 0);
6742 else
6743 nir_print_shader(sel->nir, stderr);
6744 si_dump_streamout(&sel->so);
6745 }
6746
6747 si_init_shader_ctx(&ctx, sscreen, tm);
6748 si_llvm_context_set_tgsi(&ctx, shader);
6749 ctx.separate_prolog = !is_monolithic;
6750
6751 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6752 sizeof(shader->info.vs_output_param_offset));
6753
6754 shader->info.uses_instanceid = sel->info.uses_instanceid;
6755
6756 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6757 si_llvm_dispose(&ctx);
6758 return -1;
6759 }
6760
6761 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6762 LLVMValueRef parts[2];
6763 bool need_prolog = sel->vs_needs_prolog;
6764
6765 parts[1] = ctx.main_fn;
6766
6767 if (need_prolog) {
6768 union si_shader_part_key prolog_key;
6769 si_get_vs_prolog_key(&sel->info,
6770 shader->info.num_input_sgprs,
6771 &shader->key.part.vs.prolog,
6772 shader, &prolog_key);
6773 si_build_vs_prolog_function(&ctx, &prolog_key);
6774 parts[0] = ctx.main_fn;
6775 }
6776
6777 si_build_wrapper_function(&ctx, parts + !need_prolog,
6778 1 + need_prolog, need_prolog, 0);
6779 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6780 if (sscreen->info.chip_class >= GFX9) {
6781 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6782 LLVMValueRef parts[4];
6783 bool vs_needs_prolog =
6784 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6785
6786 /* TCS main part */
6787 parts[2] = ctx.main_fn;
6788
6789 /* TCS epilog */
6790 union si_shader_part_key tcs_epilog_key;
6791 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6792 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6793 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6794 parts[3] = ctx.main_fn;
6795
6796 /* VS as LS main part */
6797 struct si_shader shader_ls = {};
6798 shader_ls.selector = ls;
6799 shader_ls.key.as_ls = 1;
6800 shader_ls.key.mono = shader->key.mono;
6801 shader_ls.key.opt = shader->key.opt;
6802 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6803
6804 if (!si_compile_tgsi_main(&ctx, true)) {
6805 si_llvm_dispose(&ctx);
6806 return -1;
6807 }
6808 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6809 parts[1] = ctx.main_fn;
6810
6811 /* LS prolog */
6812 if (vs_needs_prolog) {
6813 union si_shader_part_key vs_prolog_key;
6814 si_get_vs_prolog_key(&ls->info,
6815 shader_ls.info.num_input_sgprs,
6816 &shader->key.part.tcs.ls_prolog,
6817 shader, &vs_prolog_key);
6818 vs_prolog_key.vs_prolog.is_monolithic = true;
6819 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6820 parts[0] = ctx.main_fn;
6821 }
6822
6823 /* Reset the shader context. */
6824 ctx.shader = shader;
6825 ctx.type = PIPE_SHADER_TESS_CTRL;
6826
6827 si_build_wrapper_function(&ctx,
6828 parts + !vs_needs_prolog,
6829 4 - !vs_needs_prolog, 0,
6830 vs_needs_prolog ? 2 : 1);
6831 } else {
6832 LLVMValueRef parts[2];
6833 union si_shader_part_key epilog_key;
6834
6835 parts[0] = ctx.main_fn;
6836
6837 memset(&epilog_key, 0, sizeof(epilog_key));
6838 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6839 si_build_tcs_epilog_function(&ctx, &epilog_key);
6840 parts[1] = ctx.main_fn;
6841
6842 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6843 }
6844 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6845 if (ctx.screen->info.chip_class >= GFX9) {
6846 struct si_shader_selector *es = shader->key.part.gs.es;
6847 LLVMValueRef es_prolog = NULL;
6848 LLVMValueRef es_main = NULL;
6849 LLVMValueRef gs_prolog = NULL;
6850 LLVMValueRef gs_main = ctx.main_fn;
6851
6852 /* GS prolog */
6853 union si_shader_part_key gs_prolog_key;
6854 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6855 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6856 gs_prolog_key.gs_prolog.is_monolithic = true;
6857 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6858 gs_prolog = ctx.main_fn;
6859
6860 /* ES main part */
6861 struct si_shader shader_es = {};
6862 shader_es.selector = es;
6863 shader_es.key.as_es = 1;
6864 shader_es.key.mono = shader->key.mono;
6865 shader_es.key.opt = shader->key.opt;
6866 si_llvm_context_set_tgsi(&ctx, &shader_es);
6867
6868 if (!si_compile_tgsi_main(&ctx, true)) {
6869 si_llvm_dispose(&ctx);
6870 return -1;
6871 }
6872 shader->info.uses_instanceid |= es->info.uses_instanceid;
6873 es_main = ctx.main_fn;
6874
6875 /* ES prolog */
6876 if (es->vs_needs_prolog) {
6877 union si_shader_part_key vs_prolog_key;
6878 si_get_vs_prolog_key(&es->info,
6879 shader_es.info.num_input_sgprs,
6880 &shader->key.part.gs.vs_prolog,
6881 shader, &vs_prolog_key);
6882 vs_prolog_key.vs_prolog.is_monolithic = true;
6883 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6884 es_prolog = ctx.main_fn;
6885 }
6886
6887 /* Reset the shader context. */
6888 ctx.shader = shader;
6889 ctx.type = PIPE_SHADER_GEOMETRY;
6890
6891 /* Prepare the array of shader parts. */
6892 LLVMValueRef parts[4];
6893 unsigned num_parts = 0, main_part, next_first_part;
6894
6895 if (es_prolog)
6896 parts[num_parts++] = es_prolog;
6897
6898 parts[main_part = num_parts++] = es_main;
6899 parts[next_first_part = num_parts++] = gs_prolog;
6900 parts[num_parts++] = gs_main;
6901
6902 si_build_wrapper_function(&ctx, parts, num_parts,
6903 main_part, next_first_part);
6904 } else {
6905 LLVMValueRef parts[2];
6906 union si_shader_part_key prolog_key;
6907
6908 parts[1] = ctx.main_fn;
6909
6910 memset(&prolog_key, 0, sizeof(prolog_key));
6911 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6912 si_build_gs_prolog_function(&ctx, &prolog_key);
6913 parts[0] = ctx.main_fn;
6914
6915 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6916 }
6917 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6918 LLVMValueRef parts[3];
6919 union si_shader_part_key prolog_key;
6920 union si_shader_part_key epilog_key;
6921 bool need_prolog;
6922
6923 si_get_ps_prolog_key(shader, &prolog_key, false);
6924 need_prolog = si_need_ps_prolog(&prolog_key);
6925
6926 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6927
6928 if (need_prolog) {
6929 si_build_ps_prolog_function(&ctx, &prolog_key);
6930 parts[0] = ctx.main_fn;
6931 }
6932
6933 si_get_ps_epilog_key(shader, &epilog_key);
6934 si_build_ps_epilog_function(&ctx, &epilog_key);
6935 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6936
6937 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6938 need_prolog ? 1 : 0, 0);
6939 }
6940
6941 si_llvm_optimize_module(&ctx);
6942
6943 /* Post-optimization transformations and analysis. */
6944 si_optimize_vs_outputs(&ctx);
6945
6946 if ((debug && debug->debug_message) ||
6947 si_can_dump_shader(sscreen, ctx.type)) {
6948 ctx.shader->config.private_mem_vgprs =
6949 ac_count_scratch_private_memory(ctx.main_fn);
6950 }
6951
6952 /* Compile to bytecode. */
6953 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6954 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6955 si_llvm_dispose(&ctx);
6956 if (r) {
6957 fprintf(stderr, "LLVM failed to compile shader\n");
6958 return r;
6959 }
6960
6961 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6962 * LLVM 3.9svn has this bug.
6963 */
6964 if (sel->type == PIPE_SHADER_COMPUTE) {
6965 unsigned wave_size = 64;
6966 unsigned max_vgprs = 256;
6967 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6968 unsigned max_sgprs_per_wave = 128;
6969 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6970 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6971 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6972
6973 max_vgprs = max_vgprs / min_waves_per_simd;
6974 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6975
6976 if (shader->config.num_sgprs > max_sgprs ||
6977 shader->config.num_vgprs > max_vgprs) {
6978 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6979 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6980 shader->config.num_sgprs, shader->config.num_vgprs,
6981 max_sgprs, max_vgprs);
6982
6983 /* Just terminate the process, because dependent
6984 * shaders can hang due to bad input data, but use
6985 * the env var to allow shader-db to work.
6986 */
6987 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6988 abort();
6989 }
6990 }
6991
6992 /* Add the scratch offset to input SGPRs. */
6993 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6994 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6995
6996 /* Calculate the number of fragment input VGPRs. */
6997 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6998 shader->info.num_input_vgprs = 0;
6999 shader->info.face_vgpr_index = -1;
7000 shader->info.ancillary_vgpr_index = -1;
7001
7002 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7003 shader->info.num_input_vgprs += 2;
7004 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7005 shader->info.num_input_vgprs += 2;
7006 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7007 shader->info.num_input_vgprs += 2;
7008 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7009 shader->info.num_input_vgprs += 3;
7010 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7011 shader->info.num_input_vgprs += 2;
7012 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7013 shader->info.num_input_vgprs += 2;
7014 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7015 shader->info.num_input_vgprs += 2;
7016 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7017 shader->info.num_input_vgprs += 1;
7018 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7019 shader->info.num_input_vgprs += 1;
7020 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7021 shader->info.num_input_vgprs += 1;
7022 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7023 shader->info.num_input_vgprs += 1;
7024 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7025 shader->info.num_input_vgprs += 1;
7026 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7027 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7028 shader->info.num_input_vgprs += 1;
7029 }
7030 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7031 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7032 shader->info.num_input_vgprs += 1;
7033 }
7034 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7035 shader->info.num_input_vgprs += 1;
7036 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7037 shader->info.num_input_vgprs += 1;
7038 }
7039
7040 si_calculate_max_simd_waves(shader);
7041 si_shader_dump_stats_for_shader_db(shader, debug);
7042 return 0;
7043 }
7044
7045 /**
7046 * Create, compile and return a shader part (prolog or epilog).
7047 *
7048 * \param sscreen screen
7049 * \param list list of shader parts of the same category
7050 * \param type shader type
7051 * \param key shader part key
7052 * \param prolog whether the part being requested is a prolog
7053 * \param tm LLVM target machine
7054 * \param debug debug callback
7055 * \param build the callback responsible for building the main function
7056 * \return non-NULL on success
7057 */
7058 static struct si_shader_part *
7059 si_get_shader_part(struct si_screen *sscreen,
7060 struct si_shader_part **list,
7061 enum pipe_shader_type type,
7062 bool prolog,
7063 union si_shader_part_key *key,
7064 LLVMTargetMachineRef tm,
7065 struct pipe_debug_callback *debug,
7066 void (*build)(struct si_shader_context *,
7067 union si_shader_part_key *),
7068 const char *name)
7069 {
7070 struct si_shader_part *result;
7071
7072 mtx_lock(&sscreen->shader_parts_mutex);
7073
7074 /* Find existing. */
7075 for (result = *list; result; result = result->next) {
7076 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7077 mtx_unlock(&sscreen->shader_parts_mutex);
7078 return result;
7079 }
7080 }
7081
7082 /* Compile a new one. */
7083 result = CALLOC_STRUCT(si_shader_part);
7084 result->key = *key;
7085
7086 struct si_shader shader = {};
7087 struct si_shader_context ctx;
7088
7089 si_init_shader_ctx(&ctx, sscreen, tm);
7090 ctx.shader = &shader;
7091 ctx.type = type;
7092
7093 switch (type) {
7094 case PIPE_SHADER_VERTEX:
7095 shader.key.as_ls = key->vs_prolog.as_ls;
7096 shader.key.as_es = key->vs_prolog.as_es;
7097 break;
7098 case PIPE_SHADER_TESS_CTRL:
7099 assert(!prolog);
7100 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7101 break;
7102 case PIPE_SHADER_GEOMETRY:
7103 assert(prolog);
7104 break;
7105 case PIPE_SHADER_FRAGMENT:
7106 if (prolog)
7107 shader.key.part.ps.prolog = key->ps_prolog.states;
7108 else
7109 shader.key.part.ps.epilog = key->ps_epilog.states;
7110 break;
7111 default:
7112 unreachable("bad shader part");
7113 }
7114
7115 build(&ctx, key);
7116
7117 /* Compile. */
7118 si_llvm_optimize_module(&ctx);
7119
7120 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7121 ctx.ac.module, debug, ctx.type, name)) {
7122 FREE(result);
7123 result = NULL;
7124 goto out;
7125 }
7126
7127 result->next = *list;
7128 *list = result;
7129
7130 out:
7131 si_llvm_dispose(&ctx);
7132 mtx_unlock(&sscreen->shader_parts_mutex);
7133 return result;
7134 }
7135
7136 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7137 {
7138 LLVMValueRef ptr[2], list;
7139 bool is_merged_shader =
7140 ctx->screen->info.chip_class >= GFX9 &&
7141 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7142 ctx->type == PIPE_SHADER_GEOMETRY ||
7143 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7144
7145 if (HAVE_32BIT_POINTERS) {
7146 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7147 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7148 ac_array_in_const32_addr_space(ctx->v4i32), "");
7149 return list;
7150 }
7151
7152 /* Get the pointer to rw buffers. */
7153 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7154 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7155 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7156 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7157 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7158 ac_array_in_const_addr_space(ctx->v4i32), "");
7159 return list;
7160 }
7161
7162 /**
7163 * Build the vertex shader prolog function.
7164 *
7165 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7166 * All inputs are returned unmodified. The vertex load indices are
7167 * stored after them, which will be used by the API VS for fetching inputs.
7168 *
7169 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7170 * input_v0,
7171 * input_v1,
7172 * input_v2,
7173 * input_v3,
7174 * (VertexID + BaseVertex),
7175 * (InstanceID + StartInstance),
7176 * (InstanceID / 2 + StartInstance)
7177 */
7178 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7179 union si_shader_part_key *key)
7180 {
7181 struct si_function_info fninfo;
7182 LLVMTypeRef *returns;
7183 LLVMValueRef ret, func;
7184 int num_returns, i;
7185 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7186 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7187 LLVMValueRef input_vgprs[9];
7188 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7189 num_input_vgprs;
7190 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7191
7192 si_init_function_info(&fninfo);
7193
7194 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7195 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7196 sizeof(LLVMTypeRef));
7197 num_returns = 0;
7198
7199 /* Declare input and output SGPRs. */
7200 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7201 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7202 returns[num_returns++] = ctx->i32;
7203 }
7204
7205 /* Preloaded VGPRs (outputs must be floats) */
7206 for (i = 0; i < num_input_vgprs; i++) {
7207 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7208 returns[num_returns++] = ctx->f32;
7209 }
7210
7211 /* Vertex load indices. */
7212 for (i = 0; i <= key->vs_prolog.last_input; i++)
7213 returns[num_returns++] = ctx->f32;
7214
7215 /* Create the function. */
7216 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7217 func = ctx->main_fn;
7218
7219 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7220 if (!key->vs_prolog.is_monolithic)
7221 si_init_exec_from_input(ctx, 3, 0);
7222
7223 if (key->vs_prolog.as_ls &&
7224 ctx->screen->has_ls_vgpr_init_bug) {
7225 /* If there are no HS threads, SPI loads the LS VGPRs
7226 * starting at VGPR 0. Shift them back to where they
7227 * belong.
7228 */
7229 LLVMValueRef has_hs_threads =
7230 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7231 unpack_param(ctx, 3, 8, 8),
7232 ctx->i32_0, "");
7233
7234 for (i = 4; i > 0; --i) {
7235 input_vgprs[i + 1] =
7236 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7237 input_vgprs[i + 1],
7238 input_vgprs[i - 1], "");
7239 }
7240 }
7241 }
7242
7243 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7244 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7245
7246 /* Copy inputs to outputs. This should be no-op, as the registers match,
7247 * but it will prevent the compiler from overwriting them unintentionally.
7248 */
7249 ret = ctx->return_value;
7250 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7251 LLVMValueRef p = LLVMGetParam(func, i);
7252 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7253 }
7254 for (i = 0; i < num_input_vgprs; i++) {
7255 LLVMValueRef p = input_vgprs[i];
7256 p = ac_to_float(&ctx->ac, p);
7257 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7258 key->vs_prolog.num_input_sgprs + i, "");
7259 }
7260
7261 /* Compute vertex load indices from instance divisors. */
7262 LLVMValueRef instance_divisor_constbuf = NULL;
7263
7264 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7265 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7266 LLVMValueRef buf_index =
7267 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7268 instance_divisor_constbuf =
7269 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7270 }
7271
7272 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7273 bool divisor_is_one =
7274 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7275 bool divisor_is_fetched =
7276 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7277 LLVMValueRef index;
7278
7279 if (divisor_is_one || divisor_is_fetched) {
7280 LLVMValueRef divisor = ctx->i32_1;
7281
7282 if (divisor_is_fetched) {
7283 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7284 LLVMConstInt(ctx->i32, i * 4, 0));
7285 divisor = ac_to_integer(&ctx->ac, divisor);
7286 }
7287
7288 /* InstanceID / Divisor + StartInstance */
7289 index = get_instance_index_for_fetch(ctx,
7290 user_sgpr_base +
7291 SI_SGPR_START_INSTANCE,
7292 divisor);
7293 } else {
7294 /* VertexID + BaseVertex */
7295 index = LLVMBuildAdd(ctx->ac.builder,
7296 ctx->abi.vertex_id,
7297 LLVMGetParam(func, user_sgpr_base +
7298 SI_SGPR_BASE_VERTEX), "");
7299 }
7300
7301 index = ac_to_float(&ctx->ac, index);
7302 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7303 fninfo.num_params + i, "");
7304 }
7305
7306 si_llvm_build_ret(ctx, ret);
7307 }
7308
7309 static bool si_get_vs_prolog(struct si_screen *sscreen,
7310 LLVMTargetMachineRef tm,
7311 struct si_shader *shader,
7312 struct pipe_debug_callback *debug,
7313 struct si_shader *main_part,
7314 const struct si_vs_prolog_bits *key)
7315 {
7316 struct si_shader_selector *vs = main_part->selector;
7317
7318 if (!si_vs_needs_prolog(vs, key))
7319 return true;
7320
7321 /* Get the prolog. */
7322 union si_shader_part_key prolog_key;
7323 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7324 key, shader, &prolog_key);
7325
7326 shader->prolog =
7327 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7328 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7329 debug, si_build_vs_prolog_function,
7330 "Vertex Shader Prolog");
7331 return shader->prolog != NULL;
7332 }
7333
7334 /**
7335 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7336 */
7337 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7338 LLVMTargetMachineRef tm,
7339 struct si_shader *shader,
7340 struct pipe_debug_callback *debug)
7341 {
7342 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7343 &shader->key.part.vs.prolog);
7344 }
7345
7346 /**
7347 * Compile the TCS epilog function. This writes tesselation factors to memory
7348 * based on the output primitive type of the tesselator (determined by TES).
7349 */
7350 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7351 union si_shader_part_key *key)
7352 {
7353 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7354 struct si_function_info fninfo;
7355 LLVMValueRef func;
7356
7357 si_init_function_info(&fninfo);
7358
7359 if (ctx->screen->info.chip_class >= GFX9) {
7360 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7361 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7362 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7363 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7364 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7365 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7366 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7367 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7368 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7369 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7370 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7371 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7372 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7373 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7374 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7375 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7376 if (!HAVE_32BIT_POINTERS)
7377 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7378 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7379 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7380 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7381 } else {
7382 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7383 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7384 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7385 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7386 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7387 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7388 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7389 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7390 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7391 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7392 }
7393
7394 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7395 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7396 unsigned tess_factors_idx =
7397 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7398 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7399 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7400
7401 for (unsigned i = 0; i < 6; i++)
7402 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7403
7404 /* Create the function. */
7405 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7406 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7407 ac_declare_lds_as_pointer(&ctx->ac);
7408 func = ctx->main_fn;
7409
7410 LLVMValueRef invoc0_tess_factors[6];
7411 for (unsigned i = 0; i < 6; i++)
7412 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7413
7414 si_write_tess_factors(bld_base,
7415 LLVMGetParam(func, tess_factors_idx),
7416 LLVMGetParam(func, tess_factors_idx + 1),
7417 LLVMGetParam(func, tess_factors_idx + 2),
7418 invoc0_tess_factors, invoc0_tess_factors + 4);
7419
7420 LLVMBuildRetVoid(ctx->ac.builder);
7421 }
7422
7423 /**
7424 * Select and compile (or reuse) TCS parts (epilog).
7425 */
7426 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7427 LLVMTargetMachineRef tm,
7428 struct si_shader *shader,
7429 struct pipe_debug_callback *debug)
7430 {
7431 if (sscreen->info.chip_class >= GFX9) {
7432 struct si_shader *ls_main_part =
7433 shader->key.part.tcs.ls->main_shader_part_ls;
7434
7435 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7436 &shader->key.part.tcs.ls_prolog))
7437 return false;
7438
7439 shader->previous_stage = ls_main_part;
7440 }
7441
7442 /* Get the epilog. */
7443 union si_shader_part_key epilog_key;
7444 memset(&epilog_key, 0, sizeof(epilog_key));
7445 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7446
7447 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7448 PIPE_SHADER_TESS_CTRL, false,
7449 &epilog_key, tm, debug,
7450 si_build_tcs_epilog_function,
7451 "Tessellation Control Shader Epilog");
7452 return shader->epilog != NULL;
7453 }
7454
7455 /**
7456 * Select and compile (or reuse) GS parts (prolog).
7457 */
7458 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7459 LLVMTargetMachineRef tm,
7460 struct si_shader *shader,
7461 struct pipe_debug_callback *debug)
7462 {
7463 if (sscreen->info.chip_class >= GFX9) {
7464 struct si_shader *es_main_part =
7465 shader->key.part.gs.es->main_shader_part_es;
7466
7467 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7468 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7469 &shader->key.part.gs.vs_prolog))
7470 return false;
7471
7472 shader->previous_stage = es_main_part;
7473 }
7474
7475 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7476 return true;
7477
7478 union si_shader_part_key prolog_key;
7479 memset(&prolog_key, 0, sizeof(prolog_key));
7480 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7481
7482 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7483 PIPE_SHADER_GEOMETRY, true,
7484 &prolog_key, tm, debug,
7485 si_build_gs_prolog_function,
7486 "Geometry Shader Prolog");
7487 return shader->prolog2 != NULL;
7488 }
7489
7490 /**
7491 * Build the pixel shader prolog function. This handles:
7492 * - two-side color selection and interpolation
7493 * - overriding interpolation parameters for the API PS
7494 * - polygon stippling
7495 *
7496 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7497 * overriden by other states. (e.g. per-sample interpolation)
7498 * Interpolated colors are stored after the preloaded VGPRs.
7499 */
7500 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7501 union si_shader_part_key *key)
7502 {
7503 struct si_function_info fninfo;
7504 LLVMValueRef ret, func;
7505 int num_returns, i, num_color_channels;
7506
7507 assert(si_need_ps_prolog(key));
7508
7509 si_init_function_info(&fninfo);
7510
7511 /* Declare inputs. */
7512 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7513 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7514
7515 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7516 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7517
7518 /* Declare outputs (same as inputs + add colors if needed) */
7519 num_returns = fninfo.num_params;
7520 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7521 for (i = 0; i < num_color_channels; i++)
7522 fninfo.types[num_returns++] = ctx->f32;
7523
7524 /* Create the function. */
7525 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7526 &fninfo, 0);
7527 func = ctx->main_fn;
7528
7529 /* Copy inputs to outputs. This should be no-op, as the registers match,
7530 * but it will prevent the compiler from overwriting them unintentionally.
7531 */
7532 ret = ctx->return_value;
7533 for (i = 0; i < fninfo.num_params; i++) {
7534 LLVMValueRef p = LLVMGetParam(func, i);
7535 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7536 }
7537
7538 /* Polygon stippling. */
7539 if (key->ps_prolog.states.poly_stipple) {
7540 /* POS_FIXED_PT is always last. */
7541 unsigned pos = key->ps_prolog.num_input_sgprs +
7542 key->ps_prolog.num_input_vgprs - 1;
7543 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7544
7545 si_llvm_emit_polygon_stipple(ctx, list, pos);
7546 }
7547
7548 if (key->ps_prolog.states.bc_optimize_for_persp ||
7549 key->ps_prolog.states.bc_optimize_for_linear) {
7550 unsigned i, base = key->ps_prolog.num_input_sgprs;
7551 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7552
7553 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7554 * The hw doesn't compute CENTROID if the whole wave only
7555 * contains fully-covered quads.
7556 *
7557 * PRIM_MASK is after user SGPRs.
7558 */
7559 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7560 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7561 LLVMConstInt(ctx->i32, 31, 0), "");
7562 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7563 ctx->i1, "");
7564
7565 if (key->ps_prolog.states.bc_optimize_for_persp) {
7566 /* Read PERSP_CENTER. */
7567 for (i = 0; i < 2; i++)
7568 center[i] = LLVMGetParam(func, base + 2 + i);
7569 /* Read PERSP_CENTROID. */
7570 for (i = 0; i < 2; i++)
7571 centroid[i] = LLVMGetParam(func, base + 4 + i);
7572 /* Select PERSP_CENTROID. */
7573 for (i = 0; i < 2; i++) {
7574 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7575 center[i], centroid[i], "");
7576 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7577 tmp, base + 4 + i, "");
7578 }
7579 }
7580 if (key->ps_prolog.states.bc_optimize_for_linear) {
7581 /* Read LINEAR_CENTER. */
7582 for (i = 0; i < 2; i++)
7583 center[i] = LLVMGetParam(func, base + 8 + i);
7584 /* Read LINEAR_CENTROID. */
7585 for (i = 0; i < 2; i++)
7586 centroid[i] = LLVMGetParam(func, base + 10 + i);
7587 /* Select LINEAR_CENTROID. */
7588 for (i = 0; i < 2; i++) {
7589 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7590 center[i], centroid[i], "");
7591 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7592 tmp, base + 10 + i, "");
7593 }
7594 }
7595 }
7596
7597 /* Force per-sample interpolation. */
7598 if (key->ps_prolog.states.force_persp_sample_interp) {
7599 unsigned i, base = key->ps_prolog.num_input_sgprs;
7600 LLVMValueRef persp_sample[2];
7601
7602 /* Read PERSP_SAMPLE. */
7603 for (i = 0; i < 2; i++)
7604 persp_sample[i] = LLVMGetParam(func, base + i);
7605 /* Overwrite PERSP_CENTER. */
7606 for (i = 0; i < 2; i++)
7607 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7608 persp_sample[i], base + 2 + i, "");
7609 /* Overwrite PERSP_CENTROID. */
7610 for (i = 0; i < 2; i++)
7611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7612 persp_sample[i], base + 4 + i, "");
7613 }
7614 if (key->ps_prolog.states.force_linear_sample_interp) {
7615 unsigned i, base = key->ps_prolog.num_input_sgprs;
7616 LLVMValueRef linear_sample[2];
7617
7618 /* Read LINEAR_SAMPLE. */
7619 for (i = 0; i < 2; i++)
7620 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7621 /* Overwrite LINEAR_CENTER. */
7622 for (i = 0; i < 2; i++)
7623 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7624 linear_sample[i], base + 8 + i, "");
7625 /* Overwrite LINEAR_CENTROID. */
7626 for (i = 0; i < 2; i++)
7627 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7628 linear_sample[i], base + 10 + i, "");
7629 }
7630
7631 /* Force center interpolation. */
7632 if (key->ps_prolog.states.force_persp_center_interp) {
7633 unsigned i, base = key->ps_prolog.num_input_sgprs;
7634 LLVMValueRef persp_center[2];
7635
7636 /* Read PERSP_CENTER. */
7637 for (i = 0; i < 2; i++)
7638 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7639 /* Overwrite PERSP_SAMPLE. */
7640 for (i = 0; i < 2; i++)
7641 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7642 persp_center[i], base + i, "");
7643 /* Overwrite PERSP_CENTROID. */
7644 for (i = 0; i < 2; i++)
7645 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7646 persp_center[i], base + 4 + i, "");
7647 }
7648 if (key->ps_prolog.states.force_linear_center_interp) {
7649 unsigned i, base = key->ps_prolog.num_input_sgprs;
7650 LLVMValueRef linear_center[2];
7651
7652 /* Read LINEAR_CENTER. */
7653 for (i = 0; i < 2; i++)
7654 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7655 /* Overwrite LINEAR_SAMPLE. */
7656 for (i = 0; i < 2; i++)
7657 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7658 linear_center[i], base + 6 + i, "");
7659 /* Overwrite LINEAR_CENTROID. */
7660 for (i = 0; i < 2; i++)
7661 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7662 linear_center[i], base + 10 + i, "");
7663 }
7664
7665 /* Interpolate colors. */
7666 unsigned color_out_idx = 0;
7667 for (i = 0; i < 2; i++) {
7668 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7669 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7670 key->ps_prolog.face_vgpr_index;
7671 LLVMValueRef interp[2], color[4];
7672 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7673
7674 if (!writemask)
7675 continue;
7676
7677 /* If the interpolation qualifier is not CONSTANT (-1). */
7678 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7679 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7680 key->ps_prolog.color_interp_vgpr_index[i];
7681
7682 /* Get the (i,j) updated by bc_optimize handling. */
7683 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7684 interp_vgpr, "");
7685 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7686 interp_vgpr + 1, "");
7687 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7688 }
7689
7690 /* Use the absolute location of the input. */
7691 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7692
7693 if (key->ps_prolog.states.color_two_side) {
7694 face = LLVMGetParam(func, face_vgpr);
7695 face = ac_to_integer(&ctx->ac, face);
7696 }
7697
7698 interp_fs_input(ctx,
7699 key->ps_prolog.color_attr_index[i],
7700 TGSI_SEMANTIC_COLOR, i,
7701 key->ps_prolog.num_interp_inputs,
7702 key->ps_prolog.colors_read, interp_ij,
7703 prim_mask, face, color);
7704
7705 while (writemask) {
7706 unsigned chan = u_bit_scan(&writemask);
7707 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7708 fninfo.num_params + color_out_idx++, "");
7709 }
7710 }
7711
7712 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7713 * says:
7714 *
7715 * "When per-sample shading is active due to the use of a fragment
7716 * input qualified by sample or due to the use of the gl_SampleID
7717 * or gl_SamplePosition variables, only the bit for the current
7718 * sample is set in gl_SampleMaskIn. When state specifies multiple
7719 * fragment shader invocations for a given fragment, the sample
7720 * mask for any single fragment shader invocation may specify a
7721 * subset of the covered samples for the fragment. In this case,
7722 * the bit corresponding to each covered sample will be set in
7723 * exactly one fragment shader invocation."
7724 *
7725 * The samplemask loaded by hardware is always the coverage of the
7726 * entire pixel/fragment, so mask bits out based on the sample ID.
7727 */
7728 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7729 /* The bit pattern matches that used by fixed function fragment
7730 * processing. */
7731 static const uint16_t ps_iter_masks[] = {
7732 0xffff, /* not used */
7733 0x5555,
7734 0x1111,
7735 0x0101,
7736 0x0001,
7737 };
7738 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7739
7740 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7741 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7742 key->ps_prolog.ancillary_vgpr_index;
7743 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7744 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7745
7746 samplemask = ac_to_integer(&ctx->ac, samplemask);
7747 samplemask = LLVMBuildAnd(
7748 ctx->ac.builder,
7749 samplemask,
7750 LLVMBuildShl(ctx->ac.builder,
7751 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7752 sampleid, ""),
7753 "");
7754 samplemask = ac_to_float(&ctx->ac, samplemask);
7755
7756 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7757 ancillary_vgpr + 1, "");
7758 }
7759
7760 /* Tell LLVM to insert WQM instruction sequence when needed. */
7761 if (key->ps_prolog.wqm) {
7762 LLVMAddTargetDependentFunctionAttr(func,
7763 "amdgpu-ps-wqm-outputs", "");
7764 }
7765
7766 si_llvm_build_ret(ctx, ret);
7767 }
7768
7769 /**
7770 * Build the pixel shader epilog function. This handles everything that must be
7771 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7772 */
7773 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7774 union si_shader_part_key *key)
7775 {
7776 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7777 struct si_function_info fninfo;
7778 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7779 int i;
7780 struct si_ps_exports exp = {};
7781
7782 si_init_function_info(&fninfo);
7783
7784 /* Declare input SGPRs. */
7785 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7786 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7787 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7788 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7789 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7790
7791 /* Declare input VGPRs. */
7792 unsigned required_num_params =
7793 fninfo.num_sgpr_params +
7794 util_bitcount(key->ps_epilog.colors_written) * 4 +
7795 key->ps_epilog.writes_z +
7796 key->ps_epilog.writes_stencil +
7797 key->ps_epilog.writes_samplemask;
7798
7799 required_num_params = MAX2(required_num_params,
7800 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7801
7802 while (fninfo.num_params < required_num_params)
7803 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7804
7805 /* Create the function. */
7806 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7807 /* Disable elimination of unused inputs. */
7808 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7809 "InitialPSInputAddr", 0xffffff);
7810
7811 /* Process colors. */
7812 unsigned vgpr = fninfo.num_sgpr_params;
7813 unsigned colors_written = key->ps_epilog.colors_written;
7814 int last_color_export = -1;
7815
7816 /* Find the last color export. */
7817 if (!key->ps_epilog.writes_z &&
7818 !key->ps_epilog.writes_stencil &&
7819 !key->ps_epilog.writes_samplemask) {
7820 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7821
7822 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7823 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7824 /* Just set this if any of the colorbuffers are enabled. */
7825 if (spi_format &
7826 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7827 last_color_export = 0;
7828 } else {
7829 for (i = 0; i < 8; i++)
7830 if (colors_written & (1 << i) &&
7831 (spi_format >> (i * 4)) & 0xf)
7832 last_color_export = i;
7833 }
7834 }
7835
7836 while (colors_written) {
7837 LLVMValueRef color[4];
7838 int mrt = u_bit_scan(&colors_written);
7839
7840 for (i = 0; i < 4; i++)
7841 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7842
7843 si_export_mrt_color(bld_base, color, mrt,
7844 fninfo.num_params - 1,
7845 mrt == last_color_export, &exp);
7846 }
7847
7848 /* Process depth, stencil, samplemask. */
7849 if (key->ps_epilog.writes_z)
7850 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7851 if (key->ps_epilog.writes_stencil)
7852 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7853 if (key->ps_epilog.writes_samplemask)
7854 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7855
7856 if (depth || stencil || samplemask)
7857 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7858 else if (last_color_export == -1)
7859 ac_build_export_null(&ctx->ac);
7860
7861 if (exp.num)
7862 si_emit_ps_exports(ctx, &exp);
7863
7864 /* Compile. */
7865 LLVMBuildRetVoid(ctx->ac.builder);
7866 }
7867
7868 /**
7869 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7870 */
7871 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7872 LLVMTargetMachineRef tm,
7873 struct si_shader *shader,
7874 struct pipe_debug_callback *debug)
7875 {
7876 union si_shader_part_key prolog_key;
7877 union si_shader_part_key epilog_key;
7878
7879 /* Get the prolog. */
7880 si_get_ps_prolog_key(shader, &prolog_key, true);
7881
7882 /* The prolog is a no-op if these aren't set. */
7883 if (si_need_ps_prolog(&prolog_key)) {
7884 shader->prolog =
7885 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7886 PIPE_SHADER_FRAGMENT, true,
7887 &prolog_key, tm, debug,
7888 si_build_ps_prolog_function,
7889 "Fragment Shader Prolog");
7890 if (!shader->prolog)
7891 return false;
7892 }
7893
7894 /* Get the epilog. */
7895 si_get_ps_epilog_key(shader, &epilog_key);
7896
7897 shader->epilog =
7898 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7899 PIPE_SHADER_FRAGMENT, false,
7900 &epilog_key, tm, debug,
7901 si_build_ps_epilog_function,
7902 "Fragment Shader Epilog");
7903 if (!shader->epilog)
7904 return false;
7905
7906 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7907 if (shader->key.part.ps.prolog.poly_stipple) {
7908 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7909 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7910 }
7911
7912 /* Set up the enable bits for per-sample shading if needed. */
7913 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7914 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7915 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7916 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7917 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7918 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7919 }
7920 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7921 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7922 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7923 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7924 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7925 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7926 }
7927 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7928 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7929 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7930 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7931 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7932 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7933 }
7934 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7935 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7936 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7937 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7938 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7939 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7940 }
7941
7942 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7943 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7944 !(shader->config.spi_ps_input_ena & 0xf)) {
7945 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7946 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7947 }
7948
7949 /* At least one pair of interpolation weights must be enabled. */
7950 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7951 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7952 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7953 }
7954
7955 /* Samplemask fixup requires the sample ID. */
7956 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7957 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7958 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7959 }
7960
7961 /* The sample mask input is always enabled, because the API shader always
7962 * passes it through to the epilog. Disable it here if it's unused.
7963 */
7964 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7965 !shader->selector->info.reads_samplemask)
7966 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7967
7968 return true;
7969 }
7970
7971 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7972 unsigned *lds_size)
7973 {
7974 /* SPI barrier management bug:
7975 * Make sure we have at least 4k of LDS in use to avoid the bug.
7976 * It applies to workgroup sizes of more than one wavefront.
7977 */
7978 if (sscreen->info.family == CHIP_BONAIRE ||
7979 sscreen->info.family == CHIP_KABINI ||
7980 sscreen->info.family == CHIP_MULLINS)
7981 *lds_size = MAX2(*lds_size, 8);
7982 }
7983
7984 static void si_fix_resource_usage(struct si_screen *sscreen,
7985 struct si_shader *shader)
7986 {
7987 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7988
7989 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7990
7991 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7992 si_get_max_workgroup_size(shader) > 64) {
7993 si_multiwave_lds_size_workaround(sscreen,
7994 &shader->config.lds_size);
7995 }
7996 }
7997
7998 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7999 struct si_shader *shader,
8000 struct pipe_debug_callback *debug)
8001 {
8002 struct si_shader_selector *sel = shader->selector;
8003 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8004 int r;
8005
8006 /* LS, ES, VS are compiled on demand if the main part hasn't been
8007 * compiled for that stage.
8008 *
8009 * Vertex shaders are compiled on demand when a vertex fetch
8010 * workaround must be applied.
8011 */
8012 if (shader->is_monolithic) {
8013 /* Monolithic shader (compiled as a whole, has many variants,
8014 * may take a long time to compile).
8015 */
8016 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8017 if (r)
8018 return r;
8019 } else {
8020 /* The shader consists of several parts:
8021 *
8022 * - the middle part is the user shader, it has 1 variant only
8023 * and it was compiled during the creation of the shader
8024 * selector
8025 * - the prolog part is inserted at the beginning
8026 * - the epilog part is inserted at the end
8027 *
8028 * The prolog and epilog have many (but simple) variants.
8029 *
8030 * Starting with gfx9, geometry and tessellation control
8031 * shaders also contain the prolog and user shader parts of
8032 * the previous shader stage.
8033 */
8034
8035 if (!mainp)
8036 return -1;
8037
8038 /* Copy the compiled TGSI shader data over. */
8039 shader->is_binary_shared = true;
8040 shader->binary = mainp->binary;
8041 shader->config = mainp->config;
8042 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8043 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8044 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8045 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8046 memcpy(shader->info.vs_output_param_offset,
8047 mainp->info.vs_output_param_offset,
8048 sizeof(mainp->info.vs_output_param_offset));
8049 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8050 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8051 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8052
8053 /* Select prologs and/or epilogs. */
8054 switch (sel->type) {
8055 case PIPE_SHADER_VERTEX:
8056 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8057 return -1;
8058 break;
8059 case PIPE_SHADER_TESS_CTRL:
8060 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8061 return -1;
8062 break;
8063 case PIPE_SHADER_TESS_EVAL:
8064 break;
8065 case PIPE_SHADER_GEOMETRY:
8066 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8067 return -1;
8068 break;
8069 case PIPE_SHADER_FRAGMENT:
8070 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8071 return -1;
8072
8073 /* Make sure we have at least as many VGPRs as there
8074 * are allocated inputs.
8075 */
8076 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8077 shader->info.num_input_vgprs);
8078 break;
8079 }
8080
8081 /* Update SGPR and VGPR counts. */
8082 if (shader->prolog) {
8083 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8084 shader->prolog->config.num_sgprs);
8085 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8086 shader->prolog->config.num_vgprs);
8087 }
8088 if (shader->previous_stage) {
8089 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8090 shader->previous_stage->config.num_sgprs);
8091 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8092 shader->previous_stage->config.num_vgprs);
8093 shader->config.spilled_sgprs =
8094 MAX2(shader->config.spilled_sgprs,
8095 shader->previous_stage->config.spilled_sgprs);
8096 shader->config.spilled_vgprs =
8097 MAX2(shader->config.spilled_vgprs,
8098 shader->previous_stage->config.spilled_vgprs);
8099 shader->config.private_mem_vgprs =
8100 MAX2(shader->config.private_mem_vgprs,
8101 shader->previous_stage->config.private_mem_vgprs);
8102 shader->config.scratch_bytes_per_wave =
8103 MAX2(shader->config.scratch_bytes_per_wave,
8104 shader->previous_stage->config.scratch_bytes_per_wave);
8105 shader->info.uses_instanceid |=
8106 shader->previous_stage->info.uses_instanceid;
8107 }
8108 if (shader->prolog2) {
8109 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8110 shader->prolog2->config.num_sgprs);
8111 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8112 shader->prolog2->config.num_vgprs);
8113 }
8114 if (shader->epilog) {
8115 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8116 shader->epilog->config.num_sgprs);
8117 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8118 shader->epilog->config.num_vgprs);
8119 }
8120 si_calculate_max_simd_waves(shader);
8121 }
8122
8123 si_fix_resource_usage(sscreen, shader);
8124 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8125 stderr, true);
8126
8127 /* Upload. */
8128 r = si_shader_binary_upload(sscreen, shader);
8129 if (r) {
8130 fprintf(stderr, "LLVM failed to upload shader\n");
8131 return r;
8132 }
8133
8134 return 0;
8135 }
8136
8137 void si_shader_destroy(struct si_shader *shader)
8138 {
8139 if (shader->scratch_bo)
8140 r600_resource_reference(&shader->scratch_bo, NULL);
8141
8142 r600_resource_reference(&shader->bo, NULL);
8143
8144 if (!shader->is_binary_shared)
8145 ac_shader_binary_clean(&shader->binary);
8146
8147 free(shader->shader_log);
8148 }