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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94
95 LLVMTargetMachineRef tm;
96
97 LLVMValueRef const_md;
98 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
99 LLVMValueRef lds;
100 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
101 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
102 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
103 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
104 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
105 LLVMValueRef images[SI_NUM_IMAGES];
106 LLVMValueRef so_buffers[4];
107 LLVMValueRef esgs_ring;
108 LLVMValueRef gsvs_ring[4];
109 LLVMValueRef gs_next_vertex[4];
110 LLVMValueRef return_value;
111
112 LLVMTypeRef voidt;
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i32;
116 LLVMTypeRef i64;
117 LLVMTypeRef i128;
118 LLVMTypeRef f32;
119 LLVMTypeRef v16i8;
120 LLVMTypeRef v2i32;
121 LLVMTypeRef v4i32;
122 LLVMTypeRef v4f32;
123 LLVMTypeRef v8i32;
124 };
125
126 static struct si_shader_context *si_shader_context(
127 struct lp_build_tgsi_context *bld_base)
128 {
129 return (struct si_shader_context *)bld_base;
130 }
131
132 static void si_init_shader_ctx(struct si_shader_context *ctx,
133 struct si_screen *sscreen,
134 struct si_shader *shader,
135 LLVMTargetMachineRef tm);
136
137 /* Ideally pass the sample mask input to the PS epilog as v13, which
138 * is its usual location, so that the shader doesn't have to add v_mov.
139 */
140 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
141
142 /* The VS location of the PrimitiveID input is the same in the epilog,
143 * so that the main shader part doesn't have to move it.
144 */
145 #define VS_EPILOG_PRIMID_LOC 2
146
147 #define PERSPECTIVE_BASE 0
148 #define LINEAR_BASE 9
149
150 #define SAMPLE_OFFSET 0
151 #define CENTER_OFFSET 2
152 #define CENTROID_OFSET 4
153
154 #define USE_SGPR_MAX_SUFFIX_LEN 5
155 #define CONST_ADDR_SPACE 2
156 #define LOCAL_ADDR_SPACE 3
157 #define USER_SGPR_ADDR_SPACE 8
158
159
160 #define SENDMSG_GS 2
161 #define SENDMSG_GS_DONE 3
162
163 #define SENDMSG_GS_OP_NOP (0 << 4)
164 #define SENDMSG_GS_OP_CUT (1 << 4)
165 #define SENDMSG_GS_OP_EMIT (2 << 4)
166 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
174 {
175 switch (semantic_name) {
176 case TGSI_SEMANTIC_POSITION:
177 return 0;
178 case TGSI_SEMANTIC_PSIZE:
179 return 1;
180 case TGSI_SEMANTIC_CLIPDIST:
181 assert(index <= 1);
182 return 2 + index;
183 case TGSI_SEMANTIC_GENERIC:
184 if (index <= 63-4)
185 return 4 + index;
186 else
187 /* same explanation as in the default statement,
188 * the only user hitting this is st/nine.
189 */
190 return 0;
191
192 /* patch indices are completely separate and thus start from 0 */
193 case TGSI_SEMANTIC_TESSOUTER:
194 return 0;
195 case TGSI_SEMANTIC_TESSINNER:
196 return 1;
197 case TGSI_SEMANTIC_PATCH:
198 return 2 + index;
199
200 default:
201 /* Don't fail here. The result of this function is only used
202 * for LS, TCS, TES, and GS, where legacy GL semantics can't
203 * occur, but this function is called for all vertex shaders
204 * before it's known whether LS will be compiled or not.
205 */
206 return 0;
207 }
208 }
209
210 /**
211 * Get the value of a shader input parameter and extract a bitfield.
212 */
213 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
214 unsigned param, unsigned rshift,
215 unsigned bitwidth)
216 {
217 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
218 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
219 param);
220
221 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
222 value = bitcast(&ctx->radeon_bld.soa.bld_base,
223 TGSI_TYPE_UNSIGNED, value);
224
225 if (rshift)
226 value = LLVMBuildLShr(gallivm->builder, value,
227 lp_build_const_int32(gallivm, rshift), "");
228
229 if (rshift + bitwidth < 32) {
230 unsigned mask = (1 << bitwidth) - 1;
231 value = LLVMBuildAnd(gallivm->builder, value,
232 lp_build_const_int32(gallivm, mask), "");
233 }
234
235 return value;
236 }
237
238 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
239 {
240 switch (ctx->type) {
241 case TGSI_PROCESSOR_TESS_CTRL:
242 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
243
244 case TGSI_PROCESSOR_TESS_EVAL:
245 return LLVMGetParam(ctx->radeon_bld.main_fn,
246 ctx->param_tes_rel_patch_id);
247
248 default:
249 assert(0);
250 return NULL;
251 }
252 }
253
254 /* Tessellation shaders pass outputs to the next shader using LDS.
255 *
256 * LS outputs = TCS inputs
257 * TCS outputs = TES inputs
258 *
259 * The LDS layout is:
260 * - TCS inputs for patch 0
261 * - TCS inputs for patch 1
262 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
263 * - ...
264 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
265 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
266 * - TCS outputs for patch 1
267 * - Per-patch TCS outputs for patch 1
268 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
269 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
270 * - ...
271 *
272 * All three shaders VS(LS), TCS, TES share the same LDS space.
273 */
274
275 static LLVMValueRef
276 get_tcs_in_patch_stride(struct si_shader_context *ctx)
277 {
278 if (ctx->type == TGSI_PROCESSOR_VERTEX)
279 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
280 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
281 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
282 else {
283 assert(0);
284 return NULL;
285 }
286 }
287
288 static LLVMValueRef
289 get_tcs_out_patch_stride(struct si_shader_context *ctx)
290 {
291 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
292 }
293
294 static LLVMValueRef
295 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
296 {
297 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
298 unpack_param(ctx,
299 SI_PARAM_TCS_OUT_OFFSETS,
300 0, 16),
301 4);
302 }
303
304 static LLVMValueRef
305 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
306 {
307 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
308 unpack_param(ctx,
309 SI_PARAM_TCS_OUT_OFFSETS,
310 16, 16),
311 4);
312 }
313
314 static LLVMValueRef
315 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
316 {
317 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
318 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
319 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
320
321 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
322 }
323
324 static LLVMValueRef
325 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
326 {
327 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return LLVMBuildAdd(gallivm->builder, patch0_offset,
333 LLVMBuildMul(gallivm->builder, patch_stride,
334 rel_patch_id, ""),
335 "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_patch_data_offset =
343 get_tcs_out_patch0_patch_data_offset(ctx);
344 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
345 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
346
347 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
348 LLVMBuildMul(gallivm->builder, patch_stride,
349 rel_patch_id, ""),
350 "");
351 }
352
353 static void build_indexed_store(struct si_shader_context *ctx,
354 LLVMValueRef base_ptr, LLVMValueRef index,
355 LLVMValueRef value)
356 {
357 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
358 struct gallivm_state *gallivm = bld_base->base.gallivm;
359 LLVMValueRef indices[2], pointer;
360
361 indices[0] = bld_base->uint_bld.zero;
362 indices[1] = index;
363
364 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
365 LLVMBuildStore(gallivm->builder, value, pointer);
366 }
367
368 /**
369 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
370 * It's equivalent to doing a load from &base_ptr[index].
371 *
372 * \param base_ptr Where the array starts.
373 * \param index The element index into the array.
374 */
375 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
376 LLVMValueRef base_ptr, LLVMValueRef index)
377 {
378 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
379 struct gallivm_state *gallivm = bld_base->base.gallivm;
380 LLVMValueRef indices[2], pointer;
381
382 indices[0] = bld_base->uint_bld.zero;
383 indices[1] = index;
384
385 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
386 return LLVMBuildLoad(gallivm->builder, pointer, "");
387 }
388
389 /**
390 * Do a load from &base_ptr[index], but also add a flag that it's loading
391 * a constant.
392 */
393 static LLVMValueRef build_indexed_load_const(
394 struct si_shader_context *ctx,
395 LLVMValueRef base_ptr, LLVMValueRef index)
396 {
397 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
398 LLVMSetMetadata(result, 1, ctx->const_md);
399 return result;
400 }
401
402 static LLVMValueRef get_instance_index_for_fetch(
403 struct radeon_llvm_context *radeon_bld,
404 unsigned param_start_instance, unsigned divisor)
405 {
406 struct si_shader_context *ctx =
407 si_shader_context(&radeon_bld->soa.bld_base);
408 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
409
410 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
411 ctx->param_instance_id);
412
413 /* The division must be done before START_INSTANCE is added. */
414 if (divisor > 1)
415 result = LLVMBuildUDiv(gallivm->builder, result,
416 lp_build_const_int32(gallivm, divisor), "");
417
418 return LLVMBuildAdd(gallivm->builder, result,
419 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
420 }
421
422 static void declare_input_vs(
423 struct radeon_llvm_context *radeon_bld,
424 unsigned input_index,
425 const struct tgsi_full_declaration *decl)
426 {
427 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
428 struct gallivm_state *gallivm = base->gallivm;
429 struct si_shader_context *ctx =
430 si_shader_context(&radeon_bld->soa.bld_base);
431 unsigned divisor =
432 ctx->shader->key.vs.prolog.instance_divisors[input_index];
433
434 unsigned chan;
435
436 LLVMValueRef t_list_ptr;
437 LLVMValueRef t_offset;
438 LLVMValueRef t_list;
439 LLVMValueRef attribute_offset;
440 LLVMValueRef buffer_index;
441 LLVMValueRef args[3];
442 LLVMValueRef input;
443
444 /* Load the T list */
445 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
446
447 t_offset = lp_build_const_int32(gallivm, input_index);
448
449 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
450
451 /* Build the attribute offset */
452 attribute_offset = lp_build_const_int32(gallivm, 0);
453
454 if (!ctx->is_monolithic) {
455 buffer_index = LLVMGetParam(radeon_bld->main_fn,
456 ctx->param_vertex_index0 +
457 input_index);
458 } else if (divisor) {
459 /* Build index from instance ID, start instance and divisor */
460 ctx->shader->info.uses_instanceid = true;
461 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
462 SI_PARAM_START_INSTANCE,
463 divisor);
464 } else {
465 /* Load the buffer index for vertices. */
466 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
467 ctx->param_vertex_id);
468 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
469 SI_PARAM_BASE_VERTEX);
470 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
471 }
472
473 args[0] = t_list;
474 args[1] = attribute_offset;
475 args[2] = buffer_index;
476 input = lp_build_intrinsic(gallivm->builder,
477 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
478 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
479
480 /* Break up the vec4 into individual components */
481 for (chan = 0; chan < 4; chan++) {
482 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
483 /* XXX: Use a helper function for this. There is one in
484 * tgsi_llvm.c. */
485 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
486 LLVMBuildExtractElement(gallivm->builder,
487 input, llvm_chan, "");
488 }
489 }
490
491 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
492 unsigned swizzle)
493 {
494 struct si_shader_context *ctx = si_shader_context(bld_base);
495
496 if (swizzle > 0)
497 return bld_base->uint_bld.zero;
498
499 switch (ctx->type) {
500 case TGSI_PROCESSOR_VERTEX:
501 return LLVMGetParam(ctx->radeon_bld.main_fn,
502 ctx->param_vs_prim_id);
503 case TGSI_PROCESSOR_TESS_CTRL:
504 return LLVMGetParam(ctx->radeon_bld.main_fn,
505 SI_PARAM_PATCH_ID);
506 case TGSI_PROCESSOR_TESS_EVAL:
507 return LLVMGetParam(ctx->radeon_bld.main_fn,
508 ctx->param_tes_patch_id);
509 case TGSI_PROCESSOR_GEOMETRY:
510 return LLVMGetParam(ctx->radeon_bld.main_fn,
511 SI_PARAM_PRIMITIVE_ID);
512 default:
513 assert(0);
514 return bld_base->uint_bld.zero;
515 }
516 }
517
518 /**
519 * Return the value of tgsi_ind_register for indexing.
520 * This is the indirect index with the constant offset added to it.
521 */
522 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
523 const struct tgsi_ind_register *ind,
524 int rel_index)
525 {
526 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
527 LLVMValueRef result;
528
529 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
530 result = LLVMBuildLoad(gallivm->builder, result, "");
531 result = LLVMBuildAdd(gallivm->builder, result,
532 lp_build_const_int32(gallivm, rel_index), "");
533 return result;
534 }
535
536 /**
537 * Like get_indirect_index, but restricts the return value to a (possibly
538 * undefined) value inside [0..num).
539 */
540 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
541 const struct tgsi_ind_register *ind,
542 int rel_index, unsigned num)
543 {
544 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
545 LLVMBuilderRef builder = gallivm->builder;
546 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
547 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
548 LLVMValueRef cc;
549
550 if (util_is_power_of_two(num)) {
551 result = LLVMBuildAnd(builder, result, c_max, "");
552 } else {
553 /* In theory, this MAX pattern should result in code that is
554 * as good as the bit-wise AND above.
555 *
556 * In practice, LLVM generates worse code (at the time of
557 * writing), because its value tracking is not strong enough.
558 */
559 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
560 result = LLVMBuildSelect(builder, cc, result, c_max, "");
561 }
562
563 return result;
564 }
565
566
567 /**
568 * Calculate a dword address given an input or output register and a stride.
569 */
570 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
571 const struct tgsi_full_dst_register *dst,
572 const struct tgsi_full_src_register *src,
573 LLVMValueRef vertex_dw_stride,
574 LLVMValueRef base_addr)
575 {
576 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
577 struct tgsi_shader_info *info = &ctx->shader->selector->info;
578 ubyte *name, *index, *array_first;
579 int first, param;
580 struct tgsi_full_dst_register reg;
581
582 /* Set the register description. The address computation is the same
583 * for sources and destinations. */
584 if (src) {
585 reg.Register.File = src->Register.File;
586 reg.Register.Index = src->Register.Index;
587 reg.Register.Indirect = src->Register.Indirect;
588 reg.Register.Dimension = src->Register.Dimension;
589 reg.Indirect = src->Indirect;
590 reg.Dimension = src->Dimension;
591 reg.DimIndirect = src->DimIndirect;
592 } else
593 reg = *dst;
594
595 /* If the register is 2-dimensional (e.g. an array of vertices
596 * in a primitive), calculate the base address of the vertex. */
597 if (reg.Register.Dimension) {
598 LLVMValueRef index;
599
600 if (reg.Dimension.Indirect)
601 index = get_indirect_index(ctx, &reg.DimIndirect,
602 reg.Dimension.Index);
603 else
604 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
605
606 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
607 LLVMBuildMul(gallivm->builder, index,
608 vertex_dw_stride, ""), "");
609 }
610
611 /* Get information about the register. */
612 if (reg.Register.File == TGSI_FILE_INPUT) {
613 name = info->input_semantic_name;
614 index = info->input_semantic_index;
615 array_first = info->input_array_first;
616 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
617 name = info->output_semantic_name;
618 index = info->output_semantic_index;
619 array_first = info->output_array_first;
620 } else {
621 assert(0);
622 return NULL;
623 }
624
625 if (reg.Register.Indirect) {
626 /* Add the relative address of the element. */
627 LLVMValueRef ind_index;
628
629 if (reg.Indirect.ArrayID)
630 first = array_first[reg.Indirect.ArrayID];
631 else
632 first = reg.Register.Index;
633
634 ind_index = get_indirect_index(ctx, &reg.Indirect,
635 reg.Register.Index - first);
636
637 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
638 LLVMBuildMul(gallivm->builder, ind_index,
639 lp_build_const_int32(gallivm, 4), ""), "");
640
641 param = si_shader_io_get_unique_index(name[first], index[first]);
642 } else {
643 param = si_shader_io_get_unique_index(name[reg.Register.Index],
644 index[reg.Register.Index]);
645 }
646
647 /* Add the base address of the element. */
648 return LLVMBuildAdd(gallivm->builder, base_addr,
649 lp_build_const_int32(gallivm, param * 4), "");
650 }
651
652 /**
653 * Load from LDS.
654 *
655 * \param type output value type
656 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
657 * \param dw_addr address in dwords
658 */
659 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
660 enum tgsi_opcode_type type, unsigned swizzle,
661 LLVMValueRef dw_addr)
662 {
663 struct si_shader_context *ctx = si_shader_context(bld_base);
664 struct gallivm_state *gallivm = bld_base->base.gallivm;
665 LLVMValueRef value;
666
667 if (swizzle == ~0) {
668 LLVMValueRef values[TGSI_NUM_CHANNELS];
669
670 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
671 values[chan] = lds_load(bld_base, type, chan, dw_addr);
672
673 return lp_build_gather_values(bld_base->base.gallivm, values,
674 TGSI_NUM_CHANNELS);
675 }
676
677 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
678 lp_build_const_int32(gallivm, swizzle));
679
680 value = build_indexed_load(ctx, ctx->lds, dw_addr);
681 if (type == TGSI_TYPE_DOUBLE) {
682 LLVMValueRef value2;
683 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
684 lp_build_const_int32(gallivm, swizzle + 1));
685 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
686 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
687 }
688
689 return LLVMBuildBitCast(gallivm->builder, value,
690 tgsi2llvmtype(bld_base, type), "");
691 }
692
693 /**
694 * Store to LDS.
695 *
696 * \param swizzle offset (typically 0..3)
697 * \param dw_addr address in dwords
698 * \param value value to store
699 */
700 static void lds_store(struct lp_build_tgsi_context *bld_base,
701 unsigned swizzle, LLVMValueRef dw_addr,
702 LLVMValueRef value)
703 {
704 struct si_shader_context *ctx = si_shader_context(bld_base);
705 struct gallivm_state *gallivm = bld_base->base.gallivm;
706
707 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
708 lp_build_const_int32(gallivm, swizzle));
709
710 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
711 build_indexed_store(ctx, ctx->lds,
712 dw_addr, value);
713 }
714
715 static LLVMValueRef fetch_input_tcs(
716 struct lp_build_tgsi_context *bld_base,
717 const struct tgsi_full_src_register *reg,
718 enum tgsi_opcode_type type, unsigned swizzle)
719 {
720 struct si_shader_context *ctx = si_shader_context(bld_base);
721 LLVMValueRef dw_addr, stride;
722
723 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
724 dw_addr = get_tcs_in_current_patch_offset(ctx);
725 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
726
727 return lds_load(bld_base, type, swizzle, dw_addr);
728 }
729
730 static LLVMValueRef fetch_output_tcs(
731 struct lp_build_tgsi_context *bld_base,
732 const struct tgsi_full_src_register *reg,
733 enum tgsi_opcode_type type, unsigned swizzle)
734 {
735 struct si_shader_context *ctx = si_shader_context(bld_base);
736 LLVMValueRef dw_addr, stride;
737
738 if (reg->Register.Dimension) {
739 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
740 dw_addr = get_tcs_out_current_patch_offset(ctx);
741 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
742 } else {
743 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
744 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
745 }
746
747 return lds_load(bld_base, type, swizzle, dw_addr);
748 }
749
750 static LLVMValueRef fetch_input_tes(
751 struct lp_build_tgsi_context *bld_base,
752 const struct tgsi_full_src_register *reg,
753 enum tgsi_opcode_type type, unsigned swizzle)
754 {
755 struct si_shader_context *ctx = si_shader_context(bld_base);
756 LLVMValueRef dw_addr, stride;
757
758 if (reg->Register.Dimension) {
759 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
760 dw_addr = get_tcs_out_current_patch_offset(ctx);
761 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
762 } else {
763 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
764 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
765 }
766
767 return lds_load(bld_base, type, swizzle, dw_addr);
768 }
769
770 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
771 const struct tgsi_full_instruction *inst,
772 const struct tgsi_opcode_info *info,
773 LLVMValueRef dst[4])
774 {
775 struct si_shader_context *ctx = si_shader_context(bld_base);
776 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
777 unsigned chan_index;
778 LLVMValueRef dw_addr, stride;
779
780 /* Only handle per-patch and per-vertex outputs here.
781 * Vectors will be lowered to scalars and this function will be called again.
782 */
783 if (reg->Register.File != TGSI_FILE_OUTPUT ||
784 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
785 radeon_llvm_emit_store(bld_base, inst, info, dst);
786 return;
787 }
788
789 if (reg->Register.Dimension) {
790 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
791 dw_addr = get_tcs_out_current_patch_offset(ctx);
792 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
793 } else {
794 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
795 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
796 }
797
798 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
799 LLVMValueRef value = dst[chan_index];
800
801 if (inst->Instruction.Saturate)
802 value = radeon_llvm_saturate(bld_base, value);
803
804 lds_store(bld_base, chan_index, dw_addr, value);
805 }
806 }
807
808 static LLVMValueRef fetch_input_gs(
809 struct lp_build_tgsi_context *bld_base,
810 const struct tgsi_full_src_register *reg,
811 enum tgsi_opcode_type type,
812 unsigned swizzle)
813 {
814 struct lp_build_context *base = &bld_base->base;
815 struct si_shader_context *ctx = si_shader_context(bld_base);
816 struct si_shader *shader = ctx->shader;
817 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
818 struct gallivm_state *gallivm = base->gallivm;
819 LLVMValueRef vtx_offset;
820 LLVMValueRef args[9];
821 unsigned vtx_offset_param;
822 struct tgsi_shader_info *info = &shader->selector->info;
823 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
824 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
825 unsigned param;
826 LLVMValueRef value;
827
828 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
829 return get_primitive_id(bld_base, swizzle);
830
831 if (!reg->Register.Dimension)
832 return NULL;
833
834 if (swizzle == ~0) {
835 LLVMValueRef values[TGSI_NUM_CHANNELS];
836 unsigned chan;
837 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
838 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
839 }
840 return lp_build_gather_values(bld_base->base.gallivm, values,
841 TGSI_NUM_CHANNELS);
842 }
843
844 /* Get the vertex offset parameter */
845 vtx_offset_param = reg->Dimension.Index;
846 if (vtx_offset_param < 2) {
847 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
848 } else {
849 assert(vtx_offset_param < 6);
850 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
851 }
852 vtx_offset = lp_build_mul_imm(uint,
853 LLVMGetParam(ctx->radeon_bld.main_fn,
854 vtx_offset_param),
855 4);
856
857 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
858 args[0] = ctx->esgs_ring;
859 args[1] = vtx_offset;
860 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
861 args[3] = uint->zero;
862 args[4] = uint->one; /* OFFEN */
863 args[5] = uint->zero; /* IDXEN */
864 args[6] = uint->one; /* GLC */
865 args[7] = uint->zero; /* SLC */
866 args[8] = uint->zero; /* TFE */
867
868 value = lp_build_intrinsic(gallivm->builder,
869 "llvm.SI.buffer.load.dword.i32.i32",
870 ctx->i32, args, 9,
871 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
872 if (type == TGSI_TYPE_DOUBLE) {
873 LLVMValueRef value2;
874 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
875 value2 = lp_build_intrinsic(gallivm->builder,
876 "llvm.SI.buffer.load.dword.i32.i32",
877 ctx->i32, args, 9,
878 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
879 return radeon_llvm_emit_fetch_double(bld_base,
880 value, value2);
881 }
882 return LLVMBuildBitCast(gallivm->builder,
883 value,
884 tgsi2llvmtype(bld_base, type), "");
885 }
886
887 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
888 {
889 switch (interpolate) {
890 case TGSI_INTERPOLATE_CONSTANT:
891 return 0;
892
893 case TGSI_INTERPOLATE_LINEAR:
894 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
895 return SI_PARAM_LINEAR_SAMPLE;
896 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
897 return SI_PARAM_LINEAR_CENTROID;
898 else
899 return SI_PARAM_LINEAR_CENTER;
900 break;
901 case TGSI_INTERPOLATE_COLOR:
902 case TGSI_INTERPOLATE_PERSPECTIVE:
903 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
904 return SI_PARAM_PERSP_SAMPLE;
905 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
906 return SI_PARAM_PERSP_CENTROID;
907 else
908 return SI_PARAM_PERSP_CENTER;
909 break;
910 default:
911 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
912 return -1;
913 }
914 }
915
916 /* This shouldn't be used by explicit INTERP opcodes. */
917 static unsigned select_interp_param(struct si_shader_context *ctx,
918 unsigned param)
919 {
920 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
921 !ctx->is_monolithic)
922 return param;
923
924 /* If the shader doesn't use center/centroid, just return the parameter.
925 *
926 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
927 * switch between center/centroid and sample without shader changes.
928 */
929 switch (param) {
930 case SI_PARAM_PERSP_CENTROID:
931 case SI_PARAM_PERSP_CENTER:
932 return SI_PARAM_PERSP_SAMPLE;
933
934 case SI_PARAM_LINEAR_CENTROID:
935 case SI_PARAM_LINEAR_CENTER:
936 return SI_PARAM_LINEAR_SAMPLE;
937
938 default:
939 return param;
940 }
941 }
942
943 /**
944 * Interpolate a fragment shader input.
945 *
946 * @param ctx context
947 * @param input_index index of the input in hardware
948 * @param semantic_name TGSI_SEMANTIC_*
949 * @param semantic_index semantic index
950 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
951 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
952 * @param interp_param interpolation weights (i,j)
953 * @param prim_mask SI_PARAM_PRIM_MASK
954 * @param face SI_PARAM_FRONT_FACE
955 * @param result the return value (4 components)
956 */
957 static void interp_fs_input(struct si_shader_context *ctx,
958 unsigned input_index,
959 unsigned semantic_name,
960 unsigned semantic_index,
961 unsigned num_interp_inputs,
962 unsigned colors_read_mask,
963 LLVMValueRef interp_param,
964 LLVMValueRef prim_mask,
965 LLVMValueRef face,
966 LLVMValueRef result[4])
967 {
968 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
969 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
970 struct gallivm_state *gallivm = base->gallivm;
971 const char *intr_name;
972 LLVMValueRef attr_number;
973
974 unsigned chan;
975
976 attr_number = lp_build_const_int32(gallivm, input_index);
977
978 /* fs.constant returns the param from the middle vertex, so it's not
979 * really useful for flat shading. It's meant to be used for custom
980 * interpolation (but the intrinsic can't fetch from the other two
981 * vertices).
982 *
983 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
984 * to do the right thing. The only reason we use fs.constant is that
985 * fs.interp cannot be used on integers, because they can be equal
986 * to NaN.
987 */
988 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
989
990 if (semantic_name == TGSI_SEMANTIC_COLOR &&
991 ctx->shader->key.ps.prolog.color_two_side) {
992 LLVMValueRef args[4];
993 LLVMValueRef is_face_positive;
994 LLVMValueRef back_attr_number;
995
996 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
997 * otherwise it's at offset "num_inputs".
998 */
999 unsigned back_attr_offset = num_interp_inputs;
1000 if (semantic_index == 1 && colors_read_mask & 0xf)
1001 back_attr_offset += 1;
1002
1003 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1004
1005 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1006 face, uint->zero, "");
1007
1008 args[2] = prim_mask;
1009 args[3] = interp_param;
1010 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1011 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1012 LLVMValueRef front, back;
1013
1014 args[0] = llvm_chan;
1015 args[1] = attr_number;
1016 front = lp_build_intrinsic(gallivm->builder, intr_name,
1017 ctx->f32, args, args[3] ? 4 : 3,
1018 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1019
1020 args[1] = back_attr_number;
1021 back = lp_build_intrinsic(gallivm->builder, intr_name,
1022 ctx->f32, args, args[3] ? 4 : 3,
1023 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1024
1025 result[chan] = LLVMBuildSelect(gallivm->builder,
1026 is_face_positive,
1027 front,
1028 back,
1029 "");
1030 }
1031 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1032 LLVMValueRef args[4];
1033
1034 args[0] = uint->zero;
1035 args[1] = attr_number;
1036 args[2] = prim_mask;
1037 args[3] = interp_param;
1038 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1039 ctx->f32, args, args[3] ? 4 : 3,
1040 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1041 result[1] =
1042 result[2] = lp_build_const_float(gallivm, 0.0f);
1043 result[3] = lp_build_const_float(gallivm, 1.0f);
1044 } else {
1045 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1046 LLVMValueRef args[4];
1047 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1048
1049 args[0] = llvm_chan;
1050 args[1] = attr_number;
1051 args[2] = prim_mask;
1052 args[3] = interp_param;
1053 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1054 ctx->f32, args, args[3] ? 4 : 3,
1055 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1056 }
1057 }
1058 }
1059
1060 static void declare_input_fs(
1061 struct radeon_llvm_context *radeon_bld,
1062 unsigned input_index,
1063 const struct tgsi_full_declaration *decl)
1064 {
1065 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1066 struct si_shader_context *ctx =
1067 si_shader_context(&radeon_bld->soa.bld_base);
1068 struct si_shader *shader = ctx->shader;
1069 LLVMValueRef main_fn = radeon_bld->main_fn;
1070 LLVMValueRef interp_param = NULL;
1071 int interp_param_idx;
1072
1073 /* Get colors from input VGPRs (set by the prolog). */
1074 if (!ctx->is_monolithic &&
1075 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1076 unsigned i = decl->Semantic.Index;
1077 unsigned colors_read = shader->selector->info.colors_read;
1078 unsigned mask = colors_read >> (i * 4);
1079 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1080 (i ? util_bitcount(colors_read & 0xf) : 0);
1081
1082 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1083 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1084 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1085 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1086 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1087 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1088 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1089 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1090 return;
1091 }
1092
1093 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1094 decl->Interp.Location);
1095 if (interp_param_idx == -1)
1096 return;
1097 else if (interp_param_idx) {
1098 interp_param_idx = select_interp_param(ctx,
1099 interp_param_idx);
1100 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1101 }
1102
1103 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1104 decl->Semantic.Index, shader->selector->info.num_inputs,
1105 shader->selector->info.colors_read, interp_param,
1106 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1107 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1108 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1109 }
1110
1111 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1112 {
1113 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1114 SI_PARAM_ANCILLARY, 8, 4);
1115 }
1116
1117 /**
1118 * Load a dword from a constant buffer.
1119 */
1120 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1121 LLVMValueRef offset, LLVMTypeRef return_type)
1122 {
1123 LLVMValueRef args[2] = {resource, offset};
1124
1125 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1126 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1127 }
1128
1129 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1130 {
1131 struct si_shader_context *ctx =
1132 si_shader_context(&radeon_bld->soa.bld_base);
1133 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1134 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1135 LLVMBuilderRef builder = gallivm->builder;
1136 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1137 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1138 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1139
1140 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1141 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1142 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1143
1144 LLVMValueRef pos[4] = {
1145 buffer_load_const(builder, resource, offset0, ctx->f32),
1146 buffer_load_const(builder, resource, offset1, ctx->f32),
1147 lp_build_const_float(gallivm, 0),
1148 lp_build_const_float(gallivm, 0)
1149 };
1150
1151 return lp_build_gather_values(gallivm, pos, 4);
1152 }
1153
1154 static void declare_system_value(
1155 struct radeon_llvm_context *radeon_bld,
1156 unsigned index,
1157 const struct tgsi_full_declaration *decl)
1158 {
1159 struct si_shader_context *ctx =
1160 si_shader_context(&radeon_bld->soa.bld_base);
1161 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1162 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1163 LLVMValueRef value = 0;
1164
1165 switch (decl->Semantic.Name) {
1166 case TGSI_SEMANTIC_INSTANCEID:
1167 value = LLVMGetParam(radeon_bld->main_fn,
1168 ctx->param_instance_id);
1169 break;
1170
1171 case TGSI_SEMANTIC_VERTEXID:
1172 value = LLVMBuildAdd(gallivm->builder,
1173 LLVMGetParam(radeon_bld->main_fn,
1174 ctx->param_vertex_id),
1175 LLVMGetParam(radeon_bld->main_fn,
1176 SI_PARAM_BASE_VERTEX), "");
1177 break;
1178
1179 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1180 value = LLVMGetParam(radeon_bld->main_fn,
1181 ctx->param_vertex_id);
1182 break;
1183
1184 case TGSI_SEMANTIC_BASEVERTEX:
1185 value = LLVMGetParam(radeon_bld->main_fn,
1186 SI_PARAM_BASE_VERTEX);
1187 break;
1188
1189 case TGSI_SEMANTIC_INVOCATIONID:
1190 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1191 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1192 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1193 value = LLVMGetParam(radeon_bld->main_fn,
1194 SI_PARAM_GS_INSTANCE_ID);
1195 else
1196 assert(!"INVOCATIONID not implemented");
1197 break;
1198
1199 case TGSI_SEMANTIC_POSITION:
1200 {
1201 LLVMValueRef pos[4] = {
1202 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1203 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1204 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1205 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1206 LLVMGetParam(radeon_bld->main_fn,
1207 SI_PARAM_POS_W_FLOAT)),
1208 };
1209 value = lp_build_gather_values(gallivm, pos, 4);
1210 break;
1211 }
1212
1213 case TGSI_SEMANTIC_FACE:
1214 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1215 break;
1216
1217 case TGSI_SEMANTIC_SAMPLEID:
1218 value = get_sample_id(radeon_bld);
1219 break;
1220
1221 case TGSI_SEMANTIC_SAMPLEPOS: {
1222 LLVMValueRef pos[4] = {
1223 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1224 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1225 lp_build_const_float(gallivm, 0),
1226 lp_build_const_float(gallivm, 0)
1227 };
1228 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1229 TGSI_OPCODE_FRC, pos[0]);
1230 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1231 TGSI_OPCODE_FRC, pos[1]);
1232 value = lp_build_gather_values(gallivm, pos, 4);
1233 break;
1234 }
1235
1236 case TGSI_SEMANTIC_SAMPLEMASK:
1237 /* This can only occur with the OpenGL Core profile, which
1238 * doesn't support smoothing.
1239 */
1240 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1241 break;
1242
1243 case TGSI_SEMANTIC_TESSCOORD:
1244 {
1245 LLVMValueRef coord[4] = {
1246 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1247 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1248 bld->zero,
1249 bld->zero
1250 };
1251
1252 /* For triangles, the vector should be (u, v, 1-u-v). */
1253 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1254 PIPE_PRIM_TRIANGLES)
1255 coord[2] = lp_build_sub(bld, bld->one,
1256 lp_build_add(bld, coord[0], coord[1]));
1257
1258 value = lp_build_gather_values(gallivm, coord, 4);
1259 break;
1260 }
1261
1262 case TGSI_SEMANTIC_VERTICESIN:
1263 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1264 break;
1265
1266 case TGSI_SEMANTIC_TESSINNER:
1267 case TGSI_SEMANTIC_TESSOUTER:
1268 {
1269 LLVMValueRef dw_addr;
1270 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1271
1272 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1273 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1274 lp_build_const_int32(gallivm, param * 4), "");
1275
1276 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1277 ~0, dw_addr);
1278 break;
1279 }
1280
1281 case TGSI_SEMANTIC_PRIMID:
1282 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1283 break;
1284
1285 default:
1286 assert(!"unknown system value");
1287 return;
1288 }
1289
1290 radeon_bld->system_values[index] = value;
1291 }
1292
1293 static LLVMValueRef fetch_constant(
1294 struct lp_build_tgsi_context *bld_base,
1295 const struct tgsi_full_src_register *reg,
1296 enum tgsi_opcode_type type,
1297 unsigned swizzle)
1298 {
1299 struct si_shader_context *ctx = si_shader_context(bld_base);
1300 struct lp_build_context *base = &bld_base->base;
1301 const struct tgsi_ind_register *ireg = &reg->Indirect;
1302 unsigned buf, idx;
1303
1304 LLVMValueRef addr, bufp;
1305 LLVMValueRef result;
1306
1307 if (swizzle == LP_CHAN_ALL) {
1308 unsigned chan;
1309 LLVMValueRef values[4];
1310 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1311 values[chan] = fetch_constant(bld_base, reg, type, chan);
1312
1313 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1314 }
1315
1316 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1317 idx = reg->Register.Index * 4 + swizzle;
1318
1319 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1320 if (type != TGSI_TYPE_DOUBLE)
1321 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1322 else {
1323 return radeon_llvm_emit_fetch_double(bld_base,
1324 ctx->constants[buf][idx],
1325 ctx->constants[buf][idx + 1]);
1326 }
1327 }
1328
1329 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1330 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1331 LLVMValueRef index;
1332 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1333 reg->Dimension.Index,
1334 SI_NUM_USER_CONST_BUFFERS);
1335 bufp = build_indexed_load_const(ctx, ptr, index);
1336 } else
1337 bufp = ctx->const_buffers[buf];
1338
1339 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1340 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1341 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1342 addr = lp_build_add(&bld_base->uint_bld, addr,
1343 lp_build_const_int32(base->gallivm, idx * 4));
1344
1345 result = buffer_load_const(base->gallivm->builder, bufp,
1346 addr, ctx->f32);
1347
1348 if (type != TGSI_TYPE_DOUBLE)
1349 result = bitcast(bld_base, type, result);
1350 else {
1351 LLVMValueRef addr2, result2;
1352 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1353 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1354 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1355 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1356 lp_build_const_int32(base->gallivm, idx * 4));
1357
1358 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1359 addr2, ctx->f32);
1360
1361 result = radeon_llvm_emit_fetch_double(bld_base,
1362 result, result2);
1363 }
1364 return result;
1365 }
1366
1367 /* Upper 16 bits must be zero. */
1368 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1369 LLVMValueRef val[2])
1370 {
1371 return LLVMBuildOr(gallivm->builder, val[0],
1372 LLVMBuildShl(gallivm->builder, val[1],
1373 lp_build_const_int32(gallivm, 16),
1374 ""), "");
1375 }
1376
1377 /* Upper 16 bits are ignored and will be dropped. */
1378 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1379 LLVMValueRef val[2])
1380 {
1381 LLVMValueRef v[2] = {
1382 LLVMBuildAnd(gallivm->builder, val[0],
1383 lp_build_const_int32(gallivm, 0xffff), ""),
1384 val[1],
1385 };
1386 return si_llvm_pack_two_int16(gallivm, v);
1387 }
1388
1389 /* Initialize arguments for the shader export intrinsic */
1390 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1391 LLVMValueRef *values,
1392 unsigned target,
1393 LLVMValueRef *args)
1394 {
1395 struct si_shader_context *ctx = si_shader_context(bld_base);
1396 struct lp_build_context *uint =
1397 &ctx->radeon_bld.soa.bld_base.uint_bld;
1398 struct lp_build_context *base = &bld_base->base;
1399 struct gallivm_state *gallivm = base->gallivm;
1400 LLVMBuilderRef builder = base->gallivm->builder;
1401 LLVMValueRef val[4];
1402 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1403 unsigned chan;
1404 bool is_int8;
1405
1406 /* Default is 0xf. Adjusted below depending on the format. */
1407 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1408
1409 /* Specify whether the EXEC mask represents the valid mask */
1410 args[1] = uint->zero;
1411
1412 /* Specify whether this is the last export */
1413 args[2] = uint->zero;
1414
1415 /* Specify the target we are exporting */
1416 args[3] = lp_build_const_int32(base->gallivm, target);
1417
1418 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1419 const union si_shader_key *key = &ctx->shader->key;
1420 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1421 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1422
1423 assert(cbuf >= 0 && cbuf < 8);
1424 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1425 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1426 }
1427
1428 args[4] = uint->zero; /* COMPR flag */
1429 args[5] = base->undef;
1430 args[6] = base->undef;
1431 args[7] = base->undef;
1432 args[8] = base->undef;
1433
1434 switch (spi_shader_col_format) {
1435 case V_028714_SPI_SHADER_ZERO:
1436 args[0] = uint->zero; /* writemask */
1437 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1438 break;
1439
1440 case V_028714_SPI_SHADER_32_R:
1441 args[0] = uint->one; /* writemask */
1442 args[5] = values[0];
1443 break;
1444
1445 case V_028714_SPI_SHADER_32_GR:
1446 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1447 args[5] = values[0];
1448 args[6] = values[1];
1449 break;
1450
1451 case V_028714_SPI_SHADER_32_AR:
1452 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1453 args[5] = values[0];
1454 args[8] = values[3];
1455 break;
1456
1457 case V_028714_SPI_SHADER_FP16_ABGR:
1458 args[4] = uint->one; /* COMPR flag */
1459
1460 for (chan = 0; chan < 2; chan++) {
1461 LLVMValueRef pack_args[2] = {
1462 values[2 * chan],
1463 values[2 * chan + 1]
1464 };
1465 LLVMValueRef packed;
1466
1467 packed = lp_build_intrinsic(base->gallivm->builder,
1468 "llvm.SI.packf16",
1469 ctx->i32, pack_args, 2,
1470 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1471 args[chan + 5] =
1472 LLVMBuildBitCast(base->gallivm->builder,
1473 packed, ctx->f32, "");
1474 }
1475 break;
1476
1477 case V_028714_SPI_SHADER_UNORM16_ABGR:
1478 for (chan = 0; chan < 4; chan++) {
1479 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1480 val[chan] = LLVMBuildFMul(builder, val[chan],
1481 lp_build_const_float(gallivm, 65535), "");
1482 val[chan] = LLVMBuildFAdd(builder, val[chan],
1483 lp_build_const_float(gallivm, 0.5), "");
1484 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1485 ctx->i32, "");
1486 }
1487
1488 args[4] = uint->one; /* COMPR flag */
1489 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1490 si_llvm_pack_two_int16(gallivm, val));
1491 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1492 si_llvm_pack_two_int16(gallivm, val+2));
1493 break;
1494
1495 case V_028714_SPI_SHADER_SNORM16_ABGR:
1496 for (chan = 0; chan < 4; chan++) {
1497 /* Clamp between [-1, 1]. */
1498 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1499 values[chan],
1500 lp_build_const_float(gallivm, 1));
1501 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1502 val[chan],
1503 lp_build_const_float(gallivm, -1));
1504 /* Convert to a signed integer in [-32767, 32767]. */
1505 val[chan] = LLVMBuildFMul(builder, val[chan],
1506 lp_build_const_float(gallivm, 32767), "");
1507 /* If positive, add 0.5, else add -0.5. */
1508 val[chan] = LLVMBuildFAdd(builder, val[chan],
1509 LLVMBuildSelect(builder,
1510 LLVMBuildFCmp(builder, LLVMRealOGE,
1511 val[chan], base->zero, ""),
1512 lp_build_const_float(gallivm, 0.5),
1513 lp_build_const_float(gallivm, -0.5), ""), "");
1514 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1515 }
1516
1517 args[4] = uint->one; /* COMPR flag */
1518 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1519 si_llvm_pack_two_int32_as_int16(gallivm, val));
1520 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1521 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1522 break;
1523
1524 case V_028714_SPI_SHADER_UINT16_ABGR: {
1525 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1526 255 : 65535);
1527 /* Clamp. */
1528 for (chan = 0; chan < 4; chan++) {
1529 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1530 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1531 val[chan], max);
1532 }
1533
1534 args[4] = uint->one; /* COMPR flag */
1535 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1536 si_llvm_pack_two_int16(gallivm, val));
1537 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1538 si_llvm_pack_two_int16(gallivm, val+2));
1539 break;
1540 }
1541
1542 case V_028714_SPI_SHADER_SINT16_ABGR: {
1543 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1544 127 : 32767);
1545 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1546 -128 : -32768);
1547 /* Clamp. */
1548 for (chan = 0; chan < 4; chan++) {
1549 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1550 val[chan] = lp_build_emit_llvm_binary(bld_base,
1551 TGSI_OPCODE_IMIN,
1552 val[chan], max);
1553 val[chan] = lp_build_emit_llvm_binary(bld_base,
1554 TGSI_OPCODE_IMAX,
1555 val[chan], min);
1556 }
1557
1558 args[4] = uint->one; /* COMPR flag */
1559 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1560 si_llvm_pack_two_int32_as_int16(gallivm, val));
1561 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1562 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1563 break;
1564 }
1565
1566 case V_028714_SPI_SHADER_32_ABGR:
1567 memcpy(&args[5], values, sizeof(values[0]) * 4);
1568 break;
1569 }
1570 }
1571
1572 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1573 LLVMValueRef alpha)
1574 {
1575 struct si_shader_context *ctx = si_shader_context(bld_base);
1576 struct gallivm_state *gallivm = bld_base->base.gallivm;
1577
1578 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1579 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1580 SI_PARAM_ALPHA_REF);
1581
1582 LLVMValueRef alpha_pass =
1583 lp_build_cmp(&bld_base->base,
1584 ctx->shader->key.ps.epilog.alpha_func,
1585 alpha, alpha_ref);
1586 LLVMValueRef arg =
1587 lp_build_select(&bld_base->base,
1588 alpha_pass,
1589 lp_build_const_float(gallivm, 1.0f),
1590 lp_build_const_float(gallivm, -1.0f));
1591
1592 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1593 ctx->voidt, &arg, 1, 0);
1594 } else {
1595 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1596 ctx->voidt, NULL, 0, 0);
1597 }
1598 }
1599
1600 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1601 LLVMValueRef alpha,
1602 unsigned samplemask_param)
1603 {
1604 struct si_shader_context *ctx = si_shader_context(bld_base);
1605 struct gallivm_state *gallivm = bld_base->base.gallivm;
1606 LLVMValueRef coverage;
1607
1608 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1609 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1610 samplemask_param);
1611 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1612
1613 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1614 ctx->i32,
1615 &coverage, 1, LLVMReadNoneAttribute);
1616
1617 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1618 ctx->f32, "");
1619
1620 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1621 lp_build_const_float(gallivm,
1622 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1623
1624 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1625 }
1626
1627 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1628 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1629 {
1630 struct si_shader_context *ctx = si_shader_context(bld_base);
1631 struct lp_build_context *base = &bld_base->base;
1632 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1633 unsigned reg_index;
1634 unsigned chan;
1635 unsigned const_chan;
1636 LLVMValueRef base_elt;
1637 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1638 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1639 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1640
1641 for (reg_index = 0; reg_index < 2; reg_index ++) {
1642 LLVMValueRef *args = pos[2 + reg_index];
1643
1644 args[5] =
1645 args[6] =
1646 args[7] =
1647 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1648
1649 /* Compute dot products of position and user clip plane vectors */
1650 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1651 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1652 args[1] = lp_build_const_int32(base->gallivm,
1653 ((reg_index * 4 + chan) * 4 +
1654 const_chan) * 4);
1655 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1656 args[1], ctx->f32);
1657 args[5 + chan] =
1658 lp_build_add(base, args[5 + chan],
1659 lp_build_mul(base, base_elt,
1660 out_elts[const_chan]));
1661 }
1662 }
1663
1664 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1665 args[1] = uint->zero;
1666 args[2] = uint->zero;
1667 args[3] = lp_build_const_int32(base->gallivm,
1668 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1669 args[4] = uint->zero;
1670 }
1671 }
1672
1673 static void si_dump_streamout(struct pipe_stream_output_info *so)
1674 {
1675 unsigned i;
1676
1677 if (so->num_outputs)
1678 fprintf(stderr, "STREAMOUT\n");
1679
1680 for (i = 0; i < so->num_outputs; i++) {
1681 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1682 so->output[i].start_component;
1683 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1684 i, so->output[i].output_buffer,
1685 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1686 so->output[i].register_index,
1687 mask & 1 ? "x" : "",
1688 mask & 2 ? "y" : "",
1689 mask & 4 ? "z" : "",
1690 mask & 8 ? "w" : "");
1691 }
1692 }
1693
1694 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1695 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1696 * or v4i32 (num_channels=3,4). */
1697 static void build_tbuffer_store(struct si_shader_context *ctx,
1698 LLVMValueRef rsrc,
1699 LLVMValueRef vdata,
1700 unsigned num_channels,
1701 LLVMValueRef vaddr,
1702 LLVMValueRef soffset,
1703 unsigned inst_offset,
1704 unsigned dfmt,
1705 unsigned nfmt,
1706 unsigned offen,
1707 unsigned idxen,
1708 unsigned glc,
1709 unsigned slc,
1710 unsigned tfe)
1711 {
1712 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1713 LLVMValueRef args[] = {
1714 rsrc,
1715 vdata,
1716 LLVMConstInt(ctx->i32, num_channels, 0),
1717 vaddr,
1718 soffset,
1719 LLVMConstInt(ctx->i32, inst_offset, 0),
1720 LLVMConstInt(ctx->i32, dfmt, 0),
1721 LLVMConstInt(ctx->i32, nfmt, 0),
1722 LLVMConstInt(ctx->i32, offen, 0),
1723 LLVMConstInt(ctx->i32, idxen, 0),
1724 LLVMConstInt(ctx->i32, glc, 0),
1725 LLVMConstInt(ctx->i32, slc, 0),
1726 LLVMConstInt(ctx->i32, tfe, 0)
1727 };
1728
1729 /* The instruction offset field has 12 bits */
1730 assert(offen || inst_offset < (1 << 12));
1731
1732 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1733 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1734 const char *types[] = {"i32", "v2i32", "v4i32"};
1735 char name[256];
1736 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1737
1738 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1739 args, Elements(args), 0);
1740 }
1741
1742 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1743 LLVMValueRef rsrc,
1744 LLVMValueRef vdata,
1745 unsigned num_channels,
1746 LLVMValueRef vaddr,
1747 LLVMValueRef soffset,
1748 unsigned inst_offset)
1749 {
1750 static unsigned dfmt[] = {
1751 V_008F0C_BUF_DATA_FORMAT_32,
1752 V_008F0C_BUF_DATA_FORMAT_32_32,
1753 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1754 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1755 };
1756 assert(num_channels >= 1 && num_channels <= 4);
1757
1758 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1759 inst_offset, dfmt[num_channels-1],
1760 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1761 }
1762
1763 /* On SI, the vertex shader is responsible for writing streamout data
1764 * to buffers. */
1765 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1766 struct si_shader_output_values *outputs,
1767 unsigned noutput)
1768 {
1769 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1770 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1771 LLVMBuilderRef builder = gallivm->builder;
1772 int i, j;
1773 struct lp_build_if_state if_ctx;
1774
1775 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1776 LLVMValueRef so_vtx_count =
1777 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1778
1779 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1780 NULL, 0, LLVMReadNoneAttribute);
1781
1782 /* can_emit = tid < so_vtx_count; */
1783 LLVMValueRef can_emit =
1784 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1785
1786 LLVMValueRef stream_id =
1787 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1788
1789 /* Emit the streamout code conditionally. This actually avoids
1790 * out-of-bounds buffer access. The hw tells us via the SGPR
1791 * (so_vtx_count) which threads are allowed to emit streamout data. */
1792 lp_build_if(&if_ctx, gallivm, can_emit);
1793 {
1794 /* The buffer offset is computed as follows:
1795 * ByteOffset = streamout_offset[buffer_id]*4 +
1796 * (streamout_write_index + thread_id)*stride[buffer_id] +
1797 * attrib_offset
1798 */
1799
1800 LLVMValueRef so_write_index =
1801 LLVMGetParam(ctx->radeon_bld.main_fn,
1802 ctx->param_streamout_write_index);
1803
1804 /* Compute (streamout_write_index + thread_id). */
1805 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1806
1807 /* Compute the write offset for each enabled buffer. */
1808 LLVMValueRef so_write_offset[4] = {};
1809 for (i = 0; i < 4; i++) {
1810 if (!so->stride[i])
1811 continue;
1812
1813 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1814 ctx->param_streamout_offset[i]);
1815 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1816
1817 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1818 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1819 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1820 }
1821
1822 /* Write streamout data. */
1823 for (i = 0; i < so->num_outputs; i++) {
1824 unsigned buf_idx = so->output[i].output_buffer;
1825 unsigned reg = so->output[i].register_index;
1826 unsigned start = so->output[i].start_component;
1827 unsigned num_comps = so->output[i].num_components;
1828 unsigned stream = so->output[i].stream;
1829 LLVMValueRef out[4];
1830 struct lp_build_if_state if_ctx_stream;
1831
1832 assert(num_comps && num_comps <= 4);
1833 if (!num_comps || num_comps > 4)
1834 continue;
1835
1836 if (reg >= noutput)
1837 continue;
1838
1839 /* Load the output as int. */
1840 for (j = 0; j < num_comps; j++) {
1841 out[j] = LLVMBuildBitCast(builder,
1842 outputs[reg].values[start+j],
1843 ctx->i32, "");
1844 }
1845
1846 /* Pack the output. */
1847 LLVMValueRef vdata = NULL;
1848
1849 switch (num_comps) {
1850 case 1: /* as i32 */
1851 vdata = out[0];
1852 break;
1853 case 2: /* as v2i32 */
1854 case 3: /* as v4i32 (aligned to 4) */
1855 case 4: /* as v4i32 */
1856 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1857 for (j = 0; j < num_comps; j++) {
1858 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1859 LLVMConstInt(ctx->i32, j, 0), "");
1860 }
1861 break;
1862 }
1863
1864 LLVMValueRef can_emit_stream =
1865 LLVMBuildICmp(builder, LLVMIntEQ,
1866 stream_id,
1867 lp_build_const_int32(gallivm, stream), "");
1868
1869 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1870 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1871 vdata, num_comps,
1872 so_write_offset[buf_idx],
1873 LLVMConstInt(ctx->i32, 0, 0),
1874 so->output[i].dst_offset*4);
1875 lp_build_endif(&if_ctx_stream);
1876 }
1877 }
1878 lp_build_endif(&if_ctx);
1879 }
1880
1881
1882 /* Generate export instructions for hardware VS shader stage */
1883 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1884 struct si_shader_output_values *outputs,
1885 unsigned noutput)
1886 {
1887 struct si_shader_context *ctx = si_shader_context(bld_base);
1888 struct si_shader *shader = ctx->shader;
1889 struct lp_build_context *base = &bld_base->base;
1890 struct lp_build_context *uint =
1891 &ctx->radeon_bld.soa.bld_base.uint_bld;
1892 LLVMValueRef args[9];
1893 LLVMValueRef pos_args[4][9] = { { 0 } };
1894 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1895 unsigned semantic_name, semantic_index;
1896 unsigned target;
1897 unsigned param_count = 0;
1898 unsigned pos_idx;
1899 int i;
1900
1901 if (outputs && ctx->shader->selector->so.num_outputs) {
1902 si_llvm_emit_streamout(ctx, outputs, noutput);
1903 }
1904
1905 for (i = 0; i < noutput; i++) {
1906 semantic_name = outputs[i].name;
1907 semantic_index = outputs[i].sid;
1908
1909 handle_semantic:
1910 /* Select the correct target */
1911 switch(semantic_name) {
1912 case TGSI_SEMANTIC_PSIZE:
1913 psize_value = outputs[i].values[0];
1914 continue;
1915 case TGSI_SEMANTIC_EDGEFLAG:
1916 edgeflag_value = outputs[i].values[0];
1917 continue;
1918 case TGSI_SEMANTIC_LAYER:
1919 layer_value = outputs[i].values[0];
1920 semantic_name = TGSI_SEMANTIC_GENERIC;
1921 goto handle_semantic;
1922 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1923 viewport_index_value = outputs[i].values[0];
1924 semantic_name = TGSI_SEMANTIC_GENERIC;
1925 goto handle_semantic;
1926 case TGSI_SEMANTIC_POSITION:
1927 target = V_008DFC_SQ_EXP_POS;
1928 break;
1929 case TGSI_SEMANTIC_COLOR:
1930 case TGSI_SEMANTIC_BCOLOR:
1931 target = V_008DFC_SQ_EXP_PARAM + param_count;
1932 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1933 shader->info.vs_output_param_offset[i] = param_count;
1934 param_count++;
1935 break;
1936 case TGSI_SEMANTIC_CLIPDIST:
1937 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1938 break;
1939 case TGSI_SEMANTIC_CLIPVERTEX:
1940 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1941 continue;
1942 case TGSI_SEMANTIC_PRIMID:
1943 case TGSI_SEMANTIC_FOG:
1944 case TGSI_SEMANTIC_TEXCOORD:
1945 case TGSI_SEMANTIC_GENERIC:
1946 target = V_008DFC_SQ_EXP_PARAM + param_count;
1947 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1948 shader->info.vs_output_param_offset[i] = param_count;
1949 param_count++;
1950 break;
1951 default:
1952 target = 0;
1953 fprintf(stderr,
1954 "Warning: SI unhandled vs output type:%d\n",
1955 semantic_name);
1956 }
1957
1958 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1959
1960 if (target >= V_008DFC_SQ_EXP_POS &&
1961 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1962 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1963 args, sizeof(args));
1964 } else {
1965 lp_build_intrinsic(base->gallivm->builder,
1966 "llvm.SI.export", ctx->voidt,
1967 args, 9, 0);
1968 }
1969
1970 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1971 semantic_name = TGSI_SEMANTIC_GENERIC;
1972 goto handle_semantic;
1973 }
1974 }
1975
1976 shader->info.nr_param_exports = param_count;
1977
1978 /* We need to add the position output manually if it's missing. */
1979 if (!pos_args[0][0]) {
1980 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1981 pos_args[0][1] = uint->zero; /* EXEC mask */
1982 pos_args[0][2] = uint->zero; /* last export? */
1983 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1984 pos_args[0][4] = uint->zero; /* COMPR flag */
1985 pos_args[0][5] = base->zero; /* X */
1986 pos_args[0][6] = base->zero; /* Y */
1987 pos_args[0][7] = base->zero; /* Z */
1988 pos_args[0][8] = base->one; /* W */
1989 }
1990
1991 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1992 if (shader->selector->info.writes_psize ||
1993 shader->selector->info.writes_edgeflag ||
1994 shader->selector->info.writes_viewport_index ||
1995 shader->selector->info.writes_layer) {
1996 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1997 shader->selector->info.writes_psize |
1998 (shader->selector->info.writes_edgeflag << 1) |
1999 (shader->selector->info.writes_layer << 2) |
2000 (shader->selector->info.writes_viewport_index << 3));
2001 pos_args[1][1] = uint->zero; /* EXEC mask */
2002 pos_args[1][2] = uint->zero; /* last export? */
2003 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2004 pos_args[1][4] = uint->zero; /* COMPR flag */
2005 pos_args[1][5] = base->zero; /* X */
2006 pos_args[1][6] = base->zero; /* Y */
2007 pos_args[1][7] = base->zero; /* Z */
2008 pos_args[1][8] = base->zero; /* W */
2009
2010 if (shader->selector->info.writes_psize)
2011 pos_args[1][5] = psize_value;
2012
2013 if (shader->selector->info.writes_edgeflag) {
2014 /* The output is a float, but the hw expects an integer
2015 * with the first bit containing the edge flag. */
2016 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2017 edgeflag_value,
2018 ctx->i32, "");
2019 edgeflag_value = lp_build_min(&bld_base->int_bld,
2020 edgeflag_value,
2021 bld_base->int_bld.one);
2022
2023 /* The LLVM intrinsic expects a float. */
2024 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2025 edgeflag_value,
2026 ctx->f32, "");
2027 }
2028
2029 if (shader->selector->info.writes_layer)
2030 pos_args[1][7] = layer_value;
2031
2032 if (shader->selector->info.writes_viewport_index)
2033 pos_args[1][8] = viewport_index_value;
2034 }
2035
2036 for (i = 0; i < 4; i++)
2037 if (pos_args[i][0])
2038 shader->info.nr_pos_exports++;
2039
2040 pos_idx = 0;
2041 for (i = 0; i < 4; i++) {
2042 if (!pos_args[i][0])
2043 continue;
2044
2045 /* Specify the target we are exporting */
2046 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2047
2048 if (pos_idx == shader->info.nr_pos_exports)
2049 /* Specify that this is the last export */
2050 pos_args[i][2] = uint->one;
2051
2052 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2053 ctx->voidt, pos_args[i], 9, 0);
2054 }
2055 }
2056
2057 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2058 LLVMValueRef rel_patch_id,
2059 LLVMValueRef invocation_id,
2060 LLVMValueRef tcs_out_current_patch_data_offset)
2061 {
2062 struct si_shader_context *ctx = si_shader_context(bld_base);
2063 struct gallivm_state *gallivm = bld_base->base.gallivm;
2064 struct si_shader *shader = ctx->shader;
2065 unsigned tess_inner_index, tess_outer_index;
2066 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2067 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2068 unsigned stride, outer_comps, inner_comps, i;
2069 struct lp_build_if_state if_ctx;
2070
2071 /* Do this only for invocation 0, because the tess levels are per-patch,
2072 * not per-vertex.
2073 *
2074 * This can't jump, because invocation 0 executes this. It should
2075 * at least mask out the loads and stores for other invocations.
2076 */
2077 lp_build_if(&if_ctx, gallivm,
2078 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2079 invocation_id, bld_base->uint_bld.zero, ""));
2080
2081 /* Determine the layout of one tess factor element in the buffer. */
2082 switch (shader->key.tcs.epilog.prim_mode) {
2083 case PIPE_PRIM_LINES:
2084 stride = 2; /* 2 dwords, 1 vec2 store */
2085 outer_comps = 2;
2086 inner_comps = 0;
2087 break;
2088 case PIPE_PRIM_TRIANGLES:
2089 stride = 4; /* 4 dwords, 1 vec4 store */
2090 outer_comps = 3;
2091 inner_comps = 1;
2092 break;
2093 case PIPE_PRIM_QUADS:
2094 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2095 outer_comps = 4;
2096 inner_comps = 2;
2097 break;
2098 default:
2099 assert(0);
2100 return;
2101 }
2102
2103 /* Load tess_inner and tess_outer from LDS.
2104 * Any invocation can write them, so we can't get them from a temporary.
2105 */
2106 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2107 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2108
2109 lds_base = tcs_out_current_patch_data_offset;
2110 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2111 lp_build_const_int32(gallivm,
2112 tess_inner_index * 4), "");
2113 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2114 lp_build_const_int32(gallivm,
2115 tess_outer_index * 4), "");
2116
2117 for (i = 0; i < outer_comps; i++)
2118 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2119 for (i = 0; i < inner_comps; i++)
2120 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2121
2122 /* Convert the outputs to vectors for stores. */
2123 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2124 vec1 = NULL;
2125
2126 if (stride > 4)
2127 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2128
2129 /* Get the buffer. */
2130 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2131 SI_PARAM_RW_BUFFERS);
2132 buffer = build_indexed_load_const(ctx, rw_buffers,
2133 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2134
2135 /* Get the offset. */
2136 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2137 SI_PARAM_TESS_FACTOR_OFFSET);
2138 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2139 lp_build_const_int32(gallivm, 4 * stride), "");
2140
2141 /* Store the outputs. */
2142 build_tbuffer_store_dwords(ctx, buffer, vec0,
2143 MIN2(stride, 4), byteoffset, tf_base, 0);
2144 if (vec1)
2145 build_tbuffer_store_dwords(ctx, buffer, vec1,
2146 stride - 4, byteoffset, tf_base, 16);
2147 lp_build_endif(&if_ctx);
2148 }
2149
2150 /* This only writes the tessellation factor levels. */
2151 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2152 {
2153 struct si_shader_context *ctx = si_shader_context(bld_base);
2154 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2155
2156 rel_patch_id = get_rel_patch_id(ctx);
2157 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2158 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2159
2160 if (!ctx->is_monolithic) {
2161 /* Return epilog parameters from this function. */
2162 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2163 LLVMValueRef ret = ctx->return_value;
2164 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2165 unsigned vgpr;
2166
2167 /* RW_BUFFERS pointer */
2168 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2169 SI_PARAM_RW_BUFFERS);
2170 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2171 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2172 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2173 bld_base->uint_bld.zero, "");
2174 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2175 bld_base->uint_bld.one, "");
2176 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2177 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2178
2179 /* Tess factor buffer soffset is after user SGPRs. */
2180 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2181 SI_PARAM_TESS_FACTOR_OFFSET);
2182 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2183 SI_TCS_NUM_USER_SGPR, "");
2184
2185 /* VGPRs */
2186 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2187 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2188 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2189
2190 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2191 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2192 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2193 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2194 ctx->return_value = ret;
2195 return;
2196 }
2197
2198 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2199 }
2200
2201 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2202 {
2203 struct si_shader_context *ctx = si_shader_context(bld_base);
2204 struct si_shader *shader = ctx->shader;
2205 struct tgsi_shader_info *info = &shader->selector->info;
2206 struct gallivm_state *gallivm = bld_base->base.gallivm;
2207 unsigned i, chan;
2208 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2209 ctx->param_rel_auto_id);
2210 LLVMValueRef vertex_dw_stride =
2211 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2212 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2213 vertex_dw_stride, "");
2214
2215 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2216 * its inputs from it. */
2217 for (i = 0; i < info->num_outputs; i++) {
2218 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2219 unsigned name = info->output_semantic_name[i];
2220 unsigned index = info->output_semantic_index[i];
2221 int param = si_shader_io_get_unique_index(name, index);
2222 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2223 lp_build_const_int32(gallivm, param * 4), "");
2224
2225 for (chan = 0; chan < 4; chan++) {
2226 lds_store(bld_base, chan, dw_addr,
2227 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2228 }
2229 }
2230 }
2231
2232 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2233 {
2234 struct si_shader_context *ctx = si_shader_context(bld_base);
2235 struct gallivm_state *gallivm = bld_base->base.gallivm;
2236 struct si_shader *es = ctx->shader;
2237 struct tgsi_shader_info *info = &es->selector->info;
2238 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2239 ctx->param_es2gs_offset);
2240 unsigned chan;
2241 int i;
2242
2243 for (i = 0; i < info->num_outputs; i++) {
2244 LLVMValueRef *out_ptr =
2245 ctx->radeon_bld.soa.outputs[i];
2246 int param_index;
2247
2248 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2249 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2250 continue;
2251
2252 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2253 info->output_semantic_index[i]);
2254
2255 for (chan = 0; chan < 4; chan++) {
2256 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2257 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2258
2259 build_tbuffer_store(ctx,
2260 ctx->esgs_ring,
2261 out_val, 1,
2262 LLVMGetUndef(ctx->i32), soffset,
2263 (4 * param_index + chan) * 4,
2264 V_008F0C_BUF_DATA_FORMAT_32,
2265 V_008F0C_BUF_NUM_FORMAT_UINT,
2266 0, 0, 1, 1, 0);
2267 }
2268 }
2269 }
2270
2271 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2272 {
2273 struct si_shader_context *ctx = si_shader_context(bld_base);
2274 struct gallivm_state *gallivm = bld_base->base.gallivm;
2275 LLVMValueRef args[2];
2276
2277 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2278 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2279 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2280 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2281 }
2282
2283 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2284 {
2285 struct si_shader_context *ctx = si_shader_context(bld_base);
2286 struct gallivm_state *gallivm = bld_base->base.gallivm;
2287 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2288 struct si_shader_output_values *outputs = NULL;
2289 int i,j;
2290
2291 assert(!ctx->is_gs_copy_shader);
2292
2293 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2294
2295 /* Vertex color clamping.
2296 *
2297 * This uses a state constant loaded in a user data SGPR and
2298 * an IF statement is added that clamps all colors if the constant
2299 * is true.
2300 */
2301 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2302 struct lp_build_if_state if_ctx;
2303 LLVMValueRef cond = NULL;
2304 LLVMValueRef addr, val;
2305
2306 for (i = 0; i < info->num_outputs; i++) {
2307 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2308 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2309 continue;
2310
2311 /* We've found a color. */
2312 if (!cond) {
2313 /* The state is in the first bit of the user SGPR. */
2314 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2315 SI_PARAM_VS_STATE_BITS);
2316 cond = LLVMBuildTrunc(gallivm->builder, cond,
2317 ctx->i1, "");
2318 lp_build_if(&if_ctx, gallivm, cond);
2319 }
2320
2321 for (j = 0; j < 4; j++) {
2322 addr = ctx->radeon_bld.soa.outputs[i][j];
2323 val = LLVMBuildLoad(gallivm->builder, addr, "");
2324 val = radeon_llvm_saturate(bld_base, val);
2325 LLVMBuildStore(gallivm->builder, val, addr);
2326 }
2327 }
2328
2329 if (cond)
2330 lp_build_endif(&if_ctx);
2331 }
2332
2333 for (i = 0; i < info->num_outputs; i++) {
2334 outputs[i].name = info->output_semantic_name[i];
2335 outputs[i].sid = info->output_semantic_index[i];
2336
2337 for (j = 0; j < 4; j++)
2338 outputs[i].values[j] =
2339 LLVMBuildLoad(gallivm->builder,
2340 ctx->radeon_bld.soa.outputs[i][j],
2341 "");
2342 }
2343
2344 if (ctx->is_monolithic) {
2345 /* Export PrimitiveID when PS needs it. */
2346 if (si_vs_exports_prim_id(ctx->shader)) {
2347 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2348 outputs[i].sid = 0;
2349 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2350 get_primitive_id(bld_base, 0));
2351 outputs[i].values[1] = bld_base->base.undef;
2352 outputs[i].values[2] = bld_base->base.undef;
2353 outputs[i].values[3] = bld_base->base.undef;
2354 i++;
2355 }
2356 } else {
2357 /* Return the primitive ID from the LLVM function. */
2358 ctx->return_value =
2359 LLVMBuildInsertValue(gallivm->builder,
2360 ctx->return_value,
2361 bitcast(bld_base, TGSI_TYPE_FLOAT,
2362 get_primitive_id(bld_base, 0)),
2363 VS_EPILOG_PRIMID_LOC, "");
2364 }
2365
2366 si_llvm_export_vs(bld_base, outputs, i);
2367 FREE(outputs);
2368 }
2369
2370 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2371 LLVMValueRef depth, LLVMValueRef stencil,
2372 LLVMValueRef samplemask)
2373 {
2374 struct si_shader_context *ctx = si_shader_context(bld_base);
2375 struct lp_build_context *base = &bld_base->base;
2376 struct lp_build_context *uint = &bld_base->uint_bld;
2377 LLVMValueRef args[9];
2378 unsigned mask = 0;
2379
2380 assert(depth || stencil || samplemask);
2381
2382 args[1] = uint->one; /* whether the EXEC mask is valid */
2383 args[2] = uint->one; /* DONE bit */
2384
2385 /* Specify the target we are exporting */
2386 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2387
2388 args[4] = uint->zero; /* COMP flag */
2389 args[5] = base->undef; /* R, depth */
2390 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2391 args[7] = base->undef; /* B, sample mask */
2392 args[8] = base->undef; /* A, alpha to mask */
2393
2394 if (depth) {
2395 args[5] = depth;
2396 mask |= 0x1;
2397 }
2398
2399 if (stencil) {
2400 args[6] = stencil;
2401 mask |= 0x2;
2402 }
2403
2404 if (samplemask) {
2405 args[7] = samplemask;
2406 mask |= 0x4;
2407 }
2408
2409 /* SI (except OLAND) has a bug that it only looks
2410 * at the X writemask component. */
2411 if (ctx->screen->b.chip_class == SI &&
2412 ctx->screen->b.family != CHIP_OLAND)
2413 mask |= 0x1;
2414
2415 /* Specify which components to enable */
2416 args[0] = lp_build_const_int32(base->gallivm, mask);
2417
2418 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2419 ctx->voidt, args, 9, 0);
2420 }
2421
2422 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2423 LLVMValueRef *color, unsigned index,
2424 unsigned samplemask_param,
2425 bool is_last)
2426 {
2427 struct si_shader_context *ctx = si_shader_context(bld_base);
2428 struct lp_build_context *base = &bld_base->base;
2429 int i;
2430
2431 /* Clamp color */
2432 if (ctx->shader->key.ps.epilog.clamp_color)
2433 for (i = 0; i < 4; i++)
2434 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2435
2436 /* Alpha to one */
2437 if (ctx->shader->key.ps.epilog.alpha_to_one)
2438 color[3] = base->one;
2439
2440 /* Alpha test */
2441 if (index == 0 &&
2442 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2443 si_alpha_test(bld_base, color[3]);
2444
2445 /* Line & polygon smoothing */
2446 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2447 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2448 samplemask_param);
2449
2450 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2451 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2452 LLVMValueRef args[8][9];
2453 int c, last = -1;
2454
2455 /* Get the export arguments, also find out what the last one is. */
2456 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2457 si_llvm_init_export_args(bld_base, color,
2458 V_008DFC_SQ_EXP_MRT + c, args[c]);
2459 if (args[c][0] != bld_base->uint_bld.zero)
2460 last = c;
2461 }
2462
2463 /* Emit all exports. */
2464 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2465 if (is_last && last == c) {
2466 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2467 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2468 } else if (args[c][0] == bld_base->uint_bld.zero)
2469 continue; /* unnecessary NULL export */
2470
2471 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2472 ctx->voidt, args[c], 9, 0);
2473 }
2474 } else {
2475 LLVMValueRef args[9];
2476
2477 /* Export */
2478 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2479 args);
2480 if (is_last) {
2481 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2482 args[2] = bld_base->uint_bld.one; /* DONE bit */
2483 } else if (args[0] == bld_base->uint_bld.zero)
2484 return; /* unnecessary NULL export */
2485
2486 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2487 ctx->voidt, args, 9, 0);
2488 }
2489 }
2490
2491 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2492 {
2493 struct si_shader_context *ctx = si_shader_context(bld_base);
2494 struct lp_build_context *base = &bld_base->base;
2495 struct lp_build_context *uint = &bld_base->uint_bld;
2496 LLVMValueRef args[9];
2497
2498 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2499 args[1] = uint->one; /* whether the EXEC mask is valid */
2500 args[2] = uint->one; /* DONE bit */
2501 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2502 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2503 args[5] = uint->undef; /* R */
2504 args[6] = uint->undef; /* G */
2505 args[7] = uint->undef; /* B */
2506 args[8] = uint->undef; /* A */
2507
2508 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2509 ctx->voidt, args, 9, 0);
2510 }
2511
2512 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2513 {
2514 struct si_shader_context *ctx = si_shader_context(bld_base);
2515 struct si_shader *shader = ctx->shader;
2516 struct lp_build_context *base = &bld_base->base;
2517 struct tgsi_shader_info *info = &shader->selector->info;
2518 LLVMBuilderRef builder = base->gallivm->builder;
2519 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2520 int last_color_export = -1;
2521 int i;
2522
2523 /* Determine the last export. If MRTZ is present, it's always last.
2524 * Otherwise, find the last color export.
2525 */
2526 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2527 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2528
2529 /* Don't export NULL and return if alpha-test is enabled. */
2530 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2531 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2532 (spi_format & 0xf) == 0)
2533 spi_format |= V_028714_SPI_SHADER_32_AR;
2534
2535 for (i = 0; i < info->num_outputs; i++) {
2536 unsigned index = info->output_semantic_index[i];
2537
2538 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2539 continue;
2540
2541 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2542 if (shader->key.ps.epilog.last_cbuf > 0) {
2543 /* Just set this if any of the colorbuffers are enabled. */
2544 if (spi_format &
2545 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2546 last_color_export = i;
2547 continue;
2548 }
2549
2550 if ((spi_format >> (index * 4)) & 0xf)
2551 last_color_export = i;
2552 }
2553
2554 /* If there are no outputs, export NULL. */
2555 if (last_color_export == -1) {
2556 si_export_null(bld_base);
2557 return;
2558 }
2559 }
2560
2561 for (i = 0; i < info->num_outputs; i++) {
2562 unsigned semantic_name = info->output_semantic_name[i];
2563 unsigned semantic_index = info->output_semantic_index[i];
2564 unsigned j;
2565 LLVMValueRef color[4] = {};
2566
2567 /* Select the correct target */
2568 switch (semantic_name) {
2569 case TGSI_SEMANTIC_POSITION:
2570 depth = LLVMBuildLoad(builder,
2571 ctx->radeon_bld.soa.outputs[i][2], "");
2572 break;
2573 case TGSI_SEMANTIC_STENCIL:
2574 stencil = LLVMBuildLoad(builder,
2575 ctx->radeon_bld.soa.outputs[i][1], "");
2576 break;
2577 case TGSI_SEMANTIC_SAMPLEMASK:
2578 samplemask = LLVMBuildLoad(builder,
2579 ctx->radeon_bld.soa.outputs[i][0], "");
2580 break;
2581 case TGSI_SEMANTIC_COLOR:
2582 for (j = 0; j < 4; j++)
2583 color[j] = LLVMBuildLoad(builder,
2584 ctx->radeon_bld.soa.outputs[i][j], "");
2585
2586 si_export_mrt_color(bld_base, color, semantic_index,
2587 SI_PARAM_SAMPLE_COVERAGE,
2588 last_color_export == i);
2589 break;
2590 default:
2591 fprintf(stderr,
2592 "Warning: SI unhandled fs output type:%d\n",
2593 semantic_name);
2594 }
2595 }
2596
2597 if (depth || stencil || samplemask)
2598 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2599 }
2600
2601 /**
2602 * Return PS outputs in this order:
2603 *
2604 * v[0:3] = color0.xyzw
2605 * v[4:7] = color1.xyzw
2606 * ...
2607 * vN+0 = Depth
2608 * vN+1 = Stencil
2609 * vN+2 = SampleMask
2610 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2611 *
2612 * The alpha-ref SGPR is returned via its original location.
2613 */
2614 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2615 {
2616 struct si_shader_context *ctx = si_shader_context(bld_base);
2617 struct si_shader *shader = ctx->shader;
2618 struct lp_build_context *base = &bld_base->base;
2619 struct tgsi_shader_info *info = &shader->selector->info;
2620 LLVMBuilderRef builder = base->gallivm->builder;
2621 unsigned i, j, first_vgpr, vgpr;
2622
2623 LLVMValueRef color[8][4] = {};
2624 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2625 LLVMValueRef ret;
2626
2627 /* Read the output values. */
2628 for (i = 0; i < info->num_outputs; i++) {
2629 unsigned semantic_name = info->output_semantic_name[i];
2630 unsigned semantic_index = info->output_semantic_index[i];
2631
2632 switch (semantic_name) {
2633 case TGSI_SEMANTIC_COLOR:
2634 assert(semantic_index < 8);
2635 for (j = 0; j < 4; j++) {
2636 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2637 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2638 color[semantic_index][j] = result;
2639 }
2640 break;
2641 case TGSI_SEMANTIC_POSITION:
2642 depth = LLVMBuildLoad(builder,
2643 ctx->radeon_bld.soa.outputs[i][2], "");
2644 break;
2645 case TGSI_SEMANTIC_STENCIL:
2646 stencil = LLVMBuildLoad(builder,
2647 ctx->radeon_bld.soa.outputs[i][1], "");
2648 break;
2649 case TGSI_SEMANTIC_SAMPLEMASK:
2650 samplemask = LLVMBuildLoad(builder,
2651 ctx->radeon_bld.soa.outputs[i][0], "");
2652 break;
2653 default:
2654 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2655 semantic_name);
2656 }
2657 }
2658
2659 /* Fill the return structure. */
2660 ret = ctx->return_value;
2661
2662 /* Set SGPRs. */
2663 ret = LLVMBuildInsertValue(builder, ret,
2664 bitcast(bld_base, TGSI_TYPE_SIGNED,
2665 LLVMGetParam(ctx->radeon_bld.main_fn,
2666 SI_PARAM_ALPHA_REF)),
2667 SI_SGPR_ALPHA_REF, "");
2668
2669 /* Set VGPRs */
2670 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2671 for (i = 0; i < ARRAY_SIZE(color); i++) {
2672 if (!color[i][0])
2673 continue;
2674
2675 for (j = 0; j < 4; j++)
2676 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2677 }
2678 if (depth)
2679 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2680 if (stencil)
2681 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2682 if (samplemask)
2683 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2684
2685 /* Add the input sample mask for smoothing at the end. */
2686 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2687 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2688 ret = LLVMBuildInsertValue(builder, ret,
2689 LLVMGetParam(ctx->radeon_bld.main_fn,
2690 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2691
2692 ctx->return_value = ret;
2693 }
2694
2695 /**
2696 * Given a v8i32 resource descriptor for a buffer, extract the size of the
2697 * buffer in number of elements and return it as an i32.
2698 */
2699 static LLVMValueRef get_buffer_size(
2700 struct lp_build_tgsi_context *bld_base,
2701 LLVMValueRef descriptor)
2702 {
2703 struct si_shader_context *ctx = si_shader_context(bld_base);
2704 struct gallivm_state *gallivm = bld_base->base.gallivm;
2705 LLVMBuilderRef builder = gallivm->builder;
2706 LLVMValueRef size =
2707 LLVMBuildExtractElement(builder, descriptor,
2708 lp_build_const_int32(gallivm, 6), "");
2709
2710 if (ctx->screen->b.chip_class >= VI) {
2711 /* On VI, the descriptor contains the size in bytes,
2712 * but TXQ must return the size in elements.
2713 * The stride is always non-zero for resources using TXQ.
2714 */
2715 LLVMValueRef stride =
2716 LLVMBuildExtractElement(builder, descriptor,
2717 lp_build_const_int32(gallivm, 5), "");
2718 stride = LLVMBuildLShr(builder, stride,
2719 lp_build_const_int32(gallivm, 16), "");
2720 stride = LLVMBuildAnd(builder, stride,
2721 lp_build_const_int32(gallivm, 0x3FFF), "");
2722
2723 size = LLVMBuildUDiv(builder, size, stride, "");
2724 }
2725
2726 return size;
2727 }
2728
2729 /**
2730 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2731 * intrinsic names).
2732 */
2733 static void build_int_type_name(
2734 LLVMTypeRef type,
2735 char *buf, unsigned bufsize)
2736 {
2737 assert(bufsize >= 6);
2738
2739 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2740 snprintf(buf, bufsize, "v%ui32",
2741 LLVMGetVectorSize(type));
2742 else
2743 strcpy(buf, "i32");
2744 }
2745
2746 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2747 struct lp_build_tgsi_context *bld_base,
2748 struct lp_build_emit_data *emit_data);
2749
2750 /* Prevent optimizations (at least of memory accesses) across the current
2751 * point in the program by emitting empty inline assembly that is marked as
2752 * having side effects.
2753 */
2754 static void emit_optimization_barrier(struct si_shader_context *ctx)
2755 {
2756 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2757 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
2758 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
2759 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
2760 }
2761
2762 static void membar_emit(
2763 const struct lp_build_tgsi_action *action,
2764 struct lp_build_tgsi_context *bld_base,
2765 struct lp_build_emit_data *emit_data)
2766 {
2767 struct si_shader_context *ctx = si_shader_context(bld_base);
2768
2769 /* Since memoryBarrier only makes guarantees about atomics and
2770 * coherent image accesses (which bypass TC L1), we do not need to emit
2771 * any special cache handling here.
2772 *
2773 * We do have to prevent LLVM from re-ordering loads across
2774 * the barrier though.
2775 */
2776 emit_optimization_barrier(ctx);
2777 }
2778
2779 static LLVMValueRef
2780 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
2781 const struct tgsi_full_src_register *reg)
2782 {
2783 LLVMValueRef ind_index;
2784 LLVMValueRef rsrc_ptr;
2785
2786 if (!reg->Register.Indirect)
2787 return ctx->shader_buffers[reg->Register.Index];
2788
2789 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
2790 reg->Register.Index,
2791 SI_NUM_SHADER_BUFFERS);
2792
2793 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
2794 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2795 }
2796
2797 static bool tgsi_is_array_sampler(unsigned target)
2798 {
2799 return target == TGSI_TEXTURE_1D_ARRAY ||
2800 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2801 target == TGSI_TEXTURE_2D_ARRAY ||
2802 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2803 target == TGSI_TEXTURE_CUBE_ARRAY ||
2804 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2805 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2806 }
2807
2808 static bool tgsi_is_array_image(unsigned target)
2809 {
2810 return target == TGSI_TEXTURE_3D ||
2811 target == TGSI_TEXTURE_CUBE ||
2812 target == TGSI_TEXTURE_1D_ARRAY ||
2813 target == TGSI_TEXTURE_2D_ARRAY ||
2814 target == TGSI_TEXTURE_CUBE_ARRAY ||
2815 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2816 }
2817
2818 /**
2819 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
2820 *
2821 * At least on Tonga, executing image stores on images with DCC enabled and
2822 * non-trivial can eventually lead to lockups. This can occur when an
2823 * application binds an image as read-only but then uses a shader that writes
2824 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
2825 * program termination) in this case, but it doesn't cost much to be a bit
2826 * nicer: disabling DCC in the shader still leads to undefined results but
2827 * avoids the lockup.
2828 */
2829 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
2830 LLVMValueRef rsrc)
2831 {
2832 if (ctx->screen->b.chip_class <= CIK) {
2833 return rsrc;
2834 } else {
2835 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2836 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
2837 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
2838 LLVMValueRef tmp;
2839
2840 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
2841 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
2842 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
2843 }
2844 }
2845
2846 /**
2847 * Load the resource descriptor for \p image.
2848 */
2849 static void
2850 image_fetch_rsrc(
2851 struct lp_build_tgsi_context *bld_base,
2852 const struct tgsi_full_src_register *image,
2853 bool dcc_off,
2854 LLVMValueRef *rsrc)
2855 {
2856 struct si_shader_context *ctx = si_shader_context(bld_base);
2857
2858 assert(image->Register.File == TGSI_FILE_IMAGE);
2859
2860 if (!image->Register.Indirect) {
2861 /* Fast path: use preloaded resources */
2862 *rsrc = ctx->images[image->Register.Index];
2863 } else {
2864 /* Indexing and manual load */
2865 LLVMValueRef ind_index;
2866 LLVMValueRef rsrc_ptr;
2867 LLVMValueRef tmp;
2868
2869 /* From the GL_ARB_shader_image_load_store extension spec:
2870 *
2871 * If a shader performs an image load, store, or atomic
2872 * operation using an image variable declared as an array,
2873 * and if the index used to select an individual element is
2874 * negative or greater than or equal to the size of the
2875 * array, the results of the operation are undefined but may
2876 * not lead to termination.
2877 */
2878 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
2879 image->Register.Index,
2880 SI_NUM_IMAGES);
2881
2882 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
2883 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2884 if (dcc_off)
2885 tmp = force_dcc_off(ctx, tmp);
2886 *rsrc = tmp;
2887 }
2888 }
2889
2890 static LLVMValueRef image_fetch_coords(
2891 struct lp_build_tgsi_context *bld_base,
2892 const struct tgsi_full_instruction *inst,
2893 unsigned src)
2894 {
2895 struct gallivm_state *gallivm = bld_base->base.gallivm;
2896 LLVMBuilderRef builder = gallivm->builder;
2897 unsigned target = inst->Memory.Texture;
2898 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
2899 LLVMValueRef coords[4];
2900 LLVMValueRef tmp;
2901 int chan;
2902
2903 for (chan = 0; chan < num_coords; ++chan) {
2904 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
2905 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
2906 coords[chan] = tmp;
2907 }
2908
2909 if (num_coords == 1)
2910 return coords[0];
2911
2912 if (num_coords == 3) {
2913 /* LLVM has difficulties lowering 3-element vectors. */
2914 coords[3] = bld_base->uint_bld.undef;
2915 num_coords = 4;
2916 }
2917
2918 return lp_build_gather_values(gallivm, coords, num_coords);
2919 }
2920
2921 /**
2922 * Append the extra mode bits that are used by image load and store.
2923 */
2924 static void image_append_args(
2925 struct si_shader_context *ctx,
2926 struct lp_build_emit_data * emit_data,
2927 unsigned target,
2928 bool atomic)
2929 {
2930 const struct tgsi_full_instruction *inst = emit_data->inst;
2931 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2932 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2933
2934 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
2935 emit_data->args[emit_data->arg_count++] =
2936 tgsi_is_array_image(target) ? i1true : i1false; /* da */
2937 if (!atomic) {
2938 emit_data->args[emit_data->arg_count++] =
2939 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
2940 i1true : i1false; /* glc */
2941 }
2942 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2943 }
2944
2945 /**
2946 * Given a 256 bit resource, extract the top half (which stores the buffer
2947 * resource in the case of textures and images).
2948 */
2949 static LLVMValueRef extract_rsrc_top_half(
2950 struct si_shader_context *ctx,
2951 LLVMValueRef rsrc)
2952 {
2953 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2954 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
2955 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
2956
2957 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
2958 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
2959 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
2960
2961 return rsrc;
2962 }
2963
2964 /**
2965 * Append the resource and indexing arguments for buffer intrinsics.
2966 *
2967 * \param rsrc the v4i32 buffer resource
2968 * \param index index into the buffer (stride-based)
2969 * \param offset byte offset into the buffer
2970 */
2971 static void buffer_append_args(
2972 struct si_shader_context *ctx,
2973 struct lp_build_emit_data *emit_data,
2974 LLVMValueRef rsrc,
2975 LLVMValueRef index,
2976 LLVMValueRef offset,
2977 bool atomic)
2978 {
2979 const struct tgsi_full_instruction *inst = emit_data->inst;
2980 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2981 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2982
2983 emit_data->args[emit_data->arg_count++] = rsrc;
2984 emit_data->args[emit_data->arg_count++] = index; /* vindex */
2985 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
2986 if (!atomic) {
2987 emit_data->args[emit_data->arg_count++] =
2988 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
2989 i1true : i1false; /* glc */
2990 }
2991 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2992 }
2993
2994 static void load_fetch_args(
2995 struct lp_build_tgsi_context * bld_base,
2996 struct lp_build_emit_data * emit_data)
2997 {
2998 struct si_shader_context *ctx = si_shader_context(bld_base);
2999 struct gallivm_state *gallivm = bld_base->base.gallivm;
3000 const struct tgsi_full_instruction * inst = emit_data->inst;
3001 unsigned target = inst->Memory.Texture;
3002 LLVMValueRef rsrc;
3003
3004 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3005
3006 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3007 LLVMBuilderRef builder = gallivm->builder;
3008 LLVMValueRef offset;
3009 LLVMValueRef tmp;
3010
3011 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3012
3013 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3014 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3015
3016 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3017 offset, false);
3018 } else {
3019 LLVMValueRef coords;
3020
3021 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3022 coords = image_fetch_coords(bld_base, inst, 1);
3023
3024 if (target == TGSI_TEXTURE_BUFFER) {
3025 rsrc = extract_rsrc_top_half(ctx, rsrc);
3026 buffer_append_args(ctx, emit_data, rsrc, coords,
3027 bld_base->uint_bld.zero, false);
3028 } else {
3029 emit_data->args[0] = coords;
3030 emit_data->args[1] = rsrc;
3031 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3032 emit_data->arg_count = 3;
3033
3034 image_append_args(ctx, emit_data, target, false);
3035 }
3036 }
3037 }
3038
3039 static void load_emit_buffer(struct si_shader_context *ctx,
3040 struct lp_build_emit_data *emit_data)
3041 {
3042 const struct tgsi_full_instruction *inst = emit_data->inst;
3043 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3044 LLVMBuilderRef builder = gallivm->builder;
3045 uint writemask = inst->Dst[0].Register.WriteMask;
3046 uint count = util_last_bit(writemask);
3047 const char *intrinsic_name;
3048 LLVMTypeRef dst_type;
3049
3050 switch (count) {
3051 case 1:
3052 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3053 dst_type = ctx->f32;
3054 break;
3055 case 2:
3056 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3057 dst_type = LLVMVectorType(ctx->f32, 2);
3058 break;
3059 default: // 3 & 4
3060 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3061 dst_type = ctx->v4f32;
3062 count = 4;
3063 }
3064
3065 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3066 builder, intrinsic_name, dst_type,
3067 emit_data->args, emit_data->arg_count,
3068 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3069 }
3070
3071 static void load_emit(
3072 const struct lp_build_tgsi_action *action,
3073 struct lp_build_tgsi_context *bld_base,
3074 struct lp_build_emit_data *emit_data)
3075 {
3076 struct si_shader_context *ctx = si_shader_context(bld_base);
3077 struct gallivm_state *gallivm = bld_base->base.gallivm;
3078 LLVMBuilderRef builder = gallivm->builder;
3079 const struct tgsi_full_instruction * inst = emit_data->inst;
3080 char intrinsic_name[32];
3081 char coords_type[8];
3082
3083 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3084 emit_optimization_barrier(ctx);
3085
3086 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3087 load_emit_buffer(ctx, emit_data);
3088 return;
3089 }
3090
3091 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3092 emit_data->output[emit_data->chan] =
3093 lp_build_intrinsic(
3094 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3095 emit_data->args, emit_data->arg_count,
3096 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3097 } else {
3098 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3099 coords_type, sizeof(coords_type));
3100
3101 snprintf(intrinsic_name, sizeof(intrinsic_name),
3102 "llvm.amdgcn.image.load.%s", coords_type);
3103
3104 emit_data->output[emit_data->chan] =
3105 lp_build_intrinsic(
3106 builder, intrinsic_name, emit_data->dst_type,
3107 emit_data->args, emit_data->arg_count,
3108 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3109 }
3110 }
3111
3112 static void store_fetch_args(
3113 struct lp_build_tgsi_context * bld_base,
3114 struct lp_build_emit_data * emit_data)
3115 {
3116 struct si_shader_context *ctx = si_shader_context(bld_base);
3117 struct gallivm_state *gallivm = bld_base->base.gallivm;
3118 LLVMBuilderRef builder = gallivm->builder;
3119 const struct tgsi_full_instruction * inst = emit_data->inst;
3120 struct tgsi_full_src_register memory;
3121 LLVMValueRef chans[4];
3122 LLVMValueRef data;
3123 LLVMValueRef rsrc;
3124 unsigned chan;
3125
3126 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3127
3128 for (chan = 0; chan < 4; ++chan) {
3129 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3130 }
3131 data = lp_build_gather_values(gallivm, chans, 4);
3132
3133 emit_data->args[emit_data->arg_count++] = data;
3134
3135 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3136
3137 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3138 LLVMValueRef offset;
3139 LLVMValueRef tmp;
3140
3141 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3142
3143 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3144 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3145
3146 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3147 offset, false);
3148 } else {
3149 unsigned target = inst->Memory.Texture;
3150 LLVMValueRef coords;
3151
3152 coords = image_fetch_coords(bld_base, inst, 0);
3153
3154 if (target == TGSI_TEXTURE_BUFFER) {
3155 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3156
3157 rsrc = extract_rsrc_top_half(ctx, rsrc);
3158 buffer_append_args(ctx, emit_data, rsrc, coords,
3159 bld_base->uint_bld.zero, false);
3160 } else {
3161 emit_data->args[1] = coords;
3162 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3163 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3164 emit_data->arg_count = 4;
3165
3166 image_append_args(ctx, emit_data, target, false);
3167 }
3168 }
3169 }
3170
3171 static void store_emit_buffer(
3172 struct si_shader_context *ctx,
3173 struct lp_build_emit_data *emit_data)
3174 {
3175 const struct tgsi_full_instruction *inst = emit_data->inst;
3176 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3177 LLVMBuilderRef builder = gallivm->builder;
3178 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3179 LLVMValueRef base_data = emit_data->args[0];
3180 LLVMValueRef base_offset = emit_data->args[3];
3181 unsigned writemask = inst->Dst[0].Register.WriteMask;
3182
3183 while (writemask) {
3184 int start, count;
3185 const char *intrinsic_name;
3186 LLVMValueRef data;
3187 LLVMValueRef offset;
3188 LLVMValueRef tmp;
3189
3190 u_bit_scan_consecutive_range(&writemask, &start, &count);
3191
3192 /* Due to an LLVM limitation, split 3-element writes
3193 * into a 2-element and a 1-element write. */
3194 if (count == 3) {
3195 writemask |= 1 << (start + 2);
3196 count = 2;
3197 }
3198
3199 if (count == 4) {
3200 data = base_data;
3201 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3202 } else if (count == 2) {
3203 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3204
3205 tmp = LLVMBuildExtractElement(
3206 builder, base_data,
3207 lp_build_const_int32(gallivm, start), "");
3208 data = LLVMBuildInsertElement(
3209 builder, LLVMGetUndef(v2f32), tmp,
3210 uint_bld->zero, "");
3211
3212 tmp = LLVMBuildExtractElement(
3213 builder, base_data,
3214 lp_build_const_int32(gallivm, start + 1), "");
3215 data = LLVMBuildInsertElement(
3216 builder, data, tmp, uint_bld->one, "");
3217
3218 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3219 } else {
3220 assert(count == 1);
3221 data = LLVMBuildExtractElement(
3222 builder, base_data,
3223 lp_build_const_int32(gallivm, start), "");
3224 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3225 }
3226
3227 offset = base_offset;
3228 if (start != 0) {
3229 offset = LLVMBuildAdd(
3230 builder, offset,
3231 lp_build_const_int32(gallivm, start * 4), "");
3232 }
3233
3234 emit_data->args[0] = data;
3235 emit_data->args[3] = offset;
3236
3237 lp_build_intrinsic(
3238 builder, intrinsic_name, emit_data->dst_type,
3239 emit_data->args, emit_data->arg_count,
3240 LLVMNoUnwindAttribute);
3241 }
3242 }
3243
3244 static void store_emit(
3245 const struct lp_build_tgsi_action *action,
3246 struct lp_build_tgsi_context *bld_base,
3247 struct lp_build_emit_data *emit_data)
3248 {
3249 struct gallivm_state *gallivm = bld_base->base.gallivm;
3250 LLVMBuilderRef builder = gallivm->builder;
3251 const struct tgsi_full_instruction * inst = emit_data->inst;
3252 unsigned target = inst->Memory.Texture;
3253 char intrinsic_name[32];
3254 char coords_type[8];
3255
3256 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3257 store_emit_buffer(si_shader_context(bld_base), emit_data);
3258 return;
3259 }
3260
3261 if (target == TGSI_TEXTURE_BUFFER) {
3262 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3263 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3264 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3265 LLVMNoUnwindAttribute);
3266 } else {
3267 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3268 coords_type, sizeof(coords_type));
3269 snprintf(intrinsic_name, sizeof(intrinsic_name),
3270 "llvm.amdgcn.image.store.%s", coords_type);
3271
3272 emit_data->output[emit_data->chan] =
3273 lp_build_intrinsic(
3274 builder, intrinsic_name, emit_data->dst_type,
3275 emit_data->args, emit_data->arg_count,
3276 LLVMNoUnwindAttribute);
3277 }
3278 }
3279
3280 static void atomic_fetch_args(
3281 struct lp_build_tgsi_context * bld_base,
3282 struct lp_build_emit_data * emit_data)
3283 {
3284 struct si_shader_context *ctx = si_shader_context(bld_base);
3285 struct gallivm_state *gallivm = bld_base->base.gallivm;
3286 LLVMBuilderRef builder = gallivm->builder;
3287 const struct tgsi_full_instruction * inst = emit_data->inst;
3288 LLVMValueRef data1, data2;
3289 LLVMValueRef rsrc;
3290 LLVMValueRef tmp;
3291
3292 emit_data->dst_type = bld_base->base.elem_type;
3293
3294 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3295 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3296
3297 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3298 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3299 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3300 }
3301
3302 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3303 * of arguments, which is reversed relative to TGSI (and GLSL)
3304 */
3305 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3306 emit_data->args[emit_data->arg_count++] = data2;
3307 emit_data->args[emit_data->arg_count++] = data1;
3308
3309 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3310 LLVMValueRef offset;
3311
3312 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3313
3314 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3315 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3316
3317 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3318 offset, true);
3319 } else {
3320 unsigned target = inst->Memory.Texture;
3321 LLVMValueRef coords;
3322
3323 image_fetch_rsrc(bld_base, &inst->Src[0],
3324 target != TGSI_TEXTURE_BUFFER, &rsrc);
3325 coords = image_fetch_coords(bld_base, inst, 1);
3326
3327 if (target == TGSI_TEXTURE_BUFFER) {
3328 rsrc = extract_rsrc_top_half(ctx, rsrc);
3329 buffer_append_args(ctx, emit_data, rsrc, coords,
3330 bld_base->uint_bld.zero, true);
3331 } else {
3332 emit_data->args[emit_data->arg_count++] = coords;
3333 emit_data->args[emit_data->arg_count++] = rsrc;
3334
3335 image_append_args(ctx, emit_data, target, true);
3336 }
3337 }
3338 }
3339
3340 static void atomic_emit(
3341 const struct lp_build_tgsi_action *action,
3342 struct lp_build_tgsi_context *bld_base,
3343 struct lp_build_emit_data *emit_data)
3344 {
3345 struct gallivm_state *gallivm = bld_base->base.gallivm;
3346 LLVMBuilderRef builder = gallivm->builder;
3347 const struct tgsi_full_instruction * inst = emit_data->inst;
3348 char intrinsic_name[40];
3349 LLVMValueRef tmp;
3350
3351 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3352 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3353 snprintf(intrinsic_name, sizeof(intrinsic_name),
3354 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3355 } else {
3356 char coords_type[8];
3357
3358 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3359 coords_type, sizeof(coords_type));
3360 snprintf(intrinsic_name, sizeof(intrinsic_name),
3361 "llvm.amdgcn.image.atomic.%s.%s",
3362 action->intr_name, coords_type);
3363 }
3364
3365 tmp = lp_build_intrinsic(
3366 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3367 emit_data->args, emit_data->arg_count,
3368 LLVMNoUnwindAttribute);
3369 emit_data->output[emit_data->chan] =
3370 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3371 }
3372
3373 static void resq_fetch_args(
3374 struct lp_build_tgsi_context * bld_base,
3375 struct lp_build_emit_data * emit_data)
3376 {
3377 struct si_shader_context *ctx = si_shader_context(bld_base);
3378 struct gallivm_state *gallivm = bld_base->base.gallivm;
3379 const struct tgsi_full_instruction *inst = emit_data->inst;
3380 const struct tgsi_full_src_register *reg = &inst->Src[0];
3381
3382 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3383
3384 if (reg->Register.File == TGSI_FILE_BUFFER) {
3385 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
3386 emit_data->arg_count = 1;
3387 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3388 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
3389 emit_data->arg_count = 1;
3390 } else {
3391 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3392 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
3393 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3394 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3395 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3396 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
3397 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3398 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3399 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3400 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3401 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3402 emit_data->arg_count = 10;
3403 }
3404 }
3405
3406 static void resq_emit(
3407 const struct lp_build_tgsi_action *action,
3408 struct lp_build_tgsi_context *bld_base,
3409 struct lp_build_emit_data *emit_data)
3410 {
3411 struct gallivm_state *gallivm = bld_base->base.gallivm;
3412 LLVMBuilderRef builder = gallivm->builder;
3413 const struct tgsi_full_instruction *inst = emit_data->inst;
3414 LLVMValueRef out;
3415
3416 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3417 out = LLVMBuildExtractElement(builder, emit_data->args[0],
3418 lp_build_const_int32(gallivm, 2), "");
3419 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3420 out = get_buffer_size(bld_base, emit_data->args[0]);
3421 } else {
3422 out = lp_build_intrinsic(
3423 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
3424 emit_data->args, emit_data->arg_count,
3425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3426
3427 /* Divide the number of layers by 6 to get the number of cubes. */
3428 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
3429 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
3430 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
3431
3432 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
3433 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
3434 z = LLVMBuildSDiv(builder, z, imm6, "");
3435 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
3436 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
3437 }
3438 }
3439
3440 emit_data->output[emit_data->chan] = out;
3441 }
3442
3443 static void set_tex_fetch_args(struct si_shader_context *ctx,
3444 struct lp_build_emit_data *emit_data,
3445 unsigned opcode, unsigned target,
3446 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3447 LLVMValueRef *param, unsigned count,
3448 unsigned dmask)
3449 {
3450 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3451 unsigned num_args;
3452 unsigned is_rect = target == TGSI_TEXTURE_RECT;
3453
3454 /* Pad to power of two vector */
3455 while (count < util_next_power_of_two(count))
3456 param[count++] = LLVMGetUndef(ctx->i32);
3457
3458 /* Texture coordinates. */
3459 if (count > 1)
3460 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
3461 else
3462 emit_data->args[0] = param[0];
3463
3464 /* Resource. */
3465 emit_data->args[1] = res_ptr;
3466 num_args = 2;
3467
3468 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
3469 emit_data->dst_type = ctx->v4i32;
3470 else {
3471 emit_data->dst_type = ctx->v4f32;
3472
3473 emit_data->args[num_args++] = samp_ptr;
3474 }
3475
3476 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
3477 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
3478 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
3479 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
3480 tgsi_is_array_sampler(target)); /* da */
3481 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
3482 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
3483 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
3484 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
3485
3486 emit_data->arg_count = num_args;
3487 }
3488
3489 static const struct lp_build_tgsi_action tex_action;
3490
3491 enum desc_type {
3492 DESC_IMAGE,
3493 DESC_FMASK,
3494 DESC_SAMPLER
3495 };
3496
3497 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3498 {
3499 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3500 CONST_ADDR_SPACE);
3501 }
3502
3503 /**
3504 * Load an image view, fmask view. or sampler state descriptor.
3505 */
3506 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
3507 LLVMValueRef list, LLVMValueRef index,
3508 enum desc_type type)
3509 {
3510 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3511 LLVMBuilderRef builder = gallivm->builder;
3512
3513 switch (type) {
3514 case DESC_IMAGE:
3515 /* The image is at [0:7]. */
3516 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3517 break;
3518 case DESC_FMASK:
3519 /* The FMASK is at [8:15]. */
3520 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3521 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
3522 break;
3523 case DESC_SAMPLER:
3524 /* The sampler state is at [12:15]. */
3525 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
3526 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
3527 list = LLVMBuildPointerCast(builder, list,
3528 const_array(ctx->v4i32, 0), "");
3529 break;
3530 }
3531
3532 return build_indexed_load_const(ctx, list, index);
3533 }
3534
3535 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
3536 LLVMValueRef index, enum desc_type type)
3537 {
3538 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
3539 SI_PARAM_SAMPLERS);
3540
3541 return get_sampler_desc_custom(ctx, list, index, type);
3542 }
3543
3544 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3545 *
3546 * SI-CI:
3547 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3548 * filtering manually. The driver sets img7 to a mask clearing
3549 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3550 * s_and_b32 samp0, samp0, img7
3551 *
3552 * VI:
3553 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3554 */
3555 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
3556 LLVMValueRef res, LLVMValueRef samp)
3557 {
3558 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3559 LLVMValueRef img7, samp0;
3560
3561 if (ctx->screen->b.chip_class >= VI)
3562 return samp;
3563
3564 img7 = LLVMBuildExtractElement(builder, res,
3565 LLVMConstInt(ctx->i32, 7, 0), "");
3566 samp0 = LLVMBuildExtractElement(builder, samp,
3567 LLVMConstInt(ctx->i32, 0, 0), "");
3568 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3569 return LLVMBuildInsertElement(builder, samp, samp0,
3570 LLVMConstInt(ctx->i32, 0, 0), "");
3571 }
3572
3573 static void tex_fetch_ptrs(
3574 struct lp_build_tgsi_context *bld_base,
3575 struct lp_build_emit_data *emit_data,
3576 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
3577 {
3578 struct si_shader_context *ctx = si_shader_context(bld_base);
3579 const struct tgsi_full_instruction *inst = emit_data->inst;
3580 unsigned target = inst->Texture.Texture;
3581 unsigned sampler_src;
3582 unsigned sampler_index;
3583
3584 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
3585 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
3586
3587 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
3588 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
3589 LLVMValueRef ind_index;
3590
3591 ind_index = get_bounded_indirect_index(ctx,
3592 &reg->Indirect,
3593 reg->Register.Index,
3594 SI_NUM_USER_SAMPLERS);
3595
3596 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
3597
3598 if (target == TGSI_TEXTURE_2D_MSAA ||
3599 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3600 *samp_ptr = NULL;
3601 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
3602 } else {
3603 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
3604 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3605 *fmask_ptr = NULL;
3606 }
3607 } else {
3608 *res_ptr = ctx->sampler_views[sampler_index];
3609 *samp_ptr = ctx->sampler_states[sampler_index];
3610 *fmask_ptr = ctx->fmasks[sampler_index];
3611 }
3612 }
3613
3614 static void tex_fetch_args(
3615 struct lp_build_tgsi_context *bld_base,
3616 struct lp_build_emit_data *emit_data)
3617 {
3618 struct si_shader_context *ctx = si_shader_context(bld_base);
3619 struct gallivm_state *gallivm = bld_base->base.gallivm;
3620 LLVMBuilderRef builder = gallivm->builder;
3621 const struct tgsi_full_instruction *inst = emit_data->inst;
3622 unsigned opcode = inst->Instruction.Opcode;
3623 unsigned target = inst->Texture.Texture;
3624 LLVMValueRef coords[5], derivs[6];
3625 LLVMValueRef address[16];
3626 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3627 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
3628 unsigned count = 0;
3629 unsigned chan;
3630 unsigned num_deriv_channels = 0;
3631 bool has_offset = inst->Texture.NumOffsets > 0;
3632 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3633 unsigned dmask = 0xf;
3634
3635 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3636
3637 if (opcode == TGSI_OPCODE_TXQ) {
3638 if (target == TGSI_TEXTURE_BUFFER) {
3639 /* Read the size from the buffer descriptor directly. */
3640 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3641 emit_data->args[0] = get_buffer_size(bld_base, res);
3642 return;
3643 }
3644
3645 /* Textures - set the mip level. */
3646 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
3647
3648 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3649 NULL, address, count, 0xf);
3650 return;
3651 }
3652
3653 if (target == TGSI_TEXTURE_BUFFER) {
3654 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3655
3656 /* Bitcast and truncate v8i32 to v16i8. */
3657 LLVMValueRef res = res_ptr;
3658 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
3659 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
3660 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
3661
3662 emit_data->dst_type = ctx->v4f32;
3663 emit_data->args[0] = res;
3664 emit_data->args[1] = bld_base->uint_bld.zero;
3665 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3666 emit_data->arg_count = 3;
3667 return;
3668 }
3669
3670 /* Fetch and project texture coordinates */
3671 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
3672 for (chan = 0; chan < 3; chan++ ) {
3673 coords[chan] = lp_build_emit_fetch(bld_base,
3674 emit_data->inst, 0,
3675 chan);
3676 if (opcode == TGSI_OPCODE_TXP)
3677 coords[chan] = lp_build_emit_llvm_binary(bld_base,
3678 TGSI_OPCODE_DIV,
3679 coords[chan],
3680 coords[3]);
3681 }
3682
3683 if (opcode == TGSI_OPCODE_TXP)
3684 coords[3] = bld_base->base.one;
3685
3686 /* Pack offsets. */
3687 if (has_offset && opcode != TGSI_OPCODE_TXF) {
3688 /* The offsets are six-bit signed integers packed like this:
3689 * X=[5:0], Y=[13:8], and Z=[21:16].
3690 */
3691 LLVMValueRef offset[3], pack;
3692
3693 assert(inst->Texture.NumOffsets == 1);
3694
3695 for (chan = 0; chan < 3; chan++) {
3696 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
3697 emit_data->inst, 0, chan);
3698 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
3699 lp_build_const_int32(gallivm, 0x3f), "");
3700 if (chan)
3701 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
3702 lp_build_const_int32(gallivm, chan*8), "");
3703 }
3704
3705 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
3706 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
3707 address[count++] = pack;
3708 }
3709
3710 /* Pack LOD bias value */
3711 if (opcode == TGSI_OPCODE_TXB)
3712 address[count++] = coords[3];
3713 if (opcode == TGSI_OPCODE_TXB2)
3714 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3715
3716 /* Pack depth comparison value */
3717 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
3718 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
3719 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3720 } else {
3721 assert(ref_pos >= 0);
3722 address[count++] = coords[ref_pos];
3723 }
3724 }
3725
3726 /* Pack user derivatives */
3727 if (opcode == TGSI_OPCODE_TXD) {
3728 int param, num_src_deriv_channels;
3729
3730 switch (target) {
3731 case TGSI_TEXTURE_3D:
3732 num_src_deriv_channels = 3;
3733 num_deriv_channels = 3;
3734 break;
3735 case TGSI_TEXTURE_2D:
3736 case TGSI_TEXTURE_SHADOW2D:
3737 case TGSI_TEXTURE_RECT:
3738 case TGSI_TEXTURE_SHADOWRECT:
3739 case TGSI_TEXTURE_2D_ARRAY:
3740 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3741 num_src_deriv_channels = 2;
3742 num_deriv_channels = 2;
3743 break;
3744 case TGSI_TEXTURE_CUBE:
3745 case TGSI_TEXTURE_SHADOWCUBE:
3746 case TGSI_TEXTURE_CUBE_ARRAY:
3747 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
3748 /* Cube derivatives will be converted to 2D. */
3749 num_src_deriv_channels = 3;
3750 num_deriv_channels = 2;
3751 break;
3752 case TGSI_TEXTURE_1D:
3753 case TGSI_TEXTURE_SHADOW1D:
3754 case TGSI_TEXTURE_1D_ARRAY:
3755 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3756 num_src_deriv_channels = 1;
3757 num_deriv_channels = 1;
3758 break;
3759 default:
3760 unreachable("invalid target");
3761 }
3762
3763 for (param = 0; param < 2; param++)
3764 for (chan = 0; chan < num_src_deriv_channels; chan++)
3765 derivs[param * num_src_deriv_channels + chan] =
3766 lp_build_emit_fetch(bld_base, inst, param+1, chan);
3767 }
3768
3769 if (target == TGSI_TEXTURE_CUBE ||
3770 target == TGSI_TEXTURE_CUBE_ARRAY ||
3771 target == TGSI_TEXTURE_SHADOWCUBE ||
3772 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
3773 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
3774
3775 if (opcode == TGSI_OPCODE_TXD)
3776 for (int i = 0; i < num_deriv_channels * 2; i++)
3777 address[count++] = derivs[i];
3778
3779 /* Pack texture coordinates */
3780 address[count++] = coords[0];
3781 if (num_coords > 1)
3782 address[count++] = coords[1];
3783 if (num_coords > 2)
3784 address[count++] = coords[2];
3785
3786 /* Pack LOD or sample index */
3787 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
3788 address[count++] = coords[3];
3789 else if (opcode == TGSI_OPCODE_TXL2)
3790 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3791
3792 if (count > 16) {
3793 assert(!"Cannot handle more than 16 texture address parameters");
3794 count = 16;
3795 }
3796
3797 for (chan = 0; chan < count; chan++ ) {
3798 address[chan] = LLVMBuildBitCast(gallivm->builder,
3799 address[chan], ctx->i32, "");
3800 }
3801
3802 /* Adjust the sample index according to FMASK.
3803 *
3804 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3805 * which is the identity mapping. Each nibble says which physical sample
3806 * should be fetched to get that sample.
3807 *
3808 * For example, 0x11111100 means there are only 2 samples stored and
3809 * the second sample covers 3/4 of the pixel. When reading samples 0
3810 * and 1, return physical sample 0 (determined by the first two 0s
3811 * in FMASK), otherwise return physical sample 1.
3812 *
3813 * The sample index should be adjusted as follows:
3814 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3815 */
3816 if (target == TGSI_TEXTURE_2D_MSAA ||
3817 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3818 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3819 struct lp_build_emit_data txf_emit_data = *emit_data;
3820 LLVMValueRef txf_address[4];
3821 unsigned txf_count = count;
3822 struct tgsi_full_instruction inst = {};
3823
3824 memcpy(txf_address, address, sizeof(txf_address));
3825
3826 if (target == TGSI_TEXTURE_2D_MSAA) {
3827 txf_address[2] = bld_base->uint_bld.zero;
3828 }
3829 txf_address[3] = bld_base->uint_bld.zero;
3830
3831 /* Read FMASK using TXF. */
3832 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
3833 inst.Texture.Texture = target;
3834 txf_emit_data.inst = &inst;
3835 txf_emit_data.chan = 0;
3836 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
3837 target, fmask_ptr, NULL,
3838 txf_address, txf_count, 0xf);
3839 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
3840
3841 /* Initialize some constants. */
3842 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
3843 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
3844
3845 /* Apply the formula. */
3846 LLVMValueRef fmask =
3847 LLVMBuildExtractElement(gallivm->builder,
3848 txf_emit_data.output[0],
3849 uint_bld->zero, "");
3850
3851 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
3852
3853 LLVMValueRef sample_index4 =
3854 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
3855
3856 LLVMValueRef shifted_fmask =
3857 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
3858
3859 LLVMValueRef final_sample =
3860 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
3861
3862 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3863 * resource descriptor is 0 (invalid),
3864 */
3865 LLVMValueRef fmask_desc =
3866 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
3867 ctx->v8i32, "");
3868
3869 LLVMValueRef fmask_word1 =
3870 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
3871 uint_bld->one, "");
3872
3873 LLVMValueRef word1_is_nonzero =
3874 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3875 fmask_word1, uint_bld->zero, "");
3876
3877 /* Replace the MSAA sample index. */
3878 address[sample_chan] =
3879 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
3880 final_sample, address[sample_chan], "");
3881 }
3882
3883 if (opcode == TGSI_OPCODE_TXF) {
3884 /* add tex offsets */
3885 if (inst->Texture.NumOffsets) {
3886 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3887 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
3888 const struct tgsi_texture_offset *off = inst->TexOffsets;
3889
3890 assert(inst->Texture.NumOffsets == 1);
3891
3892 switch (target) {
3893 case TGSI_TEXTURE_3D:
3894 address[2] = lp_build_add(uint_bld, address[2],
3895 bld->immediates[off->Index][off->SwizzleZ]);
3896 /* fall through */
3897 case TGSI_TEXTURE_2D:
3898 case TGSI_TEXTURE_SHADOW2D:
3899 case TGSI_TEXTURE_RECT:
3900 case TGSI_TEXTURE_SHADOWRECT:
3901 case TGSI_TEXTURE_2D_ARRAY:
3902 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3903 address[1] =
3904 lp_build_add(uint_bld, address[1],
3905 bld->immediates[off->Index][off->SwizzleY]);
3906 /* fall through */
3907 case TGSI_TEXTURE_1D:
3908 case TGSI_TEXTURE_SHADOW1D:
3909 case TGSI_TEXTURE_1D_ARRAY:
3910 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3911 address[0] =
3912 lp_build_add(uint_bld, address[0],
3913 bld->immediates[off->Index][off->SwizzleX]);
3914 break;
3915 /* texture offsets do not apply to other texture targets */
3916 }
3917 }
3918 }
3919
3920 if (opcode == TGSI_OPCODE_TG4) {
3921 unsigned gather_comp = 0;
3922
3923 /* DMASK was repurposed for GATHER4. 4 components are always
3924 * returned and DMASK works like a swizzle - it selects
3925 * the component to fetch. The only valid DMASK values are
3926 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3927 * (red,red,red,red) etc.) The ISA document doesn't mention
3928 * this.
3929 */
3930
3931 /* Get the component index from src1.x for Gather4. */
3932 if (!tgsi_is_shadow_target(target)) {
3933 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3934 LLVMValueRef comp_imm;
3935 struct tgsi_src_register src1 = inst->Src[1].Register;
3936
3937 assert(src1.File == TGSI_FILE_IMMEDIATE);
3938
3939 comp_imm = imms[src1.Index][src1.SwizzleX];
3940 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
3941 gather_comp = CLAMP(gather_comp, 0, 3);
3942 }
3943
3944 dmask = 1 << gather_comp;
3945 }
3946
3947 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3948 samp_ptr, address, count, dmask);
3949 }
3950
3951 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3952 struct lp_build_tgsi_context *bld_base,
3953 struct lp_build_emit_data *emit_data)
3954 {
3955 struct lp_build_context *base = &bld_base->base;
3956 unsigned opcode = emit_data->inst->Instruction.Opcode;
3957 unsigned target = emit_data->inst->Texture.Texture;
3958 char intr_name[127];
3959 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
3960 bool is_shadow = tgsi_is_shadow_target(target);
3961 char type[64];
3962 const char *name = "llvm.SI.image.sample";
3963 const char *infix = "";
3964
3965 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
3966 /* Just return the buffer size. */
3967 emit_data->output[emit_data->chan] = emit_data->args[0];
3968 return;
3969 }
3970
3971 if (target == TGSI_TEXTURE_BUFFER) {
3972 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3973 base->gallivm->builder,
3974 "llvm.SI.vs.load.input", emit_data->dst_type,
3975 emit_data->args, emit_data->arg_count,
3976 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3977 return;
3978 }
3979
3980 switch (opcode) {
3981 case TGSI_OPCODE_TXF:
3982 name = target == TGSI_TEXTURE_2D_MSAA ||
3983 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
3984 "llvm.SI.image.load" :
3985 "llvm.SI.image.load.mip";
3986 is_shadow = false;
3987 has_offset = false;
3988 break;
3989 case TGSI_OPCODE_TXQ:
3990 name = "llvm.SI.getresinfo";
3991 is_shadow = false;
3992 has_offset = false;
3993 break;
3994 case TGSI_OPCODE_LODQ:
3995 name = "llvm.SI.getlod";
3996 is_shadow = false;
3997 has_offset = false;
3998 break;
3999 case TGSI_OPCODE_TEX:
4000 case TGSI_OPCODE_TEX2:
4001 case TGSI_OPCODE_TXP:
4002 break;
4003 case TGSI_OPCODE_TXB:
4004 case TGSI_OPCODE_TXB2:
4005 infix = ".b";
4006 break;
4007 case TGSI_OPCODE_TXL:
4008 case TGSI_OPCODE_TXL2:
4009 infix = ".l";
4010 break;
4011 case TGSI_OPCODE_TXD:
4012 infix = ".d";
4013 break;
4014 case TGSI_OPCODE_TG4:
4015 name = "llvm.SI.gather4";
4016 break;
4017 default:
4018 assert(0);
4019 return;
4020 }
4021
4022 /* Add the type and suffixes .c, .o if needed. */
4023 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4024 sprintf(intr_name, "%s%s%s%s.%s",
4025 name, is_shadow ? ".c" : "", infix,
4026 has_offset ? ".o" : "", type);
4027
4028 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4029 base->gallivm->builder, intr_name, emit_data->dst_type,
4030 emit_data->args, emit_data->arg_count,
4031 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4032
4033 /* Divide the number of layers by 6 to get the number of cubes. */
4034 if (opcode == TGSI_OPCODE_TXQ &&
4035 (target == TGSI_TEXTURE_CUBE_ARRAY ||
4036 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
4037 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4038 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4039 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4040
4041 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4042 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4043 z = LLVMBuildSDiv(builder, z, six, "");
4044
4045 emit_data->output[emit_data->chan] =
4046 LLVMBuildInsertElement(builder, v4, z, two, "");
4047 }
4048 }
4049
4050 static void si_llvm_emit_txqs(
4051 const struct lp_build_tgsi_action *action,
4052 struct lp_build_tgsi_context *bld_base,
4053 struct lp_build_emit_data *emit_data)
4054 {
4055 struct si_shader_context *ctx = si_shader_context(bld_base);
4056 struct gallivm_state *gallivm = bld_base->base.gallivm;
4057 LLVMBuilderRef builder = gallivm->builder;
4058 LLVMValueRef res, samples;
4059 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4060
4061 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4062
4063
4064 /* Read the samples from the descriptor directly. */
4065 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4066 samples = LLVMBuildExtractElement(
4067 builder, res,
4068 lp_build_const_int32(gallivm, 3), "");
4069 samples = LLVMBuildLShr(builder, samples,
4070 lp_build_const_int32(gallivm, 16), "");
4071 samples = LLVMBuildAnd(builder, samples,
4072 lp_build_const_int32(gallivm, 0xf), "");
4073 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4074 samples, "");
4075
4076 emit_data->output[emit_data->chan] = samples;
4077 }
4078
4079 /*
4080 * SI implements derivatives using the local data store (LDS)
4081 * All writes to the LDS happen in all executing threads at
4082 * the same time. TID is the Thread ID for the current
4083 * thread and is a value between 0 and 63, representing
4084 * the thread's position in the wavefront.
4085 *
4086 * For the pixel shader threads are grouped into quads of four pixels.
4087 * The TIDs of the pixels of a quad are:
4088 *
4089 * +------+------+
4090 * |4n + 0|4n + 1|
4091 * +------+------+
4092 * |4n + 2|4n + 3|
4093 * +------+------+
4094 *
4095 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4096 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4097 * the current pixel's column, and masking with 0xfffffffe yields the TID
4098 * of the left pixel of the current pixel's row.
4099 *
4100 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4101 * adding 2 yields the TID of the pixel below the top pixel.
4102 */
4103 /* masks for thread ID. */
4104 #define TID_MASK_TOP_LEFT 0xfffffffc
4105 #define TID_MASK_TOP 0xfffffffd
4106 #define TID_MASK_LEFT 0xfffffffe
4107
4108 static void si_llvm_emit_ddxy(
4109 const struct lp_build_tgsi_action *action,
4110 struct lp_build_tgsi_context *bld_base,
4111 struct lp_build_emit_data *emit_data)
4112 {
4113 struct si_shader_context *ctx = si_shader_context(bld_base);
4114 struct gallivm_state *gallivm = bld_base->base.gallivm;
4115 const struct tgsi_full_instruction *inst = emit_data->inst;
4116 unsigned opcode = inst->Instruction.Opcode;
4117 LLVMValueRef indices[2];
4118 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4119 LLVMValueRef tl, trbl, result[4];
4120 unsigned swizzle[4];
4121 unsigned c;
4122 int idx;
4123 unsigned mask;
4124
4125 indices[0] = bld_base->uint_bld.zero;
4126 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
4127 NULL, 0, LLVMReadNoneAttribute);
4128 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4129 indices, 2, "");
4130
4131 if (opcode == TGSI_OPCODE_DDX_FINE)
4132 mask = TID_MASK_LEFT;
4133 else if (opcode == TGSI_OPCODE_DDY_FINE)
4134 mask = TID_MASK_TOP;
4135 else
4136 mask = TID_MASK_TOP_LEFT;
4137
4138 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
4139 lp_build_const_int32(gallivm, mask), "");
4140 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4141 indices, 2, "");
4142
4143 /* for DDX we want to next X pixel, DDY next Y pixel. */
4144 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4145 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
4146 lp_build_const_int32(gallivm, idx), "");
4147 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4148 indices, 2, "");
4149
4150 for (c = 0; c < 4; ++c) {
4151 unsigned i;
4152
4153 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4154 for (i = 0; i < c; ++i) {
4155 if (swizzle[i] == swizzle[c]) {
4156 result[c] = result[i];
4157 break;
4158 }
4159 }
4160 if (i != c)
4161 continue;
4162
4163 LLVMBuildStore(gallivm->builder,
4164 LLVMBuildBitCast(gallivm->builder,
4165 lp_build_emit_fetch(bld_base, inst, 0, c),
4166 ctx->i32, ""),
4167 store_ptr);
4168
4169 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4170 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4171
4172 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4173 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4174
4175 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4176 }
4177
4178 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4179 }
4180
4181 /*
4182 * this takes an I,J coordinate pair,
4183 * and works out the X and Y derivatives.
4184 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4185 */
4186 static LLVMValueRef si_llvm_emit_ddxy_interp(
4187 struct lp_build_tgsi_context *bld_base,
4188 LLVMValueRef interp_ij)
4189 {
4190 struct si_shader_context *ctx = si_shader_context(bld_base);
4191 struct gallivm_state *gallivm = bld_base->base.gallivm;
4192 LLVMValueRef indices[2];
4193 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4194 LLVMValueRef tl, tr, bl, result[4];
4195 unsigned c;
4196
4197 indices[0] = bld_base->uint_bld.zero;
4198 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
4199 NULL, 0, LLVMReadNoneAttribute);
4200 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4201 indices, 2, "");
4202
4203 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4204 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4205
4206 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4207 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4208
4209 indices[1] = temp;
4210 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4211 indices, 2, "");
4212
4213 indices[1] = temp2;
4214 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4215 indices, 2, "");
4216
4217 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4218 lp_build_const_int32(gallivm, 1), "");
4219 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4220 indices, 2, "");
4221
4222 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4223 lp_build_const_int32(gallivm, 2), "");
4224 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4225 indices, 2, "");
4226
4227 for (c = 0; c < 2; ++c) {
4228 LLVMValueRef store_val;
4229 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4230
4231 store_val = LLVMBuildExtractElement(gallivm->builder,
4232 interp_ij, c_ll, "");
4233 LLVMBuildStore(gallivm->builder,
4234 store_val,
4235 store_ptr);
4236
4237 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4238 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4239
4240 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
4241 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
4242
4243 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
4244
4245 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
4246 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4247
4248 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
4249 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
4250
4251 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
4252 }
4253
4254 return lp_build_gather_values(gallivm, result, 4);
4255 }
4256
4257 static void interp_fetch_args(
4258 struct lp_build_tgsi_context *bld_base,
4259 struct lp_build_emit_data *emit_data)
4260 {
4261 struct si_shader_context *ctx = si_shader_context(bld_base);
4262 struct gallivm_state *gallivm = bld_base->base.gallivm;
4263 const struct tgsi_full_instruction *inst = emit_data->inst;
4264
4265 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4266 /* offset is in second src, first two channels */
4267 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4268 emit_data->inst, 1,
4269 TGSI_CHAN_X);
4270 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4271 emit_data->inst, 1,
4272 TGSI_CHAN_Y);
4273 emit_data->arg_count = 2;
4274 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4275 LLVMValueRef sample_position;
4276 LLVMValueRef sample_id;
4277 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4278
4279 /* fetch sample ID, then fetch its sample position,
4280 * and place into first two channels.
4281 */
4282 sample_id = lp_build_emit_fetch(bld_base,
4283 emit_data->inst, 1, TGSI_CHAN_X);
4284 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4285 ctx->i32, "");
4286 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4287
4288 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4289 sample_position,
4290 lp_build_const_int32(gallivm, 0), "");
4291
4292 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4293 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4294 sample_position,
4295 lp_build_const_int32(gallivm, 1), "");
4296 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4297 emit_data->arg_count = 2;
4298 }
4299 }
4300
4301 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4302 struct lp_build_tgsi_context *bld_base,
4303 struct lp_build_emit_data *emit_data)
4304 {
4305 struct si_shader_context *ctx = si_shader_context(bld_base);
4306 struct si_shader *shader = ctx->shader;
4307 struct gallivm_state *gallivm = bld_base->base.gallivm;
4308 LLVMValueRef interp_param;
4309 const struct tgsi_full_instruction *inst = emit_data->inst;
4310 const char *intr_name;
4311 int input_index = inst->Src[0].Register.Index;
4312 int chan;
4313 int i;
4314 LLVMValueRef attr_number;
4315 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
4316 int interp_param_idx;
4317 unsigned interp = shader->selector->info.input_interpolate[input_index];
4318 unsigned location;
4319
4320 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4321
4322 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4323 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4324 location = TGSI_INTERPOLATE_LOC_CENTER;
4325 else
4326 location = TGSI_INTERPOLATE_LOC_CENTROID;
4327
4328 interp_param_idx = lookup_interp_param_index(interp, location);
4329 if (interp_param_idx == -1)
4330 return;
4331 else if (interp_param_idx)
4332 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
4333 else
4334 interp_param = NULL;
4335
4336 attr_number = lp_build_const_int32(gallivm, input_index);
4337
4338 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4339 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4340 LLVMValueRef ij_out[2];
4341 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4342
4343 /*
4344 * take the I then J parameters, and the DDX/Y for it, and
4345 * calculate the IJ inputs for the interpolator.
4346 * temp1 = ddx * offset/sample.x + I;
4347 * interp_param.I = ddy * offset/sample.y + temp1;
4348 * temp1 = ddx * offset/sample.x + J;
4349 * interp_param.J = ddy * offset/sample.y + temp1;
4350 */
4351 for (i = 0; i < 2; i++) {
4352 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4353 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4354 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4355 ddxy_out, ix_ll, "");
4356 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4357 ddxy_out, iy_ll, "");
4358 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4359 interp_param, ix_ll, "");
4360 LLVMValueRef temp1, temp2;
4361
4362 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4363 ctx->f32, "");
4364
4365 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4366
4367 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4368
4369 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4370
4371 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4372
4373 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
4374 temp2, ctx->i32, "");
4375 }
4376 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4377 }
4378
4379 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4380 for (chan = 0; chan < 2; chan++) {
4381 LLVMValueRef args[4];
4382 LLVMValueRef llvm_chan;
4383 unsigned schan;
4384
4385 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4386 llvm_chan = lp_build_const_int32(gallivm, schan);
4387
4388 args[0] = llvm_chan;
4389 args[1] = attr_number;
4390 args[2] = params;
4391 args[3] = interp_param;
4392
4393 emit_data->output[chan] =
4394 lp_build_intrinsic(gallivm->builder, intr_name,
4395 ctx->f32, args, args[3] ? 4 : 3,
4396 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4397 }
4398 }
4399
4400 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4401 struct lp_build_emit_data *emit_data)
4402 {
4403 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4404 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4405 unsigned stream;
4406
4407 assert(src0.File == TGSI_FILE_IMMEDIATE);
4408
4409 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
4410 return stream;
4411 }
4412
4413 /* Emit one vertex from the geometry shader */
4414 static void si_llvm_emit_vertex(
4415 const struct lp_build_tgsi_action *action,
4416 struct lp_build_tgsi_context *bld_base,
4417 struct lp_build_emit_data *emit_data)
4418 {
4419 struct si_shader_context *ctx = si_shader_context(bld_base);
4420 struct lp_build_context *uint = &bld_base->uint_bld;
4421 struct si_shader *shader = ctx->shader;
4422 struct tgsi_shader_info *info = &shader->selector->info;
4423 struct gallivm_state *gallivm = bld_base->base.gallivm;
4424 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
4425 SI_PARAM_GS2VS_OFFSET);
4426 LLVMValueRef gs_next_vertex;
4427 LLVMValueRef can_emit, kill;
4428 LLVMValueRef args[2];
4429 unsigned chan;
4430 int i;
4431 unsigned stream;
4432
4433 stream = si_llvm_get_stream(bld_base, emit_data);
4434
4435 /* Write vertex attribute values to GSVS ring */
4436 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
4437 ctx->gs_next_vertex[stream],
4438 "");
4439
4440 /* If this thread has already emitted the declared maximum number of
4441 * vertices, kill it: excessive vertex emissions are not supposed to
4442 * have any effect, and GS threads have no externally observable
4443 * effects other than emitting vertices.
4444 */
4445 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
4446 lp_build_const_int32(gallivm,
4447 shader->selector->gs_max_out_vertices), "");
4448 kill = lp_build_select(&bld_base->base, can_emit,
4449 lp_build_const_float(gallivm, 1.0f),
4450 lp_build_const_float(gallivm, -1.0f));
4451
4452 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4453 ctx->voidt, &kill, 1, 0);
4454
4455 for (i = 0; i < info->num_outputs; i++) {
4456 LLVMValueRef *out_ptr =
4457 ctx->radeon_bld.soa.outputs[i];
4458
4459 for (chan = 0; chan < 4; chan++) {
4460 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
4461 LLVMValueRef voffset =
4462 lp_build_const_int32(gallivm, (i * 4 + chan) *
4463 shader->selector->gs_max_out_vertices);
4464
4465 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4466 voffset = lp_build_mul_imm(uint, voffset, 4);
4467
4468 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
4469
4470 build_tbuffer_store(ctx,
4471 ctx->gsvs_ring[stream],
4472 out_val, 1,
4473 voffset, soffset, 0,
4474 V_008F0C_BUF_DATA_FORMAT_32,
4475 V_008F0C_BUF_NUM_FORMAT_UINT,
4476 1, 0, 1, 1, 0);
4477 }
4478 }
4479 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4480 lp_build_const_int32(gallivm, 1));
4481
4482 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4483
4484 /* Signal vertex emission */
4485 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
4486 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4487 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4488 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4489 }
4490
4491 /* Cut one primitive from the geometry shader */
4492 static void si_llvm_emit_primitive(
4493 const struct lp_build_tgsi_action *action,
4494 struct lp_build_tgsi_context *bld_base,
4495 struct lp_build_emit_data *emit_data)
4496 {
4497 struct si_shader_context *ctx = si_shader_context(bld_base);
4498 struct gallivm_state *gallivm = bld_base->base.gallivm;
4499 LLVMValueRef args[2];
4500 unsigned stream;
4501
4502 /* Signal primitive cut */
4503 stream = si_llvm_get_stream(bld_base, emit_data);
4504 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
4505 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4506 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4507 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4508 }
4509
4510 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4511 struct lp_build_tgsi_context *bld_base,
4512 struct lp_build_emit_data *emit_data)
4513 {
4514 struct si_shader_context *ctx = si_shader_context(bld_base);
4515 struct gallivm_state *gallivm = bld_base->base.gallivm;
4516
4517 /* The real barrier instruction isn’t needed, because an entire patch
4518 * always fits into a single wave.
4519 */
4520 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
4521 emit_optimization_barrier(ctx);
4522 return;
4523 }
4524
4525 lp_build_intrinsic(gallivm->builder,
4526 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
4527 : "llvm.AMDGPU.barrier.local",
4528 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
4529 }
4530
4531 static const struct lp_build_tgsi_action tex_action = {
4532 .fetch_args = tex_fetch_args,
4533 .emit = build_tex_intrinsic,
4534 };
4535
4536 static const struct lp_build_tgsi_action interp_action = {
4537 .fetch_args = interp_fetch_args,
4538 .emit = build_interp_intrinsic,
4539 };
4540
4541 static void si_create_function(struct si_shader_context *ctx,
4542 LLVMTypeRef *returns, unsigned num_returns,
4543 LLVMTypeRef *params, unsigned num_params,
4544 int last_array_pointer, int last_sgpr)
4545 {
4546 int i;
4547
4548 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
4549 params, num_params);
4550 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
4551 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
4552
4553 for (i = 0; i <= last_sgpr; ++i) {
4554 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
4555
4556 /* We tell llvm that array inputs are passed by value to allow Sinking pass
4557 * to move load. Inputs are constant so this is fine. */
4558 if (i <= last_array_pointer)
4559 LLVMAddAttribute(P, LLVMByValAttribute);
4560 else
4561 LLVMAddAttribute(P, LLVMInRegAttribute);
4562 }
4563 }
4564
4565 static void create_meta_data(struct si_shader_context *ctx)
4566 {
4567 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
4568 LLVMValueRef args[3];
4569
4570 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
4571 args[1] = 0;
4572 args[2] = lp_build_const_int32(gallivm, 1);
4573
4574 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
4575 }
4576
4577 static void declare_streamout_params(struct si_shader_context *ctx,
4578 struct pipe_stream_output_info *so,
4579 LLVMTypeRef *params, LLVMTypeRef i32,
4580 unsigned *num_params)
4581 {
4582 int i;
4583
4584 /* Streamout SGPRs. */
4585 if (so->num_outputs) {
4586 params[ctx->param_streamout_config = (*num_params)++] = i32;
4587 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
4588 }
4589 /* A streamout buffer offset is loaded if the stride is non-zero. */
4590 for (i = 0; i < 4; i++) {
4591 if (!so->stride[i])
4592 continue;
4593
4594 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
4595 }
4596 }
4597
4598 static unsigned llvm_get_type_size(LLVMTypeRef type)
4599 {
4600 LLVMTypeKind kind = LLVMGetTypeKind(type);
4601
4602 switch (kind) {
4603 case LLVMIntegerTypeKind:
4604 return LLVMGetIntTypeWidth(type) / 8;
4605 case LLVMFloatTypeKind:
4606 return 4;
4607 case LLVMPointerTypeKind:
4608 return 8;
4609 case LLVMVectorTypeKind:
4610 return LLVMGetVectorSize(type) *
4611 llvm_get_type_size(LLVMGetElementType(type));
4612 default:
4613 assert(0);
4614 return 0;
4615 }
4616 }
4617
4618 static void declare_tess_lds(struct si_shader_context *ctx)
4619 {
4620 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4621 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
4622
4623 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
4624 unsigned vertex_data_dw_size = 32*32*4;
4625 unsigned patch_data_dw_size = 32*4;
4626 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
4627 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
4628 unsigned lds_dwords = patch_dw_size;
4629
4630 /* The actual size is computed outside of the shader to reduce
4631 * the number of shader variants. */
4632 ctx->lds =
4633 LLVMAddGlobalInAddressSpace(gallivm->module,
4634 LLVMArrayType(i32, lds_dwords),
4635 "tess_lds",
4636 LOCAL_ADDR_SPACE);
4637 }
4638
4639 static void create_function(struct si_shader_context *ctx)
4640 {
4641 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4642 struct gallivm_state *gallivm = bld_base->base.gallivm;
4643 struct si_shader *shader = ctx->shader;
4644 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
4645 LLVMTypeRef returns[16+32*4];
4646 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
4647 unsigned num_returns = 0;
4648
4649 v3i32 = LLVMVectorType(ctx->i32, 3);
4650
4651 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
4652 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
4653 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
4654 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
4655 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
4656 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
4657
4658 switch (ctx->type) {
4659 case TGSI_PROCESSOR_VERTEX:
4660 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
4661 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
4662 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
4663 params[SI_PARAM_START_INSTANCE] = ctx->i32;
4664 num_params = SI_PARAM_START_INSTANCE+1;
4665
4666 if (shader->key.vs.as_es) {
4667 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4668 } else if (shader->key.vs.as_ls) {
4669 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
4670 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
4671 } else {
4672 if (ctx->is_gs_copy_shader) {
4673 last_array_pointer = SI_PARAM_CONST_BUFFERS;
4674 num_params = SI_PARAM_CONST_BUFFERS+1;
4675 } else {
4676 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
4677 num_params = SI_PARAM_VS_STATE_BITS+1;
4678 }
4679
4680 /* The locations of the other parameters are assigned dynamically. */
4681 declare_streamout_params(ctx, &shader->selector->so,
4682 params, ctx->i32, &num_params);
4683 }
4684
4685 last_sgpr = num_params-1;
4686
4687 /* VGPRs */
4688 params[ctx->param_vertex_id = num_params++] = ctx->i32;
4689 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
4690 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
4691 params[ctx->param_instance_id = num_params++] = ctx->i32;
4692
4693 if (!ctx->is_monolithic &&
4694 !ctx->is_gs_copy_shader) {
4695 /* Vertex load indices. */
4696 ctx->param_vertex_index0 = num_params;
4697
4698 for (i = 0; i < shader->selector->info.num_inputs; i++)
4699 params[num_params++] = ctx->i32;
4700
4701 /* PrimitiveID output. */
4702 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
4703 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4704 returns[num_returns++] = ctx->f32;
4705 }
4706 break;
4707
4708 case TGSI_PROCESSOR_TESS_CTRL:
4709 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4710 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4711 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
4712 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
4713 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
4714
4715 /* VGPRs */
4716 params[SI_PARAM_PATCH_ID] = ctx->i32;
4717 params[SI_PARAM_REL_IDS] = ctx->i32;
4718 num_params = SI_PARAM_REL_IDS+1;
4719
4720 if (!ctx->is_monolithic) {
4721 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
4722 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
4723 returns[num_returns++] = ctx->i32; /* SGPRs */
4724
4725 for (i = 0; i < 3; i++)
4726 returns[num_returns++] = ctx->f32; /* VGPRs */
4727 }
4728 break;
4729
4730 case TGSI_PROCESSOR_TESS_EVAL:
4731 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4732 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4733 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
4734
4735 if (shader->key.tes.as_es) {
4736 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4737 } else {
4738 declare_streamout_params(ctx, &shader->selector->so,
4739 params, ctx->i32, &num_params);
4740 }
4741 last_sgpr = num_params - 1;
4742
4743 /* VGPRs */
4744 params[ctx->param_tes_u = num_params++] = ctx->f32;
4745 params[ctx->param_tes_v = num_params++] = ctx->f32;
4746 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
4747 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
4748
4749 /* PrimitiveID output. */
4750 if (!ctx->is_monolithic && !shader->key.tes.as_es)
4751 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4752 returns[num_returns++] = ctx->f32;
4753 break;
4754
4755 case TGSI_PROCESSOR_GEOMETRY:
4756 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
4757 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
4758 last_sgpr = SI_PARAM_GS_WAVE_ID;
4759
4760 /* VGPRs */
4761 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
4762 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
4763 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
4764 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
4765 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
4766 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
4767 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
4768 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
4769 num_params = SI_PARAM_GS_INSTANCE_ID+1;
4770 break;
4771
4772 case TGSI_PROCESSOR_FRAGMENT:
4773 params[SI_PARAM_ALPHA_REF] = ctx->f32;
4774 params[SI_PARAM_PRIM_MASK] = ctx->i32;
4775 last_sgpr = SI_PARAM_PRIM_MASK;
4776 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
4777 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
4778 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
4779 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
4780 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
4781 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
4782 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
4783 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
4784 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
4785 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
4786 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
4787 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
4788 params[SI_PARAM_FRONT_FACE] = ctx->i32;
4789 params[SI_PARAM_ANCILLARY] = ctx->i32;
4790 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
4791 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
4792 num_params = SI_PARAM_POS_FIXED_PT+1;
4793
4794 if (!ctx->is_monolithic) {
4795 /* Color inputs from the prolog. */
4796 if (shader->selector->info.colors_read) {
4797 unsigned num_color_elements =
4798 util_bitcount(shader->selector->info.colors_read);
4799
4800 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
4801 for (i = 0; i < num_color_elements; i++)
4802 params[num_params++] = ctx->f32;
4803 }
4804
4805 /* Outputs for the epilog. */
4806 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4807 num_returns =
4808 num_return_sgprs +
4809 util_bitcount(shader->selector->info.colors_written) * 4 +
4810 shader->selector->info.writes_z +
4811 shader->selector->info.writes_stencil +
4812 shader->selector->info.writes_samplemask +
4813 1 /* SampleMaskIn */;
4814
4815 num_returns = MAX2(num_returns,
4816 num_return_sgprs +
4817 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4818
4819 for (i = 0; i < num_return_sgprs; i++)
4820 returns[i] = ctx->i32;
4821 for (; i < num_returns; i++)
4822 returns[i] = ctx->f32;
4823 }
4824 break;
4825
4826 default:
4827 assert(0 && "unimplemented shader");
4828 return;
4829 }
4830
4831 assert(num_params <= Elements(params));
4832
4833 si_create_function(ctx, returns, num_returns, params,
4834 num_params, last_array_pointer, last_sgpr);
4835
4836 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4837 if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
4838 !ctx->is_monolithic) {
4839 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
4840 "InitialPSInputAddr",
4841 S_0286D0_PERSP_SAMPLE_ENA(1) |
4842 S_0286D0_PERSP_CENTER_ENA(1) |
4843 S_0286D0_PERSP_CENTROID_ENA(1) |
4844 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4845 S_0286D0_LINEAR_CENTER_ENA(1) |
4846 S_0286D0_LINEAR_CENTROID_ENA(1) |
4847 S_0286D0_FRONT_FACE_ENA(1) |
4848 S_0286D0_POS_FIXED_PT_ENA(1));
4849 }
4850
4851 shader->info.num_input_sgprs = 0;
4852 shader->info.num_input_vgprs = 0;
4853
4854 for (i = 0; i <= last_sgpr; ++i)
4855 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
4856
4857 /* Unused fragment shader inputs are eliminated by the compiler,
4858 * so we don't know yet how many there will be.
4859 */
4860 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
4861 for (; i < num_params; ++i)
4862 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
4863
4864 if (bld_base->info &&
4865 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4866 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4867 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4868 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4869 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4870 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4871 ctx->lds =
4872 LLVMAddGlobalInAddressSpace(gallivm->module,
4873 LLVMArrayType(ctx->i32, 64),
4874 "ddxy_lds",
4875 LOCAL_ADDR_SPACE);
4876
4877 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
4878 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
4879 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
4880 declare_tess_lds(ctx);
4881 }
4882
4883 static void preload_constants(struct si_shader_context *ctx)
4884 {
4885 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4886 struct gallivm_state *gallivm = bld_base->base.gallivm;
4887 const struct tgsi_shader_info *info = bld_base->info;
4888 unsigned buf;
4889 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
4890
4891 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
4892 unsigned i, num_const = info->const_file_max[buf] + 1;
4893
4894 if (num_const == 0)
4895 continue;
4896
4897 /* Allocate space for the constant values */
4898 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
4899
4900 /* Load the resource descriptor */
4901 ctx->const_buffers[buf] =
4902 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
4903
4904 /* Load the constants, we rely on the code sinking to do the rest */
4905 for (i = 0; i < num_const * 4; ++i) {
4906 ctx->constants[buf][i] =
4907 buffer_load_const(gallivm->builder,
4908 ctx->const_buffers[buf],
4909 lp_build_const_int32(gallivm, i * 4),
4910 ctx->f32);
4911 }
4912 }
4913 }
4914
4915 static void preload_shader_buffers(struct si_shader_context *ctx)
4916 {
4917 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4918 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
4919 int buf, maxbuf;
4920
4921 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
4922 SI_NUM_SHADER_BUFFERS - 1);
4923 for (buf = 0; buf <= maxbuf; ++buf) {
4924 ctx->shader_buffers[buf] =
4925 build_indexed_load_const(
4926 ctx, ptr, lp_build_const_int32(gallivm, buf));
4927 }
4928 }
4929
4930 static void preload_samplers(struct si_shader_context *ctx)
4931 {
4932 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4933 struct gallivm_state *gallivm = bld_base->base.gallivm;
4934 const struct tgsi_shader_info *info = bld_base->info;
4935 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
4936 LLVMValueRef offset;
4937
4938 if (num_samplers == 0)
4939 return;
4940
4941 /* Load the resources and samplers, we rely on the code sinking to do the rest */
4942 for (i = 0; i < num_samplers; ++i) {
4943 /* Resource */
4944 offset = lp_build_const_int32(gallivm, i);
4945 ctx->sampler_views[i] =
4946 get_sampler_desc(ctx, offset, DESC_IMAGE);
4947
4948 /* FMASK resource */
4949 if (info->is_msaa_sampler[i])
4950 ctx->fmasks[i] =
4951 get_sampler_desc(ctx, offset, DESC_FMASK);
4952 else {
4953 ctx->sampler_states[i] =
4954 get_sampler_desc(ctx, offset, DESC_SAMPLER);
4955 ctx->sampler_states[i] =
4956 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
4957 ctx->sampler_states[i]);
4958 }
4959 }
4960 }
4961
4962 static void preload_images(struct si_shader_context *ctx)
4963 {
4964 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4965 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4966 struct gallivm_state *gallivm = bld_base->base.gallivm;
4967 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
4968 LLVMValueRef res_ptr;
4969 unsigned i;
4970
4971 if (num_images == 0)
4972 return;
4973
4974 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
4975
4976 for (i = 0; i < num_images; ++i) {
4977 /* Rely on LLVM to shrink the load for buffer resources. */
4978 LLVMValueRef rsrc =
4979 build_indexed_load_const(ctx, res_ptr,
4980 lp_build_const_int32(gallivm, i));
4981
4982 if (info->images_writemask & (1 << i) &&
4983 !(info->images_buffers & (1 << i)))
4984 rsrc = force_dcc_off(ctx, rsrc);
4985
4986 ctx->images[i] = rsrc;
4987 }
4988 }
4989
4990 static void preload_streamout_buffers(struct si_shader_context *ctx)
4991 {
4992 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4993 struct gallivm_state *gallivm = bld_base->base.gallivm;
4994 unsigned i;
4995
4996 /* Streamout can only be used if the shader is compiled as VS. */
4997 if (!ctx->shader->selector->so.num_outputs ||
4998 (ctx->type == TGSI_PROCESSOR_VERTEX &&
4999 (ctx->shader->key.vs.as_es ||
5000 ctx->shader->key.vs.as_ls)) ||
5001 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
5002 ctx->shader->key.tes.as_es))
5003 return;
5004
5005 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5006 SI_PARAM_RW_BUFFERS);
5007
5008 /* Load the resources, we rely on the code sinking to do the rest */
5009 for (i = 0; i < 4; ++i) {
5010 if (ctx->shader->selector->so.stride[i]) {
5011 LLVMValueRef offset = lp_build_const_int32(gallivm,
5012 SI_SO_BUF_OFFSET + i);
5013
5014 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5015 }
5016 }
5017 }
5018
5019 /**
5020 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5021 * for later use.
5022 */
5023 static void preload_ring_buffers(struct si_shader_context *ctx)
5024 {
5025 struct gallivm_state *gallivm =
5026 ctx->radeon_bld.soa.bld_base.base.gallivm;
5027
5028 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5029 SI_PARAM_RW_BUFFERS);
5030
5031 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
5032 ctx->shader->key.vs.as_es) ||
5033 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
5034 ctx->shader->key.tes.as_es) ||
5035 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
5036 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
5037
5038 ctx->esgs_ring =
5039 build_indexed_load_const(ctx, buf_ptr, offset);
5040 }
5041
5042 if (ctx->is_gs_copy_shader) {
5043 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5044
5045 ctx->gsvs_ring[0] =
5046 build_indexed_load_const(ctx, buf_ptr, offset);
5047 }
5048 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
5049 int i;
5050 for (i = 0; i < 4; i++) {
5051 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
5052
5053 ctx->gsvs_ring[i] =
5054 build_indexed_load_const(ctx, buf_ptr, offset);
5055 }
5056 }
5057 }
5058
5059 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5060 LLVMValueRef param_sampler_views,
5061 unsigned param_pos_fixed_pt)
5062 {
5063 struct lp_build_tgsi_context *bld_base =
5064 &ctx->radeon_bld.soa.bld_base;
5065 struct gallivm_state *gallivm = bld_base->base.gallivm;
5066 struct lp_build_emit_data result = {};
5067 struct tgsi_full_instruction inst = {};
5068 LLVMValueRef desc, sampler_index, address[2], pix;
5069
5070 /* Use the fixed-point gl_FragCoord input.
5071 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5072 * per coordinate to get the repeating effect.
5073 */
5074 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5075 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5076
5077 /* Load the sampler view descriptor. */
5078 sampler_index = lp_build_const_int32(gallivm, SI_POLY_STIPPLE_SAMPLER);
5079 desc = get_sampler_desc_custom(ctx, param_sampler_views,
5080 sampler_index, DESC_IMAGE);
5081
5082 /* Load the texel. */
5083 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
5084 inst.Texture.Texture = TGSI_TEXTURE_2D_MSAA; /* = use load, not load_mip */
5085 result.inst = &inst;
5086 set_tex_fetch_args(ctx, &result, TGSI_OPCODE_TXF,
5087 inst.Texture.Texture,
5088 desc, NULL, address, ARRAY_SIZE(address), 0xf);
5089 build_tex_intrinsic(&tex_action, bld_base, &result);
5090
5091 /* Kill the thread accordingly. */
5092 pix = LLVMBuildExtractElement(gallivm->builder, result.output[0],
5093 lp_build_const_int32(gallivm, 3), "");
5094 pix = bitcast(bld_base, TGSI_TYPE_FLOAT, pix);
5095 pix = LLVMBuildFNeg(gallivm->builder, pix, "");
5096
5097 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5098 LLVMVoidTypeInContext(gallivm->context),
5099 &pix, 1, 0);
5100 }
5101
5102 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5103 struct si_shader_config *conf,
5104 unsigned symbol_offset)
5105 {
5106 unsigned i;
5107 const unsigned char *config =
5108 radeon_shader_binary_config_start(binary, symbol_offset);
5109
5110 /* XXX: We may be able to emit some of these values directly rather than
5111 * extracting fields to be emitted later.
5112 */
5113
5114 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5115 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5116 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5117 switch (reg) {
5118 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5119 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5120 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5121 case R_00B848_COMPUTE_PGM_RSRC1:
5122 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5123 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5124 conf->float_mode = G_00B028_FLOAT_MODE(value);
5125 conf->rsrc1 = value;
5126 break;
5127 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5128 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5129 break;
5130 case R_00B84C_COMPUTE_PGM_RSRC2:
5131 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5132 conf->rsrc2 = value;
5133 break;
5134 case R_0286CC_SPI_PS_INPUT_ENA:
5135 conf->spi_ps_input_ena = value;
5136 break;
5137 case R_0286D0_SPI_PS_INPUT_ADDR:
5138 conf->spi_ps_input_addr = value;
5139 break;
5140 case R_0286E8_SPI_TMPRING_SIZE:
5141 case R_00B860_COMPUTE_TMPRING_SIZE:
5142 /* WAVESIZE is in units of 256 dwords. */
5143 conf->scratch_bytes_per_wave =
5144 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
5145 break;
5146 default:
5147 {
5148 static bool printed;
5149
5150 if (!printed) {
5151 fprintf(stderr, "Warning: LLVM emitted unknown "
5152 "config register: 0x%x\n", reg);
5153 printed = true;
5154 }
5155 }
5156 break;
5157 }
5158
5159 if (!conf->spi_ps_input_addr)
5160 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5161 }
5162 }
5163
5164 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5165 struct si_shader *shader,
5166 uint64_t scratch_va)
5167 {
5168 unsigned i;
5169 uint32_t scratch_rsrc_dword0 = scratch_va;
5170 uint32_t scratch_rsrc_dword1 =
5171 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
5172 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
5173
5174 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5175 const struct radeon_shader_reloc *reloc =
5176 &shader->binary.relocs[i];
5177 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5178 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5179 &scratch_rsrc_dword0, 4);
5180 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5181 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5182 &scratch_rsrc_dword1, 4);
5183 }
5184 }
5185 }
5186
5187 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5188 {
5189 unsigned size = shader->binary.code_size;
5190
5191 if (shader->prolog)
5192 size += shader->prolog->binary.code_size;
5193 if (shader->epilog)
5194 size += shader->epilog->binary.code_size;
5195 return size;
5196 }
5197
5198 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5199 {
5200 const struct radeon_shader_binary *prolog =
5201 shader->prolog ? &shader->prolog->binary : NULL;
5202 const struct radeon_shader_binary *epilog =
5203 shader->epilog ? &shader->epilog->binary : NULL;
5204 const struct radeon_shader_binary *mainb = &shader->binary;
5205 unsigned bo_size = si_get_shader_binary_size(shader) +
5206 (!epilog ? mainb->rodata_size : 0);
5207 unsigned char *ptr;
5208
5209 assert(!prolog || !prolog->rodata_size);
5210 assert((!prolog && !epilog) || !mainb->rodata_size);
5211 assert(!epilog || !epilog->rodata_size);
5212
5213 r600_resource_reference(&shader->bo, NULL);
5214 shader->bo = si_resource_create_custom(&sscreen->b.b,
5215 PIPE_USAGE_IMMUTABLE,
5216 bo_size);
5217 if (!shader->bo)
5218 return -ENOMEM;
5219
5220 /* Upload. */
5221 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5222 PIPE_TRANSFER_READ_WRITE);
5223
5224 if (prolog) {
5225 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5226 ptr += prolog->code_size;
5227 }
5228
5229 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5230 ptr += mainb->code_size;
5231
5232 if (epilog)
5233 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5234 else if (mainb->rodata_size > 0)
5235 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5236
5237 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5238 return 0;
5239 }
5240
5241 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5242 struct pipe_debug_callback *debug,
5243 const char *name, FILE *file)
5244 {
5245 char *line, *p;
5246 unsigned i, count;
5247
5248 if (binary->disasm_string) {
5249 fprintf(file, "Shader %s disassembly:\n", name);
5250 fprintf(file, "%s", binary->disasm_string);
5251
5252 if (debug && debug->debug_message) {
5253 /* Very long debug messages are cut off, so send the
5254 * disassembly one line at a time. This causes more
5255 * overhead, but on the plus side it simplifies
5256 * parsing of resulting logs.
5257 */
5258 pipe_debug_message(debug, SHADER_INFO,
5259 "Shader Disassembly Begin");
5260
5261 line = binary->disasm_string;
5262 while (*line) {
5263 p = util_strchrnul(line, '\n');
5264 count = p - line;
5265
5266 if (count) {
5267 pipe_debug_message(debug, SHADER_INFO,
5268 "%.*s", count, line);
5269 }
5270
5271 if (!*p)
5272 break;
5273 line = p + 1;
5274 }
5275
5276 pipe_debug_message(debug, SHADER_INFO,
5277 "Shader Disassembly End");
5278 }
5279 } else {
5280 fprintf(file, "Shader %s binary:\n", name);
5281 for (i = 0; i < binary->code_size; i += 4) {
5282 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5283 binary->code[i + 3], binary->code[i + 2],
5284 binary->code[i + 1], binary->code[i]);
5285 }
5286 }
5287 }
5288
5289 static void si_shader_dump_stats(struct si_screen *sscreen,
5290 struct si_shader_config *conf,
5291 unsigned num_inputs,
5292 unsigned code_size,
5293 struct pipe_debug_callback *debug,
5294 unsigned processor,
5295 FILE *file)
5296 {
5297 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5298 unsigned lds_per_wave = 0;
5299 unsigned max_simd_waves = 10;
5300
5301 /* Compute LDS usage for PS. */
5302 if (processor == TGSI_PROCESSOR_FRAGMENT) {
5303 /* The minimum usage per wave is (num_inputs * 36). The maximum
5304 * usage is (num_inputs * 36 * 16).
5305 * We can get anything in between and it varies between waves.
5306 *
5307 * Other stages don't know the size at compile time or don't
5308 * allocate LDS per wave, but instead they do it per thread group.
5309 */
5310 lds_per_wave = conf->lds_size * lds_increment +
5311 align(num_inputs * 36, lds_increment);
5312 }
5313
5314 /* Compute the per-SIMD wave counts. */
5315 if (conf->num_sgprs) {
5316 if (sscreen->b.chip_class >= VI)
5317 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5318 else
5319 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5320 }
5321
5322 if (conf->num_vgprs)
5323 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5324
5325 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5326 * that PS can use.
5327 */
5328 if (lds_per_wave)
5329 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5330
5331 if (file != stderr ||
5332 r600_can_dump_shader(&sscreen->b, processor)) {
5333 if (processor == TGSI_PROCESSOR_FRAGMENT) {
5334 fprintf(file, "*** SHADER CONFIG ***\n"
5335 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5336 "SPI_PS_INPUT_ENA = 0x%04x\n",
5337 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5338 }
5339
5340 fprintf(file, "*** SHADER STATS ***\n"
5341 "SGPRS: %d\n"
5342 "VGPRS: %d\n"
5343 "Code Size: %d bytes\n"
5344 "LDS: %d blocks\n"
5345 "Scratch: %d bytes per wave\n"
5346 "Max Waves: %d\n"
5347 "********************\n",
5348 conf->num_sgprs, conf->num_vgprs, code_size,
5349 conf->lds_size, conf->scratch_bytes_per_wave,
5350 max_simd_waves);
5351 }
5352
5353 pipe_debug_message(debug, SHADER_INFO,
5354 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5355 "LDS: %d Scratch: %d Max Waves: %d",
5356 conf->num_sgprs, conf->num_vgprs, code_size,
5357 conf->lds_size, conf->scratch_bytes_per_wave,
5358 max_simd_waves);
5359 }
5360
5361 static const char *si_get_shader_name(struct si_shader *shader,
5362 unsigned processor)
5363 {
5364 switch (processor) {
5365 case TGSI_PROCESSOR_VERTEX:
5366 if (shader->key.vs.as_es)
5367 return "Vertex Shader as ES";
5368 else if (shader->key.vs.as_ls)
5369 return "Vertex Shader as LS";
5370 else
5371 return "Vertex Shader as VS";
5372 case TGSI_PROCESSOR_TESS_CTRL:
5373 return "Tessellation Control Shader";
5374 case TGSI_PROCESSOR_TESS_EVAL:
5375 if (shader->key.tes.as_es)
5376 return "Tessellation Evaluation Shader as ES";
5377 else
5378 return "Tessellation Evaluation Shader as VS";
5379 case TGSI_PROCESSOR_GEOMETRY:
5380 if (shader->gs_copy_shader == NULL)
5381 return "GS Copy Shader as VS";
5382 else
5383 return "Geometry Shader";
5384 case TGSI_PROCESSOR_FRAGMENT:
5385 return "Pixel Shader";
5386 case TGSI_PROCESSOR_COMPUTE:
5387 return "Compute Shader";
5388 default:
5389 return "Unknown Shader";
5390 }
5391 }
5392
5393 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5394 struct pipe_debug_callback *debug, unsigned processor,
5395 FILE *file)
5396 {
5397 if (file != stderr ||
5398 (r600_can_dump_shader(&sscreen->b, processor) &&
5399 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5400 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5401
5402 if (shader->prolog)
5403 si_shader_dump_disassembly(&shader->prolog->binary,
5404 debug, "prolog", file);
5405
5406 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5407
5408 if (shader->epilog)
5409 si_shader_dump_disassembly(&shader->epilog->binary,
5410 debug, "epilog", file);
5411 fprintf(file, "\n");
5412 }
5413
5414 si_shader_dump_stats(sscreen, &shader->config,
5415 shader->selector ? shader->selector->info.num_inputs : 0,
5416 si_get_shader_binary_size(shader), debug, processor,
5417 file);
5418 }
5419
5420 int si_compile_llvm(struct si_screen *sscreen,
5421 struct radeon_shader_binary *binary,
5422 struct si_shader_config *conf,
5423 LLVMTargetMachineRef tm,
5424 LLVMModuleRef mod,
5425 struct pipe_debug_callback *debug,
5426 unsigned processor,
5427 const char *name)
5428 {
5429 int r = 0;
5430 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5431
5432 if (r600_can_dump_shader(&sscreen->b, processor)) {
5433 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5434
5435 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5436 fprintf(stderr, "%s LLVM IR:\n\n", name);
5437 LLVMDumpModule(mod);
5438 fprintf(stderr, "\n");
5439 }
5440 }
5441
5442 if (!si_replace_shader(count, binary)) {
5443 r = radeon_llvm_compile(mod, binary,
5444 r600_get_llvm_processor_name(sscreen->b.family), tm,
5445 debug);
5446 if (r)
5447 return r;
5448 }
5449
5450 si_shader_binary_read_config(binary, conf, 0);
5451
5452 /* Enable 64-bit and 16-bit denormals, because there is no performance
5453 * cost.
5454 *
5455 * If denormals are enabled, all floating-point output modifiers are
5456 * ignored.
5457 *
5458 * Don't enable denormals for 32-bit floats, because:
5459 * - Floating-point output modifiers would be ignored by the hw.
5460 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5461 * have to stop using those.
5462 * - SI & CI would be very slow.
5463 */
5464 conf->float_mode |= V_00B028_FP_64_DENORMS;
5465
5466 FREE(binary->config);
5467 FREE(binary->global_symbol_offsets);
5468 binary->config = NULL;
5469 binary->global_symbol_offsets = NULL;
5470
5471 /* Some shaders can't have rodata because their binaries can be
5472 * concatenated.
5473 */
5474 if (binary->rodata_size &&
5475 (processor == TGSI_PROCESSOR_VERTEX ||
5476 processor == TGSI_PROCESSOR_TESS_CTRL ||
5477 processor == TGSI_PROCESSOR_TESS_EVAL ||
5478 processor == TGSI_PROCESSOR_FRAGMENT)) {
5479 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5480 return -EINVAL;
5481 }
5482
5483 return r;
5484 }
5485
5486 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5487 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
5488 struct si_shader_context *ctx,
5489 struct si_shader *gs,
5490 struct pipe_debug_callback *debug)
5491 {
5492 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5493 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5494 struct lp_build_context *uint = &bld_base->uint_bld;
5495 struct si_shader_output_values *outputs;
5496 struct tgsi_shader_info *gsinfo = &gs->selector->info;
5497 LLVMValueRef args[9];
5498 int i, r;
5499
5500 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5501
5502 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
5503 ctx->type = TGSI_PROCESSOR_VERTEX;
5504 ctx->is_gs_copy_shader = true;
5505
5506 create_meta_data(ctx);
5507 create_function(ctx);
5508 preload_streamout_buffers(ctx);
5509 preload_ring_buffers(ctx);
5510
5511 args[0] = ctx->gsvs_ring[0];
5512 args[1] = lp_build_mul_imm(uint,
5513 LLVMGetParam(ctx->radeon_bld.main_fn,
5514 ctx->param_vertex_id),
5515 4);
5516 args[3] = uint->zero;
5517 args[4] = uint->one; /* OFFEN */
5518 args[5] = uint->zero; /* IDXEN */
5519 args[6] = uint->one; /* GLC */
5520 args[7] = uint->one; /* SLC */
5521 args[8] = uint->zero; /* TFE */
5522
5523 /* Fetch vertex data from GSVS ring */
5524 for (i = 0; i < gsinfo->num_outputs; ++i) {
5525 unsigned chan;
5526
5527 outputs[i].name = gsinfo->output_semantic_name[i];
5528 outputs[i].sid = gsinfo->output_semantic_index[i];
5529
5530 for (chan = 0; chan < 4; chan++) {
5531 args[2] = lp_build_const_int32(gallivm,
5532 (i * 4 + chan) *
5533 gs->selector->gs_max_out_vertices * 16 * 4);
5534
5535 outputs[i].values[chan] =
5536 LLVMBuildBitCast(gallivm->builder,
5537 lp_build_intrinsic(gallivm->builder,
5538 "llvm.SI.buffer.load.dword.i32.i32",
5539 ctx->i32, args, 9,
5540 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
5541 ctx->f32, "");
5542 }
5543 }
5544
5545 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5546
5547 LLVMBuildRet(gallivm->builder, ctx->return_value);
5548
5549 /* Dump LLVM IR before any optimization passes */
5550 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5551 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5552 LLVMDumpModule(bld_base->base.gallivm->module);
5553
5554 radeon_llvm_finalize_module(&ctx->radeon_bld);
5555
5556 r = si_compile_llvm(sscreen, &ctx->shader->binary,
5557 &ctx->shader->config, ctx->tm,
5558 bld_base->base.gallivm->module,
5559 debug, TGSI_PROCESSOR_GEOMETRY,
5560 "GS Copy Shader");
5561 if (!r) {
5562 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5563 fprintf(stderr, "GS Copy Shader:\n");
5564 si_shader_dump(sscreen, ctx->shader, debug,
5565 TGSI_PROCESSOR_GEOMETRY, stderr);
5566 r = si_shader_binary_upload(sscreen, ctx->shader);
5567 }
5568
5569 radeon_llvm_dispose(&ctx->radeon_bld);
5570
5571 FREE(outputs);
5572 return r;
5573 }
5574
5575 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
5576 {
5577 int i;
5578
5579 fprintf(f, "SHADER KEY\n");
5580
5581 switch (shader) {
5582 case PIPE_SHADER_VERTEX:
5583 fprintf(f, " instance_divisors = {");
5584 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
5585 fprintf(f, !i ? "%u" : ", %u",
5586 key->vs.prolog.instance_divisors[i]);
5587 fprintf(f, "}\n");
5588 fprintf(f, " as_es = %u\n", key->vs.as_es);
5589 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
5590 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
5591 break;
5592
5593 case PIPE_SHADER_TESS_CTRL:
5594 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
5595 break;
5596
5597 case PIPE_SHADER_TESS_EVAL:
5598 fprintf(f, " as_es = %u\n", key->tes.as_es);
5599 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
5600 break;
5601
5602 case PIPE_SHADER_GEOMETRY:
5603 break;
5604
5605 case PIPE_SHADER_FRAGMENT:
5606 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
5607 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
5608 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
5609 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
5610 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
5611 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
5612 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
5613 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
5614 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
5615 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
5616 break;
5617
5618 default:
5619 assert(0);
5620 }
5621 }
5622
5623 static void si_init_shader_ctx(struct si_shader_context *ctx,
5624 struct si_screen *sscreen,
5625 struct si_shader *shader,
5626 LLVMTargetMachineRef tm)
5627 {
5628 struct lp_build_tgsi_context *bld_base;
5629 struct lp_build_tgsi_action tmpl = {};
5630
5631 memset(ctx, 0, sizeof(*ctx));
5632 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
5633 ctx->tm = tm;
5634 ctx->screen = sscreen;
5635 if (shader && shader->selector)
5636 ctx->type = shader->selector->info.processor;
5637 else
5638 ctx->type = -1;
5639 ctx->shader = shader;
5640
5641 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
5642 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
5643 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
5644 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
5645 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
5646 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
5647 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
5648 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
5649 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
5650 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
5651 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
5652 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
5653
5654 bld_base = &ctx->radeon_bld.soa.bld_base;
5655 if (shader && shader->selector)
5656 bld_base->info = &shader->selector->info;
5657 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5658
5659 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5660 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5661 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5662
5663 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
5664 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
5665 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
5666 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
5667 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
5668 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
5669 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
5670 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
5671 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
5672 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
5673 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
5674 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
5675 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
5676
5677 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
5678 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
5679 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
5680 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
5681 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
5682 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
5683
5684 tmpl.fetch_args = atomic_fetch_args;
5685 tmpl.emit = atomic_emit;
5686 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5687 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
5688 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
5689 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
5690 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
5691 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
5692 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
5693 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
5694 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
5695 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
5696 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
5697 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
5698 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
5699 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
5700 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
5701 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
5702 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
5703 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
5704 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
5705 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
5706
5707 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5708
5709 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5710 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5711 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5712 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5713
5714 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5715 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5716 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5717
5718 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
5719 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
5720 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
5721 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
5722 }
5723
5724 int si_compile_tgsi_shader(struct si_screen *sscreen,
5725 LLVMTargetMachineRef tm,
5726 struct si_shader *shader,
5727 bool is_monolithic,
5728 struct pipe_debug_callback *debug)
5729 {
5730 struct si_shader_selector *sel = shader->selector;
5731 struct si_shader_context ctx;
5732 struct lp_build_tgsi_context *bld_base;
5733 LLVMModuleRef mod;
5734 int r = 0;
5735
5736 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
5737 * conversion fails. */
5738 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
5739 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
5740 si_dump_shader_key(sel->type, &shader->key, stderr);
5741 tgsi_dump(sel->tokens, 0);
5742 si_dump_streamout(&sel->so);
5743 }
5744
5745 si_init_shader_ctx(&ctx, sscreen, shader, tm);
5746 ctx.is_monolithic = is_monolithic;
5747
5748 shader->info.uses_instanceid = sel->info.uses_instanceid;
5749
5750 bld_base = &ctx.radeon_bld.soa.bld_base;
5751 ctx.radeon_bld.load_system_value = declare_system_value;
5752
5753 switch (ctx.type) {
5754 case TGSI_PROCESSOR_VERTEX:
5755 ctx.radeon_bld.load_input = declare_input_vs;
5756 if (shader->key.vs.as_ls)
5757 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5758 else if (shader->key.vs.as_es)
5759 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5760 else
5761 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5762 break;
5763 case TGSI_PROCESSOR_TESS_CTRL:
5764 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5765 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5766 bld_base->emit_store = store_output_tcs;
5767 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5768 break;
5769 case TGSI_PROCESSOR_TESS_EVAL:
5770 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5771 if (shader->key.tes.as_es)
5772 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5773 else
5774 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5775 break;
5776 case TGSI_PROCESSOR_GEOMETRY:
5777 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5778 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5779 break;
5780 case TGSI_PROCESSOR_FRAGMENT:
5781 ctx.radeon_bld.load_input = declare_input_fs;
5782 if (is_monolithic)
5783 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
5784 else
5785 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
5786 break;
5787 default:
5788 assert(!"Unsupported shader type");
5789 return -1;
5790 }
5791
5792 create_meta_data(&ctx);
5793 create_function(&ctx);
5794 preload_constants(&ctx);
5795 preload_shader_buffers(&ctx);
5796 preload_samplers(&ctx);
5797 preload_images(&ctx);
5798 preload_streamout_buffers(&ctx);
5799 preload_ring_buffers(&ctx);
5800
5801 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
5802 shader->key.ps.prolog.poly_stipple) {
5803 LLVMValueRef views = LLVMGetParam(ctx.radeon_bld.main_fn,
5804 SI_PARAM_SAMPLERS);
5805 si_llvm_emit_polygon_stipple(&ctx, views,
5806 SI_PARAM_POS_FIXED_PT);
5807 }
5808
5809 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5810 int i;
5811 for (i = 0; i < 4; i++) {
5812 ctx.gs_next_vertex[i] =
5813 lp_build_alloca(bld_base->base.gallivm,
5814 ctx.i32, "");
5815 }
5816 }
5817
5818 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5819 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5820 goto out;
5821 }
5822
5823 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
5824 mod = bld_base->base.gallivm->module;
5825
5826 /* Dump LLVM IR before any optimization passes */
5827 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5828 r600_can_dump_shader(&sscreen->b, ctx.type))
5829 LLVMDumpModule(mod);
5830
5831 radeon_llvm_finalize_module(&ctx.radeon_bld);
5832
5833 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
5834 mod, debug, ctx.type, "TGSI shader");
5835 if (r) {
5836 fprintf(stderr, "LLVM failed to compile shader\n");
5837 goto out;
5838 }
5839
5840 radeon_llvm_dispose(&ctx.radeon_bld);
5841
5842 /* Add the scratch offset to input SGPRs. */
5843 if (shader->config.scratch_bytes_per_wave)
5844 shader->info.num_input_sgprs += 1; /* scratch byte offset */
5845
5846 /* Calculate the number of fragment input VGPRs. */
5847 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
5848 shader->info.num_input_vgprs = 0;
5849 shader->info.face_vgpr_index = -1;
5850
5851 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5852 shader->info.num_input_vgprs += 2;
5853 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
5854 shader->info.num_input_vgprs += 2;
5855 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
5856 shader->info.num_input_vgprs += 2;
5857 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
5858 shader->info.num_input_vgprs += 3;
5859 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5860 shader->info.num_input_vgprs += 2;
5861 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
5862 shader->info.num_input_vgprs += 2;
5863 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
5864 shader->info.num_input_vgprs += 2;
5865 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
5866 shader->info.num_input_vgprs += 1;
5867 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
5868 shader->info.num_input_vgprs += 1;
5869 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
5870 shader->info.num_input_vgprs += 1;
5871 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
5872 shader->info.num_input_vgprs += 1;
5873 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
5874 shader->info.num_input_vgprs += 1;
5875 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
5876 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
5877 shader->info.num_input_vgprs += 1;
5878 }
5879 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
5880 shader->info.num_input_vgprs += 1;
5881 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
5882 shader->info.num_input_vgprs += 1;
5883 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
5884 shader->info.num_input_vgprs += 1;
5885 }
5886
5887 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5888 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
5889 shader->gs_copy_shader->selector = shader->selector;
5890 ctx.shader = shader->gs_copy_shader;
5891 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
5892 shader, debug))) {
5893 free(shader->gs_copy_shader);
5894 shader->gs_copy_shader = NULL;
5895 goto out;
5896 }
5897 }
5898
5899 out:
5900 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
5901 FREE(ctx.constants[i]);
5902 return r;
5903 }
5904
5905 /**
5906 * Create, compile and return a shader part (prolog or epilog).
5907 *
5908 * \param sscreen screen
5909 * \param list list of shader parts of the same category
5910 * \param key shader part key
5911 * \param tm LLVM target machine
5912 * \param debug debug callback
5913 * \param compile the callback responsible for compilation
5914 * \return non-NULL on success
5915 */
5916 static struct si_shader_part *
5917 si_get_shader_part(struct si_screen *sscreen,
5918 struct si_shader_part **list,
5919 union si_shader_part_key *key,
5920 LLVMTargetMachineRef tm,
5921 struct pipe_debug_callback *debug,
5922 bool (*compile)(struct si_screen *,
5923 LLVMTargetMachineRef,
5924 struct pipe_debug_callback *,
5925 struct si_shader_part *))
5926 {
5927 struct si_shader_part *result;
5928
5929 pipe_mutex_lock(sscreen->shader_parts_mutex);
5930
5931 /* Find existing. */
5932 for (result = *list; result; result = result->next) {
5933 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
5934 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5935 return result;
5936 }
5937 }
5938
5939 /* Compile a new one. */
5940 result = CALLOC_STRUCT(si_shader_part);
5941 result->key = *key;
5942 if (!compile(sscreen, tm, debug, result)) {
5943 FREE(result);
5944 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5945 return NULL;
5946 }
5947
5948 result->next = *list;
5949 *list = result;
5950 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5951 return result;
5952 }
5953
5954 /**
5955 * Create a vertex shader prolog.
5956 *
5957 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
5958 * All inputs are returned unmodified. The vertex load indices are
5959 * stored after them, which will used by the API VS for fetching inputs.
5960 *
5961 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
5962 * input_v0,
5963 * input_v1,
5964 * input_v2,
5965 * input_v3,
5966 * (VertexID + BaseVertex),
5967 * (InstanceID + StartInstance),
5968 * (InstanceID / 2 + StartInstance)
5969 */
5970 static bool si_compile_vs_prolog(struct si_screen *sscreen,
5971 LLVMTargetMachineRef tm,
5972 struct pipe_debug_callback *debug,
5973 struct si_shader_part *out)
5974 {
5975 union si_shader_part_key *key = &out->key;
5976 struct si_shader shader = {};
5977 struct si_shader_context ctx;
5978 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5979 LLVMTypeRef *params, *returns;
5980 LLVMValueRef ret, func;
5981 int last_sgpr, num_params, num_returns, i;
5982 bool status = true;
5983
5984 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5985 ctx.type = TGSI_PROCESSOR_VERTEX;
5986 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
5987 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
5988
5989 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
5990 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
5991 sizeof(LLVMTypeRef));
5992 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
5993 key->vs_prolog.last_input + 1) *
5994 sizeof(LLVMTypeRef));
5995 num_params = 0;
5996 num_returns = 0;
5997
5998 /* Declare input and output SGPRs. */
5999 num_params = 0;
6000 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6001 params[num_params++] = ctx.i32;
6002 returns[num_returns++] = ctx.i32;
6003 }
6004 last_sgpr = num_params - 1;
6005
6006 /* 4 preloaded VGPRs (outputs must be floats) */
6007 for (i = 0; i < 4; i++) {
6008 params[num_params++] = ctx.i32;
6009 returns[num_returns++] = ctx.f32;
6010 }
6011
6012 /* Vertex load indices. */
6013 for (i = 0; i <= key->vs_prolog.last_input; i++)
6014 returns[num_returns++] = ctx.f32;
6015
6016 /* Create the function. */
6017 si_create_function(&ctx, returns, num_returns, params,
6018 num_params, -1, last_sgpr);
6019 func = ctx.radeon_bld.main_fn;
6020
6021 /* Copy inputs to outputs. This should be no-op, as the registers match,
6022 * but it will prevent the compiler from overwriting them unintentionally.
6023 */
6024 ret = ctx.return_value;
6025 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6026 LLVMValueRef p = LLVMGetParam(func, i);
6027 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6028 }
6029 for (i = num_params - 4; i < num_params; i++) {
6030 LLVMValueRef p = LLVMGetParam(func, i);
6031 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6032 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6033 }
6034
6035 /* Compute vertex load indices from instance divisors. */
6036 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6037 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6038 LLVMValueRef index;
6039
6040 if (divisor) {
6041 /* InstanceID / Divisor + StartInstance */
6042 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6043 SI_SGPR_START_INSTANCE,
6044 divisor);
6045 } else {
6046 /* VertexID + BaseVertex */
6047 index = LLVMBuildAdd(gallivm->builder,
6048 LLVMGetParam(func, ctx.param_vertex_id),
6049 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6050 }
6051
6052 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6053 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6054 num_params++, "");
6055 }
6056
6057 /* Compile. */
6058 LLVMBuildRet(gallivm->builder, ret);
6059 radeon_llvm_finalize_module(&ctx.radeon_bld);
6060
6061 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6062 gallivm->module, debug, ctx.type,
6063 "Vertex Shader Prolog"))
6064 status = false;
6065
6066 radeon_llvm_dispose(&ctx.radeon_bld);
6067 return status;
6068 }
6069
6070 /**
6071 * Compile the vertex shader epilog. This is also used by the tessellation
6072 * evaluation shader compiled as VS.
6073 *
6074 * The input is PrimitiveID.
6075 *
6076 * If PrimitiveID is required by the pixel shader, export it.
6077 * Otherwise, do nothing.
6078 */
6079 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6080 LLVMTargetMachineRef tm,
6081 struct pipe_debug_callback *debug,
6082 struct si_shader_part *out)
6083 {
6084 union si_shader_part_key *key = &out->key;
6085 struct si_shader_context ctx;
6086 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6087 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6088 LLVMTypeRef params[5];
6089 int num_params, i;
6090 bool status = true;
6091
6092 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6093 ctx.type = TGSI_PROCESSOR_VERTEX;
6094
6095 /* Declare input VGPRs. */
6096 num_params = key->vs_epilog.states.export_prim_id ?
6097 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6098 assert(num_params <= ARRAY_SIZE(params));
6099
6100 for (i = 0; i < num_params; i++)
6101 params[i] = ctx.f32;
6102
6103 /* Create the function. */
6104 si_create_function(&ctx, NULL, 0, params, num_params,
6105 -1, -1);
6106
6107 /* Emit exports. */
6108 if (key->vs_epilog.states.export_prim_id) {
6109 struct lp_build_context *base = &bld_base->base;
6110 struct lp_build_context *uint = &bld_base->uint_bld;
6111 LLVMValueRef args[9];
6112
6113 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6114 args[1] = uint->zero; /* whether the EXEC mask is valid */
6115 args[2] = uint->zero; /* DONE bit */
6116 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6117 key->vs_epilog.prim_id_param_offset);
6118 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6119 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6120 VS_EPILOG_PRIMID_LOC); /* X */
6121 args[6] = uint->undef; /* Y */
6122 args[7] = uint->undef; /* Z */
6123 args[8] = uint->undef; /* W */
6124
6125 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6126 LLVMVoidTypeInContext(base->gallivm->context),
6127 args, 9, 0);
6128 }
6129
6130 /* Compile. */
6131 LLVMBuildRet(gallivm->builder, ctx.return_value);
6132 radeon_llvm_finalize_module(&ctx.radeon_bld);
6133
6134 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6135 gallivm->module, debug, ctx.type,
6136 "Vertex Shader Epilog"))
6137 status = false;
6138
6139 radeon_llvm_dispose(&ctx.radeon_bld);
6140 return status;
6141 }
6142
6143 /**
6144 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6145 */
6146 static bool si_get_vs_epilog(struct si_screen *sscreen,
6147 LLVMTargetMachineRef tm,
6148 struct si_shader *shader,
6149 struct pipe_debug_callback *debug,
6150 struct si_vs_epilog_bits *states)
6151 {
6152 union si_shader_part_key epilog_key;
6153
6154 memset(&epilog_key, 0, sizeof(epilog_key));
6155 epilog_key.vs_epilog.states = *states;
6156
6157 /* Set up the PrimitiveID output. */
6158 if (shader->key.vs.epilog.export_prim_id) {
6159 unsigned index = shader->selector->info.num_outputs;
6160 unsigned offset = shader->info.nr_param_exports++;
6161
6162 epilog_key.vs_epilog.prim_id_param_offset = offset;
6163 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6164 shader->info.vs_output_param_offset[index] = offset;
6165 }
6166
6167 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
6168 &epilog_key, tm, debug,
6169 si_compile_vs_epilog);
6170 return shader->epilog != NULL;
6171 }
6172
6173 /**
6174 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6175 */
6176 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6177 LLVMTargetMachineRef tm,
6178 struct si_shader *shader,
6179 struct pipe_debug_callback *debug)
6180 {
6181 struct tgsi_shader_info *info = &shader->selector->info;
6182 union si_shader_part_key prolog_key;
6183 unsigned i;
6184
6185 /* Get the prolog. */
6186 memset(&prolog_key, 0, sizeof(prolog_key));
6187 prolog_key.vs_prolog.states = shader->key.vs.prolog;
6188 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6189 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6190
6191 /* The prolog is a no-op if there are no inputs. */
6192 if (info->num_inputs) {
6193 shader->prolog =
6194 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6195 &prolog_key, tm, debug,
6196 si_compile_vs_prolog);
6197 if (!shader->prolog)
6198 return false;
6199 }
6200
6201 /* Get the epilog. */
6202 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
6203 !si_get_vs_epilog(sscreen, tm, shader, debug,
6204 &shader->key.vs.epilog))
6205 return false;
6206
6207 /* Set the instanceID flag. */
6208 for (i = 0; i < info->num_inputs; i++)
6209 if (prolog_key.vs_prolog.states.instance_divisors[i])
6210 shader->info.uses_instanceid = true;
6211
6212 return true;
6213 }
6214
6215 /**
6216 * Select and compile (or reuse) TES parts (epilog).
6217 */
6218 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
6219 LLVMTargetMachineRef tm,
6220 struct si_shader *shader,
6221 struct pipe_debug_callback *debug)
6222 {
6223 if (shader->key.tes.as_es)
6224 return true;
6225
6226 /* TES compiled as VS. */
6227 return si_get_vs_epilog(sscreen, tm, shader, debug,
6228 &shader->key.tes.epilog);
6229 }
6230
6231 /**
6232 * Compile the TCS epilog. This writes tesselation factors to memory based on
6233 * the output primitive type of the tesselator (determined by TES).
6234 */
6235 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
6236 LLVMTargetMachineRef tm,
6237 struct pipe_debug_callback *debug,
6238 struct si_shader_part *out)
6239 {
6240 union si_shader_part_key *key = &out->key;
6241 struct si_shader shader = {};
6242 struct si_shader_context ctx;
6243 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6244 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6245 LLVMTypeRef params[16];
6246 LLVMValueRef func;
6247 int last_array_pointer, last_sgpr, num_params;
6248 bool status = true;
6249
6250 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6251 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
6252 shader.key.tcs.epilog = key->tcs_epilog.states;
6253
6254 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
6255 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
6256 last_array_pointer = SI_PARAM_RW_BUFFERS;
6257 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6258 params[SI_PARAM_SAMPLERS] = ctx.i64;
6259 params[SI_PARAM_IMAGES] = ctx.i64;
6260 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6261 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
6262 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
6263 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
6264 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
6265 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
6266 num_params = last_sgpr + 1;
6267
6268 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
6269 params[num_params++] = ctx.i32; /* invocation ID within the patch */
6270 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
6271
6272 /* Create the function. */
6273 si_create_function(&ctx, NULL, 0, params, num_params,
6274 last_array_pointer, last_sgpr);
6275 declare_tess_lds(&ctx);
6276 func = ctx.radeon_bld.main_fn;
6277
6278 si_write_tess_factors(bld_base,
6279 LLVMGetParam(func, last_sgpr + 1),
6280 LLVMGetParam(func, last_sgpr + 2),
6281 LLVMGetParam(func, last_sgpr + 3));
6282
6283 /* Compile. */
6284 LLVMBuildRet(gallivm->builder, ctx.return_value);
6285 radeon_llvm_finalize_module(&ctx.radeon_bld);
6286
6287 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6288 gallivm->module, debug, ctx.type,
6289 "Tessellation Control Shader Epilog"))
6290 status = false;
6291
6292 radeon_llvm_dispose(&ctx.radeon_bld);
6293 return status;
6294 }
6295
6296 /**
6297 * Select and compile (or reuse) TCS parts (epilog).
6298 */
6299 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6300 LLVMTargetMachineRef tm,
6301 struct si_shader *shader,
6302 struct pipe_debug_callback *debug)
6303 {
6304 union si_shader_part_key epilog_key;
6305
6306 /* Get the epilog. */
6307 memset(&epilog_key, 0, sizeof(epilog_key));
6308 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
6309
6310 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6311 &epilog_key, tm, debug,
6312 si_compile_tcs_epilog);
6313 return shader->epilog != NULL;
6314 }
6315
6316 /**
6317 * Compile the pixel shader prolog. This handles:
6318 * - two-side color selection and interpolation
6319 * - overriding interpolation parameters for the API PS
6320 * - polygon stippling
6321 *
6322 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6323 * overriden by other states. (e.g. per-sample interpolation)
6324 * Interpolated colors are stored after the preloaded VGPRs.
6325 */
6326 static bool si_compile_ps_prolog(struct si_screen *sscreen,
6327 LLVMTargetMachineRef tm,
6328 struct pipe_debug_callback *debug,
6329 struct si_shader_part *out)
6330 {
6331 union si_shader_part_key *key = &out->key;
6332 struct si_shader shader = {};
6333 struct si_shader_context ctx;
6334 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6335 LLVMTypeRef *params;
6336 LLVMValueRef ret, func;
6337 int last_sgpr, num_params, num_returns, i, num_color_channels;
6338 bool status = true;
6339
6340 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6341 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6342 shader.key.ps.prolog = key->ps_prolog.states;
6343
6344 /* Number of inputs + 8 color elements. */
6345 params = alloca((key->ps_prolog.num_input_sgprs +
6346 key->ps_prolog.num_input_vgprs + 8) *
6347 sizeof(LLVMTypeRef));
6348
6349 /* Declare inputs. */
6350 num_params = 0;
6351 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
6352 params[num_params++] = ctx.i32;
6353 last_sgpr = num_params - 1;
6354
6355 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
6356 params[num_params++] = ctx.f32;
6357
6358 /* Declare outputs (same as inputs + add colors if needed) */
6359 num_returns = num_params;
6360 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6361 for (i = 0; i < num_color_channels; i++)
6362 params[num_returns++] = ctx.f32;
6363
6364 /* Create the function. */
6365 si_create_function(&ctx, params, num_returns, params,
6366 num_params, -1, last_sgpr);
6367 func = ctx.radeon_bld.main_fn;
6368
6369 /* Copy inputs to outputs. This should be no-op, as the registers match,
6370 * but it will prevent the compiler from overwriting them unintentionally.
6371 */
6372 ret = ctx.return_value;
6373 for (i = 0; i < num_params; i++) {
6374 LLVMValueRef p = LLVMGetParam(func, i);
6375 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6376 }
6377
6378 /* Polygon stippling. */
6379 if (key->ps_prolog.states.poly_stipple) {
6380 /* POS_FIXED_PT is always last. */
6381 unsigned pos = key->ps_prolog.num_input_sgprs +
6382 key->ps_prolog.num_input_vgprs - 1;
6383 LLVMValueRef ptr[2], views;
6384
6385 /* Get the pointer to sampler views. */
6386 ptr[0] = LLVMGetParam(func, SI_SGPR_SAMPLERS);
6387 ptr[1] = LLVMGetParam(func, SI_SGPR_SAMPLERS+1);
6388 views = lp_build_gather_values(gallivm, ptr, 2);
6389 views = LLVMBuildBitCast(gallivm->builder, views, ctx.i64, "");
6390 views = LLVMBuildIntToPtr(gallivm->builder, views,
6391 const_array(ctx.v8i32, SI_NUM_SAMPLERS), "");
6392
6393 si_llvm_emit_polygon_stipple(&ctx, views, pos);
6394 }
6395
6396 /* Interpolate colors. */
6397 for (i = 0; i < 2; i++) {
6398 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6399 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6400 key->ps_prolog.face_vgpr_index;
6401 LLVMValueRef interp[2], color[4];
6402 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6403
6404 if (!writemask)
6405 continue;
6406
6407 /* If the interpolation qualifier is not CONSTANT (-1). */
6408 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6409 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6410 key->ps_prolog.color_interp_vgpr_index[i];
6411
6412 interp[0] = LLVMGetParam(func, interp_vgpr);
6413 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
6414 interp_ij = lp_build_gather_values(gallivm, interp, 2);
6415 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
6416 ctx.v2i32, "");
6417 }
6418
6419 /* Use the absolute location of the input. */
6420 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6421
6422 if (key->ps_prolog.states.color_two_side) {
6423 face = LLVMGetParam(func, face_vgpr);
6424 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
6425 }
6426
6427 interp_fs_input(&ctx,
6428 key->ps_prolog.color_attr_index[i],
6429 TGSI_SEMANTIC_COLOR, i,
6430 key->ps_prolog.num_interp_inputs,
6431 key->ps_prolog.colors_read, interp_ij,
6432 prim_mask, face, color);
6433
6434 while (writemask) {
6435 unsigned chan = u_bit_scan(&writemask);
6436 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
6437 num_params++, "");
6438 }
6439 }
6440
6441 /* Force per-sample interpolation. */
6442 if (key->ps_prolog.states.force_persample_interp) {
6443 unsigned i, base = key->ps_prolog.num_input_sgprs;
6444 LLVMValueRef persp_sample[2], linear_sample[2];
6445
6446 /* Read PERSP_SAMPLE. */
6447 for (i = 0; i < 2; i++)
6448 persp_sample[i] = LLVMGetParam(func, base + i);
6449 /* Overwrite PERSP_CENTER. */
6450 for (i = 0; i < 2; i++)
6451 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6452 persp_sample[i], base + 2 + i, "");
6453 /* Overwrite PERSP_CENTROID. */
6454 for (i = 0; i < 2; i++)
6455 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6456 persp_sample[i], base + 4 + i, "");
6457 /* Read LINEAR_SAMPLE. */
6458 for (i = 0; i < 2; i++)
6459 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6460 /* Overwrite LINEAR_CENTER. */
6461 for (i = 0; i < 2; i++)
6462 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6463 linear_sample[i], base + 8 + i, "");
6464 /* Overwrite LINEAR_CENTROID. */
6465 for (i = 0; i < 2; i++)
6466 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6467 linear_sample[i], base + 10 + i, "");
6468 }
6469
6470 /* Compile. */
6471 LLVMBuildRet(gallivm->builder, ret);
6472 radeon_llvm_finalize_module(&ctx.radeon_bld);
6473
6474 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6475 gallivm->module, debug, ctx.type,
6476 "Fragment Shader Prolog"))
6477 status = false;
6478
6479 radeon_llvm_dispose(&ctx.radeon_bld);
6480 return status;
6481 }
6482
6483 /**
6484 * Compile the pixel shader epilog. This handles everything that must be
6485 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6486 */
6487 static bool si_compile_ps_epilog(struct si_screen *sscreen,
6488 LLVMTargetMachineRef tm,
6489 struct pipe_debug_callback *debug,
6490 struct si_shader_part *out)
6491 {
6492 union si_shader_part_key *key = &out->key;
6493 struct si_shader shader = {};
6494 struct si_shader_context ctx;
6495 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6496 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6497 LLVMTypeRef params[16+8*4+3];
6498 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6499 int last_array_pointer, last_sgpr, num_params, i;
6500 bool status = true;
6501
6502 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6503 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6504 shader.key.ps.epilog = key->ps_epilog.states;
6505
6506 /* Declare input SGPRs. */
6507 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
6508 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6509 params[SI_PARAM_SAMPLERS] = ctx.i64;
6510 params[SI_PARAM_IMAGES] = ctx.i64;
6511 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6512 params[SI_PARAM_ALPHA_REF] = ctx.f32;
6513 last_array_pointer = -1;
6514 last_sgpr = SI_PARAM_ALPHA_REF;
6515
6516 /* Declare input VGPRs. */
6517 num_params = (last_sgpr + 1) +
6518 util_bitcount(key->ps_epilog.colors_written) * 4 +
6519 key->ps_epilog.writes_z +
6520 key->ps_epilog.writes_stencil +
6521 key->ps_epilog.writes_samplemask;
6522
6523 num_params = MAX2(num_params,
6524 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6525
6526 assert(num_params <= ARRAY_SIZE(params));
6527
6528 for (i = last_sgpr + 1; i < num_params; i++)
6529 params[i] = ctx.f32;
6530
6531 /* Create the function. */
6532 si_create_function(&ctx, NULL, 0, params, num_params,
6533 last_array_pointer, last_sgpr);
6534 /* Disable elimination of unused inputs. */
6535 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
6536 "InitialPSInputAddr", 0xffffff);
6537
6538 /* Process colors. */
6539 unsigned vgpr = last_sgpr + 1;
6540 unsigned colors_written = key->ps_epilog.colors_written;
6541 int last_color_export = -1;
6542
6543 /* Find the last color export. */
6544 if (!key->ps_epilog.writes_z &&
6545 !key->ps_epilog.writes_stencil &&
6546 !key->ps_epilog.writes_samplemask) {
6547 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6548
6549 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6550 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6551 /* Just set this if any of the colorbuffers are enabled. */
6552 if (spi_format &
6553 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6554 last_color_export = 0;
6555 } else {
6556 for (i = 0; i < 8; i++)
6557 if (colors_written & (1 << i) &&
6558 (spi_format >> (i * 4)) & 0xf)
6559 last_color_export = i;
6560 }
6561 }
6562
6563 while (colors_written) {
6564 LLVMValueRef color[4];
6565 int mrt = u_bit_scan(&colors_written);
6566
6567 for (i = 0; i < 4; i++)
6568 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6569
6570 si_export_mrt_color(bld_base, color, mrt,
6571 num_params - 1,
6572 mrt == last_color_export);
6573 }
6574
6575 /* Process depth, stencil, samplemask. */
6576 if (key->ps_epilog.writes_z)
6577 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6578 if (key->ps_epilog.writes_stencil)
6579 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6580 if (key->ps_epilog.writes_samplemask)
6581 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6582
6583 if (depth || stencil || samplemask)
6584 si_export_mrt_z(bld_base, depth, stencil, samplemask);
6585 else if (last_color_export == -1)
6586 si_export_null(bld_base);
6587
6588 /* Compile. */
6589 LLVMBuildRetVoid(gallivm->builder);
6590 radeon_llvm_finalize_module(&ctx.radeon_bld);
6591
6592 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6593 gallivm->module, debug, ctx.type,
6594 "Fragment Shader Epilog"))
6595 status = false;
6596
6597 radeon_llvm_dispose(&ctx.radeon_bld);
6598 return status;
6599 }
6600
6601 /**
6602 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6603 */
6604 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6605 LLVMTargetMachineRef tm,
6606 struct si_shader *shader,
6607 struct pipe_debug_callback *debug)
6608 {
6609 struct tgsi_shader_info *info = &shader->selector->info;
6610 union si_shader_part_key prolog_key;
6611 union si_shader_part_key epilog_key;
6612 unsigned i;
6613
6614 /* Get the prolog. */
6615 memset(&prolog_key, 0, sizeof(prolog_key));
6616 prolog_key.ps_prolog.states = shader->key.ps.prolog;
6617 prolog_key.ps_prolog.colors_read = info->colors_read;
6618 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6619 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6620
6621 if (info->colors_read) {
6622 unsigned *color = shader->selector->color_attr_index;
6623
6624 if (shader->key.ps.prolog.color_two_side) {
6625 /* BCOLORs are stored after the last input. */
6626 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
6627 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6628 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6629 }
6630
6631 for (i = 0; i < 2; i++) {
6632 unsigned location = info->input_interpolate_loc[color[i]];
6633
6634 if (!(info->colors_read & (0xf << i*4)))
6635 continue;
6636
6637 prolog_key.ps_prolog.color_attr_index[i] = color[i];
6638
6639 /* Force per-sample interpolation for the colors here. */
6640 if (shader->key.ps.prolog.force_persample_interp)
6641 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6642
6643 switch (info->input_interpolate[color[i]]) {
6644 case TGSI_INTERPOLATE_CONSTANT:
6645 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
6646 break;
6647 case TGSI_INTERPOLATE_PERSPECTIVE:
6648 case TGSI_INTERPOLATE_COLOR:
6649 switch (location) {
6650 case TGSI_INTERPOLATE_LOC_SAMPLE:
6651 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
6652 shader->config.spi_ps_input_ena |=
6653 S_0286CC_PERSP_SAMPLE_ENA(1);
6654 break;
6655 case TGSI_INTERPOLATE_LOC_CENTER:
6656 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
6657 shader->config.spi_ps_input_ena |=
6658 S_0286CC_PERSP_CENTER_ENA(1);
6659 break;
6660 case TGSI_INTERPOLATE_LOC_CENTROID:
6661 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
6662 shader->config.spi_ps_input_ena |=
6663 S_0286CC_PERSP_CENTROID_ENA(1);
6664 break;
6665 default:
6666 assert(0);
6667 }
6668 break;
6669 case TGSI_INTERPOLATE_LINEAR:
6670 switch (location) {
6671 case TGSI_INTERPOLATE_LOC_SAMPLE:
6672 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
6673 shader->config.spi_ps_input_ena |=
6674 S_0286CC_LINEAR_SAMPLE_ENA(1);
6675 break;
6676 case TGSI_INTERPOLATE_LOC_CENTER:
6677 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
6678 shader->config.spi_ps_input_ena |=
6679 S_0286CC_LINEAR_CENTER_ENA(1);
6680 break;
6681 case TGSI_INTERPOLATE_LOC_CENTROID:
6682 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
6683 shader->config.spi_ps_input_ena |=
6684 S_0286CC_LINEAR_CENTROID_ENA(1);
6685 break;
6686 default:
6687 assert(0);
6688 }
6689 break;
6690 default:
6691 assert(0);
6692 }
6693 }
6694 }
6695
6696 /* The prolog is a no-op if these aren't set. */
6697 if (prolog_key.ps_prolog.colors_read ||
6698 prolog_key.ps_prolog.states.force_persample_interp ||
6699 prolog_key.ps_prolog.states.poly_stipple) {
6700 shader->prolog =
6701 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6702 &prolog_key, tm, debug,
6703 si_compile_ps_prolog);
6704 if (!shader->prolog)
6705 return false;
6706 }
6707
6708 /* Get the epilog. */
6709 memset(&epilog_key, 0, sizeof(epilog_key));
6710 epilog_key.ps_epilog.colors_written = info->colors_written;
6711 epilog_key.ps_epilog.writes_z = info->writes_z;
6712 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
6713 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
6714 epilog_key.ps_epilog.states = shader->key.ps.epilog;
6715
6716 shader->epilog =
6717 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6718 &epilog_key, tm, debug,
6719 si_compile_ps_epilog);
6720 if (!shader->epilog)
6721 return false;
6722
6723 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6724 if (shader->key.ps.prolog.poly_stipple) {
6725 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6726 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6727 }
6728
6729 /* Set up the enable bits for per-sample shading if needed. */
6730 if (shader->key.ps.prolog.force_persample_interp) {
6731 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6732 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6733 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
6734 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6735 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
6736 }
6737 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6738 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6739 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
6740 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6741 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
6742 }
6743 }
6744
6745 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
6746 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
6747 !(shader->config.spi_ps_input_ena & 0xf)) {
6748 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6749 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
6750 }
6751
6752 /* At least one pair of interpolation weights must be enabled. */
6753 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
6754 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6755 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
6756 }
6757
6758 /* The sample mask input is always enabled, because the API shader always
6759 * passes it through to the epilog. Disable it here if it's unused.
6760 */
6761 if (!shader->key.ps.epilog.poly_line_smoothing &&
6762 !shader->selector->info.reads_samplemask)
6763 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
6764
6765 return true;
6766 }
6767
6768 static void si_fix_num_sgprs(struct si_shader *shader)
6769 {
6770 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
6771
6772 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
6773 }
6774
6775 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
6776 struct si_shader *shader,
6777 struct pipe_debug_callback *debug)
6778 {
6779 struct si_shader *mainp = shader->selector->main_shader_part;
6780 int r;
6781
6782 /* LS, ES, VS are compiled on demand if the main part hasn't been
6783 * compiled for that stage.
6784 */
6785 if (!mainp ||
6786 (shader->selector->type == PIPE_SHADER_VERTEX &&
6787 (shader->key.vs.as_es != mainp->key.vs.as_es ||
6788 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
6789 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
6790 shader->key.tes.as_es != mainp->key.tes.as_es)) {
6791 /* Monolithic shader (compiled as a whole, has many variants,
6792 * may take a long time to compile).
6793 */
6794 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
6795 if (r)
6796 return r;
6797 } else {
6798 /* The shader consists of 2-3 parts:
6799 *
6800 * - the middle part is the user shader, it has 1 variant only
6801 * and it was compiled during the creation of the shader
6802 * selector
6803 * - the prolog part is inserted at the beginning
6804 * - the epilog part is inserted at the end
6805 *
6806 * The prolog and epilog have many (but simple) variants.
6807 */
6808
6809 /* Copy the compiled TGSI shader data over. */
6810 shader->is_binary_shared = true;
6811 shader->binary = mainp->binary;
6812 shader->config = mainp->config;
6813 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
6814 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
6815 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
6816 memcpy(shader->info.vs_output_param_offset,
6817 mainp->info.vs_output_param_offset,
6818 sizeof(mainp->info.vs_output_param_offset));
6819 shader->info.uses_instanceid = mainp->info.uses_instanceid;
6820 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
6821 shader->info.nr_param_exports = mainp->info.nr_param_exports;
6822
6823 /* Select prologs and/or epilogs. */
6824 switch (shader->selector->type) {
6825 case PIPE_SHADER_VERTEX:
6826 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
6827 return -1;
6828 break;
6829 case PIPE_SHADER_TESS_CTRL:
6830 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
6831 return -1;
6832 break;
6833 case PIPE_SHADER_TESS_EVAL:
6834 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
6835 return -1;
6836 break;
6837 case PIPE_SHADER_FRAGMENT:
6838 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
6839 return -1;
6840
6841 /* Make sure we have at least as many VGPRs as there
6842 * are allocated inputs.
6843 */
6844 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6845 shader->info.num_input_vgprs);
6846 break;
6847 }
6848
6849 /* Update SGPR and VGPR counts. */
6850 if (shader->prolog) {
6851 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6852 shader->prolog->config.num_sgprs);
6853 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6854 shader->prolog->config.num_vgprs);
6855 }
6856 if (shader->epilog) {
6857 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6858 shader->epilog->config.num_sgprs);
6859 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6860 shader->epilog->config.num_vgprs);
6861 }
6862 }
6863
6864 si_fix_num_sgprs(shader);
6865 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
6866 stderr);
6867
6868 /* Upload. */
6869 r = si_shader_binary_upload(sscreen, shader);
6870 if (r) {
6871 fprintf(stderr, "LLVM failed to upload shader\n");
6872 return r;
6873 }
6874
6875 return 0;
6876 }
6877
6878 void si_shader_destroy(struct si_shader *shader)
6879 {
6880 if (shader->gs_copy_shader) {
6881 si_shader_destroy(shader->gs_copy_shader);
6882 FREE(shader->gs_copy_shader);
6883 }
6884
6885 if (shader->scratch_bo)
6886 r600_resource_reference(&shader->scratch_bo, NULL);
6887
6888 r600_resource_reference(&shader->bo, NULL);
6889
6890 if (!shader->is_binary_shared)
6891 radeon_shader_binary_clean(&shader->binary);
6892 }