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radeonsi: remove si_shader_output_values::index
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned sid;
53 };
54
55 struct si_shader_context
56 {
57 struct radeon_llvm_context radeon_bld;
58 struct tgsi_parse_context parse;
59 struct tgsi_token * tokens;
60 struct si_shader *shader;
61 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
62 int param_streamout_config;
63 int param_streamout_write_index;
64 int param_streamout_offset[4];
65 int param_vertex_id;
66 int param_instance_id;
67 LLVMValueRef const_md;
68 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
69 LLVMValueRef ddxy_lds;
70 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef *resources;
72 LLVMValueRef *samplers;
73 LLVMValueRef so_buffers[4];
74 LLVMValueRef gs_next_vertex;
75 };
76
77 static struct si_shader_context * si_shader_context(
78 struct lp_build_tgsi_context * bld_base)
79 {
80 return (struct si_shader_context *)bld_base;
81 }
82
83
84 #define PERSPECTIVE_BASE 0
85 #define LINEAR_BASE 9
86
87 #define SAMPLE_OFFSET 0
88 #define CENTER_OFFSET 2
89 #define CENTROID_OFSET 4
90
91 #define USE_SGPR_MAX_SUFFIX_LEN 5
92 #define CONST_ADDR_SPACE 2
93 #define LOCAL_ADDR_SPACE 3
94 #define USER_SGPR_ADDR_SPACE 8
95
96
97 #define SENDMSG_GS 2
98 #define SENDMSG_GS_DONE 3
99
100 #define SENDMSG_GS_OP_NOP (0 << 4)
101 #define SENDMSG_GS_OP_CUT (1 << 4)
102 #define SENDMSG_GS_OP_EMIT (2 << 4)
103 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
104
105 /**
106 * Returns a unique index for a semantic name and index. The index must be
107 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
108 * calculated.
109 */
110 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
111 {
112 switch (semantic_name) {
113 case TGSI_SEMANTIC_POSITION:
114 return 0;
115 case TGSI_SEMANTIC_PSIZE:
116 return 1;
117 case TGSI_SEMANTIC_CLIPDIST:
118 assert(index <= 1);
119 return 2 + index;
120 case TGSI_SEMANTIC_CLIPVERTEX:
121 return 4;
122 case TGSI_SEMANTIC_COLOR:
123 assert(index <= 1);
124 return 5 + index;
125 case TGSI_SEMANTIC_BCOLOR:
126 assert(index <= 1);
127 return 7 + index;
128 case TGSI_SEMANTIC_FOG:
129 return 9;
130 case TGSI_SEMANTIC_EDGEFLAG:
131 return 10;
132 case TGSI_SEMANTIC_GENERIC:
133 assert(index <= 63-11);
134 return 11 + index;
135 default:
136 assert(0);
137 return 63;
138 }
139 }
140
141 /**
142 * Given a semantic name and index of a parameter and a mask of used parameters
143 * (inputs or outputs), return the index of the parameter in the list of all
144 * used parameters.
145 *
146 * For example, assume this list of parameters:
147 * POSITION, PSIZE, GENERIC0, GENERIC2
148 * which has the mask:
149 * 11000000000101
150 * Then:
151 * querying POSITION returns 0,
152 * querying PSIZE returns 1,
153 * querying GENERIC0 returns 2,
154 * querying GENERIC2 returns 3.
155 *
156 * Which can be used as an offset to a parameter buffer in units of vec4s.
157 */
158 static int get_param_index(unsigned semantic_name, unsigned index,
159 uint64_t mask)
160 {
161 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
162 int i, param_index = 0;
163
164 /* If not present... */
165 if (!((1llu << unique_index) & mask))
166 return -1;
167
168 for (i = 0; mask; i++) {
169 uint64_t bit = 1llu << i;
170
171 if (bit & mask) {
172 if (i == unique_index)
173 return param_index;
174
175 mask &= ~bit;
176 param_index++;
177 }
178 }
179
180 assert(!"unreachable");
181 return -1;
182 }
183
184 /**
185 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
186 *
187 * @param offset The offset parameter specifies the number of
188 * elements to offset, not the number of bytes or dwords. An element is the
189 * the type pointed to by the base_ptr parameter (e.g. int is the element of
190 * an int* pointer)
191 *
192 * When LLVM lowers the load instruction, it will convert the element offset
193 * into a dword offset automatically.
194 *
195 */
196 static LLVMValueRef build_indexed_load(
197 struct si_shader_context * si_shader_ctx,
198 LLVMValueRef base_ptr,
199 LLVMValueRef offset)
200 {
201 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
202
203 LLVMValueRef indices[2] = {
204 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
205 offset
206 };
207 LLVMValueRef computed_ptr = LLVMBuildGEP(
208 base->gallivm->builder, base_ptr, indices, 2, "");
209
210 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
211 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
212 return result;
213 }
214
215 static LLVMValueRef get_instance_index_for_fetch(
216 struct radeon_llvm_context * radeon_bld,
217 unsigned divisor)
218 {
219 struct si_shader_context *si_shader_ctx =
220 si_shader_context(&radeon_bld->soa.bld_base);
221 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
222
223 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
224 si_shader_ctx->param_instance_id);
225 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
226 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
227
228 if (divisor > 1)
229 result = LLVMBuildUDiv(gallivm->builder, result,
230 lp_build_const_int32(gallivm, divisor), "");
231
232 return result;
233 }
234
235 static void declare_input_vs(
236 struct radeon_llvm_context *radeon_bld,
237 unsigned input_index,
238 const struct tgsi_full_declaration *decl)
239 {
240 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
241 struct gallivm_state *gallivm = base->gallivm;
242 struct si_shader_context *si_shader_ctx =
243 si_shader_context(&radeon_bld->soa.bld_base);
244 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
245
246 unsigned chan;
247
248 LLVMValueRef t_list_ptr;
249 LLVMValueRef t_offset;
250 LLVMValueRef t_list;
251 LLVMValueRef attribute_offset;
252 LLVMValueRef buffer_index;
253 LLVMValueRef args[3];
254 LLVMTypeRef vec4_type;
255 LLVMValueRef input;
256
257 /* Load the T list */
258 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
259
260 t_offset = lp_build_const_int32(gallivm, input_index);
261
262 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
263
264 /* Build the attribute offset */
265 attribute_offset = lp_build_const_int32(gallivm, 0);
266
267 if (divisor) {
268 /* Build index from instance ID, start instance and divisor */
269 si_shader_ctx->shader->uses_instanceid = true;
270 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
271 } else {
272 /* Load the buffer index for vertices. */
273 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
274 si_shader_ctx->param_vertex_id);
275 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
276 SI_PARAM_BASE_VERTEX);
277 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
278 }
279
280 vec4_type = LLVMVectorType(base->elem_type, 4);
281 args[0] = t_list;
282 args[1] = attribute_offset;
283 args[2] = buffer_index;
284 input = build_intrinsic(gallivm->builder,
285 "llvm.SI.vs.load.input", vec4_type, args, 3,
286 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
287
288 /* Break up the vec4 into individual components */
289 for (chan = 0; chan < 4; chan++) {
290 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
291 /* XXX: Use a helper function for this. There is one in
292 * tgsi_llvm.c. */
293 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
294 LLVMBuildExtractElement(gallivm->builder,
295 input, llvm_chan, "");
296 }
297 }
298
299 static LLVMValueRef fetch_input_gs(
300 struct lp_build_tgsi_context *bld_base,
301 const struct tgsi_full_src_register *reg,
302 enum tgsi_opcode_type type,
303 unsigned swizzle)
304 {
305 struct lp_build_context *base = &bld_base->base;
306 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
307 struct si_shader *shader = si_shader_ctx->shader;
308 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
309 struct gallivm_state *gallivm = base->gallivm;
310 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
311 LLVMValueRef vtx_offset;
312 LLVMValueRef t_list_ptr;
313 LLVMValueRef t_list;
314 LLVMValueRef args[9];
315 unsigned vtx_offset_param;
316 struct tgsi_shader_info *info = &shader->selector->info;
317 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
318 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
319
320 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
321 if (swizzle == 0)
322 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
323 SI_PARAM_PRIMITIVE_ID);
324 else
325 return uint->zero;
326 }
327
328 if (!reg->Register.Dimension)
329 return NULL;
330
331 if (swizzle == ~0) {
332 LLVMValueRef values[TGSI_NUM_CHANNELS];
333 unsigned chan;
334 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
335 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
336 }
337 return lp_build_gather_values(bld_base->base.gallivm, values,
338 TGSI_NUM_CHANNELS);
339 }
340
341 /* Get the vertex offset parameter */
342 vtx_offset_param = reg->Dimension.Index;
343 if (vtx_offset_param < 2) {
344 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
345 } else {
346 assert(vtx_offset_param < 6);
347 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
348 }
349 vtx_offset = lp_build_mul_imm(uint,
350 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
351 vtx_offset_param),
352 4);
353
354 /* Load the ESGS ring resource descriptor */
355 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
356 SI_PARAM_RW_BUFFERS);
357 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
358 lp_build_const_int32(gallivm, SI_RING_ESGS));
359
360 args[0] = t_list;
361 args[1] = vtx_offset;
362 args[2] = lp_build_const_int32(gallivm,
363 (get_param_index(semantic_name, semantic_index,
364 shader->selector->gs_used_inputs) * 4 +
365 swizzle) * 256);
366 args[3] = uint->zero;
367 args[4] = uint->one; /* OFFEN */
368 args[5] = uint->zero; /* IDXEN */
369 args[6] = uint->one; /* GLC */
370 args[7] = uint->zero; /* SLC */
371 args[8] = uint->zero; /* TFE */
372
373 return LLVMBuildBitCast(gallivm->builder,
374 build_intrinsic(gallivm->builder,
375 "llvm.SI.buffer.load.dword.i32.i32",
376 i32, args, 9,
377 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
378 tgsi2llvmtype(bld_base, type), "");
379 }
380
381 static void declare_input_fs(
382 struct radeon_llvm_context *radeon_bld,
383 unsigned input_index,
384 const struct tgsi_full_declaration *decl)
385 {
386 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
387 struct si_shader_context *si_shader_ctx =
388 si_shader_context(&radeon_bld->soa.bld_base);
389 struct si_shader *shader = si_shader_ctx->shader;
390 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
391 struct gallivm_state *gallivm = base->gallivm;
392 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
393 LLVMValueRef main_fn = radeon_bld->main_fn;
394
395 LLVMValueRef interp_param;
396 const char * intr_name;
397
398 /* This value is:
399 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
400 * quad begins a new primitive. Bit 0 always needs
401 * to be unset)
402 * [32:16] ParamOffset
403 *
404 */
405 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
406 LLVMValueRef attr_number;
407
408 unsigned chan;
409
410 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
411 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
412 unsigned soa_index =
413 radeon_llvm_reg_index_soa(input_index, chan);
414 radeon_bld->inputs[soa_index] =
415 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
416
417 if (chan == 3)
418 /* RCP for fragcoord.w */
419 radeon_bld->inputs[soa_index] =
420 LLVMBuildFDiv(gallivm->builder,
421 lp_build_const_float(gallivm, 1.0f),
422 radeon_bld->inputs[soa_index],
423 "");
424 }
425 return;
426 }
427
428 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
429 LLVMValueRef face, is_face_positive;
430
431 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
432
433 is_face_positive = LLVMBuildFCmp(gallivm->builder,
434 LLVMRealUGT, face,
435 lp_build_const_float(gallivm, 0.0f),
436 "");
437
438 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
439 LLVMBuildSelect(gallivm->builder,
440 is_face_positive,
441 lp_build_const_float(gallivm, 1.0f),
442 lp_build_const_float(gallivm, 0.0f),
443 "");
444 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
445 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
446 lp_build_const_float(gallivm, 0.0f);
447 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
448 lp_build_const_float(gallivm, 1.0f);
449
450 return;
451 }
452
453 shader->ps_input_param_offset[input_index] = shader->nparam++;
454 attr_number = lp_build_const_int32(gallivm,
455 shader->ps_input_param_offset[input_index]);
456
457 switch (decl->Interp.Interpolate) {
458 case TGSI_INTERPOLATE_CONSTANT:
459 interp_param = 0;
460 break;
461 case TGSI_INTERPOLATE_LINEAR:
462 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
463 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
464 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
465 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
466 else
467 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
468 break;
469 case TGSI_INTERPOLATE_COLOR:
470 if (si_shader_ctx->shader->key.ps.flatshade) {
471 interp_param = 0;
472 break;
473 }
474 /* fall through to perspective */
475 case TGSI_INTERPOLATE_PERSPECTIVE:
476 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
477 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
478 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
479 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
480 else
481 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
482 break;
483 default:
484 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
485 return;
486 }
487
488 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
489
490 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
491 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
492 si_shader_ctx->shader->key.ps.color_two_side) {
493 LLVMValueRef args[4];
494 LLVMValueRef face, is_face_positive;
495 LLVMValueRef back_attr_number =
496 lp_build_const_int32(gallivm,
497 shader->ps_input_param_offset[input_index] + 1);
498
499 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
500
501 is_face_positive = LLVMBuildFCmp(gallivm->builder,
502 LLVMRealUGT, face,
503 lp_build_const_float(gallivm, 0.0f),
504 "");
505
506 args[2] = params;
507 args[3] = interp_param;
508 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
509 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
510 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
511 LLVMValueRef front, back;
512
513 args[0] = llvm_chan;
514 args[1] = attr_number;
515 front = build_intrinsic(gallivm->builder, intr_name,
516 input_type, args, args[3] ? 4 : 3,
517 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
518
519 args[1] = back_attr_number;
520 back = build_intrinsic(gallivm->builder, intr_name,
521 input_type, args, args[3] ? 4 : 3,
522 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
523
524 radeon_bld->inputs[soa_index] =
525 LLVMBuildSelect(gallivm->builder,
526 is_face_positive,
527 front,
528 back,
529 "");
530 }
531
532 shader->nparam++;
533 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
534 LLVMValueRef args[4];
535
536 args[0] = uint->zero;
537 args[1] = attr_number;
538 args[2] = params;
539 args[3] = interp_param;
540 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
541 build_intrinsic(gallivm->builder, intr_name,
542 input_type, args, args[3] ? 4 : 3,
543 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
544 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
545 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
546 lp_build_const_float(gallivm, 0.0f);
547 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
548 lp_build_const_float(gallivm, 1.0f);
549 } else {
550 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
551 LLVMValueRef args[4];
552 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
553 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
554 args[0] = llvm_chan;
555 args[1] = attr_number;
556 args[2] = params;
557 args[3] = interp_param;
558 radeon_bld->inputs[soa_index] =
559 build_intrinsic(gallivm->builder, intr_name,
560 input_type, args, args[3] ? 4 : 3,
561 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
562 }
563 }
564 }
565
566 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
567 {
568 struct gallivm_state *gallivm = &radeon_bld->gallivm;
569 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
570 SI_PARAM_ANCILLARY);
571 value = LLVMBuildLShr(gallivm->builder, value,
572 lp_build_const_int32(gallivm, 8), "");
573 value = LLVMBuildAnd(gallivm->builder, value,
574 lp_build_const_int32(gallivm, 0xf), "");
575 return value;
576 }
577
578 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
579 LLVMValueRef offset, LLVMTypeRef return_type)
580 {
581 LLVMValueRef args[2] = {resource, offset};
582
583 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
584 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
585 }
586
587 static void declare_system_value(
588 struct radeon_llvm_context * radeon_bld,
589 unsigned index,
590 const struct tgsi_full_declaration *decl)
591 {
592 struct si_shader_context *si_shader_ctx =
593 si_shader_context(&radeon_bld->soa.bld_base);
594 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
595 struct gallivm_state *gallivm = &radeon_bld->gallivm;
596 LLVMValueRef value = 0;
597
598 switch (decl->Semantic.Name) {
599 case TGSI_SEMANTIC_INSTANCEID:
600 value = LLVMGetParam(radeon_bld->main_fn,
601 si_shader_ctx->param_instance_id);
602 break;
603
604 case TGSI_SEMANTIC_VERTEXID:
605 value = LLVMGetParam(radeon_bld->main_fn,
606 si_shader_ctx->param_vertex_id);
607 break;
608
609 case TGSI_SEMANTIC_SAMPLEID:
610 value = get_sample_id(radeon_bld);
611 break;
612
613 case TGSI_SEMANTIC_SAMPLEPOS:
614 {
615 LLVMBuilderRef builder = gallivm->builder;
616 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
617 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
618 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
619
620 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
621 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
622 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
623
624 LLVMValueRef pos[4] = {
625 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
626 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
627 lp_build_const_float(gallivm, 0),
628 lp_build_const_float(gallivm, 0)
629 };
630 value = lp_build_gather_values(gallivm, pos, 4);
631 break;
632 }
633
634 default:
635 assert(!"unknown system value");
636 return;
637 }
638
639 radeon_bld->system_values[index] = value;
640 }
641
642 static LLVMValueRef fetch_constant(
643 struct lp_build_tgsi_context * bld_base,
644 const struct tgsi_full_src_register *reg,
645 enum tgsi_opcode_type type,
646 unsigned swizzle)
647 {
648 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
649 struct lp_build_context * base = &bld_base->base;
650 const struct tgsi_ind_register *ireg = &reg->Indirect;
651 unsigned buf, idx;
652
653 LLVMValueRef addr;
654 LLVMValueRef result;
655
656 if (swizzle == LP_CHAN_ALL) {
657 unsigned chan;
658 LLVMValueRef values[4];
659 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
660 values[chan] = fetch_constant(bld_base, reg, type, chan);
661
662 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
663 }
664
665 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
666 idx = reg->Register.Index * 4 + swizzle;
667
668 if (!reg->Register.Indirect)
669 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
670
671 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
672 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
673 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
674 addr = lp_build_add(&bld_base->uint_bld, addr,
675 lp_build_const_int32(base->gallivm, idx * 4));
676
677 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
678 addr, base->elem_type);
679
680 return bitcast(bld_base, type, result);
681 }
682
683 /* Initialize arguments for the shader export intrinsic */
684 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
685 LLVMValueRef *values,
686 unsigned target,
687 LLVMValueRef *args)
688 {
689 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
690 struct lp_build_context *uint =
691 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
692 struct lp_build_context *base = &bld_base->base;
693 unsigned compressed = 0;
694 unsigned chan;
695
696 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
697 int cbuf = target - V_008DFC_SQ_EXP_MRT;
698
699 if (cbuf >= 0 && cbuf < 8) {
700 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
701
702 if (compressed)
703 si_shader_ctx->shader->spi_shader_col_format |=
704 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
705 else
706 si_shader_ctx->shader->spi_shader_col_format |=
707 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
708
709 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
710 }
711 }
712
713 if (compressed) {
714 /* Pixel shader needs to pack output values before export */
715 for (chan = 0; chan < 2; chan++ ) {
716 args[0] = values[2 * chan];
717 args[1] = values[2 * chan + 1];
718 args[chan + 5] =
719 build_intrinsic(base->gallivm->builder,
720 "llvm.SI.packf16",
721 LLVMInt32TypeInContext(base->gallivm->context),
722 args, 2,
723 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
724 args[chan + 7] = args[chan + 5] =
725 LLVMBuildBitCast(base->gallivm->builder,
726 args[chan + 5],
727 LLVMFloatTypeInContext(base->gallivm->context),
728 "");
729 }
730
731 /* Set COMPR flag */
732 args[4] = uint->one;
733 } else {
734 for (chan = 0; chan < 4; chan++ )
735 /* +5 because the first output value will be
736 * the 6th argument to the intrinsic. */
737 args[chan + 5] = values[chan];
738
739 /* Clear COMPR flag */
740 args[4] = uint->zero;
741 }
742
743 /* XXX: This controls which components of the output
744 * registers actually get exported. (e.g bit 0 means export
745 * X component, bit 1 means export Y component, etc.) I'm
746 * hard coding this to 0xf for now. In the future, we might
747 * want to do something else. */
748 args[0] = lp_build_const_int32(base->gallivm, 0xf);
749
750 /* Specify whether the EXEC mask represents the valid mask */
751 args[1] = uint->zero;
752
753 /* Specify whether this is the last export */
754 args[2] = uint->zero;
755
756 /* Specify the target we are exporting */
757 args[3] = lp_build_const_int32(base->gallivm, target);
758
759 /* XXX: We probably need to keep track of the output
760 * values, so we know what we are passing to the next
761 * stage. */
762 }
763
764 /* Load from output pointers and initialize arguments for the shader export intrinsic */
765 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
766 LLVMValueRef *out_ptr,
767 unsigned target,
768 LLVMValueRef *args)
769 {
770 struct gallivm_state *gallivm = bld_base->base.gallivm;
771 LLVMValueRef values[4];
772 int i;
773
774 for (i = 0; i < 4; i++)
775 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
776
777 si_llvm_init_export_args(bld_base, values, target, args);
778 }
779
780 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
781 LLVMValueRef *out_ptr)
782 {
783 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
784 struct gallivm_state *gallivm = bld_base->base.gallivm;
785
786 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
787 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
788 SI_PARAM_ALPHA_REF);
789
790 LLVMValueRef alpha_pass =
791 lp_build_cmp(&bld_base->base,
792 si_shader_ctx->shader->key.ps.alpha_func,
793 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
794 alpha_ref);
795 LLVMValueRef arg =
796 lp_build_select(&bld_base->base,
797 alpha_pass,
798 lp_build_const_float(gallivm, 1.0f),
799 lp_build_const_float(gallivm, -1.0f));
800
801 build_intrinsic(gallivm->builder,
802 "llvm.AMDGPU.kill",
803 LLVMVoidTypeInContext(gallivm->context),
804 &arg, 1, 0);
805 } else {
806 build_intrinsic(gallivm->builder,
807 "llvm.AMDGPU.kilp",
808 LLVMVoidTypeInContext(gallivm->context),
809 NULL, 0, 0);
810 }
811
812 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
813 }
814
815 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
816 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
817 {
818 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
819 struct si_shader *shader = si_shader_ctx->shader;
820 struct lp_build_context *base = &bld_base->base;
821 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
822 unsigned reg_index;
823 unsigned chan;
824 unsigned const_chan;
825 LLVMValueRef base_elt;
826 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
827 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
828 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
829
830 for (reg_index = 0; reg_index < 2; reg_index ++) {
831 LLVMValueRef *args = pos[2 + reg_index];
832
833 shader->clip_dist_write |= 0xf << (4 * reg_index);
834
835 args[5] =
836 args[6] =
837 args[7] =
838 args[8] = lp_build_const_float(base->gallivm, 0.0f);
839
840 /* Compute dot products of position and user clip plane vectors */
841 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
842 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
843 args[1] = lp_build_const_int32(base->gallivm,
844 ((reg_index * 4 + chan) * 4 +
845 const_chan) * 4);
846 base_elt = load_const(base->gallivm->builder, const_resource,
847 args[1], base->elem_type);
848 args[5 + chan] =
849 lp_build_add(base, args[5 + chan],
850 lp_build_mul(base, base_elt,
851 out_elts[const_chan]));
852 }
853 }
854
855 args[0] = lp_build_const_int32(base->gallivm, 0xf);
856 args[1] = uint->zero;
857 args[2] = uint->zero;
858 args[3] = lp_build_const_int32(base->gallivm,
859 V_008DFC_SQ_EXP_POS + 2 + reg_index);
860 args[4] = uint->zero;
861 }
862 }
863
864 static void si_dump_streamout(struct pipe_stream_output_info *so)
865 {
866 unsigned i;
867
868 if (so->num_outputs)
869 fprintf(stderr, "STREAMOUT\n");
870
871 for (i = 0; i < so->num_outputs; i++) {
872 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
873 so->output[i].start_component;
874 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
875 i, so->output[i].output_buffer,
876 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
877 so->output[i].register_index,
878 mask & 1 ? "x" : "",
879 mask & 2 ? "y" : "",
880 mask & 4 ? "z" : "",
881 mask & 8 ? "w" : "");
882 }
883 }
884
885 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
886 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
887 * or v4i32 (num_channels=3,4). */
888 static void build_tbuffer_store(struct si_shader_context *shader,
889 LLVMValueRef rsrc,
890 LLVMValueRef vdata,
891 unsigned num_channels,
892 LLVMValueRef vaddr,
893 LLVMValueRef soffset,
894 unsigned inst_offset,
895 unsigned dfmt,
896 unsigned nfmt,
897 unsigned offen,
898 unsigned idxen,
899 unsigned glc,
900 unsigned slc,
901 unsigned tfe)
902 {
903 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
904 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
905 LLVMValueRef args[] = {
906 rsrc,
907 vdata,
908 LLVMConstInt(i32, num_channels, 0),
909 vaddr,
910 soffset,
911 LLVMConstInt(i32, inst_offset, 0),
912 LLVMConstInt(i32, dfmt, 0),
913 LLVMConstInt(i32, nfmt, 0),
914 LLVMConstInt(i32, offen, 0),
915 LLVMConstInt(i32, idxen, 0),
916 LLVMConstInt(i32, glc, 0),
917 LLVMConstInt(i32, slc, 0),
918 LLVMConstInt(i32, tfe, 0)
919 };
920
921 /* The instruction offset field has 12 bits */
922 assert(offen || inst_offset < (1 << 12));
923
924 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
925 unsigned func = CLAMP(num_channels, 1, 3) - 1;
926 const char *types[] = {"i32", "v2i32", "v4i32"};
927 char name[256];
928 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
929
930 lp_build_intrinsic(gallivm->builder, name,
931 LLVMVoidTypeInContext(gallivm->context),
932 args, Elements(args));
933 }
934
935 static void build_streamout_store(struct si_shader_context *shader,
936 LLVMValueRef rsrc,
937 LLVMValueRef vdata,
938 unsigned num_channels,
939 LLVMValueRef vaddr,
940 LLVMValueRef soffset,
941 unsigned inst_offset)
942 {
943 static unsigned dfmt[] = {
944 V_008F0C_BUF_DATA_FORMAT_32,
945 V_008F0C_BUF_DATA_FORMAT_32_32,
946 V_008F0C_BUF_DATA_FORMAT_32_32_32,
947 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
948 };
949 assert(num_channels >= 1 && num_channels <= 4);
950
951 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
952 inst_offset, dfmt[num_channels-1],
953 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
954 }
955
956 /* On SI, the vertex shader is responsible for writing streamout data
957 * to buffers. */
958 static void si_llvm_emit_streamout(struct si_shader_context *shader,
959 struct si_shader_output_values *outputs,
960 unsigned noutput)
961 {
962 struct pipe_stream_output_info *so = &shader->shader->selector->so;
963 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
964 LLVMBuilderRef builder = gallivm->builder;
965 int i, j;
966 struct lp_build_if_state if_ctx;
967
968 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
969
970 LLVMValueRef so_param =
971 LLVMGetParam(shader->radeon_bld.main_fn,
972 shader->param_streamout_config);
973
974 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
975 LLVMValueRef so_vtx_count =
976 LLVMBuildAnd(builder,
977 LLVMBuildLShr(builder, so_param,
978 LLVMConstInt(i32, 16, 0), ""),
979 LLVMConstInt(i32, 127, 0), "");
980
981 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
982 NULL, 0, LLVMReadNoneAttribute);
983
984 /* can_emit = tid < so_vtx_count; */
985 LLVMValueRef can_emit =
986 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
987
988 /* Emit the streamout code conditionally. This actually avoids
989 * out-of-bounds buffer access. The hw tells us via the SGPR
990 * (so_vtx_count) which threads are allowed to emit streamout data. */
991 lp_build_if(&if_ctx, gallivm, can_emit);
992 {
993 /* The buffer offset is computed as follows:
994 * ByteOffset = streamout_offset[buffer_id]*4 +
995 * (streamout_write_index + thread_id)*stride[buffer_id] +
996 * attrib_offset
997 */
998
999 LLVMValueRef so_write_index =
1000 LLVMGetParam(shader->radeon_bld.main_fn,
1001 shader->param_streamout_write_index);
1002
1003 /* Compute (streamout_write_index + thread_id). */
1004 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1005
1006 /* Compute the write offset for each enabled buffer. */
1007 LLVMValueRef so_write_offset[4] = {};
1008 for (i = 0; i < 4; i++) {
1009 if (!so->stride[i])
1010 continue;
1011
1012 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1013 shader->param_streamout_offset[i]);
1014 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1015
1016 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1017 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1018 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1019 }
1020
1021 /* Write streamout data. */
1022 for (i = 0; i < so->num_outputs; i++) {
1023 unsigned buf_idx = so->output[i].output_buffer;
1024 unsigned reg = so->output[i].register_index;
1025 unsigned start = so->output[i].start_component;
1026 unsigned num_comps = so->output[i].num_components;
1027 LLVMValueRef out[4];
1028
1029 assert(num_comps && num_comps <= 4);
1030 if (!num_comps || num_comps > 4)
1031 continue;
1032
1033 if (reg >= noutput)
1034 continue;
1035
1036 /* Load the output as int. */
1037 for (j = 0; j < num_comps; j++) {
1038 out[j] = LLVMBuildBitCast(builder,
1039 outputs[reg].values[start+j],
1040 i32, "");
1041 }
1042
1043 /* Pack the output. */
1044 LLVMValueRef vdata = NULL;
1045
1046 switch (num_comps) {
1047 case 1: /* as i32 */
1048 vdata = out[0];
1049 break;
1050 case 2: /* as v2i32 */
1051 case 3: /* as v4i32 (aligned to 4) */
1052 case 4: /* as v4i32 */
1053 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1054 for (j = 0; j < num_comps; j++) {
1055 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1056 LLVMConstInt(i32, j, 0), "");
1057 }
1058 break;
1059 }
1060
1061 build_streamout_store(shader, shader->so_buffers[buf_idx],
1062 vdata, num_comps,
1063 so_write_offset[buf_idx],
1064 LLVMConstInt(i32, 0, 0),
1065 so->output[i].dst_offset*4);
1066 }
1067 }
1068 lp_build_endif(&if_ctx);
1069 }
1070
1071
1072 /* Generate export instructions for hardware VS shader stage */
1073 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1074 struct si_shader_output_values *outputs,
1075 unsigned noutput)
1076 {
1077 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1078 struct si_shader * shader = si_shader_ctx->shader;
1079 struct lp_build_context * base = &bld_base->base;
1080 struct lp_build_context * uint =
1081 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1082 LLVMValueRef args[9];
1083 LLVMValueRef pos_args[4][9] = { { 0 } };
1084 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1085 unsigned semantic_name, semantic_index;
1086 unsigned target;
1087 unsigned param_count = 0;
1088 unsigned pos_idx;
1089 int i;
1090
1091 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1092 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1093 }
1094
1095 for (i = 0; i < noutput; i++) {
1096 semantic_name = outputs[i].name;
1097 semantic_index = outputs[i].sid;
1098
1099 handle_semantic:
1100 /* Select the correct target */
1101 switch(semantic_name) {
1102 case TGSI_SEMANTIC_PSIZE:
1103 shader->vs_out_misc_write = true;
1104 shader->vs_out_point_size = true;
1105 psize_value = outputs[i].values[0];
1106 continue;
1107 case TGSI_SEMANTIC_EDGEFLAG:
1108 shader->vs_out_misc_write = true;
1109 shader->vs_out_edgeflag = true;
1110 edgeflag_value = outputs[i].values[0];
1111 continue;
1112 case TGSI_SEMANTIC_LAYER:
1113 shader->vs_out_misc_write = true;
1114 shader->vs_out_layer = true;
1115 layer_value = outputs[i].values[0];
1116 continue;
1117 case TGSI_SEMANTIC_POSITION:
1118 target = V_008DFC_SQ_EXP_POS;
1119 break;
1120 case TGSI_SEMANTIC_COLOR:
1121 case TGSI_SEMANTIC_BCOLOR:
1122 target = V_008DFC_SQ_EXP_PARAM + param_count;
1123 shader->vs_output_param_offset[i] = param_count;
1124 param_count++;
1125 break;
1126 case TGSI_SEMANTIC_CLIPDIST:
1127 shader->clip_dist_write |=
1128 0xf << (semantic_index * 4);
1129 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1130 break;
1131 case TGSI_SEMANTIC_CLIPVERTEX:
1132 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1133 continue;
1134 case TGSI_SEMANTIC_PRIMID:
1135 case TGSI_SEMANTIC_FOG:
1136 case TGSI_SEMANTIC_GENERIC:
1137 target = V_008DFC_SQ_EXP_PARAM + param_count;
1138 shader->vs_output_param_offset[i] = param_count;
1139 param_count++;
1140 break;
1141 default:
1142 target = 0;
1143 fprintf(stderr,
1144 "Warning: SI unhandled vs output type:%d\n",
1145 semantic_name);
1146 }
1147
1148 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1149
1150 if (target >= V_008DFC_SQ_EXP_POS &&
1151 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1152 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1153 args, sizeof(args));
1154 } else {
1155 lp_build_intrinsic(base->gallivm->builder,
1156 "llvm.SI.export",
1157 LLVMVoidTypeInContext(base->gallivm->context),
1158 args, 9);
1159 }
1160
1161 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1162 semantic_name = TGSI_SEMANTIC_GENERIC;
1163 goto handle_semantic;
1164 }
1165 }
1166
1167 /* We need to add the position output manually if it's missing. */
1168 if (!pos_args[0][0]) {
1169 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1170 pos_args[0][1] = uint->zero; /* EXEC mask */
1171 pos_args[0][2] = uint->zero; /* last export? */
1172 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1173 pos_args[0][4] = uint->zero; /* COMPR flag */
1174 pos_args[0][5] = base->zero; /* X */
1175 pos_args[0][6] = base->zero; /* Y */
1176 pos_args[0][7] = base->zero; /* Z */
1177 pos_args[0][8] = base->one; /* W */
1178 }
1179
1180 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1181 if (shader->vs_out_misc_write) {
1182 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1183 shader->vs_out_point_size |
1184 (shader->vs_out_edgeflag << 1) |
1185 (shader->vs_out_layer << 2));
1186 pos_args[1][1] = uint->zero; /* EXEC mask */
1187 pos_args[1][2] = uint->zero; /* last export? */
1188 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1189 pos_args[1][4] = uint->zero; /* COMPR flag */
1190 pos_args[1][5] = base->zero; /* X */
1191 pos_args[1][6] = base->zero; /* Y */
1192 pos_args[1][7] = base->zero; /* Z */
1193 pos_args[1][8] = base->zero; /* W */
1194
1195 if (shader->vs_out_point_size)
1196 pos_args[1][5] = psize_value;
1197
1198 if (shader->vs_out_edgeflag) {
1199 /* The output is a float, but the hw expects an integer
1200 * with the first bit containing the edge flag. */
1201 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1202 edgeflag_value,
1203 bld_base->uint_bld.elem_type, "");
1204 edgeflag_value = lp_build_min(&bld_base->int_bld,
1205 edgeflag_value,
1206 bld_base->int_bld.one);
1207
1208 /* The LLVM intrinsic expects a float. */
1209 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1210 edgeflag_value,
1211 base->elem_type, "");
1212 }
1213
1214 if (shader->vs_out_layer)
1215 pos_args[1][7] = layer_value;
1216 }
1217
1218 for (i = 0; i < 4; i++)
1219 if (pos_args[i][0])
1220 shader->nr_pos_exports++;
1221
1222 pos_idx = 0;
1223 for (i = 0; i < 4; i++) {
1224 if (!pos_args[i][0])
1225 continue;
1226
1227 /* Specify the target we are exporting */
1228 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1229
1230 if (pos_idx == shader->nr_pos_exports)
1231 /* Specify that this is the last export */
1232 pos_args[i][2] = uint->one;
1233
1234 lp_build_intrinsic(base->gallivm->builder,
1235 "llvm.SI.export",
1236 LLVMVoidTypeInContext(base->gallivm->context),
1237 pos_args[i], 9);
1238 }
1239 }
1240
1241 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1242 {
1243 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1244 struct gallivm_state *gallivm = bld_base->base.gallivm;
1245 struct si_shader *es = si_shader_ctx->shader;
1246 struct tgsi_shader_info *info = &es->selector->info;
1247 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1248 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1249 SI_PARAM_ES2GS_OFFSET);
1250 LLVMValueRef t_list_ptr;
1251 LLVMValueRef t_list;
1252 unsigned chan;
1253 int i;
1254
1255 /* Load the ESGS ring resource descriptor */
1256 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1257 SI_PARAM_RW_BUFFERS);
1258 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1259 lp_build_const_int32(gallivm, SI_RING_ESGS));
1260
1261 for (i = 0; i < info->num_outputs; i++) {
1262 LLVMValueRef *out_ptr =
1263 si_shader_ctx->radeon_bld.soa.outputs[i];
1264 int param_index = get_param_index(info->output_semantic_name[i],
1265 info->output_semantic_index[i],
1266 es->key.vs.gs_used_inputs);
1267
1268 if (param_index < 0)
1269 continue;
1270
1271 for (chan = 0; chan < 4; chan++) {
1272 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1273 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1274
1275 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1276 LLVMGetUndef(i32), soffset,
1277 (4 * param_index + chan) * 4,
1278 V_008F0C_BUF_DATA_FORMAT_32,
1279 V_008F0C_BUF_NUM_FORMAT_UINT,
1280 0, 0, 1, 1, 0);
1281 }
1282 }
1283 }
1284
1285 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1286 {
1287 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1288 struct gallivm_state *gallivm = bld_base->base.gallivm;
1289 LLVMValueRef args[2];
1290
1291 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1292 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1293 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1294 LLVMVoidTypeInContext(gallivm->context), args, 2,
1295 LLVMNoUnwindAttribute);
1296 }
1297
1298 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1299 {
1300 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1301 struct gallivm_state *gallivm = bld_base->base.gallivm;
1302 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1303 struct si_shader_output_values *outputs = NULL;
1304 int i,j;
1305
1306 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1307
1308 for (i = 0; i < info->num_outputs; i++) {
1309 outputs[i].name = info->output_semantic_name[i];
1310 outputs[i].sid = info->output_semantic_index[i];
1311
1312 for (j = 0; j < 4; j++)
1313 outputs[i].values[j] =
1314 LLVMBuildLoad(gallivm->builder,
1315 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1316 "");
1317 }
1318
1319 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1320 FREE(outputs);
1321 }
1322
1323 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1324 {
1325 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1326 struct si_shader * shader = si_shader_ctx->shader;
1327 struct lp_build_context * base = &bld_base->base;
1328 struct lp_build_context * uint =
1329 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1330 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1331 LLVMValueRef args[9];
1332 LLVMValueRef last_args[9] = { 0 };
1333 unsigned semantic_name;
1334 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1335
1336 while (!tgsi_parse_end_of_tokens(parse)) {
1337 struct tgsi_full_declaration *d =
1338 &parse->FullToken.FullDeclaration;
1339 unsigned target;
1340 unsigned index;
1341
1342 tgsi_parse_token(parse);
1343
1344 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1345 continue;
1346
1347 semantic_name = d->Semantic.Name;
1348 for (index = d->Range.First; index <= d->Range.Last; index++) {
1349 /* Select the correct target */
1350 switch(semantic_name) {
1351 case TGSI_SEMANTIC_POSITION:
1352 depth_index = index;
1353 continue;
1354 case TGSI_SEMANTIC_STENCIL:
1355 stencil_index = index;
1356 continue;
1357 case TGSI_SEMANTIC_SAMPLEMASK:
1358 samplemask_index = index;
1359 continue;
1360 case TGSI_SEMANTIC_COLOR:
1361 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1362 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1363 LLVMBuildStore(bld_base->base.gallivm->builder,
1364 bld_base->base.one,
1365 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1366
1367 if (d->Semantic.Index == 0 &&
1368 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1369 si_alpha_test(bld_base,
1370 si_shader_ctx->radeon_bld.soa.outputs[index]);
1371 break;
1372 default:
1373 target = 0;
1374 fprintf(stderr,
1375 "Warning: SI unhandled fs output type:%d\n",
1376 semantic_name);
1377 }
1378
1379 si_llvm_init_export_args_load(bld_base,
1380 si_shader_ctx->radeon_bld.soa.outputs[index],
1381 target, args);
1382
1383 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1384 /* If there is an export instruction waiting to be emitted, do so now. */
1385 if (last_args[0]) {
1386 lp_build_intrinsic(base->gallivm->builder,
1387 "llvm.SI.export",
1388 LLVMVoidTypeInContext(base->gallivm->context),
1389 last_args, 9);
1390 }
1391
1392 /* This instruction will be emitted at the end of the shader. */
1393 memcpy(last_args, args, sizeof(args));
1394
1395 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1396 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1397 d->Semantic.Index == 0 &&
1398 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1399 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1400 si_llvm_init_export_args_load(bld_base,
1401 si_shader_ctx->radeon_bld.soa.outputs[index],
1402 V_008DFC_SQ_EXP_MRT + c, args);
1403 lp_build_intrinsic(base->gallivm->builder,
1404 "llvm.SI.export",
1405 LLVMVoidTypeInContext(base->gallivm->context),
1406 args, 9);
1407 }
1408 }
1409 } else {
1410 lp_build_intrinsic(base->gallivm->builder,
1411 "llvm.SI.export",
1412 LLVMVoidTypeInContext(base->gallivm->context),
1413 args, 9);
1414 }
1415 }
1416 }
1417
1418 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1419 LLVMValueRef out_ptr;
1420 unsigned mask = 0;
1421
1422 /* Specify the target we are exporting */
1423 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1424
1425 args[5] = base->zero; /* R, depth */
1426 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1427 args[7] = base->zero; /* B, sample mask */
1428 args[8] = base->zero; /* A, alpha to mask */
1429
1430 if (depth_index >= 0) {
1431 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1432 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1433 mask |= 0x1;
1434 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1435 }
1436
1437 if (stencil_index >= 0) {
1438 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1439 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1440 /* Only setting the stencil component bit (0x2) here
1441 * breaks some stencil piglit tests
1442 */
1443 mask |= 0x3;
1444 si_shader_ctx->shader->db_shader_control |=
1445 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1446 }
1447
1448 if (samplemask_index >= 0) {
1449 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1450 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1451 mask |= 0xf; /* Set all components. */
1452 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1453 }
1454
1455 if (samplemask_index >= 0)
1456 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1457 else if (stencil_index >= 0)
1458 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1459 else
1460 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1461
1462 /* Specify which components to enable */
1463 args[0] = lp_build_const_int32(base->gallivm, mask);
1464
1465 args[1] =
1466 args[2] =
1467 args[4] = uint->zero;
1468
1469 if (last_args[0])
1470 lp_build_intrinsic(base->gallivm->builder,
1471 "llvm.SI.export",
1472 LLVMVoidTypeInContext(base->gallivm->context),
1473 args, 9);
1474 else
1475 memcpy(last_args, args, sizeof(args));
1476 }
1477
1478 if (!last_args[0]) {
1479 /* Specify which components to enable */
1480 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1481
1482 /* Specify the target we are exporting */
1483 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1484
1485 /* Set COMPR flag to zero to export data as 32-bit */
1486 last_args[4] = uint->zero;
1487
1488 /* dummy bits */
1489 last_args[5]= uint->zero;
1490 last_args[6]= uint->zero;
1491 last_args[7]= uint->zero;
1492 last_args[8]= uint->zero;
1493 }
1494
1495 /* Specify whether the EXEC mask represents the valid mask */
1496 last_args[1] = uint->one;
1497
1498 /* Specify that this is the last export */
1499 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1500
1501 lp_build_intrinsic(base->gallivm->builder,
1502 "llvm.SI.export",
1503 LLVMVoidTypeInContext(base->gallivm->context),
1504 last_args, 9);
1505 }
1506
1507 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1508 struct lp_build_tgsi_context * bld_base,
1509 struct lp_build_emit_data * emit_data);
1510
1511 static bool tgsi_is_shadow_sampler(unsigned target)
1512 {
1513 return target == TGSI_TEXTURE_SHADOW1D ||
1514 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1515 target == TGSI_TEXTURE_SHADOW2D ||
1516 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1517 target == TGSI_TEXTURE_SHADOWCUBE ||
1518 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1519 target == TGSI_TEXTURE_SHADOWRECT;
1520 }
1521
1522 static const struct lp_build_tgsi_action tex_action;
1523
1524 static void tex_fetch_args(
1525 struct lp_build_tgsi_context * bld_base,
1526 struct lp_build_emit_data * emit_data)
1527 {
1528 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1529 struct gallivm_state *gallivm = bld_base->base.gallivm;
1530 const struct tgsi_full_instruction * inst = emit_data->inst;
1531 unsigned opcode = inst->Instruction.Opcode;
1532 unsigned target = inst->Texture.Texture;
1533 LLVMValueRef coords[4];
1534 LLVMValueRef address[16];
1535 int ref_pos;
1536 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1537 unsigned count = 0;
1538 unsigned chan;
1539 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1540 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1541 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1542
1543 if (target == TGSI_TEXTURE_BUFFER) {
1544 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1545 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1546 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1547 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1548
1549 /* Bitcast and truncate v8i32 to v16i8. */
1550 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1551 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1552 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1553 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1554
1555 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1556 emit_data->args[0] = res;
1557 emit_data->args[1] = bld_base->uint_bld.zero;
1558 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1559 emit_data->arg_count = 3;
1560 return;
1561 }
1562
1563 /* Fetch and project texture coordinates */
1564 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1565 for (chan = 0; chan < 3; chan++ ) {
1566 coords[chan] = lp_build_emit_fetch(bld_base,
1567 emit_data->inst, 0,
1568 chan);
1569 if (opcode == TGSI_OPCODE_TXP)
1570 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1571 TGSI_OPCODE_DIV,
1572 coords[chan],
1573 coords[3]);
1574 }
1575
1576 if (opcode == TGSI_OPCODE_TXP)
1577 coords[3] = bld_base->base.one;
1578
1579 /* Pack offsets. */
1580 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1581 /* The offsets are six-bit signed integers packed like this:
1582 * X=[5:0], Y=[13:8], and Z=[21:16].
1583 */
1584 LLVMValueRef offset[3], pack;
1585
1586 assert(inst->Texture.NumOffsets == 1);
1587
1588 for (chan = 0; chan < 3; chan++) {
1589 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1590 emit_data->inst, 0, chan);
1591 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1592 lp_build_const_int32(gallivm, 0x3f), "");
1593 if (chan)
1594 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1595 lp_build_const_int32(gallivm, chan*8), "");
1596 }
1597
1598 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1599 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1600 address[count++] = pack;
1601 }
1602
1603 /* Pack LOD bias value */
1604 if (opcode == TGSI_OPCODE_TXB)
1605 address[count++] = coords[3];
1606 if (opcode == TGSI_OPCODE_TXB2)
1607 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1608
1609 /* Pack depth comparison value */
1610 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1611 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1612 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1613 } else {
1614 assert(ref_pos >= 0);
1615 address[count++] = coords[ref_pos];
1616 }
1617 }
1618
1619 if (target == TGSI_TEXTURE_CUBE ||
1620 target == TGSI_TEXTURE_CUBE_ARRAY ||
1621 target == TGSI_TEXTURE_SHADOWCUBE ||
1622 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1623 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1624
1625 /* Pack user derivatives */
1626 if (opcode == TGSI_OPCODE_TXD) {
1627 int num_deriv_channels, param;
1628
1629 switch (target) {
1630 case TGSI_TEXTURE_3D:
1631 num_deriv_channels = 3;
1632 break;
1633 case TGSI_TEXTURE_2D:
1634 case TGSI_TEXTURE_SHADOW2D:
1635 case TGSI_TEXTURE_RECT:
1636 case TGSI_TEXTURE_SHADOWRECT:
1637 case TGSI_TEXTURE_2D_ARRAY:
1638 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1639 case TGSI_TEXTURE_CUBE:
1640 case TGSI_TEXTURE_SHADOWCUBE:
1641 case TGSI_TEXTURE_CUBE_ARRAY:
1642 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1643 num_deriv_channels = 2;
1644 break;
1645 case TGSI_TEXTURE_1D:
1646 case TGSI_TEXTURE_SHADOW1D:
1647 case TGSI_TEXTURE_1D_ARRAY:
1648 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1649 num_deriv_channels = 1;
1650 break;
1651 default:
1652 assert(0); /* no other targets are valid here */
1653 }
1654
1655 for (param = 1; param <= 2; param++)
1656 for (chan = 0; chan < num_deriv_channels; chan++)
1657 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1658 }
1659
1660 /* Pack texture coordinates */
1661 address[count++] = coords[0];
1662 if (num_coords > 1)
1663 address[count++] = coords[1];
1664 if (num_coords > 2)
1665 address[count++] = coords[2];
1666
1667 /* Pack LOD or sample index */
1668 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1669 address[count++] = coords[3];
1670 else if (opcode == TGSI_OPCODE_TXL2)
1671 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1672
1673 if (count > 16) {
1674 assert(!"Cannot handle more than 16 texture address parameters");
1675 count = 16;
1676 }
1677
1678 for (chan = 0; chan < count; chan++ ) {
1679 address[chan] = LLVMBuildBitCast(gallivm->builder,
1680 address[chan],
1681 LLVMInt32TypeInContext(gallivm->context),
1682 "");
1683 }
1684
1685 /* Adjust the sample index according to FMASK.
1686 *
1687 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1688 * which is the identity mapping. Each nibble says which physical sample
1689 * should be fetched to get that sample.
1690 *
1691 * For example, 0x11111100 means there are only 2 samples stored and
1692 * the second sample covers 3/4 of the pixel. When reading samples 0
1693 * and 1, return physical sample 0 (determined by the first two 0s
1694 * in FMASK), otherwise return physical sample 1.
1695 *
1696 * The sample index should be adjusted as follows:
1697 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1698 */
1699 if (target == TGSI_TEXTURE_2D_MSAA ||
1700 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1701 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1702 struct lp_build_emit_data txf_emit_data = *emit_data;
1703 LLVMValueRef txf_address[4];
1704 unsigned txf_count = count;
1705 struct tgsi_full_instruction inst = {};
1706
1707 memcpy(txf_address, address, sizeof(txf_address));
1708
1709 if (target == TGSI_TEXTURE_2D_MSAA) {
1710 txf_address[2] = bld_base->uint_bld.zero;
1711 }
1712 txf_address[3] = bld_base->uint_bld.zero;
1713
1714 /* Pad to a power-of-two size. */
1715 while (txf_count < util_next_power_of_two(txf_count))
1716 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1717
1718 /* Read FMASK using TXF. */
1719 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1720 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1721 txf_emit_data.inst = &inst;
1722 txf_emit_data.chan = 0;
1723 txf_emit_data.dst_type = LLVMVectorType(
1724 LLVMInt32TypeInContext(gallivm->context), 4);
1725 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1726 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1727 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1728 txf_emit_data.arg_count = 3;
1729
1730 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1731
1732 /* Initialize some constants. */
1733 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1734 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1735
1736 /* Apply the formula. */
1737 LLVMValueRef fmask =
1738 LLVMBuildExtractElement(gallivm->builder,
1739 txf_emit_data.output[0],
1740 uint_bld->zero, "");
1741
1742 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1743
1744 LLVMValueRef sample_index4 =
1745 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1746
1747 LLVMValueRef shifted_fmask =
1748 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1749
1750 LLVMValueRef final_sample =
1751 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1752
1753 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1754 * resource descriptor is 0 (invalid),
1755 */
1756 LLVMValueRef fmask_desc =
1757 LLVMBuildBitCast(gallivm->builder,
1758 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1759 LLVMVectorType(uint_bld->elem_type, 8), "");
1760
1761 LLVMValueRef fmask_word1 =
1762 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1763 uint_bld->one, "");
1764
1765 LLVMValueRef word1_is_nonzero =
1766 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1767 fmask_word1, uint_bld->zero, "");
1768
1769 /* Replace the MSAA sample index. */
1770 address[sample_chan] =
1771 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1772 final_sample, address[sample_chan], "");
1773 }
1774
1775 /* Resource */
1776 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1777
1778 if (opcode == TGSI_OPCODE_TXF) {
1779 /* add tex offsets */
1780 if (inst->Texture.NumOffsets) {
1781 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1782 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1783 const struct tgsi_texture_offset * off = inst->TexOffsets;
1784
1785 assert(inst->Texture.NumOffsets == 1);
1786
1787 switch (target) {
1788 case TGSI_TEXTURE_3D:
1789 address[2] = lp_build_add(uint_bld, address[2],
1790 bld->immediates[off->Index][off->SwizzleZ]);
1791 /* fall through */
1792 case TGSI_TEXTURE_2D:
1793 case TGSI_TEXTURE_SHADOW2D:
1794 case TGSI_TEXTURE_RECT:
1795 case TGSI_TEXTURE_SHADOWRECT:
1796 case TGSI_TEXTURE_2D_ARRAY:
1797 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1798 address[1] =
1799 lp_build_add(uint_bld, address[1],
1800 bld->immediates[off->Index][off->SwizzleY]);
1801 /* fall through */
1802 case TGSI_TEXTURE_1D:
1803 case TGSI_TEXTURE_SHADOW1D:
1804 case TGSI_TEXTURE_1D_ARRAY:
1805 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1806 address[0] =
1807 lp_build_add(uint_bld, address[0],
1808 bld->immediates[off->Index][off->SwizzleX]);
1809 break;
1810 /* texture offsets do not apply to other texture targets */
1811 }
1812 }
1813
1814 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1815 emit_data->arg_count = 3;
1816
1817 emit_data->dst_type = LLVMVectorType(
1818 LLVMInt32TypeInContext(gallivm->context),
1819 4);
1820 } else if (opcode == TGSI_OPCODE_TG4 ||
1821 opcode == TGSI_OPCODE_LODQ ||
1822 has_offset) {
1823 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1824 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1825 target == TGSI_TEXTURE_2D_ARRAY ||
1826 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1827 target == TGSI_TEXTURE_CUBE_ARRAY ||
1828 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1829 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1830 unsigned dmask = 0xf;
1831
1832 if (opcode == TGSI_OPCODE_TG4) {
1833 unsigned gather_comp = 0;
1834
1835 /* DMASK was repurposed for GATHER4. 4 components are always
1836 * returned and DMASK works like a swizzle - it selects
1837 * the component to fetch. The only valid DMASK values are
1838 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1839 * (red,red,red,red) etc.) The ISA document doesn't mention
1840 * this.
1841 */
1842
1843 /* Get the component index from src1.x for Gather4. */
1844 if (!tgsi_is_shadow_sampler(target)) {
1845 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1846 LLVMValueRef comp_imm;
1847 struct tgsi_src_register src1 = inst->Src[1].Register;
1848
1849 assert(src1.File == TGSI_FILE_IMMEDIATE);
1850
1851 comp_imm = imms[src1.Index][src1.SwizzleX];
1852 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1853 gather_comp = CLAMP(gather_comp, 0, 3);
1854 }
1855
1856 dmask = 1 << gather_comp;
1857 }
1858
1859 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1860 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1861 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1862 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1863 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1864 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1865 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1866 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1867 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1868
1869 emit_data->arg_count = 11;
1870
1871 emit_data->dst_type = LLVMVectorType(
1872 LLVMFloatTypeInContext(gallivm->context),
1873 4);
1874 } else {
1875 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1876 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1877 emit_data->arg_count = 4;
1878
1879 emit_data->dst_type = LLVMVectorType(
1880 LLVMFloatTypeInContext(gallivm->context),
1881 4);
1882 }
1883
1884 /* The fetch opcode has been converted to a 2D array fetch.
1885 * This simplifies the LLVM backend. */
1886 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1887 target = TGSI_TEXTURE_2D_ARRAY;
1888 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1889 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1890
1891 /* Pad to power of two vector */
1892 while (count < util_next_power_of_two(count))
1893 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1894
1895 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1896 }
1897
1898 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1899 struct lp_build_tgsi_context * bld_base,
1900 struct lp_build_emit_data * emit_data)
1901 {
1902 struct lp_build_context * base = &bld_base->base;
1903 unsigned opcode = emit_data->inst->Instruction.Opcode;
1904 unsigned target = emit_data->inst->Texture.Texture;
1905 char intr_name[127];
1906 bool has_offset = HAVE_LLVM >= 0x0305 ?
1907 emit_data->inst->Texture.NumOffsets > 0 : false;
1908
1909 if (target == TGSI_TEXTURE_BUFFER) {
1910 emit_data->output[emit_data->chan] = build_intrinsic(
1911 base->gallivm->builder,
1912 "llvm.SI.vs.load.input", emit_data->dst_type,
1913 emit_data->args, emit_data->arg_count,
1914 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1915 return;
1916 }
1917
1918 if (opcode == TGSI_OPCODE_TG4 ||
1919 opcode == TGSI_OPCODE_LODQ ||
1920 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1921 bool is_shadow = tgsi_is_shadow_sampler(target);
1922 const char *name = "llvm.SI.image.sample";
1923 const char *infix = "";
1924
1925 switch (opcode) {
1926 case TGSI_OPCODE_TEX:
1927 case TGSI_OPCODE_TEX2:
1928 case TGSI_OPCODE_TXP:
1929 break;
1930 case TGSI_OPCODE_TXB:
1931 case TGSI_OPCODE_TXB2:
1932 infix = ".b";
1933 break;
1934 case TGSI_OPCODE_TXL:
1935 case TGSI_OPCODE_TXL2:
1936 infix = ".l";
1937 break;
1938 case TGSI_OPCODE_TXD:
1939 infix = ".d";
1940 break;
1941 case TGSI_OPCODE_TG4:
1942 name = "llvm.SI.gather4";
1943 break;
1944 case TGSI_OPCODE_LODQ:
1945 name = "llvm.SI.getlod";
1946 is_shadow = false;
1947 has_offset = false;
1948 break;
1949 default:
1950 assert(0);
1951 return;
1952 }
1953
1954 /* Add the type and suffixes .c, .o if needed. */
1955 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1956 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1957 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1958
1959 emit_data->output[emit_data->chan] = build_intrinsic(
1960 base->gallivm->builder, intr_name, emit_data->dst_type,
1961 emit_data->args, emit_data->arg_count,
1962 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1963 } else {
1964 LLVMTypeRef i8, v16i8, v32i8;
1965 const char *name;
1966
1967 switch (opcode) {
1968 case TGSI_OPCODE_TEX:
1969 case TGSI_OPCODE_TEX2:
1970 case TGSI_OPCODE_TXP:
1971 name = "llvm.SI.sample";
1972 break;
1973 case TGSI_OPCODE_TXB:
1974 case TGSI_OPCODE_TXB2:
1975 name = "llvm.SI.sampleb";
1976 break;
1977 case TGSI_OPCODE_TXD:
1978 name = "llvm.SI.sampled";
1979 break;
1980 case TGSI_OPCODE_TXF:
1981 name = "llvm.SI.imageload";
1982 break;
1983 case TGSI_OPCODE_TXL:
1984 case TGSI_OPCODE_TXL2:
1985 name = "llvm.SI.samplel";
1986 break;
1987 default:
1988 assert(0);
1989 return;
1990 }
1991
1992 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1993 v16i8 = LLVMVectorType(i8, 16);
1994 v32i8 = LLVMVectorType(i8, 32);
1995
1996 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1997 emit_data->args[1], v32i8, "");
1998 if (opcode != TGSI_OPCODE_TXF) {
1999 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2000 emit_data->args[2], v16i8, "");
2001 }
2002
2003 sprintf(intr_name, "%s.v%ui32", name,
2004 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2005
2006 emit_data->output[emit_data->chan] = build_intrinsic(
2007 base->gallivm->builder, intr_name, emit_data->dst_type,
2008 emit_data->args, emit_data->arg_count,
2009 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2010 }
2011 }
2012
2013 static void txq_fetch_args(
2014 struct lp_build_tgsi_context * bld_base,
2015 struct lp_build_emit_data * emit_data)
2016 {
2017 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2018 const struct tgsi_full_instruction *inst = emit_data->inst;
2019 struct gallivm_state *gallivm = bld_base->base.gallivm;
2020 unsigned target = inst->Texture.Texture;
2021
2022 if (target == TGSI_TEXTURE_BUFFER) {
2023 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2024 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2025
2026 /* Read the size from the buffer descriptor directly. */
2027 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2028 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2029 size = LLVMBuildExtractElement(gallivm->builder, size,
2030 lp_build_const_int32(gallivm, 2), "");
2031 emit_data->args[0] = size;
2032 return;
2033 }
2034
2035 /* Mip level */
2036 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2037
2038 /* Resource */
2039 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2040
2041 /* Texture target */
2042 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2043 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2044 target = TGSI_TEXTURE_2D_ARRAY;
2045
2046 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2047 target);
2048
2049 emit_data->arg_count = 3;
2050
2051 emit_data->dst_type = LLVMVectorType(
2052 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2053 4);
2054 }
2055
2056 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2057 struct lp_build_tgsi_context * bld_base,
2058 struct lp_build_emit_data * emit_data)
2059 {
2060 unsigned target = emit_data->inst->Texture.Texture;
2061
2062 if (target == TGSI_TEXTURE_BUFFER) {
2063 /* Just return the buffer size. */
2064 emit_data->output[emit_data->chan] = emit_data->args[0];
2065 return;
2066 }
2067
2068 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2069
2070 /* Divide the number of layers by 6 to get the number of cubes. */
2071 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2072 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2073 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2074 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2075 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2076
2077 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2078 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2079 z = LLVMBuildSDiv(builder, z, six, "");
2080
2081 emit_data->output[emit_data->chan] =
2082 LLVMBuildInsertElement(builder, v4, z, two, "");
2083 }
2084 }
2085
2086 static void si_llvm_emit_ddxy(
2087 const struct lp_build_tgsi_action * action,
2088 struct lp_build_tgsi_context * bld_base,
2089 struct lp_build_emit_data * emit_data)
2090 {
2091 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2092 struct gallivm_state *gallivm = bld_base->base.gallivm;
2093 struct lp_build_context * base = &bld_base->base;
2094 const struct tgsi_full_instruction *inst = emit_data->inst;
2095 unsigned opcode = inst->Instruction.Opcode;
2096 LLVMValueRef indices[2];
2097 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2098 LLVMValueRef tl, trbl, result[4];
2099 LLVMTypeRef i32;
2100 unsigned swizzle[4];
2101 unsigned c;
2102
2103 i32 = LLVMInt32TypeInContext(gallivm->context);
2104
2105 indices[0] = bld_base->uint_bld.zero;
2106 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2107 NULL, 0, LLVMReadNoneAttribute);
2108 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2109 indices, 2, "");
2110
2111 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2112 lp_build_const_int32(gallivm, 0xfffffffc), "");
2113 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2114 indices, 2, "");
2115
2116 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2117 lp_build_const_int32(gallivm,
2118 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2119 "");
2120 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2121 indices, 2, "");
2122
2123 for (c = 0; c < 4; ++c) {
2124 unsigned i;
2125
2126 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2127 for (i = 0; i < c; ++i) {
2128 if (swizzle[i] == swizzle[c]) {
2129 result[c] = result[i];
2130 break;
2131 }
2132 }
2133 if (i != c)
2134 continue;
2135
2136 LLVMBuildStore(gallivm->builder,
2137 LLVMBuildBitCast(gallivm->builder,
2138 lp_build_emit_fetch(bld_base, inst, 0, c),
2139 i32, ""),
2140 store_ptr);
2141
2142 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2143 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2144
2145 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2146 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2147
2148 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2149 }
2150
2151 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2152 }
2153
2154 /* Emit one vertex from the geometry shader */
2155 static void si_llvm_emit_vertex(
2156 const struct lp_build_tgsi_action *action,
2157 struct lp_build_tgsi_context *bld_base,
2158 struct lp_build_emit_data *emit_data)
2159 {
2160 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2161 struct lp_build_context *uint = &bld_base->uint_bld;
2162 struct si_shader *shader = si_shader_ctx->shader;
2163 struct tgsi_shader_info *info = &shader->selector->info;
2164 struct gallivm_state *gallivm = bld_base->base.gallivm;
2165 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2166 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2167 SI_PARAM_GS2VS_OFFSET);
2168 LLVMValueRef gs_next_vertex;
2169 LLVMValueRef can_emit, kill;
2170 LLVMValueRef t_list_ptr;
2171 LLVMValueRef t_list;
2172 LLVMValueRef args[2];
2173 unsigned chan;
2174 int i;
2175
2176 /* Load the GSVS ring resource descriptor */
2177 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2178 SI_PARAM_RW_BUFFERS);
2179 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2180 lp_build_const_int32(gallivm, SI_RING_GSVS));
2181
2182 /* Write vertex attribute values to GSVS ring */
2183 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2184
2185 /* If this thread has already emitted the declared maximum number of
2186 * vertices, kill it: excessive vertex emissions are not supposed to
2187 * have any effect, and GS threads have no externally observable
2188 * effects other than emitting vertices.
2189 */
2190 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2191 lp_build_const_int32(gallivm,
2192 shader->selector->gs_max_out_vertices), "");
2193 kill = lp_build_select(&bld_base->base, can_emit,
2194 lp_build_const_float(gallivm, 1.0f),
2195 lp_build_const_float(gallivm, -1.0f));
2196 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2197 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2198
2199 for (i = 0; i < info->num_outputs; i++) {
2200 LLVMValueRef *out_ptr =
2201 si_shader_ctx->radeon_bld.soa.outputs[i];
2202
2203 for (chan = 0; chan < 4; chan++) {
2204 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2205 LLVMValueRef voffset =
2206 lp_build_const_int32(gallivm, (i * 4 + chan) *
2207 shader->selector->gs_max_out_vertices);
2208
2209 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2210 voffset = lp_build_mul_imm(uint, voffset, 4);
2211
2212 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2213
2214 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2215 voffset, soffset, 0,
2216 V_008F0C_BUF_DATA_FORMAT_32,
2217 V_008F0C_BUF_NUM_FORMAT_UINT,
2218 1, 0, 1, 1, 0);
2219 }
2220 }
2221 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2222 lp_build_const_int32(gallivm, 1));
2223 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2224
2225 /* Signal vertex emission */
2226 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2227 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2228 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2229 LLVMVoidTypeInContext(gallivm->context), args, 2,
2230 LLVMNoUnwindAttribute);
2231 }
2232
2233 /* Cut one primitive from the geometry shader */
2234 static void si_llvm_emit_primitive(
2235 const struct lp_build_tgsi_action *action,
2236 struct lp_build_tgsi_context *bld_base,
2237 struct lp_build_emit_data *emit_data)
2238 {
2239 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2240 struct gallivm_state *gallivm = bld_base->base.gallivm;
2241 LLVMValueRef args[2];
2242
2243 /* Signal primitive cut */
2244 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2245 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2246 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2247 LLVMVoidTypeInContext(gallivm->context), args, 2,
2248 LLVMNoUnwindAttribute);
2249 }
2250
2251 static const struct lp_build_tgsi_action tex_action = {
2252 .fetch_args = tex_fetch_args,
2253 .emit = build_tex_intrinsic,
2254 };
2255
2256 static const struct lp_build_tgsi_action txq_action = {
2257 .fetch_args = txq_fetch_args,
2258 .emit = build_txq_intrinsic,
2259 .intr_name = "llvm.SI.resinfo"
2260 };
2261
2262 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2263 {
2264 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2265 LLVMValueRef args[3];
2266
2267 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2268 args[1] = 0;
2269 args[2] = lp_build_const_int32(gallivm, 1);
2270
2271 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2272 }
2273
2274 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2275 {
2276 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2277 CONST_ADDR_SPACE);
2278 }
2279
2280 static void create_function(struct si_shader_context *si_shader_ctx)
2281 {
2282 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2283 struct gallivm_state *gallivm = bld_base->base.gallivm;
2284 struct si_shader *shader = si_shader_ctx->shader;
2285 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2286 unsigned i, last_array_pointer, last_sgpr, num_params;
2287
2288 i8 = LLVMInt8TypeInContext(gallivm->context);
2289 i32 = LLVMInt32TypeInContext(gallivm->context);
2290 f32 = LLVMFloatTypeInContext(gallivm->context);
2291 v2i32 = LLVMVectorType(i32, 2);
2292 v3i32 = LLVMVectorType(i32, 3);
2293 v4i32 = LLVMVectorType(i32, 4);
2294 v8i32 = LLVMVectorType(i32, 8);
2295 v16i8 = LLVMVectorType(i8, 16);
2296
2297 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2298 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2299 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2300 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2301 last_array_pointer = SI_PARAM_RESOURCE;
2302
2303 switch (si_shader_ctx->type) {
2304 case TGSI_PROCESSOR_VERTEX:
2305 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2306 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2307 params[SI_PARAM_BASE_VERTEX] = i32;
2308 params[SI_PARAM_START_INSTANCE] = i32;
2309 num_params = SI_PARAM_START_INSTANCE+1;
2310
2311 if (shader->key.vs.as_es) {
2312 params[SI_PARAM_ES2GS_OFFSET] = i32;
2313 num_params++;
2314 } else {
2315 if (shader->is_gs_copy_shader) {
2316 last_array_pointer = SI_PARAM_CONST;
2317 num_params = SI_PARAM_CONST+1;
2318 }
2319
2320 /* The locations of the other parameters are assigned dynamically. */
2321
2322 /* Streamout SGPRs. */
2323 if (shader->selector->so.num_outputs) {
2324 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2325 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2326 }
2327 /* A streamout buffer offset is loaded if the stride is non-zero. */
2328 for (i = 0; i < 4; i++) {
2329 if (!shader->selector->so.stride[i])
2330 continue;
2331
2332 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2333 }
2334 }
2335
2336 last_sgpr = num_params-1;
2337
2338 /* VGPRs */
2339 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2340 params[num_params++] = i32; /* unused*/
2341 params[num_params++] = i32; /* unused */
2342 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2343 break;
2344
2345 case TGSI_PROCESSOR_GEOMETRY:
2346 params[SI_PARAM_GS2VS_OFFSET] = i32;
2347 params[SI_PARAM_GS_WAVE_ID] = i32;
2348 last_sgpr = SI_PARAM_GS_WAVE_ID;
2349
2350 /* VGPRs */
2351 params[SI_PARAM_VTX0_OFFSET] = i32;
2352 params[SI_PARAM_VTX1_OFFSET] = i32;
2353 params[SI_PARAM_PRIMITIVE_ID] = i32;
2354 params[SI_PARAM_VTX2_OFFSET] = i32;
2355 params[SI_PARAM_VTX3_OFFSET] = i32;
2356 params[SI_PARAM_VTX4_OFFSET] = i32;
2357 params[SI_PARAM_VTX5_OFFSET] = i32;
2358 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2359 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2360 break;
2361
2362 case TGSI_PROCESSOR_FRAGMENT:
2363 params[SI_PARAM_ALPHA_REF] = f32;
2364 params[SI_PARAM_PRIM_MASK] = i32;
2365 last_sgpr = SI_PARAM_PRIM_MASK;
2366 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2367 params[SI_PARAM_PERSP_CENTER] = v2i32;
2368 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2369 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2370 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2371 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2372 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2373 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2374 params[SI_PARAM_POS_X_FLOAT] = f32;
2375 params[SI_PARAM_POS_Y_FLOAT] = f32;
2376 params[SI_PARAM_POS_Z_FLOAT] = f32;
2377 params[SI_PARAM_POS_W_FLOAT] = f32;
2378 params[SI_PARAM_FRONT_FACE] = f32;
2379 params[SI_PARAM_ANCILLARY] = i32;
2380 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2381 params[SI_PARAM_POS_FIXED_PT] = f32;
2382 num_params = SI_PARAM_POS_FIXED_PT+1;
2383 break;
2384
2385 default:
2386 assert(0 && "unimplemented shader");
2387 return;
2388 }
2389
2390 assert(num_params <= Elements(params));
2391 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2392 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2393
2394 for (i = 0; i <= last_sgpr; ++i) {
2395 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2396
2397 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2398 * to move load. Inputs are constant so this is fine. */
2399 if (i <= last_array_pointer)
2400 LLVMAddAttribute(P, LLVMByValAttribute);
2401 else
2402 LLVMAddAttribute(P, LLVMInRegAttribute);
2403 }
2404
2405 if (bld_base->info &&
2406 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2407 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2408 si_shader_ctx->ddxy_lds =
2409 LLVMAddGlobalInAddressSpace(gallivm->module,
2410 LLVMArrayType(i32, 64),
2411 "ddxy_lds",
2412 LOCAL_ADDR_SPACE);
2413 }
2414
2415 static void preload_constants(struct si_shader_context *si_shader_ctx)
2416 {
2417 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2418 struct gallivm_state * gallivm = bld_base->base.gallivm;
2419 const struct tgsi_shader_info * info = bld_base->info;
2420 unsigned buf;
2421 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2422
2423 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2424 unsigned i, num_const = info->const_file_max[buf] + 1;
2425
2426 if (num_const == 0)
2427 continue;
2428
2429 /* Allocate space for the constant values */
2430 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2431
2432 /* Load the resource descriptor */
2433 si_shader_ctx->const_resource[buf] =
2434 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2435
2436 /* Load the constants, we rely on the code sinking to do the rest */
2437 for (i = 0; i < num_const * 4; ++i) {
2438 si_shader_ctx->constants[buf][i] =
2439 load_const(gallivm->builder,
2440 si_shader_ctx->const_resource[buf],
2441 lp_build_const_int32(gallivm, i * 4),
2442 bld_base->base.elem_type);
2443 }
2444 }
2445 }
2446
2447 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2448 {
2449 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2450 struct gallivm_state * gallivm = bld_base->base.gallivm;
2451 const struct tgsi_shader_info * info = bld_base->info;
2452
2453 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2454
2455 LLVMValueRef res_ptr, samp_ptr;
2456 LLVMValueRef offset;
2457
2458 if (num_samplers == 0)
2459 return;
2460
2461 /* Allocate space for the values */
2462 si_shader_ctx->resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2463 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2464
2465 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2466 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2467
2468 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2469 for (i = 0; i < num_samplers; ++i) {
2470 /* Resource */
2471 offset = lp_build_const_int32(gallivm, i);
2472 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2473
2474 /* Sampler */
2475 offset = lp_build_const_int32(gallivm, i);
2476 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2477
2478 /* FMASK resource */
2479 if (info->is_msaa_sampler[i]) {
2480 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2481 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2482 build_indexed_load(si_shader_ctx, res_ptr, offset);
2483 }
2484 }
2485 }
2486
2487 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2488 {
2489 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2490 struct gallivm_state * gallivm = bld_base->base.gallivm;
2491 unsigned i;
2492
2493 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2494 si_shader_ctx->shader->key.vs.as_es ||
2495 !si_shader_ctx->shader->selector->so.num_outputs)
2496 return;
2497
2498 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2499 SI_PARAM_RW_BUFFERS);
2500
2501 /* Load the resources, we rely on the code sinking to do the rest */
2502 for (i = 0; i < 4; ++i) {
2503 if (si_shader_ctx->shader->selector->so.stride[i]) {
2504 LLVMValueRef offset = lp_build_const_int32(gallivm,
2505 SI_SO_BUF_OFFSET + i);
2506
2507 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2508 }
2509 }
2510 }
2511
2512 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2513 LLVMModuleRef mod)
2514 {
2515 unsigned r; /* llvm_compile result */
2516 unsigned i;
2517 unsigned char *ptr;
2518 struct radeon_shader_binary binary;
2519 bool dump = r600_can_dump_shader(&sscreen->b,
2520 shader->selector ? shader->selector->tokens : NULL);
2521 const char * gpu_family = r600_get_llvm_processor_name(sscreen->b.family);
2522 unsigned code_size;
2523
2524 /* Use LLVM to compile shader */
2525 memset(&binary, 0, sizeof(binary));
2526 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2527
2528 /* Output binary dump if rscreen->debug_flags are set */
2529 if (dump && ! binary.disassembled) {
2530 fprintf(stderr, "SI CODE:\n");
2531 for (i = 0; i < binary.code_size; i+=4 ) {
2532 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2533 binary.code[i + 2], binary.code[i + 1],
2534 binary.code[i]);
2535 }
2536 }
2537
2538 /* XXX: We may be able to emit some of these values directly rather than
2539 * extracting fields to be emitted later.
2540 */
2541 /* Parse config data in compiled binary */
2542 for (i = 0; i < binary.config_size; i+= 8) {
2543 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2544 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2545 switch (reg) {
2546 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2547 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2548 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2549 case R_00B848_COMPUTE_PGM_RSRC1:
2550 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2551 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2552 break;
2553 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2554 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2555 break;
2556 case R_00B84C_COMPUTE_PGM_RSRC2:
2557 shader->lds_size = G_00B84C_LDS_SIZE(value);
2558 break;
2559 case R_0286CC_SPI_PS_INPUT_ENA:
2560 shader->spi_ps_input_ena = value;
2561 break;
2562 case R_00B860_COMPUTE_TMPRING_SIZE:
2563 /* WAVESIZE is in units of 256 dwords. */
2564 shader->scratch_bytes_per_wave =
2565 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2566 break;
2567 default:
2568 fprintf(stderr, "Warning: Compiler emitted unknown "
2569 "config register: 0x%x\n", reg);
2570 break;
2571 }
2572 }
2573
2574 /* copy new shader */
2575 code_size = binary.code_size + binary.rodata_size;
2576 r600_resource_reference(&shader->bo, NULL);
2577 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2578 code_size);
2579 if (shader->bo == NULL) {
2580 return -ENOMEM;
2581 }
2582
2583 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
2584 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2585 if (binary.rodata_size > 0) {
2586 ptr += binary.code_size;
2587 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2588 }
2589
2590 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2591
2592 free(binary.code);
2593 free(binary.config);
2594 free(binary.rodata);
2595
2596 return r;
2597 }
2598
2599 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2600 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2601 struct si_shader_context *si_shader_ctx,
2602 struct si_shader *gs, bool dump)
2603 {
2604 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2605 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2606 struct lp_build_context *base = &bld_base->base;
2607 struct lp_build_context *uint = &bld_base->uint_bld;
2608 struct si_shader *shader = si_shader_ctx->shader;
2609 struct si_shader_output_values *outputs;
2610 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2611 LLVMValueRef t_list_ptr, t_list;
2612 LLVMValueRef args[9];
2613 int i, r;
2614
2615 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2616
2617 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2618 shader->is_gs_copy_shader = true;
2619
2620 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2621
2622 create_meta_data(si_shader_ctx);
2623 create_function(si_shader_ctx);
2624 preload_streamout_buffers(si_shader_ctx);
2625
2626 /* Load the GSVS ring resource descriptor */
2627 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2628 SI_PARAM_RW_BUFFERS);
2629 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2630 lp_build_const_int32(gallivm, SI_RING_GSVS));
2631
2632 args[0] = t_list;
2633 args[1] = lp_build_mul_imm(uint,
2634 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2635 si_shader_ctx->param_vertex_id),
2636 4);
2637 args[3] = uint->zero;
2638 args[4] = uint->one; /* OFFEN */
2639 args[5] = uint->zero; /* IDXEN */
2640 args[6] = uint->one; /* GLC */
2641 args[7] = uint->one; /* SLC */
2642 args[8] = uint->zero; /* TFE */
2643
2644 /* Fetch vertex data from GSVS ring */
2645 for (i = 0; i < gsinfo->num_outputs; ++i) {
2646 unsigned chan;
2647
2648 outputs[i].name = gsinfo->output_semantic_name[i];
2649 outputs[i].sid = gsinfo->output_semantic_index[i];
2650
2651 for (chan = 0; chan < 4; chan++) {
2652 args[2] = lp_build_const_int32(gallivm,
2653 (i * 4 + chan) *
2654 gs->selector->gs_max_out_vertices * 16 * 4);
2655
2656 outputs[i].values[chan] =
2657 LLVMBuildBitCast(gallivm->builder,
2658 build_intrinsic(gallivm->builder,
2659 "llvm.SI.buffer.load.dword.i32.i32",
2660 LLVMInt32TypeInContext(gallivm->context),
2661 args, 9,
2662 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2663 base->elem_type, "");
2664 }
2665 }
2666
2667 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2668
2669 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2670
2671 if (dump)
2672 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2673
2674 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2675 bld_base->base.gallivm->module);
2676
2677 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2678
2679 FREE(outputs);
2680 return r;
2681 }
2682
2683 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2684 {
2685 struct si_shader_selector *sel = shader->selector;
2686 struct si_shader_context si_shader_ctx;
2687 struct lp_build_tgsi_context * bld_base;
2688 LLVMModuleRef mod;
2689 int r = 0;
2690 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2691
2692 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2693 * conversion fails. */
2694 if (dump) {
2695 tgsi_dump(sel->tokens, 0);
2696 si_dump_streamout(&sel->so);
2697 }
2698
2699 assert(shader->nparam == 0);
2700
2701 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2702 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2703 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2704
2705 if (sel->info.uses_kill)
2706 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2707
2708 shader->uses_instanceid = sel->info.uses_instanceid;
2709 bld_base->info = &sel->info;
2710 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2711
2712 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2713 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2714 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2715 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2716 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2717 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2718 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2719 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2720 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2721 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2722 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2723 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2724
2725 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2726 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2727
2728 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2729 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2730
2731 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2732 si_shader_ctx.tokens = sel->tokens;
2733 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2734 si_shader_ctx.shader = shader;
2735 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2736
2737 switch (si_shader_ctx.type) {
2738 case TGSI_PROCESSOR_VERTEX:
2739 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2740 if (shader->key.vs.as_es) {
2741 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2742 } else {
2743 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2744 }
2745 break;
2746 case TGSI_PROCESSOR_GEOMETRY:
2747 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2748 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2749 break;
2750 case TGSI_PROCESSOR_FRAGMENT:
2751 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2752 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2753
2754 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2755 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2756 shader->db_shader_control |=
2757 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2758 break;
2759 case TGSI_FS_DEPTH_LAYOUT_LESS:
2760 shader->db_shader_control |=
2761 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2762 break;
2763 }
2764 break;
2765 default:
2766 assert(!"Unsupported shader type");
2767 return -1;
2768 }
2769
2770 create_meta_data(&si_shader_ctx);
2771 create_function(&si_shader_ctx);
2772 preload_constants(&si_shader_ctx);
2773 preload_samplers(&si_shader_ctx);
2774 preload_streamout_buffers(&si_shader_ctx);
2775
2776 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2777 si_shader_ctx.gs_next_vertex =
2778 lp_build_alloca(bld_base->base.gallivm,
2779 bld_base->uint_bld.elem_type, "");
2780 }
2781
2782 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2783 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2784 goto out;
2785 }
2786
2787 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2788
2789 mod = bld_base->base.gallivm->module;
2790 r = si_compile_llvm(sscreen, shader, mod);
2791 if (r) {
2792 fprintf(stderr, "LLVM failed to compile shader\n");
2793 goto out;
2794 }
2795
2796 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2797
2798 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2799 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2800 shader->gs_copy_shader->selector = shader->selector;
2801 shader->gs_copy_shader->key = shader->key;
2802 si_shader_ctx.shader = shader->gs_copy_shader;
2803 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2804 shader, dump))) {
2805 free(shader->gs_copy_shader);
2806 shader->gs_copy_shader = NULL;
2807 goto out;
2808 }
2809 }
2810
2811 tgsi_parse_free(&si_shader_ctx.parse);
2812
2813 out:
2814 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2815 FREE(si_shader_ctx.constants[i]);
2816 FREE(si_shader_ctx.resources);
2817 FREE(si_shader_ctx.samplers);
2818
2819 return r;
2820 }
2821
2822 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2823 {
2824 if (shader->gs_copy_shader)
2825 si_shader_destroy(ctx, shader->gs_copy_shader);
2826
2827 r600_resource_reference(&shader->bo, NULL);
2828 r600_resource_reference(&shader->scratch_bo, NULL);
2829 }