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radeonsi: create load_const_buffer_desc_fast_path() helper
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 unsigned offset = i;
1295 if (llvm_type_is_64bit(ctx, type))
1296 offset *= 2;
1297
1298 value[i] = lds_load(bld_base, type, offset, dw_addr);
1299 }
1300
1301 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1302 }
1303
1304 static LLVMValueRef fetch_output_tcs(
1305 struct lp_build_tgsi_context *bld_base,
1306 const struct tgsi_full_src_register *reg,
1307 enum tgsi_opcode_type type, unsigned swizzle)
1308 {
1309 struct si_shader_context *ctx = si_shader_context(bld_base);
1310 LLVMValueRef dw_addr, stride;
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1316 } else {
1317 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1318 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1319 }
1320
1321 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1322 }
1323
1324 static LLVMValueRef fetch_input_tes(
1325 struct lp_build_tgsi_context *bld_base,
1326 const struct tgsi_full_src_register *reg,
1327 enum tgsi_opcode_type type, unsigned swizzle)
1328 {
1329 struct si_shader_context *ctx = si_shader_context(bld_base);
1330 LLVMValueRef base, addr;
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1334
1335 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1336 ctx->tess_offchip_ring, base, addr, true);
1337 }
1338
1339 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1340 LLVMTypeRef type,
1341 LLVMValueRef vertex_index,
1342 LLVMValueRef param_index,
1343 unsigned const_index,
1344 unsigned location,
1345 unsigned driver_location,
1346 unsigned component,
1347 unsigned num_components,
1348 bool is_patch,
1349 bool is_compact,
1350 bool load_input)
1351 {
1352 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1353 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1354 LLVMValueRef base, addr;
1355
1356 driver_location = driver_location / 4;
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 unsigned offset = i;
1382 if (llvm_type_is_64bit(ctx, type))
1383 offset *= 2;
1384
1385 value[i] = buffer_load(&ctx->bld_base, type, offset,
1386 ctx->tess_offchip_ring, base, addr, true);
1387 }
1388
1389 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1390 }
1391
1392 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1393 const struct tgsi_full_instruction *inst,
1394 const struct tgsi_opcode_info *info,
1395 unsigned index,
1396 LLVMValueRef dst[4])
1397 {
1398 struct si_shader_context *ctx = si_shader_context(bld_base);
1399 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1400 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1401 unsigned chan_index;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, buf_addr;
1404 LLVMValueRef values[4];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 /* Only handle per-patch and per-vertex outputs here.
1409 * Vectors will be lowered to scalars and this function will be called again.
1410 */
1411 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1412 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1413 si_llvm_emit_store(bld_base, inst, info, index, dst);
1414 return;
1415 }
1416
1417 if (reg->Register.Dimension) {
1418 stride = get_tcs_out_vertex_dw_stride(ctx);
1419 dw_addr = get_tcs_out_current_patch_offset(ctx);
1420 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1421 skip_lds_store = !sh_info->reads_pervertex_outputs;
1422 } else {
1423 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1424 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1425 skip_lds_store = !sh_info->reads_perpatch_outputs;
1426
1427 if (!reg->Register.Indirect) {
1428 int name = sh_info->output_semantic_name[reg->Register.Index];
1429
1430 /* Always write tess factors into LDS for the TCS epilog. */
1431 if (name == TGSI_SEMANTIC_TESSINNER ||
1432 name == TGSI_SEMANTIC_TESSOUTER) {
1433 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1434 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1435 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1436 is_tess_factor = true;
1437 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1438 }
1439 }
1440 }
1441
1442 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1443
1444 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1445 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1446
1447 uint32_t writemask = reg->Register.WriteMask;
1448 while (writemask) {
1449 chan_index = u_bit_scan(&writemask);
1450 LLVMValueRef value = dst[chan_index];
1451
1452 if (inst->Instruction.Saturate)
1453 value = ac_build_clamp(&ctx->ac, value);
1454
1455 /* Skip LDS stores if there is no LDS read of this output. */
1456 if (!skip_lds_store)
1457 lds_store(ctx, chan_index, dw_addr, value);
1458
1459 value = ac_to_integer(&ctx->ac, value);
1460 values[chan_index] = value;
1461
1462 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1463 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1464 buf_addr, base,
1465 4 * chan_index, 1, 0, true, false);
1466 }
1467
1468 /* Write tess factors into VGPRs for the epilog. */
1469 if (is_tess_factor &&
1470 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1471 if (!is_tess_inner) {
1472 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1473 ctx->invoc0_tess_factors[chan_index]);
1474 } else if (chan_index < 2) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1476 ctx->invoc0_tess_factors[4 + chan_index]);
1477 }
1478 }
1479 }
1480
1481 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1482 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1483 values, 4);
1484 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1485 base, 0, 1, 0, true, false);
1486 }
1487 }
1488
1489 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1490 const struct nir_variable *var,
1491 LLVMValueRef vertex_index,
1492 LLVMValueRef param_index,
1493 unsigned const_index,
1494 LLVMValueRef src,
1495 unsigned writemask)
1496 {
1497 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1498 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1499 const unsigned component = var->data.location_frac;
1500 const bool is_patch = var->data.patch;
1501 unsigned driver_location = var->data.driver_location;
1502 LLVMValueRef dw_addr, stride;
1503 LLVMValueRef buffer, base, addr;
1504 LLVMValueRef values[4];
1505 bool skip_lds_store;
1506 bool is_tess_factor = false, is_tess_inner = false;
1507
1508 driver_location = driver_location / 4;
1509
1510 if (param_index) {
1511 /* Add the constant index to the indirect index */
1512 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1513 LLVMConstInt(ctx->i32, const_index, 0), "");
1514 } else {
1515 if (const_index != 0)
1516 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1517 }
1518
1519 if (!is_patch) {
1520 stride = get_tcs_out_vertex_dw_stride(ctx);
1521 dw_addr = get_tcs_out_current_patch_offset(ctx);
1522 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1523 vertex_index, param_index,
1524 driver_location,
1525 info->output_semantic_name,
1526 info->output_semantic_index,
1527 is_patch);
1528
1529 skip_lds_store = !info->reads_pervertex_outputs;
1530 } else {
1531 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1532 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1533 vertex_index, param_index,
1534 driver_location,
1535 info->output_semantic_name,
1536 info->output_semantic_index,
1537 is_patch);
1538
1539 skip_lds_store = !info->reads_perpatch_outputs;
1540
1541 if (!param_index) {
1542 int name = info->output_semantic_name[driver_location];
1543
1544 /* Always write tess factors into LDS for the TCS epilog. */
1545 if (name == TGSI_SEMANTIC_TESSINNER ||
1546 name == TGSI_SEMANTIC_TESSOUTER) {
1547 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1548 skip_lds_store = !info->reads_tessfactor_outputs &&
1549 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1550 is_tess_factor = true;
1551 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1552 }
1553 }
1554 }
1555
1556 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1557
1558 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1559
1560 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1561 param_index, driver_location,
1562 info->output_semantic_name,
1563 info->output_semantic_index,
1564 is_patch);
1565
1566 for (unsigned chan = 0; chan < 4; chan++) {
1567 if (!(writemask & (1 << chan)))
1568 continue;
1569 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1570
1571 /* Skip LDS stores if there is no LDS read of this output. */
1572 if (!skip_lds_store)
1573 lds_store(ctx, chan, dw_addr, value);
1574
1575 value = ac_to_integer(&ctx->ac, value);
1576 values[chan] = value;
1577
1578 if (writemask != 0xF && !is_tess_factor) {
1579 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1580 addr, base,
1581 4 * chan, 1, 0, true, false);
1582 }
1583
1584 /* Write tess factors into VGPRs for the epilog. */
1585 if (is_tess_factor &&
1586 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1587 if (!is_tess_inner) {
1588 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1589 ctx->invoc0_tess_factors[chan]);
1590 } else if (chan < 2) {
1591 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1592 ctx->invoc0_tess_factors[4 + chan]);
1593 }
1594 }
1595 }
1596
1597 if (writemask == 0xF && !is_tess_factor) {
1598 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1599 values, 4);
1600 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1601 base, 0, 1, 0, true, false);
1602 }
1603 }
1604
1605 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1606 unsigned input_index,
1607 unsigned vtx_offset_param,
1608 LLVMTypeRef type,
1609 unsigned swizzle)
1610 {
1611 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1612 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1613 struct si_shader *shader = ctx->shader;
1614 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1615 LLVMValueRef vtx_offset, soffset;
1616 struct tgsi_shader_info *info = &shader->selector->info;
1617 unsigned semantic_name = info->input_semantic_name[input_index];
1618 unsigned semantic_index = info->input_semantic_index[input_index];
1619 unsigned param;
1620 LLVMValueRef value;
1621
1622 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1623
1624 /* GFX9 has the ESGS ring in LDS. */
1625 if (ctx->screen->info.chip_class >= GFX9) {
1626 unsigned index = vtx_offset_param;
1627
1628 switch (index / 2) {
1629 case 0:
1630 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1631 index % 2 ? 16 : 0, 16);
1632 break;
1633 case 1:
1634 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1635 index % 2 ? 16 : 0, 16);
1636 break;
1637 case 2:
1638 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1639 index % 2 ? 16 : 0, 16);
1640 break;
1641 default:
1642 assert(0);
1643 return NULL;
1644 }
1645
1646 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1647 LLVMConstInt(ctx->i32, param * 4, 0), "");
1648 return lds_load(bld_base, type, swizzle, vtx_offset);
1649 }
1650
1651 /* GFX6: input load from the ESGS ring in memory. */
1652 if (swizzle == ~0) {
1653 LLVMValueRef values[TGSI_NUM_CHANNELS];
1654 unsigned chan;
1655 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1656 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1657 type, chan);
1658 }
1659 return lp_build_gather_values(&ctx->gallivm, values,
1660 TGSI_NUM_CHANNELS);
1661 }
1662
1663 /* Get the vertex offset parameter on GFX6. */
1664 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1665
1666 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1667
1668 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1669
1670 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1671 vtx_offset, soffset, 0, 1, 0, true, false);
1672 if (llvm_type_is_64bit(ctx, type)) {
1673 LLVMValueRef value2;
1674 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1675
1676 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1677 ctx->i32_0, vtx_offset, soffset,
1678 0, 1, 0, true, false);
1679 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1680 }
1681 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1682 }
1683
1684 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1685 unsigned location,
1686 unsigned driver_location,
1687 unsigned component,
1688 unsigned num_components,
1689 unsigned vertex_index,
1690 unsigned const_index,
1691 LLVMTypeRef type)
1692 {
1693 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1694
1695 LLVMValueRef value[4];
1696 for (unsigned i = component; i < num_components + component; i++) {
1697 unsigned offset = i;
1698 if (llvm_type_is_64bit(ctx, type))
1699 offset *= 2;
1700
1701 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1702 vertex_index, type, offset);
1703 }
1704
1705 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1706 }
1707
1708 static LLVMValueRef fetch_input_gs(
1709 struct lp_build_tgsi_context *bld_base,
1710 const struct tgsi_full_src_register *reg,
1711 enum tgsi_opcode_type type,
1712 unsigned swizzle)
1713 {
1714 struct si_shader_context *ctx = si_shader_context(bld_base);
1715 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1716
1717 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1718 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1719 return get_primitive_id(ctx, swizzle);
1720
1721 if (!reg->Register.Dimension)
1722 return NULL;
1723
1724 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1725 reg->Dimension.Index,
1726 tgsi2llvmtype(bld_base, type),
1727 swizzle);
1728 }
1729
1730 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1731 {
1732 switch (interpolate) {
1733 case TGSI_INTERPOLATE_CONSTANT:
1734 return 0;
1735
1736 case TGSI_INTERPOLATE_LINEAR:
1737 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1738 return SI_PARAM_LINEAR_SAMPLE;
1739 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1740 return SI_PARAM_LINEAR_CENTROID;
1741 else
1742 return SI_PARAM_LINEAR_CENTER;
1743 break;
1744 case TGSI_INTERPOLATE_COLOR:
1745 case TGSI_INTERPOLATE_PERSPECTIVE:
1746 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1747 return SI_PARAM_PERSP_SAMPLE;
1748 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1749 return SI_PARAM_PERSP_CENTROID;
1750 else
1751 return SI_PARAM_PERSP_CENTER;
1752 break;
1753 default:
1754 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1755 return -1;
1756 }
1757 }
1758
1759 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1760 unsigned attr_index, unsigned chan,
1761 LLVMValueRef prim_mask,
1762 LLVMValueRef i, LLVMValueRef j)
1763 {
1764 if (i || j) {
1765 return ac_build_fs_interp(&ctx->ac,
1766 LLVMConstInt(ctx->i32, chan, 0),
1767 LLVMConstInt(ctx->i32, attr_index, 0),
1768 prim_mask, i, j);
1769 }
1770 return ac_build_fs_interp_mov(&ctx->ac,
1771 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1772 LLVMConstInt(ctx->i32, chan, 0),
1773 LLVMConstInt(ctx->i32, attr_index, 0),
1774 prim_mask);
1775 }
1776
1777 /**
1778 * Interpolate a fragment shader input.
1779 *
1780 * @param ctx context
1781 * @param input_index index of the input in hardware
1782 * @param semantic_name TGSI_SEMANTIC_*
1783 * @param semantic_index semantic index
1784 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1785 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1786 * @param interp_param interpolation weights (i,j)
1787 * @param prim_mask SI_PARAM_PRIM_MASK
1788 * @param face SI_PARAM_FRONT_FACE
1789 * @param result the return value (4 components)
1790 */
1791 static void interp_fs_input(struct si_shader_context *ctx,
1792 unsigned input_index,
1793 unsigned semantic_name,
1794 unsigned semantic_index,
1795 unsigned num_interp_inputs,
1796 unsigned colors_read_mask,
1797 LLVMValueRef interp_param,
1798 LLVMValueRef prim_mask,
1799 LLVMValueRef face,
1800 LLVMValueRef result[4])
1801 {
1802 LLVMValueRef i = NULL, j = NULL;
1803 unsigned chan;
1804
1805 /* fs.constant returns the param from the middle vertex, so it's not
1806 * really useful for flat shading. It's meant to be used for custom
1807 * interpolation (but the intrinsic can't fetch from the other two
1808 * vertices).
1809 *
1810 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1811 * to do the right thing. The only reason we use fs.constant is that
1812 * fs.interp cannot be used on integers, because they can be equal
1813 * to NaN.
1814 *
1815 * When interp is false we will use fs.constant or for newer llvm,
1816 * amdgcn.interp.mov.
1817 */
1818 bool interp = interp_param != NULL;
1819
1820 if (interp) {
1821 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1822 LLVMVectorType(ctx->f32, 2), "");
1823
1824 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1825 ctx->i32_0, "");
1826 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1827 ctx->i32_1, "");
1828 }
1829
1830 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1831 ctx->shader->key.part.ps.prolog.color_two_side) {
1832 LLVMValueRef is_face_positive;
1833
1834 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1835 * otherwise it's at offset "num_inputs".
1836 */
1837 unsigned back_attr_offset = num_interp_inputs;
1838 if (semantic_index == 1 && colors_read_mask & 0xf)
1839 back_attr_offset += 1;
1840
1841 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1842 face, ctx->i32_0, "");
1843
1844 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1845 LLVMValueRef front, back;
1846
1847 front = si_build_fs_interp(ctx,
1848 input_index, chan,
1849 prim_mask, i, j);
1850 back = si_build_fs_interp(ctx,
1851 back_attr_offset, chan,
1852 prim_mask, i, j);
1853
1854 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1855 is_face_positive,
1856 front,
1857 back,
1858 "");
1859 }
1860 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1861 result[0] = si_build_fs_interp(ctx, input_index,
1862 0, prim_mask, i, j);
1863 result[1] =
1864 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1865 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1866 } else {
1867 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1868 result[chan] = si_build_fs_interp(ctx,
1869 input_index, chan,
1870 prim_mask, i, j);
1871 }
1872 }
1873 }
1874
1875 void si_llvm_load_input_fs(
1876 struct si_shader_context *ctx,
1877 unsigned input_index,
1878 LLVMValueRef out[4])
1879 {
1880 struct lp_build_context *base = &ctx->bld_base.base;
1881 struct si_shader *shader = ctx->shader;
1882 struct tgsi_shader_info *info = &shader->selector->info;
1883 LLVMValueRef main_fn = ctx->main_fn;
1884 LLVMValueRef interp_param = NULL;
1885 int interp_param_idx;
1886 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1887 unsigned semantic_index = info->input_semantic_index[input_index];
1888 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1889 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1890
1891 /* Get colors from input VGPRs (set by the prolog). */
1892 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1893 unsigned colors_read = shader->selector->info.colors_read;
1894 unsigned mask = colors_read >> (semantic_index * 4);
1895 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1896 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1897
1898 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1899 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1900 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1901 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1902 return;
1903 }
1904
1905 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1906 if (interp_param_idx == -1)
1907 return;
1908 else if (interp_param_idx) {
1909 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1910 }
1911
1912 interp_fs_input(ctx, input_index, semantic_name,
1913 semantic_index, 0, /* this param is unused */
1914 shader->selector->info.colors_read, interp_param,
1915 ctx->abi.prim_mask,
1916 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1917 &out[0]);
1918 }
1919
1920 static void declare_input_fs(
1921 struct si_shader_context *ctx,
1922 unsigned input_index,
1923 const struct tgsi_full_declaration *decl,
1924 LLVMValueRef out[4])
1925 {
1926 si_llvm_load_input_fs(ctx, input_index, out);
1927 }
1928
1929 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1930 {
1931 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1932 }
1933
1934 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1935 {
1936 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1937
1938 /* For non-indexed draws, the base vertex set by the driver
1939 * (for direct draws) or the CP (for indirect draws) is the
1940 * first vertex ID, but GLSL expects 0 to be returned.
1941 */
1942 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1943 ctx->param_vs_state_bits);
1944 LLVMValueRef indexed;
1945
1946 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1947 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1948
1949 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1950 ctx->i32_0, "");
1951 }
1952
1953 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1954 {
1955 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1956
1957 LLVMValueRef values[3];
1958 LLVMValueRef result;
1959 unsigned i;
1960 unsigned *properties = ctx->shader->selector->info.properties;
1961
1962 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1963 unsigned sizes[3] = {
1964 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1965 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1966 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1967 };
1968
1969 for (i = 0; i < 3; ++i)
1970 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1971
1972 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1973 } else {
1974 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1975 }
1976
1977 return result;
1978 }
1979
1980 /**
1981 * Load a dword from a constant buffer.
1982 */
1983 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1984 LLVMValueRef resource,
1985 LLVMValueRef offset)
1986 {
1987 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1988 0, 0, 0, true, true);
1989 }
1990
1991 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1992 {
1993 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1994 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1995 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1996 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1997 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1998
1999 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2000 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
2001 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
2002
2003 LLVMValueRef pos[4] = {
2004 buffer_load_const(ctx, resource, offset0),
2005 buffer_load_const(ctx, resource, offset1),
2006 LLVMConstReal(ctx->f32, 0),
2007 LLVMConstReal(ctx->f32, 0)
2008 };
2009
2010 return lp_build_gather_values(&ctx->gallivm, pos, 4);
2011 }
2012
2013 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
2014 {
2015 return abi->sample_coverage;
2016 }
2017
2018 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2019 {
2020 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2021 struct lp_build_context *bld = &ctx->bld_base.base;
2022
2023 LLVMValueRef coord[4] = {
2024 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2025 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2026 ctx->ac.f32_0,
2027 ctx->ac.f32_0
2028 };
2029
2030 /* For triangles, the vector should be (u, v, 1-u-v). */
2031 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2032 PIPE_PRIM_TRIANGLES)
2033 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
2034 lp_build_add(bld, coord[0], coord[1]));
2035
2036 return lp_build_gather_values(&ctx->gallivm, coord, 4);
2037 }
2038
2039 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2040 unsigned semantic_name)
2041 {
2042 LLVMValueRef base, addr;
2043
2044 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2045
2046 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2047 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2048 LLVMConstInt(ctx->i32, param, 0));
2049
2050 return buffer_load(&ctx->bld_base, ctx->f32,
2051 ~0, ctx->tess_offchip_ring, base, addr, true);
2052
2053 }
2054
2055 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2056 unsigned varying_id)
2057 {
2058 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2059 unsigned semantic_name;
2060
2061 switch (varying_id) {
2062 case VARYING_SLOT_TESS_LEVEL_INNER:
2063 semantic_name = TGSI_SEMANTIC_TESSINNER;
2064 break;
2065 case VARYING_SLOT_TESS_LEVEL_OUTER:
2066 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2067 break;
2068 default:
2069 unreachable("unknown tess level");
2070 }
2071
2072 return load_tess_level(ctx, semantic_name);
2073
2074 }
2075
2076 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2077 {
2078 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2079 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2080 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2081 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2082 return get_num_tcs_out_vertices(ctx);
2083 else
2084 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2085 }
2086
2087 void si_load_system_value(struct si_shader_context *ctx,
2088 unsigned index,
2089 const struct tgsi_full_declaration *decl)
2090 {
2091 LLVMValueRef value = 0;
2092
2093 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2094
2095 switch (decl->Semantic.Name) {
2096 case TGSI_SEMANTIC_INSTANCEID:
2097 value = ctx->abi.instance_id;
2098 break;
2099
2100 case TGSI_SEMANTIC_VERTEXID:
2101 value = LLVMBuildAdd(ctx->ac.builder,
2102 ctx->abi.vertex_id,
2103 ctx->abi.base_vertex, "");
2104 break;
2105
2106 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2107 /* Unused. Clarify the meaning in indexed vs. non-indexed
2108 * draws if this is ever used again. */
2109 assert(false);
2110 break;
2111
2112 case TGSI_SEMANTIC_BASEVERTEX:
2113 value = get_base_vertex(&ctx->abi);
2114 break;
2115
2116 case TGSI_SEMANTIC_BASEINSTANCE:
2117 value = ctx->abi.start_instance;
2118 break;
2119
2120 case TGSI_SEMANTIC_DRAWID:
2121 value = ctx->abi.draw_id;
2122 break;
2123
2124 case TGSI_SEMANTIC_INVOCATIONID:
2125 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2126 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2127 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2128 value = ctx->abi.gs_invocation_id;
2129 else
2130 assert(!"INVOCATIONID not implemented");
2131 break;
2132
2133 case TGSI_SEMANTIC_POSITION:
2134 {
2135 LLVMValueRef pos[4] = {
2136 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2137 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2138 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2139 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2140 LLVMGetParam(ctx->main_fn,
2141 SI_PARAM_POS_W_FLOAT)),
2142 };
2143 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2144 break;
2145 }
2146
2147 case TGSI_SEMANTIC_FACE:
2148 value = ctx->abi.front_face;
2149 break;
2150
2151 case TGSI_SEMANTIC_SAMPLEID:
2152 value = get_sample_id(ctx);
2153 break;
2154
2155 case TGSI_SEMANTIC_SAMPLEPOS: {
2156 LLVMValueRef pos[4] = {
2157 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2158 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2159 LLVMConstReal(ctx->f32, 0),
2160 LLVMConstReal(ctx->f32, 0)
2161 };
2162 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2163 TGSI_OPCODE_FRC, pos[0]);
2164 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2165 TGSI_OPCODE_FRC, pos[1]);
2166 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2167 break;
2168 }
2169
2170 case TGSI_SEMANTIC_SAMPLEMASK:
2171 /* This can only occur with the OpenGL Core profile, which
2172 * doesn't support smoothing.
2173 */
2174 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2175 break;
2176
2177 case TGSI_SEMANTIC_TESSCOORD:
2178 value = si_load_tess_coord(&ctx->abi);
2179 break;
2180
2181 case TGSI_SEMANTIC_VERTICESIN:
2182 value = si_load_patch_vertices_in(&ctx->abi);
2183 break;
2184
2185 case TGSI_SEMANTIC_TESSINNER:
2186 case TGSI_SEMANTIC_TESSOUTER:
2187 value = load_tess_level(ctx, decl->Semantic.Name);
2188 break;
2189
2190 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2191 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2192 {
2193 LLVMValueRef buf, slot, val[4];
2194 int i, offset;
2195
2196 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2197 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2198 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2199 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2200
2201 for (i = 0; i < 4; i++)
2202 val[i] = buffer_load_const(ctx, buf,
2203 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2204 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2205 break;
2206 }
2207
2208 case TGSI_SEMANTIC_PRIMID:
2209 value = get_primitive_id(ctx, 0);
2210 break;
2211
2212 case TGSI_SEMANTIC_GRID_SIZE:
2213 value = ctx->abi.num_work_groups;
2214 break;
2215
2216 case TGSI_SEMANTIC_BLOCK_SIZE:
2217 value = get_block_size(&ctx->abi);
2218 break;
2219
2220 case TGSI_SEMANTIC_BLOCK_ID:
2221 {
2222 LLVMValueRef values[3];
2223
2224 for (int i = 0; i < 3; i++) {
2225 values[i] = ctx->i32_0;
2226 if (ctx->abi.workgroup_ids[i]) {
2227 values[i] = ctx->abi.workgroup_ids[i];
2228 }
2229 }
2230 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2231 break;
2232 }
2233
2234 case TGSI_SEMANTIC_THREAD_ID:
2235 value = ctx->abi.local_invocation_ids;
2236 break;
2237
2238 case TGSI_SEMANTIC_HELPER_INVOCATION:
2239 value = lp_build_intrinsic(ctx->ac.builder,
2240 "llvm.amdgcn.ps.live",
2241 ctx->i1, NULL, 0,
2242 LP_FUNC_ATTR_READNONE);
2243 value = LLVMBuildNot(ctx->ac.builder, value, "");
2244 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2245 break;
2246
2247 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2248 value = LLVMConstInt(ctx->i32, 64, 0);
2249 break;
2250
2251 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2252 value = ac_get_thread_id(&ctx->ac);
2253 break;
2254
2255 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2256 {
2257 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2258 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2259 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2260 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2261 break;
2262 }
2263
2264 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2265 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2266 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2267 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2268 {
2269 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2270 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2271 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2272 /* All bits set except LSB */
2273 value = LLVMConstInt(ctx->i64, -2, 0);
2274 } else {
2275 /* All bits set */
2276 value = LLVMConstInt(ctx->i64, -1, 0);
2277 }
2278 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2279 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2280 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2281 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2282 value = LLVMBuildNot(ctx->ac.builder, value, "");
2283 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2284 break;
2285 }
2286
2287 default:
2288 assert(!"unknown system value");
2289 return;
2290 }
2291
2292 ctx->system_values[index] = value;
2293 }
2294
2295 void si_declare_compute_memory(struct si_shader_context *ctx)
2296 {
2297 struct si_shader_selector *sel = ctx->shader->selector;
2298
2299 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2300 LLVMValueRef var;
2301
2302 assert(!ctx->ac.lds);
2303
2304 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2305 LLVMArrayType(ctx->i8, sel->local_size),
2306 "compute_lds",
2307 AC_LOCAL_ADDR_SPACE);
2308 LLVMSetAlignment(var, 4);
2309
2310 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2311 }
2312
2313 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2314 const struct tgsi_full_declaration *decl)
2315 {
2316 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2317 assert(decl->Range.First == decl->Range.Last);
2318
2319 si_declare_compute_memory(ctx);
2320 }
2321
2322 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2323 {
2324 LLVMValueRef ptr =
2325 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2326 struct si_shader_selector *sel = ctx->shader->selector;
2327
2328 /* Do the bounds checking with a descriptor, because
2329 * doing computation and manual bounds checking of 64-bit
2330 * addresses generates horrible VALU code with very high
2331 * VGPR usage and very low SIMD occupancy.
2332 */
2333 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2334
2335 LLVMValueRef desc0, desc1;
2336 if (HAVE_32BIT_POINTERS) {
2337 desc0 = ptr;
2338 desc1 = LLVMConstInt(ctx->i32,
2339 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2340 } else {
2341 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2342 desc0 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, "");
2343 desc1 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, "");
2344 /* Mask out all bits except BASE_ADDRESS_HI. */
2345 desc1 = LLVMBuildAnd(ctx->ac.builder, desc1,
2346 LLVMConstInt(ctx->i32, ~C_008F04_BASE_ADDRESS_HI, 0), "");
2347 }
2348
2349 LLVMValueRef desc_elems[] = {
2350 desc0,
2351 desc1,
2352 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2353 LLVMConstInt(ctx->i32,
2354 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2360 };
2361
2362 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2363 }
2364
2365 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2366 {
2367 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2368 ctx->param_const_and_shader_buffers);
2369
2370 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2371 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2372 }
2373
2374 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2375 {
2376 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2377 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2378
2379 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2380 index = LLVMBuildAdd(ctx->ac.builder, index,
2381 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2382
2383 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2384 }
2385
2386 static LLVMValueRef
2387 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2388 {
2389 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2390 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2391 ctx->param_const_and_shader_buffers);
2392
2393 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2394 index = LLVMBuildSub(ctx->ac.builder,
2395 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2396 index, "");
2397
2398 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2399 }
2400
2401 static LLVMValueRef fetch_constant(
2402 struct lp_build_tgsi_context *bld_base,
2403 const struct tgsi_full_src_register *reg,
2404 enum tgsi_opcode_type type,
2405 unsigned swizzle)
2406 {
2407 struct si_shader_context *ctx = si_shader_context(bld_base);
2408 struct si_shader_selector *sel = ctx->shader->selector;
2409 const struct tgsi_ind_register *ireg = &reg->Indirect;
2410 unsigned buf, idx;
2411
2412 LLVMValueRef addr, bufp;
2413
2414 if (swizzle == LP_CHAN_ALL) {
2415 unsigned chan;
2416 LLVMValueRef values[4];
2417 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2418 values[chan] = fetch_constant(bld_base, reg, type, chan);
2419
2420 return lp_build_gather_values(&ctx->gallivm, values, 4);
2421 }
2422
2423 /* Split 64-bit loads. */
2424 if (tgsi_type_is_64bit(type)) {
2425 LLVMValueRef lo, hi;
2426
2427 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2428 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2429 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2430 lo, hi);
2431 }
2432
2433 idx = reg->Register.Index * 4 + swizzle;
2434 if (reg->Register.Indirect) {
2435 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2436 } else {
2437 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2438 }
2439
2440 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2441 if (sel->info.const_buffers_declared == 1 &&
2442 sel->info.shader_buffers_declared == 0) {
2443
2444 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2445 * loads, and up to x4 load opcode merging. However, it leads to horrible
2446 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2447 *
2448 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2449 *
2450 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2451 * a descriptor and s_buffer_load_dword using it, so we can't expand
2452 * the pointer into a full descriptor like below. We have to use
2453 * s_load_dword instead. The only case when LLVM 5.0 would select
2454 * s_buffer_load_dword (that we have to prevent) is when we use use
2455 * a literal offset where we don't need bounds checking.
2456 */
2457 if (ctx->screen->info.chip_class == SI && HAVE_LLVM < 0x0600 &&
2458 !reg->Register.Indirect) {
2459 LLVMValueRef ptr =
2460 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2461
2462 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2463 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2464 return bitcast(bld_base, type, result);
2465 }
2466
2467 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2468 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2469 return bitcast(bld_base, type, result);
2470 }
2471
2472 assert(reg->Register.Dimension);
2473 buf = reg->Dimension.Index;
2474
2475 if (reg->Dimension.Indirect) {
2476 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2477 LLVMValueRef index;
2478 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2479 reg->Dimension.Index,
2480 ctx->num_const_buffers);
2481 index = LLVMBuildAdd(ctx->ac.builder, index,
2482 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2483 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2484 } else
2485 bufp = load_const_buffer_desc(ctx, buf);
2486
2487 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2488 }
2489
2490 /* Initialize arguments for the shader export intrinsic */
2491 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2492 LLVMValueRef *values,
2493 unsigned target,
2494 struct ac_export_args *args)
2495 {
2496 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2497 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2498 unsigned chan;
2499 bool is_int8, is_int10;
2500
2501 /* Default is 0xf. Adjusted below depending on the format. */
2502 args->enabled_channels = 0xf; /* writemask */
2503
2504 /* Specify whether the EXEC mask represents the valid mask */
2505 args->valid_mask = 0;
2506
2507 /* Specify whether this is the last export */
2508 args->done = 0;
2509
2510 /* Specify the target we are exporting */
2511 args->target = target;
2512
2513 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2514 const struct si_shader_key *key = &ctx->shader->key;
2515 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2516 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2517
2518 assert(cbuf >= 0 && cbuf < 8);
2519 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2520 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2521 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2522 }
2523
2524 args->compr = false;
2525 args->out[0] = f32undef;
2526 args->out[1] = f32undef;
2527 args->out[2] = f32undef;
2528 args->out[3] = f32undef;
2529
2530 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2531 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2532 unsigned bits, bool hi) = NULL;
2533
2534 switch (spi_shader_col_format) {
2535 case V_028714_SPI_SHADER_ZERO:
2536 args->enabled_channels = 0; /* writemask */
2537 args->target = V_008DFC_SQ_EXP_NULL;
2538 break;
2539
2540 case V_028714_SPI_SHADER_32_R:
2541 args->enabled_channels = 1; /* writemask */
2542 args->out[0] = values[0];
2543 break;
2544
2545 case V_028714_SPI_SHADER_32_GR:
2546 args->enabled_channels = 0x3; /* writemask */
2547 args->out[0] = values[0];
2548 args->out[1] = values[1];
2549 break;
2550
2551 case V_028714_SPI_SHADER_32_AR:
2552 args->enabled_channels = 0x9; /* writemask */
2553 args->out[0] = values[0];
2554 args->out[3] = values[3];
2555 break;
2556
2557 case V_028714_SPI_SHADER_FP16_ABGR:
2558 packf = ac_build_cvt_pkrtz_f16;
2559 break;
2560
2561 case V_028714_SPI_SHADER_UNORM16_ABGR:
2562 packf = ac_build_cvt_pknorm_u16;
2563 break;
2564
2565 case V_028714_SPI_SHADER_SNORM16_ABGR:
2566 packf = ac_build_cvt_pknorm_i16;
2567 break;
2568
2569 case V_028714_SPI_SHADER_UINT16_ABGR:
2570 packi = ac_build_cvt_pk_u16;
2571 break;
2572
2573 case V_028714_SPI_SHADER_SINT16_ABGR:
2574 packi = ac_build_cvt_pk_i16;
2575 break;
2576
2577 case V_028714_SPI_SHADER_32_ABGR:
2578 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2579 break;
2580 }
2581
2582 /* Pack f16 or norm_i16/u16. */
2583 if (packf) {
2584 for (chan = 0; chan < 2; chan++) {
2585 LLVMValueRef pack_args[2] = {
2586 values[2 * chan],
2587 values[2 * chan + 1]
2588 };
2589 LLVMValueRef packed;
2590
2591 packed = packf(&ctx->ac, pack_args);
2592 args->out[chan] = ac_to_float(&ctx->ac, packed);
2593 }
2594 args->compr = 1; /* COMPR flag */
2595 }
2596 /* Pack i16/u16. */
2597 if (packi) {
2598 for (chan = 0; chan < 2; chan++) {
2599 LLVMValueRef pack_args[2] = {
2600 ac_to_integer(&ctx->ac, values[2 * chan]),
2601 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2602 };
2603 LLVMValueRef packed;
2604
2605 packed = packi(&ctx->ac, pack_args,
2606 is_int8 ? 8 : is_int10 ? 10 : 16,
2607 chan == 1);
2608 args->out[chan] = ac_to_float(&ctx->ac, packed);
2609 }
2610 args->compr = 1; /* COMPR flag */
2611 }
2612 }
2613
2614 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2615 LLVMValueRef alpha)
2616 {
2617 struct si_shader_context *ctx = si_shader_context(bld_base);
2618
2619 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2620 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2621 [PIPE_FUNC_LESS] = LLVMRealOLT,
2622 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2623 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2624 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2625 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2626 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2627 };
2628 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2629 assert(cond);
2630
2631 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2632 SI_PARAM_ALPHA_REF);
2633 LLVMValueRef alpha_pass =
2634 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2635 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2636 } else {
2637 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2638 }
2639 }
2640
2641 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2642 LLVMValueRef alpha,
2643 unsigned samplemask_param)
2644 {
2645 struct si_shader_context *ctx = si_shader_context(bld_base);
2646 LLVMValueRef coverage;
2647
2648 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2649 coverage = LLVMGetParam(ctx->main_fn,
2650 samplemask_param);
2651 coverage = ac_to_integer(&ctx->ac, coverage);
2652
2653 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2654 ctx->i32,
2655 &coverage, 1, LP_FUNC_ATTR_READNONE);
2656
2657 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2658 ctx->f32, "");
2659
2660 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2661 LLVMConstReal(ctx->f32,
2662 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2663
2664 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2665 }
2666
2667 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2668 struct ac_export_args *pos, LLVMValueRef *out_elts)
2669 {
2670 unsigned reg_index;
2671 unsigned chan;
2672 unsigned const_chan;
2673 LLVMValueRef base_elt;
2674 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2675 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2676 SI_VS_CONST_CLIP_PLANES, 0);
2677 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2678
2679 for (reg_index = 0; reg_index < 2; reg_index ++) {
2680 struct ac_export_args *args = &pos[2 + reg_index];
2681
2682 args->out[0] =
2683 args->out[1] =
2684 args->out[2] =
2685 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2686
2687 /* Compute dot products of position and user clip plane vectors */
2688 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2689 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2690 LLVMValueRef addr =
2691 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2692 const_chan) * 4, 0);
2693 base_elt = buffer_load_const(ctx, const_resource,
2694 addr);
2695 args->out[chan] =
2696 lp_build_add(&ctx->bld_base.base, args->out[chan],
2697 lp_build_mul(&ctx->bld_base.base, base_elt,
2698 out_elts[const_chan]));
2699 }
2700 }
2701
2702 args->enabled_channels = 0xf;
2703 args->valid_mask = 0;
2704 args->done = 0;
2705 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2706 args->compr = 0;
2707 }
2708 }
2709
2710 static void si_dump_streamout(struct pipe_stream_output_info *so)
2711 {
2712 unsigned i;
2713
2714 if (so->num_outputs)
2715 fprintf(stderr, "STREAMOUT\n");
2716
2717 for (i = 0; i < so->num_outputs; i++) {
2718 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2719 so->output[i].start_component;
2720 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2721 i, so->output[i].output_buffer,
2722 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2723 so->output[i].register_index,
2724 mask & 1 ? "x" : "",
2725 mask & 2 ? "y" : "",
2726 mask & 4 ? "z" : "",
2727 mask & 8 ? "w" : "");
2728 }
2729 }
2730
2731 static void emit_streamout_output(struct si_shader_context *ctx,
2732 LLVMValueRef const *so_buffers,
2733 LLVMValueRef const *so_write_offsets,
2734 struct pipe_stream_output *stream_out,
2735 struct si_shader_output_values *shader_out)
2736 {
2737 unsigned buf_idx = stream_out->output_buffer;
2738 unsigned start = stream_out->start_component;
2739 unsigned num_comps = stream_out->num_components;
2740 LLVMValueRef out[4];
2741
2742 assert(num_comps && num_comps <= 4);
2743 if (!num_comps || num_comps > 4)
2744 return;
2745
2746 /* Load the output as int. */
2747 for (int j = 0; j < num_comps; j++) {
2748 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2749
2750 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2751 }
2752
2753 /* Pack the output. */
2754 LLVMValueRef vdata = NULL;
2755
2756 switch (num_comps) {
2757 case 1: /* as i32 */
2758 vdata = out[0];
2759 break;
2760 case 2: /* as v2i32 */
2761 case 3: /* as v4i32 (aligned to 4) */
2762 case 4: /* as v4i32 */
2763 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2764 for (int j = 0; j < num_comps; j++) {
2765 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2766 LLVMConstInt(ctx->i32, j, 0), "");
2767 }
2768 break;
2769 }
2770
2771 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2772 vdata, num_comps,
2773 so_write_offsets[buf_idx],
2774 ctx->i32_0,
2775 stream_out->dst_offset * 4, 1, 1, true, false);
2776 }
2777
2778 /**
2779 * Write streamout data to buffers for vertex stream @p stream (different
2780 * vertex streams can occur for GS copy shaders).
2781 */
2782 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2783 struct si_shader_output_values *outputs,
2784 unsigned noutput, unsigned stream)
2785 {
2786 struct si_shader_selector *sel = ctx->shader->selector;
2787 struct pipe_stream_output_info *so = &sel->so;
2788 LLVMBuilderRef builder = ctx->ac.builder;
2789 int i;
2790 struct lp_build_if_state if_ctx;
2791
2792 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2793 LLVMValueRef so_vtx_count =
2794 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2795
2796 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2797
2798 /* can_emit = tid < so_vtx_count; */
2799 LLVMValueRef can_emit =
2800 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2801
2802 /* Emit the streamout code conditionally. This actually avoids
2803 * out-of-bounds buffer access. The hw tells us via the SGPR
2804 * (so_vtx_count) which threads are allowed to emit streamout data. */
2805 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2806 {
2807 /* The buffer offset is computed as follows:
2808 * ByteOffset = streamout_offset[buffer_id]*4 +
2809 * (streamout_write_index + thread_id)*stride[buffer_id] +
2810 * attrib_offset
2811 */
2812
2813 LLVMValueRef so_write_index =
2814 LLVMGetParam(ctx->main_fn,
2815 ctx->param_streamout_write_index);
2816
2817 /* Compute (streamout_write_index + thread_id). */
2818 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2819
2820 /* Load the descriptor and compute the write offset for each
2821 * enabled buffer. */
2822 LLVMValueRef so_write_offset[4] = {};
2823 LLVMValueRef so_buffers[4];
2824 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2825 ctx->param_rw_buffers);
2826
2827 for (i = 0; i < 4; i++) {
2828 if (!so->stride[i])
2829 continue;
2830
2831 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2832 SI_VS_STREAMOUT_BUF0 + i, 0);
2833
2834 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2835
2836 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2837 ctx->param_streamout_offset[i]);
2838 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2839
2840 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2841 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2842 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2843 }
2844
2845 /* Write streamout data. */
2846 for (i = 0; i < so->num_outputs; i++) {
2847 unsigned reg = so->output[i].register_index;
2848
2849 if (reg >= noutput)
2850 continue;
2851
2852 if (stream != so->output[i].stream)
2853 continue;
2854
2855 emit_streamout_output(ctx, so_buffers, so_write_offset,
2856 &so->output[i], &outputs[reg]);
2857 }
2858 }
2859 lp_build_endif(&if_ctx);
2860 }
2861
2862 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2863 LLVMValueRef *values)
2864 {
2865 struct ac_export_args args;
2866
2867 si_llvm_init_export_args(ctx, values,
2868 V_008DFC_SQ_EXP_PARAM + index, &args);
2869 ac_build_export(&ctx->ac, &args);
2870 }
2871
2872 static void si_build_param_exports(struct si_shader_context *ctx,
2873 struct si_shader_output_values *outputs,
2874 unsigned noutput)
2875 {
2876 struct si_shader *shader = ctx->shader;
2877 unsigned param_count = 0;
2878
2879 for (unsigned i = 0; i < noutput; i++) {
2880 unsigned semantic_name = outputs[i].semantic_name;
2881 unsigned semantic_index = outputs[i].semantic_index;
2882
2883 if (outputs[i].vertex_stream[0] != 0 &&
2884 outputs[i].vertex_stream[1] != 0 &&
2885 outputs[i].vertex_stream[2] != 0 &&
2886 outputs[i].vertex_stream[3] != 0)
2887 continue;
2888
2889 switch (semantic_name) {
2890 case TGSI_SEMANTIC_LAYER:
2891 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2892 case TGSI_SEMANTIC_CLIPDIST:
2893 case TGSI_SEMANTIC_COLOR:
2894 case TGSI_SEMANTIC_BCOLOR:
2895 case TGSI_SEMANTIC_PRIMID:
2896 case TGSI_SEMANTIC_FOG:
2897 case TGSI_SEMANTIC_TEXCOORD:
2898 case TGSI_SEMANTIC_GENERIC:
2899 break;
2900 default:
2901 continue;
2902 }
2903
2904 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2905 semantic_index < SI_MAX_IO_GENERIC) &&
2906 shader->key.opt.kill_outputs &
2907 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2908 continue;
2909
2910 si_export_param(ctx, param_count, outputs[i].values);
2911
2912 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2913 shader->info.vs_output_param_offset[i] = param_count++;
2914 }
2915
2916 shader->info.nr_param_exports = param_count;
2917 }
2918
2919 /* Generate export instructions for hardware VS shader stage */
2920 static void si_llvm_export_vs(struct si_shader_context *ctx,
2921 struct si_shader_output_values *outputs,
2922 unsigned noutput)
2923 {
2924 struct si_shader *shader = ctx->shader;
2925 struct ac_export_args pos_args[4] = {};
2926 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2927 unsigned pos_idx;
2928 int i;
2929
2930 /* Build position exports. */
2931 for (i = 0; i < noutput; i++) {
2932 switch (outputs[i].semantic_name) {
2933 case TGSI_SEMANTIC_POSITION:
2934 si_llvm_init_export_args(ctx, outputs[i].values,
2935 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2936 break;
2937 case TGSI_SEMANTIC_PSIZE:
2938 psize_value = outputs[i].values[0];
2939 break;
2940 case TGSI_SEMANTIC_LAYER:
2941 layer_value = outputs[i].values[0];
2942 break;
2943 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2944 viewport_index_value = outputs[i].values[0];
2945 break;
2946 case TGSI_SEMANTIC_EDGEFLAG:
2947 edgeflag_value = outputs[i].values[0];
2948 break;
2949 case TGSI_SEMANTIC_CLIPDIST:
2950 if (!shader->key.opt.clip_disable) {
2951 unsigned index = 2 + outputs[i].semantic_index;
2952 si_llvm_init_export_args(ctx, outputs[i].values,
2953 V_008DFC_SQ_EXP_POS + index,
2954 &pos_args[index]);
2955 }
2956 break;
2957 case TGSI_SEMANTIC_CLIPVERTEX:
2958 if (!shader->key.opt.clip_disable) {
2959 si_llvm_emit_clipvertex(ctx, pos_args,
2960 outputs[i].values);
2961 }
2962 break;
2963 }
2964 }
2965
2966 /* We need to add the position output manually if it's missing. */
2967 if (!pos_args[0].out[0]) {
2968 pos_args[0].enabled_channels = 0xf; /* writemask */
2969 pos_args[0].valid_mask = 0; /* EXEC mask */
2970 pos_args[0].done = 0; /* last export? */
2971 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2972 pos_args[0].compr = 0; /* COMPR flag */
2973 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2974 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2975 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2976 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2977 }
2978
2979 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2980 if (shader->selector->info.writes_psize ||
2981 shader->selector->info.writes_edgeflag ||
2982 shader->selector->info.writes_viewport_index ||
2983 shader->selector->info.writes_layer) {
2984 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2985 (shader->selector->info.writes_edgeflag << 1) |
2986 (shader->selector->info.writes_layer << 2);
2987
2988 pos_args[1].valid_mask = 0; /* EXEC mask */
2989 pos_args[1].done = 0; /* last export? */
2990 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2991 pos_args[1].compr = 0; /* COMPR flag */
2992 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2993 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2994 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2995 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2996
2997 if (shader->selector->info.writes_psize)
2998 pos_args[1].out[0] = psize_value;
2999
3000 if (shader->selector->info.writes_edgeflag) {
3001 /* The output is a float, but the hw expects an integer
3002 * with the first bit containing the edge flag. */
3003 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
3004 edgeflag_value,
3005 ctx->i32, "");
3006 edgeflag_value = ac_build_umin(&ctx->ac,
3007 edgeflag_value,
3008 ctx->i32_1);
3009
3010 /* The LLVM intrinsic expects a float. */
3011 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3012 }
3013
3014 if (ctx->screen->info.chip_class >= GFX9) {
3015 /* GFX9 has the layer in out.z[10:0] and the viewport
3016 * index in out.z[19:16].
3017 */
3018 if (shader->selector->info.writes_layer)
3019 pos_args[1].out[2] = layer_value;
3020
3021 if (shader->selector->info.writes_viewport_index) {
3022 LLVMValueRef v = viewport_index_value;
3023
3024 v = ac_to_integer(&ctx->ac, v);
3025 v = LLVMBuildShl(ctx->ac.builder, v,
3026 LLVMConstInt(ctx->i32, 16, 0), "");
3027 v = LLVMBuildOr(ctx->ac.builder, v,
3028 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3029 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3030 pos_args[1].enabled_channels |= 1 << 2;
3031 }
3032 } else {
3033 if (shader->selector->info.writes_layer)
3034 pos_args[1].out[2] = layer_value;
3035
3036 if (shader->selector->info.writes_viewport_index) {
3037 pos_args[1].out[3] = viewport_index_value;
3038 pos_args[1].enabled_channels |= 1 << 3;
3039 }
3040 }
3041 }
3042
3043 for (i = 0; i < 4; i++)
3044 if (pos_args[i].out[0])
3045 shader->info.nr_pos_exports++;
3046
3047 pos_idx = 0;
3048 for (i = 0; i < 4; i++) {
3049 if (!pos_args[i].out[0])
3050 continue;
3051
3052 /* Specify the target we are exporting */
3053 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3054
3055 if (pos_idx == shader->info.nr_pos_exports)
3056 /* Specify that this is the last export */
3057 pos_args[i].done = 1;
3058
3059 ac_build_export(&ctx->ac, &pos_args[i]);
3060 }
3061
3062 /* Build parameter exports. */
3063 si_build_param_exports(ctx, outputs, noutput);
3064 }
3065
3066 /**
3067 * Forward all outputs from the vertex shader to the TES. This is only used
3068 * for the fixed function TCS.
3069 */
3070 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3071 {
3072 struct si_shader_context *ctx = si_shader_context(bld_base);
3073 LLVMValueRef invocation_id, buffer, buffer_offset;
3074 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3075 uint64_t inputs;
3076
3077 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3078 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3079 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3080
3081 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3082 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3083 lds_vertex_stride, "");
3084 lds_base = get_tcs_in_current_patch_offset(ctx);
3085 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3086
3087 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3088 while (inputs) {
3089 unsigned i = u_bit_scan64(&inputs);
3090
3091 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3092 LLVMConstInt(ctx->i32, 4 * i, 0),
3093 "");
3094
3095 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3096 get_rel_patch_id(ctx),
3097 invocation_id,
3098 LLVMConstInt(ctx->i32, i, 0));
3099
3100 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3101 lds_ptr);
3102
3103 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3104 buffer_offset, 0, 1, 0, true, false);
3105 }
3106 }
3107
3108 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3109 LLVMValueRef rel_patch_id,
3110 LLVMValueRef invocation_id,
3111 LLVMValueRef tcs_out_current_patch_data_offset,
3112 LLVMValueRef invoc0_tf_outer[4],
3113 LLVMValueRef invoc0_tf_inner[2])
3114 {
3115 struct si_shader_context *ctx = si_shader_context(bld_base);
3116 struct si_shader *shader = ctx->shader;
3117 unsigned tess_inner_index, tess_outer_index;
3118 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3119 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3120 unsigned stride, outer_comps, inner_comps, i, offset;
3121 struct lp_build_if_state if_ctx, inner_if_ctx;
3122
3123 /* Add a barrier before loading tess factors from LDS. */
3124 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3125 si_llvm_emit_barrier(NULL, bld_base, NULL);
3126
3127 /* Do this only for invocation 0, because the tess levels are per-patch,
3128 * not per-vertex.
3129 *
3130 * This can't jump, because invocation 0 executes this. It should
3131 * at least mask out the loads and stores for other invocations.
3132 */
3133 lp_build_if(&if_ctx, &ctx->gallivm,
3134 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3135 invocation_id, ctx->i32_0, ""));
3136
3137 /* Determine the layout of one tess factor element in the buffer. */
3138 switch (shader->key.part.tcs.epilog.prim_mode) {
3139 case PIPE_PRIM_LINES:
3140 stride = 2; /* 2 dwords, 1 vec2 store */
3141 outer_comps = 2;
3142 inner_comps = 0;
3143 break;
3144 case PIPE_PRIM_TRIANGLES:
3145 stride = 4; /* 4 dwords, 1 vec4 store */
3146 outer_comps = 3;
3147 inner_comps = 1;
3148 break;
3149 case PIPE_PRIM_QUADS:
3150 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3151 outer_comps = 4;
3152 inner_comps = 2;
3153 break;
3154 default:
3155 assert(0);
3156 return;
3157 }
3158
3159 for (i = 0; i < 4; i++) {
3160 inner[i] = LLVMGetUndef(ctx->i32);
3161 outer[i] = LLVMGetUndef(ctx->i32);
3162 }
3163
3164 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3165 /* Tess factors are in VGPRs. */
3166 for (i = 0; i < outer_comps; i++)
3167 outer[i] = out[i] = invoc0_tf_outer[i];
3168 for (i = 0; i < inner_comps; i++)
3169 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3170 } else {
3171 /* Load tess_inner and tess_outer from LDS.
3172 * Any invocation can write them, so we can't get them from a temporary.
3173 */
3174 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3175 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3176
3177 lds_base = tcs_out_current_patch_data_offset;
3178 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3179 LLVMConstInt(ctx->i32,
3180 tess_inner_index * 4, 0), "");
3181 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3182 LLVMConstInt(ctx->i32,
3183 tess_outer_index * 4, 0), "");
3184
3185 for (i = 0; i < outer_comps; i++) {
3186 outer[i] = out[i] =
3187 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3188 }
3189 for (i = 0; i < inner_comps; i++) {
3190 inner[i] = out[outer_comps+i] =
3191 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3192 }
3193 }
3194
3195 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3196 /* For isolines, the hardware expects tess factors in the
3197 * reverse order from what GLSL / TGSI specify.
3198 */
3199 LLVMValueRef tmp = out[0];
3200 out[0] = out[1];
3201 out[1] = tmp;
3202 }
3203
3204 /* Convert the outputs to vectors for stores. */
3205 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3206 vec1 = NULL;
3207
3208 if (stride > 4)
3209 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3210
3211 /* Get the buffer. */
3212 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3213
3214 /* Get the offset. */
3215 tf_base = LLVMGetParam(ctx->main_fn,
3216 ctx->param_tcs_factor_offset);
3217 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3218 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3219
3220 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3221 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3222 rel_patch_id, ctx->i32_0, ""));
3223
3224 /* Store the dynamic HS control word. */
3225 offset = 0;
3226 if (ctx->screen->info.chip_class <= VI) {
3227 ac_build_buffer_store_dword(&ctx->ac, buffer,
3228 LLVMConstInt(ctx->i32, 0x80000000, 0),
3229 1, ctx->i32_0, tf_base,
3230 offset, 1, 0, true, false);
3231 offset += 4;
3232 }
3233
3234 lp_build_endif(&inner_if_ctx);
3235
3236 /* Store the tessellation factors. */
3237 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3238 MIN2(stride, 4), byteoffset, tf_base,
3239 offset, 1, 0, true, false);
3240 offset += 16;
3241 if (vec1)
3242 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3243 stride - 4, byteoffset, tf_base,
3244 offset, 1, 0, true, false);
3245
3246 /* Store the tess factors into the offchip buffer if TES reads them. */
3247 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3248 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3249 LLVMValueRef tf_inner_offset;
3250 unsigned param_outer, param_inner;
3251
3252 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3253 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3254
3255 param_outer = si_shader_io_get_unique_index_patch(
3256 TGSI_SEMANTIC_TESSOUTER, 0);
3257 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3258 LLVMConstInt(ctx->i32, param_outer, 0));
3259
3260 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3261 util_next_power_of_two(outer_comps));
3262
3263 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3264 outer_comps, tf_outer_offset,
3265 base, 0, 1, 0, true, false);
3266 if (inner_comps) {
3267 param_inner = si_shader_io_get_unique_index_patch(
3268 TGSI_SEMANTIC_TESSINNER, 0);
3269 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3270 LLVMConstInt(ctx->i32, param_inner, 0));
3271
3272 inner_vec = inner_comps == 1 ? inner[0] :
3273 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3274 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3275 inner_comps, tf_inner_offset,
3276 base, 0, 1, 0, true, false);
3277 }
3278 }
3279
3280 lp_build_endif(&if_ctx);
3281 }
3282
3283 static LLVMValueRef
3284 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3285 unsigned param, unsigned return_index)
3286 {
3287 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3288 LLVMGetParam(ctx->main_fn, param),
3289 return_index, "");
3290 }
3291
3292 static LLVMValueRef
3293 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3294 unsigned param, unsigned return_index)
3295 {
3296 LLVMBuilderRef builder = ctx->ac.builder;
3297 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3298
3299 return LLVMBuildInsertValue(builder, ret,
3300 ac_to_float(&ctx->ac, p),
3301 return_index, "");
3302 }
3303
3304 static LLVMValueRef
3305 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3306 unsigned param, unsigned return_index)
3307 {
3308 LLVMBuilderRef builder = ctx->ac.builder;
3309 LLVMValueRef ptr, lo, hi;
3310
3311 if (HAVE_32BIT_POINTERS) {
3312 ptr = LLVMGetParam(ctx->main_fn, param);
3313 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3314 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3315 }
3316
3317 ptr = LLVMGetParam(ctx->main_fn, param);
3318 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3319 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3320 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3321 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3322 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3323 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3324 }
3325
3326 /* This only writes the tessellation factor levels. */
3327 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3328 unsigned max_outputs,
3329 LLVMValueRef *addrs)
3330 {
3331 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3332 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3333 LLVMBuilderRef builder = ctx->ac.builder;
3334 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3335
3336 si_copy_tcs_inputs(bld_base);
3337
3338 rel_patch_id = get_rel_patch_id(ctx);
3339 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3340 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3341
3342 if (ctx->screen->info.chip_class >= GFX9) {
3343 LLVMBasicBlockRef blocks[2] = {
3344 LLVMGetInsertBlock(builder),
3345 ctx->merged_wrap_if_state.entry_block
3346 };
3347 LLVMValueRef values[2];
3348
3349 lp_build_endif(&ctx->merged_wrap_if_state);
3350
3351 values[0] = rel_patch_id;
3352 values[1] = LLVMGetUndef(ctx->i32);
3353 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3354
3355 values[0] = tf_lds_offset;
3356 values[1] = LLVMGetUndef(ctx->i32);
3357 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3358
3359 values[0] = invocation_id;
3360 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3361 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3362 }
3363
3364 /* Return epilog parameters from this function. */
3365 LLVMValueRef ret = ctx->return_value;
3366 unsigned vgpr;
3367
3368 if (ctx->screen->info.chip_class >= GFX9) {
3369 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3370 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3372 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3373 /* Tess offchip and tess factor offsets are at the beginning. */
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3376 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3377 } else {
3378 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3379 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3380 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3381 GFX6_SGPR_TCS_OUT_LAYOUT);
3382 /* Tess offchip and tess factor offsets are after user SGPRs. */
3383 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3384 GFX6_TCS_NUM_USER_SGPR);
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3386 GFX6_TCS_NUM_USER_SGPR + 1);
3387 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3388 }
3389
3390 /* VGPRs */
3391 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3392 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3393 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3394
3395 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3396 * the invocation_id output does not alias the tcs_rel_ids input,
3397 * which saves a V_MOV on gfx9.
3398 */
3399 vgpr += 2;
3400
3401 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3402 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3403
3404 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3405 vgpr++; /* skip the tess factor LDS offset */
3406 for (unsigned i = 0; i < 6; i++) {
3407 LLVMValueRef value =
3408 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3409 value = ac_to_float(&ctx->ac, value);
3410 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3411 }
3412 } else {
3413 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3414 }
3415 ctx->return_value = ret;
3416 }
3417
3418 /* Pass TCS inputs from LS to TCS on GFX9. */
3419 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3420 {
3421 LLVMValueRef ret = ctx->return_value;
3422
3423 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3424 if (HAVE_32BIT_POINTERS)
3425 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3426 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3428 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3429 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3430
3431 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3432 8 + SI_SGPR_RW_BUFFERS);
3433 ret = si_insert_input_ptr(ctx, ret,
3434 ctx->param_bindless_samplers_and_images,
3435 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3436
3437 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3438 8 + SI_SGPR_VS_STATE_BITS);
3439
3440 #if !HAVE_32BIT_POINTERS
3441 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3442 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3443 #endif
3444
3445 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3446 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3447 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3448 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3449 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3450 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3451
3452 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3453 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3454 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3455 vgpr++, "");
3456 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3457 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3458 vgpr++, "");
3459 ctx->return_value = ret;
3460 }
3461
3462 /* Pass GS inputs from ES to GS on GFX9. */
3463 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3464 {
3465 LLVMValueRef ret = ctx->return_value;
3466
3467 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3468 if (HAVE_32BIT_POINTERS)
3469 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3470 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3471 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3472 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3473
3474 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3475 8 + SI_SGPR_RW_BUFFERS);
3476 ret = si_insert_input_ptr(ctx, ret,
3477 ctx->param_bindless_samplers_and_images,
3478 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3479
3480 #if !HAVE_32BIT_POINTERS
3481 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3482 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3483 #endif
3484
3485 unsigned vgpr;
3486 if (ctx->type == PIPE_SHADER_VERTEX)
3487 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3488 else
3489 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3490
3491 for (unsigned i = 0; i < 5; i++) {
3492 unsigned param = ctx->param_gs_vtx01_offset + i;
3493 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3494 }
3495 ctx->return_value = ret;
3496 }
3497
3498 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3499 unsigned max_outputs,
3500 LLVMValueRef *addrs)
3501 {
3502 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3503 struct si_shader *shader = ctx->shader;
3504 struct tgsi_shader_info *info = &shader->selector->info;
3505 unsigned i, chan;
3506 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3507 ctx->param_rel_auto_id);
3508 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3509 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3510 vertex_dw_stride, "");
3511
3512 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3513 * its inputs from it. */
3514 for (i = 0; i < info->num_outputs; i++) {
3515 unsigned name = info->output_semantic_name[i];
3516 unsigned index = info->output_semantic_index[i];
3517
3518 /* The ARB_shader_viewport_layer_array spec contains the
3519 * following issue:
3520 *
3521 * 2) What happens if gl_ViewportIndex or gl_Layer is
3522 * written in the vertex shader and a geometry shader is
3523 * present?
3524 *
3525 * RESOLVED: The value written by the last vertex processing
3526 * stage is used. If the last vertex processing stage
3527 * (vertex, tessellation evaluation or geometry) does not
3528 * statically assign to gl_ViewportIndex or gl_Layer, index
3529 * or layer zero is assumed.
3530 *
3531 * So writes to those outputs in VS-as-LS are simply ignored.
3532 */
3533 if (name == TGSI_SEMANTIC_LAYER ||
3534 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3535 continue;
3536
3537 int param = si_shader_io_get_unique_index(name, index);
3538 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3539 LLVMConstInt(ctx->i32, param * 4, 0), "");
3540
3541 for (chan = 0; chan < 4; chan++) {
3542 if (!(info->output_usagemask[i] & (1 << chan)))
3543 continue;
3544
3545 lds_store(ctx, chan, dw_addr,
3546 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3547 }
3548 }
3549
3550 if (ctx->screen->info.chip_class >= GFX9)
3551 si_set_ls_return_value_for_tcs(ctx);
3552 }
3553
3554 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3555 unsigned max_outputs,
3556 LLVMValueRef *addrs)
3557 {
3558 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3559 struct si_shader *es = ctx->shader;
3560 struct tgsi_shader_info *info = &es->selector->info;
3561 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3562 ctx->param_es2gs_offset);
3563 LLVMValueRef lds_base = NULL;
3564 unsigned chan;
3565 int i;
3566
3567 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3568 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3569 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3570 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3571 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3572 LLVMBuildMul(ctx->ac.builder, wave_idx,
3573 LLVMConstInt(ctx->i32, 64, false), ""), "");
3574 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3575 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3576 }
3577
3578 for (i = 0; i < info->num_outputs; i++) {
3579 int param;
3580
3581 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3582 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3583 continue;
3584
3585 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3586 info->output_semantic_index[i]);
3587
3588 for (chan = 0; chan < 4; chan++) {
3589 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3590 out_val = ac_to_integer(&ctx->ac, out_val);
3591
3592 /* GFX9 has the ESGS ring in LDS. */
3593 if (ctx->screen->info.chip_class >= GFX9) {
3594 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3595 continue;
3596 }
3597
3598 ac_build_buffer_store_dword(&ctx->ac,
3599 ctx->esgs_ring,
3600 out_val, 1, NULL, soffset,
3601 (4 * param + chan) * 4,
3602 1, 1, true, true);
3603 }
3604 }
3605
3606 if (ctx->screen->info.chip_class >= GFX9)
3607 si_set_es_return_value_for_gs(ctx);
3608 }
3609
3610 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3611 {
3612 if (ctx->screen->info.chip_class >= GFX9)
3613 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3614 else
3615 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3616 }
3617
3618 static void emit_gs_epilogue(struct si_shader_context *ctx)
3619 {
3620 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3621 si_get_gs_wave_id(ctx));
3622
3623 if (ctx->screen->info.chip_class >= GFX9)
3624 lp_build_endif(&ctx->merged_wrap_if_state);
3625 }
3626
3627 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3628 unsigned max_outputs,
3629 LLVMValueRef *addrs)
3630 {
3631 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3632 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3633
3634 assert(info->num_outputs <= max_outputs);
3635
3636 emit_gs_epilogue(ctx);
3637 }
3638
3639 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3640 {
3641 struct si_shader_context *ctx = si_shader_context(bld_base);
3642 emit_gs_epilogue(ctx);
3643 }
3644
3645 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3646 unsigned max_outputs,
3647 LLVMValueRef *addrs)
3648 {
3649 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3650 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3651 struct si_shader_output_values *outputs = NULL;
3652 int i,j;
3653
3654 assert(!ctx->shader->is_gs_copy_shader);
3655 assert(info->num_outputs <= max_outputs);
3656
3657 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3658
3659 /* Vertex color clamping.
3660 *
3661 * This uses a state constant loaded in a user data SGPR and
3662 * an IF statement is added that clamps all colors if the constant
3663 * is true.
3664 */
3665 if (ctx->type == PIPE_SHADER_VERTEX) {
3666 struct lp_build_if_state if_ctx;
3667 LLVMValueRef cond = NULL;
3668 LLVMValueRef addr, val;
3669
3670 for (i = 0; i < info->num_outputs; i++) {
3671 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3672 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3673 continue;
3674
3675 /* We've found a color. */
3676 if (!cond) {
3677 /* The state is in the first bit of the user SGPR. */
3678 cond = LLVMGetParam(ctx->main_fn,
3679 ctx->param_vs_state_bits);
3680 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3681 ctx->i1, "");
3682 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3683 }
3684
3685 for (j = 0; j < 4; j++) {
3686 addr = addrs[4 * i + j];
3687 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3688 val = ac_build_clamp(&ctx->ac, val);
3689 LLVMBuildStore(ctx->ac.builder, val, addr);
3690 }
3691 }
3692
3693 if (cond)
3694 lp_build_endif(&if_ctx);
3695 }
3696
3697 for (i = 0; i < info->num_outputs; i++) {
3698 outputs[i].semantic_name = info->output_semantic_name[i];
3699 outputs[i].semantic_index = info->output_semantic_index[i];
3700
3701 for (j = 0; j < 4; j++) {
3702 outputs[i].values[j] =
3703 LLVMBuildLoad(ctx->ac.builder,
3704 addrs[4 * i + j],
3705 "");
3706 outputs[i].vertex_stream[j] =
3707 (info->output_streams[i] >> (2 * j)) & 3;
3708 }
3709 }
3710
3711 if (ctx->shader->selector->so.num_outputs)
3712 si_llvm_emit_streamout(ctx, outputs, i, 0);
3713
3714 /* Export PrimitiveID. */
3715 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3716 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3717 outputs[i].semantic_index = 0;
3718 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3719 for (j = 1; j < 4; j++)
3720 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3721
3722 memset(outputs[i].vertex_stream, 0,
3723 sizeof(outputs[i].vertex_stream));
3724 i++;
3725 }
3726
3727 si_llvm_export_vs(ctx, outputs, i);
3728 FREE(outputs);
3729 }
3730
3731 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3732 {
3733 struct si_shader_context *ctx = si_shader_context(bld_base);
3734
3735 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3736 &ctx->outputs[0][0]);
3737 }
3738
3739 struct si_ps_exports {
3740 unsigned num;
3741 struct ac_export_args args[10];
3742 };
3743
3744 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3745 LLVMValueRef depth, LLVMValueRef stencil,
3746 LLVMValueRef samplemask, struct si_ps_exports *exp)
3747 {
3748 struct si_shader_context *ctx = si_shader_context(bld_base);
3749 struct ac_export_args args;
3750
3751 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3752
3753 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3754 }
3755
3756 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3757 LLVMValueRef *color, unsigned index,
3758 unsigned samplemask_param,
3759 bool is_last, struct si_ps_exports *exp)
3760 {
3761 struct si_shader_context *ctx = si_shader_context(bld_base);
3762 int i;
3763
3764 /* Clamp color */
3765 if (ctx->shader->key.part.ps.epilog.clamp_color)
3766 for (i = 0; i < 4; i++)
3767 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3768
3769 /* Alpha to one */
3770 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3771 color[3] = ctx->ac.f32_1;
3772
3773 /* Alpha test */
3774 if (index == 0 &&
3775 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3776 si_alpha_test(bld_base, color[3]);
3777
3778 /* Line & polygon smoothing */
3779 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3780 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3781 samplemask_param);
3782
3783 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3784 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3785 struct ac_export_args args[8];
3786 int c, last = -1;
3787
3788 /* Get the export arguments, also find out what the last one is. */
3789 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3790 si_llvm_init_export_args(ctx, color,
3791 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3792 if (args[c].enabled_channels)
3793 last = c;
3794 }
3795
3796 /* Emit all exports. */
3797 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3798 if (is_last && last == c) {
3799 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3800 args[c].done = 1; /* DONE bit */
3801 } else if (!args[c].enabled_channels)
3802 continue; /* unnecessary NULL export */
3803
3804 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3805 }
3806 } else {
3807 struct ac_export_args args;
3808
3809 /* Export */
3810 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3811 &args);
3812 if (is_last) {
3813 args.valid_mask = 1; /* whether the EXEC mask is valid */
3814 args.done = 1; /* DONE bit */
3815 } else if (!args.enabled_channels)
3816 return; /* unnecessary NULL export */
3817
3818 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3819 }
3820 }
3821
3822 static void si_emit_ps_exports(struct si_shader_context *ctx,
3823 struct si_ps_exports *exp)
3824 {
3825 for (unsigned i = 0; i < exp->num; i++)
3826 ac_build_export(&ctx->ac, &exp->args[i]);
3827 }
3828
3829 /**
3830 * Return PS outputs in this order:
3831 *
3832 * v[0:3] = color0.xyzw
3833 * v[4:7] = color1.xyzw
3834 * ...
3835 * vN+0 = Depth
3836 * vN+1 = Stencil
3837 * vN+2 = SampleMask
3838 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3839 *
3840 * The alpha-ref SGPR is returned via its original location.
3841 */
3842 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3843 unsigned max_outputs,
3844 LLVMValueRef *addrs)
3845 {
3846 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3847 struct si_shader *shader = ctx->shader;
3848 struct tgsi_shader_info *info = &shader->selector->info;
3849 LLVMBuilderRef builder = ctx->ac.builder;
3850 unsigned i, j, first_vgpr, vgpr;
3851
3852 LLVMValueRef color[8][4] = {};
3853 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3854 LLVMValueRef ret;
3855
3856 if (ctx->postponed_kill)
3857 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3858
3859 /* Read the output values. */
3860 for (i = 0; i < info->num_outputs; i++) {
3861 unsigned semantic_name = info->output_semantic_name[i];
3862 unsigned semantic_index = info->output_semantic_index[i];
3863
3864 switch (semantic_name) {
3865 case TGSI_SEMANTIC_COLOR:
3866 assert(semantic_index < 8);
3867 for (j = 0; j < 4; j++) {
3868 LLVMValueRef ptr = addrs[4 * i + j];
3869 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3870 color[semantic_index][j] = result;
3871 }
3872 break;
3873 case TGSI_SEMANTIC_POSITION:
3874 depth = LLVMBuildLoad(builder,
3875 addrs[4 * i + 2], "");
3876 break;
3877 case TGSI_SEMANTIC_STENCIL:
3878 stencil = LLVMBuildLoad(builder,
3879 addrs[4 * i + 1], "");
3880 break;
3881 case TGSI_SEMANTIC_SAMPLEMASK:
3882 samplemask = LLVMBuildLoad(builder,
3883 addrs[4 * i + 0], "");
3884 break;
3885 default:
3886 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3887 semantic_name);
3888 }
3889 }
3890
3891 /* Fill the return structure. */
3892 ret = ctx->return_value;
3893
3894 /* Set SGPRs. */
3895 ret = LLVMBuildInsertValue(builder, ret,
3896 ac_to_integer(&ctx->ac,
3897 LLVMGetParam(ctx->main_fn,
3898 SI_PARAM_ALPHA_REF)),
3899 SI_SGPR_ALPHA_REF, "");
3900
3901 /* Set VGPRs */
3902 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3903 for (i = 0; i < ARRAY_SIZE(color); i++) {
3904 if (!color[i][0])
3905 continue;
3906
3907 for (j = 0; j < 4; j++)
3908 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3909 }
3910 if (depth)
3911 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3912 if (stencil)
3913 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3914 if (samplemask)
3915 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3916
3917 /* Add the input sample mask for smoothing at the end. */
3918 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3919 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3920 ret = LLVMBuildInsertValue(builder, ret,
3921 LLVMGetParam(ctx->main_fn,
3922 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3923
3924 ctx->return_value = ret;
3925 }
3926
3927 static void membar_emit(
3928 const struct lp_build_tgsi_action *action,
3929 struct lp_build_tgsi_context *bld_base,
3930 struct lp_build_emit_data *emit_data)
3931 {
3932 struct si_shader_context *ctx = si_shader_context(bld_base);
3933 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3934 unsigned flags = LLVMConstIntGetZExtValue(src0);
3935 unsigned waitcnt = NOOP_WAITCNT;
3936
3937 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3938 waitcnt &= VM_CNT & LGKM_CNT;
3939
3940 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3941 TGSI_MEMBAR_SHADER_BUFFER |
3942 TGSI_MEMBAR_SHADER_IMAGE))
3943 waitcnt &= VM_CNT;
3944
3945 if (flags & TGSI_MEMBAR_SHARED)
3946 waitcnt &= LGKM_CNT;
3947
3948 if (waitcnt != NOOP_WAITCNT)
3949 ac_build_waitcnt(&ctx->ac, waitcnt);
3950 }
3951
3952 static void clock_emit(
3953 const struct lp_build_tgsi_action *action,
3954 struct lp_build_tgsi_context *bld_base,
3955 struct lp_build_emit_data *emit_data)
3956 {
3957 struct si_shader_context *ctx = si_shader_context(bld_base);
3958 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3959
3960 emit_data->output[0] =
3961 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3962 emit_data->output[1] =
3963 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3964 }
3965
3966 static void si_llvm_emit_ddxy(
3967 const struct lp_build_tgsi_action *action,
3968 struct lp_build_tgsi_context *bld_base,
3969 struct lp_build_emit_data *emit_data)
3970 {
3971 struct si_shader_context *ctx = si_shader_context(bld_base);
3972 unsigned opcode = emit_data->info->opcode;
3973 LLVMValueRef val;
3974 int idx;
3975 unsigned mask;
3976
3977 if (opcode == TGSI_OPCODE_DDX_FINE)
3978 mask = AC_TID_MASK_LEFT;
3979 else if (opcode == TGSI_OPCODE_DDY_FINE)
3980 mask = AC_TID_MASK_TOP;
3981 else
3982 mask = AC_TID_MASK_TOP_LEFT;
3983
3984 /* for DDX we want to next X pixel, DDY next Y pixel. */
3985 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3986
3987 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3988 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3989 emit_data->output[emit_data->chan] = val;
3990 }
3991
3992 /*
3993 * this takes an I,J coordinate pair,
3994 * and works out the X and Y derivatives.
3995 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3996 */
3997 static LLVMValueRef si_llvm_emit_ddxy_interp(
3998 struct lp_build_tgsi_context *bld_base,
3999 LLVMValueRef interp_ij)
4000 {
4001 struct si_shader_context *ctx = si_shader_context(bld_base);
4002 LLVMValueRef result[4], a;
4003 unsigned i;
4004
4005 for (i = 0; i < 2; i++) {
4006 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
4007 LLVMConstInt(ctx->i32, i, 0), "");
4008 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4009 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4010 }
4011
4012 return lp_build_gather_values(&ctx->gallivm, result, 4);
4013 }
4014
4015 static void interp_fetch_args(
4016 struct lp_build_tgsi_context *bld_base,
4017 struct lp_build_emit_data *emit_data)
4018 {
4019 struct si_shader_context *ctx = si_shader_context(bld_base);
4020 const struct tgsi_full_instruction *inst = emit_data->inst;
4021
4022 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4023 /* offset is in second src, first two channels */
4024 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4025 emit_data->inst, 1,
4026 TGSI_CHAN_X);
4027 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4028 emit_data->inst, 1,
4029 TGSI_CHAN_Y);
4030 emit_data->arg_count = 2;
4031 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4032 LLVMValueRef sample_position;
4033 LLVMValueRef sample_id;
4034 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4035
4036 /* fetch sample ID, then fetch its sample position,
4037 * and place into first two channels.
4038 */
4039 sample_id = lp_build_emit_fetch(bld_base,
4040 emit_data->inst, 1, TGSI_CHAN_X);
4041 sample_id = ac_to_integer(&ctx->ac, sample_id);
4042
4043 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4044 * Language 4.50 spec says about interpolateAtSample:
4045 *
4046 * "Returns the value of the input interpolant variable at
4047 * the location of sample number sample. If multisample
4048 * buffers are not available, the input variable will be
4049 * evaluated at the center of the pixel. If sample sample
4050 * does not exist, the position used to interpolate the
4051 * input variable is undefined."
4052 *
4053 * This means that sample_id values outside of the valid are
4054 * in fact valid input, and the usual mechanism for loading the
4055 * sample position doesn't work.
4056 */
4057 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4058 LLVMValueRef center[4] = {
4059 LLVMConstReal(ctx->f32, 0.5),
4060 LLVMConstReal(ctx->f32, 0.5),
4061 ctx->ac.f32_0,
4062 ctx->ac.f32_0,
4063 };
4064
4065 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4066 } else {
4067 sample_position = load_sample_position(&ctx->abi, sample_id);
4068 }
4069
4070 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4071 sample_position,
4072 ctx->i32_0, "");
4073
4074 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4075 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4076 sample_position,
4077 ctx->i32_1, "");
4078 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4079 emit_data->arg_count = 2;
4080 }
4081 }
4082
4083 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4084 struct lp_build_tgsi_context *bld_base,
4085 struct lp_build_emit_data *emit_data)
4086 {
4087 struct si_shader_context *ctx = si_shader_context(bld_base);
4088 struct si_shader *shader = ctx->shader;
4089 const struct tgsi_shader_info *info = &shader->selector->info;
4090 LLVMValueRef interp_param;
4091 const struct tgsi_full_instruction *inst = emit_data->inst;
4092 const struct tgsi_full_src_register *input = &inst->Src[0];
4093 int input_base, input_array_size;
4094 int chan;
4095 int i;
4096 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4097 LLVMValueRef array_idx;
4098 int interp_param_idx;
4099 unsigned interp;
4100 unsigned location;
4101
4102 assert(input->Register.File == TGSI_FILE_INPUT);
4103
4104 if (input->Register.Indirect) {
4105 unsigned array_id = input->Indirect.ArrayID;
4106
4107 if (array_id) {
4108 input_base = info->input_array_first[array_id];
4109 input_array_size = info->input_array_last[array_id] - input_base + 1;
4110 } else {
4111 input_base = inst->Src[0].Register.Index;
4112 input_array_size = info->num_inputs - input_base;
4113 }
4114
4115 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4116 1, input->Register.Index - input_base);
4117 } else {
4118 input_base = inst->Src[0].Register.Index;
4119 input_array_size = 1;
4120 array_idx = ctx->i32_0;
4121 }
4122
4123 interp = shader->selector->info.input_interpolate[input_base];
4124
4125 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4126 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4127 location = TGSI_INTERPOLATE_LOC_CENTER;
4128 else
4129 location = TGSI_INTERPOLATE_LOC_CENTROID;
4130
4131 interp_param_idx = lookup_interp_param_index(interp, location);
4132 if (interp_param_idx == -1)
4133 return;
4134 else if (interp_param_idx)
4135 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4136 else
4137 interp_param = NULL;
4138
4139 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4140 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4141 LLVMValueRef ij_out[2];
4142 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4143
4144 /*
4145 * take the I then J parameters, and the DDX/Y for it, and
4146 * calculate the IJ inputs for the interpolator.
4147 * temp1 = ddx * offset/sample.x + I;
4148 * interp_param.I = ddy * offset/sample.y + temp1;
4149 * temp1 = ddx * offset/sample.x + J;
4150 * interp_param.J = ddy * offset/sample.y + temp1;
4151 */
4152 for (i = 0; i < 2; i++) {
4153 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4154 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4155 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4156 ddxy_out, ix_ll, "");
4157 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4158 ddxy_out, iy_ll, "");
4159 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4160 interp_param, ix_ll, "");
4161 LLVMValueRef temp1, temp2;
4162
4163 interp_el = ac_to_float(&ctx->ac, interp_el);
4164
4165 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4166
4167 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4168
4169 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4170
4171 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4172 }
4173 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4174 }
4175
4176 if (interp_param)
4177 interp_param = ac_to_float(&ctx->ac, interp_param);
4178
4179 for (chan = 0; chan < 4; chan++) {
4180 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4181 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4182
4183 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4184 LLVMValueRef v, i = NULL, j = NULL;
4185
4186 if (interp_param) {
4187 i = LLVMBuildExtractElement(
4188 ctx->ac.builder, interp_param, ctx->i32_0, "");
4189 j = LLVMBuildExtractElement(
4190 ctx->ac.builder, interp_param, ctx->i32_1, "");
4191 }
4192 v = si_build_fs_interp(ctx, input_base + idx, schan,
4193 prim_mask, i, j);
4194
4195 gather = LLVMBuildInsertElement(ctx->ac.builder,
4196 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4197 }
4198
4199 emit_data->output[chan] = LLVMBuildExtractElement(
4200 ctx->ac.builder, gather, array_idx, "");
4201 }
4202 }
4203
4204 static void vote_all_emit(
4205 const struct lp_build_tgsi_action *action,
4206 struct lp_build_tgsi_context *bld_base,
4207 struct lp_build_emit_data *emit_data)
4208 {
4209 struct si_shader_context *ctx = si_shader_context(bld_base);
4210
4211 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4212 emit_data->output[emit_data->chan] =
4213 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4214 }
4215
4216 static void vote_any_emit(
4217 const struct lp_build_tgsi_action *action,
4218 struct lp_build_tgsi_context *bld_base,
4219 struct lp_build_emit_data *emit_data)
4220 {
4221 struct si_shader_context *ctx = si_shader_context(bld_base);
4222
4223 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4224 emit_data->output[emit_data->chan] =
4225 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4226 }
4227
4228 static void vote_eq_emit(
4229 const struct lp_build_tgsi_action *action,
4230 struct lp_build_tgsi_context *bld_base,
4231 struct lp_build_emit_data *emit_data)
4232 {
4233 struct si_shader_context *ctx = si_shader_context(bld_base);
4234
4235 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4236 emit_data->output[emit_data->chan] =
4237 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4238 }
4239
4240 static void ballot_emit(
4241 const struct lp_build_tgsi_action *action,
4242 struct lp_build_tgsi_context *bld_base,
4243 struct lp_build_emit_data *emit_data)
4244 {
4245 struct si_shader_context *ctx = si_shader_context(bld_base);
4246 LLVMBuilderRef builder = ctx->ac.builder;
4247 LLVMValueRef tmp;
4248
4249 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4250 tmp = ac_build_ballot(&ctx->ac, tmp);
4251 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4252
4253 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4254 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4255 }
4256
4257 static void read_invoc_fetch_args(
4258 struct lp_build_tgsi_context *bld_base,
4259 struct lp_build_emit_data *emit_data)
4260 {
4261 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4262 0, emit_data->src_chan);
4263
4264 /* Always read the source invocation (= lane) from the X channel. */
4265 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4266 1, TGSI_CHAN_X);
4267 emit_data->arg_count = 2;
4268 }
4269
4270 static void read_lane_emit(
4271 const struct lp_build_tgsi_action *action,
4272 struct lp_build_tgsi_context *bld_base,
4273 struct lp_build_emit_data *emit_data)
4274 {
4275 struct si_shader_context *ctx = si_shader_context(bld_base);
4276
4277 /* We currently have no other way to prevent LLVM from lifting the icmp
4278 * calls to a dominating basic block.
4279 */
4280 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4281
4282 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4283 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4284
4285 emit_data->output[emit_data->chan] =
4286 ac_build_intrinsic(&ctx->ac, action->intr_name,
4287 ctx->i32, emit_data->args, emit_data->arg_count,
4288 AC_FUNC_ATTR_READNONE |
4289 AC_FUNC_ATTR_CONVERGENT);
4290 }
4291
4292 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4293 struct lp_build_emit_data *emit_data)
4294 {
4295 struct si_shader_context *ctx = si_shader_context(bld_base);
4296 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4297 LLVMValueRef imm;
4298 unsigned stream;
4299
4300 assert(src0.File == TGSI_FILE_IMMEDIATE);
4301
4302 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4303 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4304 return stream;
4305 }
4306
4307 /* Emit one vertex from the geometry shader */
4308 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4309 unsigned stream,
4310 LLVMValueRef *addrs)
4311 {
4312 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4313 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4314 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4315 struct si_shader *shader = ctx->shader;
4316 struct lp_build_if_state if_state;
4317 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4318 ctx->param_gs2vs_offset);
4319 LLVMValueRef gs_next_vertex;
4320 LLVMValueRef can_emit;
4321 unsigned chan, offset;
4322 int i;
4323
4324 /* Write vertex attribute values to GSVS ring */
4325 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4326 ctx->gs_next_vertex[stream],
4327 "");
4328
4329 /* If this thread has already emitted the declared maximum number of
4330 * vertices, skip the write: excessive vertex emissions are not
4331 * supposed to have any effect.
4332 *
4333 * If the shader has no writes to memory, kill it instead. This skips
4334 * further memory loads and may allow LLVM to skip to the end
4335 * altogether.
4336 */
4337 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4338 LLVMConstInt(ctx->i32,
4339 shader->selector->gs_max_out_vertices, 0), "");
4340
4341 bool use_kill = !info->writes_memory;
4342 if (use_kill) {
4343 ac_build_kill_if_false(&ctx->ac, can_emit);
4344 } else {
4345 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4346 }
4347
4348 offset = 0;
4349 for (i = 0; i < info->num_outputs; i++) {
4350 for (chan = 0; chan < 4; chan++) {
4351 if (!(info->output_usagemask[i] & (1 << chan)) ||
4352 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4353 continue;
4354
4355 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4356 LLVMValueRef voffset =
4357 LLVMConstInt(ctx->i32, offset *
4358 shader->selector->gs_max_out_vertices, 0);
4359 offset++;
4360
4361 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4362 voffset = lp_build_mul_imm(uint, voffset, 4);
4363
4364 out_val = ac_to_integer(&ctx->ac, out_val);
4365
4366 ac_build_buffer_store_dword(&ctx->ac,
4367 ctx->gsvs_ring[stream],
4368 out_val, 1,
4369 voffset, soffset, 0,
4370 1, 1, true, true);
4371 }
4372 }
4373
4374 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4375 ctx->i32_1);
4376
4377 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4378
4379 /* Signal vertex emission */
4380 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4381 si_get_gs_wave_id(ctx));
4382 if (!use_kill)
4383 lp_build_endif(&if_state);
4384 }
4385
4386 /* Emit one vertex from the geometry shader */
4387 static void si_tgsi_emit_vertex(
4388 const struct lp_build_tgsi_action *action,
4389 struct lp_build_tgsi_context *bld_base,
4390 struct lp_build_emit_data *emit_data)
4391 {
4392 struct si_shader_context *ctx = si_shader_context(bld_base);
4393 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4394
4395 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4396 }
4397
4398 /* Cut one primitive from the geometry shader */
4399 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4400 unsigned stream)
4401 {
4402 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4403
4404 /* Signal primitive cut */
4405 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4406 si_get_gs_wave_id(ctx));
4407 }
4408
4409 /* Cut one primitive from the geometry shader */
4410 static void si_tgsi_emit_primitive(
4411 const struct lp_build_tgsi_action *action,
4412 struct lp_build_tgsi_context *bld_base,
4413 struct lp_build_emit_data *emit_data)
4414 {
4415 struct si_shader_context *ctx = si_shader_context(bld_base);
4416
4417 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4418 }
4419
4420 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4421 struct lp_build_tgsi_context *bld_base,
4422 struct lp_build_emit_data *emit_data)
4423 {
4424 struct si_shader_context *ctx = si_shader_context(bld_base);
4425
4426 /* SI only (thanks to a hw bug workaround):
4427 * The real barrier instruction isn’t needed, because an entire patch
4428 * always fits into a single wave.
4429 */
4430 if (ctx->screen->info.chip_class == SI &&
4431 ctx->type == PIPE_SHADER_TESS_CTRL) {
4432 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4433 return;
4434 }
4435
4436 lp_build_intrinsic(ctx->ac.builder,
4437 "llvm.amdgcn.s.barrier",
4438 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4439 }
4440
4441 static const struct lp_build_tgsi_action interp_action = {
4442 .fetch_args = interp_fetch_args,
4443 .emit = build_interp_intrinsic,
4444 };
4445
4446 static void si_create_function(struct si_shader_context *ctx,
4447 const char *name,
4448 LLVMTypeRef *returns, unsigned num_returns,
4449 struct si_function_info *fninfo,
4450 unsigned max_workgroup_size)
4451 {
4452 int i;
4453
4454 si_llvm_create_func(ctx, name, returns, num_returns,
4455 fninfo->types, fninfo->num_params);
4456 ctx->return_value = LLVMGetUndef(ctx->return_type);
4457
4458 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4459 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4460
4461 /* The combination of:
4462 * - noalias
4463 * - dereferenceable
4464 * - invariant.load
4465 * allows the optimization passes to move loads and reduces
4466 * SGPR spilling significantly.
4467 */
4468 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4469
4470 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4471 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4472 ac_add_attr_dereferenceable(P, UINT64_MAX);
4473 }
4474 }
4475
4476 for (i = 0; i < fninfo->num_params; ++i) {
4477 if (fninfo->assign[i])
4478 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4479 }
4480
4481 if (ctx->screen->info.address32_hi) {
4482 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4483 "amdgpu-32bit-address-high-bits",
4484 ctx->screen->info.address32_hi);
4485 }
4486
4487 if (max_workgroup_size) {
4488 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4489 "amdgpu-max-work-group-size",
4490 max_workgroup_size);
4491 }
4492 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4493 "no-signed-zeros-fp-math",
4494 "true");
4495
4496 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4497 /* These were copied from some LLVM test. */
4498 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4499 "less-precise-fpmad",
4500 "true");
4501 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4502 "no-infs-fp-math",
4503 "true");
4504 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4505 "no-nans-fp-math",
4506 "true");
4507 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4508 "unsafe-fp-math",
4509 "true");
4510 }
4511 }
4512
4513 static void declare_streamout_params(struct si_shader_context *ctx,
4514 struct pipe_stream_output_info *so,
4515 struct si_function_info *fninfo)
4516 {
4517 int i;
4518
4519 /* Streamout SGPRs. */
4520 if (so->num_outputs) {
4521 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4522 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4523 else
4524 ctx->param_streamout_config = fninfo->num_params - 1;
4525
4526 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4527 }
4528 /* A streamout buffer offset is loaded if the stride is non-zero. */
4529 for (i = 0; i < 4; i++) {
4530 if (!so->stride[i])
4531 continue;
4532
4533 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4534 }
4535 }
4536
4537 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4538 {
4539 switch (shader->selector->type) {
4540 case PIPE_SHADER_TESS_CTRL:
4541 /* Return this so that LLVM doesn't remove s_barrier
4542 * instructions on chips where we use s_barrier. */
4543 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4544
4545 case PIPE_SHADER_GEOMETRY:
4546 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4547
4548 case PIPE_SHADER_COMPUTE:
4549 break; /* see below */
4550
4551 default:
4552 return 0;
4553 }
4554
4555 const unsigned *properties = shader->selector->info.properties;
4556 unsigned max_work_group_size =
4557 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4558 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4559 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4560
4561 if (!max_work_group_size) {
4562 /* This is a variable group size compute shader,
4563 * compile it for the maximum possible group size.
4564 */
4565 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4566 }
4567 return max_work_group_size;
4568 }
4569
4570 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4571 struct si_function_info *fninfo,
4572 bool assign_params)
4573 {
4574 LLVMTypeRef const_shader_buf_type;
4575
4576 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4577 ctx->shader->selector->info.shader_buffers_declared == 0)
4578 const_shader_buf_type = ctx->f32;
4579 else
4580 const_shader_buf_type = ctx->v4i32;
4581
4582 unsigned const_and_shader_buffers =
4583 add_arg(fninfo, ARG_SGPR,
4584 ac_array_in_const32_addr_space(const_shader_buf_type));
4585
4586 if (assign_params)
4587 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4588 }
4589
4590 static void declare_samplers_and_images(struct si_shader_context *ctx,
4591 struct si_function_info *fninfo,
4592 bool assign_params)
4593 {
4594 unsigned samplers_and_images =
4595 add_arg(fninfo, ARG_SGPR,
4596 ac_array_in_const32_addr_space(ctx->v8i32));
4597
4598 if (assign_params)
4599 ctx->param_samplers_and_images = samplers_and_images;
4600 }
4601
4602 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4603 struct si_function_info *fninfo,
4604 bool assign_params)
4605 {
4606 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4607 declare_samplers_and_images(ctx, fninfo, assign_params);
4608 }
4609
4610 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4611 struct si_function_info *fninfo)
4612 {
4613 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4614 ac_array_in_const32_addr_space(ctx->v4i32));
4615 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4616 ac_array_in_const32_addr_space(ctx->v8i32));
4617 }
4618
4619 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4620 struct si_function_info *fninfo)
4621 {
4622 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4623 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4624 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4625 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4626 }
4627
4628 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4629 struct si_function_info *fninfo,
4630 unsigned *num_prolog_vgprs)
4631 {
4632 struct si_shader *shader = ctx->shader;
4633
4634 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4635 if (shader->key.as_ls) {
4636 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4637 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4638 } else {
4639 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4640 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4641 }
4642 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4643
4644 if (!shader->is_gs_copy_shader) {
4645 /* Vertex load indices. */
4646 ctx->param_vertex_index0 = fninfo->num_params;
4647 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4648 add_arg(fninfo, ARG_VGPR, ctx->i32);
4649 *num_prolog_vgprs += shader->selector->info.num_inputs;
4650 }
4651 }
4652
4653 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4654 struct si_function_info *fninfo)
4655 {
4656 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4657 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4658 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4659 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4660 }
4661
4662 enum {
4663 /* Convenient merged shader definitions. */
4664 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4665 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4666 };
4667
4668 static void create_function(struct si_shader_context *ctx)
4669 {
4670 struct si_shader *shader = ctx->shader;
4671 struct si_function_info fninfo;
4672 LLVMTypeRef returns[16+32*4];
4673 unsigned i, num_return_sgprs;
4674 unsigned num_returns = 0;
4675 unsigned num_prolog_vgprs = 0;
4676 unsigned type = ctx->type;
4677 unsigned vs_blit_property =
4678 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4679
4680 si_init_function_info(&fninfo);
4681
4682 /* Set MERGED shaders. */
4683 if (ctx->screen->info.chip_class >= GFX9) {
4684 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4685 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4686 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4687 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4688 }
4689
4690 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4691
4692 switch (type) {
4693 case PIPE_SHADER_VERTEX:
4694 declare_global_desc_pointers(ctx, &fninfo);
4695
4696 if (vs_blit_property) {
4697 ctx->param_vs_blit_inputs = fninfo.num_params;
4698 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4699 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4700 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4701
4702 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4703 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4704 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4705 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4706 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4707 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4708 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4709 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4710 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4711 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4712 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4713 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4714 }
4715
4716 /* VGPRs */
4717 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4718 break;
4719 }
4720
4721 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4722 declare_vs_specific_input_sgprs(ctx, &fninfo);
4723 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4724 ac_array_in_const32_addr_space(ctx->v4i32));
4725
4726 if (shader->key.as_es) {
4727 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 } else if (shader->key.as_ls) {
4729 /* no extra parameters */
4730 } else {
4731 if (shader->is_gs_copy_shader) {
4732 fninfo.num_params = ctx->param_rw_buffers + 1;
4733 fninfo.num_sgpr_params = fninfo.num_params;
4734 }
4735
4736 /* The locations of the other parameters are assigned dynamically. */
4737 declare_streamout_params(ctx, &shader->selector->so,
4738 &fninfo);
4739 }
4740
4741 /* VGPRs */
4742 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4743 break;
4744
4745 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4746 declare_global_desc_pointers(ctx, &fninfo);
4747 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4748 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4749 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4750 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4751 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4752 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4753 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4754
4755 /* VGPRs */
4756 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4757 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4758
4759 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4760 * placed after the user SGPRs.
4761 */
4762 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4763 returns[num_returns++] = ctx->i32; /* SGPRs */
4764 for (i = 0; i < 11; i++)
4765 returns[num_returns++] = ctx->f32; /* VGPRs */
4766 break;
4767
4768 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4769 /* Merged stages have 8 system SGPRs at the beginning. */
4770 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4771 if (HAVE_32BIT_POINTERS) {
4772 declare_per_stage_desc_pointers(ctx, &fninfo,
4773 ctx->type == PIPE_SHADER_TESS_CTRL);
4774 } else {
4775 declare_const_and_shader_buffers(ctx, &fninfo,
4776 ctx->type == PIPE_SHADER_TESS_CTRL);
4777 }
4778 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4779 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4780 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4781 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4782 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4783 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4784
4785 declare_global_desc_pointers(ctx, &fninfo);
4786 declare_per_stage_desc_pointers(ctx, &fninfo,
4787 ctx->type == PIPE_SHADER_VERTEX);
4788 declare_vs_specific_input_sgprs(ctx, &fninfo);
4789
4790 if (!HAVE_32BIT_POINTERS) {
4791 declare_samplers_and_images(ctx, &fninfo,
4792 ctx->type == PIPE_SHADER_TESS_CTRL);
4793 }
4794 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4795 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4796 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4797 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4798 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4799 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4800 ac_array_in_const32_addr_space(ctx->v4i32));
4801
4802 /* VGPRs (first TCS, then VS) */
4803 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4804 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4805
4806 if (ctx->type == PIPE_SHADER_VERTEX) {
4807 declare_vs_input_vgprs(ctx, &fninfo,
4808 &num_prolog_vgprs);
4809
4810 /* LS return values are inputs to the TCS main shader part. */
4811 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4812 returns[num_returns++] = ctx->i32; /* SGPRs */
4813 for (i = 0; i < 2; i++)
4814 returns[num_returns++] = ctx->f32; /* VGPRs */
4815 } else {
4816 /* TCS return values are inputs to the TCS epilog.
4817 *
4818 * param_tcs_offchip_offset, param_tcs_factor_offset,
4819 * param_tcs_offchip_layout, and param_rw_buffers
4820 * should be passed to the epilog.
4821 */
4822 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4823 returns[num_returns++] = ctx->i32; /* SGPRs */
4824 for (i = 0; i < 11; i++)
4825 returns[num_returns++] = ctx->f32; /* VGPRs */
4826 }
4827 break;
4828
4829 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4830 /* Merged stages have 8 system SGPRs at the beginning. */
4831 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4832 if (HAVE_32BIT_POINTERS) {
4833 declare_per_stage_desc_pointers(ctx, &fninfo,
4834 ctx->type == PIPE_SHADER_GEOMETRY);
4835 } else {
4836 declare_const_and_shader_buffers(ctx, &fninfo,
4837 ctx->type == PIPE_SHADER_GEOMETRY);
4838 }
4839 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4840 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4841 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4842 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4843 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4844 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4845
4846 declare_global_desc_pointers(ctx, &fninfo);
4847 declare_per_stage_desc_pointers(ctx, &fninfo,
4848 (ctx->type == PIPE_SHADER_VERTEX ||
4849 ctx->type == PIPE_SHADER_TESS_EVAL));
4850 if (ctx->type == PIPE_SHADER_VERTEX) {
4851 declare_vs_specific_input_sgprs(ctx, &fninfo);
4852 } else {
4853 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4854 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4855 if (!HAVE_32BIT_POINTERS) {
4856 /* Declare as many input SGPRs as the VS has. */
4857 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4858 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4859 }
4860 }
4861
4862 if (!HAVE_32BIT_POINTERS) {
4863 declare_samplers_and_images(ctx, &fninfo,
4864 ctx->type == PIPE_SHADER_GEOMETRY);
4865 }
4866 if (ctx->type == PIPE_SHADER_VERTEX) {
4867 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4868 ac_array_in_const32_addr_space(ctx->v4i32));
4869 }
4870
4871 /* VGPRs (first GS, then VS/TES) */
4872 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4873 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4874 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4875 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4876 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4877
4878 if (ctx->type == PIPE_SHADER_VERTEX) {
4879 declare_vs_input_vgprs(ctx, &fninfo,
4880 &num_prolog_vgprs);
4881 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4882 declare_tes_input_vgprs(ctx, &fninfo);
4883 }
4884
4885 if (ctx->type == PIPE_SHADER_VERTEX ||
4886 ctx->type == PIPE_SHADER_TESS_EVAL) {
4887 unsigned num_user_sgprs;
4888
4889 if (ctx->type == PIPE_SHADER_VERTEX)
4890 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4891 else
4892 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4893
4894 /* ES return values are inputs to GS. */
4895 for (i = 0; i < 8 + num_user_sgprs; i++)
4896 returns[num_returns++] = ctx->i32; /* SGPRs */
4897 for (i = 0; i < 5; i++)
4898 returns[num_returns++] = ctx->f32; /* VGPRs */
4899 }
4900 break;
4901
4902 case PIPE_SHADER_TESS_EVAL:
4903 declare_global_desc_pointers(ctx, &fninfo);
4904 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4905 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4906 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4907
4908 if (shader->key.as_es) {
4909 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4910 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4911 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4912 } else {
4913 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4914 declare_streamout_params(ctx, &shader->selector->so,
4915 &fninfo);
4916 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4917 }
4918
4919 /* VGPRs */
4920 declare_tes_input_vgprs(ctx, &fninfo);
4921 break;
4922
4923 case PIPE_SHADER_GEOMETRY:
4924 declare_global_desc_pointers(ctx, &fninfo);
4925 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4926 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4927 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4928
4929 /* VGPRs */
4930 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4931 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4932 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4933 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4934 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4935 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4936 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4937 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4938 break;
4939
4940 case PIPE_SHADER_FRAGMENT:
4941 declare_global_desc_pointers(ctx, &fninfo);
4942 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4943 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4944 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4945 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4946
4947 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4948 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4949 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4950 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4951 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4952 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4953 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4954 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4955 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4956 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4957 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4958 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4959 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4960 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4961 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4962 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4963 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4964 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4965 shader->info.face_vgpr_index = 20;
4966 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4967 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4968 shader->info.ancillary_vgpr_index = 21;
4969 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4970 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4971 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4972
4973 /* Color inputs from the prolog. */
4974 if (shader->selector->info.colors_read) {
4975 unsigned num_color_elements =
4976 util_bitcount(shader->selector->info.colors_read);
4977
4978 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4979 for (i = 0; i < num_color_elements; i++)
4980 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4981
4982 num_prolog_vgprs += num_color_elements;
4983 }
4984
4985 /* Outputs for the epilog. */
4986 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4987 num_returns =
4988 num_return_sgprs +
4989 util_bitcount(shader->selector->info.colors_written) * 4 +
4990 shader->selector->info.writes_z +
4991 shader->selector->info.writes_stencil +
4992 shader->selector->info.writes_samplemask +
4993 1 /* SampleMaskIn */;
4994
4995 num_returns = MAX2(num_returns,
4996 num_return_sgprs +
4997 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4998
4999 for (i = 0; i < num_return_sgprs; i++)
5000 returns[i] = ctx->i32;
5001 for (; i < num_returns; i++)
5002 returns[i] = ctx->f32;
5003 break;
5004
5005 case PIPE_SHADER_COMPUTE:
5006 declare_global_desc_pointers(ctx, &fninfo);
5007 declare_per_stage_desc_pointers(ctx, &fninfo, true);
5008 if (shader->selector->info.uses_grid_size)
5009 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
5010 if (shader->selector->info.uses_block_size)
5011 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
5012
5013 for (i = 0; i < 3; i++) {
5014 ctx->abi.workgroup_ids[i] = NULL;
5015 if (shader->selector->info.uses_block_id[i])
5016 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
5017 }
5018
5019 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
5020 break;
5021 default:
5022 assert(0 && "unimplemented shader");
5023 return;
5024 }
5025
5026 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5027 si_get_max_workgroup_size(shader));
5028
5029 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5030 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5031 ctx->separate_prolog) {
5032 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5033 "InitialPSInputAddr",
5034 S_0286D0_PERSP_SAMPLE_ENA(1) |
5035 S_0286D0_PERSP_CENTER_ENA(1) |
5036 S_0286D0_PERSP_CENTROID_ENA(1) |
5037 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5038 S_0286D0_LINEAR_CENTER_ENA(1) |
5039 S_0286D0_LINEAR_CENTROID_ENA(1) |
5040 S_0286D0_FRONT_FACE_ENA(1) |
5041 S_0286D0_ANCILLARY_ENA(1) |
5042 S_0286D0_POS_FIXED_PT_ENA(1));
5043 }
5044
5045 shader->info.num_input_sgprs = 0;
5046 shader->info.num_input_vgprs = 0;
5047
5048 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5049 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5050
5051 for (; i < fninfo.num_params; ++i)
5052 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5053
5054 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5055 shader->info.num_input_vgprs -= num_prolog_vgprs;
5056
5057 if (shader->key.as_ls ||
5058 ctx->type == PIPE_SHADER_TESS_CTRL ||
5059 /* GFX9 has the ESGS ring buffer in LDS. */
5060 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5061 ac_declare_lds_as_pointer(&ctx->ac);
5062 }
5063
5064 /**
5065 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5066 * for later use.
5067 */
5068 static void preload_ring_buffers(struct si_shader_context *ctx)
5069 {
5070 LLVMBuilderRef builder = ctx->ac.builder;
5071
5072 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5073 ctx->param_rw_buffers);
5074
5075 if (ctx->screen->info.chip_class <= VI &&
5076 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5077 unsigned ring =
5078 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5079 : SI_ES_RING_ESGS;
5080 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5081
5082 ctx->esgs_ring =
5083 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5084 }
5085
5086 if (ctx->shader->is_gs_copy_shader) {
5087 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5088
5089 ctx->gsvs_ring[0] =
5090 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5091 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5092 const struct si_shader_selector *sel = ctx->shader->selector;
5093 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5094 LLVMValueRef base_ring;
5095
5096 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5097
5098 /* The conceptual layout of the GSVS ring is
5099 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5100 * but the real memory layout is swizzled across
5101 * threads:
5102 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5103 * t16v0c0 ..
5104 * Override the buffer descriptor accordingly.
5105 */
5106 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5107 uint64_t stream_offset = 0;
5108
5109 for (unsigned stream = 0; stream < 4; ++stream) {
5110 unsigned num_components;
5111 unsigned stride;
5112 unsigned num_records;
5113 LLVMValueRef ring, tmp;
5114
5115 num_components = sel->info.num_stream_output_components[stream];
5116 if (!num_components)
5117 continue;
5118
5119 stride = 4 * num_components * sel->gs_max_out_vertices;
5120
5121 /* Limit on the stride field for <= CIK. */
5122 assert(stride < (1 << 14));
5123
5124 num_records = 64;
5125
5126 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5127 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5128 tmp = LLVMBuildAdd(builder, tmp,
5129 LLVMConstInt(ctx->i64,
5130 stream_offset, 0), "");
5131 stream_offset += stride * 64;
5132
5133 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5134 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5135 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5136 tmp = LLVMBuildOr(builder, tmp,
5137 LLVMConstInt(ctx->i32,
5138 S_008F04_STRIDE(stride) |
5139 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5140 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5141 ring = LLVMBuildInsertElement(builder, ring,
5142 LLVMConstInt(ctx->i32, num_records, 0),
5143 LLVMConstInt(ctx->i32, 2, 0), "");
5144 ring = LLVMBuildInsertElement(builder, ring,
5145 LLVMConstInt(ctx->i32,
5146 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5147 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5148 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5149 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5150 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5151 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5152 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5153 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5154 S_008F0C_ADD_TID_ENABLE(1),
5155 0),
5156 LLVMConstInt(ctx->i32, 3, 0), "");
5157
5158 ctx->gsvs_ring[stream] = ring;
5159 }
5160 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5161 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5162 }
5163 }
5164
5165 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5166 LLVMValueRef param_rw_buffers,
5167 unsigned param_pos_fixed_pt)
5168 {
5169 LLVMBuilderRef builder = ctx->ac.builder;
5170 LLVMValueRef slot, desc, offset, row, bit, address[2];
5171
5172 /* Use the fixed-point gl_FragCoord input.
5173 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5174 * per coordinate to get the repeating effect.
5175 */
5176 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5177 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5178
5179 /* Load the buffer descriptor. */
5180 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5181 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5182
5183 /* The stipple pattern is 32x32, each row has 32 bits. */
5184 offset = LLVMBuildMul(builder, address[1],
5185 LLVMConstInt(ctx->i32, 4, 0), "");
5186 row = buffer_load_const(ctx, desc, offset);
5187 row = ac_to_integer(&ctx->ac, row);
5188 bit = LLVMBuildLShr(builder, row, address[0], "");
5189 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5190 ac_build_kill_if_false(&ctx->ac, bit);
5191 }
5192
5193 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5194 struct si_shader_config *conf,
5195 unsigned symbol_offset)
5196 {
5197 unsigned i;
5198 const unsigned char *config =
5199 ac_shader_binary_config_start(binary, symbol_offset);
5200 bool really_needs_scratch = false;
5201
5202 /* LLVM adds SGPR spills to the scratch size.
5203 * Find out if we really need the scratch buffer.
5204 */
5205 for (i = 0; i < binary->reloc_count; i++) {
5206 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5207
5208 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5209 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5210 really_needs_scratch = true;
5211 break;
5212 }
5213 }
5214
5215 /* XXX: We may be able to emit some of these values directly rather than
5216 * extracting fields to be emitted later.
5217 */
5218
5219 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5220 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5221 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5222 switch (reg) {
5223 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5224 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5225 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5226 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5227 case R_00B848_COMPUTE_PGM_RSRC1:
5228 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5229 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5230 conf->float_mode = G_00B028_FLOAT_MODE(value);
5231 conf->rsrc1 = value;
5232 break;
5233 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5234 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5235 break;
5236 case R_00B84C_COMPUTE_PGM_RSRC2:
5237 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5238 conf->rsrc2 = value;
5239 break;
5240 case R_0286CC_SPI_PS_INPUT_ENA:
5241 conf->spi_ps_input_ena = value;
5242 break;
5243 case R_0286D0_SPI_PS_INPUT_ADDR:
5244 conf->spi_ps_input_addr = value;
5245 break;
5246 case R_0286E8_SPI_TMPRING_SIZE:
5247 case R_00B860_COMPUTE_TMPRING_SIZE:
5248 /* WAVESIZE is in units of 256 dwords. */
5249 if (really_needs_scratch)
5250 conf->scratch_bytes_per_wave =
5251 G_00B860_WAVESIZE(value) * 256 * 4;
5252 break;
5253 case 0x4: /* SPILLED_SGPRS */
5254 conf->spilled_sgprs = value;
5255 break;
5256 case 0x8: /* SPILLED_VGPRS */
5257 conf->spilled_vgprs = value;
5258 break;
5259 default:
5260 {
5261 static bool printed;
5262
5263 if (!printed) {
5264 fprintf(stderr, "Warning: LLVM emitted unknown "
5265 "config register: 0x%x\n", reg);
5266 printed = true;
5267 }
5268 }
5269 break;
5270 }
5271 }
5272
5273 if (!conf->spi_ps_input_addr)
5274 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5275 }
5276
5277 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5278 uint64_t scratch_va)
5279 {
5280 unsigned i;
5281 uint32_t scratch_rsrc_dword0 = scratch_va;
5282 uint32_t scratch_rsrc_dword1 =
5283 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5284
5285 /* Enable scratch coalescing. */
5286 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5287
5288 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5289 const struct ac_shader_reloc *reloc =
5290 &shader->binary.relocs[i];
5291 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5292 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5293 &scratch_rsrc_dword0, 4);
5294 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5295 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5296 &scratch_rsrc_dword1, 4);
5297 }
5298 }
5299 }
5300
5301 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5302 {
5303 unsigned size = shader->binary.code_size;
5304
5305 if (shader->prolog)
5306 size += shader->prolog->binary.code_size;
5307 if (shader->previous_stage)
5308 size += shader->previous_stage->binary.code_size;
5309 if (shader->prolog2)
5310 size += shader->prolog2->binary.code_size;
5311 if (shader->epilog)
5312 size += shader->epilog->binary.code_size;
5313 return size;
5314 }
5315
5316 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5317 {
5318 const struct ac_shader_binary *prolog =
5319 shader->prolog ? &shader->prolog->binary : NULL;
5320 const struct ac_shader_binary *previous_stage =
5321 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5322 const struct ac_shader_binary *prolog2 =
5323 shader->prolog2 ? &shader->prolog2->binary : NULL;
5324 const struct ac_shader_binary *epilog =
5325 shader->epilog ? &shader->epilog->binary : NULL;
5326 const struct ac_shader_binary *mainb = &shader->binary;
5327 unsigned bo_size = si_get_shader_binary_size(shader) +
5328 (!epilog ? mainb->rodata_size : 0);
5329 unsigned char *ptr;
5330
5331 assert(!prolog || !prolog->rodata_size);
5332 assert(!previous_stage || !previous_stage->rodata_size);
5333 assert(!prolog2 || !prolog2->rodata_size);
5334 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5335 !mainb->rodata_size);
5336 assert(!epilog || !epilog->rodata_size);
5337
5338 r600_resource_reference(&shader->bo, NULL);
5339 shader->bo = (struct r600_resource*)
5340 si_aligned_buffer_create(&sscreen->b,
5341 sscreen->cpdma_prefetch_writes_memory ?
5342 0 : R600_RESOURCE_FLAG_READ_ONLY,
5343 PIPE_USAGE_IMMUTABLE,
5344 align(bo_size, SI_CPDMA_ALIGNMENT),
5345 256);
5346 if (!shader->bo)
5347 return -ENOMEM;
5348
5349 /* Upload. */
5350 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5351 PIPE_TRANSFER_READ_WRITE |
5352 PIPE_TRANSFER_UNSYNCHRONIZED);
5353
5354 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5355 * endian-independent. */
5356 if (prolog) {
5357 memcpy(ptr, prolog->code, prolog->code_size);
5358 ptr += prolog->code_size;
5359 }
5360 if (previous_stage) {
5361 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5362 ptr += previous_stage->code_size;
5363 }
5364 if (prolog2) {
5365 memcpy(ptr, prolog2->code, prolog2->code_size);
5366 ptr += prolog2->code_size;
5367 }
5368
5369 memcpy(ptr, mainb->code, mainb->code_size);
5370 ptr += mainb->code_size;
5371
5372 if (epilog)
5373 memcpy(ptr, epilog->code, epilog->code_size);
5374 else if (mainb->rodata_size > 0)
5375 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5376
5377 sscreen->ws->buffer_unmap(shader->bo->buf);
5378 return 0;
5379 }
5380
5381 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5382 struct pipe_debug_callback *debug,
5383 const char *name, FILE *file)
5384 {
5385 char *line, *p;
5386 unsigned i, count;
5387
5388 if (binary->disasm_string) {
5389 fprintf(file, "Shader %s disassembly:\n", name);
5390 fprintf(file, "%s", binary->disasm_string);
5391
5392 if (debug && debug->debug_message) {
5393 /* Very long debug messages are cut off, so send the
5394 * disassembly one line at a time. This causes more
5395 * overhead, but on the plus side it simplifies
5396 * parsing of resulting logs.
5397 */
5398 pipe_debug_message(debug, SHADER_INFO,
5399 "Shader Disassembly Begin");
5400
5401 line = binary->disasm_string;
5402 while (*line) {
5403 p = util_strchrnul(line, '\n');
5404 count = p - line;
5405
5406 if (count) {
5407 pipe_debug_message(debug, SHADER_INFO,
5408 "%.*s", count, line);
5409 }
5410
5411 if (!*p)
5412 break;
5413 line = p + 1;
5414 }
5415
5416 pipe_debug_message(debug, SHADER_INFO,
5417 "Shader Disassembly End");
5418 }
5419 } else {
5420 fprintf(file, "Shader %s binary:\n", name);
5421 for (i = 0; i < binary->code_size; i += 4) {
5422 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5423 binary->code[i + 3], binary->code[i + 2],
5424 binary->code[i + 1], binary->code[i]);
5425 }
5426 }
5427 }
5428
5429 static void si_calculate_max_simd_waves(struct si_shader *shader)
5430 {
5431 struct si_screen *sscreen = shader->selector->screen;
5432 struct si_shader_config *conf = &shader->config;
5433 unsigned num_inputs = shader->selector->info.num_inputs;
5434 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5435 unsigned lds_per_wave = 0;
5436 unsigned max_simd_waves;
5437
5438 switch (sscreen->info.family) {
5439 /* These always have 8 waves: */
5440 case CHIP_POLARIS10:
5441 case CHIP_POLARIS11:
5442 case CHIP_POLARIS12:
5443 max_simd_waves = 8;
5444 break;
5445 default:
5446 max_simd_waves = 10;
5447 }
5448
5449 /* Compute LDS usage for PS. */
5450 switch (shader->selector->type) {
5451 case PIPE_SHADER_FRAGMENT:
5452 /* The minimum usage per wave is (num_inputs * 48). The maximum
5453 * usage is (num_inputs * 48 * 16).
5454 * We can get anything in between and it varies between waves.
5455 *
5456 * The 48 bytes per input for a single primitive is equal to
5457 * 4 bytes/component * 4 components/input * 3 points.
5458 *
5459 * Other stages don't know the size at compile time or don't
5460 * allocate LDS per wave, but instead they do it per thread group.
5461 */
5462 lds_per_wave = conf->lds_size * lds_increment +
5463 align(num_inputs * 48, lds_increment);
5464 break;
5465 case PIPE_SHADER_COMPUTE:
5466 if (shader->selector) {
5467 unsigned max_workgroup_size =
5468 si_get_max_workgroup_size(shader);
5469 lds_per_wave = (conf->lds_size * lds_increment) /
5470 DIV_ROUND_UP(max_workgroup_size, 64);
5471 }
5472 break;
5473 }
5474
5475 /* Compute the per-SIMD wave counts. */
5476 if (conf->num_sgprs) {
5477 if (sscreen->info.chip_class >= VI)
5478 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5479 else
5480 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5481 }
5482
5483 if (conf->num_vgprs)
5484 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5485
5486 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5487 * 16KB makes some SIMDs unoccupied). */
5488 if (lds_per_wave)
5489 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5490
5491 conf->max_simd_waves = max_simd_waves;
5492 }
5493
5494 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5495 struct pipe_debug_callback *debug)
5496 {
5497 const struct si_shader_config *conf = &shader->config;
5498
5499 pipe_debug_message(debug, SHADER_INFO,
5500 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5501 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5502 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5503 conf->num_sgprs, conf->num_vgprs,
5504 si_get_shader_binary_size(shader),
5505 conf->lds_size, conf->scratch_bytes_per_wave,
5506 conf->max_simd_waves, conf->spilled_sgprs,
5507 conf->spilled_vgprs, conf->private_mem_vgprs);
5508 }
5509
5510 static void si_shader_dump_stats(struct si_screen *sscreen,
5511 const struct si_shader *shader,
5512 unsigned processor,
5513 FILE *file,
5514 bool check_debug_option)
5515 {
5516 const struct si_shader_config *conf = &shader->config;
5517
5518 if (!check_debug_option ||
5519 si_can_dump_shader(sscreen, processor)) {
5520 if (processor == PIPE_SHADER_FRAGMENT) {
5521 fprintf(file, "*** SHADER CONFIG ***\n"
5522 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5523 "SPI_PS_INPUT_ENA = 0x%04x\n",
5524 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5525 }
5526
5527 fprintf(file, "*** SHADER STATS ***\n"
5528 "SGPRS: %d\n"
5529 "VGPRS: %d\n"
5530 "Spilled SGPRs: %d\n"
5531 "Spilled VGPRs: %d\n"
5532 "Private memory VGPRs: %d\n"
5533 "Code Size: %d bytes\n"
5534 "LDS: %d blocks\n"
5535 "Scratch: %d bytes per wave\n"
5536 "Max Waves: %d\n"
5537 "********************\n\n\n",
5538 conf->num_sgprs, conf->num_vgprs,
5539 conf->spilled_sgprs, conf->spilled_vgprs,
5540 conf->private_mem_vgprs,
5541 si_get_shader_binary_size(shader),
5542 conf->lds_size, conf->scratch_bytes_per_wave,
5543 conf->max_simd_waves);
5544 }
5545 }
5546
5547 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5548 {
5549 switch (processor) {
5550 case PIPE_SHADER_VERTEX:
5551 if (shader->key.as_es)
5552 return "Vertex Shader as ES";
5553 else if (shader->key.as_ls)
5554 return "Vertex Shader as LS";
5555 else
5556 return "Vertex Shader as VS";
5557 case PIPE_SHADER_TESS_CTRL:
5558 return "Tessellation Control Shader";
5559 case PIPE_SHADER_TESS_EVAL:
5560 if (shader->key.as_es)
5561 return "Tessellation Evaluation Shader as ES";
5562 else
5563 return "Tessellation Evaluation Shader as VS";
5564 case PIPE_SHADER_GEOMETRY:
5565 if (shader->is_gs_copy_shader)
5566 return "GS Copy Shader as VS";
5567 else
5568 return "Geometry Shader";
5569 case PIPE_SHADER_FRAGMENT:
5570 return "Pixel Shader";
5571 case PIPE_SHADER_COMPUTE:
5572 return "Compute Shader";
5573 default:
5574 return "Unknown Shader";
5575 }
5576 }
5577
5578 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5579 struct pipe_debug_callback *debug, unsigned processor,
5580 FILE *file, bool check_debug_option)
5581 {
5582 if (!check_debug_option ||
5583 si_can_dump_shader(sscreen, processor))
5584 si_dump_shader_key(processor, shader, file);
5585
5586 if (!check_debug_option && shader->binary.llvm_ir_string) {
5587 if (shader->previous_stage &&
5588 shader->previous_stage->binary.llvm_ir_string) {
5589 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5590 si_get_shader_name(shader, processor));
5591 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5592 }
5593
5594 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5595 si_get_shader_name(shader, processor));
5596 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5597 }
5598
5599 if (!check_debug_option ||
5600 (si_can_dump_shader(sscreen, processor) &&
5601 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5602 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5603
5604 if (shader->prolog)
5605 si_shader_dump_disassembly(&shader->prolog->binary,
5606 debug, "prolog", file);
5607 if (shader->previous_stage)
5608 si_shader_dump_disassembly(&shader->previous_stage->binary,
5609 debug, "previous stage", file);
5610 if (shader->prolog2)
5611 si_shader_dump_disassembly(&shader->prolog2->binary,
5612 debug, "prolog2", file);
5613
5614 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5615
5616 if (shader->epilog)
5617 si_shader_dump_disassembly(&shader->epilog->binary,
5618 debug, "epilog", file);
5619 fprintf(file, "\n");
5620 }
5621
5622 si_shader_dump_stats(sscreen, shader, processor, file,
5623 check_debug_option);
5624 }
5625
5626 static int si_compile_llvm(struct si_screen *sscreen,
5627 struct ac_shader_binary *binary,
5628 struct si_shader_config *conf,
5629 LLVMTargetMachineRef tm,
5630 LLVMModuleRef mod,
5631 struct pipe_debug_callback *debug,
5632 unsigned processor,
5633 const char *name)
5634 {
5635 int r = 0;
5636 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5637
5638 if (si_can_dump_shader(sscreen, processor)) {
5639 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5640
5641 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5642 fprintf(stderr, "%s LLVM IR:\n\n", name);
5643 ac_dump_module(mod);
5644 fprintf(stderr, "\n");
5645 }
5646 }
5647
5648 if (sscreen->record_llvm_ir) {
5649 char *ir = LLVMPrintModuleToString(mod);
5650 binary->llvm_ir_string = strdup(ir);
5651 LLVMDisposeMessage(ir);
5652 }
5653
5654 if (!si_replace_shader(count, binary)) {
5655 r = si_llvm_compile(mod, binary, tm, debug);
5656 if (r)
5657 return r;
5658 }
5659
5660 si_shader_binary_read_config(binary, conf, 0);
5661
5662 /* Enable 64-bit and 16-bit denormals, because there is no performance
5663 * cost.
5664 *
5665 * If denormals are enabled, all floating-point output modifiers are
5666 * ignored.
5667 *
5668 * Don't enable denormals for 32-bit floats, because:
5669 * - Floating-point output modifiers would be ignored by the hw.
5670 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5671 * have to stop using those.
5672 * - SI & CI would be very slow.
5673 */
5674 conf->float_mode |= V_00B028_FP_64_DENORMS;
5675
5676 FREE(binary->config);
5677 FREE(binary->global_symbol_offsets);
5678 binary->config = NULL;
5679 binary->global_symbol_offsets = NULL;
5680
5681 /* Some shaders can't have rodata because their binaries can be
5682 * concatenated.
5683 */
5684 if (binary->rodata_size &&
5685 (processor == PIPE_SHADER_VERTEX ||
5686 processor == PIPE_SHADER_TESS_CTRL ||
5687 processor == PIPE_SHADER_TESS_EVAL ||
5688 processor == PIPE_SHADER_FRAGMENT)) {
5689 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5690 return -EINVAL;
5691 }
5692
5693 return r;
5694 }
5695
5696 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5697 {
5698 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5699 LLVMBuildRetVoid(ctx->ac.builder);
5700 else
5701 LLVMBuildRet(ctx->ac.builder, ret);
5702 }
5703
5704 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5705 struct si_shader *
5706 si_generate_gs_copy_shader(struct si_screen *sscreen,
5707 LLVMTargetMachineRef tm,
5708 struct si_shader_selector *gs_selector,
5709 struct pipe_debug_callback *debug)
5710 {
5711 struct si_shader_context ctx;
5712 struct si_shader *shader;
5713 LLVMBuilderRef builder;
5714 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5715 struct lp_build_context *uint = &bld_base->uint_bld;
5716 struct si_shader_output_values *outputs;
5717 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5718 int i, r;
5719
5720 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5721
5722 if (!outputs)
5723 return NULL;
5724
5725 shader = CALLOC_STRUCT(si_shader);
5726 if (!shader) {
5727 FREE(outputs);
5728 return NULL;
5729 }
5730
5731 /* We can leave the fence as permanently signaled because the GS copy
5732 * shader only becomes visible globally after it has been compiled. */
5733 util_queue_fence_init(&shader->ready);
5734
5735 shader->selector = gs_selector;
5736 shader->is_gs_copy_shader = true;
5737
5738 si_init_shader_ctx(&ctx, sscreen, tm);
5739 ctx.shader = shader;
5740 ctx.type = PIPE_SHADER_VERTEX;
5741
5742 builder = ctx.ac.builder;
5743
5744 create_function(&ctx);
5745 preload_ring_buffers(&ctx);
5746
5747 LLVMValueRef voffset =
5748 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5749
5750 /* Fetch the vertex stream ID.*/
5751 LLVMValueRef stream_id;
5752
5753 if (gs_selector->so.num_outputs)
5754 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5755 else
5756 stream_id = ctx.i32_0;
5757
5758 /* Fill in output information. */
5759 for (i = 0; i < gsinfo->num_outputs; ++i) {
5760 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5761 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5762
5763 for (int chan = 0; chan < 4; chan++) {
5764 outputs[i].vertex_stream[chan] =
5765 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5766 }
5767 }
5768
5769 LLVMBasicBlockRef end_bb;
5770 LLVMValueRef switch_inst;
5771
5772 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5773 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5774
5775 for (int stream = 0; stream < 4; stream++) {
5776 LLVMBasicBlockRef bb;
5777 unsigned offset;
5778
5779 if (!gsinfo->num_stream_output_components[stream])
5780 continue;
5781
5782 if (stream > 0 && !gs_selector->so.num_outputs)
5783 continue;
5784
5785 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5786 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5787 LLVMPositionBuilderAtEnd(builder, bb);
5788
5789 /* Fetch vertex data from GSVS ring */
5790 offset = 0;
5791 for (i = 0; i < gsinfo->num_outputs; ++i) {
5792 for (unsigned chan = 0; chan < 4; chan++) {
5793 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5794 outputs[i].vertex_stream[chan] != stream) {
5795 outputs[i].values[chan] = ctx.bld_base.base.undef;
5796 continue;
5797 }
5798
5799 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5800 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5801 offset++;
5802
5803 outputs[i].values[chan] =
5804 ac_build_buffer_load(&ctx.ac,
5805 ctx.gsvs_ring[0], 1,
5806 ctx.i32_0, voffset,
5807 soffset, 0, 1, 1,
5808 true, false);
5809 }
5810 }
5811
5812 /* Streamout and exports. */
5813 if (gs_selector->so.num_outputs) {
5814 si_llvm_emit_streamout(&ctx, outputs,
5815 gsinfo->num_outputs,
5816 stream);
5817 }
5818
5819 if (stream == 0)
5820 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5821
5822 LLVMBuildBr(builder, end_bb);
5823 }
5824
5825 LLVMPositionBuilderAtEnd(builder, end_bb);
5826
5827 LLVMBuildRetVoid(ctx.ac.builder);
5828
5829 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5830 si_llvm_optimize_module(&ctx);
5831
5832 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5833 &ctx.shader->config, ctx.tm,
5834 ctx.gallivm.module,
5835 debug, PIPE_SHADER_GEOMETRY,
5836 "GS Copy Shader");
5837 if (!r) {
5838 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5839 fprintf(stderr, "GS Copy Shader:\n");
5840 si_shader_dump(sscreen, ctx.shader, debug,
5841 PIPE_SHADER_GEOMETRY, stderr, true);
5842 r = si_shader_binary_upload(sscreen, ctx.shader);
5843 }
5844
5845 si_llvm_dispose(&ctx);
5846
5847 FREE(outputs);
5848
5849 if (r != 0) {
5850 FREE(shader);
5851 shader = NULL;
5852 }
5853 return shader;
5854 }
5855
5856 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5857 const struct si_vs_prolog_bits *prolog,
5858 const char *prefix, FILE *f)
5859 {
5860 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5861 prefix, prolog->instance_divisor_is_one);
5862 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5863 prefix, prolog->instance_divisor_is_fetched);
5864 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5865 prefix, prolog->ls_vgpr_fix);
5866
5867 fprintf(f, " mono.vs.fix_fetch = {");
5868 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5869 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5870 fprintf(f, "}\n");
5871 }
5872
5873 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5874 FILE *f)
5875 {
5876 const struct si_shader_key *key = &shader->key;
5877
5878 fprintf(f, "SHADER KEY\n");
5879
5880 switch (processor) {
5881 case PIPE_SHADER_VERTEX:
5882 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5883 "part.vs.prolog", f);
5884 fprintf(f, " as_es = %u\n", key->as_es);
5885 fprintf(f, " as_ls = %u\n", key->as_ls);
5886 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5887 key->mono.u.vs_export_prim_id);
5888 break;
5889
5890 case PIPE_SHADER_TESS_CTRL:
5891 if (shader->selector->screen->info.chip_class >= GFX9) {
5892 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5893 "part.tcs.ls_prolog", f);
5894 }
5895 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5896 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5897 break;
5898
5899 case PIPE_SHADER_TESS_EVAL:
5900 fprintf(f, " as_es = %u\n", key->as_es);
5901 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5902 key->mono.u.vs_export_prim_id);
5903 break;
5904
5905 case PIPE_SHADER_GEOMETRY:
5906 if (shader->is_gs_copy_shader)
5907 break;
5908
5909 if (shader->selector->screen->info.chip_class >= GFX9 &&
5910 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5911 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5912 "part.gs.vs_prolog", f);
5913 }
5914 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5915 break;
5916
5917 case PIPE_SHADER_COMPUTE:
5918 break;
5919
5920 case PIPE_SHADER_FRAGMENT:
5921 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5922 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5923 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5924 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5925 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5926 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5927 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5928 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5929 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5930 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5931 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5932 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5933 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5934 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5935 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5936 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5937 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5938 break;
5939
5940 default:
5941 assert(0);
5942 }
5943
5944 if ((processor == PIPE_SHADER_GEOMETRY ||
5945 processor == PIPE_SHADER_TESS_EVAL ||
5946 processor == PIPE_SHADER_VERTEX) &&
5947 !key->as_es && !key->as_ls) {
5948 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5949 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5950 }
5951 }
5952
5953 static void si_init_shader_ctx(struct si_shader_context *ctx,
5954 struct si_screen *sscreen,
5955 LLVMTargetMachineRef tm)
5956 {
5957 struct lp_build_tgsi_context *bld_base;
5958
5959 si_llvm_context_init(ctx, sscreen, tm);
5960
5961 bld_base = &ctx->bld_base;
5962 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5963
5964 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5965 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5966 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5967
5968 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5969
5970 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5971
5972 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5973 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5974 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5975 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5976
5977 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5978 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5979 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5980 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5981 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5982 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5983 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5984 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5985 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5986
5987 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5988 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5989 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5990 }
5991
5992 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5993 {
5994 struct si_shader *shader = ctx->shader;
5995 struct tgsi_shader_info *info = &shader->selector->info;
5996
5997 if ((ctx->type != PIPE_SHADER_VERTEX &&
5998 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5999 shader->key.as_ls ||
6000 shader->key.as_es)
6001 return;
6002
6003 ac_optimize_vs_outputs(&ctx->ac,
6004 ctx->main_fn,
6005 shader->info.vs_output_param_offset,
6006 info->num_outputs,
6007 &shader->info.nr_param_exports);
6008 }
6009
6010 static void si_init_exec_from_input(struct si_shader_context *ctx,
6011 unsigned param, unsigned bitoffset)
6012 {
6013 LLVMValueRef args[] = {
6014 LLVMGetParam(ctx->main_fn, param),
6015 LLVMConstInt(ctx->i32, bitoffset, 0),
6016 };
6017 lp_build_intrinsic(ctx->ac.builder,
6018 "llvm.amdgcn.init.exec.from.input",
6019 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
6020 }
6021
6022 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6023 const struct si_vs_prolog_bits *key)
6024 {
6025 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6026 * VS prolog. */
6027 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6028 }
6029
6030 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6031 bool is_monolithic)
6032 {
6033 struct si_shader *shader = ctx->shader;
6034 struct si_shader_selector *sel = shader->selector;
6035 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6036
6037 // TODO clean all this up!
6038 switch (ctx->type) {
6039 case PIPE_SHADER_VERTEX:
6040 ctx->load_input = declare_input_vs;
6041 if (shader->key.as_ls)
6042 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6043 else if (shader->key.as_es)
6044 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6045 else
6046 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6047 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6048 ctx->abi.load_base_vertex = get_base_vertex;
6049 break;
6050 case PIPE_SHADER_TESS_CTRL:
6051 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6052 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6053 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6054 bld_base->emit_store = store_output_tcs;
6055 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6056 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6057 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6058 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6059 break;
6060 case PIPE_SHADER_TESS_EVAL:
6061 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6062 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6063 ctx->abi.load_tess_coord = si_load_tess_coord;
6064 ctx->abi.load_tess_level = si_load_tess_level;
6065 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6066 if (shader->key.as_es)
6067 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6068 else
6069 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6070 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6071 break;
6072 case PIPE_SHADER_GEOMETRY:
6073 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6074 ctx->abi.load_inputs = si_nir_load_input_gs;
6075 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6076 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6077 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6078 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6079 break;
6080 case PIPE_SHADER_FRAGMENT:
6081 ctx->load_input = declare_input_fs;
6082 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6083 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6084 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6085 ctx->abi.load_sample_position = load_sample_position;
6086 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6087 ctx->abi.emit_kill = si_llvm_emit_kill;
6088 break;
6089 case PIPE_SHADER_COMPUTE:
6090 ctx->abi.load_local_group_size = get_block_size;
6091 break;
6092 default:
6093 assert(!"Unsupported shader type");
6094 return false;
6095 }
6096
6097 ctx->abi.load_ubo = load_ubo;
6098 ctx->abi.load_ssbo = load_ssbo;
6099
6100 create_function(ctx);
6101 preload_ring_buffers(ctx);
6102
6103 /* For GFX9 merged shaders:
6104 * - Set EXEC for the first shader. If the prolog is present, set
6105 * EXEC there instead.
6106 * - Add a barrier before the second shader.
6107 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6108 * an if-statement. This is required for correctness in geometry
6109 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6110 * GS_CUT messages.
6111 *
6112 * For monolithic merged shaders, the first shader is wrapped in an
6113 * if-block together with its prolog in si_build_wrapper_function.
6114 */
6115 if (ctx->screen->info.chip_class >= GFX9) {
6116 if (!is_monolithic &&
6117 sel->info.num_instructions > 1 && /* not empty shader */
6118 (shader->key.as_es || shader->key.as_ls) &&
6119 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6120 (ctx->type == PIPE_SHADER_VERTEX &&
6121 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6122 si_init_exec_from_input(ctx,
6123 ctx->param_merged_wave_info, 0);
6124 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6125 ctx->type == PIPE_SHADER_GEOMETRY) {
6126 if (!is_monolithic)
6127 ac_init_exec_full_mask(&ctx->ac);
6128
6129 /* The barrier must execute for all shaders in a
6130 * threadgroup.
6131 */
6132 si_llvm_emit_barrier(NULL, bld_base, NULL);
6133
6134 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6135 LLVMValueRef ena =
6136 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6137 ac_get_thread_id(&ctx->ac), num_threads, "");
6138 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6139 }
6140 }
6141
6142 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6143 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6144 for (unsigned i = 0; i < 6; i++) {
6145 ctx->invoc0_tess_factors[i] =
6146 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6147 }
6148 }
6149
6150 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6151 int i;
6152 for (i = 0; i < 4; i++) {
6153 ctx->gs_next_vertex[i] =
6154 lp_build_alloca(&ctx->gallivm,
6155 ctx->i32, "");
6156 }
6157 }
6158
6159 if (sel->force_correct_derivs_after_kill) {
6160 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6161 /* true = don't kill. */
6162 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6163 ctx->postponed_kill);
6164 }
6165
6166 if (sel->tokens) {
6167 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6168 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6169 return false;
6170 }
6171 } else {
6172 if (!si_nir_build_llvm(ctx, sel->nir)) {
6173 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6174 return false;
6175 }
6176 }
6177
6178 si_llvm_build_ret(ctx, ctx->return_value);
6179 return true;
6180 }
6181
6182 /**
6183 * Compute the VS prolog key, which contains all the information needed to
6184 * build the VS prolog function, and set shader->info bits where needed.
6185 *
6186 * \param info Shader info of the vertex shader.
6187 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6188 * \param prolog_key Key of the VS prolog
6189 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6190 * \param key Output shader part key.
6191 */
6192 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6193 unsigned num_input_sgprs,
6194 const struct si_vs_prolog_bits *prolog_key,
6195 struct si_shader *shader_out,
6196 union si_shader_part_key *key)
6197 {
6198 memset(key, 0, sizeof(*key));
6199 key->vs_prolog.states = *prolog_key;
6200 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6201 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6202 key->vs_prolog.as_ls = shader_out->key.as_ls;
6203 key->vs_prolog.as_es = shader_out->key.as_es;
6204
6205 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6206 key->vs_prolog.as_ls = 1;
6207 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6208 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6209 key->vs_prolog.as_es = 1;
6210 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6211 }
6212
6213 /* Enable loading the InstanceID VGPR. */
6214 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6215
6216 if ((key->vs_prolog.states.instance_divisor_is_one |
6217 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6218 shader_out->info.uses_instanceid = true;
6219 }
6220
6221 /**
6222 * Compute the PS prolog key, which contains all the information needed to
6223 * build the PS prolog function, and set related bits in shader->config.
6224 */
6225 static void si_get_ps_prolog_key(struct si_shader *shader,
6226 union si_shader_part_key *key,
6227 bool separate_prolog)
6228 {
6229 struct tgsi_shader_info *info = &shader->selector->info;
6230
6231 memset(key, 0, sizeof(*key));
6232 key->ps_prolog.states = shader->key.part.ps.prolog;
6233 key->ps_prolog.colors_read = info->colors_read;
6234 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6235 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6236 key->ps_prolog.wqm = info->uses_derivatives &&
6237 (key->ps_prolog.colors_read ||
6238 key->ps_prolog.states.force_persp_sample_interp ||
6239 key->ps_prolog.states.force_linear_sample_interp ||
6240 key->ps_prolog.states.force_persp_center_interp ||
6241 key->ps_prolog.states.force_linear_center_interp ||
6242 key->ps_prolog.states.bc_optimize_for_persp ||
6243 key->ps_prolog.states.bc_optimize_for_linear);
6244 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6245
6246 if (info->colors_read) {
6247 unsigned *color = shader->selector->color_attr_index;
6248
6249 if (shader->key.part.ps.prolog.color_two_side) {
6250 /* BCOLORs are stored after the last input. */
6251 key->ps_prolog.num_interp_inputs = info->num_inputs;
6252 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6253 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6254 }
6255
6256 for (unsigned i = 0; i < 2; i++) {
6257 unsigned interp = info->input_interpolate[color[i]];
6258 unsigned location = info->input_interpolate_loc[color[i]];
6259
6260 if (!(info->colors_read & (0xf << i*4)))
6261 continue;
6262
6263 key->ps_prolog.color_attr_index[i] = color[i];
6264
6265 if (shader->key.part.ps.prolog.flatshade_colors &&
6266 interp == TGSI_INTERPOLATE_COLOR)
6267 interp = TGSI_INTERPOLATE_CONSTANT;
6268
6269 switch (interp) {
6270 case TGSI_INTERPOLATE_CONSTANT:
6271 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6272 break;
6273 case TGSI_INTERPOLATE_PERSPECTIVE:
6274 case TGSI_INTERPOLATE_COLOR:
6275 /* Force the interpolation location for colors here. */
6276 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6277 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6278 if (shader->key.part.ps.prolog.force_persp_center_interp)
6279 location = TGSI_INTERPOLATE_LOC_CENTER;
6280
6281 switch (location) {
6282 case TGSI_INTERPOLATE_LOC_SAMPLE:
6283 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6284 shader->config.spi_ps_input_ena |=
6285 S_0286CC_PERSP_SAMPLE_ENA(1);
6286 break;
6287 case TGSI_INTERPOLATE_LOC_CENTER:
6288 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6289 shader->config.spi_ps_input_ena |=
6290 S_0286CC_PERSP_CENTER_ENA(1);
6291 break;
6292 case TGSI_INTERPOLATE_LOC_CENTROID:
6293 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6294 shader->config.spi_ps_input_ena |=
6295 S_0286CC_PERSP_CENTROID_ENA(1);
6296 break;
6297 default:
6298 assert(0);
6299 }
6300 break;
6301 case TGSI_INTERPOLATE_LINEAR:
6302 /* Force the interpolation location for colors here. */
6303 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6304 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6305 if (shader->key.part.ps.prolog.force_linear_center_interp)
6306 location = TGSI_INTERPOLATE_LOC_CENTER;
6307
6308 /* The VGPR assignment for non-monolithic shaders
6309 * works because InitialPSInputAddr is set on the
6310 * main shader and PERSP_PULL_MODEL is never used.
6311 */
6312 switch (location) {
6313 case TGSI_INTERPOLATE_LOC_SAMPLE:
6314 key->ps_prolog.color_interp_vgpr_index[i] =
6315 separate_prolog ? 6 : 9;
6316 shader->config.spi_ps_input_ena |=
6317 S_0286CC_LINEAR_SAMPLE_ENA(1);
6318 break;
6319 case TGSI_INTERPOLATE_LOC_CENTER:
6320 key->ps_prolog.color_interp_vgpr_index[i] =
6321 separate_prolog ? 8 : 11;
6322 shader->config.spi_ps_input_ena |=
6323 S_0286CC_LINEAR_CENTER_ENA(1);
6324 break;
6325 case TGSI_INTERPOLATE_LOC_CENTROID:
6326 key->ps_prolog.color_interp_vgpr_index[i] =
6327 separate_prolog ? 10 : 13;
6328 shader->config.spi_ps_input_ena |=
6329 S_0286CC_LINEAR_CENTROID_ENA(1);
6330 break;
6331 default:
6332 assert(0);
6333 }
6334 break;
6335 default:
6336 assert(0);
6337 }
6338 }
6339 }
6340 }
6341
6342 /**
6343 * Check whether a PS prolog is required based on the key.
6344 */
6345 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6346 {
6347 return key->ps_prolog.colors_read ||
6348 key->ps_prolog.states.force_persp_sample_interp ||
6349 key->ps_prolog.states.force_linear_sample_interp ||
6350 key->ps_prolog.states.force_persp_center_interp ||
6351 key->ps_prolog.states.force_linear_center_interp ||
6352 key->ps_prolog.states.bc_optimize_for_persp ||
6353 key->ps_prolog.states.bc_optimize_for_linear ||
6354 key->ps_prolog.states.poly_stipple ||
6355 key->ps_prolog.states.samplemask_log_ps_iter;
6356 }
6357
6358 /**
6359 * Compute the PS epilog key, which contains all the information needed to
6360 * build the PS epilog function.
6361 */
6362 static void si_get_ps_epilog_key(struct si_shader *shader,
6363 union si_shader_part_key *key)
6364 {
6365 struct tgsi_shader_info *info = &shader->selector->info;
6366 memset(key, 0, sizeof(*key));
6367 key->ps_epilog.colors_written = info->colors_written;
6368 key->ps_epilog.writes_z = info->writes_z;
6369 key->ps_epilog.writes_stencil = info->writes_stencil;
6370 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6371 key->ps_epilog.states = shader->key.part.ps.epilog;
6372 }
6373
6374 /**
6375 * Build the GS prolog function. Rotate the input vertices for triangle strips
6376 * with adjacency.
6377 */
6378 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6379 union si_shader_part_key *key)
6380 {
6381 unsigned num_sgprs, num_vgprs;
6382 struct si_function_info fninfo;
6383 LLVMBuilderRef builder = ctx->ac.builder;
6384 LLVMTypeRef returns[48];
6385 LLVMValueRef func, ret;
6386
6387 si_init_function_info(&fninfo);
6388
6389 if (ctx->screen->info.chip_class >= GFX9) {
6390 if (key->gs_prolog.states.gfx9_prev_is_vs)
6391 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6392 else
6393 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6394 num_vgprs = 5; /* ES inputs are not needed by GS */
6395 } else {
6396 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6397 num_vgprs = 8;
6398 }
6399
6400 for (unsigned i = 0; i < num_sgprs; ++i) {
6401 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6402 returns[i] = ctx->i32;
6403 }
6404
6405 for (unsigned i = 0; i < num_vgprs; ++i) {
6406 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6407 returns[num_sgprs + i] = ctx->f32;
6408 }
6409
6410 /* Create the function. */
6411 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6412 &fninfo, 0);
6413 func = ctx->main_fn;
6414
6415 /* Set the full EXEC mask for the prolog, because we are only fiddling
6416 * with registers here. The main shader part will set the correct EXEC
6417 * mask.
6418 */
6419 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6420 ac_init_exec_full_mask(&ctx->ac);
6421
6422 /* Copy inputs to outputs. This should be no-op, as the registers match,
6423 * but it will prevent the compiler from overwriting them unintentionally.
6424 */
6425 ret = ctx->return_value;
6426 for (unsigned i = 0; i < num_sgprs; i++) {
6427 LLVMValueRef p = LLVMGetParam(func, i);
6428 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6429 }
6430 for (unsigned i = 0; i < num_vgprs; i++) {
6431 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6432 p = ac_to_float(&ctx->ac, p);
6433 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6434 }
6435
6436 if (key->gs_prolog.states.tri_strip_adj_fix) {
6437 /* Remap the input vertices for every other primitive. */
6438 const unsigned gfx6_vtx_params[6] = {
6439 num_sgprs,
6440 num_sgprs + 1,
6441 num_sgprs + 3,
6442 num_sgprs + 4,
6443 num_sgprs + 5,
6444 num_sgprs + 6
6445 };
6446 const unsigned gfx9_vtx_params[3] = {
6447 num_sgprs,
6448 num_sgprs + 1,
6449 num_sgprs + 4,
6450 };
6451 LLVMValueRef vtx_in[6], vtx_out[6];
6452 LLVMValueRef prim_id, rotate;
6453
6454 if (ctx->screen->info.chip_class >= GFX9) {
6455 for (unsigned i = 0; i < 3; i++) {
6456 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6457 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6458 }
6459 } else {
6460 for (unsigned i = 0; i < 6; i++)
6461 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6462 }
6463
6464 prim_id = LLVMGetParam(func, num_sgprs + 2);
6465 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6466
6467 for (unsigned i = 0; i < 6; ++i) {
6468 LLVMValueRef base, rotated;
6469 base = vtx_in[i];
6470 rotated = vtx_in[(i + 4) % 6];
6471 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6472 }
6473
6474 if (ctx->screen->info.chip_class >= GFX9) {
6475 for (unsigned i = 0; i < 3; i++) {
6476 LLVMValueRef hi, out;
6477
6478 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6479 LLVMConstInt(ctx->i32, 16, 0), "");
6480 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6481 out = ac_to_float(&ctx->ac, out);
6482 ret = LLVMBuildInsertValue(builder, ret, out,
6483 gfx9_vtx_params[i], "");
6484 }
6485 } else {
6486 for (unsigned i = 0; i < 6; i++) {
6487 LLVMValueRef out;
6488
6489 out = ac_to_float(&ctx->ac, vtx_out[i]);
6490 ret = LLVMBuildInsertValue(builder, ret, out,
6491 gfx6_vtx_params[i], "");
6492 }
6493 }
6494 }
6495
6496 LLVMBuildRet(builder, ret);
6497 }
6498
6499 /**
6500 * Given a list of shader part functions, build a wrapper function that
6501 * runs them in sequence to form a monolithic shader.
6502 */
6503 static void si_build_wrapper_function(struct si_shader_context *ctx,
6504 LLVMValueRef *parts,
6505 unsigned num_parts,
6506 unsigned main_part,
6507 unsigned next_shader_first_part)
6508 {
6509 LLVMBuilderRef builder = ctx->ac.builder;
6510 /* PS epilog has one arg per color component; gfx9 merged shader
6511 * prologs need to forward 32 user SGPRs.
6512 */
6513 struct si_function_info fninfo;
6514 LLVMValueRef initial[64], out[64];
6515 LLVMTypeRef function_type;
6516 unsigned num_first_params;
6517 unsigned num_out, initial_num_out;
6518 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6519 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6520 unsigned num_sgprs, num_vgprs;
6521 unsigned gprs;
6522 struct lp_build_if_state if_state;
6523
6524 si_init_function_info(&fninfo);
6525
6526 for (unsigned i = 0; i < num_parts; ++i) {
6527 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6528 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6529 }
6530
6531 /* The parameters of the wrapper function correspond to those of the
6532 * first part in terms of SGPRs and VGPRs, but we use the types of the
6533 * main part to get the right types. This is relevant for the
6534 * dereferenceable attribute on descriptor table pointers.
6535 */
6536 num_sgprs = 0;
6537 num_vgprs = 0;
6538
6539 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6540 num_first_params = LLVMCountParamTypes(function_type);
6541
6542 for (unsigned i = 0; i < num_first_params; ++i) {
6543 LLVMValueRef param = LLVMGetParam(parts[0], i);
6544
6545 if (ac_is_sgpr_param(param)) {
6546 assert(num_vgprs == 0);
6547 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6548 } else {
6549 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6550 }
6551 }
6552
6553 gprs = 0;
6554 while (gprs < num_sgprs + num_vgprs) {
6555 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6556 LLVMTypeRef type = LLVMTypeOf(param);
6557 unsigned size = ac_get_type_size(type) / 4;
6558
6559 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6560
6561 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6562 assert(gprs + size <= num_sgprs + num_vgprs &&
6563 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6564
6565 gprs += size;
6566 }
6567
6568 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6569 si_get_max_workgroup_size(ctx->shader));
6570
6571 if (is_merged_shader(ctx->shader))
6572 ac_init_exec_full_mask(&ctx->ac);
6573
6574 /* Record the arguments of the function as if they were an output of
6575 * a previous part.
6576 */
6577 num_out = 0;
6578 num_out_sgpr = 0;
6579
6580 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6581 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6582 LLVMTypeRef param_type = LLVMTypeOf(param);
6583 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6584 unsigned size = ac_get_type_size(param_type) / 4;
6585
6586 if (size == 1) {
6587 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6588 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6589 param_type = ctx->i32;
6590 }
6591
6592 if (param_type != out_type)
6593 param = LLVMBuildBitCast(builder, param, out_type, "");
6594 out[num_out++] = param;
6595 } else {
6596 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6597
6598 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6599 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6600 param_type = ctx->i64;
6601 }
6602
6603 if (param_type != vector_type)
6604 param = LLVMBuildBitCast(builder, param, vector_type, "");
6605
6606 for (unsigned j = 0; j < size; ++j)
6607 out[num_out++] = LLVMBuildExtractElement(
6608 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6609 }
6610
6611 if (i < fninfo.num_sgpr_params)
6612 num_out_sgpr = num_out;
6613 }
6614
6615 memcpy(initial, out, sizeof(out));
6616 initial_num_out = num_out;
6617 initial_num_out_sgpr = num_out_sgpr;
6618
6619 /* Now chain the parts. */
6620 for (unsigned part = 0; part < num_parts; ++part) {
6621 LLVMValueRef in[48];
6622 LLVMValueRef ret;
6623 LLVMTypeRef ret_type;
6624 unsigned out_idx = 0;
6625 unsigned num_params = LLVMCountParams(parts[part]);
6626
6627 /* Merged shaders are executed conditionally depending
6628 * on the number of enabled threads passed in the input SGPRs. */
6629 if (is_merged_shader(ctx->shader) && part == 0) {
6630 LLVMValueRef ena, count = initial[3];
6631
6632 count = LLVMBuildAnd(builder, count,
6633 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6634 ena = LLVMBuildICmp(builder, LLVMIntULT,
6635 ac_get_thread_id(&ctx->ac), count, "");
6636 lp_build_if(&if_state, &ctx->gallivm, ena);
6637 }
6638
6639 /* Derive arguments for the next part from outputs of the
6640 * previous one.
6641 */
6642 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6643 LLVMValueRef param;
6644 LLVMTypeRef param_type;
6645 bool is_sgpr;
6646 unsigned param_size;
6647 LLVMValueRef arg = NULL;
6648
6649 param = LLVMGetParam(parts[part], param_idx);
6650 param_type = LLVMTypeOf(param);
6651 param_size = ac_get_type_size(param_type) / 4;
6652 is_sgpr = ac_is_sgpr_param(param);
6653
6654 if (is_sgpr)
6655 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6656 else if (out_idx < num_out_sgpr) {
6657 /* Skip returned SGPRs the current part doesn't
6658 * declare on the input. */
6659 out_idx = num_out_sgpr;
6660 }
6661
6662 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6663
6664 if (param_size == 1)
6665 arg = out[out_idx];
6666 else
6667 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6668
6669 if (LLVMTypeOf(arg) != param_type) {
6670 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6671 if (LLVMGetPointerAddressSpace(param_type) ==
6672 AC_CONST_32BIT_ADDR_SPACE) {
6673 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6674 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6675 } else {
6676 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6677 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6678 }
6679 } else {
6680 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6681 }
6682 }
6683
6684 in[param_idx] = arg;
6685 out_idx += param_size;
6686 }
6687
6688 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6689
6690 if (is_merged_shader(ctx->shader) &&
6691 part + 1 == next_shader_first_part) {
6692 lp_build_endif(&if_state);
6693
6694 /* The second half of the merged shader should use
6695 * the inputs from the toplevel (wrapper) function,
6696 * not the return value from the last call.
6697 *
6698 * That's because the last call was executed condi-
6699 * tionally, so we can't consume it in the main
6700 * block.
6701 */
6702 memcpy(out, initial, sizeof(initial));
6703 num_out = initial_num_out;
6704 num_out_sgpr = initial_num_out_sgpr;
6705 continue;
6706 }
6707
6708 /* Extract the returned GPRs. */
6709 ret_type = LLVMTypeOf(ret);
6710 num_out = 0;
6711 num_out_sgpr = 0;
6712
6713 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6714 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6715
6716 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6717
6718 for (unsigned i = 0; i < ret_size; ++i) {
6719 LLVMValueRef val =
6720 LLVMBuildExtractValue(builder, ret, i, "");
6721
6722 assert(num_out < ARRAY_SIZE(out));
6723 out[num_out++] = val;
6724
6725 if (LLVMTypeOf(val) == ctx->i32) {
6726 assert(num_out_sgpr + 1 == num_out);
6727 num_out_sgpr = num_out;
6728 }
6729 }
6730 }
6731 }
6732
6733 LLVMBuildRetVoid(builder);
6734 }
6735
6736 int si_compile_tgsi_shader(struct si_screen *sscreen,
6737 LLVMTargetMachineRef tm,
6738 struct si_shader *shader,
6739 bool is_monolithic,
6740 struct pipe_debug_callback *debug)
6741 {
6742 struct si_shader_selector *sel = shader->selector;
6743 struct si_shader_context ctx;
6744 int r = -1;
6745
6746 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6747 * conversion fails. */
6748 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6749 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6750 if (sel->tokens)
6751 tgsi_dump(sel->tokens, 0);
6752 else
6753 nir_print_shader(sel->nir, stderr);
6754 si_dump_streamout(&sel->so);
6755 }
6756
6757 si_init_shader_ctx(&ctx, sscreen, tm);
6758 si_llvm_context_set_tgsi(&ctx, shader);
6759 ctx.separate_prolog = !is_monolithic;
6760
6761 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6762 sizeof(shader->info.vs_output_param_offset));
6763
6764 shader->info.uses_instanceid = sel->info.uses_instanceid;
6765
6766 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6767 si_llvm_dispose(&ctx);
6768 return -1;
6769 }
6770
6771 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6772 LLVMValueRef parts[2];
6773 bool need_prolog = sel->vs_needs_prolog;
6774
6775 parts[1] = ctx.main_fn;
6776
6777 if (need_prolog) {
6778 union si_shader_part_key prolog_key;
6779 si_get_vs_prolog_key(&sel->info,
6780 shader->info.num_input_sgprs,
6781 &shader->key.part.vs.prolog,
6782 shader, &prolog_key);
6783 si_build_vs_prolog_function(&ctx, &prolog_key);
6784 parts[0] = ctx.main_fn;
6785 }
6786
6787 si_build_wrapper_function(&ctx, parts + !need_prolog,
6788 1 + need_prolog, need_prolog, 0);
6789 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6790 if (sscreen->info.chip_class >= GFX9) {
6791 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6792 LLVMValueRef parts[4];
6793 bool vs_needs_prolog =
6794 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6795
6796 /* TCS main part */
6797 parts[2] = ctx.main_fn;
6798
6799 /* TCS epilog */
6800 union si_shader_part_key tcs_epilog_key;
6801 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6802 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6803 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6804 parts[3] = ctx.main_fn;
6805
6806 /* VS as LS main part */
6807 struct si_shader shader_ls = {};
6808 shader_ls.selector = ls;
6809 shader_ls.key.as_ls = 1;
6810 shader_ls.key.mono = shader->key.mono;
6811 shader_ls.key.opt = shader->key.opt;
6812 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6813
6814 if (!si_compile_tgsi_main(&ctx, true)) {
6815 si_llvm_dispose(&ctx);
6816 return -1;
6817 }
6818 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6819 parts[1] = ctx.main_fn;
6820
6821 /* LS prolog */
6822 if (vs_needs_prolog) {
6823 union si_shader_part_key vs_prolog_key;
6824 si_get_vs_prolog_key(&ls->info,
6825 shader_ls.info.num_input_sgprs,
6826 &shader->key.part.tcs.ls_prolog,
6827 shader, &vs_prolog_key);
6828 vs_prolog_key.vs_prolog.is_monolithic = true;
6829 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6830 parts[0] = ctx.main_fn;
6831 }
6832
6833 /* Reset the shader context. */
6834 ctx.shader = shader;
6835 ctx.type = PIPE_SHADER_TESS_CTRL;
6836
6837 si_build_wrapper_function(&ctx,
6838 parts + !vs_needs_prolog,
6839 4 - !vs_needs_prolog, 0,
6840 vs_needs_prolog ? 2 : 1);
6841 } else {
6842 LLVMValueRef parts[2];
6843 union si_shader_part_key epilog_key;
6844
6845 parts[0] = ctx.main_fn;
6846
6847 memset(&epilog_key, 0, sizeof(epilog_key));
6848 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6849 si_build_tcs_epilog_function(&ctx, &epilog_key);
6850 parts[1] = ctx.main_fn;
6851
6852 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6853 }
6854 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6855 if (ctx.screen->info.chip_class >= GFX9) {
6856 struct si_shader_selector *es = shader->key.part.gs.es;
6857 LLVMValueRef es_prolog = NULL;
6858 LLVMValueRef es_main = NULL;
6859 LLVMValueRef gs_prolog = NULL;
6860 LLVMValueRef gs_main = ctx.main_fn;
6861
6862 /* GS prolog */
6863 union si_shader_part_key gs_prolog_key;
6864 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6865 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6866 gs_prolog_key.gs_prolog.is_monolithic = true;
6867 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6868 gs_prolog = ctx.main_fn;
6869
6870 /* ES main part */
6871 struct si_shader shader_es = {};
6872 shader_es.selector = es;
6873 shader_es.key.as_es = 1;
6874 shader_es.key.mono = shader->key.mono;
6875 shader_es.key.opt = shader->key.opt;
6876 si_llvm_context_set_tgsi(&ctx, &shader_es);
6877
6878 if (!si_compile_tgsi_main(&ctx, true)) {
6879 si_llvm_dispose(&ctx);
6880 return -1;
6881 }
6882 shader->info.uses_instanceid |= es->info.uses_instanceid;
6883 es_main = ctx.main_fn;
6884
6885 /* ES prolog */
6886 if (es->vs_needs_prolog) {
6887 union si_shader_part_key vs_prolog_key;
6888 si_get_vs_prolog_key(&es->info,
6889 shader_es.info.num_input_sgprs,
6890 &shader->key.part.gs.vs_prolog,
6891 shader, &vs_prolog_key);
6892 vs_prolog_key.vs_prolog.is_monolithic = true;
6893 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6894 es_prolog = ctx.main_fn;
6895 }
6896
6897 /* Reset the shader context. */
6898 ctx.shader = shader;
6899 ctx.type = PIPE_SHADER_GEOMETRY;
6900
6901 /* Prepare the array of shader parts. */
6902 LLVMValueRef parts[4];
6903 unsigned num_parts = 0, main_part, next_first_part;
6904
6905 if (es_prolog)
6906 parts[num_parts++] = es_prolog;
6907
6908 parts[main_part = num_parts++] = es_main;
6909 parts[next_first_part = num_parts++] = gs_prolog;
6910 parts[num_parts++] = gs_main;
6911
6912 si_build_wrapper_function(&ctx, parts, num_parts,
6913 main_part, next_first_part);
6914 } else {
6915 LLVMValueRef parts[2];
6916 union si_shader_part_key prolog_key;
6917
6918 parts[1] = ctx.main_fn;
6919
6920 memset(&prolog_key, 0, sizeof(prolog_key));
6921 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6922 si_build_gs_prolog_function(&ctx, &prolog_key);
6923 parts[0] = ctx.main_fn;
6924
6925 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6926 }
6927 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6928 LLVMValueRef parts[3];
6929 union si_shader_part_key prolog_key;
6930 union si_shader_part_key epilog_key;
6931 bool need_prolog;
6932
6933 si_get_ps_prolog_key(shader, &prolog_key, false);
6934 need_prolog = si_need_ps_prolog(&prolog_key);
6935
6936 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6937
6938 if (need_prolog) {
6939 si_build_ps_prolog_function(&ctx, &prolog_key);
6940 parts[0] = ctx.main_fn;
6941 }
6942
6943 si_get_ps_epilog_key(shader, &epilog_key);
6944 si_build_ps_epilog_function(&ctx, &epilog_key);
6945 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6946
6947 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6948 need_prolog ? 1 : 0, 0);
6949 }
6950
6951 si_llvm_optimize_module(&ctx);
6952
6953 /* Post-optimization transformations and analysis. */
6954 si_optimize_vs_outputs(&ctx);
6955
6956 if ((debug && debug->debug_message) ||
6957 si_can_dump_shader(sscreen, ctx.type)) {
6958 ctx.shader->config.private_mem_vgprs =
6959 ac_count_scratch_private_memory(ctx.main_fn);
6960 }
6961
6962 /* Compile to bytecode. */
6963 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6964 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6965 si_llvm_dispose(&ctx);
6966 if (r) {
6967 fprintf(stderr, "LLVM failed to compile shader\n");
6968 return r;
6969 }
6970
6971 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6972 * LLVM 3.9svn has this bug.
6973 */
6974 if (sel->type == PIPE_SHADER_COMPUTE) {
6975 unsigned wave_size = 64;
6976 unsigned max_vgprs = 256;
6977 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6978 unsigned max_sgprs_per_wave = 128;
6979 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6980 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6981 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6982
6983 max_vgprs = max_vgprs / min_waves_per_simd;
6984 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6985
6986 if (shader->config.num_sgprs > max_sgprs ||
6987 shader->config.num_vgprs > max_vgprs) {
6988 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6989 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6990 shader->config.num_sgprs, shader->config.num_vgprs,
6991 max_sgprs, max_vgprs);
6992
6993 /* Just terminate the process, because dependent
6994 * shaders can hang due to bad input data, but use
6995 * the env var to allow shader-db to work.
6996 */
6997 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6998 abort();
6999 }
7000 }
7001
7002 /* Add the scratch offset to input SGPRs. */
7003 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
7004 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7005
7006 /* Calculate the number of fragment input VGPRs. */
7007 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7008 shader->info.num_input_vgprs = 0;
7009 shader->info.face_vgpr_index = -1;
7010 shader->info.ancillary_vgpr_index = -1;
7011
7012 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7013 shader->info.num_input_vgprs += 2;
7014 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7015 shader->info.num_input_vgprs += 2;
7016 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7017 shader->info.num_input_vgprs += 2;
7018 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7019 shader->info.num_input_vgprs += 3;
7020 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7021 shader->info.num_input_vgprs += 2;
7022 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7023 shader->info.num_input_vgprs += 2;
7024 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7025 shader->info.num_input_vgprs += 2;
7026 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7027 shader->info.num_input_vgprs += 1;
7028 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7029 shader->info.num_input_vgprs += 1;
7030 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7031 shader->info.num_input_vgprs += 1;
7032 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7033 shader->info.num_input_vgprs += 1;
7034 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7035 shader->info.num_input_vgprs += 1;
7036 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7037 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7038 shader->info.num_input_vgprs += 1;
7039 }
7040 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7041 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7042 shader->info.num_input_vgprs += 1;
7043 }
7044 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7045 shader->info.num_input_vgprs += 1;
7046 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7047 shader->info.num_input_vgprs += 1;
7048 }
7049
7050 si_calculate_max_simd_waves(shader);
7051 si_shader_dump_stats_for_shader_db(shader, debug);
7052 return 0;
7053 }
7054
7055 /**
7056 * Create, compile and return a shader part (prolog or epilog).
7057 *
7058 * \param sscreen screen
7059 * \param list list of shader parts of the same category
7060 * \param type shader type
7061 * \param key shader part key
7062 * \param prolog whether the part being requested is a prolog
7063 * \param tm LLVM target machine
7064 * \param debug debug callback
7065 * \param build the callback responsible for building the main function
7066 * \return non-NULL on success
7067 */
7068 static struct si_shader_part *
7069 si_get_shader_part(struct si_screen *sscreen,
7070 struct si_shader_part **list,
7071 enum pipe_shader_type type,
7072 bool prolog,
7073 union si_shader_part_key *key,
7074 LLVMTargetMachineRef tm,
7075 struct pipe_debug_callback *debug,
7076 void (*build)(struct si_shader_context *,
7077 union si_shader_part_key *),
7078 const char *name)
7079 {
7080 struct si_shader_part *result;
7081
7082 mtx_lock(&sscreen->shader_parts_mutex);
7083
7084 /* Find existing. */
7085 for (result = *list; result; result = result->next) {
7086 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7087 mtx_unlock(&sscreen->shader_parts_mutex);
7088 return result;
7089 }
7090 }
7091
7092 /* Compile a new one. */
7093 result = CALLOC_STRUCT(si_shader_part);
7094 result->key = *key;
7095
7096 struct si_shader shader = {};
7097 struct si_shader_context ctx;
7098
7099 si_init_shader_ctx(&ctx, sscreen, tm);
7100 ctx.shader = &shader;
7101 ctx.type = type;
7102
7103 switch (type) {
7104 case PIPE_SHADER_VERTEX:
7105 shader.key.as_ls = key->vs_prolog.as_ls;
7106 shader.key.as_es = key->vs_prolog.as_es;
7107 break;
7108 case PIPE_SHADER_TESS_CTRL:
7109 assert(!prolog);
7110 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7111 break;
7112 case PIPE_SHADER_GEOMETRY:
7113 assert(prolog);
7114 break;
7115 case PIPE_SHADER_FRAGMENT:
7116 if (prolog)
7117 shader.key.part.ps.prolog = key->ps_prolog.states;
7118 else
7119 shader.key.part.ps.epilog = key->ps_epilog.states;
7120 break;
7121 default:
7122 unreachable("bad shader part");
7123 }
7124
7125 build(&ctx, key);
7126
7127 /* Compile. */
7128 si_llvm_optimize_module(&ctx);
7129
7130 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7131 ctx.ac.module, debug, ctx.type, name)) {
7132 FREE(result);
7133 result = NULL;
7134 goto out;
7135 }
7136
7137 result->next = *list;
7138 *list = result;
7139
7140 out:
7141 si_llvm_dispose(&ctx);
7142 mtx_unlock(&sscreen->shader_parts_mutex);
7143 return result;
7144 }
7145
7146 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7147 {
7148 LLVMValueRef ptr[2], list;
7149 bool is_merged_shader =
7150 ctx->screen->info.chip_class >= GFX9 &&
7151 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7152 ctx->type == PIPE_SHADER_GEOMETRY ||
7153 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7154
7155 if (HAVE_32BIT_POINTERS) {
7156 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7157 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7158 ac_array_in_const32_addr_space(ctx->v4i32), "");
7159 return list;
7160 }
7161
7162 /* Get the pointer to rw buffers. */
7163 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7164 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7165 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7166 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7167 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7168 ac_array_in_const_addr_space(ctx->v4i32), "");
7169 return list;
7170 }
7171
7172 /**
7173 * Build the vertex shader prolog function.
7174 *
7175 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7176 * All inputs are returned unmodified. The vertex load indices are
7177 * stored after them, which will be used by the API VS for fetching inputs.
7178 *
7179 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7180 * input_v0,
7181 * input_v1,
7182 * input_v2,
7183 * input_v3,
7184 * (VertexID + BaseVertex),
7185 * (InstanceID + StartInstance),
7186 * (InstanceID / 2 + StartInstance)
7187 */
7188 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7189 union si_shader_part_key *key)
7190 {
7191 struct si_function_info fninfo;
7192 LLVMTypeRef *returns;
7193 LLVMValueRef ret, func;
7194 int num_returns, i;
7195 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7196 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7197 LLVMValueRef input_vgprs[9];
7198 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7199 num_input_vgprs;
7200 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7201
7202 si_init_function_info(&fninfo);
7203
7204 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7205 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7206 sizeof(LLVMTypeRef));
7207 num_returns = 0;
7208
7209 /* Declare input and output SGPRs. */
7210 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7211 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7212 returns[num_returns++] = ctx->i32;
7213 }
7214
7215 /* Preloaded VGPRs (outputs must be floats) */
7216 for (i = 0; i < num_input_vgprs; i++) {
7217 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7218 returns[num_returns++] = ctx->f32;
7219 }
7220
7221 /* Vertex load indices. */
7222 for (i = 0; i <= key->vs_prolog.last_input; i++)
7223 returns[num_returns++] = ctx->f32;
7224
7225 /* Create the function. */
7226 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7227 func = ctx->main_fn;
7228
7229 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7230 if (!key->vs_prolog.is_monolithic)
7231 si_init_exec_from_input(ctx, 3, 0);
7232
7233 if (key->vs_prolog.as_ls &&
7234 ctx->screen->has_ls_vgpr_init_bug) {
7235 /* If there are no HS threads, SPI loads the LS VGPRs
7236 * starting at VGPR 0. Shift them back to where they
7237 * belong.
7238 */
7239 LLVMValueRef has_hs_threads =
7240 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7241 unpack_param(ctx, 3, 8, 8),
7242 ctx->i32_0, "");
7243
7244 for (i = 4; i > 0; --i) {
7245 input_vgprs[i + 1] =
7246 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7247 input_vgprs[i + 1],
7248 input_vgprs[i - 1], "");
7249 }
7250 }
7251 }
7252
7253 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7254 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7255
7256 /* Copy inputs to outputs. This should be no-op, as the registers match,
7257 * but it will prevent the compiler from overwriting them unintentionally.
7258 */
7259 ret = ctx->return_value;
7260 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7261 LLVMValueRef p = LLVMGetParam(func, i);
7262 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7263 }
7264 for (i = 0; i < num_input_vgprs; i++) {
7265 LLVMValueRef p = input_vgprs[i];
7266 p = ac_to_float(&ctx->ac, p);
7267 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7268 key->vs_prolog.num_input_sgprs + i, "");
7269 }
7270
7271 /* Compute vertex load indices from instance divisors. */
7272 LLVMValueRef instance_divisor_constbuf = NULL;
7273
7274 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7275 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7276 LLVMValueRef buf_index =
7277 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7278 instance_divisor_constbuf =
7279 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7280 }
7281
7282 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7283 bool divisor_is_one =
7284 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7285 bool divisor_is_fetched =
7286 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7287 LLVMValueRef index;
7288
7289 if (divisor_is_one || divisor_is_fetched) {
7290 LLVMValueRef divisor = ctx->i32_1;
7291
7292 if (divisor_is_fetched) {
7293 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7294 LLVMConstInt(ctx->i32, i * 4, 0));
7295 divisor = ac_to_integer(&ctx->ac, divisor);
7296 }
7297
7298 /* InstanceID / Divisor + StartInstance */
7299 index = get_instance_index_for_fetch(ctx,
7300 user_sgpr_base +
7301 SI_SGPR_START_INSTANCE,
7302 divisor);
7303 } else {
7304 /* VertexID + BaseVertex */
7305 index = LLVMBuildAdd(ctx->ac.builder,
7306 ctx->abi.vertex_id,
7307 LLVMGetParam(func, user_sgpr_base +
7308 SI_SGPR_BASE_VERTEX), "");
7309 }
7310
7311 index = ac_to_float(&ctx->ac, index);
7312 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7313 fninfo.num_params + i, "");
7314 }
7315
7316 si_llvm_build_ret(ctx, ret);
7317 }
7318
7319 static bool si_get_vs_prolog(struct si_screen *sscreen,
7320 LLVMTargetMachineRef tm,
7321 struct si_shader *shader,
7322 struct pipe_debug_callback *debug,
7323 struct si_shader *main_part,
7324 const struct si_vs_prolog_bits *key)
7325 {
7326 struct si_shader_selector *vs = main_part->selector;
7327
7328 if (!si_vs_needs_prolog(vs, key))
7329 return true;
7330
7331 /* Get the prolog. */
7332 union si_shader_part_key prolog_key;
7333 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7334 key, shader, &prolog_key);
7335
7336 shader->prolog =
7337 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7338 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7339 debug, si_build_vs_prolog_function,
7340 "Vertex Shader Prolog");
7341 return shader->prolog != NULL;
7342 }
7343
7344 /**
7345 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7346 */
7347 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7348 LLVMTargetMachineRef tm,
7349 struct si_shader *shader,
7350 struct pipe_debug_callback *debug)
7351 {
7352 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7353 &shader->key.part.vs.prolog);
7354 }
7355
7356 /**
7357 * Compile the TCS epilog function. This writes tesselation factors to memory
7358 * based on the output primitive type of the tesselator (determined by TES).
7359 */
7360 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7361 union si_shader_part_key *key)
7362 {
7363 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7364 struct si_function_info fninfo;
7365 LLVMValueRef func;
7366
7367 si_init_function_info(&fninfo);
7368
7369 if (ctx->screen->info.chip_class >= GFX9) {
7370 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7371 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7372 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7373 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7374 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7375 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7376 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7377 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7378 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7379 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7380 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7381 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7382 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7383 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7384 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7385 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7386 if (!HAVE_32BIT_POINTERS)
7387 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7388 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7389 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7390 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7391 } else {
7392 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7393 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7394 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7395 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7396 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7397 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7398 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7399 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7400 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7401 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7402 }
7403
7404 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7405 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7406 unsigned tess_factors_idx =
7407 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7408 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7409 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7410
7411 for (unsigned i = 0; i < 6; i++)
7412 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7413
7414 /* Create the function. */
7415 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7416 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7417 ac_declare_lds_as_pointer(&ctx->ac);
7418 func = ctx->main_fn;
7419
7420 LLVMValueRef invoc0_tess_factors[6];
7421 for (unsigned i = 0; i < 6; i++)
7422 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7423
7424 si_write_tess_factors(bld_base,
7425 LLVMGetParam(func, tess_factors_idx),
7426 LLVMGetParam(func, tess_factors_idx + 1),
7427 LLVMGetParam(func, tess_factors_idx + 2),
7428 invoc0_tess_factors, invoc0_tess_factors + 4);
7429
7430 LLVMBuildRetVoid(ctx->ac.builder);
7431 }
7432
7433 /**
7434 * Select and compile (or reuse) TCS parts (epilog).
7435 */
7436 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7437 LLVMTargetMachineRef tm,
7438 struct si_shader *shader,
7439 struct pipe_debug_callback *debug)
7440 {
7441 if (sscreen->info.chip_class >= GFX9) {
7442 struct si_shader *ls_main_part =
7443 shader->key.part.tcs.ls->main_shader_part_ls;
7444
7445 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7446 &shader->key.part.tcs.ls_prolog))
7447 return false;
7448
7449 shader->previous_stage = ls_main_part;
7450 }
7451
7452 /* Get the epilog. */
7453 union si_shader_part_key epilog_key;
7454 memset(&epilog_key, 0, sizeof(epilog_key));
7455 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7456
7457 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7458 PIPE_SHADER_TESS_CTRL, false,
7459 &epilog_key, tm, debug,
7460 si_build_tcs_epilog_function,
7461 "Tessellation Control Shader Epilog");
7462 return shader->epilog != NULL;
7463 }
7464
7465 /**
7466 * Select and compile (or reuse) GS parts (prolog).
7467 */
7468 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7469 LLVMTargetMachineRef tm,
7470 struct si_shader *shader,
7471 struct pipe_debug_callback *debug)
7472 {
7473 if (sscreen->info.chip_class >= GFX9) {
7474 struct si_shader *es_main_part =
7475 shader->key.part.gs.es->main_shader_part_es;
7476
7477 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7478 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7479 &shader->key.part.gs.vs_prolog))
7480 return false;
7481
7482 shader->previous_stage = es_main_part;
7483 }
7484
7485 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7486 return true;
7487
7488 union si_shader_part_key prolog_key;
7489 memset(&prolog_key, 0, sizeof(prolog_key));
7490 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7491
7492 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7493 PIPE_SHADER_GEOMETRY, true,
7494 &prolog_key, tm, debug,
7495 si_build_gs_prolog_function,
7496 "Geometry Shader Prolog");
7497 return shader->prolog2 != NULL;
7498 }
7499
7500 /**
7501 * Build the pixel shader prolog function. This handles:
7502 * - two-side color selection and interpolation
7503 * - overriding interpolation parameters for the API PS
7504 * - polygon stippling
7505 *
7506 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7507 * overriden by other states. (e.g. per-sample interpolation)
7508 * Interpolated colors are stored after the preloaded VGPRs.
7509 */
7510 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7511 union si_shader_part_key *key)
7512 {
7513 struct si_function_info fninfo;
7514 LLVMValueRef ret, func;
7515 int num_returns, i, num_color_channels;
7516
7517 assert(si_need_ps_prolog(key));
7518
7519 si_init_function_info(&fninfo);
7520
7521 /* Declare inputs. */
7522 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7523 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7524
7525 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7526 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7527
7528 /* Declare outputs (same as inputs + add colors if needed) */
7529 num_returns = fninfo.num_params;
7530 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7531 for (i = 0; i < num_color_channels; i++)
7532 fninfo.types[num_returns++] = ctx->f32;
7533
7534 /* Create the function. */
7535 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7536 &fninfo, 0);
7537 func = ctx->main_fn;
7538
7539 /* Copy inputs to outputs. This should be no-op, as the registers match,
7540 * but it will prevent the compiler from overwriting them unintentionally.
7541 */
7542 ret = ctx->return_value;
7543 for (i = 0; i < fninfo.num_params; i++) {
7544 LLVMValueRef p = LLVMGetParam(func, i);
7545 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7546 }
7547
7548 /* Polygon stippling. */
7549 if (key->ps_prolog.states.poly_stipple) {
7550 /* POS_FIXED_PT is always last. */
7551 unsigned pos = key->ps_prolog.num_input_sgprs +
7552 key->ps_prolog.num_input_vgprs - 1;
7553 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7554
7555 si_llvm_emit_polygon_stipple(ctx, list, pos);
7556 }
7557
7558 if (key->ps_prolog.states.bc_optimize_for_persp ||
7559 key->ps_prolog.states.bc_optimize_for_linear) {
7560 unsigned i, base = key->ps_prolog.num_input_sgprs;
7561 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7562
7563 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7564 * The hw doesn't compute CENTROID if the whole wave only
7565 * contains fully-covered quads.
7566 *
7567 * PRIM_MASK is after user SGPRs.
7568 */
7569 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7570 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7571 LLVMConstInt(ctx->i32, 31, 0), "");
7572 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7573 ctx->i1, "");
7574
7575 if (key->ps_prolog.states.bc_optimize_for_persp) {
7576 /* Read PERSP_CENTER. */
7577 for (i = 0; i < 2; i++)
7578 center[i] = LLVMGetParam(func, base + 2 + i);
7579 /* Read PERSP_CENTROID. */
7580 for (i = 0; i < 2; i++)
7581 centroid[i] = LLVMGetParam(func, base + 4 + i);
7582 /* Select PERSP_CENTROID. */
7583 for (i = 0; i < 2; i++) {
7584 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7585 center[i], centroid[i], "");
7586 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7587 tmp, base + 4 + i, "");
7588 }
7589 }
7590 if (key->ps_prolog.states.bc_optimize_for_linear) {
7591 /* Read LINEAR_CENTER. */
7592 for (i = 0; i < 2; i++)
7593 center[i] = LLVMGetParam(func, base + 8 + i);
7594 /* Read LINEAR_CENTROID. */
7595 for (i = 0; i < 2; i++)
7596 centroid[i] = LLVMGetParam(func, base + 10 + i);
7597 /* Select LINEAR_CENTROID. */
7598 for (i = 0; i < 2; i++) {
7599 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7600 center[i], centroid[i], "");
7601 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7602 tmp, base + 10 + i, "");
7603 }
7604 }
7605 }
7606
7607 /* Force per-sample interpolation. */
7608 if (key->ps_prolog.states.force_persp_sample_interp) {
7609 unsigned i, base = key->ps_prolog.num_input_sgprs;
7610 LLVMValueRef persp_sample[2];
7611
7612 /* Read PERSP_SAMPLE. */
7613 for (i = 0; i < 2; i++)
7614 persp_sample[i] = LLVMGetParam(func, base + i);
7615 /* Overwrite PERSP_CENTER. */
7616 for (i = 0; i < 2; i++)
7617 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7618 persp_sample[i], base + 2 + i, "");
7619 /* Overwrite PERSP_CENTROID. */
7620 for (i = 0; i < 2; i++)
7621 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7622 persp_sample[i], base + 4 + i, "");
7623 }
7624 if (key->ps_prolog.states.force_linear_sample_interp) {
7625 unsigned i, base = key->ps_prolog.num_input_sgprs;
7626 LLVMValueRef linear_sample[2];
7627
7628 /* Read LINEAR_SAMPLE. */
7629 for (i = 0; i < 2; i++)
7630 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7631 /* Overwrite LINEAR_CENTER. */
7632 for (i = 0; i < 2; i++)
7633 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7634 linear_sample[i], base + 8 + i, "");
7635 /* Overwrite LINEAR_CENTROID. */
7636 for (i = 0; i < 2; i++)
7637 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7638 linear_sample[i], base + 10 + i, "");
7639 }
7640
7641 /* Force center interpolation. */
7642 if (key->ps_prolog.states.force_persp_center_interp) {
7643 unsigned i, base = key->ps_prolog.num_input_sgprs;
7644 LLVMValueRef persp_center[2];
7645
7646 /* Read PERSP_CENTER. */
7647 for (i = 0; i < 2; i++)
7648 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7649 /* Overwrite PERSP_SAMPLE. */
7650 for (i = 0; i < 2; i++)
7651 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7652 persp_center[i], base + i, "");
7653 /* Overwrite PERSP_CENTROID. */
7654 for (i = 0; i < 2; i++)
7655 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7656 persp_center[i], base + 4 + i, "");
7657 }
7658 if (key->ps_prolog.states.force_linear_center_interp) {
7659 unsigned i, base = key->ps_prolog.num_input_sgprs;
7660 LLVMValueRef linear_center[2];
7661
7662 /* Read LINEAR_CENTER. */
7663 for (i = 0; i < 2; i++)
7664 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7665 /* Overwrite LINEAR_SAMPLE. */
7666 for (i = 0; i < 2; i++)
7667 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7668 linear_center[i], base + 6 + i, "");
7669 /* Overwrite LINEAR_CENTROID. */
7670 for (i = 0; i < 2; i++)
7671 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7672 linear_center[i], base + 10 + i, "");
7673 }
7674
7675 /* Interpolate colors. */
7676 unsigned color_out_idx = 0;
7677 for (i = 0; i < 2; i++) {
7678 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7679 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7680 key->ps_prolog.face_vgpr_index;
7681 LLVMValueRef interp[2], color[4];
7682 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7683
7684 if (!writemask)
7685 continue;
7686
7687 /* If the interpolation qualifier is not CONSTANT (-1). */
7688 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7689 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7690 key->ps_prolog.color_interp_vgpr_index[i];
7691
7692 /* Get the (i,j) updated by bc_optimize handling. */
7693 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7694 interp_vgpr, "");
7695 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7696 interp_vgpr + 1, "");
7697 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7698 }
7699
7700 /* Use the absolute location of the input. */
7701 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7702
7703 if (key->ps_prolog.states.color_two_side) {
7704 face = LLVMGetParam(func, face_vgpr);
7705 face = ac_to_integer(&ctx->ac, face);
7706 }
7707
7708 interp_fs_input(ctx,
7709 key->ps_prolog.color_attr_index[i],
7710 TGSI_SEMANTIC_COLOR, i,
7711 key->ps_prolog.num_interp_inputs,
7712 key->ps_prolog.colors_read, interp_ij,
7713 prim_mask, face, color);
7714
7715 while (writemask) {
7716 unsigned chan = u_bit_scan(&writemask);
7717 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7718 fninfo.num_params + color_out_idx++, "");
7719 }
7720 }
7721
7722 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7723 * says:
7724 *
7725 * "When per-sample shading is active due to the use of a fragment
7726 * input qualified by sample or due to the use of the gl_SampleID
7727 * or gl_SamplePosition variables, only the bit for the current
7728 * sample is set in gl_SampleMaskIn. When state specifies multiple
7729 * fragment shader invocations for a given fragment, the sample
7730 * mask for any single fragment shader invocation may specify a
7731 * subset of the covered samples for the fragment. In this case,
7732 * the bit corresponding to each covered sample will be set in
7733 * exactly one fragment shader invocation."
7734 *
7735 * The samplemask loaded by hardware is always the coverage of the
7736 * entire pixel/fragment, so mask bits out based on the sample ID.
7737 */
7738 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7739 /* The bit pattern matches that used by fixed function fragment
7740 * processing. */
7741 static const uint16_t ps_iter_masks[] = {
7742 0xffff, /* not used */
7743 0x5555,
7744 0x1111,
7745 0x0101,
7746 0x0001,
7747 };
7748 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7749
7750 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7751 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7752 key->ps_prolog.ancillary_vgpr_index;
7753 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7754 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7755
7756 samplemask = ac_to_integer(&ctx->ac, samplemask);
7757 samplemask = LLVMBuildAnd(
7758 ctx->ac.builder,
7759 samplemask,
7760 LLVMBuildShl(ctx->ac.builder,
7761 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7762 sampleid, ""),
7763 "");
7764 samplemask = ac_to_float(&ctx->ac, samplemask);
7765
7766 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7767 ancillary_vgpr + 1, "");
7768 }
7769
7770 /* Tell LLVM to insert WQM instruction sequence when needed. */
7771 if (key->ps_prolog.wqm) {
7772 LLVMAddTargetDependentFunctionAttr(func,
7773 "amdgpu-ps-wqm-outputs", "");
7774 }
7775
7776 si_llvm_build_ret(ctx, ret);
7777 }
7778
7779 /**
7780 * Build the pixel shader epilog function. This handles everything that must be
7781 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7782 */
7783 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7784 union si_shader_part_key *key)
7785 {
7786 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7787 struct si_function_info fninfo;
7788 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7789 int i;
7790 struct si_ps_exports exp = {};
7791
7792 si_init_function_info(&fninfo);
7793
7794 /* Declare input SGPRs. */
7795 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7796 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7797 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7798 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7799 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7800
7801 /* Declare input VGPRs. */
7802 unsigned required_num_params =
7803 fninfo.num_sgpr_params +
7804 util_bitcount(key->ps_epilog.colors_written) * 4 +
7805 key->ps_epilog.writes_z +
7806 key->ps_epilog.writes_stencil +
7807 key->ps_epilog.writes_samplemask;
7808
7809 required_num_params = MAX2(required_num_params,
7810 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7811
7812 while (fninfo.num_params < required_num_params)
7813 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7814
7815 /* Create the function. */
7816 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7817 /* Disable elimination of unused inputs. */
7818 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7819 "InitialPSInputAddr", 0xffffff);
7820
7821 /* Process colors. */
7822 unsigned vgpr = fninfo.num_sgpr_params;
7823 unsigned colors_written = key->ps_epilog.colors_written;
7824 int last_color_export = -1;
7825
7826 /* Find the last color export. */
7827 if (!key->ps_epilog.writes_z &&
7828 !key->ps_epilog.writes_stencil &&
7829 !key->ps_epilog.writes_samplemask) {
7830 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7831
7832 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7833 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7834 /* Just set this if any of the colorbuffers are enabled. */
7835 if (spi_format &
7836 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7837 last_color_export = 0;
7838 } else {
7839 for (i = 0; i < 8; i++)
7840 if (colors_written & (1 << i) &&
7841 (spi_format >> (i * 4)) & 0xf)
7842 last_color_export = i;
7843 }
7844 }
7845
7846 while (colors_written) {
7847 LLVMValueRef color[4];
7848 int mrt = u_bit_scan(&colors_written);
7849
7850 for (i = 0; i < 4; i++)
7851 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7852
7853 si_export_mrt_color(bld_base, color, mrt,
7854 fninfo.num_params - 1,
7855 mrt == last_color_export, &exp);
7856 }
7857
7858 /* Process depth, stencil, samplemask. */
7859 if (key->ps_epilog.writes_z)
7860 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7861 if (key->ps_epilog.writes_stencil)
7862 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7863 if (key->ps_epilog.writes_samplemask)
7864 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7865
7866 if (depth || stencil || samplemask)
7867 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7868 else if (last_color_export == -1)
7869 ac_build_export_null(&ctx->ac);
7870
7871 if (exp.num)
7872 si_emit_ps_exports(ctx, &exp);
7873
7874 /* Compile. */
7875 LLVMBuildRetVoid(ctx->ac.builder);
7876 }
7877
7878 /**
7879 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7880 */
7881 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7882 LLVMTargetMachineRef tm,
7883 struct si_shader *shader,
7884 struct pipe_debug_callback *debug)
7885 {
7886 union si_shader_part_key prolog_key;
7887 union si_shader_part_key epilog_key;
7888
7889 /* Get the prolog. */
7890 si_get_ps_prolog_key(shader, &prolog_key, true);
7891
7892 /* The prolog is a no-op if these aren't set. */
7893 if (si_need_ps_prolog(&prolog_key)) {
7894 shader->prolog =
7895 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7896 PIPE_SHADER_FRAGMENT, true,
7897 &prolog_key, tm, debug,
7898 si_build_ps_prolog_function,
7899 "Fragment Shader Prolog");
7900 if (!shader->prolog)
7901 return false;
7902 }
7903
7904 /* Get the epilog. */
7905 si_get_ps_epilog_key(shader, &epilog_key);
7906
7907 shader->epilog =
7908 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7909 PIPE_SHADER_FRAGMENT, false,
7910 &epilog_key, tm, debug,
7911 si_build_ps_epilog_function,
7912 "Fragment Shader Epilog");
7913 if (!shader->epilog)
7914 return false;
7915
7916 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7917 if (shader->key.part.ps.prolog.poly_stipple) {
7918 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7919 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7920 }
7921
7922 /* Set up the enable bits for per-sample shading if needed. */
7923 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7924 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7925 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7926 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7927 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7928 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7929 }
7930 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7931 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7932 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7933 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7934 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7935 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7936 }
7937 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7938 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7939 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7940 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7941 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7942 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7943 }
7944 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7945 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7946 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7947 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7948 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7949 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7950 }
7951
7952 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7953 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7954 !(shader->config.spi_ps_input_ena & 0xf)) {
7955 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7956 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7957 }
7958
7959 /* At least one pair of interpolation weights must be enabled. */
7960 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7961 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7962 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7963 }
7964
7965 /* Samplemask fixup requires the sample ID. */
7966 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7967 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7968 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7969 }
7970
7971 /* The sample mask input is always enabled, because the API shader always
7972 * passes it through to the epilog. Disable it here if it's unused.
7973 */
7974 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7975 !shader->selector->info.reads_samplemask)
7976 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7977
7978 return true;
7979 }
7980
7981 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7982 unsigned *lds_size)
7983 {
7984 /* If tessellation is all offchip and on-chip GS isn't used, this
7985 * workaround is not needed.
7986 */
7987 return;
7988
7989 /* SPI barrier management bug:
7990 * Make sure we have at least 4k of LDS in use to avoid the bug.
7991 * It applies to workgroup sizes of more than one wavefront.
7992 */
7993 if (sscreen->info.family == CHIP_BONAIRE ||
7994 sscreen->info.family == CHIP_KABINI ||
7995 sscreen->info.family == CHIP_MULLINS)
7996 *lds_size = MAX2(*lds_size, 8);
7997 }
7998
7999 static void si_fix_resource_usage(struct si_screen *sscreen,
8000 struct si_shader *shader)
8001 {
8002 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8003
8004 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8005
8006 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8007 si_get_max_workgroup_size(shader) > 64) {
8008 si_multiwave_lds_size_workaround(sscreen,
8009 &shader->config.lds_size);
8010 }
8011 }
8012
8013 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8014 struct si_shader *shader,
8015 struct pipe_debug_callback *debug)
8016 {
8017 struct si_shader_selector *sel = shader->selector;
8018 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8019 int r;
8020
8021 /* LS, ES, VS are compiled on demand if the main part hasn't been
8022 * compiled for that stage.
8023 *
8024 * Vertex shaders are compiled on demand when a vertex fetch
8025 * workaround must be applied.
8026 */
8027 if (shader->is_monolithic) {
8028 /* Monolithic shader (compiled as a whole, has many variants,
8029 * may take a long time to compile).
8030 */
8031 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8032 if (r)
8033 return r;
8034 } else {
8035 /* The shader consists of several parts:
8036 *
8037 * - the middle part is the user shader, it has 1 variant only
8038 * and it was compiled during the creation of the shader
8039 * selector
8040 * - the prolog part is inserted at the beginning
8041 * - the epilog part is inserted at the end
8042 *
8043 * The prolog and epilog have many (but simple) variants.
8044 *
8045 * Starting with gfx9, geometry and tessellation control
8046 * shaders also contain the prolog and user shader parts of
8047 * the previous shader stage.
8048 */
8049
8050 if (!mainp)
8051 return -1;
8052
8053 /* Copy the compiled TGSI shader data over. */
8054 shader->is_binary_shared = true;
8055 shader->binary = mainp->binary;
8056 shader->config = mainp->config;
8057 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8058 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8059 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8060 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8061 memcpy(shader->info.vs_output_param_offset,
8062 mainp->info.vs_output_param_offset,
8063 sizeof(mainp->info.vs_output_param_offset));
8064 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8065 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8066 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8067
8068 /* Select prologs and/or epilogs. */
8069 switch (sel->type) {
8070 case PIPE_SHADER_VERTEX:
8071 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8072 return -1;
8073 break;
8074 case PIPE_SHADER_TESS_CTRL:
8075 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8076 return -1;
8077 break;
8078 case PIPE_SHADER_TESS_EVAL:
8079 break;
8080 case PIPE_SHADER_GEOMETRY:
8081 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8082 return -1;
8083 break;
8084 case PIPE_SHADER_FRAGMENT:
8085 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8086 return -1;
8087
8088 /* Make sure we have at least as many VGPRs as there
8089 * are allocated inputs.
8090 */
8091 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8092 shader->info.num_input_vgprs);
8093 break;
8094 }
8095
8096 /* Update SGPR and VGPR counts. */
8097 if (shader->prolog) {
8098 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8099 shader->prolog->config.num_sgprs);
8100 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8101 shader->prolog->config.num_vgprs);
8102 }
8103 if (shader->previous_stage) {
8104 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8105 shader->previous_stage->config.num_sgprs);
8106 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8107 shader->previous_stage->config.num_vgprs);
8108 shader->config.spilled_sgprs =
8109 MAX2(shader->config.spilled_sgprs,
8110 shader->previous_stage->config.spilled_sgprs);
8111 shader->config.spilled_vgprs =
8112 MAX2(shader->config.spilled_vgprs,
8113 shader->previous_stage->config.spilled_vgprs);
8114 shader->config.private_mem_vgprs =
8115 MAX2(shader->config.private_mem_vgprs,
8116 shader->previous_stage->config.private_mem_vgprs);
8117 shader->config.scratch_bytes_per_wave =
8118 MAX2(shader->config.scratch_bytes_per_wave,
8119 shader->previous_stage->config.scratch_bytes_per_wave);
8120 shader->info.uses_instanceid |=
8121 shader->previous_stage->info.uses_instanceid;
8122 }
8123 if (shader->prolog2) {
8124 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8125 shader->prolog2->config.num_sgprs);
8126 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8127 shader->prolog2->config.num_vgprs);
8128 }
8129 if (shader->epilog) {
8130 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8131 shader->epilog->config.num_sgprs);
8132 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8133 shader->epilog->config.num_vgprs);
8134 }
8135 si_calculate_max_simd_waves(shader);
8136 }
8137
8138 si_fix_resource_usage(sscreen, shader);
8139 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8140 stderr, true);
8141
8142 /* Upload. */
8143 r = si_shader_binary_upload(sscreen, shader);
8144 if (r) {
8145 fprintf(stderr, "LLVM failed to upload shader\n");
8146 return r;
8147 }
8148
8149 return 0;
8150 }
8151
8152 void si_shader_destroy(struct si_shader *shader)
8153 {
8154 if (shader->scratch_bo)
8155 r600_resource_reference(&shader->scratch_bo, NULL);
8156
8157 r600_resource_reference(&shader->bo, NULL);
8158
8159 if (!shader->is_binary_shared)
8160 ac_shader_binary_clean(&shader->binary);
8161
8162 free(shader->shader_log);
8163 }