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radeonsi: don't declare LDS in TES
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109 /**
110 * Returns a unique index for a semantic name and index. The index must be
111 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
112 * calculated.
113 */
114 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
115 {
116 switch (semantic_name) {
117 case TGSI_SEMANTIC_POSITION:
118 return 0;
119 case TGSI_SEMANTIC_PSIZE:
120 return 1;
121 case TGSI_SEMANTIC_CLIPDIST:
122 assert(index <= 1);
123 return 2 + index;
124 case TGSI_SEMANTIC_GENERIC:
125 if (index <= 63-4)
126 return 4 + index;
127
128 assert(!"invalid generic index");
129 return 0;
130
131 /* patch indices are completely separate and thus start from 0 */
132 case TGSI_SEMANTIC_TESSOUTER:
133 return 0;
134 case TGSI_SEMANTIC_TESSINNER:
135 return 1;
136 case TGSI_SEMANTIC_PATCH:
137 return 2 + index;
138
139 default:
140 assert(!"invalid semantic name");
141 return 0;
142 }
143 }
144
145 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
146 {
147 switch (name) {
148 case TGSI_SEMANTIC_FOG:
149 return 0;
150 case TGSI_SEMANTIC_LAYER:
151 return 1;
152 case TGSI_SEMANTIC_VIEWPORT_INDEX:
153 return 2;
154 case TGSI_SEMANTIC_PRIMID:
155 return 3;
156 case TGSI_SEMANTIC_COLOR: /* these alias */
157 case TGSI_SEMANTIC_BCOLOR:
158 return 4 + index;
159 case TGSI_SEMANTIC_TEXCOORD:
160 return 6 + index;
161 default:
162 assert(!"invalid semantic name");
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &ctx->gallivm;
175 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
176 param);
177
178 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
179 value = bitcast(&ctx->bld_base,
180 TGSI_TYPE_UNSIGNED, value);
181
182 if (rshift)
183 value = LLVMBuildLShr(gallivm->builder, value,
184 lp_build_const_int32(gallivm, rshift), "");
185
186 if (rshift + bitwidth < 32) {
187 unsigned mask = (1 << bitwidth) - 1;
188 value = LLVMBuildAnd(gallivm->builder, value,
189 lp_build_const_int32(gallivm, mask), "");
190 }
191
192 return value;
193 }
194
195 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
196 {
197 switch (ctx->type) {
198 case PIPE_SHADER_TESS_CTRL:
199 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
200
201 case PIPE_SHADER_TESS_EVAL:
202 return LLVMGetParam(ctx->main_fn,
203 ctx->param_tes_rel_patch_id);
204
205 default:
206 assert(0);
207 return NULL;
208 }
209 }
210
211 /* Tessellation shaders pass outputs to the next shader using LDS.
212 *
213 * LS outputs = TCS inputs
214 * TCS outputs = TES inputs
215 *
216 * The LDS layout is:
217 * - TCS inputs for patch 0
218 * - TCS inputs for patch 1
219 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
220 * - ...
221 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
222 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
223 * - TCS outputs for patch 1
224 * - Per-patch TCS outputs for patch 1
225 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
226 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
227 * - ...
228 *
229 * All three shaders VS(LS), TCS, TES share the same LDS space.
230 */
231
232 static LLVMValueRef
233 get_tcs_in_patch_stride(struct si_shader_context *ctx)
234 {
235 if (ctx->type == PIPE_SHADER_VERTEX)
236 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
237 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
238 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
239 else {
240 assert(0);
241 return NULL;
242 }
243 }
244
245 static LLVMValueRef
246 get_tcs_out_patch_stride(struct si_shader_context *ctx)
247 {
248 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
249 }
250
251 static LLVMValueRef
252 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
253 {
254 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
255 unpack_param(ctx,
256 SI_PARAM_TCS_OUT_OFFSETS,
257 0, 16),
258 4);
259 }
260
261 static LLVMValueRef
262 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
263 {
264 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
265 unpack_param(ctx,
266 SI_PARAM_TCS_OUT_OFFSETS,
267 16, 16),
268 4);
269 }
270
271 static LLVMValueRef
272 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
273 {
274 struct gallivm_state *gallivm = &ctx->gallivm;
275 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
276 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
277
278 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
279 }
280
281 static LLVMValueRef
282 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
283 {
284 struct gallivm_state *gallivm = &ctx->gallivm;
285 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
286 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
287 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
288
289 return LLVMBuildAdd(gallivm->builder, patch0_offset,
290 LLVMBuildMul(gallivm->builder, patch_stride,
291 rel_patch_id, ""),
292 "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
297 {
298 struct gallivm_state *gallivm = &ctx->gallivm;
299 LLVMValueRef patch0_patch_data_offset =
300 get_tcs_out_patch0_patch_data_offset(ctx);
301 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
302 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
303
304 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
305 LLVMBuildMul(gallivm->builder, patch_stride,
306 rel_patch_id, ""),
307 "");
308 }
309
310 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
311 LLVMValueRef base_ptr, LLVMValueRef index)
312 {
313 LLVMValueRef indices[2] = {
314 LLVMConstInt(ctx->i32, 0, 0),
315 index,
316 };
317 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
318 indices, 2, "");
319 }
320
321 static void build_indexed_store(struct si_shader_context *ctx,
322 LLVMValueRef base_ptr, LLVMValueRef index,
323 LLVMValueRef value)
324 {
325 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
326 struct gallivm_state *gallivm = bld_base->base.gallivm;
327
328 LLVMBuildStore(gallivm->builder, value,
329 build_gep0(ctx, base_ptr, index));
330 }
331
332 /**
333 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
334 * It's equivalent to doing a load from &base_ptr[index].
335 *
336 * \param base_ptr Where the array starts.
337 * \param index The element index into the array.
338 * \param uniform Whether the base_ptr and index can be assumed to be
339 * dynamically uniform
340 */
341 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
342 LLVMValueRef base_ptr, LLVMValueRef index,
343 bool uniform)
344 {
345 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
346 struct gallivm_state *gallivm = bld_base->base.gallivm;
347 LLVMValueRef pointer;
348
349 pointer = build_gep0(ctx, base_ptr, index);
350 if (uniform)
351 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
352 return LLVMBuildLoad(gallivm->builder, pointer, "");
353 }
354
355 /**
356 * Do a load from &base_ptr[index], but also add a flag that it's loading
357 * a constant from a dynamically uniform index.
358 */
359 static LLVMValueRef build_indexed_load_const(
360 struct si_shader_context *ctx,
361 LLVMValueRef base_ptr, LLVMValueRef index)
362 {
363 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
364 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
365 return result;
366 }
367
368 static LLVMValueRef get_instance_index_for_fetch(
369 struct si_shader_context *radeon_bld,
370 unsigned param_start_instance, unsigned divisor)
371 {
372 struct si_shader_context *ctx =
373 si_shader_context(&radeon_bld->bld_base);
374 struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
375
376 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
377 ctx->param_instance_id);
378
379 /* The division must be done before START_INSTANCE is added. */
380 if (divisor > 1)
381 result = LLVMBuildUDiv(gallivm->builder, result,
382 lp_build_const_int32(gallivm, divisor), "");
383
384 return LLVMBuildAdd(gallivm->builder, result,
385 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
386 }
387
388 static void declare_input_vs(
389 struct si_shader_context *ctx,
390 unsigned input_index,
391 const struct tgsi_full_declaration *decl,
392 LLVMValueRef out[4])
393 {
394 struct lp_build_context *base = &ctx->bld_base.base;
395 struct gallivm_state *gallivm = base->gallivm;
396
397 unsigned chan;
398 unsigned fix_fetch;
399
400 LLVMValueRef t_list_ptr;
401 LLVMValueRef t_offset;
402 LLVMValueRef t_list;
403 LLVMValueRef attribute_offset;
404 LLVMValueRef buffer_index;
405 LLVMValueRef args[3];
406 LLVMValueRef input;
407
408 /* Load the T list */
409 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
410
411 t_offset = lp_build_const_int32(gallivm, input_index);
412
413 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
414
415 /* Build the attribute offset */
416 attribute_offset = lp_build_const_int32(gallivm, 0);
417
418 buffer_index = LLVMGetParam(ctx->main_fn,
419 ctx->param_vertex_index0 +
420 input_index);
421
422 args[0] = t_list;
423 args[1] = attribute_offset;
424 args[2] = buffer_index;
425 input = lp_build_intrinsic(gallivm->builder,
426 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
427 LP_FUNC_ATTR_READNONE);
428
429 /* Break up the vec4 into individual components */
430 for (chan = 0; chan < 4; chan++) {
431 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
432 out[chan] = LLVMBuildExtractElement(gallivm->builder,
433 input, llvm_chan, "");
434 }
435
436 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (4 * input_index)) & 0xf;
437
438 switch (fix_fetch) {
439 case SI_FIX_FETCH_A2_SNORM:
440 case SI_FIX_FETCH_A2_SSCALED:
441 case SI_FIX_FETCH_A2_SINT: {
442 /* The hardware returns an unsigned value; convert it to a
443 * signed one.
444 */
445 LLVMValueRef tmp = out[3];
446 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
447
448 /* First, recover the sign-extended signed integer value. */
449 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
450 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
451 else
452 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
453
454 /* For the integer-like cases, do a natural sign extension.
455 *
456 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
457 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
458 * exponent.
459 */
460 tmp = LLVMBuildShl(gallivm->builder, tmp,
461 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
462 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
463 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
464
465 /* Convert back to the right type. */
466 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
467 LLVMValueRef clamp;
468 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
469 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
470 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
471 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
472 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
473 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
474 }
475
476 out[3] = tmp;
477 break;
478 }
479 case SI_FIX_FETCH_RGBA_32_UNORM:
480 case SI_FIX_FETCH_RGBX_32_UNORM:
481 for (chan = 0; chan < 4; chan++) {
482 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
483 ctx->i32, "");
484 out[chan] = LLVMBuildUIToFP(gallivm->builder,
485 out[chan], ctx->f32, "");
486 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
487 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
488 }
489 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
490 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
491 out[3] = LLVMConstReal(ctx->f32, 1);
492 break;
493 case SI_FIX_FETCH_RGBA_32_SNORM:
494 case SI_FIX_FETCH_RGBX_32_SNORM:
495 case SI_FIX_FETCH_RGBA_32_FIXED:
496 case SI_FIX_FETCH_RGBX_32_FIXED: {
497 double scale;
498 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
499 scale = 1.0 / 0x10000;
500 else
501 scale = 1.0 / INT_MAX;
502
503 for (chan = 0; chan < 4; chan++) {
504 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
505 ctx->i32, "");
506 out[chan] = LLVMBuildSIToFP(gallivm->builder,
507 out[chan], ctx->f32, "");
508 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
509 LLVMConstReal(ctx->f32, scale), "");
510 }
511 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
512 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
513 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
514 out[3] = LLVMConstReal(ctx->f32, 1);
515 break;
516 }
517 case SI_FIX_FETCH_RGBA_32_USCALED:
518 for (chan = 0; chan < 4; chan++) {
519 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
520 ctx->i32, "");
521 out[chan] = LLVMBuildUIToFP(gallivm->builder,
522 out[chan], ctx->f32, "");
523 }
524 break;
525 case SI_FIX_FETCH_RGBA_32_SSCALED:
526 for (chan = 0; chan < 4; chan++) {
527 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
528 ctx->i32, "");
529 out[chan] = LLVMBuildSIToFP(gallivm->builder,
530 out[chan], ctx->f32, "");
531 }
532 break;
533 }
534 }
535
536 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
537 unsigned swizzle)
538 {
539 struct si_shader_context *ctx = si_shader_context(bld_base);
540
541 if (swizzle > 0)
542 return bld_base->uint_bld.zero;
543
544 switch (ctx->type) {
545 case PIPE_SHADER_VERTEX:
546 return LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_prim_id);
548 case PIPE_SHADER_TESS_CTRL:
549 return LLVMGetParam(ctx->main_fn,
550 SI_PARAM_PATCH_ID);
551 case PIPE_SHADER_TESS_EVAL:
552 return LLVMGetParam(ctx->main_fn,
553 ctx->param_tes_patch_id);
554 case PIPE_SHADER_GEOMETRY:
555 return LLVMGetParam(ctx->main_fn,
556 SI_PARAM_PRIMITIVE_ID);
557 default:
558 assert(0);
559 return bld_base->uint_bld.zero;
560 }
561 }
562
563 /**
564 * Return the value of tgsi_ind_register for indexing.
565 * This is the indirect index with the constant offset added to it.
566 */
567 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
568 const struct tgsi_ind_register *ind,
569 int rel_index)
570 {
571 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
572 LLVMValueRef result;
573
574 result = ctx->addrs[ind->Index][ind->Swizzle];
575 result = LLVMBuildLoad(gallivm->builder, result, "");
576 result = LLVMBuildAdd(gallivm->builder, result,
577 lp_build_const_int32(gallivm, rel_index), "");
578 return result;
579 }
580
581 /**
582 * Like get_indirect_index, but restricts the return value to a (possibly
583 * undefined) value inside [0..num).
584 */
585 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
586 const struct tgsi_ind_register *ind,
587 int rel_index, unsigned num)
588 {
589 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
590
591 /* LLVM 3.8: If indirect resource indexing is used:
592 * - SI & CIK hang
593 * - VI crashes
594 */
595 if (HAVE_LLVM <= 0x0308)
596 return LLVMGetUndef(ctx->i32);
597
598 return si_llvm_bound_index(ctx, result, num);
599 }
600
601
602 /**
603 * Calculate a dword address given an input or output register and a stride.
604 */
605 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
606 const struct tgsi_full_dst_register *dst,
607 const struct tgsi_full_src_register *src,
608 LLVMValueRef vertex_dw_stride,
609 LLVMValueRef base_addr)
610 {
611 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
612 struct tgsi_shader_info *info = &ctx->shader->selector->info;
613 ubyte *name, *index, *array_first;
614 int first, param;
615 struct tgsi_full_dst_register reg;
616
617 /* Set the register description. The address computation is the same
618 * for sources and destinations. */
619 if (src) {
620 reg.Register.File = src->Register.File;
621 reg.Register.Index = src->Register.Index;
622 reg.Register.Indirect = src->Register.Indirect;
623 reg.Register.Dimension = src->Register.Dimension;
624 reg.Indirect = src->Indirect;
625 reg.Dimension = src->Dimension;
626 reg.DimIndirect = src->DimIndirect;
627 } else
628 reg = *dst;
629
630 /* If the register is 2-dimensional (e.g. an array of vertices
631 * in a primitive), calculate the base address of the vertex. */
632 if (reg.Register.Dimension) {
633 LLVMValueRef index;
634
635 if (reg.Dimension.Indirect)
636 index = get_indirect_index(ctx, &reg.DimIndirect,
637 reg.Dimension.Index);
638 else
639 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
640
641 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
642 LLVMBuildMul(gallivm->builder, index,
643 vertex_dw_stride, ""), "");
644 }
645
646 /* Get information about the register. */
647 if (reg.Register.File == TGSI_FILE_INPUT) {
648 name = info->input_semantic_name;
649 index = info->input_semantic_index;
650 array_first = info->input_array_first;
651 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
652 name = info->output_semantic_name;
653 index = info->output_semantic_index;
654 array_first = info->output_array_first;
655 } else {
656 assert(0);
657 return NULL;
658 }
659
660 if (reg.Register.Indirect) {
661 /* Add the relative address of the element. */
662 LLVMValueRef ind_index;
663
664 if (reg.Indirect.ArrayID)
665 first = array_first[reg.Indirect.ArrayID];
666 else
667 first = reg.Register.Index;
668
669 ind_index = get_indirect_index(ctx, &reg.Indirect,
670 reg.Register.Index - first);
671
672 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
673 LLVMBuildMul(gallivm->builder, ind_index,
674 lp_build_const_int32(gallivm, 4), ""), "");
675
676 param = si_shader_io_get_unique_index(name[first], index[first]);
677 } else {
678 param = si_shader_io_get_unique_index(name[reg.Register.Index],
679 index[reg.Register.Index]);
680 }
681
682 /* Add the base address of the element. */
683 return LLVMBuildAdd(gallivm->builder, base_addr,
684 lp_build_const_int32(gallivm, param * 4), "");
685 }
686
687 /* The offchip buffer layout for TCS->TES is
688 *
689 * - attribute 0 of patch 0 vertex 0
690 * - attribute 0 of patch 0 vertex 1
691 * - attribute 0 of patch 0 vertex 2
692 * ...
693 * - attribute 0 of patch 1 vertex 0
694 * - attribute 0 of patch 1 vertex 1
695 * ...
696 * - attribute 1 of patch 0 vertex 0
697 * - attribute 1 of patch 0 vertex 1
698 * ...
699 * - per patch attribute 0 of patch 0
700 * - per patch attribute 0 of patch 1
701 * ...
702 *
703 * Note that every attribute has 4 components.
704 */
705 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
706 LLVMValueRef vertex_index,
707 LLVMValueRef param_index)
708 {
709 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
710 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
711 LLVMValueRef param_stride, constant16;
712
713 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
714 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
715 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
716 num_patches, "");
717
718 constant16 = lp_build_const_int32(gallivm, 16);
719 if (vertex_index) {
720 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
721 vertices_per_patch, "");
722
723 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
724 vertex_index, "");
725
726 param_stride = total_vertices;
727 } else {
728 base_addr = get_rel_patch_id(ctx);
729 param_stride = num_patches;
730 }
731
732 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
733 LLVMBuildMul(gallivm->builder, param_index,
734 param_stride, ""), "");
735
736 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
737
738 if (!vertex_index) {
739 LLVMValueRef patch_data_offset =
740 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
741
742 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
743 patch_data_offset, "");
744 }
745 return base_addr;
746 }
747
748 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
749 struct si_shader_context *ctx,
750 const struct tgsi_full_dst_register *dst,
751 const struct tgsi_full_src_register *src)
752 {
753 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
754 struct tgsi_shader_info *info = &ctx->shader->selector->info;
755 ubyte *name, *index, *array_first;
756 struct tgsi_full_src_register reg;
757 LLVMValueRef vertex_index = NULL;
758 LLVMValueRef param_index = NULL;
759 unsigned param_index_base, param_base;
760
761 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
762
763 if (reg.Register.Dimension) {
764
765 if (reg.Dimension.Indirect)
766 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
767 reg.Dimension.Index);
768 else
769 vertex_index = lp_build_const_int32(gallivm,
770 reg.Dimension.Index);
771 }
772
773 /* Get information about the register. */
774 if (reg.Register.File == TGSI_FILE_INPUT) {
775 name = info->input_semantic_name;
776 index = info->input_semantic_index;
777 array_first = info->input_array_first;
778 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
779 name = info->output_semantic_name;
780 index = info->output_semantic_index;
781 array_first = info->output_array_first;
782 } else {
783 assert(0);
784 return NULL;
785 }
786
787 if (reg.Register.Indirect) {
788 if (reg.Indirect.ArrayID)
789 param_base = array_first[reg.Indirect.ArrayID];
790 else
791 param_base = reg.Register.Index;
792
793 param_index = get_indirect_index(ctx, &reg.Indirect,
794 reg.Register.Index - param_base);
795
796 } else {
797 param_base = reg.Register.Index;
798 param_index = lp_build_const_int32(gallivm, 0);
799 }
800
801 param_index_base = si_shader_io_get_unique_index(name[param_base],
802 index[param_base]);
803
804 param_index = LLVMBuildAdd(gallivm->builder, param_index,
805 lp_build_const_int32(gallivm, param_index_base),
806 "");
807
808 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
809 }
810
811 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
812 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
813 * or v4i32 (num_channels=3,4). */
814 static void build_tbuffer_store(struct si_shader_context *ctx,
815 LLVMValueRef rsrc,
816 LLVMValueRef vdata,
817 unsigned num_channels,
818 LLVMValueRef vaddr,
819 LLVMValueRef soffset,
820 unsigned inst_offset,
821 unsigned dfmt,
822 unsigned nfmt,
823 unsigned offen,
824 unsigned idxen,
825 unsigned glc,
826 unsigned slc,
827 unsigned tfe)
828 {
829 struct gallivm_state *gallivm = &ctx->gallivm;
830 LLVMValueRef args[] = {
831 rsrc,
832 vdata,
833 LLVMConstInt(ctx->i32, num_channels, 0),
834 vaddr,
835 soffset,
836 LLVMConstInt(ctx->i32, inst_offset, 0),
837 LLVMConstInt(ctx->i32, dfmt, 0),
838 LLVMConstInt(ctx->i32, nfmt, 0),
839 LLVMConstInt(ctx->i32, offen, 0),
840 LLVMConstInt(ctx->i32, idxen, 0),
841 LLVMConstInt(ctx->i32, glc, 0),
842 LLVMConstInt(ctx->i32, slc, 0),
843 LLVMConstInt(ctx->i32, tfe, 0)
844 };
845
846 /* The instruction offset field has 12 bits */
847 assert(offen || inst_offset < (1 << 12));
848
849 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
850 unsigned func = CLAMP(num_channels, 1, 3) - 1;
851 const char *types[] = {"i32", "v2i32", "v4i32"};
852 char name[256];
853 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
854
855 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
856 args, ARRAY_SIZE(args), 0);
857 }
858
859 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
860 LLVMValueRef rsrc,
861 LLVMValueRef vdata,
862 unsigned num_channels,
863 LLVMValueRef vaddr,
864 LLVMValueRef soffset,
865 unsigned inst_offset)
866 {
867 static unsigned dfmt[] = {
868 V_008F0C_BUF_DATA_FORMAT_32,
869 V_008F0C_BUF_DATA_FORMAT_32_32,
870 V_008F0C_BUF_DATA_FORMAT_32_32_32,
871 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
872 };
873 assert(num_channels >= 1 && num_channels <= 4);
874
875 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
876 inst_offset, dfmt[num_channels-1],
877 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
878 }
879
880 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
881 LLVMValueRef rsrc,
882 int num_channels,
883 LLVMValueRef vindex,
884 LLVMValueRef voffset,
885 LLVMValueRef soffset,
886 unsigned inst_offset,
887 unsigned glc,
888 unsigned slc)
889 {
890 struct gallivm_state *gallivm = &ctx->gallivm;
891 unsigned func = CLAMP(num_channels, 1, 3) - 1;
892
893 if (HAVE_LLVM >= 0x309) {
894 LLVMValueRef args[] = {
895 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
896 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
897 LLVMConstInt(ctx->i32, inst_offset, 0),
898 LLVMConstInt(ctx->i1, glc, 0),
899 LLVMConstInt(ctx->i1, slc, 0)
900 };
901
902 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
903 ctx->v4f32};
904 const char *type_names[] = {"f32", "v2f32", "v4f32"};
905 char name[256];
906
907 if (voffset) {
908 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
909 "");
910 }
911
912 if (soffset) {
913 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
914 "");
915 }
916
917 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
918 type_names[func]);
919
920 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
921 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
922 } else {
923 LLVMValueRef args[] = {
924 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
925 voffset ? voffset : vindex,
926 soffset,
927 LLVMConstInt(ctx->i32, inst_offset, 0),
928 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
929 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
930 LLVMConstInt(ctx->i32, glc, 0),
931 LLVMConstInt(ctx->i32, slc, 0),
932 LLVMConstInt(ctx->i32, 0, 0), // TFE
933 };
934
935 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
936 ctx->v4i32};
937 const char *type_names[] = {"i32", "v2i32", "v4i32"};
938 const char *arg_type = "i32";
939 char name[256];
940
941 if (voffset && vindex) {
942 LLVMValueRef vaddr[] = {vindex, voffset};
943
944 arg_type = "v2i32";
945 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
946 }
947
948 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
949 type_names[func], arg_type);
950
951 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
952 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
953 }
954 }
955
956 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
957 enum tgsi_opcode_type type, unsigned swizzle,
958 LLVMValueRef buffer, LLVMValueRef offset,
959 LLVMValueRef base)
960 {
961 struct si_shader_context *ctx = si_shader_context(bld_base);
962 struct gallivm_state *gallivm = bld_base->base.gallivm;
963 LLVMValueRef value, value2;
964 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
965 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
966
967 if (swizzle == ~0) {
968 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
969 0, 1, 0);
970
971 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
972 }
973
974 if (!tgsi_type_is_64bit(type)) {
975 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
976 0, 1, 0);
977
978 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
979 return LLVMBuildExtractElement(gallivm->builder, value,
980 lp_build_const_int32(gallivm, swizzle), "");
981 }
982
983 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
984 swizzle * 4, 1, 0);
985
986 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
987 swizzle * 4 + 4, 1, 0);
988
989 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
990 }
991
992 /**
993 * Load from LDS.
994 *
995 * \param type output value type
996 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
997 * \param dw_addr address in dwords
998 */
999 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1000 enum tgsi_opcode_type type, unsigned swizzle,
1001 LLVMValueRef dw_addr)
1002 {
1003 struct si_shader_context *ctx = si_shader_context(bld_base);
1004 struct gallivm_state *gallivm = bld_base->base.gallivm;
1005 LLVMValueRef value;
1006
1007 if (swizzle == ~0) {
1008 LLVMValueRef values[TGSI_NUM_CHANNELS];
1009
1010 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1011 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1012
1013 return lp_build_gather_values(bld_base->base.gallivm, values,
1014 TGSI_NUM_CHANNELS);
1015 }
1016
1017 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1018 lp_build_const_int32(gallivm, swizzle));
1019
1020 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1021 if (tgsi_type_is_64bit(type)) {
1022 LLVMValueRef value2;
1023 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1024 lp_build_const_int32(gallivm, 1));
1025 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1026 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1027 }
1028
1029 return LLVMBuildBitCast(gallivm->builder, value,
1030 tgsi2llvmtype(bld_base, type), "");
1031 }
1032
1033 /**
1034 * Store to LDS.
1035 *
1036 * \param swizzle offset (typically 0..3)
1037 * \param dw_addr address in dwords
1038 * \param value value to store
1039 */
1040 static void lds_store(struct lp_build_tgsi_context *bld_base,
1041 unsigned swizzle, LLVMValueRef dw_addr,
1042 LLVMValueRef value)
1043 {
1044 struct si_shader_context *ctx = si_shader_context(bld_base);
1045 struct gallivm_state *gallivm = bld_base->base.gallivm;
1046
1047 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1048 lp_build_const_int32(gallivm, swizzle));
1049
1050 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1051 build_indexed_store(ctx, ctx->lds,
1052 dw_addr, value);
1053 }
1054
1055 static LLVMValueRef fetch_input_tcs(
1056 struct lp_build_tgsi_context *bld_base,
1057 const struct tgsi_full_src_register *reg,
1058 enum tgsi_opcode_type type, unsigned swizzle)
1059 {
1060 struct si_shader_context *ctx = si_shader_context(bld_base);
1061 LLVMValueRef dw_addr, stride;
1062
1063 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1064 dw_addr = get_tcs_in_current_patch_offset(ctx);
1065 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1066
1067 return lds_load(bld_base, type, swizzle, dw_addr);
1068 }
1069
1070 static LLVMValueRef fetch_output_tcs(
1071 struct lp_build_tgsi_context *bld_base,
1072 const struct tgsi_full_src_register *reg,
1073 enum tgsi_opcode_type type, unsigned swizzle)
1074 {
1075 struct si_shader_context *ctx = si_shader_context(bld_base);
1076 LLVMValueRef dw_addr, stride;
1077
1078 if (reg->Register.Dimension) {
1079 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1080 dw_addr = get_tcs_out_current_patch_offset(ctx);
1081 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1082 } else {
1083 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1084 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1085 }
1086
1087 return lds_load(bld_base, type, swizzle, dw_addr);
1088 }
1089
1090 static LLVMValueRef fetch_input_tes(
1091 struct lp_build_tgsi_context *bld_base,
1092 const struct tgsi_full_src_register *reg,
1093 enum tgsi_opcode_type type, unsigned swizzle)
1094 {
1095 struct si_shader_context *ctx = si_shader_context(bld_base);
1096 struct gallivm_state *gallivm = bld_base->base.gallivm;
1097 LLVMValueRef rw_buffers, buffer, base, addr;
1098
1099 rw_buffers = LLVMGetParam(ctx->main_fn,
1100 SI_PARAM_RW_BUFFERS);
1101 buffer = build_indexed_load_const(ctx, rw_buffers,
1102 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1103
1104 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1105 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1106
1107 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1108 }
1109
1110 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1111 const struct tgsi_full_instruction *inst,
1112 const struct tgsi_opcode_info *info,
1113 LLVMValueRef dst[4])
1114 {
1115 struct si_shader_context *ctx = si_shader_context(bld_base);
1116 struct gallivm_state *gallivm = bld_base->base.gallivm;
1117 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1118 unsigned chan_index;
1119 LLVMValueRef dw_addr, stride;
1120 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1121 LLVMValueRef values[4];
1122
1123 /* Only handle per-patch and per-vertex outputs here.
1124 * Vectors will be lowered to scalars and this function will be called again.
1125 */
1126 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1127 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1128 si_llvm_emit_store(bld_base, inst, info, dst);
1129 return;
1130 }
1131
1132 if (reg->Register.Dimension) {
1133 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1134 dw_addr = get_tcs_out_current_patch_offset(ctx);
1135 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1136 } else {
1137 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1138 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1139 }
1140
1141 rw_buffers = LLVMGetParam(ctx->main_fn,
1142 SI_PARAM_RW_BUFFERS);
1143 buffer = build_indexed_load_const(ctx, rw_buffers,
1144 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1145
1146 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1147 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1148
1149
1150 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1151 LLVMValueRef value = dst[chan_index];
1152
1153 if (inst->Instruction.Saturate)
1154 value = si_llvm_saturate(bld_base, value);
1155
1156 lds_store(bld_base, chan_index, dw_addr, value);
1157
1158 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1159 values[chan_index] = value;
1160
1161 if (inst->Dst[0].Register.WriteMask != 0xF) {
1162 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1163 buf_addr, base,
1164 4 * chan_index);
1165 }
1166 }
1167
1168 if (inst->Dst[0].Register.WriteMask == 0xF) {
1169 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1170 values, 4);
1171 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1172 base, 0);
1173 }
1174 }
1175
1176 static LLVMValueRef fetch_input_gs(
1177 struct lp_build_tgsi_context *bld_base,
1178 const struct tgsi_full_src_register *reg,
1179 enum tgsi_opcode_type type,
1180 unsigned swizzle)
1181 {
1182 struct lp_build_context *base = &bld_base->base;
1183 struct si_shader_context *ctx = si_shader_context(bld_base);
1184 struct si_shader *shader = ctx->shader;
1185 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1186 struct gallivm_state *gallivm = base->gallivm;
1187 LLVMValueRef vtx_offset;
1188 LLVMValueRef args[9];
1189 unsigned vtx_offset_param;
1190 struct tgsi_shader_info *info = &shader->selector->info;
1191 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1192 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1193 unsigned param;
1194 LLVMValueRef value;
1195
1196 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1197 return get_primitive_id(bld_base, swizzle);
1198
1199 if (!reg->Register.Dimension)
1200 return NULL;
1201
1202 if (swizzle == ~0) {
1203 LLVMValueRef values[TGSI_NUM_CHANNELS];
1204 unsigned chan;
1205 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1206 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1207 }
1208 return lp_build_gather_values(bld_base->base.gallivm, values,
1209 TGSI_NUM_CHANNELS);
1210 }
1211
1212 /* Get the vertex offset parameter */
1213 vtx_offset_param = reg->Dimension.Index;
1214 if (vtx_offset_param < 2) {
1215 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1216 } else {
1217 assert(vtx_offset_param < 6);
1218 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1219 }
1220 vtx_offset = lp_build_mul_imm(uint,
1221 LLVMGetParam(ctx->main_fn,
1222 vtx_offset_param),
1223 4);
1224
1225 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1226 args[0] = ctx->esgs_ring;
1227 args[1] = vtx_offset;
1228 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1229 args[3] = uint->zero;
1230 args[4] = uint->one; /* OFFEN */
1231 args[5] = uint->zero; /* IDXEN */
1232 args[6] = uint->one; /* GLC */
1233 args[7] = uint->zero; /* SLC */
1234 args[8] = uint->zero; /* TFE */
1235
1236 value = lp_build_intrinsic(gallivm->builder,
1237 "llvm.SI.buffer.load.dword.i32.i32",
1238 ctx->i32, args, 9,
1239 LP_FUNC_ATTR_READONLY);
1240 if (tgsi_type_is_64bit(type)) {
1241 LLVMValueRef value2;
1242 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1243 value2 = lp_build_intrinsic(gallivm->builder,
1244 "llvm.SI.buffer.load.dword.i32.i32",
1245 ctx->i32, args, 9,
1246 LP_FUNC_ATTR_READONLY);
1247 return si_llvm_emit_fetch_64bit(bld_base, type,
1248 value, value2);
1249 }
1250 return LLVMBuildBitCast(gallivm->builder,
1251 value,
1252 tgsi2llvmtype(bld_base, type), "");
1253 }
1254
1255 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1256 {
1257 switch (interpolate) {
1258 case TGSI_INTERPOLATE_CONSTANT:
1259 return 0;
1260
1261 case TGSI_INTERPOLATE_LINEAR:
1262 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1263 return SI_PARAM_LINEAR_SAMPLE;
1264 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1265 return SI_PARAM_LINEAR_CENTROID;
1266 else
1267 return SI_PARAM_LINEAR_CENTER;
1268 break;
1269 case TGSI_INTERPOLATE_COLOR:
1270 case TGSI_INTERPOLATE_PERSPECTIVE:
1271 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1272 return SI_PARAM_PERSP_SAMPLE;
1273 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1274 return SI_PARAM_PERSP_CENTROID;
1275 else
1276 return SI_PARAM_PERSP_CENTER;
1277 break;
1278 default:
1279 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1280 return -1;
1281 }
1282 }
1283
1284 static LLVMValueRef build_fs_interp(
1285 struct lp_build_tgsi_context *bld_base,
1286 LLVMValueRef llvm_chan,
1287 LLVMValueRef attr_number,
1288 LLVMValueRef params,
1289 LLVMValueRef i,
1290 LLVMValueRef j) {
1291
1292 struct si_shader_context *ctx = si_shader_context(bld_base);
1293 struct gallivm_state *gallivm = bld_base->base.gallivm;
1294 LLVMValueRef args[5];
1295 LLVMValueRef p1;
1296 if (HAVE_LLVM < 0x0400) {
1297 LLVMValueRef ij[2];
1298 ij[0] = LLVMBuildBitCast(gallivm->builder, i, ctx->i32, "");
1299 ij[1] = LLVMBuildBitCast(gallivm->builder, j, ctx->i32, "");
1300
1301 args[0] = llvm_chan;
1302 args[1] = attr_number;
1303 args[2] = params;
1304 args[3] = lp_build_gather_values(gallivm, ij, 2);
1305 return lp_build_intrinsic(gallivm->builder, "llvm.SI.fs.interp",
1306 ctx->f32, args, 4,
1307 LP_FUNC_ATTR_READNONE);
1308 }
1309
1310 args[0] = i;
1311 args[1] = llvm_chan;
1312 args[2] = attr_number;
1313 args[3] = params;
1314
1315 p1 = lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p1",
1316 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1317
1318 args[0] = p1;
1319 args[1] = j;
1320 args[2] = llvm_chan;
1321 args[3] = attr_number;
1322 args[4] = params;
1323
1324 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.p2",
1325 ctx->f32, args, 5, LP_FUNC_ATTR_READNONE);
1326 }
1327
1328 static LLVMValueRef build_fs_interp_mov(
1329 struct lp_build_tgsi_context *bld_base,
1330 LLVMValueRef parameter,
1331 LLVMValueRef llvm_chan,
1332 LLVMValueRef attr_number,
1333 LLVMValueRef params) {
1334
1335 struct si_shader_context *ctx = si_shader_context(bld_base);
1336 struct gallivm_state *gallivm = bld_base->base.gallivm;
1337 LLVMValueRef args[4];
1338 if (HAVE_LLVM < 0x0400) {
1339 args[0] = llvm_chan;
1340 args[1] = attr_number;
1341 args[2] = params;
1342
1343 return lp_build_intrinsic(gallivm->builder,
1344 "llvm.SI.fs.constant",
1345 ctx->f32, args, 3,
1346 LP_FUNC_ATTR_READNONE);
1347 }
1348
1349 args[0] = parameter;
1350 args[1] = llvm_chan;
1351 args[2] = attr_number;
1352 args[3] = params;
1353
1354 return lp_build_intrinsic(gallivm->builder, "llvm.amdgcn.interp.mov",
1355 ctx->f32, args, 4, LP_FUNC_ATTR_READNONE);
1356 }
1357
1358 /**
1359 * Interpolate a fragment shader input.
1360 *
1361 * @param ctx context
1362 * @param input_index index of the input in hardware
1363 * @param semantic_name TGSI_SEMANTIC_*
1364 * @param semantic_index semantic index
1365 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1366 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1367 * @param interp_param interpolation weights (i,j)
1368 * @param prim_mask SI_PARAM_PRIM_MASK
1369 * @param face SI_PARAM_FRONT_FACE
1370 * @param result the return value (4 components)
1371 */
1372 static void interp_fs_input(struct si_shader_context *ctx,
1373 unsigned input_index,
1374 unsigned semantic_name,
1375 unsigned semantic_index,
1376 unsigned num_interp_inputs,
1377 unsigned colors_read_mask,
1378 LLVMValueRef interp_param,
1379 LLVMValueRef prim_mask,
1380 LLVMValueRef face,
1381 LLVMValueRef result[4])
1382 {
1383 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1384 struct lp_build_context *base = &bld_base->base;
1385 struct lp_build_context *uint = &bld_base->uint_bld;
1386 struct gallivm_state *gallivm = base->gallivm;
1387 LLVMValueRef attr_number;
1388 LLVMValueRef i, j;
1389
1390 unsigned chan;
1391
1392 /* fs.constant returns the param from the middle vertex, so it's not
1393 * really useful for flat shading. It's meant to be used for custom
1394 * interpolation (but the intrinsic can't fetch from the other two
1395 * vertices).
1396 *
1397 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1398 * to do the right thing. The only reason we use fs.constant is that
1399 * fs.interp cannot be used on integers, because they can be equal
1400 * to NaN.
1401 *
1402 * When interp is false we will use fs.constant or for newer llvm,
1403 * amdgcn.interp.mov.
1404 */
1405 bool interp = interp_param != NULL;
1406
1407 attr_number = lp_build_const_int32(gallivm, input_index);
1408
1409 if (interp) {
1410 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1411 LLVMVectorType(ctx->f32, 2), "");
1412
1413 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1414 uint->zero, "");
1415 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1416 uint->one, "");
1417 }
1418
1419 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1420 ctx->shader->key.part.ps.prolog.color_two_side) {
1421 LLVMValueRef is_face_positive;
1422 LLVMValueRef back_attr_number;
1423
1424 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1425 * otherwise it's at offset "num_inputs".
1426 */
1427 unsigned back_attr_offset = num_interp_inputs;
1428 if (semantic_index == 1 && colors_read_mask & 0xf)
1429 back_attr_offset += 1;
1430
1431 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1432
1433 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1434 face, uint->zero, "");
1435
1436 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1437 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1438 LLVMValueRef front, back;
1439
1440 if (interp) {
1441 front = build_fs_interp(bld_base, llvm_chan,
1442 attr_number, prim_mask,
1443 i, j);
1444 back = build_fs_interp(bld_base, llvm_chan,
1445 back_attr_number, prim_mask,
1446 i, j);
1447 } else {
1448 front = build_fs_interp_mov(bld_base,
1449 lp_build_const_int32(gallivm, 2), /* P0 */
1450 llvm_chan, attr_number, prim_mask);
1451 back = build_fs_interp_mov(bld_base,
1452 lp_build_const_int32(gallivm, 2), /* P0 */
1453 llvm_chan, back_attr_number, prim_mask);
1454 }
1455
1456 result[chan] = LLVMBuildSelect(gallivm->builder,
1457 is_face_positive,
1458 front,
1459 back,
1460 "");
1461 }
1462 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1463 if (interp) {
1464 result[0] = build_fs_interp(bld_base, uint->zero,
1465 attr_number, prim_mask, i, j);
1466 } else {
1467 result[0] = build_fs_interp_mov(bld_base, uint->zero,
1468 lp_build_const_int32(gallivm, 2), /* P0 */
1469 attr_number, prim_mask);
1470 }
1471 result[1] =
1472 result[2] = lp_build_const_float(gallivm, 0.0f);
1473 result[3] = lp_build_const_float(gallivm, 1.0f);
1474 } else {
1475 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1476 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1477
1478 if (interp) {
1479 result[chan] = build_fs_interp(bld_base,
1480 llvm_chan, attr_number, prim_mask, i, j);
1481 } else {
1482 result[chan] = build_fs_interp_mov(bld_base,
1483 lp_build_const_int32(gallivm, 2), /* P0 */
1484 llvm_chan, attr_number, prim_mask);
1485 }
1486 }
1487 }
1488 }
1489
1490 static void declare_input_fs(
1491 struct si_shader_context *radeon_bld,
1492 unsigned input_index,
1493 const struct tgsi_full_declaration *decl,
1494 LLVMValueRef out[4])
1495 {
1496 struct lp_build_context *base = &radeon_bld->bld_base.base;
1497 struct si_shader_context *ctx =
1498 si_shader_context(&radeon_bld->bld_base);
1499 struct si_shader *shader = ctx->shader;
1500 LLVMValueRef main_fn = radeon_bld->main_fn;
1501 LLVMValueRef interp_param = NULL;
1502 int interp_param_idx;
1503
1504 /* Get colors from input VGPRs (set by the prolog). */
1505 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1506 unsigned i = decl->Semantic.Index;
1507 unsigned colors_read = shader->selector->info.colors_read;
1508 unsigned mask = colors_read >> (i * 4);
1509 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1510 (i ? util_bitcount(colors_read & 0xf) : 0);
1511
1512 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1513 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1514 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1515 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1516 return;
1517 }
1518
1519 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1520 decl->Interp.Location);
1521 if (interp_param_idx == -1)
1522 return;
1523 else if (interp_param_idx) {
1524 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1525 }
1526
1527 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1528 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1529 ctx->shader->key.part.ps.prolog.flatshade_colors)
1530 interp_param = NULL; /* load the constant color */
1531
1532 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1533 decl->Semantic.Index, shader->selector->info.num_inputs,
1534 shader->selector->info.colors_read, interp_param,
1535 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1536 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1537 &out[0]);
1538 }
1539
1540 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1541 {
1542 return unpack_param(si_shader_context(&radeon_bld->bld_base),
1543 SI_PARAM_ANCILLARY, 8, 4);
1544 }
1545
1546 /**
1547 * Set range metadata on an instruction. This can only be used on load and
1548 * call instructions. If you know an instruction can only produce the values
1549 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1550 * \p lo is the minimum value inclusive.
1551 * \p hi is the maximum value exclusive.
1552 */
1553 static void set_range_metadata(struct si_shader_context *ctx,
1554 LLVMValueRef value, unsigned lo, unsigned hi)
1555 {
1556 LLVMValueRef range_md, md_args[2];
1557 LLVMTypeRef type = LLVMTypeOf(value);
1558 LLVMContextRef context = LLVMGetTypeContext(type);
1559
1560 md_args[0] = LLVMConstInt(type, lo, false);
1561 md_args[1] = LLVMConstInt(type, hi, false);
1562 range_md = LLVMMDNodeInContext(context, md_args, 2);
1563 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1564 }
1565
1566 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1567 {
1568 struct gallivm_state *gallivm = &ctx->gallivm;
1569 LLVMValueRef tid;
1570
1571 if (HAVE_LLVM < 0x0308) {
1572 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1573 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1574 } else {
1575 LLVMValueRef tid_args[2];
1576 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1577 tid_args[1] = lp_build_const_int32(gallivm, 0);
1578 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1579 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1580 tid_args, 2, LP_FUNC_ATTR_READNONE);
1581
1582 tid = lp_build_intrinsic(gallivm->builder,
1583 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1584 tid_args, 2, LP_FUNC_ATTR_READNONE);
1585 }
1586 set_range_metadata(ctx, tid, 0, 64);
1587 return tid;
1588 }
1589
1590 /**
1591 * Load a dword from a constant buffer.
1592 */
1593 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1594 LLVMValueRef resource,
1595 LLVMValueRef offset)
1596 {
1597 LLVMBuilderRef builder = ctx->gallivm.builder;
1598 LLVMValueRef args[2] = {resource, offset};
1599
1600 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1601 LP_FUNC_ATTR_READNONE);
1602 }
1603
1604 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1605 {
1606 struct si_shader_context *ctx =
1607 si_shader_context(&radeon_bld->bld_base);
1608 struct lp_build_context *uint_bld = &radeon_bld->bld_base.uint_bld;
1609 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1610 LLVMBuilderRef builder = gallivm->builder;
1611 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1612 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1613 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1614
1615 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1616 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1617 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1618
1619 LLVMValueRef pos[4] = {
1620 buffer_load_const(ctx, resource, offset0),
1621 buffer_load_const(ctx, resource, offset1),
1622 lp_build_const_float(gallivm, 0),
1623 lp_build_const_float(gallivm, 0)
1624 };
1625
1626 return lp_build_gather_values(gallivm, pos, 4);
1627 }
1628
1629 static void declare_system_value(
1630 struct si_shader_context *radeon_bld,
1631 unsigned index,
1632 const struct tgsi_full_declaration *decl)
1633 {
1634 struct si_shader_context *ctx =
1635 si_shader_context(&radeon_bld->bld_base);
1636 struct lp_build_context *bld = &radeon_bld->bld_base.base;
1637 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1638 LLVMValueRef value = 0;
1639
1640 switch (decl->Semantic.Name) {
1641 case TGSI_SEMANTIC_INSTANCEID:
1642 value = LLVMGetParam(radeon_bld->main_fn,
1643 ctx->param_instance_id);
1644 break;
1645
1646 case TGSI_SEMANTIC_VERTEXID:
1647 value = LLVMBuildAdd(gallivm->builder,
1648 LLVMGetParam(radeon_bld->main_fn,
1649 ctx->param_vertex_id),
1650 LLVMGetParam(radeon_bld->main_fn,
1651 SI_PARAM_BASE_VERTEX), "");
1652 break;
1653
1654 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1655 value = LLVMGetParam(radeon_bld->main_fn,
1656 ctx->param_vertex_id);
1657 break;
1658
1659 case TGSI_SEMANTIC_BASEVERTEX:
1660 value = LLVMGetParam(radeon_bld->main_fn,
1661 SI_PARAM_BASE_VERTEX);
1662 break;
1663
1664 case TGSI_SEMANTIC_BASEINSTANCE:
1665 value = LLVMGetParam(radeon_bld->main_fn,
1666 SI_PARAM_START_INSTANCE);
1667 break;
1668
1669 case TGSI_SEMANTIC_DRAWID:
1670 value = LLVMGetParam(radeon_bld->main_fn,
1671 SI_PARAM_DRAWID);
1672 break;
1673
1674 case TGSI_SEMANTIC_INVOCATIONID:
1675 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1676 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1677 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1678 value = LLVMGetParam(radeon_bld->main_fn,
1679 SI_PARAM_GS_INSTANCE_ID);
1680 else
1681 assert(!"INVOCATIONID not implemented");
1682 break;
1683
1684 case TGSI_SEMANTIC_POSITION:
1685 {
1686 LLVMValueRef pos[4] = {
1687 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1688 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1689 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1690 lp_build_emit_llvm_unary(&radeon_bld->bld_base, TGSI_OPCODE_RCP,
1691 LLVMGetParam(radeon_bld->main_fn,
1692 SI_PARAM_POS_W_FLOAT)),
1693 };
1694 value = lp_build_gather_values(gallivm, pos, 4);
1695 break;
1696 }
1697
1698 case TGSI_SEMANTIC_FACE:
1699 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1700 break;
1701
1702 case TGSI_SEMANTIC_SAMPLEID:
1703 value = get_sample_id(radeon_bld);
1704 break;
1705
1706 case TGSI_SEMANTIC_SAMPLEPOS: {
1707 LLVMValueRef pos[4] = {
1708 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1709 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1710 lp_build_const_float(gallivm, 0),
1711 lp_build_const_float(gallivm, 0)
1712 };
1713 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1714 TGSI_OPCODE_FRC, pos[0]);
1715 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1716 TGSI_OPCODE_FRC, pos[1]);
1717 value = lp_build_gather_values(gallivm, pos, 4);
1718 break;
1719 }
1720
1721 case TGSI_SEMANTIC_SAMPLEMASK:
1722 /* This can only occur with the OpenGL Core profile, which
1723 * doesn't support smoothing.
1724 */
1725 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1726 break;
1727
1728 case TGSI_SEMANTIC_TESSCOORD:
1729 {
1730 LLVMValueRef coord[4] = {
1731 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1732 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1733 bld->zero,
1734 bld->zero
1735 };
1736
1737 /* For triangles, the vector should be (u, v, 1-u-v). */
1738 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1739 PIPE_PRIM_TRIANGLES)
1740 coord[2] = lp_build_sub(bld, bld->one,
1741 lp_build_add(bld, coord[0], coord[1]));
1742
1743 value = lp_build_gather_values(gallivm, coord, 4);
1744 break;
1745 }
1746
1747 case TGSI_SEMANTIC_VERTICESIN:
1748 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1749 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1750 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1751 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1752 else
1753 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1754 break;
1755
1756 case TGSI_SEMANTIC_TESSINNER:
1757 case TGSI_SEMANTIC_TESSOUTER:
1758 {
1759 LLVMValueRef rw_buffers, buffer, base, addr;
1760 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1761
1762 rw_buffers = LLVMGetParam(ctx->main_fn,
1763 SI_PARAM_RW_BUFFERS);
1764 buffer = build_indexed_load_const(ctx, rw_buffers,
1765 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1766
1767 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1768 addr = get_tcs_tes_buffer_address(ctx, NULL,
1769 lp_build_const_int32(gallivm, param));
1770
1771 value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
1772 ~0, buffer, base, addr);
1773
1774 break;
1775 }
1776
1777 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1778 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1779 {
1780 LLVMValueRef buf, slot, val[4];
1781 int i, offset;
1782
1783 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1784 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1785 buf = build_indexed_load_const(ctx, buf, slot);
1786 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1787
1788 for (i = 0; i < 4; i++)
1789 val[i] = buffer_load_const(ctx, buf,
1790 lp_build_const_int32(gallivm, (offset + i) * 4));
1791 value = lp_build_gather_values(gallivm, val, 4);
1792 break;
1793 }
1794
1795 case TGSI_SEMANTIC_PRIMID:
1796 value = get_primitive_id(&radeon_bld->bld_base, 0);
1797 break;
1798
1799 case TGSI_SEMANTIC_GRID_SIZE:
1800 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1801 break;
1802
1803 case TGSI_SEMANTIC_BLOCK_SIZE:
1804 {
1805 LLVMValueRef values[3];
1806 unsigned i;
1807 unsigned *properties = ctx->shader->selector->info.properties;
1808
1809 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1810 unsigned sizes[3] = {
1811 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1812 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1813 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1814 };
1815
1816 for (i = 0; i < 3; ++i)
1817 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1818
1819 value = lp_build_gather_values(gallivm, values, 3);
1820 } else {
1821 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1822 }
1823 break;
1824 }
1825
1826 case TGSI_SEMANTIC_BLOCK_ID:
1827 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1828 break;
1829
1830 case TGSI_SEMANTIC_THREAD_ID:
1831 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1832 break;
1833
1834 case TGSI_SEMANTIC_HELPER_INVOCATION:
1835 if (HAVE_LLVM >= 0x0309) {
1836 value = lp_build_intrinsic(gallivm->builder,
1837 "llvm.amdgcn.ps.live",
1838 ctx->i1, NULL, 0,
1839 LP_FUNC_ATTR_READNONE);
1840 value = LLVMBuildNot(gallivm->builder, value, "");
1841 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1842 } else {
1843 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1844 return;
1845 }
1846 break;
1847
1848 default:
1849 assert(!"unknown system value");
1850 return;
1851 }
1852
1853 radeon_bld->system_values[index] = value;
1854 }
1855
1856 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1857 const struct tgsi_full_declaration *decl)
1858 {
1859 struct si_shader_context *ctx =
1860 si_shader_context(&radeon_bld->bld_base);
1861 struct si_shader_selector *sel = ctx->shader->selector;
1862 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1863
1864 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1865 LLVMValueRef var;
1866
1867 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1868 assert(decl->Range.First == decl->Range.Last);
1869 assert(!ctx->shared_memory);
1870
1871 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1872 LLVMArrayType(ctx->i8, sel->local_size),
1873 "compute_lds",
1874 LOCAL_ADDR_SPACE);
1875 LLVMSetAlignment(var, 4);
1876
1877 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1878 }
1879
1880 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1881 {
1882 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1883 SI_PARAM_CONST_BUFFERS);
1884
1885 return build_indexed_load_const(ctx, list_ptr,
1886 LLVMConstInt(ctx->i32, i, 0));
1887 }
1888
1889 static LLVMValueRef fetch_constant(
1890 struct lp_build_tgsi_context *bld_base,
1891 const struct tgsi_full_src_register *reg,
1892 enum tgsi_opcode_type type,
1893 unsigned swizzle)
1894 {
1895 struct si_shader_context *ctx = si_shader_context(bld_base);
1896 struct lp_build_context *base = &bld_base->base;
1897 const struct tgsi_ind_register *ireg = &reg->Indirect;
1898 unsigned buf, idx;
1899
1900 LLVMValueRef addr, bufp;
1901 LLVMValueRef result;
1902
1903 if (swizzle == LP_CHAN_ALL) {
1904 unsigned chan;
1905 LLVMValueRef values[4];
1906 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1907 values[chan] = fetch_constant(bld_base, reg, type, chan);
1908
1909 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1910 }
1911
1912 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1913 idx = reg->Register.Index * 4 + swizzle;
1914
1915 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1916 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1917 LLVMValueRef index;
1918 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1919 reg->Dimension.Index,
1920 SI_NUM_CONST_BUFFERS);
1921 bufp = build_indexed_load_const(ctx, ptr, index);
1922 } else
1923 bufp = load_const_buffer_desc(ctx, buf);
1924
1925 if (reg->Register.Indirect) {
1926 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1927 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1928 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1929 addr = lp_build_add(&bld_base->uint_bld, addr,
1930 lp_build_const_int32(base->gallivm, idx * 4));
1931 } else {
1932 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1933 }
1934
1935 result = buffer_load_const(ctx, bufp, addr);
1936
1937 if (!tgsi_type_is_64bit(type))
1938 result = bitcast(bld_base, type, result);
1939 else {
1940 LLVMValueRef addr2, result2;
1941
1942 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1943 LLVMConstInt(ctx->i32, 4, 0));
1944 result2 = buffer_load_const(ctx, bufp, addr2);
1945
1946 result = si_llvm_emit_fetch_64bit(bld_base, type,
1947 result, result2);
1948 }
1949 return result;
1950 }
1951
1952 /* Upper 16 bits must be zero. */
1953 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1954 LLVMValueRef val[2])
1955 {
1956 return LLVMBuildOr(gallivm->builder, val[0],
1957 LLVMBuildShl(gallivm->builder, val[1],
1958 lp_build_const_int32(gallivm, 16),
1959 ""), "");
1960 }
1961
1962 /* Upper 16 bits are ignored and will be dropped. */
1963 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1964 LLVMValueRef val[2])
1965 {
1966 LLVMValueRef v[2] = {
1967 LLVMBuildAnd(gallivm->builder, val[0],
1968 lp_build_const_int32(gallivm, 0xffff), ""),
1969 val[1],
1970 };
1971 return si_llvm_pack_two_int16(gallivm, v);
1972 }
1973
1974 /* Initialize arguments for the shader export intrinsic */
1975 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1976 LLVMValueRef *values,
1977 unsigned target,
1978 LLVMValueRef *args)
1979 {
1980 struct si_shader_context *ctx = si_shader_context(bld_base);
1981 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1982 struct lp_build_context *base = &bld_base->base;
1983 struct gallivm_state *gallivm = base->gallivm;
1984 LLVMBuilderRef builder = base->gallivm->builder;
1985 LLVMValueRef val[4];
1986 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1987 unsigned chan;
1988 bool is_int8;
1989
1990 /* Default is 0xf. Adjusted below depending on the format. */
1991 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1992
1993 /* Specify whether the EXEC mask represents the valid mask */
1994 args[1] = uint->zero;
1995
1996 /* Specify whether this is the last export */
1997 args[2] = uint->zero;
1998
1999 /* Specify the target we are exporting */
2000 args[3] = lp_build_const_int32(base->gallivm, target);
2001
2002 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2003 const struct si_shader_key *key = &ctx->shader->key;
2004 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2005 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2006
2007 assert(cbuf >= 0 && cbuf < 8);
2008 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2009 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2010 }
2011
2012 args[4] = uint->zero; /* COMPR flag */
2013 args[5] = base->undef;
2014 args[6] = base->undef;
2015 args[7] = base->undef;
2016 args[8] = base->undef;
2017
2018 switch (spi_shader_col_format) {
2019 case V_028714_SPI_SHADER_ZERO:
2020 args[0] = uint->zero; /* writemask */
2021 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2022 break;
2023
2024 case V_028714_SPI_SHADER_32_R:
2025 args[0] = uint->one; /* writemask */
2026 args[5] = values[0];
2027 break;
2028
2029 case V_028714_SPI_SHADER_32_GR:
2030 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2031 args[5] = values[0];
2032 args[6] = values[1];
2033 break;
2034
2035 case V_028714_SPI_SHADER_32_AR:
2036 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2037 args[5] = values[0];
2038 args[8] = values[3];
2039 break;
2040
2041 case V_028714_SPI_SHADER_FP16_ABGR:
2042 args[4] = uint->one; /* COMPR flag */
2043
2044 for (chan = 0; chan < 2; chan++) {
2045 LLVMValueRef pack_args[2] = {
2046 values[2 * chan],
2047 values[2 * chan + 1]
2048 };
2049 LLVMValueRef packed;
2050
2051 packed = lp_build_intrinsic(base->gallivm->builder,
2052 "llvm.SI.packf16",
2053 ctx->i32, pack_args, 2,
2054 LP_FUNC_ATTR_READNONE);
2055 args[chan + 5] =
2056 LLVMBuildBitCast(base->gallivm->builder,
2057 packed, ctx->f32, "");
2058 }
2059 break;
2060
2061 case V_028714_SPI_SHADER_UNORM16_ABGR:
2062 for (chan = 0; chan < 4; chan++) {
2063 val[chan] = si_llvm_saturate(bld_base, values[chan]);
2064 val[chan] = LLVMBuildFMul(builder, val[chan],
2065 lp_build_const_float(gallivm, 65535), "");
2066 val[chan] = LLVMBuildFAdd(builder, val[chan],
2067 lp_build_const_float(gallivm, 0.5), "");
2068 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2069 ctx->i32, "");
2070 }
2071
2072 args[4] = uint->one; /* COMPR flag */
2073 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2074 si_llvm_pack_two_int16(gallivm, val));
2075 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2076 si_llvm_pack_two_int16(gallivm, val+2));
2077 break;
2078
2079 case V_028714_SPI_SHADER_SNORM16_ABGR:
2080 for (chan = 0; chan < 4; chan++) {
2081 /* Clamp between [-1, 1]. */
2082 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2083 values[chan],
2084 lp_build_const_float(gallivm, 1));
2085 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2086 val[chan],
2087 lp_build_const_float(gallivm, -1));
2088 /* Convert to a signed integer in [-32767, 32767]. */
2089 val[chan] = LLVMBuildFMul(builder, val[chan],
2090 lp_build_const_float(gallivm, 32767), "");
2091 /* If positive, add 0.5, else add -0.5. */
2092 val[chan] = LLVMBuildFAdd(builder, val[chan],
2093 LLVMBuildSelect(builder,
2094 LLVMBuildFCmp(builder, LLVMRealOGE,
2095 val[chan], base->zero, ""),
2096 lp_build_const_float(gallivm, 0.5),
2097 lp_build_const_float(gallivm, -0.5), ""), "");
2098 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2099 }
2100
2101 args[4] = uint->one; /* COMPR flag */
2102 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2103 si_llvm_pack_two_int32_as_int16(gallivm, val));
2104 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2105 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2106 break;
2107
2108 case V_028714_SPI_SHADER_UINT16_ABGR: {
2109 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2110 255 : 65535);
2111 /* Clamp. */
2112 for (chan = 0; chan < 4; chan++) {
2113 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2114 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2115 val[chan], max);
2116 }
2117
2118 args[4] = uint->one; /* COMPR flag */
2119 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2120 si_llvm_pack_two_int16(gallivm, val));
2121 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2122 si_llvm_pack_two_int16(gallivm, val+2));
2123 break;
2124 }
2125
2126 case V_028714_SPI_SHADER_SINT16_ABGR: {
2127 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2128 127 : 32767);
2129 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2130 -128 : -32768);
2131 /* Clamp. */
2132 for (chan = 0; chan < 4; chan++) {
2133 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2134 val[chan] = lp_build_emit_llvm_binary(bld_base,
2135 TGSI_OPCODE_IMIN,
2136 val[chan], max);
2137 val[chan] = lp_build_emit_llvm_binary(bld_base,
2138 TGSI_OPCODE_IMAX,
2139 val[chan], min);
2140 }
2141
2142 args[4] = uint->one; /* COMPR flag */
2143 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2144 si_llvm_pack_two_int32_as_int16(gallivm, val));
2145 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2146 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2147 break;
2148 }
2149
2150 case V_028714_SPI_SHADER_32_ABGR:
2151 memcpy(&args[5], values, sizeof(values[0]) * 4);
2152 break;
2153 }
2154 }
2155
2156 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2157 LLVMValueRef alpha)
2158 {
2159 struct si_shader_context *ctx = si_shader_context(bld_base);
2160 struct gallivm_state *gallivm = bld_base->base.gallivm;
2161
2162 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2163 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2164 SI_PARAM_ALPHA_REF);
2165
2166 LLVMValueRef alpha_pass =
2167 lp_build_cmp(&bld_base->base,
2168 ctx->shader->key.part.ps.epilog.alpha_func,
2169 alpha, alpha_ref);
2170 LLVMValueRef arg =
2171 lp_build_select(&bld_base->base,
2172 alpha_pass,
2173 lp_build_const_float(gallivm, 1.0f),
2174 lp_build_const_float(gallivm, -1.0f));
2175
2176 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2177 ctx->voidt, &arg, 1, 0);
2178 } else {
2179 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2180 ctx->voidt, NULL, 0, 0);
2181 }
2182 }
2183
2184 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2185 LLVMValueRef alpha,
2186 unsigned samplemask_param)
2187 {
2188 struct si_shader_context *ctx = si_shader_context(bld_base);
2189 struct gallivm_state *gallivm = bld_base->base.gallivm;
2190 LLVMValueRef coverage;
2191
2192 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2193 coverage = LLVMGetParam(ctx->main_fn,
2194 samplemask_param);
2195 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2196
2197 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2198 ctx->i32,
2199 &coverage, 1, LP_FUNC_ATTR_READNONE);
2200
2201 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2202 ctx->f32, "");
2203
2204 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2205 lp_build_const_float(gallivm,
2206 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2207
2208 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2209 }
2210
2211 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2212 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2213 {
2214 struct si_shader_context *ctx = si_shader_context(bld_base);
2215 struct lp_build_context *base = &bld_base->base;
2216 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
2217 unsigned reg_index;
2218 unsigned chan;
2219 unsigned const_chan;
2220 LLVMValueRef base_elt;
2221 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2222 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2223 SI_VS_CONST_CLIP_PLANES);
2224 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2225
2226 for (reg_index = 0; reg_index < 2; reg_index ++) {
2227 LLVMValueRef *args = pos[2 + reg_index];
2228
2229 args[5] =
2230 args[6] =
2231 args[7] =
2232 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2233
2234 /* Compute dot products of position and user clip plane vectors */
2235 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2236 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2237 args[1] = lp_build_const_int32(base->gallivm,
2238 ((reg_index * 4 + chan) * 4 +
2239 const_chan) * 4);
2240 base_elt = buffer_load_const(ctx, const_resource,
2241 args[1]);
2242 args[5 + chan] =
2243 lp_build_add(base, args[5 + chan],
2244 lp_build_mul(base, base_elt,
2245 out_elts[const_chan]));
2246 }
2247 }
2248
2249 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2250 args[1] = uint->zero;
2251 args[2] = uint->zero;
2252 args[3] = lp_build_const_int32(base->gallivm,
2253 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2254 args[4] = uint->zero;
2255 }
2256 }
2257
2258 static void si_dump_streamout(struct pipe_stream_output_info *so)
2259 {
2260 unsigned i;
2261
2262 if (so->num_outputs)
2263 fprintf(stderr, "STREAMOUT\n");
2264
2265 for (i = 0; i < so->num_outputs; i++) {
2266 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2267 so->output[i].start_component;
2268 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2269 i, so->output[i].output_buffer,
2270 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2271 so->output[i].register_index,
2272 mask & 1 ? "x" : "",
2273 mask & 2 ? "y" : "",
2274 mask & 4 ? "z" : "",
2275 mask & 8 ? "w" : "");
2276 }
2277 }
2278
2279 static void emit_streamout_output(struct si_shader_context *ctx,
2280 LLVMValueRef const *so_buffers,
2281 LLVMValueRef const *so_write_offsets,
2282 struct pipe_stream_output *stream_out,
2283 struct si_shader_output_values *shader_out)
2284 {
2285 struct gallivm_state *gallivm = &ctx->gallivm;
2286 LLVMBuilderRef builder = gallivm->builder;
2287 unsigned buf_idx = stream_out->output_buffer;
2288 unsigned start = stream_out->start_component;
2289 unsigned num_comps = stream_out->num_components;
2290 LLVMValueRef out[4];
2291
2292 assert(num_comps && num_comps <= 4);
2293 if (!num_comps || num_comps > 4)
2294 return;
2295
2296 /* Load the output as int. */
2297 for (int j = 0; j < num_comps; j++) {
2298 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2299
2300 out[j] = LLVMBuildBitCast(builder,
2301 shader_out->values[start + j],
2302 ctx->i32, "");
2303 }
2304
2305 /* Pack the output. */
2306 LLVMValueRef vdata = NULL;
2307
2308 switch (num_comps) {
2309 case 1: /* as i32 */
2310 vdata = out[0];
2311 break;
2312 case 2: /* as v2i32 */
2313 case 3: /* as v4i32 (aligned to 4) */
2314 case 4: /* as v4i32 */
2315 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2316 for (int j = 0; j < num_comps; j++) {
2317 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2318 LLVMConstInt(ctx->i32, j, 0), "");
2319 }
2320 break;
2321 }
2322
2323 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2324 vdata, num_comps,
2325 so_write_offsets[buf_idx],
2326 LLVMConstInt(ctx->i32, 0, 0),
2327 stream_out->dst_offset * 4);
2328 }
2329
2330 /**
2331 * Write streamout data to buffers for vertex stream @p stream (different
2332 * vertex streams can occur for GS copy shaders).
2333 */
2334 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2335 struct si_shader_output_values *outputs,
2336 unsigned noutput, unsigned stream)
2337 {
2338 struct si_shader_selector *sel = ctx->shader->selector;
2339 struct pipe_stream_output_info *so = &sel->so;
2340 struct gallivm_state *gallivm = &ctx->gallivm;
2341 LLVMBuilderRef builder = gallivm->builder;
2342 int i;
2343 struct lp_build_if_state if_ctx;
2344
2345 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2346 LLVMValueRef so_vtx_count =
2347 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2348
2349 LLVMValueRef tid = get_thread_id(ctx);
2350
2351 /* can_emit = tid < so_vtx_count; */
2352 LLVMValueRef can_emit =
2353 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2354
2355 /* Emit the streamout code conditionally. This actually avoids
2356 * out-of-bounds buffer access. The hw tells us via the SGPR
2357 * (so_vtx_count) which threads are allowed to emit streamout data. */
2358 lp_build_if(&if_ctx, gallivm, can_emit);
2359 {
2360 /* The buffer offset is computed as follows:
2361 * ByteOffset = streamout_offset[buffer_id]*4 +
2362 * (streamout_write_index + thread_id)*stride[buffer_id] +
2363 * attrib_offset
2364 */
2365
2366 LLVMValueRef so_write_index =
2367 LLVMGetParam(ctx->main_fn,
2368 ctx->param_streamout_write_index);
2369
2370 /* Compute (streamout_write_index + thread_id). */
2371 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2372
2373 /* Load the descriptor and compute the write offset for each
2374 * enabled buffer. */
2375 LLVMValueRef so_write_offset[4] = {};
2376 LLVMValueRef so_buffers[4];
2377 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2378 SI_PARAM_RW_BUFFERS);
2379
2380 for (i = 0; i < 4; i++) {
2381 if (!so->stride[i])
2382 continue;
2383
2384 LLVMValueRef offset = lp_build_const_int32(gallivm,
2385 SI_VS_STREAMOUT_BUF0 + i);
2386
2387 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2388
2389 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2390 ctx->param_streamout_offset[i]);
2391 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2392
2393 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2394 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2395 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2396 }
2397
2398 /* Write streamout data. */
2399 for (i = 0; i < so->num_outputs; i++) {
2400 unsigned reg = so->output[i].register_index;
2401
2402 if (reg >= noutput)
2403 continue;
2404
2405 if (stream != so->output[i].stream)
2406 continue;
2407
2408 emit_streamout_output(ctx, so_buffers, so_write_offset,
2409 &so->output[i], &outputs[reg]);
2410 }
2411 }
2412 lp_build_endif(&if_ctx);
2413 }
2414
2415
2416 /* Generate export instructions for hardware VS shader stage */
2417 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2418 struct si_shader_output_values *outputs,
2419 unsigned noutput)
2420 {
2421 struct si_shader_context *ctx = si_shader_context(bld_base);
2422 struct si_shader *shader = ctx->shader;
2423 struct lp_build_context *base = &bld_base->base;
2424 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
2425 LLVMValueRef args[9];
2426 LLVMValueRef pos_args[4][9] = { { 0 } };
2427 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2428 unsigned semantic_name, semantic_index;
2429 unsigned target;
2430 unsigned param_count = 0;
2431 unsigned pos_idx;
2432 int i;
2433
2434 for (i = 0; i < noutput; i++) {
2435 semantic_name = outputs[i].semantic_name;
2436 semantic_index = outputs[i].semantic_index;
2437 bool export_param = true;
2438
2439 switch (semantic_name) {
2440 case TGSI_SEMANTIC_POSITION: /* ignore these */
2441 case TGSI_SEMANTIC_PSIZE:
2442 case TGSI_SEMANTIC_CLIPVERTEX:
2443 case TGSI_SEMANTIC_EDGEFLAG:
2444 break;
2445 case TGSI_SEMANTIC_GENERIC:
2446 case TGSI_SEMANTIC_CLIPDIST:
2447 if (shader->key.opt.hw_vs.kill_outputs &
2448 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2449 export_param = false;
2450 break;
2451 default:
2452 if (shader->key.opt.hw_vs.kill_outputs2 &
2453 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2454 export_param = false;
2455 break;
2456 }
2457
2458 if (outputs[i].vertex_stream[0] != 0 &&
2459 outputs[i].vertex_stream[1] != 0 &&
2460 outputs[i].vertex_stream[2] != 0 &&
2461 outputs[i].vertex_stream[3] != 0)
2462 export_param = false;
2463
2464 handle_semantic:
2465 /* Select the correct target */
2466 switch(semantic_name) {
2467 case TGSI_SEMANTIC_PSIZE:
2468 psize_value = outputs[i].values[0];
2469 continue;
2470 case TGSI_SEMANTIC_EDGEFLAG:
2471 edgeflag_value = outputs[i].values[0];
2472 continue;
2473 case TGSI_SEMANTIC_LAYER:
2474 layer_value = outputs[i].values[0];
2475 semantic_name = TGSI_SEMANTIC_GENERIC;
2476 goto handle_semantic;
2477 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2478 viewport_index_value = outputs[i].values[0];
2479 semantic_name = TGSI_SEMANTIC_GENERIC;
2480 goto handle_semantic;
2481 case TGSI_SEMANTIC_POSITION:
2482 target = V_008DFC_SQ_EXP_POS;
2483 break;
2484 case TGSI_SEMANTIC_CLIPDIST:
2485 if (shader->key.opt.hw_vs.clip_disable) {
2486 semantic_name = TGSI_SEMANTIC_GENERIC;
2487 goto handle_semantic;
2488 }
2489 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2490 break;
2491 case TGSI_SEMANTIC_CLIPVERTEX:
2492 if (shader->key.opt.hw_vs.clip_disable)
2493 continue;
2494 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2495 continue;
2496 case TGSI_SEMANTIC_COLOR:
2497 case TGSI_SEMANTIC_BCOLOR:
2498 case TGSI_SEMANTIC_PRIMID:
2499 case TGSI_SEMANTIC_FOG:
2500 case TGSI_SEMANTIC_TEXCOORD:
2501 case TGSI_SEMANTIC_GENERIC:
2502 if (!export_param)
2503 continue;
2504 target = V_008DFC_SQ_EXP_PARAM + param_count;
2505 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2506 shader->info.vs_output_param_offset[i] = param_count;
2507 param_count++;
2508 break;
2509 default:
2510 target = 0;
2511 fprintf(stderr,
2512 "Warning: SI unhandled vs output type:%d\n",
2513 semantic_name);
2514 }
2515
2516 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2517
2518 if (target >= V_008DFC_SQ_EXP_POS &&
2519 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2520 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2521 args, sizeof(args));
2522 } else {
2523 lp_build_intrinsic(base->gallivm->builder,
2524 "llvm.SI.export", ctx->voidt,
2525 args, 9, 0);
2526 }
2527
2528 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2529 semantic_name = TGSI_SEMANTIC_GENERIC;
2530 goto handle_semantic;
2531 }
2532 }
2533
2534 shader->info.nr_param_exports = param_count;
2535
2536 /* We need to add the position output manually if it's missing. */
2537 if (!pos_args[0][0]) {
2538 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2539 pos_args[0][1] = uint->zero; /* EXEC mask */
2540 pos_args[0][2] = uint->zero; /* last export? */
2541 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2542 pos_args[0][4] = uint->zero; /* COMPR flag */
2543 pos_args[0][5] = base->zero; /* X */
2544 pos_args[0][6] = base->zero; /* Y */
2545 pos_args[0][7] = base->zero; /* Z */
2546 pos_args[0][8] = base->one; /* W */
2547 }
2548
2549 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2550 if (shader->selector->info.writes_psize ||
2551 shader->selector->info.writes_edgeflag ||
2552 shader->selector->info.writes_viewport_index ||
2553 shader->selector->info.writes_layer) {
2554 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2555 shader->selector->info.writes_psize |
2556 (shader->selector->info.writes_edgeflag << 1) |
2557 (shader->selector->info.writes_layer << 2) |
2558 (shader->selector->info.writes_viewport_index << 3));
2559 pos_args[1][1] = uint->zero; /* EXEC mask */
2560 pos_args[1][2] = uint->zero; /* last export? */
2561 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2562 pos_args[1][4] = uint->zero; /* COMPR flag */
2563 pos_args[1][5] = base->zero; /* X */
2564 pos_args[1][6] = base->zero; /* Y */
2565 pos_args[1][7] = base->zero; /* Z */
2566 pos_args[1][8] = base->zero; /* W */
2567
2568 if (shader->selector->info.writes_psize)
2569 pos_args[1][5] = psize_value;
2570
2571 if (shader->selector->info.writes_edgeflag) {
2572 /* The output is a float, but the hw expects an integer
2573 * with the first bit containing the edge flag. */
2574 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2575 edgeflag_value,
2576 ctx->i32, "");
2577 edgeflag_value = lp_build_min(&bld_base->int_bld,
2578 edgeflag_value,
2579 bld_base->int_bld.one);
2580
2581 /* The LLVM intrinsic expects a float. */
2582 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2583 edgeflag_value,
2584 ctx->f32, "");
2585 }
2586
2587 if (shader->selector->info.writes_layer)
2588 pos_args[1][7] = layer_value;
2589
2590 if (shader->selector->info.writes_viewport_index)
2591 pos_args[1][8] = viewport_index_value;
2592 }
2593
2594 for (i = 0; i < 4; i++)
2595 if (pos_args[i][0])
2596 shader->info.nr_pos_exports++;
2597
2598 pos_idx = 0;
2599 for (i = 0; i < 4; i++) {
2600 if (!pos_args[i][0])
2601 continue;
2602
2603 /* Specify the target we are exporting */
2604 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2605
2606 if (pos_idx == shader->info.nr_pos_exports)
2607 /* Specify that this is the last export */
2608 pos_args[i][2] = uint->one;
2609
2610 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2611 ctx->voidt, pos_args[i], 9, 0);
2612 }
2613 }
2614
2615 /**
2616 * Forward all outputs from the vertex shader to the TES. This is only used
2617 * for the fixed function TCS.
2618 */
2619 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2620 {
2621 struct si_shader_context *ctx = si_shader_context(bld_base);
2622 struct gallivm_state *gallivm = bld_base->base.gallivm;
2623 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2624 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2625 uint64_t inputs;
2626
2627 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2628
2629 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2630 buffer = build_indexed_load_const(ctx, rw_buffers,
2631 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2632
2633 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2634
2635 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2636 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2637 lds_vertex_stride, "");
2638 lds_base = get_tcs_in_current_patch_offset(ctx);
2639 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2640
2641 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2642 while (inputs) {
2643 unsigned i = u_bit_scan64(&inputs);
2644
2645 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2646 lp_build_const_int32(gallivm, 4 * i),
2647 "");
2648
2649 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2650 invocation_id,
2651 lp_build_const_int32(gallivm, i));
2652
2653 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2654 lds_ptr);
2655
2656 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2657 buffer_offset, 0);
2658 }
2659 }
2660
2661 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2662 LLVMValueRef rel_patch_id,
2663 LLVMValueRef invocation_id,
2664 LLVMValueRef tcs_out_current_patch_data_offset)
2665 {
2666 struct si_shader_context *ctx = si_shader_context(bld_base);
2667 struct gallivm_state *gallivm = bld_base->base.gallivm;
2668 struct si_shader *shader = ctx->shader;
2669 unsigned tess_inner_index, tess_outer_index;
2670 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2671 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2672 unsigned stride, outer_comps, inner_comps, i;
2673 struct lp_build_if_state if_ctx, inner_if_ctx;
2674
2675 si_llvm_emit_barrier(NULL, bld_base, NULL);
2676
2677 /* Do this only for invocation 0, because the tess levels are per-patch,
2678 * not per-vertex.
2679 *
2680 * This can't jump, because invocation 0 executes this. It should
2681 * at least mask out the loads and stores for other invocations.
2682 */
2683 lp_build_if(&if_ctx, gallivm,
2684 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2685 invocation_id, bld_base->uint_bld.zero, ""));
2686
2687 /* Determine the layout of one tess factor element in the buffer. */
2688 switch (shader->key.part.tcs.epilog.prim_mode) {
2689 case PIPE_PRIM_LINES:
2690 stride = 2; /* 2 dwords, 1 vec2 store */
2691 outer_comps = 2;
2692 inner_comps = 0;
2693 break;
2694 case PIPE_PRIM_TRIANGLES:
2695 stride = 4; /* 4 dwords, 1 vec4 store */
2696 outer_comps = 3;
2697 inner_comps = 1;
2698 break;
2699 case PIPE_PRIM_QUADS:
2700 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2701 outer_comps = 4;
2702 inner_comps = 2;
2703 break;
2704 default:
2705 assert(0);
2706 return;
2707 }
2708
2709 /* Load tess_inner and tess_outer from LDS.
2710 * Any invocation can write them, so we can't get them from a temporary.
2711 */
2712 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2713 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2714
2715 lds_base = tcs_out_current_patch_data_offset;
2716 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2717 lp_build_const_int32(gallivm,
2718 tess_inner_index * 4), "");
2719 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2720 lp_build_const_int32(gallivm,
2721 tess_outer_index * 4), "");
2722
2723 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2724 /* For isolines, the hardware expects tess factors in the
2725 * reverse order from what GLSL / TGSI specify.
2726 */
2727 out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2728 out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2729 } else {
2730 for (i = 0; i < outer_comps; i++)
2731 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2732 for (i = 0; i < inner_comps; i++)
2733 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2734 }
2735
2736 /* Convert the outputs to vectors for stores. */
2737 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2738 vec1 = NULL;
2739
2740 if (stride > 4)
2741 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2742
2743 /* Get the buffer. */
2744 rw_buffers = LLVMGetParam(ctx->main_fn,
2745 SI_PARAM_RW_BUFFERS);
2746 buffer = build_indexed_load_const(ctx, rw_buffers,
2747 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2748
2749 /* Get the offset. */
2750 tf_base = LLVMGetParam(ctx->main_fn,
2751 SI_PARAM_TESS_FACTOR_OFFSET);
2752 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2753 lp_build_const_int32(gallivm, 4 * stride), "");
2754
2755 lp_build_if(&inner_if_ctx, gallivm,
2756 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2757 rel_patch_id, bld_base->uint_bld.zero, ""));
2758
2759 /* Store the dynamic HS control word. */
2760 build_tbuffer_store_dwords(ctx, buffer,
2761 lp_build_const_int32(gallivm, 0x80000000),
2762 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2763
2764 lp_build_endif(&inner_if_ctx);
2765
2766 /* Store the tessellation factors. */
2767 build_tbuffer_store_dwords(ctx, buffer, vec0,
2768 MIN2(stride, 4), byteoffset, tf_base, 4);
2769 if (vec1)
2770 build_tbuffer_store_dwords(ctx, buffer, vec1,
2771 stride - 4, byteoffset, tf_base, 20);
2772 lp_build_endif(&if_ctx);
2773 }
2774
2775 /* This only writes the tessellation factor levels. */
2776 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2777 {
2778 struct si_shader_context *ctx = si_shader_context(bld_base);
2779 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2780
2781 si_copy_tcs_inputs(bld_base);
2782
2783 rel_patch_id = get_rel_patch_id(ctx);
2784 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2785 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2786
2787 /* Return epilog parameters from this function. */
2788 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2789 LLVMValueRef ret = ctx->return_value;
2790 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2791 unsigned vgpr;
2792
2793 /* RW_BUFFERS pointer */
2794 rw_buffers = LLVMGetParam(ctx->main_fn,
2795 SI_PARAM_RW_BUFFERS);
2796 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2797 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2798 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2799 bld_base->uint_bld.zero, "");
2800 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2801 bld_base->uint_bld.one, "");
2802 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2803 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2804
2805 /* Tess factor buffer soffset is after user SGPRs. */
2806 tf_soffset = LLVMGetParam(ctx->main_fn,
2807 SI_PARAM_TESS_FACTOR_OFFSET);
2808 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2809 SI_TCS_NUM_USER_SGPR + 1, "");
2810
2811 /* VGPRs */
2812 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2813 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2814 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2815
2816 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2817 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2818 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2819 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2820 ctx->return_value = ret;
2821 }
2822
2823 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2824 {
2825 struct si_shader_context *ctx = si_shader_context(bld_base);
2826 struct si_shader *shader = ctx->shader;
2827 struct tgsi_shader_info *info = &shader->selector->info;
2828 struct gallivm_state *gallivm = bld_base->base.gallivm;
2829 unsigned i, chan;
2830 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2831 ctx->param_rel_auto_id);
2832 LLVMValueRef vertex_dw_stride =
2833 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2834 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2835 vertex_dw_stride, "");
2836
2837 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2838 * its inputs from it. */
2839 for (i = 0; i < info->num_outputs; i++) {
2840 LLVMValueRef *out_ptr = ctx->outputs[i];
2841 unsigned name = info->output_semantic_name[i];
2842 unsigned index = info->output_semantic_index[i];
2843 int param = si_shader_io_get_unique_index(name, index);
2844 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2845 lp_build_const_int32(gallivm, param * 4), "");
2846
2847 for (chan = 0; chan < 4; chan++) {
2848 lds_store(bld_base, chan, dw_addr,
2849 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2850 }
2851 }
2852 }
2853
2854 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2855 {
2856 struct si_shader_context *ctx = si_shader_context(bld_base);
2857 struct gallivm_state *gallivm = bld_base->base.gallivm;
2858 struct si_shader *es = ctx->shader;
2859 struct tgsi_shader_info *info = &es->selector->info;
2860 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2861 ctx->param_es2gs_offset);
2862 unsigned chan;
2863 int i;
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 LLVMValueRef *out_ptr = ctx->outputs[i];
2867 int param_index;
2868
2869 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2870 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2871 continue;
2872
2873 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2874 info->output_semantic_index[i]);
2875
2876 for (chan = 0; chan < 4; chan++) {
2877 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2878 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2879
2880 build_tbuffer_store(ctx,
2881 ctx->esgs_ring,
2882 out_val, 1,
2883 LLVMGetUndef(ctx->i32), soffset,
2884 (4 * param_index + chan) * 4,
2885 V_008F0C_BUF_DATA_FORMAT_32,
2886 V_008F0C_BUF_NUM_FORMAT_UINT,
2887 0, 0, 1, 1, 0);
2888 }
2889 }
2890 }
2891
2892 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2893 {
2894 struct si_shader_context *ctx = si_shader_context(bld_base);
2895 struct gallivm_state *gallivm = bld_base->base.gallivm;
2896 LLVMValueRef args[2];
2897
2898 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2899 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2900 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2901 ctx->voidt, args, 2, 0);
2902 }
2903
2904 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2905 {
2906 struct si_shader_context *ctx = si_shader_context(bld_base);
2907 struct gallivm_state *gallivm = bld_base->base.gallivm;
2908 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2909 struct si_shader_output_values *outputs = NULL;
2910 int i,j;
2911
2912 assert(!ctx->shader->is_gs_copy_shader);
2913
2914 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2915
2916 /* Vertex color clamping.
2917 *
2918 * This uses a state constant loaded in a user data SGPR and
2919 * an IF statement is added that clamps all colors if the constant
2920 * is true.
2921 */
2922 if (ctx->type == PIPE_SHADER_VERTEX) {
2923 struct lp_build_if_state if_ctx;
2924 LLVMValueRef cond = NULL;
2925 LLVMValueRef addr, val;
2926
2927 for (i = 0; i < info->num_outputs; i++) {
2928 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2929 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2930 continue;
2931
2932 /* We've found a color. */
2933 if (!cond) {
2934 /* The state is in the first bit of the user SGPR. */
2935 cond = LLVMGetParam(ctx->main_fn,
2936 SI_PARAM_VS_STATE_BITS);
2937 cond = LLVMBuildTrunc(gallivm->builder, cond,
2938 ctx->i1, "");
2939 lp_build_if(&if_ctx, gallivm, cond);
2940 }
2941
2942 for (j = 0; j < 4; j++) {
2943 addr = ctx->outputs[i][j];
2944 val = LLVMBuildLoad(gallivm->builder, addr, "");
2945 val = si_llvm_saturate(bld_base, val);
2946 LLVMBuildStore(gallivm->builder, val, addr);
2947 }
2948 }
2949
2950 if (cond)
2951 lp_build_endif(&if_ctx);
2952 }
2953
2954 for (i = 0; i < info->num_outputs; i++) {
2955 outputs[i].semantic_name = info->output_semantic_name[i];
2956 outputs[i].semantic_index = info->output_semantic_index[i];
2957
2958 for (j = 0; j < 4; j++) {
2959 outputs[i].values[j] =
2960 LLVMBuildLoad(gallivm->builder,
2961 ctx->outputs[i][j],
2962 "");
2963 outputs[i].vertex_stream[j] =
2964 (info->output_streams[i] >> (2 * j)) & 3;
2965 }
2966
2967 }
2968
2969 /* Return the primitive ID from the LLVM function. */
2970 ctx->return_value =
2971 LLVMBuildInsertValue(gallivm->builder,
2972 ctx->return_value,
2973 bitcast(bld_base, TGSI_TYPE_FLOAT,
2974 get_primitive_id(bld_base, 0)),
2975 VS_EPILOG_PRIMID_LOC, "");
2976
2977 if (ctx->shader->selector->so.num_outputs)
2978 si_llvm_emit_streamout(ctx, outputs, i, 0);
2979 si_llvm_export_vs(bld_base, outputs, i);
2980 FREE(outputs);
2981 }
2982
2983 struct si_ps_exports {
2984 unsigned num;
2985 LLVMValueRef args[10][9];
2986 };
2987
2988 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2989 bool writes_samplemask)
2990 {
2991 if (writes_z) {
2992 /* Z needs 32 bits. */
2993 if (writes_samplemask)
2994 return V_028710_SPI_SHADER_32_ABGR;
2995 else if (writes_stencil)
2996 return V_028710_SPI_SHADER_32_GR;
2997 else
2998 return V_028710_SPI_SHADER_32_R;
2999 } else if (writes_stencil || writes_samplemask) {
3000 /* Both stencil and sample mask need only 16 bits. */
3001 return V_028710_SPI_SHADER_UINT16_ABGR;
3002 } else {
3003 return V_028710_SPI_SHADER_ZERO;
3004 }
3005 }
3006
3007 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3008 LLVMValueRef depth, LLVMValueRef stencil,
3009 LLVMValueRef samplemask, struct si_ps_exports *exp)
3010 {
3011 struct si_shader_context *ctx = si_shader_context(bld_base);
3012 struct lp_build_context *base = &bld_base->base;
3013 struct lp_build_context *uint = &bld_base->uint_bld;
3014 LLVMValueRef args[9];
3015 unsigned mask = 0;
3016 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3017 stencil != NULL,
3018 samplemask != NULL);
3019
3020 assert(depth || stencil || samplemask);
3021
3022 args[1] = uint->one; /* whether the EXEC mask is valid */
3023 args[2] = uint->one; /* DONE bit */
3024
3025 /* Specify the target we are exporting */
3026 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
3027
3028 args[4] = uint->zero; /* COMP flag */
3029 args[5] = base->undef; /* R, depth */
3030 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3031 args[7] = base->undef; /* B, sample mask */
3032 args[8] = base->undef; /* A, alpha to mask */
3033
3034 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3035 assert(!depth);
3036 args[4] = uint->one; /* COMPR flag */
3037
3038 if (stencil) {
3039 /* Stencil should be in X[23:16]. */
3040 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
3041 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
3042 LLVMConstInt(ctx->i32, 16, 0), "");
3043 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
3044 mask |= 0x3;
3045 }
3046 if (samplemask) {
3047 /* SampleMask should be in Y[15:0]. */
3048 args[6] = samplemask;
3049 mask |= 0xc;
3050 }
3051 } else {
3052 if (depth) {
3053 args[5] = depth;
3054 mask |= 0x1;
3055 }
3056 if (stencil) {
3057 args[6] = stencil;
3058 mask |= 0x2;
3059 }
3060 if (samplemask) {
3061 args[7] = samplemask;
3062 mask |= 0x4;
3063 }
3064 }
3065
3066 /* SI (except OLAND and HAINAN) has a bug that it only looks
3067 * at the X writemask component. */
3068 if (ctx->screen->b.chip_class == SI &&
3069 ctx->screen->b.family != CHIP_OLAND &&
3070 ctx->screen->b.family != CHIP_HAINAN)
3071 mask |= 0x1;
3072
3073 /* Specify which components to enable */
3074 args[0] = lp_build_const_int32(base->gallivm, mask);
3075
3076 memcpy(exp->args[exp->num++], args, sizeof(args));
3077 }
3078
3079 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3080 LLVMValueRef *color, unsigned index,
3081 unsigned samplemask_param,
3082 bool is_last, struct si_ps_exports *exp)
3083 {
3084 struct si_shader_context *ctx = si_shader_context(bld_base);
3085 struct lp_build_context *base = &bld_base->base;
3086 int i;
3087
3088 /* Clamp color */
3089 if (ctx->shader->key.part.ps.epilog.clamp_color)
3090 for (i = 0; i < 4; i++)
3091 color[i] = si_llvm_saturate(bld_base, color[i]);
3092
3093 /* Alpha to one */
3094 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3095 color[3] = base->one;
3096
3097 /* Alpha test */
3098 if (index == 0 &&
3099 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3100 si_alpha_test(bld_base, color[3]);
3101
3102 /* Line & polygon smoothing */
3103 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3104 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3105 samplemask_param);
3106
3107 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3108 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3109 LLVMValueRef args[8][9];
3110 int c, last = -1;
3111
3112 /* Get the export arguments, also find out what the last one is. */
3113 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3114 si_llvm_init_export_args(bld_base, color,
3115 V_008DFC_SQ_EXP_MRT + c, args[c]);
3116 if (args[c][0] != bld_base->uint_bld.zero)
3117 last = c;
3118 }
3119
3120 /* Emit all exports. */
3121 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3122 if (is_last && last == c) {
3123 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3124 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3125 } else if (args[c][0] == bld_base->uint_bld.zero)
3126 continue; /* unnecessary NULL export */
3127
3128 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3129 }
3130 } else {
3131 LLVMValueRef args[9];
3132
3133 /* Export */
3134 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3135 args);
3136 if (is_last) {
3137 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3138 args[2] = bld_base->uint_bld.one; /* DONE bit */
3139 } else if (args[0] == bld_base->uint_bld.zero)
3140 return; /* unnecessary NULL export */
3141
3142 memcpy(exp->args[exp->num++], args, sizeof(args));
3143 }
3144 }
3145
3146 static void si_emit_ps_exports(struct si_shader_context *ctx,
3147 struct si_ps_exports *exp)
3148 {
3149 for (unsigned i = 0; i < exp->num; i++)
3150 lp_build_intrinsic(ctx->gallivm.builder,
3151 "llvm.SI.export", ctx->voidt,
3152 exp->args[i], 9, 0);
3153 }
3154
3155 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3156 {
3157 struct si_shader_context *ctx = si_shader_context(bld_base);
3158 struct lp_build_context *base = &bld_base->base;
3159 struct lp_build_context *uint = &bld_base->uint_bld;
3160 LLVMValueRef args[9];
3161
3162 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3163 args[1] = uint->one; /* whether the EXEC mask is valid */
3164 args[2] = uint->one; /* DONE bit */
3165 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3166 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3167 args[5] = base->undef; /* R */
3168 args[6] = base->undef; /* G */
3169 args[7] = base->undef; /* B */
3170 args[8] = base->undef; /* A */
3171
3172 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3173 ctx->voidt, args, 9, 0);
3174 }
3175
3176 /**
3177 * Return PS outputs in this order:
3178 *
3179 * v[0:3] = color0.xyzw
3180 * v[4:7] = color1.xyzw
3181 * ...
3182 * vN+0 = Depth
3183 * vN+1 = Stencil
3184 * vN+2 = SampleMask
3185 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3186 *
3187 * The alpha-ref SGPR is returned via its original location.
3188 */
3189 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3190 {
3191 struct si_shader_context *ctx = si_shader_context(bld_base);
3192 struct si_shader *shader = ctx->shader;
3193 struct lp_build_context *base = &bld_base->base;
3194 struct tgsi_shader_info *info = &shader->selector->info;
3195 LLVMBuilderRef builder = base->gallivm->builder;
3196 unsigned i, j, first_vgpr, vgpr;
3197
3198 LLVMValueRef color[8][4] = {};
3199 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3200 LLVMValueRef ret;
3201
3202 /* Read the output values. */
3203 for (i = 0; i < info->num_outputs; i++) {
3204 unsigned semantic_name = info->output_semantic_name[i];
3205 unsigned semantic_index = info->output_semantic_index[i];
3206
3207 switch (semantic_name) {
3208 case TGSI_SEMANTIC_COLOR:
3209 assert(semantic_index < 8);
3210 for (j = 0; j < 4; j++) {
3211 LLVMValueRef ptr = ctx->outputs[i][j];
3212 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3213 color[semantic_index][j] = result;
3214 }
3215 break;
3216 case TGSI_SEMANTIC_POSITION:
3217 depth = LLVMBuildLoad(builder,
3218 ctx->outputs[i][2], "");
3219 break;
3220 case TGSI_SEMANTIC_STENCIL:
3221 stencil = LLVMBuildLoad(builder,
3222 ctx->outputs[i][1], "");
3223 break;
3224 case TGSI_SEMANTIC_SAMPLEMASK:
3225 samplemask = LLVMBuildLoad(builder,
3226 ctx->outputs[i][0], "");
3227 break;
3228 default:
3229 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3230 semantic_name);
3231 }
3232 }
3233
3234 /* Fill the return structure. */
3235 ret = ctx->return_value;
3236
3237 /* Set SGPRs. */
3238 ret = LLVMBuildInsertValue(builder, ret,
3239 bitcast(bld_base, TGSI_TYPE_SIGNED,
3240 LLVMGetParam(ctx->main_fn,
3241 SI_PARAM_ALPHA_REF)),
3242 SI_SGPR_ALPHA_REF, "");
3243
3244 /* Set VGPRs */
3245 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3246 for (i = 0; i < ARRAY_SIZE(color); i++) {
3247 if (!color[i][0])
3248 continue;
3249
3250 for (j = 0; j < 4; j++)
3251 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3252 }
3253 if (depth)
3254 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3255 if (stencil)
3256 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3257 if (samplemask)
3258 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3259
3260 /* Add the input sample mask for smoothing at the end. */
3261 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3262 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3263 ret = LLVMBuildInsertValue(builder, ret,
3264 LLVMGetParam(ctx->main_fn,
3265 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3266
3267 ctx->return_value = ret;
3268 }
3269
3270 /**
3271 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3272 * buffer in number of elements and return it as an i32.
3273 */
3274 static LLVMValueRef get_buffer_size(
3275 struct lp_build_tgsi_context *bld_base,
3276 LLVMValueRef descriptor)
3277 {
3278 struct si_shader_context *ctx = si_shader_context(bld_base);
3279 struct gallivm_state *gallivm = bld_base->base.gallivm;
3280 LLVMBuilderRef builder = gallivm->builder;
3281 LLVMValueRef size =
3282 LLVMBuildExtractElement(builder, descriptor,
3283 lp_build_const_int32(gallivm, 2), "");
3284
3285 if (ctx->screen->b.chip_class >= VI) {
3286 /* On VI, the descriptor contains the size in bytes,
3287 * but TXQ must return the size in elements.
3288 * The stride is always non-zero for resources using TXQ.
3289 */
3290 LLVMValueRef stride =
3291 LLVMBuildExtractElement(builder, descriptor,
3292 lp_build_const_int32(gallivm, 1), "");
3293 stride = LLVMBuildLShr(builder, stride,
3294 lp_build_const_int32(gallivm, 16), "");
3295 stride = LLVMBuildAnd(builder, stride,
3296 lp_build_const_int32(gallivm, 0x3FFF), "");
3297
3298 size = LLVMBuildUDiv(builder, size, stride, "");
3299 }
3300
3301 return size;
3302 }
3303
3304 /**
3305 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3306 * intrinsic names).
3307 */
3308 static void build_type_name_for_intr(
3309 LLVMTypeRef type,
3310 char *buf, unsigned bufsize)
3311 {
3312 LLVMTypeRef elem_type = type;
3313
3314 assert(bufsize >= 8);
3315
3316 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3317 int ret = snprintf(buf, bufsize, "v%u",
3318 LLVMGetVectorSize(type));
3319 if (ret < 0) {
3320 char *type_name = LLVMPrintTypeToString(type);
3321 fprintf(stderr, "Error building type name for: %s\n",
3322 type_name);
3323 return;
3324 }
3325 elem_type = LLVMGetElementType(type);
3326 buf += ret;
3327 bufsize -= ret;
3328 }
3329 switch (LLVMGetTypeKind(elem_type)) {
3330 default: break;
3331 case LLVMIntegerTypeKind:
3332 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3333 break;
3334 case LLVMFloatTypeKind:
3335 snprintf(buf, bufsize, "f32");
3336 break;
3337 case LLVMDoubleTypeKind:
3338 snprintf(buf, bufsize, "f64");
3339 break;
3340 }
3341 }
3342
3343 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3344 struct lp_build_tgsi_context *bld_base,
3345 struct lp_build_emit_data *emit_data);
3346
3347 /* Prevent optimizations (at least of memory accesses) across the current
3348 * point in the program by emitting empty inline assembly that is marked as
3349 * having side effects.
3350 */
3351 #if 0 /* unused currently */
3352 static void emit_optimization_barrier(struct si_shader_context *ctx)
3353 {
3354 LLVMBuilderRef builder = ctx->gallivm.builder;
3355 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3356 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3357 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3358 }
3359 #endif
3360
3361 /* Combine these with & instead of |. */
3362 #define NOOP_WAITCNT 0xf7f
3363 #define LGKM_CNT 0x07f
3364 #define VM_CNT 0xf70
3365
3366 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3367 {
3368 struct gallivm_state *gallivm = &ctx->gallivm;
3369 LLVMBuilderRef builder = gallivm->builder;
3370 LLVMValueRef args[1] = {
3371 lp_build_const_int32(gallivm, simm16)
3372 };
3373 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3374 ctx->voidt, args, 1, 0);
3375 }
3376
3377 static void membar_emit(
3378 const struct lp_build_tgsi_action *action,
3379 struct lp_build_tgsi_context *bld_base,
3380 struct lp_build_emit_data *emit_data)
3381 {
3382 struct si_shader_context *ctx = si_shader_context(bld_base);
3383 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3384 unsigned flags = LLVMConstIntGetZExtValue(src0);
3385 unsigned waitcnt = NOOP_WAITCNT;
3386
3387 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3388 waitcnt &= VM_CNT & LGKM_CNT;
3389
3390 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3391 TGSI_MEMBAR_SHADER_BUFFER |
3392 TGSI_MEMBAR_SHADER_IMAGE))
3393 waitcnt &= VM_CNT;
3394
3395 if (flags & TGSI_MEMBAR_SHARED)
3396 waitcnt &= LGKM_CNT;
3397
3398 if (waitcnt != NOOP_WAITCNT)
3399 emit_waitcnt(ctx, waitcnt);
3400 }
3401
3402 static LLVMValueRef
3403 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3404 const struct tgsi_full_src_register *reg)
3405 {
3406 LLVMValueRef index;
3407 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3408 SI_PARAM_SHADER_BUFFERS);
3409
3410 if (!reg->Register.Indirect)
3411 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3412 else
3413 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3414 reg->Register.Index,
3415 SI_NUM_SHADER_BUFFERS);
3416
3417 return build_indexed_load_const(ctx, rsrc_ptr, index);
3418 }
3419
3420 static bool tgsi_is_array_sampler(unsigned target)
3421 {
3422 return target == TGSI_TEXTURE_1D_ARRAY ||
3423 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3424 target == TGSI_TEXTURE_2D_ARRAY ||
3425 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3426 target == TGSI_TEXTURE_CUBE_ARRAY ||
3427 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3428 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3429 }
3430
3431 static bool tgsi_is_array_image(unsigned target)
3432 {
3433 return target == TGSI_TEXTURE_3D ||
3434 target == TGSI_TEXTURE_CUBE ||
3435 target == TGSI_TEXTURE_1D_ARRAY ||
3436 target == TGSI_TEXTURE_2D_ARRAY ||
3437 target == TGSI_TEXTURE_CUBE_ARRAY ||
3438 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3439 }
3440
3441 /**
3442 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3443 *
3444 * At least on Tonga, executing image stores on images with DCC enabled and
3445 * non-trivial can eventually lead to lockups. This can occur when an
3446 * application binds an image as read-only but then uses a shader that writes
3447 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3448 * program termination) in this case, but it doesn't cost much to be a bit
3449 * nicer: disabling DCC in the shader still leads to undefined results but
3450 * avoids the lockup.
3451 */
3452 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3453 LLVMValueRef rsrc)
3454 {
3455 if (ctx->screen->b.chip_class <= CIK) {
3456 return rsrc;
3457 } else {
3458 LLVMBuilderRef builder = ctx->gallivm.builder;
3459 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3460 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3461 LLVMValueRef tmp;
3462
3463 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3464 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3465 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3466 }
3467 }
3468
3469 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3470 {
3471 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3472 CONST_ADDR_SPACE);
3473 }
3474
3475 /**
3476 * Load the resource descriptor for \p image.
3477 */
3478 static void
3479 image_fetch_rsrc(
3480 struct lp_build_tgsi_context *bld_base,
3481 const struct tgsi_full_src_register *image,
3482 bool is_store, unsigned target,
3483 LLVMValueRef *rsrc)
3484 {
3485 struct si_shader_context *ctx = si_shader_context(bld_base);
3486 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3487 SI_PARAM_IMAGES);
3488 LLVMValueRef index, tmp;
3489 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3490
3491 assert(image->Register.File == TGSI_FILE_IMAGE);
3492
3493 if (!image->Register.Indirect) {
3494 const struct tgsi_shader_info *info = bld_base->info;
3495
3496 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3497
3498 if (info->images_writemask & (1 << image->Register.Index) &&
3499 target != TGSI_TEXTURE_BUFFER)
3500 dcc_off = true;
3501 } else {
3502 /* From the GL_ARB_shader_image_load_store extension spec:
3503 *
3504 * If a shader performs an image load, store, or atomic
3505 * operation using an image variable declared as an array,
3506 * and if the index used to select an individual element is
3507 * negative or greater than or equal to the size of the
3508 * array, the results of the operation are undefined but may
3509 * not lead to termination.
3510 */
3511 index = get_bounded_indirect_index(ctx, &image->Indirect,
3512 image->Register.Index,
3513 SI_NUM_IMAGES);
3514 }
3515
3516 if (target == TGSI_TEXTURE_BUFFER) {
3517 LLVMBuilderRef builder = ctx->gallivm.builder;
3518
3519 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3520 const_array(ctx->v4i32, 0), "");
3521 index = LLVMBuildMul(builder, index,
3522 LLVMConstInt(ctx->i32, 2, 0), "");
3523 index = LLVMBuildAdd(builder, index,
3524 LLVMConstInt(ctx->i32, 1, 0), "");
3525 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3526 return;
3527 }
3528
3529 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3530 if (dcc_off)
3531 tmp = force_dcc_off(ctx, tmp);
3532 *rsrc = tmp;
3533 }
3534
3535 static LLVMValueRef image_fetch_coords(
3536 struct lp_build_tgsi_context *bld_base,
3537 const struct tgsi_full_instruction *inst,
3538 unsigned src)
3539 {
3540 struct gallivm_state *gallivm = bld_base->base.gallivm;
3541 LLVMBuilderRef builder = gallivm->builder;
3542 unsigned target = inst->Memory.Texture;
3543 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3544 LLVMValueRef coords[4];
3545 LLVMValueRef tmp;
3546 int chan;
3547
3548 for (chan = 0; chan < num_coords; ++chan) {
3549 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3550 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3551 coords[chan] = tmp;
3552 }
3553
3554 if (num_coords == 1)
3555 return coords[0];
3556
3557 if (num_coords == 3) {
3558 /* LLVM has difficulties lowering 3-element vectors. */
3559 coords[3] = bld_base->uint_bld.undef;
3560 num_coords = 4;
3561 }
3562
3563 return lp_build_gather_values(gallivm, coords, num_coords);
3564 }
3565
3566 /**
3567 * Append the extra mode bits that are used by image load and store.
3568 */
3569 static void image_append_args(
3570 struct si_shader_context *ctx,
3571 struct lp_build_emit_data * emit_data,
3572 unsigned target,
3573 bool atomic,
3574 bool force_glc)
3575 {
3576 const struct tgsi_full_instruction *inst = emit_data->inst;
3577 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3578 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3579 LLVMValueRef r128 = i1false;
3580 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3581 LLVMValueRef glc =
3582 force_glc ||
3583 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3584 i1true : i1false;
3585 LLVMValueRef slc = i1false;
3586 LLVMValueRef lwe = i1false;
3587
3588 if (atomic || (HAVE_LLVM <= 0x0309)) {
3589 emit_data->args[emit_data->arg_count++] = r128;
3590 emit_data->args[emit_data->arg_count++] = da;
3591 if (!atomic) {
3592 emit_data->args[emit_data->arg_count++] = glc;
3593 }
3594 emit_data->args[emit_data->arg_count++] = slc;
3595 return;
3596 }
3597
3598 /* HAVE_LLVM >= 0x0400 */
3599 emit_data->args[emit_data->arg_count++] = glc;
3600 emit_data->args[emit_data->arg_count++] = slc;
3601 emit_data->args[emit_data->arg_count++] = lwe;
3602 emit_data->args[emit_data->arg_count++] = da;
3603 }
3604
3605 /**
3606 * Append the resource and indexing arguments for buffer intrinsics.
3607 *
3608 * \param rsrc the v4i32 buffer resource
3609 * \param index index into the buffer (stride-based)
3610 * \param offset byte offset into the buffer
3611 */
3612 static void buffer_append_args(
3613 struct si_shader_context *ctx,
3614 struct lp_build_emit_data *emit_data,
3615 LLVMValueRef rsrc,
3616 LLVMValueRef index,
3617 LLVMValueRef offset,
3618 bool atomic,
3619 bool force_glc)
3620 {
3621 const struct tgsi_full_instruction *inst = emit_data->inst;
3622 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3623 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3624
3625 emit_data->args[emit_data->arg_count++] = rsrc;
3626 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3627 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3628 if (!atomic) {
3629 emit_data->args[emit_data->arg_count++] =
3630 force_glc ||
3631 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3632 i1true : i1false; /* glc */
3633 }
3634 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3635 }
3636
3637 static void load_fetch_args(
3638 struct lp_build_tgsi_context * bld_base,
3639 struct lp_build_emit_data * emit_data)
3640 {
3641 struct si_shader_context *ctx = si_shader_context(bld_base);
3642 struct gallivm_state *gallivm = bld_base->base.gallivm;
3643 const struct tgsi_full_instruction * inst = emit_data->inst;
3644 unsigned target = inst->Memory.Texture;
3645 LLVMValueRef rsrc;
3646
3647 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3648
3649 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3650 LLVMBuilderRef builder = gallivm->builder;
3651 LLVMValueRef offset;
3652 LLVMValueRef tmp;
3653
3654 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3655
3656 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3657 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3658
3659 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3660 offset, false, false);
3661 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3662 LLVMValueRef coords;
3663
3664 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3665 coords = image_fetch_coords(bld_base, inst, 1);
3666
3667 if (target == TGSI_TEXTURE_BUFFER) {
3668 buffer_append_args(ctx, emit_data, rsrc, coords,
3669 bld_base->uint_bld.zero, false, false);
3670 } else {
3671 emit_data->args[0] = coords;
3672 emit_data->args[1] = rsrc;
3673 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3674 emit_data->arg_count = 3;
3675
3676 image_append_args(ctx, emit_data, target, false, false);
3677 }
3678 }
3679 }
3680
3681 static void load_emit_buffer(struct si_shader_context *ctx,
3682 struct lp_build_emit_data *emit_data)
3683 {
3684 const struct tgsi_full_instruction *inst = emit_data->inst;
3685 struct gallivm_state *gallivm = &ctx->gallivm;
3686 LLVMBuilderRef builder = gallivm->builder;
3687 uint writemask = inst->Dst[0].Register.WriteMask;
3688 uint count = util_last_bit(writemask);
3689 const char *intrinsic_name;
3690 LLVMTypeRef dst_type;
3691
3692 switch (count) {
3693 case 1:
3694 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3695 dst_type = ctx->f32;
3696 break;
3697 case 2:
3698 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3699 dst_type = LLVMVectorType(ctx->f32, 2);
3700 break;
3701 default: // 3 & 4
3702 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3703 dst_type = ctx->v4f32;
3704 count = 4;
3705 }
3706
3707 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3708 builder, intrinsic_name, dst_type,
3709 emit_data->args, emit_data->arg_count,
3710 LP_FUNC_ATTR_READONLY);
3711 }
3712
3713 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3714 const struct tgsi_full_instruction *inst,
3715 LLVMTypeRef type, int arg)
3716 {
3717 struct gallivm_state *gallivm = &ctx->gallivm;
3718 LLVMBuilderRef builder = gallivm->builder;
3719 LLVMValueRef offset, ptr;
3720 int addr_space;
3721
3722 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3723 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3724
3725 ptr = ctx->shared_memory;
3726 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3727 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3728 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3729
3730 return ptr;
3731 }
3732
3733 static void load_emit_memory(
3734 struct si_shader_context *ctx,
3735 struct lp_build_emit_data *emit_data)
3736 {
3737 const struct tgsi_full_instruction *inst = emit_data->inst;
3738 struct lp_build_context *base = &ctx->bld_base.base;
3739 struct gallivm_state *gallivm = &ctx->gallivm;
3740 LLVMBuilderRef builder = gallivm->builder;
3741 unsigned writemask = inst->Dst[0].Register.WriteMask;
3742 LLVMValueRef channels[4], ptr, derived_ptr, index;
3743 int chan;
3744
3745 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3746
3747 for (chan = 0; chan < 4; ++chan) {
3748 if (!(writemask & (1 << chan))) {
3749 channels[chan] = LLVMGetUndef(base->elem_type);
3750 continue;
3751 }
3752
3753 index = lp_build_const_int32(gallivm, chan);
3754 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3755 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3756 }
3757 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3758 }
3759
3760 static void get_image_intr_name(const char *base_name,
3761 LLVMTypeRef data_type,
3762 LLVMTypeRef coords_type,
3763 LLVMTypeRef rsrc_type,
3764 char *out_name, unsigned out_len)
3765 {
3766 char coords_type_name[8];
3767
3768 build_type_name_for_intr(coords_type, coords_type_name,
3769 sizeof(coords_type_name));
3770
3771 if (HAVE_LLVM <= 0x0309) {
3772 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3773 } else {
3774 char data_type_name[8];
3775 char rsrc_type_name[8];
3776
3777 build_type_name_for_intr(data_type, data_type_name,
3778 sizeof(data_type_name));
3779 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3780 sizeof(rsrc_type_name));
3781 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3782 data_type_name, coords_type_name, rsrc_type_name);
3783 }
3784 }
3785
3786 static void load_emit(
3787 const struct lp_build_tgsi_action *action,
3788 struct lp_build_tgsi_context *bld_base,
3789 struct lp_build_emit_data *emit_data)
3790 {
3791 struct si_shader_context *ctx = si_shader_context(bld_base);
3792 struct gallivm_state *gallivm = bld_base->base.gallivm;
3793 LLVMBuilderRef builder = gallivm->builder;
3794 const struct tgsi_full_instruction * inst = emit_data->inst;
3795 char intrinsic_name[64];
3796
3797 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3798 load_emit_memory(ctx, emit_data);
3799 return;
3800 }
3801
3802 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3803 emit_waitcnt(ctx, VM_CNT);
3804
3805 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3806 load_emit_buffer(ctx, emit_data);
3807 return;
3808 }
3809
3810 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3811 emit_data->output[emit_data->chan] =
3812 lp_build_intrinsic(
3813 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3814 emit_data->args, emit_data->arg_count,
3815 LP_FUNC_ATTR_READONLY);
3816 } else {
3817 get_image_intr_name("llvm.amdgcn.image.load",
3818 emit_data->dst_type, /* vdata */
3819 LLVMTypeOf(emit_data->args[0]), /* coords */
3820 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3821 intrinsic_name, sizeof(intrinsic_name));
3822
3823 emit_data->output[emit_data->chan] =
3824 lp_build_intrinsic(
3825 builder, intrinsic_name, emit_data->dst_type,
3826 emit_data->args, emit_data->arg_count,
3827 LP_FUNC_ATTR_READONLY);
3828 }
3829 }
3830
3831 static void store_fetch_args(
3832 struct lp_build_tgsi_context * bld_base,
3833 struct lp_build_emit_data * emit_data)
3834 {
3835 struct si_shader_context *ctx = si_shader_context(bld_base);
3836 struct gallivm_state *gallivm = bld_base->base.gallivm;
3837 LLVMBuilderRef builder = gallivm->builder;
3838 const struct tgsi_full_instruction * inst = emit_data->inst;
3839 struct tgsi_full_src_register memory;
3840 LLVMValueRef chans[4];
3841 LLVMValueRef data;
3842 LLVMValueRef rsrc;
3843 unsigned chan;
3844
3845 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3846
3847 for (chan = 0; chan < 4; ++chan) {
3848 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3849 }
3850 data = lp_build_gather_values(gallivm, chans, 4);
3851
3852 emit_data->args[emit_data->arg_count++] = data;
3853
3854 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3855
3856 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3857 LLVMValueRef offset;
3858 LLVMValueRef tmp;
3859
3860 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3861
3862 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3863 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3864
3865 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3866 offset, false, false);
3867 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3868 unsigned target = inst->Memory.Texture;
3869 LLVMValueRef coords;
3870
3871 /* 8bit/16bit TC L1 write corruption bug on SI.
3872 * All store opcodes not aligned to a dword are affected.
3873 *
3874 * The only way to get unaligned stores in radeonsi is through
3875 * shader images.
3876 */
3877 bool force_glc = ctx->screen->b.chip_class == SI;
3878
3879 coords = image_fetch_coords(bld_base, inst, 0);
3880
3881 if (target == TGSI_TEXTURE_BUFFER) {
3882 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3883 buffer_append_args(ctx, emit_data, rsrc, coords,
3884 bld_base->uint_bld.zero, false, force_glc);
3885 } else {
3886 emit_data->args[1] = coords;
3887 image_fetch_rsrc(bld_base, &memory, true, target,
3888 &emit_data->args[2]);
3889 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3890 emit_data->arg_count = 4;
3891
3892 image_append_args(ctx, emit_data, target, false, force_glc);
3893 }
3894 }
3895 }
3896
3897 static void store_emit_buffer(
3898 struct si_shader_context *ctx,
3899 struct lp_build_emit_data *emit_data)
3900 {
3901 const struct tgsi_full_instruction *inst = emit_data->inst;
3902 struct gallivm_state *gallivm = &ctx->gallivm;
3903 LLVMBuilderRef builder = gallivm->builder;
3904 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
3905 LLVMValueRef base_data = emit_data->args[0];
3906 LLVMValueRef base_offset = emit_data->args[3];
3907 unsigned writemask = inst->Dst[0].Register.WriteMask;
3908
3909 while (writemask) {
3910 int start, count;
3911 const char *intrinsic_name;
3912 LLVMValueRef data;
3913 LLVMValueRef offset;
3914 LLVMValueRef tmp;
3915
3916 u_bit_scan_consecutive_range(&writemask, &start, &count);
3917
3918 /* Due to an LLVM limitation, split 3-element writes
3919 * into a 2-element and a 1-element write. */
3920 if (count == 3) {
3921 writemask |= 1 << (start + 2);
3922 count = 2;
3923 }
3924
3925 if (count == 4) {
3926 data = base_data;
3927 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3928 } else if (count == 2) {
3929 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3930
3931 tmp = LLVMBuildExtractElement(
3932 builder, base_data,
3933 lp_build_const_int32(gallivm, start), "");
3934 data = LLVMBuildInsertElement(
3935 builder, LLVMGetUndef(v2f32), tmp,
3936 uint_bld->zero, "");
3937
3938 tmp = LLVMBuildExtractElement(
3939 builder, base_data,
3940 lp_build_const_int32(gallivm, start + 1), "");
3941 data = LLVMBuildInsertElement(
3942 builder, data, tmp, uint_bld->one, "");
3943
3944 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3945 } else {
3946 assert(count == 1);
3947 data = LLVMBuildExtractElement(
3948 builder, base_data,
3949 lp_build_const_int32(gallivm, start), "");
3950 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3951 }
3952
3953 offset = base_offset;
3954 if (start != 0) {
3955 offset = LLVMBuildAdd(
3956 builder, offset,
3957 lp_build_const_int32(gallivm, start * 4), "");
3958 }
3959
3960 emit_data->args[0] = data;
3961 emit_data->args[3] = offset;
3962
3963 lp_build_intrinsic(
3964 builder, intrinsic_name, emit_data->dst_type,
3965 emit_data->args, emit_data->arg_count, 0);
3966 }
3967 }
3968
3969 static void store_emit_memory(
3970 struct si_shader_context *ctx,
3971 struct lp_build_emit_data *emit_data)
3972 {
3973 const struct tgsi_full_instruction *inst = emit_data->inst;
3974 struct gallivm_state *gallivm = &ctx->gallivm;
3975 struct lp_build_context *base = &ctx->bld_base.base;
3976 LLVMBuilderRef builder = gallivm->builder;
3977 unsigned writemask = inst->Dst[0].Register.WriteMask;
3978 LLVMValueRef ptr, derived_ptr, data, index;
3979 int chan;
3980
3981 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3982
3983 for (chan = 0; chan < 4; ++chan) {
3984 if (!(writemask & (1 << chan))) {
3985 continue;
3986 }
3987 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3988 index = lp_build_const_int32(gallivm, chan);
3989 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3990 LLVMBuildStore(builder, data, derived_ptr);
3991 }
3992 }
3993
3994 static void store_emit(
3995 const struct lp_build_tgsi_action *action,
3996 struct lp_build_tgsi_context *bld_base,
3997 struct lp_build_emit_data *emit_data)
3998 {
3999 struct si_shader_context *ctx = si_shader_context(bld_base);
4000 struct gallivm_state *gallivm = bld_base->base.gallivm;
4001 LLVMBuilderRef builder = gallivm->builder;
4002 const struct tgsi_full_instruction * inst = emit_data->inst;
4003 unsigned target = inst->Memory.Texture;
4004 char intrinsic_name[64];
4005
4006 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
4007 store_emit_memory(ctx, emit_data);
4008 return;
4009 }
4010
4011 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
4012 emit_waitcnt(ctx, VM_CNT);
4013
4014 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
4015 store_emit_buffer(ctx, emit_data);
4016 return;
4017 }
4018
4019 if (target == TGSI_TEXTURE_BUFFER) {
4020 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4021 builder, "llvm.amdgcn.buffer.store.format.v4f32",
4022 emit_data->dst_type, emit_data->args,
4023 emit_data->arg_count, 0);
4024 } else {
4025 get_image_intr_name("llvm.amdgcn.image.store",
4026 LLVMTypeOf(emit_data->args[0]), /* vdata */
4027 LLVMTypeOf(emit_data->args[1]), /* coords */
4028 LLVMTypeOf(emit_data->args[2]), /* rsrc */
4029 intrinsic_name, sizeof(intrinsic_name));
4030
4031 emit_data->output[emit_data->chan] =
4032 lp_build_intrinsic(
4033 builder, intrinsic_name, emit_data->dst_type,
4034 emit_data->args, emit_data->arg_count, 0);
4035 }
4036 }
4037
4038 static void atomic_fetch_args(
4039 struct lp_build_tgsi_context * bld_base,
4040 struct lp_build_emit_data * emit_data)
4041 {
4042 struct si_shader_context *ctx = si_shader_context(bld_base);
4043 struct gallivm_state *gallivm = bld_base->base.gallivm;
4044 LLVMBuilderRef builder = gallivm->builder;
4045 const struct tgsi_full_instruction * inst = emit_data->inst;
4046 LLVMValueRef data1, data2;
4047 LLVMValueRef rsrc;
4048 LLVMValueRef tmp;
4049
4050 emit_data->dst_type = bld_base->base.elem_type;
4051
4052 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4053 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4054
4055 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4056 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4057 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4058 }
4059
4060 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4061 * of arguments, which is reversed relative to TGSI (and GLSL)
4062 */
4063 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4064 emit_data->args[emit_data->arg_count++] = data2;
4065 emit_data->args[emit_data->arg_count++] = data1;
4066
4067 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4068 LLVMValueRef offset;
4069
4070 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4071
4072 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4073 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4074
4075 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4076 offset, true, false);
4077 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4078 unsigned target = inst->Memory.Texture;
4079 LLVMValueRef coords;
4080
4081 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
4082 coords = image_fetch_coords(bld_base, inst, 1);
4083
4084 if (target == TGSI_TEXTURE_BUFFER) {
4085 buffer_append_args(ctx, emit_data, rsrc, coords,
4086 bld_base->uint_bld.zero, true, false);
4087 } else {
4088 emit_data->args[emit_data->arg_count++] = coords;
4089 emit_data->args[emit_data->arg_count++] = rsrc;
4090
4091 image_append_args(ctx, emit_data, target, true, false);
4092 }
4093 }
4094 }
4095
4096 static void atomic_emit_memory(struct si_shader_context *ctx,
4097 struct lp_build_emit_data *emit_data) {
4098 struct gallivm_state *gallivm = &ctx->gallivm;
4099 LLVMBuilderRef builder = gallivm->builder;
4100 const struct tgsi_full_instruction * inst = emit_data->inst;
4101 LLVMValueRef ptr, result, arg;
4102
4103 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4104
4105 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
4106 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4107
4108 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4109 LLVMValueRef new_data;
4110 new_data = lp_build_emit_fetch(&ctx->bld_base,
4111 inst, 3, 0);
4112
4113 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4114
4115 #if HAVE_LLVM >= 0x309
4116 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4117 LLVMAtomicOrderingSequentiallyConsistent,
4118 LLVMAtomicOrderingSequentiallyConsistent,
4119 false);
4120 #endif
4121
4122 result = LLVMBuildExtractValue(builder, result, 0, "");
4123 } else {
4124 LLVMAtomicRMWBinOp op;
4125
4126 switch(inst->Instruction.Opcode) {
4127 case TGSI_OPCODE_ATOMUADD:
4128 op = LLVMAtomicRMWBinOpAdd;
4129 break;
4130 case TGSI_OPCODE_ATOMXCHG:
4131 op = LLVMAtomicRMWBinOpXchg;
4132 break;
4133 case TGSI_OPCODE_ATOMAND:
4134 op = LLVMAtomicRMWBinOpAnd;
4135 break;
4136 case TGSI_OPCODE_ATOMOR:
4137 op = LLVMAtomicRMWBinOpOr;
4138 break;
4139 case TGSI_OPCODE_ATOMXOR:
4140 op = LLVMAtomicRMWBinOpXor;
4141 break;
4142 case TGSI_OPCODE_ATOMUMIN:
4143 op = LLVMAtomicRMWBinOpUMin;
4144 break;
4145 case TGSI_OPCODE_ATOMUMAX:
4146 op = LLVMAtomicRMWBinOpUMax;
4147 break;
4148 case TGSI_OPCODE_ATOMIMIN:
4149 op = LLVMAtomicRMWBinOpMin;
4150 break;
4151 case TGSI_OPCODE_ATOMIMAX:
4152 op = LLVMAtomicRMWBinOpMax;
4153 break;
4154 default:
4155 unreachable("unknown atomic opcode");
4156 }
4157
4158 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4159 LLVMAtomicOrderingSequentiallyConsistent,
4160 false);
4161 }
4162 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4163 }
4164
4165 static void atomic_emit(
4166 const struct lp_build_tgsi_action *action,
4167 struct lp_build_tgsi_context *bld_base,
4168 struct lp_build_emit_data *emit_data)
4169 {
4170 struct si_shader_context *ctx = si_shader_context(bld_base);
4171 struct gallivm_state *gallivm = bld_base->base.gallivm;
4172 LLVMBuilderRef builder = gallivm->builder;
4173 const struct tgsi_full_instruction * inst = emit_data->inst;
4174 char intrinsic_name[40];
4175 LLVMValueRef tmp;
4176
4177 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4178 atomic_emit_memory(ctx, emit_data);
4179 return;
4180 }
4181
4182 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4183 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4184 snprintf(intrinsic_name, sizeof(intrinsic_name),
4185 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4186 } else {
4187 LLVMValueRef coords;
4188 char coords_type[8];
4189
4190 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4191 coords = emit_data->args[2];
4192 else
4193 coords = emit_data->args[1];
4194
4195 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4196 snprintf(intrinsic_name, sizeof(intrinsic_name),
4197 "llvm.amdgcn.image.atomic.%s.%s",
4198 action->intr_name, coords_type);
4199 }
4200
4201 tmp = lp_build_intrinsic(
4202 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4203 emit_data->args, emit_data->arg_count, 0);
4204 emit_data->output[emit_data->chan] =
4205 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4206 }
4207
4208 static void resq_fetch_args(
4209 struct lp_build_tgsi_context * bld_base,
4210 struct lp_build_emit_data * emit_data)
4211 {
4212 struct si_shader_context *ctx = si_shader_context(bld_base);
4213 struct gallivm_state *gallivm = bld_base->base.gallivm;
4214 const struct tgsi_full_instruction *inst = emit_data->inst;
4215 const struct tgsi_full_src_register *reg = &inst->Src[0];
4216
4217 emit_data->dst_type = ctx->v4i32;
4218
4219 if (reg->Register.File == TGSI_FILE_BUFFER) {
4220 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4221 emit_data->arg_count = 1;
4222 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4223 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4224 &emit_data->args[0]);
4225 emit_data->arg_count = 1;
4226 } else {
4227 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4228 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4229 &emit_data->args[1]);
4230 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4231 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4232 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4233 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4234 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4235 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4236 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4237 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4238 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4239 emit_data->arg_count = 10;
4240 }
4241 }
4242
4243 static void resq_emit(
4244 const struct lp_build_tgsi_action *action,
4245 struct lp_build_tgsi_context *bld_base,
4246 struct lp_build_emit_data *emit_data)
4247 {
4248 struct gallivm_state *gallivm = bld_base->base.gallivm;
4249 LLVMBuilderRef builder = gallivm->builder;
4250 const struct tgsi_full_instruction *inst = emit_data->inst;
4251 LLVMValueRef out;
4252
4253 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4254 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4255 lp_build_const_int32(gallivm, 2), "");
4256 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4257 out = get_buffer_size(bld_base, emit_data->args[0]);
4258 } else {
4259 out = lp_build_intrinsic(
4260 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4261 emit_data->args, emit_data->arg_count,
4262 LP_FUNC_ATTR_READNONE);
4263
4264 /* Divide the number of layers by 6 to get the number of cubes. */
4265 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4266 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4267 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4268
4269 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4270 z = LLVMBuildSDiv(builder, z, imm6, "");
4271 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4272 }
4273 }
4274
4275 emit_data->output[emit_data->chan] = out;
4276 }
4277
4278 static void set_tex_fetch_args(struct si_shader_context *ctx,
4279 struct lp_build_emit_data *emit_data,
4280 unsigned opcode, unsigned target,
4281 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4282 LLVMValueRef *param, unsigned count,
4283 unsigned dmask)
4284 {
4285 struct gallivm_state *gallivm = &ctx->gallivm;
4286 unsigned num_args;
4287 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4288
4289 /* Pad to power of two vector */
4290 while (count < util_next_power_of_two(count))
4291 param[count++] = LLVMGetUndef(ctx->i32);
4292
4293 /* Texture coordinates. */
4294 if (count > 1)
4295 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4296 else
4297 emit_data->args[0] = param[0];
4298
4299 /* Resource. */
4300 emit_data->args[1] = res_ptr;
4301 num_args = 2;
4302
4303 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4304 emit_data->dst_type = ctx->v4i32;
4305 else {
4306 emit_data->dst_type = ctx->v4f32;
4307
4308 emit_data->args[num_args++] = samp_ptr;
4309 }
4310
4311 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4312 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4313 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4314 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4315 tgsi_is_array_sampler(target)); /* da */
4316 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4317 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4318 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4319 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4320
4321 emit_data->arg_count = num_args;
4322 }
4323
4324 static const struct lp_build_tgsi_action tex_action;
4325
4326 enum desc_type {
4327 DESC_IMAGE,
4328 DESC_BUFFER,
4329 DESC_FMASK,
4330 DESC_SAMPLER,
4331 };
4332
4333 /**
4334 * Load an image view, fmask view. or sampler state descriptor.
4335 */
4336 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4337 LLVMValueRef list, LLVMValueRef index,
4338 enum desc_type type)
4339 {
4340 struct gallivm_state *gallivm = &ctx->gallivm;
4341 LLVMBuilderRef builder = gallivm->builder;
4342
4343 switch (type) {
4344 case DESC_IMAGE:
4345 /* The image is at [0:7]. */
4346 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4347 break;
4348 case DESC_BUFFER:
4349 /* The buffer is in [4:7]. */
4350 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4351 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4352 list = LLVMBuildPointerCast(builder, list,
4353 const_array(ctx->v4i32, 0), "");
4354 break;
4355 case DESC_FMASK:
4356 /* The FMASK is at [8:15]. */
4357 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4358 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4359 break;
4360 case DESC_SAMPLER:
4361 /* The sampler state is at [12:15]. */
4362 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4363 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4364 list = LLVMBuildPointerCast(builder, list,
4365 const_array(ctx->v4i32, 0), "");
4366 break;
4367 }
4368
4369 return build_indexed_load_const(ctx, list, index);
4370 }
4371
4372 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4373 LLVMValueRef index, enum desc_type type)
4374 {
4375 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4376 SI_PARAM_SAMPLERS);
4377
4378 return load_sampler_desc_custom(ctx, list, index, type);
4379 }
4380
4381 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4382 *
4383 * SI-CI:
4384 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4385 * filtering manually. The driver sets img7 to a mask clearing
4386 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4387 * s_and_b32 samp0, samp0, img7
4388 *
4389 * VI:
4390 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4391 */
4392 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4393 LLVMValueRef res, LLVMValueRef samp)
4394 {
4395 LLVMBuilderRef builder = ctx->gallivm.builder;
4396 LLVMValueRef img7, samp0;
4397
4398 if (ctx->screen->b.chip_class >= VI)
4399 return samp;
4400
4401 img7 = LLVMBuildExtractElement(builder, res,
4402 LLVMConstInt(ctx->i32, 7, 0), "");
4403 samp0 = LLVMBuildExtractElement(builder, samp,
4404 LLVMConstInt(ctx->i32, 0, 0), "");
4405 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4406 return LLVMBuildInsertElement(builder, samp, samp0,
4407 LLVMConstInt(ctx->i32, 0, 0), "");
4408 }
4409
4410 static void tex_fetch_ptrs(
4411 struct lp_build_tgsi_context *bld_base,
4412 struct lp_build_emit_data *emit_data,
4413 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4414 {
4415 struct si_shader_context *ctx = si_shader_context(bld_base);
4416 const struct tgsi_full_instruction *inst = emit_data->inst;
4417 unsigned target = inst->Texture.Texture;
4418 unsigned sampler_src;
4419 unsigned sampler_index;
4420 LLVMValueRef index;
4421
4422 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4423 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4424
4425 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4426 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4427
4428 index = get_bounded_indirect_index(ctx,
4429 &reg->Indirect,
4430 reg->Register.Index,
4431 SI_NUM_SAMPLERS);
4432 } else {
4433 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4434 }
4435
4436 if (target == TGSI_TEXTURE_BUFFER)
4437 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4438 else
4439 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4440
4441 if (samp_ptr)
4442 *samp_ptr = NULL;
4443 if (fmask_ptr)
4444 *fmask_ptr = NULL;
4445
4446 if (target == TGSI_TEXTURE_2D_MSAA ||
4447 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4448 if (fmask_ptr)
4449 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4450 } else if (target != TGSI_TEXTURE_BUFFER) {
4451 if (samp_ptr) {
4452 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4453 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4454 }
4455 }
4456 }
4457
4458 static void txq_fetch_args(
4459 struct lp_build_tgsi_context *bld_base,
4460 struct lp_build_emit_data *emit_data)
4461 {
4462 struct si_shader_context *ctx = si_shader_context(bld_base);
4463 const struct tgsi_full_instruction *inst = emit_data->inst;
4464 unsigned target = inst->Texture.Texture;
4465 LLVMValueRef res_ptr;
4466 LLVMValueRef address;
4467
4468 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4469
4470 if (target == TGSI_TEXTURE_BUFFER) {
4471 /* Read the size from the buffer descriptor directly. */
4472 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4473 return;
4474 }
4475
4476 /* Textures - set the mip level. */
4477 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4478
4479 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4480 NULL, &address, 1, 0xf);
4481 }
4482
4483 static void txq_emit(const struct lp_build_tgsi_action *action,
4484 struct lp_build_tgsi_context *bld_base,
4485 struct lp_build_emit_data *emit_data)
4486 {
4487 struct lp_build_context *base = &bld_base->base;
4488 unsigned target = emit_data->inst->Texture.Texture;
4489
4490 if (target == TGSI_TEXTURE_BUFFER) {
4491 /* Just return the buffer size. */
4492 emit_data->output[emit_data->chan] = emit_data->args[0];
4493 return;
4494 }
4495
4496 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4497 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4498 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4499 LP_FUNC_ATTR_READNONE);
4500
4501 /* Divide the number of layers by 6 to get the number of cubes. */
4502 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4503 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4504 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4505 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4506 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4507
4508 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4509 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4510 z = LLVMBuildSDiv(builder, z, six, "");
4511
4512 emit_data->output[emit_data->chan] =
4513 LLVMBuildInsertElement(builder, v4, z, two, "");
4514 }
4515 }
4516
4517 static void tex_fetch_args(
4518 struct lp_build_tgsi_context *bld_base,
4519 struct lp_build_emit_data *emit_data)
4520 {
4521 struct si_shader_context *ctx = si_shader_context(bld_base);
4522 struct gallivm_state *gallivm = bld_base->base.gallivm;
4523 const struct tgsi_full_instruction *inst = emit_data->inst;
4524 unsigned opcode = inst->Instruction.Opcode;
4525 unsigned target = inst->Texture.Texture;
4526 LLVMValueRef coords[5], derivs[6];
4527 LLVMValueRef address[16];
4528 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4529 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4530 unsigned count = 0;
4531 unsigned chan;
4532 unsigned num_deriv_channels = 0;
4533 bool has_offset = inst->Texture.NumOffsets > 0;
4534 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4535 unsigned dmask = 0xf;
4536
4537 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4538
4539 if (target == TGSI_TEXTURE_BUFFER) {
4540 emit_data->dst_type = ctx->v4f32;
4541 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4542 ctx->v16i8, "");
4543 emit_data->args[1] = bld_base->uint_bld.zero;
4544 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4545 emit_data->arg_count = 3;
4546 return;
4547 }
4548
4549 /* Fetch and project texture coordinates */
4550 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4551 for (chan = 0; chan < 3; chan++ ) {
4552 coords[chan] = lp_build_emit_fetch(bld_base,
4553 emit_data->inst, 0,
4554 chan);
4555 if (opcode == TGSI_OPCODE_TXP)
4556 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4557 TGSI_OPCODE_DIV,
4558 coords[chan],
4559 coords[3]);
4560 }
4561
4562 if (opcode == TGSI_OPCODE_TXP)
4563 coords[3] = bld_base->base.one;
4564
4565 /* Pack offsets. */
4566 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4567 /* The offsets are six-bit signed integers packed like this:
4568 * X=[5:0], Y=[13:8], and Z=[21:16].
4569 */
4570 LLVMValueRef offset[3], pack;
4571
4572 assert(inst->Texture.NumOffsets == 1);
4573
4574 for (chan = 0; chan < 3; chan++) {
4575 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4576 emit_data->inst, 0, chan);
4577 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4578 lp_build_const_int32(gallivm, 0x3f), "");
4579 if (chan)
4580 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4581 lp_build_const_int32(gallivm, chan*8), "");
4582 }
4583
4584 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4585 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4586 address[count++] = pack;
4587 }
4588
4589 /* Pack LOD bias value */
4590 if (opcode == TGSI_OPCODE_TXB)
4591 address[count++] = coords[3];
4592 if (opcode == TGSI_OPCODE_TXB2)
4593 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4594
4595 /* Pack depth comparison value */
4596 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4597 LLVMValueRef z;
4598
4599 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4600 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4601 } else {
4602 assert(ref_pos >= 0);
4603 z = coords[ref_pos];
4604 }
4605
4606 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4607 * so the depth comparison value isn't clamped for Z16 and
4608 * Z24 anymore. Do it manually here.
4609 *
4610 * It's unnecessary if the original texture format was
4611 * Z32_FLOAT, but we don't know that here.
4612 */
4613 if (ctx->screen->b.chip_class == VI)
4614 z = si_llvm_saturate(bld_base, z);
4615
4616 address[count++] = z;
4617 }
4618
4619 /* Pack user derivatives */
4620 if (opcode == TGSI_OPCODE_TXD) {
4621 int param, num_src_deriv_channels;
4622
4623 switch (target) {
4624 case TGSI_TEXTURE_3D:
4625 num_src_deriv_channels = 3;
4626 num_deriv_channels = 3;
4627 break;
4628 case TGSI_TEXTURE_2D:
4629 case TGSI_TEXTURE_SHADOW2D:
4630 case TGSI_TEXTURE_RECT:
4631 case TGSI_TEXTURE_SHADOWRECT:
4632 case TGSI_TEXTURE_2D_ARRAY:
4633 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4634 num_src_deriv_channels = 2;
4635 num_deriv_channels = 2;
4636 break;
4637 case TGSI_TEXTURE_CUBE:
4638 case TGSI_TEXTURE_SHADOWCUBE:
4639 case TGSI_TEXTURE_CUBE_ARRAY:
4640 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4641 /* Cube derivatives will be converted to 2D. */
4642 num_src_deriv_channels = 3;
4643 num_deriv_channels = 2;
4644 break;
4645 case TGSI_TEXTURE_1D:
4646 case TGSI_TEXTURE_SHADOW1D:
4647 case TGSI_TEXTURE_1D_ARRAY:
4648 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4649 num_src_deriv_channels = 1;
4650 num_deriv_channels = 1;
4651 break;
4652 default:
4653 unreachable("invalid target");
4654 }
4655
4656 for (param = 0; param < 2; param++)
4657 for (chan = 0; chan < num_src_deriv_channels; chan++)
4658 derivs[param * num_src_deriv_channels + chan] =
4659 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4660 }
4661
4662 if (target == TGSI_TEXTURE_CUBE ||
4663 target == TGSI_TEXTURE_CUBE_ARRAY ||
4664 target == TGSI_TEXTURE_SHADOWCUBE ||
4665 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4666 ac_prepare_cube_coords(&ctx->ac,
4667 opcode == TGSI_OPCODE_TXD,
4668 target == TGSI_TEXTURE_CUBE_ARRAY ||
4669 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4670 coords, derivs);
4671
4672 if (opcode == TGSI_OPCODE_TXD)
4673 for (int i = 0; i < num_deriv_channels * 2; i++)
4674 address[count++] = derivs[i];
4675
4676 /* Pack texture coordinates */
4677 address[count++] = coords[0];
4678 if (num_coords > 1)
4679 address[count++] = coords[1];
4680 if (num_coords > 2)
4681 address[count++] = coords[2];
4682
4683 /* Pack LOD or sample index */
4684 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4685 address[count++] = coords[3];
4686 else if (opcode == TGSI_OPCODE_TXL2)
4687 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4688
4689 if (count > 16) {
4690 assert(!"Cannot handle more than 16 texture address parameters");
4691 count = 16;
4692 }
4693
4694 for (chan = 0; chan < count; chan++ ) {
4695 address[chan] = LLVMBuildBitCast(gallivm->builder,
4696 address[chan], ctx->i32, "");
4697 }
4698
4699 /* Adjust the sample index according to FMASK.
4700 *
4701 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4702 * which is the identity mapping. Each nibble says which physical sample
4703 * should be fetched to get that sample.
4704 *
4705 * For example, 0x11111100 means there are only 2 samples stored and
4706 * the second sample covers 3/4 of the pixel. When reading samples 0
4707 * and 1, return physical sample 0 (determined by the first two 0s
4708 * in FMASK), otherwise return physical sample 1.
4709 *
4710 * The sample index should be adjusted as follows:
4711 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4712 */
4713 if (target == TGSI_TEXTURE_2D_MSAA ||
4714 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4715 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4716 struct lp_build_emit_data txf_emit_data = *emit_data;
4717 LLVMValueRef txf_address[4];
4718 unsigned txf_count = count;
4719 struct tgsi_full_instruction inst = {};
4720
4721 memcpy(txf_address, address, sizeof(txf_address));
4722
4723 if (target == TGSI_TEXTURE_2D_MSAA) {
4724 txf_address[2] = bld_base->uint_bld.zero;
4725 }
4726 txf_address[3] = bld_base->uint_bld.zero;
4727
4728 /* Read FMASK using TXF. */
4729 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4730 inst.Texture.Texture = target;
4731 txf_emit_data.inst = &inst;
4732 txf_emit_data.chan = 0;
4733 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4734 target, fmask_ptr, NULL,
4735 txf_address, txf_count, 0xf);
4736 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4737
4738 /* Initialize some constants. */
4739 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4740 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4741
4742 /* Apply the formula. */
4743 LLVMValueRef fmask =
4744 LLVMBuildExtractElement(gallivm->builder,
4745 txf_emit_data.output[0],
4746 uint_bld->zero, "");
4747
4748 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4749
4750 LLVMValueRef sample_index4 =
4751 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4752
4753 LLVMValueRef shifted_fmask =
4754 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4755
4756 LLVMValueRef final_sample =
4757 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4758
4759 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4760 * resource descriptor is 0 (invalid),
4761 */
4762 LLVMValueRef fmask_desc =
4763 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4764 ctx->v8i32, "");
4765
4766 LLVMValueRef fmask_word1 =
4767 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4768 uint_bld->one, "");
4769
4770 LLVMValueRef word1_is_nonzero =
4771 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4772 fmask_word1, uint_bld->zero, "");
4773
4774 /* Replace the MSAA sample index. */
4775 address[sample_chan] =
4776 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4777 final_sample, address[sample_chan], "");
4778 }
4779
4780 if (opcode == TGSI_OPCODE_TXF) {
4781 /* add tex offsets */
4782 if (inst->Texture.NumOffsets) {
4783 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4784 const struct tgsi_texture_offset *off = inst->TexOffsets;
4785
4786 assert(inst->Texture.NumOffsets == 1);
4787
4788 switch (target) {
4789 case TGSI_TEXTURE_3D:
4790 address[2] = lp_build_add(uint_bld, address[2],
4791 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4792 /* fall through */
4793 case TGSI_TEXTURE_2D:
4794 case TGSI_TEXTURE_SHADOW2D:
4795 case TGSI_TEXTURE_RECT:
4796 case TGSI_TEXTURE_SHADOWRECT:
4797 case TGSI_TEXTURE_2D_ARRAY:
4798 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4799 address[1] =
4800 lp_build_add(uint_bld, address[1],
4801 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4802 /* fall through */
4803 case TGSI_TEXTURE_1D:
4804 case TGSI_TEXTURE_SHADOW1D:
4805 case TGSI_TEXTURE_1D_ARRAY:
4806 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4807 address[0] =
4808 lp_build_add(uint_bld, address[0],
4809 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4810 break;
4811 /* texture offsets do not apply to other texture targets */
4812 }
4813 }
4814 }
4815
4816 if (opcode == TGSI_OPCODE_TG4) {
4817 unsigned gather_comp = 0;
4818
4819 /* DMASK was repurposed for GATHER4. 4 components are always
4820 * returned and DMASK works like a swizzle - it selects
4821 * the component to fetch. The only valid DMASK values are
4822 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4823 * (red,red,red,red) etc.) The ISA document doesn't mention
4824 * this.
4825 */
4826
4827 /* Get the component index from src1.x for Gather4. */
4828 if (!tgsi_is_shadow_target(target)) {
4829 LLVMValueRef comp_imm;
4830 struct tgsi_src_register src1 = inst->Src[1].Register;
4831
4832 assert(src1.File == TGSI_FILE_IMMEDIATE);
4833
4834 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4835 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4836 gather_comp = CLAMP(gather_comp, 0, 3);
4837 }
4838
4839 dmask = 1 << gather_comp;
4840 }
4841
4842 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4843 samp_ptr, address, count, dmask);
4844 }
4845
4846 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4847 * incorrectly forces nearest filtering if the texture format is integer.
4848 * The only effect it has on Gather4, which always returns 4 texels for
4849 * bilinear filtering, is that the final coordinates are off by 0.5 of
4850 * the texel size.
4851 *
4852 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4853 * or (0.5 / size) from the normalized coordinates.
4854 */
4855 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4856 struct lp_build_emit_data *emit_data,
4857 const char *intr_name,
4858 unsigned coord_vgpr_index)
4859 {
4860 LLVMBuilderRef builder = ctx->gallivm.builder;
4861 LLVMValueRef coord = emit_data->args[0];
4862 LLVMValueRef half_texel[2];
4863 int c;
4864
4865 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4866 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4867 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4868 } else {
4869 struct tgsi_full_instruction txq_inst = {};
4870 struct lp_build_emit_data txq_emit_data = {};
4871
4872 /* Query the texture size. */
4873 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4874 txq_emit_data.inst = &txq_inst;
4875 txq_emit_data.dst_type = ctx->v4i32;
4876 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4877 txq_inst.Texture.Texture,
4878 emit_data->args[1], NULL,
4879 &ctx->bld_base.uint_bld.zero,
4880 1, 0xf);
4881 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4882
4883 /* Compute -0.5 / size. */
4884 for (c = 0; c < 2; c++) {
4885 half_texel[c] =
4886 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4887 LLVMConstInt(ctx->i32, c, 0), "");
4888 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4889 half_texel[c] =
4890 lp_build_emit_llvm_unary(&ctx->bld_base,
4891 TGSI_OPCODE_RCP, half_texel[c]);
4892 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4893 LLVMConstReal(ctx->f32, -0.5), "");
4894 }
4895 }
4896
4897 for (c = 0; c < 2; c++) {
4898 LLVMValueRef tmp;
4899 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4900
4901 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4902 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4903 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4904 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4905 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4906 }
4907
4908 emit_data->args[0] = coord;
4909 emit_data->output[emit_data->chan] =
4910 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4911 emit_data->args, emit_data->arg_count,
4912 LP_FUNC_ATTR_READNONE);
4913 }
4914
4915 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4916 struct lp_build_tgsi_context *bld_base,
4917 struct lp_build_emit_data *emit_data)
4918 {
4919 struct si_shader_context *ctx = si_shader_context(bld_base);
4920 struct lp_build_context *base = &bld_base->base;
4921 const struct tgsi_full_instruction *inst = emit_data->inst;
4922 unsigned opcode = inst->Instruction.Opcode;
4923 unsigned target = inst->Texture.Texture;
4924 char intr_name[127];
4925 bool has_offset = inst->Texture.NumOffsets > 0;
4926 bool is_shadow = tgsi_is_shadow_target(target);
4927 char type[64];
4928 const char *name = "llvm.SI.image.sample";
4929 const char *infix = "";
4930
4931 if (target == TGSI_TEXTURE_BUFFER) {
4932 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4933 base->gallivm->builder,
4934 "llvm.SI.vs.load.input", emit_data->dst_type,
4935 emit_data->args, emit_data->arg_count,
4936 LP_FUNC_ATTR_READNONE);
4937 return;
4938 }
4939
4940 switch (opcode) {
4941 case TGSI_OPCODE_TXF:
4942 name = target == TGSI_TEXTURE_2D_MSAA ||
4943 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4944 "llvm.SI.image.load" :
4945 "llvm.SI.image.load.mip";
4946 is_shadow = false;
4947 has_offset = false;
4948 break;
4949 case TGSI_OPCODE_LODQ:
4950 name = "llvm.SI.getlod";
4951 is_shadow = false;
4952 has_offset = false;
4953 break;
4954 case TGSI_OPCODE_TEX:
4955 case TGSI_OPCODE_TEX2:
4956 case TGSI_OPCODE_TXP:
4957 if (ctx->type != PIPE_SHADER_FRAGMENT)
4958 infix = ".lz";
4959 break;
4960 case TGSI_OPCODE_TXB:
4961 case TGSI_OPCODE_TXB2:
4962 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4963 infix = ".b";
4964 break;
4965 case TGSI_OPCODE_TXL:
4966 case TGSI_OPCODE_TXL2:
4967 infix = ".l";
4968 break;
4969 case TGSI_OPCODE_TXD:
4970 infix = ".d";
4971 break;
4972 case TGSI_OPCODE_TG4:
4973 name = "llvm.SI.gather4";
4974 infix = ".lz";
4975 break;
4976 default:
4977 assert(0);
4978 return;
4979 }
4980
4981 /* Add the type and suffixes .c, .o if needed. */
4982 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4983 sprintf(intr_name, "%s%s%s%s.%s",
4984 name, is_shadow ? ".c" : "", infix,
4985 has_offset ? ".o" : "", type);
4986
4987 /* The hardware needs special lowering for Gather4 with integer formats. */
4988 if (opcode == TGSI_OPCODE_TG4) {
4989 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4990 /* This will also work with non-constant indexing because of how
4991 * glsl_to_tgsi works and we intent to preserve that behavior.
4992 */
4993 const unsigned src_idx = 2;
4994 unsigned sampler = inst->Src[src_idx].Register.Index;
4995
4996 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4997
4998 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4999 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
5000 /* Texture coordinates start after:
5001 * {offset, bias, z-compare, derivatives}
5002 * Only the offset and z-compare can occur here.
5003 */
5004 si_lower_gather4_integer(ctx, emit_data, intr_name,
5005 (int)has_offset + (int)is_shadow);
5006 return;
5007 }
5008 }
5009
5010 emit_data->output[emit_data->chan] = lp_build_intrinsic(
5011 base->gallivm->builder, intr_name, emit_data->dst_type,
5012 emit_data->args, emit_data->arg_count,
5013 LP_FUNC_ATTR_READNONE);
5014 }
5015
5016 static void si_llvm_emit_txqs(
5017 const struct lp_build_tgsi_action *action,
5018 struct lp_build_tgsi_context *bld_base,
5019 struct lp_build_emit_data *emit_data)
5020 {
5021 struct si_shader_context *ctx = si_shader_context(bld_base);
5022 struct gallivm_state *gallivm = bld_base->base.gallivm;
5023 LLVMBuilderRef builder = gallivm->builder;
5024 LLVMValueRef res, samples;
5025 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
5026
5027 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
5028
5029
5030 /* Read the samples from the descriptor directly. */
5031 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
5032 samples = LLVMBuildExtractElement(
5033 builder, res,
5034 lp_build_const_int32(gallivm, 3), "");
5035 samples = LLVMBuildLShr(builder, samples,
5036 lp_build_const_int32(gallivm, 16), "");
5037 samples = LLVMBuildAnd(builder, samples,
5038 lp_build_const_int32(gallivm, 0xf), "");
5039 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
5040 samples, "");
5041
5042 emit_data->output[emit_data->chan] = samples;
5043 }
5044
5045 /*
5046 * SI implements derivatives using the local data store (LDS)
5047 * All writes to the LDS happen in all executing threads at
5048 * the same time. TID is the Thread ID for the current
5049 * thread and is a value between 0 and 63, representing
5050 * the thread's position in the wavefront.
5051 *
5052 * For the pixel shader threads are grouped into quads of four pixels.
5053 * The TIDs of the pixels of a quad are:
5054 *
5055 * +------+------+
5056 * |4n + 0|4n + 1|
5057 * +------+------+
5058 * |4n + 2|4n + 3|
5059 * +------+------+
5060 *
5061 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
5062 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5063 * the current pixel's column, and masking with 0xfffffffe yields the TID
5064 * of the left pixel of the current pixel's row.
5065 *
5066 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5067 * adding 2 yields the TID of the pixel below the top pixel.
5068 */
5069 /* masks for thread ID. */
5070 #define TID_MASK_TOP_LEFT 0xfffffffc
5071 #define TID_MASK_TOP 0xfffffffd
5072 #define TID_MASK_LEFT 0xfffffffe
5073
5074 static void si_llvm_emit_ddxy(
5075 const struct lp_build_tgsi_action *action,
5076 struct lp_build_tgsi_context *bld_base,
5077 struct lp_build_emit_data *emit_data)
5078 {
5079 struct si_shader_context *ctx = si_shader_context(bld_base);
5080 struct gallivm_state *gallivm = bld_base->base.gallivm;
5081 unsigned opcode = emit_data->info->opcode;
5082 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
5083 int idx;
5084 unsigned mask;
5085
5086 thread_id = get_thread_id(ctx);
5087
5088 if (opcode == TGSI_OPCODE_DDX_FINE)
5089 mask = TID_MASK_LEFT;
5090 else if (opcode == TGSI_OPCODE_DDY_FINE)
5091 mask = TID_MASK_TOP;
5092 else
5093 mask = TID_MASK_TOP_LEFT;
5094
5095 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5096 lp_build_const_int32(gallivm, mask), "");
5097
5098 /* for DDX we want to next X pixel, DDY next Y pixel. */
5099 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5100 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5101 lp_build_const_int32(gallivm, idx), "");
5102
5103 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5104
5105 if (ctx->screen->has_ds_bpermute) {
5106 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5107 lp_build_const_int32(gallivm, 4), "");
5108 args[1] = val;
5109 tl = lp_build_intrinsic(gallivm->builder,
5110 "llvm.amdgcn.ds.bpermute", ctx->i32,
5111 args, 2, LP_FUNC_ATTR_READNONE);
5112
5113 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5114 lp_build_const_int32(gallivm, 4), "");
5115 trbl = lp_build_intrinsic(gallivm->builder,
5116 "llvm.amdgcn.ds.bpermute", ctx->i32,
5117 args, 2, LP_FUNC_ATTR_READNONE);
5118 } else {
5119 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5120
5121 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5122 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5123 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5124
5125 LLVMBuildStore(gallivm->builder, val, store_ptr);
5126 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5127 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5128 }
5129
5130 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5131 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5132
5133 emit_data->output[emit_data->chan] =
5134 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5135 }
5136
5137 /*
5138 * this takes an I,J coordinate pair,
5139 * and works out the X and Y derivatives.
5140 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5141 */
5142 static LLVMValueRef si_llvm_emit_ddxy_interp(
5143 struct lp_build_tgsi_context *bld_base,
5144 LLVMValueRef interp_ij)
5145 {
5146 struct si_shader_context *ctx = si_shader_context(bld_base);
5147 struct gallivm_state *gallivm = bld_base->base.gallivm;
5148 LLVMValueRef result[4], a;
5149 unsigned i;
5150
5151 for (i = 0; i < 2; i++) {
5152 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5153 LLVMConstInt(ctx->i32, i, 0), "");
5154 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5155 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5156 }
5157
5158 return lp_build_gather_values(gallivm, result, 4);
5159 }
5160
5161 static void interp_fetch_args(
5162 struct lp_build_tgsi_context *bld_base,
5163 struct lp_build_emit_data *emit_data)
5164 {
5165 struct si_shader_context *ctx = si_shader_context(bld_base);
5166 struct gallivm_state *gallivm = bld_base->base.gallivm;
5167 const struct tgsi_full_instruction *inst = emit_data->inst;
5168
5169 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5170 /* offset is in second src, first two channels */
5171 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5172 emit_data->inst, 1,
5173 TGSI_CHAN_X);
5174 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5175 emit_data->inst, 1,
5176 TGSI_CHAN_Y);
5177 emit_data->arg_count = 2;
5178 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5179 LLVMValueRef sample_position;
5180 LLVMValueRef sample_id;
5181 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5182
5183 /* fetch sample ID, then fetch its sample position,
5184 * and place into first two channels.
5185 */
5186 sample_id = lp_build_emit_fetch(bld_base,
5187 emit_data->inst, 1, TGSI_CHAN_X);
5188 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5189 ctx->i32, "");
5190 sample_position = load_sample_position(ctx, sample_id);
5191
5192 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5193 sample_position,
5194 lp_build_const_int32(gallivm, 0), "");
5195
5196 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5197 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5198 sample_position,
5199 lp_build_const_int32(gallivm, 1), "");
5200 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5201 emit_data->arg_count = 2;
5202 }
5203 }
5204
5205 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5206 struct lp_build_tgsi_context *bld_base,
5207 struct lp_build_emit_data *emit_data)
5208 {
5209 struct si_shader_context *ctx = si_shader_context(bld_base);
5210 struct si_shader *shader = ctx->shader;
5211 struct gallivm_state *gallivm = bld_base->base.gallivm;
5212 struct lp_build_context *uint = &bld_base->uint_bld;
5213 LLVMValueRef interp_param;
5214 const struct tgsi_full_instruction *inst = emit_data->inst;
5215 int input_index = inst->Src[0].Register.Index;
5216 int chan;
5217 int i;
5218 LLVMValueRef attr_number;
5219 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5220 int interp_param_idx;
5221 unsigned interp = shader->selector->info.input_interpolate[input_index];
5222 unsigned location;
5223
5224 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5225
5226 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5227 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5228 location = TGSI_INTERPOLATE_LOC_CENTER;
5229 else
5230 location = TGSI_INTERPOLATE_LOC_CENTROID;
5231
5232 interp_param_idx = lookup_interp_param_index(interp, location);
5233 if (interp_param_idx == -1)
5234 return;
5235 else if (interp_param_idx)
5236 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5237 else
5238 interp_param = NULL;
5239
5240 attr_number = lp_build_const_int32(gallivm, input_index);
5241
5242 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5243 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5244 LLVMValueRef ij_out[2];
5245 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5246
5247 /*
5248 * take the I then J parameters, and the DDX/Y for it, and
5249 * calculate the IJ inputs for the interpolator.
5250 * temp1 = ddx * offset/sample.x + I;
5251 * interp_param.I = ddy * offset/sample.y + temp1;
5252 * temp1 = ddx * offset/sample.x + J;
5253 * interp_param.J = ddy * offset/sample.y + temp1;
5254 */
5255 for (i = 0; i < 2; i++) {
5256 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5257 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5258 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5259 ddxy_out, ix_ll, "");
5260 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5261 ddxy_out, iy_ll, "");
5262 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5263 interp_param, ix_ll, "");
5264 LLVMValueRef temp1, temp2;
5265
5266 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5267 ctx->f32, "");
5268
5269 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5270
5271 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5272
5273 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5274
5275 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5276 }
5277 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5278 }
5279
5280 for (chan = 0; chan < 4; chan++) {
5281 LLVMValueRef llvm_chan;
5282 unsigned schan;
5283
5284 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5285 llvm_chan = lp_build_const_int32(gallivm, schan);
5286
5287 if (interp_param) {
5288 interp_param = LLVMBuildBitCast(gallivm->builder,
5289 interp_param, LLVMVectorType(ctx->f32, 2), "");
5290 LLVMValueRef i = LLVMBuildExtractElement(
5291 gallivm->builder, interp_param, uint->zero, "");
5292 LLVMValueRef j = LLVMBuildExtractElement(
5293 gallivm->builder, interp_param, uint->one, "");
5294 emit_data->output[chan] = build_fs_interp(bld_base,
5295 llvm_chan, attr_number, params,
5296 i, j);
5297 } else {
5298 emit_data->output[chan] = build_fs_interp_mov(bld_base,
5299 lp_build_const_int32(gallivm, 2), /* P0 */
5300 llvm_chan, attr_number, params);
5301 }
5302 }
5303 }
5304
5305 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5306 struct lp_build_emit_data *emit_data)
5307 {
5308 struct si_shader_context *ctx = si_shader_context(bld_base);
5309 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5310 LLVMValueRef imm;
5311 unsigned stream;
5312
5313 assert(src0.File == TGSI_FILE_IMMEDIATE);
5314
5315 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5316 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5317 return stream;
5318 }
5319
5320 /* Emit one vertex from the geometry shader */
5321 static void si_llvm_emit_vertex(
5322 const struct lp_build_tgsi_action *action,
5323 struct lp_build_tgsi_context *bld_base,
5324 struct lp_build_emit_data *emit_data)
5325 {
5326 struct si_shader_context *ctx = si_shader_context(bld_base);
5327 struct lp_build_context *uint = &bld_base->uint_bld;
5328 struct si_shader *shader = ctx->shader;
5329 struct tgsi_shader_info *info = &shader->selector->info;
5330 struct gallivm_state *gallivm = bld_base->base.gallivm;
5331 struct lp_build_if_state if_state;
5332 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5333 SI_PARAM_GS2VS_OFFSET);
5334 LLVMValueRef gs_next_vertex;
5335 LLVMValueRef can_emit, kill;
5336 LLVMValueRef args[2];
5337 unsigned chan, offset;
5338 int i;
5339 unsigned stream;
5340
5341 stream = si_llvm_get_stream(bld_base, emit_data);
5342
5343 /* Write vertex attribute values to GSVS ring */
5344 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5345 ctx->gs_next_vertex[stream],
5346 "");
5347
5348 /* If this thread has already emitted the declared maximum number of
5349 * vertices, skip the write: excessive vertex emissions are not
5350 * supposed to have any effect.
5351 *
5352 * If the shader has no writes to memory, kill it instead. This skips
5353 * further memory loads and may allow LLVM to skip to the end
5354 * altogether.
5355 */
5356 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5357 lp_build_const_int32(gallivm,
5358 shader->selector->gs_max_out_vertices), "");
5359
5360 bool use_kill = !info->writes_memory;
5361 if (use_kill) {
5362 kill = lp_build_select(&bld_base->base, can_emit,
5363 lp_build_const_float(gallivm, 1.0f),
5364 lp_build_const_float(gallivm, -1.0f));
5365
5366 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5367 ctx->voidt, &kill, 1, 0);
5368 } else {
5369 lp_build_if(&if_state, gallivm, can_emit);
5370 }
5371
5372 offset = 0;
5373 for (i = 0; i < info->num_outputs; i++) {
5374 LLVMValueRef *out_ptr = ctx->outputs[i];
5375
5376 for (chan = 0; chan < 4; chan++) {
5377 if (!(info->output_usagemask[i] & (1 << chan)) ||
5378 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5379 continue;
5380
5381 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5382 LLVMValueRef voffset =
5383 lp_build_const_int32(gallivm, offset *
5384 shader->selector->gs_max_out_vertices);
5385 offset++;
5386
5387 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5388 voffset = lp_build_mul_imm(uint, voffset, 4);
5389
5390 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5391
5392 build_tbuffer_store(ctx,
5393 ctx->gsvs_ring[stream],
5394 out_val, 1,
5395 voffset, soffset, 0,
5396 V_008F0C_BUF_DATA_FORMAT_32,
5397 V_008F0C_BUF_NUM_FORMAT_UINT,
5398 1, 0, 1, 1, 0);
5399 }
5400 }
5401
5402 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5403 lp_build_const_int32(gallivm, 1));
5404
5405 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5406
5407 /* Signal vertex emission */
5408 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5409 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5410 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5411 ctx->voidt, args, 2, 0);
5412
5413 if (!use_kill)
5414 lp_build_endif(&if_state);
5415 }
5416
5417 /* Cut one primitive from the geometry shader */
5418 static void si_llvm_emit_primitive(
5419 const struct lp_build_tgsi_action *action,
5420 struct lp_build_tgsi_context *bld_base,
5421 struct lp_build_emit_data *emit_data)
5422 {
5423 struct si_shader_context *ctx = si_shader_context(bld_base);
5424 struct gallivm_state *gallivm = bld_base->base.gallivm;
5425 LLVMValueRef args[2];
5426 unsigned stream;
5427
5428 /* Signal primitive cut */
5429 stream = si_llvm_get_stream(bld_base, emit_data);
5430 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5431 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5432 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5433 ctx->voidt, args, 2, 0);
5434 }
5435
5436 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5437 struct lp_build_tgsi_context *bld_base,
5438 struct lp_build_emit_data *emit_data)
5439 {
5440 struct si_shader_context *ctx = si_shader_context(bld_base);
5441 struct gallivm_state *gallivm = bld_base->base.gallivm;
5442
5443 /* SI only (thanks to a hw bug workaround):
5444 * The real barrier instruction isn’t needed, because an entire patch
5445 * always fits into a single wave.
5446 */
5447 if (HAVE_LLVM >= 0x0309 &&
5448 ctx->screen->b.chip_class == SI &&
5449 ctx->type == PIPE_SHADER_TESS_CTRL) {
5450 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5451 return;
5452 }
5453
5454 lp_build_intrinsic(gallivm->builder,
5455 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5456 : "llvm.AMDGPU.barrier.local",
5457 ctx->voidt, NULL, 0, 0);
5458 }
5459
5460 static const struct lp_build_tgsi_action tex_action = {
5461 .fetch_args = tex_fetch_args,
5462 .emit = build_tex_intrinsic,
5463 };
5464
5465 static const struct lp_build_tgsi_action interp_action = {
5466 .fetch_args = interp_fetch_args,
5467 .emit = build_interp_intrinsic,
5468 };
5469
5470 static void si_create_function(struct si_shader_context *ctx,
5471 const char *name,
5472 LLVMTypeRef *returns, unsigned num_returns,
5473 LLVMTypeRef *params, unsigned num_params,
5474 int last_sgpr)
5475 {
5476 int i;
5477
5478 si_llvm_create_func(ctx, name, returns, num_returns,
5479 params, num_params);
5480 si_llvm_shader_type(ctx->main_fn, ctx->type);
5481 ctx->return_value = LLVMGetUndef(ctx->return_type);
5482
5483 for (i = 0; i <= last_sgpr; ++i) {
5484 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5485
5486 /* The combination of:
5487 * - ByVal
5488 * - dereferenceable
5489 * - invariant.load
5490 * allows the optimization passes to move loads and reduces
5491 * SGPR spilling significantly.
5492 */
5493 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5494 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5495 lp_add_attr_dereferenceable(P, UINT64_MAX);
5496 } else
5497 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5498 }
5499
5500 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5501 /* These were copied from some LLVM test. */
5502 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5503 "less-precise-fpmad",
5504 "true");
5505 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5506 "no-infs-fp-math",
5507 "true");
5508 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5509 "no-nans-fp-math",
5510 "true");
5511 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5512 "unsafe-fp-math",
5513 "true");
5514 }
5515 }
5516
5517 static void create_meta_data(struct si_shader_context *ctx)
5518 {
5519 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5520
5521 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5522 "invariant.load", 14);
5523 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5524 "range", 5);
5525 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5526 "amdgpu.uniform", 14);
5527
5528 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5529 }
5530
5531 static void declare_streamout_params(struct si_shader_context *ctx,
5532 struct pipe_stream_output_info *so,
5533 LLVMTypeRef *params, LLVMTypeRef i32,
5534 unsigned *num_params)
5535 {
5536 int i;
5537
5538 /* Streamout SGPRs. */
5539 if (so->num_outputs) {
5540 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5541 params[ctx->param_streamout_config = (*num_params)++] = i32;
5542 else
5543 ctx->param_streamout_config = ctx->param_tess_offchip;
5544
5545 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5546 }
5547 /* A streamout buffer offset is loaded if the stride is non-zero. */
5548 for (i = 0; i < 4; i++) {
5549 if (!so->stride[i])
5550 continue;
5551
5552 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5553 }
5554 }
5555
5556 static unsigned llvm_get_type_size(LLVMTypeRef type)
5557 {
5558 LLVMTypeKind kind = LLVMGetTypeKind(type);
5559
5560 switch (kind) {
5561 case LLVMIntegerTypeKind:
5562 return LLVMGetIntTypeWidth(type) / 8;
5563 case LLVMFloatTypeKind:
5564 return 4;
5565 case LLVMPointerTypeKind:
5566 return 8;
5567 case LLVMVectorTypeKind:
5568 return LLVMGetVectorSize(type) *
5569 llvm_get_type_size(LLVMGetElementType(type));
5570 case LLVMArrayTypeKind:
5571 return LLVMGetArrayLength(type) *
5572 llvm_get_type_size(LLVMGetElementType(type));
5573 default:
5574 assert(0);
5575 return 0;
5576 }
5577 }
5578
5579 static void declare_tess_lds(struct si_shader_context *ctx)
5580 {
5581 struct gallivm_state *gallivm = &ctx->gallivm;
5582 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5583 struct lp_build_context *uint = &bld_base->uint_bld;
5584
5585 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5586 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5587 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5588 "tess_lds");
5589 }
5590
5591 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5592 {
5593 const unsigned *properties = shader->selector->info.properties;
5594 unsigned max_work_group_size =
5595 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5596 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5597 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5598
5599 if (!max_work_group_size) {
5600 /* This is a variable group size compute shader,
5601 * compile it for the maximum possible group size.
5602 */
5603 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5604 }
5605 return max_work_group_size;
5606 }
5607
5608 static void create_function(struct si_shader_context *ctx)
5609 {
5610 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5611 struct gallivm_state *gallivm = bld_base->base.gallivm;
5612 struct si_shader *shader = ctx->shader;
5613 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5614 LLVMTypeRef returns[16+32*4];
5615 unsigned i, last_sgpr, num_params, num_return_sgprs;
5616 unsigned num_returns = 0;
5617 unsigned num_prolog_vgprs = 0;
5618
5619 v3i32 = LLVMVectorType(ctx->i32, 3);
5620
5621 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5622 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5623 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5624 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5625 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5626
5627 switch (ctx->type) {
5628 case PIPE_SHADER_VERTEX:
5629 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5630 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5631 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5632 params[SI_PARAM_DRAWID] = ctx->i32;
5633 num_params = SI_PARAM_DRAWID+1;
5634
5635 if (shader->key.as_es) {
5636 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5637 } else if (shader->key.as_ls) {
5638 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5639 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5640 } else {
5641 if (shader->is_gs_copy_shader) {
5642 num_params = SI_PARAM_RW_BUFFERS+1;
5643 } else {
5644 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5645 num_params = SI_PARAM_VS_STATE_BITS+1;
5646 }
5647
5648 /* The locations of the other parameters are assigned dynamically. */
5649 declare_streamout_params(ctx, &shader->selector->so,
5650 params, ctx->i32, &num_params);
5651 }
5652
5653 last_sgpr = num_params-1;
5654
5655 /* VGPRs */
5656 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5657 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5658 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5659 params[ctx->param_instance_id = num_params++] = ctx->i32;
5660
5661 if (!shader->is_gs_copy_shader) {
5662 /* Vertex load indices. */
5663 ctx->param_vertex_index0 = num_params;
5664
5665 for (i = 0; i < shader->selector->info.num_inputs; i++)
5666 params[num_params++] = ctx->i32;
5667
5668 num_prolog_vgprs += shader->selector->info.num_inputs;
5669
5670 /* PrimitiveID output. */
5671 if (!shader->key.as_es && !shader->key.as_ls)
5672 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5673 returns[num_returns++] = ctx->f32;
5674 }
5675 break;
5676
5677 case PIPE_SHADER_TESS_CTRL:
5678 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5679 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5680 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5681 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5682 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5683 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5684 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5685
5686 /* VGPRs */
5687 params[SI_PARAM_PATCH_ID] = ctx->i32;
5688 params[SI_PARAM_REL_IDS] = ctx->i32;
5689 num_params = SI_PARAM_REL_IDS+1;
5690
5691 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5692 * placed after the user SGPRs.
5693 */
5694 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5695 returns[num_returns++] = ctx->i32; /* SGPRs */
5696
5697 for (i = 0; i < 3; i++)
5698 returns[num_returns++] = ctx->f32; /* VGPRs */
5699 break;
5700
5701 case PIPE_SHADER_TESS_EVAL:
5702 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5703 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5704
5705 if (shader->key.as_es) {
5706 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5707 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5708 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5709 } else {
5710 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5711 declare_streamout_params(ctx, &shader->selector->so,
5712 params, ctx->i32, &num_params);
5713 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5714 }
5715 last_sgpr = num_params - 1;
5716
5717 /* VGPRs */
5718 params[ctx->param_tes_u = num_params++] = ctx->f32;
5719 params[ctx->param_tes_v = num_params++] = ctx->f32;
5720 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5721 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5722
5723 /* PrimitiveID output. */
5724 if (!shader->key.as_es)
5725 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5726 returns[num_returns++] = ctx->f32;
5727 break;
5728
5729 case PIPE_SHADER_GEOMETRY:
5730 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5731 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5732 last_sgpr = SI_PARAM_GS_WAVE_ID;
5733
5734 /* VGPRs */
5735 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5736 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5737 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5738 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5739 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5740 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5741 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5742 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5743 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5744 break;
5745
5746 case PIPE_SHADER_FRAGMENT:
5747 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5748 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5749 last_sgpr = SI_PARAM_PRIM_MASK;
5750 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5751 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5752 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5753 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5754 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5755 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5756 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5757 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5758 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5759 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5760 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5761 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5762 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5763 shader->info.face_vgpr_index = 20;
5764 params[SI_PARAM_ANCILLARY] = ctx->i32;
5765 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5766 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5767 num_params = SI_PARAM_POS_FIXED_PT+1;
5768
5769 /* Color inputs from the prolog. */
5770 if (shader->selector->info.colors_read) {
5771 unsigned num_color_elements =
5772 util_bitcount(shader->selector->info.colors_read);
5773
5774 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5775 for (i = 0; i < num_color_elements; i++)
5776 params[num_params++] = ctx->f32;
5777
5778 num_prolog_vgprs += num_color_elements;
5779 }
5780
5781 /* Outputs for the epilog. */
5782 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5783 num_returns =
5784 num_return_sgprs +
5785 util_bitcount(shader->selector->info.colors_written) * 4 +
5786 shader->selector->info.writes_z +
5787 shader->selector->info.writes_stencil +
5788 shader->selector->info.writes_samplemask +
5789 1 /* SampleMaskIn */;
5790
5791 num_returns = MAX2(num_returns,
5792 num_return_sgprs +
5793 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5794
5795 for (i = 0; i < num_return_sgprs; i++)
5796 returns[i] = ctx->i32;
5797 for (; i < num_returns; i++)
5798 returns[i] = ctx->f32;
5799 break;
5800
5801 case PIPE_SHADER_COMPUTE:
5802 params[SI_PARAM_GRID_SIZE] = v3i32;
5803 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5804 params[SI_PARAM_BLOCK_ID] = v3i32;
5805 last_sgpr = SI_PARAM_BLOCK_ID;
5806
5807 params[SI_PARAM_THREAD_ID] = v3i32;
5808 num_params = SI_PARAM_THREAD_ID + 1;
5809 break;
5810 default:
5811 assert(0 && "unimplemented shader");
5812 return;
5813 }
5814
5815 assert(num_params <= ARRAY_SIZE(params));
5816
5817 si_create_function(ctx, "main", returns, num_returns, params,
5818 num_params, last_sgpr);
5819
5820 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5821 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5822 ctx->separate_prolog) {
5823 si_llvm_add_attribute(ctx->main_fn,
5824 "InitialPSInputAddr",
5825 S_0286D0_PERSP_SAMPLE_ENA(1) |
5826 S_0286D0_PERSP_CENTER_ENA(1) |
5827 S_0286D0_PERSP_CENTROID_ENA(1) |
5828 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5829 S_0286D0_LINEAR_CENTER_ENA(1) |
5830 S_0286D0_LINEAR_CENTROID_ENA(1) |
5831 S_0286D0_FRONT_FACE_ENA(1) |
5832 S_0286D0_POS_FIXED_PT_ENA(1));
5833 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5834 si_llvm_add_attribute(ctx->main_fn,
5835 "amdgpu-max-work-group-size",
5836 si_get_max_workgroup_size(shader));
5837 }
5838
5839 shader->info.num_input_sgprs = 0;
5840 shader->info.num_input_vgprs = 0;
5841
5842 for (i = 0; i <= last_sgpr; ++i)
5843 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5844
5845 for (; i < num_params; ++i)
5846 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5847
5848 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5849 shader->info.num_input_vgprs -= num_prolog_vgprs;
5850
5851 if (!ctx->screen->has_ds_bpermute &&
5852 bld_base->info &&
5853 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5854 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5855 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5856 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5857 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5858 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5859 ctx->lds =
5860 LLVMAddGlobalInAddressSpace(gallivm->module,
5861 LLVMArrayType(ctx->i32, 64),
5862 "ddxy_lds",
5863 LOCAL_ADDR_SPACE);
5864
5865 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5866 ctx->type == PIPE_SHADER_TESS_CTRL)
5867 declare_tess_lds(ctx);
5868 }
5869
5870 /**
5871 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5872 * for later use.
5873 */
5874 static void preload_ring_buffers(struct si_shader_context *ctx)
5875 {
5876 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5877 LLVMBuilderRef builder = gallivm->builder;
5878
5879 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5880 SI_PARAM_RW_BUFFERS);
5881
5882 if ((ctx->type == PIPE_SHADER_VERTEX &&
5883 ctx->shader->key.as_es) ||
5884 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5885 ctx->shader->key.as_es) ||
5886 ctx->type == PIPE_SHADER_GEOMETRY) {
5887 unsigned ring =
5888 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5889 : SI_ES_RING_ESGS;
5890 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5891
5892 ctx->esgs_ring =
5893 build_indexed_load_const(ctx, buf_ptr, offset);
5894 }
5895
5896 if (ctx->shader->is_gs_copy_shader) {
5897 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5898
5899 ctx->gsvs_ring[0] =
5900 build_indexed_load_const(ctx, buf_ptr, offset);
5901 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5902 const struct si_shader_selector *sel = ctx->shader->selector;
5903 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
5904 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5905 LLVMValueRef base_ring;
5906
5907 base_ring = build_indexed_load_const(ctx, buf_ptr, offset);
5908
5909 /* The conceptual layout of the GSVS ring is
5910 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5911 * but the real memory layout is swizzled across
5912 * threads:
5913 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5914 * t16v0c0 ..
5915 * Override the buffer descriptor accordingly.
5916 */
5917 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5918 uint64_t stream_offset = 0;
5919
5920 for (unsigned stream = 0; stream < 4; ++stream) {
5921 unsigned num_components;
5922 unsigned stride;
5923 unsigned num_records;
5924 LLVMValueRef ring, tmp;
5925
5926 num_components = sel->info.num_stream_output_components[stream];
5927 if (!num_components)
5928 continue;
5929
5930 stride = 4 * num_components * sel->gs_max_out_vertices;
5931
5932 /* Limit on the stride field for <= CIK. */
5933 assert(stride < (1 << 14));
5934
5935 num_records = 64;
5936
5937 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5938 tmp = LLVMBuildExtractElement(builder, ring, uint->zero, "");
5939 tmp = LLVMBuildAdd(builder, tmp,
5940 LLVMConstInt(ctx->i64,
5941 stream_offset, 0), "");
5942 stream_offset += stride * 64;
5943
5944 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->zero, "");
5945 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5946 tmp = LLVMBuildExtractElement(builder, ring, uint->one, "");
5947 tmp = LLVMBuildOr(builder, tmp,
5948 LLVMConstInt(ctx->i32,
5949 S_008F04_STRIDE(stride) |
5950 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5951 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->one, "");
5952 ring = LLVMBuildInsertElement(builder, ring,
5953 LLVMConstInt(ctx->i32, num_records, 0),
5954 LLVMConstInt(ctx->i32, 2, 0), "");
5955 ring = LLVMBuildInsertElement(builder, ring,
5956 LLVMConstInt(ctx->i32,
5957 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5958 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5959 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5960 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5961 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5962 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5963 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5964 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5965 S_008F0C_ADD_TID_ENABLE(1),
5966 0),
5967 LLVMConstInt(ctx->i32, 3, 0), "");
5968 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5969
5970 ctx->gsvs_ring[stream] = ring;
5971 }
5972 }
5973 }
5974
5975 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5976 LLVMValueRef param_rw_buffers,
5977 unsigned param_pos_fixed_pt)
5978 {
5979 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5980 struct gallivm_state *gallivm = bld_base->base.gallivm;
5981 LLVMBuilderRef builder = gallivm->builder;
5982 LLVMValueRef slot, desc, offset, row, bit, address[2];
5983
5984 /* Use the fixed-point gl_FragCoord input.
5985 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5986 * per coordinate to get the repeating effect.
5987 */
5988 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5989 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5990
5991 /* Load the buffer descriptor. */
5992 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5993 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5994
5995 /* The stipple pattern is 32x32, each row has 32 bits. */
5996 offset = LLVMBuildMul(builder, address[1],
5997 LLVMConstInt(ctx->i32, 4, 0), "");
5998 row = buffer_load_const(ctx, desc, offset);
5999 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
6000 bit = LLVMBuildLShr(builder, row, address[0], "");
6001 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
6002
6003 /* The intrinsic kills the thread if arg < 0. */
6004 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
6005 LLVMConstReal(ctx->f32, -1), "");
6006 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
6007 }
6008
6009 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
6010 struct si_shader_config *conf,
6011 unsigned symbol_offset)
6012 {
6013 unsigned i;
6014 const unsigned char *config =
6015 radeon_shader_binary_config_start(binary, symbol_offset);
6016 bool really_needs_scratch = false;
6017
6018 /* LLVM adds SGPR spills to the scratch size.
6019 * Find out if we really need the scratch buffer.
6020 */
6021 for (i = 0; i < binary->reloc_count; i++) {
6022 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
6023
6024 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6025 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6026 really_needs_scratch = true;
6027 break;
6028 }
6029 }
6030
6031 /* XXX: We may be able to emit some of these values directly rather than
6032 * extracting fields to be emitted later.
6033 */
6034
6035 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6036 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6037 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6038 switch (reg) {
6039 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6040 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6041 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6042 case R_00B848_COMPUTE_PGM_RSRC1:
6043 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6044 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6045 conf->float_mode = G_00B028_FLOAT_MODE(value);
6046 conf->rsrc1 = value;
6047 break;
6048 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6049 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6050 break;
6051 case R_00B84C_COMPUTE_PGM_RSRC2:
6052 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6053 conf->rsrc2 = value;
6054 break;
6055 case R_0286CC_SPI_PS_INPUT_ENA:
6056 conf->spi_ps_input_ena = value;
6057 break;
6058 case R_0286D0_SPI_PS_INPUT_ADDR:
6059 conf->spi_ps_input_addr = value;
6060 break;
6061 case R_0286E8_SPI_TMPRING_SIZE:
6062 case R_00B860_COMPUTE_TMPRING_SIZE:
6063 /* WAVESIZE is in units of 256 dwords. */
6064 if (really_needs_scratch)
6065 conf->scratch_bytes_per_wave =
6066 G_00B860_WAVESIZE(value) * 256 * 4;
6067 break;
6068 case 0x4: /* SPILLED_SGPRS */
6069 conf->spilled_sgprs = value;
6070 break;
6071 case 0x8: /* SPILLED_VGPRS */
6072 conf->spilled_vgprs = value;
6073 break;
6074 default:
6075 {
6076 static bool printed;
6077
6078 if (!printed) {
6079 fprintf(stderr, "Warning: LLVM emitted unknown "
6080 "config register: 0x%x\n", reg);
6081 printed = true;
6082 }
6083 }
6084 break;
6085 }
6086 }
6087
6088 if (!conf->spi_ps_input_addr)
6089 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6090 }
6091
6092 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6093 struct si_shader *shader,
6094 struct si_shader_config *config,
6095 uint64_t scratch_va)
6096 {
6097 unsigned i;
6098 uint32_t scratch_rsrc_dword0 = scratch_va;
6099 uint32_t scratch_rsrc_dword1 =
6100 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6101
6102 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6103 * correctly.
6104 */
6105 if (HAVE_LLVM >= 0x0309)
6106 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6107 else
6108 scratch_rsrc_dword1 |=
6109 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6110
6111 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6112 const struct radeon_shader_reloc *reloc =
6113 &shader->binary.relocs[i];
6114 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6115 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6116 &scratch_rsrc_dword0, 4);
6117 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6118 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6119 &scratch_rsrc_dword1, 4);
6120 }
6121 }
6122 }
6123
6124 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6125 {
6126 unsigned size = shader->binary.code_size;
6127
6128 if (shader->prolog)
6129 size += shader->prolog->binary.code_size;
6130 if (shader->epilog)
6131 size += shader->epilog->binary.code_size;
6132 return size;
6133 }
6134
6135 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6136 {
6137 const struct radeon_shader_binary *prolog =
6138 shader->prolog ? &shader->prolog->binary : NULL;
6139 const struct radeon_shader_binary *epilog =
6140 shader->epilog ? &shader->epilog->binary : NULL;
6141 const struct radeon_shader_binary *mainb = &shader->binary;
6142 unsigned bo_size = si_get_shader_binary_size(shader) +
6143 (!epilog ? mainb->rodata_size : 0);
6144 unsigned char *ptr;
6145
6146 assert(!prolog || !prolog->rodata_size);
6147 assert((!prolog && !epilog) || !mainb->rodata_size);
6148 assert(!epilog || !epilog->rodata_size);
6149
6150 r600_resource_reference(&shader->bo, NULL);
6151 shader->bo = (struct r600_resource*)
6152 pipe_buffer_create(&sscreen->b.b, 0,
6153 PIPE_USAGE_IMMUTABLE, bo_size);
6154 if (!shader->bo)
6155 return -ENOMEM;
6156
6157 /* Upload. */
6158 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6159 PIPE_TRANSFER_READ_WRITE);
6160
6161 if (prolog) {
6162 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6163 ptr += prolog->code_size;
6164 }
6165
6166 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6167 ptr += mainb->code_size;
6168
6169 if (epilog)
6170 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6171 else if (mainb->rodata_size > 0)
6172 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6173
6174 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6175 return 0;
6176 }
6177
6178 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6179 struct pipe_debug_callback *debug,
6180 const char *name, FILE *file)
6181 {
6182 char *line, *p;
6183 unsigned i, count;
6184
6185 if (binary->disasm_string) {
6186 fprintf(file, "Shader %s disassembly:\n", name);
6187 fprintf(file, "%s", binary->disasm_string);
6188
6189 if (debug && debug->debug_message) {
6190 /* Very long debug messages are cut off, so send the
6191 * disassembly one line at a time. This causes more
6192 * overhead, but on the plus side it simplifies
6193 * parsing of resulting logs.
6194 */
6195 pipe_debug_message(debug, SHADER_INFO,
6196 "Shader Disassembly Begin");
6197
6198 line = binary->disasm_string;
6199 while (*line) {
6200 p = util_strchrnul(line, '\n');
6201 count = p - line;
6202
6203 if (count) {
6204 pipe_debug_message(debug, SHADER_INFO,
6205 "%.*s", count, line);
6206 }
6207
6208 if (!*p)
6209 break;
6210 line = p + 1;
6211 }
6212
6213 pipe_debug_message(debug, SHADER_INFO,
6214 "Shader Disassembly End");
6215 }
6216 } else {
6217 fprintf(file, "Shader %s binary:\n", name);
6218 for (i = 0; i < binary->code_size; i += 4) {
6219 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6220 binary->code[i + 3], binary->code[i + 2],
6221 binary->code[i + 1], binary->code[i]);
6222 }
6223 }
6224 }
6225
6226 static void si_shader_dump_stats(struct si_screen *sscreen,
6227 struct si_shader *shader,
6228 struct pipe_debug_callback *debug,
6229 unsigned processor,
6230 FILE *file,
6231 bool check_debug_option)
6232 {
6233 struct si_shader_config *conf = &shader->config;
6234 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6235 unsigned code_size = si_get_shader_binary_size(shader);
6236 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6237 unsigned lds_per_wave = 0;
6238 unsigned max_simd_waves = 10;
6239
6240 /* Compute LDS usage for PS. */
6241 switch (processor) {
6242 case PIPE_SHADER_FRAGMENT:
6243 /* The minimum usage per wave is (num_inputs * 48). The maximum
6244 * usage is (num_inputs * 48 * 16).
6245 * We can get anything in between and it varies between waves.
6246 *
6247 * The 48 bytes per input for a single primitive is equal to
6248 * 4 bytes/component * 4 components/input * 3 points.
6249 *
6250 * Other stages don't know the size at compile time or don't
6251 * allocate LDS per wave, but instead they do it per thread group.
6252 */
6253 lds_per_wave = conf->lds_size * lds_increment +
6254 align(num_inputs * 48, lds_increment);
6255 break;
6256 case PIPE_SHADER_COMPUTE:
6257 if (shader->selector) {
6258 unsigned max_workgroup_size =
6259 si_get_max_workgroup_size(shader);
6260 lds_per_wave = (conf->lds_size * lds_increment) /
6261 DIV_ROUND_UP(max_workgroup_size, 64);
6262 }
6263 break;
6264 }
6265
6266 /* Compute the per-SIMD wave counts. */
6267 if (conf->num_sgprs) {
6268 if (sscreen->b.chip_class >= VI)
6269 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6270 else
6271 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6272 }
6273
6274 if (conf->num_vgprs)
6275 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6276
6277 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6278 * 16KB makes some SIMDs unoccupied). */
6279 if (lds_per_wave)
6280 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6281
6282 if (!check_debug_option ||
6283 r600_can_dump_shader(&sscreen->b, processor)) {
6284 if (processor == PIPE_SHADER_FRAGMENT) {
6285 fprintf(file, "*** SHADER CONFIG ***\n"
6286 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6287 "SPI_PS_INPUT_ENA = 0x%04x\n",
6288 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6289 }
6290
6291 fprintf(file, "*** SHADER STATS ***\n"
6292 "SGPRS: %d\n"
6293 "VGPRS: %d\n"
6294 "Spilled SGPRs: %d\n"
6295 "Spilled VGPRs: %d\n"
6296 "Private memory VGPRs: %d\n"
6297 "Code Size: %d bytes\n"
6298 "LDS: %d blocks\n"
6299 "Scratch: %d bytes per wave\n"
6300 "Max Waves: %d\n"
6301 "********************\n\n\n",
6302 conf->num_sgprs, conf->num_vgprs,
6303 conf->spilled_sgprs, conf->spilled_vgprs,
6304 conf->private_mem_vgprs, code_size,
6305 conf->lds_size, conf->scratch_bytes_per_wave,
6306 max_simd_waves);
6307 }
6308
6309 pipe_debug_message(debug, SHADER_INFO,
6310 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6311 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6312 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6313 conf->num_sgprs, conf->num_vgprs, code_size,
6314 conf->lds_size, conf->scratch_bytes_per_wave,
6315 max_simd_waves, conf->spilled_sgprs,
6316 conf->spilled_vgprs, conf->private_mem_vgprs);
6317 }
6318
6319 static const char *si_get_shader_name(struct si_shader *shader,
6320 unsigned processor)
6321 {
6322 switch (processor) {
6323 case PIPE_SHADER_VERTEX:
6324 if (shader->key.as_es)
6325 return "Vertex Shader as ES";
6326 else if (shader->key.as_ls)
6327 return "Vertex Shader as LS";
6328 else
6329 return "Vertex Shader as VS";
6330 case PIPE_SHADER_TESS_CTRL:
6331 return "Tessellation Control Shader";
6332 case PIPE_SHADER_TESS_EVAL:
6333 if (shader->key.as_es)
6334 return "Tessellation Evaluation Shader as ES";
6335 else
6336 return "Tessellation Evaluation Shader as VS";
6337 case PIPE_SHADER_GEOMETRY:
6338 if (shader->is_gs_copy_shader)
6339 return "GS Copy Shader as VS";
6340 else
6341 return "Geometry Shader";
6342 case PIPE_SHADER_FRAGMENT:
6343 return "Pixel Shader";
6344 case PIPE_SHADER_COMPUTE:
6345 return "Compute Shader";
6346 default:
6347 return "Unknown Shader";
6348 }
6349 }
6350
6351 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6352 struct pipe_debug_callback *debug, unsigned processor,
6353 FILE *file, bool check_debug_option)
6354 {
6355 if (!check_debug_option ||
6356 r600_can_dump_shader(&sscreen->b, processor))
6357 si_dump_shader_key(processor, &shader->key, file);
6358
6359 if (!check_debug_option && shader->binary.llvm_ir_string) {
6360 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6361 si_get_shader_name(shader, processor));
6362 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6363 }
6364
6365 if (!check_debug_option ||
6366 (r600_can_dump_shader(&sscreen->b, processor) &&
6367 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6368 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6369
6370 if (shader->prolog)
6371 si_shader_dump_disassembly(&shader->prolog->binary,
6372 debug, "prolog", file);
6373
6374 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6375
6376 if (shader->epilog)
6377 si_shader_dump_disassembly(&shader->epilog->binary,
6378 debug, "epilog", file);
6379 fprintf(file, "\n");
6380 }
6381
6382 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6383 check_debug_option);
6384 }
6385
6386 int si_compile_llvm(struct si_screen *sscreen,
6387 struct radeon_shader_binary *binary,
6388 struct si_shader_config *conf,
6389 LLVMTargetMachineRef tm,
6390 LLVMModuleRef mod,
6391 struct pipe_debug_callback *debug,
6392 unsigned processor,
6393 const char *name)
6394 {
6395 int r = 0;
6396 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6397
6398 if (r600_can_dump_shader(&sscreen->b, processor)) {
6399 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6400
6401 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6402 fprintf(stderr, "%s LLVM IR:\n\n", name);
6403 LLVMDumpModule(mod);
6404 fprintf(stderr, "\n");
6405 }
6406 }
6407
6408 if (sscreen->record_llvm_ir) {
6409 char *ir = LLVMPrintModuleToString(mod);
6410 binary->llvm_ir_string = strdup(ir);
6411 LLVMDisposeMessage(ir);
6412 }
6413
6414 if (!si_replace_shader(count, binary)) {
6415 r = si_llvm_compile(mod, binary, tm, debug);
6416 if (r)
6417 return r;
6418 }
6419
6420 si_shader_binary_read_config(binary, conf, 0);
6421
6422 /* Enable 64-bit and 16-bit denormals, because there is no performance
6423 * cost.
6424 *
6425 * If denormals are enabled, all floating-point output modifiers are
6426 * ignored.
6427 *
6428 * Don't enable denormals for 32-bit floats, because:
6429 * - Floating-point output modifiers would be ignored by the hw.
6430 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6431 * have to stop using those.
6432 * - SI & CI would be very slow.
6433 */
6434 conf->float_mode |= V_00B028_FP_64_DENORMS;
6435
6436 FREE(binary->config);
6437 FREE(binary->global_symbol_offsets);
6438 binary->config = NULL;
6439 binary->global_symbol_offsets = NULL;
6440
6441 /* Some shaders can't have rodata because their binaries can be
6442 * concatenated.
6443 */
6444 if (binary->rodata_size &&
6445 (processor == PIPE_SHADER_VERTEX ||
6446 processor == PIPE_SHADER_TESS_CTRL ||
6447 processor == PIPE_SHADER_TESS_EVAL ||
6448 processor == PIPE_SHADER_FRAGMENT)) {
6449 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6450 return -EINVAL;
6451 }
6452
6453 return r;
6454 }
6455
6456 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6457 {
6458 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6459 LLVMBuildRetVoid(ctx->gallivm.builder);
6460 else
6461 LLVMBuildRet(ctx->gallivm.builder, ret);
6462 }
6463
6464 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6465 struct si_shader *
6466 si_generate_gs_copy_shader(struct si_screen *sscreen,
6467 LLVMTargetMachineRef tm,
6468 struct si_shader_selector *gs_selector,
6469 struct pipe_debug_callback *debug)
6470 {
6471 struct si_shader_context ctx;
6472 struct si_shader *shader;
6473 struct gallivm_state *gallivm = &ctx.gallivm;
6474 LLVMBuilderRef builder;
6475 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6476 struct lp_build_context *uint = &bld_base->uint_bld;
6477 struct si_shader_output_values *outputs;
6478 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6479 LLVMValueRef args[9];
6480 int i, r;
6481
6482 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6483
6484 if (!outputs)
6485 return NULL;
6486
6487 shader = CALLOC_STRUCT(si_shader);
6488 if (!shader) {
6489 FREE(outputs);
6490 return NULL;
6491 }
6492
6493
6494 shader->selector = gs_selector;
6495 shader->is_gs_copy_shader = true;
6496
6497 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6498 ctx.type = PIPE_SHADER_VERTEX;
6499
6500 builder = gallivm->builder;
6501
6502 create_meta_data(&ctx);
6503 create_function(&ctx);
6504 preload_ring_buffers(&ctx);
6505
6506 args[0] = ctx.gsvs_ring[0];
6507 args[1] = lp_build_mul_imm(uint,
6508 LLVMGetParam(ctx.main_fn,
6509 ctx.param_vertex_id),
6510 4);
6511 args[3] = uint->zero;
6512 args[4] = uint->one; /* OFFEN */
6513 args[5] = uint->zero; /* IDXEN */
6514 args[6] = uint->one; /* GLC */
6515 args[7] = uint->one; /* SLC */
6516 args[8] = uint->zero; /* TFE */
6517
6518 /* Fetch the vertex stream ID.*/
6519 LLVMValueRef stream_id;
6520
6521 if (gs_selector->so.num_outputs)
6522 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6523 else
6524 stream_id = uint->zero;
6525
6526 /* Fill in output information. */
6527 for (i = 0; i < gsinfo->num_outputs; ++i) {
6528 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6529 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6530
6531 for (int chan = 0; chan < 4; chan++) {
6532 outputs[i].vertex_stream[chan] =
6533 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6534 }
6535 }
6536
6537 LLVMBasicBlockRef end_bb;
6538 LLVMValueRef switch_inst;
6539
6540 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6541 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6542
6543 for (int stream = 0; stream < 4; stream++) {
6544 LLVMBasicBlockRef bb;
6545 unsigned offset;
6546
6547 if (!gsinfo->num_stream_output_components[stream])
6548 continue;
6549
6550 if (stream > 0 && !gs_selector->so.num_outputs)
6551 continue;
6552
6553 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6554 LLVMAddCase(switch_inst, lp_build_const_int32(gallivm, stream), bb);
6555 LLVMPositionBuilderAtEnd(builder, bb);
6556
6557 /* Fetch vertex data from GSVS ring */
6558 offset = 0;
6559 for (i = 0; i < gsinfo->num_outputs; ++i) {
6560 for (unsigned chan = 0; chan < 4; chan++) {
6561 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6562 outputs[i].vertex_stream[chan] != stream) {
6563 outputs[i].values[chan] = ctx.bld_base.base.undef;
6564 continue;
6565 }
6566
6567 args[2] = lp_build_const_int32(
6568 gallivm,
6569 offset * gs_selector->gs_max_out_vertices * 16 * 4);
6570 offset++;
6571
6572 outputs[i].values[chan] =
6573 LLVMBuildBitCast(gallivm->builder,
6574 lp_build_intrinsic(gallivm->builder,
6575 "llvm.SI.buffer.load.dword.i32.i32",
6576 ctx.i32, args, 9,
6577 LP_FUNC_ATTR_READONLY),
6578 ctx.f32, "");
6579 }
6580 }
6581
6582 /* Streamout and exports. */
6583 if (gs_selector->so.num_outputs) {
6584 si_llvm_emit_streamout(&ctx, outputs,
6585 gsinfo->num_outputs,
6586 stream);
6587 }
6588
6589 if (stream == 0)
6590 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6591
6592 LLVMBuildBr(builder, end_bb);
6593 }
6594
6595 LLVMPositionBuilderAtEnd(builder, end_bb);
6596
6597 LLVMBuildRetVoid(gallivm->builder);
6598
6599 /* Dump LLVM IR before any optimization passes */
6600 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6601 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6602 LLVMDumpModule(bld_base->base.gallivm->module);
6603
6604 si_llvm_finalize_module(&ctx,
6605 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6606
6607 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6608 &ctx.shader->config, ctx.tm,
6609 bld_base->base.gallivm->module,
6610 debug, PIPE_SHADER_GEOMETRY,
6611 "GS Copy Shader");
6612 if (!r) {
6613 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6614 fprintf(stderr, "GS Copy Shader:\n");
6615 si_shader_dump(sscreen, ctx.shader, debug,
6616 PIPE_SHADER_GEOMETRY, stderr, true);
6617 r = si_shader_binary_upload(sscreen, ctx.shader);
6618 }
6619
6620 si_llvm_dispose(&ctx);
6621
6622 FREE(outputs);
6623
6624 if (r != 0) {
6625 FREE(shader);
6626 shader = NULL;
6627 }
6628 return shader;
6629 }
6630
6631 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6632 FILE *f)
6633 {
6634 int i;
6635
6636 fprintf(f, "SHADER KEY\n");
6637
6638 switch (shader) {
6639 case PIPE_SHADER_VERTEX:
6640 fprintf(f, " part.vs.prolog.instance_divisors = {");
6641 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6642 fprintf(f, !i ? "%u" : ", %u",
6643 key->part.vs.prolog.instance_divisors[i]);
6644 fprintf(f, "}\n");
6645 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6646 fprintf(f, " as_es = %u\n", key->as_es);
6647 fprintf(f, " as_ls = %u\n", key->as_ls);
6648 fprintf(f, " mono.vs.fix_fetch = 0x%"PRIx64"\n", key->mono.vs.fix_fetch);
6649 break;
6650
6651 case PIPE_SHADER_TESS_CTRL:
6652 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6653 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6654 break;
6655
6656 case PIPE_SHADER_TESS_EVAL:
6657 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6658 fprintf(f, " as_es = %u\n", key->as_es);
6659 break;
6660
6661 case PIPE_SHADER_GEOMETRY:
6662 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6663 break;
6664
6665 case PIPE_SHADER_COMPUTE:
6666 break;
6667
6668 case PIPE_SHADER_FRAGMENT:
6669 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6670 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6671 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6672 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6673 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6674 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6675 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6676 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6677 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6678 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6679 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6680 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6681 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6682 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6683 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6684 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6685 break;
6686
6687 default:
6688 assert(0);
6689 }
6690
6691 if ((shader == PIPE_SHADER_GEOMETRY ||
6692 shader == PIPE_SHADER_TESS_EVAL ||
6693 shader == PIPE_SHADER_VERTEX) &&
6694 !key->as_es && !key->as_ls) {
6695 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6696 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6697 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6698 }
6699 }
6700
6701 static void si_init_shader_ctx(struct si_shader_context *ctx,
6702 struct si_screen *sscreen,
6703 struct si_shader *shader,
6704 LLVMTargetMachineRef tm)
6705 {
6706 struct lp_build_tgsi_context *bld_base;
6707 struct lp_build_tgsi_action tmpl = {};
6708
6709 si_llvm_context_init(ctx, sscreen, shader, tm,
6710 (shader && shader->selector) ? &shader->selector->info : NULL,
6711 (shader && shader->selector) ? shader->selector->tokens : NULL);
6712
6713 bld_base = &ctx->bld_base;
6714 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6715
6716 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6717 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6718 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6719
6720 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6721 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6722 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6723 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6724 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6725 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6726 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6727 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6728 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6729 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6730 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6731 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6732 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6733 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6734
6735 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6736 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6737 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6738 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6739 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6740 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6741
6742 tmpl.fetch_args = atomic_fetch_args;
6743 tmpl.emit = atomic_emit;
6744 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6745 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6746 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6747 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6748 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6749 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6750 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6751 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6752 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6753 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6754 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6755 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6756 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6757 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6758 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6759 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6760 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6761 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6762 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6763 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6764
6765 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6766
6767 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6768 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6769 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6770 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6771
6772 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6773 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6774 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6775 }
6776
6777 /* Return true if the PARAM export has been eliminated. */
6778 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6779 LLVMValueRef inst, unsigned offset)
6780 {
6781 struct si_shader *shader = ctx->shader;
6782 unsigned num_outputs = shader->selector->info.num_outputs;
6783 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6784 bool is_zero[4] = {}, is_one[4] = {};
6785
6786 for (i = 0; i < 4; i++) {
6787 LLVMBool loses_info;
6788 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6789
6790 /* It's a constant expression. Undef outputs are eliminated too. */
6791 if (LLVMIsUndef(p)) {
6792 is_zero[i] = true;
6793 is_one[i] = true;
6794 } else if (LLVMIsAConstantFP(p)) {
6795 double a = LLVMConstRealGetDouble(p, &loses_info);
6796
6797 if (a == 0)
6798 is_zero[i] = true;
6799 else if (a == 1)
6800 is_one[i] = true;
6801 else
6802 return false; /* other constant */
6803 } else
6804 return false;
6805 }
6806
6807 /* Only certain combinations of 0 and 1 can be eliminated. */
6808 if (is_zero[0] && is_zero[1] && is_zero[2])
6809 default_val = is_zero[3] ? 0 : 1;
6810 else if (is_one[0] && is_one[1] && is_one[2])
6811 default_val = is_zero[3] ? 2 : 3;
6812 else
6813 return false;
6814
6815 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6816 LLVMInstructionEraseFromParent(inst);
6817
6818 /* Change OFFSET to DEFAULT_VAL. */
6819 for (i = 0; i < num_outputs; i++) {
6820 if (shader->info.vs_output_param_offset[i] == offset) {
6821 shader->info.vs_output_param_offset[i] =
6822 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6823 break;
6824 }
6825 }
6826 return true;
6827 }
6828
6829 struct si_vs_exports {
6830 unsigned num;
6831 unsigned offset[SI_MAX_VS_OUTPUTS];
6832 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6833 };
6834
6835 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6836 {
6837 struct si_shader *shader = ctx->shader;
6838 struct tgsi_shader_info *info = &shader->selector->info;
6839 LLVMBasicBlockRef bb;
6840 struct si_vs_exports exports;
6841 bool removed_any = false;
6842
6843 exports.num = 0;
6844
6845 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6846 ctx->type == PIPE_SHADER_COMPUTE ||
6847 shader->key.as_es ||
6848 shader->key.as_ls)
6849 return;
6850
6851 /* Process all LLVM instructions. */
6852 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6853 while (bb) {
6854 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6855
6856 while (inst) {
6857 LLVMValueRef cur = inst;
6858 inst = LLVMGetNextInstruction(inst);
6859
6860 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6861 continue;
6862
6863 LLVMValueRef callee = lp_get_called_value(cur);
6864
6865 if (!lp_is_function(callee))
6866 continue;
6867
6868 const char *name = LLVMGetValueName(callee);
6869 unsigned num_args = LLVMCountParams(callee);
6870
6871 /* Check if this is an export instruction. */
6872 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6873 continue;
6874
6875 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6876 unsigned target = LLVMConstIntGetZExtValue(arg);
6877
6878 if (target < V_008DFC_SQ_EXP_PARAM)
6879 continue;
6880
6881 target -= V_008DFC_SQ_EXP_PARAM;
6882
6883 /* Eliminate constant value PARAM exports. */
6884 if (si_eliminate_const_output(ctx, cur, target)) {
6885 removed_any = true;
6886 } else {
6887 exports.offset[exports.num] = target;
6888 exports.inst[exports.num] = cur;
6889 exports.num++;
6890 }
6891 }
6892 bb = LLVMGetNextBasicBlock(bb);
6893 }
6894
6895 /* Remove holes in export memory due to removed PARAM exports.
6896 * This is done by renumbering all PARAM exports.
6897 */
6898 if (removed_any) {
6899 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6900 unsigned new_count = 0;
6901 unsigned out, i;
6902
6903 /* Make a copy of the offsets. We need the old version while
6904 * we are modifying some of them. */
6905 assert(sizeof(current_offset) ==
6906 sizeof(shader->info.vs_output_param_offset));
6907 memcpy(current_offset, shader->info.vs_output_param_offset,
6908 sizeof(current_offset));
6909
6910 for (i = 0; i < exports.num; i++) {
6911 unsigned offset = exports.offset[i];
6912
6913 for (out = 0; out < info->num_outputs; out++) {
6914 if (current_offset[out] != offset)
6915 continue;
6916
6917 LLVMSetOperand(exports.inst[i], 3,
6918 LLVMConstInt(ctx->i32,
6919 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6920 shader->info.vs_output_param_offset[out] = new_count;
6921 new_count++;
6922 break;
6923 }
6924 }
6925 shader->info.nr_param_exports = new_count;
6926 }
6927 }
6928
6929 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6930 {
6931 ctx->shader->config.private_mem_vgprs = 0;
6932
6933 /* Process all LLVM instructions. */
6934 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6935 while (bb) {
6936 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6937
6938 while (next) {
6939 LLVMValueRef inst = next;
6940 next = LLVMGetNextInstruction(next);
6941
6942 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6943 continue;
6944
6945 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6946 /* No idea why LLVM aligns allocas to 4 elements. */
6947 unsigned alignment = LLVMGetAlignment(inst);
6948 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6949 ctx->shader->config.private_mem_vgprs += dw_size;
6950 }
6951 bb = LLVMGetNextBasicBlock(bb);
6952 }
6953 }
6954
6955 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6956 struct si_shader *shader)
6957 {
6958 struct si_shader_selector *sel = shader->selector;
6959 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6960
6961 switch (ctx->type) {
6962 case PIPE_SHADER_VERTEX:
6963 ctx->load_input = declare_input_vs;
6964 if (shader->key.as_ls)
6965 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6966 else if (shader->key.as_es)
6967 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6968 else
6969 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6970 break;
6971 case PIPE_SHADER_TESS_CTRL:
6972 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6973 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6974 bld_base->emit_store = store_output_tcs;
6975 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6976 break;
6977 case PIPE_SHADER_TESS_EVAL:
6978 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6979 if (shader->key.as_es)
6980 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6981 else
6982 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6983 break;
6984 case PIPE_SHADER_GEOMETRY:
6985 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6986 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6987 break;
6988 case PIPE_SHADER_FRAGMENT:
6989 ctx->load_input = declare_input_fs;
6990 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6991 break;
6992 case PIPE_SHADER_COMPUTE:
6993 ctx->declare_memory_region = declare_compute_memory;
6994 break;
6995 default:
6996 assert(!"Unsupported shader type");
6997 return false;
6998 }
6999
7000 create_meta_data(ctx);
7001 create_function(ctx);
7002 preload_ring_buffers(ctx);
7003
7004 if (ctx->type == PIPE_SHADER_GEOMETRY) {
7005 int i;
7006 for (i = 0; i < 4; i++) {
7007 ctx->gs_next_vertex[i] =
7008 lp_build_alloca(bld_base->base.gallivm,
7009 ctx->i32, "");
7010 }
7011 }
7012
7013 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
7014 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
7015 return false;
7016 }
7017
7018 si_llvm_build_ret(ctx, ctx->return_value);
7019 return true;
7020 }
7021
7022 /**
7023 * Compute the VS prolog key, which contains all the information needed to
7024 * build the VS prolog function, and set shader->info bits where needed.
7025 */
7026 static void si_get_vs_prolog_key(struct si_shader *shader,
7027 union si_shader_part_key *key)
7028 {
7029 struct tgsi_shader_info *info = &shader->selector->info;
7030
7031 memset(key, 0, sizeof(*key));
7032 key->vs_prolog.states = shader->key.part.vs.prolog;
7033 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7034 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7035
7036 /* Set the instanceID flag. */
7037 for (unsigned i = 0; i < info->num_inputs; i++)
7038 if (key->vs_prolog.states.instance_divisors[i])
7039 shader->info.uses_instanceid = true;
7040 }
7041
7042 /**
7043 * Compute the VS epilog key, which contains all the information needed to
7044 * build the VS epilog function, and set the PrimitiveID output offset.
7045 */
7046 static void si_get_vs_epilog_key(struct si_shader *shader,
7047 struct si_vs_epilog_bits *states,
7048 union si_shader_part_key *key)
7049 {
7050 memset(key, 0, sizeof(*key));
7051 key->vs_epilog.states = *states;
7052
7053 /* Set up the PrimitiveID output. */
7054 if (shader->key.part.vs.epilog.export_prim_id) {
7055 unsigned index = shader->selector->info.num_outputs;
7056 unsigned offset = shader->info.nr_param_exports++;
7057
7058 key->vs_epilog.prim_id_param_offset = offset;
7059 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7060 shader->info.vs_output_param_offset[index] = offset;
7061 }
7062 }
7063
7064 /**
7065 * Compute the PS prolog key, which contains all the information needed to
7066 * build the PS prolog function, and set related bits in shader->config.
7067 */
7068 static void si_get_ps_prolog_key(struct si_shader *shader,
7069 union si_shader_part_key *key,
7070 bool separate_prolog)
7071 {
7072 struct tgsi_shader_info *info = &shader->selector->info;
7073
7074 memset(key, 0, sizeof(*key));
7075 key->ps_prolog.states = shader->key.part.ps.prolog;
7076 key->ps_prolog.colors_read = info->colors_read;
7077 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7078 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7079 key->ps_prolog.wqm = info->uses_derivatives &&
7080 (key->ps_prolog.colors_read ||
7081 key->ps_prolog.states.force_persp_sample_interp ||
7082 key->ps_prolog.states.force_linear_sample_interp ||
7083 key->ps_prolog.states.force_persp_center_interp ||
7084 key->ps_prolog.states.force_linear_center_interp ||
7085 key->ps_prolog.states.bc_optimize_for_persp ||
7086 key->ps_prolog.states.bc_optimize_for_linear);
7087
7088 if (info->colors_read) {
7089 unsigned *color = shader->selector->color_attr_index;
7090
7091 if (shader->key.part.ps.prolog.color_two_side) {
7092 /* BCOLORs are stored after the last input. */
7093 key->ps_prolog.num_interp_inputs = info->num_inputs;
7094 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7095 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7096 }
7097
7098 for (unsigned i = 0; i < 2; i++) {
7099 unsigned interp = info->input_interpolate[color[i]];
7100 unsigned location = info->input_interpolate_loc[color[i]];
7101
7102 if (!(info->colors_read & (0xf << i*4)))
7103 continue;
7104
7105 key->ps_prolog.color_attr_index[i] = color[i];
7106
7107 if (shader->key.part.ps.prolog.flatshade_colors &&
7108 interp == TGSI_INTERPOLATE_COLOR)
7109 interp = TGSI_INTERPOLATE_CONSTANT;
7110
7111 switch (interp) {
7112 case TGSI_INTERPOLATE_CONSTANT:
7113 key->ps_prolog.color_interp_vgpr_index[i] = -1;
7114 break;
7115 case TGSI_INTERPOLATE_PERSPECTIVE:
7116 case TGSI_INTERPOLATE_COLOR:
7117 /* Force the interpolation location for colors here. */
7118 if (shader->key.part.ps.prolog.force_persp_sample_interp)
7119 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7120 if (shader->key.part.ps.prolog.force_persp_center_interp)
7121 location = TGSI_INTERPOLATE_LOC_CENTER;
7122
7123 switch (location) {
7124 case TGSI_INTERPOLATE_LOC_SAMPLE:
7125 key->ps_prolog.color_interp_vgpr_index[i] = 0;
7126 shader->config.spi_ps_input_ena |=
7127 S_0286CC_PERSP_SAMPLE_ENA(1);
7128 break;
7129 case TGSI_INTERPOLATE_LOC_CENTER:
7130 key->ps_prolog.color_interp_vgpr_index[i] = 2;
7131 shader->config.spi_ps_input_ena |=
7132 S_0286CC_PERSP_CENTER_ENA(1);
7133 break;
7134 case TGSI_INTERPOLATE_LOC_CENTROID:
7135 key->ps_prolog.color_interp_vgpr_index[i] = 4;
7136 shader->config.spi_ps_input_ena |=
7137 S_0286CC_PERSP_CENTROID_ENA(1);
7138 break;
7139 default:
7140 assert(0);
7141 }
7142 break;
7143 case TGSI_INTERPOLATE_LINEAR:
7144 /* Force the interpolation location for colors here. */
7145 if (shader->key.part.ps.prolog.force_linear_sample_interp)
7146 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7147 if (shader->key.part.ps.prolog.force_linear_center_interp)
7148 location = TGSI_INTERPOLATE_LOC_CENTER;
7149
7150 /* The VGPR assignment for non-monolithic shaders
7151 * works because InitialPSInputAddr is set on the
7152 * main shader and PERSP_PULL_MODEL is never used.
7153 */
7154 switch (location) {
7155 case TGSI_INTERPOLATE_LOC_SAMPLE:
7156 key->ps_prolog.color_interp_vgpr_index[i] =
7157 separate_prolog ? 6 : 9;
7158 shader->config.spi_ps_input_ena |=
7159 S_0286CC_LINEAR_SAMPLE_ENA(1);
7160 break;
7161 case TGSI_INTERPOLATE_LOC_CENTER:
7162 key->ps_prolog.color_interp_vgpr_index[i] =
7163 separate_prolog ? 8 : 11;
7164 shader->config.spi_ps_input_ena |=
7165 S_0286CC_LINEAR_CENTER_ENA(1);
7166 break;
7167 case TGSI_INTERPOLATE_LOC_CENTROID:
7168 key->ps_prolog.color_interp_vgpr_index[i] =
7169 separate_prolog ? 10 : 13;
7170 shader->config.spi_ps_input_ena |=
7171 S_0286CC_LINEAR_CENTROID_ENA(1);
7172 break;
7173 default:
7174 assert(0);
7175 }
7176 break;
7177 default:
7178 assert(0);
7179 }
7180 }
7181 }
7182 }
7183
7184 /**
7185 * Check whether a PS prolog is required based on the key.
7186 */
7187 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7188 {
7189 return key->ps_prolog.colors_read ||
7190 key->ps_prolog.states.force_persp_sample_interp ||
7191 key->ps_prolog.states.force_linear_sample_interp ||
7192 key->ps_prolog.states.force_persp_center_interp ||
7193 key->ps_prolog.states.force_linear_center_interp ||
7194 key->ps_prolog.states.bc_optimize_for_persp ||
7195 key->ps_prolog.states.bc_optimize_for_linear ||
7196 key->ps_prolog.states.poly_stipple;
7197 }
7198
7199 /**
7200 * Compute the PS epilog key, which contains all the information needed to
7201 * build the PS epilog function.
7202 */
7203 static void si_get_ps_epilog_key(struct si_shader *shader,
7204 union si_shader_part_key *key)
7205 {
7206 struct tgsi_shader_info *info = &shader->selector->info;
7207 memset(key, 0, sizeof(*key));
7208 key->ps_epilog.colors_written = info->colors_written;
7209 key->ps_epilog.writes_z = info->writes_z;
7210 key->ps_epilog.writes_stencil = info->writes_stencil;
7211 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7212 key->ps_epilog.states = shader->key.part.ps.epilog;
7213 }
7214
7215 /**
7216 * Build the GS prolog function. Rotate the input vertices for triangle strips
7217 * with adjacency.
7218 */
7219 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7220 union si_shader_part_key *key)
7221 {
7222 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7223 const unsigned num_vgprs = 8;
7224 struct gallivm_state *gallivm = &ctx->gallivm;
7225 LLVMBuilderRef builder = gallivm->builder;
7226 LLVMTypeRef params[32];
7227 LLVMTypeRef returns[32];
7228 LLVMValueRef func, ret;
7229
7230 for (unsigned i = 0; i < num_sgprs; ++i) {
7231 params[i] = ctx->i32;
7232 returns[i] = ctx->i32;
7233 }
7234
7235 for (unsigned i = 0; i < num_vgprs; ++i) {
7236 params[num_sgprs + i] = ctx->i32;
7237 returns[num_sgprs + i] = ctx->f32;
7238 }
7239
7240 /* Create the function. */
7241 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7242 params, num_sgprs + num_vgprs, num_sgprs - 1);
7243 func = ctx->main_fn;
7244
7245 /* Copy inputs to outputs. This should be no-op, as the registers match,
7246 * but it will prevent the compiler from overwriting them unintentionally.
7247 */
7248 ret = ctx->return_value;
7249 for (unsigned i = 0; i < num_sgprs; i++) {
7250 LLVMValueRef p = LLVMGetParam(func, i);
7251 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7252 }
7253 for (unsigned i = 0; i < num_vgprs; i++) {
7254 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7255 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7256 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7257 }
7258
7259 if (key->gs_prolog.states.tri_strip_adj_fix) {
7260 /* Remap the input vertices for every other primitive. */
7261 const unsigned vtx_params[6] = {
7262 num_sgprs,
7263 num_sgprs + 1,
7264 num_sgprs + 3,
7265 num_sgprs + 4,
7266 num_sgprs + 5,
7267 num_sgprs + 6
7268 };
7269 LLVMValueRef prim_id, rotate;
7270
7271 prim_id = LLVMGetParam(func, num_sgprs + 2);
7272 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7273
7274 for (unsigned i = 0; i < 6; ++i) {
7275 LLVMValueRef base, rotated, actual;
7276 base = LLVMGetParam(func, vtx_params[i]);
7277 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7278 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7279 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7280 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7281 }
7282 }
7283
7284 LLVMBuildRet(builder, ret);
7285 }
7286
7287 /**
7288 * Given a list of shader part functions, build a wrapper function that
7289 * runs them in sequence to form a monolithic shader.
7290 */
7291 static void si_build_wrapper_function(struct si_shader_context *ctx,
7292 LLVMValueRef *parts,
7293 unsigned num_parts,
7294 unsigned main_part)
7295 {
7296 struct gallivm_state *gallivm = &ctx->gallivm;
7297 LLVMBuilderRef builder = ctx->gallivm.builder;
7298 /* PS epilog has one arg per color component */
7299 LLVMTypeRef param_types[48];
7300 LLVMValueRef out[48];
7301 LLVMTypeRef function_type;
7302 unsigned num_params;
7303 unsigned num_out;
7304 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7305 unsigned num_sgprs, num_vgprs;
7306 unsigned last_sgpr_param;
7307 unsigned gprs;
7308
7309 for (unsigned i = 0; i < num_parts; ++i) {
7310 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7311 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7312 }
7313
7314 /* The parameters of the wrapper function correspond to those of the
7315 * first part in terms of SGPRs and VGPRs, but we use the types of the
7316 * main part to get the right types. This is relevant for the
7317 * dereferenceable attribute on descriptor table pointers.
7318 */
7319 num_sgprs = 0;
7320 num_vgprs = 0;
7321
7322 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7323 num_params = LLVMCountParamTypes(function_type);
7324
7325 for (unsigned i = 0; i < num_params; ++i) {
7326 LLVMValueRef param = LLVMGetParam(parts[0], i);
7327
7328 if (ac_is_sgpr_param(param)) {
7329 assert(num_vgprs == 0);
7330 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7331 } else {
7332 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7333 }
7334 }
7335 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7336
7337 num_params = 0;
7338 last_sgpr_param = 0;
7339 gprs = 0;
7340 while (gprs < num_sgprs + num_vgprs) {
7341 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7342 unsigned size;
7343
7344 param_types[num_params] = LLVMTypeOf(param);
7345 if (gprs < num_sgprs)
7346 last_sgpr_param = num_params;
7347 size = llvm_get_type_size(param_types[num_params]) / 4;
7348 num_params++;
7349
7350 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7351 assert(gprs + size <= num_sgprs + num_vgprs &&
7352 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7353
7354 gprs += size;
7355 }
7356
7357 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7358
7359 /* Record the arguments of the function as if they were an output of
7360 * a previous part.
7361 */
7362 num_out = 0;
7363 num_out_sgpr = 0;
7364
7365 for (unsigned i = 0; i < num_params; ++i) {
7366 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7367 LLVMTypeRef param_type = LLVMTypeOf(param);
7368 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7369 unsigned size = llvm_get_type_size(param_type) / 4;
7370
7371 if (size == 1) {
7372 if (param_type != out_type)
7373 param = LLVMBuildBitCast(builder, param, out_type, "");
7374 out[num_out++] = param;
7375 } else {
7376 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7377
7378 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7379 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7380 param_type = ctx->i64;
7381 }
7382
7383 if (param_type != vector_type)
7384 param = LLVMBuildBitCast(builder, param, vector_type, "");
7385
7386 for (unsigned j = 0; j < size; ++j)
7387 out[num_out++] = LLVMBuildExtractElement(
7388 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7389 }
7390
7391 if (i <= last_sgpr_param)
7392 num_out_sgpr = num_out;
7393 }
7394
7395 /* Now chain the parts. */
7396 for (unsigned part = 0; part < num_parts; ++part) {
7397 LLVMValueRef in[48];
7398 LLVMValueRef ret;
7399 LLVMTypeRef ret_type;
7400 unsigned out_idx = 0;
7401
7402 num_params = LLVMCountParams(parts[part]);
7403 assert(num_params <= ARRAY_SIZE(param_types));
7404
7405 /* Derive arguments for the next part from outputs of the
7406 * previous one.
7407 */
7408 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7409 LLVMValueRef param;
7410 LLVMTypeRef param_type;
7411 bool is_sgpr;
7412 unsigned param_size;
7413 LLVMValueRef arg = NULL;
7414
7415 param = LLVMGetParam(parts[part], param_idx);
7416 param_type = LLVMTypeOf(param);
7417 param_size = llvm_get_type_size(param_type) / 4;
7418 is_sgpr = ac_is_sgpr_param(param);
7419
7420 if (is_sgpr) {
7421 #if HAVE_LLVM < 0x0400
7422 LLVMRemoveAttribute(param, LLVMByValAttribute);
7423 #else
7424 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7425 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7426 #endif
7427 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7428 }
7429
7430 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7431 assert(is_sgpr || out_idx >= num_out_sgpr);
7432
7433 if (param_size == 1)
7434 arg = out[out_idx];
7435 else
7436 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7437
7438 if (LLVMTypeOf(arg) != param_type) {
7439 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7440 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7441 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7442 } else {
7443 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7444 }
7445 }
7446
7447 in[param_idx] = arg;
7448 out_idx += param_size;
7449 }
7450
7451 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7452 ret_type = LLVMTypeOf(ret);
7453
7454 /* Extract the returned GPRs. */
7455 num_out = 0;
7456 num_out_sgpr = 0;
7457
7458 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7459 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7460
7461 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7462
7463 for (unsigned i = 0; i < ret_size; ++i) {
7464 LLVMValueRef val =
7465 LLVMBuildExtractValue(builder, ret, i, "");
7466
7467 out[num_out++] = val;
7468
7469 if (LLVMTypeOf(val) == ctx->i32) {
7470 assert(num_out_sgpr + 1 == num_out);
7471 num_out_sgpr = num_out;
7472 }
7473 }
7474 }
7475 }
7476
7477 LLVMBuildRetVoid(builder);
7478 }
7479
7480 int si_compile_tgsi_shader(struct si_screen *sscreen,
7481 LLVMTargetMachineRef tm,
7482 struct si_shader *shader,
7483 bool is_monolithic,
7484 struct pipe_debug_callback *debug)
7485 {
7486 struct si_shader_selector *sel = shader->selector;
7487 struct si_shader_context ctx;
7488 struct lp_build_tgsi_context *bld_base;
7489 LLVMModuleRef mod;
7490 int r = -1;
7491
7492 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7493 * conversion fails. */
7494 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7495 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7496 tgsi_dump(sel->tokens, 0);
7497 si_dump_streamout(&sel->so);
7498 }
7499
7500 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7501 ctx.separate_prolog = !is_monolithic;
7502
7503 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7504 sizeof(shader->info.vs_output_param_offset));
7505
7506 shader->info.uses_instanceid = sel->info.uses_instanceid;
7507
7508 bld_base = &ctx.bld_base;
7509 ctx.load_system_value = declare_system_value;
7510
7511 if (!si_compile_tgsi_main(&ctx, shader)) {
7512 si_llvm_dispose(&ctx);
7513 return -1;
7514 }
7515
7516 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7517 LLVMValueRef parts[3];
7518 bool need_prolog;
7519 bool need_epilog;
7520
7521 need_prolog = sel->info.num_inputs;
7522 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7523
7524 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7525
7526 if (need_prolog) {
7527 union si_shader_part_key prolog_key;
7528 si_get_vs_prolog_key(shader, &prolog_key);
7529 si_build_vs_prolog_function(&ctx, &prolog_key);
7530 parts[0] = ctx.main_fn;
7531 }
7532
7533 if (need_epilog) {
7534 union si_shader_part_key epilog_key;
7535 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7536 si_build_vs_epilog_function(&ctx, &epilog_key);
7537 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7538 }
7539
7540 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7541 need_prolog ? 1 : 0);
7542 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7543 LLVMValueRef parts[2];
7544 union si_shader_part_key epilog_key;
7545
7546 parts[0] = ctx.main_fn;
7547
7548 memset(&epilog_key, 0, sizeof(epilog_key));
7549 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7550 si_build_tcs_epilog_function(&ctx, &epilog_key);
7551 parts[1] = ctx.main_fn;
7552
7553 si_build_wrapper_function(&ctx, parts, 2, 0);
7554 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7555 !shader->key.as_es) {
7556 LLVMValueRef parts[2];
7557 union si_shader_part_key epilog_key;
7558
7559 parts[0] = ctx.main_fn;
7560
7561 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7562 si_build_vs_epilog_function(&ctx, &epilog_key);
7563 parts[1] = ctx.main_fn;
7564
7565 si_build_wrapper_function(&ctx, parts, 2, 0);
7566 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7567 LLVMValueRef parts[2];
7568 union si_shader_part_key prolog_key;
7569
7570 parts[1] = ctx.main_fn;
7571
7572 memset(&prolog_key, 0, sizeof(prolog_key));
7573 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7574 si_build_gs_prolog_function(&ctx, &prolog_key);
7575 parts[0] = ctx.main_fn;
7576
7577 si_build_wrapper_function(&ctx, parts, 2, 1);
7578 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7579 LLVMValueRef parts[3];
7580 union si_shader_part_key prolog_key;
7581 union si_shader_part_key epilog_key;
7582 bool need_prolog;
7583
7584 si_get_ps_prolog_key(shader, &prolog_key, false);
7585 need_prolog = si_need_ps_prolog(&prolog_key);
7586
7587 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7588
7589 if (need_prolog) {
7590 si_build_ps_prolog_function(&ctx, &prolog_key);
7591 parts[0] = ctx.main_fn;
7592 }
7593
7594 si_get_ps_epilog_key(shader, &epilog_key);
7595 si_build_ps_epilog_function(&ctx, &epilog_key);
7596 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7597
7598 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7599 }
7600
7601 mod = bld_base->base.gallivm->module;
7602
7603 /* Dump LLVM IR before any optimization passes */
7604 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7605 r600_can_dump_shader(&sscreen->b, ctx.type))
7606 LLVMDumpModule(mod);
7607
7608 si_llvm_finalize_module(&ctx,
7609 r600_extra_shader_checks(&sscreen->b, ctx.type));
7610
7611 /* Post-optimization transformations and analysis. */
7612 si_eliminate_const_vs_outputs(&ctx);
7613
7614 if ((debug && debug->debug_message) ||
7615 r600_can_dump_shader(&sscreen->b, ctx.type))
7616 si_count_scratch_private_memory(&ctx);
7617
7618 /* Compile to bytecode. */
7619 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7620 mod, debug, ctx.type, "TGSI shader");
7621 si_llvm_dispose(&ctx);
7622 if (r) {
7623 fprintf(stderr, "LLVM failed to compile shader\n");
7624 return r;
7625 }
7626
7627 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7628 * LLVM 3.9svn has this bug.
7629 */
7630 if (sel->type == PIPE_SHADER_COMPUTE) {
7631 unsigned wave_size = 64;
7632 unsigned max_vgprs = 256;
7633 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7634 unsigned max_sgprs_per_wave = 128;
7635 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7636 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7637 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7638
7639 max_vgprs = max_vgprs / min_waves_per_simd;
7640 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7641
7642 if (shader->config.num_sgprs > max_sgprs ||
7643 shader->config.num_vgprs > max_vgprs) {
7644 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7645 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7646 shader->config.num_sgprs, shader->config.num_vgprs,
7647 max_sgprs, max_vgprs);
7648
7649 /* Just terminate the process, because dependent
7650 * shaders can hang due to bad input data, but use
7651 * the env var to allow shader-db to work.
7652 */
7653 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7654 abort();
7655 }
7656 }
7657
7658 /* Add the scratch offset to input SGPRs. */
7659 if (shader->config.scratch_bytes_per_wave)
7660 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7661
7662 /* Calculate the number of fragment input VGPRs. */
7663 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7664 shader->info.num_input_vgprs = 0;
7665 shader->info.face_vgpr_index = -1;
7666
7667 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7668 shader->info.num_input_vgprs += 2;
7669 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7670 shader->info.num_input_vgprs += 2;
7671 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7672 shader->info.num_input_vgprs += 2;
7673 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7674 shader->info.num_input_vgprs += 3;
7675 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7676 shader->info.num_input_vgprs += 2;
7677 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7678 shader->info.num_input_vgprs += 2;
7679 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7680 shader->info.num_input_vgprs += 2;
7681 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7682 shader->info.num_input_vgprs += 1;
7683 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7684 shader->info.num_input_vgprs += 1;
7685 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7686 shader->info.num_input_vgprs += 1;
7687 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7688 shader->info.num_input_vgprs += 1;
7689 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7690 shader->info.num_input_vgprs += 1;
7691 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7692 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7693 shader->info.num_input_vgprs += 1;
7694 }
7695 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7696 shader->info.num_input_vgprs += 1;
7697 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7698 shader->info.num_input_vgprs += 1;
7699 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7700 shader->info.num_input_vgprs += 1;
7701 }
7702
7703 return 0;
7704 }
7705
7706 /**
7707 * Create, compile and return a shader part (prolog or epilog).
7708 *
7709 * \param sscreen screen
7710 * \param list list of shader parts of the same category
7711 * \param type shader type
7712 * \param key shader part key
7713 * \param prolog whether the part being requested is a prolog
7714 * \param tm LLVM target machine
7715 * \param debug debug callback
7716 * \param build the callback responsible for building the main function
7717 * \return non-NULL on success
7718 */
7719 static struct si_shader_part *
7720 si_get_shader_part(struct si_screen *sscreen,
7721 struct si_shader_part **list,
7722 enum pipe_shader_type type,
7723 bool prolog,
7724 union si_shader_part_key *key,
7725 LLVMTargetMachineRef tm,
7726 struct pipe_debug_callback *debug,
7727 void (*build)(struct si_shader_context *,
7728 union si_shader_part_key *),
7729 const char *name)
7730 {
7731 struct si_shader_part *result;
7732
7733 pipe_mutex_lock(sscreen->shader_parts_mutex);
7734
7735 /* Find existing. */
7736 for (result = *list; result; result = result->next) {
7737 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7738 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7739 return result;
7740 }
7741 }
7742
7743 /* Compile a new one. */
7744 result = CALLOC_STRUCT(si_shader_part);
7745 result->key = *key;
7746
7747 struct si_shader shader = {};
7748 struct si_shader_context ctx;
7749 struct gallivm_state *gallivm = &ctx.gallivm;
7750
7751 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7752 ctx.type = type;
7753
7754 switch (type) {
7755 case PIPE_SHADER_VERTEX:
7756 break;
7757 case PIPE_SHADER_TESS_CTRL:
7758 assert(!prolog);
7759 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7760 break;
7761 case PIPE_SHADER_GEOMETRY:
7762 assert(prolog);
7763 break;
7764 case PIPE_SHADER_FRAGMENT:
7765 if (prolog)
7766 shader.key.part.ps.prolog = key->ps_prolog.states;
7767 else
7768 shader.key.part.ps.epilog = key->ps_epilog.states;
7769 break;
7770 default:
7771 unreachable("bad shader part");
7772 }
7773
7774 build(&ctx, key);
7775
7776 /* Compile. */
7777 si_llvm_finalize_module(&ctx,
7778 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7779
7780 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7781 gallivm->module, debug, ctx.type, name)) {
7782 FREE(result);
7783 result = NULL;
7784 goto out;
7785 }
7786
7787 result->next = *list;
7788 *list = result;
7789
7790 out:
7791 si_llvm_dispose(&ctx);
7792 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7793 return result;
7794 }
7795
7796 /**
7797 * Build the vertex shader prolog function.
7798 *
7799 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7800 * All inputs are returned unmodified. The vertex load indices are
7801 * stored after them, which will be used by the API VS for fetching inputs.
7802 *
7803 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7804 * input_v0,
7805 * input_v1,
7806 * input_v2,
7807 * input_v3,
7808 * (VertexID + BaseVertex),
7809 * (InstanceID + StartInstance),
7810 * (InstanceID / 2 + StartInstance)
7811 */
7812 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7813 union si_shader_part_key *key)
7814 {
7815 struct gallivm_state *gallivm = &ctx->gallivm;
7816 LLVMTypeRef *params, *returns;
7817 LLVMValueRef ret, func;
7818 int last_sgpr, num_params, num_returns, i;
7819
7820 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7821 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7822
7823 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7824 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7825 sizeof(LLVMTypeRef));
7826 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7827 key->vs_prolog.last_input + 1) *
7828 sizeof(LLVMTypeRef));
7829 num_params = 0;
7830 num_returns = 0;
7831
7832 /* Declare input and output SGPRs. */
7833 num_params = 0;
7834 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7835 params[num_params++] = ctx->i32;
7836 returns[num_returns++] = ctx->i32;
7837 }
7838 last_sgpr = num_params - 1;
7839
7840 /* 4 preloaded VGPRs (outputs must be floats) */
7841 for (i = 0; i < 4; i++) {
7842 params[num_params++] = ctx->i32;
7843 returns[num_returns++] = ctx->f32;
7844 }
7845
7846 /* Vertex load indices. */
7847 for (i = 0; i <= key->vs_prolog.last_input; i++)
7848 returns[num_returns++] = ctx->f32;
7849
7850 /* Create the function. */
7851 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7852 num_params, last_sgpr);
7853 func = ctx->main_fn;
7854
7855 /* Copy inputs to outputs. This should be no-op, as the registers match,
7856 * but it will prevent the compiler from overwriting them unintentionally.
7857 */
7858 ret = ctx->return_value;
7859 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7860 LLVMValueRef p = LLVMGetParam(func, i);
7861 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7862 }
7863 for (i = num_params - 4; i < num_params; i++) {
7864 LLVMValueRef p = LLVMGetParam(func, i);
7865 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7866 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7867 }
7868
7869 /* Compute vertex load indices from instance divisors. */
7870 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7871 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7872 LLVMValueRef index;
7873
7874 if (divisor) {
7875 /* InstanceID / Divisor + StartInstance */
7876 index = get_instance_index_for_fetch(ctx,
7877 SI_SGPR_START_INSTANCE,
7878 divisor);
7879 } else {
7880 /* VertexID + BaseVertex */
7881 index = LLVMBuildAdd(gallivm->builder,
7882 LLVMGetParam(func, ctx->param_vertex_id),
7883 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7884 }
7885
7886 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7887 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7888 num_params++, "");
7889 }
7890
7891 si_llvm_build_ret(ctx, ret);
7892 }
7893
7894 /**
7895 * Build the vertex shader epilog function. This is also used by the tessellation
7896 * evaluation shader compiled as VS.
7897 *
7898 * The input is PrimitiveID.
7899 *
7900 * If PrimitiveID is required by the pixel shader, export it.
7901 * Otherwise, do nothing.
7902 */
7903 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7904 union si_shader_part_key *key)
7905 {
7906 struct gallivm_state *gallivm = &ctx->gallivm;
7907 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7908 LLVMTypeRef params[5];
7909 int num_params, i;
7910
7911 /* Declare input VGPRs. */
7912 num_params = key->vs_epilog.states.export_prim_id ?
7913 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7914 assert(num_params <= ARRAY_SIZE(params));
7915
7916 for (i = 0; i < num_params; i++)
7917 params[i] = ctx->f32;
7918
7919 /* Create the function. */
7920 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7921
7922 /* Emit exports. */
7923 if (key->vs_epilog.states.export_prim_id) {
7924 struct lp_build_context *base = &bld_base->base;
7925 struct lp_build_context *uint = &bld_base->uint_bld;
7926 LLVMValueRef args[9];
7927
7928 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7929 args[1] = uint->zero; /* whether the EXEC mask is valid */
7930 args[2] = uint->zero; /* DONE bit */
7931 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7932 key->vs_epilog.prim_id_param_offset);
7933 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7934 args[5] = LLVMGetParam(ctx->main_fn,
7935 VS_EPILOG_PRIMID_LOC); /* X */
7936 args[6] = base->undef; /* Y */
7937 args[7] = base->undef; /* Z */
7938 args[8] = base->undef; /* W */
7939
7940 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7941 LLVMVoidTypeInContext(base->gallivm->context),
7942 args, 9, 0);
7943 }
7944
7945 LLVMBuildRetVoid(gallivm->builder);
7946 }
7947
7948 /**
7949 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7950 */
7951 static bool si_get_vs_epilog(struct si_screen *sscreen,
7952 LLVMTargetMachineRef tm,
7953 struct si_shader *shader,
7954 struct pipe_debug_callback *debug,
7955 struct si_vs_epilog_bits *states)
7956 {
7957 union si_shader_part_key epilog_key;
7958
7959 si_get_vs_epilog_key(shader, states, &epilog_key);
7960
7961 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7962 PIPE_SHADER_VERTEX, true,
7963 &epilog_key, tm, debug,
7964 si_build_vs_epilog_function,
7965 "Vertex Shader Epilog");
7966 return shader->epilog != NULL;
7967 }
7968
7969 /**
7970 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7971 */
7972 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7973 LLVMTargetMachineRef tm,
7974 struct si_shader *shader,
7975 struct pipe_debug_callback *debug)
7976 {
7977 struct tgsi_shader_info *info = &shader->selector->info;
7978 union si_shader_part_key prolog_key;
7979
7980 /* Get the prolog. */
7981 si_get_vs_prolog_key(shader, &prolog_key);
7982
7983 /* The prolog is a no-op if there are no inputs. */
7984 if (info->num_inputs) {
7985 shader->prolog =
7986 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7987 PIPE_SHADER_VERTEX, true,
7988 &prolog_key, tm, debug,
7989 si_build_vs_prolog_function,
7990 "Vertex Shader Prolog");
7991 if (!shader->prolog)
7992 return false;
7993 }
7994
7995 /* Get the epilog. */
7996 if (!shader->key.as_es && !shader->key.as_ls &&
7997 !si_get_vs_epilog(sscreen, tm, shader, debug,
7998 &shader->key.part.vs.epilog))
7999 return false;
8000
8001 return true;
8002 }
8003
8004 /**
8005 * Select and compile (or reuse) TES parts (epilog).
8006 */
8007 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
8008 LLVMTargetMachineRef tm,
8009 struct si_shader *shader,
8010 struct pipe_debug_callback *debug)
8011 {
8012 if (shader->key.as_es)
8013 return true;
8014
8015 /* TES compiled as VS. */
8016 return si_get_vs_epilog(sscreen, tm, shader, debug,
8017 &shader->key.part.tes.epilog);
8018 }
8019
8020 /**
8021 * Compile the TCS epilog function. This writes tesselation factors to memory
8022 * based on the output primitive type of the tesselator (determined by TES).
8023 */
8024 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
8025 union si_shader_part_key *key)
8026 {
8027 struct gallivm_state *gallivm = &ctx->gallivm;
8028 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8029 LLVMTypeRef params[16];
8030 LLVMValueRef func;
8031 int last_sgpr, num_params;
8032
8033 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
8034 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
8035 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8036 params[SI_PARAM_SAMPLERS] = ctx->i64;
8037 params[SI_PARAM_IMAGES] = ctx->i64;
8038 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8039 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
8040 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
8041 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
8042 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
8043 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
8044 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
8045 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
8046 num_params = last_sgpr + 1;
8047
8048 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
8049 params[num_params++] = ctx->i32; /* invocation ID within the patch */
8050 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
8051
8052 /* Create the function. */
8053 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
8054 declare_tess_lds(ctx);
8055 func = ctx->main_fn;
8056
8057 si_write_tess_factors(bld_base,
8058 LLVMGetParam(func, last_sgpr + 1),
8059 LLVMGetParam(func, last_sgpr + 2),
8060 LLVMGetParam(func, last_sgpr + 3));
8061
8062 LLVMBuildRetVoid(gallivm->builder);
8063 }
8064
8065 /**
8066 * Select and compile (or reuse) TCS parts (epilog).
8067 */
8068 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
8069 LLVMTargetMachineRef tm,
8070 struct si_shader *shader,
8071 struct pipe_debug_callback *debug)
8072 {
8073 union si_shader_part_key epilog_key;
8074
8075 /* Get the epilog. */
8076 memset(&epilog_key, 0, sizeof(epilog_key));
8077 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
8078
8079 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
8080 PIPE_SHADER_TESS_CTRL, false,
8081 &epilog_key, tm, debug,
8082 si_build_tcs_epilog_function,
8083 "Tessellation Control Shader Epilog");
8084 return shader->epilog != NULL;
8085 }
8086
8087 /**
8088 * Select and compile (or reuse) GS parts (prolog).
8089 */
8090 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
8091 LLVMTargetMachineRef tm,
8092 struct si_shader *shader,
8093 struct pipe_debug_callback *debug)
8094 {
8095 union si_shader_part_key prolog_key;
8096
8097 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
8098 return true;
8099
8100 memset(&prolog_key, 0, sizeof(prolog_key));
8101 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
8102
8103 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
8104 PIPE_SHADER_GEOMETRY, true,
8105 &prolog_key, tm, debug,
8106 si_build_gs_prolog_function,
8107 "Geometry Shader Prolog");
8108 return shader->prolog != NULL;
8109 }
8110
8111 /**
8112 * Build the pixel shader prolog function. This handles:
8113 * - two-side color selection and interpolation
8114 * - overriding interpolation parameters for the API PS
8115 * - polygon stippling
8116 *
8117 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
8118 * overriden by other states. (e.g. per-sample interpolation)
8119 * Interpolated colors are stored after the preloaded VGPRs.
8120 */
8121 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
8122 union si_shader_part_key *key)
8123 {
8124 struct gallivm_state *gallivm = &ctx->gallivm;
8125 LLVMTypeRef *params;
8126 LLVMValueRef ret, func;
8127 int last_sgpr, num_params, num_returns, i, num_color_channels;
8128
8129 assert(si_need_ps_prolog(key));
8130
8131 /* Number of inputs + 8 color elements. */
8132 params = alloca((key->ps_prolog.num_input_sgprs +
8133 key->ps_prolog.num_input_vgprs + 8) *
8134 sizeof(LLVMTypeRef));
8135
8136 /* Declare inputs. */
8137 num_params = 0;
8138 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
8139 params[num_params++] = ctx->i32;
8140 last_sgpr = num_params - 1;
8141
8142 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
8143 params[num_params++] = ctx->f32;
8144
8145 /* Declare outputs (same as inputs + add colors if needed) */
8146 num_returns = num_params;
8147 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
8148 for (i = 0; i < num_color_channels; i++)
8149 params[num_returns++] = ctx->f32;
8150
8151 /* Create the function. */
8152 si_create_function(ctx, "ps_prolog", params, num_returns, params,
8153 num_params, last_sgpr);
8154 func = ctx->main_fn;
8155
8156 /* Copy inputs to outputs. This should be no-op, as the registers match,
8157 * but it will prevent the compiler from overwriting them unintentionally.
8158 */
8159 ret = ctx->return_value;
8160 for (i = 0; i < num_params; i++) {
8161 LLVMValueRef p = LLVMGetParam(func, i);
8162 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
8163 }
8164
8165 /* Polygon stippling. */
8166 if (key->ps_prolog.states.poly_stipple) {
8167 /* POS_FIXED_PT is always last. */
8168 unsigned pos = key->ps_prolog.num_input_sgprs +
8169 key->ps_prolog.num_input_vgprs - 1;
8170 LLVMValueRef ptr[2], list;
8171
8172 /* Get the pointer to rw buffers. */
8173 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
8174 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
8175 list = lp_build_gather_values(gallivm, ptr, 2);
8176 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
8177 list = LLVMBuildIntToPtr(gallivm->builder, list,
8178 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8179
8180 si_llvm_emit_polygon_stipple(ctx, list, pos);
8181 }
8182
8183 if (key->ps_prolog.states.bc_optimize_for_persp ||
8184 key->ps_prolog.states.bc_optimize_for_linear) {
8185 unsigned i, base = key->ps_prolog.num_input_sgprs;
8186 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8187
8188 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8189 * The hw doesn't compute CENTROID if the whole wave only
8190 * contains fully-covered quads.
8191 *
8192 * PRIM_MASK is after user SGPRs.
8193 */
8194 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8195 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8196 LLVMConstInt(ctx->i32, 31, 0), "");
8197 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8198 ctx->i1, "");
8199
8200 if (key->ps_prolog.states.bc_optimize_for_persp) {
8201 /* Read PERSP_CENTER. */
8202 for (i = 0; i < 2; i++)
8203 center[i] = LLVMGetParam(func, base + 2 + i);
8204 /* Read PERSP_CENTROID. */
8205 for (i = 0; i < 2; i++)
8206 centroid[i] = LLVMGetParam(func, base + 4 + i);
8207 /* Select PERSP_CENTROID. */
8208 for (i = 0; i < 2; i++) {
8209 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8210 center[i], centroid[i], "");
8211 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8212 tmp, base + 4 + i, "");
8213 }
8214 }
8215 if (key->ps_prolog.states.bc_optimize_for_linear) {
8216 /* Read LINEAR_CENTER. */
8217 for (i = 0; i < 2; i++)
8218 center[i] = LLVMGetParam(func, base + 8 + i);
8219 /* Read LINEAR_CENTROID. */
8220 for (i = 0; i < 2; i++)
8221 centroid[i] = LLVMGetParam(func, base + 10 + i);
8222 /* Select LINEAR_CENTROID. */
8223 for (i = 0; i < 2; i++) {
8224 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8225 center[i], centroid[i], "");
8226 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8227 tmp, base + 10 + i, "");
8228 }
8229 }
8230 }
8231
8232 /* Force per-sample interpolation. */
8233 if (key->ps_prolog.states.force_persp_sample_interp) {
8234 unsigned i, base = key->ps_prolog.num_input_sgprs;
8235 LLVMValueRef persp_sample[2];
8236
8237 /* Read PERSP_SAMPLE. */
8238 for (i = 0; i < 2; i++)
8239 persp_sample[i] = LLVMGetParam(func, base + i);
8240 /* Overwrite PERSP_CENTER. */
8241 for (i = 0; i < 2; i++)
8242 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8243 persp_sample[i], base + 2 + i, "");
8244 /* Overwrite PERSP_CENTROID. */
8245 for (i = 0; i < 2; i++)
8246 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8247 persp_sample[i], base + 4 + i, "");
8248 }
8249 if (key->ps_prolog.states.force_linear_sample_interp) {
8250 unsigned i, base = key->ps_prolog.num_input_sgprs;
8251 LLVMValueRef linear_sample[2];
8252
8253 /* Read LINEAR_SAMPLE. */
8254 for (i = 0; i < 2; i++)
8255 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8256 /* Overwrite LINEAR_CENTER. */
8257 for (i = 0; i < 2; i++)
8258 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8259 linear_sample[i], base + 8 + i, "");
8260 /* Overwrite LINEAR_CENTROID. */
8261 for (i = 0; i < 2; i++)
8262 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8263 linear_sample[i], base + 10 + i, "");
8264 }
8265
8266 /* Force center interpolation. */
8267 if (key->ps_prolog.states.force_persp_center_interp) {
8268 unsigned i, base = key->ps_prolog.num_input_sgprs;
8269 LLVMValueRef persp_center[2];
8270
8271 /* Read PERSP_CENTER. */
8272 for (i = 0; i < 2; i++)
8273 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8274 /* Overwrite PERSP_SAMPLE. */
8275 for (i = 0; i < 2; i++)
8276 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8277 persp_center[i], base + i, "");
8278 /* Overwrite PERSP_CENTROID. */
8279 for (i = 0; i < 2; i++)
8280 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8281 persp_center[i], base + 4 + i, "");
8282 }
8283 if (key->ps_prolog.states.force_linear_center_interp) {
8284 unsigned i, base = key->ps_prolog.num_input_sgprs;
8285 LLVMValueRef linear_center[2];
8286
8287 /* Read LINEAR_CENTER. */
8288 for (i = 0; i < 2; i++)
8289 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8290 /* Overwrite LINEAR_SAMPLE. */
8291 for (i = 0; i < 2; i++)
8292 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8293 linear_center[i], base + 6 + i, "");
8294 /* Overwrite LINEAR_CENTROID. */
8295 for (i = 0; i < 2; i++)
8296 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8297 linear_center[i], base + 10 + i, "");
8298 }
8299
8300 /* Interpolate colors. */
8301 for (i = 0; i < 2; i++) {
8302 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8303 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8304 key->ps_prolog.face_vgpr_index;
8305 LLVMValueRef interp[2], color[4];
8306 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8307
8308 if (!writemask)
8309 continue;
8310
8311 /* If the interpolation qualifier is not CONSTANT (-1). */
8312 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8313 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8314 key->ps_prolog.color_interp_vgpr_index[i];
8315
8316 /* Get the (i,j) updated by bc_optimize handling. */
8317 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8318 interp_vgpr, "");
8319 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8320 interp_vgpr + 1, "");
8321 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8322 }
8323
8324 /* Use the absolute location of the input. */
8325 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8326
8327 if (key->ps_prolog.states.color_two_side) {
8328 face = LLVMGetParam(func, face_vgpr);
8329 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8330 }
8331
8332 interp_fs_input(ctx,
8333 key->ps_prolog.color_attr_index[i],
8334 TGSI_SEMANTIC_COLOR, i,
8335 key->ps_prolog.num_interp_inputs,
8336 key->ps_prolog.colors_read, interp_ij,
8337 prim_mask, face, color);
8338
8339 while (writemask) {
8340 unsigned chan = u_bit_scan(&writemask);
8341 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8342 num_params++, "");
8343 }
8344 }
8345
8346 /* Tell LLVM to insert WQM instruction sequence when needed. */
8347 if (key->ps_prolog.wqm) {
8348 LLVMAddTargetDependentFunctionAttr(func,
8349 "amdgpu-ps-wqm-outputs", "");
8350 }
8351
8352 si_llvm_build_ret(ctx, ret);
8353 }
8354
8355 /**
8356 * Build the pixel shader epilog function. This handles everything that must be
8357 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8358 */
8359 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8360 union si_shader_part_key *key)
8361 {
8362 struct gallivm_state *gallivm = &ctx->gallivm;
8363 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8364 LLVMTypeRef params[16+8*4+3];
8365 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8366 int last_sgpr, num_params, i;
8367 struct si_ps_exports exp = {};
8368
8369 /* Declare input SGPRs. */
8370 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8371 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8372 params[SI_PARAM_SAMPLERS] = ctx->i64;
8373 params[SI_PARAM_IMAGES] = ctx->i64;
8374 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8375 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8376 last_sgpr = SI_PARAM_ALPHA_REF;
8377
8378 /* Declare input VGPRs. */
8379 num_params = (last_sgpr + 1) +
8380 util_bitcount(key->ps_epilog.colors_written) * 4 +
8381 key->ps_epilog.writes_z +
8382 key->ps_epilog.writes_stencil +
8383 key->ps_epilog.writes_samplemask;
8384
8385 num_params = MAX2(num_params,
8386 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8387
8388 assert(num_params <= ARRAY_SIZE(params));
8389
8390 for (i = last_sgpr + 1; i < num_params; i++)
8391 params[i] = ctx->f32;
8392
8393 /* Create the function. */
8394 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8395 /* Disable elimination of unused inputs. */
8396 si_llvm_add_attribute(ctx->main_fn,
8397 "InitialPSInputAddr", 0xffffff);
8398
8399 /* Process colors. */
8400 unsigned vgpr = last_sgpr + 1;
8401 unsigned colors_written = key->ps_epilog.colors_written;
8402 int last_color_export = -1;
8403
8404 /* Find the last color export. */
8405 if (!key->ps_epilog.writes_z &&
8406 !key->ps_epilog.writes_stencil &&
8407 !key->ps_epilog.writes_samplemask) {
8408 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8409
8410 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8411 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8412 /* Just set this if any of the colorbuffers are enabled. */
8413 if (spi_format &
8414 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8415 last_color_export = 0;
8416 } else {
8417 for (i = 0; i < 8; i++)
8418 if (colors_written & (1 << i) &&
8419 (spi_format >> (i * 4)) & 0xf)
8420 last_color_export = i;
8421 }
8422 }
8423
8424 while (colors_written) {
8425 LLVMValueRef color[4];
8426 int mrt = u_bit_scan(&colors_written);
8427
8428 for (i = 0; i < 4; i++)
8429 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8430
8431 si_export_mrt_color(bld_base, color, mrt,
8432 num_params - 1,
8433 mrt == last_color_export, &exp);
8434 }
8435
8436 /* Process depth, stencil, samplemask. */
8437 if (key->ps_epilog.writes_z)
8438 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8439 if (key->ps_epilog.writes_stencil)
8440 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8441 if (key->ps_epilog.writes_samplemask)
8442 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8443
8444 if (depth || stencil || samplemask)
8445 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8446 else if (last_color_export == -1)
8447 si_export_null(bld_base);
8448
8449 if (exp.num)
8450 si_emit_ps_exports(ctx, &exp);
8451
8452 /* Compile. */
8453 LLVMBuildRetVoid(gallivm->builder);
8454 }
8455
8456 /**
8457 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8458 */
8459 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8460 LLVMTargetMachineRef tm,
8461 struct si_shader *shader,
8462 struct pipe_debug_callback *debug)
8463 {
8464 union si_shader_part_key prolog_key;
8465 union si_shader_part_key epilog_key;
8466
8467 /* Get the prolog. */
8468 si_get_ps_prolog_key(shader, &prolog_key, true);
8469
8470 /* The prolog is a no-op if these aren't set. */
8471 if (si_need_ps_prolog(&prolog_key)) {
8472 shader->prolog =
8473 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8474 PIPE_SHADER_FRAGMENT, true,
8475 &prolog_key, tm, debug,
8476 si_build_ps_prolog_function,
8477 "Fragment Shader Prolog");
8478 if (!shader->prolog)
8479 return false;
8480 }
8481
8482 /* Get the epilog. */
8483 si_get_ps_epilog_key(shader, &epilog_key);
8484
8485 shader->epilog =
8486 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8487 PIPE_SHADER_FRAGMENT, false,
8488 &epilog_key, tm, debug,
8489 si_build_ps_epilog_function,
8490 "Fragment Shader Epilog");
8491 if (!shader->epilog)
8492 return false;
8493
8494 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8495 if (shader->key.part.ps.prolog.poly_stipple) {
8496 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8497 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8498 }
8499
8500 /* Set up the enable bits for per-sample shading if needed. */
8501 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8502 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8503 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8504 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8505 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8506 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8507 }
8508 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8509 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8510 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8511 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8512 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8513 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8514 }
8515 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8516 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8517 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8518 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8519 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8520 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8521 }
8522 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8523 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8524 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8525 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8526 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8527 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8528 }
8529
8530 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8531 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8532 !(shader->config.spi_ps_input_ena & 0xf)) {
8533 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8534 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8535 }
8536
8537 /* At least one pair of interpolation weights must be enabled. */
8538 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8539 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8540 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8541 }
8542
8543 /* The sample mask input is always enabled, because the API shader always
8544 * passes it through to the epilog. Disable it here if it's unused.
8545 */
8546 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8547 !shader->selector->info.reads_samplemask)
8548 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8549
8550 return true;
8551 }
8552
8553 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8554 unsigned *lds_size)
8555 {
8556 /* SPI barrier management bug:
8557 * Make sure we have at least 4k of LDS in use to avoid the bug.
8558 * It applies to workgroup sizes of more than one wavefront.
8559 */
8560 if (sscreen->b.family == CHIP_BONAIRE ||
8561 sscreen->b.family == CHIP_KABINI ||
8562 sscreen->b.family == CHIP_MULLINS)
8563 *lds_size = MAX2(*lds_size, 8);
8564 }
8565
8566 static void si_fix_resource_usage(struct si_screen *sscreen,
8567 struct si_shader *shader)
8568 {
8569 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8570
8571 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8572
8573 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8574 si_get_max_workgroup_size(shader) > 64) {
8575 si_multiwave_lds_size_workaround(sscreen,
8576 &shader->config.lds_size);
8577 }
8578 }
8579
8580 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8581 struct si_shader *shader,
8582 struct pipe_debug_callback *debug)
8583 {
8584 struct si_shader_selector *sel = shader->selector;
8585 struct si_shader *mainp = sel->main_shader_part;
8586 int r;
8587
8588 /* LS, ES, VS are compiled on demand if the main part hasn't been
8589 * compiled for that stage.
8590 *
8591 * Vertex shaders are compiled on demand when a vertex fetch
8592 * workaround must be applied.
8593 */
8594 if (shader->is_monolithic) {
8595 /* Monolithic shader (compiled as a whole, has many variants,
8596 * may take a long time to compile).
8597 */
8598 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8599 if (r)
8600 return r;
8601 } else {
8602 /* The shader consists of 2-3 parts:
8603 *
8604 * - the middle part is the user shader, it has 1 variant only
8605 * and it was compiled during the creation of the shader
8606 * selector
8607 * - the prolog part is inserted at the beginning
8608 * - the epilog part is inserted at the end
8609 *
8610 * The prolog and epilog have many (but simple) variants.
8611 */
8612
8613 /* Copy the compiled TGSI shader data over. */
8614 shader->is_binary_shared = true;
8615 shader->binary = mainp->binary;
8616 shader->config = mainp->config;
8617 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8618 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8619 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8620 memcpy(shader->info.vs_output_param_offset,
8621 mainp->info.vs_output_param_offset,
8622 sizeof(mainp->info.vs_output_param_offset));
8623 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8624 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8625 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8626
8627 /* Select prologs and/or epilogs. */
8628 switch (sel->type) {
8629 case PIPE_SHADER_VERTEX:
8630 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8631 return -1;
8632 break;
8633 case PIPE_SHADER_TESS_CTRL:
8634 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8635 return -1;
8636 break;
8637 case PIPE_SHADER_TESS_EVAL:
8638 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8639 return -1;
8640 break;
8641 case PIPE_SHADER_GEOMETRY:
8642 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8643 return -1;
8644 break;
8645 case PIPE_SHADER_FRAGMENT:
8646 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8647 return -1;
8648
8649 /* Make sure we have at least as many VGPRs as there
8650 * are allocated inputs.
8651 */
8652 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8653 shader->info.num_input_vgprs);
8654 break;
8655 }
8656
8657 /* Update SGPR and VGPR counts. */
8658 if (shader->prolog) {
8659 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8660 shader->prolog->config.num_sgprs);
8661 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8662 shader->prolog->config.num_vgprs);
8663 }
8664 if (shader->epilog) {
8665 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8666 shader->epilog->config.num_sgprs);
8667 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8668 shader->epilog->config.num_vgprs);
8669 }
8670 }
8671
8672 si_fix_resource_usage(sscreen, shader);
8673 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8674 stderr, true);
8675
8676 /* Upload. */
8677 r = si_shader_binary_upload(sscreen, shader);
8678 if (r) {
8679 fprintf(stderr, "LLVM failed to upload shader\n");
8680 return r;
8681 }
8682
8683 return 0;
8684 }
8685
8686 void si_shader_destroy(struct si_shader *shader)
8687 {
8688 if (shader->scratch_bo)
8689 r600_resource_reference(&shader->scratch_bo, NULL);
8690
8691 r600_resource_reference(&shader->bo, NULL);
8692
8693 if (!shader->is_binary_shared)
8694 radeon_shader_binary_clean(&shader->binary);
8695
8696 free(shader->shader_log);
8697 }