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radeonsi: Fix streamout from geometry shader
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 unsigned usage;
55 };
56
57 struct si_shader_context
58 {
59 struct radeon_llvm_context radeon_bld;
60 struct tgsi_parse_context parse;
61 struct tgsi_token * tokens;
62 struct si_pipe_shader *shader;
63 struct si_shader *gs_for_vs;
64 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
65 int param_streamout_config;
66 int param_streamout_write_index;
67 int param_streamout_offset[4];
68 int param_vertex_id;
69 int param_instance_id;
70 LLVMValueRef const_md;
71 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
72 #if HAVE_LLVM >= 0x0304
73 LLVMValueRef ddxy_lds;
74 #endif
75 LLVMValueRef *constants[NUM_CONST_BUFFERS];
76 LLVMValueRef *resources;
77 LLVMValueRef *samplers;
78 LLVMValueRef so_buffers[4];
79 LLVMValueRef gs_next_vertex;
80 };
81
82 static struct si_shader_context * si_shader_context(
83 struct lp_build_tgsi_context * bld_base)
84 {
85 return (struct si_shader_context *)bld_base;
86 }
87
88
89 #define PERSPECTIVE_BASE 0
90 #define LINEAR_BASE 9
91
92 #define SAMPLE_OFFSET 0
93 #define CENTER_OFFSET 2
94 #define CENTROID_OFSET 4
95
96 #define USE_SGPR_MAX_SUFFIX_LEN 5
97 #define CONST_ADDR_SPACE 2
98 #define LOCAL_ADDR_SPACE 3
99 #define USER_SGPR_ADDR_SPACE 8
100
101
102 #define SENDMSG_GS 2
103 #define SENDMSG_GS_DONE 3
104
105 #define SENDMSG_GS_OP_NOP (0 << 4)
106 #define SENDMSG_GS_OP_CUT (1 << 4)
107 #define SENDMSG_GS_OP_EMIT (2 << 4)
108 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
109
110
111 /**
112 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
113 *
114 * @param offset The offset parameter specifies the number of
115 * elements to offset, not the number of bytes or dwords. An element is the
116 * the type pointed to by the base_ptr parameter (e.g. int is the element of
117 * an int* pointer)
118 *
119 * When LLVM lowers the load instruction, it will convert the element offset
120 * into a dword offset automatically.
121 *
122 */
123 static LLVMValueRef build_indexed_load(
124 struct si_shader_context * si_shader_ctx,
125 LLVMValueRef base_ptr,
126 LLVMValueRef offset)
127 {
128 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
129
130 LLVMValueRef indices[2] = {
131 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
132 offset
133 };
134 LLVMValueRef computed_ptr = LLVMBuildGEP(
135 base->gallivm->builder, base_ptr, indices, 2, "");
136
137 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
138 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
139 return result;
140 }
141
142 static LLVMValueRef get_instance_index_for_fetch(
143 struct radeon_llvm_context * radeon_bld,
144 unsigned divisor)
145 {
146 struct si_shader_context *si_shader_ctx =
147 si_shader_context(&radeon_bld->soa.bld_base);
148 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
149
150 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
151 si_shader_ctx->param_instance_id);
152 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
153 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
154
155 if (divisor > 1)
156 result = LLVMBuildUDiv(gallivm->builder, result,
157 lp_build_const_int32(gallivm, divisor), "");
158
159 return result;
160 }
161
162 static int si_store_shader_io_attribs(struct si_shader *shader,
163 const struct tgsi_full_declaration *d)
164 {
165 int i = -1;
166
167 switch (d->Declaration.File) {
168 case TGSI_FILE_INPUT:
169 i = shader->ninput++;
170 assert(i < Elements(shader->input));
171 shader->input[i].name = d->Semantic.Name;
172 shader->input[i].sid = d->Semantic.Index;
173 shader->input[i].index = d->Range.First;
174 shader->input[i].interpolate = d->Interp.Interpolate;
175 shader->input[i].centroid = d->Interp.Centroid;
176 return -1;
177
178 case TGSI_FILE_OUTPUT:
179 i = shader->noutput++;
180 assert(i < Elements(shader->output));
181 shader->output[i].name = d->Semantic.Name;
182 shader->output[i].sid = d->Semantic.Index;
183 shader->output[i].index = d->Range.First;
184 shader->output[i].usage = d->Declaration.UsageMask;
185 break;
186 }
187
188 return i;
189 }
190
191 static void declare_input_vs(
192 struct radeon_llvm_context *radeon_bld,
193 unsigned input_index,
194 const struct tgsi_full_declaration *decl)
195 {
196 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
197 struct gallivm_state *gallivm = base->gallivm;
198 struct si_shader_context *si_shader_ctx =
199 si_shader_context(&radeon_bld->soa.bld_base);
200 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
201
202 unsigned chan;
203
204 LLVMValueRef t_list_ptr;
205 LLVMValueRef t_offset;
206 LLVMValueRef t_list;
207 LLVMValueRef attribute_offset;
208 LLVMValueRef buffer_index;
209 LLVMValueRef args[3];
210 LLVMTypeRef vec4_type;
211 LLVMValueRef input;
212
213 /* Load the T list */
214 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
215
216 t_offset = lp_build_const_int32(gallivm, input_index);
217
218 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
219
220 /* Build the attribute offset */
221 attribute_offset = lp_build_const_int32(gallivm, 0);
222
223 if (divisor) {
224 /* Build index from instance ID, start instance and divisor */
225 si_shader_ctx->shader->shader.uses_instanceid = true;
226 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
227 } else {
228 /* Load the buffer index, which is always stored in VGPR0
229 * for Vertex Shaders */
230 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
231 si_shader_ctx->param_vertex_id);
232 }
233
234 vec4_type = LLVMVectorType(base->elem_type, 4);
235 args[0] = t_list;
236 args[1] = attribute_offset;
237 args[2] = buffer_index;
238 input = build_intrinsic(gallivm->builder,
239 "llvm.SI.vs.load.input", vec4_type, args, 3,
240 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
241
242 /* Break up the vec4 into individual components */
243 for (chan = 0; chan < 4; chan++) {
244 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
245 /* XXX: Use a helper function for this. There is one in
246 * tgsi_llvm.c. */
247 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
248 LLVMBuildExtractElement(gallivm->builder,
249 input, llvm_chan, "");
250 }
251 }
252
253 static void declare_input_gs(
254 struct radeon_llvm_context *radeon_bld,
255 unsigned input_index,
256 const struct tgsi_full_declaration *decl)
257 {
258 struct si_shader_context *si_shader_ctx =
259 si_shader_context(&radeon_bld->soa.bld_base);
260 struct si_shader *shader = &si_shader_ctx->shader->shader;
261
262 si_store_shader_io_attribs(shader, decl);
263
264 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID)
265 shader->input[input_index].param_offset = shader->nparam++;
266 }
267
268 static LLVMValueRef fetch_input_gs(
269 struct lp_build_tgsi_context *bld_base,
270 const struct tgsi_full_src_register *reg,
271 enum tgsi_opcode_type type,
272 unsigned swizzle)
273 {
274 struct lp_build_context *base = &bld_base->base;
275 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
276 struct si_shader *shader = &si_shader_ctx->shader->shader;
277 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
278 struct gallivm_state *gallivm = base->gallivm;
279 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
280 LLVMValueRef vtx_offset;
281 LLVMValueRef t_list_ptr;
282 LLVMValueRef t_list;
283 LLVMValueRef args[9];
284 unsigned vtx_offset_param;
285
286 if (swizzle != ~0 &&
287 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
288 if (swizzle == 0)
289 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
290 SI_PARAM_PRIMITIVE_ID);
291 else
292 return uint->zero;
293 }
294
295 if (!reg->Register.Dimension)
296 return NULL;
297
298 if (swizzle == ~0) {
299 LLVMValueRef values[TGSI_NUM_CHANNELS];
300 unsigned chan;
301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
302 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
303 }
304 return lp_build_gather_values(bld_base->base.gallivm, values,
305 TGSI_NUM_CHANNELS);
306 }
307
308 /* Get the vertex offset parameter */
309 vtx_offset_param = reg->Dimension.Index;
310 if (vtx_offset_param < 2) {
311 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
312 } else {
313 assert(vtx_offset_param < 6);
314 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
315 }
316 vtx_offset = lp_build_mul_imm(uint,
317 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
318 vtx_offset_param),
319 4);
320
321 /* Load the ESGS ring resource descriptor */
322 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
323 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
324 lp_build_const_int32(gallivm,
325 NUM_PIPE_CONST_BUFFERS + 1));
326
327 args[0] = t_list;
328 args[1] = vtx_offset;
329 args[2] = lp_build_const_int32(gallivm,
330 ((shader->input[reg->Register.Index].param_offset * 4) +
331 swizzle) * 256);
332 args[3] = uint->zero;
333 args[4] = uint->one; /* OFFEN */
334 args[5] = uint->zero; /* IDXEN */
335 args[6] = uint->one; /* GLC */
336 args[7] = uint->zero; /* SLC */
337 args[8] = uint->zero; /* TFE */
338
339 return LLVMBuildBitCast(gallivm->builder,
340 build_intrinsic(gallivm->builder,
341 "llvm.SI.buffer.load.dword.i32.i32",
342 i32, args, 9,
343 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
344 tgsi2llvmtype(bld_base, type), "");
345 }
346
347 static void declare_input_fs(
348 struct radeon_llvm_context *radeon_bld,
349 unsigned input_index,
350 const struct tgsi_full_declaration *decl)
351 {
352 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
353 struct si_shader_context *si_shader_ctx =
354 si_shader_context(&radeon_bld->soa.bld_base);
355 struct si_shader *shader = &si_shader_ctx->shader->shader;
356 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
357 struct gallivm_state *gallivm = base->gallivm;
358 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
359 LLVMValueRef main_fn = radeon_bld->main_fn;
360
361 LLVMValueRef interp_param;
362 const char * intr_name;
363
364 /* This value is:
365 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
366 * quad begins a new primitive. Bit 0 always needs
367 * to be unset)
368 * [32:16] ParamOffset
369 *
370 */
371 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
372 LLVMValueRef attr_number;
373
374 unsigned chan;
375
376 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
377 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
378 unsigned soa_index =
379 radeon_llvm_reg_index_soa(input_index, chan);
380 radeon_bld->inputs[soa_index] =
381 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
382
383 if (chan == 3)
384 /* RCP for fragcoord.w */
385 radeon_bld->inputs[soa_index] =
386 LLVMBuildFDiv(gallivm->builder,
387 lp_build_const_float(gallivm, 1.0f),
388 radeon_bld->inputs[soa_index],
389 "");
390 }
391 return;
392 }
393
394 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
395 LLVMValueRef face, is_face_positive;
396
397 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
398
399 is_face_positive = LLVMBuildFCmp(gallivm->builder,
400 LLVMRealUGT, face,
401 lp_build_const_float(gallivm, 0.0f),
402 "");
403
404 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
405 LLVMBuildSelect(gallivm->builder,
406 is_face_positive,
407 lp_build_const_float(gallivm, 1.0f),
408 lp_build_const_float(gallivm, 0.0f),
409 "");
410 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
411 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
412 lp_build_const_float(gallivm, 0.0f);
413 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
414 lp_build_const_float(gallivm, 1.0f);
415
416 return;
417 }
418
419 shader->input[input_index].param_offset = shader->nparam++;
420 attr_number = lp_build_const_int32(gallivm,
421 shader->input[input_index].param_offset);
422
423 switch (decl->Interp.Interpolate) {
424 case TGSI_INTERPOLATE_COLOR:
425 if (si_shader_ctx->shader->key.ps.flatshade) {
426 interp_param = 0;
427 } else {
428 if (decl->Interp.Centroid)
429 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
430 else
431 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
432 }
433 break;
434 case TGSI_INTERPOLATE_CONSTANT:
435 interp_param = 0;
436 break;
437 case TGSI_INTERPOLATE_LINEAR:
438 if (decl->Interp.Centroid)
439 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
440 else
441 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
442 break;
443 case TGSI_INTERPOLATE_PERSPECTIVE:
444 if (decl->Interp.Centroid)
445 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
446 else
447 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
448 break;
449 default:
450 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
451 return;
452 }
453
454 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
455
456 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
457 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
458 si_shader_ctx->shader->key.ps.color_two_side) {
459 LLVMValueRef args[4];
460 LLVMValueRef face, is_face_positive;
461 LLVMValueRef back_attr_number =
462 lp_build_const_int32(gallivm,
463 shader->input[input_index].param_offset + 1);
464
465 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
466
467 is_face_positive = LLVMBuildFCmp(gallivm->builder,
468 LLVMRealUGT, face,
469 lp_build_const_float(gallivm, 0.0f),
470 "");
471
472 args[2] = params;
473 args[3] = interp_param;
474 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
475 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
476 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
477 LLVMValueRef front, back;
478
479 args[0] = llvm_chan;
480 args[1] = attr_number;
481 front = build_intrinsic(gallivm->builder, intr_name,
482 input_type, args, args[3] ? 4 : 3,
483 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
484
485 args[1] = back_attr_number;
486 back = build_intrinsic(gallivm->builder, intr_name,
487 input_type, args, args[3] ? 4 : 3,
488 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
489
490 radeon_bld->inputs[soa_index] =
491 LLVMBuildSelect(gallivm->builder,
492 is_face_positive,
493 front,
494 back,
495 "");
496 }
497
498 shader->nparam++;
499 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
500 LLVMValueRef args[4];
501
502 args[0] = uint->zero;
503 args[1] = attr_number;
504 args[2] = params;
505 args[3] = interp_param;
506 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
507 build_intrinsic(gallivm->builder, intr_name,
508 input_type, args, args[3] ? 4 : 3,
509 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
511 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
512 lp_build_const_float(gallivm, 0.0f);
513 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
514 lp_build_const_float(gallivm, 1.0f);
515 } else {
516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
517 LLVMValueRef args[4];
518 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
519 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
520 args[0] = llvm_chan;
521 args[1] = attr_number;
522 args[2] = params;
523 args[3] = interp_param;
524 radeon_bld->inputs[soa_index] =
525 build_intrinsic(gallivm->builder, intr_name,
526 input_type, args, args[3] ? 4 : 3,
527 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
528 }
529 }
530 }
531
532 static void declare_system_value(
533 struct radeon_llvm_context * radeon_bld,
534 unsigned index,
535 const struct tgsi_full_declaration *decl)
536 {
537 struct si_shader_context *si_shader_ctx =
538 si_shader_context(&radeon_bld->soa.bld_base);
539 LLVMValueRef value = 0;
540
541 switch (decl->Semantic.Name) {
542 case TGSI_SEMANTIC_INSTANCEID:
543 value = LLVMGetParam(radeon_bld->main_fn,
544 si_shader_ctx->param_instance_id);
545 break;
546
547 case TGSI_SEMANTIC_VERTEXID:
548 value = LLVMGetParam(radeon_bld->main_fn,
549 si_shader_ctx->param_vertex_id);
550 break;
551
552 default:
553 assert(!"unknown system value");
554 return;
555 }
556
557 radeon_bld->system_values[index] = value;
558 }
559
560 static LLVMValueRef fetch_constant(
561 struct lp_build_tgsi_context * bld_base,
562 const struct tgsi_full_src_register *reg,
563 enum tgsi_opcode_type type,
564 unsigned swizzle)
565 {
566 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
567 struct lp_build_context * base = &bld_base->base;
568 const struct tgsi_ind_register *ireg = &reg->Indirect;
569 unsigned buf, idx;
570
571 LLVMValueRef args[2];
572 LLVMValueRef addr;
573 LLVMValueRef result;
574
575 if (swizzle == LP_CHAN_ALL) {
576 unsigned chan;
577 LLVMValueRef values[4];
578 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
579 values[chan] = fetch_constant(bld_base, reg, type, chan);
580
581 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
582 }
583
584 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
585 idx = reg->Register.Index * 4 + swizzle;
586
587 if (!reg->Register.Indirect)
588 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
589
590 args[0] = si_shader_ctx->const_resource[buf];
591 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
592 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
593 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
594 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
595 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
596
597 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
598 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
599
600 return bitcast(bld_base, type, result);
601 }
602
603 /* Initialize arguments for the shader export intrinsic */
604 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
605 LLVMValueRef *values,
606 unsigned target,
607 LLVMValueRef *args)
608 {
609 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
610 struct lp_build_context *uint =
611 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
612 struct lp_build_context *base = &bld_base->base;
613 unsigned compressed = 0;
614 unsigned chan;
615
616 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
617 int cbuf = target - V_008DFC_SQ_EXP_MRT;
618
619 if (cbuf >= 0 && cbuf < 8) {
620 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
621
622 if (compressed)
623 si_shader_ctx->shader->spi_shader_col_format |=
624 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
625 else
626 si_shader_ctx->shader->spi_shader_col_format |=
627 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
628
629 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
630 }
631 }
632
633 if (compressed) {
634 /* Pixel shader needs to pack output values before export */
635 for (chan = 0; chan < 2; chan++ ) {
636 args[0] = values[2 * chan];
637 args[1] = values[2 * chan + 1];
638 args[chan + 5] =
639 build_intrinsic(base->gallivm->builder,
640 "llvm.SI.packf16",
641 LLVMInt32TypeInContext(base->gallivm->context),
642 args, 2,
643 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
644 args[chan + 7] = args[chan + 5] =
645 LLVMBuildBitCast(base->gallivm->builder,
646 args[chan + 5],
647 LLVMFloatTypeInContext(base->gallivm->context),
648 "");
649 }
650
651 /* Set COMPR flag */
652 args[4] = uint->one;
653 } else {
654 for (chan = 0; chan < 4; chan++ )
655 /* +5 because the first output value will be
656 * the 6th argument to the intrinsic. */
657 args[chan + 5] = values[chan];
658
659 /* Clear COMPR flag */
660 args[4] = uint->zero;
661 }
662
663 /* XXX: This controls which components of the output
664 * registers actually get exported. (e.g bit 0 means export
665 * X component, bit 1 means export Y component, etc.) I'm
666 * hard coding this to 0xf for now. In the future, we might
667 * want to do something else. */
668 args[0] = lp_build_const_int32(base->gallivm, 0xf);
669
670 /* Specify whether the EXEC mask represents the valid mask */
671 args[1] = uint->zero;
672
673 /* Specify whether this is the last export */
674 args[2] = uint->zero;
675
676 /* Specify the target we are exporting */
677 args[3] = lp_build_const_int32(base->gallivm, target);
678
679 /* XXX: We probably need to keep track of the output
680 * values, so we know what we are passing to the next
681 * stage. */
682 }
683
684 /* Load from output pointers and initialize arguments for the shader export intrinsic */
685 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
686 LLVMValueRef *out_ptr,
687 unsigned target,
688 LLVMValueRef *args)
689 {
690 struct gallivm_state *gallivm = bld_base->base.gallivm;
691 LLVMValueRef values[4];
692 int i;
693
694 for (i = 0; i < 4; i++)
695 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
696
697 si_llvm_init_export_args(bld_base, values, target, args);
698 }
699
700 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
701 LLVMValueRef *out_ptr)
702 {
703 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
704 struct gallivm_state *gallivm = bld_base->base.gallivm;
705
706 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
707 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
708 SI_PARAM_ALPHA_REF);
709
710 LLVMValueRef alpha_pass =
711 lp_build_cmp(&bld_base->base,
712 si_shader_ctx->shader->key.ps.alpha_func,
713 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
714 alpha_ref);
715 LLVMValueRef arg =
716 lp_build_select(&bld_base->base,
717 alpha_pass,
718 lp_build_const_float(gallivm, 1.0f),
719 lp_build_const_float(gallivm, -1.0f));
720
721 build_intrinsic(gallivm->builder,
722 "llvm.AMDGPU.kill",
723 LLVMVoidTypeInContext(gallivm->context),
724 &arg, 1, 0);
725 } else {
726 build_intrinsic(gallivm->builder,
727 "llvm.AMDGPU.kilp",
728 LLVMVoidTypeInContext(gallivm->context),
729 NULL, 0, 0);
730 }
731 }
732
733 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
734 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
735 {
736 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
737 struct si_pipe_shader *shader = si_shader_ctx->shader;
738 struct lp_build_context *base = &bld_base->base;
739 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
740 unsigned reg_index;
741 unsigned chan;
742 unsigned const_chan;
743 LLVMValueRef base_elt;
744 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
745 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
746 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
747
748 for (reg_index = 0; reg_index < 2; reg_index ++) {
749 LLVMValueRef *args = pos[2 + reg_index];
750
751 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
752 continue;
753
754 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
755
756 args[5] =
757 args[6] =
758 args[7] =
759 args[8] = lp_build_const_float(base->gallivm, 0.0f);
760
761 /* Compute dot products of position and user clip plane vectors */
762 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
763 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
764 args[0] = const_resource;
765 args[1] = lp_build_const_int32(base->gallivm,
766 ((reg_index * 4 + chan) * 4 +
767 const_chan) * 4);
768 base_elt = build_intrinsic(base->gallivm->builder,
769 "llvm.SI.load.const",
770 base->elem_type,
771 args, 2,
772 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
773 args[5 + chan] =
774 lp_build_add(base, args[5 + chan],
775 lp_build_mul(base, base_elt,
776 out_elts[const_chan]));
777 }
778 }
779
780 args[0] = lp_build_const_int32(base->gallivm, 0xf);
781 args[1] = uint->zero;
782 args[2] = uint->zero;
783 args[3] = lp_build_const_int32(base->gallivm,
784 V_008DFC_SQ_EXP_POS + 2 + reg_index);
785 args[4] = uint->zero;
786 }
787 }
788
789 static void si_dump_streamout(struct pipe_stream_output_info *so)
790 {
791 unsigned i;
792
793 if (so->num_outputs)
794 fprintf(stderr, "STREAMOUT\n");
795
796 for (i = 0; i < so->num_outputs; i++) {
797 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
798 so->output[i].start_component;
799 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
800 i, so->output[i].output_buffer,
801 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
802 so->output[i].register_index,
803 mask & 1 ? "x" : "",
804 mask & 2 ? "y" : "",
805 mask & 4 ? "z" : "",
806 mask & 8 ? "w" : "");
807 }
808 }
809
810 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
811 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
812 * or v4i32 (num_channels=3,4). */
813 static void build_tbuffer_store(struct si_shader_context *shader,
814 LLVMValueRef rsrc,
815 LLVMValueRef vdata,
816 unsigned num_channels,
817 LLVMValueRef vaddr,
818 LLVMValueRef soffset,
819 unsigned inst_offset,
820 unsigned dfmt,
821 unsigned nfmt,
822 unsigned offen,
823 unsigned idxen,
824 unsigned glc,
825 unsigned slc,
826 unsigned tfe)
827 {
828 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
829 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
830 LLVMValueRef args[] = {
831 rsrc,
832 vdata,
833 LLVMConstInt(i32, num_channels, 0),
834 vaddr,
835 soffset,
836 LLVMConstInt(i32, inst_offset, 0),
837 LLVMConstInt(i32, dfmt, 0),
838 LLVMConstInt(i32, nfmt, 0),
839 LLVMConstInt(i32, offen, 0),
840 LLVMConstInt(i32, idxen, 0),
841 LLVMConstInt(i32, glc, 0),
842 LLVMConstInt(i32, slc, 0),
843 LLVMConstInt(i32, tfe, 0)
844 };
845
846 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
847 unsigned func = CLAMP(num_channels, 1, 3) - 1;
848 const char *types[] = {"i32", "v2i32", "v4i32"};
849 char name[256];
850 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
851
852 lp_build_intrinsic(gallivm->builder, name,
853 LLVMVoidTypeInContext(gallivm->context),
854 args, Elements(args));
855 }
856
857 static void build_streamout_store(struct si_shader_context *shader,
858 LLVMValueRef rsrc,
859 LLVMValueRef vdata,
860 unsigned num_channels,
861 LLVMValueRef vaddr,
862 LLVMValueRef soffset,
863 unsigned inst_offset)
864 {
865 static unsigned dfmt[] = {
866 V_008F0C_BUF_DATA_FORMAT_32,
867 V_008F0C_BUF_DATA_FORMAT_32_32,
868 V_008F0C_BUF_DATA_FORMAT_32_32_32,
869 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
870 };
871 assert(num_channels >= 1 && num_channels <= 4);
872
873 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
874 inst_offset, dfmt[num_channels-1],
875 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
876 }
877
878 /* On SI, the vertex shader is responsible for writing streamout data
879 * to buffers. */
880 static void si_llvm_emit_streamout(struct si_shader_context *shader,
881 struct si_shader_output_values *outputs,
882 unsigned noutput)
883 {
884 struct pipe_stream_output_info *so = &shader->shader->selector->so;
885 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
886 LLVMBuilderRef builder = gallivm->builder;
887 int i, j;
888 struct lp_build_if_state if_ctx;
889
890 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
891
892 LLVMValueRef so_param =
893 LLVMGetParam(shader->radeon_bld.main_fn,
894 shader->param_streamout_config);
895
896 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
897 LLVMValueRef so_vtx_count =
898 LLVMBuildAnd(builder,
899 LLVMBuildLShr(builder, so_param,
900 LLVMConstInt(i32, 16, 0), ""),
901 LLVMConstInt(i32, 127, 0), "");
902
903 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
904 NULL, 0, LLVMReadNoneAttribute);
905
906 /* can_emit = tid < so_vtx_count; */
907 LLVMValueRef can_emit =
908 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
909
910 /* Emit the streamout code conditionally. This actually avoids
911 * out-of-bounds buffer access. The hw tells us via the SGPR
912 * (so_vtx_count) which threads are allowed to emit streamout data. */
913 lp_build_if(&if_ctx, gallivm, can_emit);
914 {
915 /* The buffer offset is computed as follows:
916 * ByteOffset = streamout_offset[buffer_id]*4 +
917 * (streamout_write_index + thread_id)*stride[buffer_id] +
918 * attrib_offset
919 */
920
921 LLVMValueRef so_write_index =
922 LLVMGetParam(shader->radeon_bld.main_fn,
923 shader->param_streamout_write_index);
924
925 /* Compute (streamout_write_index + thread_id). */
926 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
927
928 /* Compute the write offset for each enabled buffer. */
929 LLVMValueRef so_write_offset[4] = {};
930 for (i = 0; i < 4; i++) {
931 if (!so->stride[i])
932 continue;
933
934 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
935 shader->param_streamout_offset[i]);
936 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
937
938 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
939 LLVMConstInt(i32, so->stride[i]*4, 0), "");
940 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
941 }
942
943 /* Write streamout data. */
944 for (i = 0; i < so->num_outputs; i++) {
945 unsigned buf_idx = so->output[i].output_buffer;
946 unsigned reg = so->output[i].register_index;
947 unsigned start = so->output[i].start_component;
948 unsigned num_comps = so->output[i].num_components;
949 LLVMValueRef out[4];
950
951 assert(num_comps && num_comps <= 4);
952 if (!num_comps || num_comps > 4)
953 continue;
954
955 /* Load the output as int. */
956 for (j = 0; j < num_comps; j++) {
957 unsigned outidx = 0;
958
959 while (outidx < noutput && outputs[outidx].index != reg)
960 outidx++;
961
962 if (outidx < noutput)
963 out[j] = LLVMBuildBitCast(builder,
964 outputs[outidx].values[start+j],
965 i32, "");
966 else
967 out[j] = NULL;
968 }
969
970 if (!out[0])
971 continue;
972
973 /* Pack the output. */
974 LLVMValueRef vdata = NULL;
975
976 switch (num_comps) {
977 case 1: /* as i32 */
978 vdata = out[0];
979 break;
980 case 2: /* as v2i32 */
981 case 3: /* as v4i32 (aligned to 4) */
982 case 4: /* as v4i32 */
983 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
984 for (j = 0; j < num_comps; j++) {
985 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
986 LLVMConstInt(i32, j, 0), "");
987 }
988 break;
989 }
990
991 build_streamout_store(shader, shader->so_buffers[buf_idx],
992 vdata, num_comps,
993 so_write_offset[buf_idx],
994 LLVMConstInt(i32, 0, 0),
995 so->output[i].dst_offset*4);
996 }
997 }
998 lp_build_endif(&if_ctx);
999 }
1000
1001
1002 /* Generate export instructions for hardware VS shader stage */
1003 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1004 struct si_shader_output_values *outputs,
1005 unsigned noutput)
1006 {
1007 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1008 struct si_shader * shader = &si_shader_ctx->shader->shader;
1009 struct lp_build_context * base = &bld_base->base;
1010 struct lp_build_context * uint =
1011 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1012 LLVMValueRef args[9];
1013 LLVMValueRef pos_args[4][9] = { { 0 } };
1014 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1015 unsigned semantic_name, semantic_index, semantic_usage;
1016 unsigned target;
1017 unsigned param_count = 0;
1018 unsigned pos_idx;
1019 int i;
1020
1021 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1022 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1023 }
1024
1025 for (i = 0; i < noutput; i++) {
1026 semantic_name = outputs[i].name;
1027 semantic_index = outputs[i].sid;
1028 semantic_usage = outputs[i].usage;
1029
1030 handle_semantic:
1031 /* Select the correct target */
1032 switch(semantic_name) {
1033 case TGSI_SEMANTIC_PSIZE:
1034 shader->vs_out_misc_write = true;
1035 shader->vs_out_point_size = true;
1036 psize_value = outputs[i].values[0];
1037 continue;
1038 case TGSI_SEMANTIC_EDGEFLAG:
1039 shader->vs_out_misc_write = true;
1040 shader->vs_out_edgeflag = true;
1041 edgeflag_value = outputs[i].values[0];
1042 continue;
1043 case TGSI_SEMANTIC_LAYER:
1044 shader->vs_out_misc_write = true;
1045 shader->vs_out_layer = true;
1046 layer_value = outputs[i].values[0];
1047 continue;
1048 case TGSI_SEMANTIC_POSITION:
1049 target = V_008DFC_SQ_EXP_POS;
1050 break;
1051 case TGSI_SEMANTIC_COLOR:
1052 case TGSI_SEMANTIC_BCOLOR:
1053 target = V_008DFC_SQ_EXP_PARAM + param_count;
1054 shader->output[i].param_offset = param_count;
1055 param_count++;
1056 break;
1057 case TGSI_SEMANTIC_CLIPDIST:
1058 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1059 (1 << semantic_index)))
1060 continue;
1061 shader->clip_dist_write |=
1062 semantic_usage << (semantic_index << 2);
1063 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1064 break;
1065 case TGSI_SEMANTIC_CLIPVERTEX:
1066 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1067 continue;
1068 case TGSI_SEMANTIC_PRIMID:
1069 case TGSI_SEMANTIC_FOG:
1070 case TGSI_SEMANTIC_GENERIC:
1071 target = V_008DFC_SQ_EXP_PARAM + param_count;
1072 shader->output[i].param_offset = param_count;
1073 param_count++;
1074 break;
1075 default:
1076 target = 0;
1077 fprintf(stderr,
1078 "Warning: SI unhandled vs output type:%d\n",
1079 semantic_name);
1080 }
1081
1082 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1083
1084 if (target >= V_008DFC_SQ_EXP_POS &&
1085 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1086 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1087 args, sizeof(args));
1088 } else {
1089 lp_build_intrinsic(base->gallivm->builder,
1090 "llvm.SI.export",
1091 LLVMVoidTypeInContext(base->gallivm->context),
1092 args, 9);
1093 }
1094
1095 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1096 semantic_name = TGSI_SEMANTIC_GENERIC;
1097 goto handle_semantic;
1098 }
1099 }
1100
1101 /* We need to add the position output manually if it's missing. */
1102 if (!pos_args[0][0]) {
1103 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1104 pos_args[0][1] = uint->zero; /* EXEC mask */
1105 pos_args[0][2] = uint->zero; /* last export? */
1106 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1107 pos_args[0][4] = uint->zero; /* COMPR flag */
1108 pos_args[0][5] = base->zero; /* X */
1109 pos_args[0][6] = base->zero; /* Y */
1110 pos_args[0][7] = base->zero; /* Z */
1111 pos_args[0][8] = base->one; /* W */
1112 }
1113
1114 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1115 if (shader->vs_out_misc_write) {
1116 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1117 shader->vs_out_point_size |
1118 (shader->vs_out_edgeflag << 1) |
1119 (shader->vs_out_layer << 2));
1120 pos_args[1][1] = uint->zero; /* EXEC mask */
1121 pos_args[1][2] = uint->zero; /* last export? */
1122 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1123 pos_args[1][4] = uint->zero; /* COMPR flag */
1124 pos_args[1][5] = base->zero; /* X */
1125 pos_args[1][6] = base->zero; /* Y */
1126 pos_args[1][7] = base->zero; /* Z */
1127 pos_args[1][8] = base->zero; /* W */
1128
1129 if (shader->vs_out_point_size)
1130 pos_args[1][5] = psize_value;
1131
1132 if (shader->vs_out_edgeflag) {
1133 /* The output is a float, but the hw expects an integer
1134 * with the first bit containing the edge flag. */
1135 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1136 edgeflag_value,
1137 bld_base->uint_bld.elem_type, "");
1138 edgeflag_value = lp_build_min(&bld_base->int_bld,
1139 edgeflag_value,
1140 bld_base->int_bld.one);
1141
1142 /* The LLVM intrinsic expects a float. */
1143 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1144 edgeflag_value,
1145 base->elem_type, "");
1146 }
1147
1148 if (shader->vs_out_layer)
1149 pos_args[1][7] = layer_value;
1150 }
1151
1152 for (i = 0; i < 4; i++)
1153 if (pos_args[i][0])
1154 shader->nr_pos_exports++;
1155
1156 pos_idx = 0;
1157 for (i = 0; i < 4; i++) {
1158 if (!pos_args[i][0])
1159 continue;
1160
1161 /* Specify the target we are exporting */
1162 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1163
1164 if (pos_idx == shader->nr_pos_exports)
1165 /* Specify that this is the last export */
1166 pos_args[i][2] = uint->one;
1167
1168 lp_build_intrinsic(base->gallivm->builder,
1169 "llvm.SI.export",
1170 LLVMVoidTypeInContext(base->gallivm->context),
1171 pos_args[i], 9);
1172 }
1173 }
1174
1175 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1176 {
1177 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1178 struct gallivm_state *gallivm = bld_base->base.gallivm;
1179 struct si_shader *es = &si_shader_ctx->shader->shader;
1180 struct si_shader *gs = si_shader_ctx->gs_for_vs;
1181 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1182 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1183 LLVMValueRef t_list_ptr;
1184 LLVMValueRef t_list;
1185 unsigned chan;
1186 int i;
1187
1188 while (!tgsi_parse_end_of_tokens(parse)) {
1189 struct tgsi_full_declaration *d =
1190 &parse->FullToken.FullDeclaration;
1191
1192 tgsi_parse_token(parse);
1193
1194 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1195 continue;
1196
1197 si_store_shader_io_attribs(es, d);
1198 }
1199
1200 /* Load the ESGS ring resource descriptor */
1201 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1202 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1203 lp_build_const_int32(gallivm,
1204 NUM_PIPE_CONST_BUFFERS + 1));
1205
1206 for (i = 0; i < es->noutput; i++) {
1207 LLVMValueRef *out_ptr =
1208 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1209 int j;
1210
1211 for (j = 0; j < gs->ninput; j++) {
1212 if (gs->input[j].name == es->output[i].name &&
1213 gs->input[j].sid == es->output[i].sid)
1214 break;
1215 }
1216 if (j == gs->ninput)
1217 continue;
1218
1219 for (chan = 0; chan < 4; chan++) {
1220 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1221 LLVMValueRef voffset =
1222 lp_build_const_int32(gallivm,
1223 (4 * gs->input[j].param_offset + chan) * 4);
1224 LLVMValueRef soffset =
1225 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1226 SI_PARAM_ES2GS_OFFSET);
1227
1228 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1229
1230 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1231 voffset, soffset, 0,
1232 V_008F0C_BUF_DATA_FORMAT_32,
1233 V_008F0C_BUF_NUM_FORMAT_UINT,
1234 1, 0, 1, 1, 0);
1235 }
1236 }
1237 }
1238
1239 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1240 {
1241 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1242 struct gallivm_state *gallivm = bld_base->base.gallivm;
1243 LLVMValueRef args[2];
1244
1245 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1246 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1247 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1248 LLVMVoidTypeInContext(gallivm->context), args, 2,
1249 LLVMNoUnwindAttribute);
1250 }
1251
1252 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1253 {
1254 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1255 struct gallivm_state *gallivm = bld_base->base.gallivm;
1256 struct si_pipe_shader *shader = si_shader_ctx->shader;
1257 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1258 struct si_shader_output_values *outputs = NULL;
1259 unsigned noutput = 0;
1260 int i;
1261
1262 while (!tgsi_parse_end_of_tokens(parse)) {
1263 struct tgsi_full_declaration *d =
1264 &parse->FullToken.FullDeclaration;
1265 unsigned index;
1266
1267 tgsi_parse_token(parse);
1268
1269 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1270 continue;
1271
1272 i = si_store_shader_io_attribs(&shader->shader, d);
1273 if (i < 0)
1274 continue;
1275
1276 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1277 (noutput + 1) * sizeof(outputs[0]));
1278 for (index = d->Range.First; index <= d->Range.Last; index++) {
1279 outputs[noutput].index = index;
1280 outputs[noutput].name = d->Semantic.Name;
1281 outputs[noutput].sid = d->Semantic.Index;
1282 outputs[noutput].usage = d->Declaration.UsageMask;
1283
1284 for (i = 0; i < 4; i++)
1285 outputs[noutput].values[i] =
1286 LLVMBuildLoad(gallivm->builder,
1287 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1288 "");
1289 }
1290 noutput++;
1291 }
1292
1293 si_llvm_export_vs(bld_base, outputs, noutput);
1294 FREE(outputs);
1295 }
1296
1297 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1298 {
1299 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1300 struct si_shader * shader = &si_shader_ctx->shader->shader;
1301 struct lp_build_context * base = &bld_base->base;
1302 struct lp_build_context * uint =
1303 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1304 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1305 LLVMValueRef args[9];
1306 LLVMValueRef last_args[9] = { 0 };
1307 unsigned semantic_name;
1308 int depth_index = -1, stencil_index = -1;
1309 int i;
1310
1311 while (!tgsi_parse_end_of_tokens(parse)) {
1312 struct tgsi_full_declaration *d =
1313 &parse->FullToken.FullDeclaration;
1314 unsigned target;
1315 unsigned index;
1316
1317 tgsi_parse_token(parse);
1318
1319 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1320 parse->FullToken.FullProperty.Property.PropertyName ==
1321 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1322 shader->fs_write_all = TRUE;
1323
1324 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1325 continue;
1326
1327 i = si_store_shader_io_attribs(shader, d);
1328 if (i < 0)
1329 continue;
1330
1331 semantic_name = d->Semantic.Name;
1332 for (index = d->Range.First; index <= d->Range.Last; index++) {
1333 /* Select the correct target */
1334 switch(semantic_name) {
1335 case TGSI_SEMANTIC_POSITION:
1336 depth_index = index;
1337 continue;
1338 case TGSI_SEMANTIC_STENCIL:
1339 stencil_index = index;
1340 continue;
1341 case TGSI_SEMANTIC_COLOR:
1342 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1343 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1344 LLVMBuildStore(bld_base->base.gallivm->builder,
1345 bld_base->base.one,
1346 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1347
1348 if (d->Semantic.Index == 0 &&
1349 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1350 si_alpha_test(bld_base,
1351 si_shader_ctx->radeon_bld.soa.outputs[index]);
1352 break;
1353 default:
1354 target = 0;
1355 fprintf(stderr,
1356 "Warning: SI unhandled fs output type:%d\n",
1357 semantic_name);
1358 }
1359
1360 si_llvm_init_export_args_load(bld_base,
1361 si_shader_ctx->radeon_bld.soa.outputs[index],
1362 target, args);
1363
1364 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1365 /* If there is an export instruction waiting to be emitted, do so now. */
1366 if (last_args[0]) {
1367 lp_build_intrinsic(base->gallivm->builder,
1368 "llvm.SI.export",
1369 LLVMVoidTypeInContext(base->gallivm->context),
1370 last_args, 9);
1371 }
1372
1373 /* This instruction will be emitted at the end of the shader. */
1374 memcpy(last_args, args, sizeof(args));
1375
1376 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1377 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1378 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1379 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1380 si_llvm_init_export_args_load(bld_base,
1381 si_shader_ctx->radeon_bld.soa.outputs[index],
1382 V_008DFC_SQ_EXP_MRT + c, args);
1383 lp_build_intrinsic(base->gallivm->builder,
1384 "llvm.SI.export",
1385 LLVMVoidTypeInContext(base->gallivm->context),
1386 args, 9);
1387 }
1388 }
1389 } else {
1390 lp_build_intrinsic(base->gallivm->builder,
1391 "llvm.SI.export",
1392 LLVMVoidTypeInContext(base->gallivm->context),
1393 args, 9);
1394 }
1395 }
1396 }
1397
1398 if (depth_index >= 0 || stencil_index >= 0) {
1399 LLVMValueRef out_ptr;
1400 unsigned mask = 0;
1401
1402 /* Specify the target we are exporting */
1403 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1404
1405 if (depth_index >= 0) {
1406 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1407 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1408 mask |= 0x1;
1409
1410 if (stencil_index < 0) {
1411 args[6] =
1412 args[7] =
1413 args[8] = args[5];
1414 }
1415 }
1416
1417 if (stencil_index >= 0) {
1418 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1419 args[7] =
1420 args[8] =
1421 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1422 /* Only setting the stencil component bit (0x2) here
1423 * breaks some stencil piglit tests
1424 */
1425 mask |= 0x3;
1426
1427 if (depth_index < 0)
1428 args[5] = args[6];
1429 }
1430
1431 /* Specify which components to enable */
1432 args[0] = lp_build_const_int32(base->gallivm, mask);
1433
1434 args[1] =
1435 args[2] =
1436 args[4] = uint->zero;
1437
1438 if (last_args[0])
1439 lp_build_intrinsic(base->gallivm->builder,
1440 "llvm.SI.export",
1441 LLVMVoidTypeInContext(base->gallivm->context),
1442 args, 9);
1443 else
1444 memcpy(last_args, args, sizeof(args));
1445 }
1446
1447 if (!last_args[0]) {
1448 /* Specify which components to enable */
1449 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1450
1451 /* Specify the target we are exporting */
1452 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1453
1454 /* Set COMPR flag to zero to export data as 32-bit */
1455 last_args[4] = uint->zero;
1456
1457 /* dummy bits */
1458 last_args[5]= uint->zero;
1459 last_args[6]= uint->zero;
1460 last_args[7]= uint->zero;
1461 last_args[8]= uint->zero;
1462
1463 si_shader_ctx->shader->spi_shader_col_format |=
1464 V_028714_SPI_SHADER_32_ABGR;
1465 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1466 }
1467
1468 /* Specify whether the EXEC mask represents the valid mask */
1469 last_args[1] = uint->one;
1470
1471 /* Specify that this is the last export */
1472 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1473
1474 lp_build_intrinsic(base->gallivm->builder,
1475 "llvm.SI.export",
1476 LLVMVoidTypeInContext(base->gallivm->context),
1477 last_args, 9);
1478 }
1479
1480 static const struct lp_build_tgsi_action txf_action;
1481
1482 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1483 struct lp_build_tgsi_context * bld_base,
1484 struct lp_build_emit_data * emit_data);
1485
1486 static void tex_fetch_args(
1487 struct lp_build_tgsi_context * bld_base,
1488 struct lp_build_emit_data * emit_data)
1489 {
1490 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1491 struct gallivm_state *gallivm = bld_base->base.gallivm;
1492 const struct tgsi_full_instruction * inst = emit_data->inst;
1493 unsigned opcode = inst->Instruction.Opcode;
1494 unsigned target = inst->Texture.Texture;
1495 LLVMValueRef coords[4];
1496 LLVMValueRef address[16];
1497 int ref_pos;
1498 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1499 unsigned count = 0;
1500 unsigned chan;
1501 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1502 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1503
1504 if (target == TGSI_TEXTURE_BUFFER) {
1505 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1506 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1507 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1508 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1509
1510 /* Truncate v32i8 to v16i8. */
1511 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1512 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1513 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1514 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1515
1516 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1517 emit_data->args[0] = res;
1518 emit_data->args[1] = bld_base->uint_bld.zero;
1519 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1520 emit_data->arg_count = 3;
1521 return;
1522 }
1523
1524 /* Fetch and project texture coordinates */
1525 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1526 for (chan = 0; chan < 3; chan++ ) {
1527 coords[chan] = lp_build_emit_fetch(bld_base,
1528 emit_data->inst, 0,
1529 chan);
1530 if (opcode == TGSI_OPCODE_TXP)
1531 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1532 TGSI_OPCODE_DIV,
1533 coords[chan],
1534 coords[3]);
1535 }
1536
1537 if (opcode == TGSI_OPCODE_TXP)
1538 coords[3] = bld_base->base.one;
1539
1540 /* Pack LOD bias value */
1541 if (opcode == TGSI_OPCODE_TXB)
1542 address[count++] = coords[3];
1543
1544 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1545 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1546
1547 /* Pack depth comparison value */
1548 switch (target) {
1549 case TGSI_TEXTURE_SHADOW1D:
1550 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1551 case TGSI_TEXTURE_SHADOW2D:
1552 case TGSI_TEXTURE_SHADOWRECT:
1553 case TGSI_TEXTURE_SHADOWCUBE:
1554 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1555 assert(ref_pos >= 0);
1556 address[count++] = coords[ref_pos];
1557 break;
1558 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1559 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1560 }
1561
1562 /* Pack user derivatives */
1563 if (opcode == TGSI_OPCODE_TXD) {
1564 for (chan = 0; chan < 2; chan++) {
1565 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1566 if (num_coords > 1)
1567 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1568 }
1569 }
1570
1571 /* Pack texture coordinates */
1572 address[count++] = coords[0];
1573 if (num_coords > 1)
1574 address[count++] = coords[1];
1575 if (num_coords > 2)
1576 address[count++] = coords[2];
1577
1578 /* Pack LOD or sample index */
1579 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1580 address[count++] = coords[3];
1581
1582 if (count > 16) {
1583 assert(!"Cannot handle more than 16 texture address parameters");
1584 count = 16;
1585 }
1586
1587 for (chan = 0; chan < count; chan++ ) {
1588 address[chan] = LLVMBuildBitCast(gallivm->builder,
1589 address[chan],
1590 LLVMInt32TypeInContext(gallivm->context),
1591 "");
1592 }
1593
1594 /* Adjust the sample index according to FMASK.
1595 *
1596 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1597 * which is the identity mapping. Each nibble says which physical sample
1598 * should be fetched to get that sample.
1599 *
1600 * For example, 0x11111100 means there are only 2 samples stored and
1601 * the second sample covers 3/4 of the pixel. When reading samples 0
1602 * and 1, return physical sample 0 (determined by the first two 0s
1603 * in FMASK), otherwise return physical sample 1.
1604 *
1605 * The sample index should be adjusted as follows:
1606 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1607 */
1608 if (target == TGSI_TEXTURE_2D_MSAA ||
1609 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1610 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1611 struct lp_build_emit_data txf_emit_data = *emit_data;
1612 LLVMValueRef txf_address[4];
1613 unsigned txf_count = count;
1614
1615 memcpy(txf_address, address, sizeof(txf_address));
1616
1617 if (target == TGSI_TEXTURE_2D_MSAA) {
1618 txf_address[2] = bld_base->uint_bld.zero;
1619 }
1620 txf_address[3] = bld_base->uint_bld.zero;
1621
1622 /* Pad to a power-of-two size. */
1623 while (txf_count < util_next_power_of_two(txf_count))
1624 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1625
1626 /* Read FMASK using TXF. */
1627 txf_emit_data.chan = 0;
1628 txf_emit_data.dst_type = LLVMVectorType(
1629 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1630 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1631 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1632 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1633 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1634 txf_emit_data.arg_count = 3;
1635
1636 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1637
1638 /* Initialize some constants. */
1639 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1640 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1641
1642 /* Apply the formula. */
1643 LLVMValueRef fmask =
1644 LLVMBuildExtractElement(gallivm->builder,
1645 txf_emit_data.output[0],
1646 uint_bld->zero, "");
1647
1648 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1649
1650 LLVMValueRef sample_index4 =
1651 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1652
1653 LLVMValueRef shifted_fmask =
1654 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1655
1656 LLVMValueRef final_sample =
1657 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1658
1659 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1660 * resource descriptor is 0 (invalid),
1661 */
1662 LLVMValueRef fmask_desc =
1663 LLVMBuildBitCast(gallivm->builder,
1664 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1665 LLVMVectorType(uint_bld->elem_type, 8), "");
1666
1667 LLVMValueRef fmask_word1 =
1668 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1669 uint_bld->one, "");
1670
1671 LLVMValueRef word1_is_nonzero =
1672 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1673 fmask_word1, uint_bld->zero, "");
1674
1675 /* Replace the MSAA sample index. */
1676 address[sample_chan] =
1677 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1678 final_sample, address[sample_chan], "");
1679 }
1680
1681 /* Resource */
1682 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1683
1684 if (opcode == TGSI_OPCODE_TXF) {
1685 /* add tex offsets */
1686 if (inst->Texture.NumOffsets) {
1687 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1688 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1689 const struct tgsi_texture_offset * off = inst->TexOffsets;
1690
1691 assert(inst->Texture.NumOffsets == 1);
1692
1693 switch (target) {
1694 case TGSI_TEXTURE_3D:
1695 address[2] = lp_build_add(uint_bld, address[2],
1696 bld->immediates[off->Index][off->SwizzleZ]);
1697 /* fall through */
1698 case TGSI_TEXTURE_2D:
1699 case TGSI_TEXTURE_SHADOW2D:
1700 case TGSI_TEXTURE_RECT:
1701 case TGSI_TEXTURE_SHADOWRECT:
1702 case TGSI_TEXTURE_2D_ARRAY:
1703 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1704 address[1] =
1705 lp_build_add(uint_bld, address[1],
1706 bld->immediates[off->Index][off->SwizzleY]);
1707 /* fall through */
1708 case TGSI_TEXTURE_1D:
1709 case TGSI_TEXTURE_SHADOW1D:
1710 case TGSI_TEXTURE_1D_ARRAY:
1711 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1712 address[0] =
1713 lp_build_add(uint_bld, address[0],
1714 bld->immediates[off->Index][off->SwizzleX]);
1715 break;
1716 /* texture offsets do not apply to other texture targets */
1717 }
1718 }
1719
1720 emit_data->dst_type = LLVMVectorType(
1721 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1722 4);
1723
1724 emit_data->arg_count = 3;
1725 } else {
1726 /* Sampler */
1727 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1728
1729 emit_data->dst_type = LLVMVectorType(
1730 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1731 4);
1732
1733 emit_data->arg_count = 4;
1734 }
1735
1736 /* Dimensions */
1737 emit_data->args[emit_data->arg_count - 1] =
1738 lp_build_const_int32(bld_base->base.gallivm, target);
1739
1740 /* Pad to power of two vector */
1741 while (count < util_next_power_of_two(count))
1742 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1743
1744 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1745 }
1746
1747 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1748 struct lp_build_tgsi_context * bld_base,
1749 struct lp_build_emit_data * emit_data)
1750 {
1751 struct lp_build_context * base = &bld_base->base;
1752 char intr_name[127];
1753
1754 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1755 emit_data->output[emit_data->chan] = build_intrinsic(
1756 base->gallivm->builder,
1757 "llvm.SI.vs.load.input", emit_data->dst_type,
1758 emit_data->args, emit_data->arg_count,
1759 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1760 return;
1761 }
1762
1763 sprintf(intr_name, "%sv%ui32", action->intr_name,
1764 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1765
1766 emit_data->output[emit_data->chan] = build_intrinsic(
1767 base->gallivm->builder, intr_name, emit_data->dst_type,
1768 emit_data->args, emit_data->arg_count,
1769 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1770 }
1771
1772 static void txq_fetch_args(
1773 struct lp_build_tgsi_context * bld_base,
1774 struct lp_build_emit_data * emit_data)
1775 {
1776 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1777 const struct tgsi_full_instruction *inst = emit_data->inst;
1778 struct gallivm_state *gallivm = bld_base->base.gallivm;
1779
1780 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1781 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1782 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1783
1784 /* Read the size from the buffer descriptor directly. */
1785 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1786 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1787 size = LLVMBuildExtractElement(gallivm->builder, size,
1788 lp_build_const_int32(gallivm, 2), "");
1789 emit_data->args[0] = size;
1790 return;
1791 }
1792
1793 /* Mip level */
1794 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1795
1796 /* Resource */
1797 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1798
1799 /* Dimensions */
1800 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1801 inst->Texture.Texture);
1802
1803 emit_data->arg_count = 3;
1804
1805 emit_data->dst_type = LLVMVectorType(
1806 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1807 4);
1808 }
1809
1810 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1811 struct lp_build_tgsi_context * bld_base,
1812 struct lp_build_emit_data * emit_data)
1813 {
1814 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1815 /* Just return the buffer size. */
1816 emit_data->output[emit_data->chan] = emit_data->args[0];
1817 return;
1818 }
1819
1820 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1821 }
1822
1823 #if HAVE_LLVM >= 0x0304
1824
1825 static void si_llvm_emit_ddxy(
1826 const struct lp_build_tgsi_action * action,
1827 struct lp_build_tgsi_context * bld_base,
1828 struct lp_build_emit_data * emit_data)
1829 {
1830 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1831 struct gallivm_state *gallivm = bld_base->base.gallivm;
1832 struct lp_build_context * base = &bld_base->base;
1833 const struct tgsi_full_instruction *inst = emit_data->inst;
1834 unsigned opcode = inst->Instruction.Opcode;
1835 LLVMValueRef indices[2];
1836 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1837 LLVMValueRef tl, trbl, result[4];
1838 LLVMTypeRef i32;
1839 unsigned swizzle[4];
1840 unsigned c;
1841
1842 i32 = LLVMInt32TypeInContext(gallivm->context);
1843
1844 indices[0] = bld_base->uint_bld.zero;
1845 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1846 NULL, 0, LLVMReadNoneAttribute);
1847 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1848 indices, 2, "");
1849
1850 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1851 lp_build_const_int32(gallivm, 0xfffffffc), "");
1852 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1853 indices, 2, "");
1854
1855 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1856 lp_build_const_int32(gallivm,
1857 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1858 "");
1859 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1860 indices, 2, "");
1861
1862 for (c = 0; c < 4; ++c) {
1863 unsigned i;
1864
1865 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1866 for (i = 0; i < c; ++i) {
1867 if (swizzle[i] == swizzle[c]) {
1868 result[c] = result[i];
1869 break;
1870 }
1871 }
1872 if (i != c)
1873 continue;
1874
1875 LLVMBuildStore(gallivm->builder,
1876 LLVMBuildBitCast(gallivm->builder,
1877 lp_build_emit_fetch(bld_base, inst, 0, c),
1878 i32, ""),
1879 store_ptr);
1880
1881 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1882 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1883
1884 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1885 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1886
1887 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1888 }
1889
1890 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1891 }
1892
1893 #endif /* HAVE_LLVM >= 0x0304 */
1894
1895 /* Emit one vertex from the geometry shader */
1896 static void si_llvm_emit_vertex(
1897 const struct lp_build_tgsi_action *action,
1898 struct lp_build_tgsi_context *bld_base,
1899 struct lp_build_emit_data *emit_data)
1900 {
1901 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1902 struct lp_build_context *uint = &bld_base->uint_bld;
1903 struct si_shader *shader = &si_shader_ctx->shader->shader;
1904 struct gallivm_state *gallivm = bld_base->base.gallivm;
1905 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1906 LLVMValueRef gs_next_vertex;
1907 LLVMValueRef t_list_ptr;
1908 LLVMValueRef t_list;
1909 LLVMValueRef args[2];
1910 unsigned chan;
1911 int i;
1912
1913 /* Load the GSVS ring resource descriptor */
1914 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1915 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1916 lp_build_const_int32(gallivm,
1917 NUM_PIPE_CONST_BUFFERS + 2));
1918
1919 if (shader->noutput == 0) {
1920 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1921
1922 while (!tgsi_parse_end_of_tokens(parse)) {
1923 tgsi_parse_token(parse);
1924
1925 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1926 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
1927
1928 if (d->Declaration.File == TGSI_FILE_OUTPUT)
1929 si_store_shader_io_attribs(shader, d);
1930 }
1931 }
1932 }
1933
1934 /* Write vertex attribute values to GSVS ring */
1935 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
1936 for (i = 0; i < shader->noutput; i++) {
1937 LLVMValueRef *out_ptr =
1938 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
1939
1940 for (chan = 0; chan < 4; chan++) {
1941 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1942 LLVMValueRef soffset =
1943 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1944 SI_PARAM_GS2VS_OFFSET);
1945 LLVMValueRef voffset =
1946 lp_build_const_int32(gallivm, (i * 4 + chan) *
1947 shader->gs_max_out_vertices);
1948
1949 voffset = lp_build_add(uint, voffset, gs_next_vertex);
1950 voffset = lp_build_mul_imm(uint, voffset, 4);
1951
1952 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1953
1954 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1955 voffset, soffset, 0,
1956 V_008F0C_BUF_DATA_FORMAT_32,
1957 V_008F0C_BUF_NUM_FORMAT_UINT,
1958 1, 0, 1, 1, 0);
1959 }
1960 }
1961 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
1962 lp_build_const_int32(gallivm, 1));
1963 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
1964
1965 /* Signal vertex emission */
1966 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
1967 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1968 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1969 LLVMVoidTypeInContext(gallivm->context), args, 2,
1970 LLVMNoUnwindAttribute);
1971 }
1972
1973 /* Cut one primitive from the geometry shader */
1974 static void si_llvm_emit_primitive(
1975 const struct lp_build_tgsi_action *action,
1976 struct lp_build_tgsi_context *bld_base,
1977 struct lp_build_emit_data *emit_data)
1978 {
1979 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1980 struct gallivm_state *gallivm = bld_base->base.gallivm;
1981 LLVMValueRef args[2];
1982
1983 /* Signal primitive cut */
1984 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
1985 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1986 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1987 LLVMVoidTypeInContext(gallivm->context), args, 2,
1988 LLVMNoUnwindAttribute);
1989 }
1990
1991 static const struct lp_build_tgsi_action tex_action = {
1992 .fetch_args = tex_fetch_args,
1993 .emit = build_tex_intrinsic,
1994 .intr_name = "llvm.SI.sample."
1995 };
1996
1997 static const struct lp_build_tgsi_action txb_action = {
1998 .fetch_args = tex_fetch_args,
1999 .emit = build_tex_intrinsic,
2000 .intr_name = "llvm.SI.sampleb."
2001 };
2002
2003 #if HAVE_LLVM >= 0x0304
2004 static const struct lp_build_tgsi_action txd_action = {
2005 .fetch_args = tex_fetch_args,
2006 .emit = build_tex_intrinsic,
2007 .intr_name = "llvm.SI.sampled."
2008 };
2009 #endif
2010
2011 static const struct lp_build_tgsi_action txf_action = {
2012 .fetch_args = tex_fetch_args,
2013 .emit = build_tex_intrinsic,
2014 .intr_name = "llvm.SI.imageload."
2015 };
2016
2017 static const struct lp_build_tgsi_action txl_action = {
2018 .fetch_args = tex_fetch_args,
2019 .emit = build_tex_intrinsic,
2020 .intr_name = "llvm.SI.samplel."
2021 };
2022
2023 static const struct lp_build_tgsi_action txq_action = {
2024 .fetch_args = txq_fetch_args,
2025 .emit = build_txq_intrinsic,
2026 .intr_name = "llvm.SI.resinfo"
2027 };
2028
2029 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2030 {
2031 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2032 LLVMValueRef args[3];
2033
2034 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2035 args[1] = 0;
2036 args[2] = lp_build_const_int32(gallivm, 1);
2037
2038 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2039 }
2040
2041 static void create_function(struct si_shader_context *si_shader_ctx)
2042 {
2043 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2044 struct gallivm_state *gallivm = bld_base->base.gallivm;
2045 struct si_pipe_shader *shader = si_shader_ctx->shader;
2046 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
2047 unsigned i, last_sgpr, num_params;
2048
2049 i8 = LLVMInt8TypeInContext(gallivm->context);
2050 i32 = LLVMInt32TypeInContext(gallivm->context);
2051 f32 = LLVMFloatTypeInContext(gallivm->context);
2052 v2i32 = LLVMVectorType(i32, 2);
2053 v3i32 = LLVMVectorType(i32, 3);
2054
2055 params[SI_PARAM_CONST] = LLVMPointerType(
2056 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
2057 /* We assume at most 16 textures per program at the moment.
2058 * This need probably need to be changed to support bindless textures */
2059 params[SI_PARAM_SAMPLER] = LLVMPointerType(
2060 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
2061 params[SI_PARAM_RESOURCE] = LLVMPointerType(
2062 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
2063
2064 switch (si_shader_ctx->type) {
2065 case TGSI_PROCESSOR_VERTEX:
2066 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
2067 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
2068 params[SI_PARAM_START_INSTANCE] = i32;
2069 num_params = SI_PARAM_START_INSTANCE+1;
2070 if (shader->key.vs.as_es) {
2071 params[SI_PARAM_ES2GS_OFFSET] = i32;
2072 num_params++;
2073 } else {
2074 /* The locations of the other parameters are assigned dynamically. */
2075
2076 /* Streamout SGPRs. */
2077 if (shader->selector->so.num_outputs) {
2078 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2079 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2080 }
2081 /* A streamout buffer offset is loaded if the stride is non-zero. */
2082 for (i = 0; i < 4; i++) {
2083 if (!shader->selector->so.stride[i])
2084 continue;
2085
2086 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2087 }
2088 }
2089
2090 last_sgpr = num_params-1;
2091
2092 /* VGPRs */
2093 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2094 params[num_params++] = i32; /* unused*/
2095 params[num_params++] = i32; /* unused */
2096 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2097 break;
2098
2099 case TGSI_PROCESSOR_GEOMETRY:
2100 params[SI_PARAM_GS2VS_OFFSET] = i32;
2101 params[SI_PARAM_GS_WAVE_ID] = i32;
2102 last_sgpr = SI_PARAM_GS_WAVE_ID;
2103
2104 /* VGPRs */
2105 params[SI_PARAM_VTX0_OFFSET] = i32;
2106 params[SI_PARAM_VTX1_OFFSET] = i32;
2107 params[SI_PARAM_PRIMITIVE_ID] = i32;
2108 params[SI_PARAM_VTX2_OFFSET] = i32;
2109 params[SI_PARAM_VTX3_OFFSET] = i32;
2110 params[SI_PARAM_VTX4_OFFSET] = i32;
2111 params[SI_PARAM_VTX5_OFFSET] = i32;
2112 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2113 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2114 break;
2115
2116 case TGSI_PROCESSOR_FRAGMENT:
2117 params[SI_PARAM_ALPHA_REF] = f32;
2118 params[SI_PARAM_PRIM_MASK] = i32;
2119 last_sgpr = SI_PARAM_PRIM_MASK;
2120 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2121 params[SI_PARAM_PERSP_CENTER] = v2i32;
2122 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2123 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2124 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2125 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2126 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2127 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2128 params[SI_PARAM_POS_X_FLOAT] = f32;
2129 params[SI_PARAM_POS_Y_FLOAT] = f32;
2130 params[SI_PARAM_POS_Z_FLOAT] = f32;
2131 params[SI_PARAM_POS_W_FLOAT] = f32;
2132 params[SI_PARAM_FRONT_FACE] = f32;
2133 params[SI_PARAM_ANCILLARY] = f32;
2134 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2135 params[SI_PARAM_POS_FIXED_PT] = f32;
2136 num_params = SI_PARAM_POS_FIXED_PT+1;
2137 break;
2138
2139 default:
2140 assert(0 && "unimplemented shader");
2141 return;
2142 }
2143
2144 assert(num_params <= Elements(params));
2145 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2146 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2147
2148 for (i = 0; i <= last_sgpr; ++i) {
2149 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2150 switch (i) {
2151 default:
2152 LLVMAddAttribute(P, LLVMInRegAttribute);
2153 break;
2154 #if HAVE_LLVM >= 0x0304
2155 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2156 * to move load. Inputs are constant so this is fine. */
2157 case SI_PARAM_CONST:
2158 case SI_PARAM_SAMPLER:
2159 case SI_PARAM_RESOURCE:
2160 LLVMAddAttribute(P, LLVMByValAttribute);
2161 break;
2162 #endif
2163 }
2164 }
2165
2166 #if HAVE_LLVM >= 0x0304
2167 if (bld_base->info &&
2168 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2169 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2170 si_shader_ctx->ddxy_lds =
2171 LLVMAddGlobalInAddressSpace(gallivm->module,
2172 LLVMArrayType(i32, 64),
2173 "ddxy_lds",
2174 LOCAL_ADDR_SPACE);
2175 #endif
2176 }
2177
2178 static void preload_constants(struct si_shader_context *si_shader_ctx)
2179 {
2180 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2181 struct gallivm_state * gallivm = bld_base->base.gallivm;
2182 const struct tgsi_shader_info * info = bld_base->info;
2183 unsigned buf;
2184 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2185
2186 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
2187 unsigned i, num_const = info->const_file_max[buf] + 1;
2188
2189 if (num_const == 0)
2190 continue;
2191
2192 /* Allocate space for the constant values */
2193 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2194
2195 /* Load the resource descriptor */
2196 si_shader_ctx->const_resource[buf] =
2197 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2198
2199 /* Load the constants, we rely on the code sinking to do the rest */
2200 for (i = 0; i < num_const * 4; ++i) {
2201 LLVMValueRef args[2] = {
2202 si_shader_ctx->const_resource[buf],
2203 lp_build_const_int32(gallivm, i * 4)
2204 };
2205 si_shader_ctx->constants[buf][i] =
2206 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
2207 bld_base->base.elem_type, args, 2,
2208 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2209 }
2210 }
2211 }
2212
2213 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2214 {
2215 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2216 struct gallivm_state * gallivm = bld_base->base.gallivm;
2217 const struct tgsi_shader_info * info = bld_base->info;
2218
2219 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2220
2221 LLVMValueRef res_ptr, samp_ptr;
2222 LLVMValueRef offset;
2223
2224 if (num_samplers == 0)
2225 return;
2226
2227 /* Allocate space for the values */
2228 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2229 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2230
2231 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2232 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2233
2234 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2235 for (i = 0; i < num_samplers; ++i) {
2236 /* Resource */
2237 offset = lp_build_const_int32(gallivm, i);
2238 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2239
2240 /* Sampler */
2241 offset = lp_build_const_int32(gallivm, i);
2242 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2243
2244 /* FMASK resource */
2245 if (info->is_msaa_sampler[i]) {
2246 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
2247 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
2248 build_indexed_load(si_shader_ctx, res_ptr, offset);
2249 }
2250 }
2251 }
2252
2253 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2254 {
2255 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2256 struct gallivm_state * gallivm = bld_base->base.gallivm;
2257 unsigned i;
2258
2259 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2260 si_shader_ctx->shader->key.vs.as_es ||
2261 !si_shader_ctx->shader->selector->so.num_outputs)
2262 return;
2263
2264 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2265 SI_PARAM_SO_BUFFER);
2266
2267 /* Load the resources, we rely on the code sinking to do the rest */
2268 for (i = 0; i < 4; ++i) {
2269 if (si_shader_ctx->shader->selector->so.stride[i]) {
2270 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
2271
2272 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2273 }
2274 }
2275 }
2276
2277 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2278 LLVMModuleRef mod)
2279 {
2280 unsigned i;
2281 uint32_t *ptr;
2282 struct radeon_llvm_binary binary;
2283 bool dump = r600_can_dump_shader(&sctx->screen->b,
2284 shader->selector ? shader->selector->tokens : NULL);
2285 memset(&binary, 0, sizeof(binary));
2286 radeon_llvm_compile(mod, &binary,
2287 r600_get_llvm_processor_name(sctx->screen->b.family), dump);
2288 if (dump && ! binary.disassembled) {
2289 fprintf(stderr, "SI CODE:\n");
2290 for (i = 0; i < binary.code_size; i+=4 ) {
2291 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2292 binary.code[i + 2], binary.code[i + 1],
2293 binary.code[i]);
2294 }
2295 }
2296
2297 /* XXX: We may be able to emit some of these values directly rather than
2298 * extracting fields to be emitted later.
2299 */
2300 for (i = 0; i < binary.config_size; i+= 8) {
2301 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2302 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2303 switch (reg) {
2304 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2305 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2306 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2307 case R_00B848_COMPUTE_PGM_RSRC1:
2308 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2309 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2310 break;
2311 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2312 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2313 break;
2314 case R_00B84C_COMPUTE_PGM_RSRC2:
2315 shader->lds_size = G_00B84C_LDS_SIZE(value);
2316 break;
2317 case R_0286CC_SPI_PS_INPUT_ENA:
2318 shader->spi_ps_input_ena = value;
2319 break;
2320 default:
2321 fprintf(stderr, "Warning: Compiler emitted unknown "
2322 "config register: 0x%x\n", reg);
2323 break;
2324 }
2325 }
2326
2327 /* copy new shader */
2328 r600_resource_reference(&shader->bo, NULL);
2329 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2330 binary.code_size);
2331 if (shader->bo == NULL) {
2332 return -ENOMEM;
2333 }
2334
2335 ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2336 if (0 /*SI_BIG_ENDIAN*/) {
2337 for (i = 0; i < binary.code_size / 4; ++i) {
2338 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
2339 }
2340 } else {
2341 memcpy(ptr, binary.code, binary.code_size);
2342 }
2343 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2344
2345 free(binary.code);
2346 free(binary.config);
2347
2348 return 0;
2349 }
2350
2351 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2352 static int si_generate_gs_copy_shader(struct si_context *sctx,
2353 struct si_shader_context *si_shader_ctx,
2354 bool dump)
2355 {
2356 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2357 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2358 struct lp_build_context *base = &bld_base->base;
2359 struct lp_build_context *uint = &bld_base->uint_bld;
2360 struct si_shader *shader = &si_shader_ctx->shader->shader;
2361 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2362 struct si_shader_output_values *outputs;
2363 LLVMValueRef t_list_ptr, t_list;
2364 LLVMValueRef args[9];
2365 int i, r;
2366
2367 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2368
2369 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2370 si_shader_ctx->gs_for_vs = gs;
2371
2372 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2373
2374 create_meta_data(si_shader_ctx);
2375 create_function(si_shader_ctx);
2376 preload_streamout_buffers(si_shader_ctx);
2377
2378 /* Load the GSVS ring resource descriptor */
2379 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2380 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2381 lp_build_const_int32(gallivm,
2382 NUM_PIPE_CONST_BUFFERS + 1));
2383
2384 args[0] = t_list;
2385 args[1] = lp_build_mul_imm(uint,
2386 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2387 si_shader_ctx->param_vertex_id),
2388 4);
2389 args[3] = uint->zero;
2390 args[4] = uint->one; /* OFFEN */
2391 args[5] = uint->zero; /* IDXEN */
2392 args[6] = uint->one; /* GLC */
2393 args[7] = uint->one; /* SLC */
2394 args[8] = uint->zero; /* TFE */
2395
2396 /* Fetch vertex data from GSVS ring */
2397 for (i = 0; i < gs->noutput; ++i) {
2398 struct si_shader_output *out = gs->output + i;
2399 unsigned chan;
2400
2401 shader->output[i] = *out;
2402
2403 outputs[i].name = out->name;
2404 outputs[i].index = out->index;
2405 outputs[i].sid = out->sid;
2406 outputs[i].usage = out->usage;
2407
2408 for (chan = 0; chan < 4; chan++) {
2409 args[2] = lp_build_const_int32(gallivm,
2410 (i * 4 + chan) *
2411 gs->gs_max_out_vertices * 16 * 4);
2412
2413 outputs[i].values[chan] =
2414 LLVMBuildBitCast(gallivm->builder,
2415 build_intrinsic(gallivm->builder,
2416 "llvm.SI.buffer.load.dword.i32.i32",
2417 LLVMInt32TypeInContext(gallivm->context),
2418 args, 9,
2419 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2420 base->elem_type, "");
2421 }
2422 }
2423 shader->noutput = gs->noutput;
2424
2425 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2426
2427 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2428
2429 if (dump)
2430 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2431
2432 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2433 bld_base->base.gallivm->module);
2434
2435 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2436
2437 FREE(outputs);
2438 return r;
2439 }
2440
2441 int si_pipe_shader_create(
2442 struct pipe_context *ctx,
2443 struct si_pipe_shader *shader)
2444 {
2445 struct si_context *sctx = (struct si_context*)ctx;
2446 struct si_pipe_shader_selector *sel = shader->selector;
2447 struct si_shader_context si_shader_ctx;
2448 struct tgsi_shader_info shader_info;
2449 struct lp_build_tgsi_context * bld_base;
2450 LLVMModuleRef mod;
2451 int r = 0;
2452 bool dump = r600_can_dump_shader(&sctx->screen->b, sel->tokens);
2453
2454 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2455 * conversion fails. */
2456 if (dump) {
2457 tgsi_dump(sel->tokens, 0);
2458 si_dump_streamout(&sel->so);
2459 }
2460
2461 assert(shader->shader.noutput == 0);
2462 assert(shader->shader.nparam == 0);
2463 assert(shader->shader.ninput == 0);
2464
2465 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2466 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2467 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2468
2469 tgsi_scan_shader(sel->tokens, &shader_info);
2470
2471 shader->shader.uses_kill = shader_info.uses_kill;
2472 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2473 bld_base->info = &shader_info;
2474 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2475
2476 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2477 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2478 #if HAVE_LLVM >= 0x0304
2479 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2480 #endif
2481 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2482 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2483 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2484 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2485
2486 #if HAVE_LLVM >= 0x0304
2487 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2488 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2489 #endif
2490
2491 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2492 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2493
2494 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2495 si_shader_ctx.tokens = sel->tokens;
2496 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2497 si_shader_ctx.shader = shader;
2498 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2499
2500 switch (si_shader_ctx.type) {
2501 case TGSI_PROCESSOR_VERTEX:
2502 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2503 if (shader->key.vs.as_es) {
2504 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2505 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2506 } else {
2507 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2508 }
2509 break;
2510 case TGSI_PROCESSOR_GEOMETRY: {
2511 int i;
2512
2513 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2514 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2515 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2516
2517 for (i = 0; i < shader_info.num_properties; i++) {
2518 switch (shader_info.properties[i].name) {
2519 case TGSI_PROPERTY_GS_INPUT_PRIM:
2520 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2521 break;
2522 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2523 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2524 break;
2525 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2526 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2527 break;
2528 }
2529 }
2530 break;
2531 }
2532 case TGSI_PROCESSOR_FRAGMENT:
2533 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2534 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2535 break;
2536 default:
2537 assert(!"Unsupported shader type");
2538 return -1;
2539 }
2540
2541 create_meta_data(&si_shader_ctx);
2542 create_function(&si_shader_ctx);
2543 preload_constants(&si_shader_ctx);
2544 preload_samplers(&si_shader_ctx);
2545 preload_streamout_buffers(&si_shader_ctx);
2546
2547 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2548 si_shader_ctx.gs_next_vertex =
2549 lp_build_alloca(bld_base->base.gallivm,
2550 bld_base->uint_bld.elem_type, "");
2551 }
2552
2553 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2554 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2555 goto out;
2556 }
2557
2558 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2559
2560 mod = bld_base->base.gallivm->module;
2561 r = si_compile_llvm(sctx, shader, mod);
2562 if (r) {
2563 fprintf(stderr, "LLVM failed to compile shader\n");
2564 goto out;
2565 }
2566
2567 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2568
2569 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2570 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2571 shader->gs_copy_shader->selector = shader->selector;
2572 shader->gs_copy_shader->key = shader->key;
2573 si_shader_ctx.shader = shader->gs_copy_shader;
2574 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2575 free(shader->gs_copy_shader);
2576 shader->gs_copy_shader = NULL;
2577 goto out;
2578 }
2579 }
2580
2581 tgsi_parse_free(&si_shader_ctx.parse);
2582
2583 out:
2584 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2585 FREE(si_shader_ctx.constants[i]);
2586 FREE(si_shader_ctx.resources);
2587 FREE(si_shader_ctx.samplers);
2588
2589 return r;
2590 }
2591
2592 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2593 {
2594 r600_resource_reference(&shader->bo, NULL);
2595 }