2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "gallivm/lp_bld_const.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "util/u_memory.h"
28 #include "util/u_string.h"
29 #include "tgsi/tgsi_build.h"
30 #include "tgsi/tgsi_util.h"
31 #include "tgsi/tgsi_dump.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
35 #include "ac_llvm_util.h"
36 #include "si_shader_internal.h"
40 #include "compiler/nir/nir.h"
42 static const char *scratch_rsrc_dword0_symbol
=
43 "SCRATCH_RSRC_DWORD0";
45 static const char *scratch_rsrc_dword1_symbol
=
46 "SCRATCH_RSRC_DWORD1";
48 struct si_shader_output_values
50 LLVMValueRef values
[4];
51 unsigned semantic_name
;
52 unsigned semantic_index
;
53 ubyte vertex_stream
[4];
57 * Used to collect types and other info about arguments of the LLVM function
58 * before the function is created.
60 struct si_function_info
{
61 LLVMTypeRef types
[100];
62 LLVMValueRef
*assign
[100];
63 unsigned num_sgpr_params
;
72 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
73 struct si_screen
*sscreen
,
74 struct si_compiler
*compiler
);
76 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
77 struct lp_build_tgsi_context
*bld_base
,
78 struct lp_build_emit_data
*emit_data
);
80 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
83 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
84 union si_shader_part_key
*key
);
85 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
86 union si_shader_part_key
*key
);
87 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
88 union si_shader_part_key
*key
);
89 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
90 union si_shader_part_key
*key
);
92 /* Ideally pass the sample mask input to the PS epilog as v14, which
93 * is its usual location, so that the shader doesn't have to add v_mov.
95 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
97 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
100 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
106 static bool is_merged_shader(struct si_shader
*shader
)
108 if (shader
->selector
->screen
->info
.chip_class
<= VI
)
111 return shader
->key
.as_ls
||
113 shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
||
114 shader
->selector
->type
== PIPE_SHADER_GEOMETRY
;
117 static void si_init_function_info(struct si_function_info
*fninfo
)
119 fninfo
->num_params
= 0;
120 fninfo
->num_sgpr_params
= 0;
123 static unsigned add_arg_assign(struct si_function_info
*fninfo
,
124 enum si_arg_regfile regfile
, LLVMTypeRef type
,
125 LLVMValueRef
*assign
)
127 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
129 unsigned idx
= fninfo
->num_params
++;
130 assert(idx
< ARRAY_SIZE(fninfo
->types
));
132 if (regfile
== ARG_SGPR
)
133 fninfo
->num_sgpr_params
= fninfo
->num_params
;
135 fninfo
->types
[idx
] = type
;
136 fninfo
->assign
[idx
] = assign
;
140 static unsigned add_arg(struct si_function_info
*fninfo
,
141 enum si_arg_regfile regfile
, LLVMTypeRef type
)
143 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
146 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
147 enum si_arg_regfile regfile
, LLVMTypeRef type
,
148 LLVMValueRef
*assign
, unsigned idx
)
150 MAYBE_UNUSED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
151 assert(actual
== idx
);
154 static void add_arg_checked(struct si_function_info
*fninfo
,
155 enum si_arg_regfile regfile
, LLVMTypeRef type
,
158 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
168 switch (semantic_name
) {
169 case TGSI_SEMANTIC_TESSOUTER
:
171 case TGSI_SEMANTIC_TESSINNER
:
173 case TGSI_SEMANTIC_PATCH
:
178 assert(!"invalid semantic name");
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
,
191 switch (semantic_name
) {
192 case TGSI_SEMANTIC_POSITION
:
194 case TGSI_SEMANTIC_GENERIC
:
195 /* Since some shader stages use the the highest used IO index
196 * to determine the size to allocate for inputs/outputs
197 * (in LDS, tess and GS rings). GENERIC should be placed right
198 * after POSITION to make that size as small as possible.
200 if (index
< SI_MAX_IO_GENERIC
)
203 assert(!"invalid generic index");
205 case TGSI_SEMANTIC_PSIZE
:
206 return SI_MAX_IO_GENERIC
+ 1;
207 case TGSI_SEMANTIC_CLIPDIST
:
209 return SI_MAX_IO_GENERIC
+ 2 + index
;
210 case TGSI_SEMANTIC_FOG
:
211 return SI_MAX_IO_GENERIC
+ 4;
212 case TGSI_SEMANTIC_LAYER
:
213 return SI_MAX_IO_GENERIC
+ 5;
214 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
215 return SI_MAX_IO_GENERIC
+ 6;
216 case TGSI_SEMANTIC_PRIMID
:
217 return SI_MAX_IO_GENERIC
+ 7;
218 case TGSI_SEMANTIC_COLOR
:
220 return SI_MAX_IO_GENERIC
+ 8 + index
;
221 case TGSI_SEMANTIC_BCOLOR
:
223 /* If it's a varying, COLOR and BCOLOR alias. */
225 return SI_MAX_IO_GENERIC
+ 8 + index
;
227 return SI_MAX_IO_GENERIC
+ 10 + index
;
228 case TGSI_SEMANTIC_TEXCOORD
:
230 STATIC_ASSERT(SI_MAX_IO_GENERIC
+ 12 + 8 <= 63);
231 return SI_MAX_IO_GENERIC
+ 12 + index
;
232 case TGSI_SEMANTIC_CLIPVERTEX
:
235 fprintf(stderr
, "invalid semantic name = %u\n", semantic_name
);
236 assert(!"invalid semantic name");
242 * Get the value of a shader input parameter and extract a bitfield.
244 static LLVMValueRef
unpack_llvm_param(struct si_shader_context
*ctx
,
245 LLVMValueRef value
, unsigned rshift
,
248 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
249 value
= ac_to_integer(&ctx
->ac
, value
);
252 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
253 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
255 if (rshift
+ bitwidth
< 32) {
256 unsigned mask
= (1 << bitwidth
) - 1;
257 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
258 LLVMConstInt(ctx
->i32
, mask
, 0), "");
264 LLVMValueRef
si_unpack_param(struct si_shader_context
*ctx
,
265 unsigned param
, unsigned rshift
,
268 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
, param
);
270 return unpack_llvm_param(ctx
, value
, rshift
, bitwidth
);
273 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
276 case PIPE_SHADER_TESS_CTRL
:
277 return unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 0, 8);
279 case PIPE_SHADER_TESS_EVAL
:
280 return LLVMGetParam(ctx
->main_fn
,
281 ctx
->param_tes_rel_patch_id
);
289 /* Tessellation shaders pass outputs to the next shader using LDS.
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
311 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
313 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
316 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
318 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
320 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
321 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
323 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
326 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
328 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
330 return LLVMConstInt(ctx
->i32
, stride
, 0);
333 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
335 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
336 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
338 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
339 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
340 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
341 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
342 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
343 num_patch_outputs
* 4;
344 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
348 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
350 return LLVMBuildMul(ctx
->ac
.builder
,
352 ctx
->param_tcs_out_lds_offsets
,
354 LLVMConstInt(ctx
->i32
, 4, 0), "");
358 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
360 return LLVMBuildMul(ctx
->ac
.builder
,
362 ctx
->param_tcs_out_lds_offsets
,
364 LLVMConstInt(ctx
->i32
, 4, 0), "");
368 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
370 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
371 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
373 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
377 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
379 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
380 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
381 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
383 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
384 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
390 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
392 LLVMValueRef patch0_patch_data_offset
=
393 get_tcs_out_patch0_patch_data_offset(ctx
);
394 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
395 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
397 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
398 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
403 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
405 unsigned tcs_out_vertices
=
406 ctx
->shader
->selector
?
407 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
409 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
410 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
411 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
413 return si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
416 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
421 case PIPE_SHADER_VERTEX
:
422 stride
= util_last_bit64(ctx
->shader
->selector
->outputs_written
);
423 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
425 case PIPE_SHADER_TESS_CTRL
:
426 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
427 ctx
->shader
->is_monolithic
) {
428 stride
= util_last_bit64(ctx
->shader
->key
.part
.tcs
.ls
->outputs_written
);
429 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
431 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
439 static LLVMValueRef
get_instance_index_for_fetch(
440 struct si_shader_context
*ctx
,
441 unsigned param_start_instance
, LLVMValueRef divisor
)
443 LLVMValueRef result
= ctx
->abi
.instance_id
;
445 /* The division must be done before START_INSTANCE is added. */
446 if (divisor
!= ctx
->i32_1
)
447 result
= LLVMBuildUDiv(ctx
->ac
.builder
, result
, divisor
, "");
449 return LLVMBuildAdd(ctx
->ac
.builder
, result
,
450 LLVMGetParam(ctx
->main_fn
, param_start_instance
), "");
453 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
455 static LLVMValueRef
extract_double_to_float(struct si_shader_context
*ctx
,
457 unsigned double_index
)
459 LLVMBuilderRef builder
= ctx
->ac
.builder
;
460 LLVMTypeRef f64
= LLVMDoubleTypeInContext(ctx
->ac
.context
);
461 LLVMValueRef dvec2
= LLVMBuildBitCast(builder
, vec4
,
462 LLVMVectorType(f64
, 2), "");
463 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, double_index
, 0);
464 LLVMValueRef value
= LLVMBuildExtractElement(builder
, dvec2
, index
, "");
465 return LLVMBuildFPTrunc(builder
, value
, ctx
->f32
, "");
468 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
469 LLVMValueRef i32
, unsigned index
)
474 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
475 LLVMConstInt(ctx
->i32
, 16, 0), "");
477 return LLVMBuildSExt(ctx
->ac
.builder
,
478 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
483 void si_llvm_load_input_vs(
484 struct si_shader_context
*ctx
,
485 unsigned input_index
,
488 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
489 unsigned vs_blit_property
= info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
491 if (vs_blit_property
) {
492 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
493 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
494 LLVMIntULE
, vertex_id
,
496 /* Use LLVMIntNE, because we have 3 vertices and only
497 * the middle one should use y2.
499 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
500 LLVMIntNE
, vertex_id
,
503 if (input_index
== 0) {
505 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
506 ctx
->param_vs_blit_inputs
);
507 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
508 ctx
->param_vs_blit_inputs
+ 1);
510 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
511 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
512 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
513 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
515 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
517 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
520 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
521 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
522 out
[2] = LLVMGetParam(ctx
->main_fn
,
523 ctx
->param_vs_blit_inputs
+ 2);
524 out
[3] = ctx
->ac
.f32_1
;
528 /* Color or texture coordinates: */
529 assert(input_index
== 1);
531 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
532 for (int i
= 0; i
< 4; i
++) {
533 out
[i
] = LLVMGetParam(ctx
->main_fn
,
534 ctx
->param_vs_blit_inputs
+ 3 + i
);
537 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
538 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
539 ctx
->param_vs_blit_inputs
+ 3);
540 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
541 ctx
->param_vs_blit_inputs
+ 4);
542 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
543 ctx
->param_vs_blit_inputs
+ 5);
544 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
545 ctx
->param_vs_blit_inputs
+ 6);
547 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
549 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
551 out
[2] = LLVMGetParam(ctx
->main_fn
,
552 ctx
->param_vs_blit_inputs
+ 7);
553 out
[3] = LLVMGetParam(ctx
->main_fn
,
554 ctx
->param_vs_blit_inputs
+ 8);
561 unsigned num_fetches
;
562 unsigned fetch_stride
;
563 unsigned num_channels
;
565 LLVMValueRef t_list_ptr
;
566 LLVMValueRef t_offset
;
568 LLVMValueRef vertex_index
;
569 LLVMValueRef input
[3];
571 /* Load the T list */
572 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
574 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
576 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
578 vertex_index
= LLVMGetParam(ctx
->main_fn
,
579 ctx
->param_vertex_index0
+
582 fix_fetch
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
];
584 /* Do multiple loads for special formats. */
586 case SI_FIX_FETCH_RGB_64_FLOAT
:
587 num_fetches
= 3; /* 3 2-dword loads */
591 case SI_FIX_FETCH_RGBA_64_FLOAT
:
592 num_fetches
= 2; /* 2 4-dword loads */
596 case SI_FIX_FETCH_RGB_8
:
597 case SI_FIX_FETCH_RGB_8_INT
:
602 case SI_FIX_FETCH_RGB_16
:
603 case SI_FIX_FETCH_RGB_16_INT
:
611 num_channels
= util_last_bit(info
->input_usage_mask
[input_index
]);
614 for (unsigned i
= 0; i
< num_fetches
; i
++) {
615 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
617 input
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
,
618 vertex_index
, voffset
,
619 num_channels
, false, true);
620 input
[i
] = ac_build_expand_to_vec4(&ctx
->ac
, input
[i
], num_channels
);
623 /* Break up the vec4 into individual components */
624 for (chan
= 0; chan
< 4; chan
++) {
625 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, 0);
626 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
627 input
[0], llvm_chan
, "");
631 case SI_FIX_FETCH_A2_SNORM
:
632 case SI_FIX_FETCH_A2_SSCALED
:
633 case SI_FIX_FETCH_A2_SINT
: {
634 /* The hardware returns an unsigned value; convert it to a
637 LLVMValueRef tmp
= out
[3];
638 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
640 /* First, recover the sign-extended signed integer value. */
641 if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
)
642 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
644 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
646 /* For the integer-like cases, do a natural sign extension.
648 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
649 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
652 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
653 fix_fetch
== SI_FIX_FETCH_A2_SNORM
?
654 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
655 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
657 /* Convert back to the right type. */
658 if (fix_fetch
== SI_FIX_FETCH_A2_SNORM
) {
660 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
661 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
662 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
663 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
664 } else if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
) {
665 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
671 case SI_FIX_FETCH_RGBA_32_UNORM
:
672 case SI_FIX_FETCH_RGBX_32_UNORM
:
673 for (chan
= 0; chan
< 4; chan
++) {
674 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
675 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
676 out
[chan
], ctx
->f32
, "");
677 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
678 LLVMConstReal(ctx
->f32
, 1.0 / UINT_MAX
), "");
680 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
681 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_UNORM
)
682 out
[3] = LLVMConstReal(ctx
->f32
, 1);
684 case SI_FIX_FETCH_RGBA_32_SNORM
:
685 case SI_FIX_FETCH_RGBX_32_SNORM
:
686 case SI_FIX_FETCH_RGBA_32_FIXED
:
687 case SI_FIX_FETCH_RGBX_32_FIXED
: {
689 if (fix_fetch
>= SI_FIX_FETCH_RGBA_32_FIXED
)
690 scale
= 1.0 / 0x10000;
692 scale
= 1.0 / INT_MAX
;
694 for (chan
= 0; chan
< 4; chan
++) {
695 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
696 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
697 out
[chan
], ctx
->f32
, "");
698 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
699 LLVMConstReal(ctx
->f32
, scale
), "");
701 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
702 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_SNORM
||
703 fix_fetch
== SI_FIX_FETCH_RGBX_32_FIXED
)
704 out
[3] = LLVMConstReal(ctx
->f32
, 1);
707 case SI_FIX_FETCH_RGBA_32_USCALED
:
708 for (chan
= 0; chan
< 4; chan
++) {
709 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
710 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
711 out
[chan
], ctx
->f32
, "");
714 case SI_FIX_FETCH_RGBA_32_SSCALED
:
715 for (chan
= 0; chan
< 4; chan
++) {
716 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
717 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
718 out
[chan
], ctx
->f32
, "");
721 case SI_FIX_FETCH_RG_64_FLOAT
:
722 for (chan
= 0; chan
< 2; chan
++)
723 out
[chan
] = extract_double_to_float(ctx
, input
[0], chan
);
725 out
[2] = LLVMConstReal(ctx
->f32
, 0);
726 out
[3] = LLVMConstReal(ctx
->f32
, 1);
728 case SI_FIX_FETCH_RGB_64_FLOAT
:
729 for (chan
= 0; chan
< 3; chan
++)
730 out
[chan
] = extract_double_to_float(ctx
, input
[chan
], 0);
732 out
[3] = LLVMConstReal(ctx
->f32
, 1);
734 case SI_FIX_FETCH_RGBA_64_FLOAT
:
735 for (chan
= 0; chan
< 4; chan
++) {
736 out
[chan
] = extract_double_to_float(ctx
, input
[chan
/ 2],
740 case SI_FIX_FETCH_RGB_8
:
741 case SI_FIX_FETCH_RGB_8_INT
:
742 case SI_FIX_FETCH_RGB_16
:
743 case SI_FIX_FETCH_RGB_16_INT
:
744 for (chan
= 0; chan
< 3; chan
++) {
745 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
749 if (fix_fetch
== SI_FIX_FETCH_RGB_8
||
750 fix_fetch
== SI_FIX_FETCH_RGB_16
) {
751 out
[3] = LLVMConstReal(ctx
->f32
, 1);
753 out
[3] = ac_to_float(&ctx
->ac
, ctx
->i32_1
);
759 static void declare_input_vs(
760 struct si_shader_context
*ctx
,
761 unsigned input_index
,
762 const struct tgsi_full_declaration
*decl
,
765 si_llvm_load_input_vs(ctx
, input_index
, out
);
768 static LLVMValueRef
get_primitive_id(struct si_shader_context
*ctx
,
775 case PIPE_SHADER_VERTEX
:
776 return LLVMGetParam(ctx
->main_fn
,
777 ctx
->param_vs_prim_id
);
778 case PIPE_SHADER_TESS_CTRL
:
779 return ctx
->abi
.tcs_patch_id
;
780 case PIPE_SHADER_TESS_EVAL
:
781 return ctx
->abi
.tes_patch_id
;
782 case PIPE_SHADER_GEOMETRY
:
783 return ctx
->abi
.gs_prim_id
;
791 * Return the value of tgsi_ind_register for indexing.
792 * This is the indirect index with the constant offset added to it.
794 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
795 const struct tgsi_ind_register
*ind
,
801 if (ind
->File
== TGSI_FILE_ADDRESS
) {
802 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
803 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
805 struct tgsi_full_src_register src
= {};
807 src
.Register
.File
= ind
->File
;
808 src
.Register
.Index
= ind
->Index
;
810 /* Set the second index to 0 for constants. */
811 if (ind
->File
== TGSI_FILE_CONSTANT
)
812 src
.Register
.Dimension
= 1;
814 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
817 result
= ac_to_integer(&ctx
->ac
, result
);
821 result
= LLVMBuildMul(ctx
->ac
.builder
, result
,
822 LLVMConstInt(ctx
->i32
, addr_mul
, 0), "");
823 result
= LLVMBuildAdd(ctx
->ac
.builder
, result
,
824 LLVMConstInt(ctx
->i32
, rel_index
, 0), "");
829 * Like si_get_indirect_index, but restricts the return value to a (possibly
830 * undefined) value inside [0..num).
832 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
833 const struct tgsi_ind_register
*ind
,
834 int rel_index
, unsigned num
)
836 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
838 return si_llvm_bound_index(ctx
, result
, num
);
841 static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context
*ctx
,
842 LLVMValueRef vertex_dw_stride
,
843 LLVMValueRef base_addr
,
844 LLVMValueRef vertex_index
,
845 LLVMValueRef param_index
,
846 unsigned input_index
,
851 if (vertex_dw_stride
) {
852 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
853 LLVMBuildMul(ctx
->ac
.builder
, vertex_index
,
854 vertex_dw_stride
, ""), "");
858 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
859 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
860 LLVMConstInt(ctx
->i32
, 4, 0), ""), "");
863 int param
= is_patch
?
864 si_shader_io_get_unique_index_patch(name
[input_index
],
865 index
[input_index
]) :
866 si_shader_io_get_unique_index(name
[input_index
],
867 index
[input_index
], false);
869 /* Add the base address of the element. */
870 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
871 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
875 * Calculate a dword address given an input or output register and a stride.
877 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
878 const struct tgsi_full_dst_register
*dst
,
879 const struct tgsi_full_src_register
*src
,
880 LLVMValueRef vertex_dw_stride
,
881 LLVMValueRef base_addr
)
883 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
884 ubyte
*name
, *index
, *array_first
;
886 struct tgsi_full_dst_register reg
;
887 LLVMValueRef vertex_index
= NULL
;
888 LLVMValueRef ind_index
= NULL
;
890 /* Set the register description. The address computation is the same
891 * for sources and destinations. */
893 reg
.Register
.File
= src
->Register
.File
;
894 reg
.Register
.Index
= src
->Register
.Index
;
895 reg
.Register
.Indirect
= src
->Register
.Indirect
;
896 reg
.Register
.Dimension
= src
->Register
.Dimension
;
897 reg
.Indirect
= src
->Indirect
;
898 reg
.Dimension
= src
->Dimension
;
899 reg
.DimIndirect
= src
->DimIndirect
;
903 /* If the register is 2-dimensional (e.g. an array of vertices
904 * in a primitive), calculate the base address of the vertex. */
905 if (reg
.Register
.Dimension
) {
906 if (reg
.Dimension
.Indirect
)
907 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
908 1, reg
.Dimension
.Index
);
910 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
913 /* Get information about the register. */
914 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
915 name
= info
->input_semantic_name
;
916 index
= info
->input_semantic_index
;
917 array_first
= info
->input_array_first
;
918 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
919 name
= info
->output_semantic_name
;
920 index
= info
->output_semantic_index
;
921 array_first
= info
->output_array_first
;
927 if (reg
.Register
.Indirect
) {
928 /* Add the relative address of the element. */
929 if (reg
.Indirect
.ArrayID
)
930 input_index
= array_first
[reg
.Indirect
.ArrayID
];
932 input_index
= reg
.Register
.Index
;
934 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
935 1, reg
.Register
.Index
- input_index
);
937 input_index
= reg
.Register
.Index
;
940 return get_dw_address_from_generic_indices(ctx
, vertex_dw_stride
,
941 base_addr
, vertex_index
,
942 ind_index
, input_index
,
944 !reg
.Register
.Dimension
);
947 /* The offchip buffer layout for TCS->TES is
949 * - attribute 0 of patch 0 vertex 0
950 * - attribute 0 of patch 0 vertex 1
951 * - attribute 0 of patch 0 vertex 2
953 * - attribute 0 of patch 1 vertex 0
954 * - attribute 0 of patch 1 vertex 1
956 * - attribute 1 of patch 0 vertex 0
957 * - attribute 1 of patch 0 vertex 1
959 * - per patch attribute 0 of patch 0
960 * - per patch attribute 0 of patch 1
963 * Note that every attribute has 4 components.
965 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
966 LLVMValueRef rel_patch_id
,
967 LLVMValueRef vertex_index
,
968 LLVMValueRef param_index
)
970 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
971 LLVMValueRef param_stride
, constant16
;
973 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
974 num_patches
= si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
975 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
978 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
980 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
981 vertices_per_patch
, "");
983 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
986 param_stride
= total_vertices
;
988 base_addr
= rel_patch_id
;
989 param_stride
= num_patches
;
992 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
993 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
994 param_stride
, ""), "");
996 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
999 LLVMValueRef patch_data_offset
=
1000 si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
1002 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1003 patch_data_offset
, "");
1008 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1009 static LLVMValueRef
get_tcs_tes_buffer_address_from_generic_indices(
1010 struct si_shader_context
*ctx
,
1011 LLVMValueRef vertex_index
,
1012 LLVMValueRef param_index
,
1013 unsigned param_base
,
1018 unsigned param_index_base
;
1020 param_index_base
= is_patch
?
1021 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]) :
1022 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
], false);
1025 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1026 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
1029 param_index
= LLVMConstInt(ctx
->i32
, param_index_base
, 0);
1032 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
1033 vertex_index
, param_index
);
1036 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
1037 struct si_shader_context
*ctx
,
1038 const struct tgsi_full_dst_register
*dst
,
1039 const struct tgsi_full_src_register
*src
)
1041 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1042 ubyte
*name
, *index
, *array_first
;
1043 struct tgsi_full_src_register reg
;
1044 LLVMValueRef vertex_index
= NULL
;
1045 LLVMValueRef param_index
= NULL
;
1046 unsigned param_base
;
1048 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
1050 if (reg
.Register
.Dimension
) {
1052 if (reg
.Dimension
.Indirect
)
1053 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
1054 1, reg
.Dimension
.Index
);
1056 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
1059 /* Get information about the register. */
1060 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1061 name
= info
->input_semantic_name
;
1062 index
= info
->input_semantic_index
;
1063 array_first
= info
->input_array_first
;
1064 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1065 name
= info
->output_semantic_name
;
1066 index
= info
->output_semantic_index
;
1067 array_first
= info
->output_array_first
;
1073 if (reg
.Register
.Indirect
) {
1074 if (reg
.Indirect
.ArrayID
)
1075 param_base
= array_first
[reg
.Indirect
.ArrayID
];
1077 param_base
= reg
.Register
.Index
;
1079 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
1080 1, reg
.Register
.Index
- param_base
);
1083 param_base
= reg
.Register
.Index
;
1086 return get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1087 param_index
, param_base
,
1088 name
, index
, !reg
.Register
.Dimension
);
1091 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
1092 LLVMTypeRef type
, unsigned swizzle
,
1093 LLVMValueRef buffer
, LLVMValueRef offset
,
1094 LLVMValueRef base
, bool can_speculate
)
1096 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1097 LLVMValueRef value
, value2
;
1098 LLVMTypeRef vec_type
= LLVMVectorType(type
, 4);
1100 if (swizzle
== ~0) {
1101 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1102 0, 1, 0, can_speculate
, false);
1104 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1107 if (!llvm_type_is_64bit(ctx
, type
)) {
1108 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1109 0, 1, 0, can_speculate
, false);
1111 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1112 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1113 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1116 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1117 swizzle
* 4, 1, 0, can_speculate
, false);
1119 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1120 swizzle
* 4 + 4, 1, 0, can_speculate
, false);
1122 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1128 * \param type output value type
1129 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1130 * \param dw_addr address in dwords
1132 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
1133 LLVMTypeRef type
, unsigned swizzle
,
1134 LLVMValueRef dw_addr
)
1136 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1139 if (swizzle
== ~0) {
1140 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1142 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1143 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
1145 return ac_build_gather_values(&ctx
->ac
, values
,
1149 /* Split 64-bit loads. */
1150 if (llvm_type_is_64bit(ctx
, type
)) {
1151 LLVMValueRef lo
, hi
;
1153 lo
= lds_load(bld_base
, ctx
->i32
, swizzle
, dw_addr
);
1154 hi
= lds_load(bld_base
, ctx
->i32
, swizzle
+ 1, dw_addr
);
1155 return si_llvm_emit_fetch_64bit(bld_base
, type
, lo
, hi
);
1158 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1159 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1161 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1163 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1169 * \param swizzle offset (typically 0..3)
1170 * \param dw_addr address in dwords
1171 * \param value value to store
1173 static void lds_store(struct si_shader_context
*ctx
,
1174 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1177 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1178 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0), "");
1180 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1185 TESS_OFFCHIP_RING_TCS
,
1186 TESS_OFFCHIP_RING_TES
,
1189 static LLVMValueRef
get_tess_ring_descriptor(struct si_shader_context
*ctx
,
1190 enum si_tess_ring ring
)
1192 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1193 unsigned param
= ring
== TESS_OFFCHIP_RING_TES
? ctx
->param_tes_offchip_addr
:
1194 ctx
->param_tcs_out_lds_layout
;
1195 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1197 /* TCS only receives high 13 bits of the address. */
1198 if (ring
== TESS_OFFCHIP_RING_TCS
|| ring
== TCS_FACTOR_RING
) {
1199 addr
= LLVMBuildAnd(builder
, addr
,
1200 LLVMConstInt(ctx
->i32
, 0xfff80000, 0), "");
1203 if (ring
== TCS_FACTOR_RING
) {
1204 unsigned tf_offset
= ctx
->screen
->tess_offchip_ring_size
;
1205 addr
= LLVMBuildAdd(builder
, addr
,
1206 LLVMConstInt(ctx
->i32
, tf_offset
, 0), "");
1209 LLVMValueRef desc
[4];
1211 desc
[1] = LLVMConstInt(ctx
->i32
,
1212 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
1213 desc
[2] = LLVMConstInt(ctx
->i32
, 0xffffffff, 0);
1214 desc
[3] = LLVMConstInt(ctx
->i32
,
1215 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1216 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1217 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1218 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1219 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1220 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0);
1222 return ac_build_gather_values(&ctx
->ac
, desc
, 4);
1225 static LLVMValueRef
fetch_input_tcs(
1226 struct lp_build_tgsi_context
*bld_base
,
1227 const struct tgsi_full_src_register
*reg
,
1228 enum tgsi_opcode_type type
, unsigned swizzle
)
1230 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1231 LLVMValueRef dw_addr
, stride
;
1233 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1234 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1235 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1237 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1240 static LLVMValueRef
si_nir_load_tcs_varyings(struct ac_shader_abi
*abi
,
1242 LLVMValueRef vertex_index
,
1243 LLVMValueRef param_index
,
1244 unsigned const_index
,
1246 unsigned driver_location
,
1248 unsigned num_components
,
1253 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1254 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1255 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1256 LLVMValueRef dw_addr
, stride
;
1258 driver_location
= driver_location
/ 4;
1261 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1262 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1266 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1268 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1269 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1274 /* Add the constant index to the indirect index */
1275 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1276 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1278 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1284 names
= info
->input_semantic_name
;
1285 indices
= info
->input_semantic_index
;
1287 names
= info
->output_semantic_name
;
1288 indices
= info
->output_semantic_index
;
1291 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1292 vertex_index
, param_index
,
1297 LLVMValueRef value
[4];
1298 for (unsigned i
= 0; i
< num_components
; i
++) {
1299 unsigned offset
= i
;
1300 if (llvm_type_is_64bit(ctx
, type
))
1303 offset
+= component
;
1304 value
[i
+ component
] = lds_load(bld_base
, type
, offset
, dw_addr
);
1307 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1310 static LLVMValueRef
fetch_output_tcs(
1311 struct lp_build_tgsi_context
*bld_base
,
1312 const struct tgsi_full_src_register
*reg
,
1313 enum tgsi_opcode_type type
, unsigned swizzle
)
1315 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1316 LLVMValueRef dw_addr
, stride
;
1318 if (reg
->Register
.Dimension
) {
1319 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1320 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1321 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1323 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1324 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1327 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1330 static LLVMValueRef
fetch_input_tes(
1331 struct lp_build_tgsi_context
*bld_base
,
1332 const struct tgsi_full_src_register
*reg
,
1333 enum tgsi_opcode_type type
, unsigned swizzle
)
1335 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1336 LLVMValueRef base
, addr
;
1338 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1339 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1341 return buffer_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
,
1342 ctx
->tess_offchip_ring
, base
, addr
, true);
1345 LLVMValueRef
si_nir_load_input_tes(struct ac_shader_abi
*abi
,
1347 LLVMValueRef vertex_index
,
1348 LLVMValueRef param_index
,
1349 unsigned const_index
,
1351 unsigned driver_location
,
1353 unsigned num_components
,
1358 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1359 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1360 LLVMValueRef base
, addr
;
1362 driver_location
= driver_location
/ 4;
1364 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1367 /* Add the constant index to the indirect index */
1368 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1369 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1371 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1374 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1375 param_index
, driver_location
,
1376 info
->input_semantic_name
,
1377 info
->input_semantic_index
,
1380 /* TODO: This will generate rather ordinary llvm code, although it
1381 * should be easy for the optimiser to fix up. In future we might want
1382 * to refactor buffer_load(), but for now this maximises code sharing
1383 * between the NIR and TGSI backends.
1385 LLVMValueRef value
[4];
1386 for (unsigned i
= 0; i
< num_components
; i
++) {
1387 unsigned offset
= i
;
1388 if (llvm_type_is_64bit(ctx
, type
))
1391 offset
+= component
;
1392 value
[i
+ component
] = buffer_load(&ctx
->bld_base
, type
, offset
,
1393 ctx
->tess_offchip_ring
, base
, addr
, true);
1396 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1399 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1400 const struct tgsi_full_instruction
*inst
,
1401 const struct tgsi_opcode_info
*info
,
1403 LLVMValueRef dst
[4])
1405 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1406 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1407 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1408 unsigned chan_index
;
1409 LLVMValueRef dw_addr
, stride
;
1410 LLVMValueRef buffer
, base
, buf_addr
;
1411 LLVMValueRef values
[4];
1412 bool skip_lds_store
;
1413 bool is_tess_factor
= false, is_tess_inner
= false;
1415 /* Only handle per-patch and per-vertex outputs here.
1416 * Vectors will be lowered to scalars and this function will be called again.
1418 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1419 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1420 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1424 if (reg
->Register
.Dimension
) {
1425 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1426 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1427 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1428 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1430 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1431 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1432 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1434 if (!reg
->Register
.Indirect
) {
1435 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1437 /* Always write tess factors into LDS for the TCS epilog. */
1438 if (name
== TGSI_SEMANTIC_TESSINNER
||
1439 name
== TGSI_SEMANTIC_TESSOUTER
) {
1440 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1441 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1442 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1443 is_tess_factor
= true;
1444 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1449 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1451 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1452 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1454 uint32_t writemask
= reg
->Register
.WriteMask
;
1456 chan_index
= u_bit_scan(&writemask
);
1457 LLVMValueRef value
= dst
[chan_index
];
1459 if (inst
->Instruction
.Saturate
)
1460 value
= ac_build_clamp(&ctx
->ac
, value
);
1462 /* Skip LDS stores if there is no LDS read of this output. */
1463 if (!skip_lds_store
)
1464 lds_store(ctx
, chan_index
, dw_addr
, value
);
1466 value
= ac_to_integer(&ctx
->ac
, value
);
1467 values
[chan_index
] = value
;
1469 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1470 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1472 4 * chan_index
, 1, 0, true, false);
1475 /* Write tess factors into VGPRs for the epilog. */
1476 if (is_tess_factor
&&
1477 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1478 if (!is_tess_inner
) {
1479 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1480 ctx
->invoc0_tess_factors
[chan_index
]);
1481 } else if (chan_index
< 2) {
1482 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1483 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1488 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1489 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1491 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1492 base
, 0, 1, 0, true, false);
1496 static void si_nir_store_output_tcs(struct ac_shader_abi
*abi
,
1497 const struct nir_variable
*var
,
1498 LLVMValueRef vertex_index
,
1499 LLVMValueRef param_index
,
1500 unsigned const_index
,
1504 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1505 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1506 const unsigned component
= var
->data
.location_frac
;
1507 const bool is_patch
= var
->data
.patch
;
1508 unsigned driver_location
= var
->data
.driver_location
;
1509 LLVMValueRef dw_addr
, stride
;
1510 LLVMValueRef buffer
, base
, addr
;
1511 LLVMValueRef values
[4];
1512 bool skip_lds_store
;
1513 bool is_tess_factor
= false, is_tess_inner
= false;
1515 driver_location
= driver_location
/ 4;
1518 /* Add the constant index to the indirect index */
1519 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1520 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1522 if (const_index
!= 0)
1523 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1527 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1528 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1529 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1530 vertex_index
, param_index
,
1532 info
->output_semantic_name
,
1533 info
->output_semantic_index
,
1536 skip_lds_store
= !info
->reads_pervertex_outputs
;
1538 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1539 dw_addr
= get_dw_address_from_generic_indices(ctx
, NULL
, dw_addr
,
1540 vertex_index
, param_index
,
1542 info
->output_semantic_name
,
1543 info
->output_semantic_index
,
1546 skip_lds_store
= !info
->reads_perpatch_outputs
;
1549 int name
= info
->output_semantic_name
[driver_location
];
1551 /* Always write tess factors into LDS for the TCS epilog. */
1552 if (name
== TGSI_SEMANTIC_TESSINNER
||
1553 name
== TGSI_SEMANTIC_TESSOUTER
) {
1554 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1555 skip_lds_store
= !info
->reads_tessfactor_outputs
&&
1556 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1557 is_tess_factor
= true;
1558 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1563 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1565 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1567 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1568 param_index
, driver_location
,
1569 info
->output_semantic_name
,
1570 info
->output_semantic_index
,
1573 for (unsigned chan
= 0; chan
< 4; chan
++) {
1574 if (!(writemask
& (1 << chan
)))
1576 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1578 /* Skip LDS stores if there is no LDS read of this output. */
1579 if (!skip_lds_store
)
1580 lds_store(ctx
, chan
, dw_addr
, value
);
1582 value
= ac_to_integer(&ctx
->ac
, value
);
1583 values
[chan
] = value
;
1585 if (writemask
!= 0xF && !is_tess_factor
) {
1586 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1588 4 * chan
, 1, 0, true, false);
1591 /* Write tess factors into VGPRs for the epilog. */
1592 if (is_tess_factor
&&
1593 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1594 if (!is_tess_inner
) {
1595 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1596 ctx
->invoc0_tess_factors
[chan
]);
1597 } else if (chan
< 2) {
1598 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1599 ctx
->invoc0_tess_factors
[4 + chan
]);
1604 if (writemask
== 0xF && !is_tess_factor
) {
1605 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1607 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, addr
,
1608 base
, 0, 1, 0, true, false);
1612 LLVMValueRef
si_llvm_load_input_gs(struct ac_shader_abi
*abi
,
1613 unsigned input_index
,
1614 unsigned vtx_offset_param
,
1618 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1619 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1620 struct si_shader
*shader
= ctx
->shader
;
1621 LLVMValueRef vtx_offset
, soffset
;
1622 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1623 unsigned semantic_name
= info
->input_semantic_name
[input_index
];
1624 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1628 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
, false);
1630 /* GFX9 has the ESGS ring in LDS. */
1631 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1632 unsigned index
= vtx_offset_param
;
1634 switch (index
/ 2) {
1636 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1637 index
% 2 ? 16 : 0, 16);
1640 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1641 index
% 2 ? 16 : 0, 16);
1644 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1645 index
% 2 ? 16 : 0, 16);
1652 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1653 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
1654 return lds_load(bld_base
, type
, swizzle
, vtx_offset
);
1657 /* GFX6: input load from the ESGS ring in memory. */
1658 if (swizzle
== ~0) {
1659 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1661 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1662 values
[chan
] = si_llvm_load_input_gs(abi
, input_index
, vtx_offset_param
,
1665 return ac_build_gather_values(&ctx
->ac
, values
,
1669 /* Get the vertex offset parameter on GFX6. */
1670 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1672 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, gs_vtx_offset
,
1673 LLVMConstInt(ctx
->i32
, 4, 0), "");
1675 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1677 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1678 vtx_offset
, soffset
, 0, 1, 0, true, false);
1679 if (llvm_type_is_64bit(ctx
, type
)) {
1680 LLVMValueRef value2
;
1681 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1683 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1684 ctx
->i32_0
, vtx_offset
, soffset
,
1685 0, 1, 0, true, false);
1686 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1688 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1691 static LLVMValueRef
si_nir_load_input_gs(struct ac_shader_abi
*abi
,
1693 unsigned driver_location
,
1695 unsigned num_components
,
1696 unsigned vertex_index
,
1697 unsigned const_index
,
1700 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1702 LLVMValueRef value
[4];
1703 for (unsigned i
= 0; i
< num_components
; i
++) {
1704 unsigned offset
= i
;
1705 if (llvm_type_is_64bit(ctx
, type
))
1708 offset
+= component
;
1709 value
[i
+ component
] = si_llvm_load_input_gs(&ctx
->abi
, driver_location
/ 4,
1710 vertex_index
, type
, offset
);
1713 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1716 static LLVMValueRef
fetch_input_gs(
1717 struct lp_build_tgsi_context
*bld_base
,
1718 const struct tgsi_full_src_register
*reg
,
1719 enum tgsi_opcode_type type
,
1722 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1723 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1725 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1726 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1727 return get_primitive_id(ctx
, swizzle
);
1729 if (!reg
->Register
.Dimension
)
1732 return si_llvm_load_input_gs(&ctx
->abi
, reg
->Register
.Index
,
1733 reg
->Dimension
.Index
,
1734 tgsi2llvmtype(bld_base
, type
),
1738 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1740 switch (interpolate
) {
1741 case TGSI_INTERPOLATE_CONSTANT
:
1744 case TGSI_INTERPOLATE_LINEAR
:
1745 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1746 return SI_PARAM_LINEAR_SAMPLE
;
1747 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1748 return SI_PARAM_LINEAR_CENTROID
;
1750 return SI_PARAM_LINEAR_CENTER
;
1752 case TGSI_INTERPOLATE_COLOR
:
1753 case TGSI_INTERPOLATE_PERSPECTIVE
:
1754 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1755 return SI_PARAM_PERSP_SAMPLE
;
1756 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1757 return SI_PARAM_PERSP_CENTROID
;
1759 return SI_PARAM_PERSP_CENTER
;
1762 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1767 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1768 unsigned attr_index
, unsigned chan
,
1769 LLVMValueRef prim_mask
,
1770 LLVMValueRef i
, LLVMValueRef j
)
1773 return ac_build_fs_interp(&ctx
->ac
,
1774 LLVMConstInt(ctx
->i32
, chan
, 0),
1775 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1778 return ac_build_fs_interp_mov(&ctx
->ac
,
1779 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1780 LLVMConstInt(ctx
->i32
, chan
, 0),
1781 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1786 * Interpolate a fragment shader input.
1788 * @param ctx context
1789 * @param input_index index of the input in hardware
1790 * @param semantic_name TGSI_SEMANTIC_*
1791 * @param semantic_index semantic index
1792 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1793 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1794 * @param interp_param interpolation weights (i,j)
1795 * @param prim_mask SI_PARAM_PRIM_MASK
1796 * @param face SI_PARAM_FRONT_FACE
1797 * @param result the return value (4 components)
1799 static void interp_fs_input(struct si_shader_context
*ctx
,
1800 unsigned input_index
,
1801 unsigned semantic_name
,
1802 unsigned semantic_index
,
1803 unsigned num_interp_inputs
,
1804 unsigned colors_read_mask
,
1805 LLVMValueRef interp_param
,
1806 LLVMValueRef prim_mask
,
1808 LLVMValueRef result
[4])
1810 LLVMValueRef i
= NULL
, j
= NULL
;
1813 /* fs.constant returns the param from the middle vertex, so it's not
1814 * really useful for flat shading. It's meant to be used for custom
1815 * interpolation (but the intrinsic can't fetch from the other two
1818 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1819 * to do the right thing. The only reason we use fs.constant is that
1820 * fs.interp cannot be used on integers, because they can be equal
1823 * When interp is false we will use fs.constant or for newer llvm,
1824 * amdgcn.interp.mov.
1826 bool interp
= interp_param
!= NULL
;
1829 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1830 LLVMVectorType(ctx
->f32
, 2), "");
1832 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1834 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1838 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1839 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1840 LLVMValueRef is_face_positive
;
1842 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1843 * otherwise it's at offset "num_inputs".
1845 unsigned back_attr_offset
= num_interp_inputs
;
1846 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1847 back_attr_offset
+= 1;
1849 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1850 face
, ctx
->i32_0
, "");
1852 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1853 LLVMValueRef front
, back
;
1855 front
= si_build_fs_interp(ctx
,
1858 back
= si_build_fs_interp(ctx
,
1859 back_attr_offset
, chan
,
1862 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1868 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1869 result
[0] = si_build_fs_interp(ctx
, input_index
,
1870 0, prim_mask
, i
, j
);
1872 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1873 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1875 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1876 result
[chan
] = si_build_fs_interp(ctx
,
1883 void si_llvm_load_input_fs(
1884 struct si_shader_context
*ctx
,
1885 unsigned input_index
,
1886 LLVMValueRef out
[4])
1888 struct si_shader
*shader
= ctx
->shader
;
1889 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1890 LLVMValueRef main_fn
= ctx
->main_fn
;
1891 LLVMValueRef interp_param
= NULL
;
1892 int interp_param_idx
;
1893 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1894 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1895 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1896 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1898 /* Get colors from input VGPRs (set by the prolog). */
1899 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1900 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1901 unsigned mask
= colors_read
>> (semantic_index
* 4);
1902 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1903 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1904 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1906 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1907 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1908 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1909 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1913 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1914 if (interp_param_idx
== -1)
1916 else if (interp_param_idx
) {
1917 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1920 interp_fs_input(ctx
, input_index
, semantic_name
,
1921 semantic_index
, 0, /* this param is unused */
1922 shader
->selector
->info
.colors_read
, interp_param
,
1924 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1928 static void declare_input_fs(
1929 struct si_shader_context
*ctx
,
1930 unsigned input_index
,
1931 const struct tgsi_full_declaration
*decl
,
1932 LLVMValueRef out
[4])
1934 si_llvm_load_input_fs(ctx
, input_index
, out
);
1937 LLVMValueRef
si_get_sample_id(struct si_shader_context
*ctx
)
1939 return si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1942 static LLVMValueRef
get_base_vertex(struct ac_shader_abi
*abi
)
1944 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1946 /* For non-indexed draws, the base vertex set by the driver
1947 * (for direct draws) or the CP (for indirect draws) is the
1948 * first vertex ID, but GLSL expects 0 to be returned.
1950 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
,
1951 ctx
->param_vs_state_bits
);
1952 LLVMValueRef indexed
;
1954 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1955 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1957 return LLVMBuildSelect(ctx
->ac
.builder
, indexed
, ctx
->abi
.base_vertex
,
1961 static LLVMValueRef
get_block_size(struct ac_shader_abi
*abi
)
1963 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1965 LLVMValueRef values
[3];
1966 LLVMValueRef result
;
1968 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1970 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1971 unsigned sizes
[3] = {
1972 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1973 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1974 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1977 for (i
= 0; i
< 3; ++i
)
1978 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1980 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
1982 result
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1989 * Load a dword from a constant buffer.
1991 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1992 LLVMValueRef resource
,
1993 LLVMValueRef offset
)
1995 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1996 0, 0, 0, true, true);
1999 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
, LLVMValueRef sample_id
)
2001 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2002 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2003 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
2004 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
2006 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2007 LLVMValueRef offset0
= LLVMBuildMul(ctx
->ac
.builder
, sample_id
, LLVMConstInt(ctx
->i32
, 8, 0), "");
2008 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2010 LLVMValueRef pos
[4] = {
2011 buffer_load_const(ctx
, resource
, offset0
),
2012 buffer_load_const(ctx
, resource
, offset1
),
2013 LLVMConstReal(ctx
->f32
, 0),
2014 LLVMConstReal(ctx
->f32
, 0)
2017 return ac_build_gather_values(&ctx
->ac
, pos
, 4);
2020 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
2022 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2023 return ac_to_integer(&ctx
->ac
, abi
->sample_coverage
);
2026 static LLVMValueRef
si_load_tess_coord(struct ac_shader_abi
*abi
)
2028 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2029 LLVMValueRef coord
[4] = {
2030 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
2031 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
2036 /* For triangles, the vector should be (u, v, 1-u-v). */
2037 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
2038 PIPE_PRIM_TRIANGLES
) {
2039 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
2040 LLVMBuildFAdd(ctx
->ac
.builder
,
2041 coord
[0], coord
[1], ""), "");
2043 return ac_build_gather_values(&ctx
->ac
, coord
, 4);
2046 static LLVMValueRef
load_tess_level(struct si_shader_context
*ctx
,
2047 unsigned semantic_name
)
2049 LLVMValueRef base
, addr
;
2051 int param
= si_shader_io_get_unique_index_patch(semantic_name
, 0);
2053 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2054 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
2055 LLVMConstInt(ctx
->i32
, param
, 0));
2057 return buffer_load(&ctx
->bld_base
, ctx
->f32
,
2058 ~0, ctx
->tess_offchip_ring
, base
, addr
, true);
2062 static LLVMValueRef
si_load_tess_level(struct ac_shader_abi
*abi
,
2063 unsigned varying_id
)
2065 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2066 unsigned semantic_name
;
2068 switch (varying_id
) {
2069 case VARYING_SLOT_TESS_LEVEL_INNER
:
2070 semantic_name
= TGSI_SEMANTIC_TESSINNER
;
2072 case VARYING_SLOT_TESS_LEVEL_OUTER
:
2073 semantic_name
= TGSI_SEMANTIC_TESSOUTER
;
2076 unreachable("unknown tess level");
2079 return load_tess_level(ctx
, semantic_name
);
2083 static LLVMValueRef
si_load_patch_vertices_in(struct ac_shader_abi
*abi
)
2085 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2086 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2087 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 13, 6);
2088 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
2089 return get_num_tcs_out_vertices(ctx
);
2091 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2094 void si_load_system_value(struct si_shader_context
*ctx
,
2096 const struct tgsi_full_declaration
*decl
)
2098 LLVMValueRef value
= 0;
2100 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
2102 switch (decl
->Semantic
.Name
) {
2103 case TGSI_SEMANTIC_INSTANCEID
:
2104 value
= ctx
->abi
.instance_id
;
2107 case TGSI_SEMANTIC_VERTEXID
:
2108 value
= LLVMBuildAdd(ctx
->ac
.builder
,
2110 ctx
->abi
.base_vertex
, "");
2113 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
2114 /* Unused. Clarify the meaning in indexed vs. non-indexed
2115 * draws if this is ever used again. */
2119 case TGSI_SEMANTIC_BASEVERTEX
:
2120 value
= get_base_vertex(&ctx
->abi
);
2123 case TGSI_SEMANTIC_BASEINSTANCE
:
2124 value
= ctx
->abi
.start_instance
;
2127 case TGSI_SEMANTIC_DRAWID
:
2128 value
= ctx
->abi
.draw_id
;
2131 case TGSI_SEMANTIC_INVOCATIONID
:
2132 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2133 value
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2134 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
2135 value
= ctx
->abi
.gs_invocation_id
;
2137 assert(!"INVOCATIONID not implemented");
2140 case TGSI_SEMANTIC_POSITION
:
2142 LLVMValueRef pos
[4] = {
2143 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2144 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2145 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
2146 lp_build_emit_llvm_unary(&ctx
->bld_base
, TGSI_OPCODE_RCP
,
2147 LLVMGetParam(ctx
->main_fn
,
2148 SI_PARAM_POS_W_FLOAT
)),
2150 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2154 case TGSI_SEMANTIC_FACE
:
2155 value
= ctx
->abi
.front_face
;
2158 case TGSI_SEMANTIC_SAMPLEID
:
2159 value
= si_get_sample_id(ctx
);
2162 case TGSI_SEMANTIC_SAMPLEPOS
: {
2163 LLVMValueRef pos
[4] = {
2164 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2165 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2166 LLVMConstReal(ctx
->f32
, 0),
2167 LLVMConstReal(ctx
->f32
, 0)
2169 pos
[0] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
2170 TGSI_OPCODE_FRC
, pos
[0]);
2171 pos
[1] = lp_build_emit_llvm_unary(&ctx
->bld_base
,
2172 TGSI_OPCODE_FRC
, pos
[1]);
2173 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2177 case TGSI_SEMANTIC_SAMPLEMASK
:
2178 /* This can only occur with the OpenGL Core profile, which
2179 * doesn't support smoothing.
2181 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
2184 case TGSI_SEMANTIC_TESSCOORD
:
2185 value
= si_load_tess_coord(&ctx
->abi
);
2188 case TGSI_SEMANTIC_VERTICESIN
:
2189 value
= si_load_patch_vertices_in(&ctx
->abi
);
2192 case TGSI_SEMANTIC_TESSINNER
:
2193 case TGSI_SEMANTIC_TESSOUTER
:
2194 value
= load_tess_level(ctx
, decl
->Semantic
.Name
);
2197 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
2198 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
2200 LLVMValueRef buf
, slot
, val
[4];
2203 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
2204 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2205 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
2206 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
2208 for (i
= 0; i
< 4; i
++)
2209 val
[i
] = buffer_load_const(ctx
, buf
,
2210 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
2211 value
= ac_build_gather_values(&ctx
->ac
, val
, 4);
2215 case TGSI_SEMANTIC_PRIMID
:
2216 value
= get_primitive_id(ctx
, 0);
2219 case TGSI_SEMANTIC_GRID_SIZE
:
2220 value
= ctx
->abi
.num_work_groups
;
2223 case TGSI_SEMANTIC_BLOCK_SIZE
:
2224 value
= get_block_size(&ctx
->abi
);
2227 case TGSI_SEMANTIC_BLOCK_ID
:
2229 LLVMValueRef values
[3];
2231 for (int i
= 0; i
< 3; i
++) {
2232 values
[i
] = ctx
->i32_0
;
2233 if (ctx
->abi
.workgroup_ids
[i
]) {
2234 values
[i
] = ctx
->abi
.workgroup_ids
[i
];
2237 value
= ac_build_gather_values(&ctx
->ac
, values
, 3);
2241 case TGSI_SEMANTIC_THREAD_ID
:
2242 value
= ctx
->abi
.local_invocation_ids
;
2245 case TGSI_SEMANTIC_HELPER_INVOCATION
:
2246 value
= lp_build_intrinsic(ctx
->ac
.builder
,
2247 "llvm.amdgcn.ps.live",
2249 LP_FUNC_ATTR_READNONE
);
2250 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2251 value
= LLVMBuildSExt(ctx
->ac
.builder
, value
, ctx
->i32
, "");
2254 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
2255 value
= LLVMConstInt(ctx
->i32
, 64, 0);
2258 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
2259 value
= ac_get_thread_id(&ctx
->ac
);
2262 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
2264 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2265 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2266 value
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->i64
, 1, 0), id
, "");
2267 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2271 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
2272 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
2273 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
2274 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
2276 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2277 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
2278 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
2279 /* All bits set except LSB */
2280 value
= LLVMConstInt(ctx
->i64
, -2, 0);
2283 value
= LLVMConstInt(ctx
->i64
, -1, 0);
2285 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2286 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
2287 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
2288 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
2289 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2290 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2295 assert(!"unknown system value");
2299 ctx
->system_values
[index
] = value
;
2302 void si_declare_compute_memory(struct si_shader_context
*ctx
)
2304 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2306 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, AC_LOCAL_ADDR_SPACE
);
2309 assert(!ctx
->ac
.lds
);
2311 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
2312 LLVMArrayType(ctx
->i8
, sel
->local_size
),
2314 AC_LOCAL_ADDR_SPACE
);
2315 LLVMSetAlignment(var
, 4);
2317 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
2320 void si_tgsi_declare_compute_memory(struct si_shader_context
*ctx
,
2321 const struct tgsi_full_declaration
*decl
)
2323 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
2324 assert(decl
->Range
.First
== decl
->Range
.Last
);
2326 si_declare_compute_memory(ctx
);
2329 static LLVMValueRef
load_const_buffer_desc_fast_path(struct si_shader_context
*ctx
)
2332 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2333 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2335 /* Do the bounds checking with a descriptor, because
2336 * doing computation and manual bounds checking of 64-bit
2337 * addresses generates horrible VALU code with very high
2338 * VGPR usage and very low SIMD occupancy.
2340 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->ac
.intptr
, "");
2342 LLVMValueRef desc0
, desc1
;
2343 if (HAVE_32BIT_POINTERS
) {
2345 desc1
= LLVMConstInt(ctx
->i32
,
2346 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
2348 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
, ctx
->v2i32
, "");
2349 desc0
= LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_0
, "");
2350 desc1
= LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_1
, "");
2351 /* Mask out all bits except BASE_ADDRESS_HI. */
2352 desc1
= LLVMBuildAnd(ctx
->ac
.builder
, desc1
,
2353 LLVMConstInt(ctx
->i32
, ~C_008F04_BASE_ADDRESS_HI
, 0), "");
2356 LLVMValueRef desc_elems
[] = {
2359 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2360 LLVMConstInt(ctx
->i32
,
2361 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2362 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2363 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2364 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2365 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2366 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0)
2369 return ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2372 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
2374 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
2375 ctx
->param_const_and_shader_buffers
);
2377 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
2378 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
2381 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
2383 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2384 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2386 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2388 if (sel
->info
.const_buffers_declared
== 1 &&
2389 sel
->info
.shader_buffers_declared
== 0) {
2390 return load_const_buffer_desc_fast_path(ctx
);
2393 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
2394 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2395 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2397 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2401 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
2403 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2404 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
2405 ctx
->param_const_and_shader_buffers
);
2407 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
2408 index
= LLVMBuildSub(ctx
->ac
.builder
,
2409 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
2412 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
2415 static LLVMValueRef
fetch_constant(
2416 struct lp_build_tgsi_context
*bld_base
,
2417 const struct tgsi_full_src_register
*reg
,
2418 enum tgsi_opcode_type type
,
2421 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2422 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2423 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
2426 LLVMValueRef addr
, bufp
;
2428 if (swizzle
== LP_CHAN_ALL
) {
2430 LLVMValueRef values
[4];
2431 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
2432 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
2434 return ac_build_gather_values(&ctx
->ac
, values
, 4);
2437 /* Split 64-bit loads. */
2438 if (tgsi_type_is_64bit(type
)) {
2439 LLVMValueRef lo
, hi
;
2441 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
2442 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
+ 1);
2443 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
2447 idx
= reg
->Register
.Index
* 4 + swizzle
;
2448 if (reg
->Register
.Indirect
) {
2449 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2451 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2454 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2455 if (sel
->info
.const_buffers_declared
== 1 &&
2456 sel
->info
.shader_buffers_declared
== 0) {
2458 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2459 * loads, and up to x4 load opcode merging. However, it leads to horrible
2460 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2462 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2464 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2465 * a descriptor and s_buffer_load_dword using it, so we can't expand
2466 * the pointer into a full descriptor like below. We have to use
2467 * s_load_dword instead. The only case when LLVM 5.0 would select
2468 * s_buffer_load_dword (that we have to prevent) is when we use use
2469 * a literal offset where we don't need bounds checking.
2471 if (ctx
->screen
->info
.chip_class
== SI
&& HAVE_LLVM
< 0x0600 &&
2472 !reg
->Register
.Indirect
) {
2474 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2476 addr
= LLVMBuildLShr(ctx
->ac
.builder
, addr
, LLVMConstInt(ctx
->i32
, 2, 0), "");
2477 LLVMValueRef result
= ac_build_load_invariant(&ctx
->ac
, ptr
, addr
);
2478 return bitcast(bld_base
, type
, result
);
2481 LLVMValueRef desc
= load_const_buffer_desc_fast_path(ctx
);
2482 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2483 return bitcast(bld_base
, type
, result
);
2486 assert(reg
->Register
.Dimension
);
2487 buf
= reg
->Dimension
.Index
;
2489 if (reg
->Dimension
.Indirect
) {
2490 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2492 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2493 reg
->Dimension
.Index
,
2494 ctx
->num_const_buffers
);
2495 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2496 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2497 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2499 bufp
= load_const_buffer_desc(ctx
, buf
);
2501 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2504 /* Initialize arguments for the shader export intrinsic */
2505 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2506 LLVMValueRef
*values
,
2508 struct ac_export_args
*args
)
2510 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2511 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2513 bool is_int8
, is_int10
;
2515 /* Default is 0xf. Adjusted below depending on the format. */
2516 args
->enabled_channels
= 0xf; /* writemask */
2518 /* Specify whether the EXEC mask represents the valid mask */
2519 args
->valid_mask
= 0;
2521 /* Specify whether this is the last export */
2524 /* Specify the target we are exporting */
2525 args
->target
= target
;
2527 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2528 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2529 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2530 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2532 assert(cbuf
>= 0 && cbuf
< 8);
2533 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2534 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2535 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2538 args
->compr
= false;
2539 args
->out
[0] = f32undef
;
2540 args
->out
[1] = f32undef
;
2541 args
->out
[2] = f32undef
;
2542 args
->out
[3] = f32undef
;
2544 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2545 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2546 unsigned bits
, bool hi
) = NULL
;
2548 switch (spi_shader_col_format
) {
2549 case V_028714_SPI_SHADER_ZERO
:
2550 args
->enabled_channels
= 0; /* writemask */
2551 args
->target
= V_008DFC_SQ_EXP_NULL
;
2554 case V_028714_SPI_SHADER_32_R
:
2555 args
->enabled_channels
= 1; /* writemask */
2556 args
->out
[0] = values
[0];
2559 case V_028714_SPI_SHADER_32_GR
:
2560 args
->enabled_channels
= 0x3; /* writemask */
2561 args
->out
[0] = values
[0];
2562 args
->out
[1] = values
[1];
2565 case V_028714_SPI_SHADER_32_AR
:
2566 args
->enabled_channels
= 0x9; /* writemask */
2567 args
->out
[0] = values
[0];
2568 args
->out
[3] = values
[3];
2571 case V_028714_SPI_SHADER_FP16_ABGR
:
2572 packf
= ac_build_cvt_pkrtz_f16
;
2575 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2576 packf
= ac_build_cvt_pknorm_u16
;
2579 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2580 packf
= ac_build_cvt_pknorm_i16
;
2583 case V_028714_SPI_SHADER_UINT16_ABGR
:
2584 packi
= ac_build_cvt_pk_u16
;
2587 case V_028714_SPI_SHADER_SINT16_ABGR
:
2588 packi
= ac_build_cvt_pk_i16
;
2591 case V_028714_SPI_SHADER_32_ABGR
:
2592 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2596 /* Pack f16 or norm_i16/u16. */
2598 for (chan
= 0; chan
< 2; chan
++) {
2599 LLVMValueRef pack_args
[2] = {
2601 values
[2 * chan
+ 1]
2603 LLVMValueRef packed
;
2605 packed
= packf(&ctx
->ac
, pack_args
);
2606 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2608 args
->compr
= 1; /* COMPR flag */
2612 for (chan
= 0; chan
< 2; chan
++) {
2613 LLVMValueRef pack_args
[2] = {
2614 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2615 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2617 LLVMValueRef packed
;
2619 packed
= packi(&ctx
->ac
, pack_args
,
2620 is_int8
? 8 : is_int10
? 10 : 16,
2622 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2624 args
->compr
= 1; /* COMPR flag */
2628 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2631 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2633 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2634 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2635 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2636 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2637 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2638 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2639 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2640 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2642 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2645 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2646 SI_PARAM_ALPHA_REF
);
2647 LLVMValueRef alpha_pass
=
2648 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2649 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2651 ac_build_kill_if_false(&ctx
->ac
, LLVMConstInt(ctx
->i1
, 0, 0));
2655 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2657 unsigned samplemask_param
)
2659 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2660 LLVMValueRef coverage
;
2662 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2663 coverage
= LLVMGetParam(ctx
->main_fn
,
2665 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2667 coverage
= lp_build_intrinsic(ctx
->ac
.builder
, "llvm.ctpop.i32",
2669 &coverage
, 1, LP_FUNC_ATTR_READNONE
);
2671 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2674 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2675 LLVMConstReal(ctx
->f32
,
2676 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2678 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2681 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2682 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2686 unsigned const_chan
;
2687 LLVMValueRef base_elt
;
2688 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2689 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2690 SI_VS_CONST_CLIP_PLANES
, 0);
2691 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2693 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2694 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2699 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2701 /* Compute dot products of position and user clip plane vectors */
2702 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2703 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2705 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2706 const_chan
) * 4, 0);
2707 base_elt
= buffer_load_const(ctx
, const_resource
,
2710 LLVMBuildFAdd(ctx
->ac
.builder
, args
->out
[chan
],
2711 LLVMBuildFMul(ctx
->ac
.builder
, base_elt
,
2712 out_elts
[const_chan
], ""), "");
2716 args
->enabled_channels
= 0xf;
2717 args
->valid_mask
= 0;
2719 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2724 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2728 if (so
->num_outputs
)
2729 fprintf(stderr
, "STREAMOUT\n");
2731 for (i
= 0; i
< so
->num_outputs
; i
++) {
2732 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2733 so
->output
[i
].start_component
;
2734 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2735 i
, so
->output
[i
].output_buffer
,
2736 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2737 so
->output
[i
].register_index
,
2738 mask
& 1 ? "x" : "",
2739 mask
& 2 ? "y" : "",
2740 mask
& 4 ? "z" : "",
2741 mask
& 8 ? "w" : "");
2745 static void emit_streamout_output(struct si_shader_context
*ctx
,
2746 LLVMValueRef
const *so_buffers
,
2747 LLVMValueRef
const *so_write_offsets
,
2748 struct pipe_stream_output
*stream_out
,
2749 struct si_shader_output_values
*shader_out
)
2751 unsigned buf_idx
= stream_out
->output_buffer
;
2752 unsigned start
= stream_out
->start_component
;
2753 unsigned num_comps
= stream_out
->num_components
;
2754 LLVMValueRef out
[4];
2756 assert(num_comps
&& num_comps
<= 4);
2757 if (!num_comps
|| num_comps
> 4)
2760 /* Load the output as int. */
2761 for (int j
= 0; j
< num_comps
; j
++) {
2762 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2764 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2767 /* Pack the output. */
2768 LLVMValueRef vdata
= NULL
;
2770 switch (num_comps
) {
2771 case 1: /* as i32 */
2774 case 2: /* as v2i32 */
2775 case 3: /* as v4i32 (aligned to 4) */
2776 case 4: /* as v4i32 */
2777 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2778 for (int j
= 0; j
< num_comps
; j
++) {
2779 vdata
= LLVMBuildInsertElement(ctx
->ac
.builder
, vdata
, out
[j
],
2780 LLVMConstInt(ctx
->i32
, j
, 0), "");
2785 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2787 so_write_offsets
[buf_idx
],
2789 stream_out
->dst_offset
* 4, 1, 1, true, false);
2793 * Write streamout data to buffers for vertex stream @p stream (different
2794 * vertex streams can occur for GS copy shaders).
2796 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2797 struct si_shader_output_values
*outputs
,
2798 unsigned noutput
, unsigned stream
)
2800 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2801 struct pipe_stream_output_info
*so
= &sel
->so
;
2802 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2804 struct lp_build_if_state if_ctx
;
2806 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2807 LLVMValueRef so_vtx_count
=
2808 si_unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2810 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2812 /* can_emit = tid < so_vtx_count; */
2813 LLVMValueRef can_emit
=
2814 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2816 /* Emit the streamout code conditionally. This actually avoids
2817 * out-of-bounds buffer access. The hw tells us via the SGPR
2818 * (so_vtx_count) which threads are allowed to emit streamout data. */
2819 lp_build_if(&if_ctx
, &ctx
->gallivm
, can_emit
);
2821 /* The buffer offset is computed as follows:
2822 * ByteOffset = streamout_offset[buffer_id]*4 +
2823 * (streamout_write_index + thread_id)*stride[buffer_id] +
2827 LLVMValueRef so_write_index
=
2828 LLVMGetParam(ctx
->main_fn
,
2829 ctx
->param_streamout_write_index
);
2831 /* Compute (streamout_write_index + thread_id). */
2832 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2834 /* Load the descriptor and compute the write offset for each
2835 * enabled buffer. */
2836 LLVMValueRef so_write_offset
[4] = {};
2837 LLVMValueRef so_buffers
[4];
2838 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2839 ctx
->param_rw_buffers
);
2841 for (i
= 0; i
< 4; i
++) {
2845 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2846 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2848 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2850 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2851 ctx
->param_streamout_offset
[i
]);
2852 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2854 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2855 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2856 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2859 /* Write streamout data. */
2860 for (i
= 0; i
< so
->num_outputs
; i
++) {
2861 unsigned reg
= so
->output
[i
].register_index
;
2866 if (stream
!= so
->output
[i
].stream
)
2869 emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2870 &so
->output
[i
], &outputs
[reg
]);
2873 lp_build_endif(&if_ctx
);
2876 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2877 LLVMValueRef
*values
)
2879 struct ac_export_args args
;
2881 si_llvm_init_export_args(ctx
, values
,
2882 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2883 ac_build_export(&ctx
->ac
, &args
);
2886 static void si_build_param_exports(struct si_shader_context
*ctx
,
2887 struct si_shader_output_values
*outputs
,
2890 struct si_shader
*shader
= ctx
->shader
;
2891 unsigned param_count
= 0;
2893 for (unsigned i
= 0; i
< noutput
; i
++) {
2894 unsigned semantic_name
= outputs
[i
].semantic_name
;
2895 unsigned semantic_index
= outputs
[i
].semantic_index
;
2897 if (outputs
[i
].vertex_stream
[0] != 0 &&
2898 outputs
[i
].vertex_stream
[1] != 0 &&
2899 outputs
[i
].vertex_stream
[2] != 0 &&
2900 outputs
[i
].vertex_stream
[3] != 0)
2903 switch (semantic_name
) {
2904 case TGSI_SEMANTIC_LAYER
:
2905 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2906 case TGSI_SEMANTIC_CLIPDIST
:
2907 case TGSI_SEMANTIC_COLOR
:
2908 case TGSI_SEMANTIC_BCOLOR
:
2909 case TGSI_SEMANTIC_PRIMID
:
2910 case TGSI_SEMANTIC_FOG
:
2911 case TGSI_SEMANTIC_TEXCOORD
:
2912 case TGSI_SEMANTIC_GENERIC
:
2918 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2919 semantic_index
< SI_MAX_IO_GENERIC
) &&
2920 shader
->key
.opt
.kill_outputs
&
2921 (1ull << si_shader_io_get_unique_index(semantic_name
,
2922 semantic_index
, true)))
2925 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2927 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2928 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2931 shader
->info
.nr_param_exports
= param_count
;
2934 /* Generate export instructions for hardware VS shader stage */
2935 static void si_llvm_export_vs(struct si_shader_context
*ctx
,
2936 struct si_shader_output_values
*outputs
,
2939 struct si_shader
*shader
= ctx
->shader
;
2940 struct ac_export_args pos_args
[4] = {};
2941 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2945 /* Build position exports. */
2946 for (i
= 0; i
< noutput
; i
++) {
2947 switch (outputs
[i
].semantic_name
) {
2948 case TGSI_SEMANTIC_POSITION
:
2949 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2950 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2952 case TGSI_SEMANTIC_PSIZE
:
2953 psize_value
= outputs
[i
].values
[0];
2955 case TGSI_SEMANTIC_LAYER
:
2956 layer_value
= outputs
[i
].values
[0];
2958 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2959 viewport_index_value
= outputs
[i
].values
[0];
2961 case TGSI_SEMANTIC_EDGEFLAG
:
2962 edgeflag_value
= outputs
[i
].values
[0];
2964 case TGSI_SEMANTIC_CLIPDIST
:
2965 if (!shader
->key
.opt
.clip_disable
) {
2966 unsigned index
= 2 + outputs
[i
].semantic_index
;
2967 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2968 V_008DFC_SQ_EXP_POS
+ index
,
2972 case TGSI_SEMANTIC_CLIPVERTEX
:
2973 if (!shader
->key
.opt
.clip_disable
) {
2974 si_llvm_emit_clipvertex(ctx
, pos_args
,
2981 /* We need to add the position output manually if it's missing. */
2982 if (!pos_args
[0].out
[0]) {
2983 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2984 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2985 pos_args
[0].done
= 0; /* last export? */
2986 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2987 pos_args
[0].compr
= 0; /* COMPR flag */
2988 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2989 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2990 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2991 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2994 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2995 if (shader
->selector
->info
.writes_psize
||
2996 shader
->selector
->info
.writes_edgeflag
||
2997 shader
->selector
->info
.writes_viewport_index
||
2998 shader
->selector
->info
.writes_layer
) {
2999 pos_args
[1].enabled_channels
= shader
->selector
->info
.writes_psize
|
3000 (shader
->selector
->info
.writes_edgeflag
<< 1) |
3001 (shader
->selector
->info
.writes_layer
<< 2);
3003 pos_args
[1].valid_mask
= 0; /* EXEC mask */
3004 pos_args
[1].done
= 0; /* last export? */
3005 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
3006 pos_args
[1].compr
= 0; /* COMPR flag */
3007 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
3008 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
3009 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
3010 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
3012 if (shader
->selector
->info
.writes_psize
)
3013 pos_args
[1].out
[0] = psize_value
;
3015 if (shader
->selector
->info
.writes_edgeflag
) {
3016 /* The output is a float, but the hw expects an integer
3017 * with the first bit containing the edge flag. */
3018 edgeflag_value
= LLVMBuildFPToUI(ctx
->ac
.builder
,
3021 edgeflag_value
= ac_build_umin(&ctx
->ac
,
3025 /* The LLVM intrinsic expects a float. */
3026 pos_args
[1].out
[1] = ac_to_float(&ctx
->ac
, edgeflag_value
);
3029 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3030 /* GFX9 has the layer in out.z[10:0] and the viewport
3031 * index in out.z[19:16].
3033 if (shader
->selector
->info
.writes_layer
)
3034 pos_args
[1].out
[2] = layer_value
;
3036 if (shader
->selector
->info
.writes_viewport_index
) {
3037 LLVMValueRef v
= viewport_index_value
;
3039 v
= ac_to_integer(&ctx
->ac
, v
);
3040 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
3041 LLVMConstInt(ctx
->i32
, 16, 0), "");
3042 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
3043 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
3044 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
3045 pos_args
[1].enabled_channels
|= 1 << 2;
3048 if (shader
->selector
->info
.writes_layer
)
3049 pos_args
[1].out
[2] = layer_value
;
3051 if (shader
->selector
->info
.writes_viewport_index
) {
3052 pos_args
[1].out
[3] = viewport_index_value
;
3053 pos_args
[1].enabled_channels
|= 1 << 3;
3058 for (i
= 0; i
< 4; i
++)
3059 if (pos_args
[i
].out
[0])
3060 shader
->info
.nr_pos_exports
++;
3063 for (i
= 0; i
< 4; i
++) {
3064 if (!pos_args
[i
].out
[0])
3067 /* Specify the target we are exporting */
3068 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
3070 if (pos_idx
== shader
->info
.nr_pos_exports
)
3071 /* Specify that this is the last export */
3072 pos_args
[i
].done
= 1;
3074 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
3077 /* Build parameter exports. */
3078 si_build_param_exports(ctx
, outputs
, noutput
);
3082 * Forward all outputs from the vertex shader to the TES. This is only used
3083 * for the fixed function TCS.
3085 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
3087 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3088 LLVMValueRef invocation_id
, buffer
, buffer_offset
;
3089 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
3092 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3093 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3094 buffer_offset
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3096 lds_vertex_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3097 lds_vertex_offset
= LLVMBuildMul(ctx
->ac
.builder
, invocation_id
,
3098 lds_vertex_stride
, "");
3099 lds_base
= get_tcs_in_current_patch_offset(ctx
);
3100 lds_base
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
, lds_vertex_offset
, "");
3102 inputs
= ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
;
3104 unsigned i
= u_bit_scan64(&inputs
);
3106 LLVMValueRef lds_ptr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3107 LLVMConstInt(ctx
->i32
, 4 * i
, 0),
3110 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
3111 get_rel_patch_id(ctx
),
3113 LLVMConstInt(ctx
->i32
, i
, 0));
3115 LLVMValueRef value
= lds_load(bld_base
, ctx
->ac
.i32
, ~0,
3118 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buffer_addr
,
3119 buffer_offset
, 0, 1, 0, true, false);
3123 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
3124 LLVMValueRef rel_patch_id
,
3125 LLVMValueRef invocation_id
,
3126 LLVMValueRef tcs_out_current_patch_data_offset
,
3127 LLVMValueRef invoc0_tf_outer
[4],
3128 LLVMValueRef invoc0_tf_inner
[2])
3130 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3131 struct si_shader
*shader
= ctx
->shader
;
3132 unsigned tess_inner_index
, tess_outer_index
;
3133 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
3134 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3135 unsigned stride
, outer_comps
, inner_comps
, i
, offset
;
3136 struct lp_build_if_state if_ctx
, inner_if_ctx
;
3138 /* Add a barrier before loading tess factors from LDS. */
3139 if (!shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
)
3140 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
3142 /* Do this only for invocation 0, because the tess levels are per-patch,
3145 * This can't jump, because invocation 0 executes this. It should
3146 * at least mask out the loads and stores for other invocations.
3148 lp_build_if(&if_ctx
, &ctx
->gallivm
,
3149 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3150 invocation_id
, ctx
->i32_0
, ""));
3152 /* Determine the layout of one tess factor element in the buffer. */
3153 switch (shader
->key
.part
.tcs
.epilog
.prim_mode
) {
3154 case PIPE_PRIM_LINES
:
3155 stride
= 2; /* 2 dwords, 1 vec2 store */
3159 case PIPE_PRIM_TRIANGLES
:
3160 stride
= 4; /* 4 dwords, 1 vec4 store */
3164 case PIPE_PRIM_QUADS
:
3165 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3174 for (i
= 0; i
< 4; i
++) {
3175 inner
[i
] = LLVMGetUndef(ctx
->i32
);
3176 outer
[i
] = LLVMGetUndef(ctx
->i32
);
3179 if (shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
) {
3180 /* Tess factors are in VGPRs. */
3181 for (i
= 0; i
< outer_comps
; i
++)
3182 outer
[i
] = out
[i
] = invoc0_tf_outer
[i
];
3183 for (i
= 0; i
< inner_comps
; i
++)
3184 inner
[i
] = out
[outer_comps
+i
] = invoc0_tf_inner
[i
];
3186 /* Load tess_inner and tess_outer from LDS.
3187 * Any invocation can write them, so we can't get them from a temporary.
3189 tess_inner_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0);
3190 tess_outer_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0);
3192 lds_base
= tcs_out_current_patch_data_offset
;
3193 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3194 LLVMConstInt(ctx
->i32
,
3195 tess_inner_index
* 4, 0), "");
3196 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3197 LLVMConstInt(ctx
->i32
,
3198 tess_outer_index
* 4, 0), "");
3200 for (i
= 0; i
< outer_comps
; i
++) {
3202 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_outer
);
3204 for (i
= 0; i
< inner_comps
; i
++) {
3205 inner
[i
] = out
[outer_comps
+i
] =
3206 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_inner
);
3210 if (shader
->key
.part
.tcs
.epilog
.prim_mode
== PIPE_PRIM_LINES
) {
3211 /* For isolines, the hardware expects tess factors in the
3212 * reverse order from what GLSL / TGSI specify.
3214 LLVMValueRef tmp
= out
[0];
3219 /* Convert the outputs to vectors for stores. */
3220 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3224 vec1
= ac_build_gather_values(&ctx
->ac
, out
+4, stride
- 4);
3226 /* Get the buffer. */
3227 buffer
= get_tess_ring_descriptor(ctx
, TCS_FACTOR_RING
);
3229 /* Get the offset. */
3230 tf_base
= LLVMGetParam(ctx
->main_fn
,
3231 ctx
->param_tcs_factor_offset
);
3232 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3233 LLVMConstInt(ctx
->i32
, 4 * stride
, 0), "");
3235 lp_build_if(&inner_if_ctx
, &ctx
->gallivm
,
3236 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3237 rel_patch_id
, ctx
->i32_0
, ""));
3239 /* Store the dynamic HS control word. */
3241 if (ctx
->screen
->info
.chip_class
<= VI
) {
3242 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3243 LLVMConstInt(ctx
->i32
, 0x80000000, 0),
3244 1, ctx
->i32_0
, tf_base
,
3245 offset
, 1, 0, true, false);
3249 lp_build_endif(&inner_if_ctx
);
3251 /* Store the tessellation factors. */
3252 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3253 MIN2(stride
, 4), byteoffset
, tf_base
,
3254 offset
, 1, 0, true, false);
3257 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3258 stride
- 4, byteoffset
, tf_base
,
3259 offset
, 1, 0, true, false);
3261 /* Store the tess factors into the offchip buffer if TES reads them. */
3262 if (shader
->key
.part
.tcs
.epilog
.tes_reads_tess_factors
) {
3263 LLVMValueRef buf
, base
, inner_vec
, outer_vec
, tf_outer_offset
;
3264 LLVMValueRef tf_inner_offset
;
3265 unsigned param_outer
, param_inner
;
3267 buf
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3268 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3270 param_outer
= si_shader_io_get_unique_index_patch(
3271 TGSI_SEMANTIC_TESSOUTER
, 0);
3272 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3273 LLVMConstInt(ctx
->i32
, param_outer
, 0));
3275 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3276 util_next_power_of_two(outer_comps
));
3278 ac_build_buffer_store_dword(&ctx
->ac
, buf
, outer_vec
,
3279 outer_comps
, tf_outer_offset
,
3280 base
, 0, 1, 0, true, false);
3282 param_inner
= si_shader_io_get_unique_index_patch(
3283 TGSI_SEMANTIC_TESSINNER
, 0);
3284 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3285 LLVMConstInt(ctx
->i32
, param_inner
, 0));
3287 inner_vec
= inner_comps
== 1 ? inner
[0] :
3288 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3289 ac_build_buffer_store_dword(&ctx
->ac
, buf
, inner_vec
,
3290 inner_comps
, tf_inner_offset
,
3291 base
, 0, 1, 0, true, false);
3295 lp_build_endif(&if_ctx
);
3299 si_insert_input_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3300 unsigned param
, unsigned return_index
)
3302 return LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3303 LLVMGetParam(ctx
->main_fn
, param
),
3308 si_insert_input_ret_float(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3309 unsigned param
, unsigned return_index
)
3311 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3312 LLVMValueRef p
= LLVMGetParam(ctx
->main_fn
, param
);
3314 return LLVMBuildInsertValue(builder
, ret
,
3315 ac_to_float(&ctx
->ac
, p
),
3320 si_insert_input_ptr(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3321 unsigned param
, unsigned return_index
)
3323 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3324 LLVMValueRef ptr
, lo
, hi
;
3326 if (HAVE_32BIT_POINTERS
) {
3327 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
3328 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i32
, "");
3329 return LLVMBuildInsertValue(builder
, ret
, ptr
, return_index
, "");
3332 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
3333 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i64
, "");
3334 ptr
= LLVMBuildBitCast(builder
, ptr
, ctx
->v2i32
, "");
3335 lo
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_0
, "");
3336 hi
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_1
, "");
3337 ret
= LLVMBuildInsertValue(builder
, ret
, lo
, return_index
, "");
3338 return LLVMBuildInsertValue(builder
, ret
, hi
, return_index
+ 1, "");
3341 /* This only writes the tessellation factor levels. */
3342 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi
*abi
,
3343 unsigned max_outputs
,
3344 LLVMValueRef
*addrs
)
3346 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3347 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
3348 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3349 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
3351 si_copy_tcs_inputs(bld_base
);
3353 rel_patch_id
= get_rel_patch_id(ctx
);
3354 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3355 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
3357 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3358 LLVMBasicBlockRef blocks
[2] = {
3359 LLVMGetInsertBlock(builder
),
3360 ctx
->merged_wrap_if_state
.entry_block
3362 LLVMValueRef values
[2];
3364 lp_build_endif(&ctx
->merged_wrap_if_state
);
3366 values
[0] = rel_patch_id
;
3367 values
[1] = LLVMGetUndef(ctx
->i32
);
3368 rel_patch_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3370 values
[0] = tf_lds_offset
;
3371 values
[1] = LLVMGetUndef(ctx
->i32
);
3372 tf_lds_offset
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3374 values
[0] = invocation_id
;
3375 values
[1] = ctx
->i32_1
; /* cause the epilog to skip threads */
3376 invocation_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3379 /* Return epilog parameters from this function. */
3380 LLVMValueRef ret
= ctx
->return_value
;
3383 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3384 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3385 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3386 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3387 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3388 /* Tess offchip and tess factor offsets are at the beginning. */
3389 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3390 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3391 vgpr
= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
+ 1;
3393 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3394 GFX6_SGPR_TCS_OFFCHIP_LAYOUT
);
3395 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3396 GFX6_SGPR_TCS_OUT_LAYOUT
);
3397 /* Tess offchip and tess factor offsets are after user SGPRs. */
3398 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
,
3399 GFX6_TCS_NUM_USER_SGPR
);
3400 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
,
3401 GFX6_TCS_NUM_USER_SGPR
+ 1);
3402 vgpr
= GFX6_TCS_NUM_USER_SGPR
+ 2;
3406 rel_patch_id
= ac_to_float(&ctx
->ac
, rel_patch_id
);
3407 invocation_id
= ac_to_float(&ctx
->ac
, invocation_id
);
3408 tf_lds_offset
= ac_to_float(&ctx
->ac
, tf_lds_offset
);
3410 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3411 * the invocation_id output does not alias the tcs_rel_ids input,
3412 * which saves a V_MOV on gfx9.
3416 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
3417 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
3419 if (ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
3420 vgpr
++; /* skip the tess factor LDS offset */
3421 for (unsigned i
= 0; i
< 6; i
++) {
3422 LLVMValueRef value
=
3423 LLVMBuildLoad(builder
, ctx
->invoc0_tess_factors
[i
], "");
3424 value
= ac_to_float(&ctx
->ac
, value
);
3425 ret
= LLVMBuildInsertValue(builder
, ret
, value
, vgpr
++, "");
3428 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
3430 ctx
->return_value
= ret
;
3433 /* Pass TCS inputs from LS to TCS on GFX9. */
3434 static void si_set_ls_return_value_for_tcs(struct si_shader_context
*ctx
)
3436 LLVMValueRef ret
= ctx
->return_value
;
3438 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3439 if (HAVE_32BIT_POINTERS
)
3440 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3441 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3442 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3443 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3444 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3446 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3447 8 + SI_SGPR_RW_BUFFERS
);
3448 ret
= si_insert_input_ptr(ctx
, ret
,
3449 ctx
->param_bindless_samplers_and_images
,
3450 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3452 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_vs_state_bits
,
3453 8 + SI_SGPR_VS_STATE_BITS
);
3455 #if !HAVE_32BIT_POINTERS
3456 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_vs_state_bits
+ 1,
3457 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
);
3460 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3461 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3462 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_offsets
,
3463 8 + GFX9_SGPR_TCS_OUT_OFFSETS
);
3464 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3465 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3467 unsigned vgpr
= 8 + GFX9_TCS_NUM_USER_SGPR
;
3468 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3469 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_patch_id
),
3471 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3472 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
),
3474 ctx
->return_value
= ret
;
3477 /* Pass GS inputs from ES to GS on GFX9. */
3478 static void si_set_es_return_value_for_gs(struct si_shader_context
*ctx
)
3480 LLVMValueRef ret
= ctx
->return_value
;
3482 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3483 if (HAVE_32BIT_POINTERS
)
3484 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3485 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_gs2vs_offset
, 2);
3486 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3487 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3489 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3490 8 + SI_SGPR_RW_BUFFERS
);
3491 ret
= si_insert_input_ptr(ctx
, ret
,
3492 ctx
->param_bindless_samplers_and_images
,
3493 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3495 #if !HAVE_32BIT_POINTERS
3496 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_vs_state_bits
+ 1,
3497 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
);
3501 if (ctx
->type
== PIPE_SHADER_VERTEX
)
3502 vgpr
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
3504 vgpr
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
3506 for (unsigned i
= 0; i
< 5; i
++) {
3507 unsigned param
= ctx
->param_gs_vtx01_offset
+ i
;
3508 ret
= si_insert_input_ret_float(ctx
, ret
, param
, vgpr
++);
3510 ctx
->return_value
= ret
;
3513 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi
*abi
,
3514 unsigned max_outputs
,
3515 LLVMValueRef
*addrs
)
3517 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3518 struct si_shader
*shader
= ctx
->shader
;
3519 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3521 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->main_fn
,
3522 ctx
->param_rel_auto_id
);
3523 LLVMValueRef vertex_dw_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3524 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3525 vertex_dw_stride
, "");
3527 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3528 * its inputs from it. */
3529 for (i
= 0; i
< info
->num_outputs
; i
++) {
3530 unsigned name
= info
->output_semantic_name
[i
];
3531 unsigned index
= info
->output_semantic_index
[i
];
3533 /* The ARB_shader_viewport_layer_array spec contains the
3536 * 2) What happens if gl_ViewportIndex or gl_Layer is
3537 * written in the vertex shader and a geometry shader is
3540 * RESOLVED: The value written by the last vertex processing
3541 * stage is used. If the last vertex processing stage
3542 * (vertex, tessellation evaluation or geometry) does not
3543 * statically assign to gl_ViewportIndex or gl_Layer, index
3544 * or layer zero is assumed.
3546 * So writes to those outputs in VS-as-LS are simply ignored.
3548 if (name
== TGSI_SEMANTIC_LAYER
||
3549 name
== TGSI_SEMANTIC_VIEWPORT_INDEX
)
3552 int param
= si_shader_io_get_unique_index(name
, index
, false);
3553 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3554 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
3556 for (chan
= 0; chan
< 4; chan
++) {
3557 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3560 lds_store(ctx
, chan
, dw_addr
,
3561 LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], ""));
3565 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3566 si_set_ls_return_value_for_tcs(ctx
);
3569 static void si_llvm_emit_es_epilogue(struct ac_shader_abi
*abi
,
3570 unsigned max_outputs
,
3571 LLVMValueRef
*addrs
)
3573 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3574 struct si_shader
*es
= ctx
->shader
;
3575 struct tgsi_shader_info
*info
= &es
->selector
->info
;
3576 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
3577 ctx
->param_es2gs_offset
);
3578 LLVMValueRef lds_base
= NULL
;
3582 if (ctx
->screen
->info
.chip_class
>= GFX9
&& info
->num_outputs
) {
3583 unsigned itemsize_dw
= es
->selector
->esgs_itemsize
/ 4;
3584 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3585 LLVMValueRef wave_idx
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 24, 4);
3586 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3587 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3588 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
3589 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3590 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
3593 for (i
= 0; i
< info
->num_outputs
; i
++) {
3596 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
3597 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
3600 param
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
3601 info
->output_semantic_index
[i
], false);
3603 for (chan
= 0; chan
< 4; chan
++) {
3604 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3607 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3608 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3610 /* GFX9 has the ESGS ring in LDS. */
3611 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3612 lds_store(ctx
, param
* 4 + chan
, lds_base
, out_val
);
3616 ac_build_buffer_store_dword(&ctx
->ac
,
3618 out_val
, 1, NULL
, soffset
,
3619 (4 * param
+ chan
) * 4,
3624 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3625 si_set_es_return_value_for_gs(ctx
);
3628 static LLVMValueRef
si_get_gs_wave_id(struct si_shader_context
*ctx
)
3630 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3631 return si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 16, 8);
3633 return LLVMGetParam(ctx
->main_fn
, ctx
->param_gs_wave_id
);
3636 static void emit_gs_epilogue(struct si_shader_context
*ctx
)
3638 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
,
3639 si_get_gs_wave_id(ctx
));
3641 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3642 lp_build_endif(&ctx
->merged_wrap_if_state
);
3645 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi
*abi
,
3646 unsigned max_outputs
,
3647 LLVMValueRef
*addrs
)
3649 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3650 struct tgsi_shader_info UNUSED
*info
= &ctx
->shader
->selector
->info
;
3652 assert(info
->num_outputs
<= max_outputs
);
3654 emit_gs_epilogue(ctx
);
3657 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3659 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3660 emit_gs_epilogue(ctx
);
3663 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi
*abi
,
3664 unsigned max_outputs
,
3665 LLVMValueRef
*addrs
)
3667 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3668 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3669 struct si_shader_output_values
*outputs
= NULL
;
3672 assert(!ctx
->shader
->is_gs_copy_shader
);
3673 assert(info
->num_outputs
<= max_outputs
);
3675 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
3677 /* Vertex color clamping.
3679 * This uses a state constant loaded in a user data SGPR and
3680 * an IF statement is added that clamps all colors if the constant
3683 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
3684 struct lp_build_if_state if_ctx
;
3685 LLVMValueRef cond
= NULL
;
3686 LLVMValueRef addr
, val
;
3688 for (i
= 0; i
< info
->num_outputs
; i
++) {
3689 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
3690 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
3693 /* We've found a color. */
3695 /* The state is in the first bit of the user SGPR. */
3696 cond
= LLVMGetParam(ctx
->main_fn
,
3697 ctx
->param_vs_state_bits
);
3698 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
,
3700 lp_build_if(&if_ctx
, &ctx
->gallivm
, cond
);
3703 for (j
= 0; j
< 4; j
++) {
3704 addr
= addrs
[4 * i
+ j
];
3705 val
= LLVMBuildLoad(ctx
->ac
.builder
, addr
, "");
3706 val
= ac_build_clamp(&ctx
->ac
, val
);
3707 LLVMBuildStore(ctx
->ac
.builder
, val
, addr
);
3712 lp_build_endif(&if_ctx
);
3715 for (i
= 0; i
< info
->num_outputs
; i
++) {
3716 outputs
[i
].semantic_name
= info
->output_semantic_name
[i
];
3717 outputs
[i
].semantic_index
= info
->output_semantic_index
[i
];
3719 for (j
= 0; j
< 4; j
++) {
3720 outputs
[i
].values
[j
] =
3721 LLVMBuildLoad(ctx
->ac
.builder
,
3724 outputs
[i
].vertex_stream
[j
] =
3725 (info
->output_streams
[i
] >> (2 * j
)) & 3;
3729 if (ctx
->shader
->selector
->so
.num_outputs
)
3730 si_llvm_emit_streamout(ctx
, outputs
, i
, 0);
3732 /* Export PrimitiveID. */
3733 if (ctx
->shader
->key
.mono
.u
.vs_export_prim_id
) {
3734 outputs
[i
].semantic_name
= TGSI_SEMANTIC_PRIMID
;
3735 outputs
[i
].semantic_index
= 0;
3736 outputs
[i
].values
[0] = ac_to_float(&ctx
->ac
, get_primitive_id(ctx
, 0));
3737 for (j
= 1; j
< 4; j
++)
3738 outputs
[i
].values
[j
] = LLVMConstReal(ctx
->f32
, 0);
3740 memset(outputs
[i
].vertex_stream
, 0,
3741 sizeof(outputs
[i
].vertex_stream
));
3745 si_llvm_export_vs(ctx
, outputs
, i
);
3749 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context
*bld_base
)
3751 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3753 ctx
->abi
.emit_outputs(&ctx
->abi
, RADEON_LLVM_MAX_OUTPUTS
,
3754 &ctx
->outputs
[0][0]);
3757 struct si_ps_exports
{
3759 struct ac_export_args args
[10];
3762 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
3763 LLVMValueRef depth
, LLVMValueRef stencil
,
3764 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
3766 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3767 struct ac_export_args args
;
3769 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3771 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3774 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
3775 LLVMValueRef
*color
, unsigned index
,
3776 unsigned samplemask_param
,
3777 bool is_last
, struct si_ps_exports
*exp
)
3779 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3783 if (ctx
->shader
->key
.part
.ps
.epilog
.clamp_color
)
3784 for (i
= 0; i
< 4; i
++)
3785 color
[i
] = ac_build_clamp(&ctx
->ac
, color
[i
]);
3788 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_to_one
)
3789 color
[3] = ctx
->ac
.f32_1
;
3793 ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
3794 si_alpha_test(bld_base
, color
[3]);
3796 /* Line & polygon smoothing */
3797 if (ctx
->shader
->key
.part
.ps
.epilog
.poly_line_smoothing
)
3798 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3801 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3802 if (ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
> 0) {
3803 struct ac_export_args args
[8];
3806 /* Get the export arguments, also find out what the last one is. */
3807 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3808 si_llvm_init_export_args(ctx
, color
,
3809 V_008DFC_SQ_EXP_MRT
+ c
, &args
[c
]);
3810 if (args
[c
].enabled_channels
)
3814 /* Emit all exports. */
3815 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3816 if (is_last
&& last
== c
) {
3817 args
[c
].valid_mask
= 1; /* whether the EXEC mask is valid */
3818 args
[c
].done
= 1; /* DONE bit */
3819 } else if (!args
[c
].enabled_channels
)
3820 continue; /* unnecessary NULL export */
3822 memcpy(&exp
->args
[exp
->num
++], &args
[c
], sizeof(args
[c
]));
3825 struct ac_export_args args
;
3828 si_llvm_init_export_args(ctx
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3831 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3832 args
.done
= 1; /* DONE bit */
3833 } else if (!args
.enabled_channels
)
3834 return; /* unnecessary NULL export */
3836 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3840 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3841 struct si_ps_exports
*exp
)
3843 for (unsigned i
= 0; i
< exp
->num
; i
++)
3844 ac_build_export(&ctx
->ac
, &exp
->args
[i
]);
3848 * Return PS outputs in this order:
3850 * v[0:3] = color0.xyzw
3851 * v[4:7] = color1.xyzw
3856 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3858 * The alpha-ref SGPR is returned via its original location.
3860 static void si_llvm_return_fs_outputs(struct ac_shader_abi
*abi
,
3861 unsigned max_outputs
,
3862 LLVMValueRef
*addrs
)
3864 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3865 struct si_shader
*shader
= ctx
->shader
;
3866 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3867 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3868 unsigned i
, j
, first_vgpr
, vgpr
;
3870 LLVMValueRef color
[8][4] = {};
3871 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3874 if (ctx
->postponed_kill
)
3875 ac_build_kill_if_false(&ctx
->ac
, LLVMBuildLoad(builder
, ctx
->postponed_kill
, ""));
3877 /* Read the output values. */
3878 for (i
= 0; i
< info
->num_outputs
; i
++) {
3879 unsigned semantic_name
= info
->output_semantic_name
[i
];
3880 unsigned semantic_index
= info
->output_semantic_index
[i
];
3882 switch (semantic_name
) {
3883 case TGSI_SEMANTIC_COLOR
:
3884 assert(semantic_index
< 8);
3885 for (j
= 0; j
< 4; j
++) {
3886 LLVMValueRef ptr
= addrs
[4 * i
+ j
];
3887 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3888 color
[semantic_index
][j
] = result
;
3891 case TGSI_SEMANTIC_POSITION
:
3892 depth
= LLVMBuildLoad(builder
,
3893 addrs
[4 * i
+ 2], "");
3895 case TGSI_SEMANTIC_STENCIL
:
3896 stencil
= LLVMBuildLoad(builder
,
3897 addrs
[4 * i
+ 1], "");
3899 case TGSI_SEMANTIC_SAMPLEMASK
:
3900 samplemask
= LLVMBuildLoad(builder
,
3901 addrs
[4 * i
+ 0], "");
3904 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3909 /* Fill the return structure. */
3910 ret
= ctx
->return_value
;
3913 ret
= LLVMBuildInsertValue(builder
, ret
,
3914 ac_to_integer(&ctx
->ac
,
3915 LLVMGetParam(ctx
->main_fn
,
3916 SI_PARAM_ALPHA_REF
)),
3917 SI_SGPR_ALPHA_REF
, "");
3920 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3921 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3925 for (j
= 0; j
< 4; j
++)
3926 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3929 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3931 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3933 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3935 /* Add the input sample mask for smoothing at the end. */
3936 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3937 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3938 ret
= LLVMBuildInsertValue(builder
, ret
,
3939 LLVMGetParam(ctx
->main_fn
,
3940 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3942 ctx
->return_value
= ret
;
3945 static void membar_emit(
3946 const struct lp_build_tgsi_action
*action
,
3947 struct lp_build_tgsi_context
*bld_base
,
3948 struct lp_build_emit_data
*emit_data
)
3950 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3951 LLVMValueRef src0
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
3952 unsigned flags
= LLVMConstIntGetZExtValue(src0
);
3953 unsigned waitcnt
= NOOP_WAITCNT
;
3955 if (flags
& TGSI_MEMBAR_THREAD_GROUP
)
3956 waitcnt
&= VM_CNT
& LGKM_CNT
;
3958 if (flags
& (TGSI_MEMBAR_ATOMIC_BUFFER
|
3959 TGSI_MEMBAR_SHADER_BUFFER
|
3960 TGSI_MEMBAR_SHADER_IMAGE
))
3963 if (flags
& TGSI_MEMBAR_SHARED
)
3964 waitcnt
&= LGKM_CNT
;
3966 if (waitcnt
!= NOOP_WAITCNT
)
3967 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3970 static void clock_emit(
3971 const struct lp_build_tgsi_action
*action
,
3972 struct lp_build_tgsi_context
*bld_base
,
3973 struct lp_build_emit_data
*emit_data
)
3975 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3976 LLVMValueRef tmp
= ac_build_shader_clock(&ctx
->ac
);
3978 emit_data
->output
[0] =
3979 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_0
, "");
3980 emit_data
->output
[1] =
3981 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_1
, "");
3984 static void si_llvm_emit_ddxy(
3985 const struct lp_build_tgsi_action
*action
,
3986 struct lp_build_tgsi_context
*bld_base
,
3987 struct lp_build_emit_data
*emit_data
)
3989 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3990 unsigned opcode
= emit_data
->info
->opcode
;
3995 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3996 mask
= AC_TID_MASK_LEFT
;
3997 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3998 mask
= AC_TID_MASK_TOP
;
4000 mask
= AC_TID_MASK_TOP_LEFT
;
4002 /* for DDX we want to next X pixel, DDY next Y pixel. */
4003 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
4005 val
= ac_to_integer(&ctx
->ac
, emit_data
->args
[0]);
4006 val
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, val
);
4007 emit_data
->output
[emit_data
->chan
] = val
;
4011 * this takes an I,J coordinate pair,
4012 * and works out the X and Y derivatives.
4013 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4015 static LLVMValueRef
si_llvm_emit_ddxy_interp(
4016 struct lp_build_tgsi_context
*bld_base
,
4017 LLVMValueRef interp_ij
)
4019 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4020 LLVMValueRef result
[4], a
;
4023 for (i
= 0; i
< 2; i
++) {
4024 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
4025 LLVMConstInt(ctx
->i32
, i
, 0), "");
4026 result
[i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDX
, a
);
4027 result
[2+i
] = lp_build_emit_llvm_unary(bld_base
, TGSI_OPCODE_DDY
, a
);
4030 return ac_build_gather_values(&ctx
->ac
, result
, 4);
4033 static void interp_fetch_args(
4034 struct lp_build_tgsi_context
*bld_base
,
4035 struct lp_build_emit_data
*emit_data
)
4037 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4038 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4040 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
4041 /* offset is in second src, first two channels */
4042 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
4045 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
4048 emit_data
->arg_count
= 2;
4049 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4050 LLVMValueRef sample_position
;
4051 LLVMValueRef sample_id
;
4052 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
4054 /* fetch sample ID, then fetch its sample position,
4055 * and place into first two channels.
4057 sample_id
= lp_build_emit_fetch(bld_base
,
4058 emit_data
->inst
, 1, TGSI_CHAN_X
);
4059 sample_id
= ac_to_integer(&ctx
->ac
, sample_id
);
4061 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4062 * Language 4.50 spec says about interpolateAtSample:
4064 * "Returns the value of the input interpolant variable at
4065 * the location of sample number sample. If multisample
4066 * buffers are not available, the input variable will be
4067 * evaluated at the center of the pixel. If sample sample
4068 * does not exist, the position used to interpolate the
4069 * input variable is undefined."
4071 * This means that sample_id values outside of the valid are
4072 * in fact valid input, and the usual mechanism for loading the
4073 * sample position doesn't work.
4075 if (ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
) {
4076 LLVMValueRef center
[4] = {
4077 LLVMConstReal(ctx
->f32
, 0.5),
4078 LLVMConstReal(ctx
->f32
, 0.5),
4083 sample_position
= ac_build_gather_values(&ctx
->ac
, center
, 4);
4085 sample_position
= load_sample_position(&ctx
->abi
, sample_id
);
4088 emit_data
->args
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
,
4092 emit_data
->args
[0] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[0], halfval
, "");
4093 emit_data
->args
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
,
4096 emit_data
->args
[1] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[1], halfval
, "");
4097 emit_data
->arg_count
= 2;
4101 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
4102 struct lp_build_tgsi_context
*bld_base
,
4103 struct lp_build_emit_data
*emit_data
)
4105 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4106 struct si_shader
*shader
= ctx
->shader
;
4107 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
4108 LLVMValueRef interp_param
;
4109 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4110 const struct tgsi_full_src_register
*input
= &inst
->Src
[0];
4111 int input_base
, input_array_size
;
4114 LLVMValueRef prim_mask
= ctx
->abi
.prim_mask
;
4115 LLVMValueRef array_idx
;
4116 int interp_param_idx
;
4120 assert(input
->Register
.File
== TGSI_FILE_INPUT
);
4122 if (input
->Register
.Indirect
) {
4123 unsigned array_id
= input
->Indirect
.ArrayID
;
4126 input_base
= info
->input_array_first
[array_id
];
4127 input_array_size
= info
->input_array_last
[array_id
] - input_base
+ 1;
4129 input_base
= inst
->Src
[0].Register
.Index
;
4130 input_array_size
= info
->num_inputs
- input_base
;
4133 array_idx
= si_get_indirect_index(ctx
, &input
->Indirect
,
4134 1, input
->Register
.Index
- input_base
);
4136 input_base
= inst
->Src
[0].Register
.Index
;
4137 input_array_size
= 1;
4138 array_idx
= ctx
->i32_0
;
4141 interp
= shader
->selector
->info
.input_interpolate
[input_base
];
4143 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4144 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
4145 location
= TGSI_INTERPOLATE_LOC_CENTER
;
4147 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
4149 interp_param_idx
= lookup_interp_param_index(interp
, location
);
4150 if (interp_param_idx
== -1)
4152 else if (interp_param_idx
)
4153 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
4155 interp_param
= NULL
;
4157 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4158 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4159 LLVMValueRef ij_out
[2];
4160 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
4163 * take the I then J parameters, and the DDX/Y for it, and
4164 * calculate the IJ inputs for the interpolator.
4165 * temp1 = ddx * offset/sample.x + I;
4166 * interp_param.I = ddy * offset/sample.y + temp1;
4167 * temp1 = ddx * offset/sample.x + J;
4168 * interp_param.J = ddy * offset/sample.y + temp1;
4170 for (i
= 0; i
< 2; i
++) {
4171 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, 0);
4172 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, 0);
4173 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4174 ddxy_out
, ix_ll
, "");
4175 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4176 ddxy_out
, iy_ll
, "");
4177 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4178 interp_param
, ix_ll
, "");
4179 LLVMValueRef temp1
, temp2
;
4181 interp_el
= ac_to_float(&ctx
->ac
, interp_el
);
4183 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, emit_data
->args
[0], "");
4185 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4187 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, emit_data
->args
[1], "");
4189 ij_out
[i
] = LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4191 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4195 interp_param
= ac_to_float(&ctx
->ac
, interp_param
);
4197 for (chan
= 0; chan
< 4; chan
++) {
4198 LLVMValueRef gather
= LLVMGetUndef(LLVMVectorType(ctx
->f32
, input_array_size
));
4199 unsigned schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
4201 for (unsigned idx
= 0; idx
< input_array_size
; ++idx
) {
4202 LLVMValueRef v
, i
= NULL
, j
= NULL
;
4205 i
= LLVMBuildExtractElement(
4206 ctx
->ac
.builder
, interp_param
, ctx
->i32_0
, "");
4207 j
= LLVMBuildExtractElement(
4208 ctx
->ac
.builder
, interp_param
, ctx
->i32_1
, "");
4210 v
= si_build_fs_interp(ctx
, input_base
+ idx
, schan
,
4213 gather
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4214 gather
, v
, LLVMConstInt(ctx
->i32
, idx
, false), "");
4217 emit_data
->output
[chan
] = LLVMBuildExtractElement(
4218 ctx
->ac
.builder
, gather
, array_idx
, "");
4222 static void vote_all_emit(
4223 const struct lp_build_tgsi_action
*action
,
4224 struct lp_build_tgsi_context
*bld_base
,
4225 struct lp_build_emit_data
*emit_data
)
4227 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4229 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, emit_data
->args
[0]);
4230 emit_data
->output
[emit_data
->chan
] =
4231 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4234 static void vote_any_emit(
4235 const struct lp_build_tgsi_action
*action
,
4236 struct lp_build_tgsi_context
*bld_base
,
4237 struct lp_build_emit_data
*emit_data
)
4239 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4241 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, emit_data
->args
[0]);
4242 emit_data
->output
[emit_data
->chan
] =
4243 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4246 static void vote_eq_emit(
4247 const struct lp_build_tgsi_action
*action
,
4248 struct lp_build_tgsi_context
*bld_base
,
4249 struct lp_build_emit_data
*emit_data
)
4251 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4253 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, emit_data
->args
[0]);
4254 emit_data
->output
[emit_data
->chan
] =
4255 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4258 static void ballot_emit(
4259 const struct lp_build_tgsi_action
*action
,
4260 struct lp_build_tgsi_context
*bld_base
,
4261 struct lp_build_emit_data
*emit_data
)
4263 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4264 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4267 tmp
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4268 tmp
= ac_build_ballot(&ctx
->ac
, tmp
);
4269 tmp
= LLVMBuildBitCast(builder
, tmp
, ctx
->v2i32
, "");
4271 emit_data
->output
[0] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_0
, "");
4272 emit_data
->output
[1] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_1
, "");
4275 static void read_invoc_fetch_args(
4276 struct lp_build_tgsi_context
*bld_base
,
4277 struct lp_build_emit_data
*emit_data
)
4279 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4280 0, emit_data
->src_chan
);
4282 /* Always read the source invocation (= lane) from the X channel. */
4283 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4285 emit_data
->arg_count
= 2;
4288 static void read_lane_emit(
4289 const struct lp_build_tgsi_action
*action
,
4290 struct lp_build_tgsi_context
*bld_base
,
4291 struct lp_build_emit_data
*emit_data
)
4293 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4295 /* We currently have no other way to prevent LLVM from lifting the icmp
4296 * calls to a dominating basic block.
4298 ac_build_optimization_barrier(&ctx
->ac
, &emit_data
->args
[0]);
4300 for (unsigned i
= 0; i
< emit_data
->arg_count
; ++i
)
4301 emit_data
->args
[i
] = ac_to_integer(&ctx
->ac
, emit_data
->args
[i
]);
4303 emit_data
->output
[emit_data
->chan
] =
4304 ac_build_intrinsic(&ctx
->ac
, action
->intr_name
,
4305 ctx
->i32
, emit_data
->args
, emit_data
->arg_count
,
4306 AC_FUNC_ATTR_READNONE
|
4307 AC_FUNC_ATTR_CONVERGENT
);
4310 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
4311 struct lp_build_emit_data
*emit_data
)
4313 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4314 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
4318 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
4320 imm
= ctx
->imms
[src0
.Index
* TGSI_NUM_CHANNELS
+ src0
.SwizzleX
];
4321 stream
= LLVMConstIntGetZExtValue(imm
) & 0x3;
4325 /* Emit one vertex from the geometry shader */
4326 static void si_llvm_emit_vertex(struct ac_shader_abi
*abi
,
4328 LLVMValueRef
*addrs
)
4330 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4331 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
4332 struct si_shader
*shader
= ctx
->shader
;
4333 struct lp_build_if_state if_state
;
4334 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
4335 ctx
->param_gs2vs_offset
);
4336 LLVMValueRef gs_next_vertex
;
4337 LLVMValueRef can_emit
;
4338 unsigned chan
, offset
;
4341 /* Write vertex attribute values to GSVS ring */
4342 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4343 ctx
->gs_next_vertex
[stream
],
4346 /* If this thread has already emitted the declared maximum number of
4347 * vertices, skip the write: excessive vertex emissions are not
4348 * supposed to have any effect.
4350 * If the shader has no writes to memory, kill it instead. This skips
4351 * further memory loads and may allow LLVM to skip to the end
4354 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4355 LLVMConstInt(ctx
->i32
,
4356 shader
->selector
->gs_max_out_vertices
, 0), "");
4358 bool use_kill
= !info
->writes_memory
;
4360 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4362 lp_build_if(&if_state
, &ctx
->gallivm
, can_emit
);
4366 for (i
= 0; i
< info
->num_outputs
; i
++) {
4367 for (chan
= 0; chan
< 4; chan
++) {
4368 if (!(info
->output_usagemask
[i
] & (1 << chan
)) ||
4369 ((info
->output_streams
[i
] >> (2 * chan
)) & 3) != stream
)
4372 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
4373 LLVMValueRef voffset
=
4374 LLVMConstInt(ctx
->i32
, offset
*
4375 shader
->selector
->gs_max_out_vertices
, 0);
4378 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4379 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
,
4380 LLVMConstInt(ctx
->i32
, 4, 0), "");
4382 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4384 ac_build_buffer_store_dword(&ctx
->ac
,
4385 ctx
->gsvs_ring
[stream
],
4387 voffset
, soffset
, 0,
4392 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
, ctx
->i32_1
, "");
4393 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
4395 /* Signal vertex emission */
4396 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
4397 si_get_gs_wave_id(ctx
));
4399 lp_build_endif(&if_state
);
4402 /* Emit one vertex from the geometry shader */
4403 static void si_tgsi_emit_vertex(
4404 const struct lp_build_tgsi_action
*action
,
4405 struct lp_build_tgsi_context
*bld_base
,
4406 struct lp_build_emit_data
*emit_data
)
4408 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4409 unsigned stream
= si_llvm_get_stream(bld_base
, emit_data
);
4411 si_llvm_emit_vertex(&ctx
->abi
, stream
, ctx
->outputs
[0]);
4414 /* Cut one primitive from the geometry shader */
4415 static void si_llvm_emit_primitive(struct ac_shader_abi
*abi
,
4418 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4420 /* Signal primitive cut */
4421 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8),
4422 si_get_gs_wave_id(ctx
));
4425 /* Cut one primitive from the geometry shader */
4426 static void si_tgsi_emit_primitive(
4427 const struct lp_build_tgsi_action
*action
,
4428 struct lp_build_tgsi_context
*bld_base
,
4429 struct lp_build_emit_data
*emit_data
)
4431 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4433 si_llvm_emit_primitive(&ctx
->abi
, si_llvm_get_stream(bld_base
, emit_data
));
4436 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
4437 struct lp_build_tgsi_context
*bld_base
,
4438 struct lp_build_emit_data
*emit_data
)
4440 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4442 /* SI only (thanks to a hw bug workaround):
4443 * The real barrier instruction isn’t needed, because an entire patch
4444 * always fits into a single wave.
4446 if (ctx
->screen
->info
.chip_class
== SI
&&
4447 ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
4448 ac_build_waitcnt(&ctx
->ac
, LGKM_CNT
& VM_CNT
);
4452 lp_build_intrinsic(ctx
->ac
.builder
,
4453 "llvm.amdgcn.s.barrier",
4454 ctx
->voidt
, NULL
, 0, LP_FUNC_ATTR_CONVERGENT
);
4457 static const struct lp_build_tgsi_action interp_action
= {
4458 .fetch_args
= interp_fetch_args
,
4459 .emit
= build_interp_intrinsic
,
4462 static void si_create_function(struct si_shader_context
*ctx
,
4464 LLVMTypeRef
*returns
, unsigned num_returns
,
4465 struct si_function_info
*fninfo
,
4466 unsigned max_workgroup_size
)
4470 si_llvm_create_func(ctx
, name
, returns
, num_returns
,
4471 fninfo
->types
, fninfo
->num_params
);
4472 ctx
->return_value
= LLVMGetUndef(ctx
->return_type
);
4474 for (i
= 0; i
< fninfo
->num_sgpr_params
; ++i
) {
4475 LLVMValueRef P
= LLVMGetParam(ctx
->main_fn
, i
);
4477 /* The combination of:
4481 * allows the optimization passes to move loads and reduces
4482 * SGPR spilling significantly.
4484 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_INREG
);
4486 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
4487 lp_add_function_attr(ctx
->main_fn
, i
+ 1, LP_FUNC_ATTR_NOALIAS
);
4488 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
4492 for (i
= 0; i
< fninfo
->num_params
; ++i
) {
4493 if (fninfo
->assign
[i
])
4494 *fninfo
->assign
[i
] = LLVMGetParam(ctx
->main_fn
, i
);
4497 if (ctx
->screen
->info
.address32_hi
) {
4498 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4499 "amdgpu-32bit-address-high-bits",
4500 ctx
->screen
->info
.address32_hi
);
4503 if (max_workgroup_size
) {
4504 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4505 "amdgpu-max-work-group-size",
4506 max_workgroup_size
);
4508 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4509 "no-signed-zeros-fp-math",
4512 if (ctx
->screen
->debug_flags
& DBG(UNSAFE_MATH
)) {
4513 /* These were copied from some LLVM test. */
4514 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4515 "less-precise-fpmad",
4517 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4520 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4523 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4529 static void declare_streamout_params(struct si_shader_context
*ctx
,
4530 struct pipe_stream_output_info
*so
,
4531 struct si_function_info
*fninfo
)
4535 /* Streamout SGPRs. */
4536 if (so
->num_outputs
) {
4537 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
4538 ctx
->param_streamout_config
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4540 ctx
->param_streamout_config
= fninfo
->num_params
- 1;
4542 ctx
->param_streamout_write_index
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4544 /* A streamout buffer offset is loaded if the stride is non-zero. */
4545 for (i
= 0; i
< 4; i
++) {
4549 ctx
->param_streamout_offset
[i
] = add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4553 static unsigned si_get_max_workgroup_size(const struct si_shader
*shader
)
4555 switch (shader
->selector
->type
) {
4556 case PIPE_SHADER_TESS_CTRL
:
4557 /* Return this so that LLVM doesn't remove s_barrier
4558 * instructions on chips where we use s_barrier. */
4559 return shader
->selector
->screen
->info
.chip_class
>= CIK
? 128 : 64;
4561 case PIPE_SHADER_GEOMETRY
:
4562 return shader
->selector
->screen
->info
.chip_class
>= GFX9
? 128 : 64;
4564 case PIPE_SHADER_COMPUTE
:
4565 break; /* see below */
4571 const unsigned *properties
= shader
->selector
->info
.properties
;
4572 unsigned max_work_group_size
=
4573 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
4574 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
4575 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
4577 if (!max_work_group_size
) {
4578 /* This is a variable group size compute shader,
4579 * compile it for the maximum possible group size.
4581 max_work_group_size
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
4583 return max_work_group_size
;
4586 static void declare_const_and_shader_buffers(struct si_shader_context
*ctx
,
4587 struct si_function_info
*fninfo
,
4590 LLVMTypeRef const_shader_buf_type
;
4592 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
4593 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
4594 const_shader_buf_type
= ctx
->f32
;
4596 const_shader_buf_type
= ctx
->v4i32
;
4598 unsigned const_and_shader_buffers
=
4599 add_arg(fninfo
, ARG_SGPR
,
4600 ac_array_in_const32_addr_space(const_shader_buf_type
));
4603 ctx
->param_const_and_shader_buffers
= const_and_shader_buffers
;
4606 static void declare_samplers_and_images(struct si_shader_context
*ctx
,
4607 struct si_function_info
*fninfo
,
4610 unsigned samplers_and_images
=
4611 add_arg(fninfo
, ARG_SGPR
,
4612 ac_array_in_const32_addr_space(ctx
->v8i32
));
4615 ctx
->param_samplers_and_images
= samplers_and_images
;
4618 static void declare_per_stage_desc_pointers(struct si_shader_context
*ctx
,
4619 struct si_function_info
*fninfo
,
4622 declare_const_and_shader_buffers(ctx
, fninfo
, assign_params
);
4623 declare_samplers_and_images(ctx
, fninfo
, assign_params
);
4626 static void declare_global_desc_pointers(struct si_shader_context
*ctx
,
4627 struct si_function_info
*fninfo
)
4629 ctx
->param_rw_buffers
= add_arg(fninfo
, ARG_SGPR
,
4630 ac_array_in_const32_addr_space(ctx
->v4i32
));
4631 ctx
->param_bindless_samplers_and_images
= add_arg(fninfo
, ARG_SGPR
,
4632 ac_array_in_const32_addr_space(ctx
->v8i32
));
4635 static void declare_vs_specific_input_sgprs(struct si_shader_context
*ctx
,
4636 struct si_function_info
*fninfo
)
4638 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.base_vertex
);
4639 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.start_instance
);
4640 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.draw_id
);
4641 ctx
->param_vs_state_bits
= add_arg(fninfo
, ARG_SGPR
, ctx
->i32
);
4644 static void declare_vs_input_vgprs(struct si_shader_context
*ctx
,
4645 struct si_function_info
*fninfo
,
4646 unsigned *num_prolog_vgprs
)
4648 struct si_shader
*shader
= ctx
->shader
;
4650 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.vertex_id
);
4651 if (shader
->key
.as_ls
) {
4652 ctx
->param_rel_auto_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4653 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4655 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4656 ctx
->param_vs_prim_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4658 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4660 if (!shader
->is_gs_copy_shader
) {
4661 /* Vertex load indices. */
4662 ctx
->param_vertex_index0
= fninfo
->num_params
;
4663 for (unsigned i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
4664 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4665 *num_prolog_vgprs
+= shader
->selector
->info
.num_inputs
;
4669 static void declare_tes_input_vgprs(struct si_shader_context
*ctx
,
4670 struct si_function_info
*fninfo
)
4672 ctx
->param_tes_u
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4673 ctx
->param_tes_v
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4674 ctx
->param_tes_rel_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4675 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tes_patch_id
);
4679 /* Convenient merged shader definitions. */
4680 SI_SHADER_MERGED_VERTEX_TESSCTRL
= PIPE_SHADER_TYPES
,
4681 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
,
4684 static void create_function(struct si_shader_context
*ctx
)
4686 struct si_shader
*shader
= ctx
->shader
;
4687 struct si_function_info fninfo
;
4688 LLVMTypeRef returns
[16+32*4];
4689 unsigned i
, num_return_sgprs
;
4690 unsigned num_returns
= 0;
4691 unsigned num_prolog_vgprs
= 0;
4692 unsigned type
= ctx
->type
;
4693 unsigned vs_blit_property
=
4694 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
4696 si_init_function_info(&fninfo
);
4698 /* Set MERGED shaders. */
4699 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
4700 if (shader
->key
.as_ls
|| type
== PIPE_SHADER_TESS_CTRL
)
4701 type
= SI_SHADER_MERGED_VERTEX_TESSCTRL
; /* LS or HS */
4702 else if (shader
->key
.as_es
|| type
== PIPE_SHADER_GEOMETRY
)
4703 type
= SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
;
4706 LLVMTypeRef v3i32
= LLVMVectorType(ctx
->i32
, 3);
4709 case PIPE_SHADER_VERTEX
:
4710 declare_global_desc_pointers(ctx
, &fninfo
);
4712 if (vs_blit_property
) {
4713 ctx
->param_vs_blit_inputs
= fninfo
.num_params
;
4714 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x1, y1 */
4715 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x2, y2 */
4716 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* depth */
4718 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
4719 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color0 */
4720 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color1 */
4721 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color2 */
4722 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color3 */
4723 } else if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
) {
4724 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x1 */
4725 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y1 */
4726 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x2 */
4727 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y2 */
4728 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.z */
4729 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.w */
4733 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4737 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4738 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4739 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4740 ac_array_in_const32_addr_space(ctx
->v4i32
));
4742 if (shader
->key
.as_es
) {
4743 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4744 } else if (shader
->key
.as_ls
) {
4745 /* no extra parameters */
4747 if (shader
->is_gs_copy_shader
) {
4748 fninfo
.num_params
= ctx
->param_rw_buffers
+ 1;
4749 fninfo
.num_sgpr_params
= fninfo
.num_params
;
4752 /* The locations of the other parameters are assigned dynamically. */
4753 declare_streamout_params(ctx
, &shader
->selector
->so
,
4758 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4761 case PIPE_SHADER_TESS_CTRL
: /* SI-CI-VI */
4762 declare_global_desc_pointers(ctx
, &fninfo
);
4763 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4764 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4765 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4766 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4767 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4768 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4769 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4772 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4773 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4775 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4776 * placed after the user SGPRs.
4778 for (i
= 0; i
< GFX6_TCS_NUM_USER_SGPR
+ 2; i
++)
4779 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4780 for (i
= 0; i
< 11; i
++)
4781 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4784 case SI_SHADER_MERGED_VERTEX_TESSCTRL
:
4785 /* Merged stages have 8 system SGPRs at the beginning. */
4786 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4787 if (HAVE_32BIT_POINTERS
) {
4788 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4789 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4791 declare_const_and_shader_buffers(ctx
, &fninfo
,
4792 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4794 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4795 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4796 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4797 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4798 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4799 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4801 declare_global_desc_pointers(ctx
, &fninfo
);
4802 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4803 ctx
->type
== PIPE_SHADER_VERTEX
);
4804 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4806 if (!HAVE_32BIT_POINTERS
) {
4807 declare_samplers_and_images(ctx
, &fninfo
,
4808 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4810 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4811 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4812 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4813 if (!HAVE_32BIT_POINTERS
) /* Align to 2 dwords. */
4814 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4815 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4816 ac_array_in_const32_addr_space(ctx
->v4i32
));
4818 /* VGPRs (first TCS, then VS) */
4819 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4820 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4822 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4823 declare_vs_input_vgprs(ctx
, &fninfo
,
4826 /* LS return values are inputs to the TCS main shader part. */
4827 for (i
= 0; i
< 8 + GFX9_TCS_NUM_USER_SGPR
; i
++)
4828 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4829 for (i
= 0; i
< 2; i
++)
4830 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4832 /* TCS return values are inputs to the TCS epilog.
4834 * param_tcs_offchip_offset, param_tcs_factor_offset,
4835 * param_tcs_offchip_layout, and param_rw_buffers
4836 * should be passed to the epilog.
4838 for (i
= 0; i
<= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
; i
++)
4839 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4840 for (i
= 0; i
< 11; i
++)
4841 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4845 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
:
4846 /* Merged stages have 8 system SGPRs at the beginning. */
4847 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4848 if (HAVE_32BIT_POINTERS
) {
4849 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4850 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4852 declare_const_and_shader_buffers(ctx
, &fninfo
,
4853 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4855 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4856 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4857 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4858 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4859 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4860 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4862 declare_global_desc_pointers(ctx
, &fninfo
);
4863 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4864 (ctx
->type
== PIPE_SHADER_VERTEX
||
4865 ctx
->type
== PIPE_SHADER_TESS_EVAL
));
4866 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4867 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4869 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4870 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4871 if (!HAVE_32BIT_POINTERS
) {
4872 /* Declare as many input SGPRs as the VS has. */
4873 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4874 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4878 if (!HAVE_32BIT_POINTERS
) {
4879 declare_samplers_and_images(ctx
, &fninfo
,
4880 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4882 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4883 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4884 ac_array_in_const32_addr_space(ctx
->v4i32
));
4887 /* VGPRs (first GS, then VS/TES) */
4888 ctx
->param_gs_vtx01_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4889 ctx
->param_gs_vtx23_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4890 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4891 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4892 ctx
->param_gs_vtx45_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4894 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4895 declare_vs_input_vgprs(ctx
, &fninfo
,
4897 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4898 declare_tes_input_vgprs(ctx
, &fninfo
);
4901 if (ctx
->type
== PIPE_SHADER_VERTEX
||
4902 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4903 unsigned num_user_sgprs
;
4905 if (ctx
->type
== PIPE_SHADER_VERTEX
)
4906 num_user_sgprs
= GFX9_VSGS_NUM_USER_SGPR
;
4908 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
4910 /* ES return values are inputs to GS. */
4911 for (i
= 0; i
< 8 + num_user_sgprs
; i
++)
4912 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4913 for (i
= 0; i
< 5; i
++)
4914 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4918 case PIPE_SHADER_TESS_EVAL
:
4919 declare_global_desc_pointers(ctx
, &fninfo
);
4920 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4921 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4922 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4924 if (shader
->key
.as_es
) {
4925 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4926 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4927 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4929 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4930 declare_streamout_params(ctx
, &shader
->selector
->so
,
4932 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4936 declare_tes_input_vgprs(ctx
, &fninfo
);
4939 case PIPE_SHADER_GEOMETRY
:
4940 declare_global_desc_pointers(ctx
, &fninfo
);
4941 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4942 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4943 ctx
->param_gs_wave_id
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4946 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]);
4947 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]);
4948 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4949 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
4950 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
4951 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
4952 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
4953 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4956 case PIPE_SHADER_FRAGMENT
:
4957 declare_global_desc_pointers(ctx
, &fninfo
);
4958 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4959 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
4960 add_arg_assign_checked(&fninfo
, ARG_SGPR
, ctx
->i32
,
4961 &ctx
->abi
.prim_mask
, SI_PARAM_PRIM_MASK
);
4963 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_SAMPLE
);
4964 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTER
);
4965 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTROID
);
4966 add_arg_checked(&fninfo
, ARG_VGPR
, v3i32
, SI_PARAM_PERSP_PULL_MODEL
);
4967 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_SAMPLE
);
4968 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTER
);
4969 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTROID
);
4970 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->f32
, SI_PARAM_LINE_STIPPLE_TEX
);
4971 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4972 &ctx
->abi
.frag_pos
[0], SI_PARAM_POS_X_FLOAT
);
4973 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4974 &ctx
->abi
.frag_pos
[1], SI_PARAM_POS_Y_FLOAT
);
4975 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4976 &ctx
->abi
.frag_pos
[2], SI_PARAM_POS_Z_FLOAT
);
4977 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4978 &ctx
->abi
.frag_pos
[3], SI_PARAM_POS_W_FLOAT
);
4979 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4980 &ctx
->abi
.front_face
, SI_PARAM_FRONT_FACE
);
4981 shader
->info
.face_vgpr_index
= 20;
4982 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4983 &ctx
->abi
.ancillary
, SI_PARAM_ANCILLARY
);
4984 shader
->info
.ancillary_vgpr_index
= 21;
4985 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4986 &ctx
->abi
.sample_coverage
, SI_PARAM_SAMPLE_COVERAGE
);
4987 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->i32
, SI_PARAM_POS_FIXED_PT
);
4989 /* Color inputs from the prolog. */
4990 if (shader
->selector
->info
.colors_read
) {
4991 unsigned num_color_elements
=
4992 util_bitcount(shader
->selector
->info
.colors_read
);
4994 assert(fninfo
.num_params
+ num_color_elements
<= ARRAY_SIZE(fninfo
.types
));
4995 for (i
= 0; i
< num_color_elements
; i
++)
4996 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
4998 num_prolog_vgprs
+= num_color_elements
;
5001 /* Outputs for the epilog. */
5002 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
5005 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
5006 shader
->selector
->info
.writes_z
+
5007 shader
->selector
->info
.writes_stencil
+
5008 shader
->selector
->info
.writes_samplemask
+
5009 1 /* SampleMaskIn */;
5011 num_returns
= MAX2(num_returns
,
5013 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
5015 for (i
= 0; i
< num_return_sgprs
; i
++)
5016 returns
[i
] = ctx
->i32
;
5017 for (; i
< num_returns
; i
++)
5018 returns
[i
] = ctx
->f32
;
5021 case PIPE_SHADER_COMPUTE
:
5022 declare_global_desc_pointers(ctx
, &fninfo
);
5023 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
5024 if (shader
->selector
->info
.uses_grid_size
)
5025 add_arg_assign(&fninfo
, ARG_SGPR
, v3i32
, &ctx
->abi
.num_work_groups
);
5026 if (shader
->selector
->info
.uses_block_size
)
5027 ctx
->param_block_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
5029 for (i
= 0; i
< 3; i
++) {
5030 ctx
->abi
.workgroup_ids
[i
] = NULL
;
5031 if (shader
->selector
->info
.uses_block_id
[i
])
5032 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.workgroup_ids
[i
]);
5035 add_arg_assign(&fninfo
, ARG_VGPR
, v3i32
, &ctx
->abi
.local_invocation_ids
);
5038 assert(0 && "unimplemented shader");
5042 si_create_function(ctx
, "main", returns
, num_returns
, &fninfo
,
5043 si_get_max_workgroup_size(shader
));
5045 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5046 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&& !ctx
->shader
->is_monolithic
) {
5047 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
5048 "InitialPSInputAddr",
5049 S_0286D0_PERSP_SAMPLE_ENA(1) |
5050 S_0286D0_PERSP_CENTER_ENA(1) |
5051 S_0286D0_PERSP_CENTROID_ENA(1) |
5052 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5053 S_0286D0_LINEAR_CENTER_ENA(1) |
5054 S_0286D0_LINEAR_CENTROID_ENA(1) |
5055 S_0286D0_FRONT_FACE_ENA(1) |
5056 S_0286D0_ANCILLARY_ENA(1) |
5057 S_0286D0_POS_FIXED_PT_ENA(1));
5060 shader
->info
.num_input_sgprs
= 0;
5061 shader
->info
.num_input_vgprs
= 0;
5063 for (i
= 0; i
< fninfo
.num_sgpr_params
; ++i
)
5064 shader
->info
.num_input_sgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5066 for (; i
< fninfo
.num_params
; ++i
)
5067 shader
->info
.num_input_vgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5069 assert(shader
->info
.num_input_vgprs
>= num_prolog_vgprs
);
5070 shader
->info
.num_input_vgprs
-= num_prolog_vgprs
;
5072 if (shader
->key
.as_ls
||
5073 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5074 /* GFX9 has the ESGS ring buffer in LDS. */
5075 type
== SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
)
5076 ac_declare_lds_as_pointer(&ctx
->ac
);
5080 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5083 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5085 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5087 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
5088 ctx
->param_rw_buffers
);
5090 if (ctx
->screen
->info
.chip_class
<= VI
&&
5091 (ctx
->shader
->key
.as_es
|| ctx
->type
== PIPE_SHADER_GEOMETRY
)) {
5093 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5095 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, ring
, 0);
5098 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5101 if (ctx
->shader
->is_gs_copy_shader
) {
5102 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5105 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5106 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5107 const struct si_shader_selector
*sel
= ctx
->shader
->selector
;
5108 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5109 LLVMValueRef base_ring
;
5111 base_ring
= ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5113 /* The conceptual layout of the GSVS ring is
5114 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5115 * but the real memory layout is swizzled across
5117 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5119 * Override the buffer descriptor accordingly.
5121 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->i64
, 2);
5122 uint64_t stream_offset
= 0;
5124 for (unsigned stream
= 0; stream
< 4; ++stream
) {
5125 unsigned num_components
;
5127 unsigned num_records
;
5128 LLVMValueRef ring
, tmp
;
5130 num_components
= sel
->info
.num_stream_output_components
[stream
];
5131 if (!num_components
)
5134 stride
= 4 * num_components
* sel
->gs_max_out_vertices
;
5136 /* Limit on the stride field for <= CIK. */
5137 assert(stride
< (1 << 14));
5141 ring
= LLVMBuildBitCast(builder
, base_ring
, v2i64
, "");
5142 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_0
, "");
5143 tmp
= LLVMBuildAdd(builder
, tmp
,
5144 LLVMConstInt(ctx
->i64
,
5145 stream_offset
, 0), "");
5146 stream_offset
+= stride
* 64;
5148 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_0
, "");
5149 ring
= LLVMBuildBitCast(builder
, ring
, ctx
->v4i32
, "");
5150 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_1
, "");
5151 tmp
= LLVMBuildOr(builder
, tmp
,
5152 LLVMConstInt(ctx
->i32
,
5153 S_008F04_STRIDE(stride
) |
5154 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5155 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_1
, "");
5156 ring
= LLVMBuildInsertElement(builder
, ring
,
5157 LLVMConstInt(ctx
->i32
, num_records
, 0),
5158 LLVMConstInt(ctx
->i32
, 2, 0), "");
5159 ring
= LLVMBuildInsertElement(builder
, ring
,
5160 LLVMConstInt(ctx
->i32
,
5161 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
5165 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
5167 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5168 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5169 S_008F0C_ADD_TID_ENABLE(1),
5171 LLVMConstInt(ctx
->i32
, 3, 0), "");
5173 ctx
->gsvs_ring
[stream
] = ring
;
5175 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
5176 ctx
->tess_offchip_ring
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TES
);
5180 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5181 LLVMValueRef param_rw_buffers
,
5182 unsigned param_pos_fixed_pt
)
5184 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5185 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5187 /* Use the fixed-point gl_FragCoord input.
5188 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5189 * per coordinate to get the repeating effect.
5191 address
[0] = si_unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5192 address
[1] = si_unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5194 /* Load the buffer descriptor. */
5195 slot
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_POLY_STIPPLE
, 0);
5196 desc
= ac_build_load_to_sgpr(&ctx
->ac
, param_rw_buffers
, slot
);
5198 /* The stipple pattern is 32x32, each row has 32 bits. */
5199 offset
= LLVMBuildMul(builder
, address
[1],
5200 LLVMConstInt(ctx
->i32
, 4, 0), "");
5201 row
= buffer_load_const(ctx
, desc
, offset
);
5202 row
= ac_to_integer(&ctx
->ac
, row
);
5203 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5204 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5205 ac_build_kill_if_false(&ctx
->ac
, bit
);
5208 void si_shader_binary_read_config(struct ac_shader_binary
*binary
,
5209 struct si_shader_config
*conf
,
5210 unsigned symbol_offset
)
5213 const unsigned char *config
=
5214 ac_shader_binary_config_start(binary
, symbol_offset
);
5215 bool really_needs_scratch
= false;
5217 /* LLVM adds SGPR spills to the scratch size.
5218 * Find out if we really need the scratch buffer.
5220 for (i
= 0; i
< binary
->reloc_count
; i
++) {
5221 const struct ac_shader_reloc
*reloc
= &binary
->relocs
[i
];
5223 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
5224 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5225 really_needs_scratch
= true;
5230 /* XXX: We may be able to emit some of these values directly rather than
5231 * extracting fields to be emitted later.
5234 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
5235 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
5236 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
5238 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
5239 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
5240 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
5241 case R_00B428_SPI_SHADER_PGM_RSRC1_HS
:
5242 case R_00B848_COMPUTE_PGM_RSRC1
:
5243 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
5244 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
5245 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
5246 conf
->rsrc1
= value
;
5248 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
5249 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
5251 case R_00B84C_COMPUTE_PGM_RSRC2
:
5252 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
5253 conf
->rsrc2
= value
;
5255 case R_0286CC_SPI_PS_INPUT_ENA
:
5256 conf
->spi_ps_input_ena
= value
;
5258 case R_0286D0_SPI_PS_INPUT_ADDR
:
5259 conf
->spi_ps_input_addr
= value
;
5261 case R_0286E8_SPI_TMPRING_SIZE
:
5262 case R_00B860_COMPUTE_TMPRING_SIZE
:
5263 /* WAVESIZE is in units of 256 dwords. */
5264 if (really_needs_scratch
)
5265 conf
->scratch_bytes_per_wave
=
5266 G_00B860_WAVESIZE(value
) * 256 * 4;
5268 case 0x4: /* SPILLED_SGPRS */
5269 conf
->spilled_sgprs
= value
;
5271 case 0x8: /* SPILLED_VGPRS */
5272 conf
->spilled_vgprs
= value
;
5276 static bool printed
;
5279 fprintf(stderr
, "Warning: LLVM emitted unknown "
5280 "config register: 0x%x\n", reg
);
5288 if (!conf
->spi_ps_input_addr
)
5289 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
5292 void si_shader_apply_scratch_relocs(struct si_shader
*shader
,
5293 uint64_t scratch_va
)
5296 uint32_t scratch_rsrc_dword0
= scratch_va
;
5297 uint32_t scratch_rsrc_dword1
=
5298 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
5300 /* Enable scratch coalescing. */
5301 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
5303 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
5304 const struct ac_shader_reloc
*reloc
=
5305 &shader
->binary
.relocs
[i
];
5306 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
5307 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5308 &scratch_rsrc_dword0
, 4);
5309 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5310 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5311 &scratch_rsrc_dword1
, 4);
5316 /* For the UMR disassembler. */
5317 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5318 #define DEBUGGER_NUM_MARKERS 5
5320 static unsigned si_get_shader_binary_size(const struct si_shader
*shader
)
5322 unsigned size
= shader
->binary
.code_size
;
5325 size
+= shader
->prolog
->binary
.code_size
;
5326 if (shader
->previous_stage
)
5327 size
+= shader
->previous_stage
->binary
.code_size
;
5328 if (shader
->prolog2
)
5329 size
+= shader
->prolog2
->binary
.code_size
;
5331 size
+= shader
->epilog
->binary
.code_size
;
5332 return size
+ DEBUGGER_NUM_MARKERS
* 4;
5335 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
5337 const struct ac_shader_binary
*prolog
=
5338 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
5339 const struct ac_shader_binary
*previous_stage
=
5340 shader
->previous_stage
? &shader
->previous_stage
->binary
: NULL
;
5341 const struct ac_shader_binary
*prolog2
=
5342 shader
->prolog2
? &shader
->prolog2
->binary
: NULL
;
5343 const struct ac_shader_binary
*epilog
=
5344 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
5345 const struct ac_shader_binary
*mainb
= &shader
->binary
;
5346 unsigned bo_size
= si_get_shader_binary_size(shader
) +
5347 (!epilog
? mainb
->rodata_size
: 0);
5350 assert(!prolog
|| !prolog
->rodata_size
);
5351 assert(!previous_stage
|| !previous_stage
->rodata_size
);
5352 assert(!prolog2
|| !prolog2
->rodata_size
);
5353 assert((!prolog
&& !previous_stage
&& !prolog2
&& !epilog
) ||
5354 !mainb
->rodata_size
);
5355 assert(!epilog
|| !epilog
->rodata_size
);
5357 r600_resource_reference(&shader
->bo
, NULL
);
5358 shader
->bo
= si_aligned_buffer_create(&sscreen
->b
,
5359 sscreen
->cpdma_prefetch_writes_memory
?
5360 0 : SI_RESOURCE_FLAG_READ_ONLY
,
5361 PIPE_USAGE_IMMUTABLE
,
5362 align(bo_size
, SI_CPDMA_ALIGNMENT
),
5368 ptr
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
5369 PIPE_TRANSFER_READ_WRITE
|
5370 PIPE_TRANSFER_UNSYNCHRONIZED
);
5372 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5373 * endian-independent. */
5375 memcpy(ptr
, prolog
->code
, prolog
->code_size
);
5376 ptr
+= prolog
->code_size
;
5378 if (previous_stage
) {
5379 memcpy(ptr
, previous_stage
->code
, previous_stage
->code_size
);
5380 ptr
+= previous_stage
->code_size
;
5383 memcpy(ptr
, prolog2
->code
, prolog2
->code_size
);
5384 ptr
+= prolog2
->code_size
;
5387 memcpy(ptr
, mainb
->code
, mainb
->code_size
);
5388 ptr
+= mainb
->code_size
;
5391 memcpy(ptr
, epilog
->code
, epilog
->code_size
);
5392 ptr
+= epilog
->code_size
;
5393 } else if (mainb
->rodata_size
> 0) {
5394 memcpy(ptr
, mainb
->rodata
, mainb
->rodata_size
);
5395 ptr
+= mainb
->rodata_size
;
5398 /* Add end-of-code markers for the UMR disassembler. */
5399 uint32_t *ptr32
= (uint32_t*)ptr
;
5400 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
5401 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
5403 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
5407 static void si_shader_dump_disassembly(const struct ac_shader_binary
*binary
,
5408 struct pipe_debug_callback
*debug
,
5409 const char *name
, FILE *file
)
5414 if (binary
->disasm_string
) {
5415 fprintf(file
, "Shader %s disassembly:\n", name
);
5416 fprintf(file
, "%s", binary
->disasm_string
);
5418 if (debug
&& debug
->debug_message
) {
5419 /* Very long debug messages are cut off, so send the
5420 * disassembly one line at a time. This causes more
5421 * overhead, but on the plus side it simplifies
5422 * parsing of resulting logs.
5424 pipe_debug_message(debug
, SHADER_INFO
,
5425 "Shader Disassembly Begin");
5427 line
= binary
->disasm_string
;
5429 p
= util_strchrnul(line
, '\n');
5433 pipe_debug_message(debug
, SHADER_INFO
,
5434 "%.*s", count
, line
);
5442 pipe_debug_message(debug
, SHADER_INFO
,
5443 "Shader Disassembly End");
5446 fprintf(file
, "Shader %s binary:\n", name
);
5447 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
5448 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
5449 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
5450 binary
->code
[i
+ 1], binary
->code
[i
]);
5455 static void si_calculate_max_simd_waves(struct si_shader
*shader
)
5457 struct si_screen
*sscreen
= shader
->selector
->screen
;
5458 struct si_shader_config
*conf
= &shader
->config
;
5459 unsigned num_inputs
= shader
->selector
->info
.num_inputs
;
5460 unsigned lds_increment
= sscreen
->info
.chip_class
>= CIK
? 512 : 256;
5461 unsigned lds_per_wave
= 0;
5462 unsigned max_simd_waves
;
5464 max_simd_waves
= ac_get_max_simd_waves(sscreen
->info
.family
);
5466 /* Compute LDS usage for PS. */
5467 switch (shader
->selector
->type
) {
5468 case PIPE_SHADER_FRAGMENT
:
5469 /* The minimum usage per wave is (num_inputs * 48). The maximum
5470 * usage is (num_inputs * 48 * 16).
5471 * We can get anything in between and it varies between waves.
5473 * The 48 bytes per input for a single primitive is equal to
5474 * 4 bytes/component * 4 components/input * 3 points.
5476 * Other stages don't know the size at compile time or don't
5477 * allocate LDS per wave, but instead they do it per thread group.
5479 lds_per_wave
= conf
->lds_size
* lds_increment
+
5480 align(num_inputs
* 48, lds_increment
);
5482 case PIPE_SHADER_COMPUTE
:
5483 if (shader
->selector
) {
5484 unsigned max_workgroup_size
=
5485 si_get_max_workgroup_size(shader
);
5486 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
5487 DIV_ROUND_UP(max_workgroup_size
, 64);
5492 /* Compute the per-SIMD wave counts. */
5493 if (conf
->num_sgprs
) {
5494 if (sscreen
->info
.chip_class
>= VI
)
5495 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
5497 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
5500 if (conf
->num_vgprs
)
5501 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
5503 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5504 * 16KB makes some SIMDs unoccupied). */
5506 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
5508 conf
->max_simd_waves
= max_simd_waves
;
5511 void si_shader_dump_stats_for_shader_db(const struct si_shader
*shader
,
5512 struct pipe_debug_callback
*debug
)
5514 const struct si_shader_config
*conf
= &shader
->config
;
5516 pipe_debug_message(debug
, SHADER_INFO
,
5517 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5518 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5519 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5520 conf
->num_sgprs
, conf
->num_vgprs
,
5521 si_get_shader_binary_size(shader
),
5522 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5523 conf
->max_simd_waves
, conf
->spilled_sgprs
,
5524 conf
->spilled_vgprs
, conf
->private_mem_vgprs
);
5527 static void si_shader_dump_stats(struct si_screen
*sscreen
,
5528 const struct si_shader
*shader
,
5531 bool check_debug_option
)
5533 const struct si_shader_config
*conf
= &shader
->config
;
5535 if (!check_debug_option
||
5536 si_can_dump_shader(sscreen
, processor
)) {
5537 if (processor
== PIPE_SHADER_FRAGMENT
) {
5538 fprintf(file
, "*** SHADER CONFIG ***\n"
5539 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5540 "SPI_PS_INPUT_ENA = 0x%04x\n",
5541 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
5544 fprintf(file
, "*** SHADER STATS ***\n"
5547 "Spilled SGPRs: %d\n"
5548 "Spilled VGPRs: %d\n"
5549 "Private memory VGPRs: %d\n"
5550 "Code Size: %d bytes\n"
5552 "Scratch: %d bytes per wave\n"
5554 "********************\n\n\n",
5555 conf
->num_sgprs
, conf
->num_vgprs
,
5556 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
5557 conf
->private_mem_vgprs
,
5558 si_get_shader_binary_size(shader
),
5559 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5560 conf
->max_simd_waves
);
5564 const char *si_get_shader_name(const struct si_shader
*shader
, unsigned processor
)
5566 switch (processor
) {
5567 case PIPE_SHADER_VERTEX
:
5568 if (shader
->key
.as_es
)
5569 return "Vertex Shader as ES";
5570 else if (shader
->key
.as_ls
)
5571 return "Vertex Shader as LS";
5573 return "Vertex Shader as VS";
5574 case PIPE_SHADER_TESS_CTRL
:
5575 return "Tessellation Control Shader";
5576 case PIPE_SHADER_TESS_EVAL
:
5577 if (shader
->key
.as_es
)
5578 return "Tessellation Evaluation Shader as ES";
5580 return "Tessellation Evaluation Shader as VS";
5581 case PIPE_SHADER_GEOMETRY
:
5582 if (shader
->is_gs_copy_shader
)
5583 return "GS Copy Shader as VS";
5585 return "Geometry Shader";
5586 case PIPE_SHADER_FRAGMENT
:
5587 return "Pixel Shader";
5588 case PIPE_SHADER_COMPUTE
:
5589 return "Compute Shader";
5591 return "Unknown Shader";
5595 void si_shader_dump(struct si_screen
*sscreen
, const struct si_shader
*shader
,
5596 struct pipe_debug_callback
*debug
, unsigned processor
,
5597 FILE *file
, bool check_debug_option
)
5599 if (!check_debug_option
||
5600 si_can_dump_shader(sscreen
, processor
))
5601 si_dump_shader_key(processor
, shader
, file
);
5603 if (!check_debug_option
&& shader
->binary
.llvm_ir_string
) {
5604 if (shader
->previous_stage
&&
5605 shader
->previous_stage
->binary
.llvm_ir_string
) {
5606 fprintf(file
, "\n%s - previous stage - LLVM IR:\n\n",
5607 si_get_shader_name(shader
, processor
));
5608 fprintf(file
, "%s\n", shader
->previous_stage
->binary
.llvm_ir_string
);
5611 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
5612 si_get_shader_name(shader
, processor
));
5613 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
5616 if (!check_debug_option
||
5617 (si_can_dump_shader(sscreen
, processor
) &&
5618 !(sscreen
->debug_flags
& DBG(NO_ASM
)))) {
5619 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
5622 si_shader_dump_disassembly(&shader
->prolog
->binary
,
5623 debug
, "prolog", file
);
5624 if (shader
->previous_stage
)
5625 si_shader_dump_disassembly(&shader
->previous_stage
->binary
,
5626 debug
, "previous stage", file
);
5627 if (shader
->prolog2
)
5628 si_shader_dump_disassembly(&shader
->prolog2
->binary
,
5629 debug
, "prolog2", file
);
5631 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
5634 si_shader_dump_disassembly(&shader
->epilog
->binary
,
5635 debug
, "epilog", file
);
5636 fprintf(file
, "\n");
5639 si_shader_dump_stats(sscreen
, shader
, processor
, file
,
5640 check_debug_option
);
5643 static int si_compile_llvm(struct si_screen
*sscreen
,
5644 struct ac_shader_binary
*binary
,
5645 struct si_shader_config
*conf
,
5646 struct si_compiler
*compiler
,
5648 struct pipe_debug_callback
*debug
,
5653 unsigned count
= p_atomic_inc_return(&sscreen
->num_compilations
);
5655 if (si_can_dump_shader(sscreen
, processor
)) {
5656 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
5658 if (!(sscreen
->debug_flags
& (DBG(NO_IR
) | DBG(PREOPT_IR
)))) {
5659 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5660 ac_dump_module(mod
);
5661 fprintf(stderr
, "\n");
5665 if (sscreen
->record_llvm_ir
) {
5666 char *ir
= LLVMPrintModuleToString(mod
);
5667 binary
->llvm_ir_string
= strdup(ir
);
5668 LLVMDisposeMessage(ir
);
5671 if (!si_replace_shader(count
, binary
)) {
5672 r
= si_llvm_compile(mod
, binary
, compiler
, debug
);
5677 si_shader_binary_read_config(binary
, conf
, 0);
5679 /* Enable 64-bit and 16-bit denormals, because there is no performance
5682 * If denormals are enabled, all floating-point output modifiers are
5685 * Don't enable denormals for 32-bit floats, because:
5686 * - Floating-point output modifiers would be ignored by the hw.
5687 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5688 * have to stop using those.
5689 * - SI & CI would be very slow.
5691 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
5693 FREE(binary
->config
);
5694 FREE(binary
->global_symbol_offsets
);
5695 binary
->config
= NULL
;
5696 binary
->global_symbol_offsets
= NULL
;
5698 /* Some shaders can't have rodata because their binaries can be
5701 if (binary
->rodata_size
&&
5702 (processor
== PIPE_SHADER_VERTEX
||
5703 processor
== PIPE_SHADER_TESS_CTRL
||
5704 processor
== PIPE_SHADER_TESS_EVAL
||
5705 processor
== PIPE_SHADER_FRAGMENT
)) {
5706 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
5713 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
5715 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
5716 LLVMBuildRetVoid(ctx
->ac
.builder
);
5718 LLVMBuildRet(ctx
->ac
.builder
, ret
);
5721 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5723 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
5724 struct si_compiler
*compiler
,
5725 struct si_shader_selector
*gs_selector
,
5726 struct pipe_debug_callback
*debug
)
5728 struct si_shader_context ctx
;
5729 struct si_shader
*shader
;
5730 LLVMBuilderRef builder
;
5731 struct si_shader_output_values
*outputs
;
5732 struct tgsi_shader_info
*gsinfo
= &gs_selector
->info
;
5735 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
5740 shader
= CALLOC_STRUCT(si_shader
);
5746 /* We can leave the fence as permanently signaled because the GS copy
5747 * shader only becomes visible globally after it has been compiled. */
5748 util_queue_fence_init(&shader
->ready
);
5750 shader
->selector
= gs_selector
;
5751 shader
->is_gs_copy_shader
= true;
5753 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
5754 ctx
.shader
= shader
;
5755 ctx
.type
= PIPE_SHADER_VERTEX
;
5757 builder
= ctx
.ac
.builder
;
5759 create_function(&ctx
);
5760 preload_ring_buffers(&ctx
);
5762 LLVMValueRef voffset
=
5763 LLVMBuildMul(ctx
.ac
.builder
, ctx
.abi
.vertex_id
,
5764 LLVMConstInt(ctx
.i32
, 4, 0), "");
5766 /* Fetch the vertex stream ID.*/
5767 LLVMValueRef stream_id
;
5769 if (gs_selector
->so
.num_outputs
)
5770 stream_id
= si_unpack_param(&ctx
, ctx
.param_streamout_config
, 24, 2);
5772 stream_id
= ctx
.i32_0
;
5774 /* Fill in output information. */
5775 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5776 outputs
[i
].semantic_name
= gsinfo
->output_semantic_name
[i
];
5777 outputs
[i
].semantic_index
= gsinfo
->output_semantic_index
[i
];
5779 for (int chan
= 0; chan
< 4; chan
++) {
5780 outputs
[i
].vertex_stream
[chan
] =
5781 (gsinfo
->output_streams
[i
] >> (2 * chan
)) & 3;
5785 LLVMBasicBlockRef end_bb
;
5786 LLVMValueRef switch_inst
;
5788 end_bb
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, ctx
.main_fn
, "end");
5789 switch_inst
= LLVMBuildSwitch(builder
, stream_id
, end_bb
, 4);
5791 for (int stream
= 0; stream
< 4; stream
++) {
5792 LLVMBasicBlockRef bb
;
5795 if (!gsinfo
->num_stream_output_components
[stream
])
5798 if (stream
> 0 && !gs_selector
->so
.num_outputs
)
5801 bb
= LLVMInsertBasicBlockInContext(ctx
.ac
.context
, end_bb
, "out");
5802 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
.i32
, stream
, 0), bb
);
5803 LLVMPositionBuilderAtEnd(builder
, bb
);
5805 /* Fetch vertex data from GSVS ring */
5807 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5808 for (unsigned chan
= 0; chan
< 4; chan
++) {
5809 if (!(gsinfo
->output_usagemask
[i
] & (1 << chan
)) ||
5810 outputs
[i
].vertex_stream
[chan
] != stream
) {
5811 outputs
[i
].values
[chan
] = LLVMGetUndef(ctx
.f32
);
5815 LLVMValueRef soffset
= LLVMConstInt(ctx
.i32
,
5816 offset
* gs_selector
->gs_max_out_vertices
* 16 * 4, 0);
5819 outputs
[i
].values
[chan
] =
5820 ac_build_buffer_load(&ctx
.ac
,
5821 ctx
.gsvs_ring
[0], 1,
5828 /* Streamout and exports. */
5829 if (gs_selector
->so
.num_outputs
) {
5830 si_llvm_emit_streamout(&ctx
, outputs
,
5831 gsinfo
->num_outputs
,
5836 si_llvm_export_vs(&ctx
, outputs
, gsinfo
->num_outputs
);
5838 LLVMBuildBr(builder
, end_bb
);
5841 LLVMPositionBuilderAtEnd(builder
, end_bb
);
5843 LLVMBuildRetVoid(ctx
.ac
.builder
);
5845 ctx
.type
= PIPE_SHADER_GEOMETRY
; /* override for shader dumping */
5846 si_llvm_optimize_module(&ctx
);
5848 r
= si_compile_llvm(sscreen
, &ctx
.shader
->binary
,
5849 &ctx
.shader
->config
, ctx
.compiler
,
5851 debug
, PIPE_SHADER_GEOMETRY
,
5854 if (si_can_dump_shader(sscreen
, PIPE_SHADER_GEOMETRY
))
5855 fprintf(stderr
, "GS Copy Shader:\n");
5856 si_shader_dump(sscreen
, ctx
.shader
, debug
,
5857 PIPE_SHADER_GEOMETRY
, stderr
, true);
5858 r
= si_shader_binary_upload(sscreen
, ctx
.shader
);
5861 si_llvm_dispose(&ctx
);
5872 static void si_dump_shader_key_vs(const struct si_shader_key
*key
,
5873 const struct si_vs_prolog_bits
*prolog
,
5874 const char *prefix
, FILE *f
)
5876 fprintf(f
, " %s.instance_divisor_is_one = %u\n",
5877 prefix
, prolog
->instance_divisor_is_one
);
5878 fprintf(f
, " %s.instance_divisor_is_fetched = %u\n",
5879 prefix
, prolog
->instance_divisor_is_fetched
);
5880 fprintf(f
, " %s.ls_vgpr_fix = %u\n",
5881 prefix
, prolog
->ls_vgpr_fix
);
5883 fprintf(f
, " mono.vs.fix_fetch = {");
5884 for (int i
= 0; i
< SI_MAX_ATTRIBS
; i
++)
5885 fprintf(f
, !i
? "%u" : ", %u", key
->mono
.vs_fix_fetch
[i
]);
5889 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
5892 const struct si_shader_key
*key
= &shader
->key
;
5894 fprintf(f
, "SHADER KEY\n");
5896 switch (processor
) {
5897 case PIPE_SHADER_VERTEX
:
5898 si_dump_shader_key_vs(key
, &key
->part
.vs
.prolog
,
5899 "part.vs.prolog", f
);
5900 fprintf(f
, " as_es = %u\n", key
->as_es
);
5901 fprintf(f
, " as_ls = %u\n", key
->as_ls
);
5902 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5903 key
->mono
.u
.vs_export_prim_id
);
5906 case PIPE_SHADER_TESS_CTRL
:
5907 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
) {
5908 si_dump_shader_key_vs(key
, &key
->part
.tcs
.ls_prolog
,
5909 "part.tcs.ls_prolog", f
);
5911 fprintf(f
, " part.tcs.epilog.prim_mode = %u\n", key
->part
.tcs
.epilog
.prim_mode
);
5912 fprintf(f
, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64
"\n", key
->mono
.u
.ff_tcs_inputs_to_copy
);
5915 case PIPE_SHADER_TESS_EVAL
:
5916 fprintf(f
, " as_es = %u\n", key
->as_es
);
5917 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5918 key
->mono
.u
.vs_export_prim_id
);
5921 case PIPE_SHADER_GEOMETRY
:
5922 if (shader
->is_gs_copy_shader
)
5925 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
&&
5926 key
->part
.gs
.es
->type
== PIPE_SHADER_VERTEX
) {
5927 si_dump_shader_key_vs(key
, &key
->part
.gs
.vs_prolog
,
5928 "part.gs.vs_prolog", f
);
5930 fprintf(f
, " part.gs.prolog.tri_strip_adj_fix = %u\n", key
->part
.gs
.prolog
.tri_strip_adj_fix
);
5933 case PIPE_SHADER_COMPUTE
:
5936 case PIPE_SHADER_FRAGMENT
:
5937 fprintf(f
, " part.ps.prolog.color_two_side = %u\n", key
->part
.ps
.prolog
.color_two_side
);
5938 fprintf(f
, " part.ps.prolog.flatshade_colors = %u\n", key
->part
.ps
.prolog
.flatshade_colors
);
5939 fprintf(f
, " part.ps.prolog.poly_stipple = %u\n", key
->part
.ps
.prolog
.poly_stipple
);
5940 fprintf(f
, " part.ps.prolog.force_persp_sample_interp = %u\n", key
->part
.ps
.prolog
.force_persp_sample_interp
);
5941 fprintf(f
, " part.ps.prolog.force_linear_sample_interp = %u\n", key
->part
.ps
.prolog
.force_linear_sample_interp
);
5942 fprintf(f
, " part.ps.prolog.force_persp_center_interp = %u\n", key
->part
.ps
.prolog
.force_persp_center_interp
);
5943 fprintf(f
, " part.ps.prolog.force_linear_center_interp = %u\n", key
->part
.ps
.prolog
.force_linear_center_interp
);
5944 fprintf(f
, " part.ps.prolog.bc_optimize_for_persp = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_persp
);
5945 fprintf(f
, " part.ps.prolog.bc_optimize_for_linear = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_linear
);
5946 fprintf(f
, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key
->part
.ps
.epilog
.spi_shader_col_format
);
5947 fprintf(f
, " part.ps.epilog.color_is_int8 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int8
);
5948 fprintf(f
, " part.ps.epilog.color_is_int10 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int10
);
5949 fprintf(f
, " part.ps.epilog.last_cbuf = %u\n", key
->part
.ps
.epilog
.last_cbuf
);
5950 fprintf(f
, " part.ps.epilog.alpha_func = %u\n", key
->part
.ps
.epilog
.alpha_func
);
5951 fprintf(f
, " part.ps.epilog.alpha_to_one = %u\n", key
->part
.ps
.epilog
.alpha_to_one
);
5952 fprintf(f
, " part.ps.epilog.poly_line_smoothing = %u\n", key
->part
.ps
.epilog
.poly_line_smoothing
);
5953 fprintf(f
, " part.ps.epilog.clamp_color = %u\n", key
->part
.ps
.epilog
.clamp_color
);
5960 if ((processor
== PIPE_SHADER_GEOMETRY
||
5961 processor
== PIPE_SHADER_TESS_EVAL
||
5962 processor
== PIPE_SHADER_VERTEX
) &&
5963 !key
->as_es
&& !key
->as_ls
) {
5964 fprintf(f
, " opt.kill_outputs = 0x%"PRIx64
"\n", key
->opt
.kill_outputs
);
5965 fprintf(f
, " opt.clip_disable = %u\n", key
->opt
.clip_disable
);
5969 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
5970 struct si_screen
*sscreen
,
5971 struct si_compiler
*compiler
)
5973 struct lp_build_tgsi_context
*bld_base
;
5975 si_llvm_context_init(ctx
, sscreen
, compiler
);
5977 bld_base
= &ctx
->bld_base
;
5978 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
5980 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
5981 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
5982 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
5984 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
5986 bld_base
->op_actions
[TGSI_OPCODE_CLOCK
].emit
= clock_emit
;
5988 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
5989 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
5990 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
5991 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
5993 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ALL
].emit
= vote_all_emit
;
5994 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ANY
].emit
= vote_any_emit
;
5995 bld_base
->op_actions
[TGSI_OPCODE_VOTE_EQ
].emit
= vote_eq_emit
;
5996 bld_base
->op_actions
[TGSI_OPCODE_BALLOT
].emit
= ballot_emit
;
5997 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].intr_name
= "llvm.amdgcn.readfirstlane";
5998 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].emit
= read_lane_emit
;
5999 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].intr_name
= "llvm.amdgcn.readlane";
6000 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].fetch_args
= read_invoc_fetch_args
;
6001 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].emit
= read_lane_emit
;
6003 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_tgsi_emit_vertex
;
6004 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_tgsi_emit_primitive
;
6005 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6008 static void si_optimize_vs_outputs(struct si_shader_context
*ctx
)
6010 struct si_shader
*shader
= ctx
->shader
;
6011 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6013 if ((ctx
->type
!= PIPE_SHADER_VERTEX
&&
6014 ctx
->type
!= PIPE_SHADER_TESS_EVAL
) ||
6015 shader
->key
.as_ls
||
6019 ac_optimize_vs_outputs(&ctx
->ac
,
6021 shader
->info
.vs_output_param_offset
,
6023 &shader
->info
.nr_param_exports
);
6026 static void si_init_exec_from_input(struct si_shader_context
*ctx
,
6027 unsigned param
, unsigned bitoffset
)
6029 LLVMValueRef args
[] = {
6030 LLVMGetParam(ctx
->main_fn
, param
),
6031 LLVMConstInt(ctx
->i32
, bitoffset
, 0),
6033 lp_build_intrinsic(ctx
->ac
.builder
,
6034 "llvm.amdgcn.init.exec.from.input",
6035 ctx
->voidt
, args
, 2, LP_FUNC_ATTR_CONVERGENT
);
6038 static bool si_vs_needs_prolog(const struct si_shader_selector
*sel
,
6039 const struct si_vs_prolog_bits
*key
)
6041 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6043 return sel
->vs_needs_prolog
|| key
->ls_vgpr_fix
;
6046 static bool si_compile_tgsi_main(struct si_shader_context
*ctx
)
6048 struct si_shader
*shader
= ctx
->shader
;
6049 struct si_shader_selector
*sel
= shader
->selector
;
6050 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
6052 // TODO clean all this up!
6053 switch (ctx
->type
) {
6054 case PIPE_SHADER_VERTEX
:
6055 ctx
->load_input
= declare_input_vs
;
6056 if (shader
->key
.as_ls
)
6057 ctx
->abi
.emit_outputs
= si_llvm_emit_ls_epilogue
;
6058 else if (shader
->key
.as_es
)
6059 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6061 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6062 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6063 ctx
->abi
.load_base_vertex
= get_base_vertex
;
6065 case PIPE_SHADER_TESS_CTRL
:
6066 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6067 ctx
->abi
.load_tess_varyings
= si_nir_load_tcs_varyings
;
6068 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6069 bld_base
->emit_store
= store_output_tcs
;
6070 ctx
->abi
.store_tcs_outputs
= si_nir_store_output_tcs
;
6071 ctx
->abi
.emit_outputs
= si_llvm_emit_tcs_epilogue
;
6072 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6073 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6075 case PIPE_SHADER_TESS_EVAL
:
6076 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6077 ctx
->abi
.load_tess_varyings
= si_nir_load_input_tes
;
6078 ctx
->abi
.load_tess_coord
= si_load_tess_coord
;
6079 ctx
->abi
.load_tess_level
= si_load_tess_level
;
6080 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6081 if (shader
->key
.as_es
)
6082 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6084 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6085 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6087 case PIPE_SHADER_GEOMETRY
:
6088 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6089 ctx
->abi
.load_inputs
= si_nir_load_input_gs
;
6090 ctx
->abi
.emit_vertex
= si_llvm_emit_vertex
;
6091 ctx
->abi
.emit_primitive
= si_llvm_emit_primitive
;
6092 ctx
->abi
.emit_outputs
= si_llvm_emit_gs_epilogue
;
6093 bld_base
->emit_epilogue
= si_tgsi_emit_gs_epilogue
;
6095 case PIPE_SHADER_FRAGMENT
:
6096 ctx
->load_input
= declare_input_fs
;
6097 ctx
->abi
.emit_outputs
= si_llvm_return_fs_outputs
;
6098 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6099 ctx
->abi
.lookup_interp_param
= si_nir_lookup_interp_param
;
6100 ctx
->abi
.load_sample_position
= load_sample_position
;
6101 ctx
->abi
.load_sample_mask_in
= load_sample_mask_in
;
6102 ctx
->abi
.emit_kill
= si_llvm_emit_kill
;
6104 case PIPE_SHADER_COMPUTE
:
6105 ctx
->abi
.load_local_group_size
= get_block_size
;
6108 assert(!"Unsupported shader type");
6112 ctx
->abi
.load_ubo
= load_ubo
;
6113 ctx
->abi
.load_ssbo
= load_ssbo
;
6115 create_function(ctx
);
6116 preload_ring_buffers(ctx
);
6118 /* For GFX9 merged shaders:
6119 * - Set EXEC for the first shader. If the prolog is present, set
6120 * EXEC there instead.
6121 * - Add a barrier before the second shader.
6122 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6123 * an if-statement. This is required for correctness in geometry
6124 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6127 * For monolithic merged shaders, the first shader is wrapped in an
6128 * if-block together with its prolog in si_build_wrapper_function.
6130 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6131 if (!shader
->is_monolithic
&&
6132 sel
->info
.num_instructions
> 1 && /* not empty shader */
6133 (shader
->key
.as_es
|| shader
->key
.as_ls
) &&
6134 (ctx
->type
== PIPE_SHADER_TESS_EVAL
||
6135 (ctx
->type
== PIPE_SHADER_VERTEX
&&
6136 !si_vs_needs_prolog(sel
, &shader
->key
.part
.vs
.prolog
)))) {
6137 si_init_exec_from_input(ctx
,
6138 ctx
->param_merged_wave_info
, 0);
6139 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6140 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6141 if (!shader
->is_monolithic
)
6142 ac_init_exec_full_mask(&ctx
->ac
);
6144 /* The barrier must execute for all shaders in a
6147 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
6149 LLVMValueRef num_threads
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 8, 8);
6151 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
6152 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
6153 lp_build_if(&ctx
->merged_wrap_if_state
, &ctx
->gallivm
, ena
);
6157 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&&
6158 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
6159 for (unsigned i
= 0; i
< 6; i
++) {
6160 ctx
->invoc0_tess_factors
[i
] =
6161 lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i32
, "");
6165 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6167 for (i
= 0; i
< 4; i
++) {
6168 ctx
->gs_next_vertex
[i
] =
6169 lp_build_alloca(&ctx
->gallivm
,
6174 if (sel
->force_correct_derivs_after_kill
) {
6175 ctx
->postponed_kill
= lp_build_alloca_undef(&ctx
->gallivm
, ctx
->i1
, "");
6176 /* true = don't kill. */
6177 LLVMBuildStore(ctx
->ac
.builder
, LLVMConstInt(ctx
->i1
, 1, 0),
6178 ctx
->postponed_kill
);
6182 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6183 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6187 if (!si_nir_build_llvm(ctx
, sel
->nir
)) {
6188 fprintf(stderr
, "Failed to translate shader from NIR to LLVM\n");
6193 si_llvm_build_ret(ctx
, ctx
->return_value
);
6198 * Compute the VS prolog key, which contains all the information needed to
6199 * build the VS prolog function, and set shader->info bits where needed.
6201 * \param info Shader info of the vertex shader.
6202 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6203 * \param prolog_key Key of the VS prolog
6204 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6205 * \param key Output shader part key.
6207 static void si_get_vs_prolog_key(const struct tgsi_shader_info
*info
,
6208 unsigned num_input_sgprs
,
6209 const struct si_vs_prolog_bits
*prolog_key
,
6210 struct si_shader
*shader_out
,
6211 union si_shader_part_key
*key
)
6213 memset(key
, 0, sizeof(*key
));
6214 key
->vs_prolog
.states
= *prolog_key
;
6215 key
->vs_prolog
.num_input_sgprs
= num_input_sgprs
;
6216 key
->vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
6217 key
->vs_prolog
.as_ls
= shader_out
->key
.as_ls
;
6218 key
->vs_prolog
.as_es
= shader_out
->key
.as_es
;
6220 if (shader_out
->selector
->type
== PIPE_SHADER_TESS_CTRL
) {
6221 key
->vs_prolog
.as_ls
= 1;
6222 key
->vs_prolog
.num_merged_next_stage_vgprs
= 2;
6223 } else if (shader_out
->selector
->type
== PIPE_SHADER_GEOMETRY
) {
6224 key
->vs_prolog
.as_es
= 1;
6225 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
6228 /* Enable loading the InstanceID VGPR. */
6229 uint16_t input_mask
= u_bit_consecutive(0, info
->num_inputs
);
6231 if ((key
->vs_prolog
.states
.instance_divisor_is_one
|
6232 key
->vs_prolog
.states
.instance_divisor_is_fetched
) & input_mask
)
6233 shader_out
->info
.uses_instanceid
= true;
6237 * Compute the PS prolog key, which contains all the information needed to
6238 * build the PS prolog function, and set related bits in shader->config.
6240 static void si_get_ps_prolog_key(struct si_shader
*shader
,
6241 union si_shader_part_key
*key
,
6242 bool separate_prolog
)
6244 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6246 memset(key
, 0, sizeof(*key
));
6247 key
->ps_prolog
.states
= shader
->key
.part
.ps
.prolog
;
6248 key
->ps_prolog
.colors_read
= info
->colors_read
;
6249 key
->ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
6250 key
->ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
6251 key
->ps_prolog
.wqm
= info
->uses_derivatives
&&
6252 (key
->ps_prolog
.colors_read
||
6253 key
->ps_prolog
.states
.force_persp_sample_interp
||
6254 key
->ps_prolog
.states
.force_linear_sample_interp
||
6255 key
->ps_prolog
.states
.force_persp_center_interp
||
6256 key
->ps_prolog
.states
.force_linear_center_interp
||
6257 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6258 key
->ps_prolog
.states
.bc_optimize_for_linear
);
6259 key
->ps_prolog
.ancillary_vgpr_index
= shader
->info
.ancillary_vgpr_index
;
6261 if (info
->colors_read
) {
6262 unsigned *color
= shader
->selector
->color_attr_index
;
6264 if (shader
->key
.part
.ps
.prolog
.color_two_side
) {
6265 /* BCOLORs are stored after the last input. */
6266 key
->ps_prolog
.num_interp_inputs
= info
->num_inputs
;
6267 key
->ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
6268 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
6271 for (unsigned i
= 0; i
< 2; i
++) {
6272 unsigned interp
= info
->input_interpolate
[color
[i
]];
6273 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
6275 if (!(info
->colors_read
& (0xf << i
*4)))
6278 key
->ps_prolog
.color_attr_index
[i
] = color
[i
];
6280 if (shader
->key
.part
.ps
.prolog
.flatshade_colors
&&
6281 interp
== TGSI_INTERPOLATE_COLOR
)
6282 interp
= TGSI_INTERPOLATE_CONSTANT
;
6285 case TGSI_INTERPOLATE_CONSTANT
:
6286 key
->ps_prolog
.color_interp_vgpr_index
[i
] = -1;
6288 case TGSI_INTERPOLATE_PERSPECTIVE
:
6289 case TGSI_INTERPOLATE_COLOR
:
6290 /* Force the interpolation location for colors here. */
6291 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
)
6292 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6293 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
)
6294 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6297 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6298 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 0;
6299 shader
->config
.spi_ps_input_ena
|=
6300 S_0286CC_PERSP_SAMPLE_ENA(1);
6302 case TGSI_INTERPOLATE_LOC_CENTER
:
6303 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 2;
6304 shader
->config
.spi_ps_input_ena
|=
6305 S_0286CC_PERSP_CENTER_ENA(1);
6307 case TGSI_INTERPOLATE_LOC_CENTROID
:
6308 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 4;
6309 shader
->config
.spi_ps_input_ena
|=
6310 S_0286CC_PERSP_CENTROID_ENA(1);
6316 case TGSI_INTERPOLATE_LINEAR
:
6317 /* Force the interpolation location for colors here. */
6318 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
)
6319 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6320 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
)
6321 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6323 /* The VGPR assignment for non-monolithic shaders
6324 * works because InitialPSInputAddr is set on the
6325 * main shader and PERSP_PULL_MODEL is never used.
6328 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6329 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6330 separate_prolog
? 6 : 9;
6331 shader
->config
.spi_ps_input_ena
|=
6332 S_0286CC_LINEAR_SAMPLE_ENA(1);
6334 case TGSI_INTERPOLATE_LOC_CENTER
:
6335 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6336 separate_prolog
? 8 : 11;
6337 shader
->config
.spi_ps_input_ena
|=
6338 S_0286CC_LINEAR_CENTER_ENA(1);
6340 case TGSI_INTERPOLATE_LOC_CENTROID
:
6341 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6342 separate_prolog
? 10 : 13;
6343 shader
->config
.spi_ps_input_ena
|=
6344 S_0286CC_LINEAR_CENTROID_ENA(1);
6358 * Check whether a PS prolog is required based on the key.
6360 static bool si_need_ps_prolog(const union si_shader_part_key
*key
)
6362 return key
->ps_prolog
.colors_read
||
6363 key
->ps_prolog
.states
.force_persp_sample_interp
||
6364 key
->ps_prolog
.states
.force_linear_sample_interp
||
6365 key
->ps_prolog
.states
.force_persp_center_interp
||
6366 key
->ps_prolog
.states
.force_linear_center_interp
||
6367 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6368 key
->ps_prolog
.states
.bc_optimize_for_linear
||
6369 key
->ps_prolog
.states
.poly_stipple
||
6370 key
->ps_prolog
.states
.samplemask_log_ps_iter
;
6374 * Compute the PS epilog key, which contains all the information needed to
6375 * build the PS epilog function.
6377 static void si_get_ps_epilog_key(struct si_shader
*shader
,
6378 union si_shader_part_key
*key
)
6380 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6381 memset(key
, 0, sizeof(*key
));
6382 key
->ps_epilog
.colors_written
= info
->colors_written
;
6383 key
->ps_epilog
.writes_z
= info
->writes_z
;
6384 key
->ps_epilog
.writes_stencil
= info
->writes_stencil
;
6385 key
->ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
6386 key
->ps_epilog
.states
= shader
->key
.part
.ps
.epilog
;
6390 * Build the GS prolog function. Rotate the input vertices for triangle strips
6393 static void si_build_gs_prolog_function(struct si_shader_context
*ctx
,
6394 union si_shader_part_key
*key
)
6396 unsigned num_sgprs
, num_vgprs
;
6397 struct si_function_info fninfo
;
6398 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6399 LLVMTypeRef returns
[48];
6400 LLVMValueRef func
, ret
;
6402 si_init_function_info(&fninfo
);
6404 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6405 if (key
->gs_prolog
.states
.gfx9_prev_is_vs
)
6406 num_sgprs
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
6408 num_sgprs
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
6409 num_vgprs
= 5; /* ES inputs are not needed by GS */
6411 num_sgprs
= GFX6_GS_NUM_USER_SGPR
+ 2;
6415 for (unsigned i
= 0; i
< num_sgprs
; ++i
) {
6416 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6417 returns
[i
] = ctx
->i32
;
6420 for (unsigned i
= 0; i
< num_vgprs
; ++i
) {
6421 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
6422 returns
[num_sgprs
+ i
] = ctx
->f32
;
6425 /* Create the function. */
6426 si_create_function(ctx
, "gs_prolog", returns
, num_sgprs
+ num_vgprs
,
6428 func
= ctx
->main_fn
;
6430 /* Set the full EXEC mask for the prolog, because we are only fiddling
6431 * with registers here. The main shader part will set the correct EXEC
6434 if (ctx
->screen
->info
.chip_class
>= GFX9
&& !key
->gs_prolog
.is_monolithic
)
6435 ac_init_exec_full_mask(&ctx
->ac
);
6437 /* Copy inputs to outputs. This should be no-op, as the registers match,
6438 * but it will prevent the compiler from overwriting them unintentionally.
6440 ret
= ctx
->return_value
;
6441 for (unsigned i
= 0; i
< num_sgprs
; i
++) {
6442 LLVMValueRef p
= LLVMGetParam(func
, i
);
6443 ret
= LLVMBuildInsertValue(builder
, ret
, p
, i
, "");
6445 for (unsigned i
= 0; i
< num_vgprs
; i
++) {
6446 LLVMValueRef p
= LLVMGetParam(func
, num_sgprs
+ i
);
6447 p
= ac_to_float(&ctx
->ac
, p
);
6448 ret
= LLVMBuildInsertValue(builder
, ret
, p
, num_sgprs
+ i
, "");
6451 if (key
->gs_prolog
.states
.tri_strip_adj_fix
) {
6452 /* Remap the input vertices for every other primitive. */
6453 const unsigned gfx6_vtx_params
[6] = {
6461 const unsigned gfx9_vtx_params
[3] = {
6466 LLVMValueRef vtx_in
[6], vtx_out
[6];
6467 LLVMValueRef prim_id
, rotate
;
6469 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6470 for (unsigned i
= 0; i
< 3; i
++) {
6471 vtx_in
[i
*2] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 0, 16);
6472 vtx_in
[i
*2+1] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 16, 16);
6475 for (unsigned i
= 0; i
< 6; i
++)
6476 vtx_in
[i
] = LLVMGetParam(func
, gfx6_vtx_params
[i
]);
6479 prim_id
= LLVMGetParam(func
, num_sgprs
+ 2);
6480 rotate
= LLVMBuildTrunc(builder
, prim_id
, ctx
->i1
, "");
6482 for (unsigned i
= 0; i
< 6; ++i
) {
6483 LLVMValueRef base
, rotated
;
6485 rotated
= vtx_in
[(i
+ 4) % 6];
6486 vtx_out
[i
] = LLVMBuildSelect(builder
, rotate
, rotated
, base
, "");
6489 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6490 for (unsigned i
= 0; i
< 3; i
++) {
6491 LLVMValueRef hi
, out
;
6493 hi
= LLVMBuildShl(builder
, vtx_out
[i
*2+1],
6494 LLVMConstInt(ctx
->i32
, 16, 0), "");
6495 out
= LLVMBuildOr(builder
, vtx_out
[i
*2], hi
, "");
6496 out
= ac_to_float(&ctx
->ac
, out
);
6497 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6498 gfx9_vtx_params
[i
], "");
6501 for (unsigned i
= 0; i
< 6; i
++) {
6504 out
= ac_to_float(&ctx
->ac
, vtx_out
[i
]);
6505 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6506 gfx6_vtx_params
[i
], "");
6511 LLVMBuildRet(builder
, ret
);
6515 * Given a list of shader part functions, build a wrapper function that
6516 * runs them in sequence to form a monolithic shader.
6518 static void si_build_wrapper_function(struct si_shader_context
*ctx
,
6519 LLVMValueRef
*parts
,
6522 unsigned next_shader_first_part
)
6524 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6525 /* PS epilog has one arg per color component; gfx9 merged shader
6526 * prologs need to forward 32 user SGPRs.
6528 struct si_function_info fninfo
;
6529 LLVMValueRef initial
[64], out
[64];
6530 LLVMTypeRef function_type
;
6531 unsigned num_first_params
;
6532 unsigned num_out
, initial_num_out
;
6533 MAYBE_UNUSED
unsigned num_out_sgpr
; /* used in debug checks */
6534 MAYBE_UNUSED
unsigned initial_num_out_sgpr
; /* used in debug checks */
6535 unsigned num_sgprs
, num_vgprs
;
6537 struct lp_build_if_state if_state
;
6539 si_init_function_info(&fninfo
);
6541 for (unsigned i
= 0; i
< num_parts
; ++i
) {
6542 lp_add_function_attr(parts
[i
], -1, LP_FUNC_ATTR_ALWAYSINLINE
);
6543 LLVMSetLinkage(parts
[i
], LLVMPrivateLinkage
);
6546 /* The parameters of the wrapper function correspond to those of the
6547 * first part in terms of SGPRs and VGPRs, but we use the types of the
6548 * main part to get the right types. This is relevant for the
6549 * dereferenceable attribute on descriptor table pointers.
6554 function_type
= LLVMGetElementType(LLVMTypeOf(parts
[0]));
6555 num_first_params
= LLVMCountParamTypes(function_type
);
6557 for (unsigned i
= 0; i
< num_first_params
; ++i
) {
6558 LLVMValueRef param
= LLVMGetParam(parts
[0], i
);
6560 if (ac_is_sgpr_param(param
)) {
6561 assert(num_vgprs
== 0);
6562 num_sgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6564 num_vgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6569 while (gprs
< num_sgprs
+ num_vgprs
) {
6570 LLVMValueRef param
= LLVMGetParam(parts
[main_part
], fninfo
.num_params
);
6571 LLVMTypeRef type
= LLVMTypeOf(param
);
6572 unsigned size
= ac_get_type_size(type
) / 4;
6574 add_arg(&fninfo
, gprs
< num_sgprs
? ARG_SGPR
: ARG_VGPR
, type
);
6576 assert(ac_is_sgpr_param(param
) == (gprs
< num_sgprs
));
6577 assert(gprs
+ size
<= num_sgprs
+ num_vgprs
&&
6578 (gprs
>= num_sgprs
|| gprs
+ size
<= num_sgprs
));
6583 si_create_function(ctx
, "wrapper", NULL
, 0, &fninfo
,
6584 si_get_max_workgroup_size(ctx
->shader
));
6586 if (is_merged_shader(ctx
->shader
))
6587 ac_init_exec_full_mask(&ctx
->ac
);
6589 /* Record the arguments of the function as if they were an output of
6595 for (unsigned i
= 0; i
< fninfo
.num_params
; ++i
) {
6596 LLVMValueRef param
= LLVMGetParam(ctx
->main_fn
, i
);
6597 LLVMTypeRef param_type
= LLVMTypeOf(param
);
6598 LLVMTypeRef out_type
= i
< fninfo
.num_sgpr_params
? ctx
->i32
: ctx
->f32
;
6599 unsigned size
= ac_get_type_size(param_type
) / 4;
6602 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6603 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i32
, "");
6604 param_type
= ctx
->i32
;
6607 if (param_type
!= out_type
)
6608 param
= LLVMBuildBitCast(builder
, param
, out_type
, "");
6609 out
[num_out
++] = param
;
6611 LLVMTypeRef vector_type
= LLVMVectorType(out_type
, size
);
6613 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6614 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i64
, "");
6615 param_type
= ctx
->i64
;
6618 if (param_type
!= vector_type
)
6619 param
= LLVMBuildBitCast(builder
, param
, vector_type
, "");
6621 for (unsigned j
= 0; j
< size
; ++j
)
6622 out
[num_out
++] = LLVMBuildExtractElement(
6623 builder
, param
, LLVMConstInt(ctx
->i32
, j
, 0), "");
6626 if (i
< fninfo
.num_sgpr_params
)
6627 num_out_sgpr
= num_out
;
6630 memcpy(initial
, out
, sizeof(out
));
6631 initial_num_out
= num_out
;
6632 initial_num_out_sgpr
= num_out_sgpr
;
6634 /* Now chain the parts. */
6635 for (unsigned part
= 0; part
< num_parts
; ++part
) {
6636 LLVMValueRef in
[48];
6638 LLVMTypeRef ret_type
;
6639 unsigned out_idx
= 0;
6640 unsigned num_params
= LLVMCountParams(parts
[part
]);
6642 /* Merged shaders are executed conditionally depending
6643 * on the number of enabled threads passed in the input SGPRs. */
6644 if (is_merged_shader(ctx
->shader
) && part
== 0) {
6645 LLVMValueRef ena
, count
= initial
[3];
6647 count
= LLVMBuildAnd(builder
, count
,
6648 LLVMConstInt(ctx
->i32
, 0x7f, 0), "");
6649 ena
= LLVMBuildICmp(builder
, LLVMIntULT
,
6650 ac_get_thread_id(&ctx
->ac
), count
, "");
6651 lp_build_if(&if_state
, &ctx
->gallivm
, ena
);
6654 /* Derive arguments for the next part from outputs of the
6657 for (unsigned param_idx
= 0; param_idx
< num_params
; ++param_idx
) {
6659 LLVMTypeRef param_type
;
6661 unsigned param_size
;
6662 LLVMValueRef arg
= NULL
;
6664 param
= LLVMGetParam(parts
[part
], param_idx
);
6665 param_type
= LLVMTypeOf(param
);
6666 param_size
= ac_get_type_size(param_type
) / 4;
6667 is_sgpr
= ac_is_sgpr_param(param
);
6670 lp_add_function_attr(parts
[part
], param_idx
+ 1, LP_FUNC_ATTR_INREG
);
6671 else if (out_idx
< num_out_sgpr
) {
6672 /* Skip returned SGPRs the current part doesn't
6673 * declare on the input. */
6674 out_idx
= num_out_sgpr
;
6677 assert(out_idx
+ param_size
<= (is_sgpr
? num_out_sgpr
: num_out
));
6679 if (param_size
== 1)
6682 arg
= ac_build_gather_values(&ctx
->ac
, &out
[out_idx
], param_size
);
6684 if (LLVMTypeOf(arg
) != param_type
) {
6685 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6686 if (LLVMGetPointerAddressSpace(param_type
) ==
6687 AC_CONST_32BIT_ADDR_SPACE
) {
6688 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
6689 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6691 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i64
, "");
6692 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6695 arg
= LLVMBuildBitCast(builder
, arg
, param_type
, "");
6699 in
[param_idx
] = arg
;
6700 out_idx
+= param_size
;
6703 ret
= LLVMBuildCall(builder
, parts
[part
], in
, num_params
, "");
6705 if (is_merged_shader(ctx
->shader
) &&
6706 part
+ 1 == next_shader_first_part
) {
6707 lp_build_endif(&if_state
);
6709 /* The second half of the merged shader should use
6710 * the inputs from the toplevel (wrapper) function,
6711 * not the return value from the last call.
6713 * That's because the last call was executed condi-
6714 * tionally, so we can't consume it in the main
6717 memcpy(out
, initial
, sizeof(initial
));
6718 num_out
= initial_num_out
;
6719 num_out_sgpr
= initial_num_out_sgpr
;
6723 /* Extract the returned GPRs. */
6724 ret_type
= LLVMTypeOf(ret
);
6728 if (LLVMGetTypeKind(ret_type
) != LLVMVoidTypeKind
) {
6729 assert(LLVMGetTypeKind(ret_type
) == LLVMStructTypeKind
);
6731 unsigned ret_size
= LLVMCountStructElementTypes(ret_type
);
6733 for (unsigned i
= 0; i
< ret_size
; ++i
) {
6735 LLVMBuildExtractValue(builder
, ret
, i
, "");
6737 assert(num_out
< ARRAY_SIZE(out
));
6738 out
[num_out
++] = val
;
6740 if (LLVMTypeOf(val
) == ctx
->i32
) {
6741 assert(num_out_sgpr
+ 1 == num_out
);
6742 num_out_sgpr
= num_out
;
6748 LLVMBuildRetVoid(builder
);
6751 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6752 struct si_compiler
*compiler
,
6753 struct si_shader
*shader
,
6754 struct pipe_debug_callback
*debug
)
6756 struct si_shader_selector
*sel
= shader
->selector
;
6757 struct si_shader_context ctx
;
6760 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6761 * conversion fails. */
6762 if (si_can_dump_shader(sscreen
, sel
->info
.processor
) &&
6763 !(sscreen
->debug_flags
& DBG(NO_TGSI
))) {
6765 tgsi_dump(sel
->tokens
, 0);
6767 nir_print_shader(sel
->nir
, stderr
);
6768 si_dump_streamout(&sel
->so
);
6771 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
6772 si_llvm_context_set_tgsi(&ctx
, shader
);
6774 memset(shader
->info
.vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6775 sizeof(shader
->info
.vs_output_param_offset
));
6777 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6779 if (!si_compile_tgsi_main(&ctx
)) {
6780 si_llvm_dispose(&ctx
);
6784 if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_VERTEX
) {
6785 LLVMValueRef parts
[2];
6786 bool need_prolog
= sel
->vs_needs_prolog
;
6788 parts
[1] = ctx
.main_fn
;
6791 union si_shader_part_key prolog_key
;
6792 si_get_vs_prolog_key(&sel
->info
,
6793 shader
->info
.num_input_sgprs
,
6794 &shader
->key
.part
.vs
.prolog
,
6795 shader
, &prolog_key
);
6796 si_build_vs_prolog_function(&ctx
, &prolog_key
);
6797 parts
[0] = ctx
.main_fn
;
6800 si_build_wrapper_function(&ctx
, parts
+ !need_prolog
,
6801 1 + need_prolog
, need_prolog
, 0);
6802 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
6803 if (sscreen
->info
.chip_class
>= GFX9
) {
6804 struct si_shader_selector
*ls
= shader
->key
.part
.tcs
.ls
;
6805 LLVMValueRef parts
[4];
6806 bool vs_needs_prolog
=
6807 si_vs_needs_prolog(ls
, &shader
->key
.part
.tcs
.ls_prolog
);
6810 parts
[2] = ctx
.main_fn
;
6813 union si_shader_part_key tcs_epilog_key
;
6814 memset(&tcs_epilog_key
, 0, sizeof(tcs_epilog_key
));
6815 tcs_epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6816 si_build_tcs_epilog_function(&ctx
, &tcs_epilog_key
);
6817 parts
[3] = ctx
.main_fn
;
6819 /* VS as LS main part */
6820 struct si_shader shader_ls
= {};
6821 shader_ls
.selector
= ls
;
6822 shader_ls
.key
.as_ls
= 1;
6823 shader_ls
.key
.mono
= shader
->key
.mono
;
6824 shader_ls
.key
.opt
= shader
->key
.opt
;
6825 shader_ls
.is_monolithic
= true;
6826 si_llvm_context_set_tgsi(&ctx
, &shader_ls
);
6828 if (!si_compile_tgsi_main(&ctx
)) {
6829 si_llvm_dispose(&ctx
);
6832 shader
->info
.uses_instanceid
|= ls
->info
.uses_instanceid
;
6833 parts
[1] = ctx
.main_fn
;
6836 if (vs_needs_prolog
) {
6837 union si_shader_part_key vs_prolog_key
;
6838 si_get_vs_prolog_key(&ls
->info
,
6839 shader_ls
.info
.num_input_sgprs
,
6840 &shader
->key
.part
.tcs
.ls_prolog
,
6841 shader
, &vs_prolog_key
);
6842 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6843 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6844 parts
[0] = ctx
.main_fn
;
6847 /* Reset the shader context. */
6848 ctx
.shader
= shader
;
6849 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
6851 si_build_wrapper_function(&ctx
,
6852 parts
+ !vs_needs_prolog
,
6853 4 - !vs_needs_prolog
, vs_needs_prolog
,
6854 vs_needs_prolog
? 2 : 1);
6856 LLVMValueRef parts
[2];
6857 union si_shader_part_key epilog_key
;
6859 parts
[0] = ctx
.main_fn
;
6861 memset(&epilog_key
, 0, sizeof(epilog_key
));
6862 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6863 si_build_tcs_epilog_function(&ctx
, &epilog_key
);
6864 parts
[1] = ctx
.main_fn
;
6866 si_build_wrapper_function(&ctx
, parts
, 2, 0, 0);
6868 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6869 if (ctx
.screen
->info
.chip_class
>= GFX9
) {
6870 struct si_shader_selector
*es
= shader
->key
.part
.gs
.es
;
6871 LLVMValueRef es_prolog
= NULL
;
6872 LLVMValueRef es_main
= NULL
;
6873 LLVMValueRef gs_prolog
= NULL
;
6874 LLVMValueRef gs_main
= ctx
.main_fn
;
6877 union si_shader_part_key gs_prolog_key
;
6878 memset(&gs_prolog_key
, 0, sizeof(gs_prolog_key
));
6879 gs_prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6880 gs_prolog_key
.gs_prolog
.is_monolithic
= true;
6881 si_build_gs_prolog_function(&ctx
, &gs_prolog_key
);
6882 gs_prolog
= ctx
.main_fn
;
6885 struct si_shader shader_es
= {};
6886 shader_es
.selector
= es
;
6887 shader_es
.key
.as_es
= 1;
6888 shader_es
.key
.mono
= shader
->key
.mono
;
6889 shader_es
.key
.opt
= shader
->key
.opt
;
6890 shader_es
.is_monolithic
= true;
6891 si_llvm_context_set_tgsi(&ctx
, &shader_es
);
6893 if (!si_compile_tgsi_main(&ctx
)) {
6894 si_llvm_dispose(&ctx
);
6897 shader
->info
.uses_instanceid
|= es
->info
.uses_instanceid
;
6898 es_main
= ctx
.main_fn
;
6901 if (es
->vs_needs_prolog
) {
6902 union si_shader_part_key vs_prolog_key
;
6903 si_get_vs_prolog_key(&es
->info
,
6904 shader_es
.info
.num_input_sgprs
,
6905 &shader
->key
.part
.gs
.vs_prolog
,
6906 shader
, &vs_prolog_key
);
6907 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6908 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6909 es_prolog
= ctx
.main_fn
;
6912 /* Reset the shader context. */
6913 ctx
.shader
= shader
;
6914 ctx
.type
= PIPE_SHADER_GEOMETRY
;
6916 /* Prepare the array of shader parts. */
6917 LLVMValueRef parts
[4];
6918 unsigned num_parts
= 0, main_part
, next_first_part
;
6921 parts
[num_parts
++] = es_prolog
;
6923 parts
[main_part
= num_parts
++] = es_main
;
6924 parts
[next_first_part
= num_parts
++] = gs_prolog
;
6925 parts
[num_parts
++] = gs_main
;
6927 si_build_wrapper_function(&ctx
, parts
, num_parts
,
6928 main_part
, next_first_part
);
6930 LLVMValueRef parts
[2];
6931 union si_shader_part_key prolog_key
;
6933 parts
[1] = ctx
.main_fn
;
6935 memset(&prolog_key
, 0, sizeof(prolog_key
));
6936 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6937 si_build_gs_prolog_function(&ctx
, &prolog_key
);
6938 parts
[0] = ctx
.main_fn
;
6940 si_build_wrapper_function(&ctx
, parts
, 2, 1, 0);
6942 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6943 LLVMValueRef parts
[3];
6944 union si_shader_part_key prolog_key
;
6945 union si_shader_part_key epilog_key
;
6948 si_get_ps_prolog_key(shader
, &prolog_key
, false);
6949 need_prolog
= si_need_ps_prolog(&prolog_key
);
6951 parts
[need_prolog
? 1 : 0] = ctx
.main_fn
;
6954 si_build_ps_prolog_function(&ctx
, &prolog_key
);
6955 parts
[0] = ctx
.main_fn
;
6958 si_get_ps_epilog_key(shader
, &epilog_key
);
6959 si_build_ps_epilog_function(&ctx
, &epilog_key
);
6960 parts
[need_prolog
? 2 : 1] = ctx
.main_fn
;
6962 si_build_wrapper_function(&ctx
, parts
, need_prolog
? 3 : 2,
6963 need_prolog
? 1 : 0, 0);
6966 si_llvm_optimize_module(&ctx
);
6968 /* Post-optimization transformations and analysis. */
6969 si_optimize_vs_outputs(&ctx
);
6971 if ((debug
&& debug
->debug_message
) ||
6972 si_can_dump_shader(sscreen
, ctx
.type
)) {
6973 ctx
.shader
->config
.private_mem_vgprs
=
6974 ac_count_scratch_private_memory(ctx
.main_fn
);
6977 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6978 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx
.main_fn
, 0))) ==
6979 LLVMPointerTypeKind
);
6981 /* Compile to bytecode. */
6982 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, compiler
,
6983 ctx
.gallivm
.module
, debug
, ctx
.type
, "TGSI shader");
6984 si_llvm_dispose(&ctx
);
6986 fprintf(stderr
, "LLVM failed to compile shader\n");
6990 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6991 * LLVM 3.9svn has this bug.
6993 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6994 unsigned wave_size
= 64;
6995 unsigned max_vgprs
= 256;
6996 unsigned max_sgprs
= sscreen
->info
.chip_class
>= VI
? 800 : 512;
6997 unsigned max_sgprs_per_wave
= 128;
6998 unsigned max_block_threads
= si_get_max_workgroup_size(shader
);
6999 unsigned min_waves_per_cu
= DIV_ROUND_UP(max_block_threads
, wave_size
);
7000 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
7002 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
7003 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
7005 if (shader
->config
.num_sgprs
> max_sgprs
||
7006 shader
->config
.num_vgprs
> max_vgprs
) {
7007 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
7008 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7009 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
7010 max_sgprs
, max_vgprs
);
7012 /* Just terminate the process, because dependent
7013 * shaders can hang due to bad input data, but use
7014 * the env var to allow shader-db to work.
7016 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7021 /* Add the scratch offset to input SGPRs. */
7022 if (shader
->config
.scratch_bytes_per_wave
&& !is_merged_shader(shader
))
7023 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
7025 /* Calculate the number of fragment input VGPRs. */
7026 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
7027 shader
->info
.num_input_vgprs
= 0;
7028 shader
->info
.face_vgpr_index
= -1;
7029 shader
->info
.ancillary_vgpr_index
= -1;
7031 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7032 shader
->info
.num_input_vgprs
+= 2;
7033 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7034 shader
->info
.num_input_vgprs
+= 2;
7035 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7036 shader
->info
.num_input_vgprs
+= 2;
7037 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
7038 shader
->info
.num_input_vgprs
+= 3;
7039 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7040 shader
->info
.num_input_vgprs
+= 2;
7041 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7042 shader
->info
.num_input_vgprs
+= 2;
7043 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7044 shader
->info
.num_input_vgprs
+= 2;
7045 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
7046 shader
->info
.num_input_vgprs
+= 1;
7047 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7048 shader
->info
.num_input_vgprs
+= 1;
7049 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7050 shader
->info
.num_input_vgprs
+= 1;
7051 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7052 shader
->info
.num_input_vgprs
+= 1;
7053 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7054 shader
->info
.num_input_vgprs
+= 1;
7055 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
7056 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
7057 shader
->info
.num_input_vgprs
+= 1;
7059 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
)) {
7060 shader
->info
.ancillary_vgpr_index
= shader
->info
.num_input_vgprs
;
7061 shader
->info
.num_input_vgprs
+= 1;
7063 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
7064 shader
->info
.num_input_vgprs
+= 1;
7065 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
7066 shader
->info
.num_input_vgprs
+= 1;
7069 si_calculate_max_simd_waves(shader
);
7070 si_shader_dump_stats_for_shader_db(shader
, debug
);
7075 * Create, compile and return a shader part (prolog or epilog).
7077 * \param sscreen screen
7078 * \param list list of shader parts of the same category
7079 * \param type shader type
7080 * \param key shader part key
7081 * \param prolog whether the part being requested is a prolog
7082 * \param tm LLVM target machine
7083 * \param debug debug callback
7084 * \param build the callback responsible for building the main function
7085 * \return non-NULL on success
7087 static struct si_shader_part
*
7088 si_get_shader_part(struct si_screen
*sscreen
,
7089 struct si_shader_part
**list
,
7090 enum pipe_shader_type type
,
7092 union si_shader_part_key
*key
,
7093 struct si_compiler
*compiler
,
7094 struct pipe_debug_callback
*debug
,
7095 void (*build
)(struct si_shader_context
*,
7096 union si_shader_part_key
*),
7099 struct si_shader_part
*result
;
7101 mtx_lock(&sscreen
->shader_parts_mutex
);
7103 /* Find existing. */
7104 for (result
= *list
; result
; result
= result
->next
) {
7105 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
7106 mtx_unlock(&sscreen
->shader_parts_mutex
);
7111 /* Compile a new one. */
7112 result
= CALLOC_STRUCT(si_shader_part
);
7115 struct si_shader shader
= {};
7116 struct si_shader_context ctx
;
7118 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
7119 ctx
.shader
= &shader
;
7123 case PIPE_SHADER_VERTEX
:
7124 shader
.key
.as_ls
= key
->vs_prolog
.as_ls
;
7125 shader
.key
.as_es
= key
->vs_prolog
.as_es
;
7127 case PIPE_SHADER_TESS_CTRL
:
7129 shader
.key
.part
.tcs
.epilog
= key
->tcs_epilog
.states
;
7131 case PIPE_SHADER_GEOMETRY
:
7134 case PIPE_SHADER_FRAGMENT
:
7136 shader
.key
.part
.ps
.prolog
= key
->ps_prolog
.states
;
7138 shader
.key
.part
.ps
.epilog
= key
->ps_epilog
.states
;
7141 unreachable("bad shader part");
7147 si_llvm_optimize_module(&ctx
);
7149 if (si_compile_llvm(sscreen
, &result
->binary
, &result
->config
, compiler
,
7150 ctx
.ac
.module
, debug
, ctx
.type
, name
)) {
7156 result
->next
= *list
;
7160 si_llvm_dispose(&ctx
);
7161 mtx_unlock(&sscreen
->shader_parts_mutex
);
7165 static LLVMValueRef
si_prolog_get_rw_buffers(struct si_shader_context
*ctx
)
7167 LLVMValueRef ptr
[2], list
;
7168 bool is_merged_shader
=
7169 ctx
->screen
->info
.chip_class
>= GFX9
&&
7170 (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
7171 ctx
->type
== PIPE_SHADER_GEOMETRY
||
7172 ctx
->shader
->key
.as_ls
|| ctx
->shader
->key
.as_es
);
7174 if (HAVE_32BIT_POINTERS
) {
7175 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
7176 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, ptr
[0],
7177 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
7181 /* Get the pointer to rw buffers. */
7182 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
7183 ptr
[1] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
+ 1);
7184 list
= ac_build_gather_values(&ctx
->ac
, ptr
, 2);
7185 list
= LLVMBuildBitCast(ctx
->ac
.builder
, list
, ctx
->i64
, "");
7186 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, list
,
7187 ac_array_in_const_addr_space(ctx
->v4i32
), "");
7192 * Build the vertex shader prolog function.
7194 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7195 * All inputs are returned unmodified. The vertex load indices are
7196 * stored after them, which will be used by the API VS for fetching inputs.
7198 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7203 * (VertexID + BaseVertex),
7204 * (InstanceID + StartInstance),
7205 * (InstanceID / 2 + StartInstance)
7207 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
7208 union si_shader_part_key
*key
)
7210 struct si_function_info fninfo
;
7211 LLVMTypeRef
*returns
;
7212 LLVMValueRef ret
, func
;
7214 unsigned first_vs_vgpr
= key
->vs_prolog
.num_merged_next_stage_vgprs
;
7215 unsigned num_input_vgprs
= key
->vs_prolog
.num_merged_next_stage_vgprs
+ 4;
7216 LLVMValueRef input_vgprs
[9];
7217 unsigned num_all_input_regs
= key
->vs_prolog
.num_input_sgprs
+
7219 unsigned user_sgpr_base
= key
->vs_prolog
.num_merged_next_stage_vgprs
? 8 : 0;
7221 si_init_function_info(&fninfo
);
7223 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7224 returns
= alloca((num_all_input_regs
+ key
->vs_prolog
.last_input
+ 1) *
7225 sizeof(LLVMTypeRef
));
7228 /* Declare input and output SGPRs. */
7229 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7230 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7231 returns
[num_returns
++] = ctx
->i32
;
7234 /* Preloaded VGPRs (outputs must be floats) */
7235 for (i
= 0; i
< num_input_vgprs
; i
++) {
7236 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &input_vgprs
[i
]);
7237 returns
[num_returns
++] = ctx
->f32
;
7240 /* Vertex load indices. */
7241 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
7242 returns
[num_returns
++] = ctx
->f32
;
7244 /* Create the function. */
7245 si_create_function(ctx
, "vs_prolog", returns
, num_returns
, &fninfo
, 0);
7246 func
= ctx
->main_fn
;
7248 if (key
->vs_prolog
.num_merged_next_stage_vgprs
) {
7249 if (!key
->vs_prolog
.is_monolithic
)
7250 si_init_exec_from_input(ctx
, 3, 0);
7252 if (key
->vs_prolog
.as_ls
&&
7253 ctx
->screen
->has_ls_vgpr_init_bug
) {
7254 /* If there are no HS threads, SPI loads the LS VGPRs
7255 * starting at VGPR 0. Shift them back to where they
7258 LLVMValueRef has_hs_threads
=
7259 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
7260 si_unpack_param(ctx
, 3, 8, 8),
7263 for (i
= 4; i
> 0; --i
) {
7264 input_vgprs
[i
+ 1] =
7265 LLVMBuildSelect(ctx
->ac
.builder
, has_hs_threads
,
7267 input_vgprs
[i
- 1], "");
7272 ctx
->abi
.vertex_id
= input_vgprs
[first_vs_vgpr
];
7273 ctx
->abi
.instance_id
= input_vgprs
[first_vs_vgpr
+ (key
->vs_prolog
.as_ls
? 2 : 1)];
7275 /* Copy inputs to outputs. This should be no-op, as the registers match,
7276 * but it will prevent the compiler from overwriting them unintentionally.
7278 ret
= ctx
->return_value
;
7279 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7280 LLVMValueRef p
= LLVMGetParam(func
, i
);
7281 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7283 for (i
= 0; i
< num_input_vgprs
; i
++) {
7284 LLVMValueRef p
= input_vgprs
[i
];
7285 p
= ac_to_float(&ctx
->ac
, p
);
7286 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
,
7287 key
->vs_prolog
.num_input_sgprs
+ i
, "");
7290 /* Compute vertex load indices from instance divisors. */
7291 LLVMValueRef instance_divisor_constbuf
= NULL
;
7293 if (key
->vs_prolog
.states
.instance_divisor_is_fetched
) {
7294 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7295 LLVMValueRef buf_index
=
7296 LLVMConstInt(ctx
->i32
, SI_VS_CONST_INSTANCE_DIVISORS
, 0);
7297 instance_divisor_constbuf
=
7298 ac_build_load_to_sgpr(&ctx
->ac
, list
, buf_index
);
7301 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
7302 bool divisor_is_one
=
7303 key
->vs_prolog
.states
.instance_divisor_is_one
& (1u << i
);
7304 bool divisor_is_fetched
=
7305 key
->vs_prolog
.states
.instance_divisor_is_fetched
& (1u << i
);
7308 if (divisor_is_one
|| divisor_is_fetched
) {
7309 LLVMValueRef divisor
= ctx
->i32_1
;
7311 if (divisor_is_fetched
) {
7312 divisor
= buffer_load_const(ctx
, instance_divisor_constbuf
,
7313 LLVMConstInt(ctx
->i32
, i
* 4, 0));
7314 divisor
= ac_to_integer(&ctx
->ac
, divisor
);
7317 /* InstanceID / Divisor + StartInstance */
7318 index
= get_instance_index_for_fetch(ctx
,
7320 SI_SGPR_START_INSTANCE
,
7323 /* VertexID + BaseVertex */
7324 index
= LLVMBuildAdd(ctx
->ac
.builder
,
7326 LLVMGetParam(func
, user_sgpr_base
+
7327 SI_SGPR_BASE_VERTEX
), "");
7330 index
= ac_to_float(&ctx
->ac
, index
);
7331 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, index
,
7332 fninfo
.num_params
+ i
, "");
7335 si_llvm_build_ret(ctx
, ret
);
7338 static bool si_get_vs_prolog(struct si_screen
*sscreen
,
7339 struct si_compiler
*compiler
,
7340 struct si_shader
*shader
,
7341 struct pipe_debug_callback
*debug
,
7342 struct si_shader
*main_part
,
7343 const struct si_vs_prolog_bits
*key
)
7345 struct si_shader_selector
*vs
= main_part
->selector
;
7347 if (!si_vs_needs_prolog(vs
, key
))
7350 /* Get the prolog. */
7351 union si_shader_part_key prolog_key
;
7352 si_get_vs_prolog_key(&vs
->info
, main_part
->info
.num_input_sgprs
,
7353 key
, shader
, &prolog_key
);
7356 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7357 PIPE_SHADER_VERTEX
, true, &prolog_key
, compiler
,
7358 debug
, si_build_vs_prolog_function
,
7359 "Vertex Shader Prolog");
7360 return shader
->prolog
!= NULL
;
7364 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7366 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7367 struct si_compiler
*compiler
,
7368 struct si_shader
*shader
,
7369 struct pipe_debug_callback
*debug
)
7371 return si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, shader
,
7372 &shader
->key
.part
.vs
.prolog
);
7376 * Compile the TCS epilog function. This writes tesselation factors to memory
7377 * based on the output primitive type of the tesselator (determined by TES).
7379 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
7380 union si_shader_part_key
*key
)
7382 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7383 struct si_function_info fninfo
;
7386 si_init_function_info(&fninfo
);
7388 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
7389 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7390 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7391 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7392 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* wave info */
7393 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7394 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7395 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7396 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7397 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7398 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7399 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7400 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7401 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7402 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7403 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7404 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7405 if (!HAVE_32BIT_POINTERS
)
7406 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7407 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7408 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7409 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7411 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7412 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7413 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7414 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7415 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7416 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7417 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7418 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7419 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7420 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7423 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7424 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7425 unsigned tess_factors_idx
=
7426 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* patch index within the wave (REL_PATCH_ID) */
7427 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* invocation ID within the patch */
7428 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* LDS offset where tess factors should be loaded from */
7430 for (unsigned i
= 0; i
< 6; i
++)
7431 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* tess factors */
7433 /* Create the function. */
7434 si_create_function(ctx
, "tcs_epilog", NULL
, 0, &fninfo
,
7435 ctx
->screen
->info
.chip_class
>= CIK
? 128 : 64);
7436 ac_declare_lds_as_pointer(&ctx
->ac
);
7437 func
= ctx
->main_fn
;
7439 LLVMValueRef invoc0_tess_factors
[6];
7440 for (unsigned i
= 0; i
< 6; i
++)
7441 invoc0_tess_factors
[i
] = LLVMGetParam(func
, tess_factors_idx
+ 3 + i
);
7443 si_write_tess_factors(bld_base
,
7444 LLVMGetParam(func
, tess_factors_idx
),
7445 LLVMGetParam(func
, tess_factors_idx
+ 1),
7446 LLVMGetParam(func
, tess_factors_idx
+ 2),
7447 invoc0_tess_factors
, invoc0_tess_factors
+ 4);
7449 LLVMBuildRetVoid(ctx
->ac
.builder
);
7453 * Select and compile (or reuse) TCS parts (epilog).
7455 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7456 struct si_compiler
*compiler
,
7457 struct si_shader
*shader
,
7458 struct pipe_debug_callback
*debug
)
7460 if (sscreen
->info
.chip_class
>= GFX9
) {
7461 struct si_shader
*ls_main_part
=
7462 shader
->key
.part
.tcs
.ls
->main_shader_part_ls
;
7464 if (!si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, ls_main_part
,
7465 &shader
->key
.part
.tcs
.ls_prolog
))
7468 shader
->previous_stage
= ls_main_part
;
7471 /* Get the epilog. */
7472 union si_shader_part_key epilog_key
;
7473 memset(&epilog_key
, 0, sizeof(epilog_key
));
7474 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7476 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7477 PIPE_SHADER_TESS_CTRL
, false,
7478 &epilog_key
, compiler
, debug
,
7479 si_build_tcs_epilog_function
,
7480 "Tessellation Control Shader Epilog");
7481 return shader
->epilog
!= NULL
;
7485 * Select and compile (or reuse) GS parts (prolog).
7487 static bool si_shader_select_gs_parts(struct si_screen
*sscreen
,
7488 struct si_compiler
*compiler
,
7489 struct si_shader
*shader
,
7490 struct pipe_debug_callback
*debug
)
7492 if (sscreen
->info
.chip_class
>= GFX9
) {
7493 struct si_shader
*es_main_part
=
7494 shader
->key
.part
.gs
.es
->main_shader_part_es
;
7496 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_VERTEX
&&
7497 !si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, es_main_part
,
7498 &shader
->key
.part
.gs
.vs_prolog
))
7501 shader
->previous_stage
= es_main_part
;
7504 if (!shader
->key
.part
.gs
.prolog
.tri_strip_adj_fix
)
7507 union si_shader_part_key prolog_key
;
7508 memset(&prolog_key
, 0, sizeof(prolog_key
));
7509 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7511 shader
->prolog2
= si_get_shader_part(sscreen
, &sscreen
->gs_prologs
,
7512 PIPE_SHADER_GEOMETRY
, true,
7513 &prolog_key
, compiler
, debug
,
7514 si_build_gs_prolog_function
,
7515 "Geometry Shader Prolog");
7516 return shader
->prolog2
!= NULL
;
7520 * Build the pixel shader prolog function. This handles:
7521 * - two-side color selection and interpolation
7522 * - overriding interpolation parameters for the API PS
7523 * - polygon stippling
7525 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7526 * overriden by other states. (e.g. per-sample interpolation)
7527 * Interpolated colors are stored after the preloaded VGPRs.
7529 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
7530 union si_shader_part_key
*key
)
7532 struct si_function_info fninfo
;
7533 LLVMValueRef ret
, func
;
7534 int num_returns
, i
, num_color_channels
;
7536 assert(si_need_ps_prolog(key
));
7538 si_init_function_info(&fninfo
);
7540 /* Declare inputs. */
7541 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7542 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7544 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7545 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7547 /* Declare outputs (same as inputs + add colors if needed) */
7548 num_returns
= fninfo
.num_params
;
7549 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7550 for (i
= 0; i
< num_color_channels
; i
++)
7551 fninfo
.types
[num_returns
++] = ctx
->f32
;
7553 /* Create the function. */
7554 si_create_function(ctx
, "ps_prolog", fninfo
.types
, num_returns
,
7556 func
= ctx
->main_fn
;
7558 /* Copy inputs to outputs. This should be no-op, as the registers match,
7559 * but it will prevent the compiler from overwriting them unintentionally.
7561 ret
= ctx
->return_value
;
7562 for (i
= 0; i
< fninfo
.num_params
; i
++) {
7563 LLVMValueRef p
= LLVMGetParam(func
, i
);
7564 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7567 /* Polygon stippling. */
7568 if (key
->ps_prolog
.states
.poly_stipple
) {
7569 /* POS_FIXED_PT is always last. */
7570 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7571 key
->ps_prolog
.num_input_vgprs
- 1;
7572 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7574 si_llvm_emit_polygon_stipple(ctx
, list
, pos
);
7577 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7578 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7579 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7580 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7582 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7583 * The hw doesn't compute CENTROID if the whole wave only
7584 * contains fully-covered quads.
7586 * PRIM_MASK is after user SGPRs.
7588 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7589 bc_optimize
= LLVMBuildLShr(ctx
->ac
.builder
, bc_optimize
,
7590 LLVMConstInt(ctx
->i32
, 31, 0), "");
7591 bc_optimize
= LLVMBuildTrunc(ctx
->ac
.builder
, bc_optimize
,
7594 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7595 /* Read PERSP_CENTER. */
7596 for (i
= 0; i
< 2; i
++)
7597 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7598 /* Read PERSP_CENTROID. */
7599 for (i
= 0; i
< 2; i
++)
7600 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7601 /* Select PERSP_CENTROID. */
7602 for (i
= 0; i
< 2; i
++) {
7603 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7604 center
[i
], centroid
[i
], "");
7605 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7606 tmp
, base
+ 4 + i
, "");
7609 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7610 /* Read LINEAR_CENTER. */
7611 for (i
= 0; i
< 2; i
++)
7612 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7613 /* Read LINEAR_CENTROID. */
7614 for (i
= 0; i
< 2; i
++)
7615 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7616 /* Select LINEAR_CENTROID. */
7617 for (i
= 0; i
< 2; i
++) {
7618 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7619 center
[i
], centroid
[i
], "");
7620 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7621 tmp
, base
+ 10 + i
, "");
7626 /* Force per-sample interpolation. */
7627 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7628 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7629 LLVMValueRef persp_sample
[2];
7631 /* Read PERSP_SAMPLE. */
7632 for (i
= 0; i
< 2; i
++)
7633 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7634 /* Overwrite PERSP_CENTER. */
7635 for (i
= 0; i
< 2; i
++)
7636 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7637 persp_sample
[i
], base
+ 2 + i
, "");
7638 /* Overwrite PERSP_CENTROID. */
7639 for (i
= 0; i
< 2; i
++)
7640 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7641 persp_sample
[i
], base
+ 4 + i
, "");
7643 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7644 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7645 LLVMValueRef linear_sample
[2];
7647 /* Read LINEAR_SAMPLE. */
7648 for (i
= 0; i
< 2; i
++)
7649 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7650 /* Overwrite LINEAR_CENTER. */
7651 for (i
= 0; i
< 2; i
++)
7652 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7653 linear_sample
[i
], base
+ 8 + i
, "");
7654 /* Overwrite LINEAR_CENTROID. */
7655 for (i
= 0; i
< 2; i
++)
7656 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7657 linear_sample
[i
], base
+ 10 + i
, "");
7660 /* Force center interpolation. */
7661 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7662 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7663 LLVMValueRef persp_center
[2];
7665 /* Read PERSP_CENTER. */
7666 for (i
= 0; i
< 2; i
++)
7667 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7668 /* Overwrite PERSP_SAMPLE. */
7669 for (i
= 0; i
< 2; i
++)
7670 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7671 persp_center
[i
], base
+ i
, "");
7672 /* Overwrite PERSP_CENTROID. */
7673 for (i
= 0; i
< 2; i
++)
7674 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7675 persp_center
[i
], base
+ 4 + i
, "");
7677 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7678 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7679 LLVMValueRef linear_center
[2];
7681 /* Read LINEAR_CENTER. */
7682 for (i
= 0; i
< 2; i
++)
7683 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7684 /* Overwrite LINEAR_SAMPLE. */
7685 for (i
= 0; i
< 2; i
++)
7686 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7687 linear_center
[i
], base
+ 6 + i
, "");
7688 /* Overwrite LINEAR_CENTROID. */
7689 for (i
= 0; i
< 2; i
++)
7690 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7691 linear_center
[i
], base
+ 10 + i
, "");
7694 /* Interpolate colors. */
7695 unsigned color_out_idx
= 0;
7696 for (i
= 0; i
< 2; i
++) {
7697 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7698 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7699 key
->ps_prolog
.face_vgpr_index
;
7700 LLVMValueRef interp
[2], color
[4];
7701 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7706 /* If the interpolation qualifier is not CONSTANT (-1). */
7707 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7708 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7709 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7711 /* Get the (i,j) updated by bc_optimize handling. */
7712 interp
[0] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7714 interp
[1] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7715 interp_vgpr
+ 1, "");
7716 interp_ij
= ac_build_gather_values(&ctx
->ac
, interp
, 2);
7719 /* Use the absolute location of the input. */
7720 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7722 if (key
->ps_prolog
.states
.color_two_side
) {
7723 face
= LLVMGetParam(func
, face_vgpr
);
7724 face
= ac_to_integer(&ctx
->ac
, face
);
7727 interp_fs_input(ctx
,
7728 key
->ps_prolog
.color_attr_index
[i
],
7729 TGSI_SEMANTIC_COLOR
, i
,
7730 key
->ps_prolog
.num_interp_inputs
,
7731 key
->ps_prolog
.colors_read
, interp_ij
,
7732 prim_mask
, face
, color
);
7735 unsigned chan
= u_bit_scan(&writemask
);
7736 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, color
[chan
],
7737 fninfo
.num_params
+ color_out_idx
++, "");
7741 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7744 * "When per-sample shading is active due to the use of a fragment
7745 * input qualified by sample or due to the use of the gl_SampleID
7746 * or gl_SamplePosition variables, only the bit for the current
7747 * sample is set in gl_SampleMaskIn. When state specifies multiple
7748 * fragment shader invocations for a given fragment, the sample
7749 * mask for any single fragment shader invocation may specify a
7750 * subset of the covered samples for the fragment. In this case,
7751 * the bit corresponding to each covered sample will be set in
7752 * exactly one fragment shader invocation."
7754 * The samplemask loaded by hardware is always the coverage of the
7755 * entire pixel/fragment, so mask bits out based on the sample ID.
7757 if (key
->ps_prolog
.states
.samplemask_log_ps_iter
) {
7758 /* The bit pattern matches that used by fixed function fragment
7760 static const uint16_t ps_iter_masks
[] = {
7761 0xffff, /* not used */
7767 assert(key
->ps_prolog
.states
.samplemask_log_ps_iter
< ARRAY_SIZE(ps_iter_masks
));
7769 uint32_t ps_iter_mask
= ps_iter_masks
[key
->ps_prolog
.states
.samplemask_log_ps_iter
];
7770 unsigned ancillary_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7771 key
->ps_prolog
.ancillary_vgpr_index
;
7772 LLVMValueRef sampleid
= si_unpack_param(ctx
, ancillary_vgpr
, 8, 4);
7773 LLVMValueRef samplemask
= LLVMGetParam(func
, ancillary_vgpr
+ 1);
7775 samplemask
= ac_to_integer(&ctx
->ac
, samplemask
);
7776 samplemask
= LLVMBuildAnd(
7779 LLVMBuildShl(ctx
->ac
.builder
,
7780 LLVMConstInt(ctx
->i32
, ps_iter_mask
, false),
7783 samplemask
= ac_to_float(&ctx
->ac
, samplemask
);
7785 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, samplemask
,
7786 ancillary_vgpr
+ 1, "");
7789 /* Tell LLVM to insert WQM instruction sequence when needed. */
7790 if (key
->ps_prolog
.wqm
) {
7791 LLVMAddTargetDependentFunctionAttr(func
,
7792 "amdgpu-ps-wqm-outputs", "");
7795 si_llvm_build_ret(ctx
, ret
);
7799 * Build the pixel shader epilog function. This handles everything that must be
7800 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7802 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
7803 union si_shader_part_key
*key
)
7805 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7806 struct si_function_info fninfo
;
7807 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7809 struct si_ps_exports exp
= {};
7811 si_init_function_info(&fninfo
);
7813 /* Declare input SGPRs. */
7814 ctx
->param_rw_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7815 ctx
->param_bindless_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7816 ctx
->param_const_and_shader_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7817 ctx
->param_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7818 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
7820 /* Declare input VGPRs. */
7821 unsigned required_num_params
=
7822 fninfo
.num_sgpr_params
+
7823 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7824 key
->ps_epilog
.writes_z
+
7825 key
->ps_epilog
.writes_stencil
+
7826 key
->ps_epilog
.writes_samplemask
;
7828 required_num_params
= MAX2(required_num_params
,
7829 fninfo
.num_sgpr_params
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7831 while (fninfo
.num_params
< required_num_params
)
7832 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7834 /* Create the function. */
7835 si_create_function(ctx
, "ps_epilog", NULL
, 0, &fninfo
, 0);
7836 /* Disable elimination of unused inputs. */
7837 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
7838 "InitialPSInputAddr", 0xffffff);
7840 /* Process colors. */
7841 unsigned vgpr
= fninfo
.num_sgpr_params
;
7842 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7843 int last_color_export
= -1;
7845 /* Find the last color export. */
7846 if (!key
->ps_epilog
.writes_z
&&
7847 !key
->ps_epilog
.writes_stencil
&&
7848 !key
->ps_epilog
.writes_samplemask
) {
7849 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7851 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7852 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7853 /* Just set this if any of the colorbuffers are enabled. */
7855 ((1ull << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7856 last_color_export
= 0;
7858 for (i
= 0; i
< 8; i
++)
7859 if (colors_written
& (1 << i
) &&
7860 (spi_format
>> (i
* 4)) & 0xf)
7861 last_color_export
= i
;
7865 while (colors_written
) {
7866 LLVMValueRef color
[4];
7867 int mrt
= u_bit_scan(&colors_written
);
7869 for (i
= 0; i
< 4; i
++)
7870 color
[i
] = LLVMGetParam(ctx
->main_fn
, vgpr
++);
7872 si_export_mrt_color(bld_base
, color
, mrt
,
7873 fninfo
.num_params
- 1,
7874 mrt
== last_color_export
, &exp
);
7877 /* Process depth, stencil, samplemask. */
7878 if (key
->ps_epilog
.writes_z
)
7879 depth
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7880 if (key
->ps_epilog
.writes_stencil
)
7881 stencil
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7882 if (key
->ps_epilog
.writes_samplemask
)
7883 samplemask
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7885 if (depth
|| stencil
|| samplemask
)
7886 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7887 else if (last_color_export
== -1)
7888 ac_build_export_null(&ctx
->ac
);
7891 si_emit_ps_exports(ctx
, &exp
);
7894 LLVMBuildRetVoid(ctx
->ac
.builder
);
7898 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7900 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7901 struct si_compiler
*compiler
,
7902 struct si_shader
*shader
,
7903 struct pipe_debug_callback
*debug
)
7905 union si_shader_part_key prolog_key
;
7906 union si_shader_part_key epilog_key
;
7908 /* Get the prolog. */
7909 si_get_ps_prolog_key(shader
, &prolog_key
, true);
7911 /* The prolog is a no-op if these aren't set. */
7912 if (si_need_ps_prolog(&prolog_key
)) {
7914 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7915 PIPE_SHADER_FRAGMENT
, true,
7916 &prolog_key
, compiler
, debug
,
7917 si_build_ps_prolog_function
,
7918 "Fragment Shader Prolog");
7919 if (!shader
->prolog
)
7923 /* Get the epilog. */
7924 si_get_ps_epilog_key(shader
, &epilog_key
);
7927 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7928 PIPE_SHADER_FRAGMENT
, false,
7929 &epilog_key
, compiler
, debug
,
7930 si_build_ps_epilog_function
,
7931 "Fragment Shader Epilog");
7932 if (!shader
->epilog
)
7935 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7936 if (shader
->key
.part
.ps
.prolog
.poly_stipple
) {
7937 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7938 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7941 /* Set up the enable bits for per-sample shading if needed. */
7942 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
&&
7943 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7944 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7945 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7946 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7947 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7949 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
&&
7950 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7951 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7952 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7953 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7954 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7956 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
&&
7957 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7958 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7959 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7960 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7961 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7963 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
&&
7964 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7965 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7966 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7967 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7968 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7971 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7972 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7973 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7974 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7975 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7978 /* At least one pair of interpolation weights must be enabled. */
7979 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7980 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7981 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7984 /* Samplemask fixup requires the sample ID. */
7985 if (shader
->key
.part
.ps
.prolog
.samplemask_log_ps_iter
) {
7986 shader
->config
.spi_ps_input_ena
|= S_0286CC_ANCILLARY_ENA(1);
7987 assert(G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
));
7990 /* The sample mask input is always enabled, because the API shader always
7991 * passes it through to the epilog. Disable it here if it's unused.
7993 if (!shader
->key
.part
.ps
.epilog
.poly_line_smoothing
&&
7994 !shader
->selector
->info
.reads_samplemask
)
7995 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
8000 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
8003 /* If tessellation is all offchip and on-chip GS isn't used, this
8004 * workaround is not needed.
8008 /* SPI barrier management bug:
8009 * Make sure we have at least 4k of LDS in use to avoid the bug.
8010 * It applies to workgroup sizes of more than one wavefront.
8012 if (sscreen
->info
.family
== CHIP_BONAIRE
||
8013 sscreen
->info
.family
== CHIP_KABINI
||
8014 sscreen
->info
.family
== CHIP_MULLINS
)
8015 *lds_size
= MAX2(*lds_size
, 8);
8018 static void si_fix_resource_usage(struct si_screen
*sscreen
,
8019 struct si_shader
*shader
)
8021 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
8023 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
8025 if (shader
->selector
->type
== PIPE_SHADER_COMPUTE
&&
8026 si_get_max_workgroup_size(shader
) > 64) {
8027 si_multiwave_lds_size_workaround(sscreen
,
8028 &shader
->config
.lds_size
);
8032 int si_shader_create(struct si_screen
*sscreen
, struct si_compiler
*compiler
,
8033 struct si_shader
*shader
,
8034 struct pipe_debug_callback
*debug
)
8036 struct si_shader_selector
*sel
= shader
->selector
;
8037 struct si_shader
*mainp
= *si_get_main_shader_part(sel
, &shader
->key
);
8040 /* LS, ES, VS are compiled on demand if the main part hasn't been
8041 * compiled for that stage.
8043 * Vertex shaders are compiled on demand when a vertex fetch
8044 * workaround must be applied.
8046 if (shader
->is_monolithic
) {
8047 /* Monolithic shader (compiled as a whole, has many variants,
8048 * may take a long time to compile).
8050 r
= si_compile_tgsi_shader(sscreen
, compiler
, shader
, debug
);
8054 /* The shader consists of several parts:
8056 * - the middle part is the user shader, it has 1 variant only
8057 * and it was compiled during the creation of the shader
8059 * - the prolog part is inserted at the beginning
8060 * - the epilog part is inserted at the end
8062 * The prolog and epilog have many (but simple) variants.
8064 * Starting with gfx9, geometry and tessellation control
8065 * shaders also contain the prolog and user shader parts of
8066 * the previous shader stage.
8072 /* Copy the compiled TGSI shader data over. */
8073 shader
->is_binary_shared
= true;
8074 shader
->binary
= mainp
->binary
;
8075 shader
->config
= mainp
->config
;
8076 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
8077 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
8078 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
8079 shader
->info
.ancillary_vgpr_index
= mainp
->info
.ancillary_vgpr_index
;
8080 memcpy(shader
->info
.vs_output_param_offset
,
8081 mainp
->info
.vs_output_param_offset
,
8082 sizeof(mainp
->info
.vs_output_param_offset
));
8083 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
8084 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
8085 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
8087 /* Select prologs and/or epilogs. */
8088 switch (sel
->type
) {
8089 case PIPE_SHADER_VERTEX
:
8090 if (!si_shader_select_vs_parts(sscreen
, compiler
, shader
, debug
))
8093 case PIPE_SHADER_TESS_CTRL
:
8094 if (!si_shader_select_tcs_parts(sscreen
, compiler
, shader
, debug
))
8097 case PIPE_SHADER_TESS_EVAL
:
8099 case PIPE_SHADER_GEOMETRY
:
8100 if (!si_shader_select_gs_parts(sscreen
, compiler
, shader
, debug
))
8103 case PIPE_SHADER_FRAGMENT
:
8104 if (!si_shader_select_ps_parts(sscreen
, compiler
, shader
, debug
))
8107 /* Make sure we have at least as many VGPRs as there
8108 * are allocated inputs.
8110 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8111 shader
->info
.num_input_vgprs
);
8115 /* Update SGPR and VGPR counts. */
8116 if (shader
->prolog
) {
8117 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8118 shader
->prolog
->config
.num_sgprs
);
8119 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8120 shader
->prolog
->config
.num_vgprs
);
8122 if (shader
->previous_stage
) {
8123 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8124 shader
->previous_stage
->config
.num_sgprs
);
8125 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8126 shader
->previous_stage
->config
.num_vgprs
);
8127 shader
->config
.spilled_sgprs
=
8128 MAX2(shader
->config
.spilled_sgprs
,
8129 shader
->previous_stage
->config
.spilled_sgprs
);
8130 shader
->config
.spilled_vgprs
=
8131 MAX2(shader
->config
.spilled_vgprs
,
8132 shader
->previous_stage
->config
.spilled_vgprs
);
8133 shader
->config
.private_mem_vgprs
=
8134 MAX2(shader
->config
.private_mem_vgprs
,
8135 shader
->previous_stage
->config
.private_mem_vgprs
);
8136 shader
->config
.scratch_bytes_per_wave
=
8137 MAX2(shader
->config
.scratch_bytes_per_wave
,
8138 shader
->previous_stage
->config
.scratch_bytes_per_wave
);
8139 shader
->info
.uses_instanceid
|=
8140 shader
->previous_stage
->info
.uses_instanceid
;
8142 if (shader
->prolog2
) {
8143 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8144 shader
->prolog2
->config
.num_sgprs
);
8145 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8146 shader
->prolog2
->config
.num_vgprs
);
8148 if (shader
->epilog
) {
8149 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8150 shader
->epilog
->config
.num_sgprs
);
8151 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8152 shader
->epilog
->config
.num_vgprs
);
8154 si_calculate_max_simd_waves(shader
);
8157 si_fix_resource_usage(sscreen
, shader
);
8158 si_shader_dump(sscreen
, shader
, debug
, sel
->info
.processor
,
8162 r
= si_shader_binary_upload(sscreen
, shader
);
8164 fprintf(stderr
, "LLVM failed to upload shader\n");
8171 void si_shader_destroy(struct si_shader
*shader
)
8173 if (shader
->scratch_bo
)
8174 r600_resource_reference(&shader
->scratch_bo
, NULL
);
8176 r600_resource_reference(&shader
->bo
, NULL
);
8178 if (!shader
->is_binary_shared
)
8179 ac_shader_binary_clean(&shader
->binary
);
8181 free(shader
->shader_log
);