2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_util.h"
29 #include "tgsi/tgsi_dump.h"
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_llvm_util.h"
34 #include "si_shader_internal.h"
38 #include "compiler/nir/nir.h"
40 static const char *scratch_rsrc_dword0_symbol
=
41 "SCRATCH_RSRC_DWORD0";
43 static const char *scratch_rsrc_dword1_symbol
=
44 "SCRATCH_RSRC_DWORD1";
46 struct si_shader_output_values
48 LLVMValueRef values
[4];
49 unsigned semantic_name
;
50 unsigned semantic_index
;
51 ubyte vertex_stream
[4];
55 * Used to collect types and other info about arguments of the LLVM function
56 * before the function is created.
58 struct si_function_info
{
59 LLVMTypeRef types
[100];
60 LLVMValueRef
*assign
[100];
61 unsigned num_sgpr_params
;
70 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
71 struct si_screen
*sscreen
,
72 struct si_compiler
*compiler
);
74 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
75 struct lp_build_tgsi_context
*bld_base
,
76 struct lp_build_emit_data
*emit_data
);
78 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
81 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
82 union si_shader_part_key
*key
);
83 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
84 union si_shader_part_key
*key
);
85 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
86 union si_shader_part_key
*key
);
87 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
88 union si_shader_part_key
*key
);
90 /* Ideally pass the sample mask input to the PS epilog as v14, which
91 * is its usual location, so that the shader doesn't have to add v_mov.
93 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
95 static bool llvm_type_is_64bit(struct si_shader_context
*ctx
,
98 if (type
== ctx
->ac
.i64
|| type
== ctx
->ac
.f64
)
104 static bool is_merged_shader(struct si_shader
*shader
)
106 if (shader
->selector
->screen
->info
.chip_class
<= VI
)
109 return shader
->key
.as_ls
||
111 shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
||
112 shader
->selector
->type
== PIPE_SHADER_GEOMETRY
;
115 static void si_init_function_info(struct si_function_info
*fninfo
)
117 fninfo
->num_params
= 0;
118 fninfo
->num_sgpr_params
= 0;
121 static unsigned add_arg_assign(struct si_function_info
*fninfo
,
122 enum si_arg_regfile regfile
, LLVMTypeRef type
,
123 LLVMValueRef
*assign
)
125 assert(regfile
!= ARG_SGPR
|| fninfo
->num_sgpr_params
== fninfo
->num_params
);
127 unsigned idx
= fninfo
->num_params
++;
128 assert(idx
< ARRAY_SIZE(fninfo
->types
));
130 if (regfile
== ARG_SGPR
)
131 fninfo
->num_sgpr_params
= fninfo
->num_params
;
133 fninfo
->types
[idx
] = type
;
134 fninfo
->assign
[idx
] = assign
;
138 static unsigned add_arg(struct si_function_info
*fninfo
,
139 enum si_arg_regfile regfile
, LLVMTypeRef type
)
141 return add_arg_assign(fninfo
, regfile
, type
, NULL
);
144 static void add_arg_assign_checked(struct si_function_info
*fninfo
,
145 enum si_arg_regfile regfile
, LLVMTypeRef type
,
146 LLVMValueRef
*assign
, unsigned idx
)
148 MAYBE_UNUSED
unsigned actual
= add_arg_assign(fninfo
, regfile
, type
, assign
);
149 assert(actual
== idx
);
152 static void add_arg_checked(struct si_function_info
*fninfo
,
153 enum si_arg_regfile regfile
, LLVMTypeRef type
,
156 add_arg_assign_checked(fninfo
, regfile
, type
, NULL
, idx
);
160 * Returns a unique index for a per-patch semantic name and index. The index
161 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name
, unsigned index
)
166 switch (semantic_name
) {
167 case TGSI_SEMANTIC_TESSOUTER
:
169 case TGSI_SEMANTIC_TESSINNER
:
171 case TGSI_SEMANTIC_PATCH
:
176 assert(!"invalid semantic name");
182 * Returns a unique index for a semantic name and index. The index must be
183 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
,
189 switch (semantic_name
) {
190 case TGSI_SEMANTIC_POSITION
:
192 case TGSI_SEMANTIC_GENERIC
:
193 /* Since some shader stages use the the highest used IO index
194 * to determine the size to allocate for inputs/outputs
195 * (in LDS, tess and GS rings). GENERIC should be placed right
196 * after POSITION to make that size as small as possible.
198 if (index
< SI_MAX_IO_GENERIC
)
201 assert(!"invalid generic index");
203 case TGSI_SEMANTIC_PSIZE
:
204 return SI_MAX_IO_GENERIC
+ 1;
205 case TGSI_SEMANTIC_CLIPDIST
:
207 return SI_MAX_IO_GENERIC
+ 2 + index
;
208 case TGSI_SEMANTIC_FOG
:
209 return SI_MAX_IO_GENERIC
+ 4;
210 case TGSI_SEMANTIC_LAYER
:
211 return SI_MAX_IO_GENERIC
+ 5;
212 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
213 return SI_MAX_IO_GENERIC
+ 6;
214 case TGSI_SEMANTIC_PRIMID
:
215 return SI_MAX_IO_GENERIC
+ 7;
216 case TGSI_SEMANTIC_COLOR
:
218 return SI_MAX_IO_GENERIC
+ 8 + index
;
219 case TGSI_SEMANTIC_BCOLOR
:
221 /* If it's a varying, COLOR and BCOLOR alias. */
223 return SI_MAX_IO_GENERIC
+ 8 + index
;
225 return SI_MAX_IO_GENERIC
+ 10 + index
;
226 case TGSI_SEMANTIC_TEXCOORD
:
228 STATIC_ASSERT(SI_MAX_IO_GENERIC
+ 12 + 8 <= 63);
229 return SI_MAX_IO_GENERIC
+ 12 + index
;
230 case TGSI_SEMANTIC_CLIPVERTEX
:
233 fprintf(stderr
, "invalid semantic name = %u\n", semantic_name
);
234 assert(!"invalid semantic name");
240 * Get the value of a shader input parameter and extract a bitfield.
242 static LLVMValueRef
unpack_llvm_param(struct si_shader_context
*ctx
,
243 LLVMValueRef value
, unsigned rshift
,
246 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMFloatTypeKind
)
247 value
= ac_to_integer(&ctx
->ac
, value
);
250 value
= LLVMBuildLShr(ctx
->ac
.builder
, value
,
251 LLVMConstInt(ctx
->i32
, rshift
, 0), "");
253 if (rshift
+ bitwidth
< 32) {
254 unsigned mask
= (1 << bitwidth
) - 1;
255 value
= LLVMBuildAnd(ctx
->ac
.builder
, value
,
256 LLVMConstInt(ctx
->i32
, mask
, 0), "");
262 LLVMValueRef
si_unpack_param(struct si_shader_context
*ctx
,
263 unsigned param
, unsigned rshift
,
266 LLVMValueRef value
= LLVMGetParam(ctx
->main_fn
, param
);
268 return unpack_llvm_param(ctx
, value
, rshift
, bitwidth
);
271 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*ctx
)
274 case PIPE_SHADER_TESS_CTRL
:
275 return unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 0, 8);
277 case PIPE_SHADER_TESS_EVAL
:
278 return LLVMGetParam(ctx
->main_fn
,
279 ctx
->param_tes_rel_patch_id
);
287 /* Tessellation shaders pass outputs to the next shader using LDS.
289 * LS outputs = TCS inputs
290 * TCS outputs = TES inputs
293 * - TCS inputs for patch 0
294 * - TCS inputs for patch 1
295 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
297 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
298 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
299 * - TCS outputs for patch 1
300 * - Per-patch TCS outputs for patch 1
301 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
302 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * All three shaders VS(LS), TCS, TES share the same LDS space.
309 get_tcs_in_patch_stride(struct si_shader_context
*ctx
)
311 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 8, 13);
314 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context
*ctx
)
316 assert(ctx
->type
== PIPE_SHADER_TESS_CTRL
);
318 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
319 return util_last_bit64(ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
) * 4;
321 return util_last_bit64(ctx
->shader
->selector
->outputs_written
) * 4;
324 static LLVMValueRef
get_tcs_out_vertex_dw_stride(struct si_shader_context
*ctx
)
326 unsigned stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
328 return LLVMConstInt(ctx
->i32
, stride
, 0);
331 static LLVMValueRef
get_tcs_out_patch_stride(struct si_shader_context
*ctx
)
333 if (ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
)
334 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 0, 13);
336 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
337 unsigned tcs_out_vertices
= info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
338 unsigned vertex_dw_stride
= get_tcs_out_vertex_dw_stride_constant(ctx
);
339 unsigned num_patch_outputs
= util_last_bit64(ctx
->shader
->selector
->patch_outputs_written
);
340 unsigned patch_dw_stride
= tcs_out_vertices
* vertex_dw_stride
+
341 num_patch_outputs
* 4;
342 return LLVMConstInt(ctx
->i32
, patch_dw_stride
, 0);
346 get_tcs_out_patch0_offset(struct si_shader_context
*ctx
)
348 return LLVMBuildMul(ctx
->ac
.builder
,
350 ctx
->param_tcs_out_lds_offsets
,
352 LLVMConstInt(ctx
->i32
, 4, 0), "");
356 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*ctx
)
358 return LLVMBuildMul(ctx
->ac
.builder
,
360 ctx
->param_tcs_out_lds_offsets
,
362 LLVMConstInt(ctx
->i32
, 4, 0), "");
366 get_tcs_in_current_patch_offset(struct si_shader_context
*ctx
)
368 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
369 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
371 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
375 get_tcs_out_current_patch_offset(struct si_shader_context
*ctx
)
377 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
378 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
379 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
381 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
382 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
388 get_tcs_out_current_patch_data_offset(struct si_shader_context
*ctx
)
390 LLVMValueRef patch0_patch_data_offset
=
391 get_tcs_out_patch0_patch_data_offset(ctx
);
392 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
393 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
395 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
396 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
401 static LLVMValueRef
get_num_tcs_out_vertices(struct si_shader_context
*ctx
)
403 unsigned tcs_out_vertices
=
404 ctx
->shader
->selector
?
405 ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] : 0;
407 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
408 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& tcs_out_vertices
)
409 return LLVMConstInt(ctx
->i32
, tcs_out_vertices
, 0);
411 return si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 6, 6);
414 static LLVMValueRef
get_tcs_in_vertex_dw_stride(struct si_shader_context
*ctx
)
419 case PIPE_SHADER_VERTEX
:
420 stride
= util_last_bit64(ctx
->shader
->selector
->outputs_written
);
421 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
423 case PIPE_SHADER_TESS_CTRL
:
424 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
425 ctx
->shader
->is_monolithic
) {
426 stride
= util_last_bit64(ctx
->shader
->key
.part
.tcs
.ls
->outputs_written
);
427 return LLVMConstInt(ctx
->i32
, stride
* 4, 0);
429 return si_unpack_param(ctx
, ctx
->param_vs_state_bits
, 24, 8);
437 static LLVMValueRef
get_instance_index_for_fetch(
438 struct si_shader_context
*ctx
,
439 unsigned param_start_instance
, LLVMValueRef divisor
)
441 LLVMValueRef result
= ctx
->abi
.instance_id
;
443 /* The division must be done before START_INSTANCE is added. */
444 if (divisor
!= ctx
->i32_1
)
445 result
= LLVMBuildUDiv(ctx
->ac
.builder
, result
, divisor
, "");
447 return LLVMBuildAdd(ctx
->ac
.builder
, result
,
448 LLVMGetParam(ctx
->main_fn
, param_start_instance
), "");
451 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
453 static LLVMValueRef
extract_double_to_float(struct si_shader_context
*ctx
,
455 unsigned double_index
)
457 LLVMBuilderRef builder
= ctx
->ac
.builder
;
458 LLVMTypeRef f64
= LLVMDoubleTypeInContext(ctx
->ac
.context
);
459 LLVMValueRef dvec2
= LLVMBuildBitCast(builder
, vec4
,
460 LLVMVectorType(f64
, 2), "");
461 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, double_index
, 0);
462 LLVMValueRef value
= LLVMBuildExtractElement(builder
, dvec2
, index
, "");
463 return LLVMBuildFPTrunc(builder
, value
, ctx
->f32
, "");
466 static LLVMValueRef
unpack_sint16(struct si_shader_context
*ctx
,
467 LLVMValueRef i32
, unsigned index
)
472 return LLVMBuildAShr(ctx
->ac
.builder
, i32
,
473 LLVMConstInt(ctx
->i32
, 16, 0), "");
475 return LLVMBuildSExt(ctx
->ac
.builder
,
476 LLVMBuildTrunc(ctx
->ac
.builder
, i32
,
481 void si_llvm_load_input_vs(
482 struct si_shader_context
*ctx
,
483 unsigned input_index
,
486 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
487 unsigned vs_blit_property
= info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
489 if (vs_blit_property
) {
490 LLVMValueRef vertex_id
= ctx
->abi
.vertex_id
;
491 LLVMValueRef sel_x1
= LLVMBuildICmp(ctx
->ac
.builder
,
492 LLVMIntULE
, vertex_id
,
494 /* Use LLVMIntNE, because we have 3 vertices and only
495 * the middle one should use y2.
497 LLVMValueRef sel_y1
= LLVMBuildICmp(ctx
->ac
.builder
,
498 LLVMIntNE
, vertex_id
,
501 if (input_index
== 0) {
503 LLVMValueRef x1y1
= LLVMGetParam(ctx
->main_fn
,
504 ctx
->param_vs_blit_inputs
);
505 LLVMValueRef x2y2
= LLVMGetParam(ctx
->main_fn
,
506 ctx
->param_vs_blit_inputs
+ 1);
508 LLVMValueRef x1
= unpack_sint16(ctx
, x1y1
, 0);
509 LLVMValueRef y1
= unpack_sint16(ctx
, x1y1
, 1);
510 LLVMValueRef x2
= unpack_sint16(ctx
, x2y2
, 0);
511 LLVMValueRef y2
= unpack_sint16(ctx
, x2y2
, 1);
513 LLVMValueRef x
= LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
515 LLVMValueRef y
= LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
518 out
[0] = LLVMBuildSIToFP(ctx
->ac
.builder
, x
, ctx
->f32
, "");
519 out
[1] = LLVMBuildSIToFP(ctx
->ac
.builder
, y
, ctx
->f32
, "");
520 out
[2] = LLVMGetParam(ctx
->main_fn
,
521 ctx
->param_vs_blit_inputs
+ 2);
522 out
[3] = ctx
->ac
.f32_1
;
526 /* Color or texture coordinates: */
527 assert(input_index
== 1);
529 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
530 for (int i
= 0; i
< 4; i
++) {
531 out
[i
] = LLVMGetParam(ctx
->main_fn
,
532 ctx
->param_vs_blit_inputs
+ 3 + i
);
535 assert(vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
);
536 LLVMValueRef x1
= LLVMGetParam(ctx
->main_fn
,
537 ctx
->param_vs_blit_inputs
+ 3);
538 LLVMValueRef y1
= LLVMGetParam(ctx
->main_fn
,
539 ctx
->param_vs_blit_inputs
+ 4);
540 LLVMValueRef x2
= LLVMGetParam(ctx
->main_fn
,
541 ctx
->param_vs_blit_inputs
+ 5);
542 LLVMValueRef y2
= LLVMGetParam(ctx
->main_fn
,
543 ctx
->param_vs_blit_inputs
+ 6);
545 out
[0] = LLVMBuildSelect(ctx
->ac
.builder
, sel_x1
,
547 out
[1] = LLVMBuildSelect(ctx
->ac
.builder
, sel_y1
,
549 out
[2] = LLVMGetParam(ctx
->main_fn
,
550 ctx
->param_vs_blit_inputs
+ 7);
551 out
[3] = LLVMGetParam(ctx
->main_fn
,
552 ctx
->param_vs_blit_inputs
+ 8);
559 unsigned num_fetches
;
560 unsigned fetch_stride
;
561 unsigned num_channels
;
563 LLVMValueRef t_list_ptr
;
564 LLVMValueRef t_offset
;
566 LLVMValueRef vertex_index
;
567 LLVMValueRef input
[3];
569 /* Load the T list */
570 t_list_ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_vertex_buffers
);
572 t_offset
= LLVMConstInt(ctx
->i32
, input_index
, 0);
574 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
576 vertex_index
= LLVMGetParam(ctx
->main_fn
,
577 ctx
->param_vertex_index0
+
580 fix_fetch
= ctx
->shader
->key
.mono
.vs_fix_fetch
[input_index
];
582 /* Do multiple loads for special formats. */
584 case SI_FIX_FETCH_RGB_64_FLOAT
:
585 num_fetches
= 3; /* 3 2-dword loads */
589 case SI_FIX_FETCH_RGBA_64_FLOAT
:
590 num_fetches
= 2; /* 2 4-dword loads */
594 case SI_FIX_FETCH_RGB_8
:
595 case SI_FIX_FETCH_RGB_8_INT
:
600 case SI_FIX_FETCH_RGB_16
:
601 case SI_FIX_FETCH_RGB_16_INT
:
609 num_channels
= util_last_bit(info
->input_usage_mask
[input_index
]);
612 for (unsigned i
= 0; i
< num_fetches
; i
++) {
613 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, fetch_stride
* i
, 0);
615 input
[i
] = ac_build_buffer_load_format(&ctx
->ac
, t_list
,
616 vertex_index
, voffset
,
617 num_channels
, false, true);
618 input
[i
] = ac_build_expand_to_vec4(&ctx
->ac
, input
[i
], num_channels
);
621 /* Break up the vec4 into individual components */
622 for (chan
= 0; chan
< 4; chan
++) {
623 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, 0);
624 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
625 input
[0], llvm_chan
, "");
629 case SI_FIX_FETCH_A2_SNORM
:
630 case SI_FIX_FETCH_A2_SSCALED
:
631 case SI_FIX_FETCH_A2_SINT
: {
632 /* The hardware returns an unsigned value; convert it to a
635 LLVMValueRef tmp
= out
[3];
636 LLVMValueRef c30
= LLVMConstInt(ctx
->i32
, 30, 0);
638 /* First, recover the sign-extended signed integer value. */
639 if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
)
640 tmp
= LLVMBuildFPToUI(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
642 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
644 /* For the integer-like cases, do a natural sign extension.
646 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
647 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
650 tmp
= LLVMBuildShl(ctx
->ac
.builder
, tmp
,
651 fix_fetch
== SI_FIX_FETCH_A2_SNORM
?
652 LLVMConstInt(ctx
->i32
, 7, 0) : c30
, "");
653 tmp
= LLVMBuildAShr(ctx
->ac
.builder
, tmp
, c30
, "");
655 /* Convert back to the right type. */
656 if (fix_fetch
== SI_FIX_FETCH_A2_SNORM
) {
658 LLVMValueRef neg_one
= LLVMConstReal(ctx
->f32
, -1.0);
659 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
660 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, tmp
, neg_one
, "");
661 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, tmp
, "");
662 } else if (fix_fetch
== SI_FIX_FETCH_A2_SSCALED
) {
663 tmp
= LLVMBuildSIToFP(ctx
->ac
.builder
, tmp
, ctx
->f32
, "");
669 case SI_FIX_FETCH_RGBA_32_UNORM
:
670 case SI_FIX_FETCH_RGBX_32_UNORM
:
671 for (chan
= 0; chan
< 4; chan
++) {
672 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
673 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
674 out
[chan
], ctx
->f32
, "");
675 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
676 LLVMConstReal(ctx
->f32
, 1.0 / UINT_MAX
), "");
678 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
679 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_UNORM
)
680 out
[3] = LLVMConstReal(ctx
->f32
, 1);
682 case SI_FIX_FETCH_RGBA_32_SNORM
:
683 case SI_FIX_FETCH_RGBX_32_SNORM
:
684 case SI_FIX_FETCH_RGBA_32_FIXED
:
685 case SI_FIX_FETCH_RGBX_32_FIXED
: {
687 if (fix_fetch
>= SI_FIX_FETCH_RGBA_32_FIXED
)
688 scale
= 1.0 / 0x10000;
690 scale
= 1.0 / INT_MAX
;
692 for (chan
= 0; chan
< 4; chan
++) {
693 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
694 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
695 out
[chan
], ctx
->f32
, "");
696 out
[chan
] = LLVMBuildFMul(ctx
->ac
.builder
, out
[chan
],
697 LLVMConstReal(ctx
->f32
, scale
), "");
699 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
700 if (fix_fetch
== SI_FIX_FETCH_RGBX_32_SNORM
||
701 fix_fetch
== SI_FIX_FETCH_RGBX_32_FIXED
)
702 out
[3] = LLVMConstReal(ctx
->f32
, 1);
705 case SI_FIX_FETCH_RGBA_32_USCALED
:
706 for (chan
= 0; chan
< 4; chan
++) {
707 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
708 out
[chan
] = LLVMBuildUIToFP(ctx
->ac
.builder
,
709 out
[chan
], ctx
->f32
, "");
712 case SI_FIX_FETCH_RGBA_32_SSCALED
:
713 for (chan
= 0; chan
< 4; chan
++) {
714 out
[chan
] = ac_to_integer(&ctx
->ac
, out
[chan
]);
715 out
[chan
] = LLVMBuildSIToFP(ctx
->ac
.builder
,
716 out
[chan
], ctx
->f32
, "");
719 case SI_FIX_FETCH_RG_64_FLOAT
:
720 for (chan
= 0; chan
< 2; chan
++)
721 out
[chan
] = extract_double_to_float(ctx
, input
[0], chan
);
723 out
[2] = LLVMConstReal(ctx
->f32
, 0);
724 out
[3] = LLVMConstReal(ctx
->f32
, 1);
726 case SI_FIX_FETCH_RGB_64_FLOAT
:
727 for (chan
= 0; chan
< 3; chan
++)
728 out
[chan
] = extract_double_to_float(ctx
, input
[chan
], 0);
730 out
[3] = LLVMConstReal(ctx
->f32
, 1);
732 case SI_FIX_FETCH_RGBA_64_FLOAT
:
733 for (chan
= 0; chan
< 4; chan
++) {
734 out
[chan
] = extract_double_to_float(ctx
, input
[chan
/ 2],
738 case SI_FIX_FETCH_RGB_8
:
739 case SI_FIX_FETCH_RGB_8_INT
:
740 case SI_FIX_FETCH_RGB_16
:
741 case SI_FIX_FETCH_RGB_16_INT
:
742 for (chan
= 0; chan
< 3; chan
++) {
743 out
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
747 if (fix_fetch
== SI_FIX_FETCH_RGB_8
||
748 fix_fetch
== SI_FIX_FETCH_RGB_16
) {
749 out
[3] = LLVMConstReal(ctx
->f32
, 1);
751 out
[3] = ac_to_float(&ctx
->ac
, ctx
->i32_1
);
757 static void declare_input_vs(
758 struct si_shader_context
*ctx
,
759 unsigned input_index
,
760 const struct tgsi_full_declaration
*decl
,
763 si_llvm_load_input_vs(ctx
, input_index
, out
);
766 static LLVMValueRef
get_primitive_id(struct si_shader_context
*ctx
,
773 case PIPE_SHADER_VERTEX
:
774 return LLVMGetParam(ctx
->main_fn
,
775 ctx
->param_vs_prim_id
);
776 case PIPE_SHADER_TESS_CTRL
:
777 return ctx
->abi
.tcs_patch_id
;
778 case PIPE_SHADER_TESS_EVAL
:
779 return ctx
->abi
.tes_patch_id
;
780 case PIPE_SHADER_GEOMETRY
:
781 return ctx
->abi
.gs_prim_id
;
789 * Return the value of tgsi_ind_register for indexing.
790 * This is the indirect index with the constant offset added to it.
792 LLVMValueRef
si_get_indirect_index(struct si_shader_context
*ctx
,
793 const struct tgsi_ind_register
*ind
,
799 if (ind
->File
== TGSI_FILE_ADDRESS
) {
800 result
= ctx
->addrs
[ind
->Index
][ind
->Swizzle
];
801 result
= LLVMBuildLoad(ctx
->ac
.builder
, result
, "");
803 struct tgsi_full_src_register src
= {};
805 src
.Register
.File
= ind
->File
;
806 src
.Register
.Index
= ind
->Index
;
808 /* Set the second index to 0 for constants. */
809 if (ind
->File
== TGSI_FILE_CONSTANT
)
810 src
.Register
.Dimension
= 1;
812 result
= ctx
->bld_base
.emit_fetch_funcs
[ind
->File
](&ctx
->bld_base
, &src
,
815 result
= ac_to_integer(&ctx
->ac
, result
);
819 result
= LLVMBuildMul(ctx
->ac
.builder
, result
,
820 LLVMConstInt(ctx
->i32
, addr_mul
, 0), "");
821 result
= LLVMBuildAdd(ctx
->ac
.builder
, result
,
822 LLVMConstInt(ctx
->i32
, rel_index
, 0), "");
827 * Like si_get_indirect_index, but restricts the return value to a (possibly
828 * undefined) value inside [0..num).
830 LLVMValueRef
si_get_bounded_indirect_index(struct si_shader_context
*ctx
,
831 const struct tgsi_ind_register
*ind
,
832 int rel_index
, unsigned num
)
834 LLVMValueRef result
= si_get_indirect_index(ctx
, ind
, 1, rel_index
);
836 return si_llvm_bound_index(ctx
, result
, num
);
839 static LLVMValueRef
get_dw_address_from_generic_indices(struct si_shader_context
*ctx
,
840 LLVMValueRef vertex_dw_stride
,
841 LLVMValueRef base_addr
,
842 LLVMValueRef vertex_index
,
843 LLVMValueRef param_index
,
844 unsigned input_index
,
849 if (vertex_dw_stride
) {
850 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
851 LLVMBuildMul(ctx
->ac
.builder
, vertex_index
,
852 vertex_dw_stride
, ""), "");
856 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
857 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
858 LLVMConstInt(ctx
->i32
, 4, 0), ""), "");
861 int param
= is_patch
?
862 si_shader_io_get_unique_index_patch(name
[input_index
],
863 index
[input_index
]) :
864 si_shader_io_get_unique_index(name
[input_index
],
865 index
[input_index
], false);
867 /* Add the base address of the element. */
868 return LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
869 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
873 * Calculate a dword address given an input or output register and a stride.
875 static LLVMValueRef
get_dw_address(struct si_shader_context
*ctx
,
876 const struct tgsi_full_dst_register
*dst
,
877 const struct tgsi_full_src_register
*src
,
878 LLVMValueRef vertex_dw_stride
,
879 LLVMValueRef base_addr
)
881 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
882 ubyte
*name
, *index
, *array_first
;
884 struct tgsi_full_dst_register reg
;
885 LLVMValueRef vertex_index
= NULL
;
886 LLVMValueRef ind_index
= NULL
;
888 /* Set the register description. The address computation is the same
889 * for sources and destinations. */
891 reg
.Register
.File
= src
->Register
.File
;
892 reg
.Register
.Index
= src
->Register
.Index
;
893 reg
.Register
.Indirect
= src
->Register
.Indirect
;
894 reg
.Register
.Dimension
= src
->Register
.Dimension
;
895 reg
.Indirect
= src
->Indirect
;
896 reg
.Dimension
= src
->Dimension
;
897 reg
.DimIndirect
= src
->DimIndirect
;
901 /* If the register is 2-dimensional (e.g. an array of vertices
902 * in a primitive), calculate the base address of the vertex. */
903 if (reg
.Register
.Dimension
) {
904 if (reg
.Dimension
.Indirect
)
905 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
906 1, reg
.Dimension
.Index
);
908 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
911 /* Get information about the register. */
912 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
913 name
= info
->input_semantic_name
;
914 index
= info
->input_semantic_index
;
915 array_first
= info
->input_array_first
;
916 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
917 name
= info
->output_semantic_name
;
918 index
= info
->output_semantic_index
;
919 array_first
= info
->output_array_first
;
925 if (reg
.Register
.Indirect
) {
926 /* Add the relative address of the element. */
927 if (reg
.Indirect
.ArrayID
)
928 input_index
= array_first
[reg
.Indirect
.ArrayID
];
930 input_index
= reg
.Register
.Index
;
932 ind_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
933 1, reg
.Register
.Index
- input_index
);
935 input_index
= reg
.Register
.Index
;
938 return get_dw_address_from_generic_indices(ctx
, vertex_dw_stride
,
939 base_addr
, vertex_index
,
940 ind_index
, input_index
,
942 !reg
.Register
.Dimension
);
945 /* The offchip buffer layout for TCS->TES is
947 * - attribute 0 of patch 0 vertex 0
948 * - attribute 0 of patch 0 vertex 1
949 * - attribute 0 of patch 0 vertex 2
951 * - attribute 0 of patch 1 vertex 0
952 * - attribute 0 of patch 1 vertex 1
954 * - attribute 1 of patch 0 vertex 0
955 * - attribute 1 of patch 0 vertex 1
957 * - per patch attribute 0 of patch 0
958 * - per patch attribute 0 of patch 1
961 * Note that every attribute has 4 components.
963 static LLVMValueRef
get_tcs_tes_buffer_address(struct si_shader_context
*ctx
,
964 LLVMValueRef rel_patch_id
,
965 LLVMValueRef vertex_index
,
966 LLVMValueRef param_index
)
968 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
969 LLVMValueRef param_stride
, constant16
;
971 vertices_per_patch
= get_num_tcs_out_vertices(ctx
);
972 num_patches
= si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 0, 6);
973 total_vertices
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
976 constant16
= LLVMConstInt(ctx
->i32
, 16, 0);
978 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
979 vertices_per_patch
, "");
981 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
984 param_stride
= total_vertices
;
986 base_addr
= rel_patch_id
;
987 param_stride
= num_patches
;
990 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
991 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
992 param_stride
, ""), "");
994 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
997 LLVMValueRef patch_data_offset
=
998 si_unpack_param(ctx
, ctx
->param_tcs_offchip_layout
, 12, 20);
1000 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1001 patch_data_offset
, "");
1006 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1007 static LLVMValueRef
get_tcs_tes_buffer_address_from_generic_indices(
1008 struct si_shader_context
*ctx
,
1009 LLVMValueRef vertex_index
,
1010 LLVMValueRef param_index
,
1011 unsigned param_base
,
1016 unsigned param_index_base
;
1018 param_index_base
= is_patch
?
1019 si_shader_io_get_unique_index_patch(name
[param_base
], index
[param_base
]) :
1020 si_shader_io_get_unique_index(name
[param_base
], index
[param_base
], false);
1023 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1024 LLVMConstInt(ctx
->i32
, param_index_base
, 0),
1027 param_index
= LLVMConstInt(ctx
->i32
, param_index_base
, 0);
1030 return get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
),
1031 vertex_index
, param_index
);
1034 static LLVMValueRef
get_tcs_tes_buffer_address_from_reg(
1035 struct si_shader_context
*ctx
,
1036 const struct tgsi_full_dst_register
*dst
,
1037 const struct tgsi_full_src_register
*src
)
1039 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1040 ubyte
*name
, *index
, *array_first
;
1041 struct tgsi_full_src_register reg
;
1042 LLVMValueRef vertex_index
= NULL
;
1043 LLVMValueRef param_index
= NULL
;
1044 unsigned param_base
;
1046 reg
= src
? *src
: tgsi_full_src_register_from_dst(dst
);
1048 if (reg
.Register
.Dimension
) {
1050 if (reg
.Dimension
.Indirect
)
1051 vertex_index
= si_get_indirect_index(ctx
, ®
.DimIndirect
,
1052 1, reg
.Dimension
.Index
);
1054 vertex_index
= LLVMConstInt(ctx
->i32
, reg
.Dimension
.Index
, 0);
1057 /* Get information about the register. */
1058 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1059 name
= info
->input_semantic_name
;
1060 index
= info
->input_semantic_index
;
1061 array_first
= info
->input_array_first
;
1062 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1063 name
= info
->output_semantic_name
;
1064 index
= info
->output_semantic_index
;
1065 array_first
= info
->output_array_first
;
1071 if (reg
.Register
.Indirect
) {
1072 if (reg
.Indirect
.ArrayID
)
1073 param_base
= array_first
[reg
.Indirect
.ArrayID
];
1075 param_base
= reg
.Register
.Index
;
1077 param_index
= si_get_indirect_index(ctx
, ®
.Indirect
,
1078 1, reg
.Register
.Index
- param_base
);
1081 param_base
= reg
.Register
.Index
;
1084 return get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1085 param_index
, param_base
,
1086 name
, index
, !reg
.Register
.Dimension
);
1089 static LLVMValueRef
buffer_load(struct lp_build_tgsi_context
*bld_base
,
1090 LLVMTypeRef type
, unsigned swizzle
,
1091 LLVMValueRef buffer
, LLVMValueRef offset
,
1092 LLVMValueRef base
, bool can_speculate
)
1094 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1095 LLVMValueRef value
, value2
;
1096 LLVMTypeRef vec_type
= LLVMVectorType(type
, 4);
1098 if (swizzle
== ~0) {
1099 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1100 0, 1, 0, can_speculate
, false);
1102 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1105 if (!llvm_type_is_64bit(ctx
, type
)) {
1106 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 4, NULL
, base
, offset
,
1107 0, 1, 0, can_speculate
, false);
1109 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, vec_type
, "");
1110 return LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1111 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1114 value
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1115 swizzle
* 4, 1, 0, can_speculate
, false);
1117 value2
= ac_build_buffer_load(&ctx
->ac
, buffer
, 1, NULL
, base
, offset
,
1118 swizzle
* 4 + 4, 1, 0, can_speculate
, false);
1120 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1126 * \param type output value type
1127 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1128 * \param dw_addr address in dwords
1130 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
1131 LLVMTypeRef type
, unsigned swizzle
,
1132 LLVMValueRef dw_addr
)
1134 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1137 if (swizzle
== ~0) {
1138 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1140 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
1141 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
1143 return ac_build_gather_values(&ctx
->ac
, values
,
1147 /* Split 64-bit loads. */
1148 if (llvm_type_is_64bit(ctx
, type
)) {
1149 LLVMValueRef lo
, hi
;
1151 lo
= lds_load(bld_base
, ctx
->i32
, swizzle
, dw_addr
);
1152 hi
= lds_load(bld_base
, ctx
->i32
, swizzle
+ 1, dw_addr
);
1153 return si_llvm_emit_fetch_64bit(bld_base
, type
, lo
, hi
);
1156 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1157 LLVMConstInt(ctx
->i32
, swizzle
, 0), "");
1159 value
= ac_lds_load(&ctx
->ac
, dw_addr
);
1161 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1167 * \param swizzle offset (typically 0..3)
1168 * \param dw_addr address in dwords
1169 * \param value value to store
1171 static void lds_store(struct si_shader_context
*ctx
,
1172 unsigned dw_offset_imm
, LLVMValueRef dw_addr
,
1175 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1176 LLVMConstInt(ctx
->i32
, dw_offset_imm
, 0), "");
1178 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
1183 TESS_OFFCHIP_RING_TCS
,
1184 TESS_OFFCHIP_RING_TES
,
1187 static LLVMValueRef
get_tess_ring_descriptor(struct si_shader_context
*ctx
,
1188 enum si_tess_ring ring
)
1190 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1191 unsigned param
= ring
== TESS_OFFCHIP_RING_TES
? ctx
->param_tes_offchip_addr
:
1192 ctx
->param_tcs_out_lds_layout
;
1193 LLVMValueRef addr
= LLVMGetParam(ctx
->main_fn
, param
);
1195 /* TCS only receives high 13 bits of the address. */
1196 if (ring
== TESS_OFFCHIP_RING_TCS
|| ring
== TCS_FACTOR_RING
) {
1197 addr
= LLVMBuildAnd(builder
, addr
,
1198 LLVMConstInt(ctx
->i32
, 0xfff80000, 0), "");
1201 if (ring
== TCS_FACTOR_RING
) {
1202 unsigned tf_offset
= ctx
->screen
->tess_offchip_ring_size
;
1203 addr
= LLVMBuildAdd(builder
, addr
,
1204 LLVMConstInt(ctx
->i32
, tf_offset
, 0), "");
1207 LLVMValueRef desc
[4];
1209 desc
[1] = LLVMConstInt(ctx
->i32
,
1210 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
1211 desc
[2] = LLVMConstInt(ctx
->i32
, 0xffffffff, 0);
1212 desc
[3] = LLVMConstInt(ctx
->i32
,
1213 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1217 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1218 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0);
1220 return ac_build_gather_values(&ctx
->ac
, desc
, 4);
1223 static LLVMValueRef
fetch_input_tcs(
1224 struct lp_build_tgsi_context
*bld_base
,
1225 const struct tgsi_full_src_register
*reg
,
1226 enum tgsi_opcode_type type
, unsigned swizzle
)
1228 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1229 LLVMValueRef dw_addr
, stride
;
1231 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1232 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1233 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1235 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1238 static LLVMValueRef
si_nir_load_tcs_varyings(struct ac_shader_abi
*abi
,
1240 LLVMValueRef vertex_index
,
1241 LLVMValueRef param_index
,
1242 unsigned const_index
,
1244 unsigned driver_location
,
1246 unsigned num_components
,
1251 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1252 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1253 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1254 LLVMValueRef dw_addr
, stride
;
1256 driver_location
= driver_location
/ 4;
1259 stride
= get_tcs_in_vertex_dw_stride(ctx
);
1260 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1264 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1266 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1267 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1272 /* Add the constant index to the indirect index */
1273 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1274 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1276 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1282 names
= info
->input_semantic_name
;
1283 indices
= info
->input_semantic_index
;
1285 names
= info
->output_semantic_name
;
1286 indices
= info
->output_semantic_index
;
1289 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1290 vertex_index
, param_index
,
1295 LLVMValueRef value
[4];
1296 for (unsigned i
= 0; i
< num_components
; i
++) {
1297 unsigned offset
= i
;
1298 if (llvm_type_is_64bit(ctx
, type
))
1301 offset
+= component
;
1302 value
[i
+ component
] = lds_load(bld_base
, type
, offset
, dw_addr
);
1305 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1308 static LLVMValueRef
fetch_output_tcs(
1309 struct lp_build_tgsi_context
*bld_base
,
1310 const struct tgsi_full_src_register
*reg
,
1311 enum tgsi_opcode_type type
, unsigned swizzle
)
1313 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1314 LLVMValueRef dw_addr
, stride
;
1316 if (reg
->Register
.Dimension
) {
1317 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1318 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1319 dw_addr
= get_dw_address(ctx
, NULL
, reg
, stride
, dw_addr
);
1321 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1322 dw_addr
= get_dw_address(ctx
, NULL
, reg
, NULL
, dw_addr
);
1325 return lds_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
, dw_addr
);
1328 static LLVMValueRef
fetch_input_tes(
1329 struct lp_build_tgsi_context
*bld_base
,
1330 const struct tgsi_full_src_register
*reg
,
1331 enum tgsi_opcode_type type
, unsigned swizzle
)
1333 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1334 LLVMValueRef base
, addr
;
1336 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1337 addr
= get_tcs_tes_buffer_address_from_reg(ctx
, NULL
, reg
);
1339 return buffer_load(bld_base
, tgsi2llvmtype(bld_base
, type
), swizzle
,
1340 ctx
->tess_offchip_ring
, base
, addr
, true);
1343 LLVMValueRef
si_nir_load_input_tes(struct ac_shader_abi
*abi
,
1345 LLVMValueRef vertex_index
,
1346 LLVMValueRef param_index
,
1347 unsigned const_index
,
1349 unsigned driver_location
,
1351 unsigned num_components
,
1356 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1357 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1358 LLVMValueRef base
, addr
;
1360 driver_location
= driver_location
/ 4;
1362 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1365 /* Add the constant index to the indirect index */
1366 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1367 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1369 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1372 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1373 param_index
, driver_location
,
1374 info
->input_semantic_name
,
1375 info
->input_semantic_index
,
1378 /* TODO: This will generate rather ordinary llvm code, although it
1379 * should be easy for the optimiser to fix up. In future we might want
1380 * to refactor buffer_load(), but for now this maximises code sharing
1381 * between the NIR and TGSI backends.
1383 LLVMValueRef value
[4];
1384 for (unsigned i
= 0; i
< num_components
; i
++) {
1385 unsigned offset
= i
;
1386 if (llvm_type_is_64bit(ctx
, type
))
1389 offset
+= component
;
1390 value
[i
+ component
] = buffer_load(&ctx
->bld_base
, type
, offset
,
1391 ctx
->tess_offchip_ring
, base
, addr
, true);
1394 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1397 static void store_output_tcs(struct lp_build_tgsi_context
*bld_base
,
1398 const struct tgsi_full_instruction
*inst
,
1399 const struct tgsi_opcode_info
*info
,
1401 LLVMValueRef dst
[4])
1403 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1404 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[index
];
1405 const struct tgsi_shader_info
*sh_info
= &ctx
->shader
->selector
->info
;
1406 unsigned chan_index
;
1407 LLVMValueRef dw_addr
, stride
;
1408 LLVMValueRef buffer
, base
, buf_addr
;
1409 LLVMValueRef values
[4];
1410 bool skip_lds_store
;
1411 bool is_tess_factor
= false, is_tess_inner
= false;
1413 /* Only handle per-patch and per-vertex outputs here.
1414 * Vectors will be lowered to scalars and this function will be called again.
1416 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
1417 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
1418 si_llvm_emit_store(bld_base
, inst
, info
, index
, dst
);
1422 if (reg
->Register
.Dimension
) {
1423 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1424 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1425 dw_addr
= get_dw_address(ctx
, reg
, NULL
, stride
, dw_addr
);
1426 skip_lds_store
= !sh_info
->reads_pervertex_outputs
;
1428 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1429 dw_addr
= get_dw_address(ctx
, reg
, NULL
, NULL
, dw_addr
);
1430 skip_lds_store
= !sh_info
->reads_perpatch_outputs
;
1432 if (!reg
->Register
.Indirect
) {
1433 int name
= sh_info
->output_semantic_name
[reg
->Register
.Index
];
1435 /* Always write tess factors into LDS for the TCS epilog. */
1436 if (name
== TGSI_SEMANTIC_TESSINNER
||
1437 name
== TGSI_SEMANTIC_TESSOUTER
) {
1438 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1439 skip_lds_store
= !sh_info
->reads_tessfactor_outputs
&&
1440 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1441 is_tess_factor
= true;
1442 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1447 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1449 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1450 buf_addr
= get_tcs_tes_buffer_address_from_reg(ctx
, reg
, NULL
);
1452 uint32_t writemask
= reg
->Register
.WriteMask
;
1454 chan_index
= u_bit_scan(&writemask
);
1455 LLVMValueRef value
= dst
[chan_index
];
1457 if (inst
->Instruction
.Saturate
)
1458 value
= ac_build_clamp(&ctx
->ac
, value
);
1460 /* Skip LDS stores if there is no LDS read of this output. */
1461 if (!skip_lds_store
)
1462 lds_store(ctx
, chan_index
, dw_addr
, value
);
1464 value
= ac_to_integer(&ctx
->ac
, value
);
1465 values
[chan_index
] = value
;
1467 if (reg
->Register
.WriteMask
!= 0xF && !is_tess_factor
) {
1468 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1470 4 * chan_index
, 1, 0, true, false);
1473 /* Write tess factors into VGPRs for the epilog. */
1474 if (is_tess_factor
&&
1475 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1476 if (!is_tess_inner
) {
1477 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1478 ctx
->invoc0_tess_factors
[chan_index
]);
1479 } else if (chan_index
< 2) {
1480 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1481 ctx
->invoc0_tess_factors
[4 + chan_index
]);
1486 if (reg
->Register
.WriteMask
== 0xF && !is_tess_factor
) {
1487 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1489 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buf_addr
,
1490 base
, 0, 1, 0, true, false);
1494 static void si_nir_store_output_tcs(struct ac_shader_abi
*abi
,
1495 const struct nir_variable
*var
,
1496 LLVMValueRef vertex_index
,
1497 LLVMValueRef param_index
,
1498 unsigned const_index
,
1502 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1503 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1504 const unsigned component
= var
->data
.location_frac
;
1505 const bool is_patch
= var
->data
.patch
;
1506 unsigned driver_location
= var
->data
.driver_location
;
1507 LLVMValueRef dw_addr
, stride
;
1508 LLVMValueRef buffer
, base
, addr
;
1509 LLVMValueRef values
[4];
1510 bool skip_lds_store
;
1511 bool is_tess_factor
= false, is_tess_inner
= false;
1513 driver_location
= driver_location
/ 4;
1516 /* Add the constant index to the indirect index */
1517 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, param_index
,
1518 LLVMConstInt(ctx
->i32
, const_index
, 0), "");
1520 if (const_index
!= 0)
1521 param_index
= LLVMConstInt(ctx
->i32
, const_index
, 0);
1525 stride
= get_tcs_out_vertex_dw_stride(ctx
);
1526 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1527 dw_addr
= get_dw_address_from_generic_indices(ctx
, stride
, dw_addr
,
1528 vertex_index
, param_index
,
1530 info
->output_semantic_name
,
1531 info
->output_semantic_index
,
1534 skip_lds_store
= !info
->reads_pervertex_outputs
;
1536 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1537 dw_addr
= get_dw_address_from_generic_indices(ctx
, NULL
, dw_addr
,
1538 vertex_index
, param_index
,
1540 info
->output_semantic_name
,
1541 info
->output_semantic_index
,
1544 skip_lds_store
= !info
->reads_perpatch_outputs
;
1547 int name
= info
->output_semantic_name
[driver_location
];
1549 /* Always write tess factors into LDS for the TCS epilog. */
1550 if (name
== TGSI_SEMANTIC_TESSINNER
||
1551 name
== TGSI_SEMANTIC_TESSOUTER
) {
1552 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1553 skip_lds_store
= !info
->reads_tessfactor_outputs
&&
1554 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1555 is_tess_factor
= true;
1556 is_tess_inner
= name
== TGSI_SEMANTIC_TESSINNER
;
1561 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
1563 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
1565 addr
= get_tcs_tes_buffer_address_from_generic_indices(ctx
, vertex_index
,
1566 param_index
, driver_location
,
1567 info
->output_semantic_name
,
1568 info
->output_semantic_index
,
1571 for (unsigned chan
= 0; chan
< 4; chan
++) {
1572 if (!(writemask
& (1 << chan
)))
1574 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1576 /* Skip LDS stores if there is no LDS read of this output. */
1577 if (!skip_lds_store
)
1578 lds_store(ctx
, chan
, dw_addr
, value
);
1580 value
= ac_to_integer(&ctx
->ac
, value
);
1581 values
[chan
] = value
;
1583 if (writemask
!= 0xF && !is_tess_factor
) {
1584 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 1,
1586 4 * chan
, 1, 0, true, false);
1589 /* Write tess factors into VGPRs for the epilog. */
1590 if (is_tess_factor
&&
1591 ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
1592 if (!is_tess_inner
) {
1593 LLVMBuildStore(ctx
->ac
.builder
, value
, /* outer */
1594 ctx
->invoc0_tess_factors
[chan
]);
1595 } else if (chan
< 2) {
1596 LLVMBuildStore(ctx
->ac
.builder
, value
, /* inner */
1597 ctx
->invoc0_tess_factors
[4 + chan
]);
1602 if (writemask
== 0xF && !is_tess_factor
) {
1603 LLVMValueRef value
= ac_build_gather_values(&ctx
->ac
,
1605 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, addr
,
1606 base
, 0, 1, 0, true, false);
1610 LLVMValueRef
si_llvm_load_input_gs(struct ac_shader_abi
*abi
,
1611 unsigned input_index
,
1612 unsigned vtx_offset_param
,
1616 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1617 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1618 struct si_shader
*shader
= ctx
->shader
;
1619 LLVMValueRef vtx_offset
, soffset
;
1620 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1621 unsigned semantic_name
= info
->input_semantic_name
[input_index
];
1622 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1626 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
, false);
1628 /* GFX9 has the ESGS ring in LDS. */
1629 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1630 unsigned index
= vtx_offset_param
;
1632 switch (index
/ 2) {
1634 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx01_offset
,
1635 index
% 2 ? 16 : 0, 16);
1638 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx23_offset
,
1639 index
% 2 ? 16 : 0, 16);
1642 vtx_offset
= si_unpack_param(ctx
, ctx
->param_gs_vtx45_offset
,
1643 index
% 2 ? 16 : 0, 16);
1650 vtx_offset
= LLVMBuildAdd(ctx
->ac
.builder
, vtx_offset
,
1651 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
1652 return lds_load(bld_base
, type
, swizzle
, vtx_offset
);
1655 /* GFX6: input load from the ESGS ring in memory. */
1656 if (swizzle
== ~0) {
1657 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
1659 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1660 values
[chan
] = si_llvm_load_input_gs(abi
, input_index
, vtx_offset_param
,
1663 return ac_build_gather_values(&ctx
->ac
, values
,
1667 /* Get the vertex offset parameter on GFX6. */
1668 LLVMValueRef gs_vtx_offset
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1670 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, gs_vtx_offset
,
1671 LLVMConstInt(ctx
->i32
, 4, 0), "");
1673 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
) * 256, 0);
1675 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1, ctx
->i32_0
,
1676 vtx_offset
, soffset
, 0, 1, 0, true, false);
1677 if (llvm_type_is_64bit(ctx
, type
)) {
1678 LLVMValueRef value2
;
1679 soffset
= LLVMConstInt(ctx
->i32
, (param
* 4 + swizzle
+ 1) * 256, 0);
1681 value2
= ac_build_buffer_load(&ctx
->ac
, ctx
->esgs_ring
, 1,
1682 ctx
->i32_0
, vtx_offset
, soffset
,
1683 0, 1, 0, true, false);
1684 return si_llvm_emit_fetch_64bit(bld_base
, type
, value
, value2
);
1686 return LLVMBuildBitCast(ctx
->ac
.builder
, value
, type
, "");
1689 static LLVMValueRef
si_nir_load_input_gs(struct ac_shader_abi
*abi
,
1691 unsigned driver_location
,
1693 unsigned num_components
,
1694 unsigned vertex_index
,
1695 unsigned const_index
,
1698 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1700 LLVMValueRef value
[4];
1701 for (unsigned i
= 0; i
< num_components
; i
++) {
1702 unsigned offset
= i
;
1703 if (llvm_type_is_64bit(ctx
, type
))
1706 offset
+= component
;
1707 value
[i
+ component
] = si_llvm_load_input_gs(&ctx
->abi
, driver_location
/ 4,
1708 vertex_index
, type
, offset
);
1711 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1714 static LLVMValueRef
fetch_input_gs(
1715 struct lp_build_tgsi_context
*bld_base
,
1716 const struct tgsi_full_src_register
*reg
,
1717 enum tgsi_opcode_type type
,
1720 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1721 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1723 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
1724 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
1725 return get_primitive_id(ctx
, swizzle
);
1727 if (!reg
->Register
.Dimension
)
1730 return si_llvm_load_input_gs(&ctx
->abi
, reg
->Register
.Index
,
1731 reg
->Dimension
.Index
,
1732 tgsi2llvmtype(bld_base
, type
),
1736 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
1738 switch (interpolate
) {
1739 case TGSI_INTERPOLATE_CONSTANT
:
1742 case TGSI_INTERPOLATE_LINEAR
:
1743 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1744 return SI_PARAM_LINEAR_SAMPLE
;
1745 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1746 return SI_PARAM_LINEAR_CENTROID
;
1748 return SI_PARAM_LINEAR_CENTER
;
1750 case TGSI_INTERPOLATE_COLOR
:
1751 case TGSI_INTERPOLATE_PERSPECTIVE
:
1752 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
1753 return SI_PARAM_PERSP_SAMPLE
;
1754 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
1755 return SI_PARAM_PERSP_CENTROID
;
1757 return SI_PARAM_PERSP_CENTER
;
1760 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
1765 static LLVMValueRef
si_build_fs_interp(struct si_shader_context
*ctx
,
1766 unsigned attr_index
, unsigned chan
,
1767 LLVMValueRef prim_mask
,
1768 LLVMValueRef i
, LLVMValueRef j
)
1771 return ac_build_fs_interp(&ctx
->ac
,
1772 LLVMConstInt(ctx
->i32
, chan
, 0),
1773 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1776 return ac_build_fs_interp_mov(&ctx
->ac
,
1777 LLVMConstInt(ctx
->i32
, 2, 0), /* P0 */
1778 LLVMConstInt(ctx
->i32
, chan
, 0),
1779 LLVMConstInt(ctx
->i32
, attr_index
, 0),
1784 * Interpolate a fragment shader input.
1786 * @param ctx context
1787 * @param input_index index of the input in hardware
1788 * @param semantic_name TGSI_SEMANTIC_*
1789 * @param semantic_index semantic index
1790 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1791 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1792 * @param interp_param interpolation weights (i,j)
1793 * @param prim_mask SI_PARAM_PRIM_MASK
1794 * @param face SI_PARAM_FRONT_FACE
1795 * @param result the return value (4 components)
1797 static void interp_fs_input(struct si_shader_context
*ctx
,
1798 unsigned input_index
,
1799 unsigned semantic_name
,
1800 unsigned semantic_index
,
1801 unsigned num_interp_inputs
,
1802 unsigned colors_read_mask
,
1803 LLVMValueRef interp_param
,
1804 LLVMValueRef prim_mask
,
1806 LLVMValueRef result
[4])
1808 LLVMValueRef i
= NULL
, j
= NULL
;
1811 /* fs.constant returns the param from the middle vertex, so it's not
1812 * really useful for flat shading. It's meant to be used for custom
1813 * interpolation (but the intrinsic can't fetch from the other two
1816 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1817 * to do the right thing. The only reason we use fs.constant is that
1818 * fs.interp cannot be used on integers, because they can be equal
1821 * When interp is false we will use fs.constant or for newer llvm,
1822 * amdgcn.interp.mov.
1824 bool interp
= interp_param
!= NULL
;
1827 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
1828 LLVMVectorType(ctx
->f32
, 2), "");
1830 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1832 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
1836 if (semantic_name
== TGSI_SEMANTIC_COLOR
&&
1837 ctx
->shader
->key
.part
.ps
.prolog
.color_two_side
) {
1838 LLVMValueRef is_face_positive
;
1840 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1841 * otherwise it's at offset "num_inputs".
1843 unsigned back_attr_offset
= num_interp_inputs
;
1844 if (semantic_index
== 1 && colors_read_mask
& 0xf)
1845 back_attr_offset
+= 1;
1847 is_face_positive
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1848 face
, ctx
->i32_0
, "");
1850 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1851 LLVMValueRef front
, back
;
1853 front
= si_build_fs_interp(ctx
,
1856 back
= si_build_fs_interp(ctx
,
1857 back_attr_offset
, chan
,
1860 result
[chan
] = LLVMBuildSelect(ctx
->ac
.builder
,
1866 } else if (semantic_name
== TGSI_SEMANTIC_FOG
) {
1867 result
[0] = si_build_fs_interp(ctx
, input_index
,
1868 0, prim_mask
, i
, j
);
1870 result
[2] = LLVMConstReal(ctx
->f32
, 0.0f
);
1871 result
[3] = LLVMConstReal(ctx
->f32
, 1.0f
);
1873 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1874 result
[chan
] = si_build_fs_interp(ctx
,
1881 void si_llvm_load_input_fs(
1882 struct si_shader_context
*ctx
,
1883 unsigned input_index
,
1884 LLVMValueRef out
[4])
1886 struct si_shader
*shader
= ctx
->shader
;
1887 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1888 LLVMValueRef main_fn
= ctx
->main_fn
;
1889 LLVMValueRef interp_param
= NULL
;
1890 int interp_param_idx
;
1891 enum tgsi_semantic semantic_name
= info
->input_semantic_name
[input_index
];
1892 unsigned semantic_index
= info
->input_semantic_index
[input_index
];
1893 enum tgsi_interpolate_mode interp_mode
= info
->input_interpolate
[input_index
];
1894 enum tgsi_interpolate_loc interp_loc
= info
->input_interpolate_loc
[input_index
];
1896 /* Get colors from input VGPRs (set by the prolog). */
1897 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1898 unsigned colors_read
= shader
->selector
->info
.colors_read
;
1899 unsigned mask
= colors_read
>> (semantic_index
* 4);
1900 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1 +
1901 (semantic_index
? util_bitcount(colors_read
& 0xf) : 0);
1902 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1904 out
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1905 out
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1906 out
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1907 out
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1911 interp_param_idx
= lookup_interp_param_index(interp_mode
, interp_loc
);
1912 if (interp_param_idx
== -1)
1914 else if (interp_param_idx
) {
1915 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
1918 interp_fs_input(ctx
, input_index
, semantic_name
,
1919 semantic_index
, 0, /* this param is unused */
1920 shader
->selector
->info
.colors_read
, interp_param
,
1922 LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
),
1926 static void declare_input_fs(
1927 struct si_shader_context
*ctx
,
1928 unsigned input_index
,
1929 const struct tgsi_full_declaration
*decl
,
1930 LLVMValueRef out
[4])
1932 si_llvm_load_input_fs(ctx
, input_index
, out
);
1935 LLVMValueRef
si_get_sample_id(struct si_shader_context
*ctx
)
1937 return si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 8, 4);
1940 static LLVMValueRef
get_base_vertex(struct ac_shader_abi
*abi
)
1942 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1944 /* For non-indexed draws, the base vertex set by the driver
1945 * (for direct draws) or the CP (for indirect draws) is the
1946 * first vertex ID, but GLSL expects 0 to be returned.
1948 LLVMValueRef vs_state
= LLVMGetParam(ctx
->main_fn
,
1949 ctx
->param_vs_state_bits
);
1950 LLVMValueRef indexed
;
1952 indexed
= LLVMBuildLShr(ctx
->ac
.builder
, vs_state
, ctx
->i32_1
, "");
1953 indexed
= LLVMBuildTrunc(ctx
->ac
.builder
, indexed
, ctx
->i1
, "");
1955 return LLVMBuildSelect(ctx
->ac
.builder
, indexed
, ctx
->abi
.base_vertex
,
1959 static LLVMValueRef
get_block_size(struct ac_shader_abi
*abi
)
1961 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1963 LLVMValueRef values
[3];
1964 LLVMValueRef result
;
1966 unsigned *properties
= ctx
->shader
->selector
->info
.properties
;
1968 if (properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] != 0) {
1969 unsigned sizes
[3] = {
1970 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
],
1971 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
],
1972 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
]
1975 for (i
= 0; i
< 3; ++i
)
1976 values
[i
] = LLVMConstInt(ctx
->i32
, sizes
[i
], 0);
1978 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
1980 result
= LLVMGetParam(ctx
->main_fn
, ctx
->param_block_size
);
1987 * Load a dword from a constant buffer.
1989 static LLVMValueRef
buffer_load_const(struct si_shader_context
*ctx
,
1990 LLVMValueRef resource
,
1991 LLVMValueRef offset
)
1993 return ac_build_buffer_load(&ctx
->ac
, resource
, 1, NULL
, offset
, NULL
,
1994 0, 0, 0, true, true);
1997 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
, LLVMValueRef sample_id
)
1999 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2000 LLVMValueRef desc
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2001 LLVMValueRef buf_index
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_SAMPLE_POSITIONS
, 0);
2002 LLVMValueRef resource
= ac_build_load_to_sgpr(&ctx
->ac
, desc
, buf_index
);
2004 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2005 LLVMValueRef offset0
= LLVMBuildMul(ctx
->ac
.builder
, sample_id
, LLVMConstInt(ctx
->i32
, 8, 0), "");
2006 LLVMValueRef offset1
= LLVMBuildAdd(ctx
->ac
.builder
, offset0
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2008 LLVMValueRef pos
[4] = {
2009 buffer_load_const(ctx
, resource
, offset0
),
2010 buffer_load_const(ctx
, resource
, offset1
),
2011 LLVMConstReal(ctx
->f32
, 0),
2012 LLVMConstReal(ctx
->f32
, 0)
2015 return ac_build_gather_values(&ctx
->ac
, pos
, 4);
2018 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
2020 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2021 return ac_to_integer(&ctx
->ac
, abi
->sample_coverage
);
2024 static LLVMValueRef
si_load_tess_coord(struct ac_shader_abi
*abi
)
2026 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2027 LLVMValueRef coord
[4] = {
2028 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_u
),
2029 LLVMGetParam(ctx
->main_fn
, ctx
->param_tes_v
),
2034 /* For triangles, the vector should be (u, v, 1-u-v). */
2035 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
2036 PIPE_PRIM_TRIANGLES
) {
2037 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
2038 LLVMBuildFAdd(ctx
->ac
.builder
,
2039 coord
[0], coord
[1], ""), "");
2041 return ac_build_gather_values(&ctx
->ac
, coord
, 4);
2044 static LLVMValueRef
load_tess_level(struct si_shader_context
*ctx
,
2045 unsigned semantic_name
)
2047 LLVMValueRef base
, addr
;
2049 int param
= si_shader_io_get_unique_index_patch(semantic_name
, 0);
2051 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
2052 addr
= get_tcs_tes_buffer_address(ctx
, get_rel_patch_id(ctx
), NULL
,
2053 LLVMConstInt(ctx
->i32
, param
, 0));
2055 return buffer_load(&ctx
->bld_base
, ctx
->f32
,
2056 ~0, ctx
->tess_offchip_ring
, base
, addr
, true);
2060 static LLVMValueRef
si_load_tess_level(struct ac_shader_abi
*abi
,
2061 unsigned varying_id
)
2063 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2064 unsigned semantic_name
;
2066 switch (varying_id
) {
2067 case VARYING_SLOT_TESS_LEVEL_INNER
:
2068 semantic_name
= TGSI_SEMANTIC_TESSINNER
;
2070 case VARYING_SLOT_TESS_LEVEL_OUTER
:
2071 semantic_name
= TGSI_SEMANTIC_TESSOUTER
;
2074 unreachable("unknown tess level");
2077 return load_tess_level(ctx
, semantic_name
);
2081 static LLVMValueRef
si_load_patch_vertices_in(struct ac_shader_abi
*abi
)
2083 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2084 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2085 return si_unpack_param(ctx
, ctx
->param_tcs_out_lds_layout
, 13, 6);
2086 else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
)
2087 return get_num_tcs_out_vertices(ctx
);
2089 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2092 void si_load_system_value(struct si_shader_context
*ctx
,
2094 const struct tgsi_full_declaration
*decl
)
2096 LLVMValueRef value
= 0;
2098 assert(index
< RADEON_LLVM_MAX_SYSTEM_VALUES
);
2100 switch (decl
->Semantic
.Name
) {
2101 case TGSI_SEMANTIC_INSTANCEID
:
2102 value
= ctx
->abi
.instance_id
;
2105 case TGSI_SEMANTIC_VERTEXID
:
2106 value
= LLVMBuildAdd(ctx
->ac
.builder
,
2108 ctx
->abi
.base_vertex
, "");
2111 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
2112 /* Unused. Clarify the meaning in indexed vs. non-indexed
2113 * draws if this is ever used again. */
2117 case TGSI_SEMANTIC_BASEVERTEX
:
2118 value
= get_base_vertex(&ctx
->abi
);
2121 case TGSI_SEMANTIC_BASEINSTANCE
:
2122 value
= ctx
->abi
.start_instance
;
2125 case TGSI_SEMANTIC_DRAWID
:
2126 value
= ctx
->abi
.draw_id
;
2129 case TGSI_SEMANTIC_INVOCATIONID
:
2130 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
2131 value
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2132 else if (ctx
->type
== PIPE_SHADER_GEOMETRY
)
2133 value
= ctx
->abi
.gs_invocation_id
;
2135 assert(!"INVOCATIONID not implemented");
2138 case TGSI_SEMANTIC_POSITION
:
2140 LLVMValueRef pos
[4] = {
2141 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2142 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2143 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
2144 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2145 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
)),
2147 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2151 case TGSI_SEMANTIC_FACE
:
2152 value
= ctx
->abi
.front_face
;
2155 case TGSI_SEMANTIC_SAMPLEID
:
2156 value
= si_get_sample_id(ctx
);
2159 case TGSI_SEMANTIC_SAMPLEPOS
: {
2160 LLVMValueRef pos
[4] = {
2161 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
),
2162 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
2163 LLVMConstReal(ctx
->f32
, 0),
2164 LLVMConstReal(ctx
->f32
, 0)
2166 pos
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
2167 pos
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
2168 value
= ac_build_gather_values(&ctx
->ac
, pos
, 4);
2172 case TGSI_SEMANTIC_SAMPLEMASK
:
2173 /* This can only occur with the OpenGL Core profile, which
2174 * doesn't support smoothing.
2176 value
= LLVMGetParam(ctx
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
2179 case TGSI_SEMANTIC_TESSCOORD
:
2180 value
= si_load_tess_coord(&ctx
->abi
);
2183 case TGSI_SEMANTIC_VERTICESIN
:
2184 value
= si_load_patch_vertices_in(&ctx
->abi
);
2187 case TGSI_SEMANTIC_TESSINNER
:
2188 case TGSI_SEMANTIC_TESSOUTER
:
2189 value
= load_tess_level(ctx
, decl
->Semantic
.Name
);
2192 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
:
2193 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
:
2195 LLVMValueRef buf
, slot
, val
[4];
2198 slot
= LLVMConstInt(ctx
->i32
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, 0);
2199 buf
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2200 buf
= ac_build_load_to_sgpr(&ctx
->ac
, buf
, slot
);
2201 offset
= decl
->Semantic
.Name
== TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
? 4 : 0;
2203 for (i
= 0; i
< 4; i
++)
2204 val
[i
] = buffer_load_const(ctx
, buf
,
2205 LLVMConstInt(ctx
->i32
, (offset
+ i
) * 4, 0));
2206 value
= ac_build_gather_values(&ctx
->ac
, val
, 4);
2210 case TGSI_SEMANTIC_PRIMID
:
2211 value
= get_primitive_id(ctx
, 0);
2214 case TGSI_SEMANTIC_GRID_SIZE
:
2215 value
= ctx
->abi
.num_work_groups
;
2218 case TGSI_SEMANTIC_BLOCK_SIZE
:
2219 value
= get_block_size(&ctx
->abi
);
2222 case TGSI_SEMANTIC_BLOCK_ID
:
2224 LLVMValueRef values
[3];
2226 for (int i
= 0; i
< 3; i
++) {
2227 values
[i
] = ctx
->i32_0
;
2228 if (ctx
->abi
.workgroup_ids
[i
]) {
2229 values
[i
] = ctx
->abi
.workgroup_ids
[i
];
2232 value
= ac_build_gather_values(&ctx
->ac
, values
, 3);
2236 case TGSI_SEMANTIC_THREAD_ID
:
2237 value
= ctx
->abi
.local_invocation_ids
;
2240 case TGSI_SEMANTIC_HELPER_INVOCATION
:
2241 value
= ac_build_intrinsic(&ctx
->ac
,
2242 "llvm.amdgcn.ps.live",
2244 AC_FUNC_ATTR_READNONE
);
2245 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2246 value
= LLVMBuildSExt(ctx
->ac
.builder
, value
, ctx
->i32
, "");
2249 case TGSI_SEMANTIC_SUBGROUP_SIZE
:
2250 value
= LLVMConstInt(ctx
->i32
, 64, 0);
2253 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
:
2254 value
= ac_get_thread_id(&ctx
->ac
);
2257 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
2259 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2260 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2261 value
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->i64
, 1, 0), id
, "");
2262 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2266 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
2267 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
2268 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
2269 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
2271 LLVMValueRef id
= ac_get_thread_id(&ctx
->ac
);
2272 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_GT_MASK
||
2273 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
) {
2274 /* All bits set except LSB */
2275 value
= LLVMConstInt(ctx
->i64
, -2, 0);
2278 value
= LLVMConstInt(ctx
->i64
, -1, 0);
2280 id
= LLVMBuildZExt(ctx
->ac
.builder
, id
, ctx
->i64
, "");
2281 value
= LLVMBuildShl(ctx
->ac
.builder
, value
, id
, "");
2282 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LE_MASK
||
2283 decl
->Semantic
.Name
== TGSI_SEMANTIC_SUBGROUP_LT_MASK
)
2284 value
= LLVMBuildNot(ctx
->ac
.builder
, value
, "");
2285 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->v2i32
, "");
2290 assert(!"unknown system value");
2294 ctx
->system_values
[index
] = value
;
2297 void si_declare_compute_memory(struct si_shader_context
*ctx
)
2299 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2301 LLVMTypeRef i8p
= LLVMPointerType(ctx
->i8
, AC_LOCAL_ADDR_SPACE
);
2304 assert(!ctx
->ac
.lds
);
2306 var
= LLVMAddGlobalInAddressSpace(ctx
->ac
.module
,
2307 LLVMArrayType(ctx
->i8
, sel
->local_size
),
2309 AC_LOCAL_ADDR_SPACE
);
2310 LLVMSetAlignment(var
, 4);
2312 ctx
->ac
.lds
= LLVMBuildBitCast(ctx
->ac
.builder
, var
, i8p
, "");
2315 void si_tgsi_declare_compute_memory(struct si_shader_context
*ctx
,
2316 const struct tgsi_full_declaration
*decl
)
2318 assert(decl
->Declaration
.MemType
== TGSI_MEMORY_TYPE_SHARED
);
2319 assert(decl
->Range
.First
== decl
->Range
.Last
);
2321 si_declare_compute_memory(ctx
);
2324 static LLVMValueRef
load_const_buffer_desc_fast_path(struct si_shader_context
*ctx
)
2327 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2328 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2330 /* Do the bounds checking with a descriptor, because
2331 * doing computation and manual bounds checking of 64-bit
2332 * addresses generates horrible VALU code with very high
2333 * VGPR usage and very low SIMD occupancy.
2335 ptr
= LLVMBuildPtrToInt(ctx
->ac
.builder
, ptr
, ctx
->ac
.intptr
, "");
2337 LLVMValueRef desc0
, desc1
;
2338 if (HAVE_32BIT_POINTERS
) {
2340 desc1
= LLVMConstInt(ctx
->i32
,
2341 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0);
2343 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
, ctx
->v2i32
, "");
2344 desc0
= LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_0
, "");
2345 desc1
= LLVMBuildExtractElement(ctx
->ac
.builder
, ptr
, ctx
->i32_1
, "");
2346 /* Mask out all bits except BASE_ADDRESS_HI. */
2347 desc1
= LLVMBuildAnd(ctx
->ac
.builder
, desc1
,
2348 LLVMConstInt(ctx
->i32
, ~C_008F04_BASE_ADDRESS_HI
, 0), "");
2351 LLVMValueRef desc_elems
[] = {
2354 LLVMConstInt(ctx
->i32
, (sel
->info
.const_file_max
[0] + 1) * 16, 0),
2355 LLVMConstInt(ctx
->i32
,
2356 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2357 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2358 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2359 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2360 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2361 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
), 0)
2364 return ac_build_gather_values(&ctx
->ac
, desc_elems
, 4);
2367 static LLVMValueRef
load_const_buffer_desc(struct si_shader_context
*ctx
, int i
)
2369 LLVMValueRef list_ptr
= LLVMGetParam(ctx
->main_fn
,
2370 ctx
->param_const_and_shader_buffers
);
2372 return ac_build_load_to_sgpr(&ctx
->ac
, list_ptr
,
2373 LLVMConstInt(ctx
->i32
, si_get_constbuf_slot(i
), 0));
2376 static LLVMValueRef
load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef index
)
2378 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2379 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2381 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2383 if (sel
->info
.const_buffers_declared
== 1 &&
2384 sel
->info
.shader_buffers_declared
== 0) {
2385 return load_const_buffer_desc_fast_path(ctx
);
2388 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_const_buffers
);
2389 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2390 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2392 return ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2396 load_ssbo(struct ac_shader_abi
*abi
, LLVMValueRef index
, bool write
)
2398 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
2399 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
2400 ctx
->param_const_and_shader_buffers
);
2402 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_shader_buffers
);
2403 index
= LLVMBuildSub(ctx
->ac
.builder
,
2404 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
- 1, 0),
2407 return ac_build_load_to_sgpr(&ctx
->ac
, rsrc_ptr
, index
);
2410 static LLVMValueRef
fetch_constant(
2411 struct lp_build_tgsi_context
*bld_base
,
2412 const struct tgsi_full_src_register
*reg
,
2413 enum tgsi_opcode_type type
,
2416 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2417 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2418 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
2421 LLVMValueRef addr
, bufp
;
2423 if (swizzle
== LP_CHAN_ALL
) {
2425 LLVMValueRef values
[4];
2426 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
2427 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
2429 return ac_build_gather_values(&ctx
->ac
, values
, 4);
2432 /* Split 64-bit loads. */
2433 if (tgsi_type_is_64bit(type
)) {
2434 LLVMValueRef lo
, hi
;
2436 lo
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
);
2437 hi
= fetch_constant(bld_base
, reg
, TGSI_TYPE_UNSIGNED
, swizzle
+ 1);
2438 return si_llvm_emit_fetch_64bit(bld_base
, tgsi2llvmtype(bld_base
, type
),
2442 idx
= reg
->Register
.Index
* 4 + swizzle
;
2443 if (reg
->Register
.Indirect
) {
2444 addr
= si_get_indirect_index(ctx
, ireg
, 16, idx
* 4);
2446 addr
= LLVMConstInt(ctx
->i32
, idx
* 4, 0);
2449 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2450 if (sel
->info
.const_buffers_declared
== 1 &&
2451 sel
->info
.shader_buffers_declared
== 0) {
2453 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2454 * loads, and up to x4 load opcode merging. However, it leads to horrible
2455 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2457 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2459 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2460 * a descriptor and s_buffer_load_dword using it, so we can't expand
2461 * the pointer into a full descriptor like below. We have to use
2462 * s_load_dword instead. The only case when LLVM 5.0 would select
2463 * s_buffer_load_dword (that we have to prevent) is when we use use
2464 * a literal offset where we don't need bounds checking.
2466 if (ctx
->screen
->info
.chip_class
== SI
&& HAVE_LLVM
< 0x0600 &&
2467 !reg
->Register
.Indirect
) {
2469 LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2471 addr
= LLVMBuildLShr(ctx
->ac
.builder
, addr
, LLVMConstInt(ctx
->i32
, 2, 0), "");
2472 LLVMValueRef result
= ac_build_load_invariant(&ctx
->ac
, ptr
, addr
);
2473 return bitcast(bld_base
, type
, result
);
2476 LLVMValueRef desc
= load_const_buffer_desc_fast_path(ctx
);
2477 LLVMValueRef result
= buffer_load_const(ctx
, desc
, addr
);
2478 return bitcast(bld_base
, type
, result
);
2481 assert(reg
->Register
.Dimension
);
2482 buf
= reg
->Dimension
.Index
;
2484 if (reg
->Dimension
.Indirect
) {
2485 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_const_and_shader_buffers
);
2487 index
= si_get_bounded_indirect_index(ctx
, ®
->DimIndirect
,
2488 reg
->Dimension
.Index
,
2489 ctx
->num_const_buffers
);
2490 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
2491 LLVMConstInt(ctx
->i32
, SI_NUM_SHADER_BUFFERS
, 0), "");
2492 bufp
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, index
);
2494 bufp
= load_const_buffer_desc(ctx
, buf
);
2496 return bitcast(bld_base
, type
, buffer_load_const(ctx
, bufp
, addr
));
2499 /* Initialize arguments for the shader export intrinsic */
2500 static void si_llvm_init_export_args(struct si_shader_context
*ctx
,
2501 LLVMValueRef
*values
,
2503 struct ac_export_args
*args
)
2505 LLVMValueRef f32undef
= LLVMGetUndef(ctx
->ac
.f32
);
2506 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
2508 bool is_int8
, is_int10
;
2510 /* Default is 0xf. Adjusted below depending on the format. */
2511 args
->enabled_channels
= 0xf; /* writemask */
2513 /* Specify whether the EXEC mask represents the valid mask */
2514 args
->valid_mask
= 0;
2516 /* Specify whether this is the last export */
2519 /* Specify the target we are exporting */
2520 args
->target
= target
;
2522 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
2523 const struct si_shader_key
*key
= &ctx
->shader
->key
;
2524 unsigned col_formats
= key
->part
.ps
.epilog
.spi_shader_col_format
;
2525 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
2527 assert(cbuf
>= 0 && cbuf
< 8);
2528 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
2529 is_int8
= (key
->part
.ps
.epilog
.color_is_int8
>> cbuf
) & 0x1;
2530 is_int10
= (key
->part
.ps
.epilog
.color_is_int10
>> cbuf
) & 0x1;
2533 args
->compr
= false;
2534 args
->out
[0] = f32undef
;
2535 args
->out
[1] = f32undef
;
2536 args
->out
[2] = f32undef
;
2537 args
->out
[3] = f32undef
;
2539 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2540 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2541 unsigned bits
, bool hi
) = NULL
;
2543 switch (spi_shader_col_format
) {
2544 case V_028714_SPI_SHADER_ZERO
:
2545 args
->enabled_channels
= 0; /* writemask */
2546 args
->target
= V_008DFC_SQ_EXP_NULL
;
2549 case V_028714_SPI_SHADER_32_R
:
2550 args
->enabled_channels
= 1; /* writemask */
2551 args
->out
[0] = values
[0];
2554 case V_028714_SPI_SHADER_32_GR
:
2555 args
->enabled_channels
= 0x3; /* writemask */
2556 args
->out
[0] = values
[0];
2557 args
->out
[1] = values
[1];
2560 case V_028714_SPI_SHADER_32_AR
:
2561 args
->enabled_channels
= 0x9; /* writemask */
2562 args
->out
[0] = values
[0];
2563 args
->out
[3] = values
[3];
2566 case V_028714_SPI_SHADER_FP16_ABGR
:
2567 packf
= ac_build_cvt_pkrtz_f16
;
2570 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2571 packf
= ac_build_cvt_pknorm_u16
;
2574 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2575 packf
= ac_build_cvt_pknorm_i16
;
2578 case V_028714_SPI_SHADER_UINT16_ABGR
:
2579 packi
= ac_build_cvt_pk_u16
;
2582 case V_028714_SPI_SHADER_SINT16_ABGR
:
2583 packi
= ac_build_cvt_pk_i16
;
2586 case V_028714_SPI_SHADER_32_ABGR
:
2587 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2591 /* Pack f16 or norm_i16/u16. */
2593 for (chan
= 0; chan
< 2; chan
++) {
2594 LLVMValueRef pack_args
[2] = {
2596 values
[2 * chan
+ 1]
2598 LLVMValueRef packed
;
2600 packed
= packf(&ctx
->ac
, pack_args
);
2601 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2603 args
->compr
= 1; /* COMPR flag */
2607 for (chan
= 0; chan
< 2; chan
++) {
2608 LLVMValueRef pack_args
[2] = {
2609 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2610 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2612 LLVMValueRef packed
;
2614 packed
= packi(&ctx
->ac
, pack_args
,
2615 is_int8
? 8 : is_int10
? 10 : 16,
2617 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2619 args
->compr
= 1; /* COMPR flag */
2623 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
2626 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2628 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_NEVER
) {
2629 static LLVMRealPredicate cond_map
[PIPE_FUNC_ALWAYS
+ 1] = {
2630 [PIPE_FUNC_LESS
] = LLVMRealOLT
,
2631 [PIPE_FUNC_EQUAL
] = LLVMRealOEQ
,
2632 [PIPE_FUNC_LEQUAL
] = LLVMRealOLE
,
2633 [PIPE_FUNC_GREATER
] = LLVMRealOGT
,
2634 [PIPE_FUNC_NOTEQUAL
] = LLVMRealONE
,
2635 [PIPE_FUNC_GEQUAL
] = LLVMRealOGE
,
2637 LLVMRealPredicate cond
= cond_map
[ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
];
2640 LLVMValueRef alpha_ref
= LLVMGetParam(ctx
->main_fn
,
2641 SI_PARAM_ALPHA_REF
);
2642 LLVMValueRef alpha_pass
=
2643 LLVMBuildFCmp(ctx
->ac
.builder
, cond
, alpha
, alpha_ref
, "");
2644 ac_build_kill_if_false(&ctx
->ac
, alpha_pass
);
2646 ac_build_kill_if_false(&ctx
->ac
, LLVMConstInt(ctx
->i1
, 0, 0));
2650 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
2652 unsigned samplemask_param
)
2654 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
2655 LLVMValueRef coverage
;
2657 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2658 coverage
= LLVMGetParam(ctx
->main_fn
,
2660 coverage
= ac_to_integer(&ctx
->ac
, coverage
);
2662 coverage
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32",
2664 &coverage
, 1, AC_FUNC_ATTR_READNONE
);
2666 coverage
= LLVMBuildUIToFP(ctx
->ac
.builder
, coverage
,
2669 coverage
= LLVMBuildFMul(ctx
->ac
.builder
, coverage
,
2670 LLVMConstReal(ctx
->f32
,
2671 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
2673 return LLVMBuildFMul(ctx
->ac
.builder
, alpha
, coverage
, "");
2676 static void si_llvm_emit_clipvertex(struct si_shader_context
*ctx
,
2677 struct ac_export_args
*pos
, LLVMValueRef
*out_elts
)
2681 unsigned const_chan
;
2682 LLVMValueRef base_elt
;
2683 LLVMValueRef ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
2684 LLVMValueRef constbuf_index
= LLVMConstInt(ctx
->i32
,
2685 SI_VS_CONST_CLIP_PLANES
, 0);
2686 LLVMValueRef const_resource
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
, constbuf_index
);
2688 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
2689 struct ac_export_args
*args
= &pos
[2 + reg_index
];
2694 args
->out
[3] = LLVMConstReal(ctx
->f32
, 0.0f
);
2696 /* Compute dot products of position and user clip plane vectors */
2697 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2698 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
2700 LLVMConstInt(ctx
->i32
, ((reg_index
* 4 + chan
) * 4 +
2701 const_chan
) * 4, 0);
2702 base_elt
= buffer_load_const(ctx
, const_resource
,
2705 LLVMBuildFAdd(ctx
->ac
.builder
, args
->out
[chan
],
2706 LLVMBuildFMul(ctx
->ac
.builder
, base_elt
,
2707 out_elts
[const_chan
], ""), "");
2711 args
->enabled_channels
= 0xf;
2712 args
->valid_mask
= 0;
2714 args
->target
= V_008DFC_SQ_EXP_POS
+ 2 + reg_index
;
2719 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
2723 if (so
->num_outputs
)
2724 fprintf(stderr
, "STREAMOUT\n");
2726 for (i
= 0; i
< so
->num_outputs
; i
++) {
2727 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
2728 so
->output
[i
].start_component
;
2729 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2730 i
, so
->output
[i
].output_buffer
,
2731 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
2732 so
->output
[i
].register_index
,
2733 mask
& 1 ? "x" : "",
2734 mask
& 2 ? "y" : "",
2735 mask
& 4 ? "z" : "",
2736 mask
& 8 ? "w" : "");
2740 static void emit_streamout_output(struct si_shader_context
*ctx
,
2741 LLVMValueRef
const *so_buffers
,
2742 LLVMValueRef
const *so_write_offsets
,
2743 struct pipe_stream_output
*stream_out
,
2744 struct si_shader_output_values
*shader_out
)
2746 unsigned buf_idx
= stream_out
->output_buffer
;
2747 unsigned start
= stream_out
->start_component
;
2748 unsigned num_comps
= stream_out
->num_components
;
2749 LLVMValueRef out
[4];
2751 assert(num_comps
&& num_comps
<= 4);
2752 if (!num_comps
|| num_comps
> 4)
2755 /* Load the output as int. */
2756 for (int j
= 0; j
< num_comps
; j
++) {
2757 assert(stream_out
->stream
== shader_out
->vertex_stream
[start
+ j
]);
2759 out
[j
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ j
]);
2762 /* Pack the output. */
2763 LLVMValueRef vdata
= NULL
;
2765 switch (num_comps
) {
2766 case 1: /* as i32 */
2769 case 2: /* as v2i32 */
2770 case 3: /* as v4i32 (aligned to 4) */
2771 case 4: /* as v4i32 */
2772 vdata
= LLVMGetUndef(LLVMVectorType(ctx
->i32
, util_next_power_of_two(num_comps
)));
2773 for (int j
= 0; j
< num_comps
; j
++) {
2774 vdata
= LLVMBuildInsertElement(ctx
->ac
.builder
, vdata
, out
[j
],
2775 LLVMConstInt(ctx
->i32
, j
, 0), "");
2780 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf_idx
],
2782 so_write_offsets
[buf_idx
],
2784 stream_out
->dst_offset
* 4, 1, 1, true, false);
2788 * Write streamout data to buffers for vertex stream @p stream (different
2789 * vertex streams can occur for GS copy shaders).
2791 static void si_llvm_emit_streamout(struct si_shader_context
*ctx
,
2792 struct si_shader_output_values
*outputs
,
2793 unsigned noutput
, unsigned stream
)
2795 struct si_shader_selector
*sel
= ctx
->shader
->selector
;
2796 struct pipe_stream_output_info
*so
= &sel
->so
;
2797 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2799 struct lp_build_if_state if_ctx
;
2801 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2802 LLVMValueRef so_vtx_count
=
2803 si_unpack_param(ctx
, ctx
->param_streamout_config
, 16, 7);
2805 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2807 /* can_emit = tid < so_vtx_count; */
2808 LLVMValueRef can_emit
=
2809 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
2811 /* Emit the streamout code conditionally. This actually avoids
2812 * out-of-bounds buffer access. The hw tells us via the SGPR
2813 * (so_vtx_count) which threads are allowed to emit streamout data. */
2814 lp_build_if(&if_ctx
, &ctx
->gallivm
, can_emit
);
2816 /* The buffer offset is computed as follows:
2817 * ByteOffset = streamout_offset[buffer_id]*4 +
2818 * (streamout_write_index + thread_id)*stride[buffer_id] +
2822 LLVMValueRef so_write_index
=
2823 LLVMGetParam(ctx
->main_fn
,
2824 ctx
->param_streamout_write_index
);
2826 /* Compute (streamout_write_index + thread_id). */
2827 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
2829 /* Load the descriptor and compute the write offset for each
2830 * enabled buffer. */
2831 LLVMValueRef so_write_offset
[4] = {};
2832 LLVMValueRef so_buffers
[4];
2833 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
2834 ctx
->param_rw_buffers
);
2836 for (i
= 0; i
< 4; i
++) {
2840 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
,
2841 SI_VS_STREAMOUT_BUF0
+ i
, 0);
2843 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
2845 LLVMValueRef so_offset
= LLVMGetParam(ctx
->main_fn
,
2846 ctx
->param_streamout_offset
[i
]);
2847 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(ctx
->i32
, 4, 0), "");
2849 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
2850 LLVMConstInt(ctx
->i32
, so
->stride
[i
]*4, 0), "");
2851 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
2854 /* Write streamout data. */
2855 for (i
= 0; i
< so
->num_outputs
; i
++) {
2856 unsigned reg
= so
->output
[i
].register_index
;
2861 if (stream
!= so
->output
[i
].stream
)
2864 emit_streamout_output(ctx
, so_buffers
, so_write_offset
,
2865 &so
->output
[i
], &outputs
[reg
]);
2868 lp_build_endif(&if_ctx
);
2871 static void si_export_param(struct si_shader_context
*ctx
, unsigned index
,
2872 LLVMValueRef
*values
)
2874 struct ac_export_args args
;
2876 si_llvm_init_export_args(ctx
, values
,
2877 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2878 ac_build_export(&ctx
->ac
, &args
);
2881 static void si_build_param_exports(struct si_shader_context
*ctx
,
2882 struct si_shader_output_values
*outputs
,
2885 struct si_shader
*shader
= ctx
->shader
;
2886 unsigned param_count
= 0;
2888 for (unsigned i
= 0; i
< noutput
; i
++) {
2889 unsigned semantic_name
= outputs
[i
].semantic_name
;
2890 unsigned semantic_index
= outputs
[i
].semantic_index
;
2892 if (outputs
[i
].vertex_stream
[0] != 0 &&
2893 outputs
[i
].vertex_stream
[1] != 0 &&
2894 outputs
[i
].vertex_stream
[2] != 0 &&
2895 outputs
[i
].vertex_stream
[3] != 0)
2898 switch (semantic_name
) {
2899 case TGSI_SEMANTIC_LAYER
:
2900 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2901 case TGSI_SEMANTIC_CLIPDIST
:
2902 case TGSI_SEMANTIC_COLOR
:
2903 case TGSI_SEMANTIC_BCOLOR
:
2904 case TGSI_SEMANTIC_PRIMID
:
2905 case TGSI_SEMANTIC_FOG
:
2906 case TGSI_SEMANTIC_TEXCOORD
:
2907 case TGSI_SEMANTIC_GENERIC
:
2913 if ((semantic_name
!= TGSI_SEMANTIC_GENERIC
||
2914 semantic_index
< SI_MAX_IO_GENERIC
) &&
2915 shader
->key
.opt
.kill_outputs
&
2916 (1ull << si_shader_io_get_unique_index(semantic_name
,
2917 semantic_index
, true)))
2920 si_export_param(ctx
, param_count
, outputs
[i
].values
);
2922 assert(i
< ARRAY_SIZE(shader
->info
.vs_output_param_offset
));
2923 shader
->info
.vs_output_param_offset
[i
] = param_count
++;
2926 shader
->info
.nr_param_exports
= param_count
;
2929 /* Generate export instructions for hardware VS shader stage */
2930 static void si_llvm_export_vs(struct si_shader_context
*ctx
,
2931 struct si_shader_output_values
*outputs
,
2934 struct si_shader
*shader
= ctx
->shader
;
2935 struct ac_export_args pos_args
[4] = {};
2936 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2940 /* Build position exports. */
2941 for (i
= 0; i
< noutput
; i
++) {
2942 switch (outputs
[i
].semantic_name
) {
2943 case TGSI_SEMANTIC_POSITION
:
2944 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2945 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2947 case TGSI_SEMANTIC_PSIZE
:
2948 psize_value
= outputs
[i
].values
[0];
2950 case TGSI_SEMANTIC_LAYER
:
2951 layer_value
= outputs
[i
].values
[0];
2953 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2954 viewport_index_value
= outputs
[i
].values
[0];
2956 case TGSI_SEMANTIC_EDGEFLAG
:
2957 edgeflag_value
= outputs
[i
].values
[0];
2959 case TGSI_SEMANTIC_CLIPDIST
:
2960 if (!shader
->key
.opt
.clip_disable
) {
2961 unsigned index
= 2 + outputs
[i
].semantic_index
;
2962 si_llvm_init_export_args(ctx
, outputs
[i
].values
,
2963 V_008DFC_SQ_EXP_POS
+ index
,
2967 case TGSI_SEMANTIC_CLIPVERTEX
:
2968 if (!shader
->key
.opt
.clip_disable
) {
2969 si_llvm_emit_clipvertex(ctx
, pos_args
,
2976 /* We need to add the position output manually if it's missing. */
2977 if (!pos_args
[0].out
[0]) {
2978 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2979 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2980 pos_args
[0].done
= 0; /* last export? */
2981 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2982 pos_args
[0].compr
= 0; /* COMPR flag */
2983 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2984 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2985 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2986 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2989 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2990 if (shader
->selector
->info
.writes_psize
||
2991 shader
->selector
->info
.writes_edgeflag
||
2992 shader
->selector
->info
.writes_viewport_index
||
2993 shader
->selector
->info
.writes_layer
) {
2994 pos_args
[1].enabled_channels
= shader
->selector
->info
.writes_psize
|
2995 (shader
->selector
->info
.writes_edgeflag
<< 1) |
2996 (shader
->selector
->info
.writes_layer
<< 2);
2998 pos_args
[1].valid_mask
= 0; /* EXEC mask */
2999 pos_args
[1].done
= 0; /* last export? */
3000 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
3001 pos_args
[1].compr
= 0; /* COMPR flag */
3002 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
3003 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
3004 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
3005 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
3007 if (shader
->selector
->info
.writes_psize
)
3008 pos_args
[1].out
[0] = psize_value
;
3010 if (shader
->selector
->info
.writes_edgeflag
) {
3011 /* The output is a float, but the hw expects an integer
3012 * with the first bit containing the edge flag. */
3013 edgeflag_value
= LLVMBuildFPToUI(ctx
->ac
.builder
,
3016 edgeflag_value
= ac_build_umin(&ctx
->ac
,
3020 /* The LLVM intrinsic expects a float. */
3021 pos_args
[1].out
[1] = ac_to_float(&ctx
->ac
, edgeflag_value
);
3024 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3025 /* GFX9 has the layer in out.z[10:0] and the viewport
3026 * index in out.z[19:16].
3028 if (shader
->selector
->info
.writes_layer
)
3029 pos_args
[1].out
[2] = layer_value
;
3031 if (shader
->selector
->info
.writes_viewport_index
) {
3032 LLVMValueRef v
= viewport_index_value
;
3034 v
= ac_to_integer(&ctx
->ac
, v
);
3035 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
3036 LLVMConstInt(ctx
->i32
, 16, 0), "");
3037 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
3038 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
3039 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
3040 pos_args
[1].enabled_channels
|= 1 << 2;
3043 if (shader
->selector
->info
.writes_layer
)
3044 pos_args
[1].out
[2] = layer_value
;
3046 if (shader
->selector
->info
.writes_viewport_index
) {
3047 pos_args
[1].out
[3] = viewport_index_value
;
3048 pos_args
[1].enabled_channels
|= 1 << 3;
3053 for (i
= 0; i
< 4; i
++)
3054 if (pos_args
[i
].out
[0])
3055 shader
->info
.nr_pos_exports
++;
3058 for (i
= 0; i
< 4; i
++) {
3059 if (!pos_args
[i
].out
[0])
3062 /* Specify the target we are exporting */
3063 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
3065 if (pos_idx
== shader
->info
.nr_pos_exports
)
3066 /* Specify that this is the last export */
3067 pos_args
[i
].done
= 1;
3069 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
3072 /* Build parameter exports. */
3073 si_build_param_exports(ctx
, outputs
, noutput
);
3077 * Forward all outputs from the vertex shader to the TES. This is only used
3078 * for the fixed function TCS.
3080 static void si_copy_tcs_inputs(struct lp_build_tgsi_context
*bld_base
)
3082 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3083 LLVMValueRef invocation_id
, buffer
, buffer_offset
;
3084 LLVMValueRef lds_vertex_stride
, lds_vertex_offset
, lds_base
;
3087 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3088 buffer
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3089 buffer_offset
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3091 lds_vertex_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3092 lds_vertex_offset
= LLVMBuildMul(ctx
->ac
.builder
, invocation_id
,
3093 lds_vertex_stride
, "");
3094 lds_base
= get_tcs_in_current_patch_offset(ctx
);
3095 lds_base
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
, lds_vertex_offset
, "");
3097 inputs
= ctx
->shader
->key
.mono
.u
.ff_tcs_inputs_to_copy
;
3099 unsigned i
= u_bit_scan64(&inputs
);
3101 LLVMValueRef lds_ptr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3102 LLVMConstInt(ctx
->i32
, 4 * i
, 0),
3105 LLVMValueRef buffer_addr
= get_tcs_tes_buffer_address(ctx
,
3106 get_rel_patch_id(ctx
),
3108 LLVMConstInt(ctx
->i32
, i
, 0));
3110 LLVMValueRef value
= lds_load(bld_base
, ctx
->ac
.i32
, ~0,
3113 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, value
, 4, buffer_addr
,
3114 buffer_offset
, 0, 1, 0, true, false);
3118 static void si_write_tess_factors(struct lp_build_tgsi_context
*bld_base
,
3119 LLVMValueRef rel_patch_id
,
3120 LLVMValueRef invocation_id
,
3121 LLVMValueRef tcs_out_current_patch_data_offset
,
3122 LLVMValueRef invoc0_tf_outer
[4],
3123 LLVMValueRef invoc0_tf_inner
[2])
3125 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3126 struct si_shader
*shader
= ctx
->shader
;
3127 unsigned tess_inner_index
, tess_outer_index
;
3128 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
3129 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3130 unsigned stride
, outer_comps
, inner_comps
, i
, offset
;
3131 struct lp_build_if_state if_ctx
, inner_if_ctx
;
3133 /* Add a barrier before loading tess factors from LDS. */
3134 if (!shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
)
3135 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
3137 /* Do this only for invocation 0, because the tess levels are per-patch,
3140 * This can't jump, because invocation 0 executes this. It should
3141 * at least mask out the loads and stores for other invocations.
3143 lp_build_if(&if_ctx
, &ctx
->gallivm
,
3144 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3145 invocation_id
, ctx
->i32_0
, ""));
3147 /* Determine the layout of one tess factor element in the buffer. */
3148 switch (shader
->key
.part
.tcs
.epilog
.prim_mode
) {
3149 case PIPE_PRIM_LINES
:
3150 stride
= 2; /* 2 dwords, 1 vec2 store */
3154 case PIPE_PRIM_TRIANGLES
:
3155 stride
= 4; /* 4 dwords, 1 vec4 store */
3159 case PIPE_PRIM_QUADS
:
3160 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3169 for (i
= 0; i
< 4; i
++) {
3170 inner
[i
] = LLVMGetUndef(ctx
->i32
);
3171 outer
[i
] = LLVMGetUndef(ctx
->i32
);
3174 if (shader
->key
.part
.tcs
.epilog
.invoc0_tess_factors_are_def
) {
3175 /* Tess factors are in VGPRs. */
3176 for (i
= 0; i
< outer_comps
; i
++)
3177 outer
[i
] = out
[i
] = invoc0_tf_outer
[i
];
3178 for (i
= 0; i
< inner_comps
; i
++)
3179 inner
[i
] = out
[outer_comps
+i
] = invoc0_tf_inner
[i
];
3181 /* Load tess_inner and tess_outer from LDS.
3182 * Any invocation can write them, so we can't get them from a temporary.
3184 tess_inner_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0);
3185 tess_outer_index
= si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0);
3187 lds_base
= tcs_out_current_patch_data_offset
;
3188 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3189 LLVMConstInt(ctx
->i32
,
3190 tess_inner_index
* 4, 0), "");
3191 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3192 LLVMConstInt(ctx
->i32
,
3193 tess_outer_index
* 4, 0), "");
3195 for (i
= 0; i
< outer_comps
; i
++) {
3197 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_outer
);
3199 for (i
= 0; i
< inner_comps
; i
++) {
3200 inner
[i
] = out
[outer_comps
+i
] =
3201 lds_load(bld_base
, ctx
->ac
.i32
, i
, lds_inner
);
3205 if (shader
->key
.part
.tcs
.epilog
.prim_mode
== PIPE_PRIM_LINES
) {
3206 /* For isolines, the hardware expects tess factors in the
3207 * reverse order from what GLSL / TGSI specify.
3209 LLVMValueRef tmp
= out
[0];
3214 /* Convert the outputs to vectors for stores. */
3215 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3219 vec1
= ac_build_gather_values(&ctx
->ac
, out
+4, stride
- 4);
3221 /* Get the buffer. */
3222 buffer
= get_tess_ring_descriptor(ctx
, TCS_FACTOR_RING
);
3224 /* Get the offset. */
3225 tf_base
= LLVMGetParam(ctx
->main_fn
,
3226 ctx
->param_tcs_factor_offset
);
3227 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3228 LLVMConstInt(ctx
->i32
, 4 * stride
, 0), "");
3230 lp_build_if(&inner_if_ctx
, &ctx
->gallivm
,
3231 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3232 rel_patch_id
, ctx
->i32_0
, ""));
3234 /* Store the dynamic HS control word. */
3236 if (ctx
->screen
->info
.chip_class
<= VI
) {
3237 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3238 LLVMConstInt(ctx
->i32
, 0x80000000, 0),
3239 1, ctx
->i32_0
, tf_base
,
3240 offset
, 1, 0, true, false);
3244 lp_build_endif(&inner_if_ctx
);
3246 /* Store the tessellation factors. */
3247 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3248 MIN2(stride
, 4), byteoffset
, tf_base
,
3249 offset
, 1, 0, true, false);
3252 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3253 stride
- 4, byteoffset
, tf_base
,
3254 offset
, 1, 0, true, false);
3256 /* Store the tess factors into the offchip buffer if TES reads them. */
3257 if (shader
->key
.part
.tcs
.epilog
.tes_reads_tess_factors
) {
3258 LLVMValueRef buf
, base
, inner_vec
, outer_vec
, tf_outer_offset
;
3259 LLVMValueRef tf_inner_offset
;
3260 unsigned param_outer
, param_inner
;
3262 buf
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TCS
);
3263 base
= LLVMGetParam(ctx
->main_fn
, ctx
->param_tcs_offchip_offset
);
3265 param_outer
= si_shader_io_get_unique_index_patch(
3266 TGSI_SEMANTIC_TESSOUTER
, 0);
3267 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3268 LLVMConstInt(ctx
->i32
, param_outer
, 0));
3270 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3271 util_next_power_of_two(outer_comps
));
3273 ac_build_buffer_store_dword(&ctx
->ac
, buf
, outer_vec
,
3274 outer_comps
, tf_outer_offset
,
3275 base
, 0, 1, 0, true, false);
3277 param_inner
= si_shader_io_get_unique_index_patch(
3278 TGSI_SEMANTIC_TESSINNER
, 0);
3279 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, rel_patch_id
, NULL
,
3280 LLVMConstInt(ctx
->i32
, param_inner
, 0));
3282 inner_vec
= inner_comps
== 1 ? inner
[0] :
3283 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3284 ac_build_buffer_store_dword(&ctx
->ac
, buf
, inner_vec
,
3285 inner_comps
, tf_inner_offset
,
3286 base
, 0, 1, 0, true, false);
3290 lp_build_endif(&if_ctx
);
3294 si_insert_input_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3295 unsigned param
, unsigned return_index
)
3297 return LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3298 LLVMGetParam(ctx
->main_fn
, param
),
3303 si_insert_input_ret_float(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3304 unsigned param
, unsigned return_index
)
3306 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3307 LLVMValueRef p
= LLVMGetParam(ctx
->main_fn
, param
);
3309 return LLVMBuildInsertValue(builder
, ret
,
3310 ac_to_float(&ctx
->ac
, p
),
3315 si_insert_input_ptr(struct si_shader_context
*ctx
, LLVMValueRef ret
,
3316 unsigned param
, unsigned return_index
)
3318 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3319 LLVMValueRef ptr
, lo
, hi
;
3321 if (HAVE_32BIT_POINTERS
) {
3322 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
3323 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i32
, "");
3324 return LLVMBuildInsertValue(builder
, ret
, ptr
, return_index
, "");
3327 ptr
= LLVMGetParam(ctx
->main_fn
, param
);
3328 ptr
= LLVMBuildPtrToInt(builder
, ptr
, ctx
->i64
, "");
3329 ptr
= LLVMBuildBitCast(builder
, ptr
, ctx
->v2i32
, "");
3330 lo
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_0
, "");
3331 hi
= LLVMBuildExtractElement(builder
, ptr
, ctx
->i32_1
, "");
3332 ret
= LLVMBuildInsertValue(builder
, ret
, lo
, return_index
, "");
3333 return LLVMBuildInsertValue(builder
, ret
, hi
, return_index
+ 1, "");
3336 /* This only writes the tessellation factor levels. */
3337 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi
*abi
,
3338 unsigned max_outputs
,
3339 LLVMValueRef
*addrs
)
3341 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3342 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
3343 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3344 LLVMValueRef rel_patch_id
, invocation_id
, tf_lds_offset
;
3346 si_copy_tcs_inputs(bld_base
);
3348 rel_patch_id
= get_rel_patch_id(ctx
);
3349 invocation_id
= unpack_llvm_param(ctx
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3350 tf_lds_offset
= get_tcs_out_current_patch_data_offset(ctx
);
3352 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3353 LLVMBasicBlockRef blocks
[2] = {
3354 LLVMGetInsertBlock(builder
),
3355 ctx
->merged_wrap_if_state
.entry_block
3357 LLVMValueRef values
[2];
3359 lp_build_endif(&ctx
->merged_wrap_if_state
);
3361 values
[0] = rel_patch_id
;
3362 values
[1] = LLVMGetUndef(ctx
->i32
);
3363 rel_patch_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3365 values
[0] = tf_lds_offset
;
3366 values
[1] = LLVMGetUndef(ctx
->i32
);
3367 tf_lds_offset
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3369 values
[0] = invocation_id
;
3370 values
[1] = ctx
->i32_1
; /* cause the epilog to skip threads */
3371 invocation_id
= ac_build_phi(&ctx
->ac
, ctx
->i32
, 2, values
, blocks
);
3374 /* Return epilog parameters from this function. */
3375 LLVMValueRef ret
= ctx
->return_value
;
3378 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3379 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3380 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3381 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3382 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3383 /* Tess offchip and tess factor offsets are at the beginning. */
3384 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3385 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3386 vgpr
= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
+ 1;
3388 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3389 GFX6_SGPR_TCS_OFFCHIP_LAYOUT
);
3390 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3391 GFX6_SGPR_TCS_OUT_LAYOUT
);
3392 /* Tess offchip and tess factor offsets are after user SGPRs. */
3393 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
,
3394 GFX6_TCS_NUM_USER_SGPR
);
3395 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
,
3396 GFX6_TCS_NUM_USER_SGPR
+ 1);
3397 vgpr
= GFX6_TCS_NUM_USER_SGPR
+ 2;
3401 rel_patch_id
= ac_to_float(&ctx
->ac
, rel_patch_id
);
3402 invocation_id
= ac_to_float(&ctx
->ac
, invocation_id
);
3403 tf_lds_offset
= ac_to_float(&ctx
->ac
, tf_lds_offset
);
3405 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3406 * the invocation_id output does not alias the tcs_rel_ids input,
3407 * which saves a V_MOV on gfx9.
3411 ret
= LLVMBuildInsertValue(builder
, ret
, rel_patch_id
, vgpr
++, "");
3412 ret
= LLVMBuildInsertValue(builder
, ret
, invocation_id
, vgpr
++, "");
3414 if (ctx
->shader
->selector
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
3415 vgpr
++; /* skip the tess factor LDS offset */
3416 for (unsigned i
= 0; i
< 6; i
++) {
3417 LLVMValueRef value
=
3418 LLVMBuildLoad(builder
, ctx
->invoc0_tess_factors
[i
], "");
3419 value
= ac_to_float(&ctx
->ac
, value
);
3420 ret
= LLVMBuildInsertValue(builder
, ret
, value
, vgpr
++, "");
3423 ret
= LLVMBuildInsertValue(builder
, ret
, tf_lds_offset
, vgpr
++, "");
3425 ctx
->return_value
= ret
;
3428 /* Pass TCS inputs from LS to TCS on GFX9. */
3429 static void si_set_ls_return_value_for_tcs(struct si_shader_context
*ctx
)
3431 LLVMValueRef ret
= ctx
->return_value
;
3433 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3434 if (HAVE_32BIT_POINTERS
)
3435 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3436 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_offset
, 2);
3437 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3438 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_factor_offset
, 4);
3439 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3441 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3442 8 + SI_SGPR_RW_BUFFERS
);
3443 ret
= si_insert_input_ptr(ctx
, ret
,
3444 ctx
->param_bindless_samplers_and_images
,
3445 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3447 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_vs_state_bits
,
3448 8 + SI_SGPR_VS_STATE_BITS
);
3450 #if !HAVE_32BIT_POINTERS
3451 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_vs_state_bits
+ 1,
3452 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
);
3455 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_offchip_layout
,
3456 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT
);
3457 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_offsets
,
3458 8 + GFX9_SGPR_TCS_OUT_OFFSETS
);
3459 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_tcs_out_lds_layout
,
3460 8 + GFX9_SGPR_TCS_OUT_LAYOUT
);
3462 unsigned vgpr
= 8 + GFX9_TCS_NUM_USER_SGPR
;
3463 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3464 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_patch_id
),
3466 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
3467 ac_to_float(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
),
3469 ctx
->return_value
= ret
;
3472 /* Pass GS inputs from ES to GS on GFX9. */
3473 static void si_set_es_return_value_for_gs(struct si_shader_context
*ctx
)
3475 LLVMValueRef ret
= ctx
->return_value
;
3477 ret
= si_insert_input_ptr(ctx
, ret
, 0, 0);
3478 if (HAVE_32BIT_POINTERS
)
3479 ret
= si_insert_input_ptr(ctx
, ret
, 1, 1);
3480 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_gs2vs_offset
, 2);
3481 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_wave_info
, 3);
3482 ret
= si_insert_input_ret(ctx
, ret
, ctx
->param_merged_scratch_offset
, 5);
3484 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_rw_buffers
,
3485 8 + SI_SGPR_RW_BUFFERS
);
3486 ret
= si_insert_input_ptr(ctx
, ret
,
3487 ctx
->param_bindless_samplers_and_images
,
3488 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
);
3490 #if !HAVE_32BIT_POINTERS
3491 ret
= si_insert_input_ptr(ctx
, ret
, ctx
->param_vs_state_bits
+ 1,
3492 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
);
3496 if (ctx
->type
== PIPE_SHADER_VERTEX
)
3497 vgpr
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
3499 vgpr
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
3501 for (unsigned i
= 0; i
< 5; i
++) {
3502 unsigned param
= ctx
->param_gs_vtx01_offset
+ i
;
3503 ret
= si_insert_input_ret_float(ctx
, ret
, param
, vgpr
++);
3505 ctx
->return_value
= ret
;
3508 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi
*abi
,
3509 unsigned max_outputs
,
3510 LLVMValueRef
*addrs
)
3512 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3513 struct si_shader
*shader
= ctx
->shader
;
3514 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3516 LLVMValueRef vertex_id
= LLVMGetParam(ctx
->main_fn
,
3517 ctx
->param_rel_auto_id
);
3518 LLVMValueRef vertex_dw_stride
= get_tcs_in_vertex_dw_stride(ctx
);
3519 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3520 vertex_dw_stride
, "");
3522 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3523 * its inputs from it. */
3524 for (i
= 0; i
< info
->num_outputs
; i
++) {
3525 unsigned name
= info
->output_semantic_name
[i
];
3526 unsigned index
= info
->output_semantic_index
[i
];
3528 /* The ARB_shader_viewport_layer_array spec contains the
3531 * 2) What happens if gl_ViewportIndex or gl_Layer is
3532 * written in the vertex shader and a geometry shader is
3535 * RESOLVED: The value written by the last vertex processing
3536 * stage is used. If the last vertex processing stage
3537 * (vertex, tessellation evaluation or geometry) does not
3538 * statically assign to gl_ViewportIndex or gl_Layer, index
3539 * or layer zero is assumed.
3541 * So writes to those outputs in VS-as-LS are simply ignored.
3543 if (name
== TGSI_SEMANTIC_LAYER
||
3544 name
== TGSI_SEMANTIC_VIEWPORT_INDEX
)
3547 int param
= si_shader_io_get_unique_index(name
, index
, false);
3548 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3549 LLVMConstInt(ctx
->i32
, param
* 4, 0), "");
3551 for (chan
= 0; chan
< 4; chan
++) {
3552 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3555 lds_store(ctx
, chan
, dw_addr
,
3556 LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], ""));
3560 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3561 si_set_ls_return_value_for_tcs(ctx
);
3564 static void si_llvm_emit_es_epilogue(struct ac_shader_abi
*abi
,
3565 unsigned max_outputs
,
3566 LLVMValueRef
*addrs
)
3568 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3569 struct si_shader
*es
= ctx
->shader
;
3570 struct tgsi_shader_info
*info
= &es
->selector
->info
;
3571 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
3572 ctx
->param_es2gs_offset
);
3573 LLVMValueRef lds_base
= NULL
;
3577 if (ctx
->screen
->info
.chip_class
>= GFX9
&& info
->num_outputs
) {
3578 unsigned itemsize_dw
= es
->selector
->esgs_itemsize
/ 4;
3579 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3580 LLVMValueRef wave_idx
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 24, 4);
3581 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3582 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3583 LLVMConstInt(ctx
->i32
, 64, false), ""), "");
3584 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3585 LLVMConstInt(ctx
->i32
, itemsize_dw
, 0), "");
3588 for (i
= 0; i
< info
->num_outputs
; i
++) {
3591 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
3592 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
3595 param
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
3596 info
->output_semantic_index
[i
], false);
3598 for (chan
= 0; chan
< 4; chan
++) {
3599 if (!(info
->output_usagemask
[i
] & (1 << chan
)))
3602 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
3603 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3605 /* GFX9 has the ESGS ring in LDS. */
3606 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
3607 lds_store(ctx
, param
* 4 + chan
, lds_base
, out_val
);
3611 ac_build_buffer_store_dword(&ctx
->ac
,
3613 out_val
, 1, NULL
, soffset
,
3614 (4 * param
+ chan
) * 4,
3619 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3620 si_set_es_return_value_for_gs(ctx
);
3623 static LLVMValueRef
si_get_gs_wave_id(struct si_shader_context
*ctx
)
3625 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3626 return si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 16, 8);
3628 return LLVMGetParam(ctx
->main_fn
, ctx
->param_gs_wave_id
);
3631 static void emit_gs_epilogue(struct si_shader_context
*ctx
)
3633 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
,
3634 si_get_gs_wave_id(ctx
));
3636 if (ctx
->screen
->info
.chip_class
>= GFX9
)
3637 lp_build_endif(&ctx
->merged_wrap_if_state
);
3640 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi
*abi
,
3641 unsigned max_outputs
,
3642 LLVMValueRef
*addrs
)
3644 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3645 struct tgsi_shader_info UNUSED
*info
= &ctx
->shader
->selector
->info
;
3647 assert(info
->num_outputs
<= max_outputs
);
3649 emit_gs_epilogue(ctx
);
3652 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
3654 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3655 emit_gs_epilogue(ctx
);
3658 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi
*abi
,
3659 unsigned max_outputs
,
3660 LLVMValueRef
*addrs
)
3662 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3663 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
3664 struct si_shader_output_values
*outputs
= NULL
;
3667 assert(!ctx
->shader
->is_gs_copy_shader
);
3668 assert(info
->num_outputs
<= max_outputs
);
3670 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
3672 /* Vertex color clamping.
3674 * This uses a state constant loaded in a user data SGPR and
3675 * an IF statement is added that clamps all colors if the constant
3678 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
3679 struct lp_build_if_state if_ctx
;
3680 LLVMValueRef cond
= NULL
;
3681 LLVMValueRef addr
, val
;
3683 for (i
= 0; i
< info
->num_outputs
; i
++) {
3684 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
3685 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
3688 /* We've found a color. */
3690 /* The state is in the first bit of the user SGPR. */
3691 cond
= LLVMGetParam(ctx
->main_fn
,
3692 ctx
->param_vs_state_bits
);
3693 cond
= LLVMBuildTrunc(ctx
->ac
.builder
, cond
,
3695 lp_build_if(&if_ctx
, &ctx
->gallivm
, cond
);
3698 for (j
= 0; j
< 4; j
++) {
3699 addr
= addrs
[4 * i
+ j
];
3700 val
= LLVMBuildLoad(ctx
->ac
.builder
, addr
, "");
3701 val
= ac_build_clamp(&ctx
->ac
, val
);
3702 LLVMBuildStore(ctx
->ac
.builder
, val
, addr
);
3707 lp_build_endif(&if_ctx
);
3710 for (i
= 0; i
< info
->num_outputs
; i
++) {
3711 outputs
[i
].semantic_name
= info
->output_semantic_name
[i
];
3712 outputs
[i
].semantic_index
= info
->output_semantic_index
[i
];
3714 for (j
= 0; j
< 4; j
++) {
3715 outputs
[i
].values
[j
] =
3716 LLVMBuildLoad(ctx
->ac
.builder
,
3719 outputs
[i
].vertex_stream
[j
] =
3720 (info
->output_streams
[i
] >> (2 * j
)) & 3;
3724 if (ctx
->shader
->selector
->so
.num_outputs
)
3725 si_llvm_emit_streamout(ctx
, outputs
, i
, 0);
3727 /* Export PrimitiveID. */
3728 if (ctx
->shader
->key
.mono
.u
.vs_export_prim_id
) {
3729 outputs
[i
].semantic_name
= TGSI_SEMANTIC_PRIMID
;
3730 outputs
[i
].semantic_index
= 0;
3731 outputs
[i
].values
[0] = ac_to_float(&ctx
->ac
, get_primitive_id(ctx
, 0));
3732 for (j
= 1; j
< 4; j
++)
3733 outputs
[i
].values
[j
] = LLVMConstReal(ctx
->f32
, 0);
3735 memset(outputs
[i
].vertex_stream
, 0,
3736 sizeof(outputs
[i
].vertex_stream
));
3740 si_llvm_export_vs(ctx
, outputs
, i
);
3744 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context
*bld_base
)
3746 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3748 ctx
->abi
.emit_outputs(&ctx
->abi
, RADEON_LLVM_MAX_OUTPUTS
,
3749 &ctx
->outputs
[0][0]);
3752 struct si_ps_exports
{
3754 struct ac_export_args args
[10];
3757 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
3758 LLVMValueRef depth
, LLVMValueRef stencil
,
3759 LLVMValueRef samplemask
, struct si_ps_exports
*exp
)
3761 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3762 struct ac_export_args args
;
3764 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3766 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3769 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
3770 LLVMValueRef
*color
, unsigned index
,
3771 unsigned samplemask_param
,
3772 bool is_last
, struct si_ps_exports
*exp
)
3774 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3778 if (ctx
->shader
->key
.part
.ps
.epilog
.clamp_color
)
3779 for (i
= 0; i
< 4; i
++)
3780 color
[i
] = ac_build_clamp(&ctx
->ac
, color
[i
]);
3783 if (ctx
->shader
->key
.part
.ps
.epilog
.alpha_to_one
)
3784 color
[3] = ctx
->ac
.f32_1
;
3788 ctx
->shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
)
3789 si_alpha_test(bld_base
, color
[3]);
3791 /* Line & polygon smoothing */
3792 if (ctx
->shader
->key
.part
.ps
.epilog
.poly_line_smoothing
)
3793 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3],
3796 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3797 if (ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
> 0) {
3798 struct ac_export_args args
[8];
3801 /* Get the export arguments, also find out what the last one is. */
3802 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3803 si_llvm_init_export_args(ctx
, color
,
3804 V_008DFC_SQ_EXP_MRT
+ c
, &args
[c
]);
3805 if (args
[c
].enabled_channels
)
3809 /* Emit all exports. */
3810 for (c
= 0; c
<= ctx
->shader
->key
.part
.ps
.epilog
.last_cbuf
; c
++) {
3811 if (is_last
&& last
== c
) {
3812 args
[c
].valid_mask
= 1; /* whether the EXEC mask is valid */
3813 args
[c
].done
= 1; /* DONE bit */
3814 } else if (!args
[c
].enabled_channels
)
3815 continue; /* unnecessary NULL export */
3817 memcpy(&exp
->args
[exp
->num
++], &args
[c
], sizeof(args
[c
]));
3820 struct ac_export_args args
;
3823 si_llvm_init_export_args(ctx
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
3826 args
.valid_mask
= 1; /* whether the EXEC mask is valid */
3827 args
.done
= 1; /* DONE bit */
3828 } else if (!args
.enabled_channels
)
3829 return; /* unnecessary NULL export */
3831 memcpy(&exp
->args
[exp
->num
++], &args
, sizeof(args
));
3835 static void si_emit_ps_exports(struct si_shader_context
*ctx
,
3836 struct si_ps_exports
*exp
)
3838 for (unsigned i
= 0; i
< exp
->num
; i
++)
3839 ac_build_export(&ctx
->ac
, &exp
->args
[i
]);
3843 * Return PS outputs in this order:
3845 * v[0:3] = color0.xyzw
3846 * v[4:7] = color1.xyzw
3851 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3853 * The alpha-ref SGPR is returned via its original location.
3855 static void si_llvm_return_fs_outputs(struct ac_shader_abi
*abi
,
3856 unsigned max_outputs
,
3857 LLVMValueRef
*addrs
)
3859 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
3860 struct si_shader
*shader
= ctx
->shader
;
3861 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3862 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3863 unsigned i
, j
, first_vgpr
, vgpr
;
3865 LLVMValueRef color
[8][4] = {};
3866 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3869 if (ctx
->postponed_kill
)
3870 ac_build_kill_if_false(&ctx
->ac
, LLVMBuildLoad(builder
, ctx
->postponed_kill
, ""));
3872 /* Read the output values. */
3873 for (i
= 0; i
< info
->num_outputs
; i
++) {
3874 unsigned semantic_name
= info
->output_semantic_name
[i
];
3875 unsigned semantic_index
= info
->output_semantic_index
[i
];
3877 switch (semantic_name
) {
3878 case TGSI_SEMANTIC_COLOR
:
3879 assert(semantic_index
< 8);
3880 for (j
= 0; j
< 4; j
++) {
3881 LLVMValueRef ptr
= addrs
[4 * i
+ j
];
3882 LLVMValueRef result
= LLVMBuildLoad(builder
, ptr
, "");
3883 color
[semantic_index
][j
] = result
;
3886 case TGSI_SEMANTIC_POSITION
:
3887 depth
= LLVMBuildLoad(builder
,
3888 addrs
[4 * i
+ 2], "");
3890 case TGSI_SEMANTIC_STENCIL
:
3891 stencil
= LLVMBuildLoad(builder
,
3892 addrs
[4 * i
+ 1], "");
3894 case TGSI_SEMANTIC_SAMPLEMASK
:
3895 samplemask
= LLVMBuildLoad(builder
,
3896 addrs
[4 * i
+ 0], "");
3899 fprintf(stderr
, "Warning: SI unhandled fs output type:%d\n",
3904 /* Fill the return structure. */
3905 ret
= ctx
->return_value
;
3908 ret
= LLVMBuildInsertValue(builder
, ret
,
3909 ac_to_integer(&ctx
->ac
,
3910 LLVMGetParam(ctx
->main_fn
,
3911 SI_PARAM_ALPHA_REF
)),
3912 SI_SGPR_ALPHA_REF
, "");
3915 first_vgpr
= vgpr
= SI_SGPR_ALPHA_REF
+ 1;
3916 for (i
= 0; i
< ARRAY_SIZE(color
); i
++) {
3920 for (j
= 0; j
< 4; j
++)
3921 ret
= LLVMBuildInsertValue(builder
, ret
, color
[i
][j
], vgpr
++, "");
3924 ret
= LLVMBuildInsertValue(builder
, ret
, depth
, vgpr
++, "");
3926 ret
= LLVMBuildInsertValue(builder
, ret
, stencil
, vgpr
++, "");
3928 ret
= LLVMBuildInsertValue(builder
, ret
, samplemask
, vgpr
++, "");
3930 /* Add the input sample mask for smoothing at the end. */
3931 if (vgpr
< first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
)
3932 vgpr
= first_vgpr
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
;
3933 ret
= LLVMBuildInsertValue(builder
, ret
,
3934 LLVMGetParam(ctx
->main_fn
,
3935 SI_PARAM_SAMPLE_COVERAGE
), vgpr
++, "");
3937 ctx
->return_value
= ret
;
3940 static void membar_emit(
3941 const struct lp_build_tgsi_action
*action
,
3942 struct lp_build_tgsi_context
*bld_base
,
3943 struct lp_build_emit_data
*emit_data
)
3945 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3946 LLVMValueRef src0
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
3947 unsigned flags
= LLVMConstIntGetZExtValue(src0
);
3948 unsigned waitcnt
= NOOP_WAITCNT
;
3950 if (flags
& TGSI_MEMBAR_THREAD_GROUP
)
3951 waitcnt
&= VM_CNT
& LGKM_CNT
;
3953 if (flags
& (TGSI_MEMBAR_ATOMIC_BUFFER
|
3954 TGSI_MEMBAR_SHADER_BUFFER
|
3955 TGSI_MEMBAR_SHADER_IMAGE
))
3958 if (flags
& TGSI_MEMBAR_SHARED
)
3959 waitcnt
&= LGKM_CNT
;
3961 if (waitcnt
!= NOOP_WAITCNT
)
3962 ac_build_waitcnt(&ctx
->ac
, waitcnt
);
3965 static void clock_emit(
3966 const struct lp_build_tgsi_action
*action
,
3967 struct lp_build_tgsi_context
*bld_base
,
3968 struct lp_build_emit_data
*emit_data
)
3970 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3971 LLVMValueRef tmp
= ac_build_shader_clock(&ctx
->ac
);
3973 emit_data
->output
[0] =
3974 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_0
, "");
3975 emit_data
->output
[1] =
3976 LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
, ctx
->i32_1
, "");
3979 static void si_llvm_emit_ddxy(
3980 const struct lp_build_tgsi_action
*action
,
3981 struct lp_build_tgsi_context
*bld_base
,
3982 struct lp_build_emit_data
*emit_data
)
3984 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
3985 unsigned opcode
= emit_data
->info
->opcode
;
3990 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3991 mask
= AC_TID_MASK_LEFT
;
3992 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3993 mask
= AC_TID_MASK_TOP
;
3995 mask
= AC_TID_MASK_TOP_LEFT
;
3997 /* for DDX we want to next X pixel, DDY next Y pixel. */
3998 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
4000 val
= ac_to_integer(&ctx
->ac
, emit_data
->args
[0]);
4001 val
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, val
);
4002 emit_data
->output
[emit_data
->chan
] = val
;
4006 * this takes an I,J coordinate pair,
4007 * and works out the X and Y derivatives.
4008 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4010 static LLVMValueRef
si_llvm_emit_ddxy_interp(
4011 struct lp_build_tgsi_context
*bld_base
,
4012 LLVMValueRef interp_ij
)
4014 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4015 LLVMValueRef result
[4], a
;
4018 for (i
= 0; i
< 2; i
++) {
4019 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
4020 LLVMConstInt(ctx
->i32
, i
, 0), "");
4021 result
[i
] = ac_build_ddxy(&ctx
->ac
, AC_TID_MASK_TOP_LEFT
, 1,
4022 ac_to_integer(&ctx
->ac
, a
)); /* DDX */
4023 result
[2+i
] = ac_build_ddxy(&ctx
->ac
, AC_TID_MASK_TOP_LEFT
, 2,
4024 ac_to_integer(&ctx
->ac
, a
)); /* DDY */
4027 return ac_build_gather_values(&ctx
->ac
, result
, 4);
4030 static void interp_fetch_args(
4031 struct lp_build_tgsi_context
*bld_base
,
4032 struct lp_build_emit_data
*emit_data
)
4034 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4035 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4037 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
4038 /* offset is in second src, first two channels */
4039 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
4042 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
4045 emit_data
->arg_count
= 2;
4046 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4047 LLVMValueRef sample_position
;
4048 LLVMValueRef sample_id
;
4049 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
4051 /* fetch sample ID, then fetch its sample position,
4052 * and place into first two channels.
4054 sample_id
= lp_build_emit_fetch(bld_base
,
4055 emit_data
->inst
, 1, TGSI_CHAN_X
);
4056 sample_id
= ac_to_integer(&ctx
->ac
, sample_id
);
4058 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4059 * Language 4.50 spec says about interpolateAtSample:
4061 * "Returns the value of the input interpolant variable at
4062 * the location of sample number sample. If multisample
4063 * buffers are not available, the input variable will be
4064 * evaluated at the center of the pixel. If sample sample
4065 * does not exist, the position used to interpolate the
4066 * input variable is undefined."
4068 * This means that sample_id values outside of the valid are
4069 * in fact valid input, and the usual mechanism for loading the
4070 * sample position doesn't work.
4072 if (ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
) {
4073 LLVMValueRef center
[4] = {
4074 LLVMConstReal(ctx
->f32
, 0.5),
4075 LLVMConstReal(ctx
->f32
, 0.5),
4080 sample_position
= ac_build_gather_values(&ctx
->ac
, center
, 4);
4082 sample_position
= load_sample_position(&ctx
->abi
, sample_id
);
4085 emit_data
->args
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
,
4089 emit_data
->args
[0] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[0], halfval
, "");
4090 emit_data
->args
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
,
4093 emit_data
->args
[1] = LLVMBuildFSub(ctx
->ac
.builder
, emit_data
->args
[1], halfval
, "");
4094 emit_data
->arg_count
= 2;
4098 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
4099 struct lp_build_tgsi_context
*bld_base
,
4100 struct lp_build_emit_data
*emit_data
)
4102 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4103 struct si_shader
*shader
= ctx
->shader
;
4104 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
4105 LLVMValueRef interp_param
;
4106 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
4107 const struct tgsi_full_src_register
*input
= &inst
->Src
[0];
4108 int input_base
, input_array_size
;
4111 LLVMValueRef prim_mask
= ctx
->abi
.prim_mask
;
4112 LLVMValueRef array_idx
;
4113 int interp_param_idx
;
4117 assert(input
->Register
.File
== TGSI_FILE_INPUT
);
4119 if (input
->Register
.Indirect
) {
4120 unsigned array_id
= input
->Indirect
.ArrayID
;
4123 input_base
= info
->input_array_first
[array_id
];
4124 input_array_size
= info
->input_array_last
[array_id
] - input_base
+ 1;
4126 input_base
= inst
->Src
[0].Register
.Index
;
4127 input_array_size
= info
->num_inputs
- input_base
;
4130 array_idx
= si_get_indirect_index(ctx
, &input
->Indirect
,
4131 1, input
->Register
.Index
- input_base
);
4133 input_base
= inst
->Src
[0].Register
.Index
;
4134 input_array_size
= 1;
4135 array_idx
= ctx
->i32_0
;
4138 interp
= shader
->selector
->info
.input_interpolate
[input_base
];
4140 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4141 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
4142 location
= TGSI_INTERPOLATE_LOC_CENTER
;
4144 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
4146 interp_param_idx
= lookup_interp_param_index(interp
, location
);
4147 if (interp_param_idx
== -1)
4149 else if (interp_param_idx
)
4150 interp_param
= LLVMGetParam(ctx
->main_fn
, interp_param_idx
);
4152 interp_param
= NULL
;
4154 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4155 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4156 LLVMValueRef ij_out
[2];
4157 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
4160 * take the I then J parameters, and the DDX/Y for it, and
4161 * calculate the IJ inputs for the interpolator.
4162 * temp1 = ddx * offset/sample.x + I;
4163 * interp_param.I = ddy * offset/sample.y + temp1;
4164 * temp1 = ddx * offset/sample.x + J;
4165 * interp_param.J = ddy * offset/sample.y + temp1;
4167 for (i
= 0; i
< 2; i
++) {
4168 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, 0);
4169 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, 0);
4170 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4171 ddxy_out
, ix_ll
, "");
4172 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4173 ddxy_out
, iy_ll
, "");
4174 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4175 interp_param
, ix_ll
, "");
4176 LLVMValueRef temp1
, temp2
;
4178 interp_el
= ac_to_float(&ctx
->ac
, interp_el
);
4180 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, emit_data
->args
[0], "");
4182 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4184 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, emit_data
->args
[1], "");
4186 ij_out
[i
] = LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4188 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4192 interp_param
= ac_to_float(&ctx
->ac
, interp_param
);
4194 for (chan
= 0; chan
< 4; chan
++) {
4195 LLVMValueRef gather
= LLVMGetUndef(LLVMVectorType(ctx
->f32
, input_array_size
));
4196 unsigned schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
4198 for (unsigned idx
= 0; idx
< input_array_size
; ++idx
) {
4199 LLVMValueRef v
, i
= NULL
, j
= NULL
;
4202 i
= LLVMBuildExtractElement(
4203 ctx
->ac
.builder
, interp_param
, ctx
->i32_0
, "");
4204 j
= LLVMBuildExtractElement(
4205 ctx
->ac
.builder
, interp_param
, ctx
->i32_1
, "");
4207 v
= si_build_fs_interp(ctx
, input_base
+ idx
, schan
,
4210 gather
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4211 gather
, v
, LLVMConstInt(ctx
->i32
, idx
, false), "");
4214 emit_data
->output
[chan
] = LLVMBuildExtractElement(
4215 ctx
->ac
.builder
, gather
, array_idx
, "");
4219 static void vote_all_emit(
4220 const struct lp_build_tgsi_action
*action
,
4221 struct lp_build_tgsi_context
*bld_base
,
4222 struct lp_build_emit_data
*emit_data
)
4224 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4226 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, emit_data
->args
[0]);
4227 emit_data
->output
[emit_data
->chan
] =
4228 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4231 static void vote_any_emit(
4232 const struct lp_build_tgsi_action
*action
,
4233 struct lp_build_tgsi_context
*bld_base
,
4234 struct lp_build_emit_data
*emit_data
)
4236 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4238 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, emit_data
->args
[0]);
4239 emit_data
->output
[emit_data
->chan
] =
4240 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4243 static void vote_eq_emit(
4244 const struct lp_build_tgsi_action
*action
,
4245 struct lp_build_tgsi_context
*bld_base
,
4246 struct lp_build_emit_data
*emit_data
)
4248 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4250 LLVMValueRef tmp
= ac_build_vote_eq(&ctx
->ac
, emit_data
->args
[0]);
4251 emit_data
->output
[emit_data
->chan
] =
4252 LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->i32
, "");
4255 static void ballot_emit(
4256 const struct lp_build_tgsi_action
*action
,
4257 struct lp_build_tgsi_context
*bld_base
,
4258 struct lp_build_emit_data
*emit_data
)
4260 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4261 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4264 tmp
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
4265 tmp
= ac_build_ballot(&ctx
->ac
, tmp
);
4266 tmp
= LLVMBuildBitCast(builder
, tmp
, ctx
->v2i32
, "");
4268 emit_data
->output
[0] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_0
, "");
4269 emit_data
->output
[1] = LLVMBuildExtractElement(builder
, tmp
, ctx
->i32_1
, "");
4272 static void read_invoc_fetch_args(
4273 struct lp_build_tgsi_context
*bld_base
,
4274 struct lp_build_emit_data
*emit_data
)
4276 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4277 0, emit_data
->src_chan
);
4279 /* Always read the source invocation (= lane) from the X channel. */
4280 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
4282 emit_data
->arg_count
= 2;
4285 static void read_lane_emit(
4286 const struct lp_build_tgsi_action
*action
,
4287 struct lp_build_tgsi_context
*bld_base
,
4288 struct lp_build_emit_data
*emit_data
)
4290 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4292 /* We currently have no other way to prevent LLVM from lifting the icmp
4293 * calls to a dominating basic block.
4295 ac_build_optimization_barrier(&ctx
->ac
, &emit_data
->args
[0]);
4297 for (unsigned i
= 0; i
< emit_data
->arg_count
; ++i
)
4298 emit_data
->args
[i
] = ac_to_integer(&ctx
->ac
, emit_data
->args
[i
]);
4300 emit_data
->output
[emit_data
->chan
] =
4301 ac_build_intrinsic(&ctx
->ac
, action
->intr_name
,
4302 ctx
->i32
, emit_data
->args
, emit_data
->arg_count
,
4303 AC_FUNC_ATTR_READNONE
|
4304 AC_FUNC_ATTR_CONVERGENT
);
4307 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
4308 struct lp_build_emit_data
*emit_data
)
4310 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4311 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
4315 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
4317 imm
= ctx
->imms
[src0
.Index
* TGSI_NUM_CHANNELS
+ src0
.SwizzleX
];
4318 stream
= LLVMConstIntGetZExtValue(imm
) & 0x3;
4322 /* Emit one vertex from the geometry shader */
4323 static void si_llvm_emit_vertex(struct ac_shader_abi
*abi
,
4325 LLVMValueRef
*addrs
)
4327 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4328 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
4329 struct si_shader
*shader
= ctx
->shader
;
4330 struct lp_build_if_state if_state
;
4331 LLVMValueRef soffset
= LLVMGetParam(ctx
->main_fn
,
4332 ctx
->param_gs2vs_offset
);
4333 LLVMValueRef gs_next_vertex
;
4334 LLVMValueRef can_emit
;
4335 unsigned chan
, offset
;
4338 /* Write vertex attribute values to GSVS ring */
4339 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4340 ctx
->gs_next_vertex
[stream
],
4343 /* If this thread has already emitted the declared maximum number of
4344 * vertices, skip the write: excessive vertex emissions are not
4345 * supposed to have any effect.
4347 * If the shader has no writes to memory, kill it instead. This skips
4348 * further memory loads and may allow LLVM to skip to the end
4351 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4352 LLVMConstInt(ctx
->i32
,
4353 shader
->selector
->gs_max_out_vertices
, 0), "");
4355 bool use_kill
= !info
->writes_memory
;
4357 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4359 lp_build_if(&if_state
, &ctx
->gallivm
, can_emit
);
4363 for (i
= 0; i
< info
->num_outputs
; i
++) {
4364 for (chan
= 0; chan
< 4; chan
++) {
4365 if (!(info
->output_usagemask
[i
] & (1 << chan
)) ||
4366 ((info
->output_streams
[i
] >> (2 * chan
)) & 3) != stream
)
4369 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, addrs
[4 * i
+ chan
], "");
4370 LLVMValueRef voffset
=
4371 LLVMConstInt(ctx
->i32
, offset
*
4372 shader
->selector
->gs_max_out_vertices
, 0);
4375 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4376 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
,
4377 LLVMConstInt(ctx
->i32
, 4, 0), "");
4379 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4381 ac_build_buffer_store_dword(&ctx
->ac
,
4382 ctx
->gsvs_ring
[stream
],
4384 voffset
, soffset
, 0,
4389 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
, ctx
->i32_1
, "");
4390 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
4392 /* Signal vertex emission */
4393 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
4394 si_get_gs_wave_id(ctx
));
4396 lp_build_endif(&if_state
);
4399 /* Emit one vertex from the geometry shader */
4400 static void si_tgsi_emit_vertex(
4401 const struct lp_build_tgsi_action
*action
,
4402 struct lp_build_tgsi_context
*bld_base
,
4403 struct lp_build_emit_data
*emit_data
)
4405 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4406 unsigned stream
= si_llvm_get_stream(bld_base
, emit_data
);
4408 si_llvm_emit_vertex(&ctx
->abi
, stream
, ctx
->outputs
[0]);
4411 /* Cut one primitive from the geometry shader */
4412 static void si_llvm_emit_primitive(struct ac_shader_abi
*abi
,
4415 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
4417 /* Signal primitive cut */
4418 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8),
4419 si_get_gs_wave_id(ctx
));
4422 /* Cut one primitive from the geometry shader */
4423 static void si_tgsi_emit_primitive(
4424 const struct lp_build_tgsi_action
*action
,
4425 struct lp_build_tgsi_context
*bld_base
,
4426 struct lp_build_emit_data
*emit_data
)
4428 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4430 si_llvm_emit_primitive(&ctx
->abi
, si_llvm_get_stream(bld_base
, emit_data
));
4433 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
4434 struct lp_build_tgsi_context
*bld_base
,
4435 struct lp_build_emit_data
*emit_data
)
4437 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
4439 /* SI only (thanks to a hw bug workaround):
4440 * The real barrier instruction isn’t needed, because an entire patch
4441 * always fits into a single wave.
4443 if (ctx
->screen
->info
.chip_class
== SI
&&
4444 ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
4445 ac_build_waitcnt(&ctx
->ac
, LGKM_CNT
& VM_CNT
);
4449 ac_build_intrinsic(&ctx
->ac
,
4450 "llvm.amdgcn.s.barrier",
4451 ctx
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
4454 static const struct lp_build_tgsi_action interp_action
= {
4455 .fetch_args
= interp_fetch_args
,
4456 .emit
= build_interp_intrinsic
,
4459 static void si_create_function(struct si_shader_context
*ctx
,
4461 LLVMTypeRef
*returns
, unsigned num_returns
,
4462 struct si_function_info
*fninfo
,
4463 unsigned max_workgroup_size
)
4467 si_llvm_create_func(ctx
, name
, returns
, num_returns
,
4468 fninfo
->types
, fninfo
->num_params
);
4469 ctx
->return_value
= LLVMGetUndef(ctx
->return_type
);
4471 for (i
= 0; i
< fninfo
->num_sgpr_params
; ++i
) {
4472 LLVMValueRef P
= LLVMGetParam(ctx
->main_fn
, i
);
4474 /* The combination of:
4478 * allows the optimization passes to move loads and reduces
4479 * SGPR spilling significantly.
4481 ac_add_function_attr(ctx
->ac
.context
, ctx
->main_fn
, i
+ 1,
4482 AC_FUNC_ATTR_INREG
);
4484 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
4485 ac_add_function_attr(ctx
->ac
.context
, ctx
->main_fn
, i
+ 1,
4486 AC_FUNC_ATTR_NOALIAS
);
4487 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
4491 for (i
= 0; i
< fninfo
->num_params
; ++i
) {
4492 if (fninfo
->assign
[i
])
4493 *fninfo
->assign
[i
] = LLVMGetParam(ctx
->main_fn
, i
);
4496 if (ctx
->screen
->info
.address32_hi
) {
4497 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4498 "amdgpu-32bit-address-high-bits",
4499 ctx
->screen
->info
.address32_hi
);
4502 if (max_workgroup_size
) {
4503 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
4504 "amdgpu-max-work-group-size",
4505 max_workgroup_size
);
4507 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4508 "no-signed-zeros-fp-math",
4511 if (ctx
->screen
->debug_flags
& DBG(UNSAFE_MATH
)) {
4512 /* These were copied from some LLVM test. */
4513 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4514 "less-precise-fpmad",
4516 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4519 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4522 LLVMAddTargetDependentFunctionAttr(ctx
->main_fn
,
4528 static void declare_streamout_params(struct si_shader_context
*ctx
,
4529 struct pipe_stream_output_info
*so
,
4530 struct si_function_info
*fninfo
)
4534 /* Streamout SGPRs. */
4535 if (so
->num_outputs
) {
4536 if (ctx
->type
!= PIPE_SHADER_TESS_EVAL
)
4537 ctx
->param_streamout_config
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4539 ctx
->param_streamout_config
= fninfo
->num_params
- 1;
4541 ctx
->param_streamout_write_index
= add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4543 /* A streamout buffer offset is loaded if the stride is non-zero. */
4544 for (i
= 0; i
< 4; i
++) {
4548 ctx
->param_streamout_offset
[i
] = add_arg(fninfo
, ARG_SGPR
, ctx
->ac
.i32
);
4552 static unsigned si_get_max_workgroup_size(const struct si_shader
*shader
)
4554 switch (shader
->selector
->type
) {
4555 case PIPE_SHADER_TESS_CTRL
:
4556 /* Return this so that LLVM doesn't remove s_barrier
4557 * instructions on chips where we use s_barrier. */
4558 return shader
->selector
->screen
->info
.chip_class
>= CIK
? 128 : 64;
4560 case PIPE_SHADER_GEOMETRY
:
4561 return shader
->selector
->screen
->info
.chip_class
>= GFX9
? 128 : 64;
4563 case PIPE_SHADER_COMPUTE
:
4564 break; /* see below */
4570 const unsigned *properties
= shader
->selector
->info
.properties
;
4571 unsigned max_work_group_size
=
4572 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] *
4573 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] *
4574 properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
];
4576 if (!max_work_group_size
) {
4577 /* This is a variable group size compute shader,
4578 * compile it for the maximum possible group size.
4580 max_work_group_size
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
4582 return max_work_group_size
;
4585 static void declare_const_and_shader_buffers(struct si_shader_context
*ctx
,
4586 struct si_function_info
*fninfo
,
4589 LLVMTypeRef const_shader_buf_type
;
4591 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
4592 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
4593 const_shader_buf_type
= ctx
->f32
;
4595 const_shader_buf_type
= ctx
->v4i32
;
4597 unsigned const_and_shader_buffers
=
4598 add_arg(fninfo
, ARG_SGPR
,
4599 ac_array_in_const32_addr_space(const_shader_buf_type
));
4602 ctx
->param_const_and_shader_buffers
= const_and_shader_buffers
;
4605 static void declare_samplers_and_images(struct si_shader_context
*ctx
,
4606 struct si_function_info
*fninfo
,
4609 unsigned samplers_and_images
=
4610 add_arg(fninfo
, ARG_SGPR
,
4611 ac_array_in_const32_addr_space(ctx
->v8i32
));
4614 ctx
->param_samplers_and_images
= samplers_and_images
;
4617 static void declare_per_stage_desc_pointers(struct si_shader_context
*ctx
,
4618 struct si_function_info
*fninfo
,
4621 declare_const_and_shader_buffers(ctx
, fninfo
, assign_params
);
4622 declare_samplers_and_images(ctx
, fninfo
, assign_params
);
4625 static void declare_global_desc_pointers(struct si_shader_context
*ctx
,
4626 struct si_function_info
*fninfo
)
4628 ctx
->param_rw_buffers
= add_arg(fninfo
, ARG_SGPR
,
4629 ac_array_in_const32_addr_space(ctx
->v4i32
));
4630 ctx
->param_bindless_samplers_and_images
= add_arg(fninfo
, ARG_SGPR
,
4631 ac_array_in_const32_addr_space(ctx
->v8i32
));
4634 static void declare_vs_specific_input_sgprs(struct si_shader_context
*ctx
,
4635 struct si_function_info
*fninfo
)
4637 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.base_vertex
);
4638 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.start_instance
);
4639 add_arg_assign(fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.draw_id
);
4640 ctx
->param_vs_state_bits
= add_arg(fninfo
, ARG_SGPR
, ctx
->i32
);
4643 static void declare_vs_input_vgprs(struct si_shader_context
*ctx
,
4644 struct si_function_info
*fninfo
,
4645 unsigned *num_prolog_vgprs
)
4647 struct si_shader
*shader
= ctx
->shader
;
4649 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.vertex_id
);
4650 if (shader
->key
.as_ls
) {
4651 ctx
->param_rel_auto_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4652 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4654 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.instance_id
);
4655 ctx
->param_vs_prim_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4657 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
); /* unused */
4659 if (!shader
->is_gs_copy_shader
) {
4660 /* Vertex load indices. */
4661 ctx
->param_vertex_index0
= fninfo
->num_params
;
4662 for (unsigned i
= 0; i
< shader
->selector
->info
.num_inputs
; i
++)
4663 add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4664 *num_prolog_vgprs
+= shader
->selector
->info
.num_inputs
;
4668 static void declare_tes_input_vgprs(struct si_shader_context
*ctx
,
4669 struct si_function_info
*fninfo
)
4671 ctx
->param_tes_u
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4672 ctx
->param_tes_v
= add_arg(fninfo
, ARG_VGPR
, ctx
->f32
);
4673 ctx
->param_tes_rel_patch_id
= add_arg(fninfo
, ARG_VGPR
, ctx
->i32
);
4674 add_arg_assign(fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tes_patch_id
);
4678 /* Convenient merged shader definitions. */
4679 SI_SHADER_MERGED_VERTEX_TESSCTRL
= PIPE_SHADER_TYPES
,
4680 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
,
4683 static void create_function(struct si_shader_context
*ctx
)
4685 struct si_shader
*shader
= ctx
->shader
;
4686 struct si_function_info fninfo
;
4687 LLVMTypeRef returns
[16+32*4];
4688 unsigned i
, num_return_sgprs
;
4689 unsigned num_returns
= 0;
4690 unsigned num_prolog_vgprs
= 0;
4691 unsigned type
= ctx
->type
;
4692 unsigned vs_blit_property
=
4693 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
4695 si_init_function_info(&fninfo
);
4697 /* Set MERGED shaders. */
4698 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
4699 if (shader
->key
.as_ls
|| type
== PIPE_SHADER_TESS_CTRL
)
4700 type
= SI_SHADER_MERGED_VERTEX_TESSCTRL
; /* LS or HS */
4701 else if (shader
->key
.as_es
|| type
== PIPE_SHADER_GEOMETRY
)
4702 type
= SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
;
4705 LLVMTypeRef v3i32
= LLVMVectorType(ctx
->i32
, 3);
4708 case PIPE_SHADER_VERTEX
:
4709 declare_global_desc_pointers(ctx
, &fninfo
);
4711 if (vs_blit_property
) {
4712 ctx
->param_vs_blit_inputs
= fninfo
.num_params
;
4713 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x1, y1 */
4714 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* i16 x2, y2 */
4715 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* depth */
4717 if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_COLOR
) {
4718 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color0 */
4719 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color1 */
4720 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color2 */
4721 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* color3 */
4722 } else if (vs_blit_property
== SI_VS_BLIT_SGPRS_POS_TEXCOORD
) {
4723 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x1 */
4724 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y1 */
4725 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.x2 */
4726 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.y2 */
4727 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.z */
4728 add_arg(&fninfo
, ARG_SGPR
, ctx
->f32
); /* texcoord.w */
4732 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4736 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4737 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4738 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4739 ac_array_in_const32_addr_space(ctx
->v4i32
));
4741 if (shader
->key
.as_es
) {
4742 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4743 } else if (shader
->key
.as_ls
) {
4744 /* no extra parameters */
4746 if (shader
->is_gs_copy_shader
) {
4747 fninfo
.num_params
= ctx
->param_rw_buffers
+ 1;
4748 fninfo
.num_sgpr_params
= fninfo
.num_params
;
4751 /* The locations of the other parameters are assigned dynamically. */
4752 declare_streamout_params(ctx
, &shader
->selector
->so
,
4757 declare_vs_input_vgprs(ctx
, &fninfo
, &num_prolog_vgprs
);
4760 case PIPE_SHADER_TESS_CTRL
: /* SI-CI-VI */
4761 declare_global_desc_pointers(ctx
, &fninfo
);
4762 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4763 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4764 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4765 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4766 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4767 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4768 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4771 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4772 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4774 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4775 * placed after the user SGPRs.
4777 for (i
= 0; i
< GFX6_TCS_NUM_USER_SGPR
+ 2; i
++)
4778 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4779 for (i
= 0; i
< 11; i
++)
4780 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4783 case SI_SHADER_MERGED_VERTEX_TESSCTRL
:
4784 /* Merged stages have 8 system SGPRs at the beginning. */
4785 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4786 if (HAVE_32BIT_POINTERS
) {
4787 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4788 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4790 declare_const_and_shader_buffers(ctx
, &fninfo
,
4791 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4793 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4794 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4795 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4796 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4797 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4798 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4800 declare_global_desc_pointers(ctx
, &fninfo
);
4801 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4802 ctx
->type
== PIPE_SHADER_VERTEX
);
4803 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4805 if (!HAVE_32BIT_POINTERS
) {
4806 declare_samplers_and_images(ctx
, &fninfo
,
4807 ctx
->type
== PIPE_SHADER_TESS_CTRL
);
4809 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4810 ctx
->param_tcs_out_lds_offsets
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4811 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4812 if (!HAVE_32BIT_POINTERS
) /* Align to 2 dwords. */
4813 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4814 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4815 ac_array_in_const32_addr_space(ctx
->v4i32
));
4817 /* VGPRs (first TCS, then VS) */
4818 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_patch_id
);
4819 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.tcs_rel_ids
);
4821 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4822 declare_vs_input_vgprs(ctx
, &fninfo
,
4825 /* LS return values are inputs to the TCS main shader part. */
4826 for (i
= 0; i
< 8 + GFX9_TCS_NUM_USER_SGPR
; i
++)
4827 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4828 for (i
= 0; i
< 2; i
++)
4829 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4831 /* TCS return values are inputs to the TCS epilog.
4833 * param_tcs_offchip_offset, param_tcs_factor_offset,
4834 * param_tcs_offchip_layout, and param_rw_buffers
4835 * should be passed to the epilog.
4837 for (i
= 0; i
<= 8 + GFX9_SGPR_TCS_OUT_LAYOUT
; i
++)
4838 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4839 for (i
= 0; i
< 11; i
++)
4840 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4844 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
:
4845 /* Merged stages have 8 system SGPRs at the beginning. */
4846 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4847 if (HAVE_32BIT_POINTERS
) {
4848 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4849 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4851 declare_const_and_shader_buffers(ctx
, &fninfo
,
4852 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4854 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4855 ctx
->param_merged_wave_info
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4856 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4857 ctx
->param_merged_scratch_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4858 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4859 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4861 declare_global_desc_pointers(ctx
, &fninfo
);
4862 declare_per_stage_desc_pointers(ctx
, &fninfo
,
4863 (ctx
->type
== PIPE_SHADER_VERTEX
||
4864 ctx
->type
== PIPE_SHADER_TESS_EVAL
));
4865 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4866 declare_vs_specific_input_sgprs(ctx
, &fninfo
);
4868 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4869 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4870 if (!HAVE_32BIT_POINTERS
) {
4871 /* Declare as many input SGPRs as the VS has. */
4872 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4873 ctx
->param_vs_state_bits
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* unused */
4877 if (!HAVE_32BIT_POINTERS
) {
4878 declare_samplers_and_images(ctx
, &fninfo
,
4879 ctx
->type
== PIPE_SHADER_GEOMETRY
);
4881 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4882 ctx
->param_vertex_buffers
= add_arg(&fninfo
, ARG_SGPR
,
4883 ac_array_in_const32_addr_space(ctx
->v4i32
));
4886 /* VGPRs (first GS, then VS/TES) */
4887 ctx
->param_gs_vtx01_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4888 ctx
->param_gs_vtx23_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4889 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4890 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4891 ctx
->param_gs_vtx45_offset
= add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
4893 if (ctx
->type
== PIPE_SHADER_VERTEX
) {
4894 declare_vs_input_vgprs(ctx
, &fninfo
,
4896 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4897 declare_tes_input_vgprs(ctx
, &fninfo
);
4900 if (ctx
->type
== PIPE_SHADER_VERTEX
||
4901 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
4902 unsigned num_user_sgprs
;
4904 if (ctx
->type
== PIPE_SHADER_VERTEX
)
4905 num_user_sgprs
= GFX9_VSGS_NUM_USER_SGPR
;
4907 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
4909 /* ES return values are inputs to GS. */
4910 for (i
= 0; i
< 8 + num_user_sgprs
; i
++)
4911 returns
[num_returns
++] = ctx
->i32
; /* SGPRs */
4912 for (i
= 0; i
< 5; i
++)
4913 returns
[num_returns
++] = ctx
->f32
; /* VGPRs */
4917 case PIPE_SHADER_TESS_EVAL
:
4918 declare_global_desc_pointers(ctx
, &fninfo
);
4919 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4920 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4921 ctx
->param_tes_offchip_addr
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4923 if (shader
->key
.as_es
) {
4924 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4925 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4926 ctx
->param_es2gs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4928 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4929 declare_streamout_params(ctx
, &shader
->selector
->so
,
4931 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4935 declare_tes_input_vgprs(ctx
, &fninfo
);
4938 case PIPE_SHADER_GEOMETRY
:
4939 declare_global_desc_pointers(ctx
, &fninfo
);
4940 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4941 ctx
->param_gs2vs_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4942 ctx
->param_gs_wave_id
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
4945 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]);
4946 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]);
4947 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_prim_id
);
4948 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
4949 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
4950 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
4951 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
4952 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &ctx
->abi
.gs_invocation_id
);
4955 case PIPE_SHADER_FRAGMENT
:
4956 declare_global_desc_pointers(ctx
, &fninfo
);
4957 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
4958 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
4959 add_arg_assign_checked(&fninfo
, ARG_SGPR
, ctx
->i32
,
4960 &ctx
->abi
.prim_mask
, SI_PARAM_PRIM_MASK
);
4962 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_SAMPLE
);
4963 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTER
);
4964 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_PERSP_CENTROID
);
4965 add_arg_checked(&fninfo
, ARG_VGPR
, v3i32
, SI_PARAM_PERSP_PULL_MODEL
);
4966 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_SAMPLE
);
4967 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTER
);
4968 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->v2i32
, SI_PARAM_LINEAR_CENTROID
);
4969 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->f32
, SI_PARAM_LINE_STIPPLE_TEX
);
4970 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4971 &ctx
->abi
.frag_pos
[0], SI_PARAM_POS_X_FLOAT
);
4972 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4973 &ctx
->abi
.frag_pos
[1], SI_PARAM_POS_Y_FLOAT
);
4974 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4975 &ctx
->abi
.frag_pos
[2], SI_PARAM_POS_Z_FLOAT
);
4976 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4977 &ctx
->abi
.frag_pos
[3], SI_PARAM_POS_W_FLOAT
);
4978 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4979 &ctx
->abi
.front_face
, SI_PARAM_FRONT_FACE
);
4980 shader
->info
.face_vgpr_index
= 20;
4981 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->i32
,
4982 &ctx
->abi
.ancillary
, SI_PARAM_ANCILLARY
);
4983 shader
->info
.ancillary_vgpr_index
= 21;
4984 add_arg_assign_checked(&fninfo
, ARG_VGPR
, ctx
->f32
,
4985 &ctx
->abi
.sample_coverage
, SI_PARAM_SAMPLE_COVERAGE
);
4986 add_arg_checked(&fninfo
, ARG_VGPR
, ctx
->i32
, SI_PARAM_POS_FIXED_PT
);
4988 /* Color inputs from the prolog. */
4989 if (shader
->selector
->info
.colors_read
) {
4990 unsigned num_color_elements
=
4991 util_bitcount(shader
->selector
->info
.colors_read
);
4993 assert(fninfo
.num_params
+ num_color_elements
<= ARRAY_SIZE(fninfo
.types
));
4994 for (i
= 0; i
< num_color_elements
; i
++)
4995 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
4997 num_prolog_vgprs
+= num_color_elements
;
5000 /* Outputs for the epilog. */
5001 num_return_sgprs
= SI_SGPR_ALPHA_REF
+ 1;
5004 util_bitcount(shader
->selector
->info
.colors_written
) * 4 +
5005 shader
->selector
->info
.writes_z
+
5006 shader
->selector
->info
.writes_stencil
+
5007 shader
->selector
->info
.writes_samplemask
+
5008 1 /* SampleMaskIn */;
5010 num_returns
= MAX2(num_returns
,
5012 PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
5014 for (i
= 0; i
< num_return_sgprs
; i
++)
5015 returns
[i
] = ctx
->i32
;
5016 for (; i
< num_returns
; i
++)
5017 returns
[i
] = ctx
->f32
;
5020 case PIPE_SHADER_COMPUTE
:
5021 declare_global_desc_pointers(ctx
, &fninfo
);
5022 declare_per_stage_desc_pointers(ctx
, &fninfo
, true);
5023 if (shader
->selector
->info
.uses_grid_size
)
5024 add_arg_assign(&fninfo
, ARG_SGPR
, v3i32
, &ctx
->abi
.num_work_groups
);
5025 if (shader
->selector
->info
.uses_block_size
)
5026 ctx
->param_block_size
= add_arg(&fninfo
, ARG_SGPR
, v3i32
);
5028 for (i
= 0; i
< 3; i
++) {
5029 ctx
->abi
.workgroup_ids
[i
] = NULL
;
5030 if (shader
->selector
->info
.uses_block_id
[i
])
5031 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &ctx
->abi
.workgroup_ids
[i
]);
5034 add_arg_assign(&fninfo
, ARG_VGPR
, v3i32
, &ctx
->abi
.local_invocation_ids
);
5037 assert(0 && "unimplemented shader");
5041 si_create_function(ctx
, "main", returns
, num_returns
, &fninfo
,
5042 si_get_max_workgroup_size(shader
));
5044 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5045 if (ctx
->type
== PIPE_SHADER_FRAGMENT
&& !ctx
->shader
->is_monolithic
) {
5046 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
5047 "InitialPSInputAddr",
5048 S_0286D0_PERSP_SAMPLE_ENA(1) |
5049 S_0286D0_PERSP_CENTER_ENA(1) |
5050 S_0286D0_PERSP_CENTROID_ENA(1) |
5051 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5052 S_0286D0_LINEAR_CENTER_ENA(1) |
5053 S_0286D0_LINEAR_CENTROID_ENA(1) |
5054 S_0286D0_FRONT_FACE_ENA(1) |
5055 S_0286D0_ANCILLARY_ENA(1) |
5056 S_0286D0_POS_FIXED_PT_ENA(1));
5059 shader
->info
.num_input_sgprs
= 0;
5060 shader
->info
.num_input_vgprs
= 0;
5062 for (i
= 0; i
< fninfo
.num_sgpr_params
; ++i
)
5063 shader
->info
.num_input_sgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5065 for (; i
< fninfo
.num_params
; ++i
)
5066 shader
->info
.num_input_vgprs
+= ac_get_type_size(fninfo
.types
[i
]) / 4;
5068 assert(shader
->info
.num_input_vgprs
>= num_prolog_vgprs
);
5069 shader
->info
.num_input_vgprs
-= num_prolog_vgprs
;
5071 if (shader
->key
.as_ls
||
5072 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
5073 /* GFX9 has the ESGS ring buffer in LDS. */
5074 type
== SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY
)
5075 ac_declare_lds_as_pointer(&ctx
->ac
);
5079 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5082 static void preload_ring_buffers(struct si_shader_context
*ctx
)
5084 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5086 LLVMValueRef buf_ptr
= LLVMGetParam(ctx
->main_fn
,
5087 ctx
->param_rw_buffers
);
5089 if (ctx
->screen
->info
.chip_class
<= VI
&&
5090 (ctx
->shader
->key
.as_es
|| ctx
->type
== PIPE_SHADER_GEOMETRY
)) {
5092 ctx
->type
== PIPE_SHADER_GEOMETRY
? SI_GS_RING_ESGS
5094 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, ring
, 0);
5097 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5100 if (ctx
->shader
->is_gs_copy_shader
) {
5101 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5104 ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5105 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
5106 const struct si_shader_selector
*sel
= ctx
->shader
->selector
;
5107 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, SI_RING_GSVS
, 0);
5108 LLVMValueRef base_ring
;
5110 base_ring
= ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
, offset
);
5112 /* The conceptual layout of the GSVS ring is
5113 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5114 * but the real memory layout is swizzled across
5116 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5118 * Override the buffer descriptor accordingly.
5120 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->i64
, 2);
5121 uint64_t stream_offset
= 0;
5123 for (unsigned stream
= 0; stream
< 4; ++stream
) {
5124 unsigned num_components
;
5126 unsigned num_records
;
5127 LLVMValueRef ring
, tmp
;
5129 num_components
= sel
->info
.num_stream_output_components
[stream
];
5130 if (!num_components
)
5133 stride
= 4 * num_components
* sel
->gs_max_out_vertices
;
5135 /* Limit on the stride field for <= CIK. */
5136 assert(stride
< (1 << 14));
5140 ring
= LLVMBuildBitCast(builder
, base_ring
, v2i64
, "");
5141 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_0
, "");
5142 tmp
= LLVMBuildAdd(builder
, tmp
,
5143 LLVMConstInt(ctx
->i64
,
5144 stream_offset
, 0), "");
5145 stream_offset
+= stride
* 64;
5147 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_0
, "");
5148 ring
= LLVMBuildBitCast(builder
, ring
, ctx
->v4i32
, "");
5149 tmp
= LLVMBuildExtractElement(builder
, ring
, ctx
->i32_1
, "");
5150 tmp
= LLVMBuildOr(builder
, tmp
,
5151 LLVMConstInt(ctx
->i32
,
5152 S_008F04_STRIDE(stride
) |
5153 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5154 ring
= LLVMBuildInsertElement(builder
, ring
, tmp
, ctx
->i32_1
, "");
5155 ring
= LLVMBuildInsertElement(builder
, ring
,
5156 LLVMConstInt(ctx
->i32
, num_records
, 0),
5157 LLVMConstInt(ctx
->i32
, 2, 0), "");
5158 ring
= LLVMBuildInsertElement(builder
, ring
,
5159 LLVMConstInt(ctx
->i32
,
5160 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5161 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5162 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5163 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
5164 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5165 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
5166 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5167 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5168 S_008F0C_ADD_TID_ENABLE(1),
5170 LLVMConstInt(ctx
->i32
, 3, 0), "");
5172 ctx
->gsvs_ring
[stream
] = ring
;
5174 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
5175 ctx
->tess_offchip_ring
= get_tess_ring_descriptor(ctx
, TESS_OFFCHIP_RING_TES
);
5179 static void si_llvm_emit_polygon_stipple(struct si_shader_context
*ctx
,
5180 LLVMValueRef param_rw_buffers
,
5181 unsigned param_pos_fixed_pt
)
5183 LLVMBuilderRef builder
= ctx
->ac
.builder
;
5184 LLVMValueRef slot
, desc
, offset
, row
, bit
, address
[2];
5186 /* Use the fixed-point gl_FragCoord input.
5187 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5188 * per coordinate to get the repeating effect.
5190 address
[0] = si_unpack_param(ctx
, param_pos_fixed_pt
, 0, 5);
5191 address
[1] = si_unpack_param(ctx
, param_pos_fixed_pt
, 16, 5);
5193 /* Load the buffer descriptor. */
5194 slot
= LLVMConstInt(ctx
->i32
, SI_PS_CONST_POLY_STIPPLE
, 0);
5195 desc
= ac_build_load_to_sgpr(&ctx
->ac
, param_rw_buffers
, slot
);
5197 /* The stipple pattern is 32x32, each row has 32 bits. */
5198 offset
= LLVMBuildMul(builder
, address
[1],
5199 LLVMConstInt(ctx
->i32
, 4, 0), "");
5200 row
= buffer_load_const(ctx
, desc
, offset
);
5201 row
= ac_to_integer(&ctx
->ac
, row
);
5202 bit
= LLVMBuildLShr(builder
, row
, address
[0], "");
5203 bit
= LLVMBuildTrunc(builder
, bit
, ctx
->i1
, "");
5204 ac_build_kill_if_false(&ctx
->ac
, bit
);
5207 void si_shader_binary_read_config(struct ac_shader_binary
*binary
,
5208 struct si_shader_config
*conf
,
5209 unsigned symbol_offset
)
5212 const unsigned char *config
=
5213 ac_shader_binary_config_start(binary
, symbol_offset
);
5214 bool really_needs_scratch
= false;
5216 /* LLVM adds SGPR spills to the scratch size.
5217 * Find out if we really need the scratch buffer.
5219 for (i
= 0; i
< binary
->reloc_count
; i
++) {
5220 const struct ac_shader_reloc
*reloc
= &binary
->relocs
[i
];
5222 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
) ||
5223 !strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5224 really_needs_scratch
= true;
5229 /* XXX: We may be able to emit some of these values directly rather than
5230 * extracting fields to be emitted later.
5233 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
5234 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
5235 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
5237 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
5238 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
5239 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
5240 case R_00B428_SPI_SHADER_PGM_RSRC1_HS
:
5241 case R_00B848_COMPUTE_PGM_RSRC1
:
5242 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
5243 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
5244 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
5245 conf
->rsrc1
= value
;
5247 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
5248 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
5250 case R_00B84C_COMPUTE_PGM_RSRC2
:
5251 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
5252 conf
->rsrc2
= value
;
5254 case R_0286CC_SPI_PS_INPUT_ENA
:
5255 conf
->spi_ps_input_ena
= value
;
5257 case R_0286D0_SPI_PS_INPUT_ADDR
:
5258 conf
->spi_ps_input_addr
= value
;
5260 case R_0286E8_SPI_TMPRING_SIZE
:
5261 case R_00B860_COMPUTE_TMPRING_SIZE
:
5262 /* WAVESIZE is in units of 256 dwords. */
5263 if (really_needs_scratch
)
5264 conf
->scratch_bytes_per_wave
=
5265 G_00B860_WAVESIZE(value
) * 256 * 4;
5267 case 0x4: /* SPILLED_SGPRS */
5268 conf
->spilled_sgprs
= value
;
5270 case 0x8: /* SPILLED_VGPRS */
5271 conf
->spilled_vgprs
= value
;
5275 static bool printed
;
5278 fprintf(stderr
, "Warning: LLVM emitted unknown "
5279 "config register: 0x%x\n", reg
);
5287 if (!conf
->spi_ps_input_addr
)
5288 conf
->spi_ps_input_addr
= conf
->spi_ps_input_ena
;
5291 void si_shader_apply_scratch_relocs(struct si_shader
*shader
,
5292 uint64_t scratch_va
)
5295 uint32_t scratch_rsrc_dword0
= scratch_va
;
5296 uint32_t scratch_rsrc_dword1
=
5297 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32);
5299 /* Enable scratch coalescing. */
5300 scratch_rsrc_dword1
|= S_008F04_SWIZZLE_ENABLE(1);
5302 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
5303 const struct ac_shader_reloc
*reloc
=
5304 &shader
->binary
.relocs
[i
];
5305 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
5306 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5307 &scratch_rsrc_dword0
, 4);
5308 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
5309 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
5310 &scratch_rsrc_dword1
, 4);
5315 /* For the UMR disassembler. */
5316 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5317 #define DEBUGGER_NUM_MARKERS 5
5319 static unsigned si_get_shader_binary_size(const struct si_shader
*shader
)
5321 unsigned size
= shader
->binary
.code_size
;
5324 size
+= shader
->prolog
->binary
.code_size
;
5325 if (shader
->previous_stage
)
5326 size
+= shader
->previous_stage
->binary
.code_size
;
5327 if (shader
->prolog2
)
5328 size
+= shader
->prolog2
->binary
.code_size
;
5330 size
+= shader
->epilog
->binary
.code_size
;
5331 return size
+ DEBUGGER_NUM_MARKERS
* 4;
5334 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
5336 const struct ac_shader_binary
*prolog
=
5337 shader
->prolog
? &shader
->prolog
->binary
: NULL
;
5338 const struct ac_shader_binary
*previous_stage
=
5339 shader
->previous_stage
? &shader
->previous_stage
->binary
: NULL
;
5340 const struct ac_shader_binary
*prolog2
=
5341 shader
->prolog2
? &shader
->prolog2
->binary
: NULL
;
5342 const struct ac_shader_binary
*epilog
=
5343 shader
->epilog
? &shader
->epilog
->binary
: NULL
;
5344 const struct ac_shader_binary
*mainb
= &shader
->binary
;
5345 unsigned bo_size
= si_get_shader_binary_size(shader
) +
5346 (!epilog
? mainb
->rodata_size
: 0);
5349 assert(!prolog
|| !prolog
->rodata_size
);
5350 assert(!previous_stage
|| !previous_stage
->rodata_size
);
5351 assert(!prolog2
|| !prolog2
->rodata_size
);
5352 assert((!prolog
&& !previous_stage
&& !prolog2
&& !epilog
) ||
5353 !mainb
->rodata_size
);
5354 assert(!epilog
|| !epilog
->rodata_size
);
5356 r600_resource_reference(&shader
->bo
, NULL
);
5357 shader
->bo
= si_aligned_buffer_create(&sscreen
->b
,
5358 sscreen
->cpdma_prefetch_writes_memory
?
5359 0 : SI_RESOURCE_FLAG_READ_ONLY
,
5360 PIPE_USAGE_IMMUTABLE
,
5361 align(bo_size
, SI_CPDMA_ALIGNMENT
),
5367 ptr
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
5368 PIPE_TRANSFER_READ_WRITE
|
5369 PIPE_TRANSFER_UNSYNCHRONIZED
);
5371 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5372 * endian-independent. */
5374 memcpy(ptr
, prolog
->code
, prolog
->code_size
);
5375 ptr
+= prolog
->code_size
;
5377 if (previous_stage
) {
5378 memcpy(ptr
, previous_stage
->code
, previous_stage
->code_size
);
5379 ptr
+= previous_stage
->code_size
;
5382 memcpy(ptr
, prolog2
->code
, prolog2
->code_size
);
5383 ptr
+= prolog2
->code_size
;
5386 memcpy(ptr
, mainb
->code
, mainb
->code_size
);
5387 ptr
+= mainb
->code_size
;
5390 memcpy(ptr
, epilog
->code
, epilog
->code_size
);
5391 ptr
+= epilog
->code_size
;
5392 } else if (mainb
->rodata_size
> 0) {
5393 memcpy(ptr
, mainb
->rodata
, mainb
->rodata_size
);
5394 ptr
+= mainb
->rodata_size
;
5397 /* Add end-of-code markers for the UMR disassembler. */
5398 uint32_t *ptr32
= (uint32_t*)ptr
;
5399 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
5400 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
5402 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
5406 static void si_shader_dump_disassembly(const struct ac_shader_binary
*binary
,
5407 struct pipe_debug_callback
*debug
,
5408 const char *name
, FILE *file
)
5413 if (binary
->disasm_string
) {
5414 fprintf(file
, "Shader %s disassembly:\n", name
);
5415 fprintf(file
, "%s", binary
->disasm_string
);
5417 if (debug
&& debug
->debug_message
) {
5418 /* Very long debug messages are cut off, so send the
5419 * disassembly one line at a time. This causes more
5420 * overhead, but on the plus side it simplifies
5421 * parsing of resulting logs.
5423 pipe_debug_message(debug
, SHADER_INFO
,
5424 "Shader Disassembly Begin");
5426 line
= binary
->disasm_string
;
5428 p
= util_strchrnul(line
, '\n');
5432 pipe_debug_message(debug
, SHADER_INFO
,
5433 "%.*s", count
, line
);
5441 pipe_debug_message(debug
, SHADER_INFO
,
5442 "Shader Disassembly End");
5445 fprintf(file
, "Shader %s binary:\n", name
);
5446 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
5447 fprintf(file
, "@0x%x: %02x%02x%02x%02x\n", i
,
5448 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
5449 binary
->code
[i
+ 1], binary
->code
[i
]);
5454 static void si_calculate_max_simd_waves(struct si_shader
*shader
)
5456 struct si_screen
*sscreen
= shader
->selector
->screen
;
5457 struct si_shader_config
*conf
= &shader
->config
;
5458 unsigned num_inputs
= shader
->selector
->info
.num_inputs
;
5459 unsigned lds_increment
= sscreen
->info
.chip_class
>= CIK
? 512 : 256;
5460 unsigned lds_per_wave
= 0;
5461 unsigned max_simd_waves
;
5463 max_simd_waves
= ac_get_max_simd_waves(sscreen
->info
.family
);
5465 /* Compute LDS usage for PS. */
5466 switch (shader
->selector
->type
) {
5467 case PIPE_SHADER_FRAGMENT
:
5468 /* The minimum usage per wave is (num_inputs * 48). The maximum
5469 * usage is (num_inputs * 48 * 16).
5470 * We can get anything in between and it varies between waves.
5472 * The 48 bytes per input for a single primitive is equal to
5473 * 4 bytes/component * 4 components/input * 3 points.
5475 * Other stages don't know the size at compile time or don't
5476 * allocate LDS per wave, but instead they do it per thread group.
5478 lds_per_wave
= conf
->lds_size
* lds_increment
+
5479 align(num_inputs
* 48, lds_increment
);
5481 case PIPE_SHADER_COMPUTE
:
5482 if (shader
->selector
) {
5483 unsigned max_workgroup_size
=
5484 si_get_max_workgroup_size(shader
);
5485 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
5486 DIV_ROUND_UP(max_workgroup_size
, 64);
5491 /* Compute the per-SIMD wave counts. */
5492 if (conf
->num_sgprs
) {
5493 if (sscreen
->info
.chip_class
>= VI
)
5494 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
5496 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
5499 if (conf
->num_vgprs
)
5500 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
5502 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5503 * 16KB makes some SIMDs unoccupied). */
5505 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
5507 conf
->max_simd_waves
= max_simd_waves
;
5510 void si_shader_dump_stats_for_shader_db(const struct si_shader
*shader
,
5511 struct pipe_debug_callback
*debug
)
5513 const struct si_shader_config
*conf
= &shader
->config
;
5515 pipe_debug_message(debug
, SHADER_INFO
,
5516 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5517 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5518 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5519 conf
->num_sgprs
, conf
->num_vgprs
,
5520 si_get_shader_binary_size(shader
),
5521 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5522 conf
->max_simd_waves
, conf
->spilled_sgprs
,
5523 conf
->spilled_vgprs
, conf
->private_mem_vgprs
);
5526 static void si_shader_dump_stats(struct si_screen
*sscreen
,
5527 const struct si_shader
*shader
,
5530 bool check_debug_option
)
5532 const struct si_shader_config
*conf
= &shader
->config
;
5534 if (!check_debug_option
||
5535 si_can_dump_shader(sscreen
, processor
)) {
5536 if (processor
== PIPE_SHADER_FRAGMENT
) {
5537 fprintf(file
, "*** SHADER CONFIG ***\n"
5538 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5539 "SPI_PS_INPUT_ENA = 0x%04x\n",
5540 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
5543 fprintf(file
, "*** SHADER STATS ***\n"
5546 "Spilled SGPRs: %d\n"
5547 "Spilled VGPRs: %d\n"
5548 "Private memory VGPRs: %d\n"
5549 "Code Size: %d bytes\n"
5551 "Scratch: %d bytes per wave\n"
5553 "********************\n\n\n",
5554 conf
->num_sgprs
, conf
->num_vgprs
,
5555 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
5556 conf
->private_mem_vgprs
,
5557 si_get_shader_binary_size(shader
),
5558 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
5559 conf
->max_simd_waves
);
5563 const char *si_get_shader_name(const struct si_shader
*shader
, unsigned processor
)
5565 switch (processor
) {
5566 case PIPE_SHADER_VERTEX
:
5567 if (shader
->key
.as_es
)
5568 return "Vertex Shader as ES";
5569 else if (shader
->key
.as_ls
)
5570 return "Vertex Shader as LS";
5572 return "Vertex Shader as VS";
5573 case PIPE_SHADER_TESS_CTRL
:
5574 return "Tessellation Control Shader";
5575 case PIPE_SHADER_TESS_EVAL
:
5576 if (shader
->key
.as_es
)
5577 return "Tessellation Evaluation Shader as ES";
5579 return "Tessellation Evaluation Shader as VS";
5580 case PIPE_SHADER_GEOMETRY
:
5581 if (shader
->is_gs_copy_shader
)
5582 return "GS Copy Shader as VS";
5584 return "Geometry Shader";
5585 case PIPE_SHADER_FRAGMENT
:
5586 return "Pixel Shader";
5587 case PIPE_SHADER_COMPUTE
:
5588 return "Compute Shader";
5590 return "Unknown Shader";
5594 void si_shader_dump(struct si_screen
*sscreen
, const struct si_shader
*shader
,
5595 struct pipe_debug_callback
*debug
, unsigned processor
,
5596 FILE *file
, bool check_debug_option
)
5598 if (!check_debug_option
||
5599 si_can_dump_shader(sscreen
, processor
))
5600 si_dump_shader_key(processor
, shader
, file
);
5602 if (!check_debug_option
&& shader
->binary
.llvm_ir_string
) {
5603 if (shader
->previous_stage
&&
5604 shader
->previous_stage
->binary
.llvm_ir_string
) {
5605 fprintf(file
, "\n%s - previous stage - LLVM IR:\n\n",
5606 si_get_shader_name(shader
, processor
));
5607 fprintf(file
, "%s\n", shader
->previous_stage
->binary
.llvm_ir_string
);
5610 fprintf(file
, "\n%s - main shader part - LLVM IR:\n\n",
5611 si_get_shader_name(shader
, processor
));
5612 fprintf(file
, "%s\n", shader
->binary
.llvm_ir_string
);
5615 if (!check_debug_option
||
5616 (si_can_dump_shader(sscreen
, processor
) &&
5617 !(sscreen
->debug_flags
& DBG(NO_ASM
)))) {
5618 fprintf(file
, "\n%s:\n", si_get_shader_name(shader
, processor
));
5621 si_shader_dump_disassembly(&shader
->prolog
->binary
,
5622 debug
, "prolog", file
);
5623 if (shader
->previous_stage
)
5624 si_shader_dump_disassembly(&shader
->previous_stage
->binary
,
5625 debug
, "previous stage", file
);
5626 if (shader
->prolog2
)
5627 si_shader_dump_disassembly(&shader
->prolog2
->binary
,
5628 debug
, "prolog2", file
);
5630 si_shader_dump_disassembly(&shader
->binary
, debug
, "main", file
);
5633 si_shader_dump_disassembly(&shader
->epilog
->binary
,
5634 debug
, "epilog", file
);
5635 fprintf(file
, "\n");
5638 si_shader_dump_stats(sscreen
, shader
, processor
, file
,
5639 check_debug_option
);
5642 static int si_compile_llvm(struct si_screen
*sscreen
,
5643 struct ac_shader_binary
*binary
,
5644 struct si_shader_config
*conf
,
5645 struct si_compiler
*compiler
,
5647 struct pipe_debug_callback
*debug
,
5652 unsigned count
= p_atomic_inc_return(&sscreen
->num_compilations
);
5654 if (si_can_dump_shader(sscreen
, processor
)) {
5655 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
5657 if (!(sscreen
->debug_flags
& (DBG(NO_IR
) | DBG(PREOPT_IR
)))) {
5658 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5659 ac_dump_module(mod
);
5660 fprintf(stderr
, "\n");
5664 if (sscreen
->record_llvm_ir
) {
5665 char *ir
= LLVMPrintModuleToString(mod
);
5666 binary
->llvm_ir_string
= strdup(ir
);
5667 LLVMDisposeMessage(ir
);
5670 if (!si_replace_shader(count
, binary
)) {
5671 r
= si_llvm_compile(mod
, binary
, compiler
, debug
);
5676 si_shader_binary_read_config(binary
, conf
, 0);
5678 /* Enable 64-bit and 16-bit denormals, because there is no performance
5681 * If denormals are enabled, all floating-point output modifiers are
5684 * Don't enable denormals for 32-bit floats, because:
5685 * - Floating-point output modifiers would be ignored by the hw.
5686 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5687 * have to stop using those.
5688 * - SI & CI would be very slow.
5690 conf
->float_mode
|= V_00B028_FP_64_DENORMS
;
5692 FREE(binary
->config
);
5693 FREE(binary
->global_symbol_offsets
);
5694 binary
->config
= NULL
;
5695 binary
->global_symbol_offsets
= NULL
;
5697 /* Some shaders can't have rodata because their binaries can be
5700 if (binary
->rodata_size
&&
5701 (processor
== PIPE_SHADER_VERTEX
||
5702 processor
== PIPE_SHADER_TESS_CTRL
||
5703 processor
== PIPE_SHADER_TESS_EVAL
||
5704 processor
== PIPE_SHADER_FRAGMENT
)) {
5705 fprintf(stderr
, "radeonsi: The shader can't have rodata.");
5712 static void si_llvm_build_ret(struct si_shader_context
*ctx
, LLVMValueRef ret
)
5714 if (LLVMGetTypeKind(LLVMTypeOf(ret
)) == LLVMVoidTypeKind
)
5715 LLVMBuildRetVoid(ctx
->ac
.builder
);
5717 LLVMBuildRet(ctx
->ac
.builder
, ret
);
5720 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5722 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
5723 struct si_compiler
*compiler
,
5724 struct si_shader_selector
*gs_selector
,
5725 struct pipe_debug_callback
*debug
)
5727 struct si_shader_context ctx
;
5728 struct si_shader
*shader
;
5729 LLVMBuilderRef builder
;
5730 struct si_shader_output_values
*outputs
;
5731 struct tgsi_shader_info
*gsinfo
= &gs_selector
->info
;
5734 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
5739 shader
= CALLOC_STRUCT(si_shader
);
5745 /* We can leave the fence as permanently signaled because the GS copy
5746 * shader only becomes visible globally after it has been compiled. */
5747 util_queue_fence_init(&shader
->ready
);
5749 shader
->selector
= gs_selector
;
5750 shader
->is_gs_copy_shader
= true;
5752 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
5753 ctx
.shader
= shader
;
5754 ctx
.type
= PIPE_SHADER_VERTEX
;
5756 builder
= ctx
.ac
.builder
;
5758 create_function(&ctx
);
5759 preload_ring_buffers(&ctx
);
5761 LLVMValueRef voffset
=
5762 LLVMBuildMul(ctx
.ac
.builder
, ctx
.abi
.vertex_id
,
5763 LLVMConstInt(ctx
.i32
, 4, 0), "");
5765 /* Fetch the vertex stream ID.*/
5766 LLVMValueRef stream_id
;
5768 if (gs_selector
->so
.num_outputs
)
5769 stream_id
= si_unpack_param(&ctx
, ctx
.param_streamout_config
, 24, 2);
5771 stream_id
= ctx
.i32_0
;
5773 /* Fill in output information. */
5774 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5775 outputs
[i
].semantic_name
= gsinfo
->output_semantic_name
[i
];
5776 outputs
[i
].semantic_index
= gsinfo
->output_semantic_index
[i
];
5778 for (int chan
= 0; chan
< 4; chan
++) {
5779 outputs
[i
].vertex_stream
[chan
] =
5780 (gsinfo
->output_streams
[i
] >> (2 * chan
)) & 3;
5784 LLVMBasicBlockRef end_bb
;
5785 LLVMValueRef switch_inst
;
5787 end_bb
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, ctx
.main_fn
, "end");
5788 switch_inst
= LLVMBuildSwitch(builder
, stream_id
, end_bb
, 4);
5790 for (int stream
= 0; stream
< 4; stream
++) {
5791 LLVMBasicBlockRef bb
;
5794 if (!gsinfo
->num_stream_output_components
[stream
])
5797 if (stream
> 0 && !gs_selector
->so
.num_outputs
)
5800 bb
= LLVMInsertBasicBlockInContext(ctx
.ac
.context
, end_bb
, "out");
5801 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
.i32
, stream
, 0), bb
);
5802 LLVMPositionBuilderAtEnd(builder
, bb
);
5804 /* Fetch vertex data from GSVS ring */
5806 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
5807 for (unsigned chan
= 0; chan
< 4; chan
++) {
5808 if (!(gsinfo
->output_usagemask
[i
] & (1 << chan
)) ||
5809 outputs
[i
].vertex_stream
[chan
] != stream
) {
5810 outputs
[i
].values
[chan
] = LLVMGetUndef(ctx
.f32
);
5814 LLVMValueRef soffset
= LLVMConstInt(ctx
.i32
,
5815 offset
* gs_selector
->gs_max_out_vertices
* 16 * 4, 0);
5818 outputs
[i
].values
[chan
] =
5819 ac_build_buffer_load(&ctx
.ac
,
5820 ctx
.gsvs_ring
[0], 1,
5827 /* Streamout and exports. */
5828 if (gs_selector
->so
.num_outputs
) {
5829 si_llvm_emit_streamout(&ctx
, outputs
,
5830 gsinfo
->num_outputs
,
5835 si_llvm_export_vs(&ctx
, outputs
, gsinfo
->num_outputs
);
5837 LLVMBuildBr(builder
, end_bb
);
5840 LLVMPositionBuilderAtEnd(builder
, end_bb
);
5842 LLVMBuildRetVoid(ctx
.ac
.builder
);
5844 ctx
.type
= PIPE_SHADER_GEOMETRY
; /* override for shader dumping */
5845 si_llvm_optimize_module(&ctx
);
5847 r
= si_compile_llvm(sscreen
, &ctx
.shader
->binary
,
5848 &ctx
.shader
->config
, ctx
.compiler
,
5850 debug
, PIPE_SHADER_GEOMETRY
,
5853 if (si_can_dump_shader(sscreen
, PIPE_SHADER_GEOMETRY
))
5854 fprintf(stderr
, "GS Copy Shader:\n");
5855 si_shader_dump(sscreen
, ctx
.shader
, debug
,
5856 PIPE_SHADER_GEOMETRY
, stderr
, true);
5857 r
= si_shader_binary_upload(sscreen
, ctx
.shader
);
5860 si_llvm_dispose(&ctx
);
5871 static void si_dump_shader_key_vs(const struct si_shader_key
*key
,
5872 const struct si_vs_prolog_bits
*prolog
,
5873 const char *prefix
, FILE *f
)
5875 fprintf(f
, " %s.instance_divisor_is_one = %u\n",
5876 prefix
, prolog
->instance_divisor_is_one
);
5877 fprintf(f
, " %s.instance_divisor_is_fetched = %u\n",
5878 prefix
, prolog
->instance_divisor_is_fetched
);
5879 fprintf(f
, " %s.ls_vgpr_fix = %u\n",
5880 prefix
, prolog
->ls_vgpr_fix
);
5882 fprintf(f
, " mono.vs.fix_fetch = {");
5883 for (int i
= 0; i
< SI_MAX_ATTRIBS
; i
++)
5884 fprintf(f
, !i
? "%u" : ", %u", key
->mono
.vs_fix_fetch
[i
]);
5888 static void si_dump_shader_key(unsigned processor
, const struct si_shader
*shader
,
5891 const struct si_shader_key
*key
= &shader
->key
;
5893 fprintf(f
, "SHADER KEY\n");
5895 switch (processor
) {
5896 case PIPE_SHADER_VERTEX
:
5897 si_dump_shader_key_vs(key
, &key
->part
.vs
.prolog
,
5898 "part.vs.prolog", f
);
5899 fprintf(f
, " as_es = %u\n", key
->as_es
);
5900 fprintf(f
, " as_ls = %u\n", key
->as_ls
);
5901 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5902 key
->mono
.u
.vs_export_prim_id
);
5905 case PIPE_SHADER_TESS_CTRL
:
5906 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
) {
5907 si_dump_shader_key_vs(key
, &key
->part
.tcs
.ls_prolog
,
5908 "part.tcs.ls_prolog", f
);
5910 fprintf(f
, " part.tcs.epilog.prim_mode = %u\n", key
->part
.tcs
.epilog
.prim_mode
);
5911 fprintf(f
, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64
"\n", key
->mono
.u
.ff_tcs_inputs_to_copy
);
5914 case PIPE_SHADER_TESS_EVAL
:
5915 fprintf(f
, " as_es = %u\n", key
->as_es
);
5916 fprintf(f
, " mono.u.vs_export_prim_id = %u\n",
5917 key
->mono
.u
.vs_export_prim_id
);
5920 case PIPE_SHADER_GEOMETRY
:
5921 if (shader
->is_gs_copy_shader
)
5924 if (shader
->selector
->screen
->info
.chip_class
>= GFX9
&&
5925 key
->part
.gs
.es
->type
== PIPE_SHADER_VERTEX
) {
5926 si_dump_shader_key_vs(key
, &key
->part
.gs
.vs_prolog
,
5927 "part.gs.vs_prolog", f
);
5929 fprintf(f
, " part.gs.prolog.tri_strip_adj_fix = %u\n", key
->part
.gs
.prolog
.tri_strip_adj_fix
);
5932 case PIPE_SHADER_COMPUTE
:
5935 case PIPE_SHADER_FRAGMENT
:
5936 fprintf(f
, " part.ps.prolog.color_two_side = %u\n", key
->part
.ps
.prolog
.color_two_side
);
5937 fprintf(f
, " part.ps.prolog.flatshade_colors = %u\n", key
->part
.ps
.prolog
.flatshade_colors
);
5938 fprintf(f
, " part.ps.prolog.poly_stipple = %u\n", key
->part
.ps
.prolog
.poly_stipple
);
5939 fprintf(f
, " part.ps.prolog.force_persp_sample_interp = %u\n", key
->part
.ps
.prolog
.force_persp_sample_interp
);
5940 fprintf(f
, " part.ps.prolog.force_linear_sample_interp = %u\n", key
->part
.ps
.prolog
.force_linear_sample_interp
);
5941 fprintf(f
, " part.ps.prolog.force_persp_center_interp = %u\n", key
->part
.ps
.prolog
.force_persp_center_interp
);
5942 fprintf(f
, " part.ps.prolog.force_linear_center_interp = %u\n", key
->part
.ps
.prolog
.force_linear_center_interp
);
5943 fprintf(f
, " part.ps.prolog.bc_optimize_for_persp = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_persp
);
5944 fprintf(f
, " part.ps.prolog.bc_optimize_for_linear = %u\n", key
->part
.ps
.prolog
.bc_optimize_for_linear
);
5945 fprintf(f
, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key
->part
.ps
.epilog
.spi_shader_col_format
);
5946 fprintf(f
, " part.ps.epilog.color_is_int8 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int8
);
5947 fprintf(f
, " part.ps.epilog.color_is_int10 = 0x%X\n", key
->part
.ps
.epilog
.color_is_int10
);
5948 fprintf(f
, " part.ps.epilog.last_cbuf = %u\n", key
->part
.ps
.epilog
.last_cbuf
);
5949 fprintf(f
, " part.ps.epilog.alpha_func = %u\n", key
->part
.ps
.epilog
.alpha_func
);
5950 fprintf(f
, " part.ps.epilog.alpha_to_one = %u\n", key
->part
.ps
.epilog
.alpha_to_one
);
5951 fprintf(f
, " part.ps.epilog.poly_line_smoothing = %u\n", key
->part
.ps
.epilog
.poly_line_smoothing
);
5952 fprintf(f
, " part.ps.epilog.clamp_color = %u\n", key
->part
.ps
.epilog
.clamp_color
);
5959 if ((processor
== PIPE_SHADER_GEOMETRY
||
5960 processor
== PIPE_SHADER_TESS_EVAL
||
5961 processor
== PIPE_SHADER_VERTEX
) &&
5962 !key
->as_es
&& !key
->as_ls
) {
5963 fprintf(f
, " opt.kill_outputs = 0x%"PRIx64
"\n", key
->opt
.kill_outputs
);
5964 fprintf(f
, " opt.clip_disable = %u\n", key
->opt
.clip_disable
);
5968 static void si_init_shader_ctx(struct si_shader_context
*ctx
,
5969 struct si_screen
*sscreen
,
5970 struct si_compiler
*compiler
)
5972 struct lp_build_tgsi_context
*bld_base
;
5974 si_llvm_context_init(ctx
, sscreen
, compiler
);
5976 bld_base
= &ctx
->bld_base
;
5977 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
5979 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
5980 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
5981 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
5983 bld_base
->op_actions
[TGSI_OPCODE_MEMBAR
].emit
= membar_emit
;
5985 bld_base
->op_actions
[TGSI_OPCODE_CLOCK
].emit
= clock_emit
;
5987 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
5988 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
5989 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
5990 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
5992 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ALL
].emit
= vote_all_emit
;
5993 bld_base
->op_actions
[TGSI_OPCODE_VOTE_ANY
].emit
= vote_any_emit
;
5994 bld_base
->op_actions
[TGSI_OPCODE_VOTE_EQ
].emit
= vote_eq_emit
;
5995 bld_base
->op_actions
[TGSI_OPCODE_BALLOT
].emit
= ballot_emit
;
5996 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].intr_name
= "llvm.amdgcn.readfirstlane";
5997 bld_base
->op_actions
[TGSI_OPCODE_READ_FIRST
].emit
= read_lane_emit
;
5998 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].intr_name
= "llvm.amdgcn.readlane";
5999 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].fetch_args
= read_invoc_fetch_args
;
6000 bld_base
->op_actions
[TGSI_OPCODE_READ_INVOC
].emit
= read_lane_emit
;
6002 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_tgsi_emit_vertex
;
6003 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_tgsi_emit_primitive
;
6004 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
6007 static void si_optimize_vs_outputs(struct si_shader_context
*ctx
)
6009 struct si_shader
*shader
= ctx
->shader
;
6010 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6012 if ((ctx
->type
!= PIPE_SHADER_VERTEX
&&
6013 ctx
->type
!= PIPE_SHADER_TESS_EVAL
) ||
6014 shader
->key
.as_ls
||
6018 ac_optimize_vs_outputs(&ctx
->ac
,
6020 shader
->info
.vs_output_param_offset
,
6022 &shader
->info
.nr_param_exports
);
6025 static void si_init_exec_from_input(struct si_shader_context
*ctx
,
6026 unsigned param
, unsigned bitoffset
)
6028 LLVMValueRef args
[] = {
6029 LLVMGetParam(ctx
->main_fn
, param
),
6030 LLVMConstInt(ctx
->i32
, bitoffset
, 0),
6032 ac_build_intrinsic(&ctx
->ac
,
6033 "llvm.amdgcn.init.exec.from.input",
6034 ctx
->voidt
, args
, 2, AC_FUNC_ATTR_CONVERGENT
);
6037 static bool si_vs_needs_prolog(const struct si_shader_selector
*sel
,
6038 const struct si_vs_prolog_bits
*key
)
6040 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6042 return sel
->vs_needs_prolog
|| key
->ls_vgpr_fix
;
6045 static bool si_compile_tgsi_main(struct si_shader_context
*ctx
)
6047 struct si_shader
*shader
= ctx
->shader
;
6048 struct si_shader_selector
*sel
= shader
->selector
;
6049 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
6051 // TODO clean all this up!
6052 switch (ctx
->type
) {
6053 case PIPE_SHADER_VERTEX
:
6054 ctx
->load_input
= declare_input_vs
;
6055 if (shader
->key
.as_ls
)
6056 ctx
->abi
.emit_outputs
= si_llvm_emit_ls_epilogue
;
6057 else if (shader
->key
.as_es
)
6058 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6060 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6061 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6062 ctx
->abi
.load_base_vertex
= get_base_vertex
;
6064 case PIPE_SHADER_TESS_CTRL
:
6065 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
6066 ctx
->abi
.load_tess_varyings
= si_nir_load_tcs_varyings
;
6067 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
6068 bld_base
->emit_store
= store_output_tcs
;
6069 ctx
->abi
.store_tcs_outputs
= si_nir_store_output_tcs
;
6070 ctx
->abi
.emit_outputs
= si_llvm_emit_tcs_epilogue
;
6071 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6072 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6074 case PIPE_SHADER_TESS_EVAL
:
6075 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
6076 ctx
->abi
.load_tess_varyings
= si_nir_load_input_tes
;
6077 ctx
->abi
.load_tess_coord
= si_load_tess_coord
;
6078 ctx
->abi
.load_tess_level
= si_load_tess_level
;
6079 ctx
->abi
.load_patch_vertices_in
= si_load_patch_vertices_in
;
6080 if (shader
->key
.as_es
)
6081 ctx
->abi
.emit_outputs
= si_llvm_emit_es_epilogue
;
6083 ctx
->abi
.emit_outputs
= si_llvm_emit_vs_epilogue
;
6084 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6086 case PIPE_SHADER_GEOMETRY
:
6087 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
6088 ctx
->abi
.load_inputs
= si_nir_load_input_gs
;
6089 ctx
->abi
.emit_vertex
= si_llvm_emit_vertex
;
6090 ctx
->abi
.emit_primitive
= si_llvm_emit_primitive
;
6091 ctx
->abi
.emit_outputs
= si_llvm_emit_gs_epilogue
;
6092 bld_base
->emit_epilogue
= si_tgsi_emit_gs_epilogue
;
6094 case PIPE_SHADER_FRAGMENT
:
6095 ctx
->load_input
= declare_input_fs
;
6096 ctx
->abi
.emit_outputs
= si_llvm_return_fs_outputs
;
6097 bld_base
->emit_epilogue
= si_tgsi_emit_epilogue
;
6098 ctx
->abi
.lookup_interp_param
= si_nir_lookup_interp_param
;
6099 ctx
->abi
.load_sample_position
= load_sample_position
;
6100 ctx
->abi
.load_sample_mask_in
= load_sample_mask_in
;
6101 ctx
->abi
.emit_kill
= si_llvm_emit_kill
;
6103 case PIPE_SHADER_COMPUTE
:
6104 ctx
->abi
.load_local_group_size
= get_block_size
;
6107 assert(!"Unsupported shader type");
6111 ctx
->abi
.load_ubo
= load_ubo
;
6112 ctx
->abi
.load_ssbo
= load_ssbo
;
6114 create_function(ctx
);
6115 preload_ring_buffers(ctx
);
6117 /* For GFX9 merged shaders:
6118 * - Set EXEC for the first shader. If the prolog is present, set
6119 * EXEC there instead.
6120 * - Add a barrier before the second shader.
6121 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6122 * an if-statement. This is required for correctness in geometry
6123 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6126 * For monolithic merged shaders, the first shader is wrapped in an
6127 * if-block together with its prolog in si_build_wrapper_function.
6129 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6130 if (!shader
->is_monolithic
&&
6131 sel
->info
.num_instructions
> 1 && /* not empty shader */
6132 (shader
->key
.as_es
|| shader
->key
.as_ls
) &&
6133 (ctx
->type
== PIPE_SHADER_TESS_EVAL
||
6134 (ctx
->type
== PIPE_SHADER_VERTEX
&&
6135 !si_vs_needs_prolog(sel
, &shader
->key
.part
.vs
.prolog
)))) {
6136 si_init_exec_from_input(ctx
,
6137 ctx
->param_merged_wave_info
, 0);
6138 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
6139 ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6140 if (!shader
->is_monolithic
)
6141 ac_init_exec_full_mask(&ctx
->ac
);
6143 /* The barrier must execute for all shaders in a
6146 si_llvm_emit_barrier(NULL
, bld_base
, NULL
);
6148 LLVMValueRef num_threads
= si_unpack_param(ctx
, ctx
->param_merged_wave_info
, 8, 8);
6150 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
6151 ac_get_thread_id(&ctx
->ac
), num_threads
, "");
6152 lp_build_if(&ctx
->merged_wrap_if_state
, &ctx
->gallivm
, ena
);
6156 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&&
6157 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
) {
6158 for (unsigned i
= 0; i
< 6; i
++) {
6159 ctx
->invoc0_tess_factors
[i
] =
6160 ac_build_alloca_undef(&ctx
->ac
, ctx
->i32
, "");
6164 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
6166 for (i
= 0; i
< 4; i
++) {
6167 ctx
->gs_next_vertex
[i
] =
6168 ac_build_alloca(&ctx
->ac
, ctx
->i32
, "");
6172 if (sel
->force_correct_derivs_after_kill
) {
6173 ctx
->postponed_kill
= ac_build_alloca_undef(&ctx
->ac
, ctx
->i1
, "");
6174 /* true = don't kill. */
6175 LLVMBuildStore(ctx
->ac
.builder
, LLVMConstInt(ctx
->i1
, 1, 0),
6176 ctx
->postponed_kill
);
6180 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
6181 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
6185 if (!si_nir_build_llvm(ctx
, sel
->nir
)) {
6186 fprintf(stderr
, "Failed to translate shader from NIR to LLVM\n");
6191 si_llvm_build_ret(ctx
, ctx
->return_value
);
6196 * Compute the VS prolog key, which contains all the information needed to
6197 * build the VS prolog function, and set shader->info bits where needed.
6199 * \param info Shader info of the vertex shader.
6200 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6201 * \param prolog_key Key of the VS prolog
6202 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6203 * \param key Output shader part key.
6205 static void si_get_vs_prolog_key(const struct tgsi_shader_info
*info
,
6206 unsigned num_input_sgprs
,
6207 const struct si_vs_prolog_bits
*prolog_key
,
6208 struct si_shader
*shader_out
,
6209 union si_shader_part_key
*key
)
6211 memset(key
, 0, sizeof(*key
));
6212 key
->vs_prolog
.states
= *prolog_key
;
6213 key
->vs_prolog
.num_input_sgprs
= num_input_sgprs
;
6214 key
->vs_prolog
.last_input
= MAX2(1, info
->num_inputs
) - 1;
6215 key
->vs_prolog
.as_ls
= shader_out
->key
.as_ls
;
6216 key
->vs_prolog
.as_es
= shader_out
->key
.as_es
;
6218 if (shader_out
->selector
->type
== PIPE_SHADER_TESS_CTRL
) {
6219 key
->vs_prolog
.as_ls
= 1;
6220 key
->vs_prolog
.num_merged_next_stage_vgprs
= 2;
6221 } else if (shader_out
->selector
->type
== PIPE_SHADER_GEOMETRY
) {
6222 key
->vs_prolog
.as_es
= 1;
6223 key
->vs_prolog
.num_merged_next_stage_vgprs
= 5;
6226 /* Enable loading the InstanceID VGPR. */
6227 uint16_t input_mask
= u_bit_consecutive(0, info
->num_inputs
);
6229 if ((key
->vs_prolog
.states
.instance_divisor_is_one
|
6230 key
->vs_prolog
.states
.instance_divisor_is_fetched
) & input_mask
)
6231 shader_out
->info
.uses_instanceid
= true;
6235 * Compute the PS prolog key, which contains all the information needed to
6236 * build the PS prolog function, and set related bits in shader->config.
6238 static void si_get_ps_prolog_key(struct si_shader
*shader
,
6239 union si_shader_part_key
*key
,
6240 bool separate_prolog
)
6242 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6244 memset(key
, 0, sizeof(*key
));
6245 key
->ps_prolog
.states
= shader
->key
.part
.ps
.prolog
;
6246 key
->ps_prolog
.colors_read
= info
->colors_read
;
6247 key
->ps_prolog
.num_input_sgprs
= shader
->info
.num_input_sgprs
;
6248 key
->ps_prolog
.num_input_vgprs
= shader
->info
.num_input_vgprs
;
6249 key
->ps_prolog
.wqm
= info
->uses_derivatives
&&
6250 (key
->ps_prolog
.colors_read
||
6251 key
->ps_prolog
.states
.force_persp_sample_interp
||
6252 key
->ps_prolog
.states
.force_linear_sample_interp
||
6253 key
->ps_prolog
.states
.force_persp_center_interp
||
6254 key
->ps_prolog
.states
.force_linear_center_interp
||
6255 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6256 key
->ps_prolog
.states
.bc_optimize_for_linear
);
6257 key
->ps_prolog
.ancillary_vgpr_index
= shader
->info
.ancillary_vgpr_index
;
6259 if (info
->colors_read
) {
6260 unsigned *color
= shader
->selector
->color_attr_index
;
6262 if (shader
->key
.part
.ps
.prolog
.color_two_side
) {
6263 /* BCOLORs are stored after the last input. */
6264 key
->ps_prolog
.num_interp_inputs
= info
->num_inputs
;
6265 key
->ps_prolog
.face_vgpr_index
= shader
->info
.face_vgpr_index
;
6266 shader
->config
.spi_ps_input_ena
|= S_0286CC_FRONT_FACE_ENA(1);
6269 for (unsigned i
= 0; i
< 2; i
++) {
6270 unsigned interp
= info
->input_interpolate
[color
[i
]];
6271 unsigned location
= info
->input_interpolate_loc
[color
[i
]];
6273 if (!(info
->colors_read
& (0xf << i
*4)))
6276 key
->ps_prolog
.color_attr_index
[i
] = color
[i
];
6278 if (shader
->key
.part
.ps
.prolog
.flatshade_colors
&&
6279 interp
== TGSI_INTERPOLATE_COLOR
)
6280 interp
= TGSI_INTERPOLATE_CONSTANT
;
6283 case TGSI_INTERPOLATE_CONSTANT
:
6284 key
->ps_prolog
.color_interp_vgpr_index
[i
] = -1;
6286 case TGSI_INTERPOLATE_PERSPECTIVE
:
6287 case TGSI_INTERPOLATE_COLOR
:
6288 /* Force the interpolation location for colors here. */
6289 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
)
6290 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6291 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
)
6292 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6295 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6296 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 0;
6297 shader
->config
.spi_ps_input_ena
|=
6298 S_0286CC_PERSP_SAMPLE_ENA(1);
6300 case TGSI_INTERPOLATE_LOC_CENTER
:
6301 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 2;
6302 shader
->config
.spi_ps_input_ena
|=
6303 S_0286CC_PERSP_CENTER_ENA(1);
6305 case TGSI_INTERPOLATE_LOC_CENTROID
:
6306 key
->ps_prolog
.color_interp_vgpr_index
[i
] = 4;
6307 shader
->config
.spi_ps_input_ena
|=
6308 S_0286CC_PERSP_CENTROID_ENA(1);
6314 case TGSI_INTERPOLATE_LINEAR
:
6315 /* Force the interpolation location for colors here. */
6316 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
)
6317 location
= TGSI_INTERPOLATE_LOC_SAMPLE
;
6318 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
)
6319 location
= TGSI_INTERPOLATE_LOC_CENTER
;
6321 /* The VGPR assignment for non-monolithic shaders
6322 * works because InitialPSInputAddr is set on the
6323 * main shader and PERSP_PULL_MODEL is never used.
6326 case TGSI_INTERPOLATE_LOC_SAMPLE
:
6327 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6328 separate_prolog
? 6 : 9;
6329 shader
->config
.spi_ps_input_ena
|=
6330 S_0286CC_LINEAR_SAMPLE_ENA(1);
6332 case TGSI_INTERPOLATE_LOC_CENTER
:
6333 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6334 separate_prolog
? 8 : 11;
6335 shader
->config
.spi_ps_input_ena
|=
6336 S_0286CC_LINEAR_CENTER_ENA(1);
6338 case TGSI_INTERPOLATE_LOC_CENTROID
:
6339 key
->ps_prolog
.color_interp_vgpr_index
[i
] =
6340 separate_prolog
? 10 : 13;
6341 shader
->config
.spi_ps_input_ena
|=
6342 S_0286CC_LINEAR_CENTROID_ENA(1);
6356 * Check whether a PS prolog is required based on the key.
6358 static bool si_need_ps_prolog(const union si_shader_part_key
*key
)
6360 return key
->ps_prolog
.colors_read
||
6361 key
->ps_prolog
.states
.force_persp_sample_interp
||
6362 key
->ps_prolog
.states
.force_linear_sample_interp
||
6363 key
->ps_prolog
.states
.force_persp_center_interp
||
6364 key
->ps_prolog
.states
.force_linear_center_interp
||
6365 key
->ps_prolog
.states
.bc_optimize_for_persp
||
6366 key
->ps_prolog
.states
.bc_optimize_for_linear
||
6367 key
->ps_prolog
.states
.poly_stipple
||
6368 key
->ps_prolog
.states
.samplemask_log_ps_iter
;
6372 * Compute the PS epilog key, which contains all the information needed to
6373 * build the PS epilog function.
6375 static void si_get_ps_epilog_key(struct si_shader
*shader
,
6376 union si_shader_part_key
*key
)
6378 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
6379 memset(key
, 0, sizeof(*key
));
6380 key
->ps_epilog
.colors_written
= info
->colors_written
;
6381 key
->ps_epilog
.writes_z
= info
->writes_z
;
6382 key
->ps_epilog
.writes_stencil
= info
->writes_stencil
;
6383 key
->ps_epilog
.writes_samplemask
= info
->writes_samplemask
;
6384 key
->ps_epilog
.states
= shader
->key
.part
.ps
.epilog
;
6388 * Build the GS prolog function. Rotate the input vertices for triangle strips
6391 static void si_build_gs_prolog_function(struct si_shader_context
*ctx
,
6392 union si_shader_part_key
*key
)
6394 unsigned num_sgprs
, num_vgprs
;
6395 struct si_function_info fninfo
;
6396 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6397 LLVMTypeRef returns
[48];
6398 LLVMValueRef func
, ret
;
6400 si_init_function_info(&fninfo
);
6402 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6403 if (key
->gs_prolog
.states
.gfx9_prev_is_vs
)
6404 num_sgprs
= 8 + GFX9_VSGS_NUM_USER_SGPR
;
6406 num_sgprs
= 8 + GFX9_TESGS_NUM_USER_SGPR
;
6407 num_vgprs
= 5; /* ES inputs are not needed by GS */
6409 num_sgprs
= GFX6_GS_NUM_USER_SGPR
+ 2;
6413 for (unsigned i
= 0; i
< num_sgprs
; ++i
) {
6414 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
6415 returns
[i
] = ctx
->i32
;
6418 for (unsigned i
= 0; i
< num_vgprs
; ++i
) {
6419 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
);
6420 returns
[num_sgprs
+ i
] = ctx
->f32
;
6423 /* Create the function. */
6424 si_create_function(ctx
, "gs_prolog", returns
, num_sgprs
+ num_vgprs
,
6426 func
= ctx
->main_fn
;
6428 /* Set the full EXEC mask for the prolog, because we are only fiddling
6429 * with registers here. The main shader part will set the correct EXEC
6432 if (ctx
->screen
->info
.chip_class
>= GFX9
&& !key
->gs_prolog
.is_monolithic
)
6433 ac_init_exec_full_mask(&ctx
->ac
);
6435 /* Copy inputs to outputs. This should be no-op, as the registers match,
6436 * but it will prevent the compiler from overwriting them unintentionally.
6438 ret
= ctx
->return_value
;
6439 for (unsigned i
= 0; i
< num_sgprs
; i
++) {
6440 LLVMValueRef p
= LLVMGetParam(func
, i
);
6441 ret
= LLVMBuildInsertValue(builder
, ret
, p
, i
, "");
6443 for (unsigned i
= 0; i
< num_vgprs
; i
++) {
6444 LLVMValueRef p
= LLVMGetParam(func
, num_sgprs
+ i
);
6445 p
= ac_to_float(&ctx
->ac
, p
);
6446 ret
= LLVMBuildInsertValue(builder
, ret
, p
, num_sgprs
+ i
, "");
6449 if (key
->gs_prolog
.states
.tri_strip_adj_fix
) {
6450 /* Remap the input vertices for every other primitive. */
6451 const unsigned gfx6_vtx_params
[6] = {
6459 const unsigned gfx9_vtx_params
[3] = {
6464 LLVMValueRef vtx_in
[6], vtx_out
[6];
6465 LLVMValueRef prim_id
, rotate
;
6467 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6468 for (unsigned i
= 0; i
< 3; i
++) {
6469 vtx_in
[i
*2] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 0, 16);
6470 vtx_in
[i
*2+1] = si_unpack_param(ctx
, gfx9_vtx_params
[i
], 16, 16);
6473 for (unsigned i
= 0; i
< 6; i
++)
6474 vtx_in
[i
] = LLVMGetParam(func
, gfx6_vtx_params
[i
]);
6477 prim_id
= LLVMGetParam(func
, num_sgprs
+ 2);
6478 rotate
= LLVMBuildTrunc(builder
, prim_id
, ctx
->i1
, "");
6480 for (unsigned i
= 0; i
< 6; ++i
) {
6481 LLVMValueRef base
, rotated
;
6483 rotated
= vtx_in
[(i
+ 4) % 6];
6484 vtx_out
[i
] = LLVMBuildSelect(builder
, rotate
, rotated
, base
, "");
6487 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
6488 for (unsigned i
= 0; i
< 3; i
++) {
6489 LLVMValueRef hi
, out
;
6491 hi
= LLVMBuildShl(builder
, vtx_out
[i
*2+1],
6492 LLVMConstInt(ctx
->i32
, 16, 0), "");
6493 out
= LLVMBuildOr(builder
, vtx_out
[i
*2], hi
, "");
6494 out
= ac_to_float(&ctx
->ac
, out
);
6495 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6496 gfx9_vtx_params
[i
], "");
6499 for (unsigned i
= 0; i
< 6; i
++) {
6502 out
= ac_to_float(&ctx
->ac
, vtx_out
[i
]);
6503 ret
= LLVMBuildInsertValue(builder
, ret
, out
,
6504 gfx6_vtx_params
[i
], "");
6509 LLVMBuildRet(builder
, ret
);
6513 * Given a list of shader part functions, build a wrapper function that
6514 * runs them in sequence to form a monolithic shader.
6516 static void si_build_wrapper_function(struct si_shader_context
*ctx
,
6517 LLVMValueRef
*parts
,
6520 unsigned next_shader_first_part
)
6522 LLVMBuilderRef builder
= ctx
->ac
.builder
;
6523 /* PS epilog has one arg per color component; gfx9 merged shader
6524 * prologs need to forward 32 user SGPRs.
6526 struct si_function_info fninfo
;
6527 LLVMValueRef initial
[64], out
[64];
6528 LLVMTypeRef function_type
;
6529 unsigned num_first_params
;
6530 unsigned num_out
, initial_num_out
;
6531 MAYBE_UNUSED
unsigned num_out_sgpr
; /* used in debug checks */
6532 MAYBE_UNUSED
unsigned initial_num_out_sgpr
; /* used in debug checks */
6533 unsigned num_sgprs
, num_vgprs
;
6535 struct lp_build_if_state if_state
;
6537 si_init_function_info(&fninfo
);
6539 for (unsigned i
= 0; i
< num_parts
; ++i
) {
6540 ac_add_function_attr(ctx
->ac
.context
, parts
[i
], -1,
6541 AC_FUNC_ATTR_ALWAYSINLINE
);
6542 LLVMSetLinkage(parts
[i
], LLVMPrivateLinkage
);
6545 /* The parameters of the wrapper function correspond to those of the
6546 * first part in terms of SGPRs and VGPRs, but we use the types of the
6547 * main part to get the right types. This is relevant for the
6548 * dereferenceable attribute on descriptor table pointers.
6553 function_type
= LLVMGetElementType(LLVMTypeOf(parts
[0]));
6554 num_first_params
= LLVMCountParamTypes(function_type
);
6556 for (unsigned i
= 0; i
< num_first_params
; ++i
) {
6557 LLVMValueRef param
= LLVMGetParam(parts
[0], i
);
6559 if (ac_is_sgpr_param(param
)) {
6560 assert(num_vgprs
== 0);
6561 num_sgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6563 num_vgprs
+= ac_get_type_size(LLVMTypeOf(param
)) / 4;
6568 while (gprs
< num_sgprs
+ num_vgprs
) {
6569 LLVMValueRef param
= LLVMGetParam(parts
[main_part
], fninfo
.num_params
);
6570 LLVMTypeRef type
= LLVMTypeOf(param
);
6571 unsigned size
= ac_get_type_size(type
) / 4;
6573 add_arg(&fninfo
, gprs
< num_sgprs
? ARG_SGPR
: ARG_VGPR
, type
);
6575 assert(ac_is_sgpr_param(param
) == (gprs
< num_sgprs
));
6576 assert(gprs
+ size
<= num_sgprs
+ num_vgprs
&&
6577 (gprs
>= num_sgprs
|| gprs
+ size
<= num_sgprs
));
6582 si_create_function(ctx
, "wrapper", NULL
, 0, &fninfo
,
6583 si_get_max_workgroup_size(ctx
->shader
));
6585 if (is_merged_shader(ctx
->shader
))
6586 ac_init_exec_full_mask(&ctx
->ac
);
6588 /* Record the arguments of the function as if they were an output of
6594 for (unsigned i
= 0; i
< fninfo
.num_params
; ++i
) {
6595 LLVMValueRef param
= LLVMGetParam(ctx
->main_fn
, i
);
6596 LLVMTypeRef param_type
= LLVMTypeOf(param
);
6597 LLVMTypeRef out_type
= i
< fninfo
.num_sgpr_params
? ctx
->i32
: ctx
->f32
;
6598 unsigned size
= ac_get_type_size(param_type
) / 4;
6601 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6602 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i32
, "");
6603 param_type
= ctx
->i32
;
6606 if (param_type
!= out_type
)
6607 param
= LLVMBuildBitCast(builder
, param
, out_type
, "");
6608 out
[num_out
++] = param
;
6610 LLVMTypeRef vector_type
= LLVMVectorType(out_type
, size
);
6612 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6613 param
= LLVMBuildPtrToInt(builder
, param
, ctx
->i64
, "");
6614 param_type
= ctx
->i64
;
6617 if (param_type
!= vector_type
)
6618 param
= LLVMBuildBitCast(builder
, param
, vector_type
, "");
6620 for (unsigned j
= 0; j
< size
; ++j
)
6621 out
[num_out
++] = LLVMBuildExtractElement(
6622 builder
, param
, LLVMConstInt(ctx
->i32
, j
, 0), "");
6625 if (i
< fninfo
.num_sgpr_params
)
6626 num_out_sgpr
= num_out
;
6629 memcpy(initial
, out
, sizeof(out
));
6630 initial_num_out
= num_out
;
6631 initial_num_out_sgpr
= num_out_sgpr
;
6633 /* Now chain the parts. */
6634 for (unsigned part
= 0; part
< num_parts
; ++part
) {
6635 LLVMValueRef in
[48];
6637 LLVMTypeRef ret_type
;
6638 unsigned out_idx
= 0;
6639 unsigned num_params
= LLVMCountParams(parts
[part
]);
6641 /* Merged shaders are executed conditionally depending
6642 * on the number of enabled threads passed in the input SGPRs. */
6643 if (is_merged_shader(ctx
->shader
) && part
== 0) {
6644 LLVMValueRef ena
, count
= initial
[3];
6646 count
= LLVMBuildAnd(builder
, count
,
6647 LLVMConstInt(ctx
->i32
, 0x7f, 0), "");
6648 ena
= LLVMBuildICmp(builder
, LLVMIntULT
,
6649 ac_get_thread_id(&ctx
->ac
), count
, "");
6650 lp_build_if(&if_state
, &ctx
->gallivm
, ena
);
6653 /* Derive arguments for the next part from outputs of the
6656 for (unsigned param_idx
= 0; param_idx
< num_params
; ++param_idx
) {
6658 LLVMTypeRef param_type
;
6660 unsigned param_size
;
6661 LLVMValueRef arg
= NULL
;
6663 param
= LLVMGetParam(parts
[part
], param_idx
);
6664 param_type
= LLVMTypeOf(param
);
6665 param_size
= ac_get_type_size(param_type
) / 4;
6666 is_sgpr
= ac_is_sgpr_param(param
);
6669 ac_add_function_attr(ctx
->ac
.context
, parts
[part
],
6670 param_idx
+ 1, AC_FUNC_ATTR_INREG
);
6671 } else if (out_idx
< num_out_sgpr
) {
6672 /* Skip returned SGPRs the current part doesn't
6673 * declare on the input. */
6674 out_idx
= num_out_sgpr
;
6677 assert(out_idx
+ param_size
<= (is_sgpr
? num_out_sgpr
: num_out
));
6679 if (param_size
== 1)
6682 arg
= ac_build_gather_values(&ctx
->ac
, &out
[out_idx
], param_size
);
6684 if (LLVMTypeOf(arg
) != param_type
) {
6685 if (LLVMGetTypeKind(param_type
) == LLVMPointerTypeKind
) {
6686 if (LLVMGetPointerAddressSpace(param_type
) ==
6687 AC_CONST_32BIT_ADDR_SPACE
) {
6688 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i32
, "");
6689 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6691 arg
= LLVMBuildBitCast(builder
, arg
, ctx
->i64
, "");
6692 arg
= LLVMBuildIntToPtr(builder
, arg
, param_type
, "");
6695 arg
= LLVMBuildBitCast(builder
, arg
, param_type
, "");
6699 in
[param_idx
] = arg
;
6700 out_idx
+= param_size
;
6703 ret
= LLVMBuildCall(builder
, parts
[part
], in
, num_params
, "");
6705 if (is_merged_shader(ctx
->shader
) &&
6706 part
+ 1 == next_shader_first_part
) {
6707 lp_build_endif(&if_state
);
6709 /* The second half of the merged shader should use
6710 * the inputs from the toplevel (wrapper) function,
6711 * not the return value from the last call.
6713 * That's because the last call was executed condi-
6714 * tionally, so we can't consume it in the main
6717 memcpy(out
, initial
, sizeof(initial
));
6718 num_out
= initial_num_out
;
6719 num_out_sgpr
= initial_num_out_sgpr
;
6723 /* Extract the returned GPRs. */
6724 ret_type
= LLVMTypeOf(ret
);
6728 if (LLVMGetTypeKind(ret_type
) != LLVMVoidTypeKind
) {
6729 assert(LLVMGetTypeKind(ret_type
) == LLVMStructTypeKind
);
6731 unsigned ret_size
= LLVMCountStructElementTypes(ret_type
);
6733 for (unsigned i
= 0; i
< ret_size
; ++i
) {
6735 LLVMBuildExtractValue(builder
, ret
, i
, "");
6737 assert(num_out
< ARRAY_SIZE(out
));
6738 out
[num_out
++] = val
;
6740 if (LLVMTypeOf(val
) == ctx
->i32
) {
6741 assert(num_out_sgpr
+ 1 == num_out
);
6742 num_out_sgpr
= num_out
;
6748 LLVMBuildRetVoid(builder
);
6751 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
6752 struct si_compiler
*compiler
,
6753 struct si_shader
*shader
,
6754 struct pipe_debug_callback
*debug
)
6756 struct si_shader_selector
*sel
= shader
->selector
;
6757 struct si_shader_context ctx
;
6760 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6761 * conversion fails. */
6762 if (si_can_dump_shader(sscreen
, sel
->info
.processor
) &&
6763 !(sscreen
->debug_flags
& DBG(NO_TGSI
))) {
6765 tgsi_dump(sel
->tokens
, 0);
6767 nir_print_shader(sel
->nir
, stderr
);
6768 si_dump_streamout(&sel
->so
);
6771 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
6772 si_llvm_context_set_tgsi(&ctx
, shader
);
6774 memset(shader
->info
.vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6775 sizeof(shader
->info
.vs_output_param_offset
));
6777 shader
->info
.uses_instanceid
= sel
->info
.uses_instanceid
;
6779 if (!si_compile_tgsi_main(&ctx
)) {
6780 si_llvm_dispose(&ctx
);
6784 if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_VERTEX
) {
6785 LLVMValueRef parts
[2];
6786 bool need_prolog
= sel
->vs_needs_prolog
;
6788 parts
[1] = ctx
.main_fn
;
6791 union si_shader_part_key prolog_key
;
6792 si_get_vs_prolog_key(&sel
->info
,
6793 shader
->info
.num_input_sgprs
,
6794 &shader
->key
.part
.vs
.prolog
,
6795 shader
, &prolog_key
);
6796 si_build_vs_prolog_function(&ctx
, &prolog_key
);
6797 parts
[0] = ctx
.main_fn
;
6800 si_build_wrapper_function(&ctx
, parts
+ !need_prolog
,
6801 1 + need_prolog
, need_prolog
, 0);
6802 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
6803 if (sscreen
->info
.chip_class
>= GFX9
) {
6804 struct si_shader_selector
*ls
= shader
->key
.part
.tcs
.ls
;
6805 LLVMValueRef parts
[4];
6806 bool vs_needs_prolog
=
6807 si_vs_needs_prolog(ls
, &shader
->key
.part
.tcs
.ls_prolog
);
6810 parts
[2] = ctx
.main_fn
;
6813 union si_shader_part_key tcs_epilog_key
;
6814 memset(&tcs_epilog_key
, 0, sizeof(tcs_epilog_key
));
6815 tcs_epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6816 si_build_tcs_epilog_function(&ctx
, &tcs_epilog_key
);
6817 parts
[3] = ctx
.main_fn
;
6819 /* VS as LS main part */
6820 struct si_shader shader_ls
= {};
6821 shader_ls
.selector
= ls
;
6822 shader_ls
.key
.as_ls
= 1;
6823 shader_ls
.key
.mono
= shader
->key
.mono
;
6824 shader_ls
.key
.opt
= shader
->key
.opt
;
6825 shader_ls
.is_monolithic
= true;
6826 si_llvm_context_set_tgsi(&ctx
, &shader_ls
);
6828 if (!si_compile_tgsi_main(&ctx
)) {
6829 si_llvm_dispose(&ctx
);
6832 shader
->info
.uses_instanceid
|= ls
->info
.uses_instanceid
;
6833 parts
[1] = ctx
.main_fn
;
6836 if (vs_needs_prolog
) {
6837 union si_shader_part_key vs_prolog_key
;
6838 si_get_vs_prolog_key(&ls
->info
,
6839 shader_ls
.info
.num_input_sgprs
,
6840 &shader
->key
.part
.tcs
.ls_prolog
,
6841 shader
, &vs_prolog_key
);
6842 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6843 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6844 parts
[0] = ctx
.main_fn
;
6847 /* Reset the shader context. */
6848 ctx
.shader
= shader
;
6849 ctx
.type
= PIPE_SHADER_TESS_CTRL
;
6851 si_build_wrapper_function(&ctx
,
6852 parts
+ !vs_needs_prolog
,
6853 4 - !vs_needs_prolog
, vs_needs_prolog
,
6854 vs_needs_prolog
? 2 : 1);
6856 LLVMValueRef parts
[2];
6857 union si_shader_part_key epilog_key
;
6859 parts
[0] = ctx
.main_fn
;
6861 memset(&epilog_key
, 0, sizeof(epilog_key
));
6862 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
6863 si_build_tcs_epilog_function(&ctx
, &epilog_key
);
6864 parts
[1] = ctx
.main_fn
;
6866 si_build_wrapper_function(&ctx
, parts
, 2, 0, 0);
6868 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_GEOMETRY
) {
6869 if (ctx
.screen
->info
.chip_class
>= GFX9
) {
6870 struct si_shader_selector
*es
= shader
->key
.part
.gs
.es
;
6871 LLVMValueRef es_prolog
= NULL
;
6872 LLVMValueRef es_main
= NULL
;
6873 LLVMValueRef gs_prolog
= NULL
;
6874 LLVMValueRef gs_main
= ctx
.main_fn
;
6877 union si_shader_part_key gs_prolog_key
;
6878 memset(&gs_prolog_key
, 0, sizeof(gs_prolog_key
));
6879 gs_prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6880 gs_prolog_key
.gs_prolog
.is_monolithic
= true;
6881 si_build_gs_prolog_function(&ctx
, &gs_prolog_key
);
6882 gs_prolog
= ctx
.main_fn
;
6885 struct si_shader shader_es
= {};
6886 shader_es
.selector
= es
;
6887 shader_es
.key
.as_es
= 1;
6888 shader_es
.key
.mono
= shader
->key
.mono
;
6889 shader_es
.key
.opt
= shader
->key
.opt
;
6890 shader_es
.is_monolithic
= true;
6891 si_llvm_context_set_tgsi(&ctx
, &shader_es
);
6893 if (!si_compile_tgsi_main(&ctx
)) {
6894 si_llvm_dispose(&ctx
);
6897 shader
->info
.uses_instanceid
|= es
->info
.uses_instanceid
;
6898 es_main
= ctx
.main_fn
;
6901 if (es
->vs_needs_prolog
) {
6902 union si_shader_part_key vs_prolog_key
;
6903 si_get_vs_prolog_key(&es
->info
,
6904 shader_es
.info
.num_input_sgprs
,
6905 &shader
->key
.part
.gs
.vs_prolog
,
6906 shader
, &vs_prolog_key
);
6907 vs_prolog_key
.vs_prolog
.is_monolithic
= true;
6908 si_build_vs_prolog_function(&ctx
, &vs_prolog_key
);
6909 es_prolog
= ctx
.main_fn
;
6912 /* Reset the shader context. */
6913 ctx
.shader
= shader
;
6914 ctx
.type
= PIPE_SHADER_GEOMETRY
;
6916 /* Prepare the array of shader parts. */
6917 LLVMValueRef parts
[4];
6918 unsigned num_parts
= 0, main_part
, next_first_part
;
6921 parts
[num_parts
++] = es_prolog
;
6923 parts
[main_part
= num_parts
++] = es_main
;
6924 parts
[next_first_part
= num_parts
++] = gs_prolog
;
6925 parts
[num_parts
++] = gs_main
;
6927 si_build_wrapper_function(&ctx
, parts
, num_parts
,
6928 main_part
, next_first_part
);
6930 LLVMValueRef parts
[2];
6931 union si_shader_part_key prolog_key
;
6933 parts
[1] = ctx
.main_fn
;
6935 memset(&prolog_key
, 0, sizeof(prolog_key
));
6936 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
6937 si_build_gs_prolog_function(&ctx
, &prolog_key
);
6938 parts
[0] = ctx
.main_fn
;
6940 si_build_wrapper_function(&ctx
, parts
, 2, 1, 0);
6942 } else if (shader
->is_monolithic
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
6943 LLVMValueRef parts
[3];
6944 union si_shader_part_key prolog_key
;
6945 union si_shader_part_key epilog_key
;
6948 si_get_ps_prolog_key(shader
, &prolog_key
, false);
6949 need_prolog
= si_need_ps_prolog(&prolog_key
);
6951 parts
[need_prolog
? 1 : 0] = ctx
.main_fn
;
6954 si_build_ps_prolog_function(&ctx
, &prolog_key
);
6955 parts
[0] = ctx
.main_fn
;
6958 si_get_ps_epilog_key(shader
, &epilog_key
);
6959 si_build_ps_epilog_function(&ctx
, &epilog_key
);
6960 parts
[need_prolog
? 2 : 1] = ctx
.main_fn
;
6962 si_build_wrapper_function(&ctx
, parts
, need_prolog
? 3 : 2,
6963 need_prolog
? 1 : 0, 0);
6966 si_llvm_optimize_module(&ctx
);
6968 /* Post-optimization transformations and analysis. */
6969 si_optimize_vs_outputs(&ctx
);
6971 if ((debug
&& debug
->debug_message
) ||
6972 si_can_dump_shader(sscreen
, ctx
.type
)) {
6973 ctx
.shader
->config
.private_mem_vgprs
=
6974 ac_count_scratch_private_memory(ctx
.main_fn
);
6977 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6978 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx
.main_fn
, 0))) ==
6979 LLVMPointerTypeKind
);
6981 /* Compile to bytecode. */
6982 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, compiler
,
6983 ctx
.ac
.module
, debug
, ctx
.type
, "TGSI shader");
6984 si_llvm_dispose(&ctx
);
6986 fprintf(stderr
, "LLVM failed to compile shader\n");
6990 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6991 * LLVM 3.9svn has this bug.
6993 if (sel
->type
== PIPE_SHADER_COMPUTE
) {
6994 unsigned wave_size
= 64;
6995 unsigned max_vgprs
= 256;
6996 unsigned max_sgprs
= sscreen
->info
.chip_class
>= VI
? 800 : 512;
6997 unsigned max_sgprs_per_wave
= 128;
6998 unsigned max_block_threads
= si_get_max_workgroup_size(shader
);
6999 unsigned min_waves_per_cu
= DIV_ROUND_UP(max_block_threads
, wave_size
);
7000 unsigned min_waves_per_simd
= DIV_ROUND_UP(min_waves_per_cu
, 4);
7002 max_vgprs
= max_vgprs
/ min_waves_per_simd
;
7003 max_sgprs
= MIN2(max_sgprs
/ min_waves_per_simd
, max_sgprs_per_wave
);
7005 if (shader
->config
.num_sgprs
> max_sgprs
||
7006 shader
->config
.num_vgprs
> max_vgprs
) {
7007 fprintf(stderr
, "LLVM failed to compile a shader correctly: "
7008 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7009 shader
->config
.num_sgprs
, shader
->config
.num_vgprs
,
7010 max_sgprs
, max_vgprs
);
7012 /* Just terminate the process, because dependent
7013 * shaders can hang due to bad input data, but use
7014 * the env var to allow shader-db to work.
7016 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7021 /* Add the scratch offset to input SGPRs. */
7022 if (shader
->config
.scratch_bytes_per_wave
&& !is_merged_shader(shader
))
7023 shader
->info
.num_input_sgprs
+= 1; /* scratch byte offset */
7025 /* Calculate the number of fragment input VGPRs. */
7026 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
7027 shader
->info
.num_input_vgprs
= 0;
7028 shader
->info
.face_vgpr_index
= -1;
7029 shader
->info
.ancillary_vgpr_index
= -1;
7031 if (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7032 shader
->info
.num_input_vgprs
+= 2;
7033 if (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7034 shader
->info
.num_input_vgprs
+= 2;
7035 if (G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7036 shader
->info
.num_input_vgprs
+= 2;
7037 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader
->config
.spi_ps_input_addr
))
7038 shader
->info
.num_input_vgprs
+= 3;
7039 if (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_addr
))
7040 shader
->info
.num_input_vgprs
+= 2;
7041 if (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
))
7042 shader
->info
.num_input_vgprs
+= 2;
7043 if (G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_addr
))
7044 shader
->info
.num_input_vgprs
+= 2;
7045 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader
->config
.spi_ps_input_addr
))
7046 shader
->info
.num_input_vgprs
+= 1;
7047 if (G_0286CC_POS_X_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7048 shader
->info
.num_input_vgprs
+= 1;
7049 if (G_0286CC_POS_Y_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7050 shader
->info
.num_input_vgprs
+= 1;
7051 if (G_0286CC_POS_Z_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7052 shader
->info
.num_input_vgprs
+= 1;
7053 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_addr
))
7054 shader
->info
.num_input_vgprs
+= 1;
7055 if (G_0286CC_FRONT_FACE_ENA(shader
->config
.spi_ps_input_addr
)) {
7056 shader
->info
.face_vgpr_index
= shader
->info
.num_input_vgprs
;
7057 shader
->info
.num_input_vgprs
+= 1;
7059 if (G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
)) {
7060 shader
->info
.ancillary_vgpr_index
= shader
->info
.num_input_vgprs
;
7061 shader
->info
.num_input_vgprs
+= 1;
7063 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader
->config
.spi_ps_input_addr
))
7064 shader
->info
.num_input_vgprs
+= 1;
7065 if (G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
))
7066 shader
->info
.num_input_vgprs
+= 1;
7069 si_calculate_max_simd_waves(shader
);
7070 si_shader_dump_stats_for_shader_db(shader
, debug
);
7075 * Create, compile and return a shader part (prolog or epilog).
7077 * \param sscreen screen
7078 * \param list list of shader parts of the same category
7079 * \param type shader type
7080 * \param key shader part key
7081 * \param prolog whether the part being requested is a prolog
7082 * \param tm LLVM target machine
7083 * \param debug debug callback
7084 * \param build the callback responsible for building the main function
7085 * \return non-NULL on success
7087 static struct si_shader_part
*
7088 si_get_shader_part(struct si_screen
*sscreen
,
7089 struct si_shader_part
**list
,
7090 enum pipe_shader_type type
,
7092 union si_shader_part_key
*key
,
7093 struct si_compiler
*compiler
,
7094 struct pipe_debug_callback
*debug
,
7095 void (*build
)(struct si_shader_context
*,
7096 union si_shader_part_key
*),
7099 struct si_shader_part
*result
;
7101 mtx_lock(&sscreen
->shader_parts_mutex
);
7103 /* Find existing. */
7104 for (result
= *list
; result
; result
= result
->next
) {
7105 if (memcmp(&result
->key
, key
, sizeof(*key
)) == 0) {
7106 mtx_unlock(&sscreen
->shader_parts_mutex
);
7111 /* Compile a new one. */
7112 result
= CALLOC_STRUCT(si_shader_part
);
7115 struct si_shader shader
= {};
7116 struct si_shader_context ctx
;
7118 si_init_shader_ctx(&ctx
, sscreen
, compiler
);
7119 ctx
.shader
= &shader
;
7123 case PIPE_SHADER_VERTEX
:
7124 shader
.key
.as_ls
= key
->vs_prolog
.as_ls
;
7125 shader
.key
.as_es
= key
->vs_prolog
.as_es
;
7127 case PIPE_SHADER_TESS_CTRL
:
7129 shader
.key
.part
.tcs
.epilog
= key
->tcs_epilog
.states
;
7131 case PIPE_SHADER_GEOMETRY
:
7134 case PIPE_SHADER_FRAGMENT
:
7136 shader
.key
.part
.ps
.prolog
= key
->ps_prolog
.states
;
7138 shader
.key
.part
.ps
.epilog
= key
->ps_epilog
.states
;
7141 unreachable("bad shader part");
7147 si_llvm_optimize_module(&ctx
);
7149 if (si_compile_llvm(sscreen
, &result
->binary
, &result
->config
, compiler
,
7150 ctx
.ac
.module
, debug
, ctx
.type
, name
)) {
7156 result
->next
= *list
;
7160 si_llvm_dispose(&ctx
);
7161 mtx_unlock(&sscreen
->shader_parts_mutex
);
7165 static LLVMValueRef
si_prolog_get_rw_buffers(struct si_shader_context
*ctx
)
7167 LLVMValueRef ptr
[2], list
;
7168 bool is_merged_shader
=
7169 ctx
->screen
->info
.chip_class
>= GFX9
&&
7170 (ctx
->type
== PIPE_SHADER_TESS_CTRL
||
7171 ctx
->type
== PIPE_SHADER_GEOMETRY
||
7172 ctx
->shader
->key
.as_ls
|| ctx
->shader
->key
.as_es
);
7174 if (HAVE_32BIT_POINTERS
) {
7175 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
7176 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, ptr
[0],
7177 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
7181 /* Get the pointer to rw buffers. */
7182 ptr
[0] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
);
7183 ptr
[1] = LLVMGetParam(ctx
->main_fn
, (is_merged_shader
? 8 : 0) + SI_SGPR_RW_BUFFERS
+ 1);
7184 list
= ac_build_gather_values(&ctx
->ac
, ptr
, 2);
7185 list
= LLVMBuildBitCast(ctx
->ac
.builder
, list
, ctx
->i64
, "");
7186 list
= LLVMBuildIntToPtr(ctx
->ac
.builder
, list
,
7187 ac_array_in_const_addr_space(ctx
->v4i32
), "");
7192 * Build the vertex shader prolog function.
7194 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7195 * All inputs are returned unmodified. The vertex load indices are
7196 * stored after them, which will be used by the API VS for fetching inputs.
7198 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7203 * (VertexID + BaseVertex),
7204 * (InstanceID + StartInstance),
7205 * (InstanceID / 2 + StartInstance)
7207 static void si_build_vs_prolog_function(struct si_shader_context
*ctx
,
7208 union si_shader_part_key
*key
)
7210 struct si_function_info fninfo
;
7211 LLVMTypeRef
*returns
;
7212 LLVMValueRef ret
, func
;
7214 unsigned first_vs_vgpr
= key
->vs_prolog
.num_merged_next_stage_vgprs
;
7215 unsigned num_input_vgprs
= key
->vs_prolog
.num_merged_next_stage_vgprs
+ 4;
7216 LLVMValueRef input_vgprs
[9];
7217 unsigned num_all_input_regs
= key
->vs_prolog
.num_input_sgprs
+
7219 unsigned user_sgpr_base
= key
->vs_prolog
.num_merged_next_stage_vgprs
? 8 : 0;
7221 si_init_function_info(&fninfo
);
7223 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7224 returns
= alloca((num_all_input_regs
+ key
->vs_prolog
.last_input
+ 1) *
7225 sizeof(LLVMTypeRef
));
7228 /* Declare input and output SGPRs. */
7229 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7230 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7231 returns
[num_returns
++] = ctx
->i32
;
7234 /* Preloaded VGPRs (outputs must be floats) */
7235 for (i
= 0; i
< num_input_vgprs
; i
++) {
7236 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &input_vgprs
[i
]);
7237 returns
[num_returns
++] = ctx
->f32
;
7240 /* Vertex load indices. */
7241 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++)
7242 returns
[num_returns
++] = ctx
->f32
;
7244 /* Create the function. */
7245 si_create_function(ctx
, "vs_prolog", returns
, num_returns
, &fninfo
, 0);
7246 func
= ctx
->main_fn
;
7248 if (key
->vs_prolog
.num_merged_next_stage_vgprs
) {
7249 if (!key
->vs_prolog
.is_monolithic
)
7250 si_init_exec_from_input(ctx
, 3, 0);
7252 if (key
->vs_prolog
.as_ls
&&
7253 ctx
->screen
->has_ls_vgpr_init_bug
) {
7254 /* If there are no HS threads, SPI loads the LS VGPRs
7255 * starting at VGPR 0. Shift them back to where they
7258 LLVMValueRef has_hs_threads
=
7259 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
7260 si_unpack_param(ctx
, 3, 8, 8),
7263 for (i
= 4; i
> 0; --i
) {
7264 input_vgprs
[i
+ 1] =
7265 LLVMBuildSelect(ctx
->ac
.builder
, has_hs_threads
,
7267 input_vgprs
[i
- 1], "");
7272 ctx
->abi
.vertex_id
= input_vgprs
[first_vs_vgpr
];
7273 ctx
->abi
.instance_id
= input_vgprs
[first_vs_vgpr
+ (key
->vs_prolog
.as_ls
? 2 : 1)];
7275 /* Copy inputs to outputs. This should be no-op, as the registers match,
7276 * but it will prevent the compiler from overwriting them unintentionally.
7278 ret
= ctx
->return_value
;
7279 for (i
= 0; i
< key
->vs_prolog
.num_input_sgprs
; i
++) {
7280 LLVMValueRef p
= LLVMGetParam(func
, i
);
7281 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7283 for (i
= 0; i
< num_input_vgprs
; i
++) {
7284 LLVMValueRef p
= input_vgprs
[i
];
7285 p
= ac_to_float(&ctx
->ac
, p
);
7286 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
,
7287 key
->vs_prolog
.num_input_sgprs
+ i
, "");
7290 /* Compute vertex load indices from instance divisors. */
7291 LLVMValueRef instance_divisor_constbuf
= NULL
;
7293 if (key
->vs_prolog
.states
.instance_divisor_is_fetched
) {
7294 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7295 LLVMValueRef buf_index
=
7296 LLVMConstInt(ctx
->i32
, SI_VS_CONST_INSTANCE_DIVISORS
, 0);
7297 instance_divisor_constbuf
=
7298 ac_build_load_to_sgpr(&ctx
->ac
, list
, buf_index
);
7301 for (i
= 0; i
<= key
->vs_prolog
.last_input
; i
++) {
7302 bool divisor_is_one
=
7303 key
->vs_prolog
.states
.instance_divisor_is_one
& (1u << i
);
7304 bool divisor_is_fetched
=
7305 key
->vs_prolog
.states
.instance_divisor_is_fetched
& (1u << i
);
7308 if (divisor_is_one
|| divisor_is_fetched
) {
7309 LLVMValueRef divisor
= ctx
->i32_1
;
7311 if (divisor_is_fetched
) {
7312 divisor
= buffer_load_const(ctx
, instance_divisor_constbuf
,
7313 LLVMConstInt(ctx
->i32
, i
* 4, 0));
7314 divisor
= ac_to_integer(&ctx
->ac
, divisor
);
7317 /* InstanceID / Divisor + StartInstance */
7318 index
= get_instance_index_for_fetch(ctx
,
7320 SI_SGPR_START_INSTANCE
,
7323 /* VertexID + BaseVertex */
7324 index
= LLVMBuildAdd(ctx
->ac
.builder
,
7326 LLVMGetParam(func
, user_sgpr_base
+
7327 SI_SGPR_BASE_VERTEX
), "");
7330 index
= ac_to_float(&ctx
->ac
, index
);
7331 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, index
,
7332 fninfo
.num_params
+ i
, "");
7335 si_llvm_build_ret(ctx
, ret
);
7338 static bool si_get_vs_prolog(struct si_screen
*sscreen
,
7339 struct si_compiler
*compiler
,
7340 struct si_shader
*shader
,
7341 struct pipe_debug_callback
*debug
,
7342 struct si_shader
*main_part
,
7343 const struct si_vs_prolog_bits
*key
)
7345 struct si_shader_selector
*vs
= main_part
->selector
;
7347 if (!si_vs_needs_prolog(vs
, key
))
7350 /* Get the prolog. */
7351 union si_shader_part_key prolog_key
;
7352 si_get_vs_prolog_key(&vs
->info
, main_part
->info
.num_input_sgprs
,
7353 key
, shader
, &prolog_key
);
7356 si_get_shader_part(sscreen
, &sscreen
->vs_prologs
,
7357 PIPE_SHADER_VERTEX
, true, &prolog_key
, compiler
,
7358 debug
, si_build_vs_prolog_function
,
7359 "Vertex Shader Prolog");
7360 return shader
->prolog
!= NULL
;
7364 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7366 static bool si_shader_select_vs_parts(struct si_screen
*sscreen
,
7367 struct si_compiler
*compiler
,
7368 struct si_shader
*shader
,
7369 struct pipe_debug_callback
*debug
)
7371 return si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, shader
,
7372 &shader
->key
.part
.vs
.prolog
);
7376 * Compile the TCS epilog function. This writes tesselation factors to memory
7377 * based on the output primitive type of the tesselator (determined by TES).
7379 static void si_build_tcs_epilog_function(struct si_shader_context
*ctx
,
7380 union si_shader_part_key
*key
)
7382 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7383 struct si_function_info fninfo
;
7386 si_init_function_info(&fninfo
);
7388 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
7389 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7390 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7391 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7392 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
); /* wave info */
7393 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7394 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7395 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7396 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7397 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7398 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7399 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7400 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7401 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7402 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7403 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7404 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7405 if (!HAVE_32BIT_POINTERS
)
7406 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7407 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7408 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7409 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7411 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7412 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7413 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7414 add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7415 ctx
->param_tcs_offchip_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7416 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7417 ctx
->param_tcs_out_lds_layout
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7418 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7419 ctx
->param_tcs_offchip_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7420 ctx
->param_tcs_factor_offset
= add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7423 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7424 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* VGPR gap */
7425 unsigned tess_factors_idx
=
7426 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* patch index within the wave (REL_PATCH_ID) */
7427 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* invocation ID within the patch */
7428 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* LDS offset where tess factors should be loaded from */
7430 for (unsigned i
= 0; i
< 6; i
++)
7431 add_arg(&fninfo
, ARG_VGPR
, ctx
->i32
); /* tess factors */
7433 /* Create the function. */
7434 si_create_function(ctx
, "tcs_epilog", NULL
, 0, &fninfo
,
7435 ctx
->screen
->info
.chip_class
>= CIK
? 128 : 64);
7436 ac_declare_lds_as_pointer(&ctx
->ac
);
7437 func
= ctx
->main_fn
;
7439 LLVMValueRef invoc0_tess_factors
[6];
7440 for (unsigned i
= 0; i
< 6; i
++)
7441 invoc0_tess_factors
[i
] = LLVMGetParam(func
, tess_factors_idx
+ 3 + i
);
7443 si_write_tess_factors(bld_base
,
7444 LLVMGetParam(func
, tess_factors_idx
),
7445 LLVMGetParam(func
, tess_factors_idx
+ 1),
7446 LLVMGetParam(func
, tess_factors_idx
+ 2),
7447 invoc0_tess_factors
, invoc0_tess_factors
+ 4);
7449 LLVMBuildRetVoid(ctx
->ac
.builder
);
7453 * Select and compile (or reuse) TCS parts (epilog).
7455 static bool si_shader_select_tcs_parts(struct si_screen
*sscreen
,
7456 struct si_compiler
*compiler
,
7457 struct si_shader
*shader
,
7458 struct pipe_debug_callback
*debug
)
7460 if (sscreen
->info
.chip_class
>= GFX9
) {
7461 struct si_shader
*ls_main_part
=
7462 shader
->key
.part
.tcs
.ls
->main_shader_part_ls
;
7464 if (!si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, ls_main_part
,
7465 &shader
->key
.part
.tcs
.ls_prolog
))
7468 shader
->previous_stage
= ls_main_part
;
7471 /* Get the epilog. */
7472 union si_shader_part_key epilog_key
;
7473 memset(&epilog_key
, 0, sizeof(epilog_key
));
7474 epilog_key
.tcs_epilog
.states
= shader
->key
.part
.tcs
.epilog
;
7476 shader
->epilog
= si_get_shader_part(sscreen
, &sscreen
->tcs_epilogs
,
7477 PIPE_SHADER_TESS_CTRL
, false,
7478 &epilog_key
, compiler
, debug
,
7479 si_build_tcs_epilog_function
,
7480 "Tessellation Control Shader Epilog");
7481 return shader
->epilog
!= NULL
;
7485 * Select and compile (or reuse) GS parts (prolog).
7487 static bool si_shader_select_gs_parts(struct si_screen
*sscreen
,
7488 struct si_compiler
*compiler
,
7489 struct si_shader
*shader
,
7490 struct pipe_debug_callback
*debug
)
7492 if (sscreen
->info
.chip_class
>= GFX9
) {
7493 struct si_shader
*es_main_part
=
7494 shader
->key
.part
.gs
.es
->main_shader_part_es
;
7496 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_VERTEX
&&
7497 !si_get_vs_prolog(sscreen
, compiler
, shader
, debug
, es_main_part
,
7498 &shader
->key
.part
.gs
.vs_prolog
))
7501 shader
->previous_stage
= es_main_part
;
7504 if (!shader
->key
.part
.gs
.prolog
.tri_strip_adj_fix
)
7507 union si_shader_part_key prolog_key
;
7508 memset(&prolog_key
, 0, sizeof(prolog_key
));
7509 prolog_key
.gs_prolog
.states
= shader
->key
.part
.gs
.prolog
;
7511 shader
->prolog2
= si_get_shader_part(sscreen
, &sscreen
->gs_prologs
,
7512 PIPE_SHADER_GEOMETRY
, true,
7513 &prolog_key
, compiler
, debug
,
7514 si_build_gs_prolog_function
,
7515 "Geometry Shader Prolog");
7516 return shader
->prolog2
!= NULL
;
7520 * Build the pixel shader prolog function. This handles:
7521 * - two-side color selection and interpolation
7522 * - overriding interpolation parameters for the API PS
7523 * - polygon stippling
7525 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7526 * overriden by other states. (e.g. per-sample interpolation)
7527 * Interpolated colors are stored after the preloaded VGPRs.
7529 static void si_build_ps_prolog_function(struct si_shader_context
*ctx
,
7530 union si_shader_part_key
*key
)
7532 struct si_function_info fninfo
;
7533 LLVMValueRef ret
, func
;
7534 int num_returns
, i
, num_color_channels
;
7536 assert(si_need_ps_prolog(key
));
7538 si_init_function_info(&fninfo
);
7540 /* Declare inputs. */
7541 for (i
= 0; i
< key
->ps_prolog
.num_input_sgprs
; i
++)
7542 add_arg(&fninfo
, ARG_SGPR
, ctx
->i32
);
7544 for (i
= 0; i
< key
->ps_prolog
.num_input_vgprs
; i
++)
7545 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7547 /* Declare outputs (same as inputs + add colors if needed) */
7548 num_returns
= fninfo
.num_params
;
7549 num_color_channels
= util_bitcount(key
->ps_prolog
.colors_read
);
7550 for (i
= 0; i
< num_color_channels
; i
++)
7551 fninfo
.types
[num_returns
++] = ctx
->f32
;
7553 /* Create the function. */
7554 si_create_function(ctx
, "ps_prolog", fninfo
.types
, num_returns
,
7556 func
= ctx
->main_fn
;
7558 /* Copy inputs to outputs. This should be no-op, as the registers match,
7559 * but it will prevent the compiler from overwriting them unintentionally.
7561 ret
= ctx
->return_value
;
7562 for (i
= 0; i
< fninfo
.num_params
; i
++) {
7563 LLVMValueRef p
= LLVMGetParam(func
, i
);
7564 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, p
, i
, "");
7567 /* Polygon stippling. */
7568 if (key
->ps_prolog
.states
.poly_stipple
) {
7569 /* POS_FIXED_PT is always last. */
7570 unsigned pos
= key
->ps_prolog
.num_input_sgprs
+
7571 key
->ps_prolog
.num_input_vgprs
- 1;
7572 LLVMValueRef list
= si_prolog_get_rw_buffers(ctx
);
7574 si_llvm_emit_polygon_stipple(ctx
, list
, pos
);
7577 if (key
->ps_prolog
.states
.bc_optimize_for_persp
||
7578 key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7579 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7580 LLVMValueRef center
[2], centroid
[2], tmp
, bc_optimize
;
7582 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7583 * The hw doesn't compute CENTROID if the whole wave only
7584 * contains fully-covered quads.
7586 * PRIM_MASK is after user SGPRs.
7588 bc_optimize
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7589 bc_optimize
= LLVMBuildLShr(ctx
->ac
.builder
, bc_optimize
,
7590 LLVMConstInt(ctx
->i32
, 31, 0), "");
7591 bc_optimize
= LLVMBuildTrunc(ctx
->ac
.builder
, bc_optimize
,
7594 if (key
->ps_prolog
.states
.bc_optimize_for_persp
) {
7595 /* Read PERSP_CENTER. */
7596 for (i
= 0; i
< 2; i
++)
7597 center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7598 /* Read PERSP_CENTROID. */
7599 for (i
= 0; i
< 2; i
++)
7600 centroid
[i
] = LLVMGetParam(func
, base
+ 4 + i
);
7601 /* Select PERSP_CENTROID. */
7602 for (i
= 0; i
< 2; i
++) {
7603 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7604 center
[i
], centroid
[i
], "");
7605 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7606 tmp
, base
+ 4 + i
, "");
7609 if (key
->ps_prolog
.states
.bc_optimize_for_linear
) {
7610 /* Read LINEAR_CENTER. */
7611 for (i
= 0; i
< 2; i
++)
7612 center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7613 /* Read LINEAR_CENTROID. */
7614 for (i
= 0; i
< 2; i
++)
7615 centroid
[i
] = LLVMGetParam(func
, base
+ 10 + i
);
7616 /* Select LINEAR_CENTROID. */
7617 for (i
= 0; i
< 2; i
++) {
7618 tmp
= LLVMBuildSelect(ctx
->ac
.builder
, bc_optimize
,
7619 center
[i
], centroid
[i
], "");
7620 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7621 tmp
, base
+ 10 + i
, "");
7626 /* Force per-sample interpolation. */
7627 if (key
->ps_prolog
.states
.force_persp_sample_interp
) {
7628 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7629 LLVMValueRef persp_sample
[2];
7631 /* Read PERSP_SAMPLE. */
7632 for (i
= 0; i
< 2; i
++)
7633 persp_sample
[i
] = LLVMGetParam(func
, base
+ i
);
7634 /* Overwrite PERSP_CENTER. */
7635 for (i
= 0; i
< 2; i
++)
7636 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7637 persp_sample
[i
], base
+ 2 + i
, "");
7638 /* Overwrite PERSP_CENTROID. */
7639 for (i
= 0; i
< 2; i
++)
7640 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7641 persp_sample
[i
], base
+ 4 + i
, "");
7643 if (key
->ps_prolog
.states
.force_linear_sample_interp
) {
7644 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7645 LLVMValueRef linear_sample
[2];
7647 /* Read LINEAR_SAMPLE. */
7648 for (i
= 0; i
< 2; i
++)
7649 linear_sample
[i
] = LLVMGetParam(func
, base
+ 6 + i
);
7650 /* Overwrite LINEAR_CENTER. */
7651 for (i
= 0; i
< 2; i
++)
7652 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7653 linear_sample
[i
], base
+ 8 + i
, "");
7654 /* Overwrite LINEAR_CENTROID. */
7655 for (i
= 0; i
< 2; i
++)
7656 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7657 linear_sample
[i
], base
+ 10 + i
, "");
7660 /* Force center interpolation. */
7661 if (key
->ps_prolog
.states
.force_persp_center_interp
) {
7662 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7663 LLVMValueRef persp_center
[2];
7665 /* Read PERSP_CENTER. */
7666 for (i
= 0; i
< 2; i
++)
7667 persp_center
[i
] = LLVMGetParam(func
, base
+ 2 + i
);
7668 /* Overwrite PERSP_SAMPLE. */
7669 for (i
= 0; i
< 2; i
++)
7670 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7671 persp_center
[i
], base
+ i
, "");
7672 /* Overwrite PERSP_CENTROID. */
7673 for (i
= 0; i
< 2; i
++)
7674 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7675 persp_center
[i
], base
+ 4 + i
, "");
7677 if (key
->ps_prolog
.states
.force_linear_center_interp
) {
7678 unsigned i
, base
= key
->ps_prolog
.num_input_sgprs
;
7679 LLVMValueRef linear_center
[2];
7681 /* Read LINEAR_CENTER. */
7682 for (i
= 0; i
< 2; i
++)
7683 linear_center
[i
] = LLVMGetParam(func
, base
+ 8 + i
);
7684 /* Overwrite LINEAR_SAMPLE. */
7685 for (i
= 0; i
< 2; i
++)
7686 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7687 linear_center
[i
], base
+ 6 + i
, "");
7688 /* Overwrite LINEAR_CENTROID. */
7689 for (i
= 0; i
< 2; i
++)
7690 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
,
7691 linear_center
[i
], base
+ 10 + i
, "");
7694 /* Interpolate colors. */
7695 unsigned color_out_idx
= 0;
7696 for (i
= 0; i
< 2; i
++) {
7697 unsigned writemask
= (key
->ps_prolog
.colors_read
>> (i
* 4)) & 0xf;
7698 unsigned face_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7699 key
->ps_prolog
.face_vgpr_index
;
7700 LLVMValueRef interp
[2], color
[4];
7701 LLVMValueRef interp_ij
= NULL
, prim_mask
= NULL
, face
= NULL
;
7706 /* If the interpolation qualifier is not CONSTANT (-1). */
7707 if (key
->ps_prolog
.color_interp_vgpr_index
[i
] != -1) {
7708 unsigned interp_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7709 key
->ps_prolog
.color_interp_vgpr_index
[i
];
7711 /* Get the (i,j) updated by bc_optimize handling. */
7712 interp
[0] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7714 interp
[1] = LLVMBuildExtractValue(ctx
->ac
.builder
, ret
,
7715 interp_vgpr
+ 1, "");
7716 interp_ij
= ac_build_gather_values(&ctx
->ac
, interp
, 2);
7719 /* Use the absolute location of the input. */
7720 prim_mask
= LLVMGetParam(func
, SI_PS_NUM_USER_SGPR
);
7722 if (key
->ps_prolog
.states
.color_two_side
) {
7723 face
= LLVMGetParam(func
, face_vgpr
);
7724 face
= ac_to_integer(&ctx
->ac
, face
);
7727 interp_fs_input(ctx
,
7728 key
->ps_prolog
.color_attr_index
[i
],
7729 TGSI_SEMANTIC_COLOR
, i
,
7730 key
->ps_prolog
.num_interp_inputs
,
7731 key
->ps_prolog
.colors_read
, interp_ij
,
7732 prim_mask
, face
, color
);
7735 unsigned chan
= u_bit_scan(&writemask
);
7736 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, color
[chan
],
7737 fninfo
.num_params
+ color_out_idx
++, "");
7741 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7744 * "When per-sample shading is active due to the use of a fragment
7745 * input qualified by sample or due to the use of the gl_SampleID
7746 * or gl_SamplePosition variables, only the bit for the current
7747 * sample is set in gl_SampleMaskIn. When state specifies multiple
7748 * fragment shader invocations for a given fragment, the sample
7749 * mask for any single fragment shader invocation may specify a
7750 * subset of the covered samples for the fragment. In this case,
7751 * the bit corresponding to each covered sample will be set in
7752 * exactly one fragment shader invocation."
7754 * The samplemask loaded by hardware is always the coverage of the
7755 * entire pixel/fragment, so mask bits out based on the sample ID.
7757 if (key
->ps_prolog
.states
.samplemask_log_ps_iter
) {
7758 /* The bit pattern matches that used by fixed function fragment
7760 static const uint16_t ps_iter_masks
[] = {
7761 0xffff, /* not used */
7767 assert(key
->ps_prolog
.states
.samplemask_log_ps_iter
< ARRAY_SIZE(ps_iter_masks
));
7769 uint32_t ps_iter_mask
= ps_iter_masks
[key
->ps_prolog
.states
.samplemask_log_ps_iter
];
7770 unsigned ancillary_vgpr
= key
->ps_prolog
.num_input_sgprs
+
7771 key
->ps_prolog
.ancillary_vgpr_index
;
7772 LLVMValueRef sampleid
= si_unpack_param(ctx
, ancillary_vgpr
, 8, 4);
7773 LLVMValueRef samplemask
= LLVMGetParam(func
, ancillary_vgpr
+ 1);
7775 samplemask
= ac_to_integer(&ctx
->ac
, samplemask
);
7776 samplemask
= LLVMBuildAnd(
7779 LLVMBuildShl(ctx
->ac
.builder
,
7780 LLVMConstInt(ctx
->i32
, ps_iter_mask
, false),
7783 samplemask
= ac_to_float(&ctx
->ac
, samplemask
);
7785 ret
= LLVMBuildInsertValue(ctx
->ac
.builder
, ret
, samplemask
,
7786 ancillary_vgpr
+ 1, "");
7789 /* Tell LLVM to insert WQM instruction sequence when needed. */
7790 if (key
->ps_prolog
.wqm
) {
7791 LLVMAddTargetDependentFunctionAttr(func
,
7792 "amdgpu-ps-wqm-outputs", "");
7795 si_llvm_build_ret(ctx
, ret
);
7799 * Build the pixel shader epilog function. This handles everything that must be
7800 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7802 static void si_build_ps_epilog_function(struct si_shader_context
*ctx
,
7803 union si_shader_part_key
*key
)
7805 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
7806 struct si_function_info fninfo
;
7807 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
7809 struct si_ps_exports exp
= {};
7811 si_init_function_info(&fninfo
);
7813 /* Declare input SGPRs. */
7814 ctx
->param_rw_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7815 ctx
->param_bindless_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7816 ctx
->param_const_and_shader_buffers
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7817 ctx
->param_samplers_and_images
= add_arg(&fninfo
, ARG_SGPR
, ctx
->ac
.intptr
);
7818 add_arg_checked(&fninfo
, ARG_SGPR
, ctx
->f32
, SI_PARAM_ALPHA_REF
);
7820 /* Declare input VGPRs. */
7821 unsigned required_num_params
=
7822 fninfo
.num_sgpr_params
+
7823 util_bitcount(key
->ps_epilog
.colors_written
) * 4 +
7824 key
->ps_epilog
.writes_z
+
7825 key
->ps_epilog
.writes_stencil
+
7826 key
->ps_epilog
.writes_samplemask
;
7828 required_num_params
= MAX2(required_num_params
,
7829 fninfo
.num_sgpr_params
+ PS_EPILOG_SAMPLEMASK_MIN_LOC
+ 1);
7831 while (fninfo
.num_params
< required_num_params
)
7832 add_arg(&fninfo
, ARG_VGPR
, ctx
->f32
);
7834 /* Create the function. */
7835 si_create_function(ctx
, "ps_epilog", NULL
, 0, &fninfo
, 0);
7836 /* Disable elimination of unused inputs. */
7837 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
,
7838 "InitialPSInputAddr", 0xffffff);
7840 /* Process colors. */
7841 unsigned vgpr
= fninfo
.num_sgpr_params
;
7842 unsigned colors_written
= key
->ps_epilog
.colors_written
;
7843 int last_color_export
= -1;
7845 /* Find the last color export. */
7846 if (!key
->ps_epilog
.writes_z
&&
7847 !key
->ps_epilog
.writes_stencil
&&
7848 !key
->ps_epilog
.writes_samplemask
) {
7849 unsigned spi_format
= key
->ps_epilog
.states
.spi_shader_col_format
;
7851 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7852 if (colors_written
== 0x1 && key
->ps_epilog
.states
.last_cbuf
> 0) {
7853 /* Just set this if any of the colorbuffers are enabled. */
7855 ((1ull << (4 * (key
->ps_epilog
.states
.last_cbuf
+ 1))) - 1))
7856 last_color_export
= 0;
7858 for (i
= 0; i
< 8; i
++)
7859 if (colors_written
& (1 << i
) &&
7860 (spi_format
>> (i
* 4)) & 0xf)
7861 last_color_export
= i
;
7865 while (colors_written
) {
7866 LLVMValueRef color
[4];
7867 int mrt
= u_bit_scan(&colors_written
);
7869 for (i
= 0; i
< 4; i
++)
7870 color
[i
] = LLVMGetParam(ctx
->main_fn
, vgpr
++);
7872 si_export_mrt_color(bld_base
, color
, mrt
,
7873 fninfo
.num_params
- 1,
7874 mrt
== last_color_export
, &exp
);
7877 /* Process depth, stencil, samplemask. */
7878 if (key
->ps_epilog
.writes_z
)
7879 depth
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7880 if (key
->ps_epilog
.writes_stencil
)
7881 stencil
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7882 if (key
->ps_epilog
.writes_samplemask
)
7883 samplemask
= LLVMGetParam(ctx
->main_fn
, vgpr
++);
7885 if (depth
|| stencil
|| samplemask
)
7886 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
, &exp
);
7887 else if (last_color_export
== -1)
7888 ac_build_export_null(&ctx
->ac
);
7891 si_emit_ps_exports(ctx
, &exp
);
7894 LLVMBuildRetVoid(ctx
->ac
.builder
);
7898 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7900 static bool si_shader_select_ps_parts(struct si_screen
*sscreen
,
7901 struct si_compiler
*compiler
,
7902 struct si_shader
*shader
,
7903 struct pipe_debug_callback
*debug
)
7905 union si_shader_part_key prolog_key
;
7906 union si_shader_part_key epilog_key
;
7908 /* Get the prolog. */
7909 si_get_ps_prolog_key(shader
, &prolog_key
, true);
7911 /* The prolog is a no-op if these aren't set. */
7912 if (si_need_ps_prolog(&prolog_key
)) {
7914 si_get_shader_part(sscreen
, &sscreen
->ps_prologs
,
7915 PIPE_SHADER_FRAGMENT
, true,
7916 &prolog_key
, compiler
, debug
,
7917 si_build_ps_prolog_function
,
7918 "Fragment Shader Prolog");
7919 if (!shader
->prolog
)
7923 /* Get the epilog. */
7924 si_get_ps_epilog_key(shader
, &epilog_key
);
7927 si_get_shader_part(sscreen
, &sscreen
->ps_epilogs
,
7928 PIPE_SHADER_FRAGMENT
, false,
7929 &epilog_key
, compiler
, debug
,
7930 si_build_ps_epilog_function
,
7931 "Fragment Shader Epilog");
7932 if (!shader
->epilog
)
7935 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7936 if (shader
->key
.part
.ps
.prolog
.poly_stipple
) {
7937 shader
->config
.spi_ps_input_ena
|= S_0286CC_POS_FIXED_PT_ENA(1);
7938 assert(G_0286CC_POS_FIXED_PT_ENA(shader
->config
.spi_ps_input_addr
));
7941 /* Set up the enable bits for per-sample shading if needed. */
7942 if (shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
&&
7943 (G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7944 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7945 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTER_ENA
;
7946 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7947 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_SAMPLE_ENA(1);
7949 if (shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
&&
7950 (G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_ena
) ||
7951 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7952 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTER_ENA
;
7953 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7954 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_SAMPLE_ENA(1);
7956 if (shader
->key
.part
.ps
.prolog
.force_persp_center_interp
&&
7957 (G_0286CC_PERSP_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7958 G_0286CC_PERSP_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7959 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_SAMPLE_ENA
;
7960 shader
->config
.spi_ps_input_ena
&= C_0286CC_PERSP_CENTROID_ENA
;
7961 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7963 if (shader
->key
.part
.ps
.prolog
.force_linear_center_interp
&&
7964 (G_0286CC_LINEAR_SAMPLE_ENA(shader
->config
.spi_ps_input_ena
) ||
7965 G_0286CC_LINEAR_CENTROID_ENA(shader
->config
.spi_ps_input_ena
))) {
7966 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_SAMPLE_ENA
;
7967 shader
->config
.spi_ps_input_ena
&= C_0286CC_LINEAR_CENTROID_ENA
;
7968 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7971 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7972 if (G_0286CC_POS_W_FLOAT_ENA(shader
->config
.spi_ps_input_ena
) &&
7973 !(shader
->config
.spi_ps_input_ena
& 0xf)) {
7974 shader
->config
.spi_ps_input_ena
|= S_0286CC_PERSP_CENTER_ENA(1);
7975 assert(G_0286CC_PERSP_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7978 /* At least one pair of interpolation weights must be enabled. */
7979 if (!(shader
->config
.spi_ps_input_ena
& 0x7f)) {
7980 shader
->config
.spi_ps_input_ena
|= S_0286CC_LINEAR_CENTER_ENA(1);
7981 assert(G_0286CC_LINEAR_CENTER_ENA(shader
->config
.spi_ps_input_addr
));
7984 /* Samplemask fixup requires the sample ID. */
7985 if (shader
->key
.part
.ps
.prolog
.samplemask_log_ps_iter
) {
7986 shader
->config
.spi_ps_input_ena
|= S_0286CC_ANCILLARY_ENA(1);
7987 assert(G_0286CC_ANCILLARY_ENA(shader
->config
.spi_ps_input_addr
));
7990 /* The sample mask input is always enabled, because the API shader always
7991 * passes it through to the epilog. Disable it here if it's unused.
7993 if (!shader
->key
.part
.ps
.epilog
.poly_line_smoothing
&&
7994 !shader
->selector
->info
.reads_samplemask
)
7995 shader
->config
.spi_ps_input_ena
&= C_0286CC_SAMPLE_COVERAGE_ENA
;
8000 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
8003 /* If tessellation is all offchip and on-chip GS isn't used, this
8004 * workaround is not needed.
8008 /* SPI barrier management bug:
8009 * Make sure we have at least 4k of LDS in use to avoid the bug.
8010 * It applies to workgroup sizes of more than one wavefront.
8012 if (sscreen
->info
.family
== CHIP_BONAIRE
||
8013 sscreen
->info
.family
== CHIP_KABINI
||
8014 sscreen
->info
.family
== CHIP_MULLINS
)
8015 *lds_size
= MAX2(*lds_size
, 8);
8018 static void si_fix_resource_usage(struct si_screen
*sscreen
,
8019 struct si_shader
*shader
)
8021 unsigned min_sgprs
= shader
->info
.num_input_sgprs
+ 2; /* VCC */
8023 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
, min_sgprs
);
8025 if (shader
->selector
->type
== PIPE_SHADER_COMPUTE
&&
8026 si_get_max_workgroup_size(shader
) > 64) {
8027 si_multiwave_lds_size_workaround(sscreen
,
8028 &shader
->config
.lds_size
);
8032 int si_shader_create(struct si_screen
*sscreen
, struct si_compiler
*compiler
,
8033 struct si_shader
*shader
,
8034 struct pipe_debug_callback
*debug
)
8036 struct si_shader_selector
*sel
= shader
->selector
;
8037 struct si_shader
*mainp
= *si_get_main_shader_part(sel
, &shader
->key
);
8040 /* LS, ES, VS are compiled on demand if the main part hasn't been
8041 * compiled for that stage.
8043 * Vertex shaders are compiled on demand when a vertex fetch
8044 * workaround must be applied.
8046 if (shader
->is_monolithic
) {
8047 /* Monolithic shader (compiled as a whole, has many variants,
8048 * may take a long time to compile).
8050 r
= si_compile_tgsi_shader(sscreen
, compiler
, shader
, debug
);
8054 /* The shader consists of several parts:
8056 * - the middle part is the user shader, it has 1 variant only
8057 * and it was compiled during the creation of the shader
8059 * - the prolog part is inserted at the beginning
8060 * - the epilog part is inserted at the end
8062 * The prolog and epilog have many (but simple) variants.
8064 * Starting with gfx9, geometry and tessellation control
8065 * shaders also contain the prolog and user shader parts of
8066 * the previous shader stage.
8072 /* Copy the compiled TGSI shader data over. */
8073 shader
->is_binary_shared
= true;
8074 shader
->binary
= mainp
->binary
;
8075 shader
->config
= mainp
->config
;
8076 shader
->info
.num_input_sgprs
= mainp
->info
.num_input_sgprs
;
8077 shader
->info
.num_input_vgprs
= mainp
->info
.num_input_vgprs
;
8078 shader
->info
.face_vgpr_index
= mainp
->info
.face_vgpr_index
;
8079 shader
->info
.ancillary_vgpr_index
= mainp
->info
.ancillary_vgpr_index
;
8080 memcpy(shader
->info
.vs_output_param_offset
,
8081 mainp
->info
.vs_output_param_offset
,
8082 sizeof(mainp
->info
.vs_output_param_offset
));
8083 shader
->info
.uses_instanceid
= mainp
->info
.uses_instanceid
;
8084 shader
->info
.nr_pos_exports
= mainp
->info
.nr_pos_exports
;
8085 shader
->info
.nr_param_exports
= mainp
->info
.nr_param_exports
;
8087 /* Select prologs and/or epilogs. */
8088 switch (sel
->type
) {
8089 case PIPE_SHADER_VERTEX
:
8090 if (!si_shader_select_vs_parts(sscreen
, compiler
, shader
, debug
))
8093 case PIPE_SHADER_TESS_CTRL
:
8094 if (!si_shader_select_tcs_parts(sscreen
, compiler
, shader
, debug
))
8097 case PIPE_SHADER_TESS_EVAL
:
8099 case PIPE_SHADER_GEOMETRY
:
8100 if (!si_shader_select_gs_parts(sscreen
, compiler
, shader
, debug
))
8103 case PIPE_SHADER_FRAGMENT
:
8104 if (!si_shader_select_ps_parts(sscreen
, compiler
, shader
, debug
))
8107 /* Make sure we have at least as many VGPRs as there
8108 * are allocated inputs.
8110 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8111 shader
->info
.num_input_vgprs
);
8115 /* Update SGPR and VGPR counts. */
8116 if (shader
->prolog
) {
8117 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8118 shader
->prolog
->config
.num_sgprs
);
8119 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8120 shader
->prolog
->config
.num_vgprs
);
8122 if (shader
->previous_stage
) {
8123 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8124 shader
->previous_stage
->config
.num_sgprs
);
8125 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8126 shader
->previous_stage
->config
.num_vgprs
);
8127 shader
->config
.spilled_sgprs
=
8128 MAX2(shader
->config
.spilled_sgprs
,
8129 shader
->previous_stage
->config
.spilled_sgprs
);
8130 shader
->config
.spilled_vgprs
=
8131 MAX2(shader
->config
.spilled_vgprs
,
8132 shader
->previous_stage
->config
.spilled_vgprs
);
8133 shader
->config
.private_mem_vgprs
=
8134 MAX2(shader
->config
.private_mem_vgprs
,
8135 shader
->previous_stage
->config
.private_mem_vgprs
);
8136 shader
->config
.scratch_bytes_per_wave
=
8137 MAX2(shader
->config
.scratch_bytes_per_wave
,
8138 shader
->previous_stage
->config
.scratch_bytes_per_wave
);
8139 shader
->info
.uses_instanceid
|=
8140 shader
->previous_stage
->info
.uses_instanceid
;
8142 if (shader
->prolog2
) {
8143 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8144 shader
->prolog2
->config
.num_sgprs
);
8145 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8146 shader
->prolog2
->config
.num_vgprs
);
8148 if (shader
->epilog
) {
8149 shader
->config
.num_sgprs
= MAX2(shader
->config
.num_sgprs
,
8150 shader
->epilog
->config
.num_sgprs
);
8151 shader
->config
.num_vgprs
= MAX2(shader
->config
.num_vgprs
,
8152 shader
->epilog
->config
.num_vgprs
);
8154 si_calculate_max_simd_waves(shader
);
8157 si_fix_resource_usage(sscreen
, shader
);
8158 si_shader_dump(sscreen
, shader
, debug
, sel
->info
.processor
,
8162 r
= si_shader_binary_upload(sscreen
, shader
);
8164 fprintf(stderr
, "LLVM failed to upload shader\n");
8171 void si_shader_destroy(struct si_shader
*shader
)
8173 if (shader
->scratch_bo
)
8174 r600_resource_reference(&shader
->scratch_bo
, NULL
);
8176 r600_resource_reference(&shader
->bo
, NULL
);
8178 if (!shader
->is_binary_shared
)
8179 ac_shader_binary_clean(&shader
->binary
);
8181 free(shader
->shader_log
);