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radeonsi: Generalize counting of shader parameters
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned usage;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_pipe_shader *shader;
62 struct si_shader *gs_for_vs;
63 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config;
65 int param_streamout_write_index;
66 int param_streamout_offset[4];
67 int param_vertex_id;
68 int param_instance_id;
69 LLVMValueRef const_md;
70 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
71 #if HAVE_LLVM >= 0x0304
72 LLVMValueRef ddxy_lds;
73 #endif
74 LLVMValueRef *constants[NUM_CONST_BUFFERS];
75 LLVMValueRef *resources;
76 LLVMValueRef *samplers;
77 LLVMValueRef so_buffers[4];
78 LLVMValueRef gs_next_vertex;
79 };
80
81 static struct si_shader_context * si_shader_context(
82 struct lp_build_tgsi_context * bld_base)
83 {
84 return (struct si_shader_context *)bld_base;
85 }
86
87
88 #define PERSPECTIVE_BASE 0
89 #define LINEAR_BASE 9
90
91 #define SAMPLE_OFFSET 0
92 #define CENTER_OFFSET 2
93 #define CENTROID_OFSET 4
94
95 #define USE_SGPR_MAX_SUFFIX_LEN 5
96 #define CONST_ADDR_SPACE 2
97 #define LOCAL_ADDR_SPACE 3
98 #define USER_SGPR_ADDR_SPACE 8
99
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109
110 /**
111 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
112 *
113 * @param offset The offset parameter specifies the number of
114 * elements to offset, not the number of bytes or dwords. An element is the
115 * the type pointed to by the base_ptr parameter (e.g. int is the element of
116 * an int* pointer)
117 *
118 * When LLVM lowers the load instruction, it will convert the element offset
119 * into a dword offset automatically.
120 *
121 */
122 static LLVMValueRef build_indexed_load(
123 struct si_shader_context * si_shader_ctx,
124 LLVMValueRef base_ptr,
125 LLVMValueRef offset)
126 {
127 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
128
129 LLVMValueRef indices[2] = {
130 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
131 offset
132 };
133 LLVMValueRef computed_ptr = LLVMBuildGEP(
134 base->gallivm->builder, base_ptr, indices, 2, "");
135
136 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
137 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
138 return result;
139 }
140
141 static LLVMValueRef get_instance_index_for_fetch(
142 struct radeon_llvm_context * radeon_bld,
143 unsigned divisor)
144 {
145 struct si_shader_context *si_shader_ctx =
146 si_shader_context(&radeon_bld->soa.bld_base);
147 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
148
149 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
150 si_shader_ctx->param_instance_id);
151 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
152 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
153
154 if (divisor > 1)
155 result = LLVMBuildUDiv(gallivm->builder, result,
156 lp_build_const_int32(gallivm, divisor), "");
157
158 return result;
159 }
160
161 static int si_store_shader_io_attribs(struct si_shader *shader,
162 const struct tgsi_full_declaration *d)
163 {
164 int i = -1;
165
166 switch (d->Declaration.File) {
167 case TGSI_FILE_INPUT:
168 i = shader->ninput++;
169 assert(i < Elements(shader->input));
170 shader->input[i].name = d->Semantic.Name;
171 shader->input[i].sid = d->Semantic.Index;
172 shader->input[i].interpolate = d->Interp.Interpolate;
173 shader->input[i].centroid = d->Interp.Centroid;
174 return -1;
175
176 case TGSI_FILE_OUTPUT:
177 i = shader->noutput++;
178 assert(i < Elements(shader->output));
179 shader->output[i].name = d->Semantic.Name;
180 shader->output[i].sid = d->Semantic.Index;
181 shader->output[i].index = d->Range.First;
182 shader->output[i].usage = d->Declaration.UsageMask;
183 break;
184 }
185
186 return i;
187 }
188
189 static void declare_input_vs(
190 struct radeon_llvm_context *radeon_bld,
191 unsigned input_index,
192 const struct tgsi_full_declaration *decl)
193 {
194 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
195 struct gallivm_state *gallivm = base->gallivm;
196 struct si_shader_context *si_shader_ctx =
197 si_shader_context(&radeon_bld->soa.bld_base);
198 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
199
200 unsigned chan;
201
202 LLVMValueRef t_list_ptr;
203 LLVMValueRef t_offset;
204 LLVMValueRef t_list;
205 LLVMValueRef attribute_offset;
206 LLVMValueRef buffer_index;
207 LLVMValueRef args[3];
208 LLVMTypeRef vec4_type;
209 LLVMValueRef input;
210
211 /* Load the T list */
212 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
213
214 t_offset = lp_build_const_int32(gallivm, input_index);
215
216 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
217
218 /* Build the attribute offset */
219 attribute_offset = lp_build_const_int32(gallivm, 0);
220
221 if (divisor) {
222 /* Build index from instance ID, start instance and divisor */
223 si_shader_ctx->shader->shader.uses_instanceid = true;
224 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
225 } else {
226 /* Load the buffer index, which is always stored in VGPR0
227 * for Vertex Shaders */
228 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
229 si_shader_ctx->param_vertex_id);
230 }
231
232 vec4_type = LLVMVectorType(base->elem_type, 4);
233 args[0] = t_list;
234 args[1] = attribute_offset;
235 args[2] = buffer_index;
236 input = build_intrinsic(gallivm->builder,
237 "llvm.SI.vs.load.input", vec4_type, args, 3,
238 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
239
240 /* Break up the vec4 into individual components */
241 for (chan = 0; chan < 4; chan++) {
242 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
243 /* XXX: Use a helper function for this. There is one in
244 * tgsi_llvm.c. */
245 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
246 LLVMBuildExtractElement(gallivm->builder,
247 input, llvm_chan, "");
248 }
249 }
250
251 static void declare_input_gs(
252 struct radeon_llvm_context *radeon_bld,
253 unsigned input_index,
254 const struct tgsi_full_declaration *decl)
255 {
256 struct si_shader_context *si_shader_ctx =
257 si_shader_context(&radeon_bld->soa.bld_base);
258 struct si_shader *shader = &si_shader_ctx->shader->shader;
259
260 si_store_shader_io_attribs(shader, decl);
261 shader->input[input_index].param_offset = shader->nparam++;
262 }
263
264 static LLVMValueRef fetch_input_gs(
265 struct lp_build_tgsi_context *bld_base,
266 const struct tgsi_full_src_register *reg,
267 enum tgsi_opcode_type type,
268 unsigned swizzle)
269 {
270 struct lp_build_context *base = &bld_base->base;
271 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
272 struct si_shader *shader = &si_shader_ctx->shader->shader;
273 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
274 struct gallivm_state *gallivm = base->gallivm;
275 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
276 LLVMValueRef vtx_offset;
277 LLVMValueRef t_list_ptr;
278 LLVMValueRef t_list;
279 LLVMValueRef args[9];
280 unsigned vtx_offset_param;
281
282 if (!reg->Register.Dimension)
283 return NULL;
284
285 if (swizzle == ~0) {
286 LLVMValueRef values[TGSI_NUM_CHANNELS];
287 unsigned chan;
288 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
289 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
290 }
291 return lp_build_gather_values(bld_base->base.gallivm, values,
292 TGSI_NUM_CHANNELS);
293 }
294
295 /* Get the vertex offset parameter */
296 vtx_offset_param = reg->Dimension.Index;
297 if (vtx_offset_param < 2) {
298 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
299 } else {
300 assert(vtx_offset_param < 6);
301 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
302 }
303 vtx_offset = lp_build_mul_imm(uint,
304 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
305 vtx_offset_param),
306 4);
307
308 /* Load the ESGS ring resource descriptor */
309 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
310 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
311 lp_build_const_int32(gallivm,
312 NUM_PIPE_CONST_BUFFERS + 1));
313
314 args[0] = t_list;
315 args[1] = vtx_offset;
316 args[2] = lp_build_const_int32(gallivm,
317 ((shader->input[reg->Register.Index].param_offset * 4) +
318 swizzle) * 256);
319 args[3] = uint->zero;
320 args[4] = uint->one; /* OFFEN */
321 args[5] = uint->zero; /* IDXEN */
322 args[6] = uint->one; /* GLC */
323 args[7] = uint->zero; /* SLC */
324 args[8] = uint->zero; /* TFE */
325
326 return LLVMBuildBitCast(gallivm->builder,
327 build_intrinsic(gallivm->builder,
328 "llvm.SI.buffer.load.dword.i32.i32",
329 i32, args, 9,
330 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
331 tgsi2llvmtype(bld_base, type), "");
332 }
333
334 static void declare_input_fs(
335 struct radeon_llvm_context *radeon_bld,
336 unsigned input_index,
337 const struct tgsi_full_declaration *decl)
338 {
339 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
340 struct si_shader_context *si_shader_ctx =
341 si_shader_context(&radeon_bld->soa.bld_base);
342 struct si_shader *shader = &si_shader_ctx->shader->shader;
343 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
344 struct gallivm_state *gallivm = base->gallivm;
345 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
346 LLVMValueRef main_fn = radeon_bld->main_fn;
347
348 LLVMValueRef interp_param;
349 const char * intr_name;
350
351 /* This value is:
352 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
353 * quad begins a new primitive. Bit 0 always needs
354 * to be unset)
355 * [32:16] ParamOffset
356 *
357 */
358 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
359 LLVMValueRef attr_number;
360
361 unsigned chan;
362
363 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
364 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
365 unsigned soa_index =
366 radeon_llvm_reg_index_soa(input_index, chan);
367 radeon_bld->inputs[soa_index] =
368 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
369
370 if (chan == 3)
371 /* RCP for fragcoord.w */
372 radeon_bld->inputs[soa_index] =
373 LLVMBuildFDiv(gallivm->builder,
374 lp_build_const_float(gallivm, 1.0f),
375 radeon_bld->inputs[soa_index],
376 "");
377 }
378 return;
379 }
380
381 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
382 LLVMValueRef face, is_face_positive;
383
384 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
385
386 is_face_positive = LLVMBuildFCmp(gallivm->builder,
387 LLVMRealUGT, face,
388 lp_build_const_float(gallivm, 0.0f),
389 "");
390
391 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
392 LLVMBuildSelect(gallivm->builder,
393 is_face_positive,
394 lp_build_const_float(gallivm, 1.0f),
395 lp_build_const_float(gallivm, 0.0f),
396 "");
397 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
398 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
399 lp_build_const_float(gallivm, 0.0f);
400 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
401 lp_build_const_float(gallivm, 1.0f);
402
403 return;
404 }
405
406 shader->input[input_index].param_offset = shader->nparam++;
407 attr_number = lp_build_const_int32(gallivm,
408 shader->input[input_index].param_offset);
409
410 switch (decl->Interp.Interpolate) {
411 case TGSI_INTERPOLATE_COLOR:
412 if (si_shader_ctx->shader->key.ps.flatshade) {
413 interp_param = 0;
414 } else {
415 if (decl->Interp.Centroid)
416 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
417 else
418 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
419 }
420 break;
421 case TGSI_INTERPOLATE_CONSTANT:
422 interp_param = 0;
423 break;
424 case TGSI_INTERPOLATE_LINEAR:
425 if (decl->Interp.Centroid)
426 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
427 else
428 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
429 break;
430 case TGSI_INTERPOLATE_PERSPECTIVE:
431 if (decl->Interp.Centroid)
432 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
433 else
434 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
435 break;
436 default:
437 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
438 return;
439 }
440
441 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
442
443 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
444 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
445 si_shader_ctx->shader->key.ps.color_two_side) {
446 LLVMValueRef args[4];
447 LLVMValueRef face, is_face_positive;
448 LLVMValueRef back_attr_number =
449 lp_build_const_int32(gallivm,
450 shader->input[input_index].param_offset + 1);
451
452 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
453
454 is_face_positive = LLVMBuildFCmp(gallivm->builder,
455 LLVMRealUGT, face,
456 lp_build_const_float(gallivm, 0.0f),
457 "");
458
459 args[2] = params;
460 args[3] = interp_param;
461 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
462 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
463 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
464 LLVMValueRef front, back;
465
466 args[0] = llvm_chan;
467 args[1] = attr_number;
468 front = build_intrinsic(gallivm->builder, intr_name,
469 input_type, args, args[3] ? 4 : 3,
470 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
471
472 args[1] = back_attr_number;
473 back = build_intrinsic(gallivm->builder, intr_name,
474 input_type, args, args[3] ? 4 : 3,
475 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
476
477 radeon_bld->inputs[soa_index] =
478 LLVMBuildSelect(gallivm->builder,
479 is_face_positive,
480 front,
481 back,
482 "");
483 }
484
485 shader->nparam++;
486 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
487 LLVMValueRef args[4];
488
489 args[0] = uint->zero;
490 args[1] = attr_number;
491 args[2] = params;
492 args[3] = interp_param;
493 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
494 build_intrinsic(gallivm->builder, intr_name,
495 input_type, args, args[3] ? 4 : 3,
496 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
497 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
498 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
499 lp_build_const_float(gallivm, 0.0f);
500 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
501 lp_build_const_float(gallivm, 1.0f);
502 } else {
503 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
504 LLVMValueRef args[4];
505 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
506 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
507 args[0] = llvm_chan;
508 args[1] = attr_number;
509 args[2] = params;
510 args[3] = interp_param;
511 radeon_bld->inputs[soa_index] =
512 build_intrinsic(gallivm->builder, intr_name,
513 input_type, args, args[3] ? 4 : 3,
514 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
515 }
516 }
517 }
518
519 static void declare_system_value(
520 struct radeon_llvm_context * radeon_bld,
521 unsigned index,
522 const struct tgsi_full_declaration *decl)
523 {
524 struct si_shader_context *si_shader_ctx =
525 si_shader_context(&radeon_bld->soa.bld_base);
526 LLVMValueRef value = 0;
527
528 switch (decl->Semantic.Name) {
529 case TGSI_SEMANTIC_INSTANCEID:
530 value = LLVMGetParam(radeon_bld->main_fn,
531 si_shader_ctx->param_instance_id);
532 break;
533
534 case TGSI_SEMANTIC_VERTEXID:
535 value = LLVMGetParam(radeon_bld->main_fn,
536 si_shader_ctx->param_vertex_id);
537 break;
538
539 default:
540 assert(!"unknown system value");
541 return;
542 }
543
544 radeon_bld->system_values[index] = value;
545 }
546
547 static LLVMValueRef fetch_constant(
548 struct lp_build_tgsi_context * bld_base,
549 const struct tgsi_full_src_register *reg,
550 enum tgsi_opcode_type type,
551 unsigned swizzle)
552 {
553 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
554 struct lp_build_context * base = &bld_base->base;
555 const struct tgsi_ind_register *ireg = &reg->Indirect;
556 unsigned buf, idx;
557
558 LLVMValueRef args[2];
559 LLVMValueRef addr;
560 LLVMValueRef result;
561
562 if (swizzle == LP_CHAN_ALL) {
563 unsigned chan;
564 LLVMValueRef values[4];
565 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
566 values[chan] = fetch_constant(bld_base, reg, type, chan);
567
568 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
569 }
570
571 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
572 idx = reg->Register.Index * 4 + swizzle;
573
574 if (!reg->Register.Indirect)
575 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
576
577 args[0] = si_shader_ctx->const_resource[buf];
578 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
579 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
580 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
581 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
582 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
583
584 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
585 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
586
587 return bitcast(bld_base, type, result);
588 }
589
590 /* Initialize arguments for the shader export intrinsic */
591 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
592 LLVMValueRef *values,
593 unsigned target,
594 LLVMValueRef *args)
595 {
596 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
597 struct lp_build_context *uint =
598 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
599 struct lp_build_context *base = &bld_base->base;
600 unsigned compressed = 0;
601 unsigned chan;
602
603 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
604 int cbuf = target - V_008DFC_SQ_EXP_MRT;
605
606 if (cbuf >= 0 && cbuf < 8) {
607 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
608
609 if (compressed)
610 si_shader_ctx->shader->spi_shader_col_format |=
611 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
612 else
613 si_shader_ctx->shader->spi_shader_col_format |=
614 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
615
616 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
617 }
618 }
619
620 if (compressed) {
621 /* Pixel shader needs to pack output values before export */
622 for (chan = 0; chan < 2; chan++ ) {
623 args[0] = values[2 * chan];
624 args[1] = values[2 * chan + 1];
625 args[chan + 5] =
626 build_intrinsic(base->gallivm->builder,
627 "llvm.SI.packf16",
628 LLVMInt32TypeInContext(base->gallivm->context),
629 args, 2,
630 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
631 args[chan + 7] = args[chan + 5] =
632 LLVMBuildBitCast(base->gallivm->builder,
633 args[chan + 5],
634 LLVMFloatTypeInContext(base->gallivm->context),
635 "");
636 }
637
638 /* Set COMPR flag */
639 args[4] = uint->one;
640 } else {
641 for (chan = 0; chan < 4; chan++ )
642 /* +5 because the first output value will be
643 * the 6th argument to the intrinsic. */
644 args[chan + 5] = values[chan];
645
646 /* Clear COMPR flag */
647 args[4] = uint->zero;
648 }
649
650 /* XXX: This controls which components of the output
651 * registers actually get exported. (e.g bit 0 means export
652 * X component, bit 1 means export Y component, etc.) I'm
653 * hard coding this to 0xf for now. In the future, we might
654 * want to do something else. */
655 args[0] = lp_build_const_int32(base->gallivm, 0xf);
656
657 /* Specify whether the EXEC mask represents the valid mask */
658 args[1] = uint->zero;
659
660 /* Specify whether this is the last export */
661 args[2] = uint->zero;
662
663 /* Specify the target we are exporting */
664 args[3] = lp_build_const_int32(base->gallivm, target);
665
666 /* XXX: We probably need to keep track of the output
667 * values, so we know what we are passing to the next
668 * stage. */
669 }
670
671 /* Load from output pointers and initialize arguments for the shader export intrinsic */
672 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
673 LLVMValueRef *out_ptr,
674 unsigned target,
675 LLVMValueRef *args)
676 {
677 struct gallivm_state *gallivm = bld_base->base.gallivm;
678 LLVMValueRef values[4];
679 int i;
680
681 for (i = 0; i < 4; i++)
682 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
683
684 si_llvm_init_export_args(bld_base, values, target, args);
685 }
686
687 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
688 LLVMValueRef *out_ptr)
689 {
690 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
691 struct gallivm_state *gallivm = bld_base->base.gallivm;
692
693 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
694 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
695 SI_PARAM_ALPHA_REF);
696
697 LLVMValueRef alpha_pass =
698 lp_build_cmp(&bld_base->base,
699 si_shader_ctx->shader->key.ps.alpha_func,
700 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
701 alpha_ref);
702 LLVMValueRef arg =
703 lp_build_select(&bld_base->base,
704 alpha_pass,
705 lp_build_const_float(gallivm, 1.0f),
706 lp_build_const_float(gallivm, -1.0f));
707
708 build_intrinsic(gallivm->builder,
709 "llvm.AMDGPU.kill",
710 LLVMVoidTypeInContext(gallivm->context),
711 &arg, 1, 0);
712 } else {
713 build_intrinsic(gallivm->builder,
714 "llvm.AMDGPU.kilp",
715 LLVMVoidTypeInContext(gallivm->context),
716 NULL, 0, 0);
717 }
718 }
719
720 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
721 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
722 {
723 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
724 struct si_pipe_shader *shader = si_shader_ctx->shader;
725 struct lp_build_context *base = &bld_base->base;
726 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
727 unsigned reg_index;
728 unsigned chan;
729 unsigned const_chan;
730 LLVMValueRef base_elt;
731 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
732 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
733 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
734
735 for (reg_index = 0; reg_index < 2; reg_index ++) {
736 LLVMValueRef *args = pos[2 + reg_index];
737
738 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
739 continue;
740
741 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
742
743 args[5] =
744 args[6] =
745 args[7] =
746 args[8] = lp_build_const_float(base->gallivm, 0.0f);
747
748 /* Compute dot products of position and user clip plane vectors */
749 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
750 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
751 args[0] = const_resource;
752 args[1] = lp_build_const_int32(base->gallivm,
753 ((reg_index * 4 + chan) * 4 +
754 const_chan) * 4);
755 base_elt = build_intrinsic(base->gallivm->builder,
756 "llvm.SI.load.const",
757 base->elem_type,
758 args, 2,
759 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
760 args[5 + chan] =
761 lp_build_add(base, args[5 + chan],
762 lp_build_mul(base, base_elt,
763 out_elts[const_chan]));
764 }
765 }
766
767 args[0] = lp_build_const_int32(base->gallivm, 0xf);
768 args[1] = uint->zero;
769 args[2] = uint->zero;
770 args[3] = lp_build_const_int32(base->gallivm,
771 V_008DFC_SQ_EXP_POS + 2 + reg_index);
772 args[4] = uint->zero;
773 }
774 }
775
776 static void si_dump_streamout(struct pipe_stream_output_info *so)
777 {
778 unsigned i;
779
780 if (so->num_outputs)
781 fprintf(stderr, "STREAMOUT\n");
782
783 for (i = 0; i < so->num_outputs; i++) {
784 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
785 so->output[i].start_component;
786 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
787 i, so->output[i].output_buffer,
788 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
789 so->output[i].register_index,
790 mask & 1 ? "x" : "",
791 mask & 2 ? "y" : "",
792 mask & 4 ? "z" : "",
793 mask & 8 ? "w" : "");
794 }
795 }
796
797 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
798 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
799 * or v4i32 (num_channels=3,4). */
800 static void build_tbuffer_store(struct si_shader_context *shader,
801 LLVMValueRef rsrc,
802 LLVMValueRef vdata,
803 unsigned num_channels,
804 LLVMValueRef vaddr,
805 LLVMValueRef soffset,
806 unsigned inst_offset,
807 unsigned dfmt,
808 unsigned nfmt,
809 unsigned offen,
810 unsigned idxen,
811 unsigned glc,
812 unsigned slc,
813 unsigned tfe)
814 {
815 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
816 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
817 LLVMValueRef args[] = {
818 rsrc,
819 vdata,
820 LLVMConstInt(i32, num_channels, 0),
821 vaddr,
822 soffset,
823 LLVMConstInt(i32, inst_offset, 0),
824 LLVMConstInt(i32, dfmt, 0),
825 LLVMConstInt(i32, nfmt, 0),
826 LLVMConstInt(i32, offen, 0),
827 LLVMConstInt(i32, idxen, 0),
828 LLVMConstInt(i32, glc, 0),
829 LLVMConstInt(i32, slc, 0),
830 LLVMConstInt(i32, tfe, 0)
831 };
832
833 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
834 unsigned func = CLAMP(num_channels, 1, 3) - 1;
835 const char *types[] = {"i32", "v2i32", "v4i32"};
836 char name[256];
837 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
838
839 lp_build_intrinsic(gallivm->builder, name,
840 LLVMVoidTypeInContext(gallivm->context),
841 args, Elements(args));
842 }
843
844 static void build_streamout_store(struct si_shader_context *shader,
845 LLVMValueRef rsrc,
846 LLVMValueRef vdata,
847 unsigned num_channels,
848 LLVMValueRef vaddr,
849 LLVMValueRef soffset,
850 unsigned inst_offset)
851 {
852 static unsigned dfmt[] = {
853 V_008F0C_BUF_DATA_FORMAT_32,
854 V_008F0C_BUF_DATA_FORMAT_32_32,
855 V_008F0C_BUF_DATA_FORMAT_32_32_32,
856 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
857 };
858 assert(num_channels >= 1 && num_channels <= 4);
859
860 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
861 inst_offset, dfmt[num_channels-1],
862 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
863 }
864
865 /* On SI, the vertex shader is responsible for writing streamout data
866 * to buffers. */
867 static void si_llvm_emit_streamout(struct si_shader_context *shader)
868 {
869 struct pipe_stream_output_info *so = &shader->shader->selector->so;
870 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
871 LLVMBuilderRef builder = gallivm->builder;
872 int i, j;
873 struct lp_build_if_state if_ctx;
874
875 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
876
877 LLVMValueRef so_param =
878 LLVMGetParam(shader->radeon_bld.main_fn,
879 shader->param_streamout_config);
880
881 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
882 LLVMValueRef so_vtx_count =
883 LLVMBuildAnd(builder,
884 LLVMBuildLShr(builder, so_param,
885 LLVMConstInt(i32, 16, 0), ""),
886 LLVMConstInt(i32, 127, 0), "");
887
888 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
889 NULL, 0, LLVMReadNoneAttribute);
890
891 /* can_emit = tid < so_vtx_count; */
892 LLVMValueRef can_emit =
893 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
894
895 /* Emit the streamout code conditionally. This actually avoids
896 * out-of-bounds buffer access. The hw tells us via the SGPR
897 * (so_vtx_count) which threads are allowed to emit streamout data. */
898 lp_build_if(&if_ctx, gallivm, can_emit);
899 {
900 /* The buffer offset is computed as follows:
901 * ByteOffset = streamout_offset[buffer_id]*4 +
902 * (streamout_write_index + thread_id)*stride[buffer_id] +
903 * attrib_offset
904 */
905
906 LLVMValueRef so_write_index =
907 LLVMGetParam(shader->radeon_bld.main_fn,
908 shader->param_streamout_write_index);
909
910 /* Compute (streamout_write_index + thread_id). */
911 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
912
913 /* Compute the write offset for each enabled buffer. */
914 LLVMValueRef so_write_offset[4] = {};
915 for (i = 0; i < 4; i++) {
916 if (!so->stride[i])
917 continue;
918
919 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
920 shader->param_streamout_offset[i]);
921 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
922
923 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
924 LLVMConstInt(i32, so->stride[i]*4, 0), "");
925 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
926 }
927
928 LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS] = shader->radeon_bld.soa.outputs;
929
930 /* Write streamout data. */
931 for (i = 0; i < so->num_outputs; i++) {
932 unsigned buf_idx = so->output[i].output_buffer;
933 unsigned reg = so->output[i].register_index;
934 unsigned start = so->output[i].start_component;
935 unsigned num_comps = so->output[i].num_components;
936 LLVMValueRef out[4];
937
938 assert(num_comps && num_comps <= 4);
939 if (!num_comps || num_comps > 4)
940 continue;
941
942 /* Load the output as int. */
943 for (j = 0; j < num_comps; j++) {
944 out[j] = LLVMBuildLoad(builder, outputs[reg][start+j], "");
945 out[j] = LLVMBuildBitCast(builder, out[j], i32, "");
946 }
947
948 /* Pack the output. */
949 LLVMValueRef vdata = NULL;
950
951 switch (num_comps) {
952 case 1: /* as i32 */
953 vdata = out[0];
954 break;
955 case 2: /* as v2i32 */
956 case 3: /* as v4i32 (aligned to 4) */
957 case 4: /* as v4i32 */
958 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
959 for (j = 0; j < num_comps; j++) {
960 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
961 LLVMConstInt(i32, j, 0), "");
962 }
963 break;
964 }
965
966 build_streamout_store(shader, shader->so_buffers[buf_idx],
967 vdata, num_comps,
968 so_write_offset[buf_idx],
969 LLVMConstInt(i32, 0, 0),
970 so->output[i].dst_offset*4);
971 }
972 }
973 lp_build_endif(&if_ctx);
974 }
975
976
977 /* Generate export instructions for hardware VS shader stage */
978 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
979 struct si_shader_output_values *outputs,
980 unsigned noutput)
981 {
982 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
983 struct si_shader * shader = &si_shader_ctx->shader->shader;
984 struct lp_build_context * base = &bld_base->base;
985 struct lp_build_context * uint =
986 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
987 LLVMValueRef args[9];
988 LLVMValueRef pos_args[4][9] = { { 0 } };
989 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
990 unsigned semantic_name, semantic_index, semantic_usage;
991 unsigned target;
992 unsigned param_count = 0;
993 unsigned pos_idx;
994 int i;
995
996 if (si_shader_ctx->shader->selector->so.num_outputs) {
997 si_llvm_emit_streamout(si_shader_ctx);
998 }
999
1000 for (i = 0; i < noutput; i++) {
1001 semantic_name = outputs[i].name;
1002 semantic_index = outputs[i].index;
1003 semantic_usage = outputs[i].usage;
1004
1005 handle_semantic:
1006 /* Select the correct target */
1007 switch(semantic_name) {
1008 case TGSI_SEMANTIC_PSIZE:
1009 shader->vs_out_misc_write = true;
1010 shader->vs_out_point_size = true;
1011 psize_value = outputs[i].values[0];
1012 continue;
1013 case TGSI_SEMANTIC_EDGEFLAG:
1014 shader->vs_out_misc_write = true;
1015 shader->vs_out_edgeflag = true;
1016 edgeflag_value = outputs[i].values[0];
1017 continue;
1018 case TGSI_SEMANTIC_LAYER:
1019 shader->vs_out_misc_write = true;
1020 shader->vs_out_layer = true;
1021 layer_value = outputs[i].values[0];
1022 continue;
1023 case TGSI_SEMANTIC_POSITION:
1024 target = V_008DFC_SQ_EXP_POS;
1025 break;
1026 case TGSI_SEMANTIC_COLOR:
1027 case TGSI_SEMANTIC_BCOLOR:
1028 target = V_008DFC_SQ_EXP_PARAM + param_count;
1029 shader->output[i].param_offset = param_count;
1030 param_count++;
1031 break;
1032 case TGSI_SEMANTIC_CLIPDIST:
1033 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1034 (1 << semantic_index)))
1035 continue;
1036 shader->clip_dist_write |=
1037 semantic_usage << (semantic_index << 2);
1038 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1039 break;
1040 case TGSI_SEMANTIC_CLIPVERTEX:
1041 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1042 continue;
1043 case TGSI_SEMANTIC_FOG:
1044 case TGSI_SEMANTIC_GENERIC:
1045 target = V_008DFC_SQ_EXP_PARAM + param_count;
1046 shader->output[i].param_offset = param_count;
1047 param_count++;
1048 break;
1049 default:
1050 target = 0;
1051 fprintf(stderr,
1052 "Warning: SI unhandled vs output type:%d\n",
1053 semantic_name);
1054 }
1055
1056 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1057
1058 if (target >= V_008DFC_SQ_EXP_POS &&
1059 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1060 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1061 args, sizeof(args));
1062 } else {
1063 lp_build_intrinsic(base->gallivm->builder,
1064 "llvm.SI.export",
1065 LLVMVoidTypeInContext(base->gallivm->context),
1066 args, 9);
1067 }
1068
1069 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1070 semantic_name = TGSI_SEMANTIC_GENERIC;
1071 goto handle_semantic;
1072 }
1073 }
1074
1075 /* We need to add the position output manually if it's missing. */
1076 if (!pos_args[0][0]) {
1077 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1078 pos_args[0][1] = uint->zero; /* EXEC mask */
1079 pos_args[0][2] = uint->zero; /* last export? */
1080 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1081 pos_args[0][4] = uint->zero; /* COMPR flag */
1082 pos_args[0][5] = base->zero; /* X */
1083 pos_args[0][6] = base->zero; /* Y */
1084 pos_args[0][7] = base->zero; /* Z */
1085 pos_args[0][8] = base->one; /* W */
1086 }
1087
1088 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1089 if (shader->vs_out_misc_write) {
1090 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1091 shader->vs_out_point_size |
1092 (shader->vs_out_edgeflag << 1) |
1093 (shader->vs_out_layer << 2));
1094 pos_args[1][1] = uint->zero; /* EXEC mask */
1095 pos_args[1][2] = uint->zero; /* last export? */
1096 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1097 pos_args[1][4] = uint->zero; /* COMPR flag */
1098 pos_args[1][5] = base->zero; /* X */
1099 pos_args[1][6] = base->zero; /* Y */
1100 pos_args[1][7] = base->zero; /* Z */
1101 pos_args[1][8] = base->zero; /* W */
1102
1103 if (shader->vs_out_point_size)
1104 pos_args[1][5] = psize_value;
1105
1106 if (shader->vs_out_edgeflag) {
1107 /* The output is a float, but the hw expects an integer
1108 * with the first bit containing the edge flag. */
1109 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1110 edgeflag_value,
1111 bld_base->uint_bld.elem_type, "");
1112 edgeflag_value = lp_build_min(&bld_base->int_bld,
1113 edgeflag_value,
1114 bld_base->int_bld.one);
1115
1116 /* The LLVM intrinsic expects a float. */
1117 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1118 edgeflag_value,
1119 base->elem_type, "");
1120 }
1121
1122 if (shader->vs_out_layer)
1123 pos_args[1][7] = layer_value;
1124 }
1125
1126 for (i = 0; i < 4; i++)
1127 if (pos_args[i][0])
1128 shader->nr_pos_exports++;
1129
1130 pos_idx = 0;
1131 for (i = 0; i < 4; i++) {
1132 if (!pos_args[i][0])
1133 continue;
1134
1135 /* Specify the target we are exporting */
1136 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1137
1138 if (pos_idx == shader->nr_pos_exports)
1139 /* Specify that this is the last export */
1140 pos_args[i][2] = uint->one;
1141
1142 lp_build_intrinsic(base->gallivm->builder,
1143 "llvm.SI.export",
1144 LLVMVoidTypeInContext(base->gallivm->context),
1145 pos_args[i], 9);
1146 }
1147 }
1148
1149 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1150 {
1151 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1152 struct gallivm_state *gallivm = bld_base->base.gallivm;
1153 struct si_pipe_shader *shader = si_shader_ctx->shader;
1154 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1155 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1156 LLVMValueRef t_list_ptr;
1157 LLVMValueRef t_list;
1158 unsigned chan;
1159 int i;
1160
1161 while (!tgsi_parse_end_of_tokens(parse)) {
1162 struct tgsi_full_declaration *d =
1163 &parse->FullToken.FullDeclaration;
1164
1165 tgsi_parse_token(parse);
1166
1167 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1168 continue;
1169
1170 si_store_shader_io_attribs(&shader->shader, d);
1171 }
1172
1173 /* Load the ESGS ring resource descriptor */
1174 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1175 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1176 lp_build_const_int32(gallivm,
1177 NUM_PIPE_CONST_BUFFERS + 1));
1178
1179 for (i = 0; i < shader->shader.noutput; i++) {
1180 LLVMValueRef *out_ptr =
1181 si_shader_ctx->radeon_bld.soa.outputs[shader->shader.output[i].index];
1182
1183 for (chan = 0; chan < 4; chan++) {
1184 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1185 LLVMValueRef voffset =
1186 lp_build_const_int32(gallivm, (4 * i + chan) * 4);
1187 LLVMValueRef soffset =
1188 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1189 SI_PARAM_ES2GS_OFFSET);
1190
1191 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1192
1193 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1194 voffset, soffset, 0,
1195 V_008F0C_BUF_DATA_FORMAT_32,
1196 V_008F0C_BUF_NUM_FORMAT_UINT,
1197 1, 0, 1, 1, 0);
1198 }
1199 }
1200 }
1201
1202 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1203 {
1204 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1205 struct gallivm_state *gallivm = bld_base->base.gallivm;
1206 LLVMValueRef args[2];
1207
1208 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1209 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1210 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1211 LLVMVoidTypeInContext(gallivm->context), args, 2,
1212 LLVMNoUnwindAttribute);
1213 }
1214
1215 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1216 {
1217 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1218 struct gallivm_state *gallivm = bld_base->base.gallivm;
1219 struct si_pipe_shader *shader = si_shader_ctx->shader;
1220 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1221 struct si_shader_output_values *outputs = NULL;
1222 unsigned noutput = 0;
1223 int i;
1224
1225 while (!tgsi_parse_end_of_tokens(parse)) {
1226 struct tgsi_full_declaration *d =
1227 &parse->FullToken.FullDeclaration;
1228 unsigned index;
1229
1230 tgsi_parse_token(parse);
1231
1232 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1233 continue;
1234
1235 i = si_store_shader_io_attribs(&shader->shader, d);
1236 if (i < 0)
1237 continue;
1238
1239 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1240 (noutput + 1) * sizeof(outputs[0]));
1241 for (index = d->Range.First; index <= d->Range.Last; index++) {
1242 outputs[noutput].name = d->Semantic.Name;
1243 outputs[noutput].index = d->Semantic.Index;
1244 outputs[noutput].usage = d->Declaration.UsageMask;
1245
1246 for (i = 0; i < 4; i++)
1247 outputs[noutput].values[i] =
1248 LLVMBuildLoad(gallivm->builder,
1249 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1250 "");
1251 }
1252 noutput++;
1253 }
1254
1255 si_llvm_export_vs(bld_base, outputs, noutput);
1256 FREE(outputs);
1257 }
1258
1259 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1260 {
1261 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1262 struct si_shader * shader = &si_shader_ctx->shader->shader;
1263 struct lp_build_context * base = &bld_base->base;
1264 struct lp_build_context * uint =
1265 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1266 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1267 LLVMValueRef args[9];
1268 LLVMValueRef last_args[9] = { 0 };
1269 unsigned semantic_name;
1270 int depth_index = -1, stencil_index = -1;
1271 int i;
1272
1273 while (!tgsi_parse_end_of_tokens(parse)) {
1274 struct tgsi_full_declaration *d =
1275 &parse->FullToken.FullDeclaration;
1276 unsigned target;
1277 unsigned index;
1278
1279 tgsi_parse_token(parse);
1280
1281 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1282 parse->FullToken.FullProperty.Property.PropertyName ==
1283 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1284 shader->fs_write_all = TRUE;
1285
1286 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1287 continue;
1288
1289 i = si_store_shader_io_attribs(shader, d);
1290 if (i < 0)
1291 continue;
1292
1293 semantic_name = d->Semantic.Name;
1294 for (index = d->Range.First; index <= d->Range.Last; index++) {
1295 /* Select the correct target */
1296 switch(semantic_name) {
1297 case TGSI_SEMANTIC_POSITION:
1298 depth_index = index;
1299 continue;
1300 case TGSI_SEMANTIC_STENCIL:
1301 stencil_index = index;
1302 continue;
1303 case TGSI_SEMANTIC_COLOR:
1304 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1305 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1306 LLVMBuildStore(bld_base->base.gallivm->builder,
1307 bld_base->base.one,
1308 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1309
1310 if (d->Semantic.Index == 0 &&
1311 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1312 si_alpha_test(bld_base,
1313 si_shader_ctx->radeon_bld.soa.outputs[index]);
1314 break;
1315 default:
1316 target = 0;
1317 fprintf(stderr,
1318 "Warning: SI unhandled fs output type:%d\n",
1319 semantic_name);
1320 }
1321
1322 si_llvm_init_export_args_load(bld_base,
1323 si_shader_ctx->radeon_bld.soa.outputs[index],
1324 target, args);
1325
1326 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1327 /* If there is an export instruction waiting to be emitted, do so now. */
1328 if (last_args[0]) {
1329 lp_build_intrinsic(base->gallivm->builder,
1330 "llvm.SI.export",
1331 LLVMVoidTypeInContext(base->gallivm->context),
1332 last_args, 9);
1333 }
1334
1335 /* This instruction will be emitted at the end of the shader. */
1336 memcpy(last_args, args, sizeof(args));
1337
1338 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1339 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1340 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1341 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1342 si_llvm_init_export_args_load(bld_base,
1343 si_shader_ctx->radeon_bld.soa.outputs[index],
1344 V_008DFC_SQ_EXP_MRT + c, args);
1345 lp_build_intrinsic(base->gallivm->builder,
1346 "llvm.SI.export",
1347 LLVMVoidTypeInContext(base->gallivm->context),
1348 args, 9);
1349 }
1350 }
1351 } else {
1352 lp_build_intrinsic(base->gallivm->builder,
1353 "llvm.SI.export",
1354 LLVMVoidTypeInContext(base->gallivm->context),
1355 args, 9);
1356 }
1357 }
1358 }
1359
1360 if (depth_index >= 0 || stencil_index >= 0) {
1361 LLVMValueRef out_ptr;
1362 unsigned mask = 0;
1363
1364 /* Specify the target we are exporting */
1365 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1366
1367 if (depth_index >= 0) {
1368 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1369 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1370 mask |= 0x1;
1371
1372 if (stencil_index < 0) {
1373 args[6] =
1374 args[7] =
1375 args[8] = args[5];
1376 }
1377 }
1378
1379 if (stencil_index >= 0) {
1380 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1381 args[7] =
1382 args[8] =
1383 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1384 /* Only setting the stencil component bit (0x2) here
1385 * breaks some stencil piglit tests
1386 */
1387 mask |= 0x3;
1388
1389 if (depth_index < 0)
1390 args[5] = args[6];
1391 }
1392
1393 /* Specify which components to enable */
1394 args[0] = lp_build_const_int32(base->gallivm, mask);
1395
1396 args[1] =
1397 args[2] =
1398 args[4] = uint->zero;
1399
1400 if (last_args[0])
1401 lp_build_intrinsic(base->gallivm->builder,
1402 "llvm.SI.export",
1403 LLVMVoidTypeInContext(base->gallivm->context),
1404 args, 9);
1405 else
1406 memcpy(last_args, args, sizeof(args));
1407 }
1408
1409 if (!last_args[0]) {
1410 /* Specify which components to enable */
1411 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1412
1413 /* Specify the target we are exporting */
1414 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1415
1416 /* Set COMPR flag to zero to export data as 32-bit */
1417 last_args[4] = uint->zero;
1418
1419 /* dummy bits */
1420 last_args[5]= uint->zero;
1421 last_args[6]= uint->zero;
1422 last_args[7]= uint->zero;
1423 last_args[8]= uint->zero;
1424
1425 si_shader_ctx->shader->spi_shader_col_format |=
1426 V_028714_SPI_SHADER_32_ABGR;
1427 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1428 }
1429
1430 /* Specify whether the EXEC mask represents the valid mask */
1431 last_args[1] = uint->one;
1432
1433 /* Specify that this is the last export */
1434 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1435
1436 lp_build_intrinsic(base->gallivm->builder,
1437 "llvm.SI.export",
1438 LLVMVoidTypeInContext(base->gallivm->context),
1439 last_args, 9);
1440 }
1441
1442 static const struct lp_build_tgsi_action txf_action;
1443
1444 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1445 struct lp_build_tgsi_context * bld_base,
1446 struct lp_build_emit_data * emit_data);
1447
1448 static void tex_fetch_args(
1449 struct lp_build_tgsi_context * bld_base,
1450 struct lp_build_emit_data * emit_data)
1451 {
1452 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1453 struct gallivm_state *gallivm = bld_base->base.gallivm;
1454 const struct tgsi_full_instruction * inst = emit_data->inst;
1455 unsigned opcode = inst->Instruction.Opcode;
1456 unsigned target = inst->Texture.Texture;
1457 LLVMValueRef coords[4];
1458 LLVMValueRef address[16];
1459 int ref_pos;
1460 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1461 unsigned count = 0;
1462 unsigned chan;
1463 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1464 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1465
1466 if (target == TGSI_TEXTURE_BUFFER) {
1467 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1468 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1469 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1470 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1471
1472 /* Truncate v32i8 to v16i8. */
1473 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1474 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1475 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1476 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1477
1478 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1479 emit_data->args[0] = res;
1480 emit_data->args[1] = bld_base->uint_bld.zero;
1481 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1482 emit_data->arg_count = 3;
1483 return;
1484 }
1485
1486 /* Fetch and project texture coordinates */
1487 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1488 for (chan = 0; chan < 3; chan++ ) {
1489 coords[chan] = lp_build_emit_fetch(bld_base,
1490 emit_data->inst, 0,
1491 chan);
1492 if (opcode == TGSI_OPCODE_TXP)
1493 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1494 TGSI_OPCODE_DIV,
1495 coords[chan],
1496 coords[3]);
1497 }
1498
1499 if (opcode == TGSI_OPCODE_TXP)
1500 coords[3] = bld_base->base.one;
1501
1502 /* Pack LOD bias value */
1503 if (opcode == TGSI_OPCODE_TXB)
1504 address[count++] = coords[3];
1505
1506 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1507 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1508
1509 /* Pack depth comparison value */
1510 switch (target) {
1511 case TGSI_TEXTURE_SHADOW1D:
1512 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1513 case TGSI_TEXTURE_SHADOW2D:
1514 case TGSI_TEXTURE_SHADOWRECT:
1515 case TGSI_TEXTURE_SHADOWCUBE:
1516 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1517 assert(ref_pos >= 0);
1518 address[count++] = coords[ref_pos];
1519 break;
1520 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1521 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1522 }
1523
1524 /* Pack user derivatives */
1525 if (opcode == TGSI_OPCODE_TXD) {
1526 for (chan = 0; chan < 2; chan++) {
1527 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1528 if (num_coords > 1)
1529 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1530 }
1531 }
1532
1533 /* Pack texture coordinates */
1534 address[count++] = coords[0];
1535 if (num_coords > 1)
1536 address[count++] = coords[1];
1537 if (num_coords > 2)
1538 address[count++] = coords[2];
1539
1540 /* Pack LOD or sample index */
1541 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1542 address[count++] = coords[3];
1543
1544 if (count > 16) {
1545 assert(!"Cannot handle more than 16 texture address parameters");
1546 count = 16;
1547 }
1548
1549 for (chan = 0; chan < count; chan++ ) {
1550 address[chan] = LLVMBuildBitCast(gallivm->builder,
1551 address[chan],
1552 LLVMInt32TypeInContext(gallivm->context),
1553 "");
1554 }
1555
1556 /* Adjust the sample index according to FMASK.
1557 *
1558 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1559 * which is the identity mapping. Each nibble says which physical sample
1560 * should be fetched to get that sample.
1561 *
1562 * For example, 0x11111100 means there are only 2 samples stored and
1563 * the second sample covers 3/4 of the pixel. When reading samples 0
1564 * and 1, return physical sample 0 (determined by the first two 0s
1565 * in FMASK), otherwise return physical sample 1.
1566 *
1567 * The sample index should be adjusted as follows:
1568 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1569 */
1570 if (target == TGSI_TEXTURE_2D_MSAA ||
1571 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1572 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1573 struct lp_build_emit_data txf_emit_data = *emit_data;
1574 LLVMValueRef txf_address[4];
1575 unsigned txf_count = count;
1576
1577 memcpy(txf_address, address, sizeof(txf_address));
1578
1579 if (target == TGSI_TEXTURE_2D_MSAA) {
1580 txf_address[2] = bld_base->uint_bld.zero;
1581 }
1582 txf_address[3] = bld_base->uint_bld.zero;
1583
1584 /* Pad to a power-of-two size. */
1585 while (txf_count < util_next_power_of_two(txf_count))
1586 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1587
1588 /* Read FMASK using TXF. */
1589 txf_emit_data.chan = 0;
1590 txf_emit_data.dst_type = LLVMVectorType(
1591 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1592 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1593 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1594 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1595 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1596 txf_emit_data.arg_count = 3;
1597
1598 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1599
1600 /* Initialize some constants. */
1601 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1602 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1603
1604 /* Apply the formula. */
1605 LLVMValueRef fmask =
1606 LLVMBuildExtractElement(gallivm->builder,
1607 txf_emit_data.output[0],
1608 uint_bld->zero, "");
1609
1610 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1611
1612 LLVMValueRef sample_index4 =
1613 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1614
1615 LLVMValueRef shifted_fmask =
1616 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1617
1618 LLVMValueRef final_sample =
1619 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1620
1621 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1622 * resource descriptor is 0 (invalid),
1623 */
1624 LLVMValueRef fmask_desc =
1625 LLVMBuildBitCast(gallivm->builder,
1626 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1627 LLVMVectorType(uint_bld->elem_type, 8), "");
1628
1629 LLVMValueRef fmask_word1 =
1630 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1631 uint_bld->one, "");
1632
1633 LLVMValueRef word1_is_nonzero =
1634 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1635 fmask_word1, uint_bld->zero, "");
1636
1637 /* Replace the MSAA sample index. */
1638 address[sample_chan] =
1639 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1640 final_sample, address[sample_chan], "");
1641 }
1642
1643 /* Resource */
1644 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1645
1646 if (opcode == TGSI_OPCODE_TXF) {
1647 /* add tex offsets */
1648 if (inst->Texture.NumOffsets) {
1649 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1650 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1651 const struct tgsi_texture_offset * off = inst->TexOffsets;
1652
1653 assert(inst->Texture.NumOffsets == 1);
1654
1655 switch (target) {
1656 case TGSI_TEXTURE_3D:
1657 address[2] = lp_build_add(uint_bld, address[2],
1658 bld->immediates[off->Index][off->SwizzleZ]);
1659 /* fall through */
1660 case TGSI_TEXTURE_2D:
1661 case TGSI_TEXTURE_SHADOW2D:
1662 case TGSI_TEXTURE_RECT:
1663 case TGSI_TEXTURE_SHADOWRECT:
1664 case TGSI_TEXTURE_2D_ARRAY:
1665 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1666 address[1] =
1667 lp_build_add(uint_bld, address[1],
1668 bld->immediates[off->Index][off->SwizzleY]);
1669 /* fall through */
1670 case TGSI_TEXTURE_1D:
1671 case TGSI_TEXTURE_SHADOW1D:
1672 case TGSI_TEXTURE_1D_ARRAY:
1673 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1674 address[0] =
1675 lp_build_add(uint_bld, address[0],
1676 bld->immediates[off->Index][off->SwizzleX]);
1677 break;
1678 /* texture offsets do not apply to other texture targets */
1679 }
1680 }
1681
1682 emit_data->dst_type = LLVMVectorType(
1683 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1684 4);
1685
1686 emit_data->arg_count = 3;
1687 } else {
1688 /* Sampler */
1689 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1690
1691 emit_data->dst_type = LLVMVectorType(
1692 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1693 4);
1694
1695 emit_data->arg_count = 4;
1696 }
1697
1698 /* Dimensions */
1699 emit_data->args[emit_data->arg_count - 1] =
1700 lp_build_const_int32(bld_base->base.gallivm, target);
1701
1702 /* Pad to power of two vector */
1703 while (count < util_next_power_of_two(count))
1704 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1705
1706 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1707 }
1708
1709 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1710 struct lp_build_tgsi_context * bld_base,
1711 struct lp_build_emit_data * emit_data)
1712 {
1713 struct lp_build_context * base = &bld_base->base;
1714 char intr_name[127];
1715
1716 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1717 emit_data->output[emit_data->chan] = build_intrinsic(
1718 base->gallivm->builder,
1719 "llvm.SI.vs.load.input", emit_data->dst_type,
1720 emit_data->args, emit_data->arg_count,
1721 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1722 return;
1723 }
1724
1725 sprintf(intr_name, "%sv%ui32", action->intr_name,
1726 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1727
1728 emit_data->output[emit_data->chan] = build_intrinsic(
1729 base->gallivm->builder, intr_name, emit_data->dst_type,
1730 emit_data->args, emit_data->arg_count,
1731 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1732 }
1733
1734 static void txq_fetch_args(
1735 struct lp_build_tgsi_context * bld_base,
1736 struct lp_build_emit_data * emit_data)
1737 {
1738 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1739 const struct tgsi_full_instruction *inst = emit_data->inst;
1740 struct gallivm_state *gallivm = bld_base->base.gallivm;
1741
1742 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1743 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1744 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1745
1746 /* Read the size from the buffer descriptor directly. */
1747 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1748 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1749 size = LLVMBuildExtractElement(gallivm->builder, size,
1750 lp_build_const_int32(gallivm, 2), "");
1751 emit_data->args[0] = size;
1752 return;
1753 }
1754
1755 /* Mip level */
1756 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1757
1758 /* Resource */
1759 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1760
1761 /* Dimensions */
1762 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1763 inst->Texture.Texture);
1764
1765 emit_data->arg_count = 3;
1766
1767 emit_data->dst_type = LLVMVectorType(
1768 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1769 4);
1770 }
1771
1772 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1773 struct lp_build_tgsi_context * bld_base,
1774 struct lp_build_emit_data * emit_data)
1775 {
1776 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1777 /* Just return the buffer size. */
1778 emit_data->output[emit_data->chan] = emit_data->args[0];
1779 return;
1780 }
1781
1782 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1783 }
1784
1785 #if HAVE_LLVM >= 0x0304
1786
1787 static void si_llvm_emit_ddxy(
1788 const struct lp_build_tgsi_action * action,
1789 struct lp_build_tgsi_context * bld_base,
1790 struct lp_build_emit_data * emit_data)
1791 {
1792 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1793 struct gallivm_state *gallivm = bld_base->base.gallivm;
1794 struct lp_build_context * base = &bld_base->base;
1795 const struct tgsi_full_instruction *inst = emit_data->inst;
1796 unsigned opcode = inst->Instruction.Opcode;
1797 LLVMValueRef indices[2];
1798 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1799 LLVMValueRef tl, trbl, result[4];
1800 LLVMTypeRef i32;
1801 unsigned swizzle[4];
1802 unsigned c;
1803
1804 i32 = LLVMInt32TypeInContext(gallivm->context);
1805
1806 indices[0] = bld_base->uint_bld.zero;
1807 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1808 NULL, 0, LLVMReadNoneAttribute);
1809 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1810 indices, 2, "");
1811
1812 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1813 lp_build_const_int32(gallivm, 0xfffffffc), "");
1814 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1815 indices, 2, "");
1816
1817 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1818 lp_build_const_int32(gallivm,
1819 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1820 "");
1821 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1822 indices, 2, "");
1823
1824 for (c = 0; c < 4; ++c) {
1825 unsigned i;
1826
1827 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1828 for (i = 0; i < c; ++i) {
1829 if (swizzle[i] == swizzle[c]) {
1830 result[c] = result[i];
1831 break;
1832 }
1833 }
1834 if (i != c)
1835 continue;
1836
1837 LLVMBuildStore(gallivm->builder,
1838 LLVMBuildBitCast(gallivm->builder,
1839 lp_build_emit_fetch(bld_base, inst, 0, c),
1840 i32, ""),
1841 store_ptr);
1842
1843 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1844 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1845
1846 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1847 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1848
1849 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1850 }
1851
1852 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1853 }
1854
1855 #endif /* HAVE_LLVM >= 0x0304 */
1856
1857 /* Emit one vertex from the geometry shader */
1858 static void si_llvm_emit_vertex(
1859 const struct lp_build_tgsi_action *action,
1860 struct lp_build_tgsi_context *bld_base,
1861 struct lp_build_emit_data *emit_data)
1862 {
1863 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1864 struct lp_build_context *uint = &bld_base->uint_bld;
1865 struct si_shader *shader = &si_shader_ctx->shader->shader;
1866 struct gallivm_state *gallivm = bld_base->base.gallivm;
1867 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1868 LLVMValueRef gs_next_vertex;
1869 LLVMValueRef t_list_ptr;
1870 LLVMValueRef t_list;
1871 LLVMValueRef args[2];
1872 unsigned chan;
1873 int i;
1874
1875 /* Load the GSVS ring resource descriptor */
1876 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1877 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1878 lp_build_const_int32(gallivm,
1879 NUM_PIPE_CONST_BUFFERS + 2));
1880
1881 if (shader->noutput == 0) {
1882 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1883
1884 while (!tgsi_parse_end_of_tokens(parse)) {
1885 tgsi_parse_token(parse);
1886
1887 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1888 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
1889
1890 if (d->Declaration.File == TGSI_FILE_OUTPUT)
1891 si_store_shader_io_attribs(shader, d);
1892 }
1893 }
1894 }
1895
1896 /* Write vertex attribute values to GSVS ring */
1897 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
1898 for (i = 0; i < shader->noutput; i++) {
1899 LLVMValueRef *out_ptr =
1900 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
1901
1902 for (chan = 0; chan < 4; chan++) {
1903 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1904 LLVMValueRef soffset =
1905 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1906 SI_PARAM_GS2VS_OFFSET);
1907 LLVMValueRef voffset =
1908 lp_build_const_int32(gallivm, (i * 4 + chan) *
1909 shader->gs_max_out_vertices);
1910
1911 voffset = lp_build_add(uint, voffset, gs_next_vertex);
1912 voffset = lp_build_mul_imm(uint, voffset, 4);
1913
1914 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1915
1916 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1917 voffset, soffset, 0,
1918 V_008F0C_BUF_DATA_FORMAT_32,
1919 V_008F0C_BUF_NUM_FORMAT_UINT,
1920 1, 0, 1, 1, 0);
1921 }
1922 }
1923 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
1924 lp_build_const_int32(gallivm, 1));
1925 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
1926
1927 /* Signal vertex emission */
1928 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
1929 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1930 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1931 LLVMVoidTypeInContext(gallivm->context), args, 2,
1932 LLVMNoUnwindAttribute);
1933 }
1934
1935 /* Cut one primitive from the geometry shader */
1936 static void si_llvm_emit_primitive(
1937 const struct lp_build_tgsi_action *action,
1938 struct lp_build_tgsi_context *bld_base,
1939 struct lp_build_emit_data *emit_data)
1940 {
1941 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1942 struct gallivm_state *gallivm = bld_base->base.gallivm;
1943 LLVMValueRef args[2];
1944
1945 /* Signal primitive cut */
1946 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
1947 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1948 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1949 LLVMVoidTypeInContext(gallivm->context), args, 2,
1950 LLVMNoUnwindAttribute);
1951 }
1952
1953 static const struct lp_build_tgsi_action tex_action = {
1954 .fetch_args = tex_fetch_args,
1955 .emit = build_tex_intrinsic,
1956 .intr_name = "llvm.SI.sample."
1957 };
1958
1959 static const struct lp_build_tgsi_action txb_action = {
1960 .fetch_args = tex_fetch_args,
1961 .emit = build_tex_intrinsic,
1962 .intr_name = "llvm.SI.sampleb."
1963 };
1964
1965 #if HAVE_LLVM >= 0x0304
1966 static const struct lp_build_tgsi_action txd_action = {
1967 .fetch_args = tex_fetch_args,
1968 .emit = build_tex_intrinsic,
1969 .intr_name = "llvm.SI.sampled."
1970 };
1971 #endif
1972
1973 static const struct lp_build_tgsi_action txf_action = {
1974 .fetch_args = tex_fetch_args,
1975 .emit = build_tex_intrinsic,
1976 .intr_name = "llvm.SI.imageload."
1977 };
1978
1979 static const struct lp_build_tgsi_action txl_action = {
1980 .fetch_args = tex_fetch_args,
1981 .emit = build_tex_intrinsic,
1982 .intr_name = "llvm.SI.samplel."
1983 };
1984
1985 static const struct lp_build_tgsi_action txq_action = {
1986 .fetch_args = txq_fetch_args,
1987 .emit = build_txq_intrinsic,
1988 .intr_name = "llvm.SI.resinfo"
1989 };
1990
1991 static void create_meta_data(struct si_shader_context *si_shader_ctx)
1992 {
1993 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
1994 LLVMValueRef args[3];
1995
1996 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
1997 args[1] = 0;
1998 args[2] = lp_build_const_int32(gallivm, 1);
1999
2000 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2001 }
2002
2003 static void create_function(struct si_shader_context *si_shader_ctx)
2004 {
2005 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2006 struct gallivm_state *gallivm = bld_base->base.gallivm;
2007 struct si_pipe_shader *shader = si_shader_ctx->shader;
2008 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
2009 unsigned i, last_sgpr, num_params;
2010
2011 i8 = LLVMInt8TypeInContext(gallivm->context);
2012 i32 = LLVMInt32TypeInContext(gallivm->context);
2013 f32 = LLVMFloatTypeInContext(gallivm->context);
2014 v2i32 = LLVMVectorType(i32, 2);
2015 v3i32 = LLVMVectorType(i32, 3);
2016
2017 params[SI_PARAM_CONST] = LLVMPointerType(
2018 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
2019 /* We assume at most 16 textures per program at the moment.
2020 * This need probably need to be changed to support bindless textures */
2021 params[SI_PARAM_SAMPLER] = LLVMPointerType(
2022 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
2023 params[SI_PARAM_RESOURCE] = LLVMPointerType(
2024 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
2025
2026 switch (si_shader_ctx->type) {
2027 case TGSI_PROCESSOR_VERTEX:
2028 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
2029 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
2030 params[SI_PARAM_START_INSTANCE] = i32;
2031 num_params = SI_PARAM_START_INSTANCE+1;
2032 if (shader->key.vs.as_es) {
2033 params[SI_PARAM_ES2GS_OFFSET] = i32;
2034 num_params++;
2035 } else {
2036 /* The locations of the other parameters are assigned dynamically. */
2037
2038 /* Streamout SGPRs. */
2039 if (shader->selector->so.num_outputs) {
2040 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2041 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2042 }
2043 /* A streamout buffer offset is loaded if the stride is non-zero. */
2044 for (i = 0; i < 4; i++) {
2045 if (!shader->selector->so.stride[i])
2046 continue;
2047
2048 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2049 }
2050 }
2051
2052 last_sgpr = num_params-1;
2053
2054 /* VGPRs */
2055 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2056 params[num_params++] = i32; /* unused*/
2057 params[num_params++] = i32; /* unused */
2058 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2059 break;
2060
2061 case TGSI_PROCESSOR_GEOMETRY:
2062 params[SI_PARAM_GS2VS_OFFSET] = i32;
2063 params[SI_PARAM_GS_WAVE_ID] = i32;
2064 last_sgpr = SI_PARAM_GS_WAVE_ID;
2065
2066 /* VGPRs */
2067 params[SI_PARAM_VTX0_OFFSET] = i32;
2068 params[SI_PARAM_VTX1_OFFSET] = i32;
2069 params[SI_PARAM_PRIMITIVE_ID] = i32;
2070 params[SI_PARAM_VTX2_OFFSET] = i32;
2071 params[SI_PARAM_VTX3_OFFSET] = i32;
2072 params[SI_PARAM_VTX4_OFFSET] = i32;
2073 params[SI_PARAM_VTX5_OFFSET] = i32;
2074 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2075 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2076 break;
2077
2078 case TGSI_PROCESSOR_FRAGMENT:
2079 params[SI_PARAM_ALPHA_REF] = f32;
2080 params[SI_PARAM_PRIM_MASK] = i32;
2081 last_sgpr = SI_PARAM_PRIM_MASK;
2082 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2083 params[SI_PARAM_PERSP_CENTER] = v2i32;
2084 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2085 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2086 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2087 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2088 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2089 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2090 params[SI_PARAM_POS_X_FLOAT] = f32;
2091 params[SI_PARAM_POS_Y_FLOAT] = f32;
2092 params[SI_PARAM_POS_Z_FLOAT] = f32;
2093 params[SI_PARAM_POS_W_FLOAT] = f32;
2094 params[SI_PARAM_FRONT_FACE] = f32;
2095 params[SI_PARAM_ANCILLARY] = f32;
2096 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2097 params[SI_PARAM_POS_FIXED_PT] = f32;
2098 num_params = SI_PARAM_POS_FIXED_PT+1;
2099 break;
2100
2101 default:
2102 assert(0 && "unimplemented shader");
2103 return;
2104 }
2105
2106 assert(num_params <= Elements(params));
2107 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2108 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2109
2110 for (i = 0; i <= last_sgpr; ++i) {
2111 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2112 switch (i) {
2113 default:
2114 LLVMAddAttribute(P, LLVMInRegAttribute);
2115 break;
2116 #if HAVE_LLVM >= 0x0304
2117 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2118 * to move load. Inputs are constant so this is fine. */
2119 case SI_PARAM_CONST:
2120 case SI_PARAM_SAMPLER:
2121 case SI_PARAM_RESOURCE:
2122 LLVMAddAttribute(P, LLVMByValAttribute);
2123 break;
2124 #endif
2125 }
2126 }
2127
2128 #if HAVE_LLVM >= 0x0304
2129 if (bld_base->info &&
2130 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2131 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2132 si_shader_ctx->ddxy_lds =
2133 LLVMAddGlobalInAddressSpace(gallivm->module,
2134 LLVMArrayType(i32, 64),
2135 "ddxy_lds",
2136 LOCAL_ADDR_SPACE);
2137 #endif
2138 }
2139
2140 static void preload_constants(struct si_shader_context *si_shader_ctx)
2141 {
2142 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2143 struct gallivm_state * gallivm = bld_base->base.gallivm;
2144 const struct tgsi_shader_info * info = bld_base->info;
2145 unsigned buf;
2146 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2147
2148 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
2149 unsigned i, num_const = info->const_file_max[buf] + 1;
2150
2151 if (num_const == 0)
2152 continue;
2153
2154 /* Allocate space for the constant values */
2155 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2156
2157 /* Load the resource descriptor */
2158 si_shader_ctx->const_resource[buf] =
2159 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2160
2161 /* Load the constants, we rely on the code sinking to do the rest */
2162 for (i = 0; i < num_const * 4; ++i) {
2163 LLVMValueRef args[2] = {
2164 si_shader_ctx->const_resource[buf],
2165 lp_build_const_int32(gallivm, i * 4)
2166 };
2167 si_shader_ctx->constants[buf][i] =
2168 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
2169 bld_base->base.elem_type, args, 2,
2170 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2171 }
2172 }
2173 }
2174
2175 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2176 {
2177 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2178 struct gallivm_state * gallivm = bld_base->base.gallivm;
2179 const struct tgsi_shader_info * info = bld_base->info;
2180
2181 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2182
2183 LLVMValueRef res_ptr, samp_ptr;
2184 LLVMValueRef offset;
2185
2186 if (num_samplers == 0)
2187 return;
2188
2189 /* Allocate space for the values */
2190 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2191 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2192
2193 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2194 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2195
2196 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2197 for (i = 0; i < num_samplers; ++i) {
2198 /* Resource */
2199 offset = lp_build_const_int32(gallivm, i);
2200 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2201
2202 /* Sampler */
2203 offset = lp_build_const_int32(gallivm, i);
2204 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2205
2206 /* FMASK resource */
2207 if (info->is_msaa_sampler[i]) {
2208 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
2209 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
2210 build_indexed_load(si_shader_ctx, res_ptr, offset);
2211 }
2212 }
2213 }
2214
2215 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2216 {
2217 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2218 struct gallivm_state * gallivm = bld_base->base.gallivm;
2219 unsigned i;
2220
2221 if (!si_shader_ctx->shader->selector->so.num_outputs)
2222 return;
2223
2224 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2225 SI_PARAM_SO_BUFFER);
2226
2227 /* Load the resources, we rely on the code sinking to do the rest */
2228 for (i = 0; i < 4; ++i) {
2229 if (si_shader_ctx->shader->selector->so.stride[i]) {
2230 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
2231
2232 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2233 }
2234 }
2235 }
2236
2237 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2238 LLVMModuleRef mod)
2239 {
2240 unsigned i;
2241 uint32_t *ptr;
2242 struct radeon_llvm_binary binary;
2243 bool dump = r600_can_dump_shader(&sctx->screen->b,
2244 shader->selector ? shader->selector->tokens : NULL);
2245 memset(&binary, 0, sizeof(binary));
2246 radeon_llvm_compile(mod, &binary,
2247 r600_get_llvm_processor_name(sctx->screen->b.family), dump);
2248 if (dump && ! binary.disassembled) {
2249 fprintf(stderr, "SI CODE:\n");
2250 for (i = 0; i < binary.code_size; i+=4 ) {
2251 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2252 binary.code[i + 2], binary.code[i + 1],
2253 binary.code[i]);
2254 }
2255 }
2256
2257 /* XXX: We may be able to emit some of these values directly rather than
2258 * extracting fields to be emitted later.
2259 */
2260 for (i = 0; i < binary.config_size; i+= 8) {
2261 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2262 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2263 switch (reg) {
2264 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2265 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2266 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2267 case R_00B848_COMPUTE_PGM_RSRC1:
2268 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2269 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2270 break;
2271 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2272 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2273 break;
2274 case R_00B84C_COMPUTE_PGM_RSRC2:
2275 shader->lds_size = G_00B84C_LDS_SIZE(value);
2276 break;
2277 case R_0286CC_SPI_PS_INPUT_ENA:
2278 shader->spi_ps_input_ena = value;
2279 break;
2280 default:
2281 fprintf(stderr, "Warning: Compiler emitted unknown "
2282 "config register: 0x%x\n", reg);
2283 break;
2284 }
2285 }
2286
2287 /* copy new shader */
2288 r600_resource_reference(&shader->bo, NULL);
2289 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2290 binary.code_size);
2291 if (shader->bo == NULL) {
2292 return -ENOMEM;
2293 }
2294
2295 ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2296 if (0 /*SI_BIG_ENDIAN*/) {
2297 for (i = 0; i < binary.code_size / 4; ++i) {
2298 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
2299 }
2300 } else {
2301 memcpy(ptr, binary.code, binary.code_size);
2302 }
2303 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2304
2305 free(binary.code);
2306 free(binary.config);
2307
2308 return 0;
2309 }
2310
2311 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2312 static int si_generate_gs_copy_shader(struct si_context *sctx,
2313 struct si_shader_context *si_shader_ctx,
2314 bool dump)
2315 {
2316 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2317 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2318 struct lp_build_context *base = &bld_base->base;
2319 struct lp_build_context *uint = &bld_base->uint_bld;
2320 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2321 struct si_shader_output_values *outputs;
2322 LLVMValueRef t_list_ptr, t_list;
2323 LLVMValueRef args[9];
2324 int i, r;
2325
2326 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2327
2328 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2329 si_shader_ctx->gs_for_vs = gs;
2330
2331 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2332
2333 create_meta_data(si_shader_ctx);
2334 create_function(si_shader_ctx);
2335 preload_streamout_buffers(si_shader_ctx);
2336
2337 /* Load the GSVS ring resource descriptor */
2338 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2339 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2340 lp_build_const_int32(gallivm,
2341 NUM_PIPE_CONST_BUFFERS + 1));
2342
2343 args[0] = t_list;
2344 args[1] = lp_build_mul_imm(uint,
2345 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2346 si_shader_ctx->param_vertex_id),
2347 4);
2348 args[3] = uint->zero;
2349 args[4] = uint->one; /* OFFEN */
2350 args[5] = uint->zero; /* IDXEN */
2351 args[6] = uint->one; /* GLC */
2352 args[7] = uint->one; /* SLC */
2353 args[8] = uint->zero; /* TFE */
2354
2355 /* Fetch vertex data from GSVS ring */
2356 for (i = 0; i < gs->noutput; ++i) {
2357 struct si_shader_output *out = gs->output + i;
2358 unsigned chan;
2359
2360 outputs[i].name = out->name;
2361 outputs[i].index = out->index;
2362 outputs[i].usage = out->usage;
2363
2364 for (chan = 0; chan < 4; chan++) {
2365 args[2] = lp_build_const_int32(gallivm,
2366 (i * 4 + chan) *
2367 gs->gs_max_out_vertices * 16 * 4);
2368
2369 outputs[i].values[chan] =
2370 LLVMBuildBitCast(gallivm->builder,
2371 build_intrinsic(gallivm->builder,
2372 "llvm.SI.buffer.load.dword.i32.i32",
2373 LLVMInt32TypeInContext(gallivm->context),
2374 args, 9,
2375 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2376 base->elem_type, "");
2377 }
2378 }
2379
2380 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2381
2382 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2383
2384 if (dump)
2385 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2386
2387 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2388 bld_base->base.gallivm->module);
2389
2390 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2391
2392 FREE(outputs);
2393 return r;
2394 }
2395
2396 int si_pipe_shader_create(
2397 struct pipe_context *ctx,
2398 struct si_pipe_shader *shader)
2399 {
2400 struct si_context *sctx = (struct si_context*)ctx;
2401 struct si_pipe_shader_selector *sel = shader->selector;
2402 struct si_shader_context si_shader_ctx;
2403 struct tgsi_shader_info shader_info;
2404 struct lp_build_tgsi_context * bld_base;
2405 LLVMModuleRef mod;
2406 int r = 0;
2407 bool dump = r600_can_dump_shader(&sctx->screen->b, shader->selector->tokens);
2408
2409 assert(shader->shader.noutput == 0);
2410 assert(shader->shader.nparam == 0);
2411 assert(shader->shader.ninput == 0);
2412
2413 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2414 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2415 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2416
2417 tgsi_scan_shader(sel->tokens, &shader_info);
2418
2419 shader->shader.uses_kill = shader_info.uses_kill;
2420 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2421 bld_base->info = &shader_info;
2422 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2423
2424 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2425 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2426 #if HAVE_LLVM >= 0x0304
2427 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2428 #endif
2429 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2430 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2431 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2432 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2433
2434 #if HAVE_LLVM >= 0x0304
2435 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2436 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2437 #endif
2438
2439 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2440 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2441
2442 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2443 si_shader_ctx.tokens = sel->tokens;
2444 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2445 si_shader_ctx.shader = shader;
2446 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2447
2448 switch (si_shader_ctx.type) {
2449 case TGSI_PROCESSOR_VERTEX:
2450 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2451 if (shader->key.vs.as_es) {
2452 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2453 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2454 } else {
2455 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2456 }
2457 break;
2458 case TGSI_PROCESSOR_GEOMETRY: {
2459 int i;
2460
2461 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2462 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2463 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2464
2465 for (i = 0; i < shader_info.num_properties; i++) {
2466 switch (shader_info.properties[i].name) {
2467 case TGSI_PROPERTY_GS_INPUT_PRIM:
2468 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2469 break;
2470 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2471 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2472 break;
2473 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2474 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2475 break;
2476 }
2477 }
2478 break;
2479 }
2480 case TGSI_PROCESSOR_FRAGMENT:
2481 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2482 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2483 break;
2484 default:
2485 assert(!"Unsupported shader type");
2486 return -1;
2487 }
2488
2489 create_meta_data(&si_shader_ctx);
2490 create_function(&si_shader_ctx);
2491 preload_constants(&si_shader_ctx);
2492 preload_samplers(&si_shader_ctx);
2493 preload_streamout_buffers(&si_shader_ctx);
2494
2495 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2496 * conversion fails. */
2497 if (dump) {
2498 tgsi_dump(sel->tokens, 0);
2499 si_dump_streamout(&sel->so);
2500 }
2501
2502 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2503 si_shader_ctx.gs_next_vertex =
2504 lp_build_alloca(bld_base->base.gallivm,
2505 bld_base->uint_bld.elem_type, "");
2506 }
2507
2508 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2509 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2510 goto out;
2511 }
2512
2513 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2514
2515 mod = bld_base->base.gallivm->module;
2516 r = si_compile_llvm(sctx, shader, mod);
2517 if (r) {
2518 fprintf(stderr, "LLVM failed to compile shader\n");
2519 goto out;
2520 }
2521
2522 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2523
2524 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2525 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2526 shader->gs_copy_shader->selector = shader->selector;
2527 si_shader_ctx.shader = shader->gs_copy_shader;
2528 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2529 free(shader->gs_copy_shader);
2530 shader->gs_copy_shader = NULL;
2531 goto out;
2532 }
2533 }
2534
2535 tgsi_parse_free(&si_shader_ctx.parse);
2536
2537 out:
2538 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2539 FREE(si_shader_ctx.constants[i]);
2540 FREE(si_shader_ctx.resources);
2541 FREE(si_shader_ctx.samplers);
2542
2543 return r;
2544 }
2545
2546 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2547 {
2548 r600_resource_reference(&shader->bo, NULL);
2549 }