projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "si_shader_internal.h"
41 #include "si_pipe.h"
42 #include "sid.h"
43
44 #include "compiler/nir/nir.h"
45
46 static const char *scratch_rsrc_dword0_symbol =
47 "SCRATCH_RSRC_DWORD0";
48
49 static const char *scratch_rsrc_dword1_symbol =
50 "SCRATCH_RSRC_DWORD1";
51
52 struct si_shader_output_values
53 {
54 LLVMValueRef values[4];
55 unsigned semantic_name;
56 unsigned semantic_index;
57 ubyte vertex_stream[4];
58 };
59
60 /**
61 * Used to collect types and other info about arguments of the LLVM function
62 * before the function is created.
63 */
64 struct si_function_info {
65 LLVMTypeRef types[100];
66 LLVMValueRef *assign[100];
67 unsigned num_sgpr_params;
68 unsigned num_params;
69 };
70
71 enum si_arg_regfile {
72 ARG_SGPR,
73 ARG_VGPR
74 };
75
76 static void si_init_shader_ctx(struct si_shader_context *ctx,
77 struct si_screen *sscreen,
78 LLVMTargetMachineRef tm);
79
80 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
81 struct lp_build_tgsi_context *bld_base,
82 struct lp_build_emit_data *emit_data);
83
84 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
85 FILE *f);
86
87 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
90 union si_shader_part_key *key);
91 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
92 union si_shader_part_key *key);
93 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
94 union si_shader_part_key *key);
95
96 /* Ideally pass the sample mask input to the PS epilog as v14, which
97 * is its usual location, so that the shader doesn't have to add v_mov.
98 */
99 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
100
101 enum {
102 CONST_ADDR_SPACE = 2,
103 LOCAL_ADDR_SPACE = 3,
104 };
105
106 static bool is_merged_shader(struct si_shader *shader)
107 {
108 if (shader->selector->screen->info.chip_class <= VI)
109 return false;
110
111 return shader->key.as_ls ||
112 shader->key.as_es ||
113 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
114 shader->selector->type == PIPE_SHADER_GEOMETRY;
115 }
116
117 static void si_init_function_info(struct si_function_info *fninfo)
118 {
119 fninfo->num_params = 0;
120 fninfo->num_sgpr_params = 0;
121 }
122
123 static unsigned add_arg_assign(struct si_function_info *fninfo,
124 enum si_arg_regfile regfile, LLVMTypeRef type,
125 LLVMValueRef *assign)
126 {
127 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
128
129 unsigned idx = fninfo->num_params++;
130 assert(idx < ARRAY_SIZE(fninfo->types));
131
132 if (regfile == ARG_SGPR)
133 fninfo->num_sgpr_params = fninfo->num_params;
134
135 fninfo->types[idx] = type;
136 fninfo->assign[idx] = assign;
137 return idx;
138 }
139
140 static unsigned add_arg(struct si_function_info *fninfo,
141 enum si_arg_regfile regfile, LLVMTypeRef type)
142 {
143 return add_arg_assign(fninfo, regfile, type, NULL);
144 }
145
146 static void add_arg_assign_checked(struct si_function_info *fninfo,
147 enum si_arg_regfile regfile, LLVMTypeRef type,
148 LLVMValueRef *assign, unsigned idx)
149 {
150 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
151 assert(actual == idx);
152 }
153
154 static void add_arg_checked(struct si_function_info *fninfo,
155 enum si_arg_regfile regfile, LLVMTypeRef type,
156 unsigned idx)
157 {
158 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Get the value of a shader input parameter and extract a bitfield.
233 */
234 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
235 unsigned param, unsigned rshift,
236 unsigned bitwidth)
237 {
238 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
239 param);
240
241 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
242 value = ac_to_integer(&ctx->ac, value);
243
244 if (rshift)
245 value = LLVMBuildLShr(ctx->ac.builder, value,
246 LLVMConstInt(ctx->i32, rshift, 0), "");
247
248 if (rshift + bitwidth < 32) {
249 unsigned mask = (1 << bitwidth) - 1;
250 value = LLVMBuildAnd(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, mask, 0), "");
252 }
253
254 return value;
255 }
256
257 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
258 {
259 switch (ctx->type) {
260 case PIPE_SHADER_TESS_CTRL:
261 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
262
263 case PIPE_SHADER_TESS_EVAL:
264 return LLVMGetParam(ctx->main_fn,
265 ctx->param_tes_rel_patch_id);
266
267 default:
268 assert(0);
269 return NULL;
270 }
271 }
272
273 /* Tessellation shaders pass outputs to the next shader using LDS.
274 *
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
277 *
278 * The LDS layout is:
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
282 * - ...
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
289 * - ...
290 *
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
292 */
293
294 static LLVMValueRef
295 get_tcs_in_patch_stride(struct si_shader_context *ctx)
296 {
297 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
298 }
299
300 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
301 {
302 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
303
304 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
305 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
306
307 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
308 }
309
310 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
311 {
312 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
313
314 return LLVMConstInt(ctx->i32, stride, 0);
315 }
316
317 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
320 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
321
322 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
323 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
324 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
325 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
326 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
327 num_patch_outputs * 4;
328 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
329 }
330
331 static LLVMValueRef
332 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
333 {
334 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
335 unpack_param(ctx,
336 ctx->param_tcs_out_lds_offsets,
337 0, 16),
338 4);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 16, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
353 {
354 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
355 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
356
357 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
358 }
359
360 static LLVMValueRef
361 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
362 {
363 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
364 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
368 LLVMBuildMul(ctx->ac.builder, patch_stride,
369 rel_patch_id, ""),
370 "");
371 }
372
373 static LLVMValueRef
374 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
375 {
376 LLVMValueRef patch0_patch_data_offset =
377 get_tcs_out_patch0_patch_data_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
382 LLVMBuildMul(ctx->ac.builder, patch_stride,
383 rel_patch_id, ""),
384 "");
385 }
386
387 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
388 {
389 unsigned tcs_out_vertices =
390 ctx->shader->selector ?
391 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
392
393 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
394 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
395 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
396
397 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
398 }
399
400 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
401 {
402 unsigned stride;
403
404 switch (ctx->type) {
405 case PIPE_SHADER_VERTEX:
406 stride = util_last_bit64(ctx->shader->selector->outputs_written);
407 return LLVMConstInt(ctx->i32, stride * 4, 0);
408
409 case PIPE_SHADER_TESS_CTRL:
410 if (ctx->screen->info.chip_class >= GFX9 &&
411 ctx->shader->is_monolithic) {
412 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
413 return LLVMConstInt(ctx->i32, stride * 4, 0);
414 }
415 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
416
417 default:
418 assert(0);
419 return NULL;
420 }
421 }
422
423 static LLVMValueRef get_instance_index_for_fetch(
424 struct si_shader_context *ctx,
425 unsigned param_start_instance, LLVMValueRef divisor)
426 {
427 LLVMValueRef result = ctx->abi.instance_id;
428
429 /* The division must be done before START_INSTANCE is added. */
430 if (divisor != ctx->i32_1)
431 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
432
433 return LLVMBuildAdd(ctx->ac.builder, result,
434 LLVMGetParam(ctx->main_fn, param_start_instance), "");
435 }
436
437 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
438 * to float. */
439 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
440 LLVMValueRef vec4,
441 unsigned double_index)
442 {
443 LLVMBuilderRef builder = ctx->ac.builder;
444 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
445 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
446 LLVMVectorType(f64, 2), "");
447 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
448 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
449 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
450 }
451
452 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
453 LLVMValueRef i32, unsigned index)
454 {
455 assert(index <= 1);
456
457 if (index == 1)
458 return LLVMBuildAShr(ctx->ac.builder, i32,
459 LLVMConstInt(ctx->i32, 16, 0), "");
460
461 return LLVMBuildSExt(ctx->ac.builder,
462 LLVMBuildTrunc(ctx->ac.builder, i32,
463 ctx->ac.i16, ""),
464 ctx->i32, "");
465 }
466
467 void si_llvm_load_input_vs(
468 struct si_shader_context *ctx,
469 unsigned input_index,
470 LLVMValueRef out[4])
471 {
472 unsigned vs_blit_property =
473 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
474
475 if (vs_blit_property) {
476 LLVMValueRef vertex_id = ctx->abi.vertex_id;
477 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
478 LLVMIntULE, vertex_id,
479 ctx->i32_1, "");
480 /* Use LLVMIntNE, because we have 3 vertices and only
481 * the middle one should use y2.
482 */
483 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
484 LLVMIntNE, vertex_id,
485 ctx->i32_1, "");
486
487 if (input_index == 0) {
488 /* Position: */
489 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs);
491 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
492 ctx->param_vs_blit_inputs + 1);
493
494 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
495 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
496 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
497 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
498
499 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
500 x1, x2, "");
501 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
502 y1, y2, "");
503
504 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
505 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
506 out[2] = LLVMGetParam(ctx->main_fn,
507 ctx->param_vs_blit_inputs + 2);
508 out[3] = ctx->ac.f32_1;
509 return;
510 }
511
512 /* Color or texture coordinates: */
513 assert(input_index == 1);
514
515 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
516 for (int i = 0; i < 4; i++) {
517 out[i] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 3 + i);
519 }
520 } else {
521 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
522 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 3);
524 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
525 ctx->param_vs_blit_inputs + 4);
526 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
527 ctx->param_vs_blit_inputs + 5);
528 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 6);
530
531 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
532 x1, x2, "");
533 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
534 y1, y2, "");
535 out[2] = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 7);
537 out[3] = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 8);
539 }
540 return;
541 }
542
543 unsigned chan;
544 unsigned fix_fetch;
545 unsigned num_fetches;
546 unsigned fetch_stride;
547
548 LLVMValueRef t_list_ptr;
549 LLVMValueRef t_offset;
550 LLVMValueRef t_list;
551 LLVMValueRef vertex_index;
552 LLVMValueRef input[3];
553
554 /* Load the T list */
555 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
556
557 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
558
559 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
560
561 vertex_index = LLVMGetParam(ctx->main_fn,
562 ctx->param_vertex_index0 +
563 input_index);
564
565 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
566
567 /* Do multiple loads for special formats. */
568 switch (fix_fetch) {
569 case SI_FIX_FETCH_RGB_64_FLOAT:
570 num_fetches = 3; /* 3 2-dword loads */
571 fetch_stride = 8;
572 break;
573 case SI_FIX_FETCH_RGBA_64_FLOAT:
574 num_fetches = 2; /* 2 4-dword loads */
575 fetch_stride = 16;
576 break;
577 case SI_FIX_FETCH_RGB_8:
578 case SI_FIX_FETCH_RGB_8_INT:
579 num_fetches = 3;
580 fetch_stride = 1;
581 break;
582 case SI_FIX_FETCH_RGB_16:
583 case SI_FIX_FETCH_RGB_16_INT:
584 num_fetches = 3;
585 fetch_stride = 2;
586 break;
587 default:
588 num_fetches = 1;
589 fetch_stride = 0;
590 }
591
592 for (unsigned i = 0; i < num_fetches; i++) {
593 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
594
595 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
596 vertex_index, voffset,
597 true);
598 }
599
600 /* Break up the vec4 into individual components */
601 for (chan = 0; chan < 4; chan++) {
602 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
603 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
604 input[0], llvm_chan, "");
605 }
606
607 switch (fix_fetch) {
608 case SI_FIX_FETCH_A2_SNORM:
609 case SI_FIX_FETCH_A2_SSCALED:
610 case SI_FIX_FETCH_A2_SINT: {
611 /* The hardware returns an unsigned value; convert it to a
612 * signed one.
613 */
614 LLVMValueRef tmp = out[3];
615 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
616
617 /* First, recover the sign-extended signed integer value. */
618 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
619 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
620 else
621 tmp = ac_to_integer(&ctx->ac, tmp);
622
623 /* For the integer-like cases, do a natural sign extension.
624 *
625 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
626 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
627 * exponent.
628 */
629 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
630 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
631 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
632 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
633
634 /* Convert back to the right type. */
635 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
636 LLVMValueRef clamp;
637 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
638 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
639 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
640 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
641 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
642 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
643 }
644
645 out[3] = tmp;
646 break;
647 }
648 case SI_FIX_FETCH_RGBA_32_UNORM:
649 case SI_FIX_FETCH_RGBX_32_UNORM:
650 for (chan = 0; chan < 4; chan++) {
651 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
652 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
653 out[chan], ctx->f32, "");
654 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
655 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
656 }
657 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
658 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
659 out[3] = LLVMConstReal(ctx->f32, 1);
660 break;
661 case SI_FIX_FETCH_RGBA_32_SNORM:
662 case SI_FIX_FETCH_RGBX_32_SNORM:
663 case SI_FIX_FETCH_RGBA_32_FIXED:
664 case SI_FIX_FETCH_RGBX_32_FIXED: {
665 double scale;
666 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
667 scale = 1.0 / 0x10000;
668 else
669 scale = 1.0 / INT_MAX;
670
671 for (chan = 0; chan < 4; chan++) {
672 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
673 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
674 out[chan], ctx->f32, "");
675 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
676 LLVMConstReal(ctx->f32, scale), "");
677 }
678 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
679 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
680 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
681 out[3] = LLVMConstReal(ctx->f32, 1);
682 break;
683 }
684 case SI_FIX_FETCH_RGBA_32_USCALED:
685 for (chan = 0; chan < 4; chan++) {
686 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
687 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
688 out[chan], ctx->f32, "");
689 }
690 break;
691 case SI_FIX_FETCH_RGBA_32_SSCALED:
692 for (chan = 0; chan < 4; chan++) {
693 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
694 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
695 out[chan], ctx->f32, "");
696 }
697 break;
698 case SI_FIX_FETCH_RG_64_FLOAT:
699 for (chan = 0; chan < 2; chan++)
700 out[chan] = extract_double_to_float(ctx, input[0], chan);
701
702 out[2] = LLVMConstReal(ctx->f32, 0);
703 out[3] = LLVMConstReal(ctx->f32, 1);
704 break;
705 case SI_FIX_FETCH_RGB_64_FLOAT:
706 for (chan = 0; chan < 3; chan++)
707 out[chan] = extract_double_to_float(ctx, input[chan], 0);
708
709 out[3] = LLVMConstReal(ctx->f32, 1);
710 break;
711 case SI_FIX_FETCH_RGBA_64_FLOAT:
712 for (chan = 0; chan < 4; chan++) {
713 out[chan] = extract_double_to_float(ctx, input[chan / 2],
714 chan % 2);
715 }
716 break;
717 case SI_FIX_FETCH_RGB_8:
718 case SI_FIX_FETCH_RGB_8_INT:
719 case SI_FIX_FETCH_RGB_16:
720 case SI_FIX_FETCH_RGB_16_INT:
721 for (chan = 0; chan < 3; chan++) {
722 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
723 input[chan],
724 ctx->i32_0, "");
725 }
726 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
727 fix_fetch == SI_FIX_FETCH_RGB_16) {
728 out[3] = LLVMConstReal(ctx->f32, 1);
729 } else {
730 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
731 }
732 break;
733 }
734 }
735
736 static void declare_input_vs(
737 struct si_shader_context *ctx,
738 unsigned input_index,
739 const struct tgsi_full_declaration *decl,
740 LLVMValueRef out[4])
741 {
742 si_llvm_load_input_vs(ctx, input_index, out);
743 }
744
745 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
746 unsigned swizzle)
747 {
748 if (swizzle > 0)
749 return ctx->i32_0;
750
751 switch (ctx->type) {
752 case PIPE_SHADER_VERTEX:
753 return LLVMGetParam(ctx->main_fn,
754 ctx->param_vs_prim_id);
755 case PIPE_SHADER_TESS_CTRL:
756 return LLVMGetParam(ctx->main_fn,
757 ctx->param_tcs_patch_id);
758 case PIPE_SHADER_TESS_EVAL:
759 return LLVMGetParam(ctx->main_fn,
760 ctx->param_tes_patch_id);
761 case PIPE_SHADER_GEOMETRY:
762 return ctx->abi.gs_prim_id;
763 default:
764 assert(0);
765 return ctx->i32_0;
766 }
767 }
768
769 /**
770 * Return the value of tgsi_ind_register for indexing.
771 * This is the indirect index with the constant offset added to it.
772 */
773 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
774 const struct tgsi_ind_register *ind,
775 unsigned addr_mul,
776 int rel_index)
777 {
778 LLVMValueRef result;
779
780 if (ind->File == TGSI_FILE_ADDRESS) {
781 result = ctx->addrs[ind->Index][ind->Swizzle];
782 result = LLVMBuildLoad(ctx->ac.builder, result, "");
783 } else {
784 struct tgsi_full_src_register src = {};
785
786 src.Register.File = ind->File;
787 src.Register.Index = ind->Index;
788
789 /* Set the second index to 0 for constants. */
790 if (ind->File == TGSI_FILE_CONSTANT)
791 src.Register.Dimension = 1;
792
793 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
794 TGSI_TYPE_SIGNED,
795 ind->Swizzle);
796 result = ac_to_integer(&ctx->ac, result);
797 }
798
799 if (addr_mul != 1)
800 result = LLVMBuildMul(ctx->ac.builder, result,
801 LLVMConstInt(ctx->i32, addr_mul, 0), "");
802 result = LLVMBuildAdd(ctx->ac.builder, result,
803 LLVMConstInt(ctx->i32, rel_index, 0), "");
804 return result;
805 }
806
807 /**
808 * Like si_get_indirect_index, but restricts the return value to a (possibly
809 * undefined) value inside [0..num).
810 */
811 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
812 const struct tgsi_ind_register *ind,
813 int rel_index, unsigned num)
814 {
815 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
816
817 return si_llvm_bound_index(ctx, result, num);
818 }
819
820
821 /**
822 * Calculate a dword address given an input or output register and a stride.
823 */
824 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
825 const struct tgsi_full_dst_register *dst,
826 const struct tgsi_full_src_register *src,
827 LLVMValueRef vertex_dw_stride,
828 LLVMValueRef base_addr)
829 {
830 struct tgsi_shader_info *info = &ctx->shader->selector->info;
831 ubyte *name, *index, *array_first;
832 int first, param;
833 struct tgsi_full_dst_register reg;
834
835 /* Set the register description. The address computation is the same
836 * for sources and destinations. */
837 if (src) {
838 reg.Register.File = src->Register.File;
839 reg.Register.Index = src->Register.Index;
840 reg.Register.Indirect = src->Register.Indirect;
841 reg.Register.Dimension = src->Register.Dimension;
842 reg.Indirect = src->Indirect;
843 reg.Dimension = src->Dimension;
844 reg.DimIndirect = src->DimIndirect;
845 } else
846 reg = *dst;
847
848 /* If the register is 2-dimensional (e.g. an array of vertices
849 * in a primitive), calculate the base address of the vertex. */
850 if (reg.Register.Dimension) {
851 LLVMValueRef index;
852
853 if (reg.Dimension.Indirect)
854 index = si_get_indirect_index(ctx, &reg.DimIndirect,
855 1, reg.Dimension.Index);
856 else
857 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
858
859 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
860 LLVMBuildMul(ctx->ac.builder, index,
861 vertex_dw_stride, ""), "");
862 }
863
864 /* Get information about the register. */
865 if (reg.Register.File == TGSI_FILE_INPUT) {
866 name = info->input_semantic_name;
867 index = info->input_semantic_index;
868 array_first = info->input_array_first;
869 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
870 name = info->output_semantic_name;
871 index = info->output_semantic_index;
872 array_first = info->output_array_first;
873 } else {
874 assert(0);
875 return NULL;
876 }
877
878 if (reg.Register.Indirect) {
879 /* Add the relative address of the element. */
880 LLVMValueRef ind_index;
881
882 if (reg.Indirect.ArrayID)
883 first = array_first[reg.Indirect.ArrayID];
884 else
885 first = reg.Register.Index;
886
887 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
888 1, reg.Register.Index - first);
889
890 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
891 LLVMBuildMul(ctx->ac.builder, ind_index,
892 LLVMConstInt(ctx->i32, 4, 0), ""), "");
893
894 param = reg.Register.Dimension ?
895 si_shader_io_get_unique_index(name[first], index[first]) :
896 si_shader_io_get_unique_index_patch(name[first], index[first]);
897 } else {
898 param = reg.Register.Dimension ?
899 si_shader_io_get_unique_index(name[reg.Register.Index],
900 index[reg.Register.Index]) :
901 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
902 index[reg.Register.Index]);
903 }
904
905 /* Add the base address of the element. */
906 return LLVMBuildAdd(ctx->ac.builder, base_addr,
907 LLVMConstInt(ctx->i32, param * 4, 0), "");
908 }
909
910 /* The offchip buffer layout for TCS->TES is
911 *
912 * - attribute 0 of patch 0 vertex 0
913 * - attribute 0 of patch 0 vertex 1
914 * - attribute 0 of patch 0 vertex 2
915 * ...
916 * - attribute 0 of patch 1 vertex 0
917 * - attribute 0 of patch 1 vertex 1
918 * ...
919 * - attribute 1 of patch 0 vertex 0
920 * - attribute 1 of patch 0 vertex 1
921 * ...
922 * - per patch attribute 0 of patch 0
923 * - per patch attribute 0 of patch 1
924 * ...
925 *
926 * Note that every attribute has 4 components.
927 */
928 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
929 LLVMValueRef rel_patch_id,
930 LLVMValueRef vertex_index,
931 LLVMValueRef param_index)
932 {
933 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
934 LLVMValueRef param_stride, constant16;
935
936 vertices_per_patch = get_num_tcs_out_vertices(ctx);
937 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
938 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
939 num_patches, "");
940
941 constant16 = LLVMConstInt(ctx->i32, 16, 0);
942 if (vertex_index) {
943 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
944 vertices_per_patch, "");
945
946 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
947 vertex_index, "");
948
949 param_stride = total_vertices;
950 } else {
951 base_addr = rel_patch_id;
952 param_stride = num_patches;
953 }
954
955 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
956 LLVMBuildMul(ctx->ac.builder, param_index,
957 param_stride, ""), "");
958
959 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
960
961 if (!vertex_index) {
962 LLVMValueRef patch_data_offset =
963 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 patch_data_offset, "");
967 }
968 return base_addr;
969 }
970
971 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
972 struct si_shader_context *ctx,
973 const struct tgsi_full_dst_register *dst,
974 const struct tgsi_full_src_register *src)
975 {
976 struct tgsi_shader_info *info = &ctx->shader->selector->info;
977 ubyte *name, *index, *array_first;
978 struct tgsi_full_src_register reg;
979 LLVMValueRef vertex_index = NULL;
980 LLVMValueRef param_index = NULL;
981 unsigned param_index_base, param_base;
982
983 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
984
985 if (reg.Register.Dimension) {
986
987 if (reg.Dimension.Indirect)
988 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
989 1, reg.Dimension.Index);
990 else
991 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
992 }
993
994 /* Get information about the register. */
995 if (reg.Register.File == TGSI_FILE_INPUT) {
996 name = info->input_semantic_name;
997 index = info->input_semantic_index;
998 array_first = info->input_array_first;
999 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1000 name = info->output_semantic_name;
1001 index = info->output_semantic_index;
1002 array_first = info->output_array_first;
1003 } else {
1004 assert(0);
1005 return NULL;
1006 }
1007
1008 if (reg.Register.Indirect) {
1009 if (reg.Indirect.ArrayID)
1010 param_base = array_first[reg.Indirect.ArrayID];
1011 else
1012 param_base = reg.Register.Index;
1013
1014 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1015 1, reg.Register.Index - param_base);
1016
1017 } else {
1018 param_base = reg.Register.Index;
1019 param_index = ctx->i32_0;
1020 }
1021
1022 param_index_base = reg.Register.Dimension ?
1023 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
1024 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
1025
1026 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1027 LLVMConstInt(ctx->i32, param_index_base, 0),
1028 "");
1029
1030 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1031 vertex_index, param_index);
1032 }
1033
1034 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1035 enum tgsi_opcode_type type, unsigned swizzle,
1036 LLVMValueRef buffer, LLVMValueRef offset,
1037 LLVMValueRef base, bool can_speculate)
1038 {
1039 struct si_shader_context *ctx = si_shader_context(bld_base);
1040 LLVMValueRef value, value2;
1041 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
1042 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
1043
1044 if (swizzle == ~0) {
1045 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1046 0, 1, 0, can_speculate, false);
1047
1048 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1049 }
1050
1051 if (!tgsi_type_is_64bit(type)) {
1052 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1053 0, 1, 0, can_speculate, false);
1054
1055 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1056 return LLVMBuildExtractElement(ctx->ac.builder, value,
1057 LLVMConstInt(ctx->i32, swizzle, 0), "");
1058 }
1059
1060 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1061 swizzle * 4, 1, 0, can_speculate, false);
1062
1063 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1064 swizzle * 4 + 4, 1, 0, can_speculate, false);
1065
1066 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
1067 value, value2);
1068 }
1069
1070 /**
1071 * Load from LDS.
1072 *
1073 * \param type output value type
1074 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1075 * \param dw_addr address in dwords
1076 */
1077 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1078 enum tgsi_opcode_type type, unsigned swizzle,
1079 LLVMValueRef dw_addr)
1080 {
1081 struct si_shader_context *ctx = si_shader_context(bld_base);
1082 LLVMValueRef value;
1083
1084 if (swizzle == ~0) {
1085 LLVMValueRef values[TGSI_NUM_CHANNELS];
1086
1087 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1088 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1089
1090 return lp_build_gather_values(&ctx->gallivm, values,
1091 TGSI_NUM_CHANNELS);
1092 }
1093
1094 /* Split 64-bit loads. */
1095 if (tgsi_type_is_64bit(type)) {
1096 LLVMValueRef lo, hi;
1097
1098 lo = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle, dw_addr);
1099 hi = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle + 1, dw_addr);
1100 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
1101 lo, hi);
1102 }
1103
1104 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1105 LLVMConstInt(ctx->i32, swizzle, 0));
1106
1107 value = ac_lds_load(&ctx->ac, dw_addr);
1108
1109 return bitcast(bld_base, type, value);
1110 }
1111
1112 /**
1113 * Store to LDS.
1114 *
1115 * \param swizzle offset (typically 0..3)
1116 * \param dw_addr address in dwords
1117 * \param value value to store
1118 */
1119 static void lds_store(struct si_shader_context *ctx,
1120 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1121 LLVMValueRef value)
1122 {
1123 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1124 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1125
1126 ac_lds_store(&ctx->ac, dw_addr, value);
1127 }
1128
1129 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1130 unsigned param)
1131 {
1132 LLVMBuilderRef builder = ctx->ac.builder;
1133
1134 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1135 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1136 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1137
1138 uint64_t desc2 = 0xffffffff;
1139 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1140 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1141 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1142 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1143 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1144 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1145 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1146
1147 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1148 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1149 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1150 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1151 }
1152
1153 static LLVMValueRef fetch_input_tcs(
1154 struct lp_build_tgsi_context *bld_base,
1155 const struct tgsi_full_src_register *reg,
1156 enum tgsi_opcode_type type, unsigned swizzle)
1157 {
1158 struct si_shader_context *ctx = si_shader_context(bld_base);
1159 LLVMValueRef dw_addr, stride;
1160
1161 stride = get_tcs_in_vertex_dw_stride(ctx);
1162 dw_addr = get_tcs_in_current_patch_offset(ctx);
1163 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1164
1165 return lds_load(bld_base, type, swizzle, dw_addr);
1166 }
1167
1168 static LLVMValueRef fetch_output_tcs(
1169 struct lp_build_tgsi_context *bld_base,
1170 const struct tgsi_full_src_register *reg,
1171 enum tgsi_opcode_type type, unsigned swizzle)
1172 {
1173 struct si_shader_context *ctx = si_shader_context(bld_base);
1174 LLVMValueRef dw_addr, stride;
1175
1176 if (reg->Register.Dimension) {
1177 stride = get_tcs_out_vertex_dw_stride(ctx);
1178 dw_addr = get_tcs_out_current_patch_offset(ctx);
1179 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1180 } else {
1181 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1182 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1183 }
1184
1185 return lds_load(bld_base, type, swizzle, dw_addr);
1186 }
1187
1188 static LLVMValueRef fetch_input_tes(
1189 struct lp_build_tgsi_context *bld_base,
1190 const struct tgsi_full_src_register *reg,
1191 enum tgsi_opcode_type type, unsigned swizzle)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef buffer, base, addr;
1195
1196 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1197
1198 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1199 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1200
1201 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1202 }
1203
1204 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1205 const struct tgsi_full_instruction *inst,
1206 const struct tgsi_opcode_info *info,
1207 unsigned index,
1208 LLVMValueRef dst[4])
1209 {
1210 struct si_shader_context *ctx = si_shader_context(bld_base);
1211 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1212 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1213 unsigned chan_index;
1214 LLVMValueRef dw_addr, stride;
1215 LLVMValueRef buffer, base, buf_addr;
1216 LLVMValueRef values[4];
1217 bool skip_lds_store;
1218 bool is_tess_factor = false, is_tess_inner = false;
1219
1220 /* Only handle per-patch and per-vertex outputs here.
1221 * Vectors will be lowered to scalars and this function will be called again.
1222 */
1223 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1224 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1225 si_llvm_emit_store(bld_base, inst, info, index, dst);
1226 return;
1227 }
1228
1229 if (reg->Register.Dimension) {
1230 stride = get_tcs_out_vertex_dw_stride(ctx);
1231 dw_addr = get_tcs_out_current_patch_offset(ctx);
1232 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1233 skip_lds_store = !sh_info->reads_pervertex_outputs;
1234 } else {
1235 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1236 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1237 skip_lds_store = !sh_info->reads_perpatch_outputs;
1238
1239 if (!reg->Register.Indirect) {
1240 int name = sh_info->output_semantic_name[reg->Register.Index];
1241
1242 /* Always write tess factors into LDS for the TCS epilog. */
1243 if (name == TGSI_SEMANTIC_TESSINNER ||
1244 name == TGSI_SEMANTIC_TESSOUTER) {
1245 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1246 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1247 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1248 is_tess_factor = true;
1249 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1250 }
1251 }
1252 }
1253
1254 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1255
1256 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1257 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1258
1259 uint32_t writemask = reg->Register.WriteMask;
1260 while (writemask) {
1261 chan_index = u_bit_scan(&writemask);
1262 LLVMValueRef value = dst[chan_index];
1263
1264 if (inst->Instruction.Saturate)
1265 value = ac_build_clamp(&ctx->ac, value);
1266
1267 /* Skip LDS stores if there is no LDS read of this output. */
1268 if (!skip_lds_store)
1269 lds_store(ctx, chan_index, dw_addr, value);
1270
1271 value = ac_to_integer(&ctx->ac, value);
1272 values[chan_index] = value;
1273
1274 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1275 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1276 buf_addr, base,
1277 4 * chan_index, 1, 0, true, false);
1278 }
1279
1280 /* Write tess factors into VGPRs for the epilog. */
1281 if (is_tess_factor &&
1282 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1283 if (!is_tess_inner) {
1284 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1285 ctx->invoc0_tess_factors[chan_index]);
1286 } else if (chan_index < 2) {
1287 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1288 ctx->invoc0_tess_factors[4 + chan_index]);
1289 }
1290 }
1291 }
1292
1293 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1294 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1295 values, 4);
1296 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1297 base, 0, 1, 0, true, false);
1298 }
1299 }
1300
1301 static LLVMValueRef fetch_input_gs(
1302 struct lp_build_tgsi_context *bld_base,
1303 const struct tgsi_full_src_register *reg,
1304 enum tgsi_opcode_type type,
1305 unsigned swizzle)
1306 {
1307 struct si_shader_context *ctx = si_shader_context(bld_base);
1308 struct si_shader *shader = ctx->shader;
1309 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1310 LLVMValueRef vtx_offset, soffset;
1311 struct tgsi_shader_info *info = &shader->selector->info;
1312 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1313 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1314 unsigned param;
1315 LLVMValueRef value;
1316
1317 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1318 return get_primitive_id(ctx, swizzle);
1319
1320 if (!reg->Register.Dimension)
1321 return NULL;
1322
1323 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1324
1325 /* GFX9 has the ESGS ring in LDS. */
1326 if (ctx->screen->info.chip_class >= GFX9) {
1327 unsigned index = reg->Dimension.Index;
1328
1329 switch (index / 2) {
1330 case 0:
1331 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1332 index % 2 ? 16 : 0, 16);
1333 break;
1334 case 1:
1335 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1336 index % 2 ? 16 : 0, 16);
1337 break;
1338 case 2:
1339 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1340 index % 2 ? 16 : 0, 16);
1341 break;
1342 default:
1343 assert(0);
1344 return NULL;
1345 }
1346
1347 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1348 LLVMConstInt(ctx->i32, param * 4, 0), "");
1349 return lds_load(bld_base, type, swizzle, vtx_offset);
1350 }
1351
1352 /* GFX6: input load from the ESGS ring in memory. */
1353 if (swizzle == ~0) {
1354 LLVMValueRef values[TGSI_NUM_CHANNELS];
1355 unsigned chan;
1356 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1357 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1358 }
1359 return lp_build_gather_values(&ctx->gallivm, values,
1360 TGSI_NUM_CHANNELS);
1361 }
1362
1363 /* Get the vertex offset parameter on GFX6. */
1364 unsigned vtx_offset_param = reg->Dimension.Index;
1365 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1366
1367 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1368
1369 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1370
1371 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1372 vtx_offset, soffset, 0, 1, 0, true, false);
1373 if (tgsi_type_is_64bit(type)) {
1374 LLVMValueRef value2;
1375 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1376
1377 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1378 ctx->i32_0, vtx_offset, soffset,
1379 0, 1, 0, true, false);
1380 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
1381 value, value2);
1382 }
1383 return bitcast(bld_base, type, value);
1384 }
1385
1386 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1387 {
1388 switch (interpolate) {
1389 case TGSI_INTERPOLATE_CONSTANT:
1390 return 0;
1391
1392 case TGSI_INTERPOLATE_LINEAR:
1393 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1394 return SI_PARAM_LINEAR_SAMPLE;
1395 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1396 return SI_PARAM_LINEAR_CENTROID;
1397 else
1398 return SI_PARAM_LINEAR_CENTER;
1399 break;
1400 case TGSI_INTERPOLATE_COLOR:
1401 case TGSI_INTERPOLATE_PERSPECTIVE:
1402 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1403 return SI_PARAM_PERSP_SAMPLE;
1404 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1405 return SI_PARAM_PERSP_CENTROID;
1406 else
1407 return SI_PARAM_PERSP_CENTER;
1408 break;
1409 default:
1410 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1411 return -1;
1412 }
1413 }
1414
1415 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1416 unsigned attr_index, unsigned chan,
1417 LLVMValueRef prim_mask,
1418 LLVMValueRef i, LLVMValueRef j)
1419 {
1420 if (i || j) {
1421 return ac_build_fs_interp(&ctx->ac,
1422 LLVMConstInt(ctx->i32, chan, 0),
1423 LLVMConstInt(ctx->i32, attr_index, 0),
1424 prim_mask, i, j);
1425 }
1426 return ac_build_fs_interp_mov(&ctx->ac,
1427 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1428 LLVMConstInt(ctx->i32, chan, 0),
1429 LLVMConstInt(ctx->i32, attr_index, 0),
1430 prim_mask);
1431 }
1432
1433 /**
1434 * Interpolate a fragment shader input.
1435 *
1436 * @param ctx context
1437 * @param input_index index of the input in hardware
1438 * @param semantic_name TGSI_SEMANTIC_*
1439 * @param semantic_index semantic index
1440 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1441 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1442 * @param interp_param interpolation weights (i,j)
1443 * @param prim_mask SI_PARAM_PRIM_MASK
1444 * @param face SI_PARAM_FRONT_FACE
1445 * @param result the return value (4 components)
1446 */
1447 static void interp_fs_input(struct si_shader_context *ctx,
1448 unsigned input_index,
1449 unsigned semantic_name,
1450 unsigned semantic_index,
1451 unsigned num_interp_inputs,
1452 unsigned colors_read_mask,
1453 LLVMValueRef interp_param,
1454 LLVMValueRef prim_mask,
1455 LLVMValueRef face,
1456 LLVMValueRef result[4])
1457 {
1458 LLVMValueRef i = NULL, j = NULL;
1459 unsigned chan;
1460
1461 /* fs.constant returns the param from the middle vertex, so it's not
1462 * really useful for flat shading. It's meant to be used for custom
1463 * interpolation (but the intrinsic can't fetch from the other two
1464 * vertices).
1465 *
1466 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1467 * to do the right thing. The only reason we use fs.constant is that
1468 * fs.interp cannot be used on integers, because they can be equal
1469 * to NaN.
1470 *
1471 * When interp is false we will use fs.constant or for newer llvm,
1472 * amdgcn.interp.mov.
1473 */
1474 bool interp = interp_param != NULL;
1475
1476 if (interp) {
1477 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1478 LLVMVectorType(ctx->f32, 2), "");
1479
1480 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1481 ctx->i32_0, "");
1482 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1483 ctx->i32_1, "");
1484 }
1485
1486 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1487 ctx->shader->key.part.ps.prolog.color_two_side) {
1488 LLVMValueRef is_face_positive;
1489
1490 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1491 * otherwise it's at offset "num_inputs".
1492 */
1493 unsigned back_attr_offset = num_interp_inputs;
1494 if (semantic_index == 1 && colors_read_mask & 0xf)
1495 back_attr_offset += 1;
1496
1497 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1498 face, ctx->i32_0, "");
1499
1500 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1501 LLVMValueRef front, back;
1502
1503 front = si_build_fs_interp(ctx,
1504 input_index, chan,
1505 prim_mask, i, j);
1506 back = si_build_fs_interp(ctx,
1507 back_attr_offset, chan,
1508 prim_mask, i, j);
1509
1510 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1511 is_face_positive,
1512 front,
1513 back,
1514 "");
1515 }
1516 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1517 result[0] = si_build_fs_interp(ctx, input_index,
1518 0, prim_mask, i, j);
1519 result[1] =
1520 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1521 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1522 } else {
1523 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1524 result[chan] = si_build_fs_interp(ctx,
1525 input_index, chan,
1526 prim_mask, i, j);
1527 }
1528 }
1529 }
1530
1531 void si_llvm_load_input_fs(
1532 struct si_shader_context *ctx,
1533 unsigned input_index,
1534 LLVMValueRef out[4])
1535 {
1536 struct lp_build_context *base = &ctx->bld_base.base;
1537 struct si_shader *shader = ctx->shader;
1538 struct tgsi_shader_info *info = &shader->selector->info;
1539 LLVMValueRef main_fn = ctx->main_fn;
1540 LLVMValueRef interp_param = NULL;
1541 int interp_param_idx;
1542 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1543 unsigned semantic_index = info->input_semantic_index[input_index];
1544 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1545 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1546
1547 /* Get colors from input VGPRs (set by the prolog). */
1548 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1549 unsigned colors_read = shader->selector->info.colors_read;
1550 unsigned mask = colors_read >> (semantic_index * 4);
1551 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1552 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1553
1554 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1555 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1556 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1557 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1558 return;
1559 }
1560
1561 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1562 if (interp_param_idx == -1)
1563 return;
1564 else if (interp_param_idx) {
1565 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1566 }
1567
1568 interp_fs_input(ctx, input_index, semantic_name,
1569 semantic_index, 0, /* this param is unused */
1570 shader->selector->info.colors_read, interp_param,
1571 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1572 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1573 &out[0]);
1574 }
1575
1576 static void declare_input_fs(
1577 struct si_shader_context *ctx,
1578 unsigned input_index,
1579 const struct tgsi_full_declaration *decl,
1580 LLVMValueRef out[4])
1581 {
1582 si_llvm_load_input_fs(ctx, input_index, out);
1583 }
1584
1585 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1586 {
1587 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1588 }
1589
1590
1591 /**
1592 * Load a dword from a constant buffer.
1593 */
1594 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1595 LLVMValueRef resource,
1596 LLVMValueRef offset)
1597 {
1598 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1599 0, 0, 0, true, true);
1600 }
1601
1602 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1603 {
1604 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1605 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1606 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1607 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1608
1609 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1610 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1611 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1612
1613 LLVMValueRef pos[4] = {
1614 buffer_load_const(ctx, resource, offset0),
1615 buffer_load_const(ctx, resource, offset1),
1616 LLVMConstReal(ctx->f32, 0),
1617 LLVMConstReal(ctx->f32, 0)
1618 };
1619
1620 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1621 }
1622
1623 void si_load_system_value(struct si_shader_context *ctx,
1624 unsigned index,
1625 const struct tgsi_full_declaration *decl)
1626 {
1627 struct lp_build_context *bld = &ctx->bld_base.base;
1628 LLVMValueRef value = 0;
1629
1630 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1631
1632 switch (decl->Semantic.Name) {
1633 case TGSI_SEMANTIC_INSTANCEID:
1634 value = ctx->abi.instance_id;
1635 break;
1636
1637 case TGSI_SEMANTIC_VERTEXID:
1638 value = LLVMBuildAdd(ctx->ac.builder,
1639 ctx->abi.vertex_id,
1640 ctx->abi.base_vertex, "");
1641 break;
1642
1643 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1644 /* Unused. Clarify the meaning in indexed vs. non-indexed
1645 * draws if this is ever used again. */
1646 assert(false);
1647 break;
1648
1649 case TGSI_SEMANTIC_BASEVERTEX:
1650 {
1651 /* For non-indexed draws, the base vertex set by the driver
1652 * (for direct draws) or the CP (for indirect draws) is the
1653 * first vertex ID, but GLSL expects 0 to be returned.
1654 */
1655 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1656 LLVMValueRef indexed;
1657
1658 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1659 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1660
1661 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1662 ctx->abi.base_vertex, ctx->i32_0, "");
1663 break;
1664 }
1665
1666 case TGSI_SEMANTIC_BASEINSTANCE:
1667 value = ctx->abi.start_instance;
1668 break;
1669
1670 case TGSI_SEMANTIC_DRAWID:
1671 value = ctx->abi.draw_id;
1672 break;
1673
1674 case TGSI_SEMANTIC_INVOCATIONID:
1675 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1676 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1677 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1678 value = ctx->abi.gs_invocation_id;
1679 else
1680 assert(!"INVOCATIONID not implemented");
1681 break;
1682
1683 case TGSI_SEMANTIC_POSITION:
1684 {
1685 LLVMValueRef pos[4] = {
1686 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1687 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1688 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1689 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1690 LLVMGetParam(ctx->main_fn,
1691 SI_PARAM_POS_W_FLOAT)),
1692 };
1693 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1694 break;
1695 }
1696
1697 case TGSI_SEMANTIC_FACE:
1698 value = ctx->abi.front_face;
1699 break;
1700
1701 case TGSI_SEMANTIC_SAMPLEID:
1702 value = get_sample_id(ctx);
1703 break;
1704
1705 case TGSI_SEMANTIC_SAMPLEPOS: {
1706 LLVMValueRef pos[4] = {
1707 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1708 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1709 LLVMConstReal(ctx->f32, 0),
1710 LLVMConstReal(ctx->f32, 0)
1711 };
1712 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1713 TGSI_OPCODE_FRC, pos[0]);
1714 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1715 TGSI_OPCODE_FRC, pos[1]);
1716 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1717 break;
1718 }
1719
1720 case TGSI_SEMANTIC_SAMPLEMASK:
1721 /* This can only occur with the OpenGL Core profile, which
1722 * doesn't support smoothing.
1723 */
1724 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1725 break;
1726
1727 case TGSI_SEMANTIC_TESSCOORD:
1728 {
1729 LLVMValueRef coord[4] = {
1730 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1731 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1732 ctx->ac.f32_0,
1733 ctx->ac.f32_0
1734 };
1735
1736 /* For triangles, the vector should be (u, v, 1-u-v). */
1737 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1738 PIPE_PRIM_TRIANGLES)
1739 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1740 lp_build_add(bld, coord[0], coord[1]));
1741
1742 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1743 break;
1744 }
1745
1746 case TGSI_SEMANTIC_VERTICESIN:
1747 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1748 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1749 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1750 value = get_num_tcs_out_vertices(ctx);
1751 else
1752 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1753 break;
1754
1755 case TGSI_SEMANTIC_TESSINNER:
1756 case TGSI_SEMANTIC_TESSOUTER:
1757 {
1758 LLVMValueRef buffer, base, addr;
1759 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1760
1761 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1762
1763 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1764 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1765 LLVMConstInt(ctx->i32, param, 0));
1766
1767 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1768 ~0, buffer, base, addr, true);
1769
1770 break;
1771 }
1772
1773 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1774 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1775 {
1776 LLVMValueRef buf, slot, val[4];
1777 int i, offset;
1778
1779 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1780 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1781 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1782 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1783
1784 for (i = 0; i < 4; i++)
1785 val[i] = buffer_load_const(ctx, buf,
1786 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1787 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1788 break;
1789 }
1790
1791 case TGSI_SEMANTIC_PRIMID:
1792 value = get_primitive_id(ctx, 0);
1793 break;
1794
1795 case TGSI_SEMANTIC_GRID_SIZE:
1796 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1797 break;
1798
1799 case TGSI_SEMANTIC_BLOCK_SIZE:
1800 {
1801 LLVMValueRef values[3];
1802 unsigned i;
1803 unsigned *properties = ctx->shader->selector->info.properties;
1804
1805 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1806 unsigned sizes[3] = {
1807 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1808 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1809 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1810 };
1811
1812 for (i = 0; i < 3; ++i)
1813 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1814
1815 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1816 } else {
1817 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1818 }
1819 break;
1820 }
1821
1822 case TGSI_SEMANTIC_BLOCK_ID:
1823 {
1824 LLVMValueRef values[3];
1825
1826 for (int i = 0; i < 3; i++) {
1827 values[i] = ctx->i32_0;
1828 if (ctx->param_block_id[i] >= 0) {
1829 values[i] = LLVMGetParam(ctx->main_fn,
1830 ctx->param_block_id[i]);
1831 }
1832 }
1833 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1834 break;
1835 }
1836
1837 case TGSI_SEMANTIC_THREAD_ID:
1838 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1839 break;
1840
1841 case TGSI_SEMANTIC_HELPER_INVOCATION:
1842 value = lp_build_intrinsic(ctx->ac.builder,
1843 "llvm.amdgcn.ps.live",
1844 ctx->i1, NULL, 0,
1845 LP_FUNC_ATTR_READNONE);
1846 value = LLVMBuildNot(ctx->ac.builder, value, "");
1847 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1848 break;
1849
1850 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1851 value = LLVMConstInt(ctx->i32, 64, 0);
1852 break;
1853
1854 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1855 value = ac_get_thread_id(&ctx->ac);
1856 break;
1857
1858 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1859 {
1860 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1861 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1862 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1863 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1864 break;
1865 }
1866
1867 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1868 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1869 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1870 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1871 {
1872 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1873 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1874 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1875 /* All bits set except LSB */
1876 value = LLVMConstInt(ctx->i64, -2, 0);
1877 } else {
1878 /* All bits set */
1879 value = LLVMConstInt(ctx->i64, -1, 0);
1880 }
1881 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1882 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1883 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1884 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1885 value = LLVMBuildNot(ctx->ac.builder, value, "");
1886 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1887 break;
1888 }
1889
1890 default:
1891 assert(!"unknown system value");
1892 return;
1893 }
1894
1895 ctx->system_values[index] = value;
1896 }
1897
1898 void si_declare_compute_memory(struct si_shader_context *ctx,
1899 const struct tgsi_full_declaration *decl)
1900 {
1901 struct si_shader_selector *sel = ctx->shader->selector;
1902
1903 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1904 LLVMValueRef var;
1905
1906 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1907 assert(decl->Range.First == decl->Range.Last);
1908 assert(!ctx->ac.lds);
1909
1910 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1911 LLVMArrayType(ctx->i8, sel->local_size),
1912 "compute_lds",
1913 LOCAL_ADDR_SPACE);
1914 LLVMSetAlignment(var, 4);
1915
1916 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1917 }
1918
1919 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1920 {
1921 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1922 ctx->param_const_and_shader_buffers);
1923
1924 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1925 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1926 }
1927
1928 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1929 {
1930 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1931 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1932
1933 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1934 index = LLVMBuildAdd(ctx->ac.builder, index,
1935 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1936
1937 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1938 }
1939
1940 static LLVMValueRef
1941 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1942 {
1943 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1944 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1945 ctx->param_const_and_shader_buffers);
1946
1947 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1948 index = LLVMBuildSub(ctx->ac.builder,
1949 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1950 index, "");
1951
1952 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1953 }
1954
1955 static LLVMValueRef fetch_constant(
1956 struct lp_build_tgsi_context *bld_base,
1957 const struct tgsi_full_src_register *reg,
1958 enum tgsi_opcode_type type,
1959 unsigned swizzle)
1960 {
1961 struct si_shader_context *ctx = si_shader_context(bld_base);
1962 struct si_shader_selector *sel = ctx->shader->selector;
1963 const struct tgsi_ind_register *ireg = &reg->Indirect;
1964 unsigned buf, idx;
1965
1966 LLVMValueRef addr, bufp;
1967
1968 if (swizzle == LP_CHAN_ALL) {
1969 unsigned chan;
1970 LLVMValueRef values[4];
1971 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1972 values[chan] = fetch_constant(bld_base, reg, type, chan);
1973
1974 return lp_build_gather_values(&ctx->gallivm, values, 4);
1975 }
1976
1977 /* Split 64-bit loads. */
1978 if (tgsi_type_is_64bit(type)) {
1979 LLVMValueRef lo, hi;
1980
1981 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
1982 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
1983 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
1984 lo, hi);
1985 }
1986
1987 idx = reg->Register.Index * 4 + swizzle;
1988 if (reg->Register.Indirect) {
1989 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
1990 } else {
1991 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1992 }
1993
1994 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
1995 if (sel->info.const_buffers_declared == 1 &&
1996 sel->info.shader_buffers_declared == 0) {
1997 LLVMValueRef ptr =
1998 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1999
2000 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2001 * loads, and up to x4 load opcode merging. However, it leads to horrible
2002 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2003 *
2004 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2005 *
2006 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2007 * a descriptor and s_buffer_load_dword using it, so we can't expand
2008 * the pointer into a full descriptor like below. We have to use
2009 * s_load_dword instead. The only case when LLVM 5.0 would select
2010 * s_buffer_load_dword (that we have to prevent) is when we use use
2011 * a literal offset where we don't need bounds checking.
2012 */
2013 if (ctx->screen->info.chip_class == SI &&
2014 HAVE_LLVM < 0x0600 &&
2015 !reg->Register.Indirect) {
2016 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2017 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2018 return bitcast(bld_base, type, result);
2019 }
2020
2021 /* Do the bounds checking with a descriptor, because
2022 * doing computation and manual bounds checking of 64-bit
2023 * addresses generates horrible VALU code with very high
2024 * VGPR usage and very low SIMD occupancy.
2025 */
2026 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2027 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2028
2029 LLVMValueRef desc_elems[] = {
2030 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2031 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2032 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2033 LLVMConstInt(ctx->i32,
2034 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2035 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2036 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2037 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2038 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2039 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2040 };
2041 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2042 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2043 return bitcast(bld_base, type, result);
2044 }
2045
2046 assert(reg->Register.Dimension);
2047 buf = reg->Dimension.Index;
2048
2049 if (reg->Dimension.Indirect) {
2050 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2051 LLVMValueRef index;
2052 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2053 reg->Dimension.Index,
2054 ctx->num_const_buffers);
2055 index = LLVMBuildAdd(ctx->ac.builder, index,
2056 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2057 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2058 } else
2059 bufp = load_const_buffer_desc(ctx, buf);
2060
2061 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2062 }
2063
2064 /* Upper 16 bits must be zero. */
2065 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2066 LLVMValueRef val[2])
2067 {
2068 return LLVMBuildOr(ctx->ac.builder, val[0],
2069 LLVMBuildShl(ctx->ac.builder, val[1],
2070 LLVMConstInt(ctx->i32, 16, 0),
2071 ""), "");
2072 }
2073
2074 /* Upper 16 bits are ignored and will be dropped. */
2075 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2076 LLVMValueRef val[2])
2077 {
2078 LLVMValueRef v[2] = {
2079 LLVMBuildAnd(ctx->ac.builder, val[0],
2080 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2081 val[1],
2082 };
2083 return si_llvm_pack_two_int16(ctx, v);
2084 }
2085
2086 /* Initialize arguments for the shader export intrinsic */
2087 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2088 LLVMValueRef *values,
2089 unsigned target,
2090 struct ac_export_args *args)
2091 {
2092 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2093 LLVMBuilderRef builder = ctx->ac.builder;
2094 LLVMValueRef val[4];
2095 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2096 unsigned chan;
2097 bool is_int8, is_int10;
2098
2099 /* Default is 0xf. Adjusted below depending on the format. */
2100 args->enabled_channels = 0xf; /* writemask */
2101
2102 /* Specify whether the EXEC mask represents the valid mask */
2103 args->valid_mask = 0;
2104
2105 /* Specify whether this is the last export */
2106 args->done = 0;
2107
2108 /* Specify the target we are exporting */
2109 args->target = target;
2110
2111 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2112 const struct si_shader_key *key = &ctx->shader->key;
2113 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2114 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2115
2116 assert(cbuf >= 0 && cbuf < 8);
2117 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2118 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2119 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2120 }
2121
2122 args->compr = false;
2123 args->out[0] = f32undef;
2124 args->out[1] = f32undef;
2125 args->out[2] = f32undef;
2126 args->out[3] = f32undef;
2127
2128 switch (spi_shader_col_format) {
2129 case V_028714_SPI_SHADER_ZERO:
2130 args->enabled_channels = 0; /* writemask */
2131 args->target = V_008DFC_SQ_EXP_NULL;
2132 break;
2133
2134 case V_028714_SPI_SHADER_32_R:
2135 args->enabled_channels = 1; /* writemask */
2136 args->out[0] = values[0];
2137 break;
2138
2139 case V_028714_SPI_SHADER_32_GR:
2140 args->enabled_channels = 0x3; /* writemask */
2141 args->out[0] = values[0];
2142 args->out[1] = values[1];
2143 break;
2144
2145 case V_028714_SPI_SHADER_32_AR:
2146 args->enabled_channels = 0x9; /* writemask */
2147 args->out[0] = values[0];
2148 args->out[3] = values[3];
2149 break;
2150
2151 case V_028714_SPI_SHADER_FP16_ABGR:
2152 args->compr = 1; /* COMPR flag */
2153
2154 for (chan = 0; chan < 2; chan++) {
2155 LLVMValueRef pack_args[2] = {
2156 values[2 * chan],
2157 values[2 * chan + 1]
2158 };
2159 LLVMValueRef packed;
2160
2161 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2162 args->out[chan] = ac_to_float(&ctx->ac, packed);
2163 }
2164 break;
2165
2166 case V_028714_SPI_SHADER_UNORM16_ABGR:
2167 for (chan = 0; chan < 4; chan++) {
2168 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2169 val[chan] = LLVMBuildFMul(builder, val[chan],
2170 LLVMConstReal(ctx->f32, 65535), "");
2171 val[chan] = LLVMBuildFAdd(builder, val[chan],
2172 LLVMConstReal(ctx->f32, 0.5), "");
2173 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2174 ctx->i32, "");
2175 }
2176
2177 args->compr = 1; /* COMPR flag */
2178 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2179 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2180 break;
2181
2182 case V_028714_SPI_SHADER_SNORM16_ABGR:
2183 for (chan = 0; chan < 4; chan++) {
2184 /* Clamp between [-1, 1]. */
2185 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2186 values[chan],
2187 LLVMConstReal(ctx->f32, 1));
2188 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2189 val[chan],
2190 LLVMConstReal(ctx->f32, -1));
2191 /* Convert to a signed integer in [-32767, 32767]. */
2192 val[chan] = LLVMBuildFMul(builder, val[chan],
2193 LLVMConstReal(ctx->f32, 32767), "");
2194 /* If positive, add 0.5, else add -0.5. */
2195 val[chan] = LLVMBuildFAdd(builder, val[chan],
2196 LLVMBuildSelect(builder,
2197 LLVMBuildFCmp(builder, LLVMRealOGE,
2198 val[chan], ctx->ac.f32_0, ""),
2199 LLVMConstReal(ctx->f32, 0.5),
2200 LLVMConstReal(ctx->f32, -0.5), ""), "");
2201 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2202 }
2203
2204 args->compr = 1; /* COMPR flag */
2205 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2206 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2207 break;
2208
2209 case V_028714_SPI_SHADER_UINT16_ABGR: {
2210 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2211 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2212 LLVMValueRef max_alpha =
2213 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2214
2215 /* Clamp. */
2216 for (chan = 0; chan < 4; chan++) {
2217 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2218 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2219 val[chan],
2220 chan == 3 ? max_alpha : max_rgb);
2221 }
2222
2223 args->compr = 1; /* COMPR flag */
2224 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2225 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2226 break;
2227 }
2228
2229 case V_028714_SPI_SHADER_SINT16_ABGR: {
2230 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2231 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2232 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2233 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2234 LLVMValueRef max_alpha =
2235 !is_int10 ? max_rgb : ctx->i32_1;
2236 LLVMValueRef min_alpha =
2237 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2238
2239 /* Clamp. */
2240 for (chan = 0; chan < 4; chan++) {
2241 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2242 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2243 TGSI_OPCODE_IMIN,
2244 val[chan], chan == 3 ? max_alpha : max_rgb);
2245 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2246 TGSI_OPCODE_IMAX,
2247 val[chan], chan == 3 ? min_alpha : min_rgb);
2248 }
2249
2250 args->compr = 1; /* COMPR flag */
2251 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2252 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2253 break;
2254 }
2255
2256 case V_028714_SPI_SHADER_32_ABGR:
2257 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2258 break;
2259 }
2260 }
2261
2262 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2263 LLVMValueRef alpha)
2264 {
2265 struct si_shader_context *ctx = si_shader_context(bld_base);
2266
2267 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2268 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2269 [PIPE_FUNC_LESS] = LLVMRealOLT,
2270 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2271 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2272 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2273 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2274 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2275 };
2276 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2277 assert(cond);
2278
2279 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2280 SI_PARAM_ALPHA_REF);
2281 LLVMValueRef alpha_pass =
2282 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2283 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2284 } else {
2285 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2286 }
2287 }
2288
2289 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2290 LLVMValueRef alpha,
2291 unsigned samplemask_param)
2292 {
2293 struct si_shader_context *ctx = si_shader_context(bld_base);
2294 LLVMValueRef coverage;
2295
2296 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2297 coverage = LLVMGetParam(ctx->main_fn,
2298 samplemask_param);
2299 coverage = ac_to_integer(&ctx->ac, coverage);
2300
2301 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2302 ctx->i32,
2303 &coverage, 1, LP_FUNC_ATTR_READNONE);
2304
2305 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2306 ctx->f32, "");
2307
2308 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2309 LLVMConstReal(ctx->f32,
2310 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2311
2312 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2313 }
2314
2315 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2316 struct ac_export_args *pos, LLVMValueRef *out_elts)
2317 {
2318 unsigned reg_index;
2319 unsigned chan;
2320 unsigned const_chan;
2321 LLVMValueRef base_elt;
2322 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2323 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2324 SI_VS_CONST_CLIP_PLANES, 0);
2325 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2326
2327 for (reg_index = 0; reg_index < 2; reg_index ++) {
2328 struct ac_export_args *args = &pos[2 + reg_index];
2329
2330 args->out[0] =
2331 args->out[1] =
2332 args->out[2] =
2333 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2334
2335 /* Compute dot products of position and user clip plane vectors */
2336 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2337 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2338 LLVMValueRef addr =
2339 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2340 const_chan) * 4, 0);
2341 base_elt = buffer_load_const(ctx, const_resource,
2342 addr);
2343 args->out[chan] =
2344 lp_build_add(&ctx->bld_base.base, args->out[chan],
2345 lp_build_mul(&ctx->bld_base.base, base_elt,
2346 out_elts[const_chan]));
2347 }
2348 }
2349
2350 args->enabled_channels = 0xf;
2351 args->valid_mask = 0;
2352 args->done = 0;
2353 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2354 args->compr = 0;
2355 }
2356 }
2357
2358 static void si_dump_streamout(struct pipe_stream_output_info *so)
2359 {
2360 unsigned i;
2361
2362 if (so->num_outputs)
2363 fprintf(stderr, "STREAMOUT\n");
2364
2365 for (i = 0; i < so->num_outputs; i++) {
2366 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2367 so->output[i].start_component;
2368 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2369 i, so->output[i].output_buffer,
2370 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2371 so->output[i].register_index,
2372 mask & 1 ? "x" : "",
2373 mask & 2 ? "y" : "",
2374 mask & 4 ? "z" : "",
2375 mask & 8 ? "w" : "");
2376 }
2377 }
2378
2379 static void emit_streamout_output(struct si_shader_context *ctx,
2380 LLVMValueRef const *so_buffers,
2381 LLVMValueRef const *so_write_offsets,
2382 struct pipe_stream_output *stream_out,
2383 struct si_shader_output_values *shader_out)
2384 {
2385 unsigned buf_idx = stream_out->output_buffer;
2386 unsigned start = stream_out->start_component;
2387 unsigned num_comps = stream_out->num_components;
2388 LLVMValueRef out[4];
2389
2390 assert(num_comps && num_comps <= 4);
2391 if (!num_comps || num_comps > 4)
2392 return;
2393
2394 /* Load the output as int. */
2395 for (int j = 0; j < num_comps; j++) {
2396 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2397
2398 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2399 }
2400
2401 /* Pack the output. */
2402 LLVMValueRef vdata = NULL;
2403
2404 switch (num_comps) {
2405 case 1: /* as i32 */
2406 vdata = out[0];
2407 break;
2408 case 2: /* as v2i32 */
2409 case 3: /* as v4i32 (aligned to 4) */
2410 case 4: /* as v4i32 */
2411 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2412 for (int j = 0; j < num_comps; j++) {
2413 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2414 LLVMConstInt(ctx->i32, j, 0), "");
2415 }
2416 break;
2417 }
2418
2419 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2420 vdata, num_comps,
2421 so_write_offsets[buf_idx],
2422 ctx->i32_0,
2423 stream_out->dst_offset * 4, 1, 1, true, false);
2424 }
2425
2426 /**
2427 * Write streamout data to buffers for vertex stream @p stream (different
2428 * vertex streams can occur for GS copy shaders).
2429 */
2430 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2431 struct si_shader_output_values *outputs,
2432 unsigned noutput, unsigned stream)
2433 {
2434 struct si_shader_selector *sel = ctx->shader->selector;
2435 struct pipe_stream_output_info *so = &sel->so;
2436 LLVMBuilderRef builder = ctx->ac.builder;
2437 int i;
2438 struct lp_build_if_state if_ctx;
2439
2440 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2441 LLVMValueRef so_vtx_count =
2442 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2443
2444 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2445
2446 /* can_emit = tid < so_vtx_count; */
2447 LLVMValueRef can_emit =
2448 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2449
2450 /* Emit the streamout code conditionally. This actually avoids
2451 * out-of-bounds buffer access. The hw tells us via the SGPR
2452 * (so_vtx_count) which threads are allowed to emit streamout data. */
2453 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2454 {
2455 /* The buffer offset is computed as follows:
2456 * ByteOffset = streamout_offset[buffer_id]*4 +
2457 * (streamout_write_index + thread_id)*stride[buffer_id] +
2458 * attrib_offset
2459 */
2460
2461 LLVMValueRef so_write_index =
2462 LLVMGetParam(ctx->main_fn,
2463 ctx->param_streamout_write_index);
2464
2465 /* Compute (streamout_write_index + thread_id). */
2466 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2467
2468 /* Load the descriptor and compute the write offset for each
2469 * enabled buffer. */
2470 LLVMValueRef so_write_offset[4] = {};
2471 LLVMValueRef so_buffers[4];
2472 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2473 ctx->param_rw_buffers);
2474
2475 for (i = 0; i < 4; i++) {
2476 if (!so->stride[i])
2477 continue;
2478
2479 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2480 SI_VS_STREAMOUT_BUF0 + i, 0);
2481
2482 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2483
2484 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2485 ctx->param_streamout_offset[i]);
2486 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2487
2488 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2489 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2490 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2491 }
2492
2493 /* Write streamout data. */
2494 for (i = 0; i < so->num_outputs; i++) {
2495 unsigned reg = so->output[i].register_index;
2496
2497 if (reg >= noutput)
2498 continue;
2499
2500 if (stream != so->output[i].stream)
2501 continue;
2502
2503 emit_streamout_output(ctx, so_buffers, so_write_offset,
2504 &so->output[i], &outputs[reg]);
2505 }
2506 }
2507 lp_build_endif(&if_ctx);
2508 }
2509
2510 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2511 LLVMValueRef *values)
2512 {
2513 struct ac_export_args args;
2514
2515 si_llvm_init_export_args(ctx, values,
2516 V_008DFC_SQ_EXP_PARAM + index, &args);
2517 ac_build_export(&ctx->ac, &args);
2518 }
2519
2520 static void si_build_param_exports(struct si_shader_context *ctx,
2521 struct si_shader_output_values *outputs,
2522 unsigned noutput)
2523 {
2524 struct si_shader *shader = ctx->shader;
2525 unsigned param_count = 0;
2526
2527 for (unsigned i = 0; i < noutput; i++) {
2528 unsigned semantic_name = outputs[i].semantic_name;
2529 unsigned semantic_index = outputs[i].semantic_index;
2530
2531 if (outputs[i].vertex_stream[0] != 0 &&
2532 outputs[i].vertex_stream[1] != 0 &&
2533 outputs[i].vertex_stream[2] != 0 &&
2534 outputs[i].vertex_stream[3] != 0)
2535 continue;
2536
2537 switch (semantic_name) {
2538 case TGSI_SEMANTIC_LAYER:
2539 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2540 case TGSI_SEMANTIC_CLIPDIST:
2541 case TGSI_SEMANTIC_COLOR:
2542 case TGSI_SEMANTIC_BCOLOR:
2543 case TGSI_SEMANTIC_PRIMID:
2544 case TGSI_SEMANTIC_FOG:
2545 case TGSI_SEMANTIC_TEXCOORD:
2546 case TGSI_SEMANTIC_GENERIC:
2547 break;
2548 default:
2549 continue;
2550 }
2551
2552 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2553 semantic_index < SI_MAX_IO_GENERIC) &&
2554 shader->key.opt.kill_outputs &
2555 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2556 continue;
2557
2558 si_export_param(ctx, param_count, outputs[i].values);
2559
2560 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2561 shader->info.vs_output_param_offset[i] = param_count++;
2562 }
2563
2564 shader->info.nr_param_exports = param_count;
2565 }
2566
2567 /* Generate export instructions for hardware VS shader stage */
2568 static void si_llvm_export_vs(struct si_shader_context *ctx,
2569 struct si_shader_output_values *outputs,
2570 unsigned noutput)
2571 {
2572 struct si_shader *shader = ctx->shader;
2573 struct ac_export_args pos_args[4] = {};
2574 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2575 unsigned pos_idx;
2576 int i;
2577
2578 /* Build position exports. */
2579 for (i = 0; i < noutput; i++) {
2580 switch (outputs[i].semantic_name) {
2581 case TGSI_SEMANTIC_POSITION:
2582 si_llvm_init_export_args(ctx, outputs[i].values,
2583 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2584 break;
2585 case TGSI_SEMANTIC_PSIZE:
2586 psize_value = outputs[i].values[0];
2587 break;
2588 case TGSI_SEMANTIC_LAYER:
2589 layer_value = outputs[i].values[0];
2590 break;
2591 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2592 viewport_index_value = outputs[i].values[0];
2593 break;
2594 case TGSI_SEMANTIC_EDGEFLAG:
2595 edgeflag_value = outputs[i].values[0];
2596 break;
2597 case TGSI_SEMANTIC_CLIPDIST:
2598 if (!shader->key.opt.clip_disable) {
2599 unsigned index = 2 + outputs[i].semantic_index;
2600 si_llvm_init_export_args(ctx, outputs[i].values,
2601 V_008DFC_SQ_EXP_POS + index,
2602 &pos_args[index]);
2603 }
2604 break;
2605 case TGSI_SEMANTIC_CLIPVERTEX:
2606 if (!shader->key.opt.clip_disable) {
2607 si_llvm_emit_clipvertex(ctx, pos_args,
2608 outputs[i].values);
2609 }
2610 break;
2611 }
2612 }
2613
2614 /* We need to add the position output manually if it's missing. */
2615 if (!pos_args[0].out[0]) {
2616 pos_args[0].enabled_channels = 0xf; /* writemask */
2617 pos_args[0].valid_mask = 0; /* EXEC mask */
2618 pos_args[0].done = 0; /* last export? */
2619 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2620 pos_args[0].compr = 0; /* COMPR flag */
2621 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2622 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2623 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2624 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2625 }
2626
2627 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2628 if (shader->selector->info.writes_psize ||
2629 shader->selector->info.writes_edgeflag ||
2630 shader->selector->info.writes_viewport_index ||
2631 shader->selector->info.writes_layer) {
2632 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2633 (shader->selector->info.writes_edgeflag << 1) |
2634 (shader->selector->info.writes_layer << 2);
2635
2636 pos_args[1].valid_mask = 0; /* EXEC mask */
2637 pos_args[1].done = 0; /* last export? */
2638 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2639 pos_args[1].compr = 0; /* COMPR flag */
2640 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2641 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2642 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2643 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2644
2645 if (shader->selector->info.writes_psize)
2646 pos_args[1].out[0] = psize_value;
2647
2648 if (shader->selector->info.writes_edgeflag) {
2649 /* The output is a float, but the hw expects an integer
2650 * with the first bit containing the edge flag. */
2651 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2652 edgeflag_value,
2653 ctx->i32, "");
2654 edgeflag_value = ac_build_umin(&ctx->ac,
2655 edgeflag_value,
2656 ctx->i32_1);
2657
2658 /* The LLVM intrinsic expects a float. */
2659 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2660 }
2661
2662 if (ctx->screen->info.chip_class >= GFX9) {
2663 /* GFX9 has the layer in out.z[10:0] and the viewport
2664 * index in out.z[19:16].
2665 */
2666 if (shader->selector->info.writes_layer)
2667 pos_args[1].out[2] = layer_value;
2668
2669 if (shader->selector->info.writes_viewport_index) {
2670 LLVMValueRef v = viewport_index_value;
2671
2672 v = ac_to_integer(&ctx->ac, v);
2673 v = LLVMBuildShl(ctx->ac.builder, v,
2674 LLVMConstInt(ctx->i32, 16, 0), "");
2675 v = LLVMBuildOr(ctx->ac.builder, v,
2676 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2677 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2678 pos_args[1].enabled_channels |= 1 << 2;
2679 }
2680 } else {
2681 if (shader->selector->info.writes_layer)
2682 pos_args[1].out[2] = layer_value;
2683
2684 if (shader->selector->info.writes_viewport_index) {
2685 pos_args[1].out[3] = viewport_index_value;
2686 pos_args[1].enabled_channels |= 1 << 3;
2687 }
2688 }
2689 }
2690
2691 for (i = 0; i < 4; i++)
2692 if (pos_args[i].out[0])
2693 shader->info.nr_pos_exports++;
2694
2695 pos_idx = 0;
2696 for (i = 0; i < 4; i++) {
2697 if (!pos_args[i].out[0])
2698 continue;
2699
2700 /* Specify the target we are exporting */
2701 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2702
2703 if (pos_idx == shader->info.nr_pos_exports)
2704 /* Specify that this is the last export */
2705 pos_args[i].done = 1;
2706
2707 ac_build_export(&ctx->ac, &pos_args[i]);
2708 }
2709
2710 /* Build parameter exports. */
2711 si_build_param_exports(ctx, outputs, noutput);
2712 }
2713
2714 /**
2715 * Forward all outputs from the vertex shader to the TES. This is only used
2716 * for the fixed function TCS.
2717 */
2718 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2719 {
2720 struct si_shader_context *ctx = si_shader_context(bld_base);
2721 LLVMValueRef invocation_id, buffer, buffer_offset;
2722 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2723 uint64_t inputs;
2724
2725 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2726 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2727 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2728
2729 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2730 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2731 lds_vertex_stride, "");
2732 lds_base = get_tcs_in_current_patch_offset(ctx);
2733 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2734
2735 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2736 while (inputs) {
2737 unsigned i = u_bit_scan64(&inputs);
2738
2739 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2740 LLVMConstInt(ctx->i32, 4 * i, 0),
2741 "");
2742
2743 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2744 get_rel_patch_id(ctx),
2745 invocation_id,
2746 LLVMConstInt(ctx->i32, i, 0));
2747
2748 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2749 lds_ptr);
2750
2751 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2752 buffer_offset, 0, 1, 0, true, false);
2753 }
2754 }
2755
2756 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2757 LLVMValueRef rel_patch_id,
2758 LLVMValueRef invocation_id,
2759 LLVMValueRef tcs_out_current_patch_data_offset,
2760 LLVMValueRef invoc0_tf_outer[4],
2761 LLVMValueRef invoc0_tf_inner[2])
2762 {
2763 struct si_shader_context *ctx = si_shader_context(bld_base);
2764 struct si_shader *shader = ctx->shader;
2765 unsigned tess_inner_index, tess_outer_index;
2766 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2767 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2768 unsigned stride, outer_comps, inner_comps, i, offset;
2769 struct lp_build_if_state if_ctx, inner_if_ctx;
2770
2771 /* Add a barrier before loading tess factors from LDS. */
2772 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2773 si_llvm_emit_barrier(NULL, bld_base, NULL);
2774
2775 /* Do this only for invocation 0, because the tess levels are per-patch,
2776 * not per-vertex.
2777 *
2778 * This can't jump, because invocation 0 executes this. It should
2779 * at least mask out the loads and stores for other invocations.
2780 */
2781 lp_build_if(&if_ctx, &ctx->gallivm,
2782 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2783 invocation_id, ctx->i32_0, ""));
2784
2785 /* Determine the layout of one tess factor element in the buffer. */
2786 switch (shader->key.part.tcs.epilog.prim_mode) {
2787 case PIPE_PRIM_LINES:
2788 stride = 2; /* 2 dwords, 1 vec2 store */
2789 outer_comps = 2;
2790 inner_comps = 0;
2791 break;
2792 case PIPE_PRIM_TRIANGLES:
2793 stride = 4; /* 4 dwords, 1 vec4 store */
2794 outer_comps = 3;
2795 inner_comps = 1;
2796 break;
2797 case PIPE_PRIM_QUADS:
2798 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2799 outer_comps = 4;
2800 inner_comps = 2;
2801 break;
2802 default:
2803 assert(0);
2804 return;
2805 }
2806
2807 for (i = 0; i < 4; i++) {
2808 inner[i] = LLVMGetUndef(ctx->i32);
2809 outer[i] = LLVMGetUndef(ctx->i32);
2810 }
2811
2812 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2813 /* Tess factors are in VGPRs. */
2814 for (i = 0; i < outer_comps; i++)
2815 outer[i] = out[i] = invoc0_tf_outer[i];
2816 for (i = 0; i < inner_comps; i++)
2817 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2818 } else {
2819 /* Load tess_inner and tess_outer from LDS.
2820 * Any invocation can write them, so we can't get them from a temporary.
2821 */
2822 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2823 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2824
2825 lds_base = tcs_out_current_patch_data_offset;
2826 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2827 LLVMConstInt(ctx->i32,
2828 tess_inner_index * 4, 0), "");
2829 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2830 LLVMConstInt(ctx->i32,
2831 tess_outer_index * 4, 0), "");
2832
2833 for (i = 0; i < outer_comps; i++) {
2834 outer[i] = out[i] =
2835 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2836 }
2837 for (i = 0; i < inner_comps; i++) {
2838 inner[i] = out[outer_comps+i] =
2839 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2840 }
2841 }
2842
2843 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2844 /* For isolines, the hardware expects tess factors in the
2845 * reverse order from what GLSL / TGSI specify.
2846 */
2847 LLVMValueRef tmp = out[0];
2848 out[0] = out[1];
2849 out[1] = tmp;
2850 }
2851
2852 /* Convert the outputs to vectors for stores. */
2853 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2854 vec1 = NULL;
2855
2856 if (stride > 4)
2857 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2858
2859 /* Get the buffer. */
2860 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2861
2862 /* Get the offset. */
2863 tf_base = LLVMGetParam(ctx->main_fn,
2864 ctx->param_tcs_factor_offset);
2865 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2866 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2867
2868 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2869 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2870 rel_patch_id, ctx->i32_0, ""));
2871
2872 /* Store the dynamic HS control word. */
2873 offset = 0;
2874 if (ctx->screen->info.chip_class <= VI) {
2875 ac_build_buffer_store_dword(&ctx->ac, buffer,
2876 LLVMConstInt(ctx->i32, 0x80000000, 0),
2877 1, ctx->i32_0, tf_base,
2878 offset, 1, 0, true, false);
2879 offset += 4;
2880 }
2881
2882 lp_build_endif(&inner_if_ctx);
2883
2884 /* Store the tessellation factors. */
2885 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2886 MIN2(stride, 4), byteoffset, tf_base,
2887 offset, 1, 0, true, false);
2888 offset += 16;
2889 if (vec1)
2890 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2891 stride - 4, byteoffset, tf_base,
2892 offset, 1, 0, true, false);
2893
2894 /* Store the tess factors into the offchip buffer if TES reads them. */
2895 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2896 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2897 LLVMValueRef tf_inner_offset;
2898 unsigned param_outer, param_inner;
2899
2900 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2901 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2902
2903 param_outer = si_shader_io_get_unique_index_patch(
2904 TGSI_SEMANTIC_TESSOUTER, 0);
2905 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2906 LLVMConstInt(ctx->i32, param_outer, 0));
2907
2908 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2909 util_next_power_of_two(outer_comps));
2910
2911 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2912 outer_comps, tf_outer_offset,
2913 base, 0, 1, 0, true, false);
2914 if (inner_comps) {
2915 param_inner = si_shader_io_get_unique_index_patch(
2916 TGSI_SEMANTIC_TESSINNER, 0);
2917 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2918 LLVMConstInt(ctx->i32, param_inner, 0));
2919
2920 inner_vec = inner_comps == 1 ? inner[0] :
2921 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2922 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2923 inner_comps, tf_inner_offset,
2924 base, 0, 1, 0, true, false);
2925 }
2926 }
2927
2928 lp_build_endif(&if_ctx);
2929 }
2930
2931 static LLVMValueRef
2932 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2933 unsigned param, unsigned return_index)
2934 {
2935 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2936 LLVMGetParam(ctx->main_fn, param),
2937 return_index, "");
2938 }
2939
2940 static LLVMValueRef
2941 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2942 unsigned param, unsigned return_index)
2943 {
2944 LLVMBuilderRef builder = ctx->ac.builder;
2945 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2946
2947 return LLVMBuildInsertValue(builder, ret,
2948 ac_to_float(&ctx->ac, p),
2949 return_index, "");
2950 }
2951
2952 static LLVMValueRef
2953 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2954 unsigned param, unsigned return_index)
2955 {
2956 LLVMBuilderRef builder = ctx->ac.builder;
2957 LLVMValueRef ptr, lo, hi;
2958
2959 ptr = LLVMGetParam(ctx->main_fn, param);
2960 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2961 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2962 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2963 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2964 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2965 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2966 }
2967
2968 /* This only writes the tessellation factor levels. */
2969 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2970 {
2971 struct si_shader_context *ctx = si_shader_context(bld_base);
2972 LLVMBuilderRef builder = ctx->ac.builder;
2973 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2974
2975 si_copy_tcs_inputs(bld_base);
2976
2977 rel_patch_id = get_rel_patch_id(ctx);
2978 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2979 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2980
2981 if (ctx->screen->info.chip_class >= GFX9) {
2982 LLVMBasicBlockRef blocks[2] = {
2983 LLVMGetInsertBlock(builder),
2984 ctx->merged_wrap_if_state.entry_block
2985 };
2986 LLVMValueRef values[2];
2987
2988 lp_build_endif(&ctx->merged_wrap_if_state);
2989
2990 values[0] = rel_patch_id;
2991 values[1] = LLVMGetUndef(ctx->i32);
2992 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2993
2994 values[0] = tf_lds_offset;
2995 values[1] = LLVMGetUndef(ctx->i32);
2996 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2997
2998 values[0] = invocation_id;
2999 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3000 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3001 }
3002
3003 /* Return epilog parameters from this function. */
3004 LLVMValueRef ret = ctx->return_value;
3005 unsigned vgpr;
3006
3007 if (ctx->screen->info.chip_class >= GFX9) {
3008 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3009 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3010 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3011 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3012 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3013 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3014 /* Tess offchip and tess factor offsets are at the beginning. */
3015 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3016 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3017 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3018 } else {
3019 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3020 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3021 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3022 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3023 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3024 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3025 /* Tess offchip and tess factor offsets are after user SGPRs. */
3026 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3027 GFX6_TCS_NUM_USER_SGPR);
3028 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3029 GFX6_TCS_NUM_USER_SGPR + 1);
3030 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3031 }
3032
3033 /* VGPRs */
3034 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3035 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3036 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3037
3038 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3039 * the invocation_id output does not alias the param_tcs_rel_ids input,
3040 * which saves a V_MOV on gfx9.
3041 */
3042 vgpr += 2;
3043
3044 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3045 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3046
3047 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3048 vgpr++; /* skip the tess factor LDS offset */
3049 for (unsigned i = 0; i < 6; i++) {
3050 LLVMValueRef value =
3051 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3052 value = ac_to_float(&ctx->ac, value);
3053 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3054 }
3055 } else {
3056 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3057 }
3058 ctx->return_value = ret;
3059 }
3060
3061 /* Pass TCS inputs from LS to TCS on GFX9. */
3062 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3063 {
3064 LLVMValueRef ret = ctx->return_value;
3065
3066 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3067 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3068 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3069 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3070
3071 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3072 8 + SI_SGPR_RW_BUFFERS);
3073 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3074 ctx->param_bindless_samplers_and_images,
3075 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3076
3077 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3078 8 + SI_SGPR_VS_STATE_BITS);
3079 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3080 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3081 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3082 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3083 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3084 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3085 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3086 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3087 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3088 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3089
3090 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3091 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3092 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3093 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3094 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3095
3096 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3097 ret = si_insert_input_ret_float(ctx, ret,
3098 ctx->param_tcs_patch_id, vgpr++);
3099 ret = si_insert_input_ret_float(ctx, ret,
3100 ctx->param_tcs_rel_ids, vgpr++);
3101 ctx->return_value = ret;
3102 }
3103
3104 /* Pass GS inputs from ES to GS on GFX9. */
3105 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3106 {
3107 LLVMValueRef ret = ctx->return_value;
3108
3109 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3110 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3111 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3112
3113 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3114 8 + SI_SGPR_RW_BUFFERS);
3115 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3116 ctx->param_bindless_samplers_and_images,
3117 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3118
3119 unsigned desc_param = ctx->param_vs_state_bits + 1;
3120 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3121 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3122 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3123 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3124
3125 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3126 for (unsigned i = 0; i < 5; i++) {
3127 unsigned param = ctx->param_gs_vtx01_offset + i;
3128 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3129 }
3130 ctx->return_value = ret;
3131 }
3132
3133 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3134 unsigned max_outputs,
3135 LLVMValueRef *addrs)
3136 {
3137 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3138 struct si_shader *shader = ctx->shader;
3139 struct tgsi_shader_info *info = &shader->selector->info;
3140 unsigned i, chan;
3141 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3142 ctx->param_rel_auto_id);
3143 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3144 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3145 vertex_dw_stride, "");
3146
3147 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3148 * its inputs from it. */
3149 for (i = 0; i < info->num_outputs; i++) {
3150 unsigned name = info->output_semantic_name[i];
3151 unsigned index = info->output_semantic_index[i];
3152
3153 /* The ARB_shader_viewport_layer_array spec contains the
3154 * following issue:
3155 *
3156 * 2) What happens if gl_ViewportIndex or gl_Layer is
3157 * written in the vertex shader and a geometry shader is
3158 * present?
3159 *
3160 * RESOLVED: The value written by the last vertex processing
3161 * stage is used. If the last vertex processing stage
3162 * (vertex, tessellation evaluation or geometry) does not
3163 * statically assign to gl_ViewportIndex or gl_Layer, index
3164 * or layer zero is assumed.
3165 *
3166 * So writes to those outputs in VS-as-LS are simply ignored.
3167 */
3168 if (name == TGSI_SEMANTIC_LAYER ||
3169 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3170 continue;
3171
3172 int param = si_shader_io_get_unique_index(name, index);
3173 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3174 LLVMConstInt(ctx->i32, param * 4, 0), "");
3175
3176 for (chan = 0; chan < 4; chan++) {
3177 if (!(info->output_usagemask[i] & (1 << chan)))
3178 continue;
3179
3180 lds_store(ctx, chan, dw_addr,
3181 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3182 }
3183 }
3184
3185 if (ctx->screen->info.chip_class >= GFX9)
3186 si_set_ls_return_value_for_tcs(ctx);
3187 }
3188
3189 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3190 unsigned max_outputs,
3191 LLVMValueRef *addrs)
3192 {
3193 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3194 struct si_shader *es = ctx->shader;
3195 struct tgsi_shader_info *info = &es->selector->info;
3196 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3197 ctx->param_es2gs_offset);
3198 LLVMValueRef lds_base = NULL;
3199 unsigned chan;
3200 int i;
3201
3202 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3203 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3204 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3205 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3206 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3207 LLVMBuildMul(ctx->ac.builder, wave_idx,
3208 LLVMConstInt(ctx->i32, 64, false), ""), "");
3209 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3210 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3211 }
3212
3213 for (i = 0; i < info->num_outputs; i++) {
3214 int param;
3215
3216 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3217 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3218 continue;
3219
3220 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3221 info->output_semantic_index[i]);
3222
3223 for (chan = 0; chan < 4; chan++) {
3224 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3225 out_val = ac_to_integer(&ctx->ac, out_val);
3226
3227 /* GFX9 has the ESGS ring in LDS. */
3228 if (ctx->screen->info.chip_class >= GFX9) {
3229 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3230 continue;
3231 }
3232
3233 ac_build_buffer_store_dword(&ctx->ac,
3234 ctx->esgs_ring,
3235 out_val, 1, NULL, soffset,
3236 (4 * param + chan) * 4,
3237 1, 1, true, true);
3238 }
3239 }
3240
3241 if (ctx->screen->info.chip_class >= GFX9)
3242 si_set_es_return_value_for_gs(ctx);
3243 }
3244
3245 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3246 {
3247 if (ctx->screen->info.chip_class >= GFX9)
3248 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3249 else
3250 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3251 }
3252
3253 static void emit_gs_epilogue(struct si_shader_context *ctx)
3254 {
3255 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3256 si_get_gs_wave_id(ctx));
3257
3258 if (ctx->screen->info.chip_class >= GFX9)
3259 lp_build_endif(&ctx->merged_wrap_if_state);
3260 }
3261
3262 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3263 unsigned max_outputs,
3264 LLVMValueRef *addrs)
3265 {
3266 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3267 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3268
3269 assert(info->num_outputs <= max_outputs);
3270
3271 emit_gs_epilogue(ctx);
3272 }
3273
3274 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3275 {
3276 struct si_shader_context *ctx = si_shader_context(bld_base);
3277 emit_gs_epilogue(ctx);
3278 }
3279
3280 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3281 unsigned max_outputs,
3282 LLVMValueRef *addrs)
3283 {
3284 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3285 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3286 struct si_shader_output_values *outputs = NULL;
3287 int i,j;
3288
3289 assert(!ctx->shader->is_gs_copy_shader);
3290 assert(info->num_outputs <= max_outputs);
3291
3292 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3293
3294 /* Vertex color clamping.
3295 *
3296 * This uses a state constant loaded in a user data SGPR and
3297 * an IF statement is added that clamps all colors if the constant
3298 * is true.
3299 */
3300 if (ctx->type == PIPE_SHADER_VERTEX) {
3301 struct lp_build_if_state if_ctx;
3302 LLVMValueRef cond = NULL;
3303 LLVMValueRef addr, val;
3304
3305 for (i = 0; i < info->num_outputs; i++) {
3306 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3307 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3308 continue;
3309
3310 /* We've found a color. */
3311 if (!cond) {
3312 /* The state is in the first bit of the user SGPR. */
3313 cond = LLVMGetParam(ctx->main_fn,
3314 ctx->param_vs_state_bits);
3315 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3316 ctx->i1, "");
3317 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3318 }
3319
3320 for (j = 0; j < 4; j++) {
3321 addr = addrs[4 * i + j];
3322 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3323 val = ac_build_clamp(&ctx->ac, val);
3324 LLVMBuildStore(ctx->ac.builder, val, addr);
3325 }
3326 }
3327
3328 if (cond)
3329 lp_build_endif(&if_ctx);
3330 }
3331
3332 for (i = 0; i < info->num_outputs; i++) {
3333 outputs[i].semantic_name = info->output_semantic_name[i];
3334 outputs[i].semantic_index = info->output_semantic_index[i];
3335
3336 for (j = 0; j < 4; j++) {
3337 outputs[i].values[j] =
3338 LLVMBuildLoad(ctx->ac.builder,
3339 addrs[4 * i + j],
3340 "");
3341 outputs[i].vertex_stream[j] =
3342 (info->output_streams[i] >> (2 * j)) & 3;
3343 }
3344 }
3345
3346 if (ctx->shader->selector->so.num_outputs)
3347 si_llvm_emit_streamout(ctx, outputs, i, 0);
3348
3349 /* Export PrimitiveID. */
3350 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3351 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3352 outputs[i].semantic_index = 0;
3353 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3354 for (j = 1; j < 4; j++)
3355 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3356
3357 memset(outputs[i].vertex_stream, 0,
3358 sizeof(outputs[i].vertex_stream));
3359 i++;
3360 }
3361
3362 si_llvm_export_vs(ctx, outputs, i);
3363 FREE(outputs);
3364 }
3365
3366 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3367 {
3368 struct si_shader_context *ctx = si_shader_context(bld_base);
3369
3370 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3371 &ctx->outputs[0][0]);
3372 }
3373
3374 struct si_ps_exports {
3375 unsigned num;
3376 struct ac_export_args args[10];
3377 };
3378
3379 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3380 bool writes_samplemask)
3381 {
3382 if (writes_z) {
3383 /* Z needs 32 bits. */
3384 if (writes_samplemask)
3385 return V_028710_SPI_SHADER_32_ABGR;
3386 else if (writes_stencil)
3387 return V_028710_SPI_SHADER_32_GR;
3388 else
3389 return V_028710_SPI_SHADER_32_R;
3390 } else if (writes_stencil || writes_samplemask) {
3391 /* Both stencil and sample mask need only 16 bits. */
3392 return V_028710_SPI_SHADER_UINT16_ABGR;
3393 } else {
3394 return V_028710_SPI_SHADER_ZERO;
3395 }
3396 }
3397
3398 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3399 LLVMValueRef depth, LLVMValueRef stencil,
3400 LLVMValueRef samplemask, struct si_ps_exports *exp)
3401 {
3402 struct si_shader_context *ctx = si_shader_context(bld_base);
3403 struct lp_build_context *base = &bld_base->base;
3404 struct ac_export_args args;
3405 unsigned mask = 0;
3406 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3407 stencil != NULL,
3408 samplemask != NULL);
3409
3410 assert(depth || stencil || samplemask);
3411
3412 args.valid_mask = 1; /* whether the EXEC mask is valid */
3413 args.done = 1; /* DONE bit */
3414
3415 /* Specify the target we are exporting */
3416 args.target = V_008DFC_SQ_EXP_MRTZ;
3417
3418 args.compr = 0; /* COMP flag */
3419 args.out[0] = base->undef; /* R, depth */
3420 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3421 args.out[2] = base->undef; /* B, sample mask */
3422 args.out[3] = base->undef; /* A, alpha to mask */
3423
3424 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3425 assert(!depth);
3426 args.compr = 1; /* COMPR flag */
3427
3428 if (stencil) {
3429 /* Stencil should be in X[23:16]. */
3430 stencil = ac_to_integer(&ctx->ac, stencil);
3431 stencil = LLVMBuildShl(ctx->ac.builder, stencil,
3432 LLVMConstInt(ctx->i32, 16, 0), "");
3433 args.out[0] = ac_to_float(&ctx->ac, stencil);
3434 mask |= 0x3;
3435 }
3436 if (samplemask) {
3437 /* SampleMask should be in Y[15:0]. */
3438 args.out[1] = samplemask;
3439 mask |= 0xc;
3440 }
3441 } else {
3442 if (depth) {
3443 args.out[0] = depth;
3444 mask |= 0x1;
3445 }
3446 if (stencil) {
3447 args.out[1] = stencil;
3448 mask |= 0x2;
3449 }
3450 if (samplemask) {
3451 args.out[2] = samplemask;
3452 mask |= 0x4;
3453 }
3454 }
3455
3456 /* SI (except OLAND and HAINAN) has a bug that it only looks
3457 * at the X writemask component. */
3458 if (ctx->screen->info.chip_class == SI &&
3459 ctx->screen->info.family != CHIP_OLAND &&
3460 ctx->screen->info.family != CHIP_HAINAN)
3461 mask |= 0x1;
3462
3463 /* Specify which components to enable */
3464 args.enabled_channels = mask;
3465
3466 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3467 }
3468
3469 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3470 LLVMValueRef *color, unsigned index,
3471 unsigned samplemask_param,
3472 bool is_last, struct si_ps_exports *exp)
3473 {
3474 struct si_shader_context *ctx = si_shader_context(bld_base);
3475 int i;
3476
3477 /* Clamp color */
3478 if (ctx->shader->key.part.ps.epilog.clamp_color)
3479 for (i = 0; i < 4; i++)
3480 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3481
3482 /* Alpha to one */
3483 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3484 color[3] = ctx->ac.f32_1;
3485
3486 /* Alpha test */
3487 if (index == 0 &&
3488 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3489 si_alpha_test(bld_base, color[3]);
3490
3491 /* Line & polygon smoothing */
3492 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3493 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3494 samplemask_param);
3495
3496 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3497 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3498 struct ac_export_args args[8];
3499 int c, last = -1;
3500
3501 /* Get the export arguments, also find out what the last one is. */
3502 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3503 si_llvm_init_export_args(ctx, color,
3504 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3505 if (args[c].enabled_channels)
3506 last = c;
3507 }
3508
3509 /* Emit all exports. */
3510 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3511 if (is_last && last == c) {
3512 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3513 args[c].done = 1; /* DONE bit */
3514 } else if (!args[c].enabled_channels)
3515 continue; /* unnecessary NULL export */
3516
3517 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3518 }
3519 } else {
3520 struct ac_export_args args;
3521
3522 /* Export */
3523 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3524 &args);
3525 if (is_last) {
3526 args.valid_mask = 1; /* whether the EXEC mask is valid */
3527 args.done = 1; /* DONE bit */
3528 } else if (!args.enabled_channels)
3529 return; /* unnecessary NULL export */
3530
3531 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3532 }
3533 }
3534
3535 static void si_emit_ps_exports(struct si_shader_context *ctx,
3536 struct si_ps_exports *exp)
3537 {
3538 for (unsigned i = 0; i < exp->num; i++)
3539 ac_build_export(&ctx->ac, &exp->args[i]);
3540 }
3541
3542 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3543 {
3544 struct si_shader_context *ctx = si_shader_context(bld_base);
3545 struct lp_build_context *base = &bld_base->base;
3546 struct ac_export_args args;
3547
3548 args.enabled_channels = 0x0; /* enabled channels */
3549 args.valid_mask = 1; /* whether the EXEC mask is valid */
3550 args.done = 1; /* DONE bit */
3551 args.target = V_008DFC_SQ_EXP_NULL;
3552 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3553 args.out[0] = base->undef; /* R */
3554 args.out[1] = base->undef; /* G */
3555 args.out[2] = base->undef; /* B */
3556 args.out[3] = base->undef; /* A */
3557
3558 ac_build_export(&ctx->ac, &args);
3559 }
3560
3561 /**
3562 * Return PS outputs in this order:
3563 *
3564 * v[0:3] = color0.xyzw
3565 * v[4:7] = color1.xyzw
3566 * ...
3567 * vN+0 = Depth
3568 * vN+1 = Stencil
3569 * vN+2 = SampleMask
3570 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3571 *
3572 * The alpha-ref SGPR is returned via its original location.
3573 */
3574 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3575 unsigned max_outputs,
3576 LLVMValueRef *addrs)
3577 {
3578 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3579 struct si_shader *shader = ctx->shader;
3580 struct tgsi_shader_info *info = &shader->selector->info;
3581 LLVMBuilderRef builder = ctx->ac.builder;
3582 unsigned i, j, first_vgpr, vgpr;
3583
3584 LLVMValueRef color[8][4] = {};
3585 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3586 LLVMValueRef ret;
3587
3588 if (ctx->postponed_kill)
3589 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3590
3591 /* Read the output values. */
3592 for (i = 0; i < info->num_outputs; i++) {
3593 unsigned semantic_name = info->output_semantic_name[i];
3594 unsigned semantic_index = info->output_semantic_index[i];
3595
3596 switch (semantic_name) {
3597 case TGSI_SEMANTIC_COLOR:
3598 assert(semantic_index < 8);
3599 for (j = 0; j < 4; j++) {
3600 LLVMValueRef ptr = addrs[4 * i + j];
3601 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3602 color[semantic_index][j] = result;
3603 }
3604 break;
3605 case TGSI_SEMANTIC_POSITION:
3606 depth = LLVMBuildLoad(builder,
3607 addrs[4 * i + 2], "");
3608 break;
3609 case TGSI_SEMANTIC_STENCIL:
3610 stencil = LLVMBuildLoad(builder,
3611 addrs[4 * i + 1], "");
3612 break;
3613 case TGSI_SEMANTIC_SAMPLEMASK:
3614 samplemask = LLVMBuildLoad(builder,
3615 addrs[4 * i + 0], "");
3616 break;
3617 default:
3618 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3619 semantic_name);
3620 }
3621 }
3622
3623 /* Fill the return structure. */
3624 ret = ctx->return_value;
3625
3626 /* Set SGPRs. */
3627 ret = LLVMBuildInsertValue(builder, ret,
3628 ac_to_integer(&ctx->ac,
3629 LLVMGetParam(ctx->main_fn,
3630 SI_PARAM_ALPHA_REF)),
3631 SI_SGPR_ALPHA_REF, "");
3632
3633 /* Set VGPRs */
3634 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3635 for (i = 0; i < ARRAY_SIZE(color); i++) {
3636 if (!color[i][0])
3637 continue;
3638
3639 for (j = 0; j < 4; j++)
3640 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3641 }
3642 if (depth)
3643 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3644 if (stencil)
3645 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3646 if (samplemask)
3647 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3648
3649 /* Add the input sample mask for smoothing at the end. */
3650 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3651 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3652 ret = LLVMBuildInsertValue(builder, ret,
3653 LLVMGetParam(ctx->main_fn,
3654 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3655
3656 ctx->return_value = ret;
3657 }
3658
3659 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3660 {
3661 LLVMValueRef args[1] = {
3662 LLVMConstInt(ctx->i32, simm16, 0)
3663 };
3664 lp_build_intrinsic(ctx->ac.builder, "llvm.amdgcn.s.waitcnt",
3665 ctx->voidt, args, 1, 0);
3666 }
3667
3668 static void membar_emit(
3669 const struct lp_build_tgsi_action *action,
3670 struct lp_build_tgsi_context *bld_base,
3671 struct lp_build_emit_data *emit_data)
3672 {
3673 struct si_shader_context *ctx = si_shader_context(bld_base);
3674 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3675 unsigned flags = LLVMConstIntGetZExtValue(src0);
3676 unsigned waitcnt = NOOP_WAITCNT;
3677
3678 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3679 waitcnt &= VM_CNT & LGKM_CNT;
3680
3681 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3682 TGSI_MEMBAR_SHADER_BUFFER |
3683 TGSI_MEMBAR_SHADER_IMAGE))
3684 waitcnt &= VM_CNT;
3685
3686 if (flags & TGSI_MEMBAR_SHARED)
3687 waitcnt &= LGKM_CNT;
3688
3689 if (waitcnt != NOOP_WAITCNT)
3690 si_emit_waitcnt(ctx, waitcnt);
3691 }
3692
3693 static void clock_emit(
3694 const struct lp_build_tgsi_action *action,
3695 struct lp_build_tgsi_context *bld_base,
3696 struct lp_build_emit_data *emit_data)
3697 {
3698 struct si_shader_context *ctx = si_shader_context(bld_base);
3699 LLVMValueRef tmp;
3700
3701 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3702 ctx->i64, NULL, 0, 0);
3703 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3704
3705 emit_data->output[0] =
3706 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3707 emit_data->output[1] =
3708 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3709 }
3710
3711 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3712 {
3713 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3714 CONST_ADDR_SPACE);
3715 }
3716
3717 static void si_llvm_emit_ddxy(
3718 const struct lp_build_tgsi_action *action,
3719 struct lp_build_tgsi_context *bld_base,
3720 struct lp_build_emit_data *emit_data)
3721 {
3722 struct si_shader_context *ctx = si_shader_context(bld_base);
3723 unsigned opcode = emit_data->info->opcode;
3724 LLVMValueRef val;
3725 int idx;
3726 unsigned mask;
3727
3728 if (opcode == TGSI_OPCODE_DDX_FINE)
3729 mask = AC_TID_MASK_LEFT;
3730 else if (opcode == TGSI_OPCODE_DDY_FINE)
3731 mask = AC_TID_MASK_TOP;
3732 else
3733 mask = AC_TID_MASK_TOP_LEFT;
3734
3735 /* for DDX we want to next X pixel, DDY next Y pixel. */
3736 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3737
3738 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3739 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3740 emit_data->output[emit_data->chan] = val;
3741 }
3742
3743 /*
3744 * this takes an I,J coordinate pair,
3745 * and works out the X and Y derivatives.
3746 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3747 */
3748 static LLVMValueRef si_llvm_emit_ddxy_interp(
3749 struct lp_build_tgsi_context *bld_base,
3750 LLVMValueRef interp_ij)
3751 {
3752 struct si_shader_context *ctx = si_shader_context(bld_base);
3753 LLVMValueRef result[4], a;
3754 unsigned i;
3755
3756 for (i = 0; i < 2; i++) {
3757 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3758 LLVMConstInt(ctx->i32, i, 0), "");
3759 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3760 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3761 }
3762
3763 return lp_build_gather_values(&ctx->gallivm, result, 4);
3764 }
3765
3766 static void interp_fetch_args(
3767 struct lp_build_tgsi_context *bld_base,
3768 struct lp_build_emit_data *emit_data)
3769 {
3770 struct si_shader_context *ctx = si_shader_context(bld_base);
3771 const struct tgsi_full_instruction *inst = emit_data->inst;
3772
3773 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3774 /* offset is in second src, first two channels */
3775 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3776 emit_data->inst, 1,
3777 TGSI_CHAN_X);
3778 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3779 emit_data->inst, 1,
3780 TGSI_CHAN_Y);
3781 emit_data->arg_count = 2;
3782 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3783 LLVMValueRef sample_position;
3784 LLVMValueRef sample_id;
3785 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3786
3787 /* fetch sample ID, then fetch its sample position,
3788 * and place into first two channels.
3789 */
3790 sample_id = lp_build_emit_fetch(bld_base,
3791 emit_data->inst, 1, TGSI_CHAN_X);
3792 sample_id = ac_to_integer(&ctx->ac, sample_id);
3793
3794 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3795 * Language 4.50 spec says about interpolateAtSample:
3796 *
3797 * "Returns the value of the input interpolant variable at
3798 * the location of sample number sample. If multisample
3799 * buffers are not available, the input variable will be
3800 * evaluated at the center of the pixel. If sample sample
3801 * does not exist, the position used to interpolate the
3802 * input variable is undefined."
3803 *
3804 * This means that sample_id values outside of the valid are
3805 * in fact valid input, and the usual mechanism for loading the
3806 * sample position doesn't work.
3807 */
3808 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3809 LLVMValueRef center[4] = {
3810 LLVMConstReal(ctx->f32, 0.5),
3811 LLVMConstReal(ctx->f32, 0.5),
3812 ctx->ac.f32_0,
3813 ctx->ac.f32_0,
3814 };
3815
3816 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3817 } else {
3818 sample_position = load_sample_position(ctx, sample_id);
3819 }
3820
3821 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3822 sample_position,
3823 ctx->i32_0, "");
3824
3825 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3826 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3827 sample_position,
3828 ctx->i32_1, "");
3829 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3830 emit_data->arg_count = 2;
3831 }
3832 }
3833
3834 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3835 struct lp_build_tgsi_context *bld_base,
3836 struct lp_build_emit_data *emit_data)
3837 {
3838 struct si_shader_context *ctx = si_shader_context(bld_base);
3839 struct si_shader *shader = ctx->shader;
3840 const struct tgsi_shader_info *info = &shader->selector->info;
3841 LLVMValueRef interp_param;
3842 const struct tgsi_full_instruction *inst = emit_data->inst;
3843 const struct tgsi_full_src_register *input = &inst->Src[0];
3844 int input_base, input_array_size;
3845 int chan;
3846 int i;
3847 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3848 LLVMValueRef array_idx;
3849 int interp_param_idx;
3850 unsigned interp;
3851 unsigned location;
3852
3853 assert(input->Register.File == TGSI_FILE_INPUT);
3854
3855 if (input->Register.Indirect) {
3856 unsigned array_id = input->Indirect.ArrayID;
3857
3858 if (array_id) {
3859 input_base = info->input_array_first[array_id];
3860 input_array_size = info->input_array_last[array_id] - input_base + 1;
3861 } else {
3862 input_base = inst->Src[0].Register.Index;
3863 input_array_size = info->num_inputs - input_base;
3864 }
3865
3866 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3867 1, input->Register.Index - input_base);
3868 } else {
3869 input_base = inst->Src[0].Register.Index;
3870 input_array_size = 1;
3871 array_idx = ctx->i32_0;
3872 }
3873
3874 interp = shader->selector->info.input_interpolate[input_base];
3875
3876 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3877 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3878 location = TGSI_INTERPOLATE_LOC_CENTER;
3879 else
3880 location = TGSI_INTERPOLATE_LOC_CENTROID;
3881
3882 interp_param_idx = lookup_interp_param_index(interp, location);
3883 if (interp_param_idx == -1)
3884 return;
3885 else if (interp_param_idx)
3886 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3887 else
3888 interp_param = NULL;
3889
3890 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3891 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3892 LLVMValueRef ij_out[2];
3893 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3894
3895 /*
3896 * take the I then J parameters, and the DDX/Y for it, and
3897 * calculate the IJ inputs for the interpolator.
3898 * temp1 = ddx * offset/sample.x + I;
3899 * interp_param.I = ddy * offset/sample.y + temp1;
3900 * temp1 = ddx * offset/sample.x + J;
3901 * interp_param.J = ddy * offset/sample.y + temp1;
3902 */
3903 for (i = 0; i < 2; i++) {
3904 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3905 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3906 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3907 ddxy_out, ix_ll, "");
3908 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3909 ddxy_out, iy_ll, "");
3910 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3911 interp_param, ix_ll, "");
3912 LLVMValueRef temp1, temp2;
3913
3914 interp_el = ac_to_float(&ctx->ac, interp_el);
3915
3916 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3917
3918 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3919
3920 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3921
3922 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3923 }
3924 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3925 }
3926
3927 if (interp_param)
3928 interp_param = ac_to_float(&ctx->ac, interp_param);
3929
3930 for (chan = 0; chan < 4; chan++) {
3931 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3932 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3933
3934 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3935 LLVMValueRef v, i = NULL, j = NULL;
3936
3937 if (interp_param) {
3938 i = LLVMBuildExtractElement(
3939 ctx->ac.builder, interp_param, ctx->i32_0, "");
3940 j = LLVMBuildExtractElement(
3941 ctx->ac.builder, interp_param, ctx->i32_1, "");
3942 }
3943 v = si_build_fs_interp(ctx, input_base + idx, schan,
3944 prim_mask, i, j);
3945
3946 gather = LLVMBuildInsertElement(ctx->ac.builder,
3947 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3948 }
3949
3950 emit_data->output[chan] = LLVMBuildExtractElement(
3951 ctx->ac.builder, gather, array_idx, "");
3952 }
3953 }
3954
3955 static void vote_all_emit(
3956 const struct lp_build_tgsi_action *action,
3957 struct lp_build_tgsi_context *bld_base,
3958 struct lp_build_emit_data *emit_data)
3959 {
3960 struct si_shader_context *ctx = si_shader_context(bld_base);
3961
3962 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3963 emit_data->output[emit_data->chan] =
3964 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3965 }
3966
3967 static void vote_any_emit(
3968 const struct lp_build_tgsi_action *action,
3969 struct lp_build_tgsi_context *bld_base,
3970 struct lp_build_emit_data *emit_data)
3971 {
3972 struct si_shader_context *ctx = si_shader_context(bld_base);
3973
3974 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3975 emit_data->output[emit_data->chan] =
3976 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3977 }
3978
3979 static void vote_eq_emit(
3980 const struct lp_build_tgsi_action *action,
3981 struct lp_build_tgsi_context *bld_base,
3982 struct lp_build_emit_data *emit_data)
3983 {
3984 struct si_shader_context *ctx = si_shader_context(bld_base);
3985
3986 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3987 emit_data->output[emit_data->chan] =
3988 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3989 }
3990
3991 static void ballot_emit(
3992 const struct lp_build_tgsi_action *action,
3993 struct lp_build_tgsi_context *bld_base,
3994 struct lp_build_emit_data *emit_data)
3995 {
3996 struct si_shader_context *ctx = si_shader_context(bld_base);
3997 LLVMBuilderRef builder = ctx->ac.builder;
3998 LLVMValueRef tmp;
3999
4000 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4001 tmp = ac_build_ballot(&ctx->ac, tmp);
4002 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4003
4004 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4005 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4006 }
4007
4008 static void read_invoc_fetch_args(
4009 struct lp_build_tgsi_context *bld_base,
4010 struct lp_build_emit_data *emit_data)
4011 {
4012 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4013 0, emit_data->src_chan);
4014
4015 /* Always read the source invocation (= lane) from the X channel. */
4016 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4017 1, TGSI_CHAN_X);
4018 emit_data->arg_count = 2;
4019 }
4020
4021 static void read_lane_emit(
4022 const struct lp_build_tgsi_action *action,
4023 struct lp_build_tgsi_context *bld_base,
4024 struct lp_build_emit_data *emit_data)
4025 {
4026 struct si_shader_context *ctx = si_shader_context(bld_base);
4027
4028 /* We currently have no other way to prevent LLVM from lifting the icmp
4029 * calls to a dominating basic block.
4030 */
4031 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4032
4033 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4034 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4035
4036 emit_data->output[emit_data->chan] =
4037 ac_build_intrinsic(&ctx->ac, action->intr_name,
4038 ctx->i32, emit_data->args, emit_data->arg_count,
4039 AC_FUNC_ATTR_READNONE |
4040 AC_FUNC_ATTR_CONVERGENT);
4041 }
4042
4043 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4044 struct lp_build_emit_data *emit_data)
4045 {
4046 struct si_shader_context *ctx = si_shader_context(bld_base);
4047 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4048 LLVMValueRef imm;
4049 unsigned stream;
4050
4051 assert(src0.File == TGSI_FILE_IMMEDIATE);
4052
4053 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4054 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4055 return stream;
4056 }
4057
4058 /* Emit one vertex from the geometry shader */
4059 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4060 unsigned stream,
4061 LLVMValueRef *addrs)
4062 {
4063 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4064 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4065 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4066 struct si_shader *shader = ctx->shader;
4067 struct lp_build_if_state if_state;
4068 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4069 ctx->param_gs2vs_offset);
4070 LLVMValueRef gs_next_vertex;
4071 LLVMValueRef can_emit;
4072 unsigned chan, offset;
4073 int i;
4074
4075 /* Write vertex attribute values to GSVS ring */
4076 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4077 ctx->gs_next_vertex[stream],
4078 "");
4079
4080 /* If this thread has already emitted the declared maximum number of
4081 * vertices, skip the write: excessive vertex emissions are not
4082 * supposed to have any effect.
4083 *
4084 * If the shader has no writes to memory, kill it instead. This skips
4085 * further memory loads and may allow LLVM to skip to the end
4086 * altogether.
4087 */
4088 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4089 LLVMConstInt(ctx->i32,
4090 shader->selector->gs_max_out_vertices, 0), "");
4091
4092 bool use_kill = !info->writes_memory;
4093 if (use_kill) {
4094 ac_build_kill_if_false(&ctx->ac, can_emit);
4095 } else {
4096 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4097 }
4098
4099 offset = 0;
4100 for (i = 0; i < info->num_outputs; i++) {
4101 for (chan = 0; chan < 4; chan++) {
4102 if (!(info->output_usagemask[i] & (1 << chan)) ||
4103 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4104 continue;
4105
4106 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4107 LLVMValueRef voffset =
4108 LLVMConstInt(ctx->i32, offset *
4109 shader->selector->gs_max_out_vertices, 0);
4110 offset++;
4111
4112 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4113 voffset = lp_build_mul_imm(uint, voffset, 4);
4114
4115 out_val = ac_to_integer(&ctx->ac, out_val);
4116
4117 ac_build_buffer_store_dword(&ctx->ac,
4118 ctx->gsvs_ring[stream],
4119 out_val, 1,
4120 voffset, soffset, 0,
4121 1, 1, true, true);
4122 }
4123 }
4124
4125 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4126 ctx->i32_1);
4127
4128 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4129
4130 /* Signal vertex emission */
4131 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4132 si_get_gs_wave_id(ctx));
4133 if (!use_kill)
4134 lp_build_endif(&if_state);
4135 }
4136
4137 /* Emit one vertex from the geometry shader */
4138 static void si_tgsi_emit_vertex(
4139 const struct lp_build_tgsi_action *action,
4140 struct lp_build_tgsi_context *bld_base,
4141 struct lp_build_emit_data *emit_data)
4142 {
4143 struct si_shader_context *ctx = si_shader_context(bld_base);
4144 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4145
4146 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4147 }
4148
4149 /* Cut one primitive from the geometry shader */
4150 static void si_llvm_emit_primitive(
4151 const struct lp_build_tgsi_action *action,
4152 struct lp_build_tgsi_context *bld_base,
4153 struct lp_build_emit_data *emit_data)
4154 {
4155 struct si_shader_context *ctx = si_shader_context(bld_base);
4156 unsigned stream;
4157
4158 /* Signal primitive cut */
4159 stream = si_llvm_get_stream(bld_base, emit_data);
4160 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4161 si_get_gs_wave_id(ctx));
4162 }
4163
4164 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4165 struct lp_build_tgsi_context *bld_base,
4166 struct lp_build_emit_data *emit_data)
4167 {
4168 struct si_shader_context *ctx = si_shader_context(bld_base);
4169
4170 /* SI only (thanks to a hw bug workaround):
4171 * The real barrier instruction isn’t needed, because an entire patch
4172 * always fits into a single wave.
4173 */
4174 if (ctx->screen->info.chip_class == SI &&
4175 ctx->type == PIPE_SHADER_TESS_CTRL) {
4176 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4177 return;
4178 }
4179
4180 lp_build_intrinsic(ctx->ac.builder,
4181 "llvm.amdgcn.s.barrier",
4182 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4183 }
4184
4185 static const struct lp_build_tgsi_action interp_action = {
4186 .fetch_args = interp_fetch_args,
4187 .emit = build_interp_intrinsic,
4188 };
4189
4190 static void si_create_function(struct si_shader_context *ctx,
4191 const char *name,
4192 LLVMTypeRef *returns, unsigned num_returns,
4193 struct si_function_info *fninfo,
4194 unsigned max_workgroup_size)
4195 {
4196 int i;
4197
4198 si_llvm_create_func(ctx, name, returns, num_returns,
4199 fninfo->types, fninfo->num_params);
4200 ctx->return_value = LLVMGetUndef(ctx->return_type);
4201
4202 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4203 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4204
4205 /* The combination of:
4206 * - ByVal
4207 * - dereferenceable
4208 * - invariant.load
4209 * allows the optimization passes to move loads and reduces
4210 * SGPR spilling significantly.
4211 */
4212 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4213 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4214 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4215 ac_add_attr_dereferenceable(P, UINT64_MAX);
4216 } else
4217 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4218 }
4219
4220 for (i = 0; i < fninfo->num_params; ++i) {
4221 if (fninfo->assign[i])
4222 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4223 }
4224
4225 if (max_workgroup_size) {
4226 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4227 max_workgroup_size);
4228 }
4229 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4230 "no-signed-zeros-fp-math",
4231 "true");
4232
4233 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4234 /* These were copied from some LLVM test. */
4235 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4236 "less-precise-fpmad",
4237 "true");
4238 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4239 "no-infs-fp-math",
4240 "true");
4241 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4242 "no-nans-fp-math",
4243 "true");
4244 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4245 "unsafe-fp-math",
4246 "true");
4247 }
4248 }
4249
4250 static void declare_streamout_params(struct si_shader_context *ctx,
4251 struct pipe_stream_output_info *so,
4252 struct si_function_info *fninfo)
4253 {
4254 int i;
4255
4256 /* Streamout SGPRs. */
4257 if (so->num_outputs) {
4258 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4259 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4260 else
4261 ctx->param_streamout_config = fninfo->num_params - 1;
4262
4263 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4264 }
4265 /* A streamout buffer offset is loaded if the stride is non-zero. */
4266 for (i = 0; i < 4; i++) {
4267 if (!so->stride[i])
4268 continue;
4269
4270 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4271 }
4272 }
4273
4274 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4275 {
4276 switch (shader->selector->type) {
4277 case PIPE_SHADER_TESS_CTRL:
4278 /* Return this so that LLVM doesn't remove s_barrier
4279 * instructions on chips where we use s_barrier. */
4280 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4281
4282 case PIPE_SHADER_GEOMETRY:
4283 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4284
4285 case PIPE_SHADER_COMPUTE:
4286 break; /* see below */
4287
4288 default:
4289 return 0;
4290 }
4291
4292 const unsigned *properties = shader->selector->info.properties;
4293 unsigned max_work_group_size =
4294 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4295 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4296 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4297
4298 if (!max_work_group_size) {
4299 /* This is a variable group size compute shader,
4300 * compile it for the maximum possible group size.
4301 */
4302 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4303 }
4304 return max_work_group_size;
4305 }
4306
4307 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4308 struct si_function_info *fninfo,
4309 bool assign_params)
4310 {
4311 LLVMTypeRef const_shader_buf_type;
4312
4313 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4314 ctx->shader->selector->info.shader_buffers_declared == 0)
4315 const_shader_buf_type = ctx->f32;
4316 else
4317 const_shader_buf_type = ctx->v4i32;
4318
4319 unsigned const_and_shader_buffers =
4320 add_arg(fninfo, ARG_SGPR,
4321 si_const_array(const_shader_buf_type, 0));
4322
4323 unsigned samplers_and_images =
4324 add_arg(fninfo, ARG_SGPR,
4325 si_const_array(ctx->v8i32,
4326 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4327
4328 if (assign_params) {
4329 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4330 ctx->param_samplers_and_images = samplers_and_images;
4331 }
4332 }
4333
4334 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4335 struct si_function_info *fninfo)
4336 {
4337 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4338 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4339 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4340 si_const_array(ctx->v8i32, 0));
4341 }
4342
4343 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4344 struct si_function_info *fninfo)
4345 {
4346 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4347 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4348 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4349 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4350 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4351 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4352 }
4353
4354 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4355 struct si_function_info *fninfo,
4356 unsigned *num_prolog_vgprs)
4357 {
4358 struct si_shader *shader = ctx->shader;
4359
4360 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4361 if (shader->key.as_ls) {
4362 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4363 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4364 } else {
4365 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4366 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4367 }
4368 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4369
4370 if (!shader->is_gs_copy_shader) {
4371 /* Vertex load indices. */
4372 ctx->param_vertex_index0 = fninfo->num_params;
4373 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4374 add_arg(fninfo, ARG_VGPR, ctx->i32);
4375 *num_prolog_vgprs += shader->selector->info.num_inputs;
4376 }
4377 }
4378
4379 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4380 struct si_function_info *fninfo)
4381 {
4382 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4383 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4384 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4385 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4386 }
4387
4388 enum {
4389 /* Convenient merged shader definitions. */
4390 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4391 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4392 };
4393
4394 static void create_function(struct si_shader_context *ctx)
4395 {
4396 struct si_shader *shader = ctx->shader;
4397 struct si_function_info fninfo;
4398 LLVMTypeRef returns[16+32*4];
4399 unsigned i, num_return_sgprs;
4400 unsigned num_returns = 0;
4401 unsigned num_prolog_vgprs = 0;
4402 unsigned type = ctx->type;
4403 unsigned vs_blit_property =
4404 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4405
4406 si_init_function_info(&fninfo);
4407
4408 /* Set MERGED shaders. */
4409 if (ctx->screen->info.chip_class >= GFX9) {
4410 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4411 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4412 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4413 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4414 }
4415
4416 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4417
4418 switch (type) {
4419 case PIPE_SHADER_VERTEX:
4420 declare_global_desc_pointers(ctx, &fninfo);
4421
4422 if (vs_blit_property) {
4423 ctx->param_vs_blit_inputs = fninfo.num_params;
4424 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4425 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4426 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4427
4428 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4429 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4430 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4431 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4432 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4433 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4434 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4435 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4436 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4437 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4438 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4439 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4440 }
4441
4442 /* VGPRs */
4443 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4444 break;
4445 }
4446
4447 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4448 declare_vs_specific_input_sgprs(ctx, &fninfo);
4449
4450 if (shader->key.as_es) {
4451 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4452 } else if (shader->key.as_ls) {
4453 /* no extra parameters */
4454 } else {
4455 if (shader->is_gs_copy_shader) {
4456 fninfo.num_params = ctx->param_rw_buffers + 1;
4457 fninfo.num_sgpr_params = fninfo.num_params;
4458 }
4459
4460 /* The locations of the other parameters are assigned dynamically. */
4461 declare_streamout_params(ctx, &shader->selector->so,
4462 &fninfo);
4463 }
4464
4465 /* VGPRs */
4466 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4467 break;
4468
4469 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4470 declare_global_desc_pointers(ctx, &fninfo);
4471 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4472 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4473 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4474 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4475 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4476 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4477 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4478 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4479 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4480
4481 /* VGPRs */
4482 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4483 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4484
4485 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4486 * placed after the user SGPRs.
4487 */
4488 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4489 returns[num_returns++] = ctx->i32; /* SGPRs */
4490 for (i = 0; i < 11; i++)
4491 returns[num_returns++] = ctx->f32; /* VGPRs */
4492 break;
4493
4494 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4495 /* Merged stages have 8 system SGPRs at the beginning. */
4496 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4497 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4498 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4499 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4500 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4501 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4502 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4503 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4504
4505 declare_global_desc_pointers(ctx, &fninfo);
4506 declare_per_stage_desc_pointers(ctx, &fninfo,
4507 ctx->type == PIPE_SHADER_VERTEX);
4508 declare_vs_specific_input_sgprs(ctx, &fninfo);
4509
4510 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4511 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4512 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4513 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4514 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4515 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4516
4517 declare_per_stage_desc_pointers(ctx, &fninfo,
4518 ctx->type == PIPE_SHADER_TESS_CTRL);
4519
4520 /* VGPRs (first TCS, then VS) */
4521 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4522 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4523
4524 if (ctx->type == PIPE_SHADER_VERTEX) {
4525 declare_vs_input_vgprs(ctx, &fninfo,
4526 &num_prolog_vgprs);
4527
4528 /* LS return values are inputs to the TCS main shader part. */
4529 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4530 returns[num_returns++] = ctx->i32; /* SGPRs */
4531 for (i = 0; i < 2; i++)
4532 returns[num_returns++] = ctx->f32; /* VGPRs */
4533 } else {
4534 /* TCS return values are inputs to the TCS epilog.
4535 *
4536 * param_tcs_offchip_offset, param_tcs_factor_offset,
4537 * param_tcs_offchip_layout, and param_rw_buffers
4538 * should be passed to the epilog.
4539 */
4540 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4541 returns[num_returns++] = ctx->i32; /* SGPRs */
4542 for (i = 0; i < 11; i++)
4543 returns[num_returns++] = ctx->f32; /* VGPRs */
4544 }
4545 break;
4546
4547 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4548 /* Merged stages have 8 system SGPRs at the beginning. */
4549 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4550 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4551 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4552 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4553 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4554 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4555 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4556 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4557
4558 declare_global_desc_pointers(ctx, &fninfo);
4559 declare_per_stage_desc_pointers(ctx, &fninfo,
4560 (ctx->type == PIPE_SHADER_VERTEX ||
4561 ctx->type == PIPE_SHADER_TESS_EVAL));
4562 if (ctx->type == PIPE_SHADER_VERTEX) {
4563 declare_vs_specific_input_sgprs(ctx, &fninfo);
4564 } else {
4565 /* TESS_EVAL (and also GEOMETRY):
4566 * Declare as many input SGPRs as the VS has. */
4567 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4568 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4569 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4570 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4571 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4572 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4573 }
4574
4575 declare_per_stage_desc_pointers(ctx, &fninfo,
4576 ctx->type == PIPE_SHADER_GEOMETRY);
4577
4578 /* VGPRs (first GS, then VS/TES) */
4579 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4580 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4581 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4582 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4583 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4584
4585 if (ctx->type == PIPE_SHADER_VERTEX) {
4586 declare_vs_input_vgprs(ctx, &fninfo,
4587 &num_prolog_vgprs);
4588 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4589 declare_tes_input_vgprs(ctx, &fninfo);
4590 }
4591
4592 if (ctx->type == PIPE_SHADER_VERTEX ||
4593 ctx->type == PIPE_SHADER_TESS_EVAL) {
4594 /* ES return values are inputs to GS. */
4595 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4596 returns[num_returns++] = ctx->i32; /* SGPRs */
4597 for (i = 0; i < 5; i++)
4598 returns[num_returns++] = ctx->f32; /* VGPRs */
4599 }
4600 break;
4601
4602 case PIPE_SHADER_TESS_EVAL:
4603 declare_global_desc_pointers(ctx, &fninfo);
4604 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4605 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4606 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4607
4608 if (shader->key.as_es) {
4609 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4610 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4611 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4612 } else {
4613 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4614 declare_streamout_params(ctx, &shader->selector->so,
4615 &fninfo);
4616 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4617 }
4618
4619 /* VGPRs */
4620 declare_tes_input_vgprs(ctx, &fninfo);
4621 break;
4622
4623 case PIPE_SHADER_GEOMETRY:
4624 declare_global_desc_pointers(ctx, &fninfo);
4625 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4626 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4627 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4628
4629 /* VGPRs */
4630 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4631 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4632 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4633 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4634 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4635 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4636 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4637 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4638 break;
4639
4640 case PIPE_SHADER_FRAGMENT:
4641 declare_global_desc_pointers(ctx, &fninfo);
4642 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4643 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4644 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4645
4646 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4647 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4648 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4649 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4650 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4651 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4652 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4653 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4654 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4655 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4656 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4657 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4658 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4659 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4660 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4661 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4662 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4663 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4664 shader->info.face_vgpr_index = 20;
4665 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4666 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4667 shader->info.ancillary_vgpr_index = 21;
4668 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4669 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4670 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4671
4672 /* Color inputs from the prolog. */
4673 if (shader->selector->info.colors_read) {
4674 unsigned num_color_elements =
4675 util_bitcount(shader->selector->info.colors_read);
4676
4677 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4678 for (i = 0; i < num_color_elements; i++)
4679 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4680
4681 num_prolog_vgprs += num_color_elements;
4682 }
4683
4684 /* Outputs for the epilog. */
4685 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4686 num_returns =
4687 num_return_sgprs +
4688 util_bitcount(shader->selector->info.colors_written) * 4 +
4689 shader->selector->info.writes_z +
4690 shader->selector->info.writes_stencil +
4691 shader->selector->info.writes_samplemask +
4692 1 /* SampleMaskIn */;
4693
4694 num_returns = MAX2(num_returns,
4695 num_return_sgprs +
4696 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4697
4698 for (i = 0; i < num_return_sgprs; i++)
4699 returns[i] = ctx->i32;
4700 for (; i < num_returns; i++)
4701 returns[i] = ctx->f32;
4702 break;
4703
4704 case PIPE_SHADER_COMPUTE:
4705 declare_global_desc_pointers(ctx, &fninfo);
4706 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4707 if (shader->selector->info.uses_grid_size)
4708 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4709 if (shader->selector->info.uses_block_size)
4710 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4711
4712 for (i = 0; i < 3; i++) {
4713 ctx->param_block_id[i] = -1;
4714 if (shader->selector->info.uses_block_id[i])
4715 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4716 }
4717
4718 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4719 break;
4720 default:
4721 assert(0 && "unimplemented shader");
4722 return;
4723 }
4724
4725 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4726 si_get_max_workgroup_size(shader));
4727
4728 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4729 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4730 ctx->separate_prolog) {
4731 si_llvm_add_attribute(ctx->main_fn,
4732 "InitialPSInputAddr",
4733 S_0286D0_PERSP_SAMPLE_ENA(1) |
4734 S_0286D0_PERSP_CENTER_ENA(1) |
4735 S_0286D0_PERSP_CENTROID_ENA(1) |
4736 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4737 S_0286D0_LINEAR_CENTER_ENA(1) |
4738 S_0286D0_LINEAR_CENTROID_ENA(1) |
4739 S_0286D0_FRONT_FACE_ENA(1) |
4740 S_0286D0_ANCILLARY_ENA(1) |
4741 S_0286D0_POS_FIXED_PT_ENA(1));
4742 }
4743
4744 shader->info.num_input_sgprs = 0;
4745 shader->info.num_input_vgprs = 0;
4746
4747 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4748 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4749
4750 for (; i < fninfo.num_params; ++i)
4751 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4752
4753 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4754 shader->info.num_input_vgprs -= num_prolog_vgprs;
4755
4756 if (shader->key.as_ls ||
4757 ctx->type == PIPE_SHADER_TESS_CTRL ||
4758 /* GFX9 has the ESGS ring buffer in LDS. */
4759 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4760 ac_declare_lds_as_pointer(&ctx->ac);
4761 }
4762
4763 /**
4764 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4765 * for later use.
4766 */
4767 static void preload_ring_buffers(struct si_shader_context *ctx)
4768 {
4769 LLVMBuilderRef builder = ctx->ac.builder;
4770
4771 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4772 ctx->param_rw_buffers);
4773
4774 if (ctx->screen->info.chip_class <= VI &&
4775 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4776 unsigned ring =
4777 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4778 : SI_ES_RING_ESGS;
4779 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4780
4781 ctx->esgs_ring =
4782 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4783 }
4784
4785 if (ctx->shader->is_gs_copy_shader) {
4786 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4787
4788 ctx->gsvs_ring[0] =
4789 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4790 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4791 const struct si_shader_selector *sel = ctx->shader->selector;
4792 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4793 LLVMValueRef base_ring;
4794
4795 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4796
4797 /* The conceptual layout of the GSVS ring is
4798 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4799 * but the real memory layout is swizzled across
4800 * threads:
4801 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4802 * t16v0c0 ..
4803 * Override the buffer descriptor accordingly.
4804 */
4805 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4806 uint64_t stream_offset = 0;
4807
4808 for (unsigned stream = 0; stream < 4; ++stream) {
4809 unsigned num_components;
4810 unsigned stride;
4811 unsigned num_records;
4812 LLVMValueRef ring, tmp;
4813
4814 num_components = sel->info.num_stream_output_components[stream];
4815 if (!num_components)
4816 continue;
4817
4818 stride = 4 * num_components * sel->gs_max_out_vertices;
4819
4820 /* Limit on the stride field for <= CIK. */
4821 assert(stride < (1 << 14));
4822
4823 num_records = 64;
4824
4825 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4826 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4827 tmp = LLVMBuildAdd(builder, tmp,
4828 LLVMConstInt(ctx->i64,
4829 stream_offset, 0), "");
4830 stream_offset += stride * 64;
4831
4832 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4833 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4834 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4835 tmp = LLVMBuildOr(builder, tmp,
4836 LLVMConstInt(ctx->i32,
4837 S_008F04_STRIDE(stride) |
4838 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4839 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4840 ring = LLVMBuildInsertElement(builder, ring,
4841 LLVMConstInt(ctx->i32, num_records, 0),
4842 LLVMConstInt(ctx->i32, 2, 0), "");
4843 ring = LLVMBuildInsertElement(builder, ring,
4844 LLVMConstInt(ctx->i32,
4845 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4846 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4847 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4848 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4849 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4850 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4851 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4852 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4853 S_008F0C_ADD_TID_ENABLE(1),
4854 0),
4855 LLVMConstInt(ctx->i32, 3, 0), "");
4856
4857 ctx->gsvs_ring[stream] = ring;
4858 }
4859 }
4860 }
4861
4862 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4863 LLVMValueRef param_rw_buffers,
4864 unsigned param_pos_fixed_pt)
4865 {
4866 LLVMBuilderRef builder = ctx->ac.builder;
4867 LLVMValueRef slot, desc, offset, row, bit, address[2];
4868
4869 /* Use the fixed-point gl_FragCoord input.
4870 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4871 * per coordinate to get the repeating effect.
4872 */
4873 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4874 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4875
4876 /* Load the buffer descriptor. */
4877 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4878 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4879
4880 /* The stipple pattern is 32x32, each row has 32 bits. */
4881 offset = LLVMBuildMul(builder, address[1],
4882 LLVMConstInt(ctx->i32, 4, 0), "");
4883 row = buffer_load_const(ctx, desc, offset);
4884 row = ac_to_integer(&ctx->ac, row);
4885 bit = LLVMBuildLShr(builder, row, address[0], "");
4886 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4887 ac_build_kill_if_false(&ctx->ac, bit);
4888 }
4889
4890 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4891 struct si_shader_config *conf,
4892 unsigned symbol_offset)
4893 {
4894 unsigned i;
4895 const unsigned char *config =
4896 ac_shader_binary_config_start(binary, symbol_offset);
4897 bool really_needs_scratch = false;
4898
4899 /* LLVM adds SGPR spills to the scratch size.
4900 * Find out if we really need the scratch buffer.
4901 */
4902 for (i = 0; i < binary->reloc_count; i++) {
4903 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4904
4905 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4906 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4907 really_needs_scratch = true;
4908 break;
4909 }
4910 }
4911
4912 /* XXX: We may be able to emit some of these values directly rather than
4913 * extracting fields to be emitted later.
4914 */
4915
4916 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4917 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4918 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4919 switch (reg) {
4920 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4921 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4922 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4923 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4924 case R_00B848_COMPUTE_PGM_RSRC1:
4925 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4926 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4927 conf->float_mode = G_00B028_FLOAT_MODE(value);
4928 conf->rsrc1 = value;
4929 break;
4930 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4931 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4932 break;
4933 case R_00B84C_COMPUTE_PGM_RSRC2:
4934 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4935 conf->rsrc2 = value;
4936 break;
4937 case R_0286CC_SPI_PS_INPUT_ENA:
4938 conf->spi_ps_input_ena = value;
4939 break;
4940 case R_0286D0_SPI_PS_INPUT_ADDR:
4941 conf->spi_ps_input_addr = value;
4942 break;
4943 case R_0286E8_SPI_TMPRING_SIZE:
4944 case R_00B860_COMPUTE_TMPRING_SIZE:
4945 /* WAVESIZE is in units of 256 dwords. */
4946 if (really_needs_scratch)
4947 conf->scratch_bytes_per_wave =
4948 G_00B860_WAVESIZE(value) * 256 * 4;
4949 break;
4950 case 0x4: /* SPILLED_SGPRS */
4951 conf->spilled_sgprs = value;
4952 break;
4953 case 0x8: /* SPILLED_VGPRS */
4954 conf->spilled_vgprs = value;
4955 break;
4956 default:
4957 {
4958 static bool printed;
4959
4960 if (!printed) {
4961 fprintf(stderr, "Warning: LLVM emitted unknown "
4962 "config register: 0x%x\n", reg);
4963 printed = true;
4964 }
4965 }
4966 break;
4967 }
4968 }
4969
4970 if (!conf->spi_ps_input_addr)
4971 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4972 }
4973
4974 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4975 uint64_t scratch_va)
4976 {
4977 unsigned i;
4978 uint32_t scratch_rsrc_dword0 = scratch_va;
4979 uint32_t scratch_rsrc_dword1 =
4980 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4981
4982 /* Enable scratch coalescing. */
4983 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4984
4985 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4986 const struct ac_shader_reloc *reloc =
4987 &shader->binary.relocs[i];
4988 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4989 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4990 &scratch_rsrc_dword0, 4);
4991 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4992 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4993 &scratch_rsrc_dword1, 4);
4994 }
4995 }
4996 }
4997
4998 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4999 {
5000 unsigned size = shader->binary.code_size;
5001
5002 if (shader->prolog)
5003 size += shader->prolog->binary.code_size;
5004 if (shader->previous_stage)
5005 size += shader->previous_stage->binary.code_size;
5006 if (shader->prolog2)
5007 size += shader->prolog2->binary.code_size;
5008 if (shader->epilog)
5009 size += shader->epilog->binary.code_size;
5010 return size;
5011 }
5012
5013 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5014 {
5015 const struct ac_shader_binary *prolog =
5016 shader->prolog ? &shader->prolog->binary : NULL;
5017 const struct ac_shader_binary *previous_stage =
5018 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5019 const struct ac_shader_binary *prolog2 =
5020 shader->prolog2 ? &shader->prolog2->binary : NULL;
5021 const struct ac_shader_binary *epilog =
5022 shader->epilog ? &shader->epilog->binary : NULL;
5023 const struct ac_shader_binary *mainb = &shader->binary;
5024 unsigned bo_size = si_get_shader_binary_size(shader) +
5025 (!epilog ? mainb->rodata_size : 0);
5026 unsigned char *ptr;
5027
5028 assert(!prolog || !prolog->rodata_size);
5029 assert(!previous_stage || !previous_stage->rodata_size);
5030 assert(!prolog2 || !prolog2->rodata_size);
5031 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5032 !mainb->rodata_size);
5033 assert(!epilog || !epilog->rodata_size);
5034
5035 r600_resource_reference(&shader->bo, NULL);
5036 shader->bo = (struct r600_resource*)
5037 pipe_buffer_create(&sscreen->b, 0,
5038 PIPE_USAGE_IMMUTABLE,
5039 align(bo_size, SI_CPDMA_ALIGNMENT));
5040 if (!shader->bo)
5041 return -ENOMEM;
5042
5043 /* Upload. */
5044 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5045 PIPE_TRANSFER_READ_WRITE |
5046 PIPE_TRANSFER_UNSYNCHRONIZED);
5047
5048 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5049 * endian-independent. */
5050 if (prolog) {
5051 memcpy(ptr, prolog->code, prolog->code_size);
5052 ptr += prolog->code_size;
5053 }
5054 if (previous_stage) {
5055 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5056 ptr += previous_stage->code_size;
5057 }
5058 if (prolog2) {
5059 memcpy(ptr, prolog2->code, prolog2->code_size);
5060 ptr += prolog2->code_size;
5061 }
5062
5063 memcpy(ptr, mainb->code, mainb->code_size);
5064 ptr += mainb->code_size;
5065
5066 if (epilog)
5067 memcpy(ptr, epilog->code, epilog->code_size);
5068 else if (mainb->rodata_size > 0)
5069 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5070
5071 sscreen->ws->buffer_unmap(shader->bo->buf);
5072 return 0;
5073 }
5074
5075 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5076 struct pipe_debug_callback *debug,
5077 const char *name, FILE *file)
5078 {
5079 char *line, *p;
5080 unsigned i, count;
5081
5082 if (binary->disasm_string) {
5083 fprintf(file, "Shader %s disassembly:\n", name);
5084 fprintf(file, "%s", binary->disasm_string);
5085
5086 if (debug && debug->debug_message) {
5087 /* Very long debug messages are cut off, so send the
5088 * disassembly one line at a time. This causes more
5089 * overhead, but on the plus side it simplifies
5090 * parsing of resulting logs.
5091 */
5092 pipe_debug_message(debug, SHADER_INFO,
5093 "Shader Disassembly Begin");
5094
5095 line = binary->disasm_string;
5096 while (*line) {
5097 p = util_strchrnul(line, '\n');
5098 count = p - line;
5099
5100 if (count) {
5101 pipe_debug_message(debug, SHADER_INFO,
5102 "%.*s", count, line);
5103 }
5104
5105 if (!*p)
5106 break;
5107 line = p + 1;
5108 }
5109
5110 pipe_debug_message(debug, SHADER_INFO,
5111 "Shader Disassembly End");
5112 }
5113 } else {
5114 fprintf(file, "Shader %s binary:\n", name);
5115 for (i = 0; i < binary->code_size; i += 4) {
5116 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5117 binary->code[i + 3], binary->code[i + 2],
5118 binary->code[i + 1], binary->code[i]);
5119 }
5120 }
5121 }
5122
5123 static void si_shader_dump_stats(struct si_screen *sscreen,
5124 const struct si_shader *shader,
5125 struct pipe_debug_callback *debug,
5126 unsigned processor,
5127 FILE *file,
5128 bool check_debug_option)
5129 {
5130 const struct si_shader_config *conf = &shader->config;
5131 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5132 unsigned code_size = si_get_shader_binary_size(shader);
5133 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5134 unsigned lds_per_wave = 0;
5135 unsigned max_simd_waves;
5136
5137 switch (sscreen->info.family) {
5138 /* These always have 8 waves: */
5139 case CHIP_POLARIS10:
5140 case CHIP_POLARIS11:
5141 case CHIP_POLARIS12:
5142 max_simd_waves = 8;
5143 break;
5144 default:
5145 max_simd_waves = 10;
5146 }
5147
5148 /* Compute LDS usage for PS. */
5149 switch (processor) {
5150 case PIPE_SHADER_FRAGMENT:
5151 /* The minimum usage per wave is (num_inputs * 48). The maximum
5152 * usage is (num_inputs * 48 * 16).
5153 * We can get anything in between and it varies between waves.
5154 *
5155 * The 48 bytes per input for a single primitive is equal to
5156 * 4 bytes/component * 4 components/input * 3 points.
5157 *
5158 * Other stages don't know the size at compile time or don't
5159 * allocate LDS per wave, but instead they do it per thread group.
5160 */
5161 lds_per_wave = conf->lds_size * lds_increment +
5162 align(num_inputs * 48, lds_increment);
5163 break;
5164 case PIPE_SHADER_COMPUTE:
5165 if (shader->selector) {
5166 unsigned max_workgroup_size =
5167 si_get_max_workgroup_size(shader);
5168 lds_per_wave = (conf->lds_size * lds_increment) /
5169 DIV_ROUND_UP(max_workgroup_size, 64);
5170 }
5171 break;
5172 }
5173
5174 /* Compute the per-SIMD wave counts. */
5175 if (conf->num_sgprs) {
5176 if (sscreen->info.chip_class >= VI)
5177 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5178 else
5179 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5180 }
5181
5182 if (conf->num_vgprs)
5183 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5184
5185 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5186 * 16KB makes some SIMDs unoccupied). */
5187 if (lds_per_wave)
5188 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5189
5190 if (!check_debug_option ||
5191 si_can_dump_shader(sscreen, processor)) {
5192 if (processor == PIPE_SHADER_FRAGMENT) {
5193 fprintf(file, "*** SHADER CONFIG ***\n"
5194 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5195 "SPI_PS_INPUT_ENA = 0x%04x\n",
5196 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5197 }
5198
5199 fprintf(file, "*** SHADER STATS ***\n"
5200 "SGPRS: %d\n"
5201 "VGPRS: %d\n"
5202 "Spilled SGPRs: %d\n"
5203 "Spilled VGPRs: %d\n"
5204 "Private memory VGPRs: %d\n"
5205 "Code Size: %d bytes\n"
5206 "LDS: %d blocks\n"
5207 "Scratch: %d bytes per wave\n"
5208 "Max Waves: %d\n"
5209 "********************\n\n\n",
5210 conf->num_sgprs, conf->num_vgprs,
5211 conf->spilled_sgprs, conf->spilled_vgprs,
5212 conf->private_mem_vgprs, code_size,
5213 conf->lds_size, conf->scratch_bytes_per_wave,
5214 max_simd_waves);
5215 }
5216
5217 pipe_debug_message(debug, SHADER_INFO,
5218 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5219 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5220 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5221 conf->num_sgprs, conf->num_vgprs, code_size,
5222 conf->lds_size, conf->scratch_bytes_per_wave,
5223 max_simd_waves, conf->spilled_sgprs,
5224 conf->spilled_vgprs, conf->private_mem_vgprs);
5225 }
5226
5227 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5228 {
5229 switch (processor) {
5230 case PIPE_SHADER_VERTEX:
5231 if (shader->key.as_es)
5232 return "Vertex Shader as ES";
5233 else if (shader->key.as_ls)
5234 return "Vertex Shader as LS";
5235 else
5236 return "Vertex Shader as VS";
5237 case PIPE_SHADER_TESS_CTRL:
5238 return "Tessellation Control Shader";
5239 case PIPE_SHADER_TESS_EVAL:
5240 if (shader->key.as_es)
5241 return "Tessellation Evaluation Shader as ES";
5242 else
5243 return "Tessellation Evaluation Shader as VS";
5244 case PIPE_SHADER_GEOMETRY:
5245 if (shader->is_gs_copy_shader)
5246 return "GS Copy Shader as VS";
5247 else
5248 return "Geometry Shader";
5249 case PIPE_SHADER_FRAGMENT:
5250 return "Pixel Shader";
5251 case PIPE_SHADER_COMPUTE:
5252 return "Compute Shader";
5253 default:
5254 return "Unknown Shader";
5255 }
5256 }
5257
5258 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5259 struct pipe_debug_callback *debug, unsigned processor,
5260 FILE *file, bool check_debug_option)
5261 {
5262 if (!check_debug_option ||
5263 si_can_dump_shader(sscreen, processor))
5264 si_dump_shader_key(processor, shader, file);
5265
5266 if (!check_debug_option && shader->binary.llvm_ir_string) {
5267 if (shader->previous_stage &&
5268 shader->previous_stage->binary.llvm_ir_string) {
5269 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5270 si_get_shader_name(shader, processor));
5271 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5272 }
5273
5274 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5275 si_get_shader_name(shader, processor));
5276 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5277 }
5278
5279 if (!check_debug_option ||
5280 (si_can_dump_shader(sscreen, processor) &&
5281 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5282 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5283
5284 if (shader->prolog)
5285 si_shader_dump_disassembly(&shader->prolog->binary,
5286 debug, "prolog", file);
5287 if (shader->previous_stage)
5288 si_shader_dump_disassembly(&shader->previous_stage->binary,
5289 debug, "previous stage", file);
5290 if (shader->prolog2)
5291 si_shader_dump_disassembly(&shader->prolog2->binary,
5292 debug, "prolog2", file);
5293
5294 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5295
5296 if (shader->epilog)
5297 si_shader_dump_disassembly(&shader->epilog->binary,
5298 debug, "epilog", file);
5299 fprintf(file, "\n");
5300 }
5301
5302 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5303 check_debug_option);
5304 }
5305
5306 static int si_compile_llvm(struct si_screen *sscreen,
5307 struct ac_shader_binary *binary,
5308 struct si_shader_config *conf,
5309 LLVMTargetMachineRef tm,
5310 LLVMModuleRef mod,
5311 struct pipe_debug_callback *debug,
5312 unsigned processor,
5313 const char *name)
5314 {
5315 int r = 0;
5316 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5317
5318 if (si_can_dump_shader(sscreen, processor)) {
5319 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5320
5321 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5322 fprintf(stderr, "%s LLVM IR:\n\n", name);
5323 ac_dump_module(mod);
5324 fprintf(stderr, "\n");
5325 }
5326 }
5327
5328 if (sscreen->record_llvm_ir) {
5329 char *ir = LLVMPrintModuleToString(mod);
5330 binary->llvm_ir_string = strdup(ir);
5331 LLVMDisposeMessage(ir);
5332 }
5333
5334 if (!si_replace_shader(count, binary)) {
5335 r = si_llvm_compile(mod, binary, tm, debug);
5336 if (r)
5337 return r;
5338 }
5339
5340 si_shader_binary_read_config(binary, conf, 0);
5341
5342 /* Enable 64-bit and 16-bit denormals, because there is no performance
5343 * cost.
5344 *
5345 * If denormals are enabled, all floating-point output modifiers are
5346 * ignored.
5347 *
5348 * Don't enable denormals for 32-bit floats, because:
5349 * - Floating-point output modifiers would be ignored by the hw.
5350 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5351 * have to stop using those.
5352 * - SI & CI would be very slow.
5353 */
5354 conf->float_mode |= V_00B028_FP_64_DENORMS;
5355
5356 FREE(binary->config);
5357 FREE(binary->global_symbol_offsets);
5358 binary->config = NULL;
5359 binary->global_symbol_offsets = NULL;
5360
5361 /* Some shaders can't have rodata because their binaries can be
5362 * concatenated.
5363 */
5364 if (binary->rodata_size &&
5365 (processor == PIPE_SHADER_VERTEX ||
5366 processor == PIPE_SHADER_TESS_CTRL ||
5367 processor == PIPE_SHADER_TESS_EVAL ||
5368 processor == PIPE_SHADER_FRAGMENT)) {
5369 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5370 return -EINVAL;
5371 }
5372
5373 return r;
5374 }
5375
5376 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5377 {
5378 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5379 LLVMBuildRetVoid(ctx->ac.builder);
5380 else
5381 LLVMBuildRet(ctx->ac.builder, ret);
5382 }
5383
5384 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5385 struct si_shader *
5386 si_generate_gs_copy_shader(struct si_screen *sscreen,
5387 LLVMTargetMachineRef tm,
5388 struct si_shader_selector *gs_selector,
5389 struct pipe_debug_callback *debug)
5390 {
5391 struct si_shader_context ctx;
5392 struct si_shader *shader;
5393 LLVMBuilderRef builder;
5394 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5395 struct lp_build_context *uint = &bld_base->uint_bld;
5396 struct si_shader_output_values *outputs;
5397 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5398 int i, r;
5399
5400 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5401
5402 if (!outputs)
5403 return NULL;
5404
5405 shader = CALLOC_STRUCT(si_shader);
5406 if (!shader) {
5407 FREE(outputs);
5408 return NULL;
5409 }
5410
5411 /* We can leave the fence as permanently signaled because the GS copy
5412 * shader only becomes visible globally after it has been compiled. */
5413 util_queue_fence_init(&shader->ready);
5414
5415 shader->selector = gs_selector;
5416 shader->is_gs_copy_shader = true;
5417
5418 si_init_shader_ctx(&ctx, sscreen, tm);
5419 ctx.shader = shader;
5420 ctx.type = PIPE_SHADER_VERTEX;
5421
5422 builder = ctx.ac.builder;
5423
5424 create_function(&ctx);
5425 preload_ring_buffers(&ctx);
5426
5427 LLVMValueRef voffset =
5428 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5429
5430 /* Fetch the vertex stream ID.*/
5431 LLVMValueRef stream_id;
5432
5433 if (gs_selector->so.num_outputs)
5434 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5435 else
5436 stream_id = ctx.i32_0;
5437
5438 /* Fill in output information. */
5439 for (i = 0; i < gsinfo->num_outputs; ++i) {
5440 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5441 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5442
5443 for (int chan = 0; chan < 4; chan++) {
5444 outputs[i].vertex_stream[chan] =
5445 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5446 }
5447 }
5448
5449 LLVMBasicBlockRef end_bb;
5450 LLVMValueRef switch_inst;
5451
5452 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5453 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5454
5455 for (int stream = 0; stream < 4; stream++) {
5456 LLVMBasicBlockRef bb;
5457 unsigned offset;
5458
5459 if (!gsinfo->num_stream_output_components[stream])
5460 continue;
5461
5462 if (stream > 0 && !gs_selector->so.num_outputs)
5463 continue;
5464
5465 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5466 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5467 LLVMPositionBuilderAtEnd(builder, bb);
5468
5469 /* Fetch vertex data from GSVS ring */
5470 offset = 0;
5471 for (i = 0; i < gsinfo->num_outputs; ++i) {
5472 for (unsigned chan = 0; chan < 4; chan++) {
5473 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5474 outputs[i].vertex_stream[chan] != stream) {
5475 outputs[i].values[chan] = ctx.bld_base.base.undef;
5476 continue;
5477 }
5478
5479 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5480 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5481 offset++;
5482
5483 outputs[i].values[chan] =
5484 ac_build_buffer_load(&ctx.ac,
5485 ctx.gsvs_ring[0], 1,
5486 ctx.i32_0, voffset,
5487 soffset, 0, 1, 1,
5488 true, false);
5489 }
5490 }
5491
5492 /* Streamout and exports. */
5493 if (gs_selector->so.num_outputs) {
5494 si_llvm_emit_streamout(&ctx, outputs,
5495 gsinfo->num_outputs,
5496 stream);
5497 }
5498
5499 if (stream == 0)
5500 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5501
5502 LLVMBuildBr(builder, end_bb);
5503 }
5504
5505 LLVMPositionBuilderAtEnd(builder, end_bb);
5506
5507 LLVMBuildRetVoid(ctx.ac.builder);
5508
5509 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5510 si_llvm_optimize_module(&ctx);
5511
5512 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5513 &ctx.shader->config, ctx.tm,
5514 ctx.gallivm.module,
5515 debug, PIPE_SHADER_GEOMETRY,
5516 "GS Copy Shader");
5517 if (!r) {
5518 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5519 fprintf(stderr, "GS Copy Shader:\n");
5520 si_shader_dump(sscreen, ctx.shader, debug,
5521 PIPE_SHADER_GEOMETRY, stderr, true);
5522 r = si_shader_binary_upload(sscreen, ctx.shader);
5523 }
5524
5525 si_llvm_dispose(&ctx);
5526
5527 FREE(outputs);
5528
5529 if (r != 0) {
5530 FREE(shader);
5531 shader = NULL;
5532 }
5533 return shader;
5534 }
5535
5536 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5537 const struct si_vs_prolog_bits *prolog,
5538 const char *prefix, FILE *f)
5539 {
5540 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5541 prefix, prolog->instance_divisor_is_one);
5542 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5543 prefix, prolog->instance_divisor_is_fetched);
5544 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5545 prefix, prolog->ls_vgpr_fix);
5546
5547 fprintf(f, " mono.vs.fix_fetch = {");
5548 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5549 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5550 fprintf(f, "}\n");
5551 }
5552
5553 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5554 FILE *f)
5555 {
5556 const struct si_shader_key *key = &shader->key;
5557
5558 fprintf(f, "SHADER KEY\n");
5559
5560 switch (processor) {
5561 case PIPE_SHADER_VERTEX:
5562 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5563 "part.vs.prolog", f);
5564 fprintf(f, " as_es = %u\n", key->as_es);
5565 fprintf(f, " as_ls = %u\n", key->as_ls);
5566 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5567 key->mono.u.vs_export_prim_id);
5568 break;
5569
5570 case PIPE_SHADER_TESS_CTRL:
5571 if (shader->selector->screen->info.chip_class >= GFX9) {
5572 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5573 "part.tcs.ls_prolog", f);
5574 }
5575 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5576 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5577 break;
5578
5579 case PIPE_SHADER_TESS_EVAL:
5580 fprintf(f, " as_es = %u\n", key->as_es);
5581 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5582 key->mono.u.vs_export_prim_id);
5583 break;
5584
5585 case PIPE_SHADER_GEOMETRY:
5586 if (shader->is_gs_copy_shader)
5587 break;
5588
5589 if (shader->selector->screen->info.chip_class >= GFX9 &&
5590 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5591 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5592 "part.gs.vs_prolog", f);
5593 }
5594 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5595 break;
5596
5597 case PIPE_SHADER_COMPUTE:
5598 break;
5599
5600 case PIPE_SHADER_FRAGMENT:
5601 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5602 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5603 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5604 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5605 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5606 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5607 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5608 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5609 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5610 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5611 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5612 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5613 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5614 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5615 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5616 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5617 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5618 break;
5619
5620 default:
5621 assert(0);
5622 }
5623
5624 if ((processor == PIPE_SHADER_GEOMETRY ||
5625 processor == PIPE_SHADER_TESS_EVAL ||
5626 processor == PIPE_SHADER_VERTEX) &&
5627 !key->as_es && !key->as_ls) {
5628 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5629 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5630 }
5631 }
5632
5633 static void si_init_shader_ctx(struct si_shader_context *ctx,
5634 struct si_screen *sscreen,
5635 LLVMTargetMachineRef tm)
5636 {
5637 struct lp_build_tgsi_context *bld_base;
5638
5639 si_llvm_context_init(ctx, sscreen, tm);
5640
5641 bld_base = &ctx->bld_base;
5642 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5643
5644 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5645 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5646 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5647
5648 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5649
5650 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5651
5652 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5653 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5654 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5655 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5656
5657 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5658 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5659 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5660 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5661 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5662 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5663 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5664 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5665 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5666
5667 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5668 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5669 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5670 }
5671
5672 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5673 {
5674 struct si_shader *shader = ctx->shader;
5675 struct tgsi_shader_info *info = &shader->selector->info;
5676
5677 if ((ctx->type != PIPE_SHADER_VERTEX &&
5678 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5679 shader->key.as_ls ||
5680 shader->key.as_es)
5681 return;
5682
5683 ac_optimize_vs_outputs(&ctx->ac,
5684 ctx->main_fn,
5685 shader->info.vs_output_param_offset,
5686 info->num_outputs,
5687 &shader->info.nr_param_exports);
5688 }
5689
5690 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5691 {
5692 ctx->shader->config.private_mem_vgprs = 0;
5693
5694 /* Process all LLVM instructions. */
5695 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5696 while (bb) {
5697 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5698
5699 while (next) {
5700 LLVMValueRef inst = next;
5701 next = LLVMGetNextInstruction(next);
5702
5703 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5704 continue;
5705
5706 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5707 /* No idea why LLVM aligns allocas to 4 elements. */
5708 unsigned alignment = LLVMGetAlignment(inst);
5709 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5710 ctx->shader->config.private_mem_vgprs += dw_size;
5711 }
5712 bb = LLVMGetNextBasicBlock(bb);
5713 }
5714 }
5715
5716 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5717 {
5718 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5719 lp_build_intrinsic(ctx->ac.builder,
5720 "llvm.amdgcn.init.exec", ctx->voidt,
5721 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5722 }
5723
5724 static void si_init_exec_from_input(struct si_shader_context *ctx,
5725 unsigned param, unsigned bitoffset)
5726 {
5727 LLVMValueRef args[] = {
5728 LLVMGetParam(ctx->main_fn, param),
5729 LLVMConstInt(ctx->i32, bitoffset, 0),
5730 };
5731 lp_build_intrinsic(ctx->ac.builder,
5732 "llvm.amdgcn.init.exec.from.input",
5733 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5734 }
5735
5736 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5737 const struct si_vs_prolog_bits *key)
5738 {
5739 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5740 * VS prolog. */
5741 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5742 }
5743
5744 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5745 bool is_monolithic)
5746 {
5747 struct si_shader *shader = ctx->shader;
5748 struct si_shader_selector *sel = shader->selector;
5749 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5750
5751 // TODO clean all this up!
5752 switch (ctx->type) {
5753 case PIPE_SHADER_VERTEX:
5754 ctx->load_input = declare_input_vs;
5755 if (shader->key.as_ls)
5756 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5757 else if (shader->key.as_es)
5758 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5759 else
5760 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5761 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5762 break;
5763 case PIPE_SHADER_TESS_CTRL:
5764 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5765 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5766 bld_base->emit_store = store_output_tcs;
5767 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5768 break;
5769 case PIPE_SHADER_TESS_EVAL:
5770 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5771 if (shader->key.as_es)
5772 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5773 else
5774 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5775 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5776 break;
5777 case PIPE_SHADER_GEOMETRY:
5778 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5779 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5780 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5781 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5782 break;
5783 case PIPE_SHADER_FRAGMENT:
5784 ctx->load_input = declare_input_fs;
5785 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5786 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5787 break;
5788 case PIPE_SHADER_COMPUTE:
5789 break;
5790 default:
5791 assert(!"Unsupported shader type");
5792 return false;
5793 }
5794
5795 ctx->abi.load_ubo = load_ubo;
5796 ctx->abi.load_ssbo = load_ssbo;
5797
5798 create_function(ctx);
5799 preload_ring_buffers(ctx);
5800
5801 /* For GFX9 merged shaders:
5802 * - Set EXEC for the first shader. If the prolog is present, set
5803 * EXEC there instead.
5804 * - Add a barrier before the second shader.
5805 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5806 * an if-statement. This is required for correctness in geometry
5807 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5808 * GS_CUT messages.
5809 *
5810 * For monolithic merged shaders, the first shader is wrapped in an
5811 * if-block together with its prolog in si_build_wrapper_function.
5812 */
5813 if (ctx->screen->info.chip_class >= GFX9) {
5814 if (!is_monolithic &&
5815 sel->info.num_instructions > 1 && /* not empty shader */
5816 (shader->key.as_es || shader->key.as_ls) &&
5817 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5818 (ctx->type == PIPE_SHADER_VERTEX &&
5819 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5820 si_init_exec_from_input(ctx,
5821 ctx->param_merged_wave_info, 0);
5822 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5823 ctx->type == PIPE_SHADER_GEOMETRY) {
5824 if (!is_monolithic)
5825 si_init_exec_full_mask(ctx);
5826
5827 /* The barrier must execute for all shaders in a
5828 * threadgroup.
5829 */
5830 si_llvm_emit_barrier(NULL, bld_base, NULL);
5831
5832 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5833 LLVMValueRef ena =
5834 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5835 ac_get_thread_id(&ctx->ac), num_threads, "");
5836 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5837 }
5838 }
5839
5840 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5841 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5842 for (unsigned i = 0; i < 6; i++) {
5843 ctx->invoc0_tess_factors[i] =
5844 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5845 }
5846 }
5847
5848 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5849 int i;
5850 for (i = 0; i < 4; i++) {
5851 ctx->gs_next_vertex[i] =
5852 lp_build_alloca(&ctx->gallivm,
5853 ctx->i32, "");
5854 }
5855 }
5856
5857 if (sel->force_correct_derivs_after_kill) {
5858 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5859 /* true = don't kill. */
5860 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5861 ctx->postponed_kill);
5862 }
5863
5864 if (sel->tokens) {
5865 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5866 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5867 return false;
5868 }
5869 } else {
5870 if (!si_nir_build_llvm(ctx, sel->nir)) {
5871 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5872 return false;
5873 }
5874 }
5875
5876 si_llvm_build_ret(ctx, ctx->return_value);
5877 return true;
5878 }
5879
5880 /**
5881 * Compute the VS prolog key, which contains all the information needed to
5882 * build the VS prolog function, and set shader->info bits where needed.
5883 *
5884 * \param info Shader info of the vertex shader.
5885 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5886 * \param prolog_key Key of the VS prolog
5887 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5888 * \param key Output shader part key.
5889 */
5890 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5891 unsigned num_input_sgprs,
5892 const struct si_vs_prolog_bits *prolog_key,
5893 struct si_shader *shader_out,
5894 union si_shader_part_key *key)
5895 {
5896 memset(key, 0, sizeof(*key));
5897 key->vs_prolog.states = *prolog_key;
5898 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5899 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5900 key->vs_prolog.as_ls = shader_out->key.as_ls;
5901 key->vs_prolog.as_es = shader_out->key.as_es;
5902
5903 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5904 key->vs_prolog.as_ls = 1;
5905 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5906 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5907 key->vs_prolog.as_es = 1;
5908 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5909 }
5910
5911 /* Enable loading the InstanceID VGPR. */
5912 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5913
5914 if ((key->vs_prolog.states.instance_divisor_is_one |
5915 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5916 shader_out->info.uses_instanceid = true;
5917 }
5918
5919 /**
5920 * Compute the PS prolog key, which contains all the information needed to
5921 * build the PS prolog function, and set related bits in shader->config.
5922 */
5923 static void si_get_ps_prolog_key(struct si_shader *shader,
5924 union si_shader_part_key *key,
5925 bool separate_prolog)
5926 {
5927 struct tgsi_shader_info *info = &shader->selector->info;
5928
5929 memset(key, 0, sizeof(*key));
5930 key->ps_prolog.states = shader->key.part.ps.prolog;
5931 key->ps_prolog.colors_read = info->colors_read;
5932 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5933 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5934 key->ps_prolog.wqm = info->uses_derivatives &&
5935 (key->ps_prolog.colors_read ||
5936 key->ps_prolog.states.force_persp_sample_interp ||
5937 key->ps_prolog.states.force_linear_sample_interp ||
5938 key->ps_prolog.states.force_persp_center_interp ||
5939 key->ps_prolog.states.force_linear_center_interp ||
5940 key->ps_prolog.states.bc_optimize_for_persp ||
5941 key->ps_prolog.states.bc_optimize_for_linear);
5942 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5943
5944 if (info->colors_read) {
5945 unsigned *color = shader->selector->color_attr_index;
5946
5947 if (shader->key.part.ps.prolog.color_two_side) {
5948 /* BCOLORs are stored after the last input. */
5949 key->ps_prolog.num_interp_inputs = info->num_inputs;
5950 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5951 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5952 }
5953
5954 for (unsigned i = 0; i < 2; i++) {
5955 unsigned interp = info->input_interpolate[color[i]];
5956 unsigned location = info->input_interpolate_loc[color[i]];
5957
5958 if (!(info->colors_read & (0xf << i*4)))
5959 continue;
5960
5961 key->ps_prolog.color_attr_index[i] = color[i];
5962
5963 if (shader->key.part.ps.prolog.flatshade_colors &&
5964 interp == TGSI_INTERPOLATE_COLOR)
5965 interp = TGSI_INTERPOLATE_CONSTANT;
5966
5967 switch (interp) {
5968 case TGSI_INTERPOLATE_CONSTANT:
5969 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5970 break;
5971 case TGSI_INTERPOLATE_PERSPECTIVE:
5972 case TGSI_INTERPOLATE_COLOR:
5973 /* Force the interpolation location for colors here. */
5974 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5975 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5976 if (shader->key.part.ps.prolog.force_persp_center_interp)
5977 location = TGSI_INTERPOLATE_LOC_CENTER;
5978
5979 switch (location) {
5980 case TGSI_INTERPOLATE_LOC_SAMPLE:
5981 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5982 shader->config.spi_ps_input_ena |=
5983 S_0286CC_PERSP_SAMPLE_ENA(1);
5984 break;
5985 case TGSI_INTERPOLATE_LOC_CENTER:
5986 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5987 shader->config.spi_ps_input_ena |=
5988 S_0286CC_PERSP_CENTER_ENA(1);
5989 break;
5990 case TGSI_INTERPOLATE_LOC_CENTROID:
5991 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5992 shader->config.spi_ps_input_ena |=
5993 S_0286CC_PERSP_CENTROID_ENA(1);
5994 break;
5995 default:
5996 assert(0);
5997 }
5998 break;
5999 case TGSI_INTERPOLATE_LINEAR:
6000 /* Force the interpolation location for colors here. */
6001 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6002 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6003 if (shader->key.part.ps.prolog.force_linear_center_interp)
6004 location = TGSI_INTERPOLATE_LOC_CENTER;
6005
6006 /* The VGPR assignment for non-monolithic shaders
6007 * works because InitialPSInputAddr is set on the
6008 * main shader and PERSP_PULL_MODEL is never used.
6009 */
6010 switch (location) {
6011 case TGSI_INTERPOLATE_LOC_SAMPLE:
6012 key->ps_prolog.color_interp_vgpr_index[i] =
6013 separate_prolog ? 6 : 9;
6014 shader->config.spi_ps_input_ena |=
6015 S_0286CC_LINEAR_SAMPLE_ENA(1);
6016 break;
6017 case TGSI_INTERPOLATE_LOC_CENTER:
6018 key->ps_prolog.color_interp_vgpr_index[i] =
6019 separate_prolog ? 8 : 11;
6020 shader->config.spi_ps_input_ena |=
6021 S_0286CC_LINEAR_CENTER_ENA(1);
6022 break;
6023 case TGSI_INTERPOLATE_LOC_CENTROID:
6024 key->ps_prolog.color_interp_vgpr_index[i] =
6025 separate_prolog ? 10 : 13;
6026 shader->config.spi_ps_input_ena |=
6027 S_0286CC_LINEAR_CENTROID_ENA(1);
6028 break;
6029 default:
6030 assert(0);
6031 }
6032 break;
6033 default:
6034 assert(0);
6035 }
6036 }
6037 }
6038 }
6039
6040 /**
6041 * Check whether a PS prolog is required based on the key.
6042 */
6043 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6044 {
6045 return key->ps_prolog.colors_read ||
6046 key->ps_prolog.states.force_persp_sample_interp ||
6047 key->ps_prolog.states.force_linear_sample_interp ||
6048 key->ps_prolog.states.force_persp_center_interp ||
6049 key->ps_prolog.states.force_linear_center_interp ||
6050 key->ps_prolog.states.bc_optimize_for_persp ||
6051 key->ps_prolog.states.bc_optimize_for_linear ||
6052 key->ps_prolog.states.poly_stipple ||
6053 key->ps_prolog.states.samplemask_log_ps_iter;
6054 }
6055
6056 /**
6057 * Compute the PS epilog key, which contains all the information needed to
6058 * build the PS epilog function.
6059 */
6060 static void si_get_ps_epilog_key(struct si_shader *shader,
6061 union si_shader_part_key *key)
6062 {
6063 struct tgsi_shader_info *info = &shader->selector->info;
6064 memset(key, 0, sizeof(*key));
6065 key->ps_epilog.colors_written = info->colors_written;
6066 key->ps_epilog.writes_z = info->writes_z;
6067 key->ps_epilog.writes_stencil = info->writes_stencil;
6068 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6069 key->ps_epilog.states = shader->key.part.ps.epilog;
6070 }
6071
6072 /**
6073 * Build the GS prolog function. Rotate the input vertices for triangle strips
6074 * with adjacency.
6075 */
6076 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6077 union si_shader_part_key *key)
6078 {
6079 unsigned num_sgprs, num_vgprs;
6080 struct si_function_info fninfo;
6081 LLVMBuilderRef builder = ctx->ac.builder;
6082 LLVMTypeRef returns[48];
6083 LLVMValueRef func, ret;
6084
6085 si_init_function_info(&fninfo);
6086
6087 if (ctx->screen->info.chip_class >= GFX9) {
6088 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6089 num_vgprs = 5; /* ES inputs are not needed by GS */
6090 } else {
6091 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6092 num_vgprs = 8;
6093 }
6094
6095 for (unsigned i = 0; i < num_sgprs; ++i) {
6096 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6097 returns[i] = ctx->i32;
6098 }
6099
6100 for (unsigned i = 0; i < num_vgprs; ++i) {
6101 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6102 returns[num_sgprs + i] = ctx->f32;
6103 }
6104
6105 /* Create the function. */
6106 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6107 &fninfo, 0);
6108 func = ctx->main_fn;
6109
6110 /* Set the full EXEC mask for the prolog, because we are only fiddling
6111 * with registers here. The main shader part will set the correct EXEC
6112 * mask.
6113 */
6114 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6115 si_init_exec_full_mask(ctx);
6116
6117 /* Copy inputs to outputs. This should be no-op, as the registers match,
6118 * but it will prevent the compiler from overwriting them unintentionally.
6119 */
6120 ret = ctx->return_value;
6121 for (unsigned i = 0; i < num_sgprs; i++) {
6122 LLVMValueRef p = LLVMGetParam(func, i);
6123 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6124 }
6125 for (unsigned i = 0; i < num_vgprs; i++) {
6126 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6127 p = ac_to_float(&ctx->ac, p);
6128 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6129 }
6130
6131 if (key->gs_prolog.states.tri_strip_adj_fix) {
6132 /* Remap the input vertices for every other primitive. */
6133 const unsigned gfx6_vtx_params[6] = {
6134 num_sgprs,
6135 num_sgprs + 1,
6136 num_sgprs + 3,
6137 num_sgprs + 4,
6138 num_sgprs + 5,
6139 num_sgprs + 6
6140 };
6141 const unsigned gfx9_vtx_params[3] = {
6142 num_sgprs,
6143 num_sgprs + 1,
6144 num_sgprs + 4,
6145 };
6146 LLVMValueRef vtx_in[6], vtx_out[6];
6147 LLVMValueRef prim_id, rotate;
6148
6149 if (ctx->screen->info.chip_class >= GFX9) {
6150 for (unsigned i = 0; i < 3; i++) {
6151 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6152 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6153 }
6154 } else {
6155 for (unsigned i = 0; i < 6; i++)
6156 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6157 }
6158
6159 prim_id = LLVMGetParam(func, num_sgprs + 2);
6160 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6161
6162 for (unsigned i = 0; i < 6; ++i) {
6163 LLVMValueRef base, rotated;
6164 base = vtx_in[i];
6165 rotated = vtx_in[(i + 4) % 6];
6166 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6167 }
6168
6169 if (ctx->screen->info.chip_class >= GFX9) {
6170 for (unsigned i = 0; i < 3; i++) {
6171 LLVMValueRef hi, out;
6172
6173 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6174 LLVMConstInt(ctx->i32, 16, 0), "");
6175 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6176 out = ac_to_float(&ctx->ac, out);
6177 ret = LLVMBuildInsertValue(builder, ret, out,
6178 gfx9_vtx_params[i], "");
6179 }
6180 } else {
6181 for (unsigned i = 0; i < 6; i++) {
6182 LLVMValueRef out;
6183
6184 out = ac_to_float(&ctx->ac, vtx_out[i]);
6185 ret = LLVMBuildInsertValue(builder, ret, out,
6186 gfx6_vtx_params[i], "");
6187 }
6188 }
6189 }
6190
6191 LLVMBuildRet(builder, ret);
6192 }
6193
6194 /**
6195 * Given a list of shader part functions, build a wrapper function that
6196 * runs them in sequence to form a monolithic shader.
6197 */
6198 static void si_build_wrapper_function(struct si_shader_context *ctx,
6199 LLVMValueRef *parts,
6200 unsigned num_parts,
6201 unsigned main_part,
6202 unsigned next_shader_first_part)
6203 {
6204 LLVMBuilderRef builder = ctx->ac.builder;
6205 /* PS epilog has one arg per color component; gfx9 merged shader
6206 * prologs need to forward 32 user SGPRs.
6207 */
6208 struct si_function_info fninfo;
6209 LLVMValueRef initial[64], out[64];
6210 LLVMTypeRef function_type;
6211 unsigned num_first_params;
6212 unsigned num_out, initial_num_out;
6213 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6214 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6215 unsigned num_sgprs, num_vgprs;
6216 unsigned gprs;
6217 struct lp_build_if_state if_state;
6218
6219 si_init_function_info(&fninfo);
6220
6221 for (unsigned i = 0; i < num_parts; ++i) {
6222 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6223 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6224 }
6225
6226 /* The parameters of the wrapper function correspond to those of the
6227 * first part in terms of SGPRs and VGPRs, but we use the types of the
6228 * main part to get the right types. This is relevant for the
6229 * dereferenceable attribute on descriptor table pointers.
6230 */
6231 num_sgprs = 0;
6232 num_vgprs = 0;
6233
6234 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6235 num_first_params = LLVMCountParamTypes(function_type);
6236
6237 for (unsigned i = 0; i < num_first_params; ++i) {
6238 LLVMValueRef param = LLVMGetParam(parts[0], i);
6239
6240 if (ac_is_sgpr_param(param)) {
6241 assert(num_vgprs == 0);
6242 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6243 } else {
6244 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6245 }
6246 }
6247
6248 gprs = 0;
6249 while (gprs < num_sgprs + num_vgprs) {
6250 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6251 LLVMTypeRef type = LLVMTypeOf(param);
6252 unsigned size = ac_get_type_size(type) / 4;
6253
6254 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6255
6256 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6257 assert(gprs + size <= num_sgprs + num_vgprs &&
6258 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6259
6260 gprs += size;
6261 }
6262
6263 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6264 si_get_max_workgroup_size(ctx->shader));
6265
6266 if (is_merged_shader(ctx->shader))
6267 si_init_exec_full_mask(ctx);
6268
6269 /* Record the arguments of the function as if they were an output of
6270 * a previous part.
6271 */
6272 num_out = 0;
6273 num_out_sgpr = 0;
6274
6275 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6276 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6277 LLVMTypeRef param_type = LLVMTypeOf(param);
6278 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6279 unsigned size = ac_get_type_size(param_type) / 4;
6280
6281 if (size == 1) {
6282 if (param_type != out_type)
6283 param = LLVMBuildBitCast(builder, param, out_type, "");
6284 out[num_out++] = param;
6285 } else {
6286 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6287
6288 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6289 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6290 param_type = ctx->i64;
6291 }
6292
6293 if (param_type != vector_type)
6294 param = LLVMBuildBitCast(builder, param, vector_type, "");
6295
6296 for (unsigned j = 0; j < size; ++j)
6297 out[num_out++] = LLVMBuildExtractElement(
6298 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6299 }
6300
6301 if (i < fninfo.num_sgpr_params)
6302 num_out_sgpr = num_out;
6303 }
6304
6305 memcpy(initial, out, sizeof(out));
6306 initial_num_out = num_out;
6307 initial_num_out_sgpr = num_out_sgpr;
6308
6309 /* Now chain the parts. */
6310 for (unsigned part = 0; part < num_parts; ++part) {
6311 LLVMValueRef in[48];
6312 LLVMValueRef ret;
6313 LLVMTypeRef ret_type;
6314 unsigned out_idx = 0;
6315 unsigned num_params = LLVMCountParams(parts[part]);
6316
6317 /* Merged shaders are executed conditionally depending
6318 * on the number of enabled threads passed in the input SGPRs. */
6319 if (is_merged_shader(ctx->shader) && part == 0) {
6320 LLVMValueRef ena, count = initial[3];
6321
6322 count = LLVMBuildAnd(builder, count,
6323 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6324 ena = LLVMBuildICmp(builder, LLVMIntULT,
6325 ac_get_thread_id(&ctx->ac), count, "");
6326 lp_build_if(&if_state, &ctx->gallivm, ena);
6327 }
6328
6329 /* Derive arguments for the next part from outputs of the
6330 * previous one.
6331 */
6332 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6333 LLVMValueRef param;
6334 LLVMTypeRef param_type;
6335 bool is_sgpr;
6336 unsigned param_size;
6337 LLVMValueRef arg = NULL;
6338
6339 param = LLVMGetParam(parts[part], param_idx);
6340 param_type = LLVMTypeOf(param);
6341 param_size = ac_get_type_size(param_type) / 4;
6342 is_sgpr = ac_is_sgpr_param(param);
6343
6344 if (is_sgpr) {
6345 #if HAVE_LLVM < 0x0400
6346 LLVMRemoveAttribute(param, LLVMByValAttribute);
6347 #else
6348 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6349 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6350 #endif
6351 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6352 }
6353
6354 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6355 assert(is_sgpr || out_idx >= num_out_sgpr);
6356
6357 if (param_size == 1)
6358 arg = out[out_idx];
6359 else
6360 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6361
6362 if (LLVMTypeOf(arg) != param_type) {
6363 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6364 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6365 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6366 } else {
6367 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6368 }
6369 }
6370
6371 in[param_idx] = arg;
6372 out_idx += param_size;
6373 }
6374
6375 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6376
6377 if (is_merged_shader(ctx->shader) &&
6378 part + 1 == next_shader_first_part) {
6379 lp_build_endif(&if_state);
6380
6381 /* The second half of the merged shader should use
6382 * the inputs from the toplevel (wrapper) function,
6383 * not the return value from the last call.
6384 *
6385 * That's because the last call was executed condi-
6386 * tionally, so we can't consume it in the main
6387 * block.
6388 */
6389 memcpy(out, initial, sizeof(initial));
6390 num_out = initial_num_out;
6391 num_out_sgpr = initial_num_out_sgpr;
6392 continue;
6393 }
6394
6395 /* Extract the returned GPRs. */
6396 ret_type = LLVMTypeOf(ret);
6397 num_out = 0;
6398 num_out_sgpr = 0;
6399
6400 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6401 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6402
6403 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6404
6405 for (unsigned i = 0; i < ret_size; ++i) {
6406 LLVMValueRef val =
6407 LLVMBuildExtractValue(builder, ret, i, "");
6408
6409 assert(num_out < ARRAY_SIZE(out));
6410 out[num_out++] = val;
6411
6412 if (LLVMTypeOf(val) == ctx->i32) {
6413 assert(num_out_sgpr + 1 == num_out);
6414 num_out_sgpr = num_out;
6415 }
6416 }
6417 }
6418 }
6419
6420 LLVMBuildRetVoid(builder);
6421 }
6422
6423 int si_compile_tgsi_shader(struct si_screen *sscreen,
6424 LLVMTargetMachineRef tm,
6425 struct si_shader *shader,
6426 bool is_monolithic,
6427 struct pipe_debug_callback *debug)
6428 {
6429 struct si_shader_selector *sel = shader->selector;
6430 struct si_shader_context ctx;
6431 int r = -1;
6432
6433 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6434 * conversion fails. */
6435 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6436 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6437 if (sel->tokens)
6438 tgsi_dump(sel->tokens, 0);
6439 else
6440 nir_print_shader(sel->nir, stderr);
6441 si_dump_streamout(&sel->so);
6442 }
6443
6444 si_init_shader_ctx(&ctx, sscreen, tm);
6445 si_llvm_context_set_tgsi(&ctx, shader);
6446 ctx.separate_prolog = !is_monolithic;
6447
6448 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6449 sizeof(shader->info.vs_output_param_offset));
6450
6451 shader->info.uses_instanceid = sel->info.uses_instanceid;
6452
6453 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6454 si_llvm_dispose(&ctx);
6455 return -1;
6456 }
6457
6458 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6459 LLVMValueRef parts[2];
6460 bool need_prolog = sel->vs_needs_prolog;
6461
6462 parts[1] = ctx.main_fn;
6463
6464 if (need_prolog) {
6465 union si_shader_part_key prolog_key;
6466 si_get_vs_prolog_key(&sel->info,
6467 shader->info.num_input_sgprs,
6468 &shader->key.part.vs.prolog,
6469 shader, &prolog_key);
6470 si_build_vs_prolog_function(&ctx, &prolog_key);
6471 parts[0] = ctx.main_fn;
6472 }
6473
6474 si_build_wrapper_function(&ctx, parts + !need_prolog,
6475 1 + need_prolog, need_prolog, 0);
6476 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6477 if (sscreen->info.chip_class >= GFX9) {
6478 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6479 LLVMValueRef parts[4];
6480 bool vs_needs_prolog =
6481 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6482
6483 /* TCS main part */
6484 parts[2] = ctx.main_fn;
6485
6486 /* TCS epilog */
6487 union si_shader_part_key tcs_epilog_key;
6488 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6489 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6490 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6491 parts[3] = ctx.main_fn;
6492
6493 /* VS prolog */
6494 if (vs_needs_prolog) {
6495 union si_shader_part_key vs_prolog_key;
6496 si_get_vs_prolog_key(&ls->info,
6497 shader->info.num_input_sgprs,
6498 &shader->key.part.tcs.ls_prolog,
6499 shader, &vs_prolog_key);
6500 vs_prolog_key.vs_prolog.is_monolithic = true;
6501 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6502 parts[0] = ctx.main_fn;
6503 }
6504
6505 /* VS as LS main part */
6506 struct si_shader shader_ls = {};
6507 shader_ls.selector = ls;
6508 shader_ls.key.as_ls = 1;
6509 shader_ls.key.mono = shader->key.mono;
6510 shader_ls.key.opt = shader->key.opt;
6511 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6512
6513 if (!si_compile_tgsi_main(&ctx, true)) {
6514 si_llvm_dispose(&ctx);
6515 return -1;
6516 }
6517 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6518 parts[1] = ctx.main_fn;
6519
6520 /* Reset the shader context. */
6521 ctx.shader = shader;
6522 ctx.type = PIPE_SHADER_TESS_CTRL;
6523
6524 si_build_wrapper_function(&ctx,
6525 parts + !vs_needs_prolog,
6526 4 - !vs_needs_prolog, 0,
6527 vs_needs_prolog ? 2 : 1);
6528 } else {
6529 LLVMValueRef parts[2];
6530 union si_shader_part_key epilog_key;
6531
6532 parts[0] = ctx.main_fn;
6533
6534 memset(&epilog_key, 0, sizeof(epilog_key));
6535 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6536 si_build_tcs_epilog_function(&ctx, &epilog_key);
6537 parts[1] = ctx.main_fn;
6538
6539 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6540 }
6541 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6542 if (ctx.screen->info.chip_class >= GFX9) {
6543 struct si_shader_selector *es = shader->key.part.gs.es;
6544 LLVMValueRef es_prolog = NULL;
6545 LLVMValueRef es_main = NULL;
6546 LLVMValueRef gs_prolog = NULL;
6547 LLVMValueRef gs_main = ctx.main_fn;
6548
6549 /* GS prolog */
6550 union si_shader_part_key gs_prolog_key;
6551 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6552 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6553 gs_prolog_key.gs_prolog.is_monolithic = true;
6554 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6555 gs_prolog = ctx.main_fn;
6556
6557 /* ES prolog */
6558 if (es->vs_needs_prolog) {
6559 union si_shader_part_key vs_prolog_key;
6560 si_get_vs_prolog_key(&es->info,
6561 shader->info.num_input_sgprs,
6562 &shader->key.part.gs.vs_prolog,
6563 shader, &vs_prolog_key);
6564 vs_prolog_key.vs_prolog.is_monolithic = true;
6565 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6566 es_prolog = ctx.main_fn;
6567 }
6568
6569 /* ES main part */
6570 struct si_shader shader_es = {};
6571 shader_es.selector = es;
6572 shader_es.key.as_es = 1;
6573 shader_es.key.mono = shader->key.mono;
6574 shader_es.key.opt = shader->key.opt;
6575 si_llvm_context_set_tgsi(&ctx, &shader_es);
6576
6577 if (!si_compile_tgsi_main(&ctx, true)) {
6578 si_llvm_dispose(&ctx);
6579 return -1;
6580 }
6581 shader->info.uses_instanceid |= es->info.uses_instanceid;
6582 es_main = ctx.main_fn;
6583
6584 /* Reset the shader context. */
6585 ctx.shader = shader;
6586 ctx.type = PIPE_SHADER_GEOMETRY;
6587
6588 /* Prepare the array of shader parts. */
6589 LLVMValueRef parts[4];
6590 unsigned num_parts = 0, main_part, next_first_part;
6591
6592 if (es_prolog)
6593 parts[num_parts++] = es_prolog;
6594
6595 parts[main_part = num_parts++] = es_main;
6596 parts[next_first_part = num_parts++] = gs_prolog;
6597 parts[num_parts++] = gs_main;
6598
6599 si_build_wrapper_function(&ctx, parts, num_parts,
6600 main_part, next_first_part);
6601 } else {
6602 LLVMValueRef parts[2];
6603 union si_shader_part_key prolog_key;
6604
6605 parts[1] = ctx.main_fn;
6606
6607 memset(&prolog_key, 0, sizeof(prolog_key));
6608 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6609 si_build_gs_prolog_function(&ctx, &prolog_key);
6610 parts[0] = ctx.main_fn;
6611
6612 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6613 }
6614 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6615 LLVMValueRef parts[3];
6616 union si_shader_part_key prolog_key;
6617 union si_shader_part_key epilog_key;
6618 bool need_prolog;
6619
6620 si_get_ps_prolog_key(shader, &prolog_key, false);
6621 need_prolog = si_need_ps_prolog(&prolog_key);
6622
6623 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6624
6625 if (need_prolog) {
6626 si_build_ps_prolog_function(&ctx, &prolog_key);
6627 parts[0] = ctx.main_fn;
6628 }
6629
6630 si_get_ps_epilog_key(shader, &epilog_key);
6631 si_build_ps_epilog_function(&ctx, &epilog_key);
6632 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6633
6634 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6635 need_prolog ? 1 : 0, 0);
6636 }
6637
6638 si_llvm_optimize_module(&ctx);
6639
6640 /* Post-optimization transformations and analysis. */
6641 si_optimize_vs_outputs(&ctx);
6642
6643 if ((debug && debug->debug_message) ||
6644 si_can_dump_shader(sscreen, ctx.type))
6645 si_count_scratch_private_memory(&ctx);
6646
6647 /* Compile to bytecode. */
6648 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6649 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6650 si_llvm_dispose(&ctx);
6651 if (r) {
6652 fprintf(stderr, "LLVM failed to compile shader\n");
6653 return r;
6654 }
6655
6656 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6657 * LLVM 3.9svn has this bug.
6658 */
6659 if (sel->type == PIPE_SHADER_COMPUTE) {
6660 unsigned wave_size = 64;
6661 unsigned max_vgprs = 256;
6662 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6663 unsigned max_sgprs_per_wave = 128;
6664 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6665 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6666 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6667
6668 max_vgprs = max_vgprs / min_waves_per_simd;
6669 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6670
6671 if (shader->config.num_sgprs > max_sgprs ||
6672 shader->config.num_vgprs > max_vgprs) {
6673 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6674 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6675 shader->config.num_sgprs, shader->config.num_vgprs,
6676 max_sgprs, max_vgprs);
6677
6678 /* Just terminate the process, because dependent
6679 * shaders can hang due to bad input data, but use
6680 * the env var to allow shader-db to work.
6681 */
6682 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6683 abort();
6684 }
6685 }
6686
6687 /* Add the scratch offset to input SGPRs. */
6688 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6689 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6690
6691 /* Calculate the number of fragment input VGPRs. */
6692 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6693 shader->info.num_input_vgprs = 0;
6694 shader->info.face_vgpr_index = -1;
6695 shader->info.ancillary_vgpr_index = -1;
6696
6697 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6698 shader->info.num_input_vgprs += 2;
6699 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6700 shader->info.num_input_vgprs += 2;
6701 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6702 shader->info.num_input_vgprs += 2;
6703 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6704 shader->info.num_input_vgprs += 3;
6705 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6706 shader->info.num_input_vgprs += 2;
6707 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6708 shader->info.num_input_vgprs += 2;
6709 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6710 shader->info.num_input_vgprs += 2;
6711 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6712 shader->info.num_input_vgprs += 1;
6713 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6714 shader->info.num_input_vgprs += 1;
6715 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6716 shader->info.num_input_vgprs += 1;
6717 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6718 shader->info.num_input_vgprs += 1;
6719 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6720 shader->info.num_input_vgprs += 1;
6721 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6722 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6723 shader->info.num_input_vgprs += 1;
6724 }
6725 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6726 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6727 shader->info.num_input_vgprs += 1;
6728 }
6729 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6730 shader->info.num_input_vgprs += 1;
6731 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6732 shader->info.num_input_vgprs += 1;
6733 }
6734
6735 return 0;
6736 }
6737
6738 /**
6739 * Create, compile and return a shader part (prolog or epilog).
6740 *
6741 * \param sscreen screen
6742 * \param list list of shader parts of the same category
6743 * \param type shader type
6744 * \param key shader part key
6745 * \param prolog whether the part being requested is a prolog
6746 * \param tm LLVM target machine
6747 * \param debug debug callback
6748 * \param build the callback responsible for building the main function
6749 * \return non-NULL on success
6750 */
6751 static struct si_shader_part *
6752 si_get_shader_part(struct si_screen *sscreen,
6753 struct si_shader_part **list,
6754 enum pipe_shader_type type,
6755 bool prolog,
6756 union si_shader_part_key *key,
6757 LLVMTargetMachineRef tm,
6758 struct pipe_debug_callback *debug,
6759 void (*build)(struct si_shader_context *,
6760 union si_shader_part_key *),
6761 const char *name)
6762 {
6763 struct si_shader_part *result;
6764
6765 mtx_lock(&sscreen->shader_parts_mutex);
6766
6767 /* Find existing. */
6768 for (result = *list; result; result = result->next) {
6769 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6770 mtx_unlock(&sscreen->shader_parts_mutex);
6771 return result;
6772 }
6773 }
6774
6775 /* Compile a new one. */
6776 result = CALLOC_STRUCT(si_shader_part);
6777 result->key = *key;
6778
6779 struct si_shader shader = {};
6780 struct si_shader_context ctx;
6781
6782 si_init_shader_ctx(&ctx, sscreen, tm);
6783 ctx.shader = &shader;
6784 ctx.type = type;
6785
6786 switch (type) {
6787 case PIPE_SHADER_VERTEX:
6788 shader.key.as_ls = key->vs_prolog.as_ls;
6789 shader.key.as_es = key->vs_prolog.as_es;
6790 break;
6791 case PIPE_SHADER_TESS_CTRL:
6792 assert(!prolog);
6793 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6794 break;
6795 case PIPE_SHADER_GEOMETRY:
6796 assert(prolog);
6797 break;
6798 case PIPE_SHADER_FRAGMENT:
6799 if (prolog)
6800 shader.key.part.ps.prolog = key->ps_prolog.states;
6801 else
6802 shader.key.part.ps.epilog = key->ps_epilog.states;
6803 break;
6804 default:
6805 unreachable("bad shader part");
6806 }
6807
6808 build(&ctx, key);
6809
6810 /* Compile. */
6811 si_llvm_optimize_module(&ctx);
6812
6813 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6814 ctx.ac.module, debug, ctx.type, name)) {
6815 FREE(result);
6816 result = NULL;
6817 goto out;
6818 }
6819
6820 result->next = *list;
6821 *list = result;
6822
6823 out:
6824 si_llvm_dispose(&ctx);
6825 mtx_unlock(&sscreen->shader_parts_mutex);
6826 return result;
6827 }
6828
6829 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6830 {
6831 LLVMValueRef ptr[2], list;
6832 bool is_merged_shader =
6833 ctx->screen->info.chip_class >= GFX9 &&
6834 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6835 ctx->type == PIPE_SHADER_GEOMETRY ||
6836 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6837
6838 /* Get the pointer to rw buffers. */
6839 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6840 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6841 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6842 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6843 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6844 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6845 return list;
6846 }
6847
6848 /**
6849 * Build the vertex shader prolog function.
6850 *
6851 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6852 * All inputs are returned unmodified. The vertex load indices are
6853 * stored after them, which will be used by the API VS for fetching inputs.
6854 *
6855 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6856 * input_v0,
6857 * input_v1,
6858 * input_v2,
6859 * input_v3,
6860 * (VertexID + BaseVertex),
6861 * (InstanceID + StartInstance),
6862 * (InstanceID / 2 + StartInstance)
6863 */
6864 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6865 union si_shader_part_key *key)
6866 {
6867 struct si_function_info fninfo;
6868 LLVMTypeRef *returns;
6869 LLVMValueRef ret, func;
6870 int num_returns, i;
6871 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6872 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6873 LLVMValueRef input_vgprs[9];
6874 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6875 num_input_vgprs;
6876 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6877
6878 si_init_function_info(&fninfo);
6879
6880 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6881 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6882 sizeof(LLVMTypeRef));
6883 num_returns = 0;
6884
6885 /* Declare input and output SGPRs. */
6886 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6887 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6888 returns[num_returns++] = ctx->i32;
6889 }
6890
6891 /* Preloaded VGPRs (outputs must be floats) */
6892 for (i = 0; i < num_input_vgprs; i++) {
6893 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6894 returns[num_returns++] = ctx->f32;
6895 }
6896
6897 /* Vertex load indices. */
6898 for (i = 0; i <= key->vs_prolog.last_input; i++)
6899 returns[num_returns++] = ctx->f32;
6900
6901 /* Create the function. */
6902 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6903 func = ctx->main_fn;
6904
6905 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6906 if (!key->vs_prolog.is_monolithic)
6907 si_init_exec_from_input(ctx, 3, 0);
6908
6909 if (key->vs_prolog.as_ls &&
6910 ctx->screen->has_ls_vgpr_init_bug) {
6911 /* If there are no HS threads, SPI loads the LS VGPRs
6912 * starting at VGPR 0. Shift them back to where they
6913 * belong.
6914 */
6915 LLVMValueRef has_hs_threads =
6916 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6917 unpack_param(ctx, 3, 8, 8),
6918 ctx->i32_0, "");
6919
6920 for (i = 4; i > 0; --i) {
6921 input_vgprs[i + 1] =
6922 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6923 input_vgprs[i + 1],
6924 input_vgprs[i - 1], "");
6925 }
6926 }
6927 }
6928
6929 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6930 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6931
6932 /* Copy inputs to outputs. This should be no-op, as the registers match,
6933 * but it will prevent the compiler from overwriting them unintentionally.
6934 */
6935 ret = ctx->return_value;
6936 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6937 LLVMValueRef p = LLVMGetParam(func, i);
6938 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6939 }
6940 for (i = 0; i < num_input_vgprs; i++) {
6941 LLVMValueRef p = input_vgprs[i];
6942 p = ac_to_float(&ctx->ac, p);
6943 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6944 key->vs_prolog.num_input_sgprs + i, "");
6945 }
6946
6947 /* Compute vertex load indices from instance divisors. */
6948 LLVMValueRef instance_divisor_constbuf = NULL;
6949
6950 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6951 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6952 LLVMValueRef buf_index =
6953 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6954 instance_divisor_constbuf =
6955 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6956 }
6957
6958 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6959 bool divisor_is_one =
6960 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6961 bool divisor_is_fetched =
6962 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6963 LLVMValueRef index;
6964
6965 if (divisor_is_one || divisor_is_fetched) {
6966 LLVMValueRef divisor = ctx->i32_1;
6967
6968 if (divisor_is_fetched) {
6969 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6970 LLVMConstInt(ctx->i32, i * 4, 0));
6971 divisor = ac_to_integer(&ctx->ac, divisor);
6972 }
6973
6974 /* InstanceID / Divisor + StartInstance */
6975 index = get_instance_index_for_fetch(ctx,
6976 user_sgpr_base +
6977 SI_SGPR_START_INSTANCE,
6978 divisor);
6979 } else {
6980 /* VertexID + BaseVertex */
6981 index = LLVMBuildAdd(ctx->ac.builder,
6982 ctx->abi.vertex_id,
6983 LLVMGetParam(func, user_sgpr_base +
6984 SI_SGPR_BASE_VERTEX), "");
6985 }
6986
6987 index = ac_to_float(&ctx->ac, index);
6988 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6989 fninfo.num_params + i, "");
6990 }
6991
6992 si_llvm_build_ret(ctx, ret);
6993 }
6994
6995 static bool si_get_vs_prolog(struct si_screen *sscreen,
6996 LLVMTargetMachineRef tm,
6997 struct si_shader *shader,
6998 struct pipe_debug_callback *debug,
6999 struct si_shader *main_part,
7000 const struct si_vs_prolog_bits *key)
7001 {
7002 struct si_shader_selector *vs = main_part->selector;
7003
7004 if (!si_vs_needs_prolog(vs, key))
7005 return true;
7006
7007 /* Get the prolog. */
7008 union si_shader_part_key prolog_key;
7009 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7010 key, shader, &prolog_key);
7011
7012 shader->prolog =
7013 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7014 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7015 debug, si_build_vs_prolog_function,
7016 "Vertex Shader Prolog");
7017 return shader->prolog != NULL;
7018 }
7019
7020 /**
7021 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7022 */
7023 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7024 LLVMTargetMachineRef tm,
7025 struct si_shader *shader,
7026 struct pipe_debug_callback *debug)
7027 {
7028 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7029 &shader->key.part.vs.prolog);
7030 }
7031
7032 /**
7033 * Compile the TCS epilog function. This writes tesselation factors to memory
7034 * based on the output primitive type of the tesselator (determined by TES).
7035 */
7036 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7037 union si_shader_part_key *key)
7038 {
7039 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7040 struct si_function_info fninfo;
7041 LLVMValueRef func;
7042
7043 si_init_function_info(&fninfo);
7044
7045 if (ctx->screen->info.chip_class >= GFX9) {
7046 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7047 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7048 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7049 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7050 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7051 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7052 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7053 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7054 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7055 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7056 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7057 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7058 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7059 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7060 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7061 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7062 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7063 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7064 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7065 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7066 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7067 } else {
7068 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7069 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7070 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7071 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7072 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7073 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7074 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7075 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7076 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7077 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7078 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7079 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7080 }
7081
7082 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7083 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7084 unsigned tess_factors_idx =
7085 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7086 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7087 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7088
7089 for (unsigned i = 0; i < 6; i++)
7090 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7091
7092 /* Create the function. */
7093 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7094 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7095 ac_declare_lds_as_pointer(&ctx->ac);
7096 func = ctx->main_fn;
7097
7098 LLVMValueRef invoc0_tess_factors[6];
7099 for (unsigned i = 0; i < 6; i++)
7100 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7101
7102 si_write_tess_factors(bld_base,
7103 LLVMGetParam(func, tess_factors_idx),
7104 LLVMGetParam(func, tess_factors_idx + 1),
7105 LLVMGetParam(func, tess_factors_idx + 2),
7106 invoc0_tess_factors, invoc0_tess_factors + 4);
7107
7108 LLVMBuildRetVoid(ctx->ac.builder);
7109 }
7110
7111 /**
7112 * Select and compile (or reuse) TCS parts (epilog).
7113 */
7114 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7115 LLVMTargetMachineRef tm,
7116 struct si_shader *shader,
7117 struct pipe_debug_callback *debug)
7118 {
7119 if (sscreen->info.chip_class >= GFX9) {
7120 struct si_shader *ls_main_part =
7121 shader->key.part.tcs.ls->main_shader_part_ls;
7122
7123 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7124 &shader->key.part.tcs.ls_prolog))
7125 return false;
7126
7127 shader->previous_stage = ls_main_part;
7128 }
7129
7130 /* Get the epilog. */
7131 union si_shader_part_key epilog_key;
7132 memset(&epilog_key, 0, sizeof(epilog_key));
7133 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7134
7135 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7136 PIPE_SHADER_TESS_CTRL, false,
7137 &epilog_key, tm, debug,
7138 si_build_tcs_epilog_function,
7139 "Tessellation Control Shader Epilog");
7140 return shader->epilog != NULL;
7141 }
7142
7143 /**
7144 * Select and compile (or reuse) GS parts (prolog).
7145 */
7146 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7147 LLVMTargetMachineRef tm,
7148 struct si_shader *shader,
7149 struct pipe_debug_callback *debug)
7150 {
7151 if (sscreen->info.chip_class >= GFX9) {
7152 struct si_shader *es_main_part =
7153 shader->key.part.gs.es->main_shader_part_es;
7154
7155 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7156 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7157 &shader->key.part.gs.vs_prolog))
7158 return false;
7159
7160 shader->previous_stage = es_main_part;
7161 }
7162
7163 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7164 return true;
7165
7166 union si_shader_part_key prolog_key;
7167 memset(&prolog_key, 0, sizeof(prolog_key));
7168 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7169
7170 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7171 PIPE_SHADER_GEOMETRY, true,
7172 &prolog_key, tm, debug,
7173 si_build_gs_prolog_function,
7174 "Geometry Shader Prolog");
7175 return shader->prolog2 != NULL;
7176 }
7177
7178 /**
7179 * Build the pixel shader prolog function. This handles:
7180 * - two-side color selection and interpolation
7181 * - overriding interpolation parameters for the API PS
7182 * - polygon stippling
7183 *
7184 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7185 * overriden by other states. (e.g. per-sample interpolation)
7186 * Interpolated colors are stored after the preloaded VGPRs.
7187 */
7188 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7189 union si_shader_part_key *key)
7190 {
7191 struct si_function_info fninfo;
7192 LLVMValueRef ret, func;
7193 int num_returns, i, num_color_channels;
7194
7195 assert(si_need_ps_prolog(key));
7196
7197 si_init_function_info(&fninfo);
7198
7199 /* Declare inputs. */
7200 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7201 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7202
7203 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7204 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7205
7206 /* Declare outputs (same as inputs + add colors if needed) */
7207 num_returns = fninfo.num_params;
7208 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7209 for (i = 0; i < num_color_channels; i++)
7210 fninfo.types[num_returns++] = ctx->f32;
7211
7212 /* Create the function. */
7213 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7214 &fninfo, 0);
7215 func = ctx->main_fn;
7216
7217 /* Copy inputs to outputs. This should be no-op, as the registers match,
7218 * but it will prevent the compiler from overwriting them unintentionally.
7219 */
7220 ret = ctx->return_value;
7221 for (i = 0; i < fninfo.num_params; i++) {
7222 LLVMValueRef p = LLVMGetParam(func, i);
7223 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7224 }
7225
7226 /* Polygon stippling. */
7227 if (key->ps_prolog.states.poly_stipple) {
7228 /* POS_FIXED_PT is always last. */
7229 unsigned pos = key->ps_prolog.num_input_sgprs +
7230 key->ps_prolog.num_input_vgprs - 1;
7231 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7232
7233 si_llvm_emit_polygon_stipple(ctx, list, pos);
7234 }
7235
7236 if (key->ps_prolog.states.bc_optimize_for_persp ||
7237 key->ps_prolog.states.bc_optimize_for_linear) {
7238 unsigned i, base = key->ps_prolog.num_input_sgprs;
7239 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7240
7241 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7242 * The hw doesn't compute CENTROID if the whole wave only
7243 * contains fully-covered quads.
7244 *
7245 * PRIM_MASK is after user SGPRs.
7246 */
7247 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7248 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7249 LLVMConstInt(ctx->i32, 31, 0), "");
7250 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7251 ctx->i1, "");
7252
7253 if (key->ps_prolog.states.bc_optimize_for_persp) {
7254 /* Read PERSP_CENTER. */
7255 for (i = 0; i < 2; i++)
7256 center[i] = LLVMGetParam(func, base + 2 + i);
7257 /* Read PERSP_CENTROID. */
7258 for (i = 0; i < 2; i++)
7259 centroid[i] = LLVMGetParam(func, base + 4 + i);
7260 /* Select PERSP_CENTROID. */
7261 for (i = 0; i < 2; i++) {
7262 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7263 center[i], centroid[i], "");
7264 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7265 tmp, base + 4 + i, "");
7266 }
7267 }
7268 if (key->ps_prolog.states.bc_optimize_for_linear) {
7269 /* Read LINEAR_CENTER. */
7270 for (i = 0; i < 2; i++)
7271 center[i] = LLVMGetParam(func, base + 8 + i);
7272 /* Read LINEAR_CENTROID. */
7273 for (i = 0; i < 2; i++)
7274 centroid[i] = LLVMGetParam(func, base + 10 + i);
7275 /* Select LINEAR_CENTROID. */
7276 for (i = 0; i < 2; i++) {
7277 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7278 center[i], centroid[i], "");
7279 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7280 tmp, base + 10 + i, "");
7281 }
7282 }
7283 }
7284
7285 /* Force per-sample interpolation. */
7286 if (key->ps_prolog.states.force_persp_sample_interp) {
7287 unsigned i, base = key->ps_prolog.num_input_sgprs;
7288 LLVMValueRef persp_sample[2];
7289
7290 /* Read PERSP_SAMPLE. */
7291 for (i = 0; i < 2; i++)
7292 persp_sample[i] = LLVMGetParam(func, base + i);
7293 /* Overwrite PERSP_CENTER. */
7294 for (i = 0; i < 2; i++)
7295 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7296 persp_sample[i], base + 2 + i, "");
7297 /* Overwrite PERSP_CENTROID. */
7298 for (i = 0; i < 2; i++)
7299 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7300 persp_sample[i], base + 4 + i, "");
7301 }
7302 if (key->ps_prolog.states.force_linear_sample_interp) {
7303 unsigned i, base = key->ps_prolog.num_input_sgprs;
7304 LLVMValueRef linear_sample[2];
7305
7306 /* Read LINEAR_SAMPLE. */
7307 for (i = 0; i < 2; i++)
7308 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7309 /* Overwrite LINEAR_CENTER. */
7310 for (i = 0; i < 2; i++)
7311 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7312 linear_sample[i], base + 8 + i, "");
7313 /* Overwrite LINEAR_CENTROID. */
7314 for (i = 0; i < 2; i++)
7315 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7316 linear_sample[i], base + 10 + i, "");
7317 }
7318
7319 /* Force center interpolation. */
7320 if (key->ps_prolog.states.force_persp_center_interp) {
7321 unsigned i, base = key->ps_prolog.num_input_sgprs;
7322 LLVMValueRef persp_center[2];
7323
7324 /* Read PERSP_CENTER. */
7325 for (i = 0; i < 2; i++)
7326 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7327 /* Overwrite PERSP_SAMPLE. */
7328 for (i = 0; i < 2; i++)
7329 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7330 persp_center[i], base + i, "");
7331 /* Overwrite PERSP_CENTROID. */
7332 for (i = 0; i < 2; i++)
7333 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7334 persp_center[i], base + 4 + i, "");
7335 }
7336 if (key->ps_prolog.states.force_linear_center_interp) {
7337 unsigned i, base = key->ps_prolog.num_input_sgprs;
7338 LLVMValueRef linear_center[2];
7339
7340 /* Read LINEAR_CENTER. */
7341 for (i = 0; i < 2; i++)
7342 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7343 /* Overwrite LINEAR_SAMPLE. */
7344 for (i = 0; i < 2; i++)
7345 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7346 linear_center[i], base + 6 + i, "");
7347 /* Overwrite LINEAR_CENTROID. */
7348 for (i = 0; i < 2; i++)
7349 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7350 linear_center[i], base + 10 + i, "");
7351 }
7352
7353 /* Interpolate colors. */
7354 unsigned color_out_idx = 0;
7355 for (i = 0; i < 2; i++) {
7356 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7357 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7358 key->ps_prolog.face_vgpr_index;
7359 LLVMValueRef interp[2], color[4];
7360 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7361
7362 if (!writemask)
7363 continue;
7364
7365 /* If the interpolation qualifier is not CONSTANT (-1). */
7366 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7367 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7368 key->ps_prolog.color_interp_vgpr_index[i];
7369
7370 /* Get the (i,j) updated by bc_optimize handling. */
7371 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7372 interp_vgpr, "");
7373 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7374 interp_vgpr + 1, "");
7375 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7376 }
7377
7378 /* Use the absolute location of the input. */
7379 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7380
7381 if (key->ps_prolog.states.color_two_side) {
7382 face = LLVMGetParam(func, face_vgpr);
7383 face = ac_to_integer(&ctx->ac, face);
7384 }
7385
7386 interp_fs_input(ctx,
7387 key->ps_prolog.color_attr_index[i],
7388 TGSI_SEMANTIC_COLOR, i,
7389 key->ps_prolog.num_interp_inputs,
7390 key->ps_prolog.colors_read, interp_ij,
7391 prim_mask, face, color);
7392
7393 while (writemask) {
7394 unsigned chan = u_bit_scan(&writemask);
7395 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7396 fninfo.num_params + color_out_idx++, "");
7397 }
7398 }
7399
7400 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7401 * says:
7402 *
7403 * "When per-sample shading is active due to the use of a fragment
7404 * input qualified by sample or due to the use of the gl_SampleID
7405 * or gl_SamplePosition variables, only the bit for the current
7406 * sample is set in gl_SampleMaskIn. When state specifies multiple
7407 * fragment shader invocations for a given fragment, the sample
7408 * mask for any single fragment shader invocation may specify a
7409 * subset of the covered samples for the fragment. In this case,
7410 * the bit corresponding to each covered sample will be set in
7411 * exactly one fragment shader invocation."
7412 *
7413 * The samplemask loaded by hardware is always the coverage of the
7414 * entire pixel/fragment, so mask bits out based on the sample ID.
7415 */
7416 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7417 /* The bit pattern matches that used by fixed function fragment
7418 * processing. */
7419 static const uint16_t ps_iter_masks[] = {
7420 0xffff, /* not used */
7421 0x5555,
7422 0x1111,
7423 0x0101,
7424 0x0001,
7425 };
7426 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7427
7428 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7429 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7430 key->ps_prolog.ancillary_vgpr_index;
7431 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7432 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7433
7434 samplemask = ac_to_integer(&ctx->ac, samplemask);
7435 samplemask = LLVMBuildAnd(
7436 ctx->ac.builder,
7437 samplemask,
7438 LLVMBuildShl(ctx->ac.builder,
7439 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7440 sampleid, ""),
7441 "");
7442 samplemask = ac_to_float(&ctx->ac, samplemask);
7443
7444 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7445 ancillary_vgpr + 1, "");
7446 }
7447
7448 /* Tell LLVM to insert WQM instruction sequence when needed. */
7449 if (key->ps_prolog.wqm) {
7450 LLVMAddTargetDependentFunctionAttr(func,
7451 "amdgpu-ps-wqm-outputs", "");
7452 }
7453
7454 si_llvm_build_ret(ctx, ret);
7455 }
7456
7457 /**
7458 * Build the pixel shader epilog function. This handles everything that must be
7459 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7460 */
7461 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7462 union si_shader_part_key *key)
7463 {
7464 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7465 struct si_function_info fninfo;
7466 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7467 int i;
7468 struct si_ps_exports exp = {};
7469
7470 si_init_function_info(&fninfo);
7471
7472 /* Declare input SGPRs. */
7473 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7474 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7475 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7476 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7477 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7478
7479 /* Declare input VGPRs. */
7480 unsigned required_num_params =
7481 fninfo.num_sgpr_params +
7482 util_bitcount(key->ps_epilog.colors_written) * 4 +
7483 key->ps_epilog.writes_z +
7484 key->ps_epilog.writes_stencil +
7485 key->ps_epilog.writes_samplemask;
7486
7487 required_num_params = MAX2(required_num_params,
7488 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7489
7490 while (fninfo.num_params < required_num_params)
7491 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7492
7493 /* Create the function. */
7494 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7495 /* Disable elimination of unused inputs. */
7496 si_llvm_add_attribute(ctx->main_fn,
7497 "InitialPSInputAddr", 0xffffff);
7498
7499 /* Process colors. */
7500 unsigned vgpr = fninfo.num_sgpr_params;
7501 unsigned colors_written = key->ps_epilog.colors_written;
7502 int last_color_export = -1;
7503
7504 /* Find the last color export. */
7505 if (!key->ps_epilog.writes_z &&
7506 !key->ps_epilog.writes_stencil &&
7507 !key->ps_epilog.writes_samplemask) {
7508 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7509
7510 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7511 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7512 /* Just set this if any of the colorbuffers are enabled. */
7513 if (spi_format &
7514 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7515 last_color_export = 0;
7516 } else {
7517 for (i = 0; i < 8; i++)
7518 if (colors_written & (1 << i) &&
7519 (spi_format >> (i * 4)) & 0xf)
7520 last_color_export = i;
7521 }
7522 }
7523
7524 while (colors_written) {
7525 LLVMValueRef color[4];
7526 int mrt = u_bit_scan(&colors_written);
7527
7528 for (i = 0; i < 4; i++)
7529 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7530
7531 si_export_mrt_color(bld_base, color, mrt,
7532 fninfo.num_params - 1,
7533 mrt == last_color_export, &exp);
7534 }
7535
7536 /* Process depth, stencil, samplemask. */
7537 if (key->ps_epilog.writes_z)
7538 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7539 if (key->ps_epilog.writes_stencil)
7540 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7541 if (key->ps_epilog.writes_samplemask)
7542 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7543
7544 if (depth || stencil || samplemask)
7545 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7546 else if (last_color_export == -1)
7547 si_export_null(bld_base);
7548
7549 if (exp.num)
7550 si_emit_ps_exports(ctx, &exp);
7551
7552 /* Compile. */
7553 LLVMBuildRetVoid(ctx->ac.builder);
7554 }
7555
7556 /**
7557 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7558 */
7559 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7560 LLVMTargetMachineRef tm,
7561 struct si_shader *shader,
7562 struct pipe_debug_callback *debug)
7563 {
7564 union si_shader_part_key prolog_key;
7565 union si_shader_part_key epilog_key;
7566
7567 /* Get the prolog. */
7568 si_get_ps_prolog_key(shader, &prolog_key, true);
7569
7570 /* The prolog is a no-op if these aren't set. */
7571 if (si_need_ps_prolog(&prolog_key)) {
7572 shader->prolog =
7573 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7574 PIPE_SHADER_FRAGMENT, true,
7575 &prolog_key, tm, debug,
7576 si_build_ps_prolog_function,
7577 "Fragment Shader Prolog");
7578 if (!shader->prolog)
7579 return false;
7580 }
7581
7582 /* Get the epilog. */
7583 si_get_ps_epilog_key(shader, &epilog_key);
7584
7585 shader->epilog =
7586 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7587 PIPE_SHADER_FRAGMENT, false,
7588 &epilog_key, tm, debug,
7589 si_build_ps_epilog_function,
7590 "Fragment Shader Epilog");
7591 if (!shader->epilog)
7592 return false;
7593
7594 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7595 if (shader->key.part.ps.prolog.poly_stipple) {
7596 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7597 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7598 }
7599
7600 /* Set up the enable bits for per-sample shading if needed. */
7601 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7602 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7603 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7604 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7605 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7606 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7607 }
7608 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7609 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7610 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7611 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7612 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7613 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7614 }
7615 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7616 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7617 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7618 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7619 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7620 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7621 }
7622 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7623 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7624 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7625 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7626 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7627 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7628 }
7629
7630 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7631 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7632 !(shader->config.spi_ps_input_ena & 0xf)) {
7633 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7634 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7635 }
7636
7637 /* At least one pair of interpolation weights must be enabled. */
7638 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7639 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7640 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7641 }
7642
7643 /* Samplemask fixup requires the sample ID. */
7644 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7645 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7646 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7647 }
7648
7649 /* The sample mask input is always enabled, because the API shader always
7650 * passes it through to the epilog. Disable it here if it's unused.
7651 */
7652 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7653 !shader->selector->info.reads_samplemask)
7654 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7655
7656 return true;
7657 }
7658
7659 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7660 unsigned *lds_size)
7661 {
7662 /* SPI barrier management bug:
7663 * Make sure we have at least 4k of LDS in use to avoid the bug.
7664 * It applies to workgroup sizes of more than one wavefront.
7665 */
7666 if (sscreen->info.family == CHIP_BONAIRE ||
7667 sscreen->info.family == CHIP_KABINI ||
7668 sscreen->info.family == CHIP_MULLINS)
7669 *lds_size = MAX2(*lds_size, 8);
7670 }
7671
7672 static void si_fix_resource_usage(struct si_screen *sscreen,
7673 struct si_shader *shader)
7674 {
7675 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7676
7677 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7678
7679 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7680 si_get_max_workgroup_size(shader) > 64) {
7681 si_multiwave_lds_size_workaround(sscreen,
7682 &shader->config.lds_size);
7683 }
7684 }
7685
7686 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7687 struct si_shader *shader,
7688 struct pipe_debug_callback *debug)
7689 {
7690 struct si_shader_selector *sel = shader->selector;
7691 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7692 int r;
7693
7694 /* LS, ES, VS are compiled on demand if the main part hasn't been
7695 * compiled for that stage.
7696 *
7697 * Vertex shaders are compiled on demand when a vertex fetch
7698 * workaround must be applied.
7699 */
7700 if (shader->is_monolithic) {
7701 /* Monolithic shader (compiled as a whole, has many variants,
7702 * may take a long time to compile).
7703 */
7704 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7705 if (r)
7706 return r;
7707 } else {
7708 /* The shader consists of several parts:
7709 *
7710 * - the middle part is the user shader, it has 1 variant only
7711 * and it was compiled during the creation of the shader
7712 * selector
7713 * - the prolog part is inserted at the beginning
7714 * - the epilog part is inserted at the end
7715 *
7716 * The prolog and epilog have many (but simple) variants.
7717 *
7718 * Starting with gfx9, geometry and tessellation control
7719 * shaders also contain the prolog and user shader parts of
7720 * the previous shader stage.
7721 */
7722
7723 if (!mainp)
7724 return -1;
7725
7726 /* Copy the compiled TGSI shader data over. */
7727 shader->is_binary_shared = true;
7728 shader->binary = mainp->binary;
7729 shader->config = mainp->config;
7730 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7731 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7732 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7733 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7734 memcpy(shader->info.vs_output_param_offset,
7735 mainp->info.vs_output_param_offset,
7736 sizeof(mainp->info.vs_output_param_offset));
7737 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7738 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7739 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7740
7741 /* Select prologs and/or epilogs. */
7742 switch (sel->type) {
7743 case PIPE_SHADER_VERTEX:
7744 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7745 return -1;
7746 break;
7747 case PIPE_SHADER_TESS_CTRL:
7748 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7749 return -1;
7750 break;
7751 case PIPE_SHADER_TESS_EVAL:
7752 break;
7753 case PIPE_SHADER_GEOMETRY:
7754 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7755 return -1;
7756 break;
7757 case PIPE_SHADER_FRAGMENT:
7758 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7759 return -1;
7760
7761 /* Make sure we have at least as many VGPRs as there
7762 * are allocated inputs.
7763 */
7764 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7765 shader->info.num_input_vgprs);
7766 break;
7767 }
7768
7769 /* Update SGPR and VGPR counts. */
7770 if (shader->prolog) {
7771 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7772 shader->prolog->config.num_sgprs);
7773 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7774 shader->prolog->config.num_vgprs);
7775 }
7776 if (shader->previous_stage) {
7777 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7778 shader->previous_stage->config.num_sgprs);
7779 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7780 shader->previous_stage->config.num_vgprs);
7781 shader->config.spilled_sgprs =
7782 MAX2(shader->config.spilled_sgprs,
7783 shader->previous_stage->config.spilled_sgprs);
7784 shader->config.spilled_vgprs =
7785 MAX2(shader->config.spilled_vgprs,
7786 shader->previous_stage->config.spilled_vgprs);
7787 shader->config.private_mem_vgprs =
7788 MAX2(shader->config.private_mem_vgprs,
7789 shader->previous_stage->config.private_mem_vgprs);
7790 shader->config.scratch_bytes_per_wave =
7791 MAX2(shader->config.scratch_bytes_per_wave,
7792 shader->previous_stage->config.scratch_bytes_per_wave);
7793 shader->info.uses_instanceid |=
7794 shader->previous_stage->info.uses_instanceid;
7795 }
7796 if (shader->prolog2) {
7797 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7798 shader->prolog2->config.num_sgprs);
7799 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7800 shader->prolog2->config.num_vgprs);
7801 }
7802 if (shader->epilog) {
7803 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7804 shader->epilog->config.num_sgprs);
7805 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7806 shader->epilog->config.num_vgprs);
7807 }
7808 }
7809
7810 si_fix_resource_usage(sscreen, shader);
7811 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7812 stderr, true);
7813
7814 /* Upload. */
7815 r = si_shader_binary_upload(sscreen, shader);
7816 if (r) {
7817 fprintf(stderr, "LLVM failed to upload shader\n");
7818 return r;
7819 }
7820
7821 return 0;
7822 }
7823
7824 void si_shader_destroy(struct si_shader *shader)
7825 {
7826 if (shader->scratch_bo)
7827 r600_resource_reference(&shader->scratch_bo, NULL);
7828
7829 r600_resource_reference(&shader->bo, NULL);
7830
7831 if (!shader->is_binary_shared)
7832 ac_shader_binary_clean(&shader->binary);
7833
7834 free(shader->shader_log);
7835 }