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radeonsi: move color clamping to si_llvm_export_vs to unify the code
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31
32 #include "ac_exp_param.h"
33 #include "ac_shader_util.h"
34 #include "ac_llvm_util.h"
35 #include "si_shader_internal.h"
36 #include "si_pipe.h"
37 #include "sid.h"
38
39 #include "compiler/nir/nir.h"
40
41 static const char *scratch_rsrc_dword0_symbol =
42 "SCRATCH_RSRC_DWORD0";
43
44 static const char *scratch_rsrc_dword1_symbol =
45 "SCRATCH_RSRC_DWORD1";
46
47 struct si_shader_output_values
48 {
49 LLVMValueRef values[4];
50 unsigned semantic_name;
51 unsigned semantic_index;
52 ubyte vertex_stream[4];
53 };
54
55 static void si_init_shader_ctx(struct si_shader_context *ctx,
56 struct si_screen *sscreen,
57 struct ac_llvm_compiler *compiler);
58
59 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
60 struct lp_build_tgsi_context *bld_base,
61 struct lp_build_emit_data *emit_data);
62
63 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
64 FILE *f);
65
66 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
67 union si_shader_part_key *key);
68 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
71 union si_shader_part_key *key);
72 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
73 union si_shader_part_key *key);
74 static void si_fix_resource_usage(struct si_screen *sscreen,
75 struct si_shader *shader);
76
77 /* Ideally pass the sample mask input to the PS epilog as v14, which
78 * is its usual location, so that the shader doesn't have to add v_mov.
79 */
80 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
81
82 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
83 LLVMTypeRef type)
84 {
85 if (type == ctx->ac.i64 || type == ctx->ac.f64)
86 return true;
87
88 return false;
89 }
90
91 static bool is_merged_shader(struct si_shader_context *ctx)
92 {
93 if (ctx->screen->info.chip_class <= GFX8)
94 return false;
95
96 return ctx->shader->key.as_ls ||
97 ctx->shader->key.as_es ||
98 ctx->type == PIPE_SHADER_TESS_CTRL ||
99 ctx->type == PIPE_SHADER_GEOMETRY;
100 }
101
102 void si_init_function_info(struct si_function_info *fninfo)
103 {
104 fninfo->num_params = 0;
105 fninfo->num_sgpr_params = 0;
106 }
107
108 unsigned add_arg_assign(struct si_function_info *fninfo,
109 enum si_arg_regfile regfile, LLVMTypeRef type,
110 LLVMValueRef *assign)
111 {
112 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
113
114 unsigned idx = fninfo->num_params++;
115 assert(idx < ARRAY_SIZE(fninfo->types));
116
117 if (regfile == ARG_SGPR)
118 fninfo->num_sgpr_params = fninfo->num_params;
119
120 fninfo->types[idx] = type;
121 fninfo->assign[idx] = assign;
122 return idx;
123 }
124
125 static unsigned add_arg(struct si_function_info *fninfo,
126 enum si_arg_regfile regfile, LLVMTypeRef type)
127 {
128 return add_arg_assign(fninfo, regfile, type, NULL);
129 }
130
131 static void add_arg_assign_checked(struct si_function_info *fninfo,
132 enum si_arg_regfile regfile, LLVMTypeRef type,
133 LLVMValueRef *assign, unsigned idx)
134 {
135 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
136 assert(actual == idx);
137 }
138
139 static void add_arg_checked(struct si_function_info *fninfo,
140 enum si_arg_regfile regfile, LLVMTypeRef type,
141 unsigned idx)
142 {
143 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
144 }
145
146 /**
147 * Returns a unique index for a per-patch semantic name and index. The index
148 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
149 * can be calculated.
150 */
151 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
152 {
153 switch (semantic_name) {
154 case TGSI_SEMANTIC_TESSOUTER:
155 return 0;
156 case TGSI_SEMANTIC_TESSINNER:
157 return 1;
158 case TGSI_SEMANTIC_PATCH:
159 assert(index < 30);
160 return 2 + index;
161
162 default:
163 assert(!"invalid semantic name");
164 return 0;
165 }
166 }
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
174 unsigned is_varying)
175 {
176 switch (semantic_name) {
177 case TGSI_SEMANTIC_POSITION:
178 return 0;
179 case TGSI_SEMANTIC_GENERIC:
180 /* Since some shader stages use the the highest used IO index
181 * to determine the size to allocate for inputs/outputs
182 * (in LDS, tess and GS rings). GENERIC should be placed right
183 * after POSITION to make that size as small as possible.
184 */
185 if (index < SI_MAX_IO_GENERIC)
186 return 1 + index;
187
188 assert(!"invalid generic index");
189 return 0;
190 case TGSI_SEMANTIC_PSIZE:
191 return SI_MAX_IO_GENERIC + 1;
192 case TGSI_SEMANTIC_CLIPDIST:
193 assert(index <= 1);
194 return SI_MAX_IO_GENERIC + 2 + index;
195 case TGSI_SEMANTIC_FOG:
196 return SI_MAX_IO_GENERIC + 4;
197 case TGSI_SEMANTIC_LAYER:
198 return SI_MAX_IO_GENERIC + 5;
199 case TGSI_SEMANTIC_VIEWPORT_INDEX:
200 return SI_MAX_IO_GENERIC + 6;
201 case TGSI_SEMANTIC_PRIMID:
202 return SI_MAX_IO_GENERIC + 7;
203 case TGSI_SEMANTIC_COLOR:
204 assert(index < 2);
205 return SI_MAX_IO_GENERIC + 8 + index;
206 case TGSI_SEMANTIC_BCOLOR:
207 assert(index < 2);
208 /* If it's a varying, COLOR and BCOLOR alias. */
209 if (is_varying)
210 return SI_MAX_IO_GENERIC + 8 + index;
211 else
212 return SI_MAX_IO_GENERIC + 10 + index;
213 case TGSI_SEMANTIC_TEXCOORD:
214 assert(index < 8);
215 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
216 return SI_MAX_IO_GENERIC + 12 + index;
217 case TGSI_SEMANTIC_CLIPVERTEX:
218 return 63;
219 default:
220 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
221 assert(!"invalid semantic name");
222 return 0;
223 }
224 }
225
226 /**
227 * Get the value of a shader input parameter and extract a bitfield.
228 */
229 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
230 LLVMValueRef value, unsigned rshift,
231 unsigned bitwidth)
232 {
233 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
234 value = ac_to_integer(&ctx->ac, value);
235
236 if (rshift)
237 value = LLVMBuildLShr(ctx->ac.builder, value,
238 LLVMConstInt(ctx->i32, rshift, 0), "");
239
240 if (rshift + bitwidth < 32) {
241 unsigned mask = (1 << bitwidth) - 1;
242 value = LLVMBuildAnd(ctx->ac.builder, value,
243 LLVMConstInt(ctx->i32, mask, 0), "");
244 }
245
246 return value;
247 }
248
249 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
250 unsigned param, unsigned rshift,
251 unsigned bitwidth)
252 {
253 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
254
255 return unpack_llvm_param(ctx, value, rshift, bitwidth);
256 }
257
258 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
259 {
260 switch (ctx->type) {
261 case PIPE_SHADER_TESS_CTRL:
262 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
263
264 case PIPE_SHADER_TESS_EVAL:
265 return LLVMGetParam(ctx->main_fn,
266 ctx->param_tes_rel_patch_id);
267
268 default:
269 assert(0);
270 return NULL;
271 }
272 }
273
274 /* Tessellation shaders pass outputs to the next shader using LDS.
275 *
276 * LS outputs = TCS inputs
277 * TCS outputs = TES inputs
278 *
279 * The LDS layout is:
280 * - TCS inputs for patch 0
281 * - TCS inputs for patch 1
282 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
283 * - ...
284 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
285 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
286 * - TCS outputs for patch 1
287 * - Per-patch TCS outputs for patch 1
288 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
289 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
290 * - ...
291 *
292 * All three shaders VS(LS), TCS, TES share the same LDS space.
293 */
294
295 static LLVMValueRef
296 get_tcs_in_patch_stride(struct si_shader_context *ctx)
297 {
298 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
299 }
300
301 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
302 {
303 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
304
305 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
306 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
307
308 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
309 }
310
311 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
312 {
313 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
314
315 return LLVMConstInt(ctx->i32, stride, 0);
316 }
317
318 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
319 {
320 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
321 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
322
323 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
324 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
325 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
326 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
327 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
328 num_patch_outputs * 4;
329 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
330 }
331
332 static LLVMValueRef
333 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
334 {
335 return LLVMBuildMul(ctx->ac.builder,
336 si_unpack_param(ctx,
337 ctx->param_tcs_out_lds_offsets,
338 0, 16),
339 LLVMConstInt(ctx->i32, 4, 0), "");
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
344 {
345 return LLVMBuildMul(ctx->ac.builder,
346 si_unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 16, 16),
349 LLVMConstInt(ctx->i32, 4, 0), "");
350 }
351
352 static LLVMValueRef
353 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
354 {
355 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
356 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
357
358 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
359 }
360
361 static LLVMValueRef
362 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
363 {
364 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
365 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_patch_data_offset =
375 get_tcs_out_patch0_patch_data_offset(ctx);
376 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
377 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
378
379 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
380 }
381
382 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
383 {
384 unsigned tcs_out_vertices =
385 ctx->shader->selector ?
386 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
387
388 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
389 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
390 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
391
392 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
393 }
394
395 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
396 {
397 unsigned stride;
398
399 switch (ctx->type) {
400 case PIPE_SHADER_VERTEX:
401 stride = ctx->shader->selector->lshs_vertex_stride / 4;
402 return LLVMConstInt(ctx->i32, stride, 0);
403
404 case PIPE_SHADER_TESS_CTRL:
405 if (ctx->screen->info.chip_class >= GFX9 &&
406 ctx->shader->is_monolithic) {
407 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
408 return LLVMConstInt(ctx->i32, stride, 0);
409 }
410 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
411
412 default:
413 assert(0);
414 return NULL;
415 }
416 }
417
418 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
419 LLVMValueRef i32, unsigned index)
420 {
421 assert(index <= 1);
422
423 if (index == 1)
424 return LLVMBuildAShr(ctx->ac.builder, i32,
425 LLVMConstInt(ctx->i32, 16, 0), "");
426
427 return LLVMBuildSExt(ctx->ac.builder,
428 LLVMBuildTrunc(ctx->ac.builder, i32,
429 ctx->ac.i16, ""),
430 ctx->i32, "");
431 }
432
433 void si_llvm_load_input_vs(
434 struct si_shader_context *ctx,
435 unsigned input_index,
436 LLVMValueRef out[4])
437 {
438 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
439 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
440
441 if (vs_blit_property) {
442 LLVMValueRef vertex_id = ctx->abi.vertex_id;
443 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
444 LLVMIntULE, vertex_id,
445 ctx->i32_1, "");
446 /* Use LLVMIntNE, because we have 3 vertices and only
447 * the middle one should use y2.
448 */
449 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
450 LLVMIntNE, vertex_id,
451 ctx->i32_1, "");
452
453 if (input_index == 0) {
454 /* Position: */
455 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
456 ctx->param_vs_blit_inputs);
457 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
458 ctx->param_vs_blit_inputs + 1);
459
460 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
461 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
462 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
463 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
464
465 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
466 x1, x2, "");
467 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
468 y1, y2, "");
469
470 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
471 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
472 out[2] = LLVMGetParam(ctx->main_fn,
473 ctx->param_vs_blit_inputs + 2);
474 out[3] = ctx->ac.f32_1;
475 return;
476 }
477
478 /* Color or texture coordinates: */
479 assert(input_index == 1);
480
481 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
482 for (int i = 0; i < 4; i++) {
483 out[i] = LLVMGetParam(ctx->main_fn,
484 ctx->param_vs_blit_inputs + 3 + i);
485 }
486 } else {
487 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
488 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
489 ctx->param_vs_blit_inputs + 3);
490 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 4);
492 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
493 ctx->param_vs_blit_inputs + 5);
494 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs + 6);
496
497 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
498 x1, x2, "");
499 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
500 y1, y2, "");
501 out[2] = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 7);
503 out[3] = LLVMGetParam(ctx->main_fn,
504 ctx->param_vs_blit_inputs + 8);
505 }
506 return;
507 }
508
509 union si_vs_fix_fetch fix_fetch;
510 LLVMValueRef t_list_ptr;
511 LLVMValueRef t_offset;
512 LLVMValueRef t_list;
513 LLVMValueRef vertex_index;
514 LLVMValueRef tmp;
515
516 /* Load the T list */
517 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
518
519 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
520
521 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
522
523 vertex_index = LLVMGetParam(ctx->main_fn,
524 ctx->param_vertex_index0 +
525 input_index);
526
527 /* Use the open-coded implementation for all loads of doubles and
528 * of dword-sized data that needs fixups. We need to insert conversion
529 * code anyway, and the amd/common code does it for us.
530 *
531 * Note: On LLVM <= 8, we can only open-code formats with
532 * channel size >= 4 bytes.
533 */
534 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
535 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
536 if (opencode ||
537 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
538 (fix_fetch.u.log_size == 2)) {
539 tmp = ac_build_opencoded_load_format(
540 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
541 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
542 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0,
543 false, false, true);
544 for (unsigned i = 0; i < 4; ++i)
545 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
546 return;
547 }
548
549 /* Do multiple loads for special formats. */
550 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
551 LLVMValueRef fetches[4];
552 unsigned num_fetches;
553 unsigned fetch_stride;
554 unsigned channels_per_fetch;
555
556 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
557 num_fetches = MIN2(required_channels, 3);
558 fetch_stride = 1 << fix_fetch.u.log_size;
559 channels_per_fetch = 1;
560 } else {
561 num_fetches = 1;
562 fetch_stride = 0;
563 channels_per_fetch = required_channels;
564 }
565
566 for (unsigned i = 0; i < num_fetches; ++i) {
567 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
568 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
569 channels_per_fetch, false, true);
570 }
571
572 if (num_fetches == 1 && channels_per_fetch > 1) {
573 LLVMValueRef fetch = fetches[0];
574 for (unsigned i = 0; i < channels_per_fetch; ++i) {
575 tmp = LLVMConstInt(ctx->i32, i, false);
576 fetches[i] = LLVMBuildExtractElement(
577 ctx->ac.builder, fetch, tmp, "");
578 }
579 num_fetches = channels_per_fetch;
580 channels_per_fetch = 1;
581 }
582
583 for (unsigned i = num_fetches; i < 4; ++i)
584 fetches[i] = LLVMGetUndef(ctx->f32);
585
586 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
587 required_channels == 4) {
588 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
589 fetches[3] = ctx->ac.i32_1;
590 else
591 fetches[3] = ctx->ac.f32_1;
592 } else if (fix_fetch.u.log_size == 3 &&
593 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
594 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
595 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
596 required_channels == 4) {
597 /* For 2_10_10_10, the hardware returns an unsigned value;
598 * convert it to a signed one.
599 */
600 LLVMValueRef tmp = fetches[3];
601 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
602
603 /* First, recover the sign-extended signed integer value. */
604 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
605 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
606 else
607 tmp = ac_to_integer(&ctx->ac, tmp);
608
609 /* For the integer-like cases, do a natural sign extension.
610 *
611 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
612 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
613 * exponent.
614 */
615 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
616 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
617 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
618 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
619
620 /* Convert back to the right type. */
621 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
622 LLVMValueRef clamp;
623 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
624 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
625 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
626 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
627 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
628 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
629 }
630
631 fetches[3] = tmp;
632 }
633
634 for (unsigned i = 0; i < 4; ++i)
635 out[i] = ac_to_float(&ctx->ac, fetches[i]);
636 }
637
638 static void declare_input_vs(
639 struct si_shader_context *ctx,
640 unsigned input_index,
641 const struct tgsi_full_declaration *decl,
642 LLVMValueRef out[4])
643 {
644 si_llvm_load_input_vs(ctx, input_index, out);
645 }
646
647 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
648 unsigned swizzle)
649 {
650 if (swizzle > 0)
651 return ctx->i32_0;
652
653 switch (ctx->type) {
654 case PIPE_SHADER_VERTEX:
655 return LLVMGetParam(ctx->main_fn,
656 ctx->param_vs_prim_id);
657 case PIPE_SHADER_TESS_CTRL:
658 return ctx->abi.tcs_patch_id;
659 case PIPE_SHADER_TESS_EVAL:
660 return ctx->abi.tes_patch_id;
661 case PIPE_SHADER_GEOMETRY:
662 return ctx->abi.gs_prim_id;
663 default:
664 assert(0);
665 return ctx->i32_0;
666 }
667 }
668
669 /**
670 * Return the value of tgsi_ind_register for indexing.
671 * This is the indirect index with the constant offset added to it.
672 */
673 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
674 const struct tgsi_ind_register *ind,
675 unsigned addr_mul,
676 int rel_index)
677 {
678 LLVMValueRef result;
679
680 if (ind->File == TGSI_FILE_ADDRESS) {
681 result = ctx->addrs[ind->Index][ind->Swizzle];
682 result = LLVMBuildLoad(ctx->ac.builder, result, "");
683 } else {
684 struct tgsi_full_src_register src = {};
685
686 src.Register.File = ind->File;
687 src.Register.Index = ind->Index;
688
689 /* Set the second index to 0 for constants. */
690 if (ind->File == TGSI_FILE_CONSTANT)
691 src.Register.Dimension = 1;
692
693 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
694 TGSI_TYPE_SIGNED,
695 ind->Swizzle);
696 result = ac_to_integer(&ctx->ac, result);
697 }
698
699 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
700 LLVMConstInt(ctx->i32, rel_index, 0));
701 }
702
703 /**
704 * Like si_get_indirect_index, but restricts the return value to a (possibly
705 * undefined) value inside [0..num).
706 */
707 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
708 const struct tgsi_ind_register *ind,
709 int rel_index, unsigned num)
710 {
711 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
712
713 return si_llvm_bound_index(ctx, result, num);
714 }
715
716 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
717 LLVMValueRef vertex_dw_stride,
718 LLVMValueRef base_addr,
719 LLVMValueRef vertex_index,
720 LLVMValueRef param_index,
721 unsigned input_index,
722 ubyte *name,
723 ubyte *index,
724 bool is_patch)
725 {
726 if (vertex_dw_stride) {
727 base_addr = ac_build_imad(&ctx->ac, vertex_index,
728 vertex_dw_stride, base_addr);
729 }
730
731 if (param_index) {
732 base_addr = ac_build_imad(&ctx->ac, param_index,
733 LLVMConstInt(ctx->i32, 4, 0), base_addr);
734 }
735
736 int param = is_patch ?
737 si_shader_io_get_unique_index_patch(name[input_index],
738 index[input_index]) :
739 si_shader_io_get_unique_index(name[input_index],
740 index[input_index], false);
741
742 /* Add the base address of the element. */
743 return LLVMBuildAdd(ctx->ac.builder, base_addr,
744 LLVMConstInt(ctx->i32, param * 4, 0), "");
745 }
746
747 /**
748 * Calculate a dword address given an input or output register and a stride.
749 */
750 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
751 const struct tgsi_full_dst_register *dst,
752 const struct tgsi_full_src_register *src,
753 LLVMValueRef vertex_dw_stride,
754 LLVMValueRef base_addr)
755 {
756 struct tgsi_shader_info *info = &ctx->shader->selector->info;
757 ubyte *name, *index, *array_first;
758 int input_index;
759 struct tgsi_full_dst_register reg;
760 LLVMValueRef vertex_index = NULL;
761 LLVMValueRef ind_index = NULL;
762
763 /* Set the register description. The address computation is the same
764 * for sources and destinations. */
765 if (src) {
766 reg.Register.File = src->Register.File;
767 reg.Register.Index = src->Register.Index;
768 reg.Register.Indirect = src->Register.Indirect;
769 reg.Register.Dimension = src->Register.Dimension;
770 reg.Indirect = src->Indirect;
771 reg.Dimension = src->Dimension;
772 reg.DimIndirect = src->DimIndirect;
773 } else
774 reg = *dst;
775
776 /* If the register is 2-dimensional (e.g. an array of vertices
777 * in a primitive), calculate the base address of the vertex. */
778 if (reg.Register.Dimension) {
779 if (reg.Dimension.Indirect)
780 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
781 1, reg.Dimension.Index);
782 else
783 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
784 }
785
786 /* Get information about the register. */
787 if (reg.Register.File == TGSI_FILE_INPUT) {
788 name = info->input_semantic_name;
789 index = info->input_semantic_index;
790 array_first = info->input_array_first;
791 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
792 name = info->output_semantic_name;
793 index = info->output_semantic_index;
794 array_first = info->output_array_first;
795 } else {
796 assert(0);
797 return NULL;
798 }
799
800 if (reg.Register.Indirect) {
801 /* Add the relative address of the element. */
802 if (reg.Indirect.ArrayID)
803 input_index = array_first[reg.Indirect.ArrayID];
804 else
805 input_index = reg.Register.Index;
806
807 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
808 1, reg.Register.Index - input_index);
809 } else {
810 input_index = reg.Register.Index;
811 }
812
813 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
814 base_addr, vertex_index,
815 ind_index, input_index,
816 name, index,
817 !reg.Register.Dimension);
818 }
819
820 /* The offchip buffer layout for TCS->TES is
821 *
822 * - attribute 0 of patch 0 vertex 0
823 * - attribute 0 of patch 0 vertex 1
824 * - attribute 0 of patch 0 vertex 2
825 * ...
826 * - attribute 0 of patch 1 vertex 0
827 * - attribute 0 of patch 1 vertex 1
828 * ...
829 * - attribute 1 of patch 0 vertex 0
830 * - attribute 1 of patch 0 vertex 1
831 * ...
832 * - per patch attribute 0 of patch 0
833 * - per patch attribute 0 of patch 1
834 * ...
835 *
836 * Note that every attribute has 4 components.
837 */
838 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
839 LLVMValueRef rel_patch_id,
840 LLVMValueRef vertex_index,
841 LLVMValueRef param_index)
842 {
843 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
844 LLVMValueRef param_stride, constant16;
845
846 vertices_per_patch = get_num_tcs_out_vertices(ctx);
847 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
848 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
849 num_patches, "");
850
851 constant16 = LLVMConstInt(ctx->i32, 16, 0);
852 if (vertex_index) {
853 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
854 vertices_per_patch, vertex_index);
855 param_stride = total_vertices;
856 } else {
857 base_addr = rel_patch_id;
858 param_stride = num_patches;
859 }
860
861 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
862 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
863
864 if (!vertex_index) {
865 LLVMValueRef patch_data_offset =
866 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
867
868 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
869 patch_data_offset, "");
870 }
871 return base_addr;
872 }
873
874 /* This is a generic helper that can be shared by the NIR and TGSI backends */
875 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
876 struct si_shader_context *ctx,
877 LLVMValueRef vertex_index,
878 LLVMValueRef param_index,
879 unsigned param_base,
880 ubyte *name,
881 ubyte *index,
882 bool is_patch)
883 {
884 unsigned param_index_base;
885
886 param_index_base = is_patch ?
887 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
888 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
889
890 if (param_index) {
891 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
892 LLVMConstInt(ctx->i32, param_index_base, 0),
893 "");
894 } else {
895 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
896 }
897
898 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
899 vertex_index, param_index);
900 }
901
902 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
903 struct si_shader_context *ctx,
904 const struct tgsi_full_dst_register *dst,
905 const struct tgsi_full_src_register *src)
906 {
907 struct tgsi_shader_info *info = &ctx->shader->selector->info;
908 ubyte *name, *index, *array_first;
909 struct tgsi_full_src_register reg;
910 LLVMValueRef vertex_index = NULL;
911 LLVMValueRef param_index = NULL;
912 unsigned param_base;
913
914 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
915
916 if (reg.Register.Dimension) {
917
918 if (reg.Dimension.Indirect)
919 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
920 1, reg.Dimension.Index);
921 else
922 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
923 }
924
925 /* Get information about the register. */
926 if (reg.Register.File == TGSI_FILE_INPUT) {
927 name = info->input_semantic_name;
928 index = info->input_semantic_index;
929 array_first = info->input_array_first;
930 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
931 name = info->output_semantic_name;
932 index = info->output_semantic_index;
933 array_first = info->output_array_first;
934 } else {
935 assert(0);
936 return NULL;
937 }
938
939 if (reg.Register.Indirect) {
940 if (reg.Indirect.ArrayID)
941 param_base = array_first[reg.Indirect.ArrayID];
942 else
943 param_base = reg.Register.Index;
944
945 param_index = si_get_indirect_index(ctx, &reg.Indirect,
946 1, reg.Register.Index - param_base);
947
948 } else {
949 param_base = reg.Register.Index;
950 }
951
952 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
953 param_index, param_base,
954 name, index, !reg.Register.Dimension);
955 }
956
957 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
958 LLVMTypeRef type, unsigned swizzle,
959 LLVMValueRef buffer, LLVMValueRef offset,
960 LLVMValueRef base, bool can_speculate)
961 {
962 struct si_shader_context *ctx = si_shader_context(bld_base);
963 LLVMValueRef value, value2;
964 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
965
966 if (swizzle == ~0) {
967 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
968 0, 1, 0, can_speculate, false);
969
970 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
971 }
972
973 if (!llvm_type_is_64bit(ctx, type)) {
974 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
975 0, 1, 0, can_speculate, false);
976
977 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
978 return LLVMBuildExtractElement(ctx->ac.builder, value,
979 LLVMConstInt(ctx->i32, swizzle, 0), "");
980 }
981
982 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
983 swizzle * 4, 1, 0, can_speculate, false);
984
985 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
986 swizzle * 4 + 4, 1, 0, can_speculate, false);
987
988 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
989 }
990
991 /**
992 * Load from LDS.
993 *
994 * \param type output value type
995 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
996 * \param dw_addr address in dwords
997 */
998 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
999 LLVMTypeRef type, unsigned swizzle,
1000 LLVMValueRef dw_addr)
1001 {
1002 struct si_shader_context *ctx = si_shader_context(bld_base);
1003 LLVMValueRef value;
1004
1005 if (swizzle == ~0) {
1006 LLVMValueRef values[TGSI_NUM_CHANNELS];
1007
1008 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1009 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1010
1011 return ac_build_gather_values(&ctx->ac, values,
1012 TGSI_NUM_CHANNELS);
1013 }
1014
1015 /* Split 64-bit loads. */
1016 if (llvm_type_is_64bit(ctx, type)) {
1017 LLVMValueRef lo, hi;
1018
1019 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1020 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1021 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1022 }
1023
1024 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1025 LLVMConstInt(ctx->i32, swizzle, 0), "");
1026
1027 value = ac_lds_load(&ctx->ac, dw_addr);
1028
1029 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1030 }
1031
1032 /**
1033 * Store to LDS.
1034 *
1035 * \param swizzle offset (typically 0..3)
1036 * \param dw_addr address in dwords
1037 * \param value value to store
1038 */
1039 static void lds_store(struct si_shader_context *ctx,
1040 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1041 LLVMValueRef value)
1042 {
1043 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1044 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1045
1046 ac_lds_store(&ctx->ac, dw_addr, value);
1047 }
1048
1049 enum si_tess_ring {
1050 TCS_FACTOR_RING,
1051 TESS_OFFCHIP_RING_TCS,
1052 TESS_OFFCHIP_RING_TES,
1053 };
1054
1055 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1056 enum si_tess_ring ring)
1057 {
1058 LLVMBuilderRef builder = ctx->ac.builder;
1059 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1060 ctx->param_tcs_out_lds_layout;
1061 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1062
1063 /* TCS only receives high 13 bits of the address. */
1064 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1065 addr = LLVMBuildAnd(builder, addr,
1066 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1067 }
1068
1069 if (ring == TCS_FACTOR_RING) {
1070 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1071 addr = LLVMBuildAdd(builder, addr,
1072 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1073 }
1074
1075 LLVMValueRef desc[4];
1076 desc[0] = addr;
1077 desc[1] = LLVMConstInt(ctx->i32,
1078 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1079 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1080 desc[3] = LLVMConstInt(ctx->i32,
1081 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1085 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1087
1088 return ac_build_gather_values(&ctx->ac, desc, 4);
1089 }
1090
1091 static LLVMValueRef fetch_input_tcs(
1092 struct lp_build_tgsi_context *bld_base,
1093 const struct tgsi_full_src_register *reg,
1094 enum tgsi_opcode_type type, unsigned swizzle_in)
1095 {
1096 struct si_shader_context *ctx = si_shader_context(bld_base);
1097 LLVMValueRef dw_addr, stride;
1098 unsigned swizzle = swizzle_in & 0xffff;
1099 stride = get_tcs_in_vertex_dw_stride(ctx);
1100 dw_addr = get_tcs_in_current_patch_offset(ctx);
1101 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1102
1103 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1104 }
1105
1106 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1107 LLVMTypeRef type,
1108 LLVMValueRef vertex_index,
1109 LLVMValueRef param_index,
1110 unsigned const_index,
1111 unsigned location,
1112 unsigned driver_location,
1113 unsigned component,
1114 unsigned num_components,
1115 bool is_patch,
1116 bool is_compact,
1117 bool load_input)
1118 {
1119 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1120 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1121 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1122 LLVMValueRef dw_addr, stride;
1123
1124 driver_location = driver_location / 4;
1125
1126 if (load_input) {
1127 stride = get_tcs_in_vertex_dw_stride(ctx);
1128 dw_addr = get_tcs_in_current_patch_offset(ctx);
1129 } else {
1130 if (is_patch) {
1131 stride = NULL;
1132 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1133 } else {
1134 stride = get_tcs_out_vertex_dw_stride(ctx);
1135 dw_addr = get_tcs_out_current_patch_offset(ctx);
1136 }
1137 }
1138
1139 if (param_index) {
1140 /* Add the constant index to the indirect index */
1141 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1142 LLVMConstInt(ctx->i32, const_index, 0), "");
1143 } else {
1144 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1145 }
1146
1147 ubyte *names;
1148 ubyte *indices;
1149 if (load_input) {
1150 names = info->input_semantic_name;
1151 indices = info->input_semantic_index;
1152 } else {
1153 names = info->output_semantic_name;
1154 indices = info->output_semantic_index;
1155 }
1156
1157 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1158 vertex_index, param_index,
1159 driver_location,
1160 names, indices,
1161 is_patch);
1162
1163 LLVMValueRef value[4];
1164 for (unsigned i = 0; i < num_components; i++) {
1165 unsigned offset = i;
1166 if (llvm_type_is_64bit(ctx, type))
1167 offset *= 2;
1168
1169 offset += component;
1170 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1171 }
1172
1173 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1174 }
1175
1176 static LLVMValueRef fetch_output_tcs(
1177 struct lp_build_tgsi_context *bld_base,
1178 const struct tgsi_full_src_register *reg,
1179 enum tgsi_opcode_type type, unsigned swizzle_in)
1180 {
1181 struct si_shader_context *ctx = si_shader_context(bld_base);
1182 LLVMValueRef dw_addr, stride;
1183 unsigned swizzle = (swizzle_in & 0xffff);
1184
1185 if (reg->Register.Dimension) {
1186 stride = get_tcs_out_vertex_dw_stride(ctx);
1187 dw_addr = get_tcs_out_current_patch_offset(ctx);
1188 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1189 } else {
1190 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1191 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1192 }
1193
1194 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1195 }
1196
1197 static LLVMValueRef fetch_input_tes(
1198 struct lp_build_tgsi_context *bld_base,
1199 const struct tgsi_full_src_register *reg,
1200 enum tgsi_opcode_type type, unsigned swizzle_in)
1201 {
1202 struct si_shader_context *ctx = si_shader_context(bld_base);
1203 LLVMValueRef base, addr;
1204 unsigned swizzle = (swizzle_in & 0xffff);
1205
1206 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1207 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1208
1209 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1210 ctx->tess_offchip_ring, base, addr, true);
1211 }
1212
1213 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1214 LLVMTypeRef type,
1215 LLVMValueRef vertex_index,
1216 LLVMValueRef param_index,
1217 unsigned const_index,
1218 unsigned location,
1219 unsigned driver_location,
1220 unsigned component,
1221 unsigned num_components,
1222 bool is_patch,
1223 bool is_compact,
1224 bool load_input)
1225 {
1226 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1227 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1228 LLVMValueRef base, addr;
1229
1230 driver_location = driver_location / 4;
1231
1232 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1233
1234 if (param_index) {
1235 /* Add the constant index to the indirect index */
1236 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1237 LLVMConstInt(ctx->i32, const_index, 0), "");
1238 } else {
1239 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1240 }
1241
1242 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1243 param_index, driver_location,
1244 info->input_semantic_name,
1245 info->input_semantic_index,
1246 is_patch);
1247
1248 /* TODO: This will generate rather ordinary llvm code, although it
1249 * should be easy for the optimiser to fix up. In future we might want
1250 * to refactor buffer_load(), but for now this maximises code sharing
1251 * between the NIR and TGSI backends.
1252 */
1253 LLVMValueRef value[4];
1254 for (unsigned i = 0; i < num_components; i++) {
1255 unsigned offset = i;
1256 if (llvm_type_is_64bit(ctx, type)) {
1257 offset *= 2;
1258 if (offset == 4) {
1259 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1260 vertex_index,
1261 param_index,
1262 driver_location + 1,
1263 info->input_semantic_name,
1264 info->input_semantic_index,
1265 is_patch);
1266 }
1267
1268 offset = offset % 4;
1269 }
1270
1271 offset += component;
1272 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1273 ctx->tess_offchip_ring, base, addr, true);
1274 }
1275
1276 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1277 }
1278
1279 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1280 const struct tgsi_full_instruction *inst,
1281 const struct tgsi_opcode_info *info,
1282 unsigned index,
1283 LLVMValueRef dst[4])
1284 {
1285 struct si_shader_context *ctx = si_shader_context(bld_base);
1286 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1287 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1288 unsigned chan_index;
1289 LLVMValueRef dw_addr, stride;
1290 LLVMValueRef buffer, base, buf_addr;
1291 LLVMValueRef values[4];
1292 bool skip_lds_store;
1293 bool is_tess_factor = false, is_tess_inner = false;
1294
1295 /* Only handle per-patch and per-vertex outputs here.
1296 * Vectors will be lowered to scalars and this function will be called again.
1297 */
1298 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1299 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1300 si_llvm_emit_store(bld_base, inst, info, index, dst);
1301 return;
1302 }
1303
1304 if (reg->Register.Dimension) {
1305 stride = get_tcs_out_vertex_dw_stride(ctx);
1306 dw_addr = get_tcs_out_current_patch_offset(ctx);
1307 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1308 skip_lds_store = !sh_info->reads_pervertex_outputs;
1309 } else {
1310 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1311 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1312 skip_lds_store = !sh_info->reads_perpatch_outputs;
1313
1314 if (!reg->Register.Indirect) {
1315 int name = sh_info->output_semantic_name[reg->Register.Index];
1316
1317 /* Always write tess factors into LDS for the TCS epilog. */
1318 if (name == TGSI_SEMANTIC_TESSINNER ||
1319 name == TGSI_SEMANTIC_TESSOUTER) {
1320 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1321 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1322 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1323 is_tess_factor = true;
1324 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1325 }
1326 }
1327 }
1328
1329 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1330
1331 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1332 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1333
1334 uint32_t writemask = reg->Register.WriteMask;
1335 while (writemask) {
1336 chan_index = u_bit_scan(&writemask);
1337 LLVMValueRef value = dst[chan_index];
1338
1339 if (inst->Instruction.Saturate)
1340 value = ac_build_clamp(&ctx->ac, value);
1341
1342 /* Skip LDS stores if there is no LDS read of this output. */
1343 if (!skip_lds_store)
1344 lds_store(ctx, chan_index, dw_addr, value);
1345
1346 value = ac_to_integer(&ctx->ac, value);
1347 values[chan_index] = value;
1348
1349 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1350 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1351 buf_addr, base,
1352 4 * chan_index, 1, 0, true, false);
1353 }
1354
1355 /* Write tess factors into VGPRs for the epilog. */
1356 if (is_tess_factor &&
1357 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1358 if (!is_tess_inner) {
1359 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1360 ctx->invoc0_tess_factors[chan_index]);
1361 } else if (chan_index < 2) {
1362 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1363 ctx->invoc0_tess_factors[4 + chan_index]);
1364 }
1365 }
1366 }
1367
1368 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1369 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1370 values, 4);
1371 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1372 base, 0, 1, 0, true, false);
1373 }
1374 }
1375
1376 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1377 const struct nir_variable *var,
1378 LLVMValueRef vertex_index,
1379 LLVMValueRef param_index,
1380 unsigned const_index,
1381 LLVMValueRef src,
1382 unsigned writemask)
1383 {
1384 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1385 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1386 const unsigned component = var->data.location_frac;
1387 const bool is_patch = var->data.patch;
1388 unsigned driver_location = var->data.driver_location;
1389 LLVMValueRef dw_addr, stride;
1390 LLVMValueRef buffer, base, addr;
1391 LLVMValueRef values[8];
1392 bool skip_lds_store;
1393 bool is_tess_factor = false, is_tess_inner = false;
1394
1395 driver_location = driver_location / 4;
1396
1397 if (param_index) {
1398 /* Add the constant index to the indirect index */
1399 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1400 LLVMConstInt(ctx->i32, const_index, 0), "");
1401 } else {
1402 if (const_index != 0)
1403 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1404 }
1405
1406 if (!is_patch) {
1407 stride = get_tcs_out_vertex_dw_stride(ctx);
1408 dw_addr = get_tcs_out_current_patch_offset(ctx);
1409 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1410 vertex_index, param_index,
1411 driver_location,
1412 info->output_semantic_name,
1413 info->output_semantic_index,
1414 is_patch);
1415
1416 skip_lds_store = !info->reads_pervertex_outputs;
1417 } else {
1418 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1419 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1420 vertex_index, param_index,
1421 driver_location,
1422 info->output_semantic_name,
1423 info->output_semantic_index,
1424 is_patch);
1425
1426 skip_lds_store = !info->reads_perpatch_outputs;
1427
1428 if (!param_index) {
1429 int name = info->output_semantic_name[driver_location];
1430
1431 /* Always write tess factors into LDS for the TCS epilog. */
1432 if (name == TGSI_SEMANTIC_TESSINNER ||
1433 name == TGSI_SEMANTIC_TESSOUTER) {
1434 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1435 skip_lds_store = !info->reads_tessfactor_outputs &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1437 is_tess_factor = true;
1438 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1439 }
1440 }
1441 }
1442
1443 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1444
1445 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1446
1447 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1448 param_index, driver_location,
1449 info->output_semantic_name,
1450 info->output_semantic_index,
1451 is_patch);
1452
1453 for (unsigned chan = 0; chan < 8; chan++) {
1454 if (!(writemask & (1 << chan)))
1455 continue;
1456 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1457
1458 unsigned buffer_store_offset = chan % 4;
1459 if (chan == 4) {
1460 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1461 vertex_index,
1462 param_index,
1463 driver_location + 1,
1464 info->output_semantic_name,
1465 info->output_semantic_index,
1466 is_patch);
1467 }
1468
1469 /* Skip LDS stores if there is no LDS read of this output. */
1470 if (!skip_lds_store)
1471 lds_store(ctx, chan, dw_addr, value);
1472
1473 value = ac_to_integer(&ctx->ac, value);
1474 values[chan] = value;
1475
1476 if (writemask != 0xF && !is_tess_factor) {
1477 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1478 addr, base,
1479 4 * buffer_store_offset,
1480 1, 0, true, false);
1481 }
1482
1483 /* Write tess factors into VGPRs for the epilog. */
1484 if (is_tess_factor &&
1485 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1486 if (!is_tess_inner) {
1487 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1488 ctx->invoc0_tess_factors[chan]);
1489 } else if (chan < 2) {
1490 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1491 ctx->invoc0_tess_factors[4 + chan]);
1492 }
1493 }
1494 }
1495
1496 if (writemask == 0xF && !is_tess_factor) {
1497 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1498 values, 4);
1499 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1500 base, 0, 1, 0, true, false);
1501 }
1502 }
1503
1504 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1505 unsigned input_index,
1506 unsigned vtx_offset_param,
1507 LLVMTypeRef type,
1508 unsigned swizzle)
1509 {
1510 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1511 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1512 struct si_shader *shader = ctx->shader;
1513 LLVMValueRef vtx_offset, soffset;
1514 struct tgsi_shader_info *info = &shader->selector->info;
1515 unsigned semantic_name = info->input_semantic_name[input_index];
1516 unsigned semantic_index = info->input_semantic_index[input_index];
1517 unsigned param;
1518 LLVMValueRef value;
1519
1520 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1521
1522 /* GFX9 has the ESGS ring in LDS. */
1523 if (ctx->screen->info.chip_class >= GFX9) {
1524 unsigned index = vtx_offset_param;
1525
1526 switch (index / 2) {
1527 case 0:
1528 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1529 index % 2 ? 16 : 0, 16);
1530 break;
1531 case 1:
1532 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1533 index % 2 ? 16 : 0, 16);
1534 break;
1535 case 2:
1536 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1537 index % 2 ? 16 : 0, 16);
1538 break;
1539 default:
1540 assert(0);
1541 return NULL;
1542 }
1543
1544 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1545 LLVMConstInt(ctx->i32, param * 4, 0), "");
1546 return lds_load(bld_base, type, swizzle, vtx_offset);
1547 }
1548
1549 /* GFX6: input load from the ESGS ring in memory. */
1550 if (swizzle == ~0) {
1551 LLVMValueRef values[TGSI_NUM_CHANNELS];
1552 unsigned chan;
1553 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1554 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1555 type, chan);
1556 }
1557 return ac_build_gather_values(&ctx->ac, values,
1558 TGSI_NUM_CHANNELS);
1559 }
1560
1561 /* Get the vertex offset parameter on GFX6. */
1562 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1563
1564 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1565 LLVMConstInt(ctx->i32, 4, 0), "");
1566
1567 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1568
1569 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1570 vtx_offset, soffset, 0, 1, 0, true, false);
1571 if (llvm_type_is_64bit(ctx, type)) {
1572 LLVMValueRef value2;
1573 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1574
1575 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1576 ctx->i32_0, vtx_offset, soffset,
1577 0, 1, 0, true, false);
1578 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1579 }
1580 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1581 }
1582
1583 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1584 unsigned location,
1585 unsigned driver_location,
1586 unsigned component,
1587 unsigned num_components,
1588 unsigned vertex_index,
1589 unsigned const_index,
1590 LLVMTypeRef type)
1591 {
1592 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1593
1594 LLVMValueRef value[4];
1595 for (unsigned i = 0; i < num_components; i++) {
1596 unsigned offset = i;
1597 if (llvm_type_is_64bit(ctx, type))
1598 offset *= 2;
1599
1600 offset += component;
1601 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1602 vertex_index, type, offset);
1603 }
1604
1605 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1606 }
1607
1608 static LLVMValueRef fetch_input_gs(
1609 struct lp_build_tgsi_context *bld_base,
1610 const struct tgsi_full_src_register *reg,
1611 enum tgsi_opcode_type type,
1612 unsigned swizzle_in)
1613 {
1614 struct si_shader_context *ctx = si_shader_context(bld_base);
1615 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1616 unsigned swizzle = swizzle_in & 0xffff;
1617
1618 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1619 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1620 return get_primitive_id(ctx, swizzle);
1621
1622 if (!reg->Register.Dimension)
1623 return NULL;
1624
1625 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1626 reg->Dimension.Index,
1627 tgsi2llvmtype(bld_base, type),
1628 swizzle);
1629 }
1630
1631 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1632 {
1633 switch (interpolate) {
1634 case TGSI_INTERPOLATE_CONSTANT:
1635 return 0;
1636
1637 case TGSI_INTERPOLATE_LINEAR:
1638 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1639 return SI_PARAM_LINEAR_SAMPLE;
1640 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1641 return SI_PARAM_LINEAR_CENTROID;
1642 else
1643 return SI_PARAM_LINEAR_CENTER;
1644 break;
1645 case TGSI_INTERPOLATE_COLOR:
1646 case TGSI_INTERPOLATE_PERSPECTIVE:
1647 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1648 return SI_PARAM_PERSP_SAMPLE;
1649 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1650 return SI_PARAM_PERSP_CENTROID;
1651 else
1652 return SI_PARAM_PERSP_CENTER;
1653 break;
1654 default:
1655 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1656 return -1;
1657 }
1658 }
1659
1660 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1661 unsigned attr_index, unsigned chan,
1662 LLVMValueRef prim_mask,
1663 LLVMValueRef i, LLVMValueRef j)
1664 {
1665 if (i || j) {
1666 return ac_build_fs_interp(&ctx->ac,
1667 LLVMConstInt(ctx->i32, chan, 0),
1668 LLVMConstInt(ctx->i32, attr_index, 0),
1669 prim_mask, i, j);
1670 }
1671 return ac_build_fs_interp_mov(&ctx->ac,
1672 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1673 LLVMConstInt(ctx->i32, chan, 0),
1674 LLVMConstInt(ctx->i32, attr_index, 0),
1675 prim_mask);
1676 }
1677
1678 /**
1679 * Interpolate a fragment shader input.
1680 *
1681 * @param ctx context
1682 * @param input_index index of the input in hardware
1683 * @param semantic_name TGSI_SEMANTIC_*
1684 * @param semantic_index semantic index
1685 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1686 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1687 * @param interp_param interpolation weights (i,j)
1688 * @param prim_mask SI_PARAM_PRIM_MASK
1689 * @param face SI_PARAM_FRONT_FACE
1690 * @param result the return value (4 components)
1691 */
1692 static void interp_fs_input(struct si_shader_context *ctx,
1693 unsigned input_index,
1694 unsigned semantic_name,
1695 unsigned semantic_index,
1696 unsigned num_interp_inputs,
1697 unsigned colors_read_mask,
1698 LLVMValueRef interp_param,
1699 LLVMValueRef prim_mask,
1700 LLVMValueRef face,
1701 LLVMValueRef result[4])
1702 {
1703 LLVMValueRef i = NULL, j = NULL;
1704 unsigned chan;
1705
1706 /* fs.constant returns the param from the middle vertex, so it's not
1707 * really useful for flat shading. It's meant to be used for custom
1708 * interpolation (but the intrinsic can't fetch from the other two
1709 * vertices).
1710 *
1711 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1712 * to do the right thing. The only reason we use fs.constant is that
1713 * fs.interp cannot be used on integers, because they can be equal
1714 * to NaN.
1715 *
1716 * When interp is false we will use fs.constant or for newer llvm,
1717 * amdgcn.interp.mov.
1718 */
1719 bool interp = interp_param != NULL;
1720
1721 if (interp) {
1722 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1723 LLVMVectorType(ctx->f32, 2), "");
1724
1725 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1726 ctx->i32_0, "");
1727 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1728 ctx->i32_1, "");
1729 }
1730
1731 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1732 ctx->shader->key.part.ps.prolog.color_two_side) {
1733 LLVMValueRef is_face_positive;
1734
1735 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1736 * otherwise it's at offset "num_inputs".
1737 */
1738 unsigned back_attr_offset = num_interp_inputs;
1739 if (semantic_index == 1 && colors_read_mask & 0xf)
1740 back_attr_offset += 1;
1741
1742 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1743 face, ctx->i32_0, "");
1744
1745 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1746 LLVMValueRef front, back;
1747
1748 front = si_build_fs_interp(ctx,
1749 input_index, chan,
1750 prim_mask, i, j);
1751 back = si_build_fs_interp(ctx,
1752 back_attr_offset, chan,
1753 prim_mask, i, j);
1754
1755 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1756 is_face_positive,
1757 front,
1758 back,
1759 "");
1760 }
1761 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1762 result[0] = si_build_fs_interp(ctx, input_index,
1763 0, prim_mask, i, j);
1764 result[1] =
1765 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1766 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1767 } else {
1768 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1769 result[chan] = si_build_fs_interp(ctx,
1770 input_index, chan,
1771 prim_mask, i, j);
1772 }
1773 }
1774 }
1775
1776 void si_llvm_load_input_fs(
1777 struct si_shader_context *ctx,
1778 unsigned input_index,
1779 LLVMValueRef out[4])
1780 {
1781 struct si_shader *shader = ctx->shader;
1782 struct tgsi_shader_info *info = &shader->selector->info;
1783 LLVMValueRef main_fn = ctx->main_fn;
1784 LLVMValueRef interp_param = NULL;
1785 int interp_param_idx;
1786 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1787 unsigned semantic_index = info->input_semantic_index[input_index];
1788 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1789 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1790
1791 /* Get colors from input VGPRs (set by the prolog). */
1792 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1793 unsigned colors_read = shader->selector->info.colors_read;
1794 unsigned mask = colors_read >> (semantic_index * 4);
1795 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1796 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1797 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1798
1799 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1800 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1801 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1802 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1803 return;
1804 }
1805
1806 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1807 if (interp_param_idx == -1)
1808 return;
1809 else if (interp_param_idx) {
1810 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1811 }
1812
1813 interp_fs_input(ctx, input_index, semantic_name,
1814 semantic_index, 0, /* this param is unused */
1815 shader->selector->info.colors_read, interp_param,
1816 ctx->abi.prim_mask,
1817 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1818 &out[0]);
1819 }
1820
1821 static void declare_input_fs(
1822 struct si_shader_context *ctx,
1823 unsigned input_index,
1824 const struct tgsi_full_declaration *decl,
1825 LLVMValueRef out[4])
1826 {
1827 si_llvm_load_input_fs(ctx, input_index, out);
1828 }
1829
1830 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1831 {
1832 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1833 }
1834
1835 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1836 {
1837 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1838
1839 /* For non-indexed draws, the base vertex set by the driver
1840 * (for direct draws) or the CP (for indirect draws) is the
1841 * first vertex ID, but GLSL expects 0 to be returned.
1842 */
1843 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1844 ctx->param_vs_state_bits);
1845 LLVMValueRef indexed;
1846
1847 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1848 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1849
1850 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1851 ctx->i32_0, "");
1852 }
1853
1854 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1855 {
1856 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1857
1858 LLVMValueRef values[3];
1859 LLVMValueRef result;
1860 unsigned i;
1861 unsigned *properties = ctx->shader->selector->info.properties;
1862
1863 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1864 unsigned sizes[3] = {
1865 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1866 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1867 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1868 };
1869
1870 for (i = 0; i < 3; ++i)
1871 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1872
1873 result = ac_build_gather_values(&ctx->ac, values, 3);
1874 } else {
1875 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1876 }
1877
1878 return result;
1879 }
1880
1881 /**
1882 * Load a dword from a constant buffer.
1883 */
1884 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1885 LLVMValueRef resource,
1886 LLVMValueRef offset)
1887 {
1888 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1889 0, 0, 0, true, true);
1890 }
1891
1892 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1893 {
1894 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1895 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1896 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1897 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1898
1899 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1900 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1901 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1902
1903 LLVMValueRef pos[4] = {
1904 buffer_load_const(ctx, resource, offset0),
1905 buffer_load_const(ctx, resource, offset1),
1906 LLVMConstReal(ctx->f32, 0),
1907 LLVMConstReal(ctx->f32, 0)
1908 };
1909
1910 return ac_build_gather_values(&ctx->ac, pos, 4);
1911 }
1912
1913 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1914 {
1915 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1916 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1917 }
1918
1919 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1920 {
1921 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1922 LLVMValueRef coord[4] = {
1923 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1924 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1925 ctx->ac.f32_0,
1926 ctx->ac.f32_0
1927 };
1928
1929 /* For triangles, the vector should be (u, v, 1-u-v). */
1930 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1931 PIPE_PRIM_TRIANGLES) {
1932 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1933 LLVMBuildFAdd(ctx->ac.builder,
1934 coord[0], coord[1], ""), "");
1935 }
1936 return ac_build_gather_values(&ctx->ac, coord, 4);
1937 }
1938
1939 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1940 unsigned semantic_name)
1941 {
1942 LLVMValueRef base, addr;
1943
1944 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1945
1946 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1947 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1948 LLVMConstInt(ctx->i32, param, 0));
1949
1950 return buffer_load(&ctx->bld_base, ctx->f32,
1951 ~0, ctx->tess_offchip_ring, base, addr, true);
1952
1953 }
1954
1955 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1956 unsigned varying_id)
1957 {
1958 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1959 unsigned semantic_name;
1960
1961 switch (varying_id) {
1962 case VARYING_SLOT_TESS_LEVEL_INNER:
1963 semantic_name = TGSI_SEMANTIC_TESSINNER;
1964 break;
1965 case VARYING_SLOT_TESS_LEVEL_OUTER:
1966 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1967 break;
1968 default:
1969 unreachable("unknown tess level");
1970 }
1971
1972 return load_tess_level(ctx, semantic_name);
1973
1974 }
1975
1976 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1977 {
1978 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1979 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1980 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
1981 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1982 return get_num_tcs_out_vertices(ctx);
1983 else
1984 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1985 }
1986
1987 void si_load_system_value(struct si_shader_context *ctx,
1988 unsigned index,
1989 const struct tgsi_full_declaration *decl)
1990 {
1991 LLVMValueRef value = 0;
1992
1993 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1994
1995 switch (decl->Semantic.Name) {
1996 case TGSI_SEMANTIC_INSTANCEID:
1997 value = ctx->abi.instance_id;
1998 break;
1999
2000 case TGSI_SEMANTIC_VERTEXID:
2001 value = LLVMBuildAdd(ctx->ac.builder,
2002 ctx->abi.vertex_id,
2003 ctx->abi.base_vertex, "");
2004 break;
2005
2006 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2007 /* Unused. Clarify the meaning in indexed vs. non-indexed
2008 * draws if this is ever used again. */
2009 assert(false);
2010 break;
2011
2012 case TGSI_SEMANTIC_BASEVERTEX:
2013 value = get_base_vertex(&ctx->abi);
2014 break;
2015
2016 case TGSI_SEMANTIC_BASEINSTANCE:
2017 value = ctx->abi.start_instance;
2018 break;
2019
2020 case TGSI_SEMANTIC_DRAWID:
2021 value = ctx->abi.draw_id;
2022 break;
2023
2024 case TGSI_SEMANTIC_INVOCATIONID:
2025 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2026 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2027 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2028 value = ctx->abi.gs_invocation_id;
2029 else
2030 assert(!"INVOCATIONID not implemented");
2031 break;
2032
2033 case TGSI_SEMANTIC_POSITION:
2034 {
2035 LLVMValueRef pos[4] = {
2036 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2037 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2038 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2039 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2040 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2041 };
2042 value = ac_build_gather_values(&ctx->ac, pos, 4);
2043 break;
2044 }
2045
2046 case TGSI_SEMANTIC_FACE:
2047 value = ctx->abi.front_face;
2048 break;
2049
2050 case TGSI_SEMANTIC_SAMPLEID:
2051 value = si_get_sample_id(ctx);
2052 break;
2053
2054 case TGSI_SEMANTIC_SAMPLEPOS: {
2055 LLVMValueRef pos[4] = {
2056 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2057 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2058 LLVMConstReal(ctx->f32, 0),
2059 LLVMConstReal(ctx->f32, 0)
2060 };
2061 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2062 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2063 value = ac_build_gather_values(&ctx->ac, pos, 4);
2064 break;
2065 }
2066
2067 case TGSI_SEMANTIC_SAMPLEMASK:
2068 /* This can only occur with the OpenGL Core profile, which
2069 * doesn't support smoothing.
2070 */
2071 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2072 break;
2073
2074 case TGSI_SEMANTIC_TESSCOORD:
2075 value = si_load_tess_coord(&ctx->abi);
2076 break;
2077
2078 case TGSI_SEMANTIC_VERTICESIN:
2079 value = si_load_patch_vertices_in(&ctx->abi);
2080 break;
2081
2082 case TGSI_SEMANTIC_TESSINNER:
2083 case TGSI_SEMANTIC_TESSOUTER:
2084 value = load_tess_level(ctx, decl->Semantic.Name);
2085 break;
2086
2087 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2088 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2089 {
2090 LLVMValueRef buf, slot, val[4];
2091 int i, offset;
2092
2093 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2094 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2095 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2096 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2097
2098 for (i = 0; i < 4; i++)
2099 val[i] = buffer_load_const(ctx, buf,
2100 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2101 value = ac_build_gather_values(&ctx->ac, val, 4);
2102 break;
2103 }
2104
2105 case TGSI_SEMANTIC_PRIMID:
2106 value = get_primitive_id(ctx, 0);
2107 break;
2108
2109 case TGSI_SEMANTIC_GRID_SIZE:
2110 value = ctx->abi.num_work_groups;
2111 break;
2112
2113 case TGSI_SEMANTIC_BLOCK_SIZE:
2114 value = get_block_size(&ctx->abi);
2115 break;
2116
2117 case TGSI_SEMANTIC_BLOCK_ID:
2118 {
2119 LLVMValueRef values[3];
2120
2121 for (int i = 0; i < 3; i++) {
2122 values[i] = ctx->i32_0;
2123 if (ctx->abi.workgroup_ids[i]) {
2124 values[i] = ctx->abi.workgroup_ids[i];
2125 }
2126 }
2127 value = ac_build_gather_values(&ctx->ac, values, 3);
2128 break;
2129 }
2130
2131 case TGSI_SEMANTIC_THREAD_ID:
2132 value = ctx->abi.local_invocation_ids;
2133 break;
2134
2135 case TGSI_SEMANTIC_HELPER_INVOCATION:
2136 value = ac_build_load_helper_invocation(&ctx->ac);
2137 break;
2138
2139 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2140 value = LLVMConstInt(ctx->i32, 64, 0);
2141 break;
2142
2143 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2144 value = ac_get_thread_id(&ctx->ac);
2145 break;
2146
2147 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2148 {
2149 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2150 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2151 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2152 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2153 break;
2154 }
2155
2156 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2157 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2158 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2159 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2160 {
2161 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2162 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2163 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2164 /* All bits set except LSB */
2165 value = LLVMConstInt(ctx->i64, -2, 0);
2166 } else {
2167 /* All bits set */
2168 value = LLVMConstInt(ctx->i64, -1, 0);
2169 }
2170 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2171 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2172 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2173 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2174 value = LLVMBuildNot(ctx->ac.builder, value, "");
2175 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2176 break;
2177 }
2178
2179 case TGSI_SEMANTIC_CS_USER_DATA:
2180 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2181 break;
2182
2183 default:
2184 assert(!"unknown system value");
2185 return;
2186 }
2187
2188 ctx->system_values[index] = value;
2189 }
2190
2191 void si_declare_compute_memory(struct si_shader_context *ctx)
2192 {
2193 struct si_shader_selector *sel = ctx->shader->selector;
2194 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2195
2196 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2197 LLVMValueRef var;
2198
2199 assert(!ctx->ac.lds);
2200
2201 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2202 LLVMArrayType(ctx->i8, lds_size),
2203 "compute_lds",
2204 AC_ADDR_SPACE_LDS);
2205 LLVMSetAlignment(var, 4);
2206
2207 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2208 }
2209
2210 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2211 const struct tgsi_full_declaration *decl)
2212 {
2213 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2214 assert(decl->Range.First == decl->Range.Last);
2215
2216 si_declare_compute_memory(ctx);
2217 }
2218
2219 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2220 {
2221 LLVMValueRef ptr =
2222 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2223 struct si_shader_selector *sel = ctx->shader->selector;
2224
2225 /* Do the bounds checking with a descriptor, because
2226 * doing computation and manual bounds checking of 64-bit
2227 * addresses generates horrible VALU code with very high
2228 * VGPR usage and very low SIMD occupancy.
2229 */
2230 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2231
2232 LLVMValueRef desc0, desc1;
2233 desc0 = ptr;
2234 desc1 = LLVMConstInt(ctx->i32,
2235 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2236
2237 LLVMValueRef desc_elems[] = {
2238 desc0,
2239 desc1,
2240 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2241 LLVMConstInt(ctx->i32,
2242 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2246 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2247 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2248 };
2249
2250 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2251 }
2252
2253 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2254 {
2255 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2256 ctx->param_const_and_shader_buffers);
2257
2258 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2259 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2260 }
2261
2262 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2263 {
2264 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2265 struct si_shader_selector *sel = ctx->shader->selector;
2266
2267 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2268
2269 if (sel->info.const_buffers_declared == 1 &&
2270 sel->info.shader_buffers_declared == 0) {
2271 return load_const_buffer_desc_fast_path(ctx);
2272 }
2273
2274 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2275 index = LLVMBuildAdd(ctx->ac.builder, index,
2276 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2277
2278 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2279 }
2280
2281 static LLVMValueRef
2282 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2283 {
2284 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2285 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2286 ctx->param_const_and_shader_buffers);
2287
2288 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2289 index = LLVMBuildSub(ctx->ac.builder,
2290 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2291 index, "");
2292
2293 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2294 }
2295
2296 static LLVMValueRef fetch_constant(
2297 struct lp_build_tgsi_context *bld_base,
2298 const struct tgsi_full_src_register *reg,
2299 enum tgsi_opcode_type type,
2300 unsigned swizzle_in)
2301 {
2302 struct si_shader_context *ctx = si_shader_context(bld_base);
2303 struct si_shader_selector *sel = ctx->shader->selector;
2304 const struct tgsi_ind_register *ireg = &reg->Indirect;
2305 unsigned buf, idx;
2306 unsigned swizzle = swizzle_in & 0xffff;
2307
2308 LLVMValueRef addr, bufp;
2309
2310 if (swizzle_in == LP_CHAN_ALL) {
2311 unsigned chan;
2312 LLVMValueRef values[4];
2313 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2314 values[chan] = fetch_constant(bld_base, reg, type, chan);
2315
2316 return ac_build_gather_values(&ctx->ac, values, 4);
2317 }
2318
2319 /* Split 64-bit loads. */
2320 if (tgsi_type_is_64bit(type)) {
2321 LLVMValueRef lo, hi;
2322
2323 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2324 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2325 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2326 lo, hi);
2327 }
2328
2329 idx = reg->Register.Index * 4 + swizzle;
2330 if (reg->Register.Indirect) {
2331 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2332 } else {
2333 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2334 }
2335
2336 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2337 if (sel->info.const_buffers_declared == 1 &&
2338 sel->info.shader_buffers_declared == 0) {
2339 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2340 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2341 return bitcast(bld_base, type, result);
2342 }
2343
2344 assert(reg->Register.Dimension);
2345 buf = reg->Dimension.Index;
2346
2347 if (reg->Dimension.Indirect) {
2348 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2349 LLVMValueRef index;
2350 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2351 reg->Dimension.Index,
2352 ctx->num_const_buffers);
2353 index = LLVMBuildAdd(ctx->ac.builder, index,
2354 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2355 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2356 } else
2357 bufp = load_const_buffer_desc(ctx, buf);
2358
2359 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2360 }
2361
2362 /* Initialize arguments for the shader export intrinsic */
2363 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2364 LLVMValueRef *values,
2365 unsigned target,
2366 struct ac_export_args *args)
2367 {
2368 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2369 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2370 unsigned chan;
2371 bool is_int8, is_int10;
2372
2373 /* Default is 0xf. Adjusted below depending on the format. */
2374 args->enabled_channels = 0xf; /* writemask */
2375
2376 /* Specify whether the EXEC mask represents the valid mask */
2377 args->valid_mask = 0;
2378
2379 /* Specify whether this is the last export */
2380 args->done = 0;
2381
2382 /* Specify the target we are exporting */
2383 args->target = target;
2384
2385 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2386 const struct si_shader_key *key = &ctx->shader->key;
2387 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2388 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2389
2390 assert(cbuf >= 0 && cbuf < 8);
2391 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2392 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2393 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2394 }
2395
2396 args->compr = false;
2397 args->out[0] = f32undef;
2398 args->out[1] = f32undef;
2399 args->out[2] = f32undef;
2400 args->out[3] = f32undef;
2401
2402 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2403 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2404 unsigned bits, bool hi) = NULL;
2405
2406 switch (spi_shader_col_format) {
2407 case V_028714_SPI_SHADER_ZERO:
2408 args->enabled_channels = 0; /* writemask */
2409 args->target = V_008DFC_SQ_EXP_NULL;
2410 break;
2411
2412 case V_028714_SPI_SHADER_32_R:
2413 args->enabled_channels = 1; /* writemask */
2414 args->out[0] = values[0];
2415 break;
2416
2417 case V_028714_SPI_SHADER_32_GR:
2418 args->enabled_channels = 0x3; /* writemask */
2419 args->out[0] = values[0];
2420 args->out[1] = values[1];
2421 break;
2422
2423 case V_028714_SPI_SHADER_32_AR:
2424 args->enabled_channels = 0x9; /* writemask */
2425 args->out[0] = values[0];
2426 args->out[3] = values[3];
2427 break;
2428
2429 case V_028714_SPI_SHADER_FP16_ABGR:
2430 packf = ac_build_cvt_pkrtz_f16;
2431 break;
2432
2433 case V_028714_SPI_SHADER_UNORM16_ABGR:
2434 packf = ac_build_cvt_pknorm_u16;
2435 break;
2436
2437 case V_028714_SPI_SHADER_SNORM16_ABGR:
2438 packf = ac_build_cvt_pknorm_i16;
2439 break;
2440
2441 case V_028714_SPI_SHADER_UINT16_ABGR:
2442 packi = ac_build_cvt_pk_u16;
2443 break;
2444
2445 case V_028714_SPI_SHADER_SINT16_ABGR:
2446 packi = ac_build_cvt_pk_i16;
2447 break;
2448
2449 case V_028714_SPI_SHADER_32_ABGR:
2450 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2451 break;
2452 }
2453
2454 /* Pack f16 or norm_i16/u16. */
2455 if (packf) {
2456 for (chan = 0; chan < 2; chan++) {
2457 LLVMValueRef pack_args[2] = {
2458 values[2 * chan],
2459 values[2 * chan + 1]
2460 };
2461 LLVMValueRef packed;
2462
2463 packed = packf(&ctx->ac, pack_args);
2464 args->out[chan] = ac_to_float(&ctx->ac, packed);
2465 }
2466 args->compr = 1; /* COMPR flag */
2467 }
2468 /* Pack i16/u16. */
2469 if (packi) {
2470 for (chan = 0; chan < 2; chan++) {
2471 LLVMValueRef pack_args[2] = {
2472 ac_to_integer(&ctx->ac, values[2 * chan]),
2473 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2474 };
2475 LLVMValueRef packed;
2476
2477 packed = packi(&ctx->ac, pack_args,
2478 is_int8 ? 8 : is_int10 ? 10 : 16,
2479 chan == 1);
2480 args->out[chan] = ac_to_float(&ctx->ac, packed);
2481 }
2482 args->compr = 1; /* COMPR flag */
2483 }
2484 }
2485
2486 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2487 LLVMValueRef alpha)
2488 {
2489 struct si_shader_context *ctx = si_shader_context(bld_base);
2490
2491 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2492 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2493 [PIPE_FUNC_LESS] = LLVMRealOLT,
2494 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2495 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2496 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2497 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2498 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2499 };
2500 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2501 assert(cond);
2502
2503 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2504 SI_PARAM_ALPHA_REF);
2505 LLVMValueRef alpha_pass =
2506 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2507 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2508 } else {
2509 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2510 }
2511 }
2512
2513 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2514 LLVMValueRef alpha,
2515 unsigned samplemask_param)
2516 {
2517 struct si_shader_context *ctx = si_shader_context(bld_base);
2518 LLVMValueRef coverage;
2519
2520 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2521 coverage = LLVMGetParam(ctx->main_fn,
2522 samplemask_param);
2523 coverage = ac_to_integer(&ctx->ac, coverage);
2524
2525 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2526 ctx->i32,
2527 &coverage, 1, AC_FUNC_ATTR_READNONE);
2528
2529 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2530 ctx->f32, "");
2531
2532 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2533 LLVMConstReal(ctx->f32,
2534 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2535
2536 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2537 }
2538
2539 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2540 struct ac_export_args *pos, LLVMValueRef *out_elts)
2541 {
2542 unsigned reg_index;
2543 unsigned chan;
2544 unsigned const_chan;
2545 LLVMValueRef base_elt;
2546 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2547 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2548 SI_VS_CONST_CLIP_PLANES, 0);
2549 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2550
2551 for (reg_index = 0; reg_index < 2; reg_index ++) {
2552 struct ac_export_args *args = &pos[2 + reg_index];
2553
2554 args->out[0] =
2555 args->out[1] =
2556 args->out[2] =
2557 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2558
2559 /* Compute dot products of position and user clip plane vectors */
2560 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2561 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2562 LLVMValueRef addr =
2563 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2564 const_chan) * 4, 0);
2565 base_elt = buffer_load_const(ctx, const_resource,
2566 addr);
2567 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2568 out_elts[const_chan], args->out[chan]);
2569 }
2570 }
2571
2572 args->enabled_channels = 0xf;
2573 args->valid_mask = 0;
2574 args->done = 0;
2575 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2576 args->compr = 0;
2577 }
2578 }
2579
2580 static void si_dump_streamout(struct pipe_stream_output_info *so)
2581 {
2582 unsigned i;
2583
2584 if (so->num_outputs)
2585 fprintf(stderr, "STREAMOUT\n");
2586
2587 for (i = 0; i < so->num_outputs; i++) {
2588 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2589 so->output[i].start_component;
2590 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2591 i, so->output[i].output_buffer,
2592 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2593 so->output[i].register_index,
2594 mask & 1 ? "x" : "",
2595 mask & 2 ? "y" : "",
2596 mask & 4 ? "z" : "",
2597 mask & 8 ? "w" : "");
2598 }
2599 }
2600
2601 static void emit_streamout_output(struct si_shader_context *ctx,
2602 LLVMValueRef const *so_buffers,
2603 LLVMValueRef const *so_write_offsets,
2604 struct pipe_stream_output *stream_out,
2605 struct si_shader_output_values *shader_out)
2606 {
2607 unsigned buf_idx = stream_out->output_buffer;
2608 unsigned start = stream_out->start_component;
2609 unsigned num_comps = stream_out->num_components;
2610 LLVMValueRef out[4];
2611
2612 assert(num_comps && num_comps <= 4);
2613 if (!num_comps || num_comps > 4)
2614 return;
2615
2616 /* Load the output as int. */
2617 for (int j = 0; j < num_comps; j++) {
2618 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2619
2620 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2621 }
2622
2623 /* Pack the output. */
2624 LLVMValueRef vdata = NULL;
2625
2626 switch (num_comps) {
2627 case 1: /* as i32 */
2628 vdata = out[0];
2629 break;
2630 case 2: /* as v2i32 */
2631 case 3: /* as v3i32 */
2632 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2633 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2634 break;
2635 }
2636 /* as v4i32 (aligned to 4) */
2637 out[3] = LLVMGetUndef(ctx->i32);
2638 /* fall through */
2639 case 4: /* as v4i32 */
2640 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2641 break;
2642 }
2643
2644 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2645 vdata, num_comps,
2646 so_write_offsets[buf_idx],
2647 ctx->i32_0,
2648 stream_out->dst_offset * 4, 1, 1, true, false);
2649 }
2650
2651 /**
2652 * Write streamout data to buffers for vertex stream @p stream (different
2653 * vertex streams can occur for GS copy shaders).
2654 */
2655 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2656 struct si_shader_output_values *outputs,
2657 unsigned noutput, unsigned stream)
2658 {
2659 struct si_shader_selector *sel = ctx->shader->selector;
2660 struct pipe_stream_output_info *so = &sel->so;
2661 LLVMBuilderRef builder = ctx->ac.builder;
2662 int i;
2663 struct lp_build_if_state if_ctx;
2664
2665 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2666 LLVMValueRef so_vtx_count =
2667 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2668
2669 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2670
2671 /* can_emit = tid < so_vtx_count; */
2672 LLVMValueRef can_emit =
2673 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2674
2675 /* Emit the streamout code conditionally. This actually avoids
2676 * out-of-bounds buffer access. The hw tells us via the SGPR
2677 * (so_vtx_count) which threads are allowed to emit streamout data. */
2678 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2679 {
2680 /* The buffer offset is computed as follows:
2681 * ByteOffset = streamout_offset[buffer_id]*4 +
2682 * (streamout_write_index + thread_id)*stride[buffer_id] +
2683 * attrib_offset
2684 */
2685
2686 LLVMValueRef so_write_index =
2687 LLVMGetParam(ctx->main_fn,
2688 ctx->param_streamout_write_index);
2689
2690 /* Compute (streamout_write_index + thread_id). */
2691 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2692
2693 /* Load the descriptor and compute the write offset for each
2694 * enabled buffer. */
2695 LLVMValueRef so_write_offset[4] = {};
2696 LLVMValueRef so_buffers[4];
2697 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2698 ctx->param_rw_buffers);
2699
2700 for (i = 0; i < 4; i++) {
2701 if (!so->stride[i])
2702 continue;
2703
2704 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2705 SI_VS_STREAMOUT_BUF0 + i, 0);
2706
2707 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2708
2709 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2710 ctx->param_streamout_offset[i]);
2711 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2712
2713 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2714 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2715 so_offset);
2716 }
2717
2718 /* Write streamout data. */
2719 for (i = 0; i < so->num_outputs; i++) {
2720 unsigned reg = so->output[i].register_index;
2721
2722 if (reg >= noutput)
2723 continue;
2724
2725 if (stream != so->output[i].stream)
2726 continue;
2727
2728 emit_streamout_output(ctx, so_buffers, so_write_offset,
2729 &so->output[i], &outputs[reg]);
2730 }
2731 }
2732 lp_build_endif(&if_ctx);
2733 }
2734
2735 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2736 LLVMValueRef *values)
2737 {
2738 struct ac_export_args args;
2739
2740 si_llvm_init_export_args(ctx, values,
2741 V_008DFC_SQ_EXP_PARAM + index, &args);
2742 ac_build_export(&ctx->ac, &args);
2743 }
2744
2745 static void si_build_param_exports(struct si_shader_context *ctx,
2746 struct si_shader_output_values *outputs,
2747 unsigned noutput)
2748 {
2749 struct si_shader *shader = ctx->shader;
2750 unsigned param_count = 0;
2751
2752 for (unsigned i = 0; i < noutput; i++) {
2753 unsigned semantic_name = outputs[i].semantic_name;
2754 unsigned semantic_index = outputs[i].semantic_index;
2755
2756 if (outputs[i].vertex_stream[0] != 0 &&
2757 outputs[i].vertex_stream[1] != 0 &&
2758 outputs[i].vertex_stream[2] != 0 &&
2759 outputs[i].vertex_stream[3] != 0)
2760 continue;
2761
2762 switch (semantic_name) {
2763 case TGSI_SEMANTIC_LAYER:
2764 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2765 case TGSI_SEMANTIC_CLIPDIST:
2766 case TGSI_SEMANTIC_COLOR:
2767 case TGSI_SEMANTIC_BCOLOR:
2768 case TGSI_SEMANTIC_PRIMID:
2769 case TGSI_SEMANTIC_FOG:
2770 case TGSI_SEMANTIC_TEXCOORD:
2771 case TGSI_SEMANTIC_GENERIC:
2772 break;
2773 default:
2774 continue;
2775 }
2776
2777 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2778 semantic_index < SI_MAX_IO_GENERIC) &&
2779 shader->key.opt.kill_outputs &
2780 (1ull << si_shader_io_get_unique_index(semantic_name,
2781 semantic_index, true)))
2782 continue;
2783
2784 si_export_param(ctx, param_count, outputs[i].values);
2785
2786 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2787 shader->info.vs_output_param_offset[i] = param_count++;
2788 }
2789
2790 shader->info.nr_param_exports = param_count;
2791 }
2792
2793 /**
2794 * Vertex color clamping.
2795 *
2796 * This uses a state constant loaded in a user data SGPR and
2797 * an IF statement is added that clamps all colors if the constant
2798 * is true.
2799 */
2800 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2801 struct si_shader_output_values *outputs,
2802 unsigned noutput)
2803 {
2804 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2805 bool has_colors = false;
2806
2807 /* Store original colors to alloca variables. */
2808 for (unsigned i = 0; i < noutput; i++) {
2809 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2810 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2811 continue;
2812
2813 for (unsigned j = 0; j < 4; j++) {
2814 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2815 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2816 }
2817 has_colors = true;
2818 }
2819
2820 if (!has_colors)
2821 return;
2822
2823 /* The state is in the first bit of the user SGPR. */
2824 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2825 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2826
2827 struct lp_build_if_state if_ctx;
2828 lp_build_if(&if_ctx, &ctx->gallivm, cond);
2829
2830 /* Store clamped colors to alloca variables within the conditional block. */
2831 for (unsigned i = 0; i < noutput; i++) {
2832 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2833 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2834 continue;
2835
2836 for (unsigned j = 0; j < 4; j++) {
2837 LLVMBuildStore(ctx->ac.builder,
2838 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2839 addr[i][j]);
2840 }
2841 }
2842 lp_build_endif(&if_ctx);
2843
2844 /* Load clamped colors */
2845 for (unsigned i = 0; i < noutput; i++) {
2846 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2847 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2848 continue;
2849
2850 for (unsigned j = 0; j < 4; j++) {
2851 outputs[i].values[j] =
2852 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2853 }
2854 }
2855 }
2856
2857 /* Generate export instructions for hardware VS shader stage */
2858 static void si_llvm_export_vs(struct si_shader_context *ctx,
2859 struct si_shader_output_values *outputs,
2860 unsigned noutput)
2861 {
2862 struct si_shader *shader = ctx->shader;
2863 struct ac_export_args pos_args[4] = {};
2864 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2865 unsigned pos_idx;
2866 int i;
2867
2868 si_vertex_color_clamping(ctx, outputs, noutput);
2869
2870 /* Build position exports. */
2871 for (i = 0; i < noutput; i++) {
2872 switch (outputs[i].semantic_name) {
2873 case TGSI_SEMANTIC_POSITION:
2874 si_llvm_init_export_args(ctx, outputs[i].values,
2875 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2876 break;
2877 case TGSI_SEMANTIC_PSIZE:
2878 psize_value = outputs[i].values[0];
2879 break;
2880 case TGSI_SEMANTIC_LAYER:
2881 layer_value = outputs[i].values[0];
2882 break;
2883 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2884 viewport_index_value = outputs[i].values[0];
2885 break;
2886 case TGSI_SEMANTIC_EDGEFLAG:
2887 edgeflag_value = outputs[i].values[0];
2888 break;
2889 case TGSI_SEMANTIC_CLIPDIST:
2890 if (!shader->key.opt.clip_disable) {
2891 unsigned index = 2 + outputs[i].semantic_index;
2892 si_llvm_init_export_args(ctx, outputs[i].values,
2893 V_008DFC_SQ_EXP_POS + index,
2894 &pos_args[index]);
2895 }
2896 break;
2897 case TGSI_SEMANTIC_CLIPVERTEX:
2898 if (!shader->key.opt.clip_disable) {
2899 si_llvm_emit_clipvertex(ctx, pos_args,
2900 outputs[i].values);
2901 }
2902 break;
2903 }
2904 }
2905
2906 /* We need to add the position output manually if it's missing. */
2907 if (!pos_args[0].out[0]) {
2908 pos_args[0].enabled_channels = 0xf; /* writemask */
2909 pos_args[0].valid_mask = 0; /* EXEC mask */
2910 pos_args[0].done = 0; /* last export? */
2911 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2912 pos_args[0].compr = 0; /* COMPR flag */
2913 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2914 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2915 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2916 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2917 }
2918
2919 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2920 if (shader->selector->info.writes_psize ||
2921 shader->selector->info.writes_edgeflag ||
2922 shader->selector->info.writes_viewport_index ||
2923 shader->selector->info.writes_layer) {
2924 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2925 (shader->selector->info.writes_edgeflag << 1) |
2926 (shader->selector->info.writes_layer << 2);
2927
2928 pos_args[1].valid_mask = 0; /* EXEC mask */
2929 pos_args[1].done = 0; /* last export? */
2930 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2931 pos_args[1].compr = 0; /* COMPR flag */
2932 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2933 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2934 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2935 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2936
2937 if (shader->selector->info.writes_psize)
2938 pos_args[1].out[0] = psize_value;
2939
2940 if (shader->selector->info.writes_edgeflag) {
2941 /* The output is a float, but the hw expects an integer
2942 * with the first bit containing the edge flag. */
2943 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2944 edgeflag_value,
2945 ctx->i32, "");
2946 edgeflag_value = ac_build_umin(&ctx->ac,
2947 edgeflag_value,
2948 ctx->i32_1);
2949
2950 /* The LLVM intrinsic expects a float. */
2951 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2952 }
2953
2954 if (ctx->screen->info.chip_class >= GFX9) {
2955 /* GFX9 has the layer in out.z[10:0] and the viewport
2956 * index in out.z[19:16].
2957 */
2958 if (shader->selector->info.writes_layer)
2959 pos_args[1].out[2] = layer_value;
2960
2961 if (shader->selector->info.writes_viewport_index) {
2962 LLVMValueRef v = viewport_index_value;
2963
2964 v = ac_to_integer(&ctx->ac, v);
2965 v = LLVMBuildShl(ctx->ac.builder, v,
2966 LLVMConstInt(ctx->i32, 16, 0), "");
2967 v = LLVMBuildOr(ctx->ac.builder, v,
2968 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2969 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2970 pos_args[1].enabled_channels |= 1 << 2;
2971 }
2972 } else {
2973 if (shader->selector->info.writes_layer)
2974 pos_args[1].out[2] = layer_value;
2975
2976 if (shader->selector->info.writes_viewport_index) {
2977 pos_args[1].out[3] = viewport_index_value;
2978 pos_args[1].enabled_channels |= 1 << 3;
2979 }
2980 }
2981 }
2982
2983 for (i = 0; i < 4; i++)
2984 if (pos_args[i].out[0])
2985 shader->info.nr_pos_exports++;
2986
2987 pos_idx = 0;
2988 for (i = 0; i < 4; i++) {
2989 if (!pos_args[i].out[0])
2990 continue;
2991
2992 /* Specify the target we are exporting */
2993 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2994
2995 if (pos_idx == shader->info.nr_pos_exports)
2996 /* Specify that this is the last export */
2997 pos_args[i].done = 1;
2998
2999 ac_build_export(&ctx->ac, &pos_args[i]);
3000 }
3001
3002 /* Build parameter exports. */
3003 si_build_param_exports(ctx, outputs, noutput);
3004 }
3005
3006 /**
3007 * Forward all outputs from the vertex shader to the TES. This is only used
3008 * for the fixed function TCS.
3009 */
3010 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3011 {
3012 struct si_shader_context *ctx = si_shader_context(bld_base);
3013 LLVMValueRef invocation_id, buffer, buffer_offset;
3014 LLVMValueRef lds_vertex_stride, lds_base;
3015 uint64_t inputs;
3016
3017 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3018 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3019 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3020
3021 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3022 lds_base = get_tcs_in_current_patch_offset(ctx);
3023 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3024 lds_base);
3025
3026 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3027 while (inputs) {
3028 unsigned i = u_bit_scan64(&inputs);
3029
3030 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3031 LLVMConstInt(ctx->i32, 4 * i, 0),
3032 "");
3033
3034 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3035 get_rel_patch_id(ctx),
3036 invocation_id,
3037 LLVMConstInt(ctx->i32, i, 0));
3038
3039 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3040 lds_ptr);
3041
3042 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3043 buffer_offset, 0, 1, 0, true, false);
3044 }
3045 }
3046
3047 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3048 LLVMValueRef rel_patch_id,
3049 LLVMValueRef invocation_id,
3050 LLVMValueRef tcs_out_current_patch_data_offset,
3051 LLVMValueRef invoc0_tf_outer[4],
3052 LLVMValueRef invoc0_tf_inner[2])
3053 {
3054 struct si_shader_context *ctx = si_shader_context(bld_base);
3055 struct si_shader *shader = ctx->shader;
3056 unsigned tess_inner_index, tess_outer_index;
3057 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3058 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3059 unsigned stride, outer_comps, inner_comps, i, offset;
3060 struct lp_build_if_state if_ctx, inner_if_ctx;
3061
3062 /* Add a barrier before loading tess factors from LDS. */
3063 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3064 si_llvm_emit_barrier(NULL, bld_base, NULL);
3065
3066 /* Do this only for invocation 0, because the tess levels are per-patch,
3067 * not per-vertex.
3068 *
3069 * This can't jump, because invocation 0 executes this. It should
3070 * at least mask out the loads and stores for other invocations.
3071 */
3072 lp_build_if(&if_ctx, &ctx->gallivm,
3073 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3074 invocation_id, ctx->i32_0, ""));
3075
3076 /* Determine the layout of one tess factor element in the buffer. */
3077 switch (shader->key.part.tcs.epilog.prim_mode) {
3078 case PIPE_PRIM_LINES:
3079 stride = 2; /* 2 dwords, 1 vec2 store */
3080 outer_comps = 2;
3081 inner_comps = 0;
3082 break;
3083 case PIPE_PRIM_TRIANGLES:
3084 stride = 4; /* 4 dwords, 1 vec4 store */
3085 outer_comps = 3;
3086 inner_comps = 1;
3087 break;
3088 case PIPE_PRIM_QUADS:
3089 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3090 outer_comps = 4;
3091 inner_comps = 2;
3092 break;
3093 default:
3094 assert(0);
3095 return;
3096 }
3097
3098 for (i = 0; i < 4; i++) {
3099 inner[i] = LLVMGetUndef(ctx->i32);
3100 outer[i] = LLVMGetUndef(ctx->i32);
3101 }
3102
3103 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3104 /* Tess factors are in VGPRs. */
3105 for (i = 0; i < outer_comps; i++)
3106 outer[i] = out[i] = invoc0_tf_outer[i];
3107 for (i = 0; i < inner_comps; i++)
3108 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3109 } else {
3110 /* Load tess_inner and tess_outer from LDS.
3111 * Any invocation can write them, so we can't get them from a temporary.
3112 */
3113 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3114 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3115
3116 lds_base = tcs_out_current_patch_data_offset;
3117 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3118 LLVMConstInt(ctx->i32,
3119 tess_inner_index * 4, 0), "");
3120 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3121 LLVMConstInt(ctx->i32,
3122 tess_outer_index * 4, 0), "");
3123
3124 for (i = 0; i < outer_comps; i++) {
3125 outer[i] = out[i] =
3126 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3127 }
3128 for (i = 0; i < inner_comps; i++) {
3129 inner[i] = out[outer_comps+i] =
3130 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3131 }
3132 }
3133
3134 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3135 /* For isolines, the hardware expects tess factors in the
3136 * reverse order from what GLSL / TGSI specify.
3137 */
3138 LLVMValueRef tmp = out[0];
3139 out[0] = out[1];
3140 out[1] = tmp;
3141 }
3142
3143 /* Convert the outputs to vectors for stores. */
3144 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3145 vec1 = NULL;
3146
3147 if (stride > 4)
3148 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3149
3150 /* Get the buffer. */
3151 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3152
3153 /* Get the offset. */
3154 tf_base = LLVMGetParam(ctx->main_fn,
3155 ctx->param_tcs_factor_offset);
3156 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3157 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3158
3159 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3160 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3161 rel_patch_id, ctx->i32_0, ""));
3162
3163 /* Store the dynamic HS control word. */
3164 offset = 0;
3165 if (ctx->screen->info.chip_class <= GFX8) {
3166 ac_build_buffer_store_dword(&ctx->ac, buffer,
3167 LLVMConstInt(ctx->i32, 0x80000000, 0),
3168 1, ctx->i32_0, tf_base,
3169 offset, 1, 0, true, false);
3170 offset += 4;
3171 }
3172
3173 lp_build_endif(&inner_if_ctx);
3174
3175 /* Store the tessellation factors. */
3176 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3177 MIN2(stride, 4), byteoffset, tf_base,
3178 offset, 1, 0, true, false);
3179 offset += 16;
3180 if (vec1)
3181 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3182 stride - 4, byteoffset, tf_base,
3183 offset, 1, 0, true, false);
3184
3185 /* Store the tess factors into the offchip buffer if TES reads them. */
3186 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3187 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3188 LLVMValueRef tf_inner_offset;
3189 unsigned param_outer, param_inner;
3190
3191 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3192 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3193
3194 param_outer = si_shader_io_get_unique_index_patch(
3195 TGSI_SEMANTIC_TESSOUTER, 0);
3196 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3197 LLVMConstInt(ctx->i32, param_outer, 0));
3198
3199 unsigned outer_vec_size =
3200 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3201 outer_comps : util_next_power_of_two(outer_comps);
3202 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3203
3204 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3205 outer_comps, tf_outer_offset,
3206 base, 0, 1, 0, true, false);
3207 if (inner_comps) {
3208 param_inner = si_shader_io_get_unique_index_patch(
3209 TGSI_SEMANTIC_TESSINNER, 0);
3210 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3211 LLVMConstInt(ctx->i32, param_inner, 0));
3212
3213 inner_vec = inner_comps == 1 ? inner[0] :
3214 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3215 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3216 inner_comps, tf_inner_offset,
3217 base, 0, 1, 0, true, false);
3218 }
3219 }
3220
3221 lp_build_endif(&if_ctx);
3222 }
3223
3224 static LLVMValueRef
3225 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3226 unsigned param, unsigned return_index)
3227 {
3228 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3229 LLVMGetParam(ctx->main_fn, param),
3230 return_index, "");
3231 }
3232
3233 static LLVMValueRef
3234 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3235 unsigned param, unsigned return_index)
3236 {
3237 LLVMBuilderRef builder = ctx->ac.builder;
3238 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3239
3240 return LLVMBuildInsertValue(builder, ret,
3241 ac_to_float(&ctx->ac, p),
3242 return_index, "");
3243 }
3244
3245 static LLVMValueRef
3246 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3247 unsigned param, unsigned return_index)
3248 {
3249 LLVMBuilderRef builder = ctx->ac.builder;
3250 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3251 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3252 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3253 }
3254
3255 /* This only writes the tessellation factor levels. */
3256 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3257 unsigned max_outputs,
3258 LLVMValueRef *addrs)
3259 {
3260 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3261 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3262 LLVMBuilderRef builder = ctx->ac.builder;
3263 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3264
3265 si_copy_tcs_inputs(bld_base);
3266
3267 rel_patch_id = get_rel_patch_id(ctx);
3268 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3269 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3270
3271 if (ctx->screen->info.chip_class >= GFX9) {
3272 LLVMBasicBlockRef blocks[2] = {
3273 LLVMGetInsertBlock(builder),
3274 ctx->merged_wrap_if_state.entry_block
3275 };
3276 LLVMValueRef values[2];
3277
3278 lp_build_endif(&ctx->merged_wrap_if_state);
3279
3280 values[0] = rel_patch_id;
3281 values[1] = LLVMGetUndef(ctx->i32);
3282 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3283
3284 values[0] = tf_lds_offset;
3285 values[1] = LLVMGetUndef(ctx->i32);
3286 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3287
3288 values[0] = invocation_id;
3289 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3290 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3291 }
3292
3293 /* Return epilog parameters from this function. */
3294 LLVMValueRef ret = ctx->return_value;
3295 unsigned vgpr;
3296
3297 if (ctx->screen->info.chip_class >= GFX9) {
3298 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3299 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3300 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3301 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3302 /* Tess offchip and tess factor offsets are at the beginning. */
3303 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3304 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3305 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3306 } else {
3307 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3308 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3309 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3310 GFX6_SGPR_TCS_OUT_LAYOUT);
3311 /* Tess offchip and tess factor offsets are after user SGPRs. */
3312 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3313 GFX6_TCS_NUM_USER_SGPR);
3314 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3315 GFX6_TCS_NUM_USER_SGPR + 1);
3316 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3317 }
3318
3319 /* VGPRs */
3320 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3321 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3322 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3323
3324 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3325 * the invocation_id output does not alias the tcs_rel_ids input,
3326 * which saves a V_MOV on gfx9.
3327 */
3328 vgpr += 2;
3329
3330 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3331 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3332
3333 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3334 vgpr++; /* skip the tess factor LDS offset */
3335 for (unsigned i = 0; i < 6; i++) {
3336 LLVMValueRef value =
3337 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3338 value = ac_to_float(&ctx->ac, value);
3339 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3340 }
3341 } else {
3342 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3343 }
3344 ctx->return_value = ret;
3345 }
3346
3347 /* Pass TCS inputs from LS to TCS on GFX9. */
3348 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3349 {
3350 LLVMValueRef ret = ctx->return_value;
3351
3352 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3353 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3354 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3355 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3356 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3357 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3358
3359 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3360 8 + SI_SGPR_RW_BUFFERS);
3361 ret = si_insert_input_ptr(ctx, ret,
3362 ctx->param_bindless_samplers_and_images,
3363 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3364
3365 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3366 8 + SI_SGPR_VS_STATE_BITS);
3367
3368 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3369 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3370 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3371 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3372 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3373 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3374
3375 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3376 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3377 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3378 vgpr++, "");
3379 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3380 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3381 vgpr++, "");
3382 ctx->return_value = ret;
3383 }
3384
3385 /* Pass GS inputs from ES to GS on GFX9. */
3386 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3387 {
3388 LLVMValueRef ret = ctx->return_value;
3389
3390 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3391 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3392 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3393 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3394 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3395
3396 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3397 8 + SI_SGPR_RW_BUFFERS);
3398 ret = si_insert_input_ptr(ctx, ret,
3399 ctx->param_bindless_samplers_and_images,
3400 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3401
3402 unsigned vgpr;
3403 if (ctx->type == PIPE_SHADER_VERTEX)
3404 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3405 else
3406 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3407
3408 for (unsigned i = 0; i < 5; i++) {
3409 unsigned param = ctx->param_gs_vtx01_offset + i;
3410 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3411 }
3412 ctx->return_value = ret;
3413 }
3414
3415 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3416 unsigned max_outputs,
3417 LLVMValueRef *addrs)
3418 {
3419 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3420 struct si_shader *shader = ctx->shader;
3421 struct tgsi_shader_info *info = &shader->selector->info;
3422 unsigned i, chan;
3423 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3424 ctx->param_rel_auto_id);
3425 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3426 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3427 vertex_dw_stride, "");
3428
3429 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3430 * its inputs from it. */
3431 for (i = 0; i < info->num_outputs; i++) {
3432 unsigned name = info->output_semantic_name[i];
3433 unsigned index = info->output_semantic_index[i];
3434
3435 /* The ARB_shader_viewport_layer_array spec contains the
3436 * following issue:
3437 *
3438 * 2) What happens if gl_ViewportIndex or gl_Layer is
3439 * written in the vertex shader and a geometry shader is
3440 * present?
3441 *
3442 * RESOLVED: The value written by the last vertex processing
3443 * stage is used. If the last vertex processing stage
3444 * (vertex, tessellation evaluation or geometry) does not
3445 * statically assign to gl_ViewportIndex or gl_Layer, index
3446 * or layer zero is assumed.
3447 *
3448 * So writes to those outputs in VS-as-LS are simply ignored.
3449 */
3450 if (name == TGSI_SEMANTIC_LAYER ||
3451 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3452 continue;
3453
3454 int param = si_shader_io_get_unique_index(name, index, false);
3455 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3456 LLVMConstInt(ctx->i32, param * 4, 0), "");
3457
3458 for (chan = 0; chan < 4; chan++) {
3459 if (!(info->output_usagemask[i] & (1 << chan)))
3460 continue;
3461
3462 lds_store(ctx, chan, dw_addr,
3463 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3464 }
3465 }
3466
3467 if (ctx->screen->info.chip_class >= GFX9)
3468 si_set_ls_return_value_for_tcs(ctx);
3469 }
3470
3471 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3472 unsigned max_outputs,
3473 LLVMValueRef *addrs)
3474 {
3475 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3476 struct si_shader *es = ctx->shader;
3477 struct tgsi_shader_info *info = &es->selector->info;
3478 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3479 ctx->param_es2gs_offset);
3480 LLVMValueRef lds_base = NULL;
3481 unsigned chan;
3482 int i;
3483
3484 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3485 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3486 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3487 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3488 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3489 LLVMBuildMul(ctx->ac.builder, wave_idx,
3490 LLVMConstInt(ctx->i32, 64, false), ""), "");
3491 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3492 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3493 }
3494
3495 for (i = 0; i < info->num_outputs; i++) {
3496 int param;
3497
3498 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3499 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3500 continue;
3501
3502 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3503 info->output_semantic_index[i], false);
3504
3505 for (chan = 0; chan < 4; chan++) {
3506 if (!(info->output_usagemask[i] & (1 << chan)))
3507 continue;
3508
3509 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3510 out_val = ac_to_integer(&ctx->ac, out_val);
3511
3512 /* GFX9 has the ESGS ring in LDS. */
3513 if (ctx->screen->info.chip_class >= GFX9) {
3514 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3515 continue;
3516 }
3517
3518 ac_build_buffer_store_dword(&ctx->ac,
3519 ctx->esgs_ring,
3520 out_val, 1, NULL, soffset,
3521 (4 * param + chan) * 4,
3522 1, 1, true, true);
3523 }
3524 }
3525
3526 if (ctx->screen->info.chip_class >= GFX9)
3527 si_set_es_return_value_for_gs(ctx);
3528 }
3529
3530 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3531 {
3532 if (ctx->screen->info.chip_class >= GFX9)
3533 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3534 else
3535 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3536 }
3537
3538 static void emit_gs_epilogue(struct si_shader_context *ctx)
3539 {
3540 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3541 si_get_gs_wave_id(ctx));
3542
3543 if (ctx->screen->info.chip_class >= GFX9)
3544 lp_build_endif(&ctx->merged_wrap_if_state);
3545 }
3546
3547 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3548 unsigned max_outputs,
3549 LLVMValueRef *addrs)
3550 {
3551 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3552 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3553
3554 assert(info->num_outputs <= max_outputs);
3555
3556 emit_gs_epilogue(ctx);
3557 }
3558
3559 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3560 {
3561 struct si_shader_context *ctx = si_shader_context(bld_base);
3562 emit_gs_epilogue(ctx);
3563 }
3564
3565 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3566 unsigned max_outputs,
3567 LLVMValueRef *addrs)
3568 {
3569 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3570 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3571 struct si_shader_output_values *outputs = NULL;
3572 int i,j;
3573
3574 assert(!ctx->shader->is_gs_copy_shader);
3575 assert(info->num_outputs <= max_outputs);
3576
3577 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3578
3579 for (i = 0; i < info->num_outputs; i++) {
3580 outputs[i].semantic_name = info->output_semantic_name[i];
3581 outputs[i].semantic_index = info->output_semantic_index[i];
3582
3583 for (j = 0; j < 4; j++) {
3584 outputs[i].values[j] =
3585 LLVMBuildLoad(ctx->ac.builder,
3586 addrs[4 * i + j],
3587 "");
3588 outputs[i].vertex_stream[j] =
3589 (info->output_streams[i] >> (2 * j)) & 3;
3590 }
3591 }
3592
3593 if (ctx->shader->selector->so.num_outputs)
3594 si_llvm_emit_streamout(ctx, outputs, i, 0);
3595
3596 /* Export PrimitiveID. */
3597 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3598 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3599 outputs[i].semantic_index = 0;
3600 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3601 for (j = 1; j < 4; j++)
3602 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3603
3604 memset(outputs[i].vertex_stream, 0,
3605 sizeof(outputs[i].vertex_stream));
3606 i++;
3607 }
3608
3609 si_llvm_export_vs(ctx, outputs, i);
3610 FREE(outputs);
3611 }
3612
3613 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3614 unsigned max_outputs,
3615 LLVMValueRef *addrs)
3616 {
3617 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3618 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3619 LLVMValueRef pos[4] = {};
3620
3621 assert(info->num_outputs <= max_outputs);
3622
3623 for (unsigned i = 0; i < info->num_outputs; i++) {
3624 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3625 continue;
3626
3627 for (unsigned chan = 0; chan < 4; chan++)
3628 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3629 break;
3630 }
3631 assert(pos[0] != NULL);
3632
3633 /* Return the position output. */
3634 LLVMValueRef ret = ctx->return_value;
3635 for (unsigned chan = 0; chan < 4; chan++)
3636 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3637 ctx->return_value = ret;
3638 }
3639
3640 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3641 {
3642 struct si_shader_context *ctx = si_shader_context(bld_base);
3643
3644 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3645 &ctx->outputs[0][0]);
3646 }
3647
3648 struct si_ps_exports {
3649 unsigned num;
3650 struct ac_export_args args[10];
3651 };
3652
3653 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3654 LLVMValueRef depth, LLVMValueRef stencil,
3655 LLVMValueRef samplemask, struct si_ps_exports *exp)
3656 {
3657 struct si_shader_context *ctx = si_shader_context(bld_base);
3658 struct ac_export_args args;
3659
3660 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3661
3662 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3663 }
3664
3665 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3666 LLVMValueRef *color, unsigned index,
3667 unsigned samplemask_param,
3668 bool is_last, struct si_ps_exports *exp)
3669 {
3670 struct si_shader_context *ctx = si_shader_context(bld_base);
3671 int i;
3672
3673 /* Clamp color */
3674 if (ctx->shader->key.part.ps.epilog.clamp_color)
3675 for (i = 0; i < 4; i++)
3676 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3677
3678 /* Alpha to one */
3679 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3680 color[3] = ctx->ac.f32_1;
3681
3682 /* Alpha test */
3683 if (index == 0 &&
3684 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3685 si_alpha_test(bld_base, color[3]);
3686
3687 /* Line & polygon smoothing */
3688 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3689 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3690 samplemask_param);
3691
3692 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3693 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3694 struct ac_export_args args[8];
3695 int c, last = -1;
3696
3697 /* Get the export arguments, also find out what the last one is. */
3698 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3699 si_llvm_init_export_args(ctx, color,
3700 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3701 if (args[c].enabled_channels)
3702 last = c;
3703 }
3704
3705 /* Emit all exports. */
3706 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3707 if (is_last && last == c) {
3708 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3709 args[c].done = 1; /* DONE bit */
3710 } else if (!args[c].enabled_channels)
3711 continue; /* unnecessary NULL export */
3712
3713 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3714 }
3715 } else {
3716 struct ac_export_args args;
3717
3718 /* Export */
3719 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3720 &args);
3721 if (is_last) {
3722 args.valid_mask = 1; /* whether the EXEC mask is valid */
3723 args.done = 1; /* DONE bit */
3724 } else if (!args.enabled_channels)
3725 return; /* unnecessary NULL export */
3726
3727 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3728 }
3729 }
3730
3731 static void si_emit_ps_exports(struct si_shader_context *ctx,
3732 struct si_ps_exports *exp)
3733 {
3734 for (unsigned i = 0; i < exp->num; i++)
3735 ac_build_export(&ctx->ac, &exp->args[i]);
3736 }
3737
3738 /**
3739 * Return PS outputs in this order:
3740 *
3741 * v[0:3] = color0.xyzw
3742 * v[4:7] = color1.xyzw
3743 * ...
3744 * vN+0 = Depth
3745 * vN+1 = Stencil
3746 * vN+2 = SampleMask
3747 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3748 *
3749 * The alpha-ref SGPR is returned via its original location.
3750 */
3751 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3752 unsigned max_outputs,
3753 LLVMValueRef *addrs)
3754 {
3755 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3756 struct si_shader *shader = ctx->shader;
3757 struct tgsi_shader_info *info = &shader->selector->info;
3758 LLVMBuilderRef builder = ctx->ac.builder;
3759 unsigned i, j, first_vgpr, vgpr;
3760
3761 LLVMValueRef color[8][4] = {};
3762 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3763 LLVMValueRef ret;
3764
3765 if (ctx->postponed_kill)
3766 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3767
3768 /* Read the output values. */
3769 for (i = 0; i < info->num_outputs; i++) {
3770 unsigned semantic_name = info->output_semantic_name[i];
3771 unsigned semantic_index = info->output_semantic_index[i];
3772
3773 switch (semantic_name) {
3774 case TGSI_SEMANTIC_COLOR:
3775 assert(semantic_index < 8);
3776 for (j = 0; j < 4; j++) {
3777 LLVMValueRef ptr = addrs[4 * i + j];
3778 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3779 color[semantic_index][j] = result;
3780 }
3781 break;
3782 case TGSI_SEMANTIC_POSITION:
3783 depth = LLVMBuildLoad(builder,
3784 addrs[4 * i + 2], "");
3785 break;
3786 case TGSI_SEMANTIC_STENCIL:
3787 stencil = LLVMBuildLoad(builder,
3788 addrs[4 * i + 1], "");
3789 break;
3790 case TGSI_SEMANTIC_SAMPLEMASK:
3791 samplemask = LLVMBuildLoad(builder,
3792 addrs[4 * i + 0], "");
3793 break;
3794 default:
3795 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3796 semantic_name);
3797 }
3798 }
3799
3800 /* Fill the return structure. */
3801 ret = ctx->return_value;
3802
3803 /* Set SGPRs. */
3804 ret = LLVMBuildInsertValue(builder, ret,
3805 ac_to_integer(&ctx->ac,
3806 LLVMGetParam(ctx->main_fn,
3807 SI_PARAM_ALPHA_REF)),
3808 SI_SGPR_ALPHA_REF, "");
3809
3810 /* Set VGPRs */
3811 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3812 for (i = 0; i < ARRAY_SIZE(color); i++) {
3813 if (!color[i][0])
3814 continue;
3815
3816 for (j = 0; j < 4; j++)
3817 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3818 }
3819 if (depth)
3820 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3821 if (stencil)
3822 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3823 if (samplemask)
3824 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3825
3826 /* Add the input sample mask for smoothing at the end. */
3827 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3828 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3829 ret = LLVMBuildInsertValue(builder, ret,
3830 LLVMGetParam(ctx->main_fn,
3831 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3832
3833 ctx->return_value = ret;
3834 }
3835
3836 static void membar_emit(
3837 const struct lp_build_tgsi_action *action,
3838 struct lp_build_tgsi_context *bld_base,
3839 struct lp_build_emit_data *emit_data)
3840 {
3841 struct si_shader_context *ctx = si_shader_context(bld_base);
3842 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3843 unsigned flags = LLVMConstIntGetZExtValue(src0);
3844 unsigned waitcnt = NOOP_WAITCNT;
3845
3846 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3847 waitcnt &= VM_CNT & LGKM_CNT;
3848
3849 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3850 TGSI_MEMBAR_SHADER_BUFFER |
3851 TGSI_MEMBAR_SHADER_IMAGE))
3852 waitcnt &= VM_CNT;
3853
3854 if (flags & TGSI_MEMBAR_SHARED)
3855 waitcnt &= LGKM_CNT;
3856
3857 if (waitcnt != NOOP_WAITCNT)
3858 ac_build_waitcnt(&ctx->ac, waitcnt);
3859 }
3860
3861 static void clock_emit(
3862 const struct lp_build_tgsi_action *action,
3863 struct lp_build_tgsi_context *bld_base,
3864 struct lp_build_emit_data *emit_data)
3865 {
3866 struct si_shader_context *ctx = si_shader_context(bld_base);
3867 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3868
3869 emit_data->output[0] =
3870 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3871 emit_data->output[1] =
3872 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3873 }
3874
3875 static void si_llvm_emit_ddxy(
3876 const struct lp_build_tgsi_action *action,
3877 struct lp_build_tgsi_context *bld_base,
3878 struct lp_build_emit_data *emit_data)
3879 {
3880 struct si_shader_context *ctx = si_shader_context(bld_base);
3881 unsigned opcode = emit_data->info->opcode;
3882 LLVMValueRef val;
3883 int idx;
3884 unsigned mask;
3885
3886 if (opcode == TGSI_OPCODE_DDX_FINE)
3887 mask = AC_TID_MASK_LEFT;
3888 else if (opcode == TGSI_OPCODE_DDY_FINE)
3889 mask = AC_TID_MASK_TOP;
3890 else
3891 mask = AC_TID_MASK_TOP_LEFT;
3892
3893 /* for DDX we want to next X pixel, DDY next Y pixel. */
3894 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3895
3896 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3897 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3898 emit_data->output[emit_data->chan] = val;
3899 }
3900
3901 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3902 struct lp_build_tgsi_context *bld_base,
3903 struct lp_build_emit_data *emit_data)
3904 {
3905 struct si_shader_context *ctx = si_shader_context(bld_base);
3906 struct si_shader *shader = ctx->shader;
3907 const struct tgsi_shader_info *info = &shader->selector->info;
3908 LLVMValueRef interp_param;
3909 const struct tgsi_full_instruction *inst = emit_data->inst;
3910 const struct tgsi_full_src_register *input = &inst->Src[0];
3911 int input_base, input_array_size;
3912 int chan;
3913 int i;
3914 LLVMValueRef prim_mask = ctx->abi.prim_mask;
3915 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
3916 int interp_param_idx;
3917 unsigned interp;
3918 unsigned location;
3919
3920 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3921 /* offset is in second src, first two channels */
3922 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3923 TGSI_CHAN_X);
3924 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
3925 TGSI_CHAN_Y);
3926 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3927 LLVMValueRef sample_position;
3928 LLVMValueRef sample_id;
3929 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3930
3931 /* fetch sample ID, then fetch its sample position,
3932 * and place into first two channels.
3933 */
3934 sample_id = lp_build_emit_fetch(bld_base,
3935 emit_data->inst, 1, TGSI_CHAN_X);
3936 sample_id = ac_to_integer(&ctx->ac, sample_id);
3937
3938 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3939 * Language 4.50 spec says about interpolateAtSample:
3940 *
3941 * "Returns the value of the input interpolant variable at
3942 * the location of sample number sample. If multisample
3943 * buffers are not available, the input variable will be
3944 * evaluated at the center of the pixel. If sample sample
3945 * does not exist, the position used to interpolate the
3946 * input variable is undefined."
3947 *
3948 * This means that sample_id values outside of the valid are
3949 * in fact valid input, and the usual mechanism for loading the
3950 * sample position doesn't work.
3951 */
3952 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3953 LLVMValueRef center[4] = {
3954 LLVMConstReal(ctx->f32, 0.5),
3955 LLVMConstReal(ctx->f32, 0.5),
3956 ctx->ac.f32_0,
3957 ctx->ac.f32_0,
3958 };
3959
3960 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
3961 } else {
3962 sample_position = load_sample_position(&ctx->abi, sample_id);
3963 }
3964
3965 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3966 ctx->i32_0, "");
3967
3968 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
3969 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
3970 ctx->i32_1, "");
3971 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
3972 }
3973
3974 assert(input->Register.File == TGSI_FILE_INPUT);
3975
3976 if (input->Register.Indirect) {
3977 unsigned array_id = input->Indirect.ArrayID;
3978
3979 if (array_id) {
3980 input_base = info->input_array_first[array_id];
3981 input_array_size = info->input_array_last[array_id] - input_base + 1;
3982 } else {
3983 input_base = inst->Src[0].Register.Index;
3984 input_array_size = info->num_inputs - input_base;
3985 }
3986
3987 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3988 1, input->Register.Index - input_base);
3989 } else {
3990 input_base = inst->Src[0].Register.Index;
3991 input_array_size = 1;
3992 array_idx = ctx->i32_0;
3993 }
3994
3995 interp = shader->selector->info.input_interpolate[input_base];
3996
3997 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3998 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3999 location = TGSI_INTERPOLATE_LOC_CENTER;
4000 else
4001 location = TGSI_INTERPOLATE_LOC_CENTROID;
4002
4003 interp_param_idx = lookup_interp_param_index(interp, location);
4004 if (interp_param_idx == -1)
4005 return;
4006 else if (interp_param_idx)
4007 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4008 else
4009 interp_param = NULL;
4010
4011 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4012 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4013 LLVMValueRef ij_out[2];
4014 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4015
4016 /*
4017 * take the I then J parameters, and the DDX/Y for it, and
4018 * calculate the IJ inputs for the interpolator.
4019 * temp1 = ddx * offset/sample.x + I;
4020 * interp_param.I = ddy * offset/sample.y + temp1;
4021 * temp1 = ddx * offset/sample.x + J;
4022 * interp_param.J = ddy * offset/sample.y + temp1;
4023 */
4024 for (i = 0; i < 2; i++) {
4025 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4026 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4027 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4028 ddxy_out, ix_ll, "");
4029 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4030 ddxy_out, iy_ll, "");
4031 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4032 interp_param, ix_ll, "");
4033 LLVMValueRef temp;
4034
4035 interp_el = ac_to_float(&ctx->ac, interp_el);
4036
4037 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4038 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4039 }
4040 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4041 }
4042
4043 if (interp_param)
4044 interp_param = ac_to_float(&ctx->ac, interp_param);
4045
4046 for (chan = 0; chan < 4; chan++) {
4047 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4048 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4049
4050 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4051 LLVMValueRef v, i = NULL, j = NULL;
4052
4053 if (interp_param) {
4054 i = LLVMBuildExtractElement(
4055 ctx->ac.builder, interp_param, ctx->i32_0, "");
4056 j = LLVMBuildExtractElement(
4057 ctx->ac.builder, interp_param, ctx->i32_1, "");
4058 }
4059 v = si_build_fs_interp(ctx, input_base + idx, schan,
4060 prim_mask, i, j);
4061
4062 gather = LLVMBuildInsertElement(ctx->ac.builder,
4063 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4064 }
4065
4066 emit_data->output[chan] = LLVMBuildExtractElement(
4067 ctx->ac.builder, gather, array_idx, "");
4068 }
4069 }
4070
4071 static void vote_all_emit(
4072 const struct lp_build_tgsi_action *action,
4073 struct lp_build_tgsi_context *bld_base,
4074 struct lp_build_emit_data *emit_data)
4075 {
4076 struct si_shader_context *ctx = si_shader_context(bld_base);
4077
4078 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4079 emit_data->output[emit_data->chan] =
4080 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4081 }
4082
4083 static void vote_any_emit(
4084 const struct lp_build_tgsi_action *action,
4085 struct lp_build_tgsi_context *bld_base,
4086 struct lp_build_emit_data *emit_data)
4087 {
4088 struct si_shader_context *ctx = si_shader_context(bld_base);
4089
4090 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4091 emit_data->output[emit_data->chan] =
4092 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4093 }
4094
4095 static void vote_eq_emit(
4096 const struct lp_build_tgsi_action *action,
4097 struct lp_build_tgsi_context *bld_base,
4098 struct lp_build_emit_data *emit_data)
4099 {
4100 struct si_shader_context *ctx = si_shader_context(bld_base);
4101
4102 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4103 emit_data->output[emit_data->chan] =
4104 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4105 }
4106
4107 static void ballot_emit(
4108 const struct lp_build_tgsi_action *action,
4109 struct lp_build_tgsi_context *bld_base,
4110 struct lp_build_emit_data *emit_data)
4111 {
4112 struct si_shader_context *ctx = si_shader_context(bld_base);
4113 LLVMBuilderRef builder = ctx->ac.builder;
4114 LLVMValueRef tmp;
4115
4116 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4117 tmp = ac_build_ballot(&ctx->ac, tmp);
4118 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4119
4120 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4121 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4122 }
4123
4124 static void read_lane_emit(
4125 const struct lp_build_tgsi_action *action,
4126 struct lp_build_tgsi_context *bld_base,
4127 struct lp_build_emit_data *emit_data)
4128 {
4129 struct si_shader_context *ctx = si_shader_context(bld_base);
4130
4131 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4132 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4133 0, emit_data->src_chan);
4134
4135 /* Always read the source invocation (= lane) from the X channel. */
4136 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4137 1, TGSI_CHAN_X);
4138 emit_data->arg_count = 2;
4139 }
4140
4141 /* We currently have no other way to prevent LLVM from lifting the icmp
4142 * calls to a dominating basic block.
4143 */
4144 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4145
4146 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4147 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4148
4149 emit_data->output[emit_data->chan] =
4150 ac_build_intrinsic(&ctx->ac, action->intr_name,
4151 ctx->i32, emit_data->args, emit_data->arg_count,
4152 AC_FUNC_ATTR_READNONE |
4153 AC_FUNC_ATTR_CONVERGENT);
4154 }
4155
4156 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4157 struct lp_build_emit_data *emit_data)
4158 {
4159 struct si_shader_context *ctx = si_shader_context(bld_base);
4160 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4161 LLVMValueRef imm;
4162 unsigned stream;
4163
4164 assert(src0.File == TGSI_FILE_IMMEDIATE);
4165
4166 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4167 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4168 return stream;
4169 }
4170
4171 /* Emit one vertex from the geometry shader */
4172 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4173 unsigned stream,
4174 LLVMValueRef *addrs)
4175 {
4176 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4177 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4178 struct si_shader *shader = ctx->shader;
4179 struct lp_build_if_state if_state;
4180 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4181 ctx->param_gs2vs_offset);
4182 LLVMValueRef gs_next_vertex;
4183 LLVMValueRef can_emit;
4184 unsigned chan, offset;
4185 int i;
4186
4187 /* Write vertex attribute values to GSVS ring */
4188 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4189 ctx->gs_next_vertex[stream],
4190 "");
4191
4192 /* If this thread has already emitted the declared maximum number of
4193 * vertices, skip the write: excessive vertex emissions are not
4194 * supposed to have any effect.
4195 *
4196 * If the shader has no writes to memory, kill it instead. This skips
4197 * further memory loads and may allow LLVM to skip to the end
4198 * altogether.
4199 */
4200 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4201 LLVMConstInt(ctx->i32,
4202 shader->selector->gs_max_out_vertices, 0), "");
4203
4204 bool use_kill = !info->writes_memory;
4205 if (use_kill) {
4206 ac_build_kill_if_false(&ctx->ac, can_emit);
4207 } else {
4208 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4209 }
4210
4211 offset = 0;
4212 for (i = 0; i < info->num_outputs; i++) {
4213 for (chan = 0; chan < 4; chan++) {
4214 if (!(info->output_usagemask[i] & (1 << chan)) ||
4215 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4216 continue;
4217
4218 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4219 LLVMValueRef voffset =
4220 LLVMConstInt(ctx->i32, offset *
4221 shader->selector->gs_max_out_vertices, 0);
4222 offset++;
4223
4224 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4225 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4226 LLVMConstInt(ctx->i32, 4, 0), "");
4227
4228 out_val = ac_to_integer(&ctx->ac, out_val);
4229
4230 ac_build_buffer_store_dword(&ctx->ac,
4231 ctx->gsvs_ring[stream],
4232 out_val, 1,
4233 voffset, soffset, 0,
4234 1, 1, true, true);
4235 }
4236 }
4237
4238 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4239 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4240
4241 /* Signal vertex emission if vertex data was written. */
4242 if (offset) {
4243 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4244 si_get_gs_wave_id(ctx));
4245 }
4246
4247 if (!use_kill)
4248 lp_build_endif(&if_state);
4249 }
4250
4251 /* Emit one vertex from the geometry shader */
4252 static void si_tgsi_emit_vertex(
4253 const struct lp_build_tgsi_action *action,
4254 struct lp_build_tgsi_context *bld_base,
4255 struct lp_build_emit_data *emit_data)
4256 {
4257 struct si_shader_context *ctx = si_shader_context(bld_base);
4258 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4259
4260 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4261 }
4262
4263 /* Cut one primitive from the geometry shader */
4264 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4265 unsigned stream)
4266 {
4267 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4268
4269 /* Signal primitive cut */
4270 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4271 si_get_gs_wave_id(ctx));
4272 }
4273
4274 /* Cut one primitive from the geometry shader */
4275 static void si_tgsi_emit_primitive(
4276 const struct lp_build_tgsi_action *action,
4277 struct lp_build_tgsi_context *bld_base,
4278 struct lp_build_emit_data *emit_data)
4279 {
4280 struct si_shader_context *ctx = si_shader_context(bld_base);
4281
4282 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4283 }
4284
4285 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4286 struct lp_build_tgsi_context *bld_base,
4287 struct lp_build_emit_data *emit_data)
4288 {
4289 struct si_shader_context *ctx = si_shader_context(bld_base);
4290
4291 /* GFX6 only (thanks to a hw bug workaround):
4292 * The real barrier instruction isn’t needed, because an entire patch
4293 * always fits into a single wave.
4294 */
4295 if (ctx->screen->info.chip_class == GFX6 &&
4296 ctx->type == PIPE_SHADER_TESS_CTRL) {
4297 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4298 return;
4299 }
4300
4301 ac_build_s_barrier(&ctx->ac);
4302 }
4303
4304 void si_create_function(struct si_shader_context *ctx,
4305 const char *name,
4306 LLVMTypeRef *returns, unsigned num_returns,
4307 struct si_function_info *fninfo,
4308 unsigned max_workgroup_size)
4309 {
4310 int i;
4311
4312 si_llvm_create_func(ctx, name, returns, num_returns,
4313 fninfo->types, fninfo->num_params);
4314 ctx->return_value = LLVMGetUndef(ctx->return_type);
4315
4316 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4317 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4318
4319 /* The combination of:
4320 * - noalias
4321 * - dereferenceable
4322 * - invariant.load
4323 * allows the optimization passes to move loads and reduces
4324 * SGPR spilling significantly.
4325 */
4326 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4327 AC_FUNC_ATTR_INREG);
4328
4329 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4330 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4331 AC_FUNC_ATTR_NOALIAS);
4332 ac_add_attr_dereferenceable(P, UINT64_MAX);
4333 }
4334 }
4335
4336 for (i = 0; i < fninfo->num_params; ++i) {
4337 if (fninfo->assign[i])
4338 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4339 }
4340
4341 if (ctx->screen->info.address32_hi) {
4342 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4343 "amdgpu-32bit-address-high-bits",
4344 ctx->screen->info.address32_hi);
4345 }
4346
4347 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4348
4349 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4350 "no-signed-zeros-fp-math",
4351 "true");
4352
4353 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4354 /* These were copied from some LLVM test. */
4355 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4356 "less-precise-fpmad",
4357 "true");
4358 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4359 "no-infs-fp-math",
4360 "true");
4361 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4362 "no-nans-fp-math",
4363 "true");
4364 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4365 "unsafe-fp-math",
4366 "true");
4367 }
4368 }
4369
4370 static void declare_streamout_params(struct si_shader_context *ctx,
4371 struct pipe_stream_output_info *so,
4372 struct si_function_info *fninfo)
4373 {
4374 int i;
4375
4376 /* Streamout SGPRs. */
4377 if (so->num_outputs) {
4378 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4379 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4380 else
4381 ctx->param_streamout_config = fninfo->num_params - 1;
4382
4383 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4384 }
4385 /* A streamout buffer offset is loaded if the stride is non-zero. */
4386 for (i = 0; i < 4; i++) {
4387 if (!so->stride[i])
4388 continue;
4389
4390 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4391 }
4392 }
4393
4394 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4395 {
4396 switch (shader->selector->type) {
4397 case PIPE_SHADER_TESS_CTRL:
4398 /* Return this so that LLVM doesn't remove s_barrier
4399 * instructions on chips where we use s_barrier. */
4400 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 64;
4401
4402 case PIPE_SHADER_GEOMETRY:
4403 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4404
4405 case PIPE_SHADER_COMPUTE:
4406 break; /* see below */
4407
4408 default:
4409 return 0;
4410 }
4411
4412 const unsigned *properties = shader->selector->info.properties;
4413 unsigned max_work_group_size =
4414 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4415 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4416 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4417
4418 if (!max_work_group_size) {
4419 /* This is a variable group size compute shader,
4420 * compile it for the maximum possible group size.
4421 */
4422 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4423 }
4424 return max_work_group_size;
4425 }
4426
4427 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4428 struct si_function_info *fninfo,
4429 bool assign_params)
4430 {
4431 LLVMTypeRef const_shader_buf_type;
4432
4433 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4434 ctx->shader->selector->info.shader_buffers_declared == 0)
4435 const_shader_buf_type = ctx->f32;
4436 else
4437 const_shader_buf_type = ctx->v4i32;
4438
4439 unsigned const_and_shader_buffers =
4440 add_arg(fninfo, ARG_SGPR,
4441 ac_array_in_const32_addr_space(const_shader_buf_type));
4442
4443 if (assign_params)
4444 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4445 }
4446
4447 static void declare_samplers_and_images(struct si_shader_context *ctx,
4448 struct si_function_info *fninfo,
4449 bool assign_params)
4450 {
4451 unsigned samplers_and_images =
4452 add_arg(fninfo, ARG_SGPR,
4453 ac_array_in_const32_addr_space(ctx->v8i32));
4454
4455 if (assign_params)
4456 ctx->param_samplers_and_images = samplers_and_images;
4457 }
4458
4459 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4460 struct si_function_info *fninfo,
4461 bool assign_params)
4462 {
4463 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4464 declare_samplers_and_images(ctx, fninfo, assign_params);
4465 }
4466
4467 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4468 struct si_function_info *fninfo)
4469 {
4470 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4471 ac_array_in_const32_addr_space(ctx->v4i32));
4472 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4473 ac_array_in_const32_addr_space(ctx->v8i32));
4474 }
4475
4476 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4477 struct si_function_info *fninfo)
4478 {
4479 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4480 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4481 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4482 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4483 }
4484
4485 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4486 struct si_function_info *fninfo,
4487 unsigned *num_prolog_vgprs)
4488 {
4489 struct si_shader *shader = ctx->shader;
4490
4491 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4492 if (shader->key.as_ls) {
4493 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4494 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4495 } else {
4496 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4497 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4498 }
4499 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4500
4501 if (!shader->is_gs_copy_shader) {
4502 /* Vertex load indices. */
4503 ctx->param_vertex_index0 = fninfo->num_params;
4504 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4505 add_arg(fninfo, ARG_VGPR, ctx->i32);
4506 *num_prolog_vgprs += shader->selector->info.num_inputs;
4507 }
4508 }
4509
4510 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4511 struct si_function_info *fninfo,
4512 unsigned vs_blit_property)
4513 {
4514 ctx->param_vs_blit_inputs = fninfo->num_params;
4515 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4516 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4517 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4518
4519 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4520 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4521 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4522 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4523 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4524 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4525 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4526 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4527 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4528 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4529 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4530 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4531 }
4532 }
4533
4534 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4535 struct si_function_info *fninfo)
4536 {
4537 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4538 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4539 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4540 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4541 }
4542
4543 enum {
4544 /* Convenient merged shader definitions. */
4545 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4546 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4547 };
4548
4549 static void create_function(struct si_shader_context *ctx)
4550 {
4551 struct si_shader *shader = ctx->shader;
4552 struct si_function_info fninfo;
4553 LLVMTypeRef returns[16+32*4];
4554 unsigned i, num_return_sgprs;
4555 unsigned num_returns = 0;
4556 unsigned num_prolog_vgprs = 0;
4557 unsigned type = ctx->type;
4558 unsigned vs_blit_property =
4559 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4560
4561 si_init_function_info(&fninfo);
4562
4563 /* Set MERGED shaders. */
4564 if (ctx->screen->info.chip_class >= GFX9) {
4565 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4566 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4567 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4568 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4569 }
4570
4571 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4572
4573 switch (type) {
4574 case PIPE_SHADER_VERTEX:
4575 declare_global_desc_pointers(ctx, &fninfo);
4576
4577 if (vs_blit_property) {
4578 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4579
4580 /* VGPRs */
4581 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4582 break;
4583 }
4584
4585 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4586 declare_vs_specific_input_sgprs(ctx, &fninfo);
4587 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4588 ac_array_in_const32_addr_space(ctx->v4i32));
4589
4590 if (shader->key.as_es) {
4591 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4592 } else if (shader->key.as_ls) {
4593 /* no extra parameters */
4594 } else {
4595 if (shader->is_gs_copy_shader) {
4596 fninfo.num_params = ctx->param_vs_state_bits + 1;
4597 fninfo.num_sgpr_params = fninfo.num_params;
4598 }
4599
4600 /* The locations of the other parameters are assigned dynamically. */
4601 declare_streamout_params(ctx, &shader->selector->so,
4602 &fninfo);
4603 }
4604
4605 /* VGPRs */
4606 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4607
4608 /* Return values */
4609 if (shader->key.opt.vs_as_prim_discard_cs) {
4610 for (i = 0; i < 4; i++)
4611 returns[num_returns++] = ctx->f32; /* VGPRs */
4612 }
4613 break;
4614
4615 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4616 declare_global_desc_pointers(ctx, &fninfo);
4617 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4618 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4619 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4620 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4621 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4622 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4623 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4624
4625 /* VGPRs */
4626 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4627 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4628
4629 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4630 * placed after the user SGPRs.
4631 */
4632 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4633 returns[num_returns++] = ctx->i32; /* SGPRs */
4634 for (i = 0; i < 11; i++)
4635 returns[num_returns++] = ctx->f32; /* VGPRs */
4636 break;
4637
4638 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4639 /* Merged stages have 8 system SGPRs at the beginning. */
4640 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4641 declare_per_stage_desc_pointers(ctx, &fninfo,
4642 ctx->type == PIPE_SHADER_TESS_CTRL);
4643 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4644 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4645 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4646 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4647 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4648 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4649
4650 declare_global_desc_pointers(ctx, &fninfo);
4651 declare_per_stage_desc_pointers(ctx, &fninfo,
4652 ctx->type == PIPE_SHADER_VERTEX);
4653 declare_vs_specific_input_sgprs(ctx, &fninfo);
4654
4655 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4656 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4657 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4658 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4659 ac_array_in_const32_addr_space(ctx->v4i32));
4660
4661 /* VGPRs (first TCS, then VS) */
4662 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4663 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4664
4665 if (ctx->type == PIPE_SHADER_VERTEX) {
4666 declare_vs_input_vgprs(ctx, &fninfo,
4667 &num_prolog_vgprs);
4668
4669 /* LS return values are inputs to the TCS main shader part. */
4670 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4671 returns[num_returns++] = ctx->i32; /* SGPRs */
4672 for (i = 0; i < 2; i++)
4673 returns[num_returns++] = ctx->f32; /* VGPRs */
4674 } else {
4675 /* TCS return values are inputs to the TCS epilog.
4676 *
4677 * param_tcs_offchip_offset, param_tcs_factor_offset,
4678 * param_tcs_offchip_layout, and param_rw_buffers
4679 * should be passed to the epilog.
4680 */
4681 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4682 returns[num_returns++] = ctx->i32; /* SGPRs */
4683 for (i = 0; i < 11; i++)
4684 returns[num_returns++] = ctx->f32; /* VGPRs */
4685 }
4686 break;
4687
4688 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4689 /* Merged stages have 8 system SGPRs at the beginning. */
4690 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4691 declare_per_stage_desc_pointers(ctx, &fninfo,
4692 ctx->type == PIPE_SHADER_GEOMETRY);
4693 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4694 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4695 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4696 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4697 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4698 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4699
4700 declare_global_desc_pointers(ctx, &fninfo);
4701 declare_per_stage_desc_pointers(ctx, &fninfo,
4702 (ctx->type == PIPE_SHADER_VERTEX ||
4703 ctx->type == PIPE_SHADER_TESS_EVAL));
4704 if (ctx->type == PIPE_SHADER_VERTEX) {
4705 declare_vs_specific_input_sgprs(ctx, &fninfo);
4706 } else {
4707 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4708 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4709 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4710 /* Declare as many input SGPRs as the VS has. */
4711 }
4712
4713 if (ctx->type == PIPE_SHADER_VERTEX) {
4714 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4715 ac_array_in_const32_addr_space(ctx->v4i32));
4716 }
4717
4718 /* VGPRs (first GS, then VS/TES) */
4719 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4720 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4721 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4722 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4723 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4724
4725 if (ctx->type == PIPE_SHADER_VERTEX) {
4726 declare_vs_input_vgprs(ctx, &fninfo,
4727 &num_prolog_vgprs);
4728 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4729 declare_tes_input_vgprs(ctx, &fninfo);
4730 }
4731
4732 if (ctx->type == PIPE_SHADER_VERTEX ||
4733 ctx->type == PIPE_SHADER_TESS_EVAL) {
4734 unsigned num_user_sgprs;
4735
4736 if (ctx->type == PIPE_SHADER_VERTEX)
4737 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4738 else
4739 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4740
4741 /* ES return values are inputs to GS. */
4742 for (i = 0; i < 8 + num_user_sgprs; i++)
4743 returns[num_returns++] = ctx->i32; /* SGPRs */
4744 for (i = 0; i < 5; i++)
4745 returns[num_returns++] = ctx->f32; /* VGPRs */
4746 }
4747 break;
4748
4749 case PIPE_SHADER_TESS_EVAL:
4750 declare_global_desc_pointers(ctx, &fninfo);
4751 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4752 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4753 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4754 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4755
4756 if (shader->key.as_es) {
4757 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4758 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4759 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4760 } else {
4761 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4762 declare_streamout_params(ctx, &shader->selector->so,
4763 &fninfo);
4764 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4765 }
4766
4767 /* VGPRs */
4768 declare_tes_input_vgprs(ctx, &fninfo);
4769 break;
4770
4771 case PIPE_SHADER_GEOMETRY:
4772 declare_global_desc_pointers(ctx, &fninfo);
4773 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4774 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4776
4777 /* VGPRs */
4778 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4779 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4780 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4781 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4782 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4783 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4784 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4785 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4786 break;
4787
4788 case PIPE_SHADER_FRAGMENT:
4789 declare_global_desc_pointers(ctx, &fninfo);
4790 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4791 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4792 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4793 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4794
4795 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4796 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4797 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4798 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4799 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4800 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4801 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4802 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4803 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4804 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4805 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4806 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4807 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4808 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4809 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4810 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4811 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4812 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4813 shader->info.face_vgpr_index = 20;
4814 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4815 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4816 shader->info.ancillary_vgpr_index = 21;
4817 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4818 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4819 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4820
4821 /* Color inputs from the prolog. */
4822 if (shader->selector->info.colors_read) {
4823 unsigned num_color_elements =
4824 util_bitcount(shader->selector->info.colors_read);
4825
4826 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4827 for (i = 0; i < num_color_elements; i++)
4828 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4829
4830 num_prolog_vgprs += num_color_elements;
4831 }
4832
4833 /* Outputs for the epilog. */
4834 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4835 num_returns =
4836 num_return_sgprs +
4837 util_bitcount(shader->selector->info.colors_written) * 4 +
4838 shader->selector->info.writes_z +
4839 shader->selector->info.writes_stencil +
4840 shader->selector->info.writes_samplemask +
4841 1 /* SampleMaskIn */;
4842
4843 num_returns = MAX2(num_returns,
4844 num_return_sgprs +
4845 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4846
4847 for (i = 0; i < num_return_sgprs; i++)
4848 returns[i] = ctx->i32;
4849 for (; i < num_returns; i++)
4850 returns[i] = ctx->f32;
4851 break;
4852
4853 case PIPE_SHADER_COMPUTE:
4854 declare_global_desc_pointers(ctx, &fninfo);
4855 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4856 if (shader->selector->info.uses_grid_size)
4857 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4858 if (shader->selector->info.uses_block_size &&
4859 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4860 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4861
4862 unsigned cs_user_data_dwords =
4863 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4864 if (cs_user_data_dwords) {
4865 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4866 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4867 }
4868
4869 for (i = 0; i < 3; i++) {
4870 ctx->abi.workgroup_ids[i] = NULL;
4871 if (shader->selector->info.uses_block_id[i])
4872 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4873 }
4874
4875 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4876 break;
4877 default:
4878 assert(0 && "unimplemented shader");
4879 return;
4880 }
4881
4882 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4883 si_get_max_workgroup_size(shader));
4884
4885 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4886 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4887 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4888 "InitialPSInputAddr",
4889 S_0286D0_PERSP_SAMPLE_ENA(1) |
4890 S_0286D0_PERSP_CENTER_ENA(1) |
4891 S_0286D0_PERSP_CENTROID_ENA(1) |
4892 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4893 S_0286D0_LINEAR_CENTER_ENA(1) |
4894 S_0286D0_LINEAR_CENTROID_ENA(1) |
4895 S_0286D0_FRONT_FACE_ENA(1) |
4896 S_0286D0_ANCILLARY_ENA(1) |
4897 S_0286D0_POS_FIXED_PT_ENA(1));
4898 }
4899
4900 shader->info.num_input_sgprs = 0;
4901 shader->info.num_input_vgprs = 0;
4902
4903 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4904 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4905
4906 for (; i < fninfo.num_params; ++i)
4907 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4908
4909 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4910 shader->info.num_input_vgprs -= num_prolog_vgprs;
4911
4912 if (shader->key.as_ls ||
4913 ctx->type == PIPE_SHADER_TESS_CTRL ||
4914 /* GFX9 has the ESGS ring buffer in LDS. */
4915 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4916 ac_declare_lds_as_pointer(&ctx->ac);
4917 }
4918
4919 /**
4920 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4921 * for later use.
4922 */
4923 static void preload_ring_buffers(struct si_shader_context *ctx)
4924 {
4925 LLVMBuilderRef builder = ctx->ac.builder;
4926
4927 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4928 ctx->param_rw_buffers);
4929
4930 if (ctx->screen->info.chip_class <= GFX8 &&
4931 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4932 unsigned ring =
4933 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4934 : SI_ES_RING_ESGS;
4935 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4936
4937 ctx->esgs_ring =
4938 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4939 }
4940
4941 if (ctx->shader->is_gs_copy_shader) {
4942 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4943
4944 ctx->gsvs_ring[0] =
4945 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4946 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4947 const struct si_shader_selector *sel = ctx->shader->selector;
4948 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4949 LLVMValueRef base_ring;
4950
4951 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4952
4953 /* The conceptual layout of the GSVS ring is
4954 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4955 * but the real memory layout is swizzled across
4956 * threads:
4957 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4958 * t16v0c0 ..
4959 * Override the buffer descriptor accordingly.
4960 */
4961 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4962 uint64_t stream_offset = 0;
4963
4964 for (unsigned stream = 0; stream < 4; ++stream) {
4965 unsigned num_components;
4966 unsigned stride;
4967 unsigned num_records;
4968 LLVMValueRef ring, tmp;
4969
4970 num_components = sel->info.num_stream_output_components[stream];
4971 if (!num_components)
4972 continue;
4973
4974 stride = 4 * num_components * sel->gs_max_out_vertices;
4975
4976 /* Limit on the stride field for <= GFX7. */
4977 assert(stride < (1 << 14));
4978
4979 num_records = 64;
4980
4981 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4982 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4983 tmp = LLVMBuildAdd(builder, tmp,
4984 LLVMConstInt(ctx->i64,
4985 stream_offset, 0), "");
4986 stream_offset += stride * 64;
4987
4988 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4989 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4990 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4991 tmp = LLVMBuildOr(builder, tmp,
4992 LLVMConstInt(ctx->i32,
4993 S_008F04_STRIDE(stride) |
4994 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4995 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4996 ring = LLVMBuildInsertElement(builder, ring,
4997 LLVMConstInt(ctx->i32, num_records, 0),
4998 LLVMConstInt(ctx->i32, 2, 0), "");
4999 ring = LLVMBuildInsertElement(builder, ring,
5000 LLVMConstInt(ctx->i32,
5001 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5002 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5003 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5004 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5005 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5006 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5007 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5008 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5009 S_008F0C_ADD_TID_ENABLE(1),
5010 0),
5011 LLVMConstInt(ctx->i32, 3, 0), "");
5012
5013 ctx->gsvs_ring[stream] = ring;
5014 }
5015 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5016 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5017 }
5018 }
5019
5020 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5021 LLVMValueRef param_rw_buffers,
5022 unsigned param_pos_fixed_pt)
5023 {
5024 LLVMBuilderRef builder = ctx->ac.builder;
5025 LLVMValueRef slot, desc, offset, row, bit, address[2];
5026
5027 /* Use the fixed-point gl_FragCoord input.
5028 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5029 * per coordinate to get the repeating effect.
5030 */
5031 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5032 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5033
5034 /* Load the buffer descriptor. */
5035 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5036 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5037
5038 /* The stipple pattern is 32x32, each row has 32 bits. */
5039 offset = LLVMBuildMul(builder, address[1],
5040 LLVMConstInt(ctx->i32, 4, 0), "");
5041 row = buffer_load_const(ctx, desc, offset);
5042 row = ac_to_integer(&ctx->ac, row);
5043 bit = LLVMBuildLShr(builder, row, address[0], "");
5044 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5045 ac_build_kill_if_false(&ctx->ac, bit);
5046 }
5047
5048 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5049 struct si_shader_config *conf,
5050 unsigned symbol_offset)
5051 {
5052 unsigned i;
5053 const unsigned char *config =
5054 ac_shader_binary_config_start(binary, symbol_offset);
5055 bool really_needs_scratch = false;
5056
5057 /* LLVM adds SGPR spills to the scratch size.
5058 * Find out if we really need the scratch buffer.
5059 */
5060 for (i = 0; i < binary->reloc_count; i++) {
5061 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5062
5063 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5064 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5065 really_needs_scratch = true;
5066 break;
5067 }
5068 }
5069
5070 /* XXX: We may be able to emit some of these values directly rather than
5071 * extracting fields to be emitted later.
5072 */
5073
5074 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5075 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5076 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5077 switch (reg) {
5078 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5079 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5080 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5081 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5082 case R_00B848_COMPUTE_PGM_RSRC1:
5083 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5084 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5085 conf->float_mode = G_00B028_FLOAT_MODE(value);
5086 conf->rsrc1 = value;
5087 break;
5088 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5089 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5090 break;
5091 case R_00B84C_COMPUTE_PGM_RSRC2:
5092 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5093 conf->rsrc2 = value;
5094 break;
5095 case R_0286CC_SPI_PS_INPUT_ENA:
5096 conf->spi_ps_input_ena = value;
5097 break;
5098 case R_0286D0_SPI_PS_INPUT_ADDR:
5099 conf->spi_ps_input_addr = value;
5100 break;
5101 case R_0286E8_SPI_TMPRING_SIZE:
5102 case R_00B860_COMPUTE_TMPRING_SIZE:
5103 /* WAVESIZE is in units of 256 dwords. */
5104 if (really_needs_scratch)
5105 conf->scratch_bytes_per_wave =
5106 G_00B860_WAVESIZE(value) * 256 * 4;
5107 break;
5108 case 0x4: /* SPILLED_SGPRS */
5109 conf->spilled_sgprs = value;
5110 break;
5111 case 0x8: /* SPILLED_VGPRS */
5112 conf->spilled_vgprs = value;
5113 break;
5114 default:
5115 {
5116 static bool printed;
5117
5118 if (!printed) {
5119 fprintf(stderr, "Warning: LLVM emitted unknown "
5120 "config register: 0x%x\n", reg);
5121 printed = true;
5122 }
5123 }
5124 break;
5125 }
5126 }
5127
5128 if (!conf->spi_ps_input_addr)
5129 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5130 }
5131
5132 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5133 uint64_t scratch_va)
5134 {
5135 unsigned i;
5136 uint32_t scratch_rsrc_dword0 = scratch_va;
5137 uint32_t scratch_rsrc_dword1 =
5138 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5139
5140 /* Enable scratch coalescing. */
5141 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5142
5143 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5144 const struct ac_shader_reloc *reloc =
5145 &shader->binary.relocs[i];
5146 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5147 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5148 &scratch_rsrc_dword0, 4);
5149 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5150 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5151 &scratch_rsrc_dword1, 4);
5152 }
5153 }
5154 }
5155
5156 /* For the UMR disassembler. */
5157 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5158 #define DEBUGGER_NUM_MARKERS 5
5159
5160 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5161 {
5162 unsigned size = shader->binary.code_size;
5163
5164 if (shader->prolog)
5165 size += shader->prolog->binary.code_size;
5166 if (shader->previous_stage)
5167 size += shader->previous_stage->binary.code_size;
5168 if (shader->prolog2)
5169 size += shader->prolog2->binary.code_size;
5170 if (shader->epilog)
5171 size += shader->epilog->binary.code_size;
5172 return size + DEBUGGER_NUM_MARKERS * 4;
5173 }
5174
5175 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5176 {
5177 const struct ac_shader_binary *prolog =
5178 shader->prolog ? &shader->prolog->binary : NULL;
5179 const struct ac_shader_binary *previous_stage =
5180 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5181 const struct ac_shader_binary *prolog2 =
5182 shader->prolog2 ? &shader->prolog2->binary : NULL;
5183 const struct ac_shader_binary *epilog =
5184 shader->epilog ? &shader->epilog->binary : NULL;
5185 const struct ac_shader_binary *mainb = &shader->binary;
5186 unsigned bo_size = si_get_shader_binary_size(shader) +
5187 (!epilog ? mainb->rodata_size : 0);
5188 unsigned char *ptr;
5189
5190 assert(!prolog || !prolog->rodata_size);
5191 assert(!previous_stage || !previous_stage->rodata_size);
5192 assert(!prolog2 || !prolog2->rodata_size);
5193 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5194 !mainb->rodata_size);
5195 assert(!epilog || !epilog->rodata_size);
5196
5197 si_resource_reference(&shader->bo, NULL);
5198 shader->bo = si_aligned_buffer_create(&sscreen->b,
5199 sscreen->cpdma_prefetch_writes_memory ?
5200 0 : SI_RESOURCE_FLAG_READ_ONLY,
5201 PIPE_USAGE_IMMUTABLE,
5202 align(bo_size, SI_CPDMA_ALIGNMENT),
5203 256);
5204 if (!shader->bo)
5205 return -ENOMEM;
5206
5207 /* Upload. */
5208 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5209 PIPE_TRANSFER_READ_WRITE |
5210 PIPE_TRANSFER_UNSYNCHRONIZED |
5211 RADEON_TRANSFER_TEMPORARY);
5212
5213 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5214 * endian-independent. */
5215 if (prolog) {
5216 memcpy(ptr, prolog->code, prolog->code_size);
5217 ptr += prolog->code_size;
5218 }
5219 if (previous_stage) {
5220 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5221 ptr += previous_stage->code_size;
5222 }
5223 if (prolog2) {
5224 memcpy(ptr, prolog2->code, prolog2->code_size);
5225 ptr += prolog2->code_size;
5226 }
5227
5228 memcpy(ptr, mainb->code, mainb->code_size);
5229 ptr += mainb->code_size;
5230
5231 if (epilog) {
5232 memcpy(ptr, epilog->code, epilog->code_size);
5233 ptr += epilog->code_size;
5234 } else if (mainb->rodata_size > 0) {
5235 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5236 ptr += mainb->rodata_size;
5237 }
5238
5239 /* Add end-of-code markers for the UMR disassembler. */
5240 uint32_t *ptr32 = (uint32_t*)ptr;
5241 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5242 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5243
5244 sscreen->ws->buffer_unmap(shader->bo->buf);
5245 return 0;
5246 }
5247
5248 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5249 struct pipe_debug_callback *debug,
5250 const char *name, FILE *file)
5251 {
5252 char *line, *p;
5253 unsigned i, count;
5254
5255 if (binary->disasm_string) {
5256 fprintf(file, "Shader %s disassembly:\n", name);
5257 fprintf(file, "%s", binary->disasm_string);
5258
5259 if (debug && debug->debug_message) {
5260 /* Very long debug messages are cut off, so send the
5261 * disassembly one line at a time. This causes more
5262 * overhead, but on the plus side it simplifies
5263 * parsing of resulting logs.
5264 */
5265 pipe_debug_message(debug, SHADER_INFO,
5266 "Shader Disassembly Begin");
5267
5268 line = binary->disasm_string;
5269 while (*line) {
5270 p = util_strchrnul(line, '\n');
5271 count = p - line;
5272
5273 if (count) {
5274 pipe_debug_message(debug, SHADER_INFO,
5275 "%.*s", count, line);
5276 }
5277
5278 if (!*p)
5279 break;
5280 line = p + 1;
5281 }
5282
5283 pipe_debug_message(debug, SHADER_INFO,
5284 "Shader Disassembly End");
5285 }
5286 } else {
5287 fprintf(file, "Shader %s binary:\n", name);
5288 for (i = 0; i < binary->code_size; i += 4) {
5289 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5290 binary->code[i + 3], binary->code[i + 2],
5291 binary->code[i + 1], binary->code[i]);
5292 }
5293 }
5294 }
5295
5296 static void si_calculate_max_simd_waves(struct si_shader *shader)
5297 {
5298 struct si_screen *sscreen = shader->selector->screen;
5299 struct si_shader_config *conf = &shader->config;
5300 unsigned num_inputs = shader->selector->info.num_inputs;
5301 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5302 unsigned lds_per_wave = 0;
5303 unsigned max_simd_waves;
5304
5305 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5306
5307 /* Compute LDS usage for PS. */
5308 switch (shader->selector->type) {
5309 case PIPE_SHADER_FRAGMENT:
5310 /* The minimum usage per wave is (num_inputs * 48). The maximum
5311 * usage is (num_inputs * 48 * 16).
5312 * We can get anything in between and it varies between waves.
5313 *
5314 * The 48 bytes per input for a single primitive is equal to
5315 * 4 bytes/component * 4 components/input * 3 points.
5316 *
5317 * Other stages don't know the size at compile time or don't
5318 * allocate LDS per wave, but instead they do it per thread group.
5319 */
5320 lds_per_wave = conf->lds_size * lds_increment +
5321 align(num_inputs * 48, lds_increment);
5322 break;
5323 case PIPE_SHADER_COMPUTE:
5324 if (shader->selector) {
5325 unsigned max_workgroup_size =
5326 si_get_max_workgroup_size(shader);
5327 lds_per_wave = (conf->lds_size * lds_increment) /
5328 DIV_ROUND_UP(max_workgroup_size, 64);
5329 }
5330 break;
5331 }
5332
5333 /* Compute the per-SIMD wave counts. */
5334 if (conf->num_sgprs) {
5335 max_simd_waves =
5336 MIN2(max_simd_waves,
5337 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5338 }
5339
5340 if (conf->num_vgprs)
5341 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5342
5343 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5344 * 16KB makes some SIMDs unoccupied). */
5345 if (lds_per_wave)
5346 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5347
5348 conf->max_simd_waves = max_simd_waves;
5349 }
5350
5351 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5352 struct pipe_debug_callback *debug)
5353 {
5354 const struct si_shader_config *conf = &shader->config;
5355
5356 pipe_debug_message(debug, SHADER_INFO,
5357 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5358 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5359 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5360 conf->num_sgprs, conf->num_vgprs,
5361 si_get_shader_binary_size(shader),
5362 conf->lds_size, conf->scratch_bytes_per_wave,
5363 conf->max_simd_waves, conf->spilled_sgprs,
5364 conf->spilled_vgprs, conf->private_mem_vgprs);
5365 }
5366
5367 static void si_shader_dump_stats(struct si_screen *sscreen,
5368 const struct si_shader *shader,
5369 unsigned processor,
5370 FILE *file,
5371 bool check_debug_option)
5372 {
5373 const struct si_shader_config *conf = &shader->config;
5374
5375 if (!check_debug_option ||
5376 si_can_dump_shader(sscreen, processor)) {
5377 if (processor == PIPE_SHADER_FRAGMENT) {
5378 fprintf(file, "*** SHADER CONFIG ***\n"
5379 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5380 "SPI_PS_INPUT_ENA = 0x%04x\n",
5381 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5382 }
5383
5384 fprintf(file, "*** SHADER STATS ***\n"
5385 "SGPRS: %d\n"
5386 "VGPRS: %d\n"
5387 "Spilled SGPRs: %d\n"
5388 "Spilled VGPRs: %d\n"
5389 "Private memory VGPRs: %d\n"
5390 "Code Size: %d bytes\n"
5391 "LDS: %d blocks\n"
5392 "Scratch: %d bytes per wave\n"
5393 "Max Waves: %d\n"
5394 "********************\n\n\n",
5395 conf->num_sgprs, conf->num_vgprs,
5396 conf->spilled_sgprs, conf->spilled_vgprs,
5397 conf->private_mem_vgprs,
5398 si_get_shader_binary_size(shader),
5399 conf->lds_size, conf->scratch_bytes_per_wave,
5400 conf->max_simd_waves);
5401 }
5402 }
5403
5404 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5405 {
5406 switch (processor) {
5407 case PIPE_SHADER_VERTEX:
5408 if (shader->key.as_es)
5409 return "Vertex Shader as ES";
5410 else if (shader->key.as_ls)
5411 return "Vertex Shader as LS";
5412 else if (shader->key.opt.vs_as_prim_discard_cs)
5413 return "Vertex Shader as Primitive Discard CS";
5414 else
5415 return "Vertex Shader as VS";
5416 case PIPE_SHADER_TESS_CTRL:
5417 return "Tessellation Control Shader";
5418 case PIPE_SHADER_TESS_EVAL:
5419 if (shader->key.as_es)
5420 return "Tessellation Evaluation Shader as ES";
5421 else
5422 return "Tessellation Evaluation Shader as VS";
5423 case PIPE_SHADER_GEOMETRY:
5424 if (shader->is_gs_copy_shader)
5425 return "GS Copy Shader as VS";
5426 else
5427 return "Geometry Shader";
5428 case PIPE_SHADER_FRAGMENT:
5429 return "Pixel Shader";
5430 case PIPE_SHADER_COMPUTE:
5431 return "Compute Shader";
5432 default:
5433 return "Unknown Shader";
5434 }
5435 }
5436
5437 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5438 struct pipe_debug_callback *debug, unsigned processor,
5439 FILE *file, bool check_debug_option)
5440 {
5441 if (!check_debug_option ||
5442 si_can_dump_shader(sscreen, processor))
5443 si_dump_shader_key(processor, shader, file);
5444
5445 if (!check_debug_option && shader->binary.llvm_ir_string) {
5446 if (shader->previous_stage &&
5447 shader->previous_stage->binary.llvm_ir_string) {
5448 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5449 si_get_shader_name(shader, processor));
5450 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5451 }
5452
5453 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5454 si_get_shader_name(shader, processor));
5455 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5456 }
5457
5458 if (!check_debug_option ||
5459 (si_can_dump_shader(sscreen, processor) &&
5460 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5461 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5462
5463 if (shader->prolog)
5464 si_shader_dump_disassembly(&shader->prolog->binary,
5465 debug, "prolog", file);
5466 if (shader->previous_stage)
5467 si_shader_dump_disassembly(&shader->previous_stage->binary,
5468 debug, "previous stage", file);
5469 if (shader->prolog2)
5470 si_shader_dump_disassembly(&shader->prolog2->binary,
5471 debug, "prolog2", file);
5472
5473 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5474
5475 if (shader->epilog)
5476 si_shader_dump_disassembly(&shader->epilog->binary,
5477 debug, "epilog", file);
5478 fprintf(file, "\n");
5479 }
5480
5481 si_shader_dump_stats(sscreen, shader, processor, file,
5482 check_debug_option);
5483 }
5484
5485 static int si_compile_llvm(struct si_screen *sscreen,
5486 struct ac_shader_binary *binary,
5487 struct si_shader_config *conf,
5488 struct ac_llvm_compiler *compiler,
5489 LLVMModuleRef mod,
5490 struct pipe_debug_callback *debug,
5491 unsigned processor,
5492 const char *name,
5493 bool less_optimized)
5494 {
5495 int r = 0;
5496 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5497
5498 if (si_can_dump_shader(sscreen, processor)) {
5499 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5500
5501 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5502 fprintf(stderr, "%s LLVM IR:\n\n", name);
5503 ac_dump_module(mod);
5504 fprintf(stderr, "\n");
5505 }
5506 }
5507
5508 if (sscreen->record_llvm_ir) {
5509 char *ir = LLVMPrintModuleToString(mod);
5510 binary->llvm_ir_string = strdup(ir);
5511 LLVMDisposeMessage(ir);
5512 }
5513
5514 if (!si_replace_shader(count, binary)) {
5515 r = si_llvm_compile(mod, binary, compiler, debug,
5516 less_optimized);
5517 if (r)
5518 return r;
5519 }
5520
5521 si_shader_binary_read_config(binary, conf, 0);
5522
5523 /* Enable 64-bit and 16-bit denormals, because there is no performance
5524 * cost.
5525 *
5526 * If denormals are enabled, all floating-point output modifiers are
5527 * ignored.
5528 *
5529 * Don't enable denormals for 32-bit floats, because:
5530 * - Floating-point output modifiers would be ignored by the hw.
5531 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5532 * have to stop using those.
5533 * - GFX6 & GFX7 would be very slow.
5534 */
5535 conf->float_mode |= V_00B028_FP_64_DENORMS;
5536
5537 FREE(binary->config);
5538 FREE(binary->global_symbol_offsets);
5539 binary->config = NULL;
5540 binary->global_symbol_offsets = NULL;
5541
5542 /* Some shaders can't have rodata because their binaries can be
5543 * concatenated.
5544 */
5545 if (binary->rodata_size &&
5546 (processor == PIPE_SHADER_VERTEX ||
5547 processor == PIPE_SHADER_TESS_CTRL ||
5548 processor == PIPE_SHADER_TESS_EVAL ||
5549 processor == PIPE_SHADER_FRAGMENT)) {
5550 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5551 return -EINVAL;
5552 }
5553
5554 return r;
5555 }
5556
5557 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5558 {
5559 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5560 LLVMBuildRetVoid(ctx->ac.builder);
5561 else
5562 LLVMBuildRet(ctx->ac.builder, ret);
5563 }
5564
5565 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5566 struct si_shader *
5567 si_generate_gs_copy_shader(struct si_screen *sscreen,
5568 struct ac_llvm_compiler *compiler,
5569 struct si_shader_selector *gs_selector,
5570 struct pipe_debug_callback *debug)
5571 {
5572 struct si_shader_context ctx;
5573 struct si_shader *shader;
5574 LLVMBuilderRef builder;
5575 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5576 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5577 int i, r;
5578
5579
5580 shader = CALLOC_STRUCT(si_shader);
5581 if (!shader)
5582 return NULL;
5583
5584 /* We can leave the fence as permanently signaled because the GS copy
5585 * shader only becomes visible globally after it has been compiled. */
5586 util_queue_fence_init(&shader->ready);
5587
5588 shader->selector = gs_selector;
5589 shader->is_gs_copy_shader = true;
5590
5591 si_init_shader_ctx(&ctx, sscreen, compiler);
5592 ctx.shader = shader;
5593 ctx.type = PIPE_SHADER_VERTEX;
5594
5595 builder = ctx.ac.builder;
5596
5597 create_function(&ctx);
5598 preload_ring_buffers(&ctx);
5599
5600 LLVMValueRef voffset =
5601 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5602 LLVMConstInt(ctx.i32, 4, 0), "");
5603
5604 /* Fetch the vertex stream ID.*/
5605 LLVMValueRef stream_id;
5606
5607 if (gs_selector->so.num_outputs)
5608 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5609 else
5610 stream_id = ctx.i32_0;
5611
5612 /* Fill in output information. */
5613 for (i = 0; i < gsinfo->num_outputs; ++i) {
5614 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5615 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5616
5617 for (int chan = 0; chan < 4; chan++) {
5618 outputs[i].vertex_stream[chan] =
5619 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5620 }
5621 }
5622
5623 LLVMBasicBlockRef end_bb;
5624 LLVMValueRef switch_inst;
5625
5626 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5627 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5628
5629 for (int stream = 0; stream < 4; stream++) {
5630 LLVMBasicBlockRef bb;
5631 unsigned offset;
5632
5633 if (!gsinfo->num_stream_output_components[stream])
5634 continue;
5635
5636 if (stream > 0 && !gs_selector->so.num_outputs)
5637 continue;
5638
5639 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5640 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5641 LLVMPositionBuilderAtEnd(builder, bb);
5642
5643 /* Fetch vertex data from GSVS ring */
5644 offset = 0;
5645 for (i = 0; i < gsinfo->num_outputs; ++i) {
5646 for (unsigned chan = 0; chan < 4; chan++) {
5647 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5648 outputs[i].vertex_stream[chan] != stream) {
5649 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5650 continue;
5651 }
5652
5653 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5654 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5655 offset++;
5656
5657 outputs[i].values[chan] =
5658 ac_build_buffer_load(&ctx.ac,
5659 ctx.gsvs_ring[0], 1,
5660 ctx.i32_0, voffset,
5661 soffset, 0, 1, 1,
5662 true, false);
5663 }
5664 }
5665
5666 /* Streamout and exports. */
5667 if (gs_selector->so.num_outputs) {
5668 si_llvm_emit_streamout(&ctx, outputs,
5669 gsinfo->num_outputs,
5670 stream);
5671 }
5672
5673 if (stream == 0)
5674 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5675
5676 LLVMBuildBr(builder, end_bb);
5677 }
5678
5679 LLVMPositionBuilderAtEnd(builder, end_bb);
5680
5681 LLVMBuildRetVoid(ctx.ac.builder);
5682
5683 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5684 si_llvm_optimize_module(&ctx);
5685
5686 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5687 &ctx.shader->config, ctx.compiler,
5688 ctx.ac.module,
5689 debug, PIPE_SHADER_GEOMETRY,
5690 "GS Copy Shader", false);
5691 if (!r) {
5692 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5693 fprintf(stderr, "GS Copy Shader:\n");
5694 si_shader_dump(sscreen, ctx.shader, debug,
5695 PIPE_SHADER_GEOMETRY, stderr, true);
5696 r = si_shader_binary_upload(sscreen, ctx.shader);
5697 }
5698
5699 si_llvm_dispose(&ctx);
5700
5701 if (r != 0) {
5702 FREE(shader);
5703 shader = NULL;
5704 } else {
5705 si_fix_resource_usage(sscreen, shader);
5706 }
5707 return shader;
5708 }
5709
5710 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5711 const struct si_vs_prolog_bits *prolog,
5712 const char *prefix, FILE *f)
5713 {
5714 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5715 prefix, prolog->instance_divisor_is_one);
5716 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5717 prefix, prolog->instance_divisor_is_fetched);
5718 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5719 prefix, prolog->unpack_instance_id_from_vertex_id);
5720 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5721 prefix, prolog->ls_vgpr_fix);
5722
5723 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5724 fprintf(f, " mono.vs.fix_fetch = {");
5725 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5726 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5727 if (i)
5728 fprintf(f, ", ");
5729 if (!fix.bits)
5730 fprintf(f, "0");
5731 else
5732 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5733 fix.u.num_channels_m1, fix.u.format);
5734 }
5735 fprintf(f, "}\n");
5736 }
5737
5738 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5739 FILE *f)
5740 {
5741 const struct si_shader_key *key = &shader->key;
5742
5743 fprintf(f, "SHADER KEY\n");
5744
5745 switch (processor) {
5746 case PIPE_SHADER_VERTEX:
5747 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5748 "part.vs.prolog", f);
5749 fprintf(f, " as_es = %u\n", key->as_es);
5750 fprintf(f, " as_ls = %u\n", key->as_ls);
5751 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5752 key->mono.u.vs_export_prim_id);
5753 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5754 key->opt.vs_as_prim_discard_cs);
5755 fprintf(f, " opt.cs_prim_type = %s\n",
5756 tgsi_primitive_names[key->opt.cs_prim_type]);
5757 fprintf(f, " opt.cs_indexed = %u\n",
5758 key->opt.cs_indexed);
5759 fprintf(f, " opt.cs_instancing = %u\n",
5760 key->opt.cs_instancing);
5761 fprintf(f, " opt.cs_primitive_restart = %u\n",
5762 key->opt.cs_primitive_restart);
5763 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5764 key->opt.cs_provoking_vertex_first);
5765 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5766 key->opt.cs_need_correct_orientation);
5767 fprintf(f, " opt.cs_cull_front = %u\n",
5768 key->opt.cs_cull_front);
5769 fprintf(f, " opt.cs_cull_back = %u\n",
5770 key->opt.cs_cull_back);
5771 fprintf(f, " opt.cs_cull_z = %u\n",
5772 key->opt.cs_cull_z);
5773 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5774 key->opt.cs_halfz_clip_space);
5775 break;
5776
5777 case PIPE_SHADER_TESS_CTRL:
5778 if (shader->selector->screen->info.chip_class >= GFX9) {
5779 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5780 "part.tcs.ls_prolog", f);
5781 }
5782 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5783 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5784 break;
5785
5786 case PIPE_SHADER_TESS_EVAL:
5787 fprintf(f, " as_es = %u\n", key->as_es);
5788 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5789 key->mono.u.vs_export_prim_id);
5790 break;
5791
5792 case PIPE_SHADER_GEOMETRY:
5793 if (shader->is_gs_copy_shader)
5794 break;
5795
5796 if (shader->selector->screen->info.chip_class >= GFX9 &&
5797 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5798 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5799 "part.gs.vs_prolog", f);
5800 }
5801 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5802 break;
5803
5804 case PIPE_SHADER_COMPUTE:
5805 break;
5806
5807 case PIPE_SHADER_FRAGMENT:
5808 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5809 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5810 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5811 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5812 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5813 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5814 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5815 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5816 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5817 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5818 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5819 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5820 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5821 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5822 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5823 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5824 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5825 break;
5826
5827 default:
5828 assert(0);
5829 }
5830
5831 if ((processor == PIPE_SHADER_GEOMETRY ||
5832 processor == PIPE_SHADER_TESS_EVAL ||
5833 processor == PIPE_SHADER_VERTEX) &&
5834 !key->as_es && !key->as_ls) {
5835 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5836 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5837 }
5838 }
5839
5840 static void si_init_shader_ctx(struct si_shader_context *ctx,
5841 struct si_screen *sscreen,
5842 struct ac_llvm_compiler *compiler)
5843 {
5844 struct lp_build_tgsi_context *bld_base;
5845
5846 si_llvm_context_init(ctx, sscreen, compiler);
5847
5848 bld_base = &ctx->bld_base;
5849 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5850
5851 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5852 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5853 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5854
5855 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5856
5857 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5858
5859 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5860 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5861 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5862 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5863
5864 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5865 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5866 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5867 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5868 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5869 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5870 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5871 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5872
5873 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5874 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5875 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5876 }
5877
5878 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5879 {
5880 struct si_shader *shader = ctx->shader;
5881 struct tgsi_shader_info *info = &shader->selector->info;
5882
5883 if ((ctx->type != PIPE_SHADER_VERTEX &&
5884 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5885 shader->key.as_ls ||
5886 shader->key.as_es)
5887 return;
5888
5889 ac_optimize_vs_outputs(&ctx->ac,
5890 ctx->main_fn,
5891 shader->info.vs_output_param_offset,
5892 info->num_outputs,
5893 &shader->info.nr_param_exports);
5894 }
5895
5896 static void si_init_exec_from_input(struct si_shader_context *ctx,
5897 unsigned param, unsigned bitoffset)
5898 {
5899 LLVMValueRef args[] = {
5900 LLVMGetParam(ctx->main_fn, param),
5901 LLVMConstInt(ctx->i32, bitoffset, 0),
5902 };
5903 ac_build_intrinsic(&ctx->ac,
5904 "llvm.amdgcn.init.exec.from.input",
5905 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
5906 }
5907
5908 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5909 const struct si_vs_prolog_bits *key)
5910 {
5911 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5912 * VS prolog. */
5913 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5914 }
5915
5916 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
5917 {
5918 struct si_shader *shader = ctx->shader;
5919 struct si_shader_selector *sel = shader->selector;
5920 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5921
5922 // TODO clean all this up!
5923 switch (ctx->type) {
5924 case PIPE_SHADER_VERTEX:
5925 ctx->load_input = declare_input_vs;
5926 if (shader->key.as_ls)
5927 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5928 else if (shader->key.as_es)
5929 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5930 else if (shader->key.opt.vs_as_prim_discard_cs)
5931 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
5932 else
5933 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5934 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5935 ctx->abi.load_base_vertex = get_base_vertex;
5936 break;
5937 case PIPE_SHADER_TESS_CTRL:
5938 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5939 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
5940 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5941 bld_base->emit_store = store_output_tcs;
5942 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
5943 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
5944 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5945 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5946 break;
5947 case PIPE_SHADER_TESS_EVAL:
5948 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5949 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
5950 ctx->abi.load_tess_coord = si_load_tess_coord;
5951 ctx->abi.load_tess_level = si_load_tess_level;
5952 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
5953 if (shader->key.as_es)
5954 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5955 else
5956 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5957 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5958 break;
5959 case PIPE_SHADER_GEOMETRY:
5960 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5961 ctx->abi.load_inputs = si_nir_load_input_gs;
5962 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5963 ctx->abi.emit_primitive = si_llvm_emit_primitive;
5964 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5965 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5966 break;
5967 case PIPE_SHADER_FRAGMENT:
5968 ctx->load_input = declare_input_fs;
5969 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5970 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5971 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
5972 ctx->abi.load_sample_position = load_sample_position;
5973 ctx->abi.load_sample_mask_in = load_sample_mask_in;
5974 ctx->abi.emit_kill = si_llvm_emit_kill;
5975 break;
5976 case PIPE_SHADER_COMPUTE:
5977 ctx->abi.load_local_group_size = get_block_size;
5978 break;
5979 default:
5980 assert(!"Unsupported shader type");
5981 return false;
5982 }
5983
5984 ctx->abi.load_ubo = load_ubo;
5985 ctx->abi.load_ssbo = load_ssbo;
5986
5987 create_function(ctx);
5988 preload_ring_buffers(ctx);
5989
5990 /* For GFX9 merged shaders:
5991 * - Set EXEC for the first shader. If the prolog is present, set
5992 * EXEC there instead.
5993 * - Add a barrier before the second shader.
5994 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5995 * an if-statement. This is required for correctness in geometry
5996 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5997 * GS_CUT messages.
5998 *
5999 * For monolithic merged shaders, the first shader is wrapped in an
6000 * if-block together with its prolog in si_build_wrapper_function.
6001 */
6002 if (ctx->screen->info.chip_class >= GFX9) {
6003 if (!shader->is_monolithic &&
6004 sel->info.num_instructions > 1 && /* not empty shader */
6005 (shader->key.as_es || shader->key.as_ls) &&
6006 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6007 (ctx->type == PIPE_SHADER_VERTEX &&
6008 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6009 si_init_exec_from_input(ctx,
6010 ctx->param_merged_wave_info, 0);
6011 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6012 ctx->type == PIPE_SHADER_GEOMETRY) {
6013 if (!shader->is_monolithic)
6014 ac_init_exec_full_mask(&ctx->ac);
6015
6016 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6017 LLVMValueRef ena =
6018 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6019 ac_get_thread_id(&ctx->ac), num_threads, "");
6020 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6021
6022 /* The barrier must execute for all shaders in a
6023 * threadgroup.
6024 *
6025 * Execute the barrier inside the conditional block,
6026 * so that empty waves can jump directly to s_endpgm,
6027 * which will also signal the barrier.
6028 *
6029 * If the shader is TCS and the TCS epilog is present
6030 * and contains a barrier, it will wait there and then
6031 * reach s_endpgm.
6032 */
6033 si_llvm_emit_barrier(NULL, bld_base, NULL);
6034 }
6035 }
6036
6037 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6038 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6039 for (unsigned i = 0; i < 6; i++) {
6040 ctx->invoc0_tess_factors[i] =
6041 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6042 }
6043 }
6044
6045 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6046 int i;
6047 for (i = 0; i < 4; i++) {
6048 ctx->gs_next_vertex[i] =
6049 ac_build_alloca(&ctx->ac, ctx->i32, "");
6050 }
6051 }
6052
6053 if (sel->force_correct_derivs_after_kill) {
6054 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6055 /* true = don't kill. */
6056 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6057 ctx->postponed_kill);
6058 }
6059
6060 if (sel->tokens) {
6061 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6062 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6063 return false;
6064 }
6065 } else {
6066 if (!si_nir_build_llvm(ctx, sel->nir)) {
6067 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6068 return false;
6069 }
6070 }
6071
6072 si_llvm_build_ret(ctx, ctx->return_value);
6073 return true;
6074 }
6075
6076 /**
6077 * Compute the VS prolog key, which contains all the information needed to
6078 * build the VS prolog function, and set shader->info bits where needed.
6079 *
6080 * \param info Shader info of the vertex shader.
6081 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6082 * \param prolog_key Key of the VS prolog
6083 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6084 * \param key Output shader part key.
6085 */
6086 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6087 unsigned num_input_sgprs,
6088 const struct si_vs_prolog_bits *prolog_key,
6089 struct si_shader *shader_out,
6090 union si_shader_part_key *key)
6091 {
6092 memset(key, 0, sizeof(*key));
6093 key->vs_prolog.states = *prolog_key;
6094 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6095 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6096 key->vs_prolog.as_ls = shader_out->key.as_ls;
6097 key->vs_prolog.as_es = shader_out->key.as_es;
6098
6099 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6100 key->vs_prolog.as_ls = 1;
6101 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6102 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6103 key->vs_prolog.as_es = 1;
6104 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6105 }
6106
6107 /* Enable loading the InstanceID VGPR. */
6108 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6109
6110 if ((key->vs_prolog.states.instance_divisor_is_one |
6111 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6112 shader_out->info.uses_instanceid = true;
6113 }
6114
6115 /**
6116 * Compute the PS prolog key, which contains all the information needed to
6117 * build the PS prolog function, and set related bits in shader->config.
6118 */
6119 static void si_get_ps_prolog_key(struct si_shader *shader,
6120 union si_shader_part_key *key,
6121 bool separate_prolog)
6122 {
6123 struct tgsi_shader_info *info = &shader->selector->info;
6124
6125 memset(key, 0, sizeof(*key));
6126 key->ps_prolog.states = shader->key.part.ps.prolog;
6127 key->ps_prolog.colors_read = info->colors_read;
6128 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6129 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6130 key->ps_prolog.wqm = info->uses_derivatives &&
6131 (key->ps_prolog.colors_read ||
6132 key->ps_prolog.states.force_persp_sample_interp ||
6133 key->ps_prolog.states.force_linear_sample_interp ||
6134 key->ps_prolog.states.force_persp_center_interp ||
6135 key->ps_prolog.states.force_linear_center_interp ||
6136 key->ps_prolog.states.bc_optimize_for_persp ||
6137 key->ps_prolog.states.bc_optimize_for_linear);
6138 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6139
6140 if (info->colors_read) {
6141 unsigned *color = shader->selector->color_attr_index;
6142
6143 if (shader->key.part.ps.prolog.color_two_side) {
6144 /* BCOLORs are stored after the last input. */
6145 key->ps_prolog.num_interp_inputs = info->num_inputs;
6146 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6147 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6148 }
6149
6150 for (unsigned i = 0; i < 2; i++) {
6151 unsigned interp = info->input_interpolate[color[i]];
6152 unsigned location = info->input_interpolate_loc[color[i]];
6153
6154 if (!(info->colors_read & (0xf << i*4)))
6155 continue;
6156
6157 key->ps_prolog.color_attr_index[i] = color[i];
6158
6159 if (shader->key.part.ps.prolog.flatshade_colors &&
6160 interp == TGSI_INTERPOLATE_COLOR)
6161 interp = TGSI_INTERPOLATE_CONSTANT;
6162
6163 switch (interp) {
6164 case TGSI_INTERPOLATE_CONSTANT:
6165 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6166 break;
6167 case TGSI_INTERPOLATE_PERSPECTIVE:
6168 case TGSI_INTERPOLATE_COLOR:
6169 /* Force the interpolation location for colors here. */
6170 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6171 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6172 if (shader->key.part.ps.prolog.force_persp_center_interp)
6173 location = TGSI_INTERPOLATE_LOC_CENTER;
6174
6175 switch (location) {
6176 case TGSI_INTERPOLATE_LOC_SAMPLE:
6177 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6178 shader->config.spi_ps_input_ena |=
6179 S_0286CC_PERSP_SAMPLE_ENA(1);
6180 break;
6181 case TGSI_INTERPOLATE_LOC_CENTER:
6182 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6183 shader->config.spi_ps_input_ena |=
6184 S_0286CC_PERSP_CENTER_ENA(1);
6185 break;
6186 case TGSI_INTERPOLATE_LOC_CENTROID:
6187 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6188 shader->config.spi_ps_input_ena |=
6189 S_0286CC_PERSP_CENTROID_ENA(1);
6190 break;
6191 default:
6192 assert(0);
6193 }
6194 break;
6195 case TGSI_INTERPOLATE_LINEAR:
6196 /* Force the interpolation location for colors here. */
6197 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6198 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6199 if (shader->key.part.ps.prolog.force_linear_center_interp)
6200 location = TGSI_INTERPOLATE_LOC_CENTER;
6201
6202 /* The VGPR assignment for non-monolithic shaders
6203 * works because InitialPSInputAddr is set on the
6204 * main shader and PERSP_PULL_MODEL is never used.
6205 */
6206 switch (location) {
6207 case TGSI_INTERPOLATE_LOC_SAMPLE:
6208 key->ps_prolog.color_interp_vgpr_index[i] =
6209 separate_prolog ? 6 : 9;
6210 shader->config.spi_ps_input_ena |=
6211 S_0286CC_LINEAR_SAMPLE_ENA(1);
6212 break;
6213 case TGSI_INTERPOLATE_LOC_CENTER:
6214 key->ps_prolog.color_interp_vgpr_index[i] =
6215 separate_prolog ? 8 : 11;
6216 shader->config.spi_ps_input_ena |=
6217 S_0286CC_LINEAR_CENTER_ENA(1);
6218 break;
6219 case TGSI_INTERPOLATE_LOC_CENTROID:
6220 key->ps_prolog.color_interp_vgpr_index[i] =
6221 separate_prolog ? 10 : 13;
6222 shader->config.spi_ps_input_ena |=
6223 S_0286CC_LINEAR_CENTROID_ENA(1);
6224 break;
6225 default:
6226 assert(0);
6227 }
6228 break;
6229 default:
6230 assert(0);
6231 }
6232 }
6233 }
6234 }
6235
6236 /**
6237 * Check whether a PS prolog is required based on the key.
6238 */
6239 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6240 {
6241 return key->ps_prolog.colors_read ||
6242 key->ps_prolog.states.force_persp_sample_interp ||
6243 key->ps_prolog.states.force_linear_sample_interp ||
6244 key->ps_prolog.states.force_persp_center_interp ||
6245 key->ps_prolog.states.force_linear_center_interp ||
6246 key->ps_prolog.states.bc_optimize_for_persp ||
6247 key->ps_prolog.states.bc_optimize_for_linear ||
6248 key->ps_prolog.states.poly_stipple ||
6249 key->ps_prolog.states.samplemask_log_ps_iter;
6250 }
6251
6252 /**
6253 * Compute the PS epilog key, which contains all the information needed to
6254 * build the PS epilog function.
6255 */
6256 static void si_get_ps_epilog_key(struct si_shader *shader,
6257 union si_shader_part_key *key)
6258 {
6259 struct tgsi_shader_info *info = &shader->selector->info;
6260 memset(key, 0, sizeof(*key));
6261 key->ps_epilog.colors_written = info->colors_written;
6262 key->ps_epilog.writes_z = info->writes_z;
6263 key->ps_epilog.writes_stencil = info->writes_stencil;
6264 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6265 key->ps_epilog.states = shader->key.part.ps.epilog;
6266 }
6267
6268 /**
6269 * Build the GS prolog function. Rotate the input vertices for triangle strips
6270 * with adjacency.
6271 */
6272 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6273 union si_shader_part_key *key)
6274 {
6275 unsigned num_sgprs, num_vgprs;
6276 struct si_function_info fninfo;
6277 LLVMBuilderRef builder = ctx->ac.builder;
6278 LLVMTypeRef returns[48];
6279 LLVMValueRef func, ret;
6280
6281 si_init_function_info(&fninfo);
6282
6283 if (ctx->screen->info.chip_class >= GFX9) {
6284 if (key->gs_prolog.states.gfx9_prev_is_vs)
6285 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6286 else
6287 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6288 num_vgprs = 5; /* ES inputs are not needed by GS */
6289 } else {
6290 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6291 num_vgprs = 8;
6292 }
6293
6294 for (unsigned i = 0; i < num_sgprs; ++i) {
6295 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6296 returns[i] = ctx->i32;
6297 }
6298
6299 for (unsigned i = 0; i < num_vgprs; ++i) {
6300 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6301 returns[num_sgprs + i] = ctx->f32;
6302 }
6303
6304 /* Create the function. */
6305 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6306 &fninfo, 0);
6307 func = ctx->main_fn;
6308
6309 /* Set the full EXEC mask for the prolog, because we are only fiddling
6310 * with registers here. The main shader part will set the correct EXEC
6311 * mask.
6312 */
6313 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6314 ac_init_exec_full_mask(&ctx->ac);
6315
6316 /* Copy inputs to outputs. This should be no-op, as the registers match,
6317 * but it will prevent the compiler from overwriting them unintentionally.
6318 */
6319 ret = ctx->return_value;
6320 for (unsigned i = 0; i < num_sgprs; i++) {
6321 LLVMValueRef p = LLVMGetParam(func, i);
6322 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6323 }
6324 for (unsigned i = 0; i < num_vgprs; i++) {
6325 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6326 p = ac_to_float(&ctx->ac, p);
6327 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6328 }
6329
6330 if (key->gs_prolog.states.tri_strip_adj_fix) {
6331 /* Remap the input vertices for every other primitive. */
6332 const unsigned gfx6_vtx_params[6] = {
6333 num_sgprs,
6334 num_sgprs + 1,
6335 num_sgprs + 3,
6336 num_sgprs + 4,
6337 num_sgprs + 5,
6338 num_sgprs + 6
6339 };
6340 const unsigned gfx9_vtx_params[3] = {
6341 num_sgprs,
6342 num_sgprs + 1,
6343 num_sgprs + 4,
6344 };
6345 LLVMValueRef vtx_in[6], vtx_out[6];
6346 LLVMValueRef prim_id, rotate;
6347
6348 if (ctx->screen->info.chip_class >= GFX9) {
6349 for (unsigned i = 0; i < 3; i++) {
6350 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6351 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6352 }
6353 } else {
6354 for (unsigned i = 0; i < 6; i++)
6355 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6356 }
6357
6358 prim_id = LLVMGetParam(func, num_sgprs + 2);
6359 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6360
6361 for (unsigned i = 0; i < 6; ++i) {
6362 LLVMValueRef base, rotated;
6363 base = vtx_in[i];
6364 rotated = vtx_in[(i + 4) % 6];
6365 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6366 }
6367
6368 if (ctx->screen->info.chip_class >= GFX9) {
6369 for (unsigned i = 0; i < 3; i++) {
6370 LLVMValueRef hi, out;
6371
6372 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6373 LLVMConstInt(ctx->i32, 16, 0), "");
6374 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6375 out = ac_to_float(&ctx->ac, out);
6376 ret = LLVMBuildInsertValue(builder, ret, out,
6377 gfx9_vtx_params[i], "");
6378 }
6379 } else {
6380 for (unsigned i = 0; i < 6; i++) {
6381 LLVMValueRef out;
6382
6383 out = ac_to_float(&ctx->ac, vtx_out[i]);
6384 ret = LLVMBuildInsertValue(builder, ret, out,
6385 gfx6_vtx_params[i], "");
6386 }
6387 }
6388 }
6389
6390 LLVMBuildRet(builder, ret);
6391 }
6392
6393 /**
6394 * Given a list of shader part functions, build a wrapper function that
6395 * runs them in sequence to form a monolithic shader.
6396 */
6397 static void si_build_wrapper_function(struct si_shader_context *ctx,
6398 LLVMValueRef *parts,
6399 unsigned num_parts,
6400 unsigned main_part,
6401 unsigned next_shader_first_part)
6402 {
6403 LLVMBuilderRef builder = ctx->ac.builder;
6404 /* PS epilog has one arg per color component; gfx9 merged shader
6405 * prologs need to forward 32 user SGPRs.
6406 */
6407 struct si_function_info fninfo;
6408 LLVMValueRef initial[64], out[64];
6409 LLVMTypeRef function_type;
6410 unsigned num_first_params;
6411 unsigned num_out, initial_num_out;
6412 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6413 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6414 unsigned num_sgprs, num_vgprs;
6415 unsigned gprs;
6416 struct lp_build_if_state if_state;
6417
6418 si_init_function_info(&fninfo);
6419
6420 for (unsigned i = 0; i < num_parts; ++i) {
6421 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6422 AC_FUNC_ATTR_ALWAYSINLINE);
6423 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6424 }
6425
6426 /* The parameters of the wrapper function correspond to those of the
6427 * first part in terms of SGPRs and VGPRs, but we use the types of the
6428 * main part to get the right types. This is relevant for the
6429 * dereferenceable attribute on descriptor table pointers.
6430 */
6431 num_sgprs = 0;
6432 num_vgprs = 0;
6433
6434 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6435 num_first_params = LLVMCountParamTypes(function_type);
6436
6437 for (unsigned i = 0; i < num_first_params; ++i) {
6438 LLVMValueRef param = LLVMGetParam(parts[0], i);
6439
6440 if (ac_is_sgpr_param(param)) {
6441 assert(num_vgprs == 0);
6442 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6443 } else {
6444 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6445 }
6446 }
6447
6448 gprs = 0;
6449 while (gprs < num_sgprs + num_vgprs) {
6450 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6451 LLVMTypeRef type = LLVMTypeOf(param);
6452 unsigned size = ac_get_type_size(type) / 4;
6453
6454 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6455
6456 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6457 assert(gprs + size <= num_sgprs + num_vgprs &&
6458 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6459
6460 gprs += size;
6461 }
6462
6463 /* Prepare the return type. */
6464 unsigned num_returns = 0;
6465 LLVMTypeRef returns[32], last_func_type, return_type;
6466
6467 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6468 return_type = LLVMGetReturnType(last_func_type);
6469
6470 switch (LLVMGetTypeKind(return_type)) {
6471 case LLVMStructTypeKind:
6472 num_returns = LLVMCountStructElementTypes(return_type);
6473 assert(num_returns <= ARRAY_SIZE(returns));
6474 LLVMGetStructElementTypes(return_type, returns);
6475 break;
6476 case LLVMVoidTypeKind:
6477 break;
6478 default:
6479 unreachable("unexpected type");
6480 }
6481
6482 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6483 si_get_max_workgroup_size(ctx->shader));
6484
6485 if (is_merged_shader(ctx))
6486 ac_init_exec_full_mask(&ctx->ac);
6487
6488 /* Record the arguments of the function as if they were an output of
6489 * a previous part.
6490 */
6491 num_out = 0;
6492 num_out_sgpr = 0;
6493
6494 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6495 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6496 LLVMTypeRef param_type = LLVMTypeOf(param);
6497 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6498 unsigned size = ac_get_type_size(param_type) / 4;
6499
6500 if (size == 1) {
6501 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6502 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6503 param_type = ctx->i32;
6504 }
6505
6506 if (param_type != out_type)
6507 param = LLVMBuildBitCast(builder, param, out_type, "");
6508 out[num_out++] = param;
6509 } else {
6510 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6511
6512 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6513 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6514 param_type = ctx->i64;
6515 }
6516
6517 if (param_type != vector_type)
6518 param = LLVMBuildBitCast(builder, param, vector_type, "");
6519
6520 for (unsigned j = 0; j < size; ++j)
6521 out[num_out++] = LLVMBuildExtractElement(
6522 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6523 }
6524
6525 if (i < fninfo.num_sgpr_params)
6526 num_out_sgpr = num_out;
6527 }
6528
6529 memcpy(initial, out, sizeof(out));
6530 initial_num_out = num_out;
6531 initial_num_out_sgpr = num_out_sgpr;
6532
6533 /* Now chain the parts. */
6534 LLVMValueRef ret;
6535 for (unsigned part = 0; part < num_parts; ++part) {
6536 LLVMValueRef in[48];
6537 LLVMTypeRef ret_type;
6538 unsigned out_idx = 0;
6539 unsigned num_params = LLVMCountParams(parts[part]);
6540
6541 /* Merged shaders are executed conditionally depending
6542 * on the number of enabled threads passed in the input SGPRs. */
6543 if (is_merged_shader(ctx) && part == 0) {
6544 LLVMValueRef ena, count = initial[3];
6545
6546 count = LLVMBuildAnd(builder, count,
6547 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6548 ena = LLVMBuildICmp(builder, LLVMIntULT,
6549 ac_get_thread_id(&ctx->ac), count, "");
6550 lp_build_if(&if_state, &ctx->gallivm, ena);
6551 }
6552
6553 /* Derive arguments for the next part from outputs of the
6554 * previous one.
6555 */
6556 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6557 LLVMValueRef param;
6558 LLVMTypeRef param_type;
6559 bool is_sgpr;
6560 unsigned param_size;
6561 LLVMValueRef arg = NULL;
6562
6563 param = LLVMGetParam(parts[part], param_idx);
6564 param_type = LLVMTypeOf(param);
6565 param_size = ac_get_type_size(param_type) / 4;
6566 is_sgpr = ac_is_sgpr_param(param);
6567
6568 if (is_sgpr) {
6569 ac_add_function_attr(ctx->ac.context, parts[part],
6570 param_idx + 1, AC_FUNC_ATTR_INREG);
6571 } else if (out_idx < num_out_sgpr) {
6572 /* Skip returned SGPRs the current part doesn't
6573 * declare on the input. */
6574 out_idx = num_out_sgpr;
6575 }
6576
6577 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6578
6579 if (param_size == 1)
6580 arg = out[out_idx];
6581 else
6582 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6583
6584 if (LLVMTypeOf(arg) != param_type) {
6585 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6586 if (LLVMGetPointerAddressSpace(param_type) ==
6587 AC_ADDR_SPACE_CONST_32BIT) {
6588 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6589 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6590 } else {
6591 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6592 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6593 }
6594 } else {
6595 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6596 }
6597 }
6598
6599 in[param_idx] = arg;
6600 out_idx += param_size;
6601 }
6602
6603 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6604
6605 if (is_merged_shader(ctx) &&
6606 part + 1 == next_shader_first_part) {
6607 lp_build_endif(&if_state);
6608
6609 /* The second half of the merged shader should use
6610 * the inputs from the toplevel (wrapper) function,
6611 * not the return value from the last call.
6612 *
6613 * That's because the last call was executed condi-
6614 * tionally, so we can't consume it in the main
6615 * block.
6616 */
6617 memcpy(out, initial, sizeof(initial));
6618 num_out = initial_num_out;
6619 num_out_sgpr = initial_num_out_sgpr;
6620 continue;
6621 }
6622
6623 /* Extract the returned GPRs. */
6624 ret_type = LLVMTypeOf(ret);
6625 num_out = 0;
6626 num_out_sgpr = 0;
6627
6628 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6629 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6630
6631 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6632
6633 for (unsigned i = 0; i < ret_size; ++i) {
6634 LLVMValueRef val =
6635 LLVMBuildExtractValue(builder, ret, i, "");
6636
6637 assert(num_out < ARRAY_SIZE(out));
6638 out[num_out++] = val;
6639
6640 if (LLVMTypeOf(val) == ctx->i32) {
6641 assert(num_out_sgpr + 1 == num_out);
6642 num_out_sgpr = num_out;
6643 }
6644 }
6645 }
6646 }
6647
6648 /* Return the value from the last part. */
6649 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6650 LLVMBuildRetVoid(builder);
6651 else
6652 LLVMBuildRet(builder, ret);
6653 }
6654
6655 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6656 struct si_shader_selector *sel)
6657 {
6658 if (!compiler->low_opt_passes)
6659 return false;
6660
6661 /* Assume a slow CPU. */
6662 assert(!sel->screen->info.has_dedicated_vram &&
6663 sel->screen->info.chip_class <= GFX8);
6664
6665 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6666 * buffer stores. */
6667 return sel->type == PIPE_SHADER_COMPUTE &&
6668 sel->info.num_memory_instructions > 1000;
6669 }
6670
6671 int si_compile_tgsi_shader(struct si_screen *sscreen,
6672 struct ac_llvm_compiler *compiler,
6673 struct si_shader *shader,
6674 struct pipe_debug_callback *debug)
6675 {
6676 struct si_shader_selector *sel = shader->selector;
6677 struct si_shader_context ctx;
6678 int r = -1;
6679
6680 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6681 * conversion fails. */
6682 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6683 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6684 if (sel->tokens)
6685 tgsi_dump(sel->tokens, 0);
6686 else
6687 nir_print_shader(sel->nir, stderr);
6688 si_dump_streamout(&sel->so);
6689 }
6690
6691 si_init_shader_ctx(&ctx, sscreen, compiler);
6692 si_llvm_context_set_tgsi(&ctx, shader);
6693
6694 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6695 sizeof(shader->info.vs_output_param_offset));
6696
6697 shader->info.uses_instanceid = sel->info.uses_instanceid;
6698
6699 if (!si_compile_tgsi_main(&ctx)) {
6700 si_llvm_dispose(&ctx);
6701 return -1;
6702 }
6703
6704 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6705 LLVMValueRef parts[2];
6706 bool need_prolog = sel->vs_needs_prolog;
6707
6708 parts[1] = ctx.main_fn;
6709
6710 if (need_prolog) {
6711 union si_shader_part_key prolog_key;
6712 si_get_vs_prolog_key(&sel->info,
6713 shader->info.num_input_sgprs,
6714 &shader->key.part.vs.prolog,
6715 shader, &prolog_key);
6716 si_build_vs_prolog_function(&ctx, &prolog_key);
6717 parts[0] = ctx.main_fn;
6718 }
6719
6720 si_build_wrapper_function(&ctx, parts + !need_prolog,
6721 1 + need_prolog, need_prolog, 0);
6722
6723 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6724 si_build_prim_discard_compute_shader(&ctx);
6725 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6726 if (sscreen->info.chip_class >= GFX9) {
6727 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6728 LLVMValueRef parts[4];
6729 bool vs_needs_prolog =
6730 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6731
6732 /* TCS main part */
6733 parts[2] = ctx.main_fn;
6734
6735 /* TCS epilog */
6736 union si_shader_part_key tcs_epilog_key;
6737 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6738 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6739 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6740 parts[3] = ctx.main_fn;
6741
6742 /* VS as LS main part */
6743 struct si_shader shader_ls = {};
6744 shader_ls.selector = ls;
6745 shader_ls.key.as_ls = 1;
6746 shader_ls.key.mono = shader->key.mono;
6747 shader_ls.key.opt = shader->key.opt;
6748 shader_ls.is_monolithic = true;
6749 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6750
6751 if (!si_compile_tgsi_main(&ctx)) {
6752 si_llvm_dispose(&ctx);
6753 return -1;
6754 }
6755 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6756 parts[1] = ctx.main_fn;
6757
6758 /* LS prolog */
6759 if (vs_needs_prolog) {
6760 union si_shader_part_key vs_prolog_key;
6761 si_get_vs_prolog_key(&ls->info,
6762 shader_ls.info.num_input_sgprs,
6763 &shader->key.part.tcs.ls_prolog,
6764 shader, &vs_prolog_key);
6765 vs_prolog_key.vs_prolog.is_monolithic = true;
6766 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6767 parts[0] = ctx.main_fn;
6768 }
6769
6770 /* Reset the shader context. */
6771 ctx.shader = shader;
6772 ctx.type = PIPE_SHADER_TESS_CTRL;
6773
6774 si_build_wrapper_function(&ctx,
6775 parts + !vs_needs_prolog,
6776 4 - !vs_needs_prolog, vs_needs_prolog,
6777 vs_needs_prolog ? 2 : 1);
6778 } else {
6779 LLVMValueRef parts[2];
6780 union si_shader_part_key epilog_key;
6781
6782 parts[0] = ctx.main_fn;
6783
6784 memset(&epilog_key, 0, sizeof(epilog_key));
6785 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6786 si_build_tcs_epilog_function(&ctx, &epilog_key);
6787 parts[1] = ctx.main_fn;
6788
6789 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6790 }
6791 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6792 if (ctx.screen->info.chip_class >= GFX9) {
6793 struct si_shader_selector *es = shader->key.part.gs.es;
6794 LLVMValueRef es_prolog = NULL;
6795 LLVMValueRef es_main = NULL;
6796 LLVMValueRef gs_prolog = NULL;
6797 LLVMValueRef gs_main = ctx.main_fn;
6798
6799 /* GS prolog */
6800 union si_shader_part_key gs_prolog_key;
6801 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6802 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6803 gs_prolog_key.gs_prolog.is_monolithic = true;
6804 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6805 gs_prolog = ctx.main_fn;
6806
6807 /* ES main part */
6808 struct si_shader shader_es = {};
6809 shader_es.selector = es;
6810 shader_es.key.as_es = 1;
6811 shader_es.key.mono = shader->key.mono;
6812 shader_es.key.opt = shader->key.opt;
6813 shader_es.is_monolithic = true;
6814 si_llvm_context_set_tgsi(&ctx, &shader_es);
6815
6816 if (!si_compile_tgsi_main(&ctx)) {
6817 si_llvm_dispose(&ctx);
6818 return -1;
6819 }
6820 shader->info.uses_instanceid |= es->info.uses_instanceid;
6821 es_main = ctx.main_fn;
6822
6823 /* ES prolog */
6824 if (es->vs_needs_prolog) {
6825 union si_shader_part_key vs_prolog_key;
6826 si_get_vs_prolog_key(&es->info,
6827 shader_es.info.num_input_sgprs,
6828 &shader->key.part.gs.vs_prolog,
6829 shader, &vs_prolog_key);
6830 vs_prolog_key.vs_prolog.is_monolithic = true;
6831 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6832 es_prolog = ctx.main_fn;
6833 }
6834
6835 /* Reset the shader context. */
6836 ctx.shader = shader;
6837 ctx.type = PIPE_SHADER_GEOMETRY;
6838
6839 /* Prepare the array of shader parts. */
6840 LLVMValueRef parts[4];
6841 unsigned num_parts = 0, main_part, next_first_part;
6842
6843 if (es_prolog)
6844 parts[num_parts++] = es_prolog;
6845
6846 parts[main_part = num_parts++] = es_main;
6847 parts[next_first_part = num_parts++] = gs_prolog;
6848 parts[num_parts++] = gs_main;
6849
6850 si_build_wrapper_function(&ctx, parts, num_parts,
6851 main_part, next_first_part);
6852 } else {
6853 LLVMValueRef parts[2];
6854 union si_shader_part_key prolog_key;
6855
6856 parts[1] = ctx.main_fn;
6857
6858 memset(&prolog_key, 0, sizeof(prolog_key));
6859 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6860 si_build_gs_prolog_function(&ctx, &prolog_key);
6861 parts[0] = ctx.main_fn;
6862
6863 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6864 }
6865 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6866 LLVMValueRef parts[3];
6867 union si_shader_part_key prolog_key;
6868 union si_shader_part_key epilog_key;
6869 bool need_prolog;
6870
6871 si_get_ps_prolog_key(shader, &prolog_key, false);
6872 need_prolog = si_need_ps_prolog(&prolog_key);
6873
6874 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6875
6876 if (need_prolog) {
6877 si_build_ps_prolog_function(&ctx, &prolog_key);
6878 parts[0] = ctx.main_fn;
6879 }
6880
6881 si_get_ps_epilog_key(shader, &epilog_key);
6882 si_build_ps_epilog_function(&ctx, &epilog_key);
6883 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6884
6885 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6886 need_prolog ? 1 : 0, 0);
6887 }
6888
6889 si_llvm_optimize_module(&ctx);
6890
6891 /* Post-optimization transformations and analysis. */
6892 si_optimize_vs_outputs(&ctx);
6893
6894 if ((debug && debug->debug_message) ||
6895 si_can_dump_shader(sscreen, ctx.type)) {
6896 ctx.shader->config.private_mem_vgprs =
6897 ac_count_scratch_private_memory(ctx.main_fn);
6898 }
6899
6900 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6901 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6902 LLVMPointerTypeKind);
6903
6904 /* Compile to bytecode. */
6905 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6906 ctx.ac.module, debug, ctx.type,
6907 si_get_shader_name(shader, ctx.type),
6908 si_should_optimize_less(compiler, shader->selector));
6909 si_llvm_dispose(&ctx);
6910 if (r) {
6911 fprintf(stderr, "LLVM failed to compile shader\n");
6912 return r;
6913 }
6914
6915 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6916 * LLVM 3.9svn has this bug.
6917 */
6918 if (sel->type == PIPE_SHADER_COMPUTE) {
6919 unsigned wave_size = 64;
6920 unsigned max_vgprs = 256;
6921 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
6922 unsigned max_sgprs_per_wave = 128;
6923 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6924 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6925 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6926
6927 max_vgprs = max_vgprs / min_waves_per_simd;
6928 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6929
6930 if (shader->config.num_sgprs > max_sgprs ||
6931 shader->config.num_vgprs > max_vgprs) {
6932 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6933 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6934 shader->config.num_sgprs, shader->config.num_vgprs,
6935 max_sgprs, max_vgprs);
6936
6937 /* Just terminate the process, because dependent
6938 * shaders can hang due to bad input data, but use
6939 * the env var to allow shader-db to work.
6940 */
6941 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6942 abort();
6943 }
6944 }
6945
6946 /* Add the scratch offset to input SGPRs. */
6947 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6948 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6949
6950 /* Calculate the number of fragment input VGPRs. */
6951 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6952 shader->info.num_input_vgprs = 0;
6953 shader->info.face_vgpr_index = -1;
6954 shader->info.ancillary_vgpr_index = -1;
6955
6956 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6957 shader->info.num_input_vgprs += 2;
6958 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6959 shader->info.num_input_vgprs += 2;
6960 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6961 shader->info.num_input_vgprs += 2;
6962 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6963 shader->info.num_input_vgprs += 3;
6964 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6965 shader->info.num_input_vgprs += 2;
6966 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6967 shader->info.num_input_vgprs += 2;
6968 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6969 shader->info.num_input_vgprs += 2;
6970 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6971 shader->info.num_input_vgprs += 1;
6972 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6973 shader->info.num_input_vgprs += 1;
6974 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6975 shader->info.num_input_vgprs += 1;
6976 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6977 shader->info.num_input_vgprs += 1;
6978 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6979 shader->info.num_input_vgprs += 1;
6980 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6981 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6982 shader->info.num_input_vgprs += 1;
6983 }
6984 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6985 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6986 shader->info.num_input_vgprs += 1;
6987 }
6988 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6989 shader->info.num_input_vgprs += 1;
6990 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6991 shader->info.num_input_vgprs += 1;
6992 }
6993
6994 si_calculate_max_simd_waves(shader);
6995 si_shader_dump_stats_for_shader_db(shader, debug);
6996 return 0;
6997 }
6998
6999 /**
7000 * Create, compile and return a shader part (prolog or epilog).
7001 *
7002 * \param sscreen screen
7003 * \param list list of shader parts of the same category
7004 * \param type shader type
7005 * \param key shader part key
7006 * \param prolog whether the part being requested is a prolog
7007 * \param tm LLVM target machine
7008 * \param debug debug callback
7009 * \param build the callback responsible for building the main function
7010 * \return non-NULL on success
7011 */
7012 static struct si_shader_part *
7013 si_get_shader_part(struct si_screen *sscreen,
7014 struct si_shader_part **list,
7015 enum pipe_shader_type type,
7016 bool prolog,
7017 union si_shader_part_key *key,
7018 struct ac_llvm_compiler *compiler,
7019 struct pipe_debug_callback *debug,
7020 void (*build)(struct si_shader_context *,
7021 union si_shader_part_key *),
7022 const char *name)
7023 {
7024 struct si_shader_part *result;
7025
7026 mtx_lock(&sscreen->shader_parts_mutex);
7027
7028 /* Find existing. */
7029 for (result = *list; result; result = result->next) {
7030 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7031 mtx_unlock(&sscreen->shader_parts_mutex);
7032 return result;
7033 }
7034 }
7035
7036 /* Compile a new one. */
7037 result = CALLOC_STRUCT(si_shader_part);
7038 result->key = *key;
7039
7040 struct si_shader shader = {};
7041 struct si_shader_context ctx;
7042
7043 si_init_shader_ctx(&ctx, sscreen, compiler);
7044 ctx.shader = &shader;
7045 ctx.type = type;
7046
7047 switch (type) {
7048 case PIPE_SHADER_VERTEX:
7049 shader.key.as_ls = key->vs_prolog.as_ls;
7050 shader.key.as_es = key->vs_prolog.as_es;
7051 break;
7052 case PIPE_SHADER_TESS_CTRL:
7053 assert(!prolog);
7054 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7055 break;
7056 case PIPE_SHADER_GEOMETRY:
7057 assert(prolog);
7058 break;
7059 case PIPE_SHADER_FRAGMENT:
7060 if (prolog)
7061 shader.key.part.ps.prolog = key->ps_prolog.states;
7062 else
7063 shader.key.part.ps.epilog = key->ps_epilog.states;
7064 break;
7065 default:
7066 unreachable("bad shader part");
7067 }
7068
7069 build(&ctx, key);
7070
7071 /* Compile. */
7072 si_llvm_optimize_module(&ctx);
7073
7074 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7075 ctx.ac.module, debug, ctx.type, name, false)) {
7076 FREE(result);
7077 result = NULL;
7078 goto out;
7079 }
7080
7081 result->next = *list;
7082 *list = result;
7083
7084 out:
7085 si_llvm_dispose(&ctx);
7086 mtx_unlock(&sscreen->shader_parts_mutex);
7087 return result;
7088 }
7089
7090 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7091 {
7092 LLVMValueRef ptr[2], list;
7093 bool merged_shader = is_merged_shader(ctx);
7094
7095 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7096 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7097 ac_array_in_const32_addr_space(ctx->v4i32), "");
7098 return list;
7099 }
7100
7101 /**
7102 * Build the vertex shader prolog function.
7103 *
7104 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7105 * All inputs are returned unmodified. The vertex load indices are
7106 * stored after them, which will be used by the API VS for fetching inputs.
7107 *
7108 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7109 * input_v0,
7110 * input_v1,
7111 * input_v2,
7112 * input_v3,
7113 * (VertexID + BaseVertex),
7114 * (InstanceID + StartInstance),
7115 * (InstanceID / 2 + StartInstance)
7116 */
7117 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7118 union si_shader_part_key *key)
7119 {
7120 struct si_function_info fninfo;
7121 LLVMTypeRef *returns;
7122 LLVMValueRef ret, func;
7123 int num_returns, i;
7124 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7125 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7126 LLVMValueRef input_vgprs[9];
7127 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7128 num_input_vgprs;
7129 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7130
7131 si_init_function_info(&fninfo);
7132
7133 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7134 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7135 sizeof(LLVMTypeRef));
7136 num_returns = 0;
7137
7138 /* Declare input and output SGPRs. */
7139 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7140 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7141 returns[num_returns++] = ctx->i32;
7142 }
7143
7144 /* Preloaded VGPRs (outputs must be floats) */
7145 for (i = 0; i < num_input_vgprs; i++) {
7146 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7147 returns[num_returns++] = ctx->f32;
7148 }
7149
7150 /* Vertex load indices. */
7151 for (i = 0; i <= key->vs_prolog.last_input; i++)
7152 returns[num_returns++] = ctx->f32;
7153
7154 /* Create the function. */
7155 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7156 func = ctx->main_fn;
7157
7158 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7159 if (!key->vs_prolog.is_monolithic)
7160 si_init_exec_from_input(ctx, 3, 0);
7161
7162 if (key->vs_prolog.as_ls &&
7163 ctx->screen->has_ls_vgpr_init_bug) {
7164 /* If there are no HS threads, SPI loads the LS VGPRs
7165 * starting at VGPR 0. Shift them back to where they
7166 * belong.
7167 */
7168 LLVMValueRef has_hs_threads =
7169 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7170 si_unpack_param(ctx, 3, 8, 8),
7171 ctx->i32_0, "");
7172
7173 for (i = 4; i > 0; --i) {
7174 input_vgprs[i + 1] =
7175 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7176 input_vgprs[i + 1],
7177 input_vgprs[i - 1], "");
7178 }
7179 }
7180 }
7181
7182 unsigned vertex_id_vgpr = first_vs_vgpr;
7183 unsigned instance_id_vgpr = first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7184
7185 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7186 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7187
7188 /* InstanceID = VertexID >> 16;
7189 * VertexID = VertexID & 0xffff;
7190 */
7191 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7192 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7193 LLVMConstInt(ctx->i32, 16, 0), "");
7194 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7195 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7196 }
7197
7198 /* Copy inputs to outputs. This should be no-op, as the registers match,
7199 * but it will prevent the compiler from overwriting them unintentionally.
7200 */
7201 ret = ctx->return_value;
7202 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7203 LLVMValueRef p = LLVMGetParam(func, i);
7204 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7205 }
7206 for (i = 0; i < num_input_vgprs; i++) {
7207 LLVMValueRef p = input_vgprs[i];
7208
7209 if (i == vertex_id_vgpr)
7210 p = ctx->abi.vertex_id;
7211 else if (i == instance_id_vgpr)
7212 p = ctx->abi.instance_id;
7213
7214 p = ac_to_float(&ctx->ac, p);
7215 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7216 key->vs_prolog.num_input_sgprs + i, "");
7217 }
7218
7219 /* Compute vertex load indices from instance divisors. */
7220 LLVMValueRef instance_divisor_constbuf = NULL;
7221
7222 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7223 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7224 LLVMValueRef buf_index =
7225 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7226 instance_divisor_constbuf =
7227 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7228 }
7229
7230 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7231 bool divisor_is_one =
7232 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7233 bool divisor_is_fetched =
7234 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7235 LLVMValueRef index = NULL;
7236
7237 if (divisor_is_one) {
7238 index = ctx->abi.instance_id;
7239 } else if (divisor_is_fetched) {
7240 LLVMValueRef udiv_factors[4];
7241
7242 for (unsigned j = 0; j < 4; j++) {
7243 udiv_factors[j] =
7244 buffer_load_const(ctx, instance_divisor_constbuf,
7245 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7246 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7247 }
7248 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7249 * Such InstanceID might not be achievable in a reasonable time though.
7250 */
7251 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7252 udiv_factors[0], udiv_factors[1],
7253 udiv_factors[2], udiv_factors[3]);
7254 }
7255
7256 if (divisor_is_one || divisor_is_fetched) {
7257 /* Add StartInstance. */
7258 index = LLVMBuildAdd(ctx->ac.builder, index,
7259 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7260 SI_SGPR_START_INSTANCE), "");
7261 } else {
7262 /* VertexID + BaseVertex */
7263 index = LLVMBuildAdd(ctx->ac.builder,
7264 ctx->abi.vertex_id,
7265 LLVMGetParam(func, user_sgpr_base +
7266 SI_SGPR_BASE_VERTEX), "");
7267 }
7268
7269 index = ac_to_float(&ctx->ac, index);
7270 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7271 fninfo.num_params + i, "");
7272 }
7273
7274 si_llvm_build_ret(ctx, ret);
7275 }
7276
7277 static bool si_get_vs_prolog(struct si_screen *sscreen,
7278 struct ac_llvm_compiler *compiler,
7279 struct si_shader *shader,
7280 struct pipe_debug_callback *debug,
7281 struct si_shader *main_part,
7282 const struct si_vs_prolog_bits *key)
7283 {
7284 struct si_shader_selector *vs = main_part->selector;
7285
7286 if (!si_vs_needs_prolog(vs, key))
7287 return true;
7288
7289 /* Get the prolog. */
7290 union si_shader_part_key prolog_key;
7291 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7292 key, shader, &prolog_key);
7293
7294 shader->prolog =
7295 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7296 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7297 debug, si_build_vs_prolog_function,
7298 "Vertex Shader Prolog");
7299 return shader->prolog != NULL;
7300 }
7301
7302 /**
7303 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7304 */
7305 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7306 struct ac_llvm_compiler *compiler,
7307 struct si_shader *shader,
7308 struct pipe_debug_callback *debug)
7309 {
7310 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7311 &shader->key.part.vs.prolog);
7312 }
7313
7314 /**
7315 * Compile the TCS epilog function. This writes tesselation factors to memory
7316 * based on the output primitive type of the tesselator (determined by TES).
7317 */
7318 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7319 union si_shader_part_key *key)
7320 {
7321 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7322 struct si_function_info fninfo;
7323 LLVMValueRef func;
7324
7325 si_init_function_info(&fninfo);
7326
7327 if (ctx->screen->info.chip_class >= GFX9) {
7328 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7329 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7330 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7331 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7332 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7333 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7334 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7337 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7338 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7339 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7340 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7341 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7343 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7344 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7345 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7346 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7347 } else {
7348 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7349 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7350 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7351 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7352 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7353 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7354 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7355 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7356 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7357 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7358 }
7359
7360 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7361 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7362 unsigned tess_factors_idx =
7363 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7364 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7365 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7366
7367 for (unsigned i = 0; i < 6; i++)
7368 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7369
7370 /* Create the function. */
7371 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7372 ctx->screen->info.chip_class >= GFX7 ? 128 : 64);
7373 ac_declare_lds_as_pointer(&ctx->ac);
7374 func = ctx->main_fn;
7375
7376 LLVMValueRef invoc0_tess_factors[6];
7377 for (unsigned i = 0; i < 6; i++)
7378 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7379
7380 si_write_tess_factors(bld_base,
7381 LLVMGetParam(func, tess_factors_idx),
7382 LLVMGetParam(func, tess_factors_idx + 1),
7383 LLVMGetParam(func, tess_factors_idx + 2),
7384 invoc0_tess_factors, invoc0_tess_factors + 4);
7385
7386 LLVMBuildRetVoid(ctx->ac.builder);
7387 }
7388
7389 /**
7390 * Select and compile (or reuse) TCS parts (epilog).
7391 */
7392 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7393 struct ac_llvm_compiler *compiler,
7394 struct si_shader *shader,
7395 struct pipe_debug_callback *debug)
7396 {
7397 if (sscreen->info.chip_class >= GFX9) {
7398 struct si_shader *ls_main_part =
7399 shader->key.part.tcs.ls->main_shader_part_ls;
7400
7401 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7402 &shader->key.part.tcs.ls_prolog))
7403 return false;
7404
7405 shader->previous_stage = ls_main_part;
7406 }
7407
7408 /* Get the epilog. */
7409 union si_shader_part_key epilog_key;
7410 memset(&epilog_key, 0, sizeof(epilog_key));
7411 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7412
7413 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7414 PIPE_SHADER_TESS_CTRL, false,
7415 &epilog_key, compiler, debug,
7416 si_build_tcs_epilog_function,
7417 "Tessellation Control Shader Epilog");
7418 return shader->epilog != NULL;
7419 }
7420
7421 /**
7422 * Select and compile (or reuse) GS parts (prolog).
7423 */
7424 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7425 struct ac_llvm_compiler *compiler,
7426 struct si_shader *shader,
7427 struct pipe_debug_callback *debug)
7428 {
7429 if (sscreen->info.chip_class >= GFX9) {
7430 struct si_shader *es_main_part =
7431 shader->key.part.gs.es->main_shader_part_es;
7432
7433 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7434 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7435 &shader->key.part.gs.vs_prolog))
7436 return false;
7437
7438 shader->previous_stage = es_main_part;
7439 }
7440
7441 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7442 return true;
7443
7444 union si_shader_part_key prolog_key;
7445 memset(&prolog_key, 0, sizeof(prolog_key));
7446 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7447
7448 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7449 PIPE_SHADER_GEOMETRY, true,
7450 &prolog_key, compiler, debug,
7451 si_build_gs_prolog_function,
7452 "Geometry Shader Prolog");
7453 return shader->prolog2 != NULL;
7454 }
7455
7456 /**
7457 * Build the pixel shader prolog function. This handles:
7458 * - two-side color selection and interpolation
7459 * - overriding interpolation parameters for the API PS
7460 * - polygon stippling
7461 *
7462 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7463 * overriden by other states. (e.g. per-sample interpolation)
7464 * Interpolated colors are stored after the preloaded VGPRs.
7465 */
7466 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7467 union si_shader_part_key *key)
7468 {
7469 struct si_function_info fninfo;
7470 LLVMValueRef ret, func;
7471 int num_returns, i, num_color_channels;
7472
7473 assert(si_need_ps_prolog(key));
7474
7475 si_init_function_info(&fninfo);
7476
7477 /* Declare inputs. */
7478 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7479 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7480
7481 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7482 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7483
7484 /* Declare outputs (same as inputs + add colors if needed) */
7485 num_returns = fninfo.num_params;
7486 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7487 for (i = 0; i < num_color_channels; i++)
7488 fninfo.types[num_returns++] = ctx->f32;
7489
7490 /* Create the function. */
7491 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7492 &fninfo, 0);
7493 func = ctx->main_fn;
7494
7495 /* Copy inputs to outputs. This should be no-op, as the registers match,
7496 * but it will prevent the compiler from overwriting them unintentionally.
7497 */
7498 ret = ctx->return_value;
7499 for (i = 0; i < fninfo.num_params; i++) {
7500 LLVMValueRef p = LLVMGetParam(func, i);
7501 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7502 }
7503
7504 /* Polygon stippling. */
7505 if (key->ps_prolog.states.poly_stipple) {
7506 /* POS_FIXED_PT is always last. */
7507 unsigned pos = key->ps_prolog.num_input_sgprs +
7508 key->ps_prolog.num_input_vgprs - 1;
7509 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7510
7511 si_llvm_emit_polygon_stipple(ctx, list, pos);
7512 }
7513
7514 if (key->ps_prolog.states.bc_optimize_for_persp ||
7515 key->ps_prolog.states.bc_optimize_for_linear) {
7516 unsigned i, base = key->ps_prolog.num_input_sgprs;
7517 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7518
7519 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7520 * The hw doesn't compute CENTROID if the whole wave only
7521 * contains fully-covered quads.
7522 *
7523 * PRIM_MASK is after user SGPRs.
7524 */
7525 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7526 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7527 LLVMConstInt(ctx->i32, 31, 0), "");
7528 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7529 ctx->i1, "");
7530
7531 if (key->ps_prolog.states.bc_optimize_for_persp) {
7532 /* Read PERSP_CENTER. */
7533 for (i = 0; i < 2; i++)
7534 center[i] = LLVMGetParam(func, base + 2 + i);
7535 /* Read PERSP_CENTROID. */
7536 for (i = 0; i < 2; i++)
7537 centroid[i] = LLVMGetParam(func, base + 4 + i);
7538 /* Select PERSP_CENTROID. */
7539 for (i = 0; i < 2; i++) {
7540 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7541 center[i], centroid[i], "");
7542 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7543 tmp, base + 4 + i, "");
7544 }
7545 }
7546 if (key->ps_prolog.states.bc_optimize_for_linear) {
7547 /* Read LINEAR_CENTER. */
7548 for (i = 0; i < 2; i++)
7549 center[i] = LLVMGetParam(func, base + 8 + i);
7550 /* Read LINEAR_CENTROID. */
7551 for (i = 0; i < 2; i++)
7552 centroid[i] = LLVMGetParam(func, base + 10 + i);
7553 /* Select LINEAR_CENTROID. */
7554 for (i = 0; i < 2; i++) {
7555 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7556 center[i], centroid[i], "");
7557 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7558 tmp, base + 10 + i, "");
7559 }
7560 }
7561 }
7562
7563 /* Force per-sample interpolation. */
7564 if (key->ps_prolog.states.force_persp_sample_interp) {
7565 unsigned i, base = key->ps_prolog.num_input_sgprs;
7566 LLVMValueRef persp_sample[2];
7567
7568 /* Read PERSP_SAMPLE. */
7569 for (i = 0; i < 2; i++)
7570 persp_sample[i] = LLVMGetParam(func, base + i);
7571 /* Overwrite PERSP_CENTER. */
7572 for (i = 0; i < 2; i++)
7573 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7574 persp_sample[i], base + 2 + i, "");
7575 /* Overwrite PERSP_CENTROID. */
7576 for (i = 0; i < 2; i++)
7577 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7578 persp_sample[i], base + 4 + i, "");
7579 }
7580 if (key->ps_prolog.states.force_linear_sample_interp) {
7581 unsigned i, base = key->ps_prolog.num_input_sgprs;
7582 LLVMValueRef linear_sample[2];
7583
7584 /* Read LINEAR_SAMPLE. */
7585 for (i = 0; i < 2; i++)
7586 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7587 /* Overwrite LINEAR_CENTER. */
7588 for (i = 0; i < 2; i++)
7589 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7590 linear_sample[i], base + 8 + i, "");
7591 /* Overwrite LINEAR_CENTROID. */
7592 for (i = 0; i < 2; i++)
7593 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7594 linear_sample[i], base + 10 + i, "");
7595 }
7596
7597 /* Force center interpolation. */
7598 if (key->ps_prolog.states.force_persp_center_interp) {
7599 unsigned i, base = key->ps_prolog.num_input_sgprs;
7600 LLVMValueRef persp_center[2];
7601
7602 /* Read PERSP_CENTER. */
7603 for (i = 0; i < 2; i++)
7604 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7605 /* Overwrite PERSP_SAMPLE. */
7606 for (i = 0; i < 2; i++)
7607 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7608 persp_center[i], base + i, "");
7609 /* Overwrite PERSP_CENTROID. */
7610 for (i = 0; i < 2; i++)
7611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7612 persp_center[i], base + 4 + i, "");
7613 }
7614 if (key->ps_prolog.states.force_linear_center_interp) {
7615 unsigned i, base = key->ps_prolog.num_input_sgprs;
7616 LLVMValueRef linear_center[2];
7617
7618 /* Read LINEAR_CENTER. */
7619 for (i = 0; i < 2; i++)
7620 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7621 /* Overwrite LINEAR_SAMPLE. */
7622 for (i = 0; i < 2; i++)
7623 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7624 linear_center[i], base + 6 + i, "");
7625 /* Overwrite LINEAR_CENTROID. */
7626 for (i = 0; i < 2; i++)
7627 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7628 linear_center[i], base + 10 + i, "");
7629 }
7630
7631 /* Interpolate colors. */
7632 unsigned color_out_idx = 0;
7633 for (i = 0; i < 2; i++) {
7634 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7635 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7636 key->ps_prolog.face_vgpr_index;
7637 LLVMValueRef interp[2], color[4];
7638 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7639
7640 if (!writemask)
7641 continue;
7642
7643 /* If the interpolation qualifier is not CONSTANT (-1). */
7644 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7645 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7646 key->ps_prolog.color_interp_vgpr_index[i];
7647
7648 /* Get the (i,j) updated by bc_optimize handling. */
7649 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7650 interp_vgpr, "");
7651 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7652 interp_vgpr + 1, "");
7653 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7654 }
7655
7656 /* Use the absolute location of the input. */
7657 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7658
7659 if (key->ps_prolog.states.color_two_side) {
7660 face = LLVMGetParam(func, face_vgpr);
7661 face = ac_to_integer(&ctx->ac, face);
7662 }
7663
7664 interp_fs_input(ctx,
7665 key->ps_prolog.color_attr_index[i],
7666 TGSI_SEMANTIC_COLOR, i,
7667 key->ps_prolog.num_interp_inputs,
7668 key->ps_prolog.colors_read, interp_ij,
7669 prim_mask, face, color);
7670
7671 while (writemask) {
7672 unsigned chan = u_bit_scan(&writemask);
7673 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7674 fninfo.num_params + color_out_idx++, "");
7675 }
7676 }
7677
7678 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7679 * says:
7680 *
7681 * "When per-sample shading is active due to the use of a fragment
7682 * input qualified by sample or due to the use of the gl_SampleID
7683 * or gl_SamplePosition variables, only the bit for the current
7684 * sample is set in gl_SampleMaskIn. When state specifies multiple
7685 * fragment shader invocations for a given fragment, the sample
7686 * mask for any single fragment shader invocation may specify a
7687 * subset of the covered samples for the fragment. In this case,
7688 * the bit corresponding to each covered sample will be set in
7689 * exactly one fragment shader invocation."
7690 *
7691 * The samplemask loaded by hardware is always the coverage of the
7692 * entire pixel/fragment, so mask bits out based on the sample ID.
7693 */
7694 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7695 /* The bit pattern matches that used by fixed function fragment
7696 * processing. */
7697 static const uint16_t ps_iter_masks[] = {
7698 0xffff, /* not used */
7699 0x5555,
7700 0x1111,
7701 0x0101,
7702 0x0001,
7703 };
7704 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7705
7706 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7707 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7708 key->ps_prolog.ancillary_vgpr_index;
7709 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7710 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7711
7712 samplemask = ac_to_integer(&ctx->ac, samplemask);
7713 samplemask = LLVMBuildAnd(
7714 ctx->ac.builder,
7715 samplemask,
7716 LLVMBuildShl(ctx->ac.builder,
7717 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7718 sampleid, ""),
7719 "");
7720 samplemask = ac_to_float(&ctx->ac, samplemask);
7721
7722 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7723 ancillary_vgpr + 1, "");
7724 }
7725
7726 /* Tell LLVM to insert WQM instruction sequence when needed. */
7727 if (key->ps_prolog.wqm) {
7728 LLVMAddTargetDependentFunctionAttr(func,
7729 "amdgpu-ps-wqm-outputs", "");
7730 }
7731
7732 si_llvm_build_ret(ctx, ret);
7733 }
7734
7735 /**
7736 * Build the pixel shader epilog function. This handles everything that must be
7737 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7738 */
7739 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7740 union si_shader_part_key *key)
7741 {
7742 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7743 struct si_function_info fninfo;
7744 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7745 int i;
7746 struct si_ps_exports exp = {};
7747
7748 si_init_function_info(&fninfo);
7749
7750 /* Declare input SGPRs. */
7751 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7752 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7753 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7754 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7755 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7756
7757 /* Declare input VGPRs. */
7758 unsigned required_num_params =
7759 fninfo.num_sgpr_params +
7760 util_bitcount(key->ps_epilog.colors_written) * 4 +
7761 key->ps_epilog.writes_z +
7762 key->ps_epilog.writes_stencil +
7763 key->ps_epilog.writes_samplemask;
7764
7765 required_num_params = MAX2(required_num_params,
7766 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7767
7768 while (fninfo.num_params < required_num_params)
7769 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7770
7771 /* Create the function. */
7772 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7773 /* Disable elimination of unused inputs. */
7774 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7775 "InitialPSInputAddr", 0xffffff);
7776
7777 /* Process colors. */
7778 unsigned vgpr = fninfo.num_sgpr_params;
7779 unsigned colors_written = key->ps_epilog.colors_written;
7780 int last_color_export = -1;
7781
7782 /* Find the last color export. */
7783 if (!key->ps_epilog.writes_z &&
7784 !key->ps_epilog.writes_stencil &&
7785 !key->ps_epilog.writes_samplemask) {
7786 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7787
7788 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7789 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7790 /* Just set this if any of the colorbuffers are enabled. */
7791 if (spi_format &
7792 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7793 last_color_export = 0;
7794 } else {
7795 for (i = 0; i < 8; i++)
7796 if (colors_written & (1 << i) &&
7797 (spi_format >> (i * 4)) & 0xf)
7798 last_color_export = i;
7799 }
7800 }
7801
7802 while (colors_written) {
7803 LLVMValueRef color[4];
7804 int mrt = u_bit_scan(&colors_written);
7805
7806 for (i = 0; i < 4; i++)
7807 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7808
7809 si_export_mrt_color(bld_base, color, mrt,
7810 fninfo.num_params - 1,
7811 mrt == last_color_export, &exp);
7812 }
7813
7814 /* Process depth, stencil, samplemask. */
7815 if (key->ps_epilog.writes_z)
7816 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7817 if (key->ps_epilog.writes_stencil)
7818 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7819 if (key->ps_epilog.writes_samplemask)
7820 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7821
7822 if (depth || stencil || samplemask)
7823 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7824 else if (last_color_export == -1)
7825 ac_build_export_null(&ctx->ac);
7826
7827 if (exp.num)
7828 si_emit_ps_exports(ctx, &exp);
7829
7830 /* Compile. */
7831 LLVMBuildRetVoid(ctx->ac.builder);
7832 }
7833
7834 /**
7835 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7836 */
7837 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7838 struct ac_llvm_compiler *compiler,
7839 struct si_shader *shader,
7840 struct pipe_debug_callback *debug)
7841 {
7842 union si_shader_part_key prolog_key;
7843 union si_shader_part_key epilog_key;
7844
7845 /* Get the prolog. */
7846 si_get_ps_prolog_key(shader, &prolog_key, true);
7847
7848 /* The prolog is a no-op if these aren't set. */
7849 if (si_need_ps_prolog(&prolog_key)) {
7850 shader->prolog =
7851 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7852 PIPE_SHADER_FRAGMENT, true,
7853 &prolog_key, compiler, debug,
7854 si_build_ps_prolog_function,
7855 "Fragment Shader Prolog");
7856 if (!shader->prolog)
7857 return false;
7858 }
7859
7860 /* Get the epilog. */
7861 si_get_ps_epilog_key(shader, &epilog_key);
7862
7863 shader->epilog =
7864 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7865 PIPE_SHADER_FRAGMENT, false,
7866 &epilog_key, compiler, debug,
7867 si_build_ps_epilog_function,
7868 "Fragment Shader Epilog");
7869 if (!shader->epilog)
7870 return false;
7871
7872 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7873 if (shader->key.part.ps.prolog.poly_stipple) {
7874 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7875 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7876 }
7877
7878 /* Set up the enable bits for per-sample shading if needed. */
7879 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7880 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7881 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7882 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7883 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7884 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7885 }
7886 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7887 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7888 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7889 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7890 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7891 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7892 }
7893 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7894 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7895 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7896 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7897 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7898 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7899 }
7900 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7901 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7902 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7903 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7904 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7905 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7906 }
7907
7908 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7909 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7910 !(shader->config.spi_ps_input_ena & 0xf)) {
7911 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7912 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7913 }
7914
7915 /* At least one pair of interpolation weights must be enabled. */
7916 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7917 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7918 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7919 }
7920
7921 /* Samplemask fixup requires the sample ID. */
7922 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7923 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7924 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7925 }
7926
7927 /* The sample mask input is always enabled, because the API shader always
7928 * passes it through to the epilog. Disable it here if it's unused.
7929 */
7930 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7931 !shader->selector->info.reads_samplemask)
7932 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7933
7934 return true;
7935 }
7936
7937 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7938 unsigned *lds_size)
7939 {
7940 /* If tessellation is all offchip and on-chip GS isn't used, this
7941 * workaround is not needed.
7942 */
7943 return;
7944
7945 /* SPI barrier management bug:
7946 * Make sure we have at least 4k of LDS in use to avoid the bug.
7947 * It applies to workgroup sizes of more than one wavefront.
7948 */
7949 if (sscreen->info.family == CHIP_BONAIRE ||
7950 sscreen->info.family == CHIP_KABINI)
7951 *lds_size = MAX2(*lds_size, 8);
7952 }
7953
7954 static void si_fix_resource_usage(struct si_screen *sscreen,
7955 struct si_shader *shader)
7956 {
7957 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7958
7959 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7960
7961 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7962 si_get_max_workgroup_size(shader) > 64) {
7963 si_multiwave_lds_size_workaround(sscreen,
7964 &shader->config.lds_size);
7965 }
7966 }
7967
7968 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
7969 struct si_shader *shader,
7970 struct pipe_debug_callback *debug)
7971 {
7972 struct si_shader_selector *sel = shader->selector;
7973 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7974 int r;
7975
7976 /* LS, ES, VS are compiled on demand if the main part hasn't been
7977 * compiled for that stage.
7978 *
7979 * Vertex shaders are compiled on demand when a vertex fetch
7980 * workaround must be applied.
7981 */
7982 if (shader->is_monolithic) {
7983 /* Monolithic shader (compiled as a whole, has many variants,
7984 * may take a long time to compile).
7985 */
7986 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
7987 if (r)
7988 return r;
7989 } else {
7990 /* The shader consists of several parts:
7991 *
7992 * - the middle part is the user shader, it has 1 variant only
7993 * and it was compiled during the creation of the shader
7994 * selector
7995 * - the prolog part is inserted at the beginning
7996 * - the epilog part is inserted at the end
7997 *
7998 * The prolog and epilog have many (but simple) variants.
7999 *
8000 * Starting with gfx9, geometry and tessellation control
8001 * shaders also contain the prolog and user shader parts of
8002 * the previous shader stage.
8003 */
8004
8005 if (!mainp)
8006 return -1;
8007
8008 /* Copy the compiled TGSI shader data over. */
8009 shader->is_binary_shared = true;
8010 shader->binary = mainp->binary;
8011 shader->config = mainp->config;
8012 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8013 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8014 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8015 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8016 memcpy(shader->info.vs_output_param_offset,
8017 mainp->info.vs_output_param_offset,
8018 sizeof(mainp->info.vs_output_param_offset));
8019 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8020 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8021 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8022
8023 /* Select prologs and/or epilogs. */
8024 switch (sel->type) {
8025 case PIPE_SHADER_VERTEX:
8026 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8027 return -1;
8028 break;
8029 case PIPE_SHADER_TESS_CTRL:
8030 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8031 return -1;
8032 break;
8033 case PIPE_SHADER_TESS_EVAL:
8034 break;
8035 case PIPE_SHADER_GEOMETRY:
8036 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8037 return -1;
8038 break;
8039 case PIPE_SHADER_FRAGMENT:
8040 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8041 return -1;
8042
8043 /* Make sure we have at least as many VGPRs as there
8044 * are allocated inputs.
8045 */
8046 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8047 shader->info.num_input_vgprs);
8048 break;
8049 }
8050
8051 /* Update SGPR and VGPR counts. */
8052 if (shader->prolog) {
8053 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8054 shader->prolog->config.num_sgprs);
8055 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8056 shader->prolog->config.num_vgprs);
8057 }
8058 if (shader->previous_stage) {
8059 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8060 shader->previous_stage->config.num_sgprs);
8061 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8062 shader->previous_stage->config.num_vgprs);
8063 shader->config.spilled_sgprs =
8064 MAX2(shader->config.spilled_sgprs,
8065 shader->previous_stage->config.spilled_sgprs);
8066 shader->config.spilled_vgprs =
8067 MAX2(shader->config.spilled_vgprs,
8068 shader->previous_stage->config.spilled_vgprs);
8069 shader->config.private_mem_vgprs =
8070 MAX2(shader->config.private_mem_vgprs,
8071 shader->previous_stage->config.private_mem_vgprs);
8072 shader->config.scratch_bytes_per_wave =
8073 MAX2(shader->config.scratch_bytes_per_wave,
8074 shader->previous_stage->config.scratch_bytes_per_wave);
8075 shader->info.uses_instanceid |=
8076 shader->previous_stage->info.uses_instanceid;
8077 }
8078 if (shader->prolog2) {
8079 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8080 shader->prolog2->config.num_sgprs);
8081 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8082 shader->prolog2->config.num_vgprs);
8083 }
8084 if (shader->epilog) {
8085 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8086 shader->epilog->config.num_sgprs);
8087 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8088 shader->epilog->config.num_vgprs);
8089 }
8090 si_calculate_max_simd_waves(shader);
8091 }
8092
8093 si_fix_resource_usage(sscreen, shader);
8094 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8095 stderr, true);
8096
8097 /* Upload. */
8098 r = si_shader_binary_upload(sscreen, shader);
8099 if (r) {
8100 fprintf(stderr, "LLVM failed to upload shader\n");
8101 return r;
8102 }
8103
8104 return 0;
8105 }
8106
8107 void si_shader_destroy(struct si_shader *shader)
8108 {
8109 if (shader->scratch_bo)
8110 si_resource_reference(&shader->scratch_bo, NULL);
8111
8112 si_resource_reference(&shader->bo, NULL);
8113
8114 if (!shader->is_binary_shared)
8115 ac_shader_binary_clean(&shader->binary);
8116
8117 free(shader->shader_log);
8118 }