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radeonsi: remove unused parameter from si_shader_binary_read_config
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 if (type == TGSI_TYPE_DOUBLE) {
598 LLVMValueRef value2;
599 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
600 lp_build_const_int32(gallivm, swizzle + 1));
601 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
602 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
603 }
604
605 return LLVMBuildBitCast(gallivm->builder, value,
606 tgsi2llvmtype(bld_base, type), "");
607 }
608
609 /**
610 * Store to LDS.
611 *
612 * \param swizzle offset (typically 0..3)
613 * \param dw_addr address in dwords
614 * \param value value to store
615 */
616 static void lds_store(struct lp_build_tgsi_context * bld_base,
617 unsigned swizzle, LLVMValueRef dw_addr,
618 LLVMValueRef value)
619 {
620 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
621 struct gallivm_state *gallivm = bld_base->base.gallivm;
622
623 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
624 lp_build_const_int32(gallivm, swizzle));
625
626 value = LLVMBuildBitCast(gallivm->builder, value,
627 LLVMInt32TypeInContext(gallivm->context), "");
628 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
629 dw_addr, value);
630 }
631
632 static LLVMValueRef fetch_input_tcs(
633 struct lp_build_tgsi_context *bld_base,
634 const struct tgsi_full_src_register *reg,
635 enum tgsi_opcode_type type, unsigned swizzle)
636 {
637 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
638 LLVMValueRef dw_addr, stride;
639
640 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
641 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
642 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
643
644 return lds_load(bld_base, type, swizzle, dw_addr);
645 }
646
647 static LLVMValueRef fetch_output_tcs(
648 struct lp_build_tgsi_context *bld_base,
649 const struct tgsi_full_src_register *reg,
650 enum tgsi_opcode_type type, unsigned swizzle)
651 {
652 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
653 LLVMValueRef dw_addr, stride;
654
655 if (reg->Register.Dimension) {
656 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
657 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
658 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
659 } else {
660 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
661 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
662 }
663
664 return lds_load(bld_base, type, swizzle, dw_addr);
665 }
666
667 static LLVMValueRef fetch_input_tes(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 if (reg->Register.Dimension) {
676 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
677 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
678 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
679 } else {
680 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
681 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
682 }
683
684 return lds_load(bld_base, type, swizzle, dw_addr);
685 }
686
687 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
688 const struct tgsi_full_instruction * inst,
689 const struct tgsi_opcode_info * info,
690 LLVMValueRef dst[4])
691 {
692 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
693 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
694 unsigned chan_index;
695 LLVMValueRef dw_addr, stride;
696
697 /* Only handle per-patch and per-vertex outputs here.
698 * Vectors will be lowered to scalars and this function will be called again.
699 */
700 if (reg->Register.File != TGSI_FILE_OUTPUT ||
701 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
702 radeon_llvm_emit_store(bld_base, inst, info, dst);
703 return;
704 }
705
706 if (reg->Register.Dimension) {
707 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
708 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
709 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
710 } else {
711 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
712 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
713 }
714
715 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
716 LLVMValueRef value = dst[chan_index];
717
718 if (inst->Instruction.Saturate)
719 value = radeon_llvm_saturate(bld_base, value);
720
721 lds_store(bld_base, chan_index, dw_addr, value);
722 }
723 }
724
725 static LLVMValueRef fetch_input_gs(
726 struct lp_build_tgsi_context *bld_base,
727 const struct tgsi_full_src_register *reg,
728 enum tgsi_opcode_type type,
729 unsigned swizzle)
730 {
731 struct lp_build_context *base = &bld_base->base;
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct si_shader *shader = si_shader_ctx->shader;
734 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
735 struct gallivm_state *gallivm = base->gallivm;
736 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
737 LLVMValueRef vtx_offset;
738 LLVMValueRef args[9];
739 unsigned vtx_offset_param;
740 struct tgsi_shader_info *info = &shader->selector->info;
741 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
742 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
743 unsigned param;
744 LLVMValueRef value;
745
746 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
747 return get_primitive_id(bld_base, swizzle);
748
749 if (!reg->Register.Dimension)
750 return NULL;
751
752 if (swizzle == ~0) {
753 LLVMValueRef values[TGSI_NUM_CHANNELS];
754 unsigned chan;
755 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
756 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
757 }
758 return lp_build_gather_values(bld_base->base.gallivm, values,
759 TGSI_NUM_CHANNELS);
760 }
761
762 /* Get the vertex offset parameter */
763 vtx_offset_param = reg->Dimension.Index;
764 if (vtx_offset_param < 2) {
765 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
766 } else {
767 assert(vtx_offset_param < 6);
768 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
769 }
770 vtx_offset = lp_build_mul_imm(uint,
771 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
772 vtx_offset_param),
773 4);
774
775 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
776 args[0] = si_shader_ctx->esgs_ring;
777 args[1] = vtx_offset;
778 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
779 args[3] = uint->zero;
780 args[4] = uint->one; /* OFFEN */
781 args[5] = uint->zero; /* IDXEN */
782 args[6] = uint->one; /* GLC */
783 args[7] = uint->zero; /* SLC */
784 args[8] = uint->zero; /* TFE */
785
786 value = lp_build_intrinsic(gallivm->builder,
787 "llvm.SI.buffer.load.dword.i32.i32",
788 i32, args, 9,
789 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
790 if (type == TGSI_TYPE_DOUBLE) {
791 LLVMValueRef value2;
792 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
793 value2 = lp_build_intrinsic(gallivm->builder,
794 "llvm.SI.buffer.load.dword.i32.i32",
795 i32, args, 9,
796 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
797 return radeon_llvm_emit_fetch_double(bld_base,
798 value, value2);
799 }
800 return LLVMBuildBitCast(gallivm->builder,
801 value,
802 tgsi2llvmtype(bld_base, type), "");
803 }
804
805 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
806 {
807 switch (interpolate) {
808 case TGSI_INTERPOLATE_CONSTANT:
809 return 0;
810
811 case TGSI_INTERPOLATE_LINEAR:
812 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
813 return SI_PARAM_LINEAR_SAMPLE;
814 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
815 return SI_PARAM_LINEAR_CENTROID;
816 else
817 return SI_PARAM_LINEAR_CENTER;
818 break;
819 case TGSI_INTERPOLATE_COLOR:
820 case TGSI_INTERPOLATE_PERSPECTIVE:
821 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
822 return SI_PARAM_PERSP_SAMPLE;
823 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
824 return SI_PARAM_PERSP_CENTROID;
825 else
826 return SI_PARAM_PERSP_CENTER;
827 break;
828 default:
829 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
830 return -1;
831 }
832 }
833
834 /* This shouldn't be used by explicit INTERP opcodes. */
835 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
836 unsigned param)
837 {
838 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
839 unsigned sample_param = 0;
840 LLVMValueRef default_ij, sample_ij, force_sample;
841
842 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
843
844 /* If the shader doesn't use center/centroid, just return the parameter.
845 *
846 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
847 * switch between center/centroid and sample without shader changes.
848 */
849 switch (param) {
850 case SI_PARAM_PERSP_CENTROID:
851 case SI_PARAM_PERSP_CENTER:
852 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
853 return default_ij;
854
855 sample_param = SI_PARAM_PERSP_SAMPLE;
856 break;
857
858 case SI_PARAM_LINEAR_CENTROID:
859 case SI_PARAM_LINEAR_CENTER:
860 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
861 return default_ij;
862
863 sample_param = SI_PARAM_LINEAR_SAMPLE;
864 break;
865
866 default:
867 return default_ij;
868 }
869
870 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
871 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
872
873 /* TODO: this can be done more efficiently by switching between
874 * 2 prologs.
875 */
876 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
877 SI_PARAM_PS_STATE_BITS);
878 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
879 LLVMInt1TypeInContext(gallivm->context), "");
880 return LLVMBuildSelect(gallivm->builder, force_sample,
881 sample_ij, default_ij, "");
882 }
883
884 static void declare_input_fs(
885 struct radeon_llvm_context *radeon_bld,
886 unsigned input_index,
887 const struct tgsi_full_declaration *decl)
888 {
889 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
890 struct si_shader_context *si_shader_ctx =
891 si_shader_context(&radeon_bld->soa.bld_base);
892 struct si_shader *shader = si_shader_ctx->shader;
893 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
894 struct gallivm_state *gallivm = base->gallivm;
895 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
896 LLVMValueRef main_fn = radeon_bld->main_fn;
897
898 LLVMValueRef interp_param = NULL;
899 int interp_param_idx;
900 const char * intr_name;
901
902 /* This value is:
903 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
904 * quad begins a new primitive. Bit 0 always needs
905 * to be unset)
906 * [32:16] ParamOffset
907 *
908 */
909 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
910 LLVMValueRef attr_number;
911
912 unsigned chan;
913
914 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
915 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
916 unsigned soa_index =
917 radeon_llvm_reg_index_soa(input_index, chan);
918 radeon_bld->inputs[soa_index] =
919 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
920
921 if (chan == 3)
922 /* RCP for fragcoord.w */
923 radeon_bld->inputs[soa_index] =
924 LLVMBuildFDiv(gallivm->builder,
925 lp_build_const_float(gallivm, 1.0f),
926 radeon_bld->inputs[soa_index],
927 "");
928 }
929 return;
930 }
931
932 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
933 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
934 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
935 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
936 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
937 lp_build_const_float(gallivm, 0.0f);
938 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
939 lp_build_const_float(gallivm, 1.0f);
940
941 return;
942 }
943
944 shader->ps_input_param_offset[input_index] = shader->nparam++;
945 attr_number = lp_build_const_int32(gallivm,
946 shader->ps_input_param_offset[input_index]);
947
948 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
949 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
950 decl->Interp.Location);
951 if (interp_param_idx == -1)
952 return;
953 else if (interp_param_idx)
954 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
955
956 /* fs.constant returns the param from the middle vertex, so it's not
957 * really useful for flat shading. It's meant to be used for custom
958 * interpolation (but the intrinsic can't fetch from the other two
959 * vertices).
960 *
961 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
962 * to do the right thing. The only reason we use fs.constant is that
963 * fs.interp cannot be used on integers, because they can be equal
964 * to NaN.
965 */
966 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
967
968 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
969 si_shader_ctx->shader->key.ps.color_two_side) {
970 LLVMValueRef args[4];
971 LLVMValueRef face, is_face_positive;
972 LLVMValueRef back_attr_number =
973 lp_build_const_int32(gallivm,
974 shader->ps_input_param_offset[input_index] + 1);
975
976 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
977
978 is_face_positive = LLVMBuildFCmp(gallivm->builder,
979 LLVMRealOGT, face,
980 lp_build_const_float(gallivm, 0.0f),
981 "");
982
983 args[2] = params;
984 args[3] = interp_param;
985 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
986 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
987 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
988 LLVMValueRef front, back;
989
990 args[0] = llvm_chan;
991 args[1] = attr_number;
992 front = lp_build_intrinsic(gallivm->builder, intr_name,
993 input_type, args, args[3] ? 4 : 3,
994 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
995
996 args[1] = back_attr_number;
997 back = lp_build_intrinsic(gallivm->builder, intr_name,
998 input_type, args, args[3] ? 4 : 3,
999 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1000
1001 radeon_bld->inputs[soa_index] =
1002 LLVMBuildSelect(gallivm->builder,
1003 is_face_positive,
1004 front,
1005 back,
1006 "");
1007 }
1008
1009 shader->nparam++;
1010 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1011 LLVMValueRef args[4];
1012
1013 args[0] = uint->zero;
1014 args[1] = attr_number;
1015 args[2] = params;
1016 args[3] = interp_param;
1017 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1018 lp_build_intrinsic(gallivm->builder, intr_name,
1019 input_type, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1022 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1023 lp_build_const_float(gallivm, 0.0f);
1024 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1025 lp_build_const_float(gallivm, 1.0f);
1026 } else {
1027 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1028 LLVMValueRef args[4];
1029 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1030 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1031 args[0] = llvm_chan;
1032 args[1] = attr_number;
1033 args[2] = params;
1034 args[3] = interp_param;
1035 radeon_bld->inputs[soa_index] =
1036 lp_build_intrinsic(gallivm->builder, intr_name,
1037 input_type, args, args[3] ? 4 : 3,
1038 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1039 }
1040 }
1041 }
1042
1043 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1044 {
1045 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1046 SI_PARAM_ANCILLARY, 8, 4);
1047 }
1048
1049 /**
1050 * Load a dword from a constant buffer.
1051 */
1052 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1053 LLVMValueRef offset, LLVMTypeRef return_type)
1054 {
1055 LLVMValueRef args[2] = {resource, offset};
1056
1057 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1058 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1059 }
1060
1061 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1062 {
1063 struct si_shader_context *si_shader_ctx =
1064 si_shader_context(&radeon_bld->soa.bld_base);
1065 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1066 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1067 LLVMBuilderRef builder = gallivm->builder;
1068 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1069 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1070 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1071
1072 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1073 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1074 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1075
1076 LLVMValueRef pos[4] = {
1077 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1078 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1079 lp_build_const_float(gallivm, 0),
1080 lp_build_const_float(gallivm, 0)
1081 };
1082
1083 return lp_build_gather_values(gallivm, pos, 4);
1084 }
1085
1086 static void declare_system_value(
1087 struct radeon_llvm_context * radeon_bld,
1088 unsigned index,
1089 const struct tgsi_full_declaration *decl)
1090 {
1091 struct si_shader_context *si_shader_ctx =
1092 si_shader_context(&radeon_bld->soa.bld_base);
1093 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1094 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1095 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1096 LLVMValueRef value = 0;
1097
1098 switch (decl->Semantic.Name) {
1099 case TGSI_SEMANTIC_INSTANCEID:
1100 value = LLVMGetParam(radeon_bld->main_fn,
1101 si_shader_ctx->param_instance_id);
1102 break;
1103
1104 case TGSI_SEMANTIC_VERTEXID:
1105 value = LLVMBuildAdd(gallivm->builder,
1106 LLVMGetParam(radeon_bld->main_fn,
1107 si_shader_ctx->param_vertex_id),
1108 LLVMGetParam(radeon_bld->main_fn,
1109 SI_PARAM_BASE_VERTEX), "");
1110 break;
1111
1112 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1113 value = LLVMGetParam(radeon_bld->main_fn,
1114 si_shader_ctx->param_vertex_id);
1115 break;
1116
1117 case TGSI_SEMANTIC_BASEVERTEX:
1118 value = LLVMGetParam(radeon_bld->main_fn,
1119 SI_PARAM_BASE_VERTEX);
1120 break;
1121
1122 case TGSI_SEMANTIC_INVOCATIONID:
1123 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1124 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1125 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1126 value = LLVMGetParam(radeon_bld->main_fn,
1127 SI_PARAM_GS_INSTANCE_ID);
1128 else
1129 assert(!"INVOCATIONID not implemented");
1130 break;
1131
1132 case TGSI_SEMANTIC_SAMPLEID:
1133 value = get_sample_id(radeon_bld);
1134 break;
1135
1136 case TGSI_SEMANTIC_SAMPLEPOS:
1137 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1138 break;
1139
1140 case TGSI_SEMANTIC_SAMPLEMASK:
1141 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1142 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1143 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1144 value = uint_bld->one;
1145 else
1146 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1147 break;
1148
1149 case TGSI_SEMANTIC_TESSCOORD:
1150 {
1151 LLVMValueRef coord[4] = {
1152 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1153 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1154 bld->zero,
1155 bld->zero
1156 };
1157
1158 /* For triangles, the vector should be (u, v, 1-u-v). */
1159 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1160 PIPE_PRIM_TRIANGLES)
1161 coord[2] = lp_build_sub(bld, bld->one,
1162 lp_build_add(bld, coord[0], coord[1]));
1163
1164 value = lp_build_gather_values(gallivm, coord, 4);
1165 break;
1166 }
1167
1168 case TGSI_SEMANTIC_VERTICESIN:
1169 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1170 break;
1171
1172 case TGSI_SEMANTIC_TESSINNER:
1173 case TGSI_SEMANTIC_TESSOUTER:
1174 {
1175 LLVMValueRef dw_addr;
1176 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1177
1178 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1179 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1180 lp_build_const_int32(gallivm, param * 4), "");
1181
1182 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1183 ~0, dw_addr);
1184 break;
1185 }
1186
1187 case TGSI_SEMANTIC_PRIMID:
1188 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1189 break;
1190
1191 default:
1192 assert(!"unknown system value");
1193 return;
1194 }
1195
1196 radeon_bld->system_values[index] = value;
1197 }
1198
1199 static LLVMValueRef fetch_constant(
1200 struct lp_build_tgsi_context * bld_base,
1201 const struct tgsi_full_src_register *reg,
1202 enum tgsi_opcode_type type,
1203 unsigned swizzle)
1204 {
1205 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1206 struct lp_build_context * base = &bld_base->base;
1207 const struct tgsi_ind_register *ireg = &reg->Indirect;
1208 unsigned buf, idx;
1209
1210 LLVMValueRef addr, bufp;
1211 LLVMValueRef result;
1212
1213 if (swizzle == LP_CHAN_ALL) {
1214 unsigned chan;
1215 LLVMValueRef values[4];
1216 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1217 values[chan] = fetch_constant(bld_base, reg, type, chan);
1218
1219 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1220 }
1221
1222 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1223 idx = reg->Register.Index * 4 + swizzle;
1224
1225 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1226 if (type != TGSI_TYPE_DOUBLE)
1227 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1228 else {
1229 return radeon_llvm_emit_fetch_double(bld_base,
1230 si_shader_ctx->constants[buf][idx],
1231 si_shader_ctx->constants[buf][idx + 1]);
1232 }
1233 }
1234
1235 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1236 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1237 LLVMValueRef index;
1238 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1239 reg->Dimension.Index);
1240 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1241 } else
1242 bufp = si_shader_ctx->const_buffers[buf];
1243
1244 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1245 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1246 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1247 addr = lp_build_add(&bld_base->uint_bld, addr,
1248 lp_build_const_int32(base->gallivm, idx * 4));
1249
1250 result = buffer_load_const(base->gallivm->builder, bufp,
1251 addr, bld_base->base.elem_type);
1252
1253 if (type != TGSI_TYPE_DOUBLE)
1254 result = bitcast(bld_base, type, result);
1255 else {
1256 LLVMValueRef addr2, result2;
1257 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1258 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1259 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1260 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1261 lp_build_const_int32(base->gallivm, idx * 4));
1262
1263 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1264 addr2, bld_base->base.elem_type);
1265
1266 result = radeon_llvm_emit_fetch_double(bld_base,
1267 result, result2);
1268 }
1269 return result;
1270 }
1271
1272 /* Initialize arguments for the shader export intrinsic */
1273 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1274 LLVMValueRef *values,
1275 unsigned target,
1276 LLVMValueRef *args)
1277 {
1278 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1279 struct lp_build_context *uint =
1280 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1281 struct lp_build_context *base = &bld_base->base;
1282 unsigned compressed = 0;
1283 unsigned chan;
1284
1285 /* XXX: This controls which components of the output
1286 * registers actually get exported. (e.g bit 0 means export
1287 * X component, bit 1 means export Y component, etc.) I'm
1288 * hard coding this to 0xf for now. In the future, we might
1289 * want to do something else.
1290 */
1291 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1292
1293 /* Specify whether the EXEC mask represents the valid mask */
1294 args[1] = uint->zero;
1295
1296 /* Specify whether this is the last export */
1297 args[2] = uint->zero;
1298
1299 /* Specify the target we are exporting */
1300 args[3] = lp_build_const_int32(base->gallivm, target);
1301
1302 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1303 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1304
1305 if (cbuf >= 0 && cbuf < 8) {
1306 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1307
1308 if (compressed)
1309 si_shader_ctx->shader->spi_shader_col_format |=
1310 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1311 else
1312 si_shader_ctx->shader->spi_shader_col_format |=
1313 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1314
1315 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1316 }
1317 }
1318
1319 /* Set COMPR flag */
1320 args[4] = compressed ? uint->one : uint->zero;
1321
1322 if (compressed) {
1323 /* Pixel shader needs to pack output values before export */
1324 for (chan = 0; chan < 2; chan++) {
1325 LLVMValueRef pack_args[2] = {
1326 values[2 * chan],
1327 values[2 * chan + 1]
1328 };
1329 LLVMValueRef packed;
1330
1331 packed = lp_build_intrinsic(base->gallivm->builder,
1332 "llvm.SI.packf16",
1333 LLVMInt32TypeInContext(base->gallivm->context),
1334 pack_args, 2,
1335 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1336 args[chan + 7] = args[chan + 5] =
1337 LLVMBuildBitCast(base->gallivm->builder,
1338 packed,
1339 LLVMFloatTypeInContext(base->gallivm->context),
1340 "");
1341 }
1342 } else
1343 memcpy(&args[5], values, sizeof(values[0]) * 4);
1344 }
1345
1346 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1347 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1348 LLVMValueRef *out_ptr,
1349 unsigned target,
1350 LLVMValueRef *args)
1351 {
1352 struct gallivm_state *gallivm = bld_base->base.gallivm;
1353 LLVMValueRef values[4];
1354 int i;
1355
1356 for (i = 0; i < 4; i++)
1357 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1358
1359 si_llvm_init_export_args(bld_base, values, target, args);
1360 }
1361
1362 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1363 LLVMValueRef alpha_ptr)
1364 {
1365 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1366 struct gallivm_state *gallivm = bld_base->base.gallivm;
1367
1368 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1369 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1370 SI_PARAM_ALPHA_REF);
1371
1372 LLVMValueRef alpha_pass =
1373 lp_build_cmp(&bld_base->base,
1374 si_shader_ctx->shader->key.ps.alpha_func,
1375 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1376 alpha_ref);
1377 LLVMValueRef arg =
1378 lp_build_select(&bld_base->base,
1379 alpha_pass,
1380 lp_build_const_float(gallivm, 1.0f),
1381 lp_build_const_float(gallivm, -1.0f));
1382
1383 lp_build_intrinsic(gallivm->builder,
1384 "llvm.AMDGPU.kill",
1385 LLVMVoidTypeInContext(gallivm->context),
1386 &arg, 1, 0);
1387 } else {
1388 lp_build_intrinsic(gallivm->builder,
1389 "llvm.AMDGPU.kilp",
1390 LLVMVoidTypeInContext(gallivm->context),
1391 NULL, 0, 0);
1392 }
1393
1394 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1395 }
1396
1397 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1398 LLVMValueRef alpha_ptr)
1399 {
1400 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1401 struct gallivm_state *gallivm = bld_base->base.gallivm;
1402 LLVMValueRef coverage, alpha;
1403
1404 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1405 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1406 SI_PARAM_SAMPLE_COVERAGE);
1407 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1408
1409 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1410 bld_base->int_bld.elem_type,
1411 &coverage, 1, LLVMReadNoneAttribute);
1412
1413 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1414 bld_base->base.elem_type, "");
1415
1416 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1417 lp_build_const_float(gallivm,
1418 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1419
1420 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1421 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1422 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1423 }
1424
1425 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1426 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1427 {
1428 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1429 struct lp_build_context *base = &bld_base->base;
1430 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1431 unsigned reg_index;
1432 unsigned chan;
1433 unsigned const_chan;
1434 LLVMValueRef base_elt;
1435 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1436 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1437 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1438
1439 for (reg_index = 0; reg_index < 2; reg_index ++) {
1440 LLVMValueRef *args = pos[2 + reg_index];
1441
1442 args[5] =
1443 args[6] =
1444 args[7] =
1445 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1446
1447 /* Compute dot products of position and user clip plane vectors */
1448 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1449 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1450 args[1] = lp_build_const_int32(base->gallivm,
1451 ((reg_index * 4 + chan) * 4 +
1452 const_chan) * 4);
1453 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1454 args[1], base->elem_type);
1455 args[5 + chan] =
1456 lp_build_add(base, args[5 + chan],
1457 lp_build_mul(base, base_elt,
1458 out_elts[const_chan]));
1459 }
1460 }
1461
1462 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1463 args[1] = uint->zero;
1464 args[2] = uint->zero;
1465 args[3] = lp_build_const_int32(base->gallivm,
1466 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1467 args[4] = uint->zero;
1468 }
1469 }
1470
1471 static void si_dump_streamout(struct pipe_stream_output_info *so)
1472 {
1473 unsigned i;
1474
1475 if (so->num_outputs)
1476 fprintf(stderr, "STREAMOUT\n");
1477
1478 for (i = 0; i < so->num_outputs; i++) {
1479 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1480 so->output[i].start_component;
1481 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1482 i, so->output[i].output_buffer,
1483 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1484 so->output[i].register_index,
1485 mask & 1 ? "x" : "",
1486 mask & 2 ? "y" : "",
1487 mask & 4 ? "z" : "",
1488 mask & 8 ? "w" : "");
1489 }
1490 }
1491
1492 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1493 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1494 * or v4i32 (num_channels=3,4). */
1495 static void build_tbuffer_store(struct si_shader_context *shader,
1496 LLVMValueRef rsrc,
1497 LLVMValueRef vdata,
1498 unsigned num_channels,
1499 LLVMValueRef vaddr,
1500 LLVMValueRef soffset,
1501 unsigned inst_offset,
1502 unsigned dfmt,
1503 unsigned nfmt,
1504 unsigned offen,
1505 unsigned idxen,
1506 unsigned glc,
1507 unsigned slc,
1508 unsigned tfe)
1509 {
1510 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1511 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1512 LLVMValueRef args[] = {
1513 rsrc,
1514 vdata,
1515 LLVMConstInt(i32, num_channels, 0),
1516 vaddr,
1517 soffset,
1518 LLVMConstInt(i32, inst_offset, 0),
1519 LLVMConstInt(i32, dfmt, 0),
1520 LLVMConstInt(i32, nfmt, 0),
1521 LLVMConstInt(i32, offen, 0),
1522 LLVMConstInt(i32, idxen, 0),
1523 LLVMConstInt(i32, glc, 0),
1524 LLVMConstInt(i32, slc, 0),
1525 LLVMConstInt(i32, tfe, 0)
1526 };
1527
1528 /* The instruction offset field has 12 bits */
1529 assert(offen || inst_offset < (1 << 12));
1530
1531 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1532 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1533 const char *types[] = {"i32", "v2i32", "v4i32"};
1534 char name[256];
1535 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1536
1537 lp_build_intrinsic(gallivm->builder, name,
1538 LLVMVoidTypeInContext(gallivm->context),
1539 args, Elements(args), 0);
1540 }
1541
1542 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1543 LLVMValueRef rsrc,
1544 LLVMValueRef vdata,
1545 unsigned num_channels,
1546 LLVMValueRef vaddr,
1547 LLVMValueRef soffset,
1548 unsigned inst_offset)
1549 {
1550 static unsigned dfmt[] = {
1551 V_008F0C_BUF_DATA_FORMAT_32,
1552 V_008F0C_BUF_DATA_FORMAT_32_32,
1553 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1554 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1555 };
1556 assert(num_channels >= 1 && num_channels <= 4);
1557
1558 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1559 inst_offset, dfmt[num_channels-1],
1560 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1561 }
1562
1563 /* On SI, the vertex shader is responsible for writing streamout data
1564 * to buffers. */
1565 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1566 struct si_shader_output_values *outputs,
1567 unsigned noutput)
1568 {
1569 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1570 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1571 LLVMBuilderRef builder = gallivm->builder;
1572 int i, j;
1573 struct lp_build_if_state if_ctx;
1574
1575 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1576
1577 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1578 LLVMValueRef so_vtx_count =
1579 unpack_param(shader, shader->param_streamout_config, 16, 7);
1580
1581 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1582 NULL, 0, LLVMReadNoneAttribute);
1583
1584 /* can_emit = tid < so_vtx_count; */
1585 LLVMValueRef can_emit =
1586 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1587
1588 LLVMValueRef stream_id =
1589 unpack_param(shader, shader->param_streamout_config, 24, 2);
1590
1591 /* Emit the streamout code conditionally. This actually avoids
1592 * out-of-bounds buffer access. The hw tells us via the SGPR
1593 * (so_vtx_count) which threads are allowed to emit streamout data. */
1594 lp_build_if(&if_ctx, gallivm, can_emit);
1595 {
1596 /* The buffer offset is computed as follows:
1597 * ByteOffset = streamout_offset[buffer_id]*4 +
1598 * (streamout_write_index + thread_id)*stride[buffer_id] +
1599 * attrib_offset
1600 */
1601
1602 LLVMValueRef so_write_index =
1603 LLVMGetParam(shader->radeon_bld.main_fn,
1604 shader->param_streamout_write_index);
1605
1606 /* Compute (streamout_write_index + thread_id). */
1607 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1608
1609 /* Compute the write offset for each enabled buffer. */
1610 LLVMValueRef so_write_offset[4] = {};
1611 for (i = 0; i < 4; i++) {
1612 if (!so->stride[i])
1613 continue;
1614
1615 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1616 shader->param_streamout_offset[i]);
1617 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1618
1619 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1620 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1621 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1622 }
1623
1624 /* Write streamout data. */
1625 for (i = 0; i < so->num_outputs; i++) {
1626 unsigned buf_idx = so->output[i].output_buffer;
1627 unsigned reg = so->output[i].register_index;
1628 unsigned start = so->output[i].start_component;
1629 unsigned num_comps = so->output[i].num_components;
1630 unsigned stream = so->output[i].stream;
1631 LLVMValueRef out[4];
1632 struct lp_build_if_state if_ctx_stream;
1633
1634 assert(num_comps && num_comps <= 4);
1635 if (!num_comps || num_comps > 4)
1636 continue;
1637
1638 if (reg >= noutput)
1639 continue;
1640
1641 /* Load the output as int. */
1642 for (j = 0; j < num_comps; j++) {
1643 out[j] = LLVMBuildBitCast(builder,
1644 outputs[reg].values[start+j],
1645 i32, "");
1646 }
1647
1648 /* Pack the output. */
1649 LLVMValueRef vdata = NULL;
1650
1651 switch (num_comps) {
1652 case 1: /* as i32 */
1653 vdata = out[0];
1654 break;
1655 case 2: /* as v2i32 */
1656 case 3: /* as v4i32 (aligned to 4) */
1657 case 4: /* as v4i32 */
1658 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1659 for (j = 0; j < num_comps; j++) {
1660 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1661 LLVMConstInt(i32, j, 0), "");
1662 }
1663 break;
1664 }
1665
1666 LLVMValueRef can_emit_stream =
1667 LLVMBuildICmp(builder, LLVMIntEQ,
1668 stream_id,
1669 lp_build_const_int32(gallivm, stream), "");
1670
1671 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1672 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1673 vdata, num_comps,
1674 so_write_offset[buf_idx],
1675 LLVMConstInt(i32, 0, 0),
1676 so->output[i].dst_offset*4);
1677 lp_build_endif(&if_ctx_stream);
1678 }
1679 }
1680 lp_build_endif(&if_ctx);
1681 }
1682
1683
1684 /* Generate export instructions for hardware VS shader stage */
1685 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1686 struct si_shader_output_values *outputs,
1687 unsigned noutput)
1688 {
1689 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1690 struct si_shader * shader = si_shader_ctx->shader;
1691 struct lp_build_context * base = &bld_base->base;
1692 struct lp_build_context * uint =
1693 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1694 LLVMValueRef args[9];
1695 LLVMValueRef pos_args[4][9] = { { 0 } };
1696 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1697 unsigned semantic_name, semantic_index;
1698 unsigned target;
1699 unsigned param_count = 0;
1700 unsigned pos_idx;
1701 int i;
1702
1703 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1704 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1705 }
1706
1707 for (i = 0; i < noutput; i++) {
1708 semantic_name = outputs[i].name;
1709 semantic_index = outputs[i].sid;
1710
1711 handle_semantic:
1712 /* Select the correct target */
1713 switch(semantic_name) {
1714 case TGSI_SEMANTIC_PSIZE:
1715 psize_value = outputs[i].values[0];
1716 continue;
1717 case TGSI_SEMANTIC_EDGEFLAG:
1718 edgeflag_value = outputs[i].values[0];
1719 continue;
1720 case TGSI_SEMANTIC_LAYER:
1721 layer_value = outputs[i].values[0];
1722 semantic_name = TGSI_SEMANTIC_GENERIC;
1723 goto handle_semantic;
1724 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1725 viewport_index_value = outputs[i].values[0];
1726 semantic_name = TGSI_SEMANTIC_GENERIC;
1727 goto handle_semantic;
1728 case TGSI_SEMANTIC_POSITION:
1729 target = V_008DFC_SQ_EXP_POS;
1730 break;
1731 case TGSI_SEMANTIC_COLOR:
1732 case TGSI_SEMANTIC_BCOLOR:
1733 target = V_008DFC_SQ_EXP_PARAM + param_count;
1734 shader->vs_output_param_offset[i] = param_count;
1735 param_count++;
1736 break;
1737 case TGSI_SEMANTIC_CLIPDIST:
1738 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1739 break;
1740 case TGSI_SEMANTIC_CLIPVERTEX:
1741 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1742 continue;
1743 case TGSI_SEMANTIC_PRIMID:
1744 case TGSI_SEMANTIC_FOG:
1745 case TGSI_SEMANTIC_TEXCOORD:
1746 case TGSI_SEMANTIC_GENERIC:
1747 target = V_008DFC_SQ_EXP_PARAM + param_count;
1748 shader->vs_output_param_offset[i] = param_count;
1749 param_count++;
1750 break;
1751 default:
1752 target = 0;
1753 fprintf(stderr,
1754 "Warning: SI unhandled vs output type:%d\n",
1755 semantic_name);
1756 }
1757
1758 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1759
1760 if (target >= V_008DFC_SQ_EXP_POS &&
1761 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1762 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1763 args, sizeof(args));
1764 } else {
1765 lp_build_intrinsic(base->gallivm->builder,
1766 "llvm.SI.export",
1767 LLVMVoidTypeInContext(base->gallivm->context),
1768 args, 9, 0);
1769 }
1770
1771 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1772 semantic_name = TGSI_SEMANTIC_GENERIC;
1773 goto handle_semantic;
1774 }
1775 }
1776
1777 shader->nr_param_exports = param_count;
1778
1779 /* We need to add the position output manually if it's missing. */
1780 if (!pos_args[0][0]) {
1781 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1782 pos_args[0][1] = uint->zero; /* EXEC mask */
1783 pos_args[0][2] = uint->zero; /* last export? */
1784 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1785 pos_args[0][4] = uint->zero; /* COMPR flag */
1786 pos_args[0][5] = base->zero; /* X */
1787 pos_args[0][6] = base->zero; /* Y */
1788 pos_args[0][7] = base->zero; /* Z */
1789 pos_args[0][8] = base->one; /* W */
1790 }
1791
1792 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1793 if (shader->selector->info.writes_psize ||
1794 shader->selector->info.writes_edgeflag ||
1795 shader->selector->info.writes_viewport_index ||
1796 shader->selector->info.writes_layer) {
1797 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1798 shader->selector->info.writes_psize |
1799 (shader->selector->info.writes_edgeflag << 1) |
1800 (shader->selector->info.writes_layer << 2) |
1801 (shader->selector->info.writes_viewport_index << 3));
1802 pos_args[1][1] = uint->zero; /* EXEC mask */
1803 pos_args[1][2] = uint->zero; /* last export? */
1804 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1805 pos_args[1][4] = uint->zero; /* COMPR flag */
1806 pos_args[1][5] = base->zero; /* X */
1807 pos_args[1][6] = base->zero; /* Y */
1808 pos_args[1][7] = base->zero; /* Z */
1809 pos_args[1][8] = base->zero; /* W */
1810
1811 if (shader->selector->info.writes_psize)
1812 pos_args[1][5] = psize_value;
1813
1814 if (shader->selector->info.writes_edgeflag) {
1815 /* The output is a float, but the hw expects an integer
1816 * with the first bit containing the edge flag. */
1817 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1818 edgeflag_value,
1819 bld_base->uint_bld.elem_type, "");
1820 edgeflag_value = lp_build_min(&bld_base->int_bld,
1821 edgeflag_value,
1822 bld_base->int_bld.one);
1823
1824 /* The LLVM intrinsic expects a float. */
1825 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1826 edgeflag_value,
1827 base->elem_type, "");
1828 }
1829
1830 if (shader->selector->info.writes_layer)
1831 pos_args[1][7] = layer_value;
1832
1833 if (shader->selector->info.writes_viewport_index)
1834 pos_args[1][8] = viewport_index_value;
1835 }
1836
1837 for (i = 0; i < 4; i++)
1838 if (pos_args[i][0])
1839 shader->nr_pos_exports++;
1840
1841 pos_idx = 0;
1842 for (i = 0; i < 4; i++) {
1843 if (!pos_args[i][0])
1844 continue;
1845
1846 /* Specify the target we are exporting */
1847 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1848
1849 if (pos_idx == shader->nr_pos_exports)
1850 /* Specify that this is the last export */
1851 pos_args[i][2] = uint->one;
1852
1853 lp_build_intrinsic(base->gallivm->builder,
1854 "llvm.SI.export",
1855 LLVMVoidTypeInContext(base->gallivm->context),
1856 pos_args[i], 9, 0);
1857 }
1858 }
1859
1860 /* This only writes the tessellation factor levels. */
1861 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1862 {
1863 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1864 struct gallivm_state *gallivm = bld_base->base.gallivm;
1865 struct si_shader *shader = si_shader_ctx->shader;
1866 unsigned tess_inner_index, tess_outer_index;
1867 LLVMValueRef lds_base, lds_inner, lds_outer;
1868 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1869 LLVMValueRef out[6], vec0, vec1, invocation_id;
1870 unsigned stride, outer_comps, inner_comps, i;
1871 struct lp_build_if_state if_ctx;
1872
1873 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1874
1875 /* Do this only for invocation 0, because the tess levels are per-patch,
1876 * not per-vertex.
1877 *
1878 * This can't jump, because invocation 0 executes this. It should
1879 * at least mask out the loads and stores for other invocations.
1880 */
1881 lp_build_if(&if_ctx, gallivm,
1882 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1883 invocation_id, bld_base->uint_bld.zero, ""));
1884
1885 /* Determine the layout of one tess factor element in the buffer. */
1886 switch (shader->key.tcs.prim_mode) {
1887 case PIPE_PRIM_LINES:
1888 stride = 2; /* 2 dwords, 1 vec2 store */
1889 outer_comps = 2;
1890 inner_comps = 0;
1891 break;
1892 case PIPE_PRIM_TRIANGLES:
1893 stride = 4; /* 4 dwords, 1 vec4 store */
1894 outer_comps = 3;
1895 inner_comps = 1;
1896 break;
1897 case PIPE_PRIM_QUADS:
1898 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1899 outer_comps = 4;
1900 inner_comps = 2;
1901 break;
1902 default:
1903 assert(0);
1904 return;
1905 }
1906
1907 /* Load tess_inner and tess_outer from LDS.
1908 * Any invocation can write them, so we can't get them from a temporary.
1909 */
1910 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1911 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1912
1913 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1914 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1915 lp_build_const_int32(gallivm,
1916 tess_inner_index * 4), "");
1917 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1918 lp_build_const_int32(gallivm,
1919 tess_outer_index * 4), "");
1920
1921 for (i = 0; i < outer_comps; i++)
1922 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1923 for (i = 0; i < inner_comps; i++)
1924 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1925
1926 /* Convert the outputs to vectors for stores. */
1927 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1928 vec1 = NULL;
1929
1930 if (stride > 4)
1931 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1932
1933 /* Get the buffer. */
1934 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1935 SI_PARAM_RW_BUFFERS);
1936 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1937 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1938
1939 /* Get the offset. */
1940 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1941 SI_PARAM_TESS_FACTOR_OFFSET);
1942 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1943 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1944 lp_build_const_int32(gallivm, 4 * stride), "");
1945
1946 /* Store the outputs. */
1947 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1948 MIN2(stride, 4), byteoffset, tf_base, 0);
1949 if (vec1)
1950 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1951 stride - 4, byteoffset, tf_base, 16);
1952 lp_build_endif(&if_ctx);
1953 }
1954
1955 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1956 {
1957 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1958 struct si_shader *shader = si_shader_ctx->shader;
1959 struct tgsi_shader_info *info = &shader->selector->info;
1960 struct gallivm_state *gallivm = bld_base->base.gallivm;
1961 unsigned i, chan;
1962 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1963 si_shader_ctx->param_rel_auto_id);
1964 LLVMValueRef vertex_dw_stride =
1965 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1966 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1967 vertex_dw_stride, "");
1968
1969 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1970 * its inputs from it. */
1971 for (i = 0; i < info->num_outputs; i++) {
1972 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1973 unsigned name = info->output_semantic_name[i];
1974 unsigned index = info->output_semantic_index[i];
1975 int param = si_shader_io_get_unique_index(name, index);
1976 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1977 lp_build_const_int32(gallivm, param * 4), "");
1978
1979 for (chan = 0; chan < 4; chan++) {
1980 lds_store(bld_base, chan, dw_addr,
1981 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1982 }
1983 }
1984 }
1985
1986 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1987 {
1988 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1989 struct gallivm_state *gallivm = bld_base->base.gallivm;
1990 struct si_shader *es = si_shader_ctx->shader;
1991 struct tgsi_shader_info *info = &es->selector->info;
1992 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1993 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1994 si_shader_ctx->param_es2gs_offset);
1995 unsigned chan;
1996 int i;
1997
1998 for (i = 0; i < info->num_outputs; i++) {
1999 LLVMValueRef *out_ptr =
2000 si_shader_ctx->radeon_bld.soa.outputs[i];
2001 int param_index;
2002
2003 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2004 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2005 continue;
2006
2007 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2008 info->output_semantic_index[i]);
2009
2010 for (chan = 0; chan < 4; chan++) {
2011 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2012 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2013
2014 build_tbuffer_store(si_shader_ctx,
2015 si_shader_ctx->esgs_ring,
2016 out_val, 1,
2017 LLVMGetUndef(i32), soffset,
2018 (4 * param_index + chan) * 4,
2019 V_008F0C_BUF_DATA_FORMAT_32,
2020 V_008F0C_BUF_NUM_FORMAT_UINT,
2021 0, 0, 1, 1, 0);
2022 }
2023 }
2024 }
2025
2026 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2027 {
2028 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2029 struct gallivm_state *gallivm = bld_base->base.gallivm;
2030 LLVMValueRef args[2];
2031
2032 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2033 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2034 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2035 LLVMVoidTypeInContext(gallivm->context), args, 2,
2036 LLVMNoUnwindAttribute);
2037 }
2038
2039 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2040 {
2041 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2042 struct gallivm_state *gallivm = bld_base->base.gallivm;
2043 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2044 struct si_shader_output_values *outputs = NULL;
2045 int i,j;
2046
2047 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2048
2049 /* Vertex color clamping.
2050 *
2051 * This uses a state constant loaded in a user data SGPR and
2052 * an IF statement is added that clamps all colors if the constant
2053 * is true.
2054 */
2055 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2056 !si_shader_ctx->shader->is_gs_copy_shader) {
2057 struct lp_build_if_state if_ctx;
2058 LLVMValueRef cond = NULL;
2059 LLVMValueRef addr, val;
2060
2061 for (i = 0; i < info->num_outputs; i++) {
2062 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2063 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2064 continue;
2065
2066 /* We've found a color. */
2067 if (!cond) {
2068 /* The state is in the first bit of the user SGPR. */
2069 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2070 SI_PARAM_VS_STATE_BITS);
2071 cond = LLVMBuildTrunc(gallivm->builder, cond,
2072 LLVMInt1TypeInContext(gallivm->context), "");
2073 lp_build_if(&if_ctx, gallivm, cond);
2074 }
2075
2076 for (j = 0; j < 4; j++) {
2077 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2078 val = LLVMBuildLoad(gallivm->builder, addr, "");
2079 val = radeon_llvm_saturate(bld_base, val);
2080 LLVMBuildStore(gallivm->builder, val, addr);
2081 }
2082 }
2083
2084 if (cond)
2085 lp_build_endif(&if_ctx);
2086 }
2087
2088 for (i = 0; i < info->num_outputs; i++) {
2089 outputs[i].name = info->output_semantic_name[i];
2090 outputs[i].sid = info->output_semantic_index[i];
2091
2092 for (j = 0; j < 4; j++)
2093 outputs[i].values[j] =
2094 LLVMBuildLoad(gallivm->builder,
2095 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2096 "");
2097 }
2098
2099 /* Export PrimitiveID when PS needs it. */
2100 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2101 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2102 outputs[i].sid = 0;
2103 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2104 get_primitive_id(bld_base, 0));
2105 outputs[i].values[1] = bld_base->base.undef;
2106 outputs[i].values[2] = bld_base->base.undef;
2107 outputs[i].values[3] = bld_base->base.undef;
2108 i++;
2109 }
2110
2111 si_llvm_export_vs(bld_base, outputs, i);
2112 FREE(outputs);
2113 }
2114
2115 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2116 {
2117 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2118 struct si_shader * shader = si_shader_ctx->shader;
2119 struct lp_build_context * base = &bld_base->base;
2120 struct lp_build_context * uint = &bld_base->uint_bld;
2121 struct tgsi_shader_info *info = &shader->selector->info;
2122 LLVMBuilderRef builder = base->gallivm->builder;
2123 LLVMValueRef args[9];
2124 LLVMValueRef last_args[9] = { 0 };
2125 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2126 int i;
2127
2128 for (i = 0; i < info->num_outputs; i++) {
2129 unsigned semantic_name = info->output_semantic_name[i];
2130 unsigned semantic_index = info->output_semantic_index[i];
2131 unsigned target;
2132 LLVMValueRef alpha_ptr;
2133
2134 /* Select the correct target */
2135 switch (semantic_name) {
2136 case TGSI_SEMANTIC_POSITION:
2137 depth_index = i;
2138 continue;
2139 case TGSI_SEMANTIC_STENCIL:
2140 stencil_index = i;
2141 continue;
2142 case TGSI_SEMANTIC_SAMPLEMASK:
2143 samplemask_index = i;
2144 continue;
2145 case TGSI_SEMANTIC_COLOR:
2146 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2147 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2148
2149 if (si_shader_ctx->shader->key.ps.clamp_color) {
2150 for (int j = 0; j < 4; j++) {
2151 LLVMValueRef ptr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2152 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2153
2154 result = radeon_llvm_saturate(bld_base, result);
2155 LLVMBuildStore(builder, result, ptr);
2156 }
2157 }
2158
2159 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2160 LLVMBuildStore(base->gallivm->builder,
2161 base->one, alpha_ptr);
2162
2163 if (semantic_index == 0 &&
2164 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2165 si_alpha_test(bld_base, alpha_ptr);
2166
2167 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2168 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2169
2170 break;
2171 default:
2172 target = 0;
2173 fprintf(stderr,
2174 "Warning: SI unhandled fs output type:%d\n",
2175 semantic_name);
2176 }
2177
2178 si_llvm_init_export_args_load(bld_base,
2179 si_shader_ctx->radeon_bld.soa.outputs[i],
2180 target, args);
2181
2182 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2183 /* If there is an export instruction waiting to be emitted, do so now. */
2184 if (last_args[0]) {
2185 lp_build_intrinsic(base->gallivm->builder,
2186 "llvm.SI.export",
2187 LLVMVoidTypeInContext(base->gallivm->context),
2188 last_args, 9, 0);
2189 }
2190
2191 /* This instruction will be emitted at the end of the shader. */
2192 memcpy(last_args, args, sizeof(args));
2193
2194 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2195 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2196 semantic_index == 0 &&
2197 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2198 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2199 si_llvm_init_export_args_load(bld_base,
2200 si_shader_ctx->radeon_bld.soa.outputs[i],
2201 V_008DFC_SQ_EXP_MRT + c, args);
2202 lp_build_intrinsic(base->gallivm->builder,
2203 "llvm.SI.export",
2204 LLVMVoidTypeInContext(base->gallivm->context),
2205 args, 9, 0);
2206 }
2207 }
2208 } else {
2209 lp_build_intrinsic(base->gallivm->builder,
2210 "llvm.SI.export",
2211 LLVMVoidTypeInContext(base->gallivm->context),
2212 args, 9, 0);
2213 }
2214 }
2215
2216 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2217 LLVMValueRef out_ptr;
2218 unsigned mask = 0;
2219
2220 /* Specify the target we are exporting */
2221 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2222
2223 args[5] = base->zero; /* R, depth */
2224 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2225 args[7] = base->zero; /* B, sample mask */
2226 args[8] = base->zero; /* A, alpha to mask */
2227
2228 if (depth_index >= 0) {
2229 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2230 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2231 mask |= 0x1;
2232 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2233 }
2234
2235 if (stencil_index >= 0) {
2236 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2237 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2238 mask |= 0x2;
2239 si_shader_ctx->shader->db_shader_control |=
2240 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2241 }
2242
2243 if (samplemask_index >= 0) {
2244 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2245 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2246 mask |= 0x4;
2247 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2248 }
2249
2250 /* SI (except OLAND) has a bug that it only looks
2251 * at the X writemask component. */
2252 if (si_shader_ctx->screen->b.chip_class == SI &&
2253 si_shader_ctx->screen->b.family != CHIP_OLAND)
2254 mask |= 0x1;
2255
2256 if (samplemask_index >= 0)
2257 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2258 else if (stencil_index >= 0)
2259 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2260 else
2261 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2262
2263 /* Specify which components to enable */
2264 args[0] = lp_build_const_int32(base->gallivm, mask);
2265
2266 args[1] =
2267 args[2] =
2268 args[4] = uint->zero;
2269
2270 if (last_args[0])
2271 lp_build_intrinsic(base->gallivm->builder,
2272 "llvm.SI.export",
2273 LLVMVoidTypeInContext(base->gallivm->context),
2274 args, 9, 0);
2275 else
2276 memcpy(last_args, args, sizeof(args));
2277 }
2278
2279 if (!last_args[0]) {
2280 /* Specify which components to enable */
2281 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2282
2283 /* Specify the target we are exporting */
2284 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2285
2286 /* Set COMPR flag to zero to export data as 32-bit */
2287 last_args[4] = uint->zero;
2288
2289 /* dummy bits */
2290 last_args[5]= uint->zero;
2291 last_args[6]= uint->zero;
2292 last_args[7]= uint->zero;
2293 last_args[8]= uint->zero;
2294 }
2295
2296 /* Specify whether the EXEC mask represents the valid mask */
2297 last_args[1] = uint->one;
2298
2299 /* Specify that this is the last export */
2300 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2301
2302 lp_build_intrinsic(base->gallivm->builder,
2303 "llvm.SI.export",
2304 LLVMVoidTypeInContext(base->gallivm->context),
2305 last_args, 9, 0);
2306 }
2307
2308 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2309 struct lp_build_tgsi_context * bld_base,
2310 struct lp_build_emit_data * emit_data);
2311
2312 static bool tgsi_is_array_sampler(unsigned target)
2313 {
2314 return target == TGSI_TEXTURE_1D_ARRAY ||
2315 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2316 target == TGSI_TEXTURE_2D_ARRAY ||
2317 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2318 target == TGSI_TEXTURE_CUBE_ARRAY ||
2319 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2320 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2321 }
2322
2323 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2324 struct lp_build_emit_data *emit_data,
2325 unsigned opcode, unsigned target,
2326 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2327 LLVMValueRef *param, unsigned count,
2328 unsigned dmask)
2329 {
2330 unsigned num_args;
2331 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2332 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2333
2334 /* Pad to power of two vector */
2335 while (count < util_next_power_of_two(count))
2336 param[count++] = LLVMGetUndef(i32);
2337
2338 /* Texture coordinates. */
2339 if (count > 1)
2340 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2341 else
2342 emit_data->args[0] = param[0];
2343
2344 /* Resource. */
2345 emit_data->args[1] = res_ptr;
2346 num_args = 2;
2347
2348 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2349 emit_data->dst_type = LLVMVectorType(i32, 4);
2350 else {
2351 emit_data->dst_type = LLVMVectorType(
2352 LLVMFloatTypeInContext(gallivm->context), 4);
2353
2354 emit_data->args[num_args++] = samp_ptr;
2355 }
2356
2357 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2358 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2359 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2360 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2361 tgsi_is_array_sampler(target)); /* da */
2362 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2363 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2364 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2365 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2366
2367 emit_data->arg_count = num_args;
2368 }
2369
2370 static const struct lp_build_tgsi_action tex_action;
2371
2372 static void tex_fetch_ptrs(
2373 struct lp_build_tgsi_context * bld_base,
2374 struct lp_build_emit_data * emit_data,
2375 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2376 {
2377 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2378 struct gallivm_state *gallivm = bld_base->base.gallivm;
2379 const struct tgsi_full_instruction * inst = emit_data->inst;
2380 unsigned target = inst->Texture.Texture;
2381 unsigned sampler_src;
2382 unsigned sampler_index;
2383
2384 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2385 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2386
2387 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2388 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2389 LLVMValueRef ind_index;
2390
2391 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2392
2393 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2394 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2395
2396 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2397 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2398
2399 if (target == TGSI_TEXTURE_2D_MSAA ||
2400 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2401 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2402 lp_build_const_int32(gallivm,
2403 SI_FMASK_TEX_OFFSET), "");
2404 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2405 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2406 }
2407 } else {
2408 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2409 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2410 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2411 }
2412 }
2413
2414 static void tex_fetch_args(
2415 struct lp_build_tgsi_context * bld_base,
2416 struct lp_build_emit_data * emit_data)
2417 {
2418 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2419 struct gallivm_state *gallivm = bld_base->base.gallivm;
2420 LLVMBuilderRef builder = gallivm->builder;
2421 const struct tgsi_full_instruction * inst = emit_data->inst;
2422 unsigned opcode = inst->Instruction.Opcode;
2423 unsigned target = inst->Texture.Texture;
2424 LLVMValueRef coords[5], derivs[6];
2425 LLVMValueRef address[16];
2426 int ref_pos;
2427 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2428 unsigned count = 0;
2429 unsigned chan;
2430 unsigned num_deriv_channels = 0;
2431 bool has_offset = inst->Texture.NumOffsets > 0;
2432 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2433 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2434 unsigned dmask = 0xf;
2435
2436 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2437
2438 if (opcode == TGSI_OPCODE_TXQ) {
2439 if (target == TGSI_TEXTURE_BUFFER) {
2440 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2441
2442 /* Read the size from the buffer descriptor directly. */
2443 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2444 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2445 lp_build_const_int32(gallivm, 6), "");
2446
2447 if (si_shader_ctx->screen->b.chip_class >= VI) {
2448 /* On VI, the descriptor contains the size in bytes,
2449 * but TXQ must return the size in elements.
2450 * The stride is always non-zero for resources using TXQ.
2451 */
2452 LLVMValueRef stride =
2453 LLVMBuildExtractElement(builder, res,
2454 lp_build_const_int32(gallivm, 5), "");
2455 stride = LLVMBuildLShr(builder, stride,
2456 lp_build_const_int32(gallivm, 16), "");
2457 stride = LLVMBuildAnd(builder, stride,
2458 lp_build_const_int32(gallivm, 0x3FFF), "");
2459
2460 size = LLVMBuildUDiv(builder, size, stride, "");
2461 }
2462
2463 emit_data->args[0] = size;
2464 return;
2465 }
2466
2467 /* Textures - set the mip level. */
2468 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2469
2470 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2471 NULL, address, count, 0xf);
2472 return;
2473 }
2474
2475 if (target == TGSI_TEXTURE_BUFFER) {
2476 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2477 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2478 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2479 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2480
2481 /* Bitcast and truncate v8i32 to v16i8. */
2482 LLVMValueRef res = res_ptr;
2483 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2484 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2485 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2486
2487 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2488 emit_data->args[0] = res;
2489 emit_data->args[1] = bld_base->uint_bld.zero;
2490 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2491 emit_data->arg_count = 3;
2492 return;
2493 }
2494
2495 /* Fetch and project texture coordinates */
2496 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2497 for (chan = 0; chan < 3; chan++ ) {
2498 coords[chan] = lp_build_emit_fetch(bld_base,
2499 emit_data->inst, 0,
2500 chan);
2501 if (opcode == TGSI_OPCODE_TXP)
2502 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2503 TGSI_OPCODE_DIV,
2504 coords[chan],
2505 coords[3]);
2506 }
2507
2508 if (opcode == TGSI_OPCODE_TXP)
2509 coords[3] = bld_base->base.one;
2510
2511 /* Pack offsets. */
2512 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2513 /* The offsets are six-bit signed integers packed like this:
2514 * X=[5:0], Y=[13:8], and Z=[21:16].
2515 */
2516 LLVMValueRef offset[3], pack;
2517
2518 assert(inst->Texture.NumOffsets == 1);
2519
2520 for (chan = 0; chan < 3; chan++) {
2521 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2522 emit_data->inst, 0, chan);
2523 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2524 lp_build_const_int32(gallivm, 0x3f), "");
2525 if (chan)
2526 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2527 lp_build_const_int32(gallivm, chan*8), "");
2528 }
2529
2530 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2531 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2532 address[count++] = pack;
2533 }
2534
2535 /* Pack LOD bias value */
2536 if (opcode == TGSI_OPCODE_TXB)
2537 address[count++] = coords[3];
2538 if (opcode == TGSI_OPCODE_TXB2)
2539 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2540
2541 /* Pack depth comparison value */
2542 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2543 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2544 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2545 } else {
2546 assert(ref_pos >= 0);
2547 address[count++] = coords[ref_pos];
2548 }
2549 }
2550
2551 /* Pack user derivatives */
2552 if (opcode == TGSI_OPCODE_TXD) {
2553 int param, num_src_deriv_channels;
2554
2555 switch (target) {
2556 case TGSI_TEXTURE_3D:
2557 num_src_deriv_channels = 3;
2558 num_deriv_channels = 3;
2559 break;
2560 case TGSI_TEXTURE_2D:
2561 case TGSI_TEXTURE_SHADOW2D:
2562 case TGSI_TEXTURE_RECT:
2563 case TGSI_TEXTURE_SHADOWRECT:
2564 case TGSI_TEXTURE_2D_ARRAY:
2565 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2566 num_src_deriv_channels = 2;
2567 num_deriv_channels = 2;
2568 break;
2569 case TGSI_TEXTURE_CUBE:
2570 case TGSI_TEXTURE_SHADOWCUBE:
2571 case TGSI_TEXTURE_CUBE_ARRAY:
2572 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2573 /* Cube derivatives will be converted to 2D. */
2574 num_src_deriv_channels = 3;
2575 num_deriv_channels = 2;
2576 break;
2577 case TGSI_TEXTURE_1D:
2578 case TGSI_TEXTURE_SHADOW1D:
2579 case TGSI_TEXTURE_1D_ARRAY:
2580 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2581 num_src_deriv_channels = 1;
2582 num_deriv_channels = 1;
2583 break;
2584 default:
2585 unreachable("invalid target");
2586 }
2587
2588 for (param = 0; param < 2; param++)
2589 for (chan = 0; chan < num_src_deriv_channels; chan++)
2590 derivs[param * num_src_deriv_channels + chan] =
2591 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2592 }
2593
2594 if (target == TGSI_TEXTURE_CUBE ||
2595 target == TGSI_TEXTURE_CUBE_ARRAY ||
2596 target == TGSI_TEXTURE_SHADOWCUBE ||
2597 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2598 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2599
2600 if (opcode == TGSI_OPCODE_TXD)
2601 for (int i = 0; i < num_deriv_channels * 2; i++)
2602 address[count++] = derivs[i];
2603
2604 /* Pack texture coordinates */
2605 address[count++] = coords[0];
2606 if (num_coords > 1)
2607 address[count++] = coords[1];
2608 if (num_coords > 2)
2609 address[count++] = coords[2];
2610
2611 /* Pack LOD or sample index */
2612 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2613 address[count++] = coords[3];
2614 else if (opcode == TGSI_OPCODE_TXL2)
2615 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2616
2617 if (count > 16) {
2618 assert(!"Cannot handle more than 16 texture address parameters");
2619 count = 16;
2620 }
2621
2622 for (chan = 0; chan < count; chan++ ) {
2623 address[chan] = LLVMBuildBitCast(gallivm->builder,
2624 address[chan], i32, "");
2625 }
2626
2627 /* Adjust the sample index according to FMASK.
2628 *
2629 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2630 * which is the identity mapping. Each nibble says which physical sample
2631 * should be fetched to get that sample.
2632 *
2633 * For example, 0x11111100 means there are only 2 samples stored and
2634 * the second sample covers 3/4 of the pixel. When reading samples 0
2635 * and 1, return physical sample 0 (determined by the first two 0s
2636 * in FMASK), otherwise return physical sample 1.
2637 *
2638 * The sample index should be adjusted as follows:
2639 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2640 */
2641 if (target == TGSI_TEXTURE_2D_MSAA ||
2642 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2643 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2644 struct lp_build_emit_data txf_emit_data = *emit_data;
2645 LLVMValueRef txf_address[4];
2646 unsigned txf_count = count;
2647 struct tgsi_full_instruction inst = {};
2648
2649 memcpy(txf_address, address, sizeof(txf_address));
2650
2651 if (target == TGSI_TEXTURE_2D_MSAA) {
2652 txf_address[2] = bld_base->uint_bld.zero;
2653 }
2654 txf_address[3] = bld_base->uint_bld.zero;
2655
2656 /* Read FMASK using TXF. */
2657 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2658 inst.Texture.Texture = target;
2659 txf_emit_data.inst = &inst;
2660 txf_emit_data.chan = 0;
2661 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2662 target, fmask_ptr, NULL,
2663 txf_address, txf_count, 0xf);
2664 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2665
2666 /* Initialize some constants. */
2667 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2668 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2669
2670 /* Apply the formula. */
2671 LLVMValueRef fmask =
2672 LLVMBuildExtractElement(gallivm->builder,
2673 txf_emit_data.output[0],
2674 uint_bld->zero, "");
2675
2676 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2677
2678 LLVMValueRef sample_index4 =
2679 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2680
2681 LLVMValueRef shifted_fmask =
2682 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2683
2684 LLVMValueRef final_sample =
2685 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2686
2687 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2688 * resource descriptor is 0 (invalid),
2689 */
2690 LLVMValueRef fmask_desc =
2691 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2692 LLVMVectorType(uint_bld->elem_type, 8), "");
2693
2694 LLVMValueRef fmask_word1 =
2695 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2696 uint_bld->one, "");
2697
2698 LLVMValueRef word1_is_nonzero =
2699 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2700 fmask_word1, uint_bld->zero, "");
2701
2702 /* Replace the MSAA sample index. */
2703 address[sample_chan] =
2704 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2705 final_sample, address[sample_chan], "");
2706 }
2707
2708 if (opcode == TGSI_OPCODE_TXF) {
2709 /* add tex offsets */
2710 if (inst->Texture.NumOffsets) {
2711 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2712 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2713 const struct tgsi_texture_offset * off = inst->TexOffsets;
2714
2715 assert(inst->Texture.NumOffsets == 1);
2716
2717 switch (target) {
2718 case TGSI_TEXTURE_3D:
2719 address[2] = lp_build_add(uint_bld, address[2],
2720 bld->immediates[off->Index][off->SwizzleZ]);
2721 /* fall through */
2722 case TGSI_TEXTURE_2D:
2723 case TGSI_TEXTURE_SHADOW2D:
2724 case TGSI_TEXTURE_RECT:
2725 case TGSI_TEXTURE_SHADOWRECT:
2726 case TGSI_TEXTURE_2D_ARRAY:
2727 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2728 address[1] =
2729 lp_build_add(uint_bld, address[1],
2730 bld->immediates[off->Index][off->SwizzleY]);
2731 /* fall through */
2732 case TGSI_TEXTURE_1D:
2733 case TGSI_TEXTURE_SHADOW1D:
2734 case TGSI_TEXTURE_1D_ARRAY:
2735 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2736 address[0] =
2737 lp_build_add(uint_bld, address[0],
2738 bld->immediates[off->Index][off->SwizzleX]);
2739 break;
2740 /* texture offsets do not apply to other texture targets */
2741 }
2742 }
2743 }
2744
2745 if (opcode == TGSI_OPCODE_TG4) {
2746 unsigned gather_comp = 0;
2747
2748 /* DMASK was repurposed for GATHER4. 4 components are always
2749 * returned and DMASK works like a swizzle - it selects
2750 * the component to fetch. The only valid DMASK values are
2751 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2752 * (red,red,red,red) etc.) The ISA document doesn't mention
2753 * this.
2754 */
2755
2756 /* Get the component index from src1.x for Gather4. */
2757 if (!tgsi_is_shadow_target(target)) {
2758 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2759 LLVMValueRef comp_imm;
2760 struct tgsi_src_register src1 = inst->Src[1].Register;
2761
2762 assert(src1.File == TGSI_FILE_IMMEDIATE);
2763
2764 comp_imm = imms[src1.Index][src1.SwizzleX];
2765 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2766 gather_comp = CLAMP(gather_comp, 0, 3);
2767 }
2768
2769 dmask = 1 << gather_comp;
2770 }
2771
2772 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2773 samp_ptr, address, count, dmask);
2774 }
2775
2776 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2777 struct lp_build_tgsi_context * bld_base,
2778 struct lp_build_emit_data * emit_data)
2779 {
2780 struct lp_build_context * base = &bld_base->base;
2781 unsigned opcode = emit_data->inst->Instruction.Opcode;
2782 unsigned target = emit_data->inst->Texture.Texture;
2783 char intr_name[127];
2784 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2785 bool is_shadow = tgsi_is_shadow_target(target);
2786 char type[64];
2787 const char *name = "llvm.SI.image.sample";
2788 const char *infix = "";
2789
2790 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2791 /* Just return the buffer size. */
2792 emit_data->output[emit_data->chan] = emit_data->args[0];
2793 return;
2794 }
2795
2796 if (target == TGSI_TEXTURE_BUFFER) {
2797 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2798 base->gallivm->builder,
2799 "llvm.SI.vs.load.input", emit_data->dst_type,
2800 emit_data->args, emit_data->arg_count,
2801 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2802 return;
2803 }
2804
2805 switch (opcode) {
2806 case TGSI_OPCODE_TXF:
2807 name = target == TGSI_TEXTURE_2D_MSAA ||
2808 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2809 "llvm.SI.image.load" :
2810 "llvm.SI.image.load.mip";
2811 is_shadow = false;
2812 has_offset = false;
2813 break;
2814 case TGSI_OPCODE_TXQ:
2815 name = "llvm.SI.getresinfo";
2816 is_shadow = false;
2817 has_offset = false;
2818 break;
2819 case TGSI_OPCODE_LODQ:
2820 name = "llvm.SI.getlod";
2821 is_shadow = false;
2822 has_offset = false;
2823 break;
2824 case TGSI_OPCODE_TEX:
2825 case TGSI_OPCODE_TEX2:
2826 case TGSI_OPCODE_TXP:
2827 break;
2828 case TGSI_OPCODE_TXB:
2829 case TGSI_OPCODE_TXB2:
2830 infix = ".b";
2831 break;
2832 case TGSI_OPCODE_TXL:
2833 case TGSI_OPCODE_TXL2:
2834 infix = ".l";
2835 break;
2836 case TGSI_OPCODE_TXD:
2837 infix = ".d";
2838 break;
2839 case TGSI_OPCODE_TG4:
2840 name = "llvm.SI.gather4";
2841 break;
2842 default:
2843 assert(0);
2844 return;
2845 }
2846
2847 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2848 sprintf(type, ".v%ui32",
2849 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2850 else
2851 strcpy(type, ".i32");
2852
2853 /* Add the type and suffixes .c, .o if needed. */
2854 sprintf(intr_name, "%s%s%s%s%s",
2855 name, is_shadow ? ".c" : "", infix,
2856 has_offset ? ".o" : "", type);
2857
2858 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2859 base->gallivm->builder, intr_name, emit_data->dst_type,
2860 emit_data->args, emit_data->arg_count,
2861 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2862
2863 /* Divide the number of layers by 6 to get the number of cubes. */
2864 if (opcode == TGSI_OPCODE_TXQ &&
2865 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2866 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2867 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2868 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2869 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2870
2871 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2872 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2873 z = LLVMBuildSDiv(builder, z, six, "");
2874
2875 emit_data->output[emit_data->chan] =
2876 LLVMBuildInsertElement(builder, v4, z, two, "");
2877 }
2878 }
2879
2880 static void si_llvm_emit_txqs(
2881 const struct lp_build_tgsi_action * action,
2882 struct lp_build_tgsi_context * bld_base,
2883 struct lp_build_emit_data * emit_data)
2884 {
2885 struct gallivm_state *gallivm = bld_base->base.gallivm;
2886 LLVMBuilderRef builder = gallivm->builder;
2887 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2888 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2889 LLVMValueRef res, samples;
2890 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2891
2892 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2893
2894
2895 /* Read the samples from the descriptor directly. */
2896 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2897 samples = LLVMBuildExtractElement(
2898 builder, res,
2899 lp_build_const_int32(gallivm, 3), "");
2900 samples = LLVMBuildLShr(builder, samples,
2901 lp_build_const_int32(gallivm, 16), "");
2902 samples = LLVMBuildAnd(builder, samples,
2903 lp_build_const_int32(gallivm, 0xf), "");
2904 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2905 samples, "");
2906
2907 emit_data->output[emit_data->chan] = samples;
2908 }
2909
2910 /*
2911 * SI implements derivatives using the local data store (LDS)
2912 * All writes to the LDS happen in all executing threads at
2913 * the same time. TID is the Thread ID for the current
2914 * thread and is a value between 0 and 63, representing
2915 * the thread's position in the wavefront.
2916 *
2917 * For the pixel shader threads are grouped into quads of four pixels.
2918 * The TIDs of the pixels of a quad are:
2919 *
2920 * +------+------+
2921 * |4n + 0|4n + 1|
2922 * +------+------+
2923 * |4n + 2|4n + 3|
2924 * +------+------+
2925 *
2926 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2927 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2928 * the current pixel's column, and masking with 0xfffffffe yields the TID
2929 * of the left pixel of the current pixel's row.
2930 *
2931 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2932 * adding 2 yields the TID of the pixel below the top pixel.
2933 */
2934 /* masks for thread ID. */
2935 #define TID_MASK_TOP_LEFT 0xfffffffc
2936 #define TID_MASK_TOP 0xfffffffd
2937 #define TID_MASK_LEFT 0xfffffffe
2938
2939 static void si_llvm_emit_ddxy(
2940 const struct lp_build_tgsi_action * action,
2941 struct lp_build_tgsi_context * bld_base,
2942 struct lp_build_emit_data * emit_data)
2943 {
2944 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2945 struct gallivm_state *gallivm = bld_base->base.gallivm;
2946 struct lp_build_context * base = &bld_base->base;
2947 const struct tgsi_full_instruction *inst = emit_data->inst;
2948 unsigned opcode = inst->Instruction.Opcode;
2949 LLVMValueRef indices[2];
2950 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2951 LLVMValueRef tl, trbl, result[4];
2952 LLVMTypeRef i32;
2953 unsigned swizzle[4];
2954 unsigned c;
2955 int idx;
2956 unsigned mask;
2957
2958 i32 = LLVMInt32TypeInContext(gallivm->context);
2959
2960 indices[0] = bld_base->uint_bld.zero;
2961 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2962 NULL, 0, LLVMReadNoneAttribute);
2963 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2964 indices, 2, "");
2965
2966 if (opcode == TGSI_OPCODE_DDX_FINE)
2967 mask = TID_MASK_LEFT;
2968 else if (opcode == TGSI_OPCODE_DDY_FINE)
2969 mask = TID_MASK_TOP;
2970 else
2971 mask = TID_MASK_TOP_LEFT;
2972
2973 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2974 lp_build_const_int32(gallivm, mask), "");
2975 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2976 indices, 2, "");
2977
2978 /* for DDX we want to next X pixel, DDY next Y pixel. */
2979 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2980 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2981 lp_build_const_int32(gallivm, idx), "");
2982 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2983 indices, 2, "");
2984
2985 for (c = 0; c < 4; ++c) {
2986 unsigned i;
2987
2988 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2989 for (i = 0; i < c; ++i) {
2990 if (swizzle[i] == swizzle[c]) {
2991 result[c] = result[i];
2992 break;
2993 }
2994 }
2995 if (i != c)
2996 continue;
2997
2998 LLVMBuildStore(gallivm->builder,
2999 LLVMBuildBitCast(gallivm->builder,
3000 lp_build_emit_fetch(bld_base, inst, 0, c),
3001 i32, ""),
3002 store_ptr);
3003
3004 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3005 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3006
3007 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3008 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3009
3010 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3011 }
3012
3013 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3014 }
3015
3016 /*
3017 * this takes an I,J coordinate pair,
3018 * and works out the X and Y derivatives.
3019 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3020 */
3021 static LLVMValueRef si_llvm_emit_ddxy_interp(
3022 struct lp_build_tgsi_context *bld_base,
3023 LLVMValueRef interp_ij)
3024 {
3025 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3026 struct gallivm_state *gallivm = bld_base->base.gallivm;
3027 struct lp_build_context *base = &bld_base->base;
3028 LLVMValueRef indices[2];
3029 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3030 LLVMValueRef tl, tr, bl, result[4];
3031 LLVMTypeRef i32;
3032 unsigned c;
3033
3034 i32 = LLVMInt32TypeInContext(gallivm->context);
3035
3036 indices[0] = bld_base->uint_bld.zero;
3037 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3038 NULL, 0, LLVMReadNoneAttribute);
3039 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3040 indices, 2, "");
3041
3042 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3043 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3044
3045 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3046 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3047
3048 indices[1] = temp;
3049 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3050 indices, 2, "");
3051
3052 indices[1] = temp2;
3053 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3054 indices, 2, "");
3055
3056 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3057 lp_build_const_int32(gallivm, 1), "");
3058 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3059 indices, 2, "");
3060
3061 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3062 lp_build_const_int32(gallivm, 2), "");
3063 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3064 indices, 2, "");
3065
3066 for (c = 0; c < 2; ++c) {
3067 LLVMValueRef store_val;
3068 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3069
3070 store_val = LLVMBuildExtractElement(gallivm->builder,
3071 interp_ij, c_ll, "");
3072 LLVMBuildStore(gallivm->builder,
3073 store_val,
3074 store_ptr);
3075
3076 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3077 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3078
3079 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3080 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3081
3082 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3083
3084 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3085 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3086
3087 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3088 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3089
3090 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3091 }
3092
3093 return lp_build_gather_values(gallivm, result, 4);
3094 }
3095
3096 static void interp_fetch_args(
3097 struct lp_build_tgsi_context *bld_base,
3098 struct lp_build_emit_data *emit_data)
3099 {
3100 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3101 struct gallivm_state *gallivm = bld_base->base.gallivm;
3102 const struct tgsi_full_instruction *inst = emit_data->inst;
3103
3104 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3105 /* offset is in second src, first two channels */
3106 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3107 emit_data->inst, 1,
3108 0);
3109 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3110 emit_data->inst, 1,
3111 1);
3112 emit_data->arg_count = 2;
3113 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3114 LLVMValueRef sample_position;
3115 LLVMValueRef sample_id;
3116 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3117
3118 /* fetch sample ID, then fetch its sample position,
3119 * and place into first two channels.
3120 */
3121 sample_id = lp_build_emit_fetch(bld_base,
3122 emit_data->inst, 1, 0);
3123 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3124 LLVMInt32TypeInContext(gallivm->context),
3125 "");
3126 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3127
3128 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3129 sample_position,
3130 lp_build_const_int32(gallivm, 0), "");
3131
3132 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3133 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3134 sample_position,
3135 lp_build_const_int32(gallivm, 1), "");
3136 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3137 emit_data->arg_count = 2;
3138 }
3139 }
3140
3141 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3142 struct lp_build_tgsi_context *bld_base,
3143 struct lp_build_emit_data *emit_data)
3144 {
3145 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3146 struct si_shader *shader = si_shader_ctx->shader;
3147 struct gallivm_state *gallivm = bld_base->base.gallivm;
3148 LLVMValueRef interp_param;
3149 const struct tgsi_full_instruction *inst = emit_data->inst;
3150 const char *intr_name;
3151 int input_index;
3152 int chan;
3153 int i;
3154 LLVMValueRef attr_number;
3155 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3156 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3157 int interp_param_idx;
3158 unsigned location;
3159
3160 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3161 input_index = inst->Src[0].Register.Index;
3162
3163 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3164 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3165 location = TGSI_INTERPOLATE_LOC_CENTER;
3166 else
3167 location = TGSI_INTERPOLATE_LOC_CENTROID;
3168
3169 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3170 location);
3171 if (interp_param_idx == -1)
3172 return;
3173 else if (interp_param_idx)
3174 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3175 else
3176 interp_param = NULL;
3177
3178 attr_number = lp_build_const_int32(gallivm,
3179 shader->ps_input_param_offset[input_index]);
3180
3181 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3182 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3183 LLVMValueRef ij_out[2];
3184 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3185
3186 /*
3187 * take the I then J parameters, and the DDX/Y for it, and
3188 * calculate the IJ inputs for the interpolator.
3189 * temp1 = ddx * offset/sample.x + I;
3190 * interp_param.I = ddy * offset/sample.y + temp1;
3191 * temp1 = ddx * offset/sample.x + J;
3192 * interp_param.J = ddy * offset/sample.y + temp1;
3193 */
3194 for (i = 0; i < 2; i++) {
3195 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3196 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3197 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3198 ddxy_out, ix_ll, "");
3199 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3200 ddxy_out, iy_ll, "");
3201 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3202 interp_param, ix_ll, "");
3203 LLVMValueRef temp1, temp2;
3204
3205 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3206 LLVMFloatTypeInContext(gallivm->context), "");
3207
3208 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3209
3210 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3211
3212 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3213
3214 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3215
3216 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3217 temp2,
3218 LLVMIntTypeInContext(gallivm->context, 32), "");
3219 }
3220 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3221 }
3222
3223 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3224 for (chan = 0; chan < 2; chan++) {
3225 LLVMValueRef args[4];
3226 LLVMValueRef llvm_chan;
3227 unsigned schan;
3228
3229 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3230 llvm_chan = lp_build_const_int32(gallivm, schan);
3231
3232 args[0] = llvm_chan;
3233 args[1] = attr_number;
3234 args[2] = params;
3235 args[3] = interp_param;
3236
3237 emit_data->output[chan] =
3238 lp_build_intrinsic(gallivm->builder, intr_name,
3239 input_type, args, args[3] ? 4 : 3,
3240 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3241 }
3242 }
3243
3244 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3245 struct lp_build_emit_data *emit_data)
3246 {
3247 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3248 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3249 unsigned stream;
3250
3251 assert(src0.File == TGSI_FILE_IMMEDIATE);
3252
3253 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3254 return stream;
3255 }
3256
3257 /* Emit one vertex from the geometry shader */
3258 static void si_llvm_emit_vertex(
3259 const struct lp_build_tgsi_action *action,
3260 struct lp_build_tgsi_context *bld_base,
3261 struct lp_build_emit_data *emit_data)
3262 {
3263 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3264 struct lp_build_context *uint = &bld_base->uint_bld;
3265 struct si_shader *shader = si_shader_ctx->shader;
3266 struct tgsi_shader_info *info = &shader->selector->info;
3267 struct gallivm_state *gallivm = bld_base->base.gallivm;
3268 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3269 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3270 SI_PARAM_GS2VS_OFFSET);
3271 LLVMValueRef gs_next_vertex;
3272 LLVMValueRef can_emit, kill;
3273 LLVMValueRef args[2];
3274 unsigned chan;
3275 int i;
3276 unsigned stream;
3277
3278 stream = si_llvm_get_stream(bld_base, emit_data);
3279
3280 /* Write vertex attribute values to GSVS ring */
3281 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3282 si_shader_ctx->gs_next_vertex[stream],
3283 "");
3284
3285 /* If this thread has already emitted the declared maximum number of
3286 * vertices, kill it: excessive vertex emissions are not supposed to
3287 * have any effect, and GS threads have no externally observable
3288 * effects other than emitting vertices.
3289 */
3290 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3291 lp_build_const_int32(gallivm,
3292 shader->selector->gs_max_out_vertices), "");
3293 kill = lp_build_select(&bld_base->base, can_emit,
3294 lp_build_const_float(gallivm, 1.0f),
3295 lp_build_const_float(gallivm, -1.0f));
3296
3297 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3298 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3299
3300 for (i = 0; i < info->num_outputs; i++) {
3301 LLVMValueRef *out_ptr =
3302 si_shader_ctx->radeon_bld.soa.outputs[i];
3303
3304 for (chan = 0; chan < 4; chan++) {
3305 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3306 LLVMValueRef voffset =
3307 lp_build_const_int32(gallivm, (i * 4 + chan) *
3308 shader->selector->gs_max_out_vertices);
3309
3310 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3311 voffset = lp_build_mul_imm(uint, voffset, 4);
3312
3313 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3314
3315 build_tbuffer_store(si_shader_ctx,
3316 si_shader_ctx->gsvs_ring[stream],
3317 out_val, 1,
3318 voffset, soffset, 0,
3319 V_008F0C_BUF_DATA_FORMAT_32,
3320 V_008F0C_BUF_NUM_FORMAT_UINT,
3321 1, 0, 1, 1, 0);
3322 }
3323 }
3324 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3325 lp_build_const_int32(gallivm, 1));
3326
3327 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3328
3329 /* Signal vertex emission */
3330 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3331 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3332 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3333 LLVMVoidTypeInContext(gallivm->context), args, 2,
3334 LLVMNoUnwindAttribute);
3335 }
3336
3337 /* Cut one primitive from the geometry shader */
3338 static void si_llvm_emit_primitive(
3339 const struct lp_build_tgsi_action *action,
3340 struct lp_build_tgsi_context *bld_base,
3341 struct lp_build_emit_data *emit_data)
3342 {
3343 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3344 struct gallivm_state *gallivm = bld_base->base.gallivm;
3345 LLVMValueRef args[2];
3346 unsigned stream;
3347
3348 /* Signal primitive cut */
3349 stream = si_llvm_get_stream(bld_base, emit_data);
3350 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3351 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3352 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3353 LLVMVoidTypeInContext(gallivm->context), args, 2,
3354 LLVMNoUnwindAttribute);
3355 }
3356
3357 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3358 struct lp_build_tgsi_context *bld_base,
3359 struct lp_build_emit_data *emit_data)
3360 {
3361 struct gallivm_state *gallivm = bld_base->base.gallivm;
3362
3363 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3364 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3365 LLVMNoUnwindAttribute);
3366 }
3367
3368 static const struct lp_build_tgsi_action tex_action = {
3369 .fetch_args = tex_fetch_args,
3370 .emit = build_tex_intrinsic,
3371 };
3372
3373 static const struct lp_build_tgsi_action interp_action = {
3374 .fetch_args = interp_fetch_args,
3375 .emit = build_interp_intrinsic,
3376 };
3377
3378 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3379 {
3380 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3381 LLVMValueRef args[3];
3382
3383 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3384 args[1] = 0;
3385 args[2] = lp_build_const_int32(gallivm, 1);
3386
3387 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3388 }
3389
3390 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3391 {
3392 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3393 CONST_ADDR_SPACE);
3394 }
3395
3396 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3397 struct pipe_stream_output_info *so,
3398 LLVMTypeRef *params, LLVMTypeRef i32,
3399 unsigned *num_params)
3400 {
3401 int i;
3402
3403 /* Streamout SGPRs. */
3404 if (so->num_outputs) {
3405 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3406 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3407 }
3408 /* A streamout buffer offset is loaded if the stride is non-zero. */
3409 for (i = 0; i < 4; i++) {
3410 if (!so->stride[i])
3411 continue;
3412
3413 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3414 }
3415 }
3416
3417 static void create_function(struct si_shader_context *si_shader_ctx)
3418 {
3419 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3420 struct gallivm_state *gallivm = bld_base->base.gallivm;
3421 struct si_shader *shader = si_shader_ctx->shader;
3422 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3423 unsigned i, last_array_pointer, last_sgpr, num_params;
3424
3425 i8 = LLVMInt8TypeInContext(gallivm->context);
3426 i32 = LLVMInt32TypeInContext(gallivm->context);
3427 f32 = LLVMFloatTypeInContext(gallivm->context);
3428 v2i32 = LLVMVectorType(i32, 2);
3429 v3i32 = LLVMVectorType(i32, 3);
3430 v4i32 = LLVMVectorType(i32, 4);
3431 v8i32 = LLVMVectorType(i32, 8);
3432 v16i8 = LLVMVectorType(i8, 16);
3433
3434 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3435 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3436 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3437 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3438 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3439
3440 switch (si_shader_ctx->type) {
3441 case TGSI_PROCESSOR_VERTEX:
3442 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3443 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3444 params[SI_PARAM_BASE_VERTEX] = i32;
3445 params[SI_PARAM_START_INSTANCE] = i32;
3446 num_params = SI_PARAM_START_INSTANCE+1;
3447
3448 if (shader->key.vs.as_es) {
3449 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3450 } else if (shader->key.vs.as_ls) {
3451 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3452 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3453 } else {
3454 if (shader->is_gs_copy_shader) {
3455 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3456 num_params = SI_PARAM_CONST_BUFFERS+1;
3457 } else {
3458 params[SI_PARAM_VS_STATE_BITS] = i32;
3459 num_params = SI_PARAM_VS_STATE_BITS+1;
3460 }
3461
3462 /* The locations of the other parameters are assigned dynamically. */
3463 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3464 params, i32, &num_params);
3465 }
3466
3467 last_sgpr = num_params-1;
3468
3469 /* VGPRs */
3470 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3471 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3472 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3473 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3474 break;
3475
3476 case TGSI_PROCESSOR_TESS_CTRL:
3477 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3478 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3479 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3480 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3481 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3482
3483 /* VGPRs */
3484 params[SI_PARAM_PATCH_ID] = i32;
3485 params[SI_PARAM_REL_IDS] = i32;
3486 num_params = SI_PARAM_REL_IDS+1;
3487 break;
3488
3489 case TGSI_PROCESSOR_TESS_EVAL:
3490 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3491 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3492 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3493
3494 if (shader->key.tes.as_es) {
3495 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3496 } else {
3497 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3498 params, i32, &num_params);
3499 }
3500 last_sgpr = num_params - 1;
3501
3502 /* VGPRs */
3503 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3504 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3505 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3506 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3507 break;
3508
3509 case TGSI_PROCESSOR_GEOMETRY:
3510 params[SI_PARAM_GS2VS_OFFSET] = i32;
3511 params[SI_PARAM_GS_WAVE_ID] = i32;
3512 last_sgpr = SI_PARAM_GS_WAVE_ID;
3513
3514 /* VGPRs */
3515 params[SI_PARAM_VTX0_OFFSET] = i32;
3516 params[SI_PARAM_VTX1_OFFSET] = i32;
3517 params[SI_PARAM_PRIMITIVE_ID] = i32;
3518 params[SI_PARAM_VTX2_OFFSET] = i32;
3519 params[SI_PARAM_VTX3_OFFSET] = i32;
3520 params[SI_PARAM_VTX4_OFFSET] = i32;
3521 params[SI_PARAM_VTX5_OFFSET] = i32;
3522 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3523 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3524 break;
3525
3526 case TGSI_PROCESSOR_FRAGMENT:
3527 params[SI_PARAM_ALPHA_REF] = f32;
3528 params[SI_PARAM_PS_STATE_BITS] = i32;
3529 params[SI_PARAM_PRIM_MASK] = i32;
3530 last_sgpr = SI_PARAM_PRIM_MASK;
3531 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3532 params[SI_PARAM_PERSP_CENTER] = v2i32;
3533 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3534 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3535 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3536 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3537 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3538 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3539 params[SI_PARAM_POS_X_FLOAT] = f32;
3540 params[SI_PARAM_POS_Y_FLOAT] = f32;
3541 params[SI_PARAM_POS_Z_FLOAT] = f32;
3542 params[SI_PARAM_POS_W_FLOAT] = f32;
3543 params[SI_PARAM_FRONT_FACE] = f32;
3544 params[SI_PARAM_ANCILLARY] = i32;
3545 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3546 params[SI_PARAM_POS_FIXED_PT] = f32;
3547 num_params = SI_PARAM_POS_FIXED_PT+1;
3548 break;
3549
3550 default:
3551 assert(0 && "unimplemented shader");
3552 return;
3553 }
3554
3555 assert(num_params <= Elements(params));
3556 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3557 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3558
3559 if (shader->dx10_clamp_mode)
3560 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3561 "enable-no-nans-fp-math", "true");
3562
3563 for (i = 0; i <= last_sgpr; ++i) {
3564 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3565
3566 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3567 * to move load. Inputs are constant so this is fine. */
3568 if (i <= last_array_pointer)
3569 LLVMAddAttribute(P, LLVMByValAttribute);
3570 else
3571 LLVMAddAttribute(P, LLVMInRegAttribute);
3572 }
3573
3574 if (bld_base->info &&
3575 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3576 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3577 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3578 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3579 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3580 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3581 si_shader_ctx->lds =
3582 LLVMAddGlobalInAddressSpace(gallivm->module,
3583 LLVMArrayType(i32, 64),
3584 "ddxy_lds",
3585 LOCAL_ADDR_SPACE);
3586
3587 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3588 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3589 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3590 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3591 unsigned vertex_data_dw_size = 32*32*4;
3592 unsigned patch_data_dw_size = 32*4;
3593 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3594 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3595 unsigned lds_dwords = patch_dw_size;
3596
3597 /* The actual size is computed outside of the shader to reduce
3598 * the number of shader variants. */
3599 si_shader_ctx->lds =
3600 LLVMAddGlobalInAddressSpace(gallivm->module,
3601 LLVMArrayType(i32, lds_dwords),
3602 "tess_lds",
3603 LOCAL_ADDR_SPACE);
3604 }
3605 }
3606
3607 static void preload_constants(struct si_shader_context *si_shader_ctx)
3608 {
3609 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3610 struct gallivm_state * gallivm = bld_base->base.gallivm;
3611 const struct tgsi_shader_info * info = bld_base->info;
3612 unsigned buf;
3613 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3614
3615 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3616 unsigned i, num_const = info->const_file_max[buf] + 1;
3617
3618 if (num_const == 0)
3619 continue;
3620
3621 /* Allocate space for the constant values */
3622 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3623
3624 /* Load the resource descriptor */
3625 si_shader_ctx->const_buffers[buf] =
3626 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3627
3628 /* Load the constants, we rely on the code sinking to do the rest */
3629 for (i = 0; i < num_const * 4; ++i) {
3630 si_shader_ctx->constants[buf][i] =
3631 buffer_load_const(gallivm->builder,
3632 si_shader_ctx->const_buffers[buf],
3633 lp_build_const_int32(gallivm, i * 4),
3634 bld_base->base.elem_type);
3635 }
3636 }
3637 }
3638
3639 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3640 {
3641 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3642 struct gallivm_state * gallivm = bld_base->base.gallivm;
3643 const struct tgsi_shader_info * info = bld_base->info;
3644
3645 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3646
3647 LLVMValueRef res_ptr, samp_ptr;
3648 LLVMValueRef offset;
3649
3650 if (num_samplers == 0)
3651 return;
3652
3653 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3654 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3655
3656 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3657 for (i = 0; i < num_samplers; ++i) {
3658 /* Resource */
3659 offset = lp_build_const_int32(gallivm, i);
3660 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3661
3662 /* Sampler */
3663 offset = lp_build_const_int32(gallivm, i);
3664 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3665
3666 /* FMASK resource */
3667 if (info->is_msaa_sampler[i]) {
3668 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3669 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3670 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3671 }
3672 }
3673 }
3674
3675 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3676 {
3677 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3678 struct gallivm_state * gallivm = bld_base->base.gallivm;
3679 unsigned i;
3680
3681 /* Streamout can only be used if the shader is compiled as VS. */
3682 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3683 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3684 (si_shader_ctx->shader->key.vs.as_es ||
3685 si_shader_ctx->shader->key.vs.as_ls)) ||
3686 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3687 si_shader_ctx->shader->key.tes.as_es))
3688 return;
3689
3690 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3691 SI_PARAM_RW_BUFFERS);
3692
3693 /* Load the resources, we rely on the code sinking to do the rest */
3694 for (i = 0; i < 4; ++i) {
3695 if (si_shader_ctx->shader->selector->so.stride[i]) {
3696 LLVMValueRef offset = lp_build_const_int32(gallivm,
3697 SI_SO_BUF_OFFSET + i);
3698
3699 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3700 }
3701 }
3702 }
3703
3704 /**
3705 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3706 * for later use.
3707 */
3708 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3709 {
3710 struct gallivm_state *gallivm =
3711 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3712
3713 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3714 SI_PARAM_RW_BUFFERS);
3715
3716 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3717 si_shader_ctx->shader->key.vs.as_es) ||
3718 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3719 si_shader_ctx->shader->key.tes.as_es) ||
3720 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3721 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3722
3723 si_shader_ctx->esgs_ring =
3724 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3725 }
3726
3727 if (si_shader_ctx->shader->is_gs_copy_shader) {
3728 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3729
3730 si_shader_ctx->gsvs_ring[0] =
3731 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3732 }
3733 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3734 int i;
3735 for (i = 0; i < 4; i++) {
3736 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3737
3738 si_shader_ctx->gsvs_ring[i] =
3739 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3740 }
3741 }
3742 }
3743
3744 void si_shader_binary_read_config(struct si_shader *shader,
3745 unsigned symbol_offset)
3746 {
3747 unsigned i;
3748 const unsigned char *config =
3749 radeon_shader_binary_config_start(&shader->binary,
3750 symbol_offset);
3751
3752 /* XXX: We may be able to emit some of these values directly rather than
3753 * extracting fields to be emitted later.
3754 */
3755
3756 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3757 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3758 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3759 switch (reg) {
3760 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3761 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3762 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3763 case R_00B848_COMPUTE_PGM_RSRC1:
3764 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3765 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3766 shader->float_mode = G_00B028_FLOAT_MODE(value);
3767 shader->rsrc1 = value;
3768 break;
3769 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3770 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3771 break;
3772 case R_00B84C_COMPUTE_PGM_RSRC2:
3773 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3774 shader->rsrc2 = value;
3775 break;
3776 case R_0286CC_SPI_PS_INPUT_ENA:
3777 shader->spi_ps_input_ena = value;
3778 break;
3779 case R_0286E8_SPI_TMPRING_SIZE:
3780 case R_00B860_COMPUTE_TMPRING_SIZE:
3781 /* WAVESIZE is in units of 256 dwords. */
3782 shader->scratch_bytes_per_wave =
3783 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3784 break;
3785 default:
3786 fprintf(stderr, "Warning: Compiler emitted unknown "
3787 "config register: 0x%x\n", reg);
3788 break;
3789 }
3790 }
3791 }
3792
3793 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3794 struct si_shader *shader,
3795 uint64_t scratch_va)
3796 {
3797 unsigned i;
3798 uint32_t scratch_rsrc_dword0 = scratch_va;
3799 uint32_t scratch_rsrc_dword1 =
3800 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3801 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3802
3803 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3804 const struct radeon_shader_reloc *reloc =
3805 &shader->binary.relocs[i];
3806 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3807 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3808 &scratch_rsrc_dword0, 4);
3809 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3810 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3811 &scratch_rsrc_dword1, 4);
3812 }
3813 }
3814 }
3815
3816 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3817 {
3818 const struct radeon_shader_binary *binary = &shader->binary;
3819 unsigned code_size = binary->code_size + binary->rodata_size;
3820 unsigned char *ptr;
3821
3822 r600_resource_reference(&shader->bo, NULL);
3823 shader->bo = si_resource_create_custom(&sscreen->b.b,
3824 PIPE_USAGE_IMMUTABLE,
3825 code_size);
3826 if (!shader->bo)
3827 return -ENOMEM;
3828
3829 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3830 PIPE_TRANSFER_READ_WRITE);
3831 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3832 if (binary->rodata_size > 0) {
3833 ptr += binary->code_size;
3834 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3835 binary->rodata_size);
3836 }
3837
3838 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3839 return 0;
3840 }
3841
3842 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3843 struct pipe_debug_callback *debug)
3844 {
3845 char *line, *p;
3846 unsigned i, count;
3847
3848 if (binary->disasm_string) {
3849 fprintf(stderr, "\nShader Disassembly:\n\n");
3850 fprintf(stderr, "%s\n", binary->disasm_string);
3851
3852 if (debug && debug->debug_message) {
3853 /* Very long debug messages are cut off, so send the
3854 * disassembly one line at a time. This causes more
3855 * overhead, but on the plus side it simplifies
3856 * parsing of resulting logs.
3857 */
3858 pipe_debug_message(debug, SHADER_INFO,
3859 "Shader Disassembly Begin");
3860
3861 line = binary->disasm_string;
3862 while (*line) {
3863 p = strchrnul(line, '\n');
3864 count = p - line;
3865
3866 if (count) {
3867 pipe_debug_message(debug, SHADER_INFO,
3868 "%.*s", count, line);
3869 }
3870
3871 if (!*p)
3872 break;
3873 line = p + 1;
3874 }
3875
3876 pipe_debug_message(debug, SHADER_INFO,
3877 "Shader Disassembly End");
3878 }
3879 } else {
3880 fprintf(stderr, "SI CODE:\n");
3881 for (i = 0; i < binary->code_size; i += 4) {
3882 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3883 binary->code[i + 3], binary->code[i + 2],
3884 binary->code[i + 1], binary->code[i]);
3885 }
3886 }
3887 }
3888
3889 void si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
3890 struct pipe_debug_callback *debug, unsigned processor)
3891 {
3892 const struct radeon_shader_binary *binary = &shader->binary;
3893
3894 si_shader_binary_read_config(shader, 0);
3895
3896 if (r600_can_dump_shader(&sscreen->b, processor)) {
3897 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
3898 si_shader_dump_disassembly(binary, debug);
3899
3900 fprintf(stderr, "*** SHADER STATS ***\n"
3901 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3902 "Scratch: %d bytes per wave\n********************\n",
3903 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3904 shader->lds_size, shader->scratch_bytes_per_wave);
3905 }
3906
3907 pipe_debug_message(debug, SHADER_INFO,
3908 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
3909 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3910 shader->lds_size, shader->scratch_bytes_per_wave);
3911 }
3912
3913 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3914 LLVMTargetMachineRef tm, LLVMModuleRef mod,
3915 struct pipe_debug_callback *debug, unsigned processor)
3916 {
3917 int r = 0;
3918 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
3919
3920 if (r600_can_dump_shader(&sscreen->b, processor)) {
3921 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
3922
3923 if (!(sscreen->b.debug_flags & DBG_NO_IR))
3924 LLVMDumpModule(mod);
3925 }
3926
3927 if (!si_replace_shader(count, &shader->binary)) {
3928 r = radeon_llvm_compile(mod, &shader->binary,
3929 r600_get_llvm_processor_name(sscreen->b.family), tm,
3930 debug);
3931 if (r)
3932 return r;
3933 }
3934
3935 si_shader_binary_read(sscreen, shader, debug, processor);
3936
3937 r = si_shader_binary_upload(sscreen, shader);
3938 if (r)
3939 return r;
3940
3941 FREE(shader->binary.config);
3942 FREE(shader->binary.rodata);
3943 FREE(shader->binary.global_symbol_offsets);
3944 if (shader->scratch_bytes_per_wave == 0) {
3945 FREE(shader->binary.code);
3946 FREE(shader->binary.relocs);
3947 memset(&shader->binary, 0,
3948 offsetof(struct radeon_shader_binary, disasm_string));
3949 }
3950 return r;
3951 }
3952
3953 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3954 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3955 struct si_shader_context *si_shader_ctx,
3956 struct si_shader *gs, bool dump,
3957 struct pipe_debug_callback *debug)
3958 {
3959 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3960 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3961 struct lp_build_context *base = &bld_base->base;
3962 struct lp_build_context *uint = &bld_base->uint_bld;
3963 struct si_shader *shader = si_shader_ctx->shader;
3964 struct si_shader_output_values *outputs;
3965 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3966 LLVMValueRef args[9];
3967 int i, r;
3968
3969 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3970
3971 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3972 shader->is_gs_copy_shader = true;
3973
3974 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3975
3976 create_meta_data(si_shader_ctx);
3977 create_function(si_shader_ctx);
3978 preload_streamout_buffers(si_shader_ctx);
3979 preload_ring_buffers(si_shader_ctx);
3980
3981 args[0] = si_shader_ctx->gsvs_ring[0];
3982 args[1] = lp_build_mul_imm(uint,
3983 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3984 si_shader_ctx->param_vertex_id),
3985 4);
3986 args[3] = uint->zero;
3987 args[4] = uint->one; /* OFFEN */
3988 args[5] = uint->zero; /* IDXEN */
3989 args[6] = uint->one; /* GLC */
3990 args[7] = uint->one; /* SLC */
3991 args[8] = uint->zero; /* TFE */
3992
3993 /* Fetch vertex data from GSVS ring */
3994 for (i = 0; i < gsinfo->num_outputs; ++i) {
3995 unsigned chan;
3996
3997 outputs[i].name = gsinfo->output_semantic_name[i];
3998 outputs[i].sid = gsinfo->output_semantic_index[i];
3999
4000 for (chan = 0; chan < 4; chan++) {
4001 args[2] = lp_build_const_int32(gallivm,
4002 (i * 4 + chan) *
4003 gs->selector->gs_max_out_vertices * 16 * 4);
4004
4005 outputs[i].values[chan] =
4006 LLVMBuildBitCast(gallivm->builder,
4007 lp_build_intrinsic(gallivm->builder,
4008 "llvm.SI.buffer.load.dword.i32.i32",
4009 LLVMInt32TypeInContext(gallivm->context),
4010 args, 9,
4011 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4012 base->elem_type, "");
4013 }
4014 }
4015
4016 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4017
4018 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4019
4020 if (dump)
4021 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4022
4023 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
4024 si_shader_ctx->tm, bld_base->base.gallivm->module,
4025 debug, TGSI_PROCESSOR_GEOMETRY);
4026
4027 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4028
4029 FREE(outputs);
4030 return r;
4031 }
4032
4033 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4034 {
4035 int i;
4036
4037 fprintf(f, "SHADER KEY\n");
4038
4039 switch (shader) {
4040 case PIPE_SHADER_VERTEX:
4041 fprintf(f, " instance_divisors = {");
4042 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4043 fprintf(f, !i ? "%u" : ", %u",
4044 key->vs.instance_divisors[i]);
4045 fprintf(f, "}\n");
4046 fprintf(f, " as_es = %u\n", key->vs.as_es);
4047 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4048 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4049 break;
4050
4051 case PIPE_SHADER_TESS_CTRL:
4052 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4053 break;
4054
4055 case PIPE_SHADER_TESS_EVAL:
4056 fprintf(f, " as_es = %u\n", key->tes.as_es);
4057 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4058 break;
4059
4060 case PIPE_SHADER_GEOMETRY:
4061 break;
4062
4063 case PIPE_SHADER_FRAGMENT:
4064 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4065 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4066 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4067 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4068 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4069 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4070 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4071 break;
4072
4073 default:
4074 assert(0);
4075 }
4076 }
4077
4078 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4079 struct si_shader *shader,
4080 struct pipe_debug_callback *debug)
4081 {
4082 struct si_shader_selector *sel = shader->selector;
4083 struct tgsi_token *tokens = sel->tokens;
4084 struct si_shader_context si_shader_ctx;
4085 struct lp_build_tgsi_context * bld_base;
4086 struct tgsi_shader_info stipple_shader_info;
4087 LLVMModuleRef mod;
4088 int r = 0;
4089 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4090 shader->key.ps.poly_stipple;
4091 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4092
4093 if (poly_stipple) {
4094 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4095 SI_POLY_STIPPLE_SAMPLER);
4096 tgsi_scan_shader(tokens, &stipple_shader_info);
4097 }
4098
4099 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4100 * conversion fails. */
4101 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4102 si_dump_shader_key(sel->type, &shader->key, stderr);
4103 tgsi_dump(tokens, 0);
4104 si_dump_streamout(&sel->so);
4105 }
4106
4107 assert(shader->nparam == 0);
4108
4109 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4110 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4111 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4112
4113 if (sel->type != PIPE_SHADER_COMPUTE)
4114 shader->dx10_clamp_mode = true;
4115
4116 if (sel->info.uses_kill)
4117 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4118
4119 shader->uses_instanceid = sel->info.uses_instanceid;
4120 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4121 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4122
4123 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4124 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4125 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4126
4127 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4128 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4129 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4130 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4131 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4132 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4133 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4134 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4135 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4136 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4137 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4138 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4139 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4140
4141 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4142 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4143 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4144 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4145
4146 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4147 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4148 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4149
4150 if (HAVE_LLVM >= 0x0306) {
4151 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4152 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4153 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4154 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4155 }
4156
4157 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4158 si_shader_ctx.shader = shader;
4159 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4160 si_shader_ctx.screen = sscreen;
4161 si_shader_ctx.tm = tm;
4162
4163 switch (si_shader_ctx.type) {
4164 case TGSI_PROCESSOR_VERTEX:
4165 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4166 if (shader->key.vs.as_ls)
4167 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4168 else if (shader->key.vs.as_es)
4169 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4170 else
4171 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4172 break;
4173 case TGSI_PROCESSOR_TESS_CTRL:
4174 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4175 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4176 bld_base->emit_store = store_output_tcs;
4177 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4178 break;
4179 case TGSI_PROCESSOR_TESS_EVAL:
4180 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4181 if (shader->key.tes.as_es)
4182 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4183 else
4184 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4185 break;
4186 case TGSI_PROCESSOR_GEOMETRY:
4187 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4188 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4189 break;
4190 case TGSI_PROCESSOR_FRAGMENT:
4191 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4192 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4193
4194 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4195 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4196 shader->db_shader_control |=
4197 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4198 break;
4199 case TGSI_FS_DEPTH_LAYOUT_LESS:
4200 shader->db_shader_control |=
4201 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4202 break;
4203 }
4204 break;
4205 default:
4206 assert(!"Unsupported shader type");
4207 return -1;
4208 }
4209
4210 create_meta_data(&si_shader_ctx);
4211 create_function(&si_shader_ctx);
4212 preload_constants(&si_shader_ctx);
4213 preload_samplers(&si_shader_ctx);
4214 preload_streamout_buffers(&si_shader_ctx);
4215 preload_ring_buffers(&si_shader_ctx);
4216
4217 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4218 int i;
4219 for (i = 0; i < 4; i++) {
4220 si_shader_ctx.gs_next_vertex[i] =
4221 lp_build_alloca(bld_base->base.gallivm,
4222 bld_base->uint_bld.elem_type, "");
4223 }
4224 }
4225
4226 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4227 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4228 goto out;
4229 }
4230
4231 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4232
4233 mod = bld_base->base.gallivm->module;
4234 r = si_compile_llvm(sscreen, shader, tm, mod, debug, si_shader_ctx.type);
4235 if (r) {
4236 fprintf(stderr, "LLVM failed to compile shader\n");
4237 goto out;
4238 }
4239
4240 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4241
4242 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4243 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4244 shader->gs_copy_shader->selector = shader->selector;
4245 shader->gs_copy_shader->key = shader->key;
4246 si_shader_ctx.shader = shader->gs_copy_shader;
4247 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4248 shader, dump, debug))) {
4249 free(shader->gs_copy_shader);
4250 shader->gs_copy_shader = NULL;
4251 goto out;
4252 }
4253 }
4254
4255 out:
4256 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4257 FREE(si_shader_ctx.constants[i]);
4258 if (poly_stipple)
4259 tgsi_free_tokens(tokens);
4260 return r;
4261 }
4262
4263 void si_shader_destroy(struct si_shader *shader)
4264 {
4265 if (shader->gs_copy_shader) {
4266 si_shader_destroy(shader->gs_copy_shader);
4267 FREE(shader->gs_copy_shader);
4268 }
4269
4270 if (shader->scratch_bo)
4271 r600_resource_reference(&shader->scratch_bo, NULL);
4272
4273 r600_resource_reference(&shader->bo, NULL);
4274
4275 FREE(shader->binary.code);
4276 FREE(shader->binary.relocs);
4277 FREE(shader->binary.disasm_string);
4278 }