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radeonsi: move param_offset out of shader->input[] and output[]
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_shader *shader;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config;
64 int param_streamout_write_index;
65 int param_streamout_offset[4];
66 int param_vertex_id;
67 int param_instance_id;
68 LLVMValueRef const_md;
69 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
70 LLVMValueRef ddxy_lds;
71 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
72 LLVMValueRef *resources;
73 LLVMValueRef *samplers;
74 LLVMValueRef so_buffers[4];
75 LLVMValueRef gs_next_vertex;
76 };
77
78 static struct si_shader_context * si_shader_context(
79 struct lp_build_tgsi_context * bld_base)
80 {
81 return (struct si_shader_context *)bld_base;
82 }
83
84
85 #define PERSPECTIVE_BASE 0
86 #define LINEAR_BASE 9
87
88 #define SAMPLE_OFFSET 0
89 #define CENTER_OFFSET 2
90 #define CENTROID_OFSET 4
91
92 #define USE_SGPR_MAX_SUFFIX_LEN 5
93 #define CONST_ADDR_SPACE 2
94 #define LOCAL_ADDR_SPACE 3
95 #define USER_SGPR_ADDR_SPACE 8
96
97
98 #define SENDMSG_GS 2
99 #define SENDMSG_GS_DONE 3
100
101 #define SENDMSG_GS_OP_NOP (0 << 4)
102 #define SENDMSG_GS_OP_CUT (1 << 4)
103 #define SENDMSG_GS_OP_EMIT (2 << 4)
104 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
105
106 /**
107 * Returns a unique index for a semantic name and index. The index must be
108 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
109 * calculated.
110 */
111 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
112 {
113 switch (semantic_name) {
114 case TGSI_SEMANTIC_POSITION:
115 return 0;
116 case TGSI_SEMANTIC_PSIZE:
117 return 1;
118 case TGSI_SEMANTIC_CLIPDIST:
119 assert(index <= 1);
120 return 2 + index;
121 case TGSI_SEMANTIC_CLIPVERTEX:
122 return 4;
123 case TGSI_SEMANTIC_COLOR:
124 assert(index <= 1);
125 return 5 + index;
126 case TGSI_SEMANTIC_BCOLOR:
127 assert(index <= 1);
128 return 7 + index;
129 case TGSI_SEMANTIC_FOG:
130 return 9;
131 case TGSI_SEMANTIC_EDGEFLAG:
132 return 10;
133 case TGSI_SEMANTIC_GENERIC:
134 assert(index <= 63-11);
135 return 11 + index;
136 default:
137 assert(0);
138 return 63;
139 }
140 }
141
142 /**
143 * Given a semantic name and index of a parameter and a mask of used parameters
144 * (inputs or outputs), return the index of the parameter in the list of all
145 * used parameters.
146 *
147 * For example, assume this list of parameters:
148 * POSITION, PSIZE, GENERIC0, GENERIC2
149 * which has the mask:
150 * 11000000000101
151 * Then:
152 * querying POSITION returns 0,
153 * querying PSIZE returns 1,
154 * querying GENERIC0 returns 2,
155 * querying GENERIC2 returns 3.
156 *
157 * Which can be used as an offset to a parameter buffer in units of vec4s.
158 */
159 static int get_param_index(unsigned semantic_name, unsigned index,
160 uint64_t mask)
161 {
162 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
163 int i, param_index = 0;
164
165 /* If not present... */
166 if (!((1llu << unique_index) & mask))
167 return -1;
168
169 for (i = 0; mask; i++) {
170 uint64_t bit = 1llu << i;
171
172 if (bit & mask) {
173 if (i == unique_index)
174 return param_index;
175
176 mask &= ~bit;
177 param_index++;
178 }
179 }
180
181 assert(!"unreachable");
182 return -1;
183 }
184
185 /**
186 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
187 *
188 * @param offset The offset parameter specifies the number of
189 * elements to offset, not the number of bytes or dwords. An element is the
190 * the type pointed to by the base_ptr parameter (e.g. int is the element of
191 * an int* pointer)
192 *
193 * When LLVM lowers the load instruction, it will convert the element offset
194 * into a dword offset automatically.
195 *
196 */
197 static LLVMValueRef build_indexed_load(
198 struct si_shader_context * si_shader_ctx,
199 LLVMValueRef base_ptr,
200 LLVMValueRef offset)
201 {
202 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
203
204 LLVMValueRef indices[2] = {
205 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
206 offset
207 };
208 LLVMValueRef computed_ptr = LLVMBuildGEP(
209 base->gallivm->builder, base_ptr, indices, 2, "");
210
211 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
212 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
213 return result;
214 }
215
216 static LLVMValueRef get_instance_index_for_fetch(
217 struct radeon_llvm_context * radeon_bld,
218 unsigned divisor)
219 {
220 struct si_shader_context *si_shader_ctx =
221 si_shader_context(&radeon_bld->soa.bld_base);
222 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
223
224 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
225 si_shader_ctx->param_instance_id);
226 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
227 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
228
229 if (divisor > 1)
230 result = LLVMBuildUDiv(gallivm->builder, result,
231 lp_build_const_int32(gallivm, divisor), "");
232
233 return result;
234 }
235
236 static int si_store_shader_io_attribs(struct si_shader *shader,
237 const struct tgsi_full_declaration *d)
238 {
239 int i = -1;
240
241 switch (d->Declaration.File) {
242 case TGSI_FILE_INPUT:
243 i = shader->ninput++;
244 assert(i < Elements(shader->input));
245 shader->input[i].name = d->Semantic.Name;
246 shader->input[i].sid = d->Semantic.Index;
247 shader->input[i].index = d->Range.First;
248 shader->input[i].interpolate = d->Interp.Interpolate;
249 return -1;
250
251 case TGSI_FILE_OUTPUT:
252 i = shader->noutput++;
253 assert(i < Elements(shader->output));
254 shader->output[i].name = d->Semantic.Name;
255 shader->output[i].sid = d->Semantic.Index;
256 shader->output[i].index = d->Range.First;
257 break;
258 }
259
260 return i;
261 }
262
263 static void declare_input_vs(
264 struct radeon_llvm_context *radeon_bld,
265 unsigned input_index,
266 const struct tgsi_full_declaration *decl)
267 {
268 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
269 struct gallivm_state *gallivm = base->gallivm;
270 struct si_shader_context *si_shader_ctx =
271 si_shader_context(&radeon_bld->soa.bld_base);
272 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
273
274 unsigned chan;
275
276 LLVMValueRef t_list_ptr;
277 LLVMValueRef t_offset;
278 LLVMValueRef t_list;
279 LLVMValueRef attribute_offset;
280 LLVMValueRef buffer_index;
281 LLVMValueRef args[3];
282 LLVMTypeRef vec4_type;
283 LLVMValueRef input;
284
285 /* Load the T list */
286 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
287
288 t_offset = lp_build_const_int32(gallivm, input_index);
289
290 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
291
292 /* Build the attribute offset */
293 attribute_offset = lp_build_const_int32(gallivm, 0);
294
295 if (divisor) {
296 /* Build index from instance ID, start instance and divisor */
297 si_shader_ctx->shader->uses_instanceid = true;
298 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
299 } else {
300 /* Load the buffer index for vertices. */
301 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
302 si_shader_ctx->param_vertex_id);
303 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
304 SI_PARAM_BASE_VERTEX);
305 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
306 }
307
308 vec4_type = LLVMVectorType(base->elem_type, 4);
309 args[0] = t_list;
310 args[1] = attribute_offset;
311 args[2] = buffer_index;
312 input = build_intrinsic(gallivm->builder,
313 "llvm.SI.vs.load.input", vec4_type, args, 3,
314 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
315
316 /* Break up the vec4 into individual components */
317 for (chan = 0; chan < 4; chan++) {
318 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
319 /* XXX: Use a helper function for this. There is one in
320 * tgsi_llvm.c. */
321 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
322 LLVMBuildExtractElement(gallivm->builder,
323 input, llvm_chan, "");
324 }
325 }
326
327 static void declare_input_gs(
328 struct radeon_llvm_context *radeon_bld,
329 unsigned input_index,
330 const struct tgsi_full_declaration *decl)
331 {
332 struct si_shader_context *si_shader_ctx =
333 si_shader_context(&radeon_bld->soa.bld_base);
334 struct si_shader *shader = si_shader_ctx->shader;
335
336 si_store_shader_io_attribs(shader, decl);
337 }
338
339 static LLVMValueRef fetch_input_gs(
340 struct lp_build_tgsi_context *bld_base,
341 const struct tgsi_full_src_register *reg,
342 enum tgsi_opcode_type type,
343 unsigned swizzle)
344 {
345 struct lp_build_context *base = &bld_base->base;
346 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
347 struct si_shader *shader = si_shader_ctx->shader;
348 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
349 struct gallivm_state *gallivm = base->gallivm;
350 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
351 LLVMValueRef vtx_offset;
352 LLVMValueRef t_list_ptr;
353 LLVMValueRef t_list;
354 LLVMValueRef args[9];
355 unsigned vtx_offset_param;
356 struct tgsi_shader_info *info = &shader->selector->info;
357 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
358 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
359
360 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
361 if (swizzle == 0)
362 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
363 SI_PARAM_PRIMITIVE_ID);
364 else
365 return uint->zero;
366 }
367
368 if (!reg->Register.Dimension)
369 return NULL;
370
371 if (swizzle == ~0) {
372 LLVMValueRef values[TGSI_NUM_CHANNELS];
373 unsigned chan;
374 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
375 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
376 }
377 return lp_build_gather_values(bld_base->base.gallivm, values,
378 TGSI_NUM_CHANNELS);
379 }
380
381 /* Get the vertex offset parameter */
382 vtx_offset_param = reg->Dimension.Index;
383 if (vtx_offset_param < 2) {
384 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
385 } else {
386 assert(vtx_offset_param < 6);
387 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
388 }
389 vtx_offset = lp_build_mul_imm(uint,
390 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
391 vtx_offset_param),
392 4);
393
394 /* Load the ESGS ring resource descriptor */
395 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
396 SI_PARAM_RW_BUFFERS);
397 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
398 lp_build_const_int32(gallivm, SI_RING_ESGS));
399
400 args[0] = t_list;
401 args[1] = vtx_offset;
402 args[2] = lp_build_const_int32(gallivm,
403 (get_param_index(semantic_name, semantic_index,
404 shader->selector->gs_used_inputs) * 4 +
405 swizzle) * 256);
406 args[3] = uint->zero;
407 args[4] = uint->one; /* OFFEN */
408 args[5] = uint->zero; /* IDXEN */
409 args[6] = uint->one; /* GLC */
410 args[7] = uint->zero; /* SLC */
411 args[8] = uint->zero; /* TFE */
412
413 return LLVMBuildBitCast(gallivm->builder,
414 build_intrinsic(gallivm->builder,
415 "llvm.SI.buffer.load.dword.i32.i32",
416 i32, args, 9,
417 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
418 tgsi2llvmtype(bld_base, type), "");
419 }
420
421 static void declare_input_fs(
422 struct radeon_llvm_context *radeon_bld,
423 unsigned input_index,
424 const struct tgsi_full_declaration *decl)
425 {
426 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
427 struct si_shader_context *si_shader_ctx =
428 si_shader_context(&radeon_bld->soa.bld_base);
429 struct si_shader *shader = si_shader_ctx->shader;
430 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
431 struct gallivm_state *gallivm = base->gallivm;
432 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
433 LLVMValueRef main_fn = radeon_bld->main_fn;
434
435 LLVMValueRef interp_param;
436 const char * intr_name;
437
438 /* This value is:
439 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
440 * quad begins a new primitive. Bit 0 always needs
441 * to be unset)
442 * [32:16] ParamOffset
443 *
444 */
445 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
446 LLVMValueRef attr_number;
447
448 unsigned chan;
449
450 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
451 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
452 unsigned soa_index =
453 radeon_llvm_reg_index_soa(input_index, chan);
454 radeon_bld->inputs[soa_index] =
455 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
456
457 if (chan == 3)
458 /* RCP for fragcoord.w */
459 radeon_bld->inputs[soa_index] =
460 LLVMBuildFDiv(gallivm->builder,
461 lp_build_const_float(gallivm, 1.0f),
462 radeon_bld->inputs[soa_index],
463 "");
464 }
465 return;
466 }
467
468 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
469 LLVMValueRef face, is_face_positive;
470
471 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
472
473 is_face_positive = LLVMBuildFCmp(gallivm->builder,
474 LLVMRealUGT, face,
475 lp_build_const_float(gallivm, 0.0f),
476 "");
477
478 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
479 LLVMBuildSelect(gallivm->builder,
480 is_face_positive,
481 lp_build_const_float(gallivm, 1.0f),
482 lp_build_const_float(gallivm, 0.0f),
483 "");
484 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
485 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
486 lp_build_const_float(gallivm, 0.0f);
487 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
488 lp_build_const_float(gallivm, 1.0f);
489
490 return;
491 }
492
493 shader->ps_input_param_offset[input_index] = shader->nparam++;
494 attr_number = lp_build_const_int32(gallivm,
495 shader->ps_input_param_offset[input_index]);
496
497 switch (decl->Interp.Interpolate) {
498 case TGSI_INTERPOLATE_CONSTANT:
499 interp_param = 0;
500 break;
501 case TGSI_INTERPOLATE_LINEAR:
502 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
503 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
504 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
505 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
506 else
507 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
508 break;
509 case TGSI_INTERPOLATE_COLOR:
510 if (si_shader_ctx->shader->key.ps.flatshade) {
511 interp_param = 0;
512 break;
513 }
514 /* fall through to perspective */
515 case TGSI_INTERPOLATE_PERSPECTIVE:
516 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
517 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
518 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
519 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
520 else
521 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
522 break;
523 default:
524 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
525 return;
526 }
527
528 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
529
530 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
531 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
532 si_shader_ctx->shader->key.ps.color_two_side) {
533 LLVMValueRef args[4];
534 LLVMValueRef face, is_face_positive;
535 LLVMValueRef back_attr_number =
536 lp_build_const_int32(gallivm,
537 shader->ps_input_param_offset[input_index] + 1);
538
539 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
540
541 is_face_positive = LLVMBuildFCmp(gallivm->builder,
542 LLVMRealUGT, face,
543 lp_build_const_float(gallivm, 0.0f),
544 "");
545
546 args[2] = params;
547 args[3] = interp_param;
548 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
549 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
550 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
551 LLVMValueRef front, back;
552
553 args[0] = llvm_chan;
554 args[1] = attr_number;
555 front = build_intrinsic(gallivm->builder, intr_name,
556 input_type, args, args[3] ? 4 : 3,
557 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
558
559 args[1] = back_attr_number;
560 back = build_intrinsic(gallivm->builder, intr_name,
561 input_type, args, args[3] ? 4 : 3,
562 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
563
564 radeon_bld->inputs[soa_index] =
565 LLVMBuildSelect(gallivm->builder,
566 is_face_positive,
567 front,
568 back,
569 "");
570 }
571
572 shader->nparam++;
573 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
574 LLVMValueRef args[4];
575
576 args[0] = uint->zero;
577 args[1] = attr_number;
578 args[2] = params;
579 args[3] = interp_param;
580 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
581 build_intrinsic(gallivm->builder, intr_name,
582 input_type, args, args[3] ? 4 : 3,
583 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
584 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
585 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
586 lp_build_const_float(gallivm, 0.0f);
587 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
588 lp_build_const_float(gallivm, 1.0f);
589 } else {
590 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
591 LLVMValueRef args[4];
592 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
593 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
594 args[0] = llvm_chan;
595 args[1] = attr_number;
596 args[2] = params;
597 args[3] = interp_param;
598 radeon_bld->inputs[soa_index] =
599 build_intrinsic(gallivm->builder, intr_name,
600 input_type, args, args[3] ? 4 : 3,
601 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
602 }
603 }
604 }
605
606 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
607 {
608 struct gallivm_state *gallivm = &radeon_bld->gallivm;
609 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
610 SI_PARAM_ANCILLARY);
611 value = LLVMBuildLShr(gallivm->builder, value,
612 lp_build_const_int32(gallivm, 8), "");
613 value = LLVMBuildAnd(gallivm->builder, value,
614 lp_build_const_int32(gallivm, 0xf), "");
615 return value;
616 }
617
618 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
619 LLVMValueRef offset, LLVMTypeRef return_type)
620 {
621 LLVMValueRef args[2] = {resource, offset};
622
623 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
624 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
625 }
626
627 static void declare_system_value(
628 struct radeon_llvm_context * radeon_bld,
629 unsigned index,
630 const struct tgsi_full_declaration *decl)
631 {
632 struct si_shader_context *si_shader_ctx =
633 si_shader_context(&radeon_bld->soa.bld_base);
634 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
635 struct gallivm_state *gallivm = &radeon_bld->gallivm;
636 LLVMValueRef value = 0;
637
638 switch (decl->Semantic.Name) {
639 case TGSI_SEMANTIC_INSTANCEID:
640 value = LLVMGetParam(radeon_bld->main_fn,
641 si_shader_ctx->param_instance_id);
642 break;
643
644 case TGSI_SEMANTIC_VERTEXID:
645 value = LLVMGetParam(radeon_bld->main_fn,
646 si_shader_ctx->param_vertex_id);
647 break;
648
649 case TGSI_SEMANTIC_SAMPLEID:
650 value = get_sample_id(radeon_bld);
651 break;
652
653 case TGSI_SEMANTIC_SAMPLEPOS:
654 {
655 LLVMBuilderRef builder = gallivm->builder;
656 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
657 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
658 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
659
660 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
661 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
662 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
663
664 LLVMValueRef pos[4] = {
665 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
666 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
667 lp_build_const_float(gallivm, 0),
668 lp_build_const_float(gallivm, 0)
669 };
670 value = lp_build_gather_values(gallivm, pos, 4);
671 break;
672 }
673
674 default:
675 assert(!"unknown system value");
676 return;
677 }
678
679 radeon_bld->system_values[index] = value;
680 }
681
682 static LLVMValueRef fetch_constant(
683 struct lp_build_tgsi_context * bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type,
686 unsigned swizzle)
687 {
688 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
689 struct lp_build_context * base = &bld_base->base;
690 const struct tgsi_ind_register *ireg = &reg->Indirect;
691 unsigned buf, idx;
692
693 LLVMValueRef addr;
694 LLVMValueRef result;
695
696 if (swizzle == LP_CHAN_ALL) {
697 unsigned chan;
698 LLVMValueRef values[4];
699 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
700 values[chan] = fetch_constant(bld_base, reg, type, chan);
701
702 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
703 }
704
705 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
706 idx = reg->Register.Index * 4 + swizzle;
707
708 if (!reg->Register.Indirect)
709 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
710
711 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
712 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
713 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
714 addr = lp_build_add(&bld_base->uint_bld, addr,
715 lp_build_const_int32(base->gallivm, idx * 4));
716
717 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
718 addr, base->elem_type);
719
720 return bitcast(bld_base, type, result);
721 }
722
723 /* Initialize arguments for the shader export intrinsic */
724 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
725 LLVMValueRef *values,
726 unsigned target,
727 LLVMValueRef *args)
728 {
729 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
730 struct lp_build_context *uint =
731 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
732 struct lp_build_context *base = &bld_base->base;
733 unsigned compressed = 0;
734 unsigned chan;
735
736 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
737 int cbuf = target - V_008DFC_SQ_EXP_MRT;
738
739 if (cbuf >= 0 && cbuf < 8) {
740 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
741
742 if (compressed)
743 si_shader_ctx->shader->spi_shader_col_format |=
744 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
745 else
746 si_shader_ctx->shader->spi_shader_col_format |=
747 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
748
749 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
750 }
751 }
752
753 if (compressed) {
754 /* Pixel shader needs to pack output values before export */
755 for (chan = 0; chan < 2; chan++ ) {
756 args[0] = values[2 * chan];
757 args[1] = values[2 * chan + 1];
758 args[chan + 5] =
759 build_intrinsic(base->gallivm->builder,
760 "llvm.SI.packf16",
761 LLVMInt32TypeInContext(base->gallivm->context),
762 args, 2,
763 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
764 args[chan + 7] = args[chan + 5] =
765 LLVMBuildBitCast(base->gallivm->builder,
766 args[chan + 5],
767 LLVMFloatTypeInContext(base->gallivm->context),
768 "");
769 }
770
771 /* Set COMPR flag */
772 args[4] = uint->one;
773 } else {
774 for (chan = 0; chan < 4; chan++ )
775 /* +5 because the first output value will be
776 * the 6th argument to the intrinsic. */
777 args[chan + 5] = values[chan];
778
779 /* Clear COMPR flag */
780 args[4] = uint->zero;
781 }
782
783 /* XXX: This controls which components of the output
784 * registers actually get exported. (e.g bit 0 means export
785 * X component, bit 1 means export Y component, etc.) I'm
786 * hard coding this to 0xf for now. In the future, we might
787 * want to do something else. */
788 args[0] = lp_build_const_int32(base->gallivm, 0xf);
789
790 /* Specify whether the EXEC mask represents the valid mask */
791 args[1] = uint->zero;
792
793 /* Specify whether this is the last export */
794 args[2] = uint->zero;
795
796 /* Specify the target we are exporting */
797 args[3] = lp_build_const_int32(base->gallivm, target);
798
799 /* XXX: We probably need to keep track of the output
800 * values, so we know what we are passing to the next
801 * stage. */
802 }
803
804 /* Load from output pointers and initialize arguments for the shader export intrinsic */
805 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
806 LLVMValueRef *out_ptr,
807 unsigned target,
808 LLVMValueRef *args)
809 {
810 struct gallivm_state *gallivm = bld_base->base.gallivm;
811 LLVMValueRef values[4];
812 int i;
813
814 for (i = 0; i < 4; i++)
815 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
816
817 si_llvm_init_export_args(bld_base, values, target, args);
818 }
819
820 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
821 LLVMValueRef *out_ptr)
822 {
823 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
824 struct gallivm_state *gallivm = bld_base->base.gallivm;
825
826 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
827 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
828 SI_PARAM_ALPHA_REF);
829
830 LLVMValueRef alpha_pass =
831 lp_build_cmp(&bld_base->base,
832 si_shader_ctx->shader->key.ps.alpha_func,
833 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
834 alpha_ref);
835 LLVMValueRef arg =
836 lp_build_select(&bld_base->base,
837 alpha_pass,
838 lp_build_const_float(gallivm, 1.0f),
839 lp_build_const_float(gallivm, -1.0f));
840
841 build_intrinsic(gallivm->builder,
842 "llvm.AMDGPU.kill",
843 LLVMVoidTypeInContext(gallivm->context),
844 &arg, 1, 0);
845 } else {
846 build_intrinsic(gallivm->builder,
847 "llvm.AMDGPU.kilp",
848 LLVMVoidTypeInContext(gallivm->context),
849 NULL, 0, 0);
850 }
851
852 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
853 }
854
855 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
856 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
857 {
858 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
859 struct si_shader *shader = si_shader_ctx->shader;
860 struct lp_build_context *base = &bld_base->base;
861 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
862 unsigned reg_index;
863 unsigned chan;
864 unsigned const_chan;
865 LLVMValueRef base_elt;
866 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
867 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
868 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
869
870 for (reg_index = 0; reg_index < 2; reg_index ++) {
871 LLVMValueRef *args = pos[2 + reg_index];
872
873 shader->clip_dist_write |= 0xf << (4 * reg_index);
874
875 args[5] =
876 args[6] =
877 args[7] =
878 args[8] = lp_build_const_float(base->gallivm, 0.0f);
879
880 /* Compute dot products of position and user clip plane vectors */
881 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
882 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
883 args[1] = lp_build_const_int32(base->gallivm,
884 ((reg_index * 4 + chan) * 4 +
885 const_chan) * 4);
886 base_elt = load_const(base->gallivm->builder, const_resource,
887 args[1], base->elem_type);
888 args[5 + chan] =
889 lp_build_add(base, args[5 + chan],
890 lp_build_mul(base, base_elt,
891 out_elts[const_chan]));
892 }
893 }
894
895 args[0] = lp_build_const_int32(base->gallivm, 0xf);
896 args[1] = uint->zero;
897 args[2] = uint->zero;
898 args[3] = lp_build_const_int32(base->gallivm,
899 V_008DFC_SQ_EXP_POS + 2 + reg_index);
900 args[4] = uint->zero;
901 }
902 }
903
904 static void si_dump_streamout(struct pipe_stream_output_info *so)
905 {
906 unsigned i;
907
908 if (so->num_outputs)
909 fprintf(stderr, "STREAMOUT\n");
910
911 for (i = 0; i < so->num_outputs; i++) {
912 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
913 so->output[i].start_component;
914 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
915 i, so->output[i].output_buffer,
916 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
917 so->output[i].register_index,
918 mask & 1 ? "x" : "",
919 mask & 2 ? "y" : "",
920 mask & 4 ? "z" : "",
921 mask & 8 ? "w" : "");
922 }
923 }
924
925 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
926 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
927 * or v4i32 (num_channels=3,4). */
928 static void build_tbuffer_store(struct si_shader_context *shader,
929 LLVMValueRef rsrc,
930 LLVMValueRef vdata,
931 unsigned num_channels,
932 LLVMValueRef vaddr,
933 LLVMValueRef soffset,
934 unsigned inst_offset,
935 unsigned dfmt,
936 unsigned nfmt,
937 unsigned offen,
938 unsigned idxen,
939 unsigned glc,
940 unsigned slc,
941 unsigned tfe)
942 {
943 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
944 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
945 LLVMValueRef args[] = {
946 rsrc,
947 vdata,
948 LLVMConstInt(i32, num_channels, 0),
949 vaddr,
950 soffset,
951 LLVMConstInt(i32, inst_offset, 0),
952 LLVMConstInt(i32, dfmt, 0),
953 LLVMConstInt(i32, nfmt, 0),
954 LLVMConstInt(i32, offen, 0),
955 LLVMConstInt(i32, idxen, 0),
956 LLVMConstInt(i32, glc, 0),
957 LLVMConstInt(i32, slc, 0),
958 LLVMConstInt(i32, tfe, 0)
959 };
960
961 /* The instruction offset field has 12 bits */
962 assert(offen || inst_offset < (1 << 12));
963
964 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
965 unsigned func = CLAMP(num_channels, 1, 3) - 1;
966 const char *types[] = {"i32", "v2i32", "v4i32"};
967 char name[256];
968 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
969
970 lp_build_intrinsic(gallivm->builder, name,
971 LLVMVoidTypeInContext(gallivm->context),
972 args, Elements(args));
973 }
974
975 static void build_streamout_store(struct si_shader_context *shader,
976 LLVMValueRef rsrc,
977 LLVMValueRef vdata,
978 unsigned num_channels,
979 LLVMValueRef vaddr,
980 LLVMValueRef soffset,
981 unsigned inst_offset)
982 {
983 static unsigned dfmt[] = {
984 V_008F0C_BUF_DATA_FORMAT_32,
985 V_008F0C_BUF_DATA_FORMAT_32_32,
986 V_008F0C_BUF_DATA_FORMAT_32_32_32,
987 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
988 };
989 assert(num_channels >= 1 && num_channels <= 4);
990
991 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
992 inst_offset, dfmt[num_channels-1],
993 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
994 }
995
996 /* On SI, the vertex shader is responsible for writing streamout data
997 * to buffers. */
998 static void si_llvm_emit_streamout(struct si_shader_context *shader,
999 struct si_shader_output_values *outputs,
1000 unsigned noutput)
1001 {
1002 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1003 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1004 LLVMBuilderRef builder = gallivm->builder;
1005 int i, j;
1006 struct lp_build_if_state if_ctx;
1007
1008 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1009
1010 LLVMValueRef so_param =
1011 LLVMGetParam(shader->radeon_bld.main_fn,
1012 shader->param_streamout_config);
1013
1014 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1015 LLVMValueRef so_vtx_count =
1016 LLVMBuildAnd(builder,
1017 LLVMBuildLShr(builder, so_param,
1018 LLVMConstInt(i32, 16, 0), ""),
1019 LLVMConstInt(i32, 127, 0), "");
1020
1021 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
1022 NULL, 0, LLVMReadNoneAttribute);
1023
1024 /* can_emit = tid < so_vtx_count; */
1025 LLVMValueRef can_emit =
1026 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1027
1028 /* Emit the streamout code conditionally. This actually avoids
1029 * out-of-bounds buffer access. The hw tells us via the SGPR
1030 * (so_vtx_count) which threads are allowed to emit streamout data. */
1031 lp_build_if(&if_ctx, gallivm, can_emit);
1032 {
1033 /* The buffer offset is computed as follows:
1034 * ByteOffset = streamout_offset[buffer_id]*4 +
1035 * (streamout_write_index + thread_id)*stride[buffer_id] +
1036 * attrib_offset
1037 */
1038
1039 LLVMValueRef so_write_index =
1040 LLVMGetParam(shader->radeon_bld.main_fn,
1041 shader->param_streamout_write_index);
1042
1043 /* Compute (streamout_write_index + thread_id). */
1044 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1045
1046 /* Compute the write offset for each enabled buffer. */
1047 LLVMValueRef so_write_offset[4] = {};
1048 for (i = 0; i < 4; i++) {
1049 if (!so->stride[i])
1050 continue;
1051
1052 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1053 shader->param_streamout_offset[i]);
1054 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1055
1056 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1057 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1058 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1059 }
1060
1061 /* Write streamout data. */
1062 for (i = 0; i < so->num_outputs; i++) {
1063 unsigned buf_idx = so->output[i].output_buffer;
1064 unsigned reg = so->output[i].register_index;
1065 unsigned start = so->output[i].start_component;
1066 unsigned num_comps = so->output[i].num_components;
1067 LLVMValueRef out[4];
1068
1069 assert(num_comps && num_comps <= 4);
1070 if (!num_comps || num_comps > 4)
1071 continue;
1072
1073 /* Load the output as int. */
1074 for (j = 0; j < num_comps; j++) {
1075 unsigned outidx = 0;
1076
1077 while (outidx < noutput && outputs[outidx].index != reg)
1078 outidx++;
1079
1080 if (outidx < noutput)
1081 out[j] = LLVMBuildBitCast(builder,
1082 outputs[outidx].values[start+j],
1083 i32, "");
1084 else
1085 out[j] = NULL;
1086 }
1087
1088 if (!out[0])
1089 continue;
1090
1091 /* Pack the output. */
1092 LLVMValueRef vdata = NULL;
1093
1094 switch (num_comps) {
1095 case 1: /* as i32 */
1096 vdata = out[0];
1097 break;
1098 case 2: /* as v2i32 */
1099 case 3: /* as v4i32 (aligned to 4) */
1100 case 4: /* as v4i32 */
1101 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1102 for (j = 0; j < num_comps; j++) {
1103 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1104 LLVMConstInt(i32, j, 0), "");
1105 }
1106 break;
1107 }
1108
1109 build_streamout_store(shader, shader->so_buffers[buf_idx],
1110 vdata, num_comps,
1111 so_write_offset[buf_idx],
1112 LLVMConstInt(i32, 0, 0),
1113 so->output[i].dst_offset*4);
1114 }
1115 }
1116 lp_build_endif(&if_ctx);
1117 }
1118
1119
1120 /* Generate export instructions for hardware VS shader stage */
1121 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1122 struct si_shader_output_values *outputs,
1123 unsigned noutput)
1124 {
1125 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1126 struct si_shader * shader = si_shader_ctx->shader;
1127 struct lp_build_context * base = &bld_base->base;
1128 struct lp_build_context * uint =
1129 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1130 LLVMValueRef args[9];
1131 LLVMValueRef pos_args[4][9] = { { 0 } };
1132 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1133 unsigned semantic_name, semantic_index;
1134 unsigned target;
1135 unsigned param_count = 0;
1136 unsigned pos_idx;
1137 int i;
1138
1139 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1140 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1141 }
1142
1143 for (i = 0; i < noutput; i++) {
1144 semantic_name = outputs[i].name;
1145 semantic_index = outputs[i].sid;
1146
1147 handle_semantic:
1148 /* Select the correct target */
1149 switch(semantic_name) {
1150 case TGSI_SEMANTIC_PSIZE:
1151 shader->vs_out_misc_write = true;
1152 shader->vs_out_point_size = true;
1153 psize_value = outputs[i].values[0];
1154 continue;
1155 case TGSI_SEMANTIC_EDGEFLAG:
1156 shader->vs_out_misc_write = true;
1157 shader->vs_out_edgeflag = true;
1158 edgeflag_value = outputs[i].values[0];
1159 continue;
1160 case TGSI_SEMANTIC_LAYER:
1161 shader->vs_out_misc_write = true;
1162 shader->vs_out_layer = true;
1163 layer_value = outputs[i].values[0];
1164 continue;
1165 case TGSI_SEMANTIC_POSITION:
1166 target = V_008DFC_SQ_EXP_POS;
1167 break;
1168 case TGSI_SEMANTIC_COLOR:
1169 case TGSI_SEMANTIC_BCOLOR:
1170 target = V_008DFC_SQ_EXP_PARAM + param_count;
1171 shader->vs_output_param_offset[i] = param_count;
1172 param_count++;
1173 break;
1174 case TGSI_SEMANTIC_CLIPDIST:
1175 shader->clip_dist_write |=
1176 0xf << (semantic_index * 4);
1177 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1178 break;
1179 case TGSI_SEMANTIC_CLIPVERTEX:
1180 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1181 continue;
1182 case TGSI_SEMANTIC_PRIMID:
1183 case TGSI_SEMANTIC_FOG:
1184 case TGSI_SEMANTIC_GENERIC:
1185 target = V_008DFC_SQ_EXP_PARAM + param_count;
1186 shader->vs_output_param_offset[i] = param_count;
1187 param_count++;
1188 break;
1189 default:
1190 target = 0;
1191 fprintf(stderr,
1192 "Warning: SI unhandled vs output type:%d\n",
1193 semantic_name);
1194 }
1195
1196 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1197
1198 if (target >= V_008DFC_SQ_EXP_POS &&
1199 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1200 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1201 args, sizeof(args));
1202 } else {
1203 lp_build_intrinsic(base->gallivm->builder,
1204 "llvm.SI.export",
1205 LLVMVoidTypeInContext(base->gallivm->context),
1206 args, 9);
1207 }
1208
1209 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1210 semantic_name = TGSI_SEMANTIC_GENERIC;
1211 goto handle_semantic;
1212 }
1213 }
1214
1215 /* We need to add the position output manually if it's missing. */
1216 if (!pos_args[0][0]) {
1217 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1218 pos_args[0][1] = uint->zero; /* EXEC mask */
1219 pos_args[0][2] = uint->zero; /* last export? */
1220 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1221 pos_args[0][4] = uint->zero; /* COMPR flag */
1222 pos_args[0][5] = base->zero; /* X */
1223 pos_args[0][6] = base->zero; /* Y */
1224 pos_args[0][7] = base->zero; /* Z */
1225 pos_args[0][8] = base->one; /* W */
1226 }
1227
1228 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1229 if (shader->vs_out_misc_write) {
1230 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1231 shader->vs_out_point_size |
1232 (shader->vs_out_edgeflag << 1) |
1233 (shader->vs_out_layer << 2));
1234 pos_args[1][1] = uint->zero; /* EXEC mask */
1235 pos_args[1][2] = uint->zero; /* last export? */
1236 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1237 pos_args[1][4] = uint->zero; /* COMPR flag */
1238 pos_args[1][5] = base->zero; /* X */
1239 pos_args[1][6] = base->zero; /* Y */
1240 pos_args[1][7] = base->zero; /* Z */
1241 pos_args[1][8] = base->zero; /* W */
1242
1243 if (shader->vs_out_point_size)
1244 pos_args[1][5] = psize_value;
1245
1246 if (shader->vs_out_edgeflag) {
1247 /* The output is a float, but the hw expects an integer
1248 * with the first bit containing the edge flag. */
1249 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1250 edgeflag_value,
1251 bld_base->uint_bld.elem_type, "");
1252 edgeflag_value = lp_build_min(&bld_base->int_bld,
1253 edgeflag_value,
1254 bld_base->int_bld.one);
1255
1256 /* The LLVM intrinsic expects a float. */
1257 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1258 edgeflag_value,
1259 base->elem_type, "");
1260 }
1261
1262 if (shader->vs_out_layer)
1263 pos_args[1][7] = layer_value;
1264 }
1265
1266 for (i = 0; i < 4; i++)
1267 if (pos_args[i][0])
1268 shader->nr_pos_exports++;
1269
1270 pos_idx = 0;
1271 for (i = 0; i < 4; i++) {
1272 if (!pos_args[i][0])
1273 continue;
1274
1275 /* Specify the target we are exporting */
1276 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1277
1278 if (pos_idx == shader->nr_pos_exports)
1279 /* Specify that this is the last export */
1280 pos_args[i][2] = uint->one;
1281
1282 lp_build_intrinsic(base->gallivm->builder,
1283 "llvm.SI.export",
1284 LLVMVoidTypeInContext(base->gallivm->context),
1285 pos_args[i], 9);
1286 }
1287 }
1288
1289 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1290 {
1291 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1292 struct gallivm_state *gallivm = bld_base->base.gallivm;
1293 struct si_shader *es = si_shader_ctx->shader;
1294 struct tgsi_shader_info *info = &es->selector->info;
1295 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1296 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1297 SI_PARAM_ES2GS_OFFSET);
1298 LLVMValueRef t_list_ptr;
1299 LLVMValueRef t_list;
1300 unsigned chan;
1301 int i;
1302
1303 /* Load the ESGS ring resource descriptor */
1304 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1305 SI_PARAM_RW_BUFFERS);
1306 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1307 lp_build_const_int32(gallivm, SI_RING_ESGS));
1308
1309 for (i = 0; i < info->num_outputs; i++) {
1310 LLVMValueRef *out_ptr =
1311 si_shader_ctx->radeon_bld.soa.outputs[i];
1312 int param_index = get_param_index(info->output_semantic_name[i],
1313 info->output_semantic_index[i],
1314 es->key.vs.gs_used_inputs);
1315
1316 if (param_index < 0)
1317 continue;
1318
1319 for (chan = 0; chan < 4; chan++) {
1320 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1321 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1322
1323 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1324 LLVMGetUndef(i32), soffset,
1325 (4 * param_index + chan) * 4,
1326 V_008F0C_BUF_DATA_FORMAT_32,
1327 V_008F0C_BUF_NUM_FORMAT_UINT,
1328 0, 0, 1, 1, 0);
1329 }
1330 }
1331 }
1332
1333 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1334 {
1335 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1336 struct gallivm_state *gallivm = bld_base->base.gallivm;
1337 LLVMValueRef args[2];
1338
1339 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1340 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1341 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1342 LLVMVoidTypeInContext(gallivm->context), args, 2,
1343 LLVMNoUnwindAttribute);
1344 }
1345
1346 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1347 {
1348 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1349 struct gallivm_state *gallivm = bld_base->base.gallivm;
1350 struct si_shader *shader = si_shader_ctx->shader;
1351 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1352 struct si_shader_output_values *outputs = NULL;
1353 unsigned noutput = 0;
1354 int i;
1355
1356 while (!tgsi_parse_end_of_tokens(parse)) {
1357 struct tgsi_full_declaration *d =
1358 &parse->FullToken.FullDeclaration;
1359 unsigned index;
1360
1361 tgsi_parse_token(parse);
1362
1363 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1364 continue;
1365
1366 i = si_store_shader_io_attribs(shader, d);
1367 if (i < 0)
1368 continue;
1369
1370 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1371 (noutput + 1) * sizeof(outputs[0]));
1372 for (index = d->Range.First; index <= d->Range.Last; index++) {
1373 outputs[noutput].index = index;
1374 outputs[noutput].name = d->Semantic.Name;
1375 outputs[noutput].sid = d->Semantic.Index;
1376
1377 for (i = 0; i < 4; i++)
1378 outputs[noutput].values[i] =
1379 LLVMBuildLoad(gallivm->builder,
1380 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1381 "");
1382 }
1383 noutput++;
1384 }
1385
1386 si_llvm_export_vs(bld_base, outputs, noutput);
1387 FREE(outputs);
1388 }
1389
1390 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1391 {
1392 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1393 struct si_shader * shader = si_shader_ctx->shader;
1394 struct lp_build_context * base = &bld_base->base;
1395 struct lp_build_context * uint =
1396 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1397 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1398 LLVMValueRef args[9];
1399 LLVMValueRef last_args[9] = { 0 };
1400 unsigned semantic_name;
1401 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1402 int i;
1403
1404 while (!tgsi_parse_end_of_tokens(parse)) {
1405 struct tgsi_full_declaration *d =
1406 &parse->FullToken.FullDeclaration;
1407 unsigned target;
1408 unsigned index;
1409
1410 tgsi_parse_token(parse);
1411
1412 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1413 continue;
1414
1415 i = si_store_shader_io_attribs(shader, d);
1416 if (i < 0)
1417 continue;
1418
1419 semantic_name = d->Semantic.Name;
1420 for (index = d->Range.First; index <= d->Range.Last; index++) {
1421 /* Select the correct target */
1422 switch(semantic_name) {
1423 case TGSI_SEMANTIC_POSITION:
1424 depth_index = index;
1425 continue;
1426 case TGSI_SEMANTIC_STENCIL:
1427 stencil_index = index;
1428 continue;
1429 case TGSI_SEMANTIC_SAMPLEMASK:
1430 samplemask_index = index;
1431 continue;
1432 case TGSI_SEMANTIC_COLOR:
1433 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1434 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1435 LLVMBuildStore(bld_base->base.gallivm->builder,
1436 bld_base->base.one,
1437 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1438
1439 if (d->Semantic.Index == 0 &&
1440 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1441 si_alpha_test(bld_base,
1442 si_shader_ctx->radeon_bld.soa.outputs[index]);
1443 break;
1444 default:
1445 target = 0;
1446 fprintf(stderr,
1447 "Warning: SI unhandled fs output type:%d\n",
1448 semantic_name);
1449 }
1450
1451 si_llvm_init_export_args_load(bld_base,
1452 si_shader_ctx->radeon_bld.soa.outputs[index],
1453 target, args);
1454
1455 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1456 /* If there is an export instruction waiting to be emitted, do so now. */
1457 if (last_args[0]) {
1458 lp_build_intrinsic(base->gallivm->builder,
1459 "llvm.SI.export",
1460 LLVMVoidTypeInContext(base->gallivm->context),
1461 last_args, 9);
1462 }
1463
1464 /* This instruction will be emitted at the end of the shader. */
1465 memcpy(last_args, args, sizeof(args));
1466
1467 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1468 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1469 d->Semantic.Index == 0 &&
1470 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1471 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1472 si_llvm_init_export_args_load(bld_base,
1473 si_shader_ctx->radeon_bld.soa.outputs[index],
1474 V_008DFC_SQ_EXP_MRT + c, args);
1475 lp_build_intrinsic(base->gallivm->builder,
1476 "llvm.SI.export",
1477 LLVMVoidTypeInContext(base->gallivm->context),
1478 args, 9);
1479 }
1480 }
1481 } else {
1482 lp_build_intrinsic(base->gallivm->builder,
1483 "llvm.SI.export",
1484 LLVMVoidTypeInContext(base->gallivm->context),
1485 args, 9);
1486 }
1487 }
1488 }
1489
1490 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1491 LLVMValueRef out_ptr;
1492 unsigned mask = 0;
1493
1494 /* Specify the target we are exporting */
1495 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1496
1497 args[5] = base->zero; /* R, depth */
1498 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1499 args[7] = base->zero; /* B, sample mask */
1500 args[8] = base->zero; /* A, alpha to mask */
1501
1502 if (depth_index >= 0) {
1503 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1504 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1505 mask |= 0x1;
1506 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1507 }
1508
1509 if (stencil_index >= 0) {
1510 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1511 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1512 /* Only setting the stencil component bit (0x2) here
1513 * breaks some stencil piglit tests
1514 */
1515 mask |= 0x3;
1516 si_shader_ctx->shader->db_shader_control |=
1517 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1518 }
1519
1520 if (samplemask_index >= 0) {
1521 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1522 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1523 mask |= 0xf; /* Set all components. */
1524 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1525 }
1526
1527 if (samplemask_index >= 0)
1528 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1529 else if (stencil_index >= 0)
1530 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1531 else
1532 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1533
1534 /* Specify which components to enable */
1535 args[0] = lp_build_const_int32(base->gallivm, mask);
1536
1537 args[1] =
1538 args[2] =
1539 args[4] = uint->zero;
1540
1541 if (last_args[0])
1542 lp_build_intrinsic(base->gallivm->builder,
1543 "llvm.SI.export",
1544 LLVMVoidTypeInContext(base->gallivm->context),
1545 args, 9);
1546 else
1547 memcpy(last_args, args, sizeof(args));
1548 }
1549
1550 if (!last_args[0]) {
1551 /* Specify which components to enable */
1552 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1553
1554 /* Specify the target we are exporting */
1555 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1556
1557 /* Set COMPR flag to zero to export data as 32-bit */
1558 last_args[4] = uint->zero;
1559
1560 /* dummy bits */
1561 last_args[5]= uint->zero;
1562 last_args[6]= uint->zero;
1563 last_args[7]= uint->zero;
1564 last_args[8]= uint->zero;
1565 }
1566
1567 /* Specify whether the EXEC mask represents the valid mask */
1568 last_args[1] = uint->one;
1569
1570 /* Specify that this is the last export */
1571 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1572
1573 lp_build_intrinsic(base->gallivm->builder,
1574 "llvm.SI.export",
1575 LLVMVoidTypeInContext(base->gallivm->context),
1576 last_args, 9);
1577 }
1578
1579 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1580 struct lp_build_tgsi_context * bld_base,
1581 struct lp_build_emit_data * emit_data);
1582
1583 static bool tgsi_is_shadow_sampler(unsigned target)
1584 {
1585 return target == TGSI_TEXTURE_SHADOW1D ||
1586 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1587 target == TGSI_TEXTURE_SHADOW2D ||
1588 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1589 target == TGSI_TEXTURE_SHADOWCUBE ||
1590 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1591 target == TGSI_TEXTURE_SHADOWRECT;
1592 }
1593
1594 static const struct lp_build_tgsi_action tex_action;
1595
1596 static void tex_fetch_args(
1597 struct lp_build_tgsi_context * bld_base,
1598 struct lp_build_emit_data * emit_data)
1599 {
1600 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1601 struct gallivm_state *gallivm = bld_base->base.gallivm;
1602 const struct tgsi_full_instruction * inst = emit_data->inst;
1603 unsigned opcode = inst->Instruction.Opcode;
1604 unsigned target = inst->Texture.Texture;
1605 LLVMValueRef coords[4];
1606 LLVMValueRef address[16];
1607 int ref_pos;
1608 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1609 unsigned count = 0;
1610 unsigned chan;
1611 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1612 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1613 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1614
1615 if (target == TGSI_TEXTURE_BUFFER) {
1616 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1617 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1618 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1619 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1620
1621 /* Bitcast and truncate v8i32 to v16i8. */
1622 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1623 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1624 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1625 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1626
1627 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1628 emit_data->args[0] = res;
1629 emit_data->args[1] = bld_base->uint_bld.zero;
1630 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1631 emit_data->arg_count = 3;
1632 return;
1633 }
1634
1635 /* Fetch and project texture coordinates */
1636 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1637 for (chan = 0; chan < 3; chan++ ) {
1638 coords[chan] = lp_build_emit_fetch(bld_base,
1639 emit_data->inst, 0,
1640 chan);
1641 if (opcode == TGSI_OPCODE_TXP)
1642 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1643 TGSI_OPCODE_DIV,
1644 coords[chan],
1645 coords[3]);
1646 }
1647
1648 if (opcode == TGSI_OPCODE_TXP)
1649 coords[3] = bld_base->base.one;
1650
1651 /* Pack offsets. */
1652 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1653 /* The offsets are six-bit signed integers packed like this:
1654 * X=[5:0], Y=[13:8], and Z=[21:16].
1655 */
1656 LLVMValueRef offset[3], pack;
1657
1658 assert(inst->Texture.NumOffsets == 1);
1659
1660 for (chan = 0; chan < 3; chan++) {
1661 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1662 emit_data->inst, 0, chan);
1663 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1664 lp_build_const_int32(gallivm, 0x3f), "");
1665 if (chan)
1666 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1667 lp_build_const_int32(gallivm, chan*8), "");
1668 }
1669
1670 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1671 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1672 address[count++] = pack;
1673 }
1674
1675 /* Pack LOD bias value */
1676 if (opcode == TGSI_OPCODE_TXB)
1677 address[count++] = coords[3];
1678 if (opcode == TGSI_OPCODE_TXB2)
1679 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1680
1681 /* Pack depth comparison value */
1682 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1683 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1684 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1685 } else {
1686 assert(ref_pos >= 0);
1687 address[count++] = coords[ref_pos];
1688 }
1689 }
1690
1691 if (target == TGSI_TEXTURE_CUBE ||
1692 target == TGSI_TEXTURE_CUBE_ARRAY ||
1693 target == TGSI_TEXTURE_SHADOWCUBE ||
1694 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1695 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1696
1697 /* Pack user derivatives */
1698 if (opcode == TGSI_OPCODE_TXD) {
1699 int num_deriv_channels, param;
1700
1701 switch (target) {
1702 case TGSI_TEXTURE_3D:
1703 num_deriv_channels = 3;
1704 break;
1705 case TGSI_TEXTURE_2D:
1706 case TGSI_TEXTURE_SHADOW2D:
1707 case TGSI_TEXTURE_RECT:
1708 case TGSI_TEXTURE_SHADOWRECT:
1709 case TGSI_TEXTURE_2D_ARRAY:
1710 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1711 case TGSI_TEXTURE_CUBE:
1712 case TGSI_TEXTURE_SHADOWCUBE:
1713 case TGSI_TEXTURE_CUBE_ARRAY:
1714 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1715 num_deriv_channels = 2;
1716 break;
1717 case TGSI_TEXTURE_1D:
1718 case TGSI_TEXTURE_SHADOW1D:
1719 case TGSI_TEXTURE_1D_ARRAY:
1720 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1721 num_deriv_channels = 1;
1722 break;
1723 default:
1724 assert(0); /* no other targets are valid here */
1725 }
1726
1727 for (param = 1; param <= 2; param++)
1728 for (chan = 0; chan < num_deriv_channels; chan++)
1729 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1730 }
1731
1732 /* Pack texture coordinates */
1733 address[count++] = coords[0];
1734 if (num_coords > 1)
1735 address[count++] = coords[1];
1736 if (num_coords > 2)
1737 address[count++] = coords[2];
1738
1739 /* Pack LOD or sample index */
1740 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1741 address[count++] = coords[3];
1742 else if (opcode == TGSI_OPCODE_TXL2)
1743 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1744
1745 if (count > 16) {
1746 assert(!"Cannot handle more than 16 texture address parameters");
1747 count = 16;
1748 }
1749
1750 for (chan = 0; chan < count; chan++ ) {
1751 address[chan] = LLVMBuildBitCast(gallivm->builder,
1752 address[chan],
1753 LLVMInt32TypeInContext(gallivm->context),
1754 "");
1755 }
1756
1757 /* Adjust the sample index according to FMASK.
1758 *
1759 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1760 * which is the identity mapping. Each nibble says which physical sample
1761 * should be fetched to get that sample.
1762 *
1763 * For example, 0x11111100 means there are only 2 samples stored and
1764 * the second sample covers 3/4 of the pixel. When reading samples 0
1765 * and 1, return physical sample 0 (determined by the first two 0s
1766 * in FMASK), otherwise return physical sample 1.
1767 *
1768 * The sample index should be adjusted as follows:
1769 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1770 */
1771 if (target == TGSI_TEXTURE_2D_MSAA ||
1772 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1773 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1774 struct lp_build_emit_data txf_emit_data = *emit_data;
1775 LLVMValueRef txf_address[4];
1776 unsigned txf_count = count;
1777 struct tgsi_full_instruction inst = {};
1778
1779 memcpy(txf_address, address, sizeof(txf_address));
1780
1781 if (target == TGSI_TEXTURE_2D_MSAA) {
1782 txf_address[2] = bld_base->uint_bld.zero;
1783 }
1784 txf_address[3] = bld_base->uint_bld.zero;
1785
1786 /* Pad to a power-of-two size. */
1787 while (txf_count < util_next_power_of_two(txf_count))
1788 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1789
1790 /* Read FMASK using TXF. */
1791 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1792 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1793 txf_emit_data.inst = &inst;
1794 txf_emit_data.chan = 0;
1795 txf_emit_data.dst_type = LLVMVectorType(
1796 LLVMInt32TypeInContext(gallivm->context), 4);
1797 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1798 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1799 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1800 txf_emit_data.arg_count = 3;
1801
1802 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1803
1804 /* Initialize some constants. */
1805 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1806 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1807
1808 /* Apply the formula. */
1809 LLVMValueRef fmask =
1810 LLVMBuildExtractElement(gallivm->builder,
1811 txf_emit_data.output[0],
1812 uint_bld->zero, "");
1813
1814 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1815
1816 LLVMValueRef sample_index4 =
1817 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1818
1819 LLVMValueRef shifted_fmask =
1820 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1821
1822 LLVMValueRef final_sample =
1823 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1824
1825 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1826 * resource descriptor is 0 (invalid),
1827 */
1828 LLVMValueRef fmask_desc =
1829 LLVMBuildBitCast(gallivm->builder,
1830 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1831 LLVMVectorType(uint_bld->elem_type, 8), "");
1832
1833 LLVMValueRef fmask_word1 =
1834 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1835 uint_bld->one, "");
1836
1837 LLVMValueRef word1_is_nonzero =
1838 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1839 fmask_word1, uint_bld->zero, "");
1840
1841 /* Replace the MSAA sample index. */
1842 address[sample_chan] =
1843 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1844 final_sample, address[sample_chan], "");
1845 }
1846
1847 /* Resource */
1848 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1849
1850 if (opcode == TGSI_OPCODE_TXF) {
1851 /* add tex offsets */
1852 if (inst->Texture.NumOffsets) {
1853 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1854 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1855 const struct tgsi_texture_offset * off = inst->TexOffsets;
1856
1857 assert(inst->Texture.NumOffsets == 1);
1858
1859 switch (target) {
1860 case TGSI_TEXTURE_3D:
1861 address[2] = lp_build_add(uint_bld, address[2],
1862 bld->immediates[off->Index][off->SwizzleZ]);
1863 /* fall through */
1864 case TGSI_TEXTURE_2D:
1865 case TGSI_TEXTURE_SHADOW2D:
1866 case TGSI_TEXTURE_RECT:
1867 case TGSI_TEXTURE_SHADOWRECT:
1868 case TGSI_TEXTURE_2D_ARRAY:
1869 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1870 address[1] =
1871 lp_build_add(uint_bld, address[1],
1872 bld->immediates[off->Index][off->SwizzleY]);
1873 /* fall through */
1874 case TGSI_TEXTURE_1D:
1875 case TGSI_TEXTURE_SHADOW1D:
1876 case TGSI_TEXTURE_1D_ARRAY:
1877 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1878 address[0] =
1879 lp_build_add(uint_bld, address[0],
1880 bld->immediates[off->Index][off->SwizzleX]);
1881 break;
1882 /* texture offsets do not apply to other texture targets */
1883 }
1884 }
1885
1886 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1887 emit_data->arg_count = 3;
1888
1889 emit_data->dst_type = LLVMVectorType(
1890 LLVMInt32TypeInContext(gallivm->context),
1891 4);
1892 } else if (opcode == TGSI_OPCODE_TG4 ||
1893 opcode == TGSI_OPCODE_LODQ ||
1894 has_offset) {
1895 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1896 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1897 target == TGSI_TEXTURE_2D_ARRAY ||
1898 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1899 target == TGSI_TEXTURE_CUBE_ARRAY ||
1900 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1901 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1902 unsigned dmask = 0xf;
1903
1904 if (opcode == TGSI_OPCODE_TG4) {
1905 unsigned gather_comp = 0;
1906
1907 /* DMASK was repurposed for GATHER4. 4 components are always
1908 * returned and DMASK works like a swizzle - it selects
1909 * the component to fetch. The only valid DMASK values are
1910 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1911 * (red,red,red,red) etc.) The ISA document doesn't mention
1912 * this.
1913 */
1914
1915 /* Get the component index from src1.x for Gather4. */
1916 if (!tgsi_is_shadow_sampler(target)) {
1917 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1918 LLVMValueRef comp_imm;
1919 struct tgsi_src_register src1 = inst->Src[1].Register;
1920
1921 assert(src1.File == TGSI_FILE_IMMEDIATE);
1922
1923 comp_imm = imms[src1.Index][src1.SwizzleX];
1924 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1925 gather_comp = CLAMP(gather_comp, 0, 3);
1926 }
1927
1928 dmask = 1 << gather_comp;
1929 }
1930
1931 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1932 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1933 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1934 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1935 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1936 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1937 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1938 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1939 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1940
1941 emit_data->arg_count = 11;
1942
1943 emit_data->dst_type = LLVMVectorType(
1944 LLVMFloatTypeInContext(gallivm->context),
1945 4);
1946 } else {
1947 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1948 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1949 emit_data->arg_count = 4;
1950
1951 emit_data->dst_type = LLVMVectorType(
1952 LLVMFloatTypeInContext(gallivm->context),
1953 4);
1954 }
1955
1956 /* The fetch opcode has been converted to a 2D array fetch.
1957 * This simplifies the LLVM backend. */
1958 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1959 target = TGSI_TEXTURE_2D_ARRAY;
1960 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1961 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1962
1963 /* Pad to power of two vector */
1964 while (count < util_next_power_of_two(count))
1965 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1966
1967 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1968 }
1969
1970 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1971 struct lp_build_tgsi_context * bld_base,
1972 struct lp_build_emit_data * emit_data)
1973 {
1974 struct lp_build_context * base = &bld_base->base;
1975 unsigned opcode = emit_data->inst->Instruction.Opcode;
1976 unsigned target = emit_data->inst->Texture.Texture;
1977 char intr_name[127];
1978 bool has_offset = HAVE_LLVM >= 0x0305 ?
1979 emit_data->inst->Texture.NumOffsets > 0 : false;
1980
1981 if (target == TGSI_TEXTURE_BUFFER) {
1982 emit_data->output[emit_data->chan] = build_intrinsic(
1983 base->gallivm->builder,
1984 "llvm.SI.vs.load.input", emit_data->dst_type,
1985 emit_data->args, emit_data->arg_count,
1986 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1987 return;
1988 }
1989
1990 if (opcode == TGSI_OPCODE_TG4 ||
1991 opcode == TGSI_OPCODE_LODQ ||
1992 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1993 bool is_shadow = tgsi_is_shadow_sampler(target);
1994 const char *name = "llvm.SI.image.sample";
1995 const char *infix = "";
1996
1997 switch (opcode) {
1998 case TGSI_OPCODE_TEX:
1999 case TGSI_OPCODE_TEX2:
2000 case TGSI_OPCODE_TXP:
2001 break;
2002 case TGSI_OPCODE_TXB:
2003 case TGSI_OPCODE_TXB2:
2004 infix = ".b";
2005 break;
2006 case TGSI_OPCODE_TXL:
2007 case TGSI_OPCODE_TXL2:
2008 infix = ".l";
2009 break;
2010 case TGSI_OPCODE_TXD:
2011 infix = ".d";
2012 break;
2013 case TGSI_OPCODE_TG4:
2014 name = "llvm.SI.gather4";
2015 break;
2016 case TGSI_OPCODE_LODQ:
2017 name = "llvm.SI.getlod";
2018 is_shadow = false;
2019 has_offset = false;
2020 break;
2021 default:
2022 assert(0);
2023 return;
2024 }
2025
2026 /* Add the type and suffixes .c, .o if needed. */
2027 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
2028 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
2029 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2030
2031 emit_data->output[emit_data->chan] = build_intrinsic(
2032 base->gallivm->builder, intr_name, emit_data->dst_type,
2033 emit_data->args, emit_data->arg_count,
2034 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2035 } else {
2036 LLVMTypeRef i8, v16i8, v32i8;
2037 const char *name;
2038
2039 switch (opcode) {
2040 case TGSI_OPCODE_TEX:
2041 case TGSI_OPCODE_TEX2:
2042 case TGSI_OPCODE_TXP:
2043 name = "llvm.SI.sample";
2044 break;
2045 case TGSI_OPCODE_TXB:
2046 case TGSI_OPCODE_TXB2:
2047 name = "llvm.SI.sampleb";
2048 break;
2049 case TGSI_OPCODE_TXD:
2050 name = "llvm.SI.sampled";
2051 break;
2052 case TGSI_OPCODE_TXF:
2053 name = "llvm.SI.imageload";
2054 break;
2055 case TGSI_OPCODE_TXL:
2056 case TGSI_OPCODE_TXL2:
2057 name = "llvm.SI.samplel";
2058 break;
2059 default:
2060 assert(0);
2061 return;
2062 }
2063
2064 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2065 v16i8 = LLVMVectorType(i8, 16);
2066 v32i8 = LLVMVectorType(i8, 32);
2067
2068 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2069 emit_data->args[1], v32i8, "");
2070 if (opcode != TGSI_OPCODE_TXF) {
2071 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2072 emit_data->args[2], v16i8, "");
2073 }
2074
2075 sprintf(intr_name, "%s.v%ui32", name,
2076 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2077
2078 emit_data->output[emit_data->chan] = build_intrinsic(
2079 base->gallivm->builder, intr_name, emit_data->dst_type,
2080 emit_data->args, emit_data->arg_count,
2081 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2082 }
2083 }
2084
2085 static void txq_fetch_args(
2086 struct lp_build_tgsi_context * bld_base,
2087 struct lp_build_emit_data * emit_data)
2088 {
2089 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2090 const struct tgsi_full_instruction *inst = emit_data->inst;
2091 struct gallivm_state *gallivm = bld_base->base.gallivm;
2092 unsigned target = inst->Texture.Texture;
2093
2094 if (target == TGSI_TEXTURE_BUFFER) {
2095 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2096 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2097
2098 /* Read the size from the buffer descriptor directly. */
2099 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2100 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2101 size = LLVMBuildExtractElement(gallivm->builder, size,
2102 lp_build_const_int32(gallivm, 2), "");
2103 emit_data->args[0] = size;
2104 return;
2105 }
2106
2107 /* Mip level */
2108 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2109
2110 /* Resource */
2111 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2112
2113 /* Texture target */
2114 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2115 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2116 target = TGSI_TEXTURE_2D_ARRAY;
2117
2118 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2119 target);
2120
2121 emit_data->arg_count = 3;
2122
2123 emit_data->dst_type = LLVMVectorType(
2124 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2125 4);
2126 }
2127
2128 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2129 struct lp_build_tgsi_context * bld_base,
2130 struct lp_build_emit_data * emit_data)
2131 {
2132 unsigned target = emit_data->inst->Texture.Texture;
2133
2134 if (target == TGSI_TEXTURE_BUFFER) {
2135 /* Just return the buffer size. */
2136 emit_data->output[emit_data->chan] = emit_data->args[0];
2137 return;
2138 }
2139
2140 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2141
2142 /* Divide the number of layers by 6 to get the number of cubes. */
2143 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2144 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2145 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2146 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2147 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2148
2149 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2150 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2151 z = LLVMBuildSDiv(builder, z, six, "");
2152
2153 emit_data->output[emit_data->chan] =
2154 LLVMBuildInsertElement(builder, v4, z, two, "");
2155 }
2156 }
2157
2158 static void si_llvm_emit_ddxy(
2159 const struct lp_build_tgsi_action * action,
2160 struct lp_build_tgsi_context * bld_base,
2161 struct lp_build_emit_data * emit_data)
2162 {
2163 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2164 struct gallivm_state *gallivm = bld_base->base.gallivm;
2165 struct lp_build_context * base = &bld_base->base;
2166 const struct tgsi_full_instruction *inst = emit_data->inst;
2167 unsigned opcode = inst->Instruction.Opcode;
2168 LLVMValueRef indices[2];
2169 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2170 LLVMValueRef tl, trbl, result[4];
2171 LLVMTypeRef i32;
2172 unsigned swizzle[4];
2173 unsigned c;
2174
2175 i32 = LLVMInt32TypeInContext(gallivm->context);
2176
2177 indices[0] = bld_base->uint_bld.zero;
2178 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2179 NULL, 0, LLVMReadNoneAttribute);
2180 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2181 indices, 2, "");
2182
2183 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2184 lp_build_const_int32(gallivm, 0xfffffffc), "");
2185 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2186 indices, 2, "");
2187
2188 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2189 lp_build_const_int32(gallivm,
2190 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2191 "");
2192 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2193 indices, 2, "");
2194
2195 for (c = 0; c < 4; ++c) {
2196 unsigned i;
2197
2198 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2199 for (i = 0; i < c; ++i) {
2200 if (swizzle[i] == swizzle[c]) {
2201 result[c] = result[i];
2202 break;
2203 }
2204 }
2205 if (i != c)
2206 continue;
2207
2208 LLVMBuildStore(gallivm->builder,
2209 LLVMBuildBitCast(gallivm->builder,
2210 lp_build_emit_fetch(bld_base, inst, 0, c),
2211 i32, ""),
2212 store_ptr);
2213
2214 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2215 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2216
2217 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2218 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2219
2220 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2221 }
2222
2223 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2224 }
2225
2226 /* Emit one vertex from the geometry shader */
2227 static void si_llvm_emit_vertex(
2228 const struct lp_build_tgsi_action *action,
2229 struct lp_build_tgsi_context *bld_base,
2230 struct lp_build_emit_data *emit_data)
2231 {
2232 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2233 struct lp_build_context *uint = &bld_base->uint_bld;
2234 struct si_shader *shader = si_shader_ctx->shader;
2235 struct tgsi_shader_info *info = &shader->selector->info;
2236 struct gallivm_state *gallivm = bld_base->base.gallivm;
2237 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2238 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2239 SI_PARAM_GS2VS_OFFSET);
2240 LLVMValueRef gs_next_vertex;
2241 LLVMValueRef can_emit, kill;
2242 LLVMValueRef t_list_ptr;
2243 LLVMValueRef t_list;
2244 LLVMValueRef args[2];
2245 unsigned chan;
2246 int i;
2247
2248 /* Load the GSVS ring resource descriptor */
2249 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2250 SI_PARAM_RW_BUFFERS);
2251 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2252 lp_build_const_int32(gallivm, SI_RING_GSVS));
2253
2254 if (shader->noutput == 0) {
2255 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
2256
2257 while (!tgsi_parse_end_of_tokens(parse)) {
2258 tgsi_parse_token(parse);
2259
2260 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
2261 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
2262
2263 if (d->Declaration.File == TGSI_FILE_OUTPUT)
2264 si_store_shader_io_attribs(shader, d);
2265 }
2266 }
2267 }
2268
2269 /* Write vertex attribute values to GSVS ring */
2270 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2271
2272 /* If this thread has already emitted the declared maximum number of
2273 * vertices, kill it: excessive vertex emissions are not supposed to
2274 * have any effect, and GS threads have no externally observable
2275 * effects other than emitting vertices.
2276 */
2277 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2278 lp_build_const_int32(gallivm,
2279 shader->selector->gs_max_out_vertices), "");
2280 kill = lp_build_select(&bld_base->base, can_emit,
2281 lp_build_const_float(gallivm, 1.0f),
2282 lp_build_const_float(gallivm, -1.0f));
2283 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2284 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2285
2286 for (i = 0; i < info->num_outputs; i++) {
2287 LLVMValueRef *out_ptr =
2288 si_shader_ctx->radeon_bld.soa.outputs[i];
2289
2290 for (chan = 0; chan < 4; chan++) {
2291 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2292 LLVMValueRef voffset =
2293 lp_build_const_int32(gallivm, (i * 4 + chan) *
2294 shader->selector->gs_max_out_vertices);
2295
2296 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2297 voffset = lp_build_mul_imm(uint, voffset, 4);
2298
2299 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2300
2301 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2302 voffset, soffset, 0,
2303 V_008F0C_BUF_DATA_FORMAT_32,
2304 V_008F0C_BUF_NUM_FORMAT_UINT,
2305 1, 0, 1, 1, 0);
2306 }
2307 }
2308 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2309 lp_build_const_int32(gallivm, 1));
2310 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2311
2312 /* Signal vertex emission */
2313 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2314 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2315 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2316 LLVMVoidTypeInContext(gallivm->context), args, 2,
2317 LLVMNoUnwindAttribute);
2318 }
2319
2320 /* Cut one primitive from the geometry shader */
2321 static void si_llvm_emit_primitive(
2322 const struct lp_build_tgsi_action *action,
2323 struct lp_build_tgsi_context *bld_base,
2324 struct lp_build_emit_data *emit_data)
2325 {
2326 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2327 struct gallivm_state *gallivm = bld_base->base.gallivm;
2328 LLVMValueRef args[2];
2329
2330 /* Signal primitive cut */
2331 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2332 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2333 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2334 LLVMVoidTypeInContext(gallivm->context), args, 2,
2335 LLVMNoUnwindAttribute);
2336 }
2337
2338 static const struct lp_build_tgsi_action tex_action = {
2339 .fetch_args = tex_fetch_args,
2340 .emit = build_tex_intrinsic,
2341 };
2342
2343 static const struct lp_build_tgsi_action txq_action = {
2344 .fetch_args = txq_fetch_args,
2345 .emit = build_txq_intrinsic,
2346 .intr_name = "llvm.SI.resinfo"
2347 };
2348
2349 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2350 {
2351 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2352 LLVMValueRef args[3];
2353
2354 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2355 args[1] = 0;
2356 args[2] = lp_build_const_int32(gallivm, 1);
2357
2358 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2359 }
2360
2361 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2362 {
2363 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2364 CONST_ADDR_SPACE);
2365 }
2366
2367 static void create_function(struct si_shader_context *si_shader_ctx)
2368 {
2369 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2370 struct gallivm_state *gallivm = bld_base->base.gallivm;
2371 struct si_shader *shader = si_shader_ctx->shader;
2372 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2373 unsigned i, last_array_pointer, last_sgpr, num_params;
2374
2375 i8 = LLVMInt8TypeInContext(gallivm->context);
2376 i32 = LLVMInt32TypeInContext(gallivm->context);
2377 f32 = LLVMFloatTypeInContext(gallivm->context);
2378 v2i32 = LLVMVectorType(i32, 2);
2379 v3i32 = LLVMVectorType(i32, 3);
2380 v4i32 = LLVMVectorType(i32, 4);
2381 v8i32 = LLVMVectorType(i32, 8);
2382 v16i8 = LLVMVectorType(i8, 16);
2383
2384 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2385 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2386 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2387 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2388 last_array_pointer = SI_PARAM_RESOURCE;
2389
2390 switch (si_shader_ctx->type) {
2391 case TGSI_PROCESSOR_VERTEX:
2392 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2393 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2394 params[SI_PARAM_BASE_VERTEX] = i32;
2395 params[SI_PARAM_START_INSTANCE] = i32;
2396 num_params = SI_PARAM_START_INSTANCE+1;
2397
2398 if (shader->key.vs.as_es) {
2399 params[SI_PARAM_ES2GS_OFFSET] = i32;
2400 num_params++;
2401 } else {
2402 if (shader->is_gs_copy_shader) {
2403 last_array_pointer = SI_PARAM_CONST;
2404 num_params = SI_PARAM_CONST+1;
2405 }
2406
2407 /* The locations of the other parameters are assigned dynamically. */
2408
2409 /* Streamout SGPRs. */
2410 if (shader->selector->so.num_outputs) {
2411 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2412 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2413 }
2414 /* A streamout buffer offset is loaded if the stride is non-zero. */
2415 for (i = 0; i < 4; i++) {
2416 if (!shader->selector->so.stride[i])
2417 continue;
2418
2419 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2420 }
2421 }
2422
2423 last_sgpr = num_params-1;
2424
2425 /* VGPRs */
2426 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2427 params[num_params++] = i32; /* unused*/
2428 params[num_params++] = i32; /* unused */
2429 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2430 break;
2431
2432 case TGSI_PROCESSOR_GEOMETRY:
2433 params[SI_PARAM_GS2VS_OFFSET] = i32;
2434 params[SI_PARAM_GS_WAVE_ID] = i32;
2435 last_sgpr = SI_PARAM_GS_WAVE_ID;
2436
2437 /* VGPRs */
2438 params[SI_PARAM_VTX0_OFFSET] = i32;
2439 params[SI_PARAM_VTX1_OFFSET] = i32;
2440 params[SI_PARAM_PRIMITIVE_ID] = i32;
2441 params[SI_PARAM_VTX2_OFFSET] = i32;
2442 params[SI_PARAM_VTX3_OFFSET] = i32;
2443 params[SI_PARAM_VTX4_OFFSET] = i32;
2444 params[SI_PARAM_VTX5_OFFSET] = i32;
2445 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2446 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2447 break;
2448
2449 case TGSI_PROCESSOR_FRAGMENT:
2450 params[SI_PARAM_ALPHA_REF] = f32;
2451 params[SI_PARAM_PRIM_MASK] = i32;
2452 last_sgpr = SI_PARAM_PRIM_MASK;
2453 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2454 params[SI_PARAM_PERSP_CENTER] = v2i32;
2455 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2456 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2457 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2458 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2459 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2460 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2461 params[SI_PARAM_POS_X_FLOAT] = f32;
2462 params[SI_PARAM_POS_Y_FLOAT] = f32;
2463 params[SI_PARAM_POS_Z_FLOAT] = f32;
2464 params[SI_PARAM_POS_W_FLOAT] = f32;
2465 params[SI_PARAM_FRONT_FACE] = f32;
2466 params[SI_PARAM_ANCILLARY] = i32;
2467 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2468 params[SI_PARAM_POS_FIXED_PT] = f32;
2469 num_params = SI_PARAM_POS_FIXED_PT+1;
2470 break;
2471
2472 default:
2473 assert(0 && "unimplemented shader");
2474 return;
2475 }
2476
2477 assert(num_params <= Elements(params));
2478 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2479 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2480
2481 for (i = 0; i <= last_sgpr; ++i) {
2482 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2483
2484 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2485 * to move load. Inputs are constant so this is fine. */
2486 if (i <= last_array_pointer)
2487 LLVMAddAttribute(P, LLVMByValAttribute);
2488 else
2489 LLVMAddAttribute(P, LLVMInRegAttribute);
2490 }
2491
2492 if (bld_base->info &&
2493 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2494 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2495 si_shader_ctx->ddxy_lds =
2496 LLVMAddGlobalInAddressSpace(gallivm->module,
2497 LLVMArrayType(i32, 64),
2498 "ddxy_lds",
2499 LOCAL_ADDR_SPACE);
2500 }
2501
2502 static void preload_constants(struct si_shader_context *si_shader_ctx)
2503 {
2504 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2505 struct gallivm_state * gallivm = bld_base->base.gallivm;
2506 const struct tgsi_shader_info * info = bld_base->info;
2507 unsigned buf;
2508 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2509
2510 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2511 unsigned i, num_const = info->const_file_max[buf] + 1;
2512
2513 if (num_const == 0)
2514 continue;
2515
2516 /* Allocate space for the constant values */
2517 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2518
2519 /* Load the resource descriptor */
2520 si_shader_ctx->const_resource[buf] =
2521 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2522
2523 /* Load the constants, we rely on the code sinking to do the rest */
2524 for (i = 0; i < num_const * 4; ++i) {
2525 si_shader_ctx->constants[buf][i] =
2526 load_const(gallivm->builder,
2527 si_shader_ctx->const_resource[buf],
2528 lp_build_const_int32(gallivm, i * 4),
2529 bld_base->base.elem_type);
2530 }
2531 }
2532 }
2533
2534 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2535 {
2536 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2537 struct gallivm_state * gallivm = bld_base->base.gallivm;
2538 const struct tgsi_shader_info * info = bld_base->info;
2539
2540 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2541
2542 LLVMValueRef res_ptr, samp_ptr;
2543 LLVMValueRef offset;
2544
2545 if (num_samplers == 0)
2546 return;
2547
2548 /* Allocate space for the values */
2549 si_shader_ctx->resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2550 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2551
2552 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2553 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2554
2555 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2556 for (i = 0; i < num_samplers; ++i) {
2557 /* Resource */
2558 offset = lp_build_const_int32(gallivm, i);
2559 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2560
2561 /* Sampler */
2562 offset = lp_build_const_int32(gallivm, i);
2563 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2564
2565 /* FMASK resource */
2566 if (info->is_msaa_sampler[i]) {
2567 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2568 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2569 build_indexed_load(si_shader_ctx, res_ptr, offset);
2570 }
2571 }
2572 }
2573
2574 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2575 {
2576 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2577 struct gallivm_state * gallivm = bld_base->base.gallivm;
2578 unsigned i;
2579
2580 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2581 si_shader_ctx->shader->key.vs.as_es ||
2582 !si_shader_ctx->shader->selector->so.num_outputs)
2583 return;
2584
2585 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2586 SI_PARAM_RW_BUFFERS);
2587
2588 /* Load the resources, we rely on the code sinking to do the rest */
2589 for (i = 0; i < 4; ++i) {
2590 if (si_shader_ctx->shader->selector->so.stride[i]) {
2591 LLVMValueRef offset = lp_build_const_int32(gallivm,
2592 SI_SO_BUF_OFFSET + i);
2593
2594 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2595 }
2596 }
2597 }
2598
2599 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2600 LLVMModuleRef mod)
2601 {
2602 unsigned r; /* llvm_compile result */
2603 unsigned i;
2604 unsigned char *ptr;
2605 struct radeon_shader_binary binary;
2606 bool dump = r600_can_dump_shader(&sscreen->b,
2607 shader->selector ? shader->selector->tokens : NULL);
2608 const char * gpu_family = r600_get_llvm_processor_name(sscreen->b.family);
2609 unsigned code_size;
2610
2611 /* Use LLVM to compile shader */
2612 memset(&binary, 0, sizeof(binary));
2613 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2614
2615 /* Output binary dump if rscreen->debug_flags are set */
2616 if (dump && ! binary.disassembled) {
2617 fprintf(stderr, "SI CODE:\n");
2618 for (i = 0; i < binary.code_size; i+=4 ) {
2619 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2620 binary.code[i + 2], binary.code[i + 1],
2621 binary.code[i]);
2622 }
2623 }
2624
2625 /* XXX: We may be able to emit some of these values directly rather than
2626 * extracting fields to be emitted later.
2627 */
2628 /* Parse config data in compiled binary */
2629 for (i = 0; i < binary.config_size; i+= 8) {
2630 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2631 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2632 switch (reg) {
2633 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2634 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2635 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2636 case R_00B848_COMPUTE_PGM_RSRC1:
2637 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2638 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2639 break;
2640 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2641 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2642 break;
2643 case R_00B84C_COMPUTE_PGM_RSRC2:
2644 shader->lds_size = G_00B84C_LDS_SIZE(value);
2645 break;
2646 case R_0286CC_SPI_PS_INPUT_ENA:
2647 shader->spi_ps_input_ena = value;
2648 break;
2649 case R_00B860_COMPUTE_TMPRING_SIZE:
2650 /* WAVESIZE is in units of 256 dwords. */
2651 shader->scratch_bytes_per_wave =
2652 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2653 break;
2654 default:
2655 fprintf(stderr, "Warning: Compiler emitted unknown "
2656 "config register: 0x%x\n", reg);
2657 break;
2658 }
2659 }
2660
2661 /* copy new shader */
2662 code_size = binary.code_size + binary.rodata_size;
2663 r600_resource_reference(&shader->bo, NULL);
2664 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2665 code_size);
2666 if (shader->bo == NULL) {
2667 return -ENOMEM;
2668 }
2669
2670 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
2671 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2672 if (binary.rodata_size > 0) {
2673 ptr += binary.code_size;
2674 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2675 }
2676
2677 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2678
2679 free(binary.code);
2680 free(binary.config);
2681 free(binary.rodata);
2682
2683 return r;
2684 }
2685
2686 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2687 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2688 struct si_shader_context *si_shader_ctx,
2689 struct si_shader *gs, bool dump)
2690 {
2691 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2692 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2693 struct lp_build_context *base = &bld_base->base;
2694 struct lp_build_context *uint = &bld_base->uint_bld;
2695 struct si_shader *shader = si_shader_ctx->shader;
2696 struct si_shader_output_values *outputs;
2697 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2698 LLVMValueRef t_list_ptr, t_list;
2699 LLVMValueRef args[9];
2700 int i, r;
2701
2702 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2703
2704 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2705 shader->is_gs_copy_shader = true;
2706
2707 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2708
2709 create_meta_data(si_shader_ctx);
2710 create_function(si_shader_ctx);
2711 preload_streamout_buffers(si_shader_ctx);
2712
2713 /* Load the GSVS ring resource descriptor */
2714 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2715 SI_PARAM_RW_BUFFERS);
2716 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2717 lp_build_const_int32(gallivm, SI_RING_GSVS));
2718
2719 args[0] = t_list;
2720 args[1] = lp_build_mul_imm(uint,
2721 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2722 si_shader_ctx->param_vertex_id),
2723 4);
2724 args[3] = uint->zero;
2725 args[4] = uint->one; /* OFFEN */
2726 args[5] = uint->zero; /* IDXEN */
2727 args[6] = uint->one; /* GLC */
2728 args[7] = uint->one; /* SLC */
2729 args[8] = uint->zero; /* TFE */
2730
2731 /* Fetch vertex data from GSVS ring */
2732 for (i = 0; i < gsinfo->num_outputs; ++i) {
2733 unsigned chan;
2734
2735 outputs[i].name = gsinfo->output_semantic_name[i];
2736 outputs[i].index = i;
2737 outputs[i].sid = gsinfo->output_semantic_index[i];
2738
2739 for (chan = 0; chan < 4; chan++) {
2740 args[2] = lp_build_const_int32(gallivm,
2741 (i * 4 + chan) *
2742 gs->selector->gs_max_out_vertices * 16 * 4);
2743
2744 outputs[i].values[chan] =
2745 LLVMBuildBitCast(gallivm->builder,
2746 build_intrinsic(gallivm->builder,
2747 "llvm.SI.buffer.load.dword.i32.i32",
2748 LLVMInt32TypeInContext(gallivm->context),
2749 args, 9,
2750 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2751 base->elem_type, "");
2752 }
2753 }
2754
2755 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2756
2757 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2758
2759 if (dump)
2760 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2761
2762 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2763 bld_base->base.gallivm->module);
2764
2765 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2766
2767 FREE(outputs);
2768 return r;
2769 }
2770
2771 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2772 {
2773 struct si_shader_selector *sel = shader->selector;
2774 struct si_shader_context si_shader_ctx;
2775 struct lp_build_tgsi_context * bld_base;
2776 LLVMModuleRef mod;
2777 int r = 0;
2778 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2779
2780 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2781 * conversion fails. */
2782 if (dump) {
2783 tgsi_dump(sel->tokens, 0);
2784 si_dump_streamout(&sel->so);
2785 }
2786
2787 assert(shader->noutput == 0);
2788 assert(shader->nparam == 0);
2789 assert(shader->ninput == 0);
2790
2791 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2792 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2793 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2794
2795 if (sel->info.uses_kill)
2796 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2797
2798 shader->uses_instanceid = sel->info.uses_instanceid;
2799 bld_base->info = &sel->info;
2800 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2801
2802 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2803 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2804 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2805 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2806 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2807 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2808 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2809 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2810 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2811 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2812 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2813 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2814
2815 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2816 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2817
2818 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2819 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2820
2821 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2822 si_shader_ctx.tokens = sel->tokens;
2823 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2824 si_shader_ctx.shader = shader;
2825 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2826
2827 switch (si_shader_ctx.type) {
2828 case TGSI_PROCESSOR_VERTEX:
2829 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2830 if (shader->key.vs.as_es) {
2831 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2832 } else {
2833 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2834 }
2835 break;
2836 case TGSI_PROCESSOR_GEOMETRY:
2837 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2838 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2839 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2840 break;
2841 case TGSI_PROCESSOR_FRAGMENT:
2842 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2843 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2844
2845 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2846 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2847 shader->db_shader_control |=
2848 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2849 break;
2850 case TGSI_FS_DEPTH_LAYOUT_LESS:
2851 shader->db_shader_control |=
2852 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2853 break;
2854 }
2855 break;
2856 default:
2857 assert(!"Unsupported shader type");
2858 return -1;
2859 }
2860
2861 create_meta_data(&si_shader_ctx);
2862 create_function(&si_shader_ctx);
2863 preload_constants(&si_shader_ctx);
2864 preload_samplers(&si_shader_ctx);
2865 preload_streamout_buffers(&si_shader_ctx);
2866
2867 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2868 si_shader_ctx.gs_next_vertex =
2869 lp_build_alloca(bld_base->base.gallivm,
2870 bld_base->uint_bld.elem_type, "");
2871 }
2872
2873 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2874 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2875 goto out;
2876 }
2877
2878 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2879
2880 mod = bld_base->base.gallivm->module;
2881 r = si_compile_llvm(sscreen, shader, mod);
2882 if (r) {
2883 fprintf(stderr, "LLVM failed to compile shader\n");
2884 goto out;
2885 }
2886
2887 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2888
2889 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2890 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2891 shader->gs_copy_shader->selector = shader->selector;
2892 shader->gs_copy_shader->key = shader->key;
2893 si_shader_ctx.shader = shader->gs_copy_shader;
2894 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2895 shader, dump))) {
2896 free(shader->gs_copy_shader);
2897 shader->gs_copy_shader = NULL;
2898 goto out;
2899 }
2900 }
2901
2902 tgsi_parse_free(&si_shader_ctx.parse);
2903
2904 out:
2905 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2906 FREE(si_shader_ctx.constants[i]);
2907 FREE(si_shader_ctx.resources);
2908 FREE(si_shader_ctx.samplers);
2909
2910 return r;
2911 }
2912
2913 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2914 {
2915 if (shader->gs_copy_shader)
2916 si_shader_destroy(ctx, shader->gs_copy_shader);
2917
2918 r600_resource_reference(&shader->bo, NULL);
2919 r600_resource_reference(&shader->scratch_bo, NULL);
2920 }