2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
43 #include "si_shader.h"
48 struct si_shader_output_values
50 LLVMValueRef values
[4];
57 struct si_shader_context
59 struct radeon_llvm_context radeon_bld
;
60 struct tgsi_parse_context parse
;
61 struct tgsi_token
* tokens
;
62 struct si_shader
*shader
;
63 struct si_shader
*gs_for_vs
;
64 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
65 int param_streamout_config
;
66 int param_streamout_write_index
;
67 int param_streamout_offset
[4];
69 int param_instance_id
;
70 LLVMValueRef const_md
;
71 LLVMValueRef const_resource
[SI_NUM_CONST_BUFFERS
];
72 LLVMValueRef ddxy_lds
;
73 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
74 LLVMValueRef
*resources
;
75 LLVMValueRef
*samplers
;
76 LLVMValueRef so_buffers
[4];
77 LLVMValueRef gs_next_vertex
;
80 static struct si_shader_context
* si_shader_context(
81 struct lp_build_tgsi_context
* bld_base
)
83 return (struct si_shader_context
*)bld_base
;
87 #define PERSPECTIVE_BASE 0
90 #define SAMPLE_OFFSET 0
91 #define CENTER_OFFSET 2
92 #define CENTROID_OFSET 4
94 #define USE_SGPR_MAX_SUFFIX_LEN 5
95 #define CONST_ADDR_SPACE 2
96 #define LOCAL_ADDR_SPACE 3
97 #define USER_SGPR_ADDR_SPACE 8
101 #define SENDMSG_GS_DONE 3
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
110 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
112 * @param offset The offset parameter specifies the number of
113 * elements to offset, not the number of bytes or dwords. An element is the
114 * the type pointed to by the base_ptr parameter (e.g. int is the element of
117 * When LLVM lowers the load instruction, it will convert the element offset
118 * into a dword offset automatically.
121 static LLVMValueRef
build_indexed_load(
122 struct si_shader_context
* si_shader_ctx
,
123 LLVMValueRef base_ptr
,
126 struct lp_build_context
* base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
128 LLVMValueRef indices
[2] = {
129 LLVMConstInt(LLVMInt64TypeInContext(base
->gallivm
->context
), 0, false),
132 LLVMValueRef computed_ptr
= LLVMBuildGEP(
133 base
->gallivm
->builder
, base_ptr
, indices
, 2, "");
135 LLVMValueRef result
= LLVMBuildLoad(base
->gallivm
->builder
, computed_ptr
, "");
136 LLVMSetMetadata(result
, 1, si_shader_ctx
->const_md
);
140 static LLVMValueRef
get_instance_index_for_fetch(
141 struct radeon_llvm_context
* radeon_bld
,
144 struct si_shader_context
*si_shader_ctx
=
145 si_shader_context(&radeon_bld
->soa
.bld_base
);
146 struct gallivm_state
* gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
148 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
149 si_shader_ctx
->param_instance_id
);
150 result
= LLVMBuildAdd(gallivm
->builder
, result
, LLVMGetParam(
151 radeon_bld
->main_fn
, SI_PARAM_START_INSTANCE
), "");
154 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
155 lp_build_const_int32(gallivm
, divisor
), "");
160 static int si_store_shader_io_attribs(struct si_shader
*shader
,
161 const struct tgsi_full_declaration
*d
)
165 switch (d
->Declaration
.File
) {
166 case TGSI_FILE_INPUT
:
167 i
= shader
->ninput
++;
168 assert(i
< Elements(shader
->input
));
169 shader
->input
[i
].name
= d
->Semantic
.Name
;
170 shader
->input
[i
].sid
= d
->Semantic
.Index
;
171 shader
->input
[i
].index
= d
->Range
.First
;
172 shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
173 shader
->input
[i
].centroid
= d
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
;
176 case TGSI_FILE_OUTPUT
:
177 i
= shader
->noutput
++;
178 assert(i
< Elements(shader
->output
));
179 shader
->output
[i
].name
= d
->Semantic
.Name
;
180 shader
->output
[i
].sid
= d
->Semantic
.Index
;
181 shader
->output
[i
].index
= d
->Range
.First
;
182 shader
->output
[i
].usage
= d
->Declaration
.UsageMask
;
189 static void declare_input_vs(
190 struct radeon_llvm_context
*radeon_bld
,
191 unsigned input_index
,
192 const struct tgsi_full_declaration
*decl
)
194 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
195 struct gallivm_state
*gallivm
= base
->gallivm
;
196 struct si_shader_context
*si_shader_ctx
=
197 si_shader_context(&radeon_bld
->soa
.bld_base
);
198 unsigned divisor
= si_shader_ctx
->shader
->key
.vs
.instance_divisors
[input_index
];
202 LLVMValueRef t_list_ptr
;
203 LLVMValueRef t_offset
;
205 LLVMValueRef attribute_offset
;
206 LLVMValueRef buffer_index
;
207 LLVMValueRef args
[3];
208 LLVMTypeRef vec4_type
;
211 /* Load the T list */
212 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFER
);
214 t_offset
= lp_build_const_int32(gallivm
, input_index
);
216 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
, t_offset
);
218 /* Build the attribute offset */
219 attribute_offset
= lp_build_const_int32(gallivm
, 0);
222 /* Build index from instance ID, start instance and divisor */
223 si_shader_ctx
->shader
->uses_instanceid
= true;
224 buffer_index
= get_instance_index_for_fetch(&si_shader_ctx
->radeon_bld
, divisor
);
226 /* Load the buffer index for vertices. */
227 LLVMValueRef vertex_id
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
228 si_shader_ctx
->param_vertex_id
);
229 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
230 SI_PARAM_BASE_VERTEX
);
231 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
234 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
236 args
[1] = attribute_offset
;
237 args
[2] = buffer_index
;
238 input
= build_intrinsic(gallivm
->builder
,
239 "llvm.SI.vs.load.input", vec4_type
, args
, 3,
240 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
242 /* Break up the vec4 into individual components */
243 for (chan
= 0; chan
< 4; chan
++) {
244 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
245 /* XXX: Use a helper function for this. There is one in
247 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
248 LLVMBuildExtractElement(gallivm
->builder
,
249 input
, llvm_chan
, "");
253 static void declare_input_gs(
254 struct radeon_llvm_context
*radeon_bld
,
255 unsigned input_index
,
256 const struct tgsi_full_declaration
*decl
)
258 struct si_shader_context
*si_shader_ctx
=
259 si_shader_context(&radeon_bld
->soa
.bld_base
);
260 struct si_shader
*shader
= si_shader_ctx
->shader
;
262 si_store_shader_io_attribs(shader
, decl
);
264 if (decl
->Semantic
.Name
!= TGSI_SEMANTIC_PRIMID
)
265 shader
->input
[input_index
].param_offset
= shader
->nparam
++;
268 static LLVMValueRef
fetch_input_gs(
269 struct lp_build_tgsi_context
*bld_base
,
270 const struct tgsi_full_src_register
*reg
,
271 enum tgsi_opcode_type type
,
274 struct lp_build_context
*base
= &bld_base
->base
;
275 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
276 struct si_shader
*shader
= si_shader_ctx
->shader
;
277 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
278 struct gallivm_state
*gallivm
= base
->gallivm
;
279 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
280 LLVMValueRef vtx_offset
;
281 LLVMValueRef t_list_ptr
;
283 LLVMValueRef args
[9];
284 unsigned vtx_offset_param
;
287 shader
->input
[reg
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
289 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
290 SI_PARAM_PRIMITIVE_ID
);
295 if (!reg
->Register
.Dimension
)
299 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
301 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
302 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
304 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
308 /* Get the vertex offset parameter */
309 vtx_offset_param
= reg
->Dimension
.Index
;
310 if (vtx_offset_param
< 2) {
311 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
313 assert(vtx_offset_param
< 6);
314 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
316 vtx_offset
= lp_build_mul_imm(uint
,
317 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
321 /* Load the ESGS ring resource descriptor */
322 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
323 SI_PARAM_RW_BUFFERS
);
324 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
325 lp_build_const_int32(gallivm
, SI_RING_ESGS
));
328 args
[1] = vtx_offset
;
329 args
[2] = lp_build_const_int32(gallivm
,
330 ((shader
->input
[reg
->Register
.Index
].param_offset
* 4) +
332 args
[3] = uint
->zero
;
333 args
[4] = uint
->one
; /* OFFEN */
334 args
[5] = uint
->zero
; /* IDXEN */
335 args
[6] = uint
->one
; /* GLC */
336 args
[7] = uint
->zero
; /* SLC */
337 args
[8] = uint
->zero
; /* TFE */
339 return LLVMBuildBitCast(gallivm
->builder
,
340 build_intrinsic(gallivm
->builder
,
341 "llvm.SI.buffer.load.dword.i32.i32",
343 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
344 tgsi2llvmtype(bld_base
, type
), "");
347 static void declare_input_fs(
348 struct radeon_llvm_context
*radeon_bld
,
349 unsigned input_index
,
350 const struct tgsi_full_declaration
*decl
)
352 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
353 struct si_shader_context
*si_shader_ctx
=
354 si_shader_context(&radeon_bld
->soa
.bld_base
);
355 struct si_shader
*shader
= si_shader_ctx
->shader
;
356 struct lp_build_context
*uint
= &radeon_bld
->soa
.bld_base
.uint_bld
;
357 struct gallivm_state
*gallivm
= base
->gallivm
;
358 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
359 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
361 LLVMValueRef interp_param
;
362 const char * intr_name
;
365 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
366 * quad begins a new primitive. Bit 0 always needs
368 * [32:16] ParamOffset
371 LLVMValueRef params
= LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
372 LLVMValueRef attr_number
;
376 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) {
377 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
379 radeon_llvm_reg_index_soa(input_index
, chan
);
380 radeon_bld
->inputs
[soa_index
] =
381 LLVMGetParam(main_fn
, SI_PARAM_POS_X_FLOAT
+ chan
);
384 /* RCP for fragcoord.w */
385 radeon_bld
->inputs
[soa_index
] =
386 LLVMBuildFDiv(gallivm
->builder
,
387 lp_build_const_float(gallivm
, 1.0f
),
388 radeon_bld
->inputs
[soa_index
],
394 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
395 LLVMValueRef face
, is_face_positive
;
397 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
399 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
401 lp_build_const_float(gallivm
, 0.0f
),
404 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
405 LLVMBuildSelect(gallivm
->builder
,
407 lp_build_const_float(gallivm
, 1.0f
),
408 lp_build_const_float(gallivm
, 0.0f
),
410 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
411 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
412 lp_build_const_float(gallivm
, 0.0f
);
413 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
414 lp_build_const_float(gallivm
, 1.0f
);
419 shader
->input
[input_index
].param_offset
= shader
->nparam
++;
420 attr_number
= lp_build_const_int32(gallivm
,
421 shader
->input
[input_index
].param_offset
);
423 switch (decl
->Interp
.Interpolate
) {
424 case TGSI_INTERPOLATE_CONSTANT
:
427 case TGSI_INTERPOLATE_LINEAR
:
428 if (si_shader_ctx
->shader
->key
.ps
.interp_at_sample
)
429 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_SAMPLE
);
430 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
431 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTROID
);
433 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_LINEAR_CENTER
);
435 case TGSI_INTERPOLATE_COLOR
:
436 if (si_shader_ctx
->shader
->key
.ps
.flatshade
) {
440 /* fall through to perspective */
441 case TGSI_INTERPOLATE_PERSPECTIVE
:
442 if (si_shader_ctx
->shader
->key
.ps
.interp_at_sample
)
443 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_SAMPLE
);
444 else if (decl
->Interp
.Location
== TGSI_INTERPOLATE_LOC_CENTROID
)
445 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTROID
);
447 interp_param
= LLVMGetParam(main_fn
, SI_PARAM_PERSP_CENTER
);
450 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
454 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
456 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
457 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
458 si_shader_ctx
->shader
->key
.ps
.color_two_side
) {
459 LLVMValueRef args
[4];
460 LLVMValueRef face
, is_face_positive
;
461 LLVMValueRef back_attr_number
=
462 lp_build_const_int32(gallivm
,
463 shader
->input
[input_index
].param_offset
+ 1);
465 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
467 is_face_positive
= LLVMBuildFCmp(gallivm
->builder
,
469 lp_build_const_float(gallivm
, 0.0f
),
473 args
[3] = interp_param
;
474 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
475 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
476 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
477 LLVMValueRef front
, back
;
480 args
[1] = attr_number
;
481 front
= build_intrinsic(gallivm
->builder
, intr_name
,
482 input_type
, args
, args
[3] ? 4 : 3,
483 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
485 args
[1] = back_attr_number
;
486 back
= build_intrinsic(gallivm
->builder
, intr_name
,
487 input_type
, args
, args
[3] ? 4 : 3,
488 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
490 radeon_bld
->inputs
[soa_index
] =
491 LLVMBuildSelect(gallivm
->builder
,
499 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FOG
) {
500 LLVMValueRef args
[4];
502 args
[0] = uint
->zero
;
503 args
[1] = attr_number
;
505 args
[3] = interp_param
;
506 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
507 build_intrinsic(gallivm
->builder
, intr_name
,
508 input_type
, args
, args
[3] ? 4 : 3,
509 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
510 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
511 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
512 lp_build_const_float(gallivm
, 0.0f
);
513 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
514 lp_build_const_float(gallivm
, 1.0f
);
516 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
517 LLVMValueRef args
[4];
518 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
519 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
521 args
[1] = attr_number
;
523 args
[3] = interp_param
;
524 radeon_bld
->inputs
[soa_index
] =
525 build_intrinsic(gallivm
->builder
, intr_name
,
526 input_type
, args
, args
[3] ? 4 : 3,
527 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
532 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
534 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
535 LLVMValueRef value
= LLVMGetParam(radeon_bld
->main_fn
,
537 value
= LLVMBuildLShr(gallivm
->builder
, value
,
538 lp_build_const_int32(gallivm
, 8), "");
539 value
= LLVMBuildAnd(gallivm
->builder
, value
,
540 lp_build_const_int32(gallivm
, 0xf), "");
544 static LLVMValueRef
load_const(LLVMBuilderRef builder
, LLVMValueRef resource
,
545 LLVMValueRef offset
, LLVMTypeRef return_type
)
547 LLVMValueRef args
[2] = {resource
, offset
};
549 return build_intrinsic(builder
, "llvm.SI.load.const", return_type
, args
, 2,
550 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
553 static void declare_system_value(
554 struct radeon_llvm_context
* radeon_bld
,
556 const struct tgsi_full_declaration
*decl
)
558 struct si_shader_context
*si_shader_ctx
=
559 si_shader_context(&radeon_bld
->soa
.bld_base
);
560 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
561 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
562 LLVMValueRef value
= 0;
564 switch (decl
->Semantic
.Name
) {
565 case TGSI_SEMANTIC_INSTANCEID
:
566 value
= LLVMGetParam(radeon_bld
->main_fn
,
567 si_shader_ctx
->param_instance_id
);
570 case TGSI_SEMANTIC_VERTEXID
:
571 value
= LLVMGetParam(radeon_bld
->main_fn
,
572 si_shader_ctx
->param_vertex_id
);
575 case TGSI_SEMANTIC_SAMPLEID
:
576 value
= get_sample_id(radeon_bld
);
579 case TGSI_SEMANTIC_SAMPLEPOS
:
581 LLVMBuilderRef builder
= gallivm
->builder
;
582 LLVMValueRef desc
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
583 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_DRIVER_STATE_CONST_BUF
);
584 LLVMValueRef resource
= build_indexed_load(si_shader_ctx
, desc
, buf_index
);
586 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
587 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, get_sample_id(radeon_bld
), 8);
588 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
590 LLVMValueRef pos
[4] = {
591 load_const(builder
, resource
, offset0
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
592 load_const(builder
, resource
, offset1
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
593 lp_build_const_float(gallivm
, 0),
594 lp_build_const_float(gallivm
, 0)
596 value
= lp_build_gather_values(gallivm
, pos
, 4);
601 assert(!"unknown system value");
605 radeon_bld
->system_values
[index
] = value
;
608 static LLVMValueRef
fetch_constant(
609 struct lp_build_tgsi_context
* bld_base
,
610 const struct tgsi_full_src_register
*reg
,
611 enum tgsi_opcode_type type
,
614 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
615 struct lp_build_context
* base
= &bld_base
->base
;
616 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
622 if (swizzle
== LP_CHAN_ALL
) {
624 LLVMValueRef values
[4];
625 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
626 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
628 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
631 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
632 idx
= reg
->Register
.Index
* 4 + swizzle
;
634 if (!reg
->Register
.Indirect
)
635 return bitcast(bld_base
, type
, si_shader_ctx
->constants
[buf
][idx
]);
637 addr
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
638 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
639 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
640 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
641 lp_build_const_int32(base
->gallivm
, idx
* 4));
643 result
= load_const(base
->gallivm
->builder
, si_shader_ctx
->const_resource
[buf
],
644 addr
, base
->elem_type
);
646 return bitcast(bld_base
, type
, result
);
649 /* Initialize arguments for the shader export intrinsic */
650 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
651 LLVMValueRef
*values
,
655 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
656 struct lp_build_context
*uint
=
657 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
658 struct lp_build_context
*base
= &bld_base
->base
;
659 unsigned compressed
= 0;
662 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
663 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
665 if (cbuf
>= 0 && cbuf
< 8) {
666 compressed
= (si_shader_ctx
->shader
->key
.ps
.export_16bpc
>> cbuf
) & 0x1;
669 si_shader_ctx
->shader
->spi_shader_col_format
|=
670 V_028714_SPI_SHADER_FP16_ABGR
<< (4 * cbuf
);
672 si_shader_ctx
->shader
->spi_shader_col_format
|=
673 V_028714_SPI_SHADER_32_ABGR
<< (4 * cbuf
);
675 si_shader_ctx
->shader
->cb_shader_mask
|= 0xf << (4 * cbuf
);
680 /* Pixel shader needs to pack output values before export */
681 for (chan
= 0; chan
< 2; chan
++ ) {
682 args
[0] = values
[2 * chan
];
683 args
[1] = values
[2 * chan
+ 1];
685 build_intrinsic(base
->gallivm
->builder
,
687 LLVMInt32TypeInContext(base
->gallivm
->context
),
689 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
690 args
[chan
+ 7] = args
[chan
+ 5] =
691 LLVMBuildBitCast(base
->gallivm
->builder
,
693 LLVMFloatTypeInContext(base
->gallivm
->context
),
700 for (chan
= 0; chan
< 4; chan
++ )
701 /* +5 because the first output value will be
702 * the 6th argument to the intrinsic. */
703 args
[chan
+ 5] = values
[chan
];
705 /* Clear COMPR flag */
706 args
[4] = uint
->zero
;
709 /* XXX: This controls which components of the output
710 * registers actually get exported. (e.g bit 0 means export
711 * X component, bit 1 means export Y component, etc.) I'm
712 * hard coding this to 0xf for now. In the future, we might
713 * want to do something else. */
714 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
716 /* Specify whether the EXEC mask represents the valid mask */
717 args
[1] = uint
->zero
;
719 /* Specify whether this is the last export */
720 args
[2] = uint
->zero
;
722 /* Specify the target we are exporting */
723 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
725 /* XXX: We probably need to keep track of the output
726 * values, so we know what we are passing to the next
730 /* Load from output pointers and initialize arguments for the shader export intrinsic */
731 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context
*bld_base
,
732 LLVMValueRef
*out_ptr
,
736 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
737 LLVMValueRef values
[4];
740 for (i
= 0; i
< 4; i
++)
741 values
[i
] = LLVMBuildLoad(gallivm
->builder
, out_ptr
[i
], "");
743 si_llvm_init_export_args(bld_base
, values
, target
, args
);
746 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
747 LLVMValueRef
*out_ptr
)
749 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
750 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
752 if (si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_NEVER
) {
753 LLVMValueRef alpha_ref
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
756 LLVMValueRef alpha_pass
=
757 lp_build_cmp(&bld_base
->base
,
758 si_shader_ctx
->shader
->key
.ps
.alpha_func
,
759 LLVMBuildLoad(gallivm
->builder
, out_ptr
[3], ""),
762 lp_build_select(&bld_base
->base
,
764 lp_build_const_float(gallivm
, 1.0f
),
765 lp_build_const_float(gallivm
, -1.0f
));
767 build_intrinsic(gallivm
->builder
,
769 LLVMVoidTypeInContext(gallivm
->context
),
772 build_intrinsic(gallivm
->builder
,
774 LLVMVoidTypeInContext(gallivm
->context
),
778 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
781 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
* bld_base
,
782 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
784 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
785 struct si_shader
*shader
= si_shader_ctx
->shader
;
786 struct lp_build_context
*base
= &bld_base
->base
;
787 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
791 LLVMValueRef base_elt
;
792 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
793 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
, SI_DRIVER_STATE_CONST_BUF
);
794 LLVMValueRef const_resource
= build_indexed_load(si_shader_ctx
, ptr
, constbuf_index
);
796 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
797 LLVMValueRef
*args
= pos
[2 + reg_index
];
799 if (!(shader
->key
.vs
.ucps_enabled
& (1 << reg_index
)))
802 shader
->clip_dist_write
|= 0xf << (4 * reg_index
);
807 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
809 /* Compute dot products of position and user clip plane vectors */
810 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
811 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
812 args
[1] = lp_build_const_int32(base
->gallivm
,
813 ((reg_index
* 4 + chan
) * 4 +
815 base_elt
= load_const(base
->gallivm
->builder
, const_resource
,
816 args
[1], base
->elem_type
);
818 lp_build_add(base
, args
[5 + chan
],
819 lp_build_mul(base
, base_elt
,
820 out_elts
[const_chan
]));
824 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
825 args
[1] = uint
->zero
;
826 args
[2] = uint
->zero
;
827 args
[3] = lp_build_const_int32(base
->gallivm
,
828 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
829 args
[4] = uint
->zero
;
833 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
838 fprintf(stderr
, "STREAMOUT\n");
840 for (i
= 0; i
< so
->num_outputs
; i
++) {
841 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
842 so
->output
[i
].start_component
;
843 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
844 i
, so
->output
[i
].output_buffer
,
845 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
846 so
->output
[i
].register_index
,
850 mask
& 8 ? "w" : "");
854 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
855 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
856 * or v4i32 (num_channels=3,4). */
857 static void build_tbuffer_store(struct si_shader_context
*shader
,
860 unsigned num_channels
,
862 LLVMValueRef soffset
,
863 unsigned inst_offset
,
872 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
873 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
874 LLVMValueRef args
[] = {
877 LLVMConstInt(i32
, num_channels
, 0),
880 LLVMConstInt(i32
, inst_offset
, 0),
881 LLVMConstInt(i32
, dfmt
, 0),
882 LLVMConstInt(i32
, nfmt
, 0),
883 LLVMConstInt(i32
, offen
, 0),
884 LLVMConstInt(i32
, idxen
, 0),
885 LLVMConstInt(i32
, glc
, 0),
886 LLVMConstInt(i32
, slc
, 0),
887 LLVMConstInt(i32
, tfe
, 0)
890 /* The instruction offset field has 12 bits */
891 assert(offen
|| inst_offset
< (1 << 12));
893 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
894 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
895 const char *types
[] = {"i32", "v2i32", "v4i32"};
897 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
899 lp_build_intrinsic(gallivm
->builder
, name
,
900 LLVMVoidTypeInContext(gallivm
->context
),
901 args
, Elements(args
));
904 static void build_streamout_store(struct si_shader_context
*shader
,
907 unsigned num_channels
,
909 LLVMValueRef soffset
,
910 unsigned inst_offset
)
912 static unsigned dfmt
[] = {
913 V_008F0C_BUF_DATA_FORMAT_32
,
914 V_008F0C_BUF_DATA_FORMAT_32_32
,
915 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
916 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
918 assert(num_channels
>= 1 && num_channels
<= 4);
920 build_tbuffer_store(shader
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
921 inst_offset
, dfmt
[num_channels
-1],
922 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
925 /* On SI, the vertex shader is responsible for writing streamout data
927 static void si_llvm_emit_streamout(struct si_shader_context
*shader
,
928 struct si_shader_output_values
*outputs
,
931 struct pipe_stream_output_info
*so
= &shader
->shader
->selector
->so
;
932 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
933 LLVMBuilderRef builder
= gallivm
->builder
;
935 struct lp_build_if_state if_ctx
;
937 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
939 LLVMValueRef so_param
=
940 LLVMGetParam(shader
->radeon_bld
.main_fn
,
941 shader
->param_streamout_config
);
943 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
944 LLVMValueRef so_vtx_count
=
945 LLVMBuildAnd(builder
,
946 LLVMBuildLShr(builder
, so_param
,
947 LLVMConstInt(i32
, 16, 0), ""),
948 LLVMConstInt(i32
, 127, 0), "");
950 LLVMValueRef tid
= build_intrinsic(builder
, "llvm.SI.tid", i32
,
951 NULL
, 0, LLVMReadNoneAttribute
);
953 /* can_emit = tid < so_vtx_count; */
954 LLVMValueRef can_emit
=
955 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
957 /* Emit the streamout code conditionally. This actually avoids
958 * out-of-bounds buffer access. The hw tells us via the SGPR
959 * (so_vtx_count) which threads are allowed to emit streamout data. */
960 lp_build_if(&if_ctx
, gallivm
, can_emit
);
962 /* The buffer offset is computed as follows:
963 * ByteOffset = streamout_offset[buffer_id]*4 +
964 * (streamout_write_index + thread_id)*stride[buffer_id] +
968 LLVMValueRef so_write_index
=
969 LLVMGetParam(shader
->radeon_bld
.main_fn
,
970 shader
->param_streamout_write_index
);
972 /* Compute (streamout_write_index + thread_id). */
973 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
975 /* Compute the write offset for each enabled buffer. */
976 LLVMValueRef so_write_offset
[4] = {};
977 for (i
= 0; i
< 4; i
++) {
981 LLVMValueRef so_offset
= LLVMGetParam(shader
->radeon_bld
.main_fn
,
982 shader
->param_streamout_offset
[i
]);
983 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(i32
, 4, 0), "");
985 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
986 LLVMConstInt(i32
, so
->stride
[i
]*4, 0), "");
987 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
990 /* Write streamout data. */
991 for (i
= 0; i
< so
->num_outputs
; i
++) {
992 unsigned buf_idx
= so
->output
[i
].output_buffer
;
993 unsigned reg
= so
->output
[i
].register_index
;
994 unsigned start
= so
->output
[i
].start_component
;
995 unsigned num_comps
= so
->output
[i
].num_components
;
998 assert(num_comps
&& num_comps
<= 4);
999 if (!num_comps
|| num_comps
> 4)
1002 /* Load the output as int. */
1003 for (j
= 0; j
< num_comps
; j
++) {
1004 unsigned outidx
= 0;
1006 while (outidx
< noutput
&& outputs
[outidx
].index
!= reg
)
1009 if (outidx
< noutput
)
1010 out
[j
] = LLVMBuildBitCast(builder
,
1011 outputs
[outidx
].values
[start
+j
],
1020 /* Pack the output. */
1021 LLVMValueRef vdata
= NULL
;
1023 switch (num_comps
) {
1024 case 1: /* as i32 */
1027 case 2: /* as v2i32 */
1028 case 3: /* as v4i32 (aligned to 4) */
1029 case 4: /* as v4i32 */
1030 vdata
= LLVMGetUndef(LLVMVectorType(i32
, util_next_power_of_two(num_comps
)));
1031 for (j
= 0; j
< num_comps
; j
++) {
1032 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
1033 LLVMConstInt(i32
, j
, 0), "");
1038 build_streamout_store(shader
, shader
->so_buffers
[buf_idx
],
1040 so_write_offset
[buf_idx
],
1041 LLVMConstInt(i32
, 0, 0),
1042 so
->output
[i
].dst_offset
*4);
1045 lp_build_endif(&if_ctx
);
1049 /* Generate export instructions for hardware VS shader stage */
1050 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
1051 struct si_shader_output_values
*outputs
,
1054 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1055 struct si_shader
* shader
= si_shader_ctx
->shader
;
1056 struct lp_build_context
* base
= &bld_base
->base
;
1057 struct lp_build_context
* uint
=
1058 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1059 LLVMValueRef args
[9];
1060 LLVMValueRef pos_args
[4][9] = { { 0 } };
1061 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
;
1062 unsigned semantic_name
, semantic_index
, semantic_usage
;
1064 unsigned param_count
= 0;
1068 if (outputs
&& si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
1069 si_llvm_emit_streamout(si_shader_ctx
, outputs
, noutput
);
1072 for (i
= 0; i
< noutput
; i
++) {
1073 semantic_name
= outputs
[i
].name
;
1074 semantic_index
= outputs
[i
].sid
;
1075 semantic_usage
= outputs
[i
].usage
;
1078 /* Select the correct target */
1079 switch(semantic_name
) {
1080 case TGSI_SEMANTIC_PSIZE
:
1081 shader
->vs_out_misc_write
= true;
1082 shader
->vs_out_point_size
= true;
1083 psize_value
= outputs
[i
].values
[0];
1085 case TGSI_SEMANTIC_EDGEFLAG
:
1086 shader
->vs_out_misc_write
= true;
1087 shader
->vs_out_edgeflag
= true;
1088 edgeflag_value
= outputs
[i
].values
[0];
1090 case TGSI_SEMANTIC_LAYER
:
1091 shader
->vs_out_misc_write
= true;
1092 shader
->vs_out_layer
= true;
1093 layer_value
= outputs
[i
].values
[0];
1095 case TGSI_SEMANTIC_POSITION
:
1096 target
= V_008DFC_SQ_EXP_POS
;
1098 case TGSI_SEMANTIC_COLOR
:
1099 case TGSI_SEMANTIC_BCOLOR
:
1100 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1101 shader
->output
[i
].param_offset
= param_count
;
1104 case TGSI_SEMANTIC_CLIPDIST
:
1105 if (!(si_shader_ctx
->shader
->key
.vs
.ucps_enabled
&
1106 (1 << semantic_index
)))
1108 shader
->clip_dist_write
|=
1109 semantic_usage
<< (semantic_index
<< 2);
1110 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
1112 case TGSI_SEMANTIC_CLIPVERTEX
:
1113 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
1115 case TGSI_SEMANTIC_PRIMID
:
1116 case TGSI_SEMANTIC_FOG
:
1117 case TGSI_SEMANTIC_GENERIC
:
1118 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1119 shader
->output
[i
].param_offset
= param_count
;
1125 "Warning: SI unhandled vs output type:%d\n",
1129 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
1131 if (target
>= V_008DFC_SQ_EXP_POS
&&
1132 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
1133 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
1134 args
, sizeof(args
));
1136 lp_build_intrinsic(base
->gallivm
->builder
,
1138 LLVMVoidTypeInContext(base
->gallivm
->context
),
1142 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
1143 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1144 goto handle_semantic
;
1148 /* We need to add the position output manually if it's missing. */
1149 if (!pos_args
[0][0]) {
1150 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1151 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
1152 pos_args
[0][2] = uint
->zero
; /* last export? */
1153 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
1154 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
1155 pos_args
[0][5] = base
->zero
; /* X */
1156 pos_args
[0][6] = base
->zero
; /* Y */
1157 pos_args
[0][7] = base
->zero
; /* Z */
1158 pos_args
[0][8] = base
->one
; /* W */
1161 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1162 if (shader
->vs_out_misc_write
) {
1163 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
1164 shader
->vs_out_point_size
|
1165 (shader
->vs_out_edgeflag
<< 1) |
1166 (shader
->vs_out_layer
<< 2));
1167 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
1168 pos_args
[1][2] = uint
->zero
; /* last export? */
1169 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
1170 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
1171 pos_args
[1][5] = base
->zero
; /* X */
1172 pos_args
[1][6] = base
->zero
; /* Y */
1173 pos_args
[1][7] = base
->zero
; /* Z */
1174 pos_args
[1][8] = base
->zero
; /* W */
1176 if (shader
->vs_out_point_size
)
1177 pos_args
[1][5] = psize_value
;
1179 if (shader
->vs_out_edgeflag
) {
1180 /* The output is a float, but the hw expects an integer
1181 * with the first bit containing the edge flag. */
1182 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
1184 bld_base
->uint_bld
.elem_type
, "");
1185 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
1187 bld_base
->int_bld
.one
);
1189 /* The LLVM intrinsic expects a float. */
1190 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
1192 base
->elem_type
, "");
1195 if (shader
->vs_out_layer
)
1196 pos_args
[1][7] = layer_value
;
1199 for (i
= 0; i
< 4; i
++)
1201 shader
->nr_pos_exports
++;
1204 for (i
= 0; i
< 4; i
++) {
1205 if (!pos_args
[i
][0])
1208 /* Specify the target we are exporting */
1209 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
1211 if (pos_idx
== shader
->nr_pos_exports
)
1212 /* Specify that this is the last export */
1213 pos_args
[i
][2] = uint
->one
;
1215 lp_build_intrinsic(base
->gallivm
->builder
,
1217 LLVMVoidTypeInContext(base
->gallivm
->context
),
1222 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
* bld_base
)
1224 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1225 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1226 struct si_shader
*es
= si_shader_ctx
->shader
;
1227 struct si_shader
*gs
= si_shader_ctx
->gs_for_vs
;
1228 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
1229 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1230 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1231 SI_PARAM_ES2GS_OFFSET
);
1232 LLVMValueRef t_list_ptr
;
1233 LLVMValueRef t_list
;
1237 while (!tgsi_parse_end_of_tokens(parse
)) {
1238 struct tgsi_full_declaration
*d
=
1239 &parse
->FullToken
.FullDeclaration
;
1241 tgsi_parse_token(parse
);
1243 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
1246 si_store_shader_io_attribs(es
, d
);
1249 /* Load the ESGS ring resource descriptor */
1250 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1251 SI_PARAM_RW_BUFFERS
);
1252 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
1253 lp_build_const_int32(gallivm
, SI_RING_ESGS
));
1255 for (i
= 0; i
< es
->noutput
; i
++) {
1256 LLVMValueRef
*out_ptr
=
1257 si_shader_ctx
->radeon_bld
.soa
.outputs
[es
->output
[i
].index
];
1260 for (j
= 0; j
< gs
->ninput
; j
++) {
1261 if (gs
->input
[j
].name
== es
->output
[i
].name
&&
1262 gs
->input
[j
].sid
== es
->output
[i
].sid
)
1265 if (j
== gs
->ninput
)
1268 for (chan
= 0; chan
< 4; chan
++) {
1269 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
1270 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
1272 build_tbuffer_store(si_shader_ctx
, t_list
, out_val
, 1,
1273 LLVMGetUndef(i32
), soffset
,
1274 (4 * gs
->input
[j
].param_offset
+ chan
) * 4,
1275 V_008F0C_BUF_DATA_FORMAT_32
,
1276 V_008F0C_BUF_NUM_FORMAT_UINT
,
1282 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
1284 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1285 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1286 LLVMValueRef args
[2];
1288 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
1289 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
1290 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
1291 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
1292 LLVMNoUnwindAttribute
);
1295 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1297 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1298 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1299 struct si_shader
*shader
= si_shader_ctx
->shader
;
1300 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
1301 struct si_shader_output_values
*outputs
= NULL
;
1302 unsigned noutput
= 0;
1305 while (!tgsi_parse_end_of_tokens(parse
)) {
1306 struct tgsi_full_declaration
*d
=
1307 &parse
->FullToken
.FullDeclaration
;
1310 tgsi_parse_token(parse
);
1312 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
1315 i
= si_store_shader_io_attribs(shader
, d
);
1319 outputs
= REALLOC(outputs
, noutput
* sizeof(outputs
[0]),
1320 (noutput
+ 1) * sizeof(outputs
[0]));
1321 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
1322 outputs
[noutput
].index
= index
;
1323 outputs
[noutput
].name
= d
->Semantic
.Name
;
1324 outputs
[noutput
].sid
= d
->Semantic
.Index
;
1325 outputs
[noutput
].usage
= d
->Declaration
.UsageMask
;
1327 for (i
= 0; i
< 4; i
++)
1328 outputs
[noutput
].values
[i
] =
1329 LLVMBuildLoad(gallivm
->builder
,
1330 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][i
],
1336 si_llvm_export_vs(bld_base
, outputs
, noutput
);
1340 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
* bld_base
)
1342 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1343 struct si_shader
* shader
= si_shader_ctx
->shader
;
1344 struct lp_build_context
* base
= &bld_base
->base
;
1345 struct lp_build_context
* uint
=
1346 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1347 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
1348 LLVMValueRef args
[9];
1349 LLVMValueRef last_args
[9] = { 0 };
1350 unsigned semantic_name
;
1351 int depth_index
= -1, stencil_index
= -1, samplemask_index
= -1;
1354 while (!tgsi_parse_end_of_tokens(parse
)) {
1355 struct tgsi_full_declaration
*d
=
1356 &parse
->FullToken
.FullDeclaration
;
1360 tgsi_parse_token(parse
);
1362 if (parse
->FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_PROPERTY
&&
1363 parse
->FullToken
.FullProperty
.Property
.PropertyName
==
1364 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
)
1365 shader
->fs_write_all
= TRUE
;
1367 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
1370 i
= si_store_shader_io_attribs(shader
, d
);
1374 semantic_name
= d
->Semantic
.Name
;
1375 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
1376 /* Select the correct target */
1377 switch(semantic_name
) {
1378 case TGSI_SEMANTIC_POSITION
:
1379 depth_index
= index
;
1381 case TGSI_SEMANTIC_STENCIL
:
1382 stencil_index
= index
;
1384 case TGSI_SEMANTIC_SAMPLEMASK
:
1385 samplemask_index
= index
;
1387 case TGSI_SEMANTIC_COLOR
:
1388 target
= V_008DFC_SQ_EXP_MRT
+ d
->Semantic
.Index
;
1389 if (si_shader_ctx
->shader
->key
.ps
.alpha_to_one
)
1390 LLVMBuildStore(bld_base
->base
.gallivm
->builder
,
1392 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][3]);
1394 if (d
->Semantic
.Index
== 0 &&
1395 si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
1396 si_alpha_test(bld_base
,
1397 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
]);
1402 "Warning: SI unhandled fs output type:%d\n",
1406 si_llvm_init_export_args_load(bld_base
,
1407 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
],
1410 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
1411 /* If there is an export instruction waiting to be emitted, do so now. */
1413 lp_build_intrinsic(base
->gallivm
->builder
,
1415 LLVMVoidTypeInContext(base
->gallivm
->context
),
1419 /* This instruction will be emitted at the end of the shader. */
1420 memcpy(last_args
, args
, sizeof(args
));
1422 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1423 if (shader
->fs_write_all
&& shader
->output
[i
].sid
== 0 &&
1424 si_shader_ctx
->shader
->key
.ps
.nr_cbufs
> 1) {
1425 for (int c
= 1; c
< si_shader_ctx
->shader
->key
.ps
.nr_cbufs
; c
++) {
1426 si_llvm_init_export_args_load(bld_base
,
1427 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
],
1428 V_008DFC_SQ_EXP_MRT
+ c
, args
);
1429 lp_build_intrinsic(base
->gallivm
->builder
,
1431 LLVMVoidTypeInContext(base
->gallivm
->context
),
1436 lp_build_intrinsic(base
->gallivm
->builder
,
1438 LLVMVoidTypeInContext(base
->gallivm
->context
),
1444 if (depth_index
>= 0 || stencil_index
>= 0 || samplemask_index
>= 0) {
1445 LLVMValueRef out_ptr
;
1448 /* Specify the target we are exporting */
1449 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
1451 args
[5] = base
->zero
; /* R, depth */
1452 args
[6] = base
->zero
; /* G, stencil test value[0:7], stencil op value[8:15] */
1453 args
[7] = base
->zero
; /* B, sample mask */
1454 args
[8] = base
->zero
; /* A, alpha to mask */
1456 if (depth_index
>= 0) {
1457 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[depth_index
][2];
1458 args
[5] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1460 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
1463 if (stencil_index
>= 0) {
1464 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[stencil_index
][1];
1465 args
[6] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1466 /* Only setting the stencil component bit (0x2) here
1467 * breaks some stencil piglit tests
1470 si_shader_ctx
->shader
->db_shader_control
|=
1471 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1474 if (samplemask_index
>= 0) {
1475 out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[samplemask_index
][0];
1476 args
[7] = LLVMBuildLoad(base
->gallivm
->builder
, out_ptr
, "");
1477 mask
|= 0xf; /* Set all components. */
1478 si_shader_ctx
->shader
->db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(1);
1481 if (samplemask_index
>= 0)
1482 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_ABGR
;
1483 else if (stencil_index
>= 0)
1484 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
1486 si_shader_ctx
->shader
->spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
1488 /* Specify which components to enable */
1489 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
1493 args
[4] = uint
->zero
;
1496 lp_build_intrinsic(base
->gallivm
->builder
,
1498 LLVMVoidTypeInContext(base
->gallivm
->context
),
1501 memcpy(last_args
, args
, sizeof(args
));
1504 if (!last_args
[0]) {
1505 /* Specify which components to enable */
1506 last_args
[0] = lp_build_const_int32(base
->gallivm
, 0x0);
1508 /* Specify the target we are exporting */
1509 last_args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRT
);
1511 /* Set COMPR flag to zero to export data as 32-bit */
1512 last_args
[4] = uint
->zero
;
1515 last_args
[5]= uint
->zero
;
1516 last_args
[6]= uint
->zero
;
1517 last_args
[7]= uint
->zero
;
1518 last_args
[8]= uint
->zero
;
1521 /* Specify whether the EXEC mask represents the valid mask */
1522 last_args
[1] = uint
->one
;
1524 /* Specify that this is the last export */
1525 last_args
[2] = lp_build_const_int32(base
->gallivm
, 1);
1527 lp_build_intrinsic(base
->gallivm
->builder
,
1529 LLVMVoidTypeInContext(base
->gallivm
->context
),
1533 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1534 struct lp_build_tgsi_context
* bld_base
,
1535 struct lp_build_emit_data
* emit_data
);
1537 static bool tgsi_is_shadow_sampler(unsigned target
)
1539 return target
== TGSI_TEXTURE_SHADOW1D
||
1540 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1541 target
== TGSI_TEXTURE_SHADOW2D
||
1542 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1543 target
== TGSI_TEXTURE_SHADOWCUBE
||
1544 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
1545 target
== TGSI_TEXTURE_SHADOWRECT
;
1548 static const struct lp_build_tgsi_action tex_action
;
1550 static void tex_fetch_args(
1551 struct lp_build_tgsi_context
* bld_base
,
1552 struct lp_build_emit_data
* emit_data
)
1554 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1555 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1556 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
1557 unsigned opcode
= inst
->Instruction
.Opcode
;
1558 unsigned target
= inst
->Texture
.Texture
;
1559 LLVMValueRef coords
[4];
1560 LLVMValueRef address
[16];
1562 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
, &ref_pos
);
1565 unsigned sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1566 unsigned sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
1567 bool has_offset
= HAVE_LLVM
>= 0x0305 ? inst
->Texture
.NumOffsets
> 0 : false;
1569 if (target
== TGSI_TEXTURE_BUFFER
) {
1570 LLVMTypeRef i128
= LLVMIntTypeInContext(gallivm
->context
, 128);
1571 LLVMTypeRef v2i128
= LLVMVectorType(i128
, 2);
1572 LLVMTypeRef i8
= LLVMInt8TypeInContext(gallivm
->context
);
1573 LLVMTypeRef v16i8
= LLVMVectorType(i8
, 16);
1575 /* Bitcast and truncate v8i32 to v16i8. */
1576 LLVMValueRef res
= si_shader_ctx
->resources
[sampler_index
];
1577 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
1578 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.zero
, "");
1579 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v16i8
, "");
1581 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
1582 emit_data
->args
[0] = res
;
1583 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
1584 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, 0);
1585 emit_data
->arg_count
= 3;
1589 /* Fetch and project texture coordinates */
1590 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1591 for (chan
= 0; chan
< 3; chan
++ ) {
1592 coords
[chan
] = lp_build_emit_fetch(bld_base
,
1595 if (opcode
== TGSI_OPCODE_TXP
)
1596 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1602 if (opcode
== TGSI_OPCODE_TXP
)
1603 coords
[3] = bld_base
->base
.one
;
1606 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
1607 /* The offsets are six-bit signed integers packed like this:
1608 * X=[5:0], Y=[13:8], and Z=[21:16].
1610 LLVMValueRef offset
[3], pack
;
1612 assert(inst
->Texture
.NumOffsets
== 1);
1614 for (chan
= 0; chan
< 3; chan
++) {
1615 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1616 emit_data
->inst
, 0, chan
);
1617 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
1618 lp_build_const_int32(gallivm
, 0x3f), "");
1620 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
1621 lp_build_const_int32(gallivm
, chan
*8), "");
1624 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
1625 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
1626 address
[count
++] = pack
;
1629 /* Pack LOD bias value */
1630 if (opcode
== TGSI_OPCODE_TXB
)
1631 address
[count
++] = coords
[3];
1632 if (opcode
== TGSI_OPCODE_TXB2
)
1633 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1635 /* Pack depth comparison value */
1636 if (tgsi_is_shadow_sampler(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1637 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1638 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1640 assert(ref_pos
>= 0);
1641 address
[count
++] = coords
[ref_pos
];
1645 if (target
== TGSI_TEXTURE_CUBE
||
1646 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1647 target
== TGSI_TEXTURE_SHADOWCUBE
||
1648 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1649 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
);
1651 /* Pack user derivatives */
1652 if (opcode
== TGSI_OPCODE_TXD
) {
1653 int num_deriv_channels
, param
;
1656 case TGSI_TEXTURE_3D
:
1657 num_deriv_channels
= 3;
1659 case TGSI_TEXTURE_2D
:
1660 case TGSI_TEXTURE_SHADOW2D
:
1661 case TGSI_TEXTURE_RECT
:
1662 case TGSI_TEXTURE_SHADOWRECT
:
1663 case TGSI_TEXTURE_2D_ARRAY
:
1664 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1665 case TGSI_TEXTURE_CUBE
:
1666 case TGSI_TEXTURE_SHADOWCUBE
:
1667 case TGSI_TEXTURE_CUBE_ARRAY
:
1668 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1669 num_deriv_channels
= 2;
1671 case TGSI_TEXTURE_1D
:
1672 case TGSI_TEXTURE_SHADOW1D
:
1673 case TGSI_TEXTURE_1D_ARRAY
:
1674 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1675 num_deriv_channels
= 1;
1678 assert(0); /* no other targets are valid here */
1681 for (param
= 1; param
<= 2; param
++)
1682 for (chan
= 0; chan
< num_deriv_channels
; chan
++)
1683 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, param
, chan
);
1686 /* Pack texture coordinates */
1687 address
[count
++] = coords
[0];
1689 address
[count
++] = coords
[1];
1691 address
[count
++] = coords
[2];
1693 /* Pack LOD or sample index */
1694 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
1695 address
[count
++] = coords
[3];
1696 else if (opcode
== TGSI_OPCODE_TXL2
)
1697 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, 0);
1700 assert(!"Cannot handle more than 16 texture address parameters");
1704 for (chan
= 0; chan
< count
; chan
++ ) {
1705 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
1707 LLVMInt32TypeInContext(gallivm
->context
),
1711 /* Adjust the sample index according to FMASK.
1713 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1714 * which is the identity mapping. Each nibble says which physical sample
1715 * should be fetched to get that sample.
1717 * For example, 0x11111100 means there are only 2 samples stored and
1718 * the second sample covers 3/4 of the pixel. When reading samples 0
1719 * and 1, return physical sample 0 (determined by the first two 0s
1720 * in FMASK), otherwise return physical sample 1.
1722 * The sample index should be adjusted as follows:
1723 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1725 if (target
== TGSI_TEXTURE_2D_MSAA
||
1726 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1727 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1728 struct lp_build_emit_data txf_emit_data
= *emit_data
;
1729 LLVMValueRef txf_address
[4];
1730 unsigned txf_count
= count
;
1731 struct tgsi_full_instruction inst
= {};
1733 memcpy(txf_address
, address
, sizeof(txf_address
));
1735 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1736 txf_address
[2] = bld_base
->uint_bld
.zero
;
1738 txf_address
[3] = bld_base
->uint_bld
.zero
;
1740 /* Pad to a power-of-two size. */
1741 while (txf_count
< util_next_power_of_two(txf_count
))
1742 txf_address
[txf_count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1744 /* Read FMASK using TXF. */
1745 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
1746 inst
.Texture
.Texture
= target
== TGSI_TEXTURE_2D_MSAA
? TGSI_TEXTURE_2D
: TGSI_TEXTURE_2D_ARRAY
;
1747 txf_emit_data
.inst
= &inst
;
1748 txf_emit_data
.chan
= 0;
1749 txf_emit_data
.dst_type
= LLVMVectorType(
1750 LLVMInt32TypeInContext(gallivm
->context
), 4);
1751 txf_emit_data
.args
[0] = lp_build_gather_values(gallivm
, txf_address
, txf_count
);
1752 txf_emit_data
.args
[1] = si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
];
1753 txf_emit_data
.args
[2] = lp_build_const_int32(gallivm
, inst
.Texture
.Texture
);
1754 txf_emit_data
.arg_count
= 3;
1756 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
1758 /* Initialize some constants. */
1759 LLVMValueRef four
= LLVMConstInt(uint_bld
->elem_type
, 4, 0);
1760 LLVMValueRef F
= LLVMConstInt(uint_bld
->elem_type
, 0xF, 0);
1762 /* Apply the formula. */
1763 LLVMValueRef fmask
=
1764 LLVMBuildExtractElement(gallivm
->builder
,
1765 txf_emit_data
.output
[0],
1766 uint_bld
->zero
, "");
1768 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
1770 LLVMValueRef sample_index4
=
1771 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
1773 LLVMValueRef shifted_fmask
=
1774 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
1776 LLVMValueRef final_sample
=
1777 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
1779 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1780 * resource descriptor is 0 (invalid),
1782 LLVMValueRef fmask_desc
=
1783 LLVMBuildBitCast(gallivm
->builder
,
1784 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ sampler_index
],
1785 LLVMVectorType(uint_bld
->elem_type
, 8), "");
1787 LLVMValueRef fmask_word1
=
1788 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
1791 LLVMValueRef word1_is_nonzero
=
1792 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
1793 fmask_word1
, uint_bld
->zero
, "");
1795 /* Replace the MSAA sample index. */
1796 address
[sample_chan
] =
1797 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
1798 final_sample
, address
[sample_chan
], "");
1802 emit_data
->args
[1] = si_shader_ctx
->resources
[sampler_index
];
1804 if (opcode
== TGSI_OPCODE_TXF
) {
1805 /* add tex offsets */
1806 if (inst
->Texture
.NumOffsets
) {
1807 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1808 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
1809 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
1811 assert(inst
->Texture
.NumOffsets
== 1);
1814 case TGSI_TEXTURE_3D
:
1815 address
[2] = lp_build_add(uint_bld
, address
[2],
1816 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
1818 case TGSI_TEXTURE_2D
:
1819 case TGSI_TEXTURE_SHADOW2D
:
1820 case TGSI_TEXTURE_RECT
:
1821 case TGSI_TEXTURE_SHADOWRECT
:
1822 case TGSI_TEXTURE_2D_ARRAY
:
1823 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1825 lp_build_add(uint_bld
, address
[1],
1826 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
1828 case TGSI_TEXTURE_1D
:
1829 case TGSI_TEXTURE_SHADOW1D
:
1830 case TGSI_TEXTURE_1D_ARRAY
:
1831 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1833 lp_build_add(uint_bld
, address
[0],
1834 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
1836 /* texture offsets do not apply to other texture targets */
1840 emit_data
->args
[2] = lp_build_const_int32(gallivm
, target
);
1841 emit_data
->arg_count
= 3;
1843 emit_data
->dst_type
= LLVMVectorType(
1844 LLVMInt32TypeInContext(gallivm
->context
),
1846 } else if (opcode
== TGSI_OPCODE_TG4
||
1847 opcode
== TGSI_OPCODE_LODQ
||
1849 unsigned is_array
= target
== TGSI_TEXTURE_1D_ARRAY
||
1850 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1851 target
== TGSI_TEXTURE_2D_ARRAY
||
1852 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1853 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1854 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
1855 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
1856 unsigned dmask
= 0xf;
1858 if (opcode
== TGSI_OPCODE_TG4
) {
1859 unsigned gather_comp
= 0;
1861 /* DMASK was repurposed for GATHER4. 4 components are always
1862 * returned and DMASK works like a swizzle - it selects
1863 * the component to fetch. The only valid DMASK values are
1864 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1865 * (red,red,red,red) etc.) The ISA document doesn't mention
1869 /* Get the component index from src1.x for Gather4. */
1870 if (!tgsi_is_shadow_sampler(target
)) {
1871 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
1872 LLVMValueRef comp_imm
;
1873 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1875 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1877 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
1878 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1879 gather_comp
= CLAMP(gather_comp
, 0, 3);
1882 dmask
= 1 << gather_comp
;
1885 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1886 emit_data
->args
[3] = lp_build_const_int32(gallivm
, dmask
);
1887 emit_data
->args
[4] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
1888 emit_data
->args
[5] = lp_build_const_int32(gallivm
, 0); /* r128 */
1889 emit_data
->args
[6] = lp_build_const_int32(gallivm
, is_array
); /* da */
1890 emit_data
->args
[7] = lp_build_const_int32(gallivm
, 0); /* glc */
1891 emit_data
->args
[8] = lp_build_const_int32(gallivm
, 0); /* slc */
1892 emit_data
->args
[9] = lp_build_const_int32(gallivm
, 0); /* tfe */
1893 emit_data
->args
[10] = lp_build_const_int32(gallivm
, 0); /* lwe */
1895 emit_data
->arg_count
= 11;
1897 emit_data
->dst_type
= LLVMVectorType(
1898 LLVMFloatTypeInContext(gallivm
->context
),
1901 emit_data
->args
[2] = si_shader_ctx
->samplers
[sampler_index
];
1902 emit_data
->args
[3] = lp_build_const_int32(gallivm
, target
);
1903 emit_data
->arg_count
= 4;
1905 emit_data
->dst_type
= LLVMVectorType(
1906 LLVMFloatTypeInContext(gallivm
->context
),
1910 /* The fetch opcode has been converted to a 2D array fetch.
1911 * This simplifies the LLVM backend. */
1912 if (target
== TGSI_TEXTURE_CUBE_ARRAY
)
1913 target
= TGSI_TEXTURE_2D_ARRAY
;
1914 else if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
1915 target
= TGSI_TEXTURE_SHADOW2D_ARRAY
;
1917 /* Pad to power of two vector */
1918 while (count
< util_next_power_of_two(count
))
1919 address
[count
++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm
->context
));
1921 emit_data
->args
[0] = lp_build_gather_values(gallivm
, address
, count
);
1924 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
1925 struct lp_build_tgsi_context
* bld_base
,
1926 struct lp_build_emit_data
* emit_data
)
1928 struct lp_build_context
* base
= &bld_base
->base
;
1929 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
1930 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1931 char intr_name
[127];
1932 bool has_offset
= HAVE_LLVM
>= 0x0305 ?
1933 emit_data
->inst
->Texture
.NumOffsets
> 0 : false;
1935 if (target
== TGSI_TEXTURE_BUFFER
) {
1936 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1937 base
->gallivm
->builder
,
1938 "llvm.SI.vs.load.input", emit_data
->dst_type
,
1939 emit_data
->args
, emit_data
->arg_count
,
1940 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1944 if (opcode
== TGSI_OPCODE_TG4
||
1945 opcode
== TGSI_OPCODE_LODQ
||
1946 (opcode
!= TGSI_OPCODE_TXF
&& has_offset
)) {
1947 bool is_shadow
= tgsi_is_shadow_sampler(target
);
1948 const char *name
= "llvm.SI.image.sample";
1949 const char *infix
= "";
1952 case TGSI_OPCODE_TEX
:
1953 case TGSI_OPCODE_TEX2
:
1954 case TGSI_OPCODE_TXP
:
1956 case TGSI_OPCODE_TXB
:
1957 case TGSI_OPCODE_TXB2
:
1960 case TGSI_OPCODE_TXL
:
1961 case TGSI_OPCODE_TXL2
:
1964 case TGSI_OPCODE_TXD
:
1967 case TGSI_OPCODE_TG4
:
1968 name
= "llvm.SI.gather4";
1970 case TGSI_OPCODE_LODQ
:
1971 name
= "llvm.SI.getlod";
1980 /* Add the type and suffixes .c, .o if needed. */
1981 sprintf(intr_name
, "%s%s%s%s.v%ui32", name
,
1982 is_shadow
? ".c" : "", infix
, has_offset
? ".o" : "",
1983 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
1985 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
1986 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
1987 emit_data
->args
, emit_data
->arg_count
,
1988 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1990 LLVMTypeRef i8
, v16i8
, v32i8
;
1994 case TGSI_OPCODE_TEX
:
1995 case TGSI_OPCODE_TEX2
:
1996 case TGSI_OPCODE_TXP
:
1997 name
= "llvm.SI.sample";
1999 case TGSI_OPCODE_TXB
:
2000 case TGSI_OPCODE_TXB2
:
2001 name
= "llvm.SI.sampleb";
2003 case TGSI_OPCODE_TXD
:
2004 name
= "llvm.SI.sampled";
2006 case TGSI_OPCODE_TXF
:
2007 name
= "llvm.SI.imageload";
2009 case TGSI_OPCODE_TXL
:
2010 case TGSI_OPCODE_TXL2
:
2011 name
= "llvm.SI.samplel";
2018 i8
= LLVMInt8TypeInContext(base
->gallivm
->context
);
2019 v16i8
= LLVMVectorType(i8
, 16);
2020 v32i8
= LLVMVectorType(i8
, 32);
2022 emit_data
->args
[1] = LLVMBuildBitCast(base
->gallivm
->builder
,
2023 emit_data
->args
[1], v32i8
, "");
2024 if (opcode
!= TGSI_OPCODE_TXF
) {
2025 emit_data
->args
[2] = LLVMBuildBitCast(base
->gallivm
->builder
,
2026 emit_data
->args
[2], v16i8
, "");
2029 sprintf(intr_name
, "%s.v%ui32", name
,
2030 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
2032 emit_data
->output
[emit_data
->chan
] = build_intrinsic(
2033 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
2034 emit_data
->args
, emit_data
->arg_count
,
2035 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
2039 static void txq_fetch_args(
2040 struct lp_build_tgsi_context
* bld_base
,
2041 struct lp_build_emit_data
* emit_data
)
2043 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2044 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2045 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2046 unsigned target
= inst
->Texture
.Texture
;
2048 if (target
== TGSI_TEXTURE_BUFFER
) {
2049 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2050 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
2052 /* Read the size from the buffer descriptor directly. */
2053 LLVMValueRef size
= si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2054 size
= LLVMBuildBitCast(gallivm
->builder
, size
, v8i32
, "");
2055 size
= LLVMBuildExtractElement(gallivm
->builder
, size
,
2056 lp_build_const_int32(gallivm
, 2), "");
2057 emit_data
->args
[0] = size
;
2062 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
2065 emit_data
->args
[1] = si_shader_ctx
->resources
[inst
->Src
[1].Register
.Index
];
2067 /* Texture target */
2068 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2069 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
2070 target
= TGSI_TEXTURE_2D_ARRAY
;
2072 emit_data
->args
[2] = lp_build_const_int32(bld_base
->base
.gallivm
,
2075 emit_data
->arg_count
= 3;
2077 emit_data
->dst_type
= LLVMVectorType(
2078 LLVMInt32TypeInContext(bld_base
->base
.gallivm
->context
),
2082 static void build_txq_intrinsic(const struct lp_build_tgsi_action
* action
,
2083 struct lp_build_tgsi_context
* bld_base
,
2084 struct lp_build_emit_data
* emit_data
)
2086 unsigned target
= emit_data
->inst
->Texture
.Texture
;
2088 if (target
== TGSI_TEXTURE_BUFFER
) {
2089 /* Just return the buffer size. */
2090 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
2094 build_tgsi_intrinsic_nomem(action
, bld_base
, emit_data
);
2096 /* Divide the number of layers by 6 to get the number of cubes. */
2097 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2098 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
2099 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2100 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
2101 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
2103 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
2104 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
2105 z
= LLVMBuildSDiv(builder
, z
, six
, "");
2107 emit_data
->output
[emit_data
->chan
] =
2108 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
2112 static void si_llvm_emit_ddxy(
2113 const struct lp_build_tgsi_action
* action
,
2114 struct lp_build_tgsi_context
* bld_base
,
2115 struct lp_build_emit_data
* emit_data
)
2117 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2118 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2119 struct lp_build_context
* base
= &bld_base
->base
;
2120 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
2121 unsigned opcode
= inst
->Instruction
.Opcode
;
2122 LLVMValueRef indices
[2];
2123 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
2124 LLVMValueRef tl
, trbl
, result
[4];
2126 unsigned swizzle
[4];
2129 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2131 indices
[0] = bld_base
->uint_bld
.zero
;
2132 indices
[1] = build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
2133 NULL
, 0, LLVMReadNoneAttribute
);
2134 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2137 indices
[1] = LLVMBuildAnd(gallivm
->builder
, indices
[1],
2138 lp_build_const_int32(gallivm
, 0xfffffffc), "");
2139 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2142 indices
[1] = LLVMBuildAdd(gallivm
->builder
, indices
[1],
2143 lp_build_const_int32(gallivm
,
2144 opcode
== TGSI_OPCODE_DDX
? 1 : 2),
2146 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->ddxy_lds
,
2149 for (c
= 0; c
< 4; ++c
) {
2152 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
2153 for (i
= 0; i
< c
; ++i
) {
2154 if (swizzle
[i
] == swizzle
[c
]) {
2155 result
[c
] = result
[i
];
2162 LLVMBuildStore(gallivm
->builder
,
2163 LLVMBuildBitCast(gallivm
->builder
,
2164 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
2168 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
2169 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
2171 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
2172 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, base
->elem_type
, "");
2174 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
2177 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
2180 /* Emit one vertex from the geometry shader */
2181 static void si_llvm_emit_vertex(
2182 const struct lp_build_tgsi_action
*action
,
2183 struct lp_build_tgsi_context
*bld_base
,
2184 struct lp_build_emit_data
*emit_data
)
2186 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2187 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2188 struct si_shader
*shader
= si_shader_ctx
->shader
;
2189 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2190 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2191 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2192 SI_PARAM_GS2VS_OFFSET
);
2193 LLVMValueRef gs_next_vertex
;
2194 LLVMValueRef can_emit
, kill
;
2195 LLVMValueRef t_list_ptr
;
2196 LLVMValueRef t_list
;
2197 LLVMValueRef args
[2];
2201 /* Load the GSVS ring resource descriptor */
2202 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2203 SI_PARAM_RW_BUFFERS
);
2204 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
2205 lp_build_const_int32(gallivm
, SI_RING_GSVS
));
2207 if (shader
->noutput
== 0) {
2208 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
2210 while (!tgsi_parse_end_of_tokens(parse
)) {
2211 tgsi_parse_token(parse
);
2213 if (parse
->FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
2214 struct tgsi_full_declaration
*d
= &parse
->FullToken
.FullDeclaration
;
2216 if (d
->Declaration
.File
== TGSI_FILE_OUTPUT
)
2217 si_store_shader_io_attribs(shader
, d
);
2222 /* Write vertex attribute values to GSVS ring */
2223 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
, si_shader_ctx
->gs_next_vertex
, "");
2225 /* If this thread has already emitted the declared maximum number of
2226 * vertices, kill it: excessive vertex emissions are not supposed to
2227 * have any effect, and GS threads have no externally observable
2228 * effects other than emitting vertices.
2230 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
2231 lp_build_const_int32(gallivm
,
2232 shader
->gs_max_out_vertices
), "");
2233 kill
= lp_build_select(&bld_base
->base
, can_emit
,
2234 lp_build_const_float(gallivm
, 1.0f
),
2235 lp_build_const_float(gallivm
, -1.0f
));
2236 build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
2237 LLVMVoidTypeInContext(gallivm
->context
), &kill
, 1, 0);
2239 for (i
= 0; i
< shader
->noutput
; i
++) {
2240 LLVMValueRef
*out_ptr
=
2241 si_shader_ctx
->radeon_bld
.soa
.outputs
[shader
->output
[i
].index
];
2243 for (chan
= 0; chan
< 4; chan
++) {
2244 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2245 LLVMValueRef voffset
=
2246 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
2247 shader
->gs_max_out_vertices
);
2249 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
2250 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
2252 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
2254 build_tbuffer_store(si_shader_ctx
, t_list
, out_val
, 1,
2255 voffset
, soffset
, 0,
2256 V_008F0C_BUF_DATA_FORMAT_32
,
2257 V_008F0C_BUF_NUM_FORMAT_UINT
,
2261 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
2262 lp_build_const_int32(gallivm
, 1));
2263 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, si_shader_ctx
->gs_next_vertex
);
2265 /* Signal vertex emission */
2266 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
);
2267 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2268 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2269 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2270 LLVMNoUnwindAttribute
);
2273 /* Cut one primitive from the geometry shader */
2274 static void si_llvm_emit_primitive(
2275 const struct lp_build_tgsi_action
*action
,
2276 struct lp_build_tgsi_context
*bld_base
,
2277 struct lp_build_emit_data
*emit_data
)
2279 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2280 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2281 LLVMValueRef args
[2];
2283 /* Signal primitive cut */
2284 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
);
2285 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2286 build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2287 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2288 LLVMNoUnwindAttribute
);
2291 static const struct lp_build_tgsi_action tex_action
= {
2292 .fetch_args
= tex_fetch_args
,
2293 .emit
= build_tex_intrinsic
,
2296 static const struct lp_build_tgsi_action txq_action
= {
2297 .fetch_args
= txq_fetch_args
,
2298 .emit
= build_txq_intrinsic
,
2299 .intr_name
= "llvm.SI.resinfo"
2302 static void create_meta_data(struct si_shader_context
*si_shader_ctx
)
2304 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
2305 LLVMValueRef args
[3];
2307 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
2309 args
[2] = lp_build_const_int32(gallivm
, 1);
2311 si_shader_ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
2314 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
2316 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
2320 static void create_function(struct si_shader_context
*si_shader_ctx
)
2322 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2323 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2324 struct si_shader
*shader
= si_shader_ctx
->shader
;
2325 LLVMTypeRef params
[SI_NUM_PARAMS
], f32
, i8
, i32
, v2i32
, v3i32
, v16i8
, v4i32
, v8i32
;
2326 unsigned i
, last_sgpr
, num_params
;
2328 i8
= LLVMInt8TypeInContext(gallivm
->context
);
2329 i32
= LLVMInt32TypeInContext(gallivm
->context
);
2330 f32
= LLVMFloatTypeInContext(gallivm
->context
);
2331 v2i32
= LLVMVectorType(i32
, 2);
2332 v3i32
= LLVMVectorType(i32
, 3);
2333 v4i32
= LLVMVectorType(i32
, 4);
2334 v8i32
= LLVMVectorType(i32
, 8);
2335 v16i8
= LLVMVectorType(i8
, 16);
2337 params
[SI_PARAM_CONST
] = const_array(v16i8
, SI_NUM_CONST_BUFFERS
);
2338 params
[SI_PARAM_RW_BUFFERS
] = const_array(v16i8
, SI_NUM_RW_BUFFERS
);
2339 params
[SI_PARAM_SAMPLER
] = const_array(v4i32
, SI_NUM_SAMPLER_STATES
);
2340 params
[SI_PARAM_RESOURCE
] = const_array(v8i32
, SI_NUM_SAMPLER_VIEWS
);
2342 switch (si_shader_ctx
->type
) {
2343 case TGSI_PROCESSOR_VERTEX
:
2344 params
[SI_PARAM_VERTEX_BUFFER
] = const_array(v16i8
, SI_NUM_VERTEX_BUFFERS
);
2345 params
[SI_PARAM_BASE_VERTEX
] = i32
;
2346 params
[SI_PARAM_START_INSTANCE
] = i32
;
2347 num_params
= SI_PARAM_START_INSTANCE
+1;
2348 if (shader
->key
.vs
.as_es
) {
2349 params
[SI_PARAM_ES2GS_OFFSET
] = i32
;
2352 /* The locations of the other parameters are assigned dynamically. */
2354 /* Streamout SGPRs. */
2355 if (shader
->selector
->so
.num_outputs
) {
2356 params
[si_shader_ctx
->param_streamout_config
= num_params
++] = i32
;
2357 params
[si_shader_ctx
->param_streamout_write_index
= num_params
++] = i32
;
2359 /* A streamout buffer offset is loaded if the stride is non-zero. */
2360 for (i
= 0; i
< 4; i
++) {
2361 if (!shader
->selector
->so
.stride
[i
])
2364 params
[si_shader_ctx
->param_streamout_offset
[i
] = num_params
++] = i32
;
2368 last_sgpr
= num_params
-1;
2371 params
[si_shader_ctx
->param_vertex_id
= num_params
++] = i32
;
2372 params
[num_params
++] = i32
; /* unused*/
2373 params
[num_params
++] = i32
; /* unused */
2374 params
[si_shader_ctx
->param_instance_id
= num_params
++] = i32
;
2377 case TGSI_PROCESSOR_GEOMETRY
:
2378 params
[SI_PARAM_GS2VS_OFFSET
] = i32
;
2379 params
[SI_PARAM_GS_WAVE_ID
] = i32
;
2380 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
2383 params
[SI_PARAM_VTX0_OFFSET
] = i32
;
2384 params
[SI_PARAM_VTX1_OFFSET
] = i32
;
2385 params
[SI_PARAM_PRIMITIVE_ID
] = i32
;
2386 params
[SI_PARAM_VTX2_OFFSET
] = i32
;
2387 params
[SI_PARAM_VTX3_OFFSET
] = i32
;
2388 params
[SI_PARAM_VTX4_OFFSET
] = i32
;
2389 params
[SI_PARAM_VTX5_OFFSET
] = i32
;
2390 params
[SI_PARAM_GS_INSTANCE_ID
] = i32
;
2391 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
2394 case TGSI_PROCESSOR_FRAGMENT
:
2395 params
[SI_PARAM_ALPHA_REF
] = f32
;
2396 params
[SI_PARAM_PRIM_MASK
] = i32
;
2397 last_sgpr
= SI_PARAM_PRIM_MASK
;
2398 params
[SI_PARAM_PERSP_SAMPLE
] = v2i32
;
2399 params
[SI_PARAM_PERSP_CENTER
] = v2i32
;
2400 params
[SI_PARAM_PERSP_CENTROID
] = v2i32
;
2401 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
2402 params
[SI_PARAM_LINEAR_SAMPLE
] = v2i32
;
2403 params
[SI_PARAM_LINEAR_CENTER
] = v2i32
;
2404 params
[SI_PARAM_LINEAR_CENTROID
] = v2i32
;
2405 params
[SI_PARAM_LINE_STIPPLE_TEX
] = f32
;
2406 params
[SI_PARAM_POS_X_FLOAT
] = f32
;
2407 params
[SI_PARAM_POS_Y_FLOAT
] = f32
;
2408 params
[SI_PARAM_POS_Z_FLOAT
] = f32
;
2409 params
[SI_PARAM_POS_W_FLOAT
] = f32
;
2410 params
[SI_PARAM_FRONT_FACE
] = f32
;
2411 params
[SI_PARAM_ANCILLARY
] = i32
;
2412 params
[SI_PARAM_SAMPLE_COVERAGE
] = f32
;
2413 params
[SI_PARAM_POS_FIXED_PT
] = f32
;
2414 num_params
= SI_PARAM_POS_FIXED_PT
+1;
2418 assert(0 && "unimplemented shader");
2422 assert(num_params
<= Elements(params
));
2423 radeon_llvm_create_func(&si_shader_ctx
->radeon_bld
, params
, num_params
);
2424 radeon_llvm_shader_type(si_shader_ctx
->radeon_bld
.main_fn
, si_shader_ctx
->type
);
2426 for (i
= 0; i
<= last_sgpr
; ++i
) {
2427 LLVMValueRef P
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, i
);
2430 LLVMAddAttribute(P
, LLVMInRegAttribute
);
2432 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2433 * to move load. Inputs are constant so this is fine. */
2434 case SI_PARAM_CONST
:
2435 case SI_PARAM_SAMPLER
:
2436 case SI_PARAM_RESOURCE
:
2437 LLVMAddAttribute(P
, LLVMByValAttribute
);
2442 if (bld_base
->info
&&
2443 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
2444 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0))
2445 si_shader_ctx
->ddxy_lds
=
2446 LLVMAddGlobalInAddressSpace(gallivm
->module
,
2447 LLVMArrayType(i32
, 64),
2452 static void preload_constants(struct si_shader_context
*si_shader_ctx
)
2454 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2455 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2456 const struct tgsi_shader_info
* info
= bld_base
->info
;
2458 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST
);
2460 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
2461 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
2466 /* Allocate space for the constant values */
2467 si_shader_ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
2469 /* Load the resource descriptor */
2470 si_shader_ctx
->const_resource
[buf
] =
2471 build_indexed_load(si_shader_ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
2473 /* Load the constants, we rely on the code sinking to do the rest */
2474 for (i
= 0; i
< num_const
* 4; ++i
) {
2475 si_shader_ctx
->constants
[buf
][i
] =
2476 load_const(gallivm
->builder
,
2477 si_shader_ctx
->const_resource
[buf
],
2478 lp_build_const_int32(gallivm
, i
* 4),
2479 bld_base
->base
.elem_type
);
2484 static void preload_samplers(struct si_shader_context
*si_shader_ctx
)
2486 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2487 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2488 const struct tgsi_shader_info
* info
= bld_base
->info
;
2490 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
2492 LLVMValueRef res_ptr
, samp_ptr
;
2493 LLVMValueRef offset
;
2495 if (num_samplers
== 0)
2498 /* Allocate space for the values */
2499 si_shader_ctx
->resources
= CALLOC(SI_NUM_SAMPLER_VIEWS
, sizeof(LLVMValueRef
));
2500 si_shader_ctx
->samplers
= CALLOC(num_samplers
, sizeof(LLVMValueRef
));
2502 res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_RESOURCE
);
2503 samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER
);
2505 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2506 for (i
= 0; i
< num_samplers
; ++i
) {
2508 offset
= lp_build_const_int32(gallivm
, i
);
2509 si_shader_ctx
->resources
[i
] = build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
2512 offset
= lp_build_const_int32(gallivm
, i
);
2513 si_shader_ctx
->samplers
[i
] = build_indexed_load(si_shader_ctx
, samp_ptr
, offset
);
2515 /* FMASK resource */
2516 if (info
->is_msaa_sampler
[i
]) {
2517 offset
= lp_build_const_int32(gallivm
, SI_FMASK_TEX_OFFSET
+ i
);
2518 si_shader_ctx
->resources
[SI_FMASK_TEX_OFFSET
+ i
] =
2519 build_indexed_load(si_shader_ctx
, res_ptr
, offset
);
2524 static void preload_streamout_buffers(struct si_shader_context
*si_shader_ctx
)
2526 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2527 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
2530 if (si_shader_ctx
->type
!= TGSI_PROCESSOR_VERTEX
||
2531 si_shader_ctx
->shader
->key
.vs
.as_es
||
2532 !si_shader_ctx
->shader
->selector
->so
.num_outputs
)
2535 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2536 SI_PARAM_RW_BUFFERS
);
2538 /* Load the resources, we rely on the code sinking to do the rest */
2539 for (i
= 0; i
< 4; ++i
) {
2540 if (si_shader_ctx
->shader
->selector
->so
.stride
[i
]) {
2541 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
2542 SI_SO_BUF_OFFSET
+ i
);
2544 si_shader_ctx
->so_buffers
[i
] = build_indexed_load(si_shader_ctx
, buf_ptr
, offset
);
2549 int si_compile_llvm(struct si_context
*sctx
, struct si_shader
*shader
,
2552 unsigned r
; /* llvm_compile result */
2555 struct radeon_shader_binary binary
;
2556 bool dump
= r600_can_dump_shader(&sctx
->screen
->b
,
2557 shader
->selector
? shader
->selector
->tokens
: NULL
);
2558 const char * gpu_family
= r600_get_llvm_processor_name(sctx
->screen
->b
.family
);
2561 /* Use LLVM to compile shader */
2562 memset(&binary
, 0, sizeof(binary
));
2563 r
= radeon_llvm_compile(mod
, &binary
, gpu_family
, dump
);
2565 /* Output binary dump if rscreen->debug_flags are set */
2566 if (dump
&& ! binary
.disassembled
) {
2567 fprintf(stderr
, "SI CODE:\n");
2568 for (i
= 0; i
< binary
.code_size
; i
+=4 ) {
2569 fprintf(stderr
, "%02x%02x%02x%02x\n", binary
.code
[i
+ 3],
2570 binary
.code
[i
+ 2], binary
.code
[i
+ 1],
2575 /* XXX: We may be able to emit some of these values directly rather than
2576 * extracting fields to be emitted later.
2578 /* Parse config data in compiled binary */
2579 for (i
= 0; i
< binary
.config_size
; i
+= 8) {
2580 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
));
2581 unsigned value
= util_le32_to_cpu(*(uint32_t*)(binary
.config
+ i
+ 4));
2583 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
2584 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
2585 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
2586 case R_00B848_COMPUTE_PGM_RSRC1
:
2587 shader
->num_sgprs
= (G_00B028_SGPRS(value
) + 1) * 8;
2588 shader
->num_vgprs
= (G_00B028_VGPRS(value
) + 1) * 4;
2590 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
2591 shader
->lds_size
= G_00B02C_EXTRA_LDS_SIZE(value
);
2593 case R_00B84C_COMPUTE_PGM_RSRC2
:
2594 shader
->lds_size
= G_00B84C_LDS_SIZE(value
);
2596 case R_0286CC_SPI_PS_INPUT_ENA
:
2597 shader
->spi_ps_input_ena
= value
;
2599 case R_00B860_COMPUTE_TMPRING_SIZE
:
2600 /* WAVESIZE is in units of 256 dwords. */
2601 shader
->scratch_bytes_per_wave
=
2602 G_00B860_WAVESIZE(value
) * 256 * 4 * 1;
2605 fprintf(stderr
, "Warning: Compiler emitted unknown "
2606 "config register: 0x%x\n", reg
);
2611 /* copy new shader */
2612 code_size
= binary
.code_size
+ binary
.rodata_size
;
2613 r600_resource_reference(&shader
->bo
, NULL
);
2614 shader
->bo
= si_resource_create_custom(sctx
->b
.b
.screen
, PIPE_USAGE_IMMUTABLE
,
2616 if (shader
->bo
== NULL
) {
2620 ptr
= sctx
->b
.ws
->buffer_map(shader
->bo
->cs_buf
, sctx
->b
.rings
.gfx
.cs
, PIPE_TRANSFER_WRITE
);
2621 util_memcpy_cpu_to_le32(ptr
, binary
.code
, binary
.code_size
);
2622 if (binary
.rodata_size
> 0) {
2623 ptr
+= binary
.code_size
;
2624 util_memcpy_cpu_to_le32(ptr
, binary
.rodata
, binary
.rodata_size
);
2627 sctx
->b
.ws
->buffer_unmap(shader
->bo
->cs_buf
);
2630 free(binary
.config
);
2631 free(binary
.rodata
);
2636 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2637 static int si_generate_gs_copy_shader(struct si_context
*sctx
,
2638 struct si_shader_context
*si_shader_ctx
,
2641 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
2642 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
2643 struct lp_build_context
*base
= &bld_base
->base
;
2644 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2645 struct si_shader
*shader
= si_shader_ctx
->shader
;
2646 struct si_shader
*gs
= si_shader_ctx
->shader
->selector
->current
;
2647 struct si_shader_output_values
*outputs
;
2648 LLVMValueRef t_list_ptr
, t_list
;
2649 LLVMValueRef args
[9];
2652 outputs
= MALLOC(gs
->noutput
* sizeof(outputs
[0]));
2654 si_shader_ctx
->type
= TGSI_PROCESSOR_VERTEX
;
2655 si_shader_ctx
->gs_for_vs
= gs
;
2657 radeon_llvm_context_init(&si_shader_ctx
->radeon_bld
);
2659 create_meta_data(si_shader_ctx
);
2660 create_function(si_shader_ctx
);
2661 preload_streamout_buffers(si_shader_ctx
);
2663 /* Load the GSVS ring resource descriptor */
2664 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2665 SI_PARAM_RW_BUFFERS
);
2666 t_list
= build_indexed_load(si_shader_ctx
, t_list_ptr
,
2667 lp_build_const_int32(gallivm
, SI_RING_GSVS
));
2670 args
[1] = lp_build_mul_imm(uint
,
2671 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2672 si_shader_ctx
->param_vertex_id
),
2674 args
[3] = uint
->zero
;
2675 args
[4] = uint
->one
; /* OFFEN */
2676 args
[5] = uint
->zero
; /* IDXEN */
2677 args
[6] = uint
->one
; /* GLC */
2678 args
[7] = uint
->one
; /* SLC */
2679 args
[8] = uint
->zero
; /* TFE */
2681 /* Fetch vertex data from GSVS ring */
2682 for (i
= 0; i
< gs
->noutput
; ++i
) {
2683 struct si_shader_output
*out
= gs
->output
+ i
;
2686 shader
->output
[i
] = *out
;
2688 outputs
[i
].name
= out
->name
;
2689 outputs
[i
].index
= out
->index
;
2690 outputs
[i
].sid
= out
->sid
;
2691 outputs
[i
].usage
= out
->usage
;
2693 for (chan
= 0; chan
< 4; chan
++) {
2694 args
[2] = lp_build_const_int32(gallivm
,
2696 gs
->gs_max_out_vertices
* 16 * 4);
2698 outputs
[i
].values
[chan
] =
2699 LLVMBuildBitCast(gallivm
->builder
,
2700 build_intrinsic(gallivm
->builder
,
2701 "llvm.SI.buffer.load.dword.i32.i32",
2702 LLVMInt32TypeInContext(gallivm
->context
),
2704 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
2705 base
->elem_type
, "");
2708 shader
->noutput
= gs
->noutput
;
2710 si_llvm_export_vs(bld_base
, outputs
, gs
->noutput
);
2712 radeon_llvm_finalize_module(&si_shader_ctx
->radeon_bld
);
2715 fprintf(stderr
, "Copy Vertex Shader for Geometry Shader:\n\n");
2717 r
= si_compile_llvm(sctx
, si_shader_ctx
->shader
,
2718 bld_base
->base
.gallivm
->module
);
2720 radeon_llvm_dispose(&si_shader_ctx
->radeon_bld
);
2726 int si_pipe_shader_create(
2727 struct pipe_context
*ctx
,
2728 struct si_shader
*shader
)
2730 struct si_context
*sctx
= (struct si_context
*)ctx
;
2731 struct si_pipe_shader_selector
*sel
= shader
->selector
;
2732 struct si_shader_context si_shader_ctx
;
2733 struct tgsi_shader_info shader_info
;
2734 struct lp_build_tgsi_context
* bld_base
;
2737 bool dump
= r600_can_dump_shader(&sctx
->screen
->b
, sel
->tokens
);
2739 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2740 * conversion fails. */
2742 tgsi_dump(sel
->tokens
, 0);
2743 si_dump_streamout(&sel
->so
);
2746 assert(shader
->noutput
== 0);
2747 assert(shader
->nparam
== 0);
2748 assert(shader
->ninput
== 0);
2750 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
2751 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
2752 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
2754 tgsi_scan_shader(sel
->tokens
, &shader_info
);
2756 if (shader_info
.uses_kill
)
2757 shader
->db_shader_control
|= S_02880C_KILL_ENABLE(1);
2759 shader
->uses_instanceid
= shader_info
.uses_instanceid
;
2760 bld_base
->info
= &shader_info
;
2761 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
2763 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
2764 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
2765 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
2766 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
2767 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
2768 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
2769 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
2770 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
2771 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
2772 bld_base
->op_actions
[TGSI_OPCODE_TXQ
] = txq_action
;
2773 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
2774 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
2776 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
2777 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
2779 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
2780 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
2782 si_shader_ctx
.radeon_bld
.load_system_value
= declare_system_value
;
2783 si_shader_ctx
.tokens
= sel
->tokens
;
2784 tgsi_parse_init(&si_shader_ctx
.parse
, si_shader_ctx
.tokens
);
2785 si_shader_ctx
.shader
= shader
;
2786 si_shader_ctx
.type
= si_shader_ctx
.parse
.FullHeader
.Processor
.Processor
;
2788 switch (si_shader_ctx
.type
) {
2789 case TGSI_PROCESSOR_VERTEX
:
2790 si_shader_ctx
.radeon_bld
.load_input
= declare_input_vs
;
2791 if (shader
->key
.vs
.as_es
) {
2792 si_shader_ctx
.gs_for_vs
= sctx
->gs_shader
->current
;
2793 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
2795 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
2798 case TGSI_PROCESSOR_GEOMETRY
: {
2801 si_shader_ctx
.radeon_bld
.load_input
= declare_input_gs
;
2802 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
2803 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
2805 for (i
= 0; i
< shader_info
.num_properties
; i
++) {
2806 switch (shader_info
.properties
[i
].name
) {
2807 case TGSI_PROPERTY_GS_INPUT_PRIM
:
2808 shader
->gs_input_prim
= shader_info
.properties
[i
].data
[0];
2810 case TGSI_PROPERTY_GS_OUTPUT_PRIM
:
2811 shader
->gs_output_prim
= shader_info
.properties
[i
].data
[0];
2813 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
:
2814 shader
->gs_max_out_vertices
= shader_info
.properties
[i
].data
[0];
2820 case TGSI_PROCESSOR_FRAGMENT
: {
2823 si_shader_ctx
.radeon_bld
.load_input
= declare_input_fs
;
2824 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
2826 for (i
= 0; i
< shader_info
.num_properties
; i
++) {
2827 switch (shader_info
.properties
[i
].name
) {
2828 case TGSI_PROPERTY_FS_DEPTH_LAYOUT
:
2829 switch (shader_info
.properties
[i
].data
[0]) {
2830 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2831 shader
->db_shader_control
|=
2832 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2834 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2835 shader
->db_shader_control
|=
2836 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2845 assert(!"Unsupported shader type");
2849 create_meta_data(&si_shader_ctx
);
2850 create_function(&si_shader_ctx
);
2851 preload_constants(&si_shader_ctx
);
2852 preload_samplers(&si_shader_ctx
);
2853 preload_streamout_buffers(&si_shader_ctx
);
2855 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2856 si_shader_ctx
.gs_next_vertex
=
2857 lp_build_alloca(bld_base
->base
.gallivm
,
2858 bld_base
->uint_bld
.elem_type
, "");
2861 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
2862 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
2866 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
2868 mod
= bld_base
->base
.gallivm
->module
;
2869 r
= si_compile_llvm(sctx
, shader
, mod
);
2871 fprintf(stderr
, "LLVM failed to compile shader\n");
2875 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
2877 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2878 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
2879 shader
->gs_copy_shader
->selector
= shader
->selector
;
2880 shader
->gs_copy_shader
->key
= shader
->key
;
2881 si_shader_ctx
.shader
= shader
->gs_copy_shader
;
2882 if ((r
= si_generate_gs_copy_shader(sctx
, &si_shader_ctx
, dump
))) {
2883 free(shader
->gs_copy_shader
);
2884 shader
->gs_copy_shader
= NULL
;
2889 tgsi_parse_free(&si_shader_ctx
.parse
);
2892 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
2893 FREE(si_shader_ctx
.constants
[i
]);
2894 FREE(si_shader_ctx
.resources
);
2895 FREE(si_shader_ctx
.samplers
);
2900 void si_pipe_shader_destroy(struct pipe_context
*ctx
, struct si_shader
*shader
)
2902 r600_resource_reference(&shader
->bo
, NULL
);