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radeonsi: remove si_llvm_add_attribute
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, false, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 enum si_tess_ring {
1179 TCS_FACTOR_RING,
1180 TESS_OFFCHIP_RING_TCS,
1181 TESS_OFFCHIP_RING_TES,
1182 };
1183
1184 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1185 enum si_tess_ring ring)
1186 {
1187 LLVMBuilderRef builder = ctx->ac.builder;
1188 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1189 ctx->param_tcs_out_lds_layout;
1190 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1191
1192 /* TCS only receives high 13 bits of the address. */
1193 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1194 addr = LLVMBuildAnd(builder, addr,
1195 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1196 }
1197
1198 if (ring == TCS_FACTOR_RING) {
1199 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1200 addr = LLVMBuildAdd(builder, addr,
1201 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1202 }
1203
1204 LLVMValueRef desc[4];
1205 desc[0] = addr;
1206 desc[1] = LLVMConstInt(ctx->i32,
1207 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1208 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1209 desc[3] = LLVMConstInt(ctx->i32,
1210 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1211 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1212 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1213 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1214 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1215 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1216
1217 return ac_build_gather_values(&ctx->ac, desc, 4);
1218 }
1219
1220 static LLVMValueRef fetch_input_tcs(
1221 struct lp_build_tgsi_context *bld_base,
1222 const struct tgsi_full_src_register *reg,
1223 enum tgsi_opcode_type type, unsigned swizzle)
1224 {
1225 struct si_shader_context *ctx = si_shader_context(bld_base);
1226 LLVMValueRef dw_addr, stride;
1227
1228 stride = get_tcs_in_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_in_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1231
1232 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1233 }
1234
1235 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1236 LLVMTypeRef type,
1237 LLVMValueRef vertex_index,
1238 LLVMValueRef param_index,
1239 unsigned const_index,
1240 unsigned location,
1241 unsigned driver_location,
1242 unsigned component,
1243 unsigned num_components,
1244 bool is_patch,
1245 bool is_compact,
1246 bool load_input)
1247 {
1248 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1249 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1250 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1251 LLVMValueRef dw_addr, stride;
1252
1253 driver_location = driver_location / 4;
1254
1255 if (load_input) {
1256 stride = get_tcs_in_vertex_dw_stride(ctx);
1257 dw_addr = get_tcs_in_current_patch_offset(ctx);
1258 } else {
1259 if (is_patch) {
1260 stride = NULL;
1261 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1262 } else {
1263 stride = get_tcs_out_vertex_dw_stride(ctx);
1264 dw_addr = get_tcs_out_current_patch_offset(ctx);
1265 }
1266 }
1267
1268 if (param_index) {
1269 /* Add the constant index to the indirect index */
1270 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1271 LLVMConstInt(ctx->i32, const_index, 0), "");
1272 } else {
1273 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1274 }
1275
1276 ubyte *names;
1277 ubyte *indices;
1278 if (load_input) {
1279 names = info->input_semantic_name;
1280 indices = info->input_semantic_index;
1281 } else {
1282 names = info->output_semantic_name;
1283 indices = info->output_semantic_index;
1284 }
1285
1286 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1287 vertex_index, param_index,
1288 driver_location,
1289 names, indices,
1290 is_patch);
1291
1292 LLVMValueRef value[4];
1293 for (unsigned i = 0; i < num_components + component; i++) {
1294 unsigned offset = i;
1295 if (llvm_type_is_64bit(ctx, type))
1296 offset *= 2;
1297
1298 value[i] = lds_load(bld_base, type, offset, dw_addr);
1299 }
1300
1301 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1302 }
1303
1304 static LLVMValueRef fetch_output_tcs(
1305 struct lp_build_tgsi_context *bld_base,
1306 const struct tgsi_full_src_register *reg,
1307 enum tgsi_opcode_type type, unsigned swizzle)
1308 {
1309 struct si_shader_context *ctx = si_shader_context(bld_base);
1310 LLVMValueRef dw_addr, stride;
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1316 } else {
1317 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1318 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1319 }
1320
1321 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1322 }
1323
1324 static LLVMValueRef fetch_input_tes(
1325 struct lp_build_tgsi_context *bld_base,
1326 const struct tgsi_full_src_register *reg,
1327 enum tgsi_opcode_type type, unsigned swizzle)
1328 {
1329 struct si_shader_context *ctx = si_shader_context(bld_base);
1330 LLVMValueRef base, addr;
1331
1332 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1333 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1334
1335 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1336 ctx->tess_offchip_ring, base, addr, true);
1337 }
1338
1339 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1340 LLVMTypeRef type,
1341 LLVMValueRef vertex_index,
1342 LLVMValueRef param_index,
1343 unsigned const_index,
1344 unsigned location,
1345 unsigned driver_location,
1346 unsigned component,
1347 unsigned num_components,
1348 bool is_patch,
1349 bool is_compact,
1350 bool load_input)
1351 {
1352 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1353 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1354 LLVMValueRef base, addr;
1355
1356 driver_location = driver_location / 4;
1357
1358 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1359
1360 if (param_index) {
1361 /* Add the constant index to the indirect index */
1362 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1363 LLVMConstInt(ctx->i32, const_index, 0), "");
1364 } else {
1365 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1366 }
1367
1368 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1369 param_index, driver_location,
1370 info->input_semantic_name,
1371 info->input_semantic_index,
1372 is_patch);
1373
1374 /* TODO: This will generate rather ordinary llvm code, although it
1375 * should be easy for the optimiser to fix up. In future we might want
1376 * to refactor buffer_load(), but for now this maximises code sharing
1377 * between the NIR and TGSI backends.
1378 */
1379 LLVMValueRef value[4];
1380 for (unsigned i = component; i < num_components + component; i++) {
1381 unsigned offset = i;
1382 if (llvm_type_is_64bit(ctx, type))
1383 offset *= 2;
1384
1385 value[i] = buffer_load(&ctx->bld_base, type, offset,
1386 ctx->tess_offchip_ring, base, addr, true);
1387 }
1388
1389 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1390 }
1391
1392 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1393 const struct tgsi_full_instruction *inst,
1394 const struct tgsi_opcode_info *info,
1395 unsigned index,
1396 LLVMValueRef dst[4])
1397 {
1398 struct si_shader_context *ctx = si_shader_context(bld_base);
1399 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1400 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1401 unsigned chan_index;
1402 LLVMValueRef dw_addr, stride;
1403 LLVMValueRef buffer, base, buf_addr;
1404 LLVMValueRef values[4];
1405 bool skip_lds_store;
1406 bool is_tess_factor = false, is_tess_inner = false;
1407
1408 /* Only handle per-patch and per-vertex outputs here.
1409 * Vectors will be lowered to scalars and this function will be called again.
1410 */
1411 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1412 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1413 si_llvm_emit_store(bld_base, inst, info, index, dst);
1414 return;
1415 }
1416
1417 if (reg->Register.Dimension) {
1418 stride = get_tcs_out_vertex_dw_stride(ctx);
1419 dw_addr = get_tcs_out_current_patch_offset(ctx);
1420 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1421 skip_lds_store = !sh_info->reads_pervertex_outputs;
1422 } else {
1423 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1424 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1425 skip_lds_store = !sh_info->reads_perpatch_outputs;
1426
1427 if (!reg->Register.Indirect) {
1428 int name = sh_info->output_semantic_name[reg->Register.Index];
1429
1430 /* Always write tess factors into LDS for the TCS epilog. */
1431 if (name == TGSI_SEMANTIC_TESSINNER ||
1432 name == TGSI_SEMANTIC_TESSOUTER) {
1433 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1434 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1435 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1436 is_tess_factor = true;
1437 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1438 }
1439 }
1440 }
1441
1442 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1443
1444 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1445 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1446
1447 uint32_t writemask = reg->Register.WriteMask;
1448 while (writemask) {
1449 chan_index = u_bit_scan(&writemask);
1450 LLVMValueRef value = dst[chan_index];
1451
1452 if (inst->Instruction.Saturate)
1453 value = ac_build_clamp(&ctx->ac, value);
1454
1455 /* Skip LDS stores if there is no LDS read of this output. */
1456 if (!skip_lds_store)
1457 lds_store(ctx, chan_index, dw_addr, value);
1458
1459 value = ac_to_integer(&ctx->ac, value);
1460 values[chan_index] = value;
1461
1462 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1463 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1464 buf_addr, base,
1465 4 * chan_index, 1, 0, true, false);
1466 }
1467
1468 /* Write tess factors into VGPRs for the epilog. */
1469 if (is_tess_factor &&
1470 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1471 if (!is_tess_inner) {
1472 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1473 ctx->invoc0_tess_factors[chan_index]);
1474 } else if (chan_index < 2) {
1475 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1476 ctx->invoc0_tess_factors[4 + chan_index]);
1477 }
1478 }
1479 }
1480
1481 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1482 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1483 values, 4);
1484 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1485 base, 0, 1, 0, true, false);
1486 }
1487 }
1488
1489 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1490 LLVMValueRef vertex_index,
1491 LLVMValueRef param_index,
1492 unsigned const_index,
1493 unsigned location,
1494 unsigned driver_location,
1495 LLVMValueRef src,
1496 unsigned component,
1497 bool is_patch,
1498 bool is_compact,
1499 unsigned writemask)
1500 {
1501 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1502 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1503 LLVMValueRef dw_addr, stride;
1504 LLVMValueRef buffer, base, addr;
1505 LLVMValueRef values[4];
1506 bool skip_lds_store;
1507 bool is_tess_factor = false, is_tess_inner = false;
1508
1509 driver_location = driver_location / 4;
1510
1511 if (param_index) {
1512 /* Add the constant index to the indirect index */
1513 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1514 LLVMConstInt(ctx->i32, const_index, 0), "");
1515 } else {
1516 if (const_index != 0)
1517 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1518 }
1519
1520 if (!is_patch) {
1521 stride = get_tcs_out_vertex_dw_stride(ctx);
1522 dw_addr = get_tcs_out_current_patch_offset(ctx);
1523 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1524 vertex_index, param_index,
1525 driver_location,
1526 info->output_semantic_name,
1527 info->output_semantic_index,
1528 is_patch);
1529
1530 skip_lds_store = !info->reads_pervertex_outputs;
1531 } else {
1532 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1533 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1534 vertex_index, param_index,
1535 driver_location,
1536 info->output_semantic_name,
1537 info->output_semantic_index,
1538 is_patch);
1539
1540 skip_lds_store = !info->reads_perpatch_outputs;
1541
1542 if (!param_index) {
1543 int name = info->output_semantic_name[driver_location];
1544
1545 /* Always write tess factors into LDS for the TCS epilog. */
1546 if (name == TGSI_SEMANTIC_TESSINNER ||
1547 name == TGSI_SEMANTIC_TESSOUTER) {
1548 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1549 skip_lds_store = !info->reads_tessfactor_outputs &&
1550 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1551 is_tess_factor = true;
1552 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1553 }
1554 }
1555 }
1556
1557 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1558
1559 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1560
1561 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1562 param_index, driver_location,
1563 info->output_semantic_name,
1564 info->output_semantic_index,
1565 is_patch);
1566
1567 for (unsigned chan = 0; chan < 4; chan++) {
1568 if (!(writemask & (1 << chan)))
1569 continue;
1570 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1571
1572 /* Skip LDS stores if there is no LDS read of this output. */
1573 if (!skip_lds_store)
1574 lds_store(ctx, chan, dw_addr, value);
1575
1576 value = ac_to_integer(&ctx->ac, value);
1577 values[chan] = value;
1578
1579 if (writemask != 0xF && !is_tess_factor) {
1580 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1581 addr, base,
1582 4 * chan, 1, 0, true, false);
1583 }
1584
1585 /* Write tess factors into VGPRs for the epilog. */
1586 if (is_tess_factor &&
1587 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1588 if (!is_tess_inner) {
1589 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1590 ctx->invoc0_tess_factors[chan]);
1591 } else if (chan < 2) {
1592 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1593 ctx->invoc0_tess_factors[4 + chan]);
1594 }
1595 }
1596 }
1597
1598 if (writemask == 0xF && !is_tess_factor) {
1599 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1600 values, 4);
1601 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1602 base, 0, 1, 0, true, false);
1603 }
1604 }
1605
1606 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1607 unsigned input_index,
1608 unsigned vtx_offset_param,
1609 LLVMTypeRef type,
1610 unsigned swizzle)
1611 {
1612 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1613 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1614 struct si_shader *shader = ctx->shader;
1615 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1616 LLVMValueRef vtx_offset, soffset;
1617 struct tgsi_shader_info *info = &shader->selector->info;
1618 unsigned semantic_name = info->input_semantic_name[input_index];
1619 unsigned semantic_index = info->input_semantic_index[input_index];
1620 unsigned param;
1621 LLVMValueRef value;
1622
1623 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1624
1625 /* GFX9 has the ESGS ring in LDS. */
1626 if (ctx->screen->info.chip_class >= GFX9) {
1627 unsigned index = vtx_offset_param;
1628
1629 switch (index / 2) {
1630 case 0:
1631 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1632 index % 2 ? 16 : 0, 16);
1633 break;
1634 case 1:
1635 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1636 index % 2 ? 16 : 0, 16);
1637 break;
1638 case 2:
1639 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1640 index % 2 ? 16 : 0, 16);
1641 break;
1642 default:
1643 assert(0);
1644 return NULL;
1645 }
1646
1647 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1648 LLVMConstInt(ctx->i32, param * 4, 0), "");
1649 return lds_load(bld_base, type, swizzle, vtx_offset);
1650 }
1651
1652 /* GFX6: input load from the ESGS ring in memory. */
1653 if (swizzle == ~0) {
1654 LLVMValueRef values[TGSI_NUM_CHANNELS];
1655 unsigned chan;
1656 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1657 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1658 type, chan);
1659 }
1660 return lp_build_gather_values(&ctx->gallivm, values,
1661 TGSI_NUM_CHANNELS);
1662 }
1663
1664 /* Get the vertex offset parameter on GFX6. */
1665 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1666
1667 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1668
1669 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1670
1671 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1672 vtx_offset, soffset, 0, 1, 0, true, false);
1673 if (llvm_type_is_64bit(ctx, type)) {
1674 LLVMValueRef value2;
1675 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1676
1677 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1678 ctx->i32_0, vtx_offset, soffset,
1679 0, 1, 0, true, false);
1680 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1681 }
1682 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1683 }
1684
1685 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1686 unsigned location,
1687 unsigned driver_location,
1688 unsigned component,
1689 unsigned num_components,
1690 unsigned vertex_index,
1691 unsigned const_index,
1692 LLVMTypeRef type)
1693 {
1694 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1695
1696 LLVMValueRef value[4];
1697 for (unsigned i = component; i < num_components + component; i++) {
1698 unsigned offset = i;
1699 if (llvm_type_is_64bit(ctx, type))
1700 offset *= 2;
1701
1702 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1703 vertex_index, type, offset);
1704 }
1705
1706 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1707 }
1708
1709 static LLVMValueRef fetch_input_gs(
1710 struct lp_build_tgsi_context *bld_base,
1711 const struct tgsi_full_src_register *reg,
1712 enum tgsi_opcode_type type,
1713 unsigned swizzle)
1714 {
1715 struct si_shader_context *ctx = si_shader_context(bld_base);
1716 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1717
1718 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1719 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1720 return get_primitive_id(ctx, swizzle);
1721
1722 if (!reg->Register.Dimension)
1723 return NULL;
1724
1725 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1726 reg->Dimension.Index,
1727 tgsi2llvmtype(bld_base, type),
1728 swizzle);
1729 }
1730
1731 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1732 {
1733 switch (interpolate) {
1734 case TGSI_INTERPOLATE_CONSTANT:
1735 return 0;
1736
1737 case TGSI_INTERPOLATE_LINEAR:
1738 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1739 return SI_PARAM_LINEAR_SAMPLE;
1740 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1741 return SI_PARAM_LINEAR_CENTROID;
1742 else
1743 return SI_PARAM_LINEAR_CENTER;
1744 break;
1745 case TGSI_INTERPOLATE_COLOR:
1746 case TGSI_INTERPOLATE_PERSPECTIVE:
1747 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1748 return SI_PARAM_PERSP_SAMPLE;
1749 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1750 return SI_PARAM_PERSP_CENTROID;
1751 else
1752 return SI_PARAM_PERSP_CENTER;
1753 break;
1754 default:
1755 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1756 return -1;
1757 }
1758 }
1759
1760 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1761 unsigned attr_index, unsigned chan,
1762 LLVMValueRef prim_mask,
1763 LLVMValueRef i, LLVMValueRef j)
1764 {
1765 if (i || j) {
1766 return ac_build_fs_interp(&ctx->ac,
1767 LLVMConstInt(ctx->i32, chan, 0),
1768 LLVMConstInt(ctx->i32, attr_index, 0),
1769 prim_mask, i, j);
1770 }
1771 return ac_build_fs_interp_mov(&ctx->ac,
1772 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1773 LLVMConstInt(ctx->i32, chan, 0),
1774 LLVMConstInt(ctx->i32, attr_index, 0),
1775 prim_mask);
1776 }
1777
1778 /**
1779 * Interpolate a fragment shader input.
1780 *
1781 * @param ctx context
1782 * @param input_index index of the input in hardware
1783 * @param semantic_name TGSI_SEMANTIC_*
1784 * @param semantic_index semantic index
1785 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1786 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1787 * @param interp_param interpolation weights (i,j)
1788 * @param prim_mask SI_PARAM_PRIM_MASK
1789 * @param face SI_PARAM_FRONT_FACE
1790 * @param result the return value (4 components)
1791 */
1792 static void interp_fs_input(struct si_shader_context *ctx,
1793 unsigned input_index,
1794 unsigned semantic_name,
1795 unsigned semantic_index,
1796 unsigned num_interp_inputs,
1797 unsigned colors_read_mask,
1798 LLVMValueRef interp_param,
1799 LLVMValueRef prim_mask,
1800 LLVMValueRef face,
1801 LLVMValueRef result[4])
1802 {
1803 LLVMValueRef i = NULL, j = NULL;
1804 unsigned chan;
1805
1806 /* fs.constant returns the param from the middle vertex, so it's not
1807 * really useful for flat shading. It's meant to be used for custom
1808 * interpolation (but the intrinsic can't fetch from the other two
1809 * vertices).
1810 *
1811 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1812 * to do the right thing. The only reason we use fs.constant is that
1813 * fs.interp cannot be used on integers, because they can be equal
1814 * to NaN.
1815 *
1816 * When interp is false we will use fs.constant or for newer llvm,
1817 * amdgcn.interp.mov.
1818 */
1819 bool interp = interp_param != NULL;
1820
1821 if (interp) {
1822 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1823 LLVMVectorType(ctx->f32, 2), "");
1824
1825 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1826 ctx->i32_0, "");
1827 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1828 ctx->i32_1, "");
1829 }
1830
1831 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1832 ctx->shader->key.part.ps.prolog.color_two_side) {
1833 LLVMValueRef is_face_positive;
1834
1835 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1836 * otherwise it's at offset "num_inputs".
1837 */
1838 unsigned back_attr_offset = num_interp_inputs;
1839 if (semantic_index == 1 && colors_read_mask & 0xf)
1840 back_attr_offset += 1;
1841
1842 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1843 face, ctx->i32_0, "");
1844
1845 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1846 LLVMValueRef front, back;
1847
1848 front = si_build_fs_interp(ctx,
1849 input_index, chan,
1850 prim_mask, i, j);
1851 back = si_build_fs_interp(ctx,
1852 back_attr_offset, chan,
1853 prim_mask, i, j);
1854
1855 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1856 is_face_positive,
1857 front,
1858 back,
1859 "");
1860 }
1861 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1862 result[0] = si_build_fs_interp(ctx, input_index,
1863 0, prim_mask, i, j);
1864 result[1] =
1865 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1866 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1867 } else {
1868 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1869 result[chan] = si_build_fs_interp(ctx,
1870 input_index, chan,
1871 prim_mask, i, j);
1872 }
1873 }
1874 }
1875
1876 void si_llvm_load_input_fs(
1877 struct si_shader_context *ctx,
1878 unsigned input_index,
1879 LLVMValueRef out[4])
1880 {
1881 struct lp_build_context *base = &ctx->bld_base.base;
1882 struct si_shader *shader = ctx->shader;
1883 struct tgsi_shader_info *info = &shader->selector->info;
1884 LLVMValueRef main_fn = ctx->main_fn;
1885 LLVMValueRef interp_param = NULL;
1886 int interp_param_idx;
1887 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1888 unsigned semantic_index = info->input_semantic_index[input_index];
1889 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1890 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1891
1892 /* Get colors from input VGPRs (set by the prolog). */
1893 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1894 unsigned colors_read = shader->selector->info.colors_read;
1895 unsigned mask = colors_read >> (semantic_index * 4);
1896 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1897 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1898
1899 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1900 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1901 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1902 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1903 return;
1904 }
1905
1906 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1907 if (interp_param_idx == -1)
1908 return;
1909 else if (interp_param_idx) {
1910 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1911 }
1912
1913 interp_fs_input(ctx, input_index, semantic_name,
1914 semantic_index, 0, /* this param is unused */
1915 shader->selector->info.colors_read, interp_param,
1916 ctx->abi.prim_mask,
1917 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1918 &out[0]);
1919 }
1920
1921 static void declare_input_fs(
1922 struct si_shader_context *ctx,
1923 unsigned input_index,
1924 const struct tgsi_full_declaration *decl,
1925 LLVMValueRef out[4])
1926 {
1927 si_llvm_load_input_fs(ctx, input_index, out);
1928 }
1929
1930 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1931 {
1932 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1933 }
1934
1935 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1936 {
1937 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1938
1939 /* For non-indexed draws, the base vertex set by the driver
1940 * (for direct draws) or the CP (for indirect draws) is the
1941 * first vertex ID, but GLSL expects 0 to be returned.
1942 */
1943 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1944 ctx->param_vs_state_bits);
1945 LLVMValueRef indexed;
1946
1947 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1948 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1949
1950 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1951 ctx->i32_0, "");
1952 }
1953
1954 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1955 {
1956 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1957
1958 LLVMValueRef values[3];
1959 LLVMValueRef result;
1960 unsigned i;
1961 unsigned *properties = ctx->shader->selector->info.properties;
1962
1963 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1964 unsigned sizes[3] = {
1965 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1966 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1967 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1968 };
1969
1970 for (i = 0; i < 3; ++i)
1971 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1972
1973 result = lp_build_gather_values(&ctx->gallivm, values, 3);
1974 } else {
1975 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1976 }
1977
1978 return result;
1979 }
1980
1981 /**
1982 * Load a dword from a constant buffer.
1983 */
1984 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1985 LLVMValueRef resource,
1986 LLVMValueRef offset)
1987 {
1988 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1989 0, 0, 0, true, true);
1990 }
1991
1992 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1993 {
1994 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1995 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1996 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1997 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1998 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1999
2000 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2001 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
2002 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
2003
2004 LLVMValueRef pos[4] = {
2005 buffer_load_const(ctx, resource, offset0),
2006 buffer_load_const(ctx, resource, offset1),
2007 LLVMConstReal(ctx->f32, 0),
2008 LLVMConstReal(ctx->f32, 0)
2009 };
2010
2011 return lp_build_gather_values(&ctx->gallivm, pos, 4);
2012 }
2013
2014 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
2015 {
2016 return abi->sample_coverage;
2017 }
2018
2019 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2020 {
2021 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2022 struct lp_build_context *bld = &ctx->bld_base.base;
2023
2024 LLVMValueRef coord[4] = {
2025 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2026 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2027 ctx->ac.f32_0,
2028 ctx->ac.f32_0
2029 };
2030
2031 /* For triangles, the vector should be (u, v, 1-u-v). */
2032 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2033 PIPE_PRIM_TRIANGLES)
2034 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
2035 lp_build_add(bld, coord[0], coord[1]));
2036
2037 return lp_build_gather_values(&ctx->gallivm, coord, 4);
2038 }
2039
2040 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2041 unsigned semantic_name)
2042 {
2043 LLVMValueRef base, addr;
2044
2045 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2046
2047 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2048 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2049 LLVMConstInt(ctx->i32, param, 0));
2050
2051 return buffer_load(&ctx->bld_base, ctx->f32,
2052 ~0, ctx->tess_offchip_ring, base, addr, true);
2053
2054 }
2055
2056 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2057 unsigned varying_id)
2058 {
2059 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2060 unsigned semantic_name;
2061
2062 switch (varying_id) {
2063 case VARYING_SLOT_TESS_LEVEL_INNER:
2064 semantic_name = TGSI_SEMANTIC_TESSINNER;
2065 break;
2066 case VARYING_SLOT_TESS_LEVEL_OUTER:
2067 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2068 break;
2069 default:
2070 unreachable("unknown tess level");
2071 }
2072
2073 return load_tess_level(ctx, semantic_name);
2074
2075 }
2076
2077 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2078 {
2079 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2080 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2081 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2082 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2083 return get_num_tcs_out_vertices(ctx);
2084 else
2085 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2086 }
2087
2088 void si_load_system_value(struct si_shader_context *ctx,
2089 unsigned index,
2090 const struct tgsi_full_declaration *decl)
2091 {
2092 LLVMValueRef value = 0;
2093
2094 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2095
2096 switch (decl->Semantic.Name) {
2097 case TGSI_SEMANTIC_INSTANCEID:
2098 value = ctx->abi.instance_id;
2099 break;
2100
2101 case TGSI_SEMANTIC_VERTEXID:
2102 value = LLVMBuildAdd(ctx->ac.builder,
2103 ctx->abi.vertex_id,
2104 ctx->abi.base_vertex, "");
2105 break;
2106
2107 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2108 /* Unused. Clarify the meaning in indexed vs. non-indexed
2109 * draws if this is ever used again. */
2110 assert(false);
2111 break;
2112
2113 case TGSI_SEMANTIC_BASEVERTEX:
2114 value = get_base_vertex(&ctx->abi);
2115 break;
2116
2117 case TGSI_SEMANTIC_BASEINSTANCE:
2118 value = ctx->abi.start_instance;
2119 break;
2120
2121 case TGSI_SEMANTIC_DRAWID:
2122 value = ctx->abi.draw_id;
2123 break;
2124
2125 case TGSI_SEMANTIC_INVOCATIONID:
2126 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2127 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2128 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2129 value = ctx->abi.gs_invocation_id;
2130 else
2131 assert(!"INVOCATIONID not implemented");
2132 break;
2133
2134 case TGSI_SEMANTIC_POSITION:
2135 {
2136 LLVMValueRef pos[4] = {
2137 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2138 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2139 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2140 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2141 LLVMGetParam(ctx->main_fn,
2142 SI_PARAM_POS_W_FLOAT)),
2143 };
2144 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2145 break;
2146 }
2147
2148 case TGSI_SEMANTIC_FACE:
2149 value = ctx->abi.front_face;
2150 break;
2151
2152 case TGSI_SEMANTIC_SAMPLEID:
2153 value = get_sample_id(ctx);
2154 break;
2155
2156 case TGSI_SEMANTIC_SAMPLEPOS: {
2157 LLVMValueRef pos[4] = {
2158 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2159 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2160 LLVMConstReal(ctx->f32, 0),
2161 LLVMConstReal(ctx->f32, 0)
2162 };
2163 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2164 TGSI_OPCODE_FRC, pos[0]);
2165 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2166 TGSI_OPCODE_FRC, pos[1]);
2167 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2168 break;
2169 }
2170
2171 case TGSI_SEMANTIC_SAMPLEMASK:
2172 /* This can only occur with the OpenGL Core profile, which
2173 * doesn't support smoothing.
2174 */
2175 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2176 break;
2177
2178 case TGSI_SEMANTIC_TESSCOORD:
2179 value = si_load_tess_coord(&ctx->abi);
2180 break;
2181
2182 case TGSI_SEMANTIC_VERTICESIN:
2183 value = si_load_patch_vertices_in(&ctx->abi);
2184 break;
2185
2186 case TGSI_SEMANTIC_TESSINNER:
2187 case TGSI_SEMANTIC_TESSOUTER:
2188 value = load_tess_level(ctx, decl->Semantic.Name);
2189 break;
2190
2191 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2192 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2193 {
2194 LLVMValueRef buf, slot, val[4];
2195 int i, offset;
2196
2197 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2198 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2199 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2200 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2201
2202 for (i = 0; i < 4; i++)
2203 val[i] = buffer_load_const(ctx, buf,
2204 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2205 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2206 break;
2207 }
2208
2209 case TGSI_SEMANTIC_PRIMID:
2210 value = get_primitive_id(ctx, 0);
2211 break;
2212
2213 case TGSI_SEMANTIC_GRID_SIZE:
2214 value = ctx->abi.num_work_groups;
2215 break;
2216
2217 case TGSI_SEMANTIC_BLOCK_SIZE:
2218 value = get_block_size(&ctx->abi);
2219 break;
2220
2221 case TGSI_SEMANTIC_BLOCK_ID:
2222 {
2223 LLVMValueRef values[3];
2224
2225 for (int i = 0; i < 3; i++) {
2226 values[i] = ctx->i32_0;
2227 if (ctx->abi.workgroup_ids[i]) {
2228 values[i] = ctx->abi.workgroup_ids[i];
2229 }
2230 }
2231 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2232 break;
2233 }
2234
2235 case TGSI_SEMANTIC_THREAD_ID:
2236 value = ctx->abi.local_invocation_ids;
2237 break;
2238
2239 case TGSI_SEMANTIC_HELPER_INVOCATION:
2240 value = lp_build_intrinsic(ctx->ac.builder,
2241 "llvm.amdgcn.ps.live",
2242 ctx->i1, NULL, 0,
2243 LP_FUNC_ATTR_READNONE);
2244 value = LLVMBuildNot(ctx->ac.builder, value, "");
2245 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2246 break;
2247
2248 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2249 value = LLVMConstInt(ctx->i32, 64, 0);
2250 break;
2251
2252 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2253 value = ac_get_thread_id(&ctx->ac);
2254 break;
2255
2256 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2257 {
2258 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2259 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2260 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2261 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2262 break;
2263 }
2264
2265 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2266 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2267 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2268 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2269 {
2270 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2271 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2272 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2273 /* All bits set except LSB */
2274 value = LLVMConstInt(ctx->i64, -2, 0);
2275 } else {
2276 /* All bits set */
2277 value = LLVMConstInt(ctx->i64, -1, 0);
2278 }
2279 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2280 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2281 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2282 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2283 value = LLVMBuildNot(ctx->ac.builder, value, "");
2284 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2285 break;
2286 }
2287
2288 default:
2289 assert(!"unknown system value");
2290 return;
2291 }
2292
2293 ctx->system_values[index] = value;
2294 }
2295
2296 void si_declare_compute_memory(struct si_shader_context *ctx)
2297 {
2298 struct si_shader_selector *sel = ctx->shader->selector;
2299
2300 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2301 LLVMValueRef var;
2302
2303 assert(!ctx->ac.lds);
2304
2305 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2306 LLVMArrayType(ctx->i8, sel->local_size),
2307 "compute_lds",
2308 AC_LOCAL_ADDR_SPACE);
2309 LLVMSetAlignment(var, 4);
2310
2311 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2312 }
2313
2314 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2315 const struct tgsi_full_declaration *decl)
2316 {
2317 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2318 assert(decl->Range.First == decl->Range.Last);
2319
2320 si_declare_compute_memory(ctx);
2321 }
2322
2323 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2324 {
2325 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2326 ctx->param_const_and_shader_buffers);
2327
2328 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2329 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2330 }
2331
2332 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2333 {
2334 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2335 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2336
2337 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2338 index = LLVMBuildAdd(ctx->ac.builder, index,
2339 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2340
2341 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2342 }
2343
2344 static LLVMValueRef
2345 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2346 {
2347 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2348 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2349 ctx->param_const_and_shader_buffers);
2350
2351 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2352 index = LLVMBuildSub(ctx->ac.builder,
2353 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2354 index, "");
2355
2356 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2357 }
2358
2359 static LLVMValueRef fetch_constant(
2360 struct lp_build_tgsi_context *bld_base,
2361 const struct tgsi_full_src_register *reg,
2362 enum tgsi_opcode_type type,
2363 unsigned swizzle)
2364 {
2365 struct si_shader_context *ctx = si_shader_context(bld_base);
2366 struct si_shader_selector *sel = ctx->shader->selector;
2367 const struct tgsi_ind_register *ireg = &reg->Indirect;
2368 unsigned buf, idx;
2369
2370 LLVMValueRef addr, bufp;
2371
2372 if (swizzle == LP_CHAN_ALL) {
2373 unsigned chan;
2374 LLVMValueRef values[4];
2375 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2376 values[chan] = fetch_constant(bld_base, reg, type, chan);
2377
2378 return lp_build_gather_values(&ctx->gallivm, values, 4);
2379 }
2380
2381 /* Split 64-bit loads. */
2382 if (tgsi_type_is_64bit(type)) {
2383 LLVMValueRef lo, hi;
2384
2385 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2386 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2387 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2388 lo, hi);
2389 }
2390
2391 idx = reg->Register.Index * 4 + swizzle;
2392 if (reg->Register.Indirect) {
2393 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2394 } else {
2395 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2396 }
2397
2398 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2399 if (sel->info.const_buffers_declared == 1 &&
2400 sel->info.shader_buffers_declared == 0) {
2401 LLVMValueRef ptr =
2402 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2403
2404 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2405 * loads, and up to x4 load opcode merging. However, it leads to horrible
2406 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2407 *
2408 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2409 *
2410 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2411 * a descriptor and s_buffer_load_dword using it, so we can't expand
2412 * the pointer into a full descriptor like below. We have to use
2413 * s_load_dword instead. The only case when LLVM 5.0 would select
2414 * s_buffer_load_dword (that we have to prevent) is when we use use
2415 * a literal offset where we don't need bounds checking.
2416 */
2417 if (ctx->screen->info.chip_class == SI &&
2418 HAVE_LLVM < 0x0600 &&
2419 !reg->Register.Indirect) {
2420 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2421 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2422 return bitcast(bld_base, type, result);
2423 }
2424
2425 /* Do the bounds checking with a descriptor, because
2426 * doing computation and manual bounds checking of 64-bit
2427 * addresses generates horrible VALU code with very high
2428 * VGPR usage and very low SIMD occupancy.
2429 */
2430 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2431 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2432
2433 LLVMValueRef desc_elems[] = {
2434 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2435 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2436 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2437 LLVMConstInt(ctx->i32,
2438 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2439 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2440 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2441 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2442 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2443 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2444 };
2445 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2446 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2447 return bitcast(bld_base, type, result);
2448 }
2449
2450 assert(reg->Register.Dimension);
2451 buf = reg->Dimension.Index;
2452
2453 if (reg->Dimension.Indirect) {
2454 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2455 LLVMValueRef index;
2456 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2457 reg->Dimension.Index,
2458 ctx->num_const_buffers);
2459 index = LLVMBuildAdd(ctx->ac.builder, index,
2460 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2461 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2462 } else
2463 bufp = load_const_buffer_desc(ctx, buf);
2464
2465 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2466 }
2467
2468 /* Initialize arguments for the shader export intrinsic */
2469 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2470 LLVMValueRef *values,
2471 unsigned target,
2472 struct ac_export_args *args)
2473 {
2474 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2475 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2476 unsigned chan;
2477 bool is_int8, is_int10;
2478
2479 /* Default is 0xf. Adjusted below depending on the format. */
2480 args->enabled_channels = 0xf; /* writemask */
2481
2482 /* Specify whether the EXEC mask represents the valid mask */
2483 args->valid_mask = 0;
2484
2485 /* Specify whether this is the last export */
2486 args->done = 0;
2487
2488 /* Specify the target we are exporting */
2489 args->target = target;
2490
2491 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2492 const struct si_shader_key *key = &ctx->shader->key;
2493 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2494 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2495
2496 assert(cbuf >= 0 && cbuf < 8);
2497 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2498 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2499 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2500 }
2501
2502 args->compr = false;
2503 args->out[0] = f32undef;
2504 args->out[1] = f32undef;
2505 args->out[2] = f32undef;
2506 args->out[3] = f32undef;
2507
2508 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2509 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2510 unsigned bits, bool hi) = NULL;
2511
2512 switch (spi_shader_col_format) {
2513 case V_028714_SPI_SHADER_ZERO:
2514 args->enabled_channels = 0; /* writemask */
2515 args->target = V_008DFC_SQ_EXP_NULL;
2516 break;
2517
2518 case V_028714_SPI_SHADER_32_R:
2519 args->enabled_channels = 1; /* writemask */
2520 args->out[0] = values[0];
2521 break;
2522
2523 case V_028714_SPI_SHADER_32_GR:
2524 args->enabled_channels = 0x3; /* writemask */
2525 args->out[0] = values[0];
2526 args->out[1] = values[1];
2527 break;
2528
2529 case V_028714_SPI_SHADER_32_AR:
2530 args->enabled_channels = 0x9; /* writemask */
2531 args->out[0] = values[0];
2532 args->out[3] = values[3];
2533 break;
2534
2535 case V_028714_SPI_SHADER_FP16_ABGR:
2536 packf = ac_build_cvt_pkrtz_f16;
2537 break;
2538
2539 case V_028714_SPI_SHADER_UNORM16_ABGR:
2540 packf = ac_build_cvt_pknorm_u16;
2541 break;
2542
2543 case V_028714_SPI_SHADER_SNORM16_ABGR:
2544 packf = ac_build_cvt_pknorm_i16;
2545 break;
2546
2547 case V_028714_SPI_SHADER_UINT16_ABGR:
2548 packi = ac_build_cvt_pk_u16;
2549 break;
2550
2551 case V_028714_SPI_SHADER_SINT16_ABGR:
2552 packi = ac_build_cvt_pk_i16;
2553 break;
2554
2555 case V_028714_SPI_SHADER_32_ABGR:
2556 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2557 break;
2558 }
2559
2560 /* Pack f16 or norm_i16/u16. */
2561 if (packf) {
2562 for (chan = 0; chan < 2; chan++) {
2563 LLVMValueRef pack_args[2] = {
2564 values[2 * chan],
2565 values[2 * chan + 1]
2566 };
2567 LLVMValueRef packed;
2568
2569 packed = packf(&ctx->ac, pack_args);
2570 args->out[chan] = ac_to_float(&ctx->ac, packed);
2571 }
2572 args->compr = 1; /* COMPR flag */
2573 }
2574 /* Pack i16/u16. */
2575 if (packi) {
2576 for (chan = 0; chan < 2; chan++) {
2577 LLVMValueRef pack_args[2] = {
2578 ac_to_integer(&ctx->ac, values[2 * chan]),
2579 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2580 };
2581 LLVMValueRef packed;
2582
2583 packed = packi(&ctx->ac, pack_args,
2584 is_int8 ? 8 : is_int10 ? 10 : 16,
2585 chan == 1);
2586 args->out[chan] = ac_to_float(&ctx->ac, packed);
2587 }
2588 args->compr = 1; /* COMPR flag */
2589 }
2590 }
2591
2592 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2593 LLVMValueRef alpha)
2594 {
2595 struct si_shader_context *ctx = si_shader_context(bld_base);
2596
2597 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2598 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2599 [PIPE_FUNC_LESS] = LLVMRealOLT,
2600 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2601 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2602 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2603 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2604 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2605 };
2606 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2607 assert(cond);
2608
2609 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2610 SI_PARAM_ALPHA_REF);
2611 LLVMValueRef alpha_pass =
2612 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2613 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2614 } else {
2615 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2616 }
2617 }
2618
2619 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2620 LLVMValueRef alpha,
2621 unsigned samplemask_param)
2622 {
2623 struct si_shader_context *ctx = si_shader_context(bld_base);
2624 LLVMValueRef coverage;
2625
2626 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2627 coverage = LLVMGetParam(ctx->main_fn,
2628 samplemask_param);
2629 coverage = ac_to_integer(&ctx->ac, coverage);
2630
2631 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2632 ctx->i32,
2633 &coverage, 1, LP_FUNC_ATTR_READNONE);
2634
2635 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2636 ctx->f32, "");
2637
2638 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2639 LLVMConstReal(ctx->f32,
2640 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2641
2642 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2643 }
2644
2645 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2646 struct ac_export_args *pos, LLVMValueRef *out_elts)
2647 {
2648 unsigned reg_index;
2649 unsigned chan;
2650 unsigned const_chan;
2651 LLVMValueRef base_elt;
2652 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2653 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2654 SI_VS_CONST_CLIP_PLANES, 0);
2655 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2656
2657 for (reg_index = 0; reg_index < 2; reg_index ++) {
2658 struct ac_export_args *args = &pos[2 + reg_index];
2659
2660 args->out[0] =
2661 args->out[1] =
2662 args->out[2] =
2663 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2664
2665 /* Compute dot products of position and user clip plane vectors */
2666 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2667 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2668 LLVMValueRef addr =
2669 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2670 const_chan) * 4, 0);
2671 base_elt = buffer_load_const(ctx, const_resource,
2672 addr);
2673 args->out[chan] =
2674 lp_build_add(&ctx->bld_base.base, args->out[chan],
2675 lp_build_mul(&ctx->bld_base.base, base_elt,
2676 out_elts[const_chan]));
2677 }
2678 }
2679
2680 args->enabled_channels = 0xf;
2681 args->valid_mask = 0;
2682 args->done = 0;
2683 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2684 args->compr = 0;
2685 }
2686 }
2687
2688 static void si_dump_streamout(struct pipe_stream_output_info *so)
2689 {
2690 unsigned i;
2691
2692 if (so->num_outputs)
2693 fprintf(stderr, "STREAMOUT\n");
2694
2695 for (i = 0; i < so->num_outputs; i++) {
2696 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2697 so->output[i].start_component;
2698 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2699 i, so->output[i].output_buffer,
2700 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2701 so->output[i].register_index,
2702 mask & 1 ? "x" : "",
2703 mask & 2 ? "y" : "",
2704 mask & 4 ? "z" : "",
2705 mask & 8 ? "w" : "");
2706 }
2707 }
2708
2709 static void emit_streamout_output(struct si_shader_context *ctx,
2710 LLVMValueRef const *so_buffers,
2711 LLVMValueRef const *so_write_offsets,
2712 struct pipe_stream_output *stream_out,
2713 struct si_shader_output_values *shader_out)
2714 {
2715 unsigned buf_idx = stream_out->output_buffer;
2716 unsigned start = stream_out->start_component;
2717 unsigned num_comps = stream_out->num_components;
2718 LLVMValueRef out[4];
2719
2720 assert(num_comps && num_comps <= 4);
2721 if (!num_comps || num_comps > 4)
2722 return;
2723
2724 /* Load the output as int. */
2725 for (int j = 0; j < num_comps; j++) {
2726 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2727
2728 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2729 }
2730
2731 /* Pack the output. */
2732 LLVMValueRef vdata = NULL;
2733
2734 switch (num_comps) {
2735 case 1: /* as i32 */
2736 vdata = out[0];
2737 break;
2738 case 2: /* as v2i32 */
2739 case 3: /* as v4i32 (aligned to 4) */
2740 case 4: /* as v4i32 */
2741 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2742 for (int j = 0; j < num_comps; j++) {
2743 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2744 LLVMConstInt(ctx->i32, j, 0), "");
2745 }
2746 break;
2747 }
2748
2749 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2750 vdata, num_comps,
2751 so_write_offsets[buf_idx],
2752 ctx->i32_0,
2753 stream_out->dst_offset * 4, 1, 1, true, false);
2754 }
2755
2756 /**
2757 * Write streamout data to buffers for vertex stream @p stream (different
2758 * vertex streams can occur for GS copy shaders).
2759 */
2760 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2761 struct si_shader_output_values *outputs,
2762 unsigned noutput, unsigned stream)
2763 {
2764 struct si_shader_selector *sel = ctx->shader->selector;
2765 struct pipe_stream_output_info *so = &sel->so;
2766 LLVMBuilderRef builder = ctx->ac.builder;
2767 int i;
2768 struct lp_build_if_state if_ctx;
2769
2770 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2771 LLVMValueRef so_vtx_count =
2772 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2773
2774 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2775
2776 /* can_emit = tid < so_vtx_count; */
2777 LLVMValueRef can_emit =
2778 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2779
2780 /* Emit the streamout code conditionally. This actually avoids
2781 * out-of-bounds buffer access. The hw tells us via the SGPR
2782 * (so_vtx_count) which threads are allowed to emit streamout data. */
2783 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2784 {
2785 /* The buffer offset is computed as follows:
2786 * ByteOffset = streamout_offset[buffer_id]*4 +
2787 * (streamout_write_index + thread_id)*stride[buffer_id] +
2788 * attrib_offset
2789 */
2790
2791 LLVMValueRef so_write_index =
2792 LLVMGetParam(ctx->main_fn,
2793 ctx->param_streamout_write_index);
2794
2795 /* Compute (streamout_write_index + thread_id). */
2796 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2797
2798 /* Load the descriptor and compute the write offset for each
2799 * enabled buffer. */
2800 LLVMValueRef so_write_offset[4] = {};
2801 LLVMValueRef so_buffers[4];
2802 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2803 ctx->param_rw_buffers);
2804
2805 for (i = 0; i < 4; i++) {
2806 if (!so->stride[i])
2807 continue;
2808
2809 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2810 SI_VS_STREAMOUT_BUF0 + i, 0);
2811
2812 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2813
2814 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2815 ctx->param_streamout_offset[i]);
2816 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2817
2818 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2819 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2820 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2821 }
2822
2823 /* Write streamout data. */
2824 for (i = 0; i < so->num_outputs; i++) {
2825 unsigned reg = so->output[i].register_index;
2826
2827 if (reg >= noutput)
2828 continue;
2829
2830 if (stream != so->output[i].stream)
2831 continue;
2832
2833 emit_streamout_output(ctx, so_buffers, so_write_offset,
2834 &so->output[i], &outputs[reg]);
2835 }
2836 }
2837 lp_build_endif(&if_ctx);
2838 }
2839
2840 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2841 LLVMValueRef *values)
2842 {
2843 struct ac_export_args args;
2844
2845 si_llvm_init_export_args(ctx, values,
2846 V_008DFC_SQ_EXP_PARAM + index, &args);
2847 ac_build_export(&ctx->ac, &args);
2848 }
2849
2850 static void si_build_param_exports(struct si_shader_context *ctx,
2851 struct si_shader_output_values *outputs,
2852 unsigned noutput)
2853 {
2854 struct si_shader *shader = ctx->shader;
2855 unsigned param_count = 0;
2856
2857 for (unsigned i = 0; i < noutput; i++) {
2858 unsigned semantic_name = outputs[i].semantic_name;
2859 unsigned semantic_index = outputs[i].semantic_index;
2860
2861 if (outputs[i].vertex_stream[0] != 0 &&
2862 outputs[i].vertex_stream[1] != 0 &&
2863 outputs[i].vertex_stream[2] != 0 &&
2864 outputs[i].vertex_stream[3] != 0)
2865 continue;
2866
2867 switch (semantic_name) {
2868 case TGSI_SEMANTIC_LAYER:
2869 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2870 case TGSI_SEMANTIC_CLIPDIST:
2871 case TGSI_SEMANTIC_COLOR:
2872 case TGSI_SEMANTIC_BCOLOR:
2873 case TGSI_SEMANTIC_PRIMID:
2874 case TGSI_SEMANTIC_FOG:
2875 case TGSI_SEMANTIC_TEXCOORD:
2876 case TGSI_SEMANTIC_GENERIC:
2877 break;
2878 default:
2879 continue;
2880 }
2881
2882 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2883 semantic_index < SI_MAX_IO_GENERIC) &&
2884 shader->key.opt.kill_outputs &
2885 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2886 continue;
2887
2888 si_export_param(ctx, param_count, outputs[i].values);
2889
2890 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2891 shader->info.vs_output_param_offset[i] = param_count++;
2892 }
2893
2894 shader->info.nr_param_exports = param_count;
2895 }
2896
2897 /* Generate export instructions for hardware VS shader stage */
2898 static void si_llvm_export_vs(struct si_shader_context *ctx,
2899 struct si_shader_output_values *outputs,
2900 unsigned noutput)
2901 {
2902 struct si_shader *shader = ctx->shader;
2903 struct ac_export_args pos_args[4] = {};
2904 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2905 unsigned pos_idx;
2906 int i;
2907
2908 /* Build position exports. */
2909 for (i = 0; i < noutput; i++) {
2910 switch (outputs[i].semantic_name) {
2911 case TGSI_SEMANTIC_POSITION:
2912 si_llvm_init_export_args(ctx, outputs[i].values,
2913 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2914 break;
2915 case TGSI_SEMANTIC_PSIZE:
2916 psize_value = outputs[i].values[0];
2917 break;
2918 case TGSI_SEMANTIC_LAYER:
2919 layer_value = outputs[i].values[0];
2920 break;
2921 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2922 viewport_index_value = outputs[i].values[0];
2923 break;
2924 case TGSI_SEMANTIC_EDGEFLAG:
2925 edgeflag_value = outputs[i].values[0];
2926 break;
2927 case TGSI_SEMANTIC_CLIPDIST:
2928 if (!shader->key.opt.clip_disable) {
2929 unsigned index = 2 + outputs[i].semantic_index;
2930 si_llvm_init_export_args(ctx, outputs[i].values,
2931 V_008DFC_SQ_EXP_POS + index,
2932 &pos_args[index]);
2933 }
2934 break;
2935 case TGSI_SEMANTIC_CLIPVERTEX:
2936 if (!shader->key.opt.clip_disable) {
2937 si_llvm_emit_clipvertex(ctx, pos_args,
2938 outputs[i].values);
2939 }
2940 break;
2941 }
2942 }
2943
2944 /* We need to add the position output manually if it's missing. */
2945 if (!pos_args[0].out[0]) {
2946 pos_args[0].enabled_channels = 0xf; /* writemask */
2947 pos_args[0].valid_mask = 0; /* EXEC mask */
2948 pos_args[0].done = 0; /* last export? */
2949 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2950 pos_args[0].compr = 0; /* COMPR flag */
2951 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2952 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2953 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2954 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2955 }
2956
2957 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2958 if (shader->selector->info.writes_psize ||
2959 shader->selector->info.writes_edgeflag ||
2960 shader->selector->info.writes_viewport_index ||
2961 shader->selector->info.writes_layer) {
2962 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2963 (shader->selector->info.writes_edgeflag << 1) |
2964 (shader->selector->info.writes_layer << 2);
2965
2966 pos_args[1].valid_mask = 0; /* EXEC mask */
2967 pos_args[1].done = 0; /* last export? */
2968 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2969 pos_args[1].compr = 0; /* COMPR flag */
2970 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2971 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2972 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2973 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2974
2975 if (shader->selector->info.writes_psize)
2976 pos_args[1].out[0] = psize_value;
2977
2978 if (shader->selector->info.writes_edgeflag) {
2979 /* The output is a float, but the hw expects an integer
2980 * with the first bit containing the edge flag. */
2981 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2982 edgeflag_value,
2983 ctx->i32, "");
2984 edgeflag_value = ac_build_umin(&ctx->ac,
2985 edgeflag_value,
2986 ctx->i32_1);
2987
2988 /* The LLVM intrinsic expects a float. */
2989 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2990 }
2991
2992 if (ctx->screen->info.chip_class >= GFX9) {
2993 /* GFX9 has the layer in out.z[10:0] and the viewport
2994 * index in out.z[19:16].
2995 */
2996 if (shader->selector->info.writes_layer)
2997 pos_args[1].out[2] = layer_value;
2998
2999 if (shader->selector->info.writes_viewport_index) {
3000 LLVMValueRef v = viewport_index_value;
3001
3002 v = ac_to_integer(&ctx->ac, v);
3003 v = LLVMBuildShl(ctx->ac.builder, v,
3004 LLVMConstInt(ctx->i32, 16, 0), "");
3005 v = LLVMBuildOr(ctx->ac.builder, v,
3006 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3007 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3008 pos_args[1].enabled_channels |= 1 << 2;
3009 }
3010 } else {
3011 if (shader->selector->info.writes_layer)
3012 pos_args[1].out[2] = layer_value;
3013
3014 if (shader->selector->info.writes_viewport_index) {
3015 pos_args[1].out[3] = viewport_index_value;
3016 pos_args[1].enabled_channels |= 1 << 3;
3017 }
3018 }
3019 }
3020
3021 for (i = 0; i < 4; i++)
3022 if (pos_args[i].out[0])
3023 shader->info.nr_pos_exports++;
3024
3025 pos_idx = 0;
3026 for (i = 0; i < 4; i++) {
3027 if (!pos_args[i].out[0])
3028 continue;
3029
3030 /* Specify the target we are exporting */
3031 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3032
3033 if (pos_idx == shader->info.nr_pos_exports)
3034 /* Specify that this is the last export */
3035 pos_args[i].done = 1;
3036
3037 ac_build_export(&ctx->ac, &pos_args[i]);
3038 }
3039
3040 /* Build parameter exports. */
3041 si_build_param_exports(ctx, outputs, noutput);
3042 }
3043
3044 /**
3045 * Forward all outputs from the vertex shader to the TES. This is only used
3046 * for the fixed function TCS.
3047 */
3048 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3049 {
3050 struct si_shader_context *ctx = si_shader_context(bld_base);
3051 LLVMValueRef invocation_id, buffer, buffer_offset;
3052 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3053 uint64_t inputs;
3054
3055 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3056 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3057 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3058
3059 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3060 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3061 lds_vertex_stride, "");
3062 lds_base = get_tcs_in_current_patch_offset(ctx);
3063 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3064
3065 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3066 while (inputs) {
3067 unsigned i = u_bit_scan64(&inputs);
3068
3069 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3070 LLVMConstInt(ctx->i32, 4 * i, 0),
3071 "");
3072
3073 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3074 get_rel_patch_id(ctx),
3075 invocation_id,
3076 LLVMConstInt(ctx->i32, i, 0));
3077
3078 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3079 lds_ptr);
3080
3081 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3082 buffer_offset, 0, 1, 0, true, false);
3083 }
3084 }
3085
3086 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3087 LLVMValueRef rel_patch_id,
3088 LLVMValueRef invocation_id,
3089 LLVMValueRef tcs_out_current_patch_data_offset,
3090 LLVMValueRef invoc0_tf_outer[4],
3091 LLVMValueRef invoc0_tf_inner[2])
3092 {
3093 struct si_shader_context *ctx = si_shader_context(bld_base);
3094 struct si_shader *shader = ctx->shader;
3095 unsigned tess_inner_index, tess_outer_index;
3096 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3097 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3098 unsigned stride, outer_comps, inner_comps, i, offset;
3099 struct lp_build_if_state if_ctx, inner_if_ctx;
3100
3101 /* Add a barrier before loading tess factors from LDS. */
3102 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3103 si_llvm_emit_barrier(NULL, bld_base, NULL);
3104
3105 /* Do this only for invocation 0, because the tess levels are per-patch,
3106 * not per-vertex.
3107 *
3108 * This can't jump, because invocation 0 executes this. It should
3109 * at least mask out the loads and stores for other invocations.
3110 */
3111 lp_build_if(&if_ctx, &ctx->gallivm,
3112 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3113 invocation_id, ctx->i32_0, ""));
3114
3115 /* Determine the layout of one tess factor element in the buffer. */
3116 switch (shader->key.part.tcs.epilog.prim_mode) {
3117 case PIPE_PRIM_LINES:
3118 stride = 2; /* 2 dwords, 1 vec2 store */
3119 outer_comps = 2;
3120 inner_comps = 0;
3121 break;
3122 case PIPE_PRIM_TRIANGLES:
3123 stride = 4; /* 4 dwords, 1 vec4 store */
3124 outer_comps = 3;
3125 inner_comps = 1;
3126 break;
3127 case PIPE_PRIM_QUADS:
3128 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3129 outer_comps = 4;
3130 inner_comps = 2;
3131 break;
3132 default:
3133 assert(0);
3134 return;
3135 }
3136
3137 for (i = 0; i < 4; i++) {
3138 inner[i] = LLVMGetUndef(ctx->i32);
3139 outer[i] = LLVMGetUndef(ctx->i32);
3140 }
3141
3142 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3143 /* Tess factors are in VGPRs. */
3144 for (i = 0; i < outer_comps; i++)
3145 outer[i] = out[i] = invoc0_tf_outer[i];
3146 for (i = 0; i < inner_comps; i++)
3147 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3148 } else {
3149 /* Load tess_inner and tess_outer from LDS.
3150 * Any invocation can write them, so we can't get them from a temporary.
3151 */
3152 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3153 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3154
3155 lds_base = tcs_out_current_patch_data_offset;
3156 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3157 LLVMConstInt(ctx->i32,
3158 tess_inner_index * 4, 0), "");
3159 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3160 LLVMConstInt(ctx->i32,
3161 tess_outer_index * 4, 0), "");
3162
3163 for (i = 0; i < outer_comps; i++) {
3164 outer[i] = out[i] =
3165 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3166 }
3167 for (i = 0; i < inner_comps; i++) {
3168 inner[i] = out[outer_comps+i] =
3169 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3170 }
3171 }
3172
3173 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3174 /* For isolines, the hardware expects tess factors in the
3175 * reverse order from what GLSL / TGSI specify.
3176 */
3177 LLVMValueRef tmp = out[0];
3178 out[0] = out[1];
3179 out[1] = tmp;
3180 }
3181
3182 /* Convert the outputs to vectors for stores. */
3183 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3184 vec1 = NULL;
3185
3186 if (stride > 4)
3187 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3188
3189 /* Get the buffer. */
3190 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3191
3192 /* Get the offset. */
3193 tf_base = LLVMGetParam(ctx->main_fn,
3194 ctx->param_tcs_factor_offset);
3195 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3196 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3197
3198 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3199 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3200 rel_patch_id, ctx->i32_0, ""));
3201
3202 /* Store the dynamic HS control word. */
3203 offset = 0;
3204 if (ctx->screen->info.chip_class <= VI) {
3205 ac_build_buffer_store_dword(&ctx->ac, buffer,
3206 LLVMConstInt(ctx->i32, 0x80000000, 0),
3207 1, ctx->i32_0, tf_base,
3208 offset, 1, 0, true, false);
3209 offset += 4;
3210 }
3211
3212 lp_build_endif(&inner_if_ctx);
3213
3214 /* Store the tessellation factors. */
3215 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3216 MIN2(stride, 4), byteoffset, tf_base,
3217 offset, 1, 0, true, false);
3218 offset += 16;
3219 if (vec1)
3220 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3221 stride - 4, byteoffset, tf_base,
3222 offset, 1, 0, true, false);
3223
3224 /* Store the tess factors into the offchip buffer if TES reads them. */
3225 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3226 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3227 LLVMValueRef tf_inner_offset;
3228 unsigned param_outer, param_inner;
3229
3230 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3231 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3232
3233 param_outer = si_shader_io_get_unique_index_patch(
3234 TGSI_SEMANTIC_TESSOUTER, 0);
3235 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3236 LLVMConstInt(ctx->i32, param_outer, 0));
3237
3238 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3239 util_next_power_of_two(outer_comps));
3240
3241 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3242 outer_comps, tf_outer_offset,
3243 base, 0, 1, 0, true, false);
3244 if (inner_comps) {
3245 param_inner = si_shader_io_get_unique_index_patch(
3246 TGSI_SEMANTIC_TESSINNER, 0);
3247 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3248 LLVMConstInt(ctx->i32, param_inner, 0));
3249
3250 inner_vec = inner_comps == 1 ? inner[0] :
3251 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3252 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3253 inner_comps, tf_inner_offset,
3254 base, 0, 1, 0, true, false);
3255 }
3256 }
3257
3258 lp_build_endif(&if_ctx);
3259 }
3260
3261 static LLVMValueRef
3262 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3263 unsigned param, unsigned return_index)
3264 {
3265 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3266 LLVMGetParam(ctx->main_fn, param),
3267 return_index, "");
3268 }
3269
3270 static LLVMValueRef
3271 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3272 unsigned param, unsigned return_index)
3273 {
3274 LLVMBuilderRef builder = ctx->ac.builder;
3275 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3276
3277 return LLVMBuildInsertValue(builder, ret,
3278 ac_to_float(&ctx->ac, p),
3279 return_index, "");
3280 }
3281
3282 static LLVMValueRef
3283 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3284 unsigned param, unsigned return_index)
3285 {
3286 LLVMBuilderRef builder = ctx->ac.builder;
3287 LLVMValueRef ptr, lo, hi;
3288
3289 if (HAVE_32BIT_POINTERS) {
3290 ptr = LLVMGetParam(ctx->main_fn, param);
3291 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3292 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3293 }
3294
3295 ptr = LLVMGetParam(ctx->main_fn, param);
3296 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3297 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3298 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3299 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3300 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3301 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3302 }
3303
3304 /* This only writes the tessellation factor levels. */
3305 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3306 unsigned max_outputs,
3307 LLVMValueRef *addrs)
3308 {
3309 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3310 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3311 LLVMBuilderRef builder = ctx->ac.builder;
3312 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3313
3314 si_copy_tcs_inputs(bld_base);
3315
3316 rel_patch_id = get_rel_patch_id(ctx);
3317 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3318 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3319
3320 if (ctx->screen->info.chip_class >= GFX9) {
3321 LLVMBasicBlockRef blocks[2] = {
3322 LLVMGetInsertBlock(builder),
3323 ctx->merged_wrap_if_state.entry_block
3324 };
3325 LLVMValueRef values[2];
3326
3327 lp_build_endif(&ctx->merged_wrap_if_state);
3328
3329 values[0] = rel_patch_id;
3330 values[1] = LLVMGetUndef(ctx->i32);
3331 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3332
3333 values[0] = tf_lds_offset;
3334 values[1] = LLVMGetUndef(ctx->i32);
3335 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3336
3337 values[0] = invocation_id;
3338 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3339 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3340 }
3341
3342 /* Return epilog parameters from this function. */
3343 LLVMValueRef ret = ctx->return_value;
3344 unsigned vgpr;
3345
3346 if (ctx->screen->info.chip_class >= GFX9) {
3347 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3348 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3349 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3350 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3351 /* Tess offchip and tess factor offsets are at the beginning. */
3352 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3353 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3354 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3355 } else {
3356 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3357 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3358 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3359 GFX6_SGPR_TCS_OUT_LAYOUT);
3360 /* Tess offchip and tess factor offsets are after user SGPRs. */
3361 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3362 GFX6_TCS_NUM_USER_SGPR);
3363 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3364 GFX6_TCS_NUM_USER_SGPR + 1);
3365 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3366 }
3367
3368 /* VGPRs */
3369 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3370 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3371 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3372
3373 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3374 * the invocation_id output does not alias the tcs_rel_ids input,
3375 * which saves a V_MOV on gfx9.
3376 */
3377 vgpr += 2;
3378
3379 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3380 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3381
3382 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3383 vgpr++; /* skip the tess factor LDS offset */
3384 for (unsigned i = 0; i < 6; i++) {
3385 LLVMValueRef value =
3386 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3387 value = ac_to_float(&ctx->ac, value);
3388 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3389 }
3390 } else {
3391 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3392 }
3393 ctx->return_value = ret;
3394 }
3395
3396 /* Pass TCS inputs from LS to TCS on GFX9. */
3397 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3398 {
3399 LLVMValueRef ret = ctx->return_value;
3400
3401 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3402 if (HAVE_32BIT_POINTERS)
3403 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3404 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3405 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3406 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3407 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3408
3409 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3410 8 + SI_SGPR_RW_BUFFERS);
3411 ret = si_insert_input_ptr(ctx, ret,
3412 ctx->param_bindless_samplers_and_images,
3413 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3414
3415 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3416 8 + SI_SGPR_VS_STATE_BITS);
3417
3418 #if !HAVE_32BIT_POINTERS
3419 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3420 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3421 #endif
3422
3423 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3424 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3425 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3426 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3428 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3429
3430 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3431 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3432 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3433 vgpr++, "");
3434 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3435 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3436 vgpr++, "");
3437 ctx->return_value = ret;
3438 }
3439
3440 /* Pass GS inputs from ES to GS on GFX9. */
3441 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3442 {
3443 LLVMValueRef ret = ctx->return_value;
3444
3445 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3446 if (HAVE_32BIT_POINTERS)
3447 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3448 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3449 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3450 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3451
3452 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3453 8 + SI_SGPR_RW_BUFFERS);
3454 ret = si_insert_input_ptr(ctx, ret,
3455 ctx->param_bindless_samplers_and_images,
3456 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3457
3458 #if !HAVE_32BIT_POINTERS
3459 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 1,
3460 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3461 #endif
3462
3463 unsigned vgpr;
3464 if (ctx->type == PIPE_SHADER_VERTEX)
3465 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3466 else
3467 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3468
3469 for (unsigned i = 0; i < 5; i++) {
3470 unsigned param = ctx->param_gs_vtx01_offset + i;
3471 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3472 }
3473 ctx->return_value = ret;
3474 }
3475
3476 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3477 unsigned max_outputs,
3478 LLVMValueRef *addrs)
3479 {
3480 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3481 struct si_shader *shader = ctx->shader;
3482 struct tgsi_shader_info *info = &shader->selector->info;
3483 unsigned i, chan;
3484 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3485 ctx->param_rel_auto_id);
3486 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3487 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3488 vertex_dw_stride, "");
3489
3490 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3491 * its inputs from it. */
3492 for (i = 0; i < info->num_outputs; i++) {
3493 unsigned name = info->output_semantic_name[i];
3494 unsigned index = info->output_semantic_index[i];
3495
3496 /* The ARB_shader_viewport_layer_array spec contains the
3497 * following issue:
3498 *
3499 * 2) What happens if gl_ViewportIndex or gl_Layer is
3500 * written in the vertex shader and a geometry shader is
3501 * present?
3502 *
3503 * RESOLVED: The value written by the last vertex processing
3504 * stage is used. If the last vertex processing stage
3505 * (vertex, tessellation evaluation or geometry) does not
3506 * statically assign to gl_ViewportIndex or gl_Layer, index
3507 * or layer zero is assumed.
3508 *
3509 * So writes to those outputs in VS-as-LS are simply ignored.
3510 */
3511 if (name == TGSI_SEMANTIC_LAYER ||
3512 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3513 continue;
3514
3515 int param = si_shader_io_get_unique_index(name, index);
3516 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3517 LLVMConstInt(ctx->i32, param * 4, 0), "");
3518
3519 for (chan = 0; chan < 4; chan++) {
3520 if (!(info->output_usagemask[i] & (1 << chan)))
3521 continue;
3522
3523 lds_store(ctx, chan, dw_addr,
3524 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3525 }
3526 }
3527
3528 if (ctx->screen->info.chip_class >= GFX9)
3529 si_set_ls_return_value_for_tcs(ctx);
3530 }
3531
3532 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3533 unsigned max_outputs,
3534 LLVMValueRef *addrs)
3535 {
3536 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3537 struct si_shader *es = ctx->shader;
3538 struct tgsi_shader_info *info = &es->selector->info;
3539 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3540 ctx->param_es2gs_offset);
3541 LLVMValueRef lds_base = NULL;
3542 unsigned chan;
3543 int i;
3544
3545 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3546 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3547 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3548 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3549 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3550 LLVMBuildMul(ctx->ac.builder, wave_idx,
3551 LLVMConstInt(ctx->i32, 64, false), ""), "");
3552 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3553 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3554 }
3555
3556 for (i = 0; i < info->num_outputs; i++) {
3557 int param;
3558
3559 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3560 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3561 continue;
3562
3563 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3564 info->output_semantic_index[i]);
3565
3566 for (chan = 0; chan < 4; chan++) {
3567 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3568 out_val = ac_to_integer(&ctx->ac, out_val);
3569
3570 /* GFX9 has the ESGS ring in LDS. */
3571 if (ctx->screen->info.chip_class >= GFX9) {
3572 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3573 continue;
3574 }
3575
3576 ac_build_buffer_store_dword(&ctx->ac,
3577 ctx->esgs_ring,
3578 out_val, 1, NULL, soffset,
3579 (4 * param + chan) * 4,
3580 1, 1, true, true);
3581 }
3582 }
3583
3584 if (ctx->screen->info.chip_class >= GFX9)
3585 si_set_es_return_value_for_gs(ctx);
3586 }
3587
3588 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3589 {
3590 if (ctx->screen->info.chip_class >= GFX9)
3591 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3592 else
3593 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3594 }
3595
3596 static void emit_gs_epilogue(struct si_shader_context *ctx)
3597 {
3598 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3599 si_get_gs_wave_id(ctx));
3600
3601 if (ctx->screen->info.chip_class >= GFX9)
3602 lp_build_endif(&ctx->merged_wrap_if_state);
3603 }
3604
3605 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3606 unsigned max_outputs,
3607 LLVMValueRef *addrs)
3608 {
3609 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3610 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3611
3612 assert(info->num_outputs <= max_outputs);
3613
3614 emit_gs_epilogue(ctx);
3615 }
3616
3617 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3618 {
3619 struct si_shader_context *ctx = si_shader_context(bld_base);
3620 emit_gs_epilogue(ctx);
3621 }
3622
3623 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3624 unsigned max_outputs,
3625 LLVMValueRef *addrs)
3626 {
3627 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3628 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3629 struct si_shader_output_values *outputs = NULL;
3630 int i,j;
3631
3632 assert(!ctx->shader->is_gs_copy_shader);
3633 assert(info->num_outputs <= max_outputs);
3634
3635 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3636
3637 /* Vertex color clamping.
3638 *
3639 * This uses a state constant loaded in a user data SGPR and
3640 * an IF statement is added that clamps all colors if the constant
3641 * is true.
3642 */
3643 if (ctx->type == PIPE_SHADER_VERTEX) {
3644 struct lp_build_if_state if_ctx;
3645 LLVMValueRef cond = NULL;
3646 LLVMValueRef addr, val;
3647
3648 for (i = 0; i < info->num_outputs; i++) {
3649 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3650 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3651 continue;
3652
3653 /* We've found a color. */
3654 if (!cond) {
3655 /* The state is in the first bit of the user SGPR. */
3656 cond = LLVMGetParam(ctx->main_fn,
3657 ctx->param_vs_state_bits);
3658 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3659 ctx->i1, "");
3660 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3661 }
3662
3663 for (j = 0; j < 4; j++) {
3664 addr = addrs[4 * i + j];
3665 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3666 val = ac_build_clamp(&ctx->ac, val);
3667 LLVMBuildStore(ctx->ac.builder, val, addr);
3668 }
3669 }
3670
3671 if (cond)
3672 lp_build_endif(&if_ctx);
3673 }
3674
3675 for (i = 0; i < info->num_outputs; i++) {
3676 outputs[i].semantic_name = info->output_semantic_name[i];
3677 outputs[i].semantic_index = info->output_semantic_index[i];
3678
3679 for (j = 0; j < 4; j++) {
3680 outputs[i].values[j] =
3681 LLVMBuildLoad(ctx->ac.builder,
3682 addrs[4 * i + j],
3683 "");
3684 outputs[i].vertex_stream[j] =
3685 (info->output_streams[i] >> (2 * j)) & 3;
3686 }
3687 }
3688
3689 if (ctx->shader->selector->so.num_outputs)
3690 si_llvm_emit_streamout(ctx, outputs, i, 0);
3691
3692 /* Export PrimitiveID. */
3693 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3694 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3695 outputs[i].semantic_index = 0;
3696 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3697 for (j = 1; j < 4; j++)
3698 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3699
3700 memset(outputs[i].vertex_stream, 0,
3701 sizeof(outputs[i].vertex_stream));
3702 i++;
3703 }
3704
3705 si_llvm_export_vs(ctx, outputs, i);
3706 FREE(outputs);
3707 }
3708
3709 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3710 {
3711 struct si_shader_context *ctx = si_shader_context(bld_base);
3712
3713 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3714 &ctx->outputs[0][0]);
3715 }
3716
3717 struct si_ps_exports {
3718 unsigned num;
3719 struct ac_export_args args[10];
3720 };
3721
3722 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3723 LLVMValueRef depth, LLVMValueRef stencil,
3724 LLVMValueRef samplemask, struct si_ps_exports *exp)
3725 {
3726 struct si_shader_context *ctx = si_shader_context(bld_base);
3727 struct ac_export_args args;
3728
3729 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3730
3731 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3732 }
3733
3734 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3735 LLVMValueRef *color, unsigned index,
3736 unsigned samplemask_param,
3737 bool is_last, struct si_ps_exports *exp)
3738 {
3739 struct si_shader_context *ctx = si_shader_context(bld_base);
3740 int i;
3741
3742 /* Clamp color */
3743 if (ctx->shader->key.part.ps.epilog.clamp_color)
3744 for (i = 0; i < 4; i++)
3745 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3746
3747 /* Alpha to one */
3748 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3749 color[3] = ctx->ac.f32_1;
3750
3751 /* Alpha test */
3752 if (index == 0 &&
3753 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3754 si_alpha_test(bld_base, color[3]);
3755
3756 /* Line & polygon smoothing */
3757 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3758 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3759 samplemask_param);
3760
3761 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3762 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3763 struct ac_export_args args[8];
3764 int c, last = -1;
3765
3766 /* Get the export arguments, also find out what the last one is. */
3767 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3768 si_llvm_init_export_args(ctx, color,
3769 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3770 if (args[c].enabled_channels)
3771 last = c;
3772 }
3773
3774 /* Emit all exports. */
3775 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3776 if (is_last && last == c) {
3777 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3778 args[c].done = 1; /* DONE bit */
3779 } else if (!args[c].enabled_channels)
3780 continue; /* unnecessary NULL export */
3781
3782 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3783 }
3784 } else {
3785 struct ac_export_args args;
3786
3787 /* Export */
3788 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3789 &args);
3790 if (is_last) {
3791 args.valid_mask = 1; /* whether the EXEC mask is valid */
3792 args.done = 1; /* DONE bit */
3793 } else if (!args.enabled_channels)
3794 return; /* unnecessary NULL export */
3795
3796 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3797 }
3798 }
3799
3800 static void si_emit_ps_exports(struct si_shader_context *ctx,
3801 struct si_ps_exports *exp)
3802 {
3803 for (unsigned i = 0; i < exp->num; i++)
3804 ac_build_export(&ctx->ac, &exp->args[i]);
3805 }
3806
3807 /**
3808 * Return PS outputs in this order:
3809 *
3810 * v[0:3] = color0.xyzw
3811 * v[4:7] = color1.xyzw
3812 * ...
3813 * vN+0 = Depth
3814 * vN+1 = Stencil
3815 * vN+2 = SampleMask
3816 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3817 *
3818 * The alpha-ref SGPR is returned via its original location.
3819 */
3820 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3821 unsigned max_outputs,
3822 LLVMValueRef *addrs)
3823 {
3824 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3825 struct si_shader *shader = ctx->shader;
3826 struct tgsi_shader_info *info = &shader->selector->info;
3827 LLVMBuilderRef builder = ctx->ac.builder;
3828 unsigned i, j, first_vgpr, vgpr;
3829
3830 LLVMValueRef color[8][4] = {};
3831 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3832 LLVMValueRef ret;
3833
3834 if (ctx->postponed_kill)
3835 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3836
3837 /* Read the output values. */
3838 for (i = 0; i < info->num_outputs; i++) {
3839 unsigned semantic_name = info->output_semantic_name[i];
3840 unsigned semantic_index = info->output_semantic_index[i];
3841
3842 switch (semantic_name) {
3843 case TGSI_SEMANTIC_COLOR:
3844 assert(semantic_index < 8);
3845 for (j = 0; j < 4; j++) {
3846 LLVMValueRef ptr = addrs[4 * i + j];
3847 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3848 color[semantic_index][j] = result;
3849 }
3850 break;
3851 case TGSI_SEMANTIC_POSITION:
3852 depth = LLVMBuildLoad(builder,
3853 addrs[4 * i + 2], "");
3854 break;
3855 case TGSI_SEMANTIC_STENCIL:
3856 stencil = LLVMBuildLoad(builder,
3857 addrs[4 * i + 1], "");
3858 break;
3859 case TGSI_SEMANTIC_SAMPLEMASK:
3860 samplemask = LLVMBuildLoad(builder,
3861 addrs[4 * i + 0], "");
3862 break;
3863 default:
3864 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3865 semantic_name);
3866 }
3867 }
3868
3869 /* Fill the return structure. */
3870 ret = ctx->return_value;
3871
3872 /* Set SGPRs. */
3873 ret = LLVMBuildInsertValue(builder, ret,
3874 ac_to_integer(&ctx->ac,
3875 LLVMGetParam(ctx->main_fn,
3876 SI_PARAM_ALPHA_REF)),
3877 SI_SGPR_ALPHA_REF, "");
3878
3879 /* Set VGPRs */
3880 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3881 for (i = 0; i < ARRAY_SIZE(color); i++) {
3882 if (!color[i][0])
3883 continue;
3884
3885 for (j = 0; j < 4; j++)
3886 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3887 }
3888 if (depth)
3889 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3890 if (stencil)
3891 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3892 if (samplemask)
3893 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3894
3895 /* Add the input sample mask for smoothing at the end. */
3896 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3897 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3898 ret = LLVMBuildInsertValue(builder, ret,
3899 LLVMGetParam(ctx->main_fn,
3900 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3901
3902 ctx->return_value = ret;
3903 }
3904
3905 static void membar_emit(
3906 const struct lp_build_tgsi_action *action,
3907 struct lp_build_tgsi_context *bld_base,
3908 struct lp_build_emit_data *emit_data)
3909 {
3910 struct si_shader_context *ctx = si_shader_context(bld_base);
3911 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3912 unsigned flags = LLVMConstIntGetZExtValue(src0);
3913 unsigned waitcnt = NOOP_WAITCNT;
3914
3915 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3916 waitcnt &= VM_CNT & LGKM_CNT;
3917
3918 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3919 TGSI_MEMBAR_SHADER_BUFFER |
3920 TGSI_MEMBAR_SHADER_IMAGE))
3921 waitcnt &= VM_CNT;
3922
3923 if (flags & TGSI_MEMBAR_SHARED)
3924 waitcnt &= LGKM_CNT;
3925
3926 if (waitcnt != NOOP_WAITCNT)
3927 ac_build_waitcnt(&ctx->ac, waitcnt);
3928 }
3929
3930 static void clock_emit(
3931 const struct lp_build_tgsi_action *action,
3932 struct lp_build_tgsi_context *bld_base,
3933 struct lp_build_emit_data *emit_data)
3934 {
3935 struct si_shader_context *ctx = si_shader_context(bld_base);
3936 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3937
3938 emit_data->output[0] =
3939 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3940 emit_data->output[1] =
3941 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3942 }
3943
3944 static void si_llvm_emit_ddxy(
3945 const struct lp_build_tgsi_action *action,
3946 struct lp_build_tgsi_context *bld_base,
3947 struct lp_build_emit_data *emit_data)
3948 {
3949 struct si_shader_context *ctx = si_shader_context(bld_base);
3950 unsigned opcode = emit_data->info->opcode;
3951 LLVMValueRef val;
3952 int idx;
3953 unsigned mask;
3954
3955 if (opcode == TGSI_OPCODE_DDX_FINE)
3956 mask = AC_TID_MASK_LEFT;
3957 else if (opcode == TGSI_OPCODE_DDY_FINE)
3958 mask = AC_TID_MASK_TOP;
3959 else
3960 mask = AC_TID_MASK_TOP_LEFT;
3961
3962 /* for DDX we want to next X pixel, DDY next Y pixel. */
3963 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3964
3965 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3966 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3967 emit_data->output[emit_data->chan] = val;
3968 }
3969
3970 /*
3971 * this takes an I,J coordinate pair,
3972 * and works out the X and Y derivatives.
3973 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3974 */
3975 static LLVMValueRef si_llvm_emit_ddxy_interp(
3976 struct lp_build_tgsi_context *bld_base,
3977 LLVMValueRef interp_ij)
3978 {
3979 struct si_shader_context *ctx = si_shader_context(bld_base);
3980 LLVMValueRef result[4], a;
3981 unsigned i;
3982
3983 for (i = 0; i < 2; i++) {
3984 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3985 LLVMConstInt(ctx->i32, i, 0), "");
3986 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3987 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3988 }
3989
3990 return lp_build_gather_values(&ctx->gallivm, result, 4);
3991 }
3992
3993 static void interp_fetch_args(
3994 struct lp_build_tgsi_context *bld_base,
3995 struct lp_build_emit_data *emit_data)
3996 {
3997 struct si_shader_context *ctx = si_shader_context(bld_base);
3998 const struct tgsi_full_instruction *inst = emit_data->inst;
3999
4000 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4001 /* offset is in second src, first two channels */
4002 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4003 emit_data->inst, 1,
4004 TGSI_CHAN_X);
4005 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4006 emit_data->inst, 1,
4007 TGSI_CHAN_Y);
4008 emit_data->arg_count = 2;
4009 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4010 LLVMValueRef sample_position;
4011 LLVMValueRef sample_id;
4012 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4013
4014 /* fetch sample ID, then fetch its sample position,
4015 * and place into first two channels.
4016 */
4017 sample_id = lp_build_emit_fetch(bld_base,
4018 emit_data->inst, 1, TGSI_CHAN_X);
4019 sample_id = ac_to_integer(&ctx->ac, sample_id);
4020
4021 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4022 * Language 4.50 spec says about interpolateAtSample:
4023 *
4024 * "Returns the value of the input interpolant variable at
4025 * the location of sample number sample. If multisample
4026 * buffers are not available, the input variable will be
4027 * evaluated at the center of the pixel. If sample sample
4028 * does not exist, the position used to interpolate the
4029 * input variable is undefined."
4030 *
4031 * This means that sample_id values outside of the valid are
4032 * in fact valid input, and the usual mechanism for loading the
4033 * sample position doesn't work.
4034 */
4035 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4036 LLVMValueRef center[4] = {
4037 LLVMConstReal(ctx->f32, 0.5),
4038 LLVMConstReal(ctx->f32, 0.5),
4039 ctx->ac.f32_0,
4040 ctx->ac.f32_0,
4041 };
4042
4043 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4044 } else {
4045 sample_position = load_sample_position(&ctx->abi, sample_id);
4046 }
4047
4048 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4049 sample_position,
4050 ctx->i32_0, "");
4051
4052 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4053 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4054 sample_position,
4055 ctx->i32_1, "");
4056 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4057 emit_data->arg_count = 2;
4058 }
4059 }
4060
4061 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4062 struct lp_build_tgsi_context *bld_base,
4063 struct lp_build_emit_data *emit_data)
4064 {
4065 struct si_shader_context *ctx = si_shader_context(bld_base);
4066 struct si_shader *shader = ctx->shader;
4067 const struct tgsi_shader_info *info = &shader->selector->info;
4068 LLVMValueRef interp_param;
4069 const struct tgsi_full_instruction *inst = emit_data->inst;
4070 const struct tgsi_full_src_register *input = &inst->Src[0];
4071 int input_base, input_array_size;
4072 int chan;
4073 int i;
4074 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4075 LLVMValueRef array_idx;
4076 int interp_param_idx;
4077 unsigned interp;
4078 unsigned location;
4079
4080 assert(input->Register.File == TGSI_FILE_INPUT);
4081
4082 if (input->Register.Indirect) {
4083 unsigned array_id = input->Indirect.ArrayID;
4084
4085 if (array_id) {
4086 input_base = info->input_array_first[array_id];
4087 input_array_size = info->input_array_last[array_id] - input_base + 1;
4088 } else {
4089 input_base = inst->Src[0].Register.Index;
4090 input_array_size = info->num_inputs - input_base;
4091 }
4092
4093 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4094 1, input->Register.Index - input_base);
4095 } else {
4096 input_base = inst->Src[0].Register.Index;
4097 input_array_size = 1;
4098 array_idx = ctx->i32_0;
4099 }
4100
4101 interp = shader->selector->info.input_interpolate[input_base];
4102
4103 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4104 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4105 location = TGSI_INTERPOLATE_LOC_CENTER;
4106 else
4107 location = TGSI_INTERPOLATE_LOC_CENTROID;
4108
4109 interp_param_idx = lookup_interp_param_index(interp, location);
4110 if (interp_param_idx == -1)
4111 return;
4112 else if (interp_param_idx)
4113 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4114 else
4115 interp_param = NULL;
4116
4117 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4118 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4119 LLVMValueRef ij_out[2];
4120 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4121
4122 /*
4123 * take the I then J parameters, and the DDX/Y for it, and
4124 * calculate the IJ inputs for the interpolator.
4125 * temp1 = ddx * offset/sample.x + I;
4126 * interp_param.I = ddy * offset/sample.y + temp1;
4127 * temp1 = ddx * offset/sample.x + J;
4128 * interp_param.J = ddy * offset/sample.y + temp1;
4129 */
4130 for (i = 0; i < 2; i++) {
4131 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4132 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4133 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4134 ddxy_out, ix_ll, "");
4135 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4136 ddxy_out, iy_ll, "");
4137 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4138 interp_param, ix_ll, "");
4139 LLVMValueRef temp1, temp2;
4140
4141 interp_el = ac_to_float(&ctx->ac, interp_el);
4142
4143 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4144
4145 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4146
4147 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4148
4149 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4150 }
4151 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4152 }
4153
4154 if (interp_param)
4155 interp_param = ac_to_float(&ctx->ac, interp_param);
4156
4157 for (chan = 0; chan < 4; chan++) {
4158 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4159 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4160
4161 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4162 LLVMValueRef v, i = NULL, j = NULL;
4163
4164 if (interp_param) {
4165 i = LLVMBuildExtractElement(
4166 ctx->ac.builder, interp_param, ctx->i32_0, "");
4167 j = LLVMBuildExtractElement(
4168 ctx->ac.builder, interp_param, ctx->i32_1, "");
4169 }
4170 v = si_build_fs_interp(ctx, input_base + idx, schan,
4171 prim_mask, i, j);
4172
4173 gather = LLVMBuildInsertElement(ctx->ac.builder,
4174 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4175 }
4176
4177 emit_data->output[chan] = LLVMBuildExtractElement(
4178 ctx->ac.builder, gather, array_idx, "");
4179 }
4180 }
4181
4182 static void vote_all_emit(
4183 const struct lp_build_tgsi_action *action,
4184 struct lp_build_tgsi_context *bld_base,
4185 struct lp_build_emit_data *emit_data)
4186 {
4187 struct si_shader_context *ctx = si_shader_context(bld_base);
4188
4189 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4190 emit_data->output[emit_data->chan] =
4191 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4192 }
4193
4194 static void vote_any_emit(
4195 const struct lp_build_tgsi_action *action,
4196 struct lp_build_tgsi_context *bld_base,
4197 struct lp_build_emit_data *emit_data)
4198 {
4199 struct si_shader_context *ctx = si_shader_context(bld_base);
4200
4201 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4202 emit_data->output[emit_data->chan] =
4203 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4204 }
4205
4206 static void vote_eq_emit(
4207 const struct lp_build_tgsi_action *action,
4208 struct lp_build_tgsi_context *bld_base,
4209 struct lp_build_emit_data *emit_data)
4210 {
4211 struct si_shader_context *ctx = si_shader_context(bld_base);
4212
4213 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4214 emit_data->output[emit_data->chan] =
4215 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4216 }
4217
4218 static void ballot_emit(
4219 const struct lp_build_tgsi_action *action,
4220 struct lp_build_tgsi_context *bld_base,
4221 struct lp_build_emit_data *emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224 LLVMBuilderRef builder = ctx->ac.builder;
4225 LLVMValueRef tmp;
4226
4227 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4228 tmp = ac_build_ballot(&ctx->ac, tmp);
4229 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4230
4231 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4232 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4233 }
4234
4235 static void read_invoc_fetch_args(
4236 struct lp_build_tgsi_context *bld_base,
4237 struct lp_build_emit_data *emit_data)
4238 {
4239 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4240 0, emit_data->src_chan);
4241
4242 /* Always read the source invocation (= lane) from the X channel. */
4243 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4244 1, TGSI_CHAN_X);
4245 emit_data->arg_count = 2;
4246 }
4247
4248 static void read_lane_emit(
4249 const struct lp_build_tgsi_action *action,
4250 struct lp_build_tgsi_context *bld_base,
4251 struct lp_build_emit_data *emit_data)
4252 {
4253 struct si_shader_context *ctx = si_shader_context(bld_base);
4254
4255 /* We currently have no other way to prevent LLVM from lifting the icmp
4256 * calls to a dominating basic block.
4257 */
4258 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4259
4260 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4261 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4262
4263 emit_data->output[emit_data->chan] =
4264 ac_build_intrinsic(&ctx->ac, action->intr_name,
4265 ctx->i32, emit_data->args, emit_data->arg_count,
4266 AC_FUNC_ATTR_READNONE |
4267 AC_FUNC_ATTR_CONVERGENT);
4268 }
4269
4270 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4271 struct lp_build_emit_data *emit_data)
4272 {
4273 struct si_shader_context *ctx = si_shader_context(bld_base);
4274 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4275 LLVMValueRef imm;
4276 unsigned stream;
4277
4278 assert(src0.File == TGSI_FILE_IMMEDIATE);
4279
4280 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4281 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4282 return stream;
4283 }
4284
4285 /* Emit one vertex from the geometry shader */
4286 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4287 unsigned stream,
4288 LLVMValueRef *addrs)
4289 {
4290 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4291 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4292 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4293 struct si_shader *shader = ctx->shader;
4294 struct lp_build_if_state if_state;
4295 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4296 ctx->param_gs2vs_offset);
4297 LLVMValueRef gs_next_vertex;
4298 LLVMValueRef can_emit;
4299 unsigned chan, offset;
4300 int i;
4301
4302 /* Write vertex attribute values to GSVS ring */
4303 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4304 ctx->gs_next_vertex[stream],
4305 "");
4306
4307 /* If this thread has already emitted the declared maximum number of
4308 * vertices, skip the write: excessive vertex emissions are not
4309 * supposed to have any effect.
4310 *
4311 * If the shader has no writes to memory, kill it instead. This skips
4312 * further memory loads and may allow LLVM to skip to the end
4313 * altogether.
4314 */
4315 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4316 LLVMConstInt(ctx->i32,
4317 shader->selector->gs_max_out_vertices, 0), "");
4318
4319 bool use_kill = !info->writes_memory;
4320 if (use_kill) {
4321 ac_build_kill_if_false(&ctx->ac, can_emit);
4322 } else {
4323 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4324 }
4325
4326 offset = 0;
4327 for (i = 0; i < info->num_outputs; i++) {
4328 for (chan = 0; chan < 4; chan++) {
4329 if (!(info->output_usagemask[i] & (1 << chan)) ||
4330 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4331 continue;
4332
4333 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4334 LLVMValueRef voffset =
4335 LLVMConstInt(ctx->i32, offset *
4336 shader->selector->gs_max_out_vertices, 0);
4337 offset++;
4338
4339 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4340 voffset = lp_build_mul_imm(uint, voffset, 4);
4341
4342 out_val = ac_to_integer(&ctx->ac, out_val);
4343
4344 ac_build_buffer_store_dword(&ctx->ac,
4345 ctx->gsvs_ring[stream],
4346 out_val, 1,
4347 voffset, soffset, 0,
4348 1, 1, true, true);
4349 }
4350 }
4351
4352 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4353 ctx->i32_1);
4354
4355 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4356
4357 /* Signal vertex emission */
4358 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4359 si_get_gs_wave_id(ctx));
4360 if (!use_kill)
4361 lp_build_endif(&if_state);
4362 }
4363
4364 /* Emit one vertex from the geometry shader */
4365 static void si_tgsi_emit_vertex(
4366 const struct lp_build_tgsi_action *action,
4367 struct lp_build_tgsi_context *bld_base,
4368 struct lp_build_emit_data *emit_data)
4369 {
4370 struct si_shader_context *ctx = si_shader_context(bld_base);
4371 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4372
4373 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4374 }
4375
4376 /* Cut one primitive from the geometry shader */
4377 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4378 unsigned stream)
4379 {
4380 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4381
4382 /* Signal primitive cut */
4383 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4384 si_get_gs_wave_id(ctx));
4385 }
4386
4387 /* Cut one primitive from the geometry shader */
4388 static void si_tgsi_emit_primitive(
4389 const struct lp_build_tgsi_action *action,
4390 struct lp_build_tgsi_context *bld_base,
4391 struct lp_build_emit_data *emit_data)
4392 {
4393 struct si_shader_context *ctx = si_shader_context(bld_base);
4394
4395 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4396 }
4397
4398 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4399 struct lp_build_tgsi_context *bld_base,
4400 struct lp_build_emit_data *emit_data)
4401 {
4402 struct si_shader_context *ctx = si_shader_context(bld_base);
4403
4404 /* SI only (thanks to a hw bug workaround):
4405 * The real barrier instruction isn’t needed, because an entire patch
4406 * always fits into a single wave.
4407 */
4408 if (ctx->screen->info.chip_class == SI &&
4409 ctx->type == PIPE_SHADER_TESS_CTRL) {
4410 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4411 return;
4412 }
4413
4414 lp_build_intrinsic(ctx->ac.builder,
4415 "llvm.amdgcn.s.barrier",
4416 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4417 }
4418
4419 static const struct lp_build_tgsi_action interp_action = {
4420 .fetch_args = interp_fetch_args,
4421 .emit = build_interp_intrinsic,
4422 };
4423
4424 static void si_create_function(struct si_shader_context *ctx,
4425 const char *name,
4426 LLVMTypeRef *returns, unsigned num_returns,
4427 struct si_function_info *fninfo,
4428 unsigned max_workgroup_size)
4429 {
4430 int i;
4431
4432 si_llvm_create_func(ctx, name, returns, num_returns,
4433 fninfo->types, fninfo->num_params);
4434 ctx->return_value = LLVMGetUndef(ctx->return_type);
4435
4436 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4437 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4438
4439 /* The combination of:
4440 * - noalias
4441 * - dereferenceable
4442 * - invariant.load
4443 * allows the optimization passes to move loads and reduces
4444 * SGPR spilling significantly.
4445 */
4446 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4447
4448 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4449 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4450 ac_add_attr_dereferenceable(P, UINT64_MAX);
4451 }
4452 }
4453
4454 for (i = 0; i < fninfo->num_params; ++i) {
4455 if (fninfo->assign[i])
4456 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4457 }
4458
4459 if (ctx->screen->info.address32_hi) {
4460 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4461 "amdgpu-32bit-address-high-bits",
4462 ctx->screen->info.address32_hi);
4463 }
4464
4465 if (max_workgroup_size) {
4466 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4467 "amdgpu-max-work-group-size",
4468 max_workgroup_size);
4469 }
4470 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4471 "no-signed-zeros-fp-math",
4472 "true");
4473
4474 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4475 /* These were copied from some LLVM test. */
4476 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4477 "less-precise-fpmad",
4478 "true");
4479 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4480 "no-infs-fp-math",
4481 "true");
4482 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4483 "no-nans-fp-math",
4484 "true");
4485 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4486 "unsafe-fp-math",
4487 "true");
4488 }
4489 }
4490
4491 static void declare_streamout_params(struct si_shader_context *ctx,
4492 struct pipe_stream_output_info *so,
4493 struct si_function_info *fninfo)
4494 {
4495 int i;
4496
4497 /* Streamout SGPRs. */
4498 if (so->num_outputs) {
4499 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4500 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4501 else
4502 ctx->param_streamout_config = fninfo->num_params - 1;
4503
4504 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4505 }
4506 /* A streamout buffer offset is loaded if the stride is non-zero. */
4507 for (i = 0; i < 4; i++) {
4508 if (!so->stride[i])
4509 continue;
4510
4511 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4512 }
4513 }
4514
4515 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4516 {
4517 switch (shader->selector->type) {
4518 case PIPE_SHADER_TESS_CTRL:
4519 /* Return this so that LLVM doesn't remove s_barrier
4520 * instructions on chips where we use s_barrier. */
4521 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4522
4523 case PIPE_SHADER_GEOMETRY:
4524 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4525
4526 case PIPE_SHADER_COMPUTE:
4527 break; /* see below */
4528
4529 default:
4530 return 0;
4531 }
4532
4533 const unsigned *properties = shader->selector->info.properties;
4534 unsigned max_work_group_size =
4535 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4536 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4537 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4538
4539 if (!max_work_group_size) {
4540 /* This is a variable group size compute shader,
4541 * compile it for the maximum possible group size.
4542 */
4543 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4544 }
4545 return max_work_group_size;
4546 }
4547
4548 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4549 struct si_function_info *fninfo,
4550 bool assign_params)
4551 {
4552 LLVMTypeRef const_shader_buf_type;
4553
4554 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4555 ctx->shader->selector->info.shader_buffers_declared == 0)
4556 const_shader_buf_type = ctx->f32;
4557 else
4558 const_shader_buf_type = ctx->v4i32;
4559
4560 unsigned const_and_shader_buffers =
4561 add_arg(fninfo, ARG_SGPR,
4562 ac_array_in_const32_addr_space(const_shader_buf_type));
4563
4564 if (assign_params)
4565 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4566 }
4567
4568 static void declare_samplers_and_images(struct si_shader_context *ctx,
4569 struct si_function_info *fninfo,
4570 bool assign_params)
4571 {
4572 unsigned samplers_and_images =
4573 add_arg(fninfo, ARG_SGPR,
4574 ac_array_in_const32_addr_space(ctx->v8i32));
4575
4576 if (assign_params)
4577 ctx->param_samplers_and_images = samplers_and_images;
4578 }
4579
4580 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4581 struct si_function_info *fninfo,
4582 bool assign_params)
4583 {
4584 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4585 declare_samplers_and_images(ctx, fninfo, assign_params);
4586 }
4587
4588 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4589 struct si_function_info *fninfo)
4590 {
4591 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4592 ac_array_in_const32_addr_space(ctx->v4i32));
4593 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4594 ac_array_in_const32_addr_space(ctx->v8i32));
4595 }
4596
4597 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4598 struct si_function_info *fninfo)
4599 {
4600 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4601 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4602 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4603 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4604 }
4605
4606 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4607 struct si_function_info *fninfo,
4608 unsigned *num_prolog_vgprs)
4609 {
4610 struct si_shader *shader = ctx->shader;
4611
4612 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4613 if (shader->key.as_ls) {
4614 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4615 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4616 } else {
4617 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4618 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4619 }
4620 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4621
4622 if (!shader->is_gs_copy_shader) {
4623 /* Vertex load indices. */
4624 ctx->param_vertex_index0 = fninfo->num_params;
4625 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4626 add_arg(fninfo, ARG_VGPR, ctx->i32);
4627 *num_prolog_vgprs += shader->selector->info.num_inputs;
4628 }
4629 }
4630
4631 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4632 struct si_function_info *fninfo)
4633 {
4634 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4635 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4636 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4637 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4638 }
4639
4640 enum {
4641 /* Convenient merged shader definitions. */
4642 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4643 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4644 };
4645
4646 static void create_function(struct si_shader_context *ctx)
4647 {
4648 struct si_shader *shader = ctx->shader;
4649 struct si_function_info fninfo;
4650 LLVMTypeRef returns[16+32*4];
4651 unsigned i, num_return_sgprs;
4652 unsigned num_returns = 0;
4653 unsigned num_prolog_vgprs = 0;
4654 unsigned type = ctx->type;
4655 unsigned vs_blit_property =
4656 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4657
4658 si_init_function_info(&fninfo);
4659
4660 /* Set MERGED shaders. */
4661 if (ctx->screen->info.chip_class >= GFX9) {
4662 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4663 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4664 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4665 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4666 }
4667
4668 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4669
4670 switch (type) {
4671 case PIPE_SHADER_VERTEX:
4672 declare_global_desc_pointers(ctx, &fninfo);
4673
4674 if (vs_blit_property) {
4675 ctx->param_vs_blit_inputs = fninfo.num_params;
4676 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4677 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4678 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4679
4680 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4681 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4682 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4683 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4684 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4685 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4686 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4687 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4688 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4689 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4690 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4691 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4692 }
4693
4694 /* VGPRs */
4695 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4696 break;
4697 }
4698
4699 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4700 declare_vs_specific_input_sgprs(ctx, &fninfo);
4701 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4702 ac_array_in_const32_addr_space(ctx->v4i32));
4703
4704 if (shader->key.as_es) {
4705 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4706 } else if (shader->key.as_ls) {
4707 /* no extra parameters */
4708 } else {
4709 if (shader->is_gs_copy_shader) {
4710 fninfo.num_params = ctx->param_rw_buffers + 1;
4711 fninfo.num_sgpr_params = fninfo.num_params;
4712 }
4713
4714 /* The locations of the other parameters are assigned dynamically. */
4715 declare_streamout_params(ctx, &shader->selector->so,
4716 &fninfo);
4717 }
4718
4719 /* VGPRs */
4720 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4721 break;
4722
4723 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4724 declare_global_desc_pointers(ctx, &fninfo);
4725 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4726 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4727 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4731 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4732
4733 /* VGPRs */
4734 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4735 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4736
4737 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4738 * placed after the user SGPRs.
4739 */
4740 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4741 returns[num_returns++] = ctx->i32; /* SGPRs */
4742 for (i = 0; i < 11; i++)
4743 returns[num_returns++] = ctx->f32; /* VGPRs */
4744 break;
4745
4746 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4747 /* Merged stages have 8 system SGPRs at the beginning. */
4748 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4749 if (HAVE_32BIT_POINTERS) {
4750 declare_per_stage_desc_pointers(ctx, &fninfo,
4751 ctx->type == PIPE_SHADER_TESS_CTRL);
4752 } else {
4753 declare_const_and_shader_buffers(ctx, &fninfo,
4754 ctx->type == PIPE_SHADER_TESS_CTRL);
4755 }
4756 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4757 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4758 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4759 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4760 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4761 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4762
4763 declare_global_desc_pointers(ctx, &fninfo);
4764 declare_per_stage_desc_pointers(ctx, &fninfo,
4765 ctx->type == PIPE_SHADER_VERTEX);
4766 declare_vs_specific_input_sgprs(ctx, &fninfo);
4767
4768 if (!HAVE_32BIT_POINTERS) {
4769 declare_samplers_and_images(ctx, &fninfo,
4770 ctx->type == PIPE_SHADER_TESS_CTRL);
4771 }
4772 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4773 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4774 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4775 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4776 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4777 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4778 ac_array_in_const32_addr_space(ctx->v4i32));
4779
4780 /* VGPRs (first TCS, then VS) */
4781 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4782 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4783
4784 if (ctx->type == PIPE_SHADER_VERTEX) {
4785 declare_vs_input_vgprs(ctx, &fninfo,
4786 &num_prolog_vgprs);
4787
4788 /* LS return values are inputs to the TCS main shader part. */
4789 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4790 returns[num_returns++] = ctx->i32; /* SGPRs */
4791 for (i = 0; i < 2; i++)
4792 returns[num_returns++] = ctx->f32; /* VGPRs */
4793 } else {
4794 /* TCS return values are inputs to the TCS epilog.
4795 *
4796 * param_tcs_offchip_offset, param_tcs_factor_offset,
4797 * param_tcs_offchip_layout, and param_rw_buffers
4798 * should be passed to the epilog.
4799 */
4800 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4801 returns[num_returns++] = ctx->i32; /* SGPRs */
4802 for (i = 0; i < 11; i++)
4803 returns[num_returns++] = ctx->f32; /* VGPRs */
4804 }
4805 break;
4806
4807 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4808 /* Merged stages have 8 system SGPRs at the beginning. */
4809 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4810 if (HAVE_32BIT_POINTERS) {
4811 declare_per_stage_desc_pointers(ctx, &fninfo,
4812 ctx->type == PIPE_SHADER_GEOMETRY);
4813 } else {
4814 declare_const_and_shader_buffers(ctx, &fninfo,
4815 ctx->type == PIPE_SHADER_GEOMETRY);
4816 }
4817 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4818 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4819 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4820 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4821 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4822 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4823
4824 declare_global_desc_pointers(ctx, &fninfo);
4825 declare_per_stage_desc_pointers(ctx, &fninfo,
4826 (ctx->type == PIPE_SHADER_VERTEX ||
4827 ctx->type == PIPE_SHADER_TESS_EVAL));
4828 if (ctx->type == PIPE_SHADER_VERTEX) {
4829 declare_vs_specific_input_sgprs(ctx, &fninfo);
4830 } else {
4831 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4832 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4833 if (!HAVE_32BIT_POINTERS) {
4834 /* Declare as many input SGPRs as the VS has. */
4835 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4836 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4837 }
4838 }
4839
4840 if (!HAVE_32BIT_POINTERS) {
4841 declare_samplers_and_images(ctx, &fninfo,
4842 ctx->type == PIPE_SHADER_GEOMETRY);
4843 }
4844 if (ctx->type == PIPE_SHADER_VERTEX) {
4845 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4846 ac_array_in_const32_addr_space(ctx->v4i32));
4847 }
4848
4849 /* VGPRs (first GS, then VS/TES) */
4850 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4851 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4852 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4853 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4854 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4855
4856 if (ctx->type == PIPE_SHADER_VERTEX) {
4857 declare_vs_input_vgprs(ctx, &fninfo,
4858 &num_prolog_vgprs);
4859 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4860 declare_tes_input_vgprs(ctx, &fninfo);
4861 }
4862
4863 if (ctx->type == PIPE_SHADER_VERTEX ||
4864 ctx->type == PIPE_SHADER_TESS_EVAL) {
4865 unsigned num_user_sgprs;
4866
4867 if (ctx->type == PIPE_SHADER_VERTEX)
4868 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4869 else
4870 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4871
4872 /* ES return values are inputs to GS. */
4873 for (i = 0; i < 8 + num_user_sgprs; i++)
4874 returns[num_returns++] = ctx->i32; /* SGPRs */
4875 for (i = 0; i < 5; i++)
4876 returns[num_returns++] = ctx->f32; /* VGPRs */
4877 }
4878 break;
4879
4880 case PIPE_SHADER_TESS_EVAL:
4881 declare_global_desc_pointers(ctx, &fninfo);
4882 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4883 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4884 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4885
4886 if (shader->key.as_es) {
4887 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4888 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4889 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4890 } else {
4891 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4892 declare_streamout_params(ctx, &shader->selector->so,
4893 &fninfo);
4894 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4895 }
4896
4897 /* VGPRs */
4898 declare_tes_input_vgprs(ctx, &fninfo);
4899 break;
4900
4901 case PIPE_SHADER_GEOMETRY:
4902 declare_global_desc_pointers(ctx, &fninfo);
4903 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4904 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4905 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4906
4907 /* VGPRs */
4908 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4909 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4910 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4911 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4912 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4913 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4914 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4915 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4916 break;
4917
4918 case PIPE_SHADER_FRAGMENT:
4919 declare_global_desc_pointers(ctx, &fninfo);
4920 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4921 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4922 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4923 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4924
4925 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4926 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4927 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4928 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4929 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4930 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4931 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4932 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4933 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4934 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4935 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4936 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4937 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4938 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4939 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4940 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4941 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4942 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4943 shader->info.face_vgpr_index = 20;
4944 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4945 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4946 shader->info.ancillary_vgpr_index = 21;
4947 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4948 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4949 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4950
4951 /* Color inputs from the prolog. */
4952 if (shader->selector->info.colors_read) {
4953 unsigned num_color_elements =
4954 util_bitcount(shader->selector->info.colors_read);
4955
4956 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4957 for (i = 0; i < num_color_elements; i++)
4958 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4959
4960 num_prolog_vgprs += num_color_elements;
4961 }
4962
4963 /* Outputs for the epilog. */
4964 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4965 num_returns =
4966 num_return_sgprs +
4967 util_bitcount(shader->selector->info.colors_written) * 4 +
4968 shader->selector->info.writes_z +
4969 shader->selector->info.writes_stencil +
4970 shader->selector->info.writes_samplemask +
4971 1 /* SampleMaskIn */;
4972
4973 num_returns = MAX2(num_returns,
4974 num_return_sgprs +
4975 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4976
4977 for (i = 0; i < num_return_sgprs; i++)
4978 returns[i] = ctx->i32;
4979 for (; i < num_returns; i++)
4980 returns[i] = ctx->f32;
4981 break;
4982
4983 case PIPE_SHADER_COMPUTE:
4984 declare_global_desc_pointers(ctx, &fninfo);
4985 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4986 if (shader->selector->info.uses_grid_size)
4987 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4988 if (shader->selector->info.uses_block_size)
4989 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4990
4991 for (i = 0; i < 3; i++) {
4992 ctx->abi.workgroup_ids[i] = NULL;
4993 if (shader->selector->info.uses_block_id[i])
4994 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4995 }
4996
4997 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4998 break;
4999 default:
5000 assert(0 && "unimplemented shader");
5001 return;
5002 }
5003
5004 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5005 si_get_max_workgroup_size(shader));
5006
5007 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5008 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5009 ctx->separate_prolog) {
5010 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5011 "InitialPSInputAddr",
5012 S_0286D0_PERSP_SAMPLE_ENA(1) |
5013 S_0286D0_PERSP_CENTER_ENA(1) |
5014 S_0286D0_PERSP_CENTROID_ENA(1) |
5015 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5016 S_0286D0_LINEAR_CENTER_ENA(1) |
5017 S_0286D0_LINEAR_CENTROID_ENA(1) |
5018 S_0286D0_FRONT_FACE_ENA(1) |
5019 S_0286D0_ANCILLARY_ENA(1) |
5020 S_0286D0_POS_FIXED_PT_ENA(1));
5021 }
5022
5023 shader->info.num_input_sgprs = 0;
5024 shader->info.num_input_vgprs = 0;
5025
5026 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5027 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5028
5029 for (; i < fninfo.num_params; ++i)
5030 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5031
5032 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5033 shader->info.num_input_vgprs -= num_prolog_vgprs;
5034
5035 if (shader->key.as_ls ||
5036 ctx->type == PIPE_SHADER_TESS_CTRL ||
5037 /* GFX9 has the ESGS ring buffer in LDS. */
5038 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5039 ac_declare_lds_as_pointer(&ctx->ac);
5040 }
5041
5042 /**
5043 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5044 * for later use.
5045 */
5046 static void preload_ring_buffers(struct si_shader_context *ctx)
5047 {
5048 LLVMBuilderRef builder = ctx->ac.builder;
5049
5050 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5051 ctx->param_rw_buffers);
5052
5053 if (ctx->screen->info.chip_class <= VI &&
5054 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5055 unsigned ring =
5056 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5057 : SI_ES_RING_ESGS;
5058 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5059
5060 ctx->esgs_ring =
5061 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5062 }
5063
5064 if (ctx->shader->is_gs_copy_shader) {
5065 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5066
5067 ctx->gsvs_ring[0] =
5068 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5069 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5070 const struct si_shader_selector *sel = ctx->shader->selector;
5071 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5072 LLVMValueRef base_ring;
5073
5074 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5075
5076 /* The conceptual layout of the GSVS ring is
5077 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5078 * but the real memory layout is swizzled across
5079 * threads:
5080 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5081 * t16v0c0 ..
5082 * Override the buffer descriptor accordingly.
5083 */
5084 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5085 uint64_t stream_offset = 0;
5086
5087 for (unsigned stream = 0; stream < 4; ++stream) {
5088 unsigned num_components;
5089 unsigned stride;
5090 unsigned num_records;
5091 LLVMValueRef ring, tmp;
5092
5093 num_components = sel->info.num_stream_output_components[stream];
5094 if (!num_components)
5095 continue;
5096
5097 stride = 4 * num_components * sel->gs_max_out_vertices;
5098
5099 /* Limit on the stride field for <= CIK. */
5100 assert(stride < (1 << 14));
5101
5102 num_records = 64;
5103
5104 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5105 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5106 tmp = LLVMBuildAdd(builder, tmp,
5107 LLVMConstInt(ctx->i64,
5108 stream_offset, 0), "");
5109 stream_offset += stride * 64;
5110
5111 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5112 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5113 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5114 tmp = LLVMBuildOr(builder, tmp,
5115 LLVMConstInt(ctx->i32,
5116 S_008F04_STRIDE(stride) |
5117 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5118 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5119 ring = LLVMBuildInsertElement(builder, ring,
5120 LLVMConstInt(ctx->i32, num_records, 0),
5121 LLVMConstInt(ctx->i32, 2, 0), "");
5122 ring = LLVMBuildInsertElement(builder, ring,
5123 LLVMConstInt(ctx->i32,
5124 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5125 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5126 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5127 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5128 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5129 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5130 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5131 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5132 S_008F0C_ADD_TID_ENABLE(1),
5133 0),
5134 LLVMConstInt(ctx->i32, 3, 0), "");
5135
5136 ctx->gsvs_ring[stream] = ring;
5137 }
5138 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5139 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5140 }
5141 }
5142
5143 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5144 LLVMValueRef param_rw_buffers,
5145 unsigned param_pos_fixed_pt)
5146 {
5147 LLVMBuilderRef builder = ctx->ac.builder;
5148 LLVMValueRef slot, desc, offset, row, bit, address[2];
5149
5150 /* Use the fixed-point gl_FragCoord input.
5151 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5152 * per coordinate to get the repeating effect.
5153 */
5154 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5155 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5156
5157 /* Load the buffer descriptor. */
5158 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5159 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5160
5161 /* The stipple pattern is 32x32, each row has 32 bits. */
5162 offset = LLVMBuildMul(builder, address[1],
5163 LLVMConstInt(ctx->i32, 4, 0), "");
5164 row = buffer_load_const(ctx, desc, offset);
5165 row = ac_to_integer(&ctx->ac, row);
5166 bit = LLVMBuildLShr(builder, row, address[0], "");
5167 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5168 ac_build_kill_if_false(&ctx->ac, bit);
5169 }
5170
5171 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5172 struct si_shader_config *conf,
5173 unsigned symbol_offset)
5174 {
5175 unsigned i;
5176 const unsigned char *config =
5177 ac_shader_binary_config_start(binary, symbol_offset);
5178 bool really_needs_scratch = false;
5179
5180 /* LLVM adds SGPR spills to the scratch size.
5181 * Find out if we really need the scratch buffer.
5182 */
5183 for (i = 0; i < binary->reloc_count; i++) {
5184 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5185
5186 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5187 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5188 really_needs_scratch = true;
5189 break;
5190 }
5191 }
5192
5193 /* XXX: We may be able to emit some of these values directly rather than
5194 * extracting fields to be emitted later.
5195 */
5196
5197 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5198 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5199 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5200 switch (reg) {
5201 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5202 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5203 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5204 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5205 case R_00B848_COMPUTE_PGM_RSRC1:
5206 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5207 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5208 conf->float_mode = G_00B028_FLOAT_MODE(value);
5209 conf->rsrc1 = value;
5210 break;
5211 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5212 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5213 break;
5214 case R_00B84C_COMPUTE_PGM_RSRC2:
5215 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5216 conf->rsrc2 = value;
5217 break;
5218 case R_0286CC_SPI_PS_INPUT_ENA:
5219 conf->spi_ps_input_ena = value;
5220 break;
5221 case R_0286D0_SPI_PS_INPUT_ADDR:
5222 conf->spi_ps_input_addr = value;
5223 break;
5224 case R_0286E8_SPI_TMPRING_SIZE:
5225 case R_00B860_COMPUTE_TMPRING_SIZE:
5226 /* WAVESIZE is in units of 256 dwords. */
5227 if (really_needs_scratch)
5228 conf->scratch_bytes_per_wave =
5229 G_00B860_WAVESIZE(value) * 256 * 4;
5230 break;
5231 case 0x4: /* SPILLED_SGPRS */
5232 conf->spilled_sgprs = value;
5233 break;
5234 case 0x8: /* SPILLED_VGPRS */
5235 conf->spilled_vgprs = value;
5236 break;
5237 default:
5238 {
5239 static bool printed;
5240
5241 if (!printed) {
5242 fprintf(stderr, "Warning: LLVM emitted unknown "
5243 "config register: 0x%x\n", reg);
5244 printed = true;
5245 }
5246 }
5247 break;
5248 }
5249 }
5250
5251 if (!conf->spi_ps_input_addr)
5252 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5253 }
5254
5255 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5256 uint64_t scratch_va)
5257 {
5258 unsigned i;
5259 uint32_t scratch_rsrc_dword0 = scratch_va;
5260 uint32_t scratch_rsrc_dword1 =
5261 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5262
5263 /* Enable scratch coalescing. */
5264 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5265
5266 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5267 const struct ac_shader_reloc *reloc =
5268 &shader->binary.relocs[i];
5269 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5270 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5271 &scratch_rsrc_dword0, 4);
5272 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5273 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5274 &scratch_rsrc_dword1, 4);
5275 }
5276 }
5277 }
5278
5279 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5280 {
5281 unsigned size = shader->binary.code_size;
5282
5283 if (shader->prolog)
5284 size += shader->prolog->binary.code_size;
5285 if (shader->previous_stage)
5286 size += shader->previous_stage->binary.code_size;
5287 if (shader->prolog2)
5288 size += shader->prolog2->binary.code_size;
5289 if (shader->epilog)
5290 size += shader->epilog->binary.code_size;
5291 return size;
5292 }
5293
5294 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5295 {
5296 const struct ac_shader_binary *prolog =
5297 shader->prolog ? &shader->prolog->binary : NULL;
5298 const struct ac_shader_binary *previous_stage =
5299 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5300 const struct ac_shader_binary *prolog2 =
5301 shader->prolog2 ? &shader->prolog2->binary : NULL;
5302 const struct ac_shader_binary *epilog =
5303 shader->epilog ? &shader->epilog->binary : NULL;
5304 const struct ac_shader_binary *mainb = &shader->binary;
5305 unsigned bo_size = si_get_shader_binary_size(shader) +
5306 (!epilog ? mainb->rodata_size : 0);
5307 unsigned char *ptr;
5308
5309 assert(!prolog || !prolog->rodata_size);
5310 assert(!previous_stage || !previous_stage->rodata_size);
5311 assert(!prolog2 || !prolog2->rodata_size);
5312 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5313 !mainb->rodata_size);
5314 assert(!epilog || !epilog->rodata_size);
5315
5316 r600_resource_reference(&shader->bo, NULL);
5317 shader->bo = (struct r600_resource*)
5318 si_aligned_buffer_create(&sscreen->b,
5319 sscreen->cpdma_prefetch_writes_memory ?
5320 0 : R600_RESOURCE_FLAG_READ_ONLY,
5321 PIPE_USAGE_IMMUTABLE,
5322 align(bo_size, SI_CPDMA_ALIGNMENT),
5323 256);
5324 if (!shader->bo)
5325 return -ENOMEM;
5326
5327 /* Upload. */
5328 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5329 PIPE_TRANSFER_READ_WRITE |
5330 PIPE_TRANSFER_UNSYNCHRONIZED);
5331
5332 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5333 * endian-independent. */
5334 if (prolog) {
5335 memcpy(ptr, prolog->code, prolog->code_size);
5336 ptr += prolog->code_size;
5337 }
5338 if (previous_stage) {
5339 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5340 ptr += previous_stage->code_size;
5341 }
5342 if (prolog2) {
5343 memcpy(ptr, prolog2->code, prolog2->code_size);
5344 ptr += prolog2->code_size;
5345 }
5346
5347 memcpy(ptr, mainb->code, mainb->code_size);
5348 ptr += mainb->code_size;
5349
5350 if (epilog)
5351 memcpy(ptr, epilog->code, epilog->code_size);
5352 else if (mainb->rodata_size > 0)
5353 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5354
5355 sscreen->ws->buffer_unmap(shader->bo->buf);
5356 return 0;
5357 }
5358
5359 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5360 struct pipe_debug_callback *debug,
5361 const char *name, FILE *file)
5362 {
5363 char *line, *p;
5364 unsigned i, count;
5365
5366 if (binary->disasm_string) {
5367 fprintf(file, "Shader %s disassembly:\n", name);
5368 fprintf(file, "%s", binary->disasm_string);
5369
5370 if (debug && debug->debug_message) {
5371 /* Very long debug messages are cut off, so send the
5372 * disassembly one line at a time. This causes more
5373 * overhead, but on the plus side it simplifies
5374 * parsing of resulting logs.
5375 */
5376 pipe_debug_message(debug, SHADER_INFO,
5377 "Shader Disassembly Begin");
5378
5379 line = binary->disasm_string;
5380 while (*line) {
5381 p = util_strchrnul(line, '\n');
5382 count = p - line;
5383
5384 if (count) {
5385 pipe_debug_message(debug, SHADER_INFO,
5386 "%.*s", count, line);
5387 }
5388
5389 if (!*p)
5390 break;
5391 line = p + 1;
5392 }
5393
5394 pipe_debug_message(debug, SHADER_INFO,
5395 "Shader Disassembly End");
5396 }
5397 } else {
5398 fprintf(file, "Shader %s binary:\n", name);
5399 for (i = 0; i < binary->code_size; i += 4) {
5400 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5401 binary->code[i + 3], binary->code[i + 2],
5402 binary->code[i + 1], binary->code[i]);
5403 }
5404 }
5405 }
5406
5407 static void si_calculate_max_simd_waves(struct si_shader *shader)
5408 {
5409 struct si_screen *sscreen = shader->selector->screen;
5410 struct si_shader_config *conf = &shader->config;
5411 unsigned num_inputs = shader->selector->info.num_inputs;
5412 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5413 unsigned lds_per_wave = 0;
5414 unsigned max_simd_waves;
5415
5416 switch (sscreen->info.family) {
5417 /* These always have 8 waves: */
5418 case CHIP_POLARIS10:
5419 case CHIP_POLARIS11:
5420 case CHIP_POLARIS12:
5421 max_simd_waves = 8;
5422 break;
5423 default:
5424 max_simd_waves = 10;
5425 }
5426
5427 /* Compute LDS usage for PS. */
5428 switch (shader->selector->type) {
5429 case PIPE_SHADER_FRAGMENT:
5430 /* The minimum usage per wave is (num_inputs * 48). The maximum
5431 * usage is (num_inputs * 48 * 16).
5432 * We can get anything in between and it varies between waves.
5433 *
5434 * The 48 bytes per input for a single primitive is equal to
5435 * 4 bytes/component * 4 components/input * 3 points.
5436 *
5437 * Other stages don't know the size at compile time or don't
5438 * allocate LDS per wave, but instead they do it per thread group.
5439 */
5440 lds_per_wave = conf->lds_size * lds_increment +
5441 align(num_inputs * 48, lds_increment);
5442 break;
5443 case PIPE_SHADER_COMPUTE:
5444 if (shader->selector) {
5445 unsigned max_workgroup_size =
5446 si_get_max_workgroup_size(shader);
5447 lds_per_wave = (conf->lds_size * lds_increment) /
5448 DIV_ROUND_UP(max_workgroup_size, 64);
5449 }
5450 break;
5451 }
5452
5453 /* Compute the per-SIMD wave counts. */
5454 if (conf->num_sgprs) {
5455 if (sscreen->info.chip_class >= VI)
5456 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5457 else
5458 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5459 }
5460
5461 if (conf->num_vgprs)
5462 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5463
5464 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5465 * 16KB makes some SIMDs unoccupied). */
5466 if (lds_per_wave)
5467 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5468
5469 conf->max_simd_waves = max_simd_waves;
5470 }
5471
5472 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5473 struct pipe_debug_callback *debug)
5474 {
5475 const struct si_shader_config *conf = &shader->config;
5476
5477 pipe_debug_message(debug, SHADER_INFO,
5478 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5479 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5480 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5481 conf->num_sgprs, conf->num_vgprs,
5482 si_get_shader_binary_size(shader),
5483 conf->lds_size, conf->scratch_bytes_per_wave,
5484 conf->max_simd_waves, conf->spilled_sgprs,
5485 conf->spilled_vgprs, conf->private_mem_vgprs);
5486 }
5487
5488 static void si_shader_dump_stats(struct si_screen *sscreen,
5489 const struct si_shader *shader,
5490 unsigned processor,
5491 FILE *file,
5492 bool check_debug_option)
5493 {
5494 const struct si_shader_config *conf = &shader->config;
5495
5496 if (!check_debug_option ||
5497 si_can_dump_shader(sscreen, processor)) {
5498 if (processor == PIPE_SHADER_FRAGMENT) {
5499 fprintf(file, "*** SHADER CONFIG ***\n"
5500 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5501 "SPI_PS_INPUT_ENA = 0x%04x\n",
5502 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5503 }
5504
5505 fprintf(file, "*** SHADER STATS ***\n"
5506 "SGPRS: %d\n"
5507 "VGPRS: %d\n"
5508 "Spilled SGPRs: %d\n"
5509 "Spilled VGPRs: %d\n"
5510 "Private memory VGPRs: %d\n"
5511 "Code Size: %d bytes\n"
5512 "LDS: %d blocks\n"
5513 "Scratch: %d bytes per wave\n"
5514 "Max Waves: %d\n"
5515 "********************\n\n\n",
5516 conf->num_sgprs, conf->num_vgprs,
5517 conf->spilled_sgprs, conf->spilled_vgprs,
5518 conf->private_mem_vgprs,
5519 si_get_shader_binary_size(shader),
5520 conf->lds_size, conf->scratch_bytes_per_wave,
5521 conf->max_simd_waves);
5522 }
5523 }
5524
5525 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5526 {
5527 switch (processor) {
5528 case PIPE_SHADER_VERTEX:
5529 if (shader->key.as_es)
5530 return "Vertex Shader as ES";
5531 else if (shader->key.as_ls)
5532 return "Vertex Shader as LS";
5533 else
5534 return "Vertex Shader as VS";
5535 case PIPE_SHADER_TESS_CTRL:
5536 return "Tessellation Control Shader";
5537 case PIPE_SHADER_TESS_EVAL:
5538 if (shader->key.as_es)
5539 return "Tessellation Evaluation Shader as ES";
5540 else
5541 return "Tessellation Evaluation Shader as VS";
5542 case PIPE_SHADER_GEOMETRY:
5543 if (shader->is_gs_copy_shader)
5544 return "GS Copy Shader as VS";
5545 else
5546 return "Geometry Shader";
5547 case PIPE_SHADER_FRAGMENT:
5548 return "Pixel Shader";
5549 case PIPE_SHADER_COMPUTE:
5550 return "Compute Shader";
5551 default:
5552 return "Unknown Shader";
5553 }
5554 }
5555
5556 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5557 struct pipe_debug_callback *debug, unsigned processor,
5558 FILE *file, bool check_debug_option)
5559 {
5560 if (!check_debug_option ||
5561 si_can_dump_shader(sscreen, processor))
5562 si_dump_shader_key(processor, shader, file);
5563
5564 if (!check_debug_option && shader->binary.llvm_ir_string) {
5565 if (shader->previous_stage &&
5566 shader->previous_stage->binary.llvm_ir_string) {
5567 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5568 si_get_shader_name(shader, processor));
5569 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5570 }
5571
5572 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5573 si_get_shader_name(shader, processor));
5574 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5575 }
5576
5577 if (!check_debug_option ||
5578 (si_can_dump_shader(sscreen, processor) &&
5579 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5580 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5581
5582 if (shader->prolog)
5583 si_shader_dump_disassembly(&shader->prolog->binary,
5584 debug, "prolog", file);
5585 if (shader->previous_stage)
5586 si_shader_dump_disassembly(&shader->previous_stage->binary,
5587 debug, "previous stage", file);
5588 if (shader->prolog2)
5589 si_shader_dump_disassembly(&shader->prolog2->binary,
5590 debug, "prolog2", file);
5591
5592 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5593
5594 if (shader->epilog)
5595 si_shader_dump_disassembly(&shader->epilog->binary,
5596 debug, "epilog", file);
5597 fprintf(file, "\n");
5598 }
5599
5600 si_shader_dump_stats(sscreen, shader, processor, file,
5601 check_debug_option);
5602 }
5603
5604 static int si_compile_llvm(struct si_screen *sscreen,
5605 struct ac_shader_binary *binary,
5606 struct si_shader_config *conf,
5607 LLVMTargetMachineRef tm,
5608 LLVMModuleRef mod,
5609 struct pipe_debug_callback *debug,
5610 unsigned processor,
5611 const char *name)
5612 {
5613 int r = 0;
5614 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5615
5616 if (si_can_dump_shader(sscreen, processor)) {
5617 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5618
5619 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5620 fprintf(stderr, "%s LLVM IR:\n\n", name);
5621 ac_dump_module(mod);
5622 fprintf(stderr, "\n");
5623 }
5624 }
5625
5626 if (sscreen->record_llvm_ir) {
5627 char *ir = LLVMPrintModuleToString(mod);
5628 binary->llvm_ir_string = strdup(ir);
5629 LLVMDisposeMessage(ir);
5630 }
5631
5632 if (!si_replace_shader(count, binary)) {
5633 r = si_llvm_compile(mod, binary, tm, debug);
5634 if (r)
5635 return r;
5636 }
5637
5638 si_shader_binary_read_config(binary, conf, 0);
5639
5640 /* Enable 64-bit and 16-bit denormals, because there is no performance
5641 * cost.
5642 *
5643 * If denormals are enabled, all floating-point output modifiers are
5644 * ignored.
5645 *
5646 * Don't enable denormals for 32-bit floats, because:
5647 * - Floating-point output modifiers would be ignored by the hw.
5648 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5649 * have to stop using those.
5650 * - SI & CI would be very slow.
5651 */
5652 conf->float_mode |= V_00B028_FP_64_DENORMS;
5653
5654 FREE(binary->config);
5655 FREE(binary->global_symbol_offsets);
5656 binary->config = NULL;
5657 binary->global_symbol_offsets = NULL;
5658
5659 /* Some shaders can't have rodata because their binaries can be
5660 * concatenated.
5661 */
5662 if (binary->rodata_size &&
5663 (processor == PIPE_SHADER_VERTEX ||
5664 processor == PIPE_SHADER_TESS_CTRL ||
5665 processor == PIPE_SHADER_TESS_EVAL ||
5666 processor == PIPE_SHADER_FRAGMENT)) {
5667 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5668 return -EINVAL;
5669 }
5670
5671 return r;
5672 }
5673
5674 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5675 {
5676 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5677 LLVMBuildRetVoid(ctx->ac.builder);
5678 else
5679 LLVMBuildRet(ctx->ac.builder, ret);
5680 }
5681
5682 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5683 struct si_shader *
5684 si_generate_gs_copy_shader(struct si_screen *sscreen,
5685 LLVMTargetMachineRef tm,
5686 struct si_shader_selector *gs_selector,
5687 struct pipe_debug_callback *debug)
5688 {
5689 struct si_shader_context ctx;
5690 struct si_shader *shader;
5691 LLVMBuilderRef builder;
5692 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5693 struct lp_build_context *uint = &bld_base->uint_bld;
5694 struct si_shader_output_values *outputs;
5695 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5696 int i, r;
5697
5698 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5699
5700 if (!outputs)
5701 return NULL;
5702
5703 shader = CALLOC_STRUCT(si_shader);
5704 if (!shader) {
5705 FREE(outputs);
5706 return NULL;
5707 }
5708
5709 /* We can leave the fence as permanently signaled because the GS copy
5710 * shader only becomes visible globally after it has been compiled. */
5711 util_queue_fence_init(&shader->ready);
5712
5713 shader->selector = gs_selector;
5714 shader->is_gs_copy_shader = true;
5715
5716 si_init_shader_ctx(&ctx, sscreen, tm);
5717 ctx.shader = shader;
5718 ctx.type = PIPE_SHADER_VERTEX;
5719
5720 builder = ctx.ac.builder;
5721
5722 create_function(&ctx);
5723 preload_ring_buffers(&ctx);
5724
5725 LLVMValueRef voffset =
5726 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5727
5728 /* Fetch the vertex stream ID.*/
5729 LLVMValueRef stream_id;
5730
5731 if (gs_selector->so.num_outputs)
5732 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5733 else
5734 stream_id = ctx.i32_0;
5735
5736 /* Fill in output information. */
5737 for (i = 0; i < gsinfo->num_outputs; ++i) {
5738 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5739 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5740
5741 for (int chan = 0; chan < 4; chan++) {
5742 outputs[i].vertex_stream[chan] =
5743 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5744 }
5745 }
5746
5747 LLVMBasicBlockRef end_bb;
5748 LLVMValueRef switch_inst;
5749
5750 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5751 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5752
5753 for (int stream = 0; stream < 4; stream++) {
5754 LLVMBasicBlockRef bb;
5755 unsigned offset;
5756
5757 if (!gsinfo->num_stream_output_components[stream])
5758 continue;
5759
5760 if (stream > 0 && !gs_selector->so.num_outputs)
5761 continue;
5762
5763 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5764 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5765 LLVMPositionBuilderAtEnd(builder, bb);
5766
5767 /* Fetch vertex data from GSVS ring */
5768 offset = 0;
5769 for (i = 0; i < gsinfo->num_outputs; ++i) {
5770 for (unsigned chan = 0; chan < 4; chan++) {
5771 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5772 outputs[i].vertex_stream[chan] != stream) {
5773 outputs[i].values[chan] = ctx.bld_base.base.undef;
5774 continue;
5775 }
5776
5777 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5778 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5779 offset++;
5780
5781 outputs[i].values[chan] =
5782 ac_build_buffer_load(&ctx.ac,
5783 ctx.gsvs_ring[0], 1,
5784 ctx.i32_0, voffset,
5785 soffset, 0, 1, 1,
5786 true, false);
5787 }
5788 }
5789
5790 /* Streamout and exports. */
5791 if (gs_selector->so.num_outputs) {
5792 si_llvm_emit_streamout(&ctx, outputs,
5793 gsinfo->num_outputs,
5794 stream);
5795 }
5796
5797 if (stream == 0)
5798 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5799
5800 LLVMBuildBr(builder, end_bb);
5801 }
5802
5803 LLVMPositionBuilderAtEnd(builder, end_bb);
5804
5805 LLVMBuildRetVoid(ctx.ac.builder);
5806
5807 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5808 si_llvm_optimize_module(&ctx);
5809
5810 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5811 &ctx.shader->config, ctx.tm,
5812 ctx.gallivm.module,
5813 debug, PIPE_SHADER_GEOMETRY,
5814 "GS Copy Shader");
5815 if (!r) {
5816 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5817 fprintf(stderr, "GS Copy Shader:\n");
5818 si_shader_dump(sscreen, ctx.shader, debug,
5819 PIPE_SHADER_GEOMETRY, stderr, true);
5820 r = si_shader_binary_upload(sscreen, ctx.shader);
5821 }
5822
5823 si_llvm_dispose(&ctx);
5824
5825 FREE(outputs);
5826
5827 if (r != 0) {
5828 FREE(shader);
5829 shader = NULL;
5830 }
5831 return shader;
5832 }
5833
5834 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5835 const struct si_vs_prolog_bits *prolog,
5836 const char *prefix, FILE *f)
5837 {
5838 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5839 prefix, prolog->instance_divisor_is_one);
5840 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5841 prefix, prolog->instance_divisor_is_fetched);
5842 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5843 prefix, prolog->ls_vgpr_fix);
5844
5845 fprintf(f, " mono.vs.fix_fetch = {");
5846 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5847 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5848 fprintf(f, "}\n");
5849 }
5850
5851 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5852 FILE *f)
5853 {
5854 const struct si_shader_key *key = &shader->key;
5855
5856 fprintf(f, "SHADER KEY\n");
5857
5858 switch (processor) {
5859 case PIPE_SHADER_VERTEX:
5860 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5861 "part.vs.prolog", f);
5862 fprintf(f, " as_es = %u\n", key->as_es);
5863 fprintf(f, " as_ls = %u\n", key->as_ls);
5864 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5865 key->mono.u.vs_export_prim_id);
5866 break;
5867
5868 case PIPE_SHADER_TESS_CTRL:
5869 if (shader->selector->screen->info.chip_class >= GFX9) {
5870 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5871 "part.tcs.ls_prolog", f);
5872 }
5873 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5874 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5875 break;
5876
5877 case PIPE_SHADER_TESS_EVAL:
5878 fprintf(f, " as_es = %u\n", key->as_es);
5879 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5880 key->mono.u.vs_export_prim_id);
5881 break;
5882
5883 case PIPE_SHADER_GEOMETRY:
5884 if (shader->is_gs_copy_shader)
5885 break;
5886
5887 if (shader->selector->screen->info.chip_class >= GFX9 &&
5888 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5889 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5890 "part.gs.vs_prolog", f);
5891 }
5892 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5893 break;
5894
5895 case PIPE_SHADER_COMPUTE:
5896 break;
5897
5898 case PIPE_SHADER_FRAGMENT:
5899 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5900 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5901 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5902 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5903 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5904 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5905 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5906 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5907 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5908 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5909 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5910 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5911 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5912 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5913 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5914 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5915 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5916 break;
5917
5918 default:
5919 assert(0);
5920 }
5921
5922 if ((processor == PIPE_SHADER_GEOMETRY ||
5923 processor == PIPE_SHADER_TESS_EVAL ||
5924 processor == PIPE_SHADER_VERTEX) &&
5925 !key->as_es && !key->as_ls) {
5926 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5927 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5928 }
5929 }
5930
5931 static void si_init_shader_ctx(struct si_shader_context *ctx,
5932 struct si_screen *sscreen,
5933 LLVMTargetMachineRef tm)
5934 {
5935 struct lp_build_tgsi_context *bld_base;
5936
5937 si_llvm_context_init(ctx, sscreen, tm);
5938
5939 bld_base = &ctx->bld_base;
5940 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5941
5942 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5943 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5944 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5945
5946 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5947
5948 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5949
5950 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5951 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5952 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5953 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5954
5955 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5956 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5957 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5958 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5959 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5960 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5961 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5962 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5963 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5964
5965 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5966 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5967 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5968 }
5969
5970 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5971 {
5972 struct si_shader *shader = ctx->shader;
5973 struct tgsi_shader_info *info = &shader->selector->info;
5974
5975 if ((ctx->type != PIPE_SHADER_VERTEX &&
5976 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5977 shader->key.as_ls ||
5978 shader->key.as_es)
5979 return;
5980
5981 ac_optimize_vs_outputs(&ctx->ac,
5982 ctx->main_fn,
5983 shader->info.vs_output_param_offset,
5984 info->num_outputs,
5985 &shader->info.nr_param_exports);
5986 }
5987
5988 static void si_init_exec_from_input(struct si_shader_context *ctx,
5989 unsigned param, unsigned bitoffset)
5990 {
5991 LLVMValueRef args[] = {
5992 LLVMGetParam(ctx->main_fn, param),
5993 LLVMConstInt(ctx->i32, bitoffset, 0),
5994 };
5995 lp_build_intrinsic(ctx->ac.builder,
5996 "llvm.amdgcn.init.exec.from.input",
5997 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5998 }
5999
6000 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6001 const struct si_vs_prolog_bits *key)
6002 {
6003 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6004 * VS prolog. */
6005 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6006 }
6007
6008 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6009 bool is_monolithic)
6010 {
6011 struct si_shader *shader = ctx->shader;
6012 struct si_shader_selector *sel = shader->selector;
6013 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6014
6015 // TODO clean all this up!
6016 switch (ctx->type) {
6017 case PIPE_SHADER_VERTEX:
6018 ctx->load_input = declare_input_vs;
6019 if (shader->key.as_ls)
6020 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6021 else if (shader->key.as_es)
6022 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6023 else
6024 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6025 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6026 ctx->abi.load_base_vertex = get_base_vertex;
6027 break;
6028 case PIPE_SHADER_TESS_CTRL:
6029 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6030 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6031 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6032 bld_base->emit_store = store_output_tcs;
6033 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6034 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6035 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6036 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6037 break;
6038 case PIPE_SHADER_TESS_EVAL:
6039 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6040 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6041 ctx->abi.load_tess_coord = si_load_tess_coord;
6042 ctx->abi.load_tess_level = si_load_tess_level;
6043 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6044 if (shader->key.as_es)
6045 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6046 else
6047 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6048 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6049 break;
6050 case PIPE_SHADER_GEOMETRY:
6051 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6052 ctx->abi.load_inputs = si_nir_load_input_gs;
6053 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6054 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6055 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6056 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6057 break;
6058 case PIPE_SHADER_FRAGMENT:
6059 ctx->load_input = declare_input_fs;
6060 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6061 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6062 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6063 ctx->abi.load_sample_position = load_sample_position;
6064 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6065 break;
6066 case PIPE_SHADER_COMPUTE:
6067 ctx->abi.load_local_group_size = get_block_size;
6068 break;
6069 default:
6070 assert(!"Unsupported shader type");
6071 return false;
6072 }
6073
6074 ctx->abi.load_ubo = load_ubo;
6075 ctx->abi.load_ssbo = load_ssbo;
6076
6077 create_function(ctx);
6078 preload_ring_buffers(ctx);
6079
6080 /* For GFX9 merged shaders:
6081 * - Set EXEC for the first shader. If the prolog is present, set
6082 * EXEC there instead.
6083 * - Add a barrier before the second shader.
6084 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6085 * an if-statement. This is required for correctness in geometry
6086 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6087 * GS_CUT messages.
6088 *
6089 * For monolithic merged shaders, the first shader is wrapped in an
6090 * if-block together with its prolog in si_build_wrapper_function.
6091 */
6092 if (ctx->screen->info.chip_class >= GFX9) {
6093 if (!is_monolithic &&
6094 sel->info.num_instructions > 1 && /* not empty shader */
6095 (shader->key.as_es || shader->key.as_ls) &&
6096 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6097 (ctx->type == PIPE_SHADER_VERTEX &&
6098 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6099 si_init_exec_from_input(ctx,
6100 ctx->param_merged_wave_info, 0);
6101 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6102 ctx->type == PIPE_SHADER_GEOMETRY) {
6103 if (!is_monolithic)
6104 ac_init_exec_full_mask(&ctx->ac);
6105
6106 /* The barrier must execute for all shaders in a
6107 * threadgroup.
6108 */
6109 si_llvm_emit_barrier(NULL, bld_base, NULL);
6110
6111 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6112 LLVMValueRef ena =
6113 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6114 ac_get_thread_id(&ctx->ac), num_threads, "");
6115 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6116 }
6117 }
6118
6119 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6120 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6121 for (unsigned i = 0; i < 6; i++) {
6122 ctx->invoc0_tess_factors[i] =
6123 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6124 }
6125 }
6126
6127 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6128 int i;
6129 for (i = 0; i < 4; i++) {
6130 ctx->gs_next_vertex[i] =
6131 lp_build_alloca(&ctx->gallivm,
6132 ctx->i32, "");
6133 }
6134 }
6135
6136 if (sel->force_correct_derivs_after_kill) {
6137 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6138 /* true = don't kill. */
6139 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6140 ctx->postponed_kill);
6141 }
6142
6143 if (sel->tokens) {
6144 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6145 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6146 return false;
6147 }
6148 } else {
6149 if (!si_nir_build_llvm(ctx, sel->nir)) {
6150 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6151 return false;
6152 }
6153 }
6154
6155 si_llvm_build_ret(ctx, ctx->return_value);
6156 return true;
6157 }
6158
6159 /**
6160 * Compute the VS prolog key, which contains all the information needed to
6161 * build the VS prolog function, and set shader->info bits where needed.
6162 *
6163 * \param info Shader info of the vertex shader.
6164 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6165 * \param prolog_key Key of the VS prolog
6166 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6167 * \param key Output shader part key.
6168 */
6169 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6170 unsigned num_input_sgprs,
6171 const struct si_vs_prolog_bits *prolog_key,
6172 struct si_shader *shader_out,
6173 union si_shader_part_key *key)
6174 {
6175 memset(key, 0, sizeof(*key));
6176 key->vs_prolog.states = *prolog_key;
6177 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6178 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6179 key->vs_prolog.as_ls = shader_out->key.as_ls;
6180 key->vs_prolog.as_es = shader_out->key.as_es;
6181
6182 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6183 key->vs_prolog.as_ls = 1;
6184 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6185 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6186 key->vs_prolog.as_es = 1;
6187 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6188 }
6189
6190 /* Enable loading the InstanceID VGPR. */
6191 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6192
6193 if ((key->vs_prolog.states.instance_divisor_is_one |
6194 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6195 shader_out->info.uses_instanceid = true;
6196 }
6197
6198 /**
6199 * Compute the PS prolog key, which contains all the information needed to
6200 * build the PS prolog function, and set related bits in shader->config.
6201 */
6202 static void si_get_ps_prolog_key(struct si_shader *shader,
6203 union si_shader_part_key *key,
6204 bool separate_prolog)
6205 {
6206 struct tgsi_shader_info *info = &shader->selector->info;
6207
6208 memset(key, 0, sizeof(*key));
6209 key->ps_prolog.states = shader->key.part.ps.prolog;
6210 key->ps_prolog.colors_read = info->colors_read;
6211 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6212 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6213 key->ps_prolog.wqm = info->uses_derivatives &&
6214 (key->ps_prolog.colors_read ||
6215 key->ps_prolog.states.force_persp_sample_interp ||
6216 key->ps_prolog.states.force_linear_sample_interp ||
6217 key->ps_prolog.states.force_persp_center_interp ||
6218 key->ps_prolog.states.force_linear_center_interp ||
6219 key->ps_prolog.states.bc_optimize_for_persp ||
6220 key->ps_prolog.states.bc_optimize_for_linear);
6221 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6222
6223 if (info->colors_read) {
6224 unsigned *color = shader->selector->color_attr_index;
6225
6226 if (shader->key.part.ps.prolog.color_two_side) {
6227 /* BCOLORs are stored after the last input. */
6228 key->ps_prolog.num_interp_inputs = info->num_inputs;
6229 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6230 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6231 }
6232
6233 for (unsigned i = 0; i < 2; i++) {
6234 unsigned interp = info->input_interpolate[color[i]];
6235 unsigned location = info->input_interpolate_loc[color[i]];
6236
6237 if (!(info->colors_read & (0xf << i*4)))
6238 continue;
6239
6240 key->ps_prolog.color_attr_index[i] = color[i];
6241
6242 if (shader->key.part.ps.prolog.flatshade_colors &&
6243 interp == TGSI_INTERPOLATE_COLOR)
6244 interp = TGSI_INTERPOLATE_CONSTANT;
6245
6246 switch (interp) {
6247 case TGSI_INTERPOLATE_CONSTANT:
6248 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6249 break;
6250 case TGSI_INTERPOLATE_PERSPECTIVE:
6251 case TGSI_INTERPOLATE_COLOR:
6252 /* Force the interpolation location for colors here. */
6253 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6254 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6255 if (shader->key.part.ps.prolog.force_persp_center_interp)
6256 location = TGSI_INTERPOLATE_LOC_CENTER;
6257
6258 switch (location) {
6259 case TGSI_INTERPOLATE_LOC_SAMPLE:
6260 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6261 shader->config.spi_ps_input_ena |=
6262 S_0286CC_PERSP_SAMPLE_ENA(1);
6263 break;
6264 case TGSI_INTERPOLATE_LOC_CENTER:
6265 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6266 shader->config.spi_ps_input_ena |=
6267 S_0286CC_PERSP_CENTER_ENA(1);
6268 break;
6269 case TGSI_INTERPOLATE_LOC_CENTROID:
6270 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6271 shader->config.spi_ps_input_ena |=
6272 S_0286CC_PERSP_CENTROID_ENA(1);
6273 break;
6274 default:
6275 assert(0);
6276 }
6277 break;
6278 case TGSI_INTERPOLATE_LINEAR:
6279 /* Force the interpolation location for colors here. */
6280 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6281 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6282 if (shader->key.part.ps.prolog.force_linear_center_interp)
6283 location = TGSI_INTERPOLATE_LOC_CENTER;
6284
6285 /* The VGPR assignment for non-monolithic shaders
6286 * works because InitialPSInputAddr is set on the
6287 * main shader and PERSP_PULL_MODEL is never used.
6288 */
6289 switch (location) {
6290 case TGSI_INTERPOLATE_LOC_SAMPLE:
6291 key->ps_prolog.color_interp_vgpr_index[i] =
6292 separate_prolog ? 6 : 9;
6293 shader->config.spi_ps_input_ena |=
6294 S_0286CC_LINEAR_SAMPLE_ENA(1);
6295 break;
6296 case TGSI_INTERPOLATE_LOC_CENTER:
6297 key->ps_prolog.color_interp_vgpr_index[i] =
6298 separate_prolog ? 8 : 11;
6299 shader->config.spi_ps_input_ena |=
6300 S_0286CC_LINEAR_CENTER_ENA(1);
6301 break;
6302 case TGSI_INTERPOLATE_LOC_CENTROID:
6303 key->ps_prolog.color_interp_vgpr_index[i] =
6304 separate_prolog ? 10 : 13;
6305 shader->config.spi_ps_input_ena |=
6306 S_0286CC_LINEAR_CENTROID_ENA(1);
6307 break;
6308 default:
6309 assert(0);
6310 }
6311 break;
6312 default:
6313 assert(0);
6314 }
6315 }
6316 }
6317 }
6318
6319 /**
6320 * Check whether a PS prolog is required based on the key.
6321 */
6322 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6323 {
6324 return key->ps_prolog.colors_read ||
6325 key->ps_prolog.states.force_persp_sample_interp ||
6326 key->ps_prolog.states.force_linear_sample_interp ||
6327 key->ps_prolog.states.force_persp_center_interp ||
6328 key->ps_prolog.states.force_linear_center_interp ||
6329 key->ps_prolog.states.bc_optimize_for_persp ||
6330 key->ps_prolog.states.bc_optimize_for_linear ||
6331 key->ps_prolog.states.poly_stipple ||
6332 key->ps_prolog.states.samplemask_log_ps_iter;
6333 }
6334
6335 /**
6336 * Compute the PS epilog key, which contains all the information needed to
6337 * build the PS epilog function.
6338 */
6339 static void si_get_ps_epilog_key(struct si_shader *shader,
6340 union si_shader_part_key *key)
6341 {
6342 struct tgsi_shader_info *info = &shader->selector->info;
6343 memset(key, 0, sizeof(*key));
6344 key->ps_epilog.colors_written = info->colors_written;
6345 key->ps_epilog.writes_z = info->writes_z;
6346 key->ps_epilog.writes_stencil = info->writes_stencil;
6347 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6348 key->ps_epilog.states = shader->key.part.ps.epilog;
6349 }
6350
6351 /**
6352 * Build the GS prolog function. Rotate the input vertices for triangle strips
6353 * with adjacency.
6354 */
6355 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6356 union si_shader_part_key *key)
6357 {
6358 unsigned num_sgprs, num_vgprs;
6359 struct si_function_info fninfo;
6360 LLVMBuilderRef builder = ctx->ac.builder;
6361 LLVMTypeRef returns[48];
6362 LLVMValueRef func, ret;
6363
6364 si_init_function_info(&fninfo);
6365
6366 if (ctx->screen->info.chip_class >= GFX9) {
6367 if (key->gs_prolog.states.gfx9_prev_is_vs)
6368 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6369 else
6370 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6371 num_vgprs = 5; /* ES inputs are not needed by GS */
6372 } else {
6373 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6374 num_vgprs = 8;
6375 }
6376
6377 for (unsigned i = 0; i < num_sgprs; ++i) {
6378 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6379 returns[i] = ctx->i32;
6380 }
6381
6382 for (unsigned i = 0; i < num_vgprs; ++i) {
6383 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6384 returns[num_sgprs + i] = ctx->f32;
6385 }
6386
6387 /* Create the function. */
6388 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6389 &fninfo, 0);
6390 func = ctx->main_fn;
6391
6392 /* Set the full EXEC mask for the prolog, because we are only fiddling
6393 * with registers here. The main shader part will set the correct EXEC
6394 * mask.
6395 */
6396 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6397 ac_init_exec_full_mask(&ctx->ac);
6398
6399 /* Copy inputs to outputs. This should be no-op, as the registers match,
6400 * but it will prevent the compiler from overwriting them unintentionally.
6401 */
6402 ret = ctx->return_value;
6403 for (unsigned i = 0; i < num_sgprs; i++) {
6404 LLVMValueRef p = LLVMGetParam(func, i);
6405 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6406 }
6407 for (unsigned i = 0; i < num_vgprs; i++) {
6408 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6409 p = ac_to_float(&ctx->ac, p);
6410 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6411 }
6412
6413 if (key->gs_prolog.states.tri_strip_adj_fix) {
6414 /* Remap the input vertices for every other primitive. */
6415 const unsigned gfx6_vtx_params[6] = {
6416 num_sgprs,
6417 num_sgprs + 1,
6418 num_sgprs + 3,
6419 num_sgprs + 4,
6420 num_sgprs + 5,
6421 num_sgprs + 6
6422 };
6423 const unsigned gfx9_vtx_params[3] = {
6424 num_sgprs,
6425 num_sgprs + 1,
6426 num_sgprs + 4,
6427 };
6428 LLVMValueRef vtx_in[6], vtx_out[6];
6429 LLVMValueRef prim_id, rotate;
6430
6431 if (ctx->screen->info.chip_class >= GFX9) {
6432 for (unsigned i = 0; i < 3; i++) {
6433 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6434 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6435 }
6436 } else {
6437 for (unsigned i = 0; i < 6; i++)
6438 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6439 }
6440
6441 prim_id = LLVMGetParam(func, num_sgprs + 2);
6442 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6443
6444 for (unsigned i = 0; i < 6; ++i) {
6445 LLVMValueRef base, rotated;
6446 base = vtx_in[i];
6447 rotated = vtx_in[(i + 4) % 6];
6448 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6449 }
6450
6451 if (ctx->screen->info.chip_class >= GFX9) {
6452 for (unsigned i = 0; i < 3; i++) {
6453 LLVMValueRef hi, out;
6454
6455 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6456 LLVMConstInt(ctx->i32, 16, 0), "");
6457 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6458 out = ac_to_float(&ctx->ac, out);
6459 ret = LLVMBuildInsertValue(builder, ret, out,
6460 gfx9_vtx_params[i], "");
6461 }
6462 } else {
6463 for (unsigned i = 0; i < 6; i++) {
6464 LLVMValueRef out;
6465
6466 out = ac_to_float(&ctx->ac, vtx_out[i]);
6467 ret = LLVMBuildInsertValue(builder, ret, out,
6468 gfx6_vtx_params[i], "");
6469 }
6470 }
6471 }
6472
6473 LLVMBuildRet(builder, ret);
6474 }
6475
6476 /**
6477 * Given a list of shader part functions, build a wrapper function that
6478 * runs them in sequence to form a monolithic shader.
6479 */
6480 static void si_build_wrapper_function(struct si_shader_context *ctx,
6481 LLVMValueRef *parts,
6482 unsigned num_parts,
6483 unsigned main_part,
6484 unsigned next_shader_first_part)
6485 {
6486 LLVMBuilderRef builder = ctx->ac.builder;
6487 /* PS epilog has one arg per color component; gfx9 merged shader
6488 * prologs need to forward 32 user SGPRs.
6489 */
6490 struct si_function_info fninfo;
6491 LLVMValueRef initial[64], out[64];
6492 LLVMTypeRef function_type;
6493 unsigned num_first_params;
6494 unsigned num_out, initial_num_out;
6495 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6496 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6497 unsigned num_sgprs, num_vgprs;
6498 unsigned gprs;
6499 struct lp_build_if_state if_state;
6500
6501 si_init_function_info(&fninfo);
6502
6503 for (unsigned i = 0; i < num_parts; ++i) {
6504 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6505 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6506 }
6507
6508 /* The parameters of the wrapper function correspond to those of the
6509 * first part in terms of SGPRs and VGPRs, but we use the types of the
6510 * main part to get the right types. This is relevant for the
6511 * dereferenceable attribute on descriptor table pointers.
6512 */
6513 num_sgprs = 0;
6514 num_vgprs = 0;
6515
6516 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6517 num_first_params = LLVMCountParamTypes(function_type);
6518
6519 for (unsigned i = 0; i < num_first_params; ++i) {
6520 LLVMValueRef param = LLVMGetParam(parts[0], i);
6521
6522 if (ac_is_sgpr_param(param)) {
6523 assert(num_vgprs == 0);
6524 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6525 } else {
6526 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6527 }
6528 }
6529
6530 gprs = 0;
6531 while (gprs < num_sgprs + num_vgprs) {
6532 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6533 LLVMTypeRef type = LLVMTypeOf(param);
6534 unsigned size = ac_get_type_size(type) / 4;
6535
6536 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6537
6538 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6539 assert(gprs + size <= num_sgprs + num_vgprs &&
6540 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6541
6542 gprs += size;
6543 }
6544
6545 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6546 si_get_max_workgroup_size(ctx->shader));
6547
6548 if (is_merged_shader(ctx->shader))
6549 ac_init_exec_full_mask(&ctx->ac);
6550
6551 /* Record the arguments of the function as if they were an output of
6552 * a previous part.
6553 */
6554 num_out = 0;
6555 num_out_sgpr = 0;
6556
6557 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6558 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6559 LLVMTypeRef param_type = LLVMTypeOf(param);
6560 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6561 unsigned size = ac_get_type_size(param_type) / 4;
6562
6563 if (size == 1) {
6564 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6565 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6566 param_type = ctx->i32;
6567 }
6568
6569 if (param_type != out_type)
6570 param = LLVMBuildBitCast(builder, param, out_type, "");
6571 out[num_out++] = param;
6572 } else {
6573 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6574
6575 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6576 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6577 param_type = ctx->i64;
6578 }
6579
6580 if (param_type != vector_type)
6581 param = LLVMBuildBitCast(builder, param, vector_type, "");
6582
6583 for (unsigned j = 0; j < size; ++j)
6584 out[num_out++] = LLVMBuildExtractElement(
6585 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6586 }
6587
6588 if (i < fninfo.num_sgpr_params)
6589 num_out_sgpr = num_out;
6590 }
6591
6592 memcpy(initial, out, sizeof(out));
6593 initial_num_out = num_out;
6594 initial_num_out_sgpr = num_out_sgpr;
6595
6596 /* Now chain the parts. */
6597 for (unsigned part = 0; part < num_parts; ++part) {
6598 LLVMValueRef in[48];
6599 LLVMValueRef ret;
6600 LLVMTypeRef ret_type;
6601 unsigned out_idx = 0;
6602 unsigned num_params = LLVMCountParams(parts[part]);
6603
6604 /* Merged shaders are executed conditionally depending
6605 * on the number of enabled threads passed in the input SGPRs. */
6606 if (is_merged_shader(ctx->shader) && part == 0) {
6607 LLVMValueRef ena, count = initial[3];
6608
6609 count = LLVMBuildAnd(builder, count,
6610 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6611 ena = LLVMBuildICmp(builder, LLVMIntULT,
6612 ac_get_thread_id(&ctx->ac), count, "");
6613 lp_build_if(&if_state, &ctx->gallivm, ena);
6614 }
6615
6616 /* Derive arguments for the next part from outputs of the
6617 * previous one.
6618 */
6619 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6620 LLVMValueRef param;
6621 LLVMTypeRef param_type;
6622 bool is_sgpr;
6623 unsigned param_size;
6624 LLVMValueRef arg = NULL;
6625
6626 param = LLVMGetParam(parts[part], param_idx);
6627 param_type = LLVMTypeOf(param);
6628 param_size = ac_get_type_size(param_type) / 4;
6629 is_sgpr = ac_is_sgpr_param(param);
6630
6631 if (is_sgpr)
6632 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6633 else if (out_idx < num_out_sgpr) {
6634 /* Skip returned SGPRs the current part doesn't
6635 * declare on the input. */
6636 out_idx = num_out_sgpr;
6637 }
6638
6639 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6640
6641 if (param_size == 1)
6642 arg = out[out_idx];
6643 else
6644 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6645
6646 if (LLVMTypeOf(arg) != param_type) {
6647 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6648 if (LLVMGetPointerAddressSpace(param_type) ==
6649 AC_CONST_32BIT_ADDR_SPACE) {
6650 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6651 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6652 } else {
6653 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6654 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6655 }
6656 } else {
6657 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6658 }
6659 }
6660
6661 in[param_idx] = arg;
6662 out_idx += param_size;
6663 }
6664
6665 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6666
6667 if (is_merged_shader(ctx->shader) &&
6668 part + 1 == next_shader_first_part) {
6669 lp_build_endif(&if_state);
6670
6671 /* The second half of the merged shader should use
6672 * the inputs from the toplevel (wrapper) function,
6673 * not the return value from the last call.
6674 *
6675 * That's because the last call was executed condi-
6676 * tionally, so we can't consume it in the main
6677 * block.
6678 */
6679 memcpy(out, initial, sizeof(initial));
6680 num_out = initial_num_out;
6681 num_out_sgpr = initial_num_out_sgpr;
6682 continue;
6683 }
6684
6685 /* Extract the returned GPRs. */
6686 ret_type = LLVMTypeOf(ret);
6687 num_out = 0;
6688 num_out_sgpr = 0;
6689
6690 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6691 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6692
6693 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6694
6695 for (unsigned i = 0; i < ret_size; ++i) {
6696 LLVMValueRef val =
6697 LLVMBuildExtractValue(builder, ret, i, "");
6698
6699 assert(num_out < ARRAY_SIZE(out));
6700 out[num_out++] = val;
6701
6702 if (LLVMTypeOf(val) == ctx->i32) {
6703 assert(num_out_sgpr + 1 == num_out);
6704 num_out_sgpr = num_out;
6705 }
6706 }
6707 }
6708 }
6709
6710 LLVMBuildRetVoid(builder);
6711 }
6712
6713 int si_compile_tgsi_shader(struct si_screen *sscreen,
6714 LLVMTargetMachineRef tm,
6715 struct si_shader *shader,
6716 bool is_monolithic,
6717 struct pipe_debug_callback *debug)
6718 {
6719 struct si_shader_selector *sel = shader->selector;
6720 struct si_shader_context ctx;
6721 int r = -1;
6722
6723 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6724 * conversion fails. */
6725 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6726 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6727 if (sel->tokens)
6728 tgsi_dump(sel->tokens, 0);
6729 else
6730 nir_print_shader(sel->nir, stderr);
6731 si_dump_streamout(&sel->so);
6732 }
6733
6734 si_init_shader_ctx(&ctx, sscreen, tm);
6735 si_llvm_context_set_tgsi(&ctx, shader);
6736 ctx.separate_prolog = !is_monolithic;
6737
6738 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6739 sizeof(shader->info.vs_output_param_offset));
6740
6741 shader->info.uses_instanceid = sel->info.uses_instanceid;
6742
6743 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6744 si_llvm_dispose(&ctx);
6745 return -1;
6746 }
6747
6748 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6749 LLVMValueRef parts[2];
6750 bool need_prolog = sel->vs_needs_prolog;
6751
6752 parts[1] = ctx.main_fn;
6753
6754 if (need_prolog) {
6755 union si_shader_part_key prolog_key;
6756 si_get_vs_prolog_key(&sel->info,
6757 shader->info.num_input_sgprs,
6758 &shader->key.part.vs.prolog,
6759 shader, &prolog_key);
6760 si_build_vs_prolog_function(&ctx, &prolog_key);
6761 parts[0] = ctx.main_fn;
6762 }
6763
6764 si_build_wrapper_function(&ctx, parts + !need_prolog,
6765 1 + need_prolog, need_prolog, 0);
6766 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6767 if (sscreen->info.chip_class >= GFX9) {
6768 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6769 LLVMValueRef parts[4];
6770 bool vs_needs_prolog =
6771 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6772
6773 /* TCS main part */
6774 parts[2] = ctx.main_fn;
6775
6776 /* TCS epilog */
6777 union si_shader_part_key tcs_epilog_key;
6778 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6779 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6780 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6781 parts[3] = ctx.main_fn;
6782
6783 /* VS as LS main part */
6784 struct si_shader shader_ls = {};
6785 shader_ls.selector = ls;
6786 shader_ls.key.as_ls = 1;
6787 shader_ls.key.mono = shader->key.mono;
6788 shader_ls.key.opt = shader->key.opt;
6789 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6790
6791 if (!si_compile_tgsi_main(&ctx, true)) {
6792 si_llvm_dispose(&ctx);
6793 return -1;
6794 }
6795 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6796 parts[1] = ctx.main_fn;
6797
6798 /* LS prolog */
6799 if (vs_needs_prolog) {
6800 union si_shader_part_key vs_prolog_key;
6801 si_get_vs_prolog_key(&ls->info,
6802 shader_ls.info.num_input_sgprs,
6803 &shader->key.part.tcs.ls_prolog,
6804 shader, &vs_prolog_key);
6805 vs_prolog_key.vs_prolog.is_monolithic = true;
6806 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6807 parts[0] = ctx.main_fn;
6808 }
6809
6810 /* Reset the shader context. */
6811 ctx.shader = shader;
6812 ctx.type = PIPE_SHADER_TESS_CTRL;
6813
6814 si_build_wrapper_function(&ctx,
6815 parts + !vs_needs_prolog,
6816 4 - !vs_needs_prolog, 0,
6817 vs_needs_prolog ? 2 : 1);
6818 } else {
6819 LLVMValueRef parts[2];
6820 union si_shader_part_key epilog_key;
6821
6822 parts[0] = ctx.main_fn;
6823
6824 memset(&epilog_key, 0, sizeof(epilog_key));
6825 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6826 si_build_tcs_epilog_function(&ctx, &epilog_key);
6827 parts[1] = ctx.main_fn;
6828
6829 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6830 }
6831 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6832 if (ctx.screen->info.chip_class >= GFX9) {
6833 struct si_shader_selector *es = shader->key.part.gs.es;
6834 LLVMValueRef es_prolog = NULL;
6835 LLVMValueRef es_main = NULL;
6836 LLVMValueRef gs_prolog = NULL;
6837 LLVMValueRef gs_main = ctx.main_fn;
6838
6839 /* GS prolog */
6840 union si_shader_part_key gs_prolog_key;
6841 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6842 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6843 gs_prolog_key.gs_prolog.is_monolithic = true;
6844 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6845 gs_prolog = ctx.main_fn;
6846
6847 /* ES main part */
6848 struct si_shader shader_es = {};
6849 shader_es.selector = es;
6850 shader_es.key.as_es = 1;
6851 shader_es.key.mono = shader->key.mono;
6852 shader_es.key.opt = shader->key.opt;
6853 si_llvm_context_set_tgsi(&ctx, &shader_es);
6854
6855 if (!si_compile_tgsi_main(&ctx, true)) {
6856 si_llvm_dispose(&ctx);
6857 return -1;
6858 }
6859 shader->info.uses_instanceid |= es->info.uses_instanceid;
6860 es_main = ctx.main_fn;
6861
6862 /* ES prolog */
6863 if (es->vs_needs_prolog) {
6864 union si_shader_part_key vs_prolog_key;
6865 si_get_vs_prolog_key(&es->info,
6866 shader_es.info.num_input_sgprs,
6867 &shader->key.part.gs.vs_prolog,
6868 shader, &vs_prolog_key);
6869 vs_prolog_key.vs_prolog.is_monolithic = true;
6870 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6871 es_prolog = ctx.main_fn;
6872 }
6873
6874 /* Reset the shader context. */
6875 ctx.shader = shader;
6876 ctx.type = PIPE_SHADER_GEOMETRY;
6877
6878 /* Prepare the array of shader parts. */
6879 LLVMValueRef parts[4];
6880 unsigned num_parts = 0, main_part, next_first_part;
6881
6882 if (es_prolog)
6883 parts[num_parts++] = es_prolog;
6884
6885 parts[main_part = num_parts++] = es_main;
6886 parts[next_first_part = num_parts++] = gs_prolog;
6887 parts[num_parts++] = gs_main;
6888
6889 si_build_wrapper_function(&ctx, parts, num_parts,
6890 main_part, next_first_part);
6891 } else {
6892 LLVMValueRef parts[2];
6893 union si_shader_part_key prolog_key;
6894
6895 parts[1] = ctx.main_fn;
6896
6897 memset(&prolog_key, 0, sizeof(prolog_key));
6898 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6899 si_build_gs_prolog_function(&ctx, &prolog_key);
6900 parts[0] = ctx.main_fn;
6901
6902 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6903 }
6904 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6905 LLVMValueRef parts[3];
6906 union si_shader_part_key prolog_key;
6907 union si_shader_part_key epilog_key;
6908 bool need_prolog;
6909
6910 si_get_ps_prolog_key(shader, &prolog_key, false);
6911 need_prolog = si_need_ps_prolog(&prolog_key);
6912
6913 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6914
6915 if (need_prolog) {
6916 si_build_ps_prolog_function(&ctx, &prolog_key);
6917 parts[0] = ctx.main_fn;
6918 }
6919
6920 si_get_ps_epilog_key(shader, &epilog_key);
6921 si_build_ps_epilog_function(&ctx, &epilog_key);
6922 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6923
6924 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6925 need_prolog ? 1 : 0, 0);
6926 }
6927
6928 si_llvm_optimize_module(&ctx);
6929
6930 /* Post-optimization transformations and analysis. */
6931 si_optimize_vs_outputs(&ctx);
6932
6933 if ((debug && debug->debug_message) ||
6934 si_can_dump_shader(sscreen, ctx.type)) {
6935 ctx.shader->config.private_mem_vgprs =
6936 ac_count_scratch_private_memory(ctx.main_fn);
6937 }
6938
6939 /* Compile to bytecode. */
6940 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6941 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6942 si_llvm_dispose(&ctx);
6943 if (r) {
6944 fprintf(stderr, "LLVM failed to compile shader\n");
6945 return r;
6946 }
6947
6948 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6949 * LLVM 3.9svn has this bug.
6950 */
6951 if (sel->type == PIPE_SHADER_COMPUTE) {
6952 unsigned wave_size = 64;
6953 unsigned max_vgprs = 256;
6954 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6955 unsigned max_sgprs_per_wave = 128;
6956 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6957 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6958 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6959
6960 max_vgprs = max_vgprs / min_waves_per_simd;
6961 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6962
6963 if (shader->config.num_sgprs > max_sgprs ||
6964 shader->config.num_vgprs > max_vgprs) {
6965 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6966 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6967 shader->config.num_sgprs, shader->config.num_vgprs,
6968 max_sgprs, max_vgprs);
6969
6970 /* Just terminate the process, because dependent
6971 * shaders can hang due to bad input data, but use
6972 * the env var to allow shader-db to work.
6973 */
6974 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6975 abort();
6976 }
6977 }
6978
6979 /* Add the scratch offset to input SGPRs. */
6980 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6981 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6982
6983 /* Calculate the number of fragment input VGPRs. */
6984 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6985 shader->info.num_input_vgprs = 0;
6986 shader->info.face_vgpr_index = -1;
6987 shader->info.ancillary_vgpr_index = -1;
6988
6989 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6990 shader->info.num_input_vgprs += 2;
6991 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6992 shader->info.num_input_vgprs += 2;
6993 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6994 shader->info.num_input_vgprs += 2;
6995 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6996 shader->info.num_input_vgprs += 3;
6997 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6998 shader->info.num_input_vgprs += 2;
6999 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7000 shader->info.num_input_vgprs += 2;
7001 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7002 shader->info.num_input_vgprs += 2;
7003 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7004 shader->info.num_input_vgprs += 1;
7005 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7006 shader->info.num_input_vgprs += 1;
7007 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7008 shader->info.num_input_vgprs += 1;
7009 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7010 shader->info.num_input_vgprs += 1;
7011 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7012 shader->info.num_input_vgprs += 1;
7013 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7014 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7015 shader->info.num_input_vgprs += 1;
7016 }
7017 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7018 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7019 shader->info.num_input_vgprs += 1;
7020 }
7021 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7022 shader->info.num_input_vgprs += 1;
7023 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7024 shader->info.num_input_vgprs += 1;
7025 }
7026
7027 si_calculate_max_simd_waves(shader);
7028 si_shader_dump_stats_for_shader_db(shader, debug);
7029 return 0;
7030 }
7031
7032 /**
7033 * Create, compile and return a shader part (prolog or epilog).
7034 *
7035 * \param sscreen screen
7036 * \param list list of shader parts of the same category
7037 * \param type shader type
7038 * \param key shader part key
7039 * \param prolog whether the part being requested is a prolog
7040 * \param tm LLVM target machine
7041 * \param debug debug callback
7042 * \param build the callback responsible for building the main function
7043 * \return non-NULL on success
7044 */
7045 static struct si_shader_part *
7046 si_get_shader_part(struct si_screen *sscreen,
7047 struct si_shader_part **list,
7048 enum pipe_shader_type type,
7049 bool prolog,
7050 union si_shader_part_key *key,
7051 LLVMTargetMachineRef tm,
7052 struct pipe_debug_callback *debug,
7053 void (*build)(struct si_shader_context *,
7054 union si_shader_part_key *),
7055 const char *name)
7056 {
7057 struct si_shader_part *result;
7058
7059 mtx_lock(&sscreen->shader_parts_mutex);
7060
7061 /* Find existing. */
7062 for (result = *list; result; result = result->next) {
7063 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7064 mtx_unlock(&sscreen->shader_parts_mutex);
7065 return result;
7066 }
7067 }
7068
7069 /* Compile a new one. */
7070 result = CALLOC_STRUCT(si_shader_part);
7071 result->key = *key;
7072
7073 struct si_shader shader = {};
7074 struct si_shader_context ctx;
7075
7076 si_init_shader_ctx(&ctx, sscreen, tm);
7077 ctx.shader = &shader;
7078 ctx.type = type;
7079
7080 switch (type) {
7081 case PIPE_SHADER_VERTEX:
7082 shader.key.as_ls = key->vs_prolog.as_ls;
7083 shader.key.as_es = key->vs_prolog.as_es;
7084 break;
7085 case PIPE_SHADER_TESS_CTRL:
7086 assert(!prolog);
7087 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7088 break;
7089 case PIPE_SHADER_GEOMETRY:
7090 assert(prolog);
7091 break;
7092 case PIPE_SHADER_FRAGMENT:
7093 if (prolog)
7094 shader.key.part.ps.prolog = key->ps_prolog.states;
7095 else
7096 shader.key.part.ps.epilog = key->ps_epilog.states;
7097 break;
7098 default:
7099 unreachable("bad shader part");
7100 }
7101
7102 build(&ctx, key);
7103
7104 /* Compile. */
7105 si_llvm_optimize_module(&ctx);
7106
7107 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7108 ctx.ac.module, debug, ctx.type, name)) {
7109 FREE(result);
7110 result = NULL;
7111 goto out;
7112 }
7113
7114 result->next = *list;
7115 *list = result;
7116
7117 out:
7118 si_llvm_dispose(&ctx);
7119 mtx_unlock(&sscreen->shader_parts_mutex);
7120 return result;
7121 }
7122
7123 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7124 {
7125 LLVMValueRef ptr[2], list;
7126 bool is_merged_shader =
7127 ctx->screen->info.chip_class >= GFX9 &&
7128 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7129 ctx->type == PIPE_SHADER_GEOMETRY ||
7130 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7131
7132 if (HAVE_32BIT_POINTERS) {
7133 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7134 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7135 ac_array_in_const32_addr_space(ctx->v4i32), "");
7136 return list;
7137 }
7138
7139 /* Get the pointer to rw buffers. */
7140 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7141 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7142 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7143 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7144 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7145 ac_array_in_const_addr_space(ctx->v4i32), "");
7146 return list;
7147 }
7148
7149 /**
7150 * Build the vertex shader prolog function.
7151 *
7152 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7153 * All inputs are returned unmodified. The vertex load indices are
7154 * stored after them, which will be used by the API VS for fetching inputs.
7155 *
7156 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7157 * input_v0,
7158 * input_v1,
7159 * input_v2,
7160 * input_v3,
7161 * (VertexID + BaseVertex),
7162 * (InstanceID + StartInstance),
7163 * (InstanceID / 2 + StartInstance)
7164 */
7165 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7166 union si_shader_part_key *key)
7167 {
7168 struct si_function_info fninfo;
7169 LLVMTypeRef *returns;
7170 LLVMValueRef ret, func;
7171 int num_returns, i;
7172 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7173 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7174 LLVMValueRef input_vgprs[9];
7175 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7176 num_input_vgprs;
7177 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7178
7179 si_init_function_info(&fninfo);
7180
7181 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7182 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7183 sizeof(LLVMTypeRef));
7184 num_returns = 0;
7185
7186 /* Declare input and output SGPRs. */
7187 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7188 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7189 returns[num_returns++] = ctx->i32;
7190 }
7191
7192 /* Preloaded VGPRs (outputs must be floats) */
7193 for (i = 0; i < num_input_vgprs; i++) {
7194 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7195 returns[num_returns++] = ctx->f32;
7196 }
7197
7198 /* Vertex load indices. */
7199 for (i = 0; i <= key->vs_prolog.last_input; i++)
7200 returns[num_returns++] = ctx->f32;
7201
7202 /* Create the function. */
7203 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7204 func = ctx->main_fn;
7205
7206 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7207 if (!key->vs_prolog.is_monolithic)
7208 si_init_exec_from_input(ctx, 3, 0);
7209
7210 if (key->vs_prolog.as_ls &&
7211 ctx->screen->has_ls_vgpr_init_bug) {
7212 /* If there are no HS threads, SPI loads the LS VGPRs
7213 * starting at VGPR 0. Shift them back to where they
7214 * belong.
7215 */
7216 LLVMValueRef has_hs_threads =
7217 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7218 unpack_param(ctx, 3, 8, 8),
7219 ctx->i32_0, "");
7220
7221 for (i = 4; i > 0; --i) {
7222 input_vgprs[i + 1] =
7223 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7224 input_vgprs[i + 1],
7225 input_vgprs[i - 1], "");
7226 }
7227 }
7228 }
7229
7230 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7231 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7232
7233 /* Copy inputs to outputs. This should be no-op, as the registers match,
7234 * but it will prevent the compiler from overwriting them unintentionally.
7235 */
7236 ret = ctx->return_value;
7237 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7238 LLVMValueRef p = LLVMGetParam(func, i);
7239 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7240 }
7241 for (i = 0; i < num_input_vgprs; i++) {
7242 LLVMValueRef p = input_vgprs[i];
7243 p = ac_to_float(&ctx->ac, p);
7244 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7245 key->vs_prolog.num_input_sgprs + i, "");
7246 }
7247
7248 /* Compute vertex load indices from instance divisors. */
7249 LLVMValueRef instance_divisor_constbuf = NULL;
7250
7251 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7252 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7253 LLVMValueRef buf_index =
7254 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7255 instance_divisor_constbuf =
7256 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7257 }
7258
7259 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7260 bool divisor_is_one =
7261 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7262 bool divisor_is_fetched =
7263 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7264 LLVMValueRef index;
7265
7266 if (divisor_is_one || divisor_is_fetched) {
7267 LLVMValueRef divisor = ctx->i32_1;
7268
7269 if (divisor_is_fetched) {
7270 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7271 LLVMConstInt(ctx->i32, i * 4, 0));
7272 divisor = ac_to_integer(&ctx->ac, divisor);
7273 }
7274
7275 /* InstanceID / Divisor + StartInstance */
7276 index = get_instance_index_for_fetch(ctx,
7277 user_sgpr_base +
7278 SI_SGPR_START_INSTANCE,
7279 divisor);
7280 } else {
7281 /* VertexID + BaseVertex */
7282 index = LLVMBuildAdd(ctx->ac.builder,
7283 ctx->abi.vertex_id,
7284 LLVMGetParam(func, user_sgpr_base +
7285 SI_SGPR_BASE_VERTEX), "");
7286 }
7287
7288 index = ac_to_float(&ctx->ac, index);
7289 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7290 fninfo.num_params + i, "");
7291 }
7292
7293 si_llvm_build_ret(ctx, ret);
7294 }
7295
7296 static bool si_get_vs_prolog(struct si_screen *sscreen,
7297 LLVMTargetMachineRef tm,
7298 struct si_shader *shader,
7299 struct pipe_debug_callback *debug,
7300 struct si_shader *main_part,
7301 const struct si_vs_prolog_bits *key)
7302 {
7303 struct si_shader_selector *vs = main_part->selector;
7304
7305 if (!si_vs_needs_prolog(vs, key))
7306 return true;
7307
7308 /* Get the prolog. */
7309 union si_shader_part_key prolog_key;
7310 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7311 key, shader, &prolog_key);
7312
7313 shader->prolog =
7314 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7315 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7316 debug, si_build_vs_prolog_function,
7317 "Vertex Shader Prolog");
7318 return shader->prolog != NULL;
7319 }
7320
7321 /**
7322 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7323 */
7324 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7325 LLVMTargetMachineRef tm,
7326 struct si_shader *shader,
7327 struct pipe_debug_callback *debug)
7328 {
7329 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7330 &shader->key.part.vs.prolog);
7331 }
7332
7333 /**
7334 * Compile the TCS epilog function. This writes tesselation factors to memory
7335 * based on the output primitive type of the tesselator (determined by TES).
7336 */
7337 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7338 union si_shader_part_key *key)
7339 {
7340 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7341 struct si_function_info fninfo;
7342 LLVMValueRef func;
7343
7344 si_init_function_info(&fninfo);
7345
7346 if (ctx->screen->info.chip_class >= GFX9) {
7347 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7348 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7349 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7350 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7351 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7352 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7353 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7354 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7355 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7356 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7357 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7358 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7359 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7360 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7361 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7362 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7363 if (!HAVE_32BIT_POINTERS)
7364 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7365 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7366 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7367 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7368 } else {
7369 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7370 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7371 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7372 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7373 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7374 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7375 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7376 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7377 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7378 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7379 }
7380
7381 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7382 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7383 unsigned tess_factors_idx =
7384 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7385 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7386 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7387
7388 for (unsigned i = 0; i < 6; i++)
7389 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7390
7391 /* Create the function. */
7392 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7393 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7394 ac_declare_lds_as_pointer(&ctx->ac);
7395 func = ctx->main_fn;
7396
7397 LLVMValueRef invoc0_tess_factors[6];
7398 for (unsigned i = 0; i < 6; i++)
7399 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7400
7401 si_write_tess_factors(bld_base,
7402 LLVMGetParam(func, tess_factors_idx),
7403 LLVMGetParam(func, tess_factors_idx + 1),
7404 LLVMGetParam(func, tess_factors_idx + 2),
7405 invoc0_tess_factors, invoc0_tess_factors + 4);
7406
7407 LLVMBuildRetVoid(ctx->ac.builder);
7408 }
7409
7410 /**
7411 * Select and compile (or reuse) TCS parts (epilog).
7412 */
7413 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7414 LLVMTargetMachineRef tm,
7415 struct si_shader *shader,
7416 struct pipe_debug_callback *debug)
7417 {
7418 if (sscreen->info.chip_class >= GFX9) {
7419 struct si_shader *ls_main_part =
7420 shader->key.part.tcs.ls->main_shader_part_ls;
7421
7422 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7423 &shader->key.part.tcs.ls_prolog))
7424 return false;
7425
7426 shader->previous_stage = ls_main_part;
7427 }
7428
7429 /* Get the epilog. */
7430 union si_shader_part_key epilog_key;
7431 memset(&epilog_key, 0, sizeof(epilog_key));
7432 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7433
7434 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7435 PIPE_SHADER_TESS_CTRL, false,
7436 &epilog_key, tm, debug,
7437 si_build_tcs_epilog_function,
7438 "Tessellation Control Shader Epilog");
7439 return shader->epilog != NULL;
7440 }
7441
7442 /**
7443 * Select and compile (or reuse) GS parts (prolog).
7444 */
7445 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7446 LLVMTargetMachineRef tm,
7447 struct si_shader *shader,
7448 struct pipe_debug_callback *debug)
7449 {
7450 if (sscreen->info.chip_class >= GFX9) {
7451 struct si_shader *es_main_part =
7452 shader->key.part.gs.es->main_shader_part_es;
7453
7454 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7455 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7456 &shader->key.part.gs.vs_prolog))
7457 return false;
7458
7459 shader->previous_stage = es_main_part;
7460 }
7461
7462 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7463 return true;
7464
7465 union si_shader_part_key prolog_key;
7466 memset(&prolog_key, 0, sizeof(prolog_key));
7467 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7468
7469 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7470 PIPE_SHADER_GEOMETRY, true,
7471 &prolog_key, tm, debug,
7472 si_build_gs_prolog_function,
7473 "Geometry Shader Prolog");
7474 return shader->prolog2 != NULL;
7475 }
7476
7477 /**
7478 * Build the pixel shader prolog function. This handles:
7479 * - two-side color selection and interpolation
7480 * - overriding interpolation parameters for the API PS
7481 * - polygon stippling
7482 *
7483 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7484 * overriden by other states. (e.g. per-sample interpolation)
7485 * Interpolated colors are stored after the preloaded VGPRs.
7486 */
7487 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7488 union si_shader_part_key *key)
7489 {
7490 struct si_function_info fninfo;
7491 LLVMValueRef ret, func;
7492 int num_returns, i, num_color_channels;
7493
7494 assert(si_need_ps_prolog(key));
7495
7496 si_init_function_info(&fninfo);
7497
7498 /* Declare inputs. */
7499 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7500 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7501
7502 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7503 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7504
7505 /* Declare outputs (same as inputs + add colors if needed) */
7506 num_returns = fninfo.num_params;
7507 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7508 for (i = 0; i < num_color_channels; i++)
7509 fninfo.types[num_returns++] = ctx->f32;
7510
7511 /* Create the function. */
7512 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7513 &fninfo, 0);
7514 func = ctx->main_fn;
7515
7516 /* Copy inputs to outputs. This should be no-op, as the registers match,
7517 * but it will prevent the compiler from overwriting them unintentionally.
7518 */
7519 ret = ctx->return_value;
7520 for (i = 0; i < fninfo.num_params; i++) {
7521 LLVMValueRef p = LLVMGetParam(func, i);
7522 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7523 }
7524
7525 /* Polygon stippling. */
7526 if (key->ps_prolog.states.poly_stipple) {
7527 /* POS_FIXED_PT is always last. */
7528 unsigned pos = key->ps_prolog.num_input_sgprs +
7529 key->ps_prolog.num_input_vgprs - 1;
7530 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7531
7532 si_llvm_emit_polygon_stipple(ctx, list, pos);
7533 }
7534
7535 if (key->ps_prolog.states.bc_optimize_for_persp ||
7536 key->ps_prolog.states.bc_optimize_for_linear) {
7537 unsigned i, base = key->ps_prolog.num_input_sgprs;
7538 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7539
7540 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7541 * The hw doesn't compute CENTROID if the whole wave only
7542 * contains fully-covered quads.
7543 *
7544 * PRIM_MASK is after user SGPRs.
7545 */
7546 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7547 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7548 LLVMConstInt(ctx->i32, 31, 0), "");
7549 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7550 ctx->i1, "");
7551
7552 if (key->ps_prolog.states.bc_optimize_for_persp) {
7553 /* Read PERSP_CENTER. */
7554 for (i = 0; i < 2; i++)
7555 center[i] = LLVMGetParam(func, base + 2 + i);
7556 /* Read PERSP_CENTROID. */
7557 for (i = 0; i < 2; i++)
7558 centroid[i] = LLVMGetParam(func, base + 4 + i);
7559 /* Select PERSP_CENTROID. */
7560 for (i = 0; i < 2; i++) {
7561 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7562 center[i], centroid[i], "");
7563 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7564 tmp, base + 4 + i, "");
7565 }
7566 }
7567 if (key->ps_prolog.states.bc_optimize_for_linear) {
7568 /* Read LINEAR_CENTER. */
7569 for (i = 0; i < 2; i++)
7570 center[i] = LLVMGetParam(func, base + 8 + i);
7571 /* Read LINEAR_CENTROID. */
7572 for (i = 0; i < 2; i++)
7573 centroid[i] = LLVMGetParam(func, base + 10 + i);
7574 /* Select LINEAR_CENTROID. */
7575 for (i = 0; i < 2; i++) {
7576 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7577 center[i], centroid[i], "");
7578 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7579 tmp, base + 10 + i, "");
7580 }
7581 }
7582 }
7583
7584 /* Force per-sample interpolation. */
7585 if (key->ps_prolog.states.force_persp_sample_interp) {
7586 unsigned i, base = key->ps_prolog.num_input_sgprs;
7587 LLVMValueRef persp_sample[2];
7588
7589 /* Read PERSP_SAMPLE. */
7590 for (i = 0; i < 2; i++)
7591 persp_sample[i] = LLVMGetParam(func, base + i);
7592 /* Overwrite PERSP_CENTER. */
7593 for (i = 0; i < 2; i++)
7594 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7595 persp_sample[i], base + 2 + i, "");
7596 /* Overwrite PERSP_CENTROID. */
7597 for (i = 0; i < 2; i++)
7598 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7599 persp_sample[i], base + 4 + i, "");
7600 }
7601 if (key->ps_prolog.states.force_linear_sample_interp) {
7602 unsigned i, base = key->ps_prolog.num_input_sgprs;
7603 LLVMValueRef linear_sample[2];
7604
7605 /* Read LINEAR_SAMPLE. */
7606 for (i = 0; i < 2; i++)
7607 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7608 /* Overwrite LINEAR_CENTER. */
7609 for (i = 0; i < 2; i++)
7610 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7611 linear_sample[i], base + 8 + i, "");
7612 /* Overwrite LINEAR_CENTROID. */
7613 for (i = 0; i < 2; i++)
7614 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7615 linear_sample[i], base + 10 + i, "");
7616 }
7617
7618 /* Force center interpolation. */
7619 if (key->ps_prolog.states.force_persp_center_interp) {
7620 unsigned i, base = key->ps_prolog.num_input_sgprs;
7621 LLVMValueRef persp_center[2];
7622
7623 /* Read PERSP_CENTER. */
7624 for (i = 0; i < 2; i++)
7625 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7626 /* Overwrite PERSP_SAMPLE. */
7627 for (i = 0; i < 2; i++)
7628 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7629 persp_center[i], base + i, "");
7630 /* Overwrite PERSP_CENTROID. */
7631 for (i = 0; i < 2; i++)
7632 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7633 persp_center[i], base + 4 + i, "");
7634 }
7635 if (key->ps_prolog.states.force_linear_center_interp) {
7636 unsigned i, base = key->ps_prolog.num_input_sgprs;
7637 LLVMValueRef linear_center[2];
7638
7639 /* Read LINEAR_CENTER. */
7640 for (i = 0; i < 2; i++)
7641 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7642 /* Overwrite LINEAR_SAMPLE. */
7643 for (i = 0; i < 2; i++)
7644 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7645 linear_center[i], base + 6 + i, "");
7646 /* Overwrite LINEAR_CENTROID. */
7647 for (i = 0; i < 2; i++)
7648 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7649 linear_center[i], base + 10 + i, "");
7650 }
7651
7652 /* Interpolate colors. */
7653 unsigned color_out_idx = 0;
7654 for (i = 0; i < 2; i++) {
7655 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7656 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7657 key->ps_prolog.face_vgpr_index;
7658 LLVMValueRef interp[2], color[4];
7659 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7660
7661 if (!writemask)
7662 continue;
7663
7664 /* If the interpolation qualifier is not CONSTANT (-1). */
7665 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7666 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7667 key->ps_prolog.color_interp_vgpr_index[i];
7668
7669 /* Get the (i,j) updated by bc_optimize handling. */
7670 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7671 interp_vgpr, "");
7672 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7673 interp_vgpr + 1, "");
7674 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7675 }
7676
7677 /* Use the absolute location of the input. */
7678 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7679
7680 if (key->ps_prolog.states.color_two_side) {
7681 face = LLVMGetParam(func, face_vgpr);
7682 face = ac_to_integer(&ctx->ac, face);
7683 }
7684
7685 interp_fs_input(ctx,
7686 key->ps_prolog.color_attr_index[i],
7687 TGSI_SEMANTIC_COLOR, i,
7688 key->ps_prolog.num_interp_inputs,
7689 key->ps_prolog.colors_read, interp_ij,
7690 prim_mask, face, color);
7691
7692 while (writemask) {
7693 unsigned chan = u_bit_scan(&writemask);
7694 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7695 fninfo.num_params + color_out_idx++, "");
7696 }
7697 }
7698
7699 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7700 * says:
7701 *
7702 * "When per-sample shading is active due to the use of a fragment
7703 * input qualified by sample or due to the use of the gl_SampleID
7704 * or gl_SamplePosition variables, only the bit for the current
7705 * sample is set in gl_SampleMaskIn. When state specifies multiple
7706 * fragment shader invocations for a given fragment, the sample
7707 * mask for any single fragment shader invocation may specify a
7708 * subset of the covered samples for the fragment. In this case,
7709 * the bit corresponding to each covered sample will be set in
7710 * exactly one fragment shader invocation."
7711 *
7712 * The samplemask loaded by hardware is always the coverage of the
7713 * entire pixel/fragment, so mask bits out based on the sample ID.
7714 */
7715 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7716 /* The bit pattern matches that used by fixed function fragment
7717 * processing. */
7718 static const uint16_t ps_iter_masks[] = {
7719 0xffff, /* not used */
7720 0x5555,
7721 0x1111,
7722 0x0101,
7723 0x0001,
7724 };
7725 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7726
7727 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7728 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7729 key->ps_prolog.ancillary_vgpr_index;
7730 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7731 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7732
7733 samplemask = ac_to_integer(&ctx->ac, samplemask);
7734 samplemask = LLVMBuildAnd(
7735 ctx->ac.builder,
7736 samplemask,
7737 LLVMBuildShl(ctx->ac.builder,
7738 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7739 sampleid, ""),
7740 "");
7741 samplemask = ac_to_float(&ctx->ac, samplemask);
7742
7743 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7744 ancillary_vgpr + 1, "");
7745 }
7746
7747 /* Tell LLVM to insert WQM instruction sequence when needed. */
7748 if (key->ps_prolog.wqm) {
7749 LLVMAddTargetDependentFunctionAttr(func,
7750 "amdgpu-ps-wqm-outputs", "");
7751 }
7752
7753 si_llvm_build_ret(ctx, ret);
7754 }
7755
7756 /**
7757 * Build the pixel shader epilog function. This handles everything that must be
7758 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7759 */
7760 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7761 union si_shader_part_key *key)
7762 {
7763 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7764 struct si_function_info fninfo;
7765 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7766 int i;
7767 struct si_ps_exports exp = {};
7768
7769 si_init_function_info(&fninfo);
7770
7771 /* Declare input SGPRs. */
7772 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7773 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7774 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7775 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7776 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7777
7778 /* Declare input VGPRs. */
7779 unsigned required_num_params =
7780 fninfo.num_sgpr_params +
7781 util_bitcount(key->ps_epilog.colors_written) * 4 +
7782 key->ps_epilog.writes_z +
7783 key->ps_epilog.writes_stencil +
7784 key->ps_epilog.writes_samplemask;
7785
7786 required_num_params = MAX2(required_num_params,
7787 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7788
7789 while (fninfo.num_params < required_num_params)
7790 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7791
7792 /* Create the function. */
7793 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7794 /* Disable elimination of unused inputs. */
7795 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7796 "InitialPSInputAddr", 0xffffff);
7797
7798 /* Process colors. */
7799 unsigned vgpr = fninfo.num_sgpr_params;
7800 unsigned colors_written = key->ps_epilog.colors_written;
7801 int last_color_export = -1;
7802
7803 /* Find the last color export. */
7804 if (!key->ps_epilog.writes_z &&
7805 !key->ps_epilog.writes_stencil &&
7806 !key->ps_epilog.writes_samplemask) {
7807 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7808
7809 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7810 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7811 /* Just set this if any of the colorbuffers are enabled. */
7812 if (spi_format &
7813 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7814 last_color_export = 0;
7815 } else {
7816 for (i = 0; i < 8; i++)
7817 if (colors_written & (1 << i) &&
7818 (spi_format >> (i * 4)) & 0xf)
7819 last_color_export = i;
7820 }
7821 }
7822
7823 while (colors_written) {
7824 LLVMValueRef color[4];
7825 int mrt = u_bit_scan(&colors_written);
7826
7827 for (i = 0; i < 4; i++)
7828 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7829
7830 si_export_mrt_color(bld_base, color, mrt,
7831 fninfo.num_params - 1,
7832 mrt == last_color_export, &exp);
7833 }
7834
7835 /* Process depth, stencil, samplemask. */
7836 if (key->ps_epilog.writes_z)
7837 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7838 if (key->ps_epilog.writes_stencil)
7839 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7840 if (key->ps_epilog.writes_samplemask)
7841 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7842
7843 if (depth || stencil || samplemask)
7844 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7845 else if (last_color_export == -1)
7846 ac_build_export_null(&ctx->ac);
7847
7848 if (exp.num)
7849 si_emit_ps_exports(ctx, &exp);
7850
7851 /* Compile. */
7852 LLVMBuildRetVoid(ctx->ac.builder);
7853 }
7854
7855 /**
7856 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7857 */
7858 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7859 LLVMTargetMachineRef tm,
7860 struct si_shader *shader,
7861 struct pipe_debug_callback *debug)
7862 {
7863 union si_shader_part_key prolog_key;
7864 union si_shader_part_key epilog_key;
7865
7866 /* Get the prolog. */
7867 si_get_ps_prolog_key(shader, &prolog_key, true);
7868
7869 /* The prolog is a no-op if these aren't set. */
7870 if (si_need_ps_prolog(&prolog_key)) {
7871 shader->prolog =
7872 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7873 PIPE_SHADER_FRAGMENT, true,
7874 &prolog_key, tm, debug,
7875 si_build_ps_prolog_function,
7876 "Fragment Shader Prolog");
7877 if (!shader->prolog)
7878 return false;
7879 }
7880
7881 /* Get the epilog. */
7882 si_get_ps_epilog_key(shader, &epilog_key);
7883
7884 shader->epilog =
7885 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7886 PIPE_SHADER_FRAGMENT, false,
7887 &epilog_key, tm, debug,
7888 si_build_ps_epilog_function,
7889 "Fragment Shader Epilog");
7890 if (!shader->epilog)
7891 return false;
7892
7893 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7894 if (shader->key.part.ps.prolog.poly_stipple) {
7895 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7896 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7897 }
7898
7899 /* Set up the enable bits for per-sample shading if needed. */
7900 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7901 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7902 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7903 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7904 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7905 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7906 }
7907 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7908 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7909 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7910 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7911 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7912 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7913 }
7914 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7915 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7916 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7917 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7918 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7919 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7920 }
7921 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7922 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7923 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7924 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7925 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7926 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7927 }
7928
7929 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7930 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7931 !(shader->config.spi_ps_input_ena & 0xf)) {
7932 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7933 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7934 }
7935
7936 /* At least one pair of interpolation weights must be enabled. */
7937 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7938 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7939 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7940 }
7941
7942 /* Samplemask fixup requires the sample ID. */
7943 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7944 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7945 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7946 }
7947
7948 /* The sample mask input is always enabled, because the API shader always
7949 * passes it through to the epilog. Disable it here if it's unused.
7950 */
7951 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7952 !shader->selector->info.reads_samplemask)
7953 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7954
7955 return true;
7956 }
7957
7958 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7959 unsigned *lds_size)
7960 {
7961 /* SPI barrier management bug:
7962 * Make sure we have at least 4k of LDS in use to avoid the bug.
7963 * It applies to workgroup sizes of more than one wavefront.
7964 */
7965 if (sscreen->info.family == CHIP_BONAIRE ||
7966 sscreen->info.family == CHIP_KABINI ||
7967 sscreen->info.family == CHIP_MULLINS)
7968 *lds_size = MAX2(*lds_size, 8);
7969 }
7970
7971 static void si_fix_resource_usage(struct si_screen *sscreen,
7972 struct si_shader *shader)
7973 {
7974 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7975
7976 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7977
7978 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7979 si_get_max_workgroup_size(shader) > 64) {
7980 si_multiwave_lds_size_workaround(sscreen,
7981 &shader->config.lds_size);
7982 }
7983 }
7984
7985 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7986 struct si_shader *shader,
7987 struct pipe_debug_callback *debug)
7988 {
7989 struct si_shader_selector *sel = shader->selector;
7990 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7991 int r;
7992
7993 /* LS, ES, VS are compiled on demand if the main part hasn't been
7994 * compiled for that stage.
7995 *
7996 * Vertex shaders are compiled on demand when a vertex fetch
7997 * workaround must be applied.
7998 */
7999 if (shader->is_monolithic) {
8000 /* Monolithic shader (compiled as a whole, has many variants,
8001 * may take a long time to compile).
8002 */
8003 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8004 if (r)
8005 return r;
8006 } else {
8007 /* The shader consists of several parts:
8008 *
8009 * - the middle part is the user shader, it has 1 variant only
8010 * and it was compiled during the creation of the shader
8011 * selector
8012 * - the prolog part is inserted at the beginning
8013 * - the epilog part is inserted at the end
8014 *
8015 * The prolog and epilog have many (but simple) variants.
8016 *
8017 * Starting with gfx9, geometry and tessellation control
8018 * shaders also contain the prolog and user shader parts of
8019 * the previous shader stage.
8020 */
8021
8022 if (!mainp)
8023 return -1;
8024
8025 /* Copy the compiled TGSI shader data over. */
8026 shader->is_binary_shared = true;
8027 shader->binary = mainp->binary;
8028 shader->config = mainp->config;
8029 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8030 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8031 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8032 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8033 memcpy(shader->info.vs_output_param_offset,
8034 mainp->info.vs_output_param_offset,
8035 sizeof(mainp->info.vs_output_param_offset));
8036 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8037 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8038 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8039
8040 /* Select prologs and/or epilogs. */
8041 switch (sel->type) {
8042 case PIPE_SHADER_VERTEX:
8043 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8044 return -1;
8045 break;
8046 case PIPE_SHADER_TESS_CTRL:
8047 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8048 return -1;
8049 break;
8050 case PIPE_SHADER_TESS_EVAL:
8051 break;
8052 case PIPE_SHADER_GEOMETRY:
8053 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8054 return -1;
8055 break;
8056 case PIPE_SHADER_FRAGMENT:
8057 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8058 return -1;
8059
8060 /* Make sure we have at least as many VGPRs as there
8061 * are allocated inputs.
8062 */
8063 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8064 shader->info.num_input_vgprs);
8065 break;
8066 }
8067
8068 /* Update SGPR and VGPR counts. */
8069 if (shader->prolog) {
8070 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8071 shader->prolog->config.num_sgprs);
8072 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8073 shader->prolog->config.num_vgprs);
8074 }
8075 if (shader->previous_stage) {
8076 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8077 shader->previous_stage->config.num_sgprs);
8078 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8079 shader->previous_stage->config.num_vgprs);
8080 shader->config.spilled_sgprs =
8081 MAX2(shader->config.spilled_sgprs,
8082 shader->previous_stage->config.spilled_sgprs);
8083 shader->config.spilled_vgprs =
8084 MAX2(shader->config.spilled_vgprs,
8085 shader->previous_stage->config.spilled_vgprs);
8086 shader->config.private_mem_vgprs =
8087 MAX2(shader->config.private_mem_vgprs,
8088 shader->previous_stage->config.private_mem_vgprs);
8089 shader->config.scratch_bytes_per_wave =
8090 MAX2(shader->config.scratch_bytes_per_wave,
8091 shader->previous_stage->config.scratch_bytes_per_wave);
8092 shader->info.uses_instanceid |=
8093 shader->previous_stage->info.uses_instanceid;
8094 }
8095 if (shader->prolog2) {
8096 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8097 shader->prolog2->config.num_sgprs);
8098 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8099 shader->prolog2->config.num_vgprs);
8100 }
8101 if (shader->epilog) {
8102 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8103 shader->epilog->config.num_sgprs);
8104 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8105 shader->epilog->config.num_vgprs);
8106 }
8107 si_calculate_max_simd_waves(shader);
8108 }
8109
8110 si_fix_resource_usage(sscreen, shader);
8111 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8112 stderr, true);
8113
8114 /* Upload. */
8115 r = si_shader_binary_upload(sscreen, shader);
8116 if (r) {
8117 fprintf(stderr, "LLVM failed to upload shader\n");
8118 return r;
8119 }
8120
8121 return 0;
8122 }
8123
8124 void si_shader_destroy(struct si_shader *shader)
8125 {
8126 if (shader->scratch_bo)
8127 r600_resource_reference(&shader->scratch_bo, NULL);
8128
8129 r600_resource_reference(&shader->bo, NULL);
8130
8131 if (!shader->is_binary_shared)
8132 ac_shader_binary_clean(&shader->binary);
8133
8134 free(shader->shader_log);
8135 }