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radeonsi: fix a typo in creating monolithic ES-GS
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "si_shader_internal.h"
41 #include "si_pipe.h"
42 #include "sid.h"
43
44 #include "compiler/nir/nir.h"
45
46 static const char *scratch_rsrc_dword0_symbol =
47 "SCRATCH_RSRC_DWORD0";
48
49 static const char *scratch_rsrc_dword1_symbol =
50 "SCRATCH_RSRC_DWORD1";
51
52 struct si_shader_output_values
53 {
54 LLVMValueRef values[4];
55 unsigned semantic_name;
56 unsigned semantic_index;
57 ubyte vertex_stream[4];
58 };
59
60 /**
61 * Used to collect types and other info about arguments of the LLVM function
62 * before the function is created.
63 */
64 struct si_function_info {
65 LLVMTypeRef types[100];
66 LLVMValueRef *assign[100];
67 unsigned num_sgpr_params;
68 unsigned num_params;
69 };
70
71 enum si_arg_regfile {
72 ARG_SGPR,
73 ARG_VGPR
74 };
75
76 static void si_init_shader_ctx(struct si_shader_context *ctx,
77 struct si_screen *sscreen,
78 LLVMTargetMachineRef tm);
79
80 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
81 struct lp_build_tgsi_context *bld_base,
82 struct lp_build_emit_data *emit_data);
83
84 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
85 FILE *f);
86
87 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
90 union si_shader_part_key *key);
91 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
92 union si_shader_part_key *key);
93 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
94 union si_shader_part_key *key);
95
96 /* Ideally pass the sample mask input to the PS epilog as v14, which
97 * is its usual location, so that the shader doesn't have to add v_mov.
98 */
99 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
100
101 enum {
102 CONST_ADDR_SPACE = 2,
103 LOCAL_ADDR_SPACE = 3,
104 };
105
106 static bool is_merged_shader(struct si_shader *shader)
107 {
108 if (shader->selector->screen->b.chip_class <= VI)
109 return false;
110
111 return shader->key.as_ls ||
112 shader->key.as_es ||
113 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
114 shader->selector->type == PIPE_SHADER_GEOMETRY;
115 }
116
117 static void si_init_function_info(struct si_function_info *fninfo)
118 {
119 fninfo->num_params = 0;
120 fninfo->num_sgpr_params = 0;
121 }
122
123 static unsigned add_arg_assign(struct si_function_info *fninfo,
124 enum si_arg_regfile regfile, LLVMTypeRef type,
125 LLVMValueRef *assign)
126 {
127 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
128
129 unsigned idx = fninfo->num_params++;
130 assert(idx < ARRAY_SIZE(fninfo->types));
131
132 if (regfile == ARG_SGPR)
133 fninfo->num_sgpr_params = fninfo->num_params;
134
135 fninfo->types[idx] = type;
136 fninfo->assign[idx] = assign;
137 return idx;
138 }
139
140 static unsigned add_arg(struct si_function_info *fninfo,
141 enum si_arg_regfile regfile, LLVMTypeRef type)
142 {
143 return add_arg_assign(fninfo, regfile, type, NULL);
144 }
145
146 static void add_arg_assign_checked(struct si_function_info *fninfo,
147 enum si_arg_regfile regfile, LLVMTypeRef type,
148 LLVMValueRef *assign, unsigned idx)
149 {
150 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
151 assert(actual == idx);
152 }
153
154 static void add_arg_checked(struct si_function_info *fninfo,
155 enum si_arg_regfile regfile, LLVMTypeRef type,
156 unsigned idx)
157 {
158 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Get the value of a shader input parameter and extract a bitfield.
233 */
234 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
235 unsigned param, unsigned rshift,
236 unsigned bitwidth)
237 {
238 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
239 param);
240
241 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
242 value = ac_to_integer(&ctx->ac, value);
243
244 if (rshift)
245 value = LLVMBuildLShr(ctx->ac.builder, value,
246 LLVMConstInt(ctx->i32, rshift, 0), "");
247
248 if (rshift + bitwidth < 32) {
249 unsigned mask = (1 << bitwidth) - 1;
250 value = LLVMBuildAnd(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, mask, 0), "");
252 }
253
254 return value;
255 }
256
257 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
258 {
259 switch (ctx->type) {
260 case PIPE_SHADER_TESS_CTRL:
261 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
262
263 case PIPE_SHADER_TESS_EVAL:
264 return LLVMGetParam(ctx->main_fn,
265 ctx->param_tes_rel_patch_id);
266
267 default:
268 assert(0);
269 return NULL;
270 }
271 }
272
273 /* Tessellation shaders pass outputs to the next shader using LDS.
274 *
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
277 *
278 * The LDS layout is:
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
282 * - ...
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
289 * - ...
290 *
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
292 */
293
294 static LLVMValueRef
295 get_tcs_in_patch_stride(struct si_shader_context *ctx)
296 {
297 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
298 }
299
300 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
301 {
302 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
303
304 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
305 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
306
307 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
308 }
309
310 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
311 {
312 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
313
314 return LLVMConstInt(ctx->i32, stride, 0);
315 }
316
317 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
320 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
321
322 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
323 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
324 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
325 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
326 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
327 num_patch_outputs * 4;
328 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
329 }
330
331 static LLVMValueRef
332 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
333 {
334 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
335 unpack_param(ctx,
336 ctx->param_tcs_out_lds_offsets,
337 0, 16),
338 4);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 16, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
353 {
354 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
355 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
356
357 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
358 }
359
360 static LLVMValueRef
361 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
362 {
363 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
364 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
368 LLVMBuildMul(ctx->ac.builder, patch_stride,
369 rel_patch_id, ""),
370 "");
371 }
372
373 static LLVMValueRef
374 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
375 {
376 LLVMValueRef patch0_patch_data_offset =
377 get_tcs_out_patch0_patch_data_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
382 LLVMBuildMul(ctx->ac.builder, patch_stride,
383 rel_patch_id, ""),
384 "");
385 }
386
387 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
388 {
389 unsigned tcs_out_vertices =
390 ctx->shader->selector ?
391 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
392
393 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
394 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
395 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
396
397 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
398 }
399
400 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
401 {
402 unsigned stride;
403
404 switch (ctx->type) {
405 case PIPE_SHADER_VERTEX:
406 stride = util_last_bit64(ctx->shader->selector->outputs_written);
407 return LLVMConstInt(ctx->i32, stride * 4, 0);
408
409 case PIPE_SHADER_TESS_CTRL:
410 if (ctx->screen->b.chip_class >= GFX9 &&
411 ctx->shader->is_monolithic) {
412 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
413 return LLVMConstInt(ctx->i32, stride * 4, 0);
414 }
415 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
416
417 default:
418 assert(0);
419 return NULL;
420 }
421 }
422
423 static LLVMValueRef get_instance_index_for_fetch(
424 struct si_shader_context *ctx,
425 unsigned param_start_instance, LLVMValueRef divisor)
426 {
427 LLVMValueRef result = ctx->abi.instance_id;
428
429 /* The division must be done before START_INSTANCE is added. */
430 if (divisor != ctx->i32_1)
431 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
432
433 return LLVMBuildAdd(ctx->ac.builder, result,
434 LLVMGetParam(ctx->main_fn, param_start_instance), "");
435 }
436
437 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
438 * to float. */
439 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
440 LLVMValueRef vec4,
441 unsigned double_index)
442 {
443 LLVMBuilderRef builder = ctx->ac.builder;
444 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
445 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
446 LLVMVectorType(f64, 2), "");
447 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
448 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
449 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
450 }
451
452 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
453 LLVMValueRef i32, unsigned index)
454 {
455 assert(index <= 1);
456
457 if (index == 1)
458 return LLVMBuildAShr(ctx->ac.builder, i32,
459 LLVMConstInt(ctx->i32, 16, 0), "");
460
461 return LLVMBuildSExt(ctx->ac.builder,
462 LLVMBuildTrunc(ctx->ac.builder, i32,
463 ctx->ac.i16, ""),
464 ctx->i32, "");
465 }
466
467 void si_llvm_load_input_vs(
468 struct si_shader_context *ctx,
469 unsigned input_index,
470 LLVMValueRef out[4])
471 {
472 unsigned vs_blit_property =
473 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
474
475 if (vs_blit_property) {
476 LLVMValueRef vertex_id = ctx->abi.vertex_id;
477 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
478 LLVMIntULE, vertex_id,
479 ctx->i32_1, "");
480 /* Use LLVMIntNE, because we have 3 vertices and only
481 * the middle one should use y2.
482 */
483 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
484 LLVMIntNE, vertex_id,
485 ctx->i32_1, "");
486
487 if (input_index == 0) {
488 /* Position: */
489 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs);
491 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
492 ctx->param_vs_blit_inputs + 1);
493
494 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
495 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
496 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
497 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
498
499 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
500 x1, x2, "");
501 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
502 y1, y2, "");
503
504 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
505 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
506 out[2] = LLVMGetParam(ctx->main_fn,
507 ctx->param_vs_blit_inputs + 2);
508 out[3] = ctx->ac.f32_1;
509 return;
510 }
511
512 /* Color or texture coordinates: */
513 assert(input_index == 1);
514
515 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
516 for (int i = 0; i < 4; i++) {
517 out[i] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 3 + i);
519 }
520 } else {
521 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
522 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 3);
524 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
525 ctx->param_vs_blit_inputs + 4);
526 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
527 ctx->param_vs_blit_inputs + 5);
528 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 6);
530
531 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
532 x1, x2, "");
533 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
534 y1, y2, "");
535 out[2] = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 7);
537 out[3] = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 8);
539 }
540 return;
541 }
542
543 unsigned chan;
544 unsigned fix_fetch;
545 unsigned num_fetches;
546 unsigned fetch_stride;
547
548 LLVMValueRef t_list_ptr;
549 LLVMValueRef t_offset;
550 LLVMValueRef t_list;
551 LLVMValueRef vertex_index;
552 LLVMValueRef input[3];
553
554 /* Load the T list */
555 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
556
557 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
558
559 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
560
561 vertex_index = LLVMGetParam(ctx->main_fn,
562 ctx->param_vertex_index0 +
563 input_index);
564
565 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
566
567 /* Do multiple loads for special formats. */
568 switch (fix_fetch) {
569 case SI_FIX_FETCH_RGB_64_FLOAT:
570 num_fetches = 3; /* 3 2-dword loads */
571 fetch_stride = 8;
572 break;
573 case SI_FIX_FETCH_RGBA_64_FLOAT:
574 num_fetches = 2; /* 2 4-dword loads */
575 fetch_stride = 16;
576 break;
577 case SI_FIX_FETCH_RGB_8:
578 case SI_FIX_FETCH_RGB_8_INT:
579 num_fetches = 3;
580 fetch_stride = 1;
581 break;
582 case SI_FIX_FETCH_RGB_16:
583 case SI_FIX_FETCH_RGB_16_INT:
584 num_fetches = 3;
585 fetch_stride = 2;
586 break;
587 default:
588 num_fetches = 1;
589 fetch_stride = 0;
590 }
591
592 for (unsigned i = 0; i < num_fetches; i++) {
593 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
594
595 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
596 vertex_index, voffset,
597 true);
598 }
599
600 /* Break up the vec4 into individual components */
601 for (chan = 0; chan < 4; chan++) {
602 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
603 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
604 input[0], llvm_chan, "");
605 }
606
607 switch (fix_fetch) {
608 case SI_FIX_FETCH_A2_SNORM:
609 case SI_FIX_FETCH_A2_SSCALED:
610 case SI_FIX_FETCH_A2_SINT: {
611 /* The hardware returns an unsigned value; convert it to a
612 * signed one.
613 */
614 LLVMValueRef tmp = out[3];
615 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
616
617 /* First, recover the sign-extended signed integer value. */
618 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
619 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
620 else
621 tmp = ac_to_integer(&ctx->ac, tmp);
622
623 /* For the integer-like cases, do a natural sign extension.
624 *
625 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
626 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
627 * exponent.
628 */
629 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
630 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
631 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
632 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
633
634 /* Convert back to the right type. */
635 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
636 LLVMValueRef clamp;
637 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
638 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
639 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
640 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
641 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
642 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
643 }
644
645 out[3] = tmp;
646 break;
647 }
648 case SI_FIX_FETCH_RGBA_32_UNORM:
649 case SI_FIX_FETCH_RGBX_32_UNORM:
650 for (chan = 0; chan < 4; chan++) {
651 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
652 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
653 out[chan], ctx->f32, "");
654 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
655 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
656 }
657 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
658 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
659 out[3] = LLVMConstReal(ctx->f32, 1);
660 break;
661 case SI_FIX_FETCH_RGBA_32_SNORM:
662 case SI_FIX_FETCH_RGBX_32_SNORM:
663 case SI_FIX_FETCH_RGBA_32_FIXED:
664 case SI_FIX_FETCH_RGBX_32_FIXED: {
665 double scale;
666 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
667 scale = 1.0 / 0x10000;
668 else
669 scale = 1.0 / INT_MAX;
670
671 for (chan = 0; chan < 4; chan++) {
672 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
673 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
674 out[chan], ctx->f32, "");
675 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
676 LLVMConstReal(ctx->f32, scale), "");
677 }
678 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
679 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
680 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
681 out[3] = LLVMConstReal(ctx->f32, 1);
682 break;
683 }
684 case SI_FIX_FETCH_RGBA_32_USCALED:
685 for (chan = 0; chan < 4; chan++) {
686 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
687 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
688 out[chan], ctx->f32, "");
689 }
690 break;
691 case SI_FIX_FETCH_RGBA_32_SSCALED:
692 for (chan = 0; chan < 4; chan++) {
693 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
694 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
695 out[chan], ctx->f32, "");
696 }
697 break;
698 case SI_FIX_FETCH_RG_64_FLOAT:
699 for (chan = 0; chan < 2; chan++)
700 out[chan] = extract_double_to_float(ctx, input[0], chan);
701
702 out[2] = LLVMConstReal(ctx->f32, 0);
703 out[3] = LLVMConstReal(ctx->f32, 1);
704 break;
705 case SI_FIX_FETCH_RGB_64_FLOAT:
706 for (chan = 0; chan < 3; chan++)
707 out[chan] = extract_double_to_float(ctx, input[chan], 0);
708
709 out[3] = LLVMConstReal(ctx->f32, 1);
710 break;
711 case SI_FIX_FETCH_RGBA_64_FLOAT:
712 for (chan = 0; chan < 4; chan++) {
713 out[chan] = extract_double_to_float(ctx, input[chan / 2],
714 chan % 2);
715 }
716 break;
717 case SI_FIX_FETCH_RGB_8:
718 case SI_FIX_FETCH_RGB_8_INT:
719 case SI_FIX_FETCH_RGB_16:
720 case SI_FIX_FETCH_RGB_16_INT:
721 for (chan = 0; chan < 3; chan++) {
722 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
723 input[chan],
724 ctx->i32_0, "");
725 }
726 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
727 fix_fetch == SI_FIX_FETCH_RGB_16) {
728 out[3] = LLVMConstReal(ctx->f32, 1);
729 } else {
730 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
731 }
732 break;
733 }
734 }
735
736 static void declare_input_vs(
737 struct si_shader_context *ctx,
738 unsigned input_index,
739 const struct tgsi_full_declaration *decl,
740 LLVMValueRef out[4])
741 {
742 si_llvm_load_input_vs(ctx, input_index, out);
743 }
744
745 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
746 unsigned swizzle)
747 {
748 if (swizzle > 0)
749 return ctx->i32_0;
750
751 switch (ctx->type) {
752 case PIPE_SHADER_VERTEX:
753 return LLVMGetParam(ctx->main_fn,
754 ctx->param_vs_prim_id);
755 case PIPE_SHADER_TESS_CTRL:
756 return LLVMGetParam(ctx->main_fn,
757 ctx->param_tcs_patch_id);
758 case PIPE_SHADER_TESS_EVAL:
759 return LLVMGetParam(ctx->main_fn,
760 ctx->param_tes_patch_id);
761 case PIPE_SHADER_GEOMETRY:
762 return ctx->abi.gs_prim_id;
763 default:
764 assert(0);
765 return ctx->i32_0;
766 }
767 }
768
769 /**
770 * Return the value of tgsi_ind_register for indexing.
771 * This is the indirect index with the constant offset added to it.
772 */
773 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
774 const struct tgsi_ind_register *ind,
775 unsigned addr_mul,
776 int rel_index)
777 {
778 LLVMValueRef result;
779
780 if (ind->File == TGSI_FILE_ADDRESS) {
781 result = ctx->addrs[ind->Index][ind->Swizzle];
782 result = LLVMBuildLoad(ctx->ac.builder, result, "");
783 } else {
784 struct tgsi_full_src_register src = {};
785
786 src.Register.File = ind->File;
787 src.Register.Index = ind->Index;
788
789 /* Set the second index to 0 for constants. */
790 if (ind->File == TGSI_FILE_CONSTANT)
791 src.Register.Dimension = 1;
792
793 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
794 TGSI_TYPE_SIGNED,
795 ind->Swizzle);
796 result = ac_to_integer(&ctx->ac, result);
797 }
798
799 if (addr_mul != 1)
800 result = LLVMBuildMul(ctx->ac.builder, result,
801 LLVMConstInt(ctx->i32, addr_mul, 0), "");
802 result = LLVMBuildAdd(ctx->ac.builder, result,
803 LLVMConstInt(ctx->i32, rel_index, 0), "");
804 return result;
805 }
806
807 /**
808 * Like si_get_indirect_index, but restricts the return value to a (possibly
809 * undefined) value inside [0..num).
810 */
811 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
812 const struct tgsi_ind_register *ind,
813 int rel_index, unsigned num)
814 {
815 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
816
817 return si_llvm_bound_index(ctx, result, num);
818 }
819
820
821 /**
822 * Calculate a dword address given an input or output register and a stride.
823 */
824 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
825 const struct tgsi_full_dst_register *dst,
826 const struct tgsi_full_src_register *src,
827 LLVMValueRef vertex_dw_stride,
828 LLVMValueRef base_addr)
829 {
830 struct tgsi_shader_info *info = &ctx->shader->selector->info;
831 ubyte *name, *index, *array_first;
832 int first, param;
833 struct tgsi_full_dst_register reg;
834
835 /* Set the register description. The address computation is the same
836 * for sources and destinations. */
837 if (src) {
838 reg.Register.File = src->Register.File;
839 reg.Register.Index = src->Register.Index;
840 reg.Register.Indirect = src->Register.Indirect;
841 reg.Register.Dimension = src->Register.Dimension;
842 reg.Indirect = src->Indirect;
843 reg.Dimension = src->Dimension;
844 reg.DimIndirect = src->DimIndirect;
845 } else
846 reg = *dst;
847
848 /* If the register is 2-dimensional (e.g. an array of vertices
849 * in a primitive), calculate the base address of the vertex. */
850 if (reg.Register.Dimension) {
851 LLVMValueRef index;
852
853 if (reg.Dimension.Indirect)
854 index = si_get_indirect_index(ctx, &reg.DimIndirect,
855 1, reg.Dimension.Index);
856 else
857 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
858
859 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
860 LLVMBuildMul(ctx->ac.builder, index,
861 vertex_dw_stride, ""), "");
862 }
863
864 /* Get information about the register. */
865 if (reg.Register.File == TGSI_FILE_INPUT) {
866 name = info->input_semantic_name;
867 index = info->input_semantic_index;
868 array_first = info->input_array_first;
869 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
870 name = info->output_semantic_name;
871 index = info->output_semantic_index;
872 array_first = info->output_array_first;
873 } else {
874 assert(0);
875 return NULL;
876 }
877
878 if (reg.Register.Indirect) {
879 /* Add the relative address of the element. */
880 LLVMValueRef ind_index;
881
882 if (reg.Indirect.ArrayID)
883 first = array_first[reg.Indirect.ArrayID];
884 else
885 first = reg.Register.Index;
886
887 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
888 1, reg.Register.Index - first);
889
890 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
891 LLVMBuildMul(ctx->ac.builder, ind_index,
892 LLVMConstInt(ctx->i32, 4, 0), ""), "");
893
894 param = reg.Register.Dimension ?
895 si_shader_io_get_unique_index(name[first], index[first]) :
896 si_shader_io_get_unique_index_patch(name[first], index[first]);
897 } else {
898 param = reg.Register.Dimension ?
899 si_shader_io_get_unique_index(name[reg.Register.Index],
900 index[reg.Register.Index]) :
901 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
902 index[reg.Register.Index]);
903 }
904
905 /* Add the base address of the element. */
906 return LLVMBuildAdd(ctx->ac.builder, base_addr,
907 LLVMConstInt(ctx->i32, param * 4, 0), "");
908 }
909
910 /* The offchip buffer layout for TCS->TES is
911 *
912 * - attribute 0 of patch 0 vertex 0
913 * - attribute 0 of patch 0 vertex 1
914 * - attribute 0 of patch 0 vertex 2
915 * ...
916 * - attribute 0 of patch 1 vertex 0
917 * - attribute 0 of patch 1 vertex 1
918 * ...
919 * - attribute 1 of patch 0 vertex 0
920 * - attribute 1 of patch 0 vertex 1
921 * ...
922 * - per patch attribute 0 of patch 0
923 * - per patch attribute 0 of patch 1
924 * ...
925 *
926 * Note that every attribute has 4 components.
927 */
928 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
929 LLVMValueRef rel_patch_id,
930 LLVMValueRef vertex_index,
931 LLVMValueRef param_index)
932 {
933 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
934 LLVMValueRef param_stride, constant16;
935
936 vertices_per_patch = get_num_tcs_out_vertices(ctx);
937 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
938 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
939 num_patches, "");
940
941 constant16 = LLVMConstInt(ctx->i32, 16, 0);
942 if (vertex_index) {
943 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
944 vertices_per_patch, "");
945
946 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
947 vertex_index, "");
948
949 param_stride = total_vertices;
950 } else {
951 base_addr = rel_patch_id;
952 param_stride = num_patches;
953 }
954
955 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
956 LLVMBuildMul(ctx->ac.builder, param_index,
957 param_stride, ""), "");
958
959 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
960
961 if (!vertex_index) {
962 LLVMValueRef patch_data_offset =
963 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 patch_data_offset, "");
967 }
968 return base_addr;
969 }
970
971 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
972 struct si_shader_context *ctx,
973 const struct tgsi_full_dst_register *dst,
974 const struct tgsi_full_src_register *src)
975 {
976 struct tgsi_shader_info *info = &ctx->shader->selector->info;
977 ubyte *name, *index, *array_first;
978 struct tgsi_full_src_register reg;
979 LLVMValueRef vertex_index = NULL;
980 LLVMValueRef param_index = NULL;
981 unsigned param_index_base, param_base;
982
983 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
984
985 if (reg.Register.Dimension) {
986
987 if (reg.Dimension.Indirect)
988 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
989 1, reg.Dimension.Index);
990 else
991 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
992 }
993
994 /* Get information about the register. */
995 if (reg.Register.File == TGSI_FILE_INPUT) {
996 name = info->input_semantic_name;
997 index = info->input_semantic_index;
998 array_first = info->input_array_first;
999 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1000 name = info->output_semantic_name;
1001 index = info->output_semantic_index;
1002 array_first = info->output_array_first;
1003 } else {
1004 assert(0);
1005 return NULL;
1006 }
1007
1008 if (reg.Register.Indirect) {
1009 if (reg.Indirect.ArrayID)
1010 param_base = array_first[reg.Indirect.ArrayID];
1011 else
1012 param_base = reg.Register.Index;
1013
1014 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1015 1, reg.Register.Index - param_base);
1016
1017 } else {
1018 param_base = reg.Register.Index;
1019 param_index = ctx->i32_0;
1020 }
1021
1022 param_index_base = reg.Register.Dimension ?
1023 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
1024 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
1025
1026 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1027 LLVMConstInt(ctx->i32, param_index_base, 0),
1028 "");
1029
1030 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1031 vertex_index, param_index);
1032 }
1033
1034 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1035 enum tgsi_opcode_type type, unsigned swizzle,
1036 LLVMValueRef buffer, LLVMValueRef offset,
1037 LLVMValueRef base, bool can_speculate)
1038 {
1039 struct si_shader_context *ctx = si_shader_context(bld_base);
1040 LLVMValueRef value, value2;
1041 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
1042 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
1043
1044 if (swizzle == ~0) {
1045 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1046 0, 1, 0, can_speculate, false);
1047
1048 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1049 }
1050
1051 if (!tgsi_type_is_64bit(type)) {
1052 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1053 0, 1, 0, can_speculate, false);
1054
1055 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1056 return LLVMBuildExtractElement(ctx->ac.builder, value,
1057 LLVMConstInt(ctx->i32, swizzle, 0), "");
1058 }
1059
1060 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1061 swizzle * 4, 1, 0, can_speculate, false);
1062
1063 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1064 swizzle * 4 + 4, 1, 0, can_speculate, false);
1065
1066 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1067 }
1068
1069 /**
1070 * Load from LDS.
1071 *
1072 * \param type output value type
1073 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1074 * \param dw_addr address in dwords
1075 */
1076 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1077 enum tgsi_opcode_type type, unsigned swizzle,
1078 LLVMValueRef dw_addr)
1079 {
1080 struct si_shader_context *ctx = si_shader_context(bld_base);
1081 LLVMValueRef value;
1082
1083 if (swizzle == ~0) {
1084 LLVMValueRef values[TGSI_NUM_CHANNELS];
1085
1086 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1087 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1088
1089 return lp_build_gather_values(&ctx->gallivm, values,
1090 TGSI_NUM_CHANNELS);
1091 }
1092
1093 /* Split 64-bit loads. */
1094 if (tgsi_type_is_64bit(type)) {
1095 LLVMValueRef lo, hi;
1096
1097 lo = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle, dw_addr);
1098 hi = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle + 1, dw_addr);
1099 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1100 }
1101
1102 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1103 LLVMConstInt(ctx->i32, swizzle, 0));
1104
1105 value = ac_lds_load(&ctx->ac, dw_addr);
1106
1107 return bitcast(bld_base, type, value);
1108 }
1109
1110 /**
1111 * Store to LDS.
1112 *
1113 * \param swizzle offset (typically 0..3)
1114 * \param dw_addr address in dwords
1115 * \param value value to store
1116 */
1117 static void lds_store(struct lp_build_tgsi_context *bld_base,
1118 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1119 LLVMValueRef value)
1120 {
1121 struct si_shader_context *ctx = si_shader_context(bld_base);
1122
1123 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1124 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1125
1126 ac_lds_store(&ctx->ac, dw_addr, value);
1127 }
1128
1129 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1130 unsigned param)
1131 {
1132 LLVMBuilderRef builder = ctx->ac.builder;
1133
1134 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1135 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1136 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1137
1138 uint64_t desc2 = 0xffffffff;
1139 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1140 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1141 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1142 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1143 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1144 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1145 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1146
1147 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1148 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1149 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1150 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1151 }
1152
1153 static LLVMValueRef fetch_input_tcs(
1154 struct lp_build_tgsi_context *bld_base,
1155 const struct tgsi_full_src_register *reg,
1156 enum tgsi_opcode_type type, unsigned swizzle)
1157 {
1158 struct si_shader_context *ctx = si_shader_context(bld_base);
1159 LLVMValueRef dw_addr, stride;
1160
1161 stride = get_tcs_in_vertex_dw_stride(ctx);
1162 dw_addr = get_tcs_in_current_patch_offset(ctx);
1163 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1164
1165 return lds_load(bld_base, type, swizzle, dw_addr);
1166 }
1167
1168 static LLVMValueRef fetch_output_tcs(
1169 struct lp_build_tgsi_context *bld_base,
1170 const struct tgsi_full_src_register *reg,
1171 enum tgsi_opcode_type type, unsigned swizzle)
1172 {
1173 struct si_shader_context *ctx = si_shader_context(bld_base);
1174 LLVMValueRef dw_addr, stride;
1175
1176 if (reg->Register.Dimension) {
1177 stride = get_tcs_out_vertex_dw_stride(ctx);
1178 dw_addr = get_tcs_out_current_patch_offset(ctx);
1179 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1180 } else {
1181 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1182 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1183 }
1184
1185 return lds_load(bld_base, type, swizzle, dw_addr);
1186 }
1187
1188 static LLVMValueRef fetch_input_tes(
1189 struct lp_build_tgsi_context *bld_base,
1190 const struct tgsi_full_src_register *reg,
1191 enum tgsi_opcode_type type, unsigned swizzle)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef buffer, base, addr;
1195
1196 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1197
1198 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1199 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1200
1201 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1202 }
1203
1204 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1205 const struct tgsi_full_instruction *inst,
1206 const struct tgsi_opcode_info *info,
1207 unsigned index,
1208 LLVMValueRef dst[4])
1209 {
1210 struct si_shader_context *ctx = si_shader_context(bld_base);
1211 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1212 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1213 unsigned chan_index;
1214 LLVMValueRef dw_addr, stride;
1215 LLVMValueRef buffer, base, buf_addr;
1216 LLVMValueRef values[4];
1217 bool skip_lds_store;
1218 bool is_tess_factor = false, is_tess_inner = false;
1219
1220 /* Only handle per-patch and per-vertex outputs here.
1221 * Vectors will be lowered to scalars and this function will be called again.
1222 */
1223 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1224 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1225 si_llvm_emit_store(bld_base, inst, info, index, dst);
1226 return;
1227 }
1228
1229 if (reg->Register.Dimension) {
1230 stride = get_tcs_out_vertex_dw_stride(ctx);
1231 dw_addr = get_tcs_out_current_patch_offset(ctx);
1232 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1233 skip_lds_store = !sh_info->reads_pervertex_outputs;
1234 } else {
1235 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1236 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1237 skip_lds_store = !sh_info->reads_perpatch_outputs;
1238
1239 if (!reg->Register.Indirect) {
1240 int name = sh_info->output_semantic_name[reg->Register.Index];
1241
1242 /* Always write tess factors into LDS for the TCS epilog. */
1243 if (name == TGSI_SEMANTIC_TESSINNER ||
1244 name == TGSI_SEMANTIC_TESSOUTER) {
1245 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1246 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1247 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1248 is_tess_factor = true;
1249 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1250 }
1251 }
1252 }
1253
1254 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1255
1256 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1257 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1258
1259 uint32_t writemask = reg->Register.WriteMask;
1260 while (writemask) {
1261 chan_index = u_bit_scan(&writemask);
1262 LLVMValueRef value = dst[chan_index];
1263
1264 if (inst->Instruction.Saturate)
1265 value = ac_build_clamp(&ctx->ac, value);
1266
1267 /* Skip LDS stores if there is no LDS read of this output. */
1268 if (!skip_lds_store)
1269 lds_store(bld_base, chan_index, dw_addr, value);
1270
1271 value = ac_to_integer(&ctx->ac, value);
1272 values[chan_index] = value;
1273
1274 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1275 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1276 buf_addr, base,
1277 4 * chan_index, 1, 0, true, false);
1278 }
1279
1280 /* Write tess factors into VGPRs for the epilog. */
1281 if (is_tess_factor &&
1282 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1283 if (!is_tess_inner) {
1284 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1285 ctx->invoc0_tess_factors[chan_index]);
1286 } else if (chan_index < 2) {
1287 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1288 ctx->invoc0_tess_factors[4 + chan_index]);
1289 }
1290 }
1291 }
1292
1293 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1294 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1295 values, 4);
1296 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1297 base, 0, 1, 0, true, false);
1298 }
1299 }
1300
1301 static LLVMValueRef fetch_input_gs(
1302 struct lp_build_tgsi_context *bld_base,
1303 const struct tgsi_full_src_register *reg,
1304 enum tgsi_opcode_type type,
1305 unsigned swizzle)
1306 {
1307 struct si_shader_context *ctx = si_shader_context(bld_base);
1308 struct si_shader *shader = ctx->shader;
1309 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1310 LLVMValueRef vtx_offset, soffset;
1311 struct tgsi_shader_info *info = &shader->selector->info;
1312 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1313 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1314 unsigned param;
1315 LLVMValueRef value;
1316
1317 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1318 return get_primitive_id(ctx, swizzle);
1319
1320 if (!reg->Register.Dimension)
1321 return NULL;
1322
1323 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1324
1325 /* GFX9 has the ESGS ring in LDS. */
1326 if (ctx->screen->b.chip_class >= GFX9) {
1327 unsigned index = reg->Dimension.Index;
1328
1329 switch (index / 2) {
1330 case 0:
1331 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1332 index % 2 ? 16 : 0, 16);
1333 break;
1334 case 1:
1335 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1336 index % 2 ? 16 : 0, 16);
1337 break;
1338 case 2:
1339 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1340 index % 2 ? 16 : 0, 16);
1341 break;
1342 default:
1343 assert(0);
1344 return NULL;
1345 }
1346
1347 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1348 LLVMConstInt(ctx->i32, param * 4, 0), "");
1349 return lds_load(bld_base, type, swizzle, vtx_offset);
1350 }
1351
1352 /* GFX6: input load from the ESGS ring in memory. */
1353 if (swizzle == ~0) {
1354 LLVMValueRef values[TGSI_NUM_CHANNELS];
1355 unsigned chan;
1356 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1357 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1358 }
1359 return lp_build_gather_values(&ctx->gallivm, values,
1360 TGSI_NUM_CHANNELS);
1361 }
1362
1363 /* Get the vertex offset parameter on GFX6. */
1364 unsigned vtx_offset_param = reg->Dimension.Index;
1365 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1366
1367 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1368
1369 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1370
1371 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1372 vtx_offset, soffset, 0, 1, 0, true, false);
1373 if (tgsi_type_is_64bit(type)) {
1374 LLVMValueRef value2;
1375 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1376
1377 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1378 ctx->i32_0, vtx_offset, soffset,
1379 0, 1, 0, true, false);
1380 return si_llvm_emit_fetch_64bit(bld_base, type,
1381 value, value2);
1382 }
1383 return bitcast(bld_base, type, value);
1384 }
1385
1386 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1387 {
1388 switch (interpolate) {
1389 case TGSI_INTERPOLATE_CONSTANT:
1390 return 0;
1391
1392 case TGSI_INTERPOLATE_LINEAR:
1393 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1394 return SI_PARAM_LINEAR_SAMPLE;
1395 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1396 return SI_PARAM_LINEAR_CENTROID;
1397 else
1398 return SI_PARAM_LINEAR_CENTER;
1399 break;
1400 case TGSI_INTERPOLATE_COLOR:
1401 case TGSI_INTERPOLATE_PERSPECTIVE:
1402 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1403 return SI_PARAM_PERSP_SAMPLE;
1404 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1405 return SI_PARAM_PERSP_CENTROID;
1406 else
1407 return SI_PARAM_PERSP_CENTER;
1408 break;
1409 default:
1410 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1411 return -1;
1412 }
1413 }
1414
1415 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1416 unsigned attr_index, unsigned chan,
1417 LLVMValueRef prim_mask,
1418 LLVMValueRef i, LLVMValueRef j)
1419 {
1420 if (i || j) {
1421 return ac_build_fs_interp(&ctx->ac,
1422 LLVMConstInt(ctx->i32, chan, 0),
1423 LLVMConstInt(ctx->i32, attr_index, 0),
1424 prim_mask, i, j);
1425 }
1426 return ac_build_fs_interp_mov(&ctx->ac,
1427 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1428 LLVMConstInt(ctx->i32, chan, 0),
1429 LLVMConstInt(ctx->i32, attr_index, 0),
1430 prim_mask);
1431 }
1432
1433 /**
1434 * Interpolate a fragment shader input.
1435 *
1436 * @param ctx context
1437 * @param input_index index of the input in hardware
1438 * @param semantic_name TGSI_SEMANTIC_*
1439 * @param semantic_index semantic index
1440 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1441 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1442 * @param interp_param interpolation weights (i,j)
1443 * @param prim_mask SI_PARAM_PRIM_MASK
1444 * @param face SI_PARAM_FRONT_FACE
1445 * @param result the return value (4 components)
1446 */
1447 static void interp_fs_input(struct si_shader_context *ctx,
1448 unsigned input_index,
1449 unsigned semantic_name,
1450 unsigned semantic_index,
1451 unsigned num_interp_inputs,
1452 unsigned colors_read_mask,
1453 LLVMValueRef interp_param,
1454 LLVMValueRef prim_mask,
1455 LLVMValueRef face,
1456 LLVMValueRef result[4])
1457 {
1458 LLVMValueRef i = NULL, j = NULL;
1459 unsigned chan;
1460
1461 /* fs.constant returns the param from the middle vertex, so it's not
1462 * really useful for flat shading. It's meant to be used for custom
1463 * interpolation (but the intrinsic can't fetch from the other two
1464 * vertices).
1465 *
1466 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1467 * to do the right thing. The only reason we use fs.constant is that
1468 * fs.interp cannot be used on integers, because they can be equal
1469 * to NaN.
1470 *
1471 * When interp is false we will use fs.constant or for newer llvm,
1472 * amdgcn.interp.mov.
1473 */
1474 bool interp = interp_param != NULL;
1475
1476 if (interp) {
1477 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1478 LLVMVectorType(ctx->f32, 2), "");
1479
1480 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1481 ctx->i32_0, "");
1482 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1483 ctx->i32_1, "");
1484 }
1485
1486 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1487 ctx->shader->key.part.ps.prolog.color_two_side) {
1488 LLVMValueRef is_face_positive;
1489
1490 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1491 * otherwise it's at offset "num_inputs".
1492 */
1493 unsigned back_attr_offset = num_interp_inputs;
1494 if (semantic_index == 1 && colors_read_mask & 0xf)
1495 back_attr_offset += 1;
1496
1497 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1498 face, ctx->i32_0, "");
1499
1500 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1501 LLVMValueRef front, back;
1502
1503 front = si_build_fs_interp(ctx,
1504 input_index, chan,
1505 prim_mask, i, j);
1506 back = si_build_fs_interp(ctx,
1507 back_attr_offset, chan,
1508 prim_mask, i, j);
1509
1510 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1511 is_face_positive,
1512 front,
1513 back,
1514 "");
1515 }
1516 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1517 result[0] = si_build_fs_interp(ctx, input_index,
1518 0, prim_mask, i, j);
1519 result[1] =
1520 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1521 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1522 } else {
1523 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1524 result[chan] = si_build_fs_interp(ctx,
1525 input_index, chan,
1526 prim_mask, i, j);
1527 }
1528 }
1529 }
1530
1531 void si_llvm_load_input_fs(
1532 struct si_shader_context *ctx,
1533 unsigned input_index,
1534 LLVMValueRef out[4])
1535 {
1536 struct lp_build_context *base = &ctx->bld_base.base;
1537 struct si_shader *shader = ctx->shader;
1538 struct tgsi_shader_info *info = &shader->selector->info;
1539 LLVMValueRef main_fn = ctx->main_fn;
1540 LLVMValueRef interp_param = NULL;
1541 int interp_param_idx;
1542 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1543 unsigned semantic_index = info->input_semantic_index[input_index];
1544 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1545 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1546
1547 /* Get colors from input VGPRs (set by the prolog). */
1548 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1549 unsigned colors_read = shader->selector->info.colors_read;
1550 unsigned mask = colors_read >> (semantic_index * 4);
1551 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1552 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1553
1554 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1555 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1556 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1557 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1558 return;
1559 }
1560
1561 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1562 if (interp_param_idx == -1)
1563 return;
1564 else if (interp_param_idx) {
1565 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1566 }
1567
1568 interp_fs_input(ctx, input_index, semantic_name,
1569 semantic_index, 0, /* this param is unused */
1570 shader->selector->info.colors_read, interp_param,
1571 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1572 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1573 &out[0]);
1574 }
1575
1576 static void declare_input_fs(
1577 struct si_shader_context *ctx,
1578 unsigned input_index,
1579 const struct tgsi_full_declaration *decl,
1580 LLVMValueRef out[4])
1581 {
1582 si_llvm_load_input_fs(ctx, input_index, out);
1583 }
1584
1585 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1586 {
1587 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1588 }
1589
1590
1591 /**
1592 * Load a dword from a constant buffer.
1593 */
1594 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1595 LLVMValueRef resource,
1596 LLVMValueRef offset)
1597 {
1598 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1599 0, 0, 0, true, true);
1600 }
1601
1602 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1603 {
1604 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1605 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1606 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1607 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1608
1609 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1610 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1611 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1612
1613 LLVMValueRef pos[4] = {
1614 buffer_load_const(ctx, resource, offset0),
1615 buffer_load_const(ctx, resource, offset1),
1616 LLVMConstReal(ctx->f32, 0),
1617 LLVMConstReal(ctx->f32, 0)
1618 };
1619
1620 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1621 }
1622
1623 void si_load_system_value(struct si_shader_context *ctx,
1624 unsigned index,
1625 const struct tgsi_full_declaration *decl)
1626 {
1627 struct lp_build_context *bld = &ctx->bld_base.base;
1628 LLVMValueRef value = 0;
1629
1630 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1631
1632 switch (decl->Semantic.Name) {
1633 case TGSI_SEMANTIC_INSTANCEID:
1634 value = ctx->abi.instance_id;
1635 break;
1636
1637 case TGSI_SEMANTIC_VERTEXID:
1638 value = LLVMBuildAdd(ctx->ac.builder,
1639 ctx->abi.vertex_id,
1640 ctx->abi.base_vertex, "");
1641 break;
1642
1643 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1644 /* Unused. Clarify the meaning in indexed vs. non-indexed
1645 * draws if this is ever used again. */
1646 assert(false);
1647 break;
1648
1649 case TGSI_SEMANTIC_BASEVERTEX:
1650 {
1651 /* For non-indexed draws, the base vertex set by the driver
1652 * (for direct draws) or the CP (for indirect draws) is the
1653 * first vertex ID, but GLSL expects 0 to be returned.
1654 */
1655 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1656 LLVMValueRef indexed;
1657
1658 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1659 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1660
1661 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1662 ctx->abi.base_vertex, ctx->i32_0, "");
1663 break;
1664 }
1665
1666 case TGSI_SEMANTIC_BASEINSTANCE:
1667 value = ctx->abi.start_instance;
1668 break;
1669
1670 case TGSI_SEMANTIC_DRAWID:
1671 value = ctx->abi.draw_id;
1672 break;
1673
1674 case TGSI_SEMANTIC_INVOCATIONID:
1675 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1676 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1677 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1678 value = ctx->abi.gs_invocation_id;
1679 else
1680 assert(!"INVOCATIONID not implemented");
1681 break;
1682
1683 case TGSI_SEMANTIC_POSITION:
1684 {
1685 LLVMValueRef pos[4] = {
1686 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1687 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1688 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1689 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1690 LLVMGetParam(ctx->main_fn,
1691 SI_PARAM_POS_W_FLOAT)),
1692 };
1693 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1694 break;
1695 }
1696
1697 case TGSI_SEMANTIC_FACE:
1698 value = ctx->abi.front_face;
1699 break;
1700
1701 case TGSI_SEMANTIC_SAMPLEID:
1702 value = get_sample_id(ctx);
1703 break;
1704
1705 case TGSI_SEMANTIC_SAMPLEPOS: {
1706 LLVMValueRef pos[4] = {
1707 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1708 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1709 LLVMConstReal(ctx->f32, 0),
1710 LLVMConstReal(ctx->f32, 0)
1711 };
1712 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1713 TGSI_OPCODE_FRC, pos[0]);
1714 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1715 TGSI_OPCODE_FRC, pos[1]);
1716 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1717 break;
1718 }
1719
1720 case TGSI_SEMANTIC_SAMPLEMASK:
1721 /* This can only occur with the OpenGL Core profile, which
1722 * doesn't support smoothing.
1723 */
1724 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1725 break;
1726
1727 case TGSI_SEMANTIC_TESSCOORD:
1728 {
1729 LLVMValueRef coord[4] = {
1730 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1731 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1732 ctx->ac.f32_0,
1733 ctx->ac.f32_0
1734 };
1735
1736 /* For triangles, the vector should be (u, v, 1-u-v). */
1737 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1738 PIPE_PRIM_TRIANGLES)
1739 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1740 lp_build_add(bld, coord[0], coord[1]));
1741
1742 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1743 break;
1744 }
1745
1746 case TGSI_SEMANTIC_VERTICESIN:
1747 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1748 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1749 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1750 value = get_num_tcs_out_vertices(ctx);
1751 else
1752 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1753 break;
1754
1755 case TGSI_SEMANTIC_TESSINNER:
1756 case TGSI_SEMANTIC_TESSOUTER:
1757 {
1758 LLVMValueRef buffer, base, addr;
1759 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1760
1761 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1762
1763 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1764 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1765 LLVMConstInt(ctx->i32, param, 0));
1766
1767 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1768 ~0, buffer, base, addr, true);
1769
1770 break;
1771 }
1772
1773 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1774 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1775 {
1776 LLVMValueRef buf, slot, val[4];
1777 int i, offset;
1778
1779 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1780 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1781 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1782 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1783
1784 for (i = 0; i < 4; i++)
1785 val[i] = buffer_load_const(ctx, buf,
1786 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1787 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1788 break;
1789 }
1790
1791 case TGSI_SEMANTIC_PRIMID:
1792 value = get_primitive_id(ctx, 0);
1793 break;
1794
1795 case TGSI_SEMANTIC_GRID_SIZE:
1796 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1797 break;
1798
1799 case TGSI_SEMANTIC_BLOCK_SIZE:
1800 {
1801 LLVMValueRef values[3];
1802 unsigned i;
1803 unsigned *properties = ctx->shader->selector->info.properties;
1804
1805 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1806 unsigned sizes[3] = {
1807 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1808 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1809 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1810 };
1811
1812 for (i = 0; i < 3; ++i)
1813 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1814
1815 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1816 } else {
1817 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1818 }
1819 break;
1820 }
1821
1822 case TGSI_SEMANTIC_BLOCK_ID:
1823 {
1824 LLVMValueRef values[3];
1825
1826 for (int i = 0; i < 3; i++) {
1827 values[i] = ctx->i32_0;
1828 if (ctx->param_block_id[i] >= 0) {
1829 values[i] = LLVMGetParam(ctx->main_fn,
1830 ctx->param_block_id[i]);
1831 }
1832 }
1833 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1834 break;
1835 }
1836
1837 case TGSI_SEMANTIC_THREAD_ID:
1838 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1839 break;
1840
1841 case TGSI_SEMANTIC_HELPER_INVOCATION:
1842 value = lp_build_intrinsic(ctx->ac.builder,
1843 "llvm.amdgcn.ps.live",
1844 ctx->i1, NULL, 0,
1845 LP_FUNC_ATTR_READNONE);
1846 value = LLVMBuildNot(ctx->ac.builder, value, "");
1847 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1848 break;
1849
1850 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1851 value = LLVMConstInt(ctx->i32, 64, 0);
1852 break;
1853
1854 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1855 value = ac_get_thread_id(&ctx->ac);
1856 break;
1857
1858 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1859 {
1860 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1861 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1862 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1863 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1864 break;
1865 }
1866
1867 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1868 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1869 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1870 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1871 {
1872 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1873 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1874 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1875 /* All bits set except LSB */
1876 value = LLVMConstInt(ctx->i64, -2, 0);
1877 } else {
1878 /* All bits set */
1879 value = LLVMConstInt(ctx->i64, -1, 0);
1880 }
1881 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1882 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1883 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1884 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1885 value = LLVMBuildNot(ctx->ac.builder, value, "");
1886 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1887 break;
1888 }
1889
1890 default:
1891 assert(!"unknown system value");
1892 return;
1893 }
1894
1895 ctx->system_values[index] = value;
1896 }
1897
1898 void si_declare_compute_memory(struct si_shader_context *ctx,
1899 const struct tgsi_full_declaration *decl)
1900 {
1901 struct si_shader_selector *sel = ctx->shader->selector;
1902
1903 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1904 LLVMValueRef var;
1905
1906 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1907 assert(decl->Range.First == decl->Range.Last);
1908 assert(!ctx->ac.lds);
1909
1910 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1911 LLVMArrayType(ctx->i8, sel->local_size),
1912 "compute_lds",
1913 LOCAL_ADDR_SPACE);
1914 LLVMSetAlignment(var, 4);
1915
1916 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1917 }
1918
1919 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1920 {
1921 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1922 ctx->param_const_and_shader_buffers);
1923
1924 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1925 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1926 }
1927
1928 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1929 {
1930 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1931 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1932
1933 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1934 index = LLVMBuildAdd(ctx->ac.builder, index,
1935 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1936
1937 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1938 }
1939
1940 static LLVMValueRef
1941 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1942 {
1943 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1944 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1945 ctx->param_const_and_shader_buffers);
1946
1947 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1948 index = LLVMBuildSub(ctx->ac.builder,
1949 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1950 index, "");
1951
1952 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1953 }
1954
1955 static LLVMValueRef fetch_constant(
1956 struct lp_build_tgsi_context *bld_base,
1957 const struct tgsi_full_src_register *reg,
1958 enum tgsi_opcode_type type,
1959 unsigned swizzle)
1960 {
1961 struct si_shader_context *ctx = si_shader_context(bld_base);
1962 struct si_shader_selector *sel = ctx->shader->selector;
1963 const struct tgsi_ind_register *ireg = &reg->Indirect;
1964 unsigned buf, idx;
1965
1966 LLVMValueRef addr, bufp;
1967
1968 if (swizzle == LP_CHAN_ALL) {
1969 unsigned chan;
1970 LLVMValueRef values[4];
1971 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1972 values[chan] = fetch_constant(bld_base, reg, type, chan);
1973
1974 return lp_build_gather_values(&ctx->gallivm, values, 4);
1975 }
1976
1977 /* Split 64-bit loads. */
1978 if (tgsi_type_is_64bit(type)) {
1979 LLVMValueRef lo, hi;
1980
1981 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
1982 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
1983 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1984 }
1985
1986 idx = reg->Register.Index * 4 + swizzle;
1987 if (reg->Register.Indirect) {
1988 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
1989 } else {
1990 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1991 }
1992
1993 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
1994 if (sel->info.const_buffers_declared == 1 &&
1995 sel->info.shader_buffers_declared == 0) {
1996 LLVMValueRef ptr =
1997 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1998
1999 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2000 * loads, and up to x4 load opcode merging. However, it leads to horrible
2001 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2002 *
2003 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2004 *
2005 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2006 * a descriptor and s_buffer_load_dword using it, so we can't expand
2007 * the pointer into a full descriptor like below. We have to use
2008 * s_load_dword instead. The only case when LLVM 5.0 would select
2009 * s_buffer_load_dword (that we have to prevent) is when we use use
2010 * a literal offset where we don't need bounds checking.
2011 */
2012 if (ctx->screen->b.chip_class == SI &&
2013 HAVE_LLVM < 0x0600 &&
2014 !reg->Register.Indirect) {
2015 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2016 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2017 return bitcast(bld_base, type, result);
2018 }
2019
2020 /* Do the bounds checking with a descriptor, because
2021 * doing computation and manual bounds checking of 64-bit
2022 * addresses generates horrible VALU code with very high
2023 * VGPR usage and very low SIMD occupancy.
2024 */
2025 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2026 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2027
2028 LLVMValueRef desc_elems[] = {
2029 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2030 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2031 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2032 LLVMConstInt(ctx->i32,
2033 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2034 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2035 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2036 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2037 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2038 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2039 };
2040 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2041 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2042 return bitcast(bld_base, type, result);
2043 }
2044
2045 assert(reg->Register.Dimension);
2046 buf = reg->Dimension.Index;
2047
2048 if (reg->Dimension.Indirect) {
2049 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2050 LLVMValueRef index;
2051 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2052 reg->Dimension.Index,
2053 ctx->num_const_buffers);
2054 index = LLVMBuildAdd(ctx->ac.builder, index,
2055 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2056 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2057 } else
2058 bufp = load_const_buffer_desc(ctx, buf);
2059
2060 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2061 }
2062
2063 /* Upper 16 bits must be zero. */
2064 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2065 LLVMValueRef val[2])
2066 {
2067 return LLVMBuildOr(ctx->ac.builder, val[0],
2068 LLVMBuildShl(ctx->ac.builder, val[1],
2069 LLVMConstInt(ctx->i32, 16, 0),
2070 ""), "");
2071 }
2072
2073 /* Upper 16 bits are ignored and will be dropped. */
2074 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2075 LLVMValueRef val[2])
2076 {
2077 LLVMValueRef v[2] = {
2078 LLVMBuildAnd(ctx->ac.builder, val[0],
2079 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2080 val[1],
2081 };
2082 return si_llvm_pack_two_int16(ctx, v);
2083 }
2084
2085 /* Initialize arguments for the shader export intrinsic */
2086 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
2087 LLVMValueRef *values,
2088 unsigned target,
2089 struct ac_export_args *args)
2090 {
2091 struct si_shader_context *ctx = si_shader_context(bld_base);
2092 struct lp_build_context *base = &bld_base->base;
2093 LLVMBuilderRef builder = ctx->ac.builder;
2094 LLVMValueRef val[4];
2095 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2096 unsigned chan;
2097 bool is_int8, is_int10;
2098
2099 /* Default is 0xf. Adjusted below depending on the format. */
2100 args->enabled_channels = 0xf; /* writemask */
2101
2102 /* Specify whether the EXEC mask represents the valid mask */
2103 args->valid_mask = 0;
2104
2105 /* Specify whether this is the last export */
2106 args->done = 0;
2107
2108 /* Specify the target we are exporting */
2109 args->target = target;
2110
2111 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2112 const struct si_shader_key *key = &ctx->shader->key;
2113 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2114 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2115
2116 assert(cbuf >= 0 && cbuf < 8);
2117 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2118 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2119 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2120 }
2121
2122 args->compr = false;
2123 args->out[0] = base->undef;
2124 args->out[1] = base->undef;
2125 args->out[2] = base->undef;
2126 args->out[3] = base->undef;
2127
2128 switch (spi_shader_col_format) {
2129 case V_028714_SPI_SHADER_ZERO:
2130 args->enabled_channels = 0; /* writemask */
2131 args->target = V_008DFC_SQ_EXP_NULL;
2132 break;
2133
2134 case V_028714_SPI_SHADER_32_R:
2135 args->enabled_channels = 1; /* writemask */
2136 args->out[0] = values[0];
2137 break;
2138
2139 case V_028714_SPI_SHADER_32_GR:
2140 args->enabled_channels = 0x3; /* writemask */
2141 args->out[0] = values[0];
2142 args->out[1] = values[1];
2143 break;
2144
2145 case V_028714_SPI_SHADER_32_AR:
2146 args->enabled_channels = 0x9; /* writemask */
2147 args->out[0] = values[0];
2148 args->out[3] = values[3];
2149 break;
2150
2151 case V_028714_SPI_SHADER_FP16_ABGR:
2152 args->compr = 1; /* COMPR flag */
2153
2154 for (chan = 0; chan < 2; chan++) {
2155 LLVMValueRef pack_args[2] = {
2156 values[2 * chan],
2157 values[2 * chan + 1]
2158 };
2159 LLVMValueRef packed;
2160
2161 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2162 args->out[chan] = ac_to_float(&ctx->ac, packed);
2163 }
2164 break;
2165
2166 case V_028714_SPI_SHADER_UNORM16_ABGR:
2167 for (chan = 0; chan < 4; chan++) {
2168 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2169 val[chan] = LLVMBuildFMul(builder, val[chan],
2170 LLVMConstReal(ctx->f32, 65535), "");
2171 val[chan] = LLVMBuildFAdd(builder, val[chan],
2172 LLVMConstReal(ctx->f32, 0.5), "");
2173 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2174 ctx->i32, "");
2175 }
2176
2177 args->compr = 1; /* COMPR flag */
2178 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2179 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2180 break;
2181
2182 case V_028714_SPI_SHADER_SNORM16_ABGR:
2183 for (chan = 0; chan < 4; chan++) {
2184 /* Clamp between [-1, 1]. */
2185 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2186 values[chan],
2187 LLVMConstReal(ctx->f32, 1));
2188 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2189 val[chan],
2190 LLVMConstReal(ctx->f32, -1));
2191 /* Convert to a signed integer in [-32767, 32767]. */
2192 val[chan] = LLVMBuildFMul(builder, val[chan],
2193 LLVMConstReal(ctx->f32, 32767), "");
2194 /* If positive, add 0.5, else add -0.5. */
2195 val[chan] = LLVMBuildFAdd(builder, val[chan],
2196 LLVMBuildSelect(builder,
2197 LLVMBuildFCmp(builder, LLVMRealOGE,
2198 val[chan], ctx->ac.f32_0, ""),
2199 LLVMConstReal(ctx->f32, 0.5),
2200 LLVMConstReal(ctx->f32, -0.5), ""), "");
2201 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2202 }
2203
2204 args->compr = 1; /* COMPR flag */
2205 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2206 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2207 break;
2208
2209 case V_028714_SPI_SHADER_UINT16_ABGR: {
2210 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2211 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2212 LLVMValueRef max_alpha =
2213 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2214
2215 /* Clamp. */
2216 for (chan = 0; chan < 4; chan++) {
2217 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2218 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2219 val[chan],
2220 chan == 3 ? max_alpha : max_rgb);
2221 }
2222
2223 args->compr = 1; /* COMPR flag */
2224 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2225 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2226 break;
2227 }
2228
2229 case V_028714_SPI_SHADER_SINT16_ABGR: {
2230 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2231 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2232 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2233 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2234 LLVMValueRef max_alpha =
2235 !is_int10 ? max_rgb : ctx->i32_1;
2236 LLVMValueRef min_alpha =
2237 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2238
2239 /* Clamp. */
2240 for (chan = 0; chan < 4; chan++) {
2241 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2242 val[chan] = lp_build_emit_llvm_binary(bld_base,
2243 TGSI_OPCODE_IMIN,
2244 val[chan], chan == 3 ? max_alpha : max_rgb);
2245 val[chan] = lp_build_emit_llvm_binary(bld_base,
2246 TGSI_OPCODE_IMAX,
2247 val[chan], chan == 3 ? min_alpha : min_rgb);
2248 }
2249
2250 args->compr = 1; /* COMPR flag */
2251 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2252 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2253 break;
2254 }
2255
2256 case V_028714_SPI_SHADER_32_ABGR:
2257 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2258 break;
2259 }
2260 }
2261
2262 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2263 LLVMValueRef alpha)
2264 {
2265 struct si_shader_context *ctx = si_shader_context(bld_base);
2266
2267 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2268 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2269 [PIPE_FUNC_LESS] = LLVMRealOLT,
2270 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2271 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2272 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2273 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2274 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2275 };
2276 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2277 assert(cond);
2278
2279 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2280 SI_PARAM_ALPHA_REF);
2281 LLVMValueRef alpha_pass =
2282 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2283 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2284 } else {
2285 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2286 }
2287 }
2288
2289 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2290 LLVMValueRef alpha,
2291 unsigned samplemask_param)
2292 {
2293 struct si_shader_context *ctx = si_shader_context(bld_base);
2294 LLVMValueRef coverage;
2295
2296 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2297 coverage = LLVMGetParam(ctx->main_fn,
2298 samplemask_param);
2299 coverage = ac_to_integer(&ctx->ac, coverage);
2300
2301 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2302 ctx->i32,
2303 &coverage, 1, LP_FUNC_ATTR_READNONE);
2304
2305 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2306 ctx->f32, "");
2307
2308 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2309 LLVMConstReal(ctx->f32,
2310 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2311
2312 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2313 }
2314
2315 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2316 struct ac_export_args *pos, LLVMValueRef *out_elts)
2317 {
2318 struct si_shader_context *ctx = si_shader_context(bld_base);
2319 struct lp_build_context *base = &bld_base->base;
2320 unsigned reg_index;
2321 unsigned chan;
2322 unsigned const_chan;
2323 LLVMValueRef base_elt;
2324 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2325 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2326 SI_VS_CONST_CLIP_PLANES, 0);
2327 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2328
2329 for (reg_index = 0; reg_index < 2; reg_index ++) {
2330 struct ac_export_args *args = &pos[2 + reg_index];
2331
2332 args->out[0] =
2333 args->out[1] =
2334 args->out[2] =
2335 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2336
2337 /* Compute dot products of position and user clip plane vectors */
2338 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2339 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2340 LLVMValueRef addr =
2341 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2342 const_chan) * 4, 0);
2343 base_elt = buffer_load_const(ctx, const_resource,
2344 addr);
2345 args->out[chan] =
2346 lp_build_add(base, args->out[chan],
2347 lp_build_mul(base, base_elt,
2348 out_elts[const_chan]));
2349 }
2350 }
2351
2352 args->enabled_channels = 0xf;
2353 args->valid_mask = 0;
2354 args->done = 0;
2355 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2356 args->compr = 0;
2357 }
2358 }
2359
2360 static void si_dump_streamout(struct pipe_stream_output_info *so)
2361 {
2362 unsigned i;
2363
2364 if (so->num_outputs)
2365 fprintf(stderr, "STREAMOUT\n");
2366
2367 for (i = 0; i < so->num_outputs; i++) {
2368 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2369 so->output[i].start_component;
2370 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2371 i, so->output[i].output_buffer,
2372 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2373 so->output[i].register_index,
2374 mask & 1 ? "x" : "",
2375 mask & 2 ? "y" : "",
2376 mask & 4 ? "z" : "",
2377 mask & 8 ? "w" : "");
2378 }
2379 }
2380
2381 static void emit_streamout_output(struct si_shader_context *ctx,
2382 LLVMValueRef const *so_buffers,
2383 LLVMValueRef const *so_write_offsets,
2384 struct pipe_stream_output *stream_out,
2385 struct si_shader_output_values *shader_out)
2386 {
2387 unsigned buf_idx = stream_out->output_buffer;
2388 unsigned start = stream_out->start_component;
2389 unsigned num_comps = stream_out->num_components;
2390 LLVMValueRef out[4];
2391
2392 assert(num_comps && num_comps <= 4);
2393 if (!num_comps || num_comps > 4)
2394 return;
2395
2396 /* Load the output as int. */
2397 for (int j = 0; j < num_comps; j++) {
2398 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2399
2400 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2401 }
2402
2403 /* Pack the output. */
2404 LLVMValueRef vdata = NULL;
2405
2406 switch (num_comps) {
2407 case 1: /* as i32 */
2408 vdata = out[0];
2409 break;
2410 case 2: /* as v2i32 */
2411 case 3: /* as v4i32 (aligned to 4) */
2412 case 4: /* as v4i32 */
2413 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2414 for (int j = 0; j < num_comps; j++) {
2415 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2416 LLVMConstInt(ctx->i32, j, 0), "");
2417 }
2418 break;
2419 }
2420
2421 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2422 vdata, num_comps,
2423 so_write_offsets[buf_idx],
2424 ctx->i32_0,
2425 stream_out->dst_offset * 4, 1, 1, true, false);
2426 }
2427
2428 /**
2429 * Write streamout data to buffers for vertex stream @p stream (different
2430 * vertex streams can occur for GS copy shaders).
2431 */
2432 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2433 struct si_shader_output_values *outputs,
2434 unsigned noutput, unsigned stream)
2435 {
2436 struct si_shader_selector *sel = ctx->shader->selector;
2437 struct pipe_stream_output_info *so = &sel->so;
2438 LLVMBuilderRef builder = ctx->ac.builder;
2439 int i;
2440 struct lp_build_if_state if_ctx;
2441
2442 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2443 LLVMValueRef so_vtx_count =
2444 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2445
2446 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2447
2448 /* can_emit = tid < so_vtx_count; */
2449 LLVMValueRef can_emit =
2450 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2451
2452 /* Emit the streamout code conditionally. This actually avoids
2453 * out-of-bounds buffer access. The hw tells us via the SGPR
2454 * (so_vtx_count) which threads are allowed to emit streamout data. */
2455 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2456 {
2457 /* The buffer offset is computed as follows:
2458 * ByteOffset = streamout_offset[buffer_id]*4 +
2459 * (streamout_write_index + thread_id)*stride[buffer_id] +
2460 * attrib_offset
2461 */
2462
2463 LLVMValueRef so_write_index =
2464 LLVMGetParam(ctx->main_fn,
2465 ctx->param_streamout_write_index);
2466
2467 /* Compute (streamout_write_index + thread_id). */
2468 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2469
2470 /* Load the descriptor and compute the write offset for each
2471 * enabled buffer. */
2472 LLVMValueRef so_write_offset[4] = {};
2473 LLVMValueRef so_buffers[4];
2474 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2475 ctx->param_rw_buffers);
2476
2477 for (i = 0; i < 4; i++) {
2478 if (!so->stride[i])
2479 continue;
2480
2481 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2482 SI_VS_STREAMOUT_BUF0 + i, 0);
2483
2484 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2485
2486 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2487 ctx->param_streamout_offset[i]);
2488 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2489
2490 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2491 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2492 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2493 }
2494
2495 /* Write streamout data. */
2496 for (i = 0; i < so->num_outputs; i++) {
2497 unsigned reg = so->output[i].register_index;
2498
2499 if (reg >= noutput)
2500 continue;
2501
2502 if (stream != so->output[i].stream)
2503 continue;
2504
2505 emit_streamout_output(ctx, so_buffers, so_write_offset,
2506 &so->output[i], &outputs[reg]);
2507 }
2508 }
2509 lp_build_endif(&if_ctx);
2510 }
2511
2512 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2513 LLVMValueRef *values)
2514 {
2515 struct ac_export_args args;
2516
2517 si_llvm_init_export_args(&ctx->bld_base, values,
2518 V_008DFC_SQ_EXP_PARAM + index, &args);
2519 ac_build_export(&ctx->ac, &args);
2520 }
2521
2522 static void si_build_param_exports(struct si_shader_context *ctx,
2523 struct si_shader_output_values *outputs,
2524 unsigned noutput)
2525 {
2526 struct si_shader *shader = ctx->shader;
2527 unsigned param_count = 0;
2528
2529 for (unsigned i = 0; i < noutput; i++) {
2530 unsigned semantic_name = outputs[i].semantic_name;
2531 unsigned semantic_index = outputs[i].semantic_index;
2532
2533 if (outputs[i].vertex_stream[0] != 0 &&
2534 outputs[i].vertex_stream[1] != 0 &&
2535 outputs[i].vertex_stream[2] != 0 &&
2536 outputs[i].vertex_stream[3] != 0)
2537 continue;
2538
2539 switch (semantic_name) {
2540 case TGSI_SEMANTIC_LAYER:
2541 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2542 case TGSI_SEMANTIC_CLIPDIST:
2543 case TGSI_SEMANTIC_COLOR:
2544 case TGSI_SEMANTIC_BCOLOR:
2545 case TGSI_SEMANTIC_PRIMID:
2546 case TGSI_SEMANTIC_FOG:
2547 case TGSI_SEMANTIC_TEXCOORD:
2548 case TGSI_SEMANTIC_GENERIC:
2549 break;
2550 default:
2551 continue;
2552 }
2553
2554 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2555 semantic_index < SI_MAX_IO_GENERIC) &&
2556 shader->key.opt.kill_outputs &
2557 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2558 continue;
2559
2560 si_export_param(ctx, param_count, outputs[i].values);
2561
2562 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2563 shader->info.vs_output_param_offset[i] = param_count++;
2564 }
2565
2566 shader->info.nr_param_exports = param_count;
2567 }
2568
2569 /* Generate export instructions for hardware VS shader stage */
2570 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2571 struct si_shader_output_values *outputs,
2572 unsigned noutput)
2573 {
2574 struct si_shader_context *ctx = si_shader_context(bld_base);
2575 struct si_shader *shader = ctx->shader;
2576 struct ac_export_args pos_args[4] = {};
2577 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2578 unsigned pos_idx;
2579 int i;
2580
2581 /* Build position exports. */
2582 for (i = 0; i < noutput; i++) {
2583 switch (outputs[i].semantic_name) {
2584 case TGSI_SEMANTIC_POSITION:
2585 si_llvm_init_export_args(bld_base, outputs[i].values,
2586 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2587 break;
2588 case TGSI_SEMANTIC_PSIZE:
2589 psize_value = outputs[i].values[0];
2590 break;
2591 case TGSI_SEMANTIC_LAYER:
2592 layer_value = outputs[i].values[0];
2593 break;
2594 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2595 viewport_index_value = outputs[i].values[0];
2596 break;
2597 case TGSI_SEMANTIC_EDGEFLAG:
2598 edgeflag_value = outputs[i].values[0];
2599 break;
2600 case TGSI_SEMANTIC_CLIPDIST:
2601 if (!shader->key.opt.clip_disable) {
2602 unsigned index = 2 + outputs[i].semantic_index;
2603 si_llvm_init_export_args(bld_base, outputs[i].values,
2604 V_008DFC_SQ_EXP_POS + index,
2605 &pos_args[index]);
2606 }
2607 break;
2608 case TGSI_SEMANTIC_CLIPVERTEX:
2609 if (!shader->key.opt.clip_disable) {
2610 si_llvm_emit_clipvertex(bld_base, pos_args,
2611 outputs[i].values);
2612 }
2613 break;
2614 }
2615 }
2616
2617 /* We need to add the position output manually if it's missing. */
2618 if (!pos_args[0].out[0]) {
2619 pos_args[0].enabled_channels = 0xf; /* writemask */
2620 pos_args[0].valid_mask = 0; /* EXEC mask */
2621 pos_args[0].done = 0; /* last export? */
2622 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2623 pos_args[0].compr = 0; /* COMPR flag */
2624 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2625 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2626 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2627 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2628 }
2629
2630 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2631 if (shader->selector->info.writes_psize ||
2632 shader->selector->info.writes_edgeflag ||
2633 shader->selector->info.writes_viewport_index ||
2634 shader->selector->info.writes_layer) {
2635 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2636 (shader->selector->info.writes_edgeflag << 1) |
2637 (shader->selector->info.writes_layer << 2);
2638
2639 pos_args[1].valid_mask = 0; /* EXEC mask */
2640 pos_args[1].done = 0; /* last export? */
2641 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2642 pos_args[1].compr = 0; /* COMPR flag */
2643 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2644 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2645 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2646 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2647
2648 if (shader->selector->info.writes_psize)
2649 pos_args[1].out[0] = psize_value;
2650
2651 if (shader->selector->info.writes_edgeflag) {
2652 /* The output is a float, but the hw expects an integer
2653 * with the first bit containing the edge flag. */
2654 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2655 edgeflag_value,
2656 ctx->i32, "");
2657 edgeflag_value = ac_build_umin(&ctx->ac,
2658 edgeflag_value,
2659 ctx->i32_1);
2660
2661 /* The LLVM intrinsic expects a float. */
2662 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2663 }
2664
2665 if (ctx->screen->b.chip_class >= GFX9) {
2666 /* GFX9 has the layer in out.z[10:0] and the viewport
2667 * index in out.z[19:16].
2668 */
2669 if (shader->selector->info.writes_layer)
2670 pos_args[1].out[2] = layer_value;
2671
2672 if (shader->selector->info.writes_viewport_index) {
2673 LLVMValueRef v = viewport_index_value;
2674
2675 v = ac_to_integer(&ctx->ac, v);
2676 v = LLVMBuildShl(ctx->ac.builder, v,
2677 LLVMConstInt(ctx->i32, 16, 0), "");
2678 v = LLVMBuildOr(ctx->ac.builder, v,
2679 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2680 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2681 pos_args[1].enabled_channels |= 1 << 2;
2682 }
2683 } else {
2684 if (shader->selector->info.writes_layer)
2685 pos_args[1].out[2] = layer_value;
2686
2687 if (shader->selector->info.writes_viewport_index) {
2688 pos_args[1].out[3] = viewport_index_value;
2689 pos_args[1].enabled_channels |= 1 << 3;
2690 }
2691 }
2692 }
2693
2694 for (i = 0; i < 4; i++)
2695 if (pos_args[i].out[0])
2696 shader->info.nr_pos_exports++;
2697
2698 pos_idx = 0;
2699 for (i = 0; i < 4; i++) {
2700 if (!pos_args[i].out[0])
2701 continue;
2702
2703 /* Specify the target we are exporting */
2704 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2705
2706 if (pos_idx == shader->info.nr_pos_exports)
2707 /* Specify that this is the last export */
2708 pos_args[i].done = 1;
2709
2710 ac_build_export(&ctx->ac, &pos_args[i]);
2711 }
2712
2713 /* Build parameter exports. */
2714 si_build_param_exports(ctx, outputs, noutput);
2715 }
2716
2717 /**
2718 * Forward all outputs from the vertex shader to the TES. This is only used
2719 * for the fixed function TCS.
2720 */
2721 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2722 {
2723 struct si_shader_context *ctx = si_shader_context(bld_base);
2724 LLVMValueRef invocation_id, buffer, buffer_offset;
2725 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2726 uint64_t inputs;
2727
2728 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2729 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2730 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2731
2732 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2733 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2734 lds_vertex_stride, "");
2735 lds_base = get_tcs_in_current_patch_offset(ctx);
2736 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2737
2738 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2739 while (inputs) {
2740 unsigned i = u_bit_scan64(&inputs);
2741
2742 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2743 LLVMConstInt(ctx->i32, 4 * i, 0),
2744 "");
2745
2746 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2747 get_rel_patch_id(ctx),
2748 invocation_id,
2749 LLVMConstInt(ctx->i32, i, 0));
2750
2751 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2752 lds_ptr);
2753
2754 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2755 buffer_offset, 0, 1, 0, true, false);
2756 }
2757 }
2758
2759 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2760 LLVMValueRef rel_patch_id,
2761 LLVMValueRef invocation_id,
2762 LLVMValueRef tcs_out_current_patch_data_offset,
2763 LLVMValueRef invoc0_tf_outer[4],
2764 LLVMValueRef invoc0_tf_inner[2])
2765 {
2766 struct si_shader_context *ctx = si_shader_context(bld_base);
2767 struct si_shader *shader = ctx->shader;
2768 unsigned tess_inner_index, tess_outer_index;
2769 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2770 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2771 unsigned stride, outer_comps, inner_comps, i, offset;
2772 struct lp_build_if_state if_ctx, inner_if_ctx;
2773
2774 /* Add a barrier before loading tess factors from LDS. */
2775 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2776 si_llvm_emit_barrier(NULL, bld_base, NULL);
2777
2778 /* Do this only for invocation 0, because the tess levels are per-patch,
2779 * not per-vertex.
2780 *
2781 * This can't jump, because invocation 0 executes this. It should
2782 * at least mask out the loads and stores for other invocations.
2783 */
2784 lp_build_if(&if_ctx, &ctx->gallivm,
2785 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2786 invocation_id, ctx->i32_0, ""));
2787
2788 /* Determine the layout of one tess factor element in the buffer. */
2789 switch (shader->key.part.tcs.epilog.prim_mode) {
2790 case PIPE_PRIM_LINES:
2791 stride = 2; /* 2 dwords, 1 vec2 store */
2792 outer_comps = 2;
2793 inner_comps = 0;
2794 break;
2795 case PIPE_PRIM_TRIANGLES:
2796 stride = 4; /* 4 dwords, 1 vec4 store */
2797 outer_comps = 3;
2798 inner_comps = 1;
2799 break;
2800 case PIPE_PRIM_QUADS:
2801 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2802 outer_comps = 4;
2803 inner_comps = 2;
2804 break;
2805 default:
2806 assert(0);
2807 return;
2808 }
2809
2810 for (i = 0; i < 4; i++) {
2811 inner[i] = LLVMGetUndef(ctx->i32);
2812 outer[i] = LLVMGetUndef(ctx->i32);
2813 }
2814
2815 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2816 /* Tess factors are in VGPRs. */
2817 for (i = 0; i < outer_comps; i++)
2818 outer[i] = out[i] = invoc0_tf_outer[i];
2819 for (i = 0; i < inner_comps; i++)
2820 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2821 } else {
2822 /* Load tess_inner and tess_outer from LDS.
2823 * Any invocation can write them, so we can't get them from a temporary.
2824 */
2825 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2826 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2827
2828 lds_base = tcs_out_current_patch_data_offset;
2829 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2830 LLVMConstInt(ctx->i32,
2831 tess_inner_index * 4, 0), "");
2832 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2833 LLVMConstInt(ctx->i32,
2834 tess_outer_index * 4, 0), "");
2835
2836 for (i = 0; i < outer_comps; i++) {
2837 outer[i] = out[i] =
2838 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2839 }
2840 for (i = 0; i < inner_comps; i++) {
2841 inner[i] = out[outer_comps+i] =
2842 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2843 }
2844 }
2845
2846 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2847 /* For isolines, the hardware expects tess factors in the
2848 * reverse order from what GLSL / TGSI specify.
2849 */
2850 LLVMValueRef tmp = out[0];
2851 out[0] = out[1];
2852 out[1] = tmp;
2853 }
2854
2855 /* Convert the outputs to vectors for stores. */
2856 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2857 vec1 = NULL;
2858
2859 if (stride > 4)
2860 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2861
2862 /* Get the buffer. */
2863 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2864
2865 /* Get the offset. */
2866 tf_base = LLVMGetParam(ctx->main_fn,
2867 ctx->param_tcs_factor_offset);
2868 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2869 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2870
2871 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2872 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2873 rel_patch_id, ctx->i32_0, ""));
2874
2875 /* Store the dynamic HS control word. */
2876 offset = 0;
2877 if (ctx->screen->b.chip_class <= VI) {
2878 ac_build_buffer_store_dword(&ctx->ac, buffer,
2879 LLVMConstInt(ctx->i32, 0x80000000, 0),
2880 1, ctx->i32_0, tf_base,
2881 offset, 1, 0, true, false);
2882 offset += 4;
2883 }
2884
2885 lp_build_endif(&inner_if_ctx);
2886
2887 /* Store the tessellation factors. */
2888 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2889 MIN2(stride, 4), byteoffset, tf_base,
2890 offset, 1, 0, true, false);
2891 offset += 16;
2892 if (vec1)
2893 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2894 stride - 4, byteoffset, tf_base,
2895 offset, 1, 0, true, false);
2896
2897 /* Store the tess factors into the offchip buffer if TES reads them. */
2898 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2899 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2900 LLVMValueRef tf_inner_offset;
2901 unsigned param_outer, param_inner;
2902
2903 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2904 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2905
2906 param_outer = si_shader_io_get_unique_index_patch(
2907 TGSI_SEMANTIC_TESSOUTER, 0);
2908 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2909 LLVMConstInt(ctx->i32, param_outer, 0));
2910
2911 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2912 util_next_power_of_two(outer_comps));
2913
2914 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2915 outer_comps, tf_outer_offset,
2916 base, 0, 1, 0, true, false);
2917 if (inner_comps) {
2918 param_inner = si_shader_io_get_unique_index_patch(
2919 TGSI_SEMANTIC_TESSINNER, 0);
2920 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2921 LLVMConstInt(ctx->i32, param_inner, 0));
2922
2923 inner_vec = inner_comps == 1 ? inner[0] :
2924 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2925 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2926 inner_comps, tf_inner_offset,
2927 base, 0, 1, 0, true, false);
2928 }
2929 }
2930
2931 lp_build_endif(&if_ctx);
2932 }
2933
2934 static LLVMValueRef
2935 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2936 unsigned param, unsigned return_index)
2937 {
2938 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2939 LLVMGetParam(ctx->main_fn, param),
2940 return_index, "");
2941 }
2942
2943 static LLVMValueRef
2944 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2945 unsigned param, unsigned return_index)
2946 {
2947 LLVMBuilderRef builder = ctx->ac.builder;
2948 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2949
2950 return LLVMBuildInsertValue(builder, ret,
2951 ac_to_float(&ctx->ac, p),
2952 return_index, "");
2953 }
2954
2955 static LLVMValueRef
2956 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2957 unsigned param, unsigned return_index)
2958 {
2959 LLVMBuilderRef builder = ctx->ac.builder;
2960 LLVMValueRef ptr, lo, hi;
2961
2962 ptr = LLVMGetParam(ctx->main_fn, param);
2963 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2964 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2965 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2966 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2967 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2968 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2969 }
2970
2971 /* This only writes the tessellation factor levels. */
2972 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2973 {
2974 struct si_shader_context *ctx = si_shader_context(bld_base);
2975 LLVMBuilderRef builder = ctx->ac.builder;
2976 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2977
2978 si_copy_tcs_inputs(bld_base);
2979
2980 rel_patch_id = get_rel_patch_id(ctx);
2981 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2982 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2983
2984 if (ctx->screen->b.chip_class >= GFX9) {
2985 LLVMBasicBlockRef blocks[2] = {
2986 LLVMGetInsertBlock(builder),
2987 ctx->merged_wrap_if_state.entry_block
2988 };
2989 LLVMValueRef values[2];
2990
2991 lp_build_endif(&ctx->merged_wrap_if_state);
2992
2993 values[0] = rel_patch_id;
2994 values[1] = LLVMGetUndef(ctx->i32);
2995 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2996
2997 values[0] = tf_lds_offset;
2998 values[1] = LLVMGetUndef(ctx->i32);
2999 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3000
3001 values[0] = invocation_id;
3002 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3003 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3004 }
3005
3006 /* Return epilog parameters from this function. */
3007 LLVMValueRef ret = ctx->return_value;
3008 unsigned vgpr;
3009
3010 if (ctx->screen->b.chip_class >= GFX9) {
3011 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3012 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3013 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3014 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3015 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3016 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3017 /* Tess offchip and tess factor offsets are at the beginning. */
3018 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3019 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3020 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3021 } else {
3022 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3023 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3024 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3025 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3026 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3027 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3028 /* Tess offchip and tess factor offsets are after user SGPRs. */
3029 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3030 GFX6_TCS_NUM_USER_SGPR);
3031 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3032 GFX6_TCS_NUM_USER_SGPR + 1);
3033 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3034 }
3035
3036 /* VGPRs */
3037 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3038 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3039 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3040
3041 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3042 * the invocation_id output does not alias the param_tcs_rel_ids input,
3043 * which saves a V_MOV on gfx9.
3044 */
3045 vgpr += 2;
3046
3047 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3048 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3049
3050 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3051 vgpr++; /* skip the tess factor LDS offset */
3052 for (unsigned i = 0; i < 6; i++) {
3053 LLVMValueRef value =
3054 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3055 value = ac_to_float(&ctx->ac, value);
3056 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3057 }
3058 } else {
3059 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3060 }
3061 ctx->return_value = ret;
3062 }
3063
3064 /* Pass TCS inputs from LS to TCS on GFX9. */
3065 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3066 {
3067 LLVMValueRef ret = ctx->return_value;
3068
3069 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3070 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3071 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3072 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3073
3074 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3075 8 + SI_SGPR_RW_BUFFERS);
3076 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3077 ctx->param_bindless_samplers_and_images,
3078 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3079
3080 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3081 8 + SI_SGPR_VS_STATE_BITS);
3082 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3083 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3084 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3085 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3086 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3087 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3088 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3089 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3090 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3091 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3092
3093 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3094 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3095 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3096 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3097 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3098
3099 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3100 ret = si_insert_input_ret_float(ctx, ret,
3101 ctx->param_tcs_patch_id, vgpr++);
3102 ret = si_insert_input_ret_float(ctx, ret,
3103 ctx->param_tcs_rel_ids, vgpr++);
3104 ctx->return_value = ret;
3105 }
3106
3107 /* Pass GS inputs from ES to GS on GFX9. */
3108 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3109 {
3110 LLVMValueRef ret = ctx->return_value;
3111
3112 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3113 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3114 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3115
3116 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3117 8 + SI_SGPR_RW_BUFFERS);
3118 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3119 ctx->param_bindless_samplers_and_images,
3120 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3121
3122 unsigned desc_param = ctx->param_vs_state_bits + 1;
3123 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3124 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3125 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3126 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3127
3128 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3129 for (unsigned i = 0; i < 5; i++) {
3130 unsigned param = ctx->param_gs_vtx01_offset + i;
3131 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3132 }
3133 ctx->return_value = ret;
3134 }
3135
3136 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
3137 {
3138 struct si_shader_context *ctx = si_shader_context(bld_base);
3139 struct si_shader *shader = ctx->shader;
3140 struct tgsi_shader_info *info = &shader->selector->info;
3141 unsigned i, chan;
3142 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3143 ctx->param_rel_auto_id);
3144 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3145 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3146 vertex_dw_stride, "");
3147
3148 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3149 * its inputs from it. */
3150 for (i = 0; i < info->num_outputs; i++) {
3151 LLVMValueRef *out_ptr = ctx->outputs[i];
3152 unsigned name = info->output_semantic_name[i];
3153 unsigned index = info->output_semantic_index[i];
3154
3155 /* The ARB_shader_viewport_layer_array spec contains the
3156 * following issue:
3157 *
3158 * 2) What happens if gl_ViewportIndex or gl_Layer is
3159 * written in the vertex shader and a geometry shader is
3160 * present?
3161 *
3162 * RESOLVED: The value written by the last vertex processing
3163 * stage is used. If the last vertex processing stage
3164 * (vertex, tessellation evaluation or geometry) does not
3165 * statically assign to gl_ViewportIndex or gl_Layer, index
3166 * or layer zero is assumed.
3167 *
3168 * So writes to those outputs in VS-as-LS are simply ignored.
3169 */
3170 if (name == TGSI_SEMANTIC_LAYER ||
3171 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3172 continue;
3173
3174 int param = si_shader_io_get_unique_index(name, index);
3175 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3176 LLVMConstInt(ctx->i32, param * 4, 0), "");
3177
3178 for (chan = 0; chan < 4; chan++) {
3179 if (!(info->output_usagemask[i] & (1 << chan)))
3180 continue;
3181
3182 lds_store(bld_base, chan, dw_addr,
3183 LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], ""));
3184 }
3185 }
3186
3187 if (ctx->screen->b.chip_class >= GFX9)
3188 si_set_ls_return_value_for_tcs(ctx);
3189 }
3190
3191 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
3192 {
3193 struct si_shader_context *ctx = si_shader_context(bld_base);
3194 struct si_shader *es = ctx->shader;
3195 struct tgsi_shader_info *info = &es->selector->info;
3196 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3197 ctx->param_es2gs_offset);
3198 LLVMValueRef lds_base = NULL;
3199 unsigned chan;
3200 int i;
3201
3202 if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
3203 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3204 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3205 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3206 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3207 LLVMBuildMul(ctx->ac.builder, wave_idx,
3208 LLVMConstInt(ctx->i32, 64, false), ""), "");
3209 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3210 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3211 }
3212
3213 for (i = 0; i < info->num_outputs; i++) {
3214 LLVMValueRef *out_ptr = ctx->outputs[i];
3215 int param;
3216
3217 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3218 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3219 continue;
3220
3221 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3222 info->output_semantic_index[i]);
3223
3224 for (chan = 0; chan < 4; chan++) {
3225 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], "");
3226 out_val = ac_to_integer(&ctx->ac, out_val);
3227
3228 /* GFX9 has the ESGS ring in LDS. */
3229 if (ctx->screen->b.chip_class >= GFX9) {
3230 lds_store(bld_base, param * 4 + chan, lds_base, out_val);
3231 continue;
3232 }
3233
3234 ac_build_buffer_store_dword(&ctx->ac,
3235 ctx->esgs_ring,
3236 out_val, 1, NULL, soffset,
3237 (4 * param + chan) * 4,
3238 1, 1, true, true);
3239 }
3240 }
3241
3242 if (ctx->screen->b.chip_class >= GFX9)
3243 si_set_es_return_value_for_gs(ctx);
3244 }
3245
3246 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3247 {
3248 if (ctx->screen->b.chip_class >= GFX9)
3249 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3250 else
3251 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3252 }
3253
3254 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3255 {
3256 struct si_shader_context *ctx = si_shader_context(bld_base);
3257
3258 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3259 si_get_gs_wave_id(ctx));
3260
3261 if (ctx->screen->b.chip_class >= GFX9)
3262 lp_build_endif(&ctx->merged_wrap_if_state);
3263 }
3264
3265 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3266 unsigned max_outputs,
3267 LLVMValueRef *addrs)
3268 {
3269 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3270 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3271 struct si_shader_output_values *outputs = NULL;
3272 int i,j;
3273
3274 assert(!ctx->shader->is_gs_copy_shader);
3275 assert(info->num_outputs <= max_outputs);
3276
3277 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3278
3279 /* Vertex color clamping.
3280 *
3281 * This uses a state constant loaded in a user data SGPR and
3282 * an IF statement is added that clamps all colors if the constant
3283 * is true.
3284 */
3285 if (ctx->type == PIPE_SHADER_VERTEX) {
3286 struct lp_build_if_state if_ctx;
3287 LLVMValueRef cond = NULL;
3288 LLVMValueRef addr, val;
3289
3290 for (i = 0; i < info->num_outputs; i++) {
3291 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3292 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3293 continue;
3294
3295 /* We've found a color. */
3296 if (!cond) {
3297 /* The state is in the first bit of the user SGPR. */
3298 cond = LLVMGetParam(ctx->main_fn,
3299 ctx->param_vs_state_bits);
3300 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3301 ctx->i1, "");
3302 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3303 }
3304
3305 for (j = 0; j < 4; j++) {
3306 addr = addrs[4 * i + j];
3307 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3308 val = ac_build_clamp(&ctx->ac, val);
3309 LLVMBuildStore(ctx->ac.builder, val, addr);
3310 }
3311 }
3312
3313 if (cond)
3314 lp_build_endif(&if_ctx);
3315 }
3316
3317 for (i = 0; i < info->num_outputs; i++) {
3318 outputs[i].semantic_name = info->output_semantic_name[i];
3319 outputs[i].semantic_index = info->output_semantic_index[i];
3320
3321 for (j = 0; j < 4; j++) {
3322 outputs[i].values[j] =
3323 LLVMBuildLoad(ctx->ac.builder,
3324 addrs[4 * i + j],
3325 "");
3326 outputs[i].vertex_stream[j] =
3327 (info->output_streams[i] >> (2 * j)) & 3;
3328 }
3329 }
3330
3331 if (ctx->shader->selector->so.num_outputs)
3332 si_llvm_emit_streamout(ctx, outputs, i, 0);
3333
3334 /* Export PrimitiveID. */
3335 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3336 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3337 outputs[i].semantic_index = 0;
3338 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3339 for (j = 1; j < 4; j++)
3340 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3341
3342 memset(outputs[i].vertex_stream, 0,
3343 sizeof(outputs[i].vertex_stream));
3344 i++;
3345 }
3346
3347 si_llvm_export_vs(&ctx->bld_base, outputs, i);
3348 FREE(outputs);
3349 }
3350
3351 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3352 {
3353 struct si_shader_context *ctx = si_shader_context(bld_base);
3354
3355 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3356 &ctx->outputs[0][0]);
3357 }
3358
3359 struct si_ps_exports {
3360 unsigned num;
3361 struct ac_export_args args[10];
3362 };
3363
3364 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3365 bool writes_samplemask)
3366 {
3367 if (writes_z) {
3368 /* Z needs 32 bits. */
3369 if (writes_samplemask)
3370 return V_028710_SPI_SHADER_32_ABGR;
3371 else if (writes_stencil)
3372 return V_028710_SPI_SHADER_32_GR;
3373 else
3374 return V_028710_SPI_SHADER_32_R;
3375 } else if (writes_stencil || writes_samplemask) {
3376 /* Both stencil and sample mask need only 16 bits. */
3377 return V_028710_SPI_SHADER_UINT16_ABGR;
3378 } else {
3379 return V_028710_SPI_SHADER_ZERO;
3380 }
3381 }
3382
3383 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3384 LLVMValueRef depth, LLVMValueRef stencil,
3385 LLVMValueRef samplemask, struct si_ps_exports *exp)
3386 {
3387 struct si_shader_context *ctx = si_shader_context(bld_base);
3388 struct lp_build_context *base = &bld_base->base;
3389 struct ac_export_args args;
3390 unsigned mask = 0;
3391 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3392 stencil != NULL,
3393 samplemask != NULL);
3394
3395 assert(depth || stencil || samplemask);
3396
3397 args.valid_mask = 1; /* whether the EXEC mask is valid */
3398 args.done = 1; /* DONE bit */
3399
3400 /* Specify the target we are exporting */
3401 args.target = V_008DFC_SQ_EXP_MRTZ;
3402
3403 args.compr = 0; /* COMP flag */
3404 args.out[0] = base->undef; /* R, depth */
3405 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3406 args.out[2] = base->undef; /* B, sample mask */
3407 args.out[3] = base->undef; /* A, alpha to mask */
3408
3409 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3410 assert(!depth);
3411 args.compr = 1; /* COMPR flag */
3412
3413 if (stencil) {
3414 /* Stencil should be in X[23:16]. */
3415 stencil = ac_to_integer(&ctx->ac, stencil);
3416 stencil = LLVMBuildShl(ctx->ac.builder, stencil,
3417 LLVMConstInt(ctx->i32, 16, 0), "");
3418 args.out[0] = ac_to_float(&ctx->ac, stencil);
3419 mask |= 0x3;
3420 }
3421 if (samplemask) {
3422 /* SampleMask should be in Y[15:0]. */
3423 args.out[1] = samplemask;
3424 mask |= 0xc;
3425 }
3426 } else {
3427 if (depth) {
3428 args.out[0] = depth;
3429 mask |= 0x1;
3430 }
3431 if (stencil) {
3432 args.out[1] = stencil;
3433 mask |= 0x2;
3434 }
3435 if (samplemask) {
3436 args.out[2] = samplemask;
3437 mask |= 0x4;
3438 }
3439 }
3440
3441 /* SI (except OLAND and HAINAN) has a bug that it only looks
3442 * at the X writemask component. */
3443 if (ctx->screen->b.chip_class == SI &&
3444 ctx->screen->b.family != CHIP_OLAND &&
3445 ctx->screen->b.family != CHIP_HAINAN)
3446 mask |= 0x1;
3447
3448 /* Specify which components to enable */
3449 args.enabled_channels = mask;
3450
3451 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3452 }
3453
3454 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3455 LLVMValueRef *color, unsigned index,
3456 unsigned samplemask_param,
3457 bool is_last, struct si_ps_exports *exp)
3458 {
3459 struct si_shader_context *ctx = si_shader_context(bld_base);
3460 int i;
3461
3462 /* Clamp color */
3463 if (ctx->shader->key.part.ps.epilog.clamp_color)
3464 for (i = 0; i < 4; i++)
3465 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3466
3467 /* Alpha to one */
3468 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3469 color[3] = ctx->ac.f32_1;
3470
3471 /* Alpha test */
3472 if (index == 0 &&
3473 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3474 si_alpha_test(bld_base, color[3]);
3475
3476 /* Line & polygon smoothing */
3477 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3478 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3479 samplemask_param);
3480
3481 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3482 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3483 struct ac_export_args args[8];
3484 int c, last = -1;
3485
3486 /* Get the export arguments, also find out what the last one is. */
3487 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3488 si_llvm_init_export_args(bld_base, color,
3489 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3490 if (args[c].enabled_channels)
3491 last = c;
3492 }
3493
3494 /* Emit all exports. */
3495 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3496 if (is_last && last == c) {
3497 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3498 args[c].done = 1; /* DONE bit */
3499 } else if (!args[c].enabled_channels)
3500 continue; /* unnecessary NULL export */
3501
3502 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3503 }
3504 } else {
3505 struct ac_export_args args;
3506
3507 /* Export */
3508 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3509 &args);
3510 if (is_last) {
3511 args.valid_mask = 1; /* whether the EXEC mask is valid */
3512 args.done = 1; /* DONE bit */
3513 } else if (!args.enabled_channels)
3514 return; /* unnecessary NULL export */
3515
3516 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3517 }
3518 }
3519
3520 static void si_emit_ps_exports(struct si_shader_context *ctx,
3521 struct si_ps_exports *exp)
3522 {
3523 for (unsigned i = 0; i < exp->num; i++)
3524 ac_build_export(&ctx->ac, &exp->args[i]);
3525 }
3526
3527 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3528 {
3529 struct si_shader_context *ctx = si_shader_context(bld_base);
3530 struct lp_build_context *base = &bld_base->base;
3531 struct ac_export_args args;
3532
3533 args.enabled_channels = 0x0; /* enabled channels */
3534 args.valid_mask = 1; /* whether the EXEC mask is valid */
3535 args.done = 1; /* DONE bit */
3536 args.target = V_008DFC_SQ_EXP_NULL;
3537 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3538 args.out[0] = base->undef; /* R */
3539 args.out[1] = base->undef; /* G */
3540 args.out[2] = base->undef; /* B */
3541 args.out[3] = base->undef; /* A */
3542
3543 ac_build_export(&ctx->ac, &args);
3544 }
3545
3546 /**
3547 * Return PS outputs in this order:
3548 *
3549 * v[0:3] = color0.xyzw
3550 * v[4:7] = color1.xyzw
3551 * ...
3552 * vN+0 = Depth
3553 * vN+1 = Stencil
3554 * vN+2 = SampleMask
3555 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3556 *
3557 * The alpha-ref SGPR is returned via its original location.
3558 */
3559 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3560 unsigned max_outputs,
3561 LLVMValueRef *addrs)
3562 {
3563 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3564 struct si_shader *shader = ctx->shader;
3565 struct tgsi_shader_info *info = &shader->selector->info;
3566 LLVMBuilderRef builder = ctx->ac.builder;
3567 unsigned i, j, first_vgpr, vgpr;
3568
3569 LLVMValueRef color[8][4] = {};
3570 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3571 LLVMValueRef ret;
3572
3573 if (ctx->postponed_kill)
3574 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3575
3576 /* Read the output values. */
3577 for (i = 0; i < info->num_outputs; i++) {
3578 unsigned semantic_name = info->output_semantic_name[i];
3579 unsigned semantic_index = info->output_semantic_index[i];
3580
3581 switch (semantic_name) {
3582 case TGSI_SEMANTIC_COLOR:
3583 assert(semantic_index < 8);
3584 for (j = 0; j < 4; j++) {
3585 LLVMValueRef ptr = addrs[4 * i + j];
3586 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3587 color[semantic_index][j] = result;
3588 }
3589 break;
3590 case TGSI_SEMANTIC_POSITION:
3591 depth = LLVMBuildLoad(builder,
3592 addrs[4 * i + 2], "");
3593 break;
3594 case TGSI_SEMANTIC_STENCIL:
3595 stencil = LLVMBuildLoad(builder,
3596 addrs[4 * i + 1], "");
3597 break;
3598 case TGSI_SEMANTIC_SAMPLEMASK:
3599 samplemask = LLVMBuildLoad(builder,
3600 addrs[4 * i + 0], "");
3601 break;
3602 default:
3603 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3604 semantic_name);
3605 }
3606 }
3607
3608 /* Fill the return structure. */
3609 ret = ctx->return_value;
3610
3611 /* Set SGPRs. */
3612 ret = LLVMBuildInsertValue(builder, ret,
3613 ac_to_integer(&ctx->ac,
3614 LLVMGetParam(ctx->main_fn,
3615 SI_PARAM_ALPHA_REF)),
3616 SI_SGPR_ALPHA_REF, "");
3617
3618 /* Set VGPRs */
3619 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3620 for (i = 0; i < ARRAY_SIZE(color); i++) {
3621 if (!color[i][0])
3622 continue;
3623
3624 for (j = 0; j < 4; j++)
3625 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3626 }
3627 if (depth)
3628 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3629 if (stencil)
3630 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3631 if (samplemask)
3632 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3633
3634 /* Add the input sample mask for smoothing at the end. */
3635 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3636 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3637 ret = LLVMBuildInsertValue(builder, ret,
3638 LLVMGetParam(ctx->main_fn,
3639 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3640
3641 ctx->return_value = ret;
3642 }
3643
3644 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3645 {
3646 LLVMValueRef args[1] = {
3647 LLVMConstInt(ctx->i32, simm16, 0)
3648 };
3649 lp_build_intrinsic(ctx->ac.builder, "llvm.amdgcn.s.waitcnt",
3650 ctx->voidt, args, 1, 0);
3651 }
3652
3653 static void membar_emit(
3654 const struct lp_build_tgsi_action *action,
3655 struct lp_build_tgsi_context *bld_base,
3656 struct lp_build_emit_data *emit_data)
3657 {
3658 struct si_shader_context *ctx = si_shader_context(bld_base);
3659 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3660 unsigned flags = LLVMConstIntGetZExtValue(src0);
3661 unsigned waitcnt = NOOP_WAITCNT;
3662
3663 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3664 waitcnt &= VM_CNT & LGKM_CNT;
3665
3666 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3667 TGSI_MEMBAR_SHADER_BUFFER |
3668 TGSI_MEMBAR_SHADER_IMAGE))
3669 waitcnt &= VM_CNT;
3670
3671 if (flags & TGSI_MEMBAR_SHARED)
3672 waitcnt &= LGKM_CNT;
3673
3674 if (waitcnt != NOOP_WAITCNT)
3675 si_emit_waitcnt(ctx, waitcnt);
3676 }
3677
3678 static void clock_emit(
3679 const struct lp_build_tgsi_action *action,
3680 struct lp_build_tgsi_context *bld_base,
3681 struct lp_build_emit_data *emit_data)
3682 {
3683 struct si_shader_context *ctx = si_shader_context(bld_base);
3684 LLVMValueRef tmp;
3685
3686 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3687 ctx->i64, NULL, 0, 0);
3688 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3689
3690 emit_data->output[0] =
3691 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3692 emit_data->output[1] =
3693 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3694 }
3695
3696 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3697 {
3698 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3699 CONST_ADDR_SPACE);
3700 }
3701
3702 static void si_llvm_emit_ddxy(
3703 const struct lp_build_tgsi_action *action,
3704 struct lp_build_tgsi_context *bld_base,
3705 struct lp_build_emit_data *emit_data)
3706 {
3707 struct si_shader_context *ctx = si_shader_context(bld_base);
3708 unsigned opcode = emit_data->info->opcode;
3709 LLVMValueRef val;
3710 int idx;
3711 unsigned mask;
3712
3713 if (opcode == TGSI_OPCODE_DDX_FINE)
3714 mask = AC_TID_MASK_LEFT;
3715 else if (opcode == TGSI_OPCODE_DDY_FINE)
3716 mask = AC_TID_MASK_TOP;
3717 else
3718 mask = AC_TID_MASK_TOP_LEFT;
3719
3720 /* for DDX we want to next X pixel, DDY next Y pixel. */
3721 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3722
3723 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3724 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3725 emit_data->output[emit_data->chan] = val;
3726 }
3727
3728 /*
3729 * this takes an I,J coordinate pair,
3730 * and works out the X and Y derivatives.
3731 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3732 */
3733 static LLVMValueRef si_llvm_emit_ddxy_interp(
3734 struct lp_build_tgsi_context *bld_base,
3735 LLVMValueRef interp_ij)
3736 {
3737 struct si_shader_context *ctx = si_shader_context(bld_base);
3738 LLVMValueRef result[4], a;
3739 unsigned i;
3740
3741 for (i = 0; i < 2; i++) {
3742 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3743 LLVMConstInt(ctx->i32, i, 0), "");
3744 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3745 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3746 }
3747
3748 return lp_build_gather_values(&ctx->gallivm, result, 4);
3749 }
3750
3751 static void interp_fetch_args(
3752 struct lp_build_tgsi_context *bld_base,
3753 struct lp_build_emit_data *emit_data)
3754 {
3755 struct si_shader_context *ctx = si_shader_context(bld_base);
3756 const struct tgsi_full_instruction *inst = emit_data->inst;
3757
3758 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3759 /* offset is in second src, first two channels */
3760 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3761 emit_data->inst, 1,
3762 TGSI_CHAN_X);
3763 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3764 emit_data->inst, 1,
3765 TGSI_CHAN_Y);
3766 emit_data->arg_count = 2;
3767 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3768 LLVMValueRef sample_position;
3769 LLVMValueRef sample_id;
3770 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3771
3772 /* fetch sample ID, then fetch its sample position,
3773 * and place into first two channels.
3774 */
3775 sample_id = lp_build_emit_fetch(bld_base,
3776 emit_data->inst, 1, TGSI_CHAN_X);
3777 sample_id = ac_to_integer(&ctx->ac, sample_id);
3778
3779 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3780 * Language 4.50 spec says about interpolateAtSample:
3781 *
3782 * "Returns the value of the input interpolant variable at
3783 * the location of sample number sample. If multisample
3784 * buffers are not available, the input variable will be
3785 * evaluated at the center of the pixel. If sample sample
3786 * does not exist, the position used to interpolate the
3787 * input variable is undefined."
3788 *
3789 * This means that sample_id values outside of the valid are
3790 * in fact valid input, and the usual mechanism for loading the
3791 * sample position doesn't work.
3792 */
3793 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3794 LLVMValueRef center[4] = {
3795 LLVMConstReal(ctx->f32, 0.5),
3796 LLVMConstReal(ctx->f32, 0.5),
3797 ctx->ac.f32_0,
3798 ctx->ac.f32_0,
3799 };
3800
3801 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3802 } else {
3803 sample_position = load_sample_position(ctx, sample_id);
3804 }
3805
3806 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3807 sample_position,
3808 ctx->i32_0, "");
3809
3810 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3811 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3812 sample_position,
3813 ctx->i32_1, "");
3814 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3815 emit_data->arg_count = 2;
3816 }
3817 }
3818
3819 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3820 struct lp_build_tgsi_context *bld_base,
3821 struct lp_build_emit_data *emit_data)
3822 {
3823 struct si_shader_context *ctx = si_shader_context(bld_base);
3824 struct si_shader *shader = ctx->shader;
3825 const struct tgsi_shader_info *info = &shader->selector->info;
3826 LLVMValueRef interp_param;
3827 const struct tgsi_full_instruction *inst = emit_data->inst;
3828 const struct tgsi_full_src_register *input = &inst->Src[0];
3829 int input_base, input_array_size;
3830 int chan;
3831 int i;
3832 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3833 LLVMValueRef array_idx;
3834 int interp_param_idx;
3835 unsigned interp;
3836 unsigned location;
3837
3838 assert(input->Register.File == TGSI_FILE_INPUT);
3839
3840 if (input->Register.Indirect) {
3841 unsigned array_id = input->Indirect.ArrayID;
3842
3843 if (array_id) {
3844 input_base = info->input_array_first[array_id];
3845 input_array_size = info->input_array_last[array_id] - input_base + 1;
3846 } else {
3847 input_base = inst->Src[0].Register.Index;
3848 input_array_size = info->num_inputs - input_base;
3849 }
3850
3851 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3852 1, input->Register.Index - input_base);
3853 } else {
3854 input_base = inst->Src[0].Register.Index;
3855 input_array_size = 1;
3856 array_idx = ctx->i32_0;
3857 }
3858
3859 interp = shader->selector->info.input_interpolate[input_base];
3860
3861 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3862 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3863 location = TGSI_INTERPOLATE_LOC_CENTER;
3864 else
3865 location = TGSI_INTERPOLATE_LOC_CENTROID;
3866
3867 interp_param_idx = lookup_interp_param_index(interp, location);
3868 if (interp_param_idx == -1)
3869 return;
3870 else if (interp_param_idx)
3871 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3872 else
3873 interp_param = NULL;
3874
3875 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3876 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3877 LLVMValueRef ij_out[2];
3878 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3879
3880 /*
3881 * take the I then J parameters, and the DDX/Y for it, and
3882 * calculate the IJ inputs for the interpolator.
3883 * temp1 = ddx * offset/sample.x + I;
3884 * interp_param.I = ddy * offset/sample.y + temp1;
3885 * temp1 = ddx * offset/sample.x + J;
3886 * interp_param.J = ddy * offset/sample.y + temp1;
3887 */
3888 for (i = 0; i < 2; i++) {
3889 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3890 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3891 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3892 ddxy_out, ix_ll, "");
3893 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3894 ddxy_out, iy_ll, "");
3895 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3896 interp_param, ix_ll, "");
3897 LLVMValueRef temp1, temp2;
3898
3899 interp_el = ac_to_float(&ctx->ac, interp_el);
3900
3901 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3902
3903 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3904
3905 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3906
3907 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3908 }
3909 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3910 }
3911
3912 if (interp_param)
3913 interp_param = ac_to_float(&ctx->ac, interp_param);
3914
3915 for (chan = 0; chan < 4; chan++) {
3916 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3917 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3918
3919 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3920 LLVMValueRef v, i = NULL, j = NULL;
3921
3922 if (interp_param) {
3923 i = LLVMBuildExtractElement(
3924 ctx->ac.builder, interp_param, ctx->i32_0, "");
3925 j = LLVMBuildExtractElement(
3926 ctx->ac.builder, interp_param, ctx->i32_1, "");
3927 }
3928 v = si_build_fs_interp(ctx, input_base + idx, schan,
3929 prim_mask, i, j);
3930
3931 gather = LLVMBuildInsertElement(ctx->ac.builder,
3932 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3933 }
3934
3935 emit_data->output[chan] = LLVMBuildExtractElement(
3936 ctx->ac.builder, gather, array_idx, "");
3937 }
3938 }
3939
3940 static void vote_all_emit(
3941 const struct lp_build_tgsi_action *action,
3942 struct lp_build_tgsi_context *bld_base,
3943 struct lp_build_emit_data *emit_data)
3944 {
3945 struct si_shader_context *ctx = si_shader_context(bld_base);
3946
3947 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3948 emit_data->output[emit_data->chan] =
3949 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3950 }
3951
3952 static void vote_any_emit(
3953 const struct lp_build_tgsi_action *action,
3954 struct lp_build_tgsi_context *bld_base,
3955 struct lp_build_emit_data *emit_data)
3956 {
3957 struct si_shader_context *ctx = si_shader_context(bld_base);
3958
3959 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3960 emit_data->output[emit_data->chan] =
3961 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3962 }
3963
3964 static void vote_eq_emit(
3965 const struct lp_build_tgsi_action *action,
3966 struct lp_build_tgsi_context *bld_base,
3967 struct lp_build_emit_data *emit_data)
3968 {
3969 struct si_shader_context *ctx = si_shader_context(bld_base);
3970
3971 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3972 emit_data->output[emit_data->chan] =
3973 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3974 }
3975
3976 static void ballot_emit(
3977 const struct lp_build_tgsi_action *action,
3978 struct lp_build_tgsi_context *bld_base,
3979 struct lp_build_emit_data *emit_data)
3980 {
3981 struct si_shader_context *ctx = si_shader_context(bld_base);
3982 LLVMBuilderRef builder = ctx->ac.builder;
3983 LLVMValueRef tmp;
3984
3985 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3986 tmp = ac_build_ballot(&ctx->ac, tmp);
3987 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3988
3989 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3990 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3991 }
3992
3993 static void read_invoc_fetch_args(
3994 struct lp_build_tgsi_context *bld_base,
3995 struct lp_build_emit_data *emit_data)
3996 {
3997 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
3998 0, emit_data->src_chan);
3999
4000 /* Always read the source invocation (= lane) from the X channel. */
4001 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4002 1, TGSI_CHAN_X);
4003 emit_data->arg_count = 2;
4004 }
4005
4006 static void read_lane_emit(
4007 const struct lp_build_tgsi_action *action,
4008 struct lp_build_tgsi_context *bld_base,
4009 struct lp_build_emit_data *emit_data)
4010 {
4011 struct si_shader_context *ctx = si_shader_context(bld_base);
4012
4013 /* We currently have no other way to prevent LLVM from lifting the icmp
4014 * calls to a dominating basic block.
4015 */
4016 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4017
4018 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4019 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4020
4021 emit_data->output[emit_data->chan] =
4022 ac_build_intrinsic(&ctx->ac, action->intr_name,
4023 ctx->i32, emit_data->args, emit_data->arg_count,
4024 AC_FUNC_ATTR_READNONE |
4025 AC_FUNC_ATTR_CONVERGENT);
4026 }
4027
4028 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4029 struct lp_build_emit_data *emit_data)
4030 {
4031 struct si_shader_context *ctx = si_shader_context(bld_base);
4032 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4033 LLVMValueRef imm;
4034 unsigned stream;
4035
4036 assert(src0.File == TGSI_FILE_IMMEDIATE);
4037
4038 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4039 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4040 return stream;
4041 }
4042
4043 /* Emit one vertex from the geometry shader */
4044 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4045 unsigned stream,
4046 LLVMValueRef *addrs)
4047 {
4048 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4049 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4050 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4051 struct si_shader *shader = ctx->shader;
4052 struct lp_build_if_state if_state;
4053 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4054 ctx->param_gs2vs_offset);
4055 LLVMValueRef gs_next_vertex;
4056 LLVMValueRef can_emit;
4057 unsigned chan, offset;
4058 int i;
4059
4060 /* Write vertex attribute values to GSVS ring */
4061 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4062 ctx->gs_next_vertex[stream],
4063 "");
4064
4065 /* If this thread has already emitted the declared maximum number of
4066 * vertices, skip the write: excessive vertex emissions are not
4067 * supposed to have any effect.
4068 *
4069 * If the shader has no writes to memory, kill it instead. This skips
4070 * further memory loads and may allow LLVM to skip to the end
4071 * altogether.
4072 */
4073 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4074 LLVMConstInt(ctx->i32,
4075 shader->selector->gs_max_out_vertices, 0), "");
4076
4077 bool use_kill = !info->writes_memory;
4078 if (use_kill) {
4079 ac_build_kill_if_false(&ctx->ac, can_emit);
4080 } else {
4081 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4082 }
4083
4084 offset = 0;
4085 for (i = 0; i < info->num_outputs; i++) {
4086 for (chan = 0; chan < 4; chan++) {
4087 if (!(info->output_usagemask[i] & (1 << chan)) ||
4088 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4089 continue;
4090
4091 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4092 LLVMValueRef voffset =
4093 LLVMConstInt(ctx->i32, offset *
4094 shader->selector->gs_max_out_vertices, 0);
4095 offset++;
4096
4097 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4098 voffset = lp_build_mul_imm(uint, voffset, 4);
4099
4100 out_val = ac_to_integer(&ctx->ac, out_val);
4101
4102 ac_build_buffer_store_dword(&ctx->ac,
4103 ctx->gsvs_ring[stream],
4104 out_val, 1,
4105 voffset, soffset, 0,
4106 1, 1, true, true);
4107 }
4108 }
4109
4110 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4111 ctx->i32_1);
4112
4113 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4114
4115 /* Signal vertex emission */
4116 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4117 si_get_gs_wave_id(ctx));
4118 if (!use_kill)
4119 lp_build_endif(&if_state);
4120 }
4121
4122 /* Emit one vertex from the geometry shader */
4123 static void si_tgsi_emit_vertex(
4124 const struct lp_build_tgsi_action *action,
4125 struct lp_build_tgsi_context *bld_base,
4126 struct lp_build_emit_data *emit_data)
4127 {
4128 struct si_shader_context *ctx = si_shader_context(bld_base);
4129 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4130
4131 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4132 }
4133
4134 /* Cut one primitive from the geometry shader */
4135 static void si_llvm_emit_primitive(
4136 const struct lp_build_tgsi_action *action,
4137 struct lp_build_tgsi_context *bld_base,
4138 struct lp_build_emit_data *emit_data)
4139 {
4140 struct si_shader_context *ctx = si_shader_context(bld_base);
4141 unsigned stream;
4142
4143 /* Signal primitive cut */
4144 stream = si_llvm_get_stream(bld_base, emit_data);
4145 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4146 si_get_gs_wave_id(ctx));
4147 }
4148
4149 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4150 struct lp_build_tgsi_context *bld_base,
4151 struct lp_build_emit_data *emit_data)
4152 {
4153 struct si_shader_context *ctx = si_shader_context(bld_base);
4154
4155 /* SI only (thanks to a hw bug workaround):
4156 * The real barrier instruction isn’t needed, because an entire patch
4157 * always fits into a single wave.
4158 */
4159 if (ctx->screen->b.chip_class == SI &&
4160 ctx->type == PIPE_SHADER_TESS_CTRL) {
4161 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4162 return;
4163 }
4164
4165 lp_build_intrinsic(ctx->ac.builder,
4166 "llvm.amdgcn.s.barrier",
4167 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4168 }
4169
4170 static const struct lp_build_tgsi_action interp_action = {
4171 .fetch_args = interp_fetch_args,
4172 .emit = build_interp_intrinsic,
4173 };
4174
4175 static void si_create_function(struct si_shader_context *ctx,
4176 const char *name,
4177 LLVMTypeRef *returns, unsigned num_returns,
4178 struct si_function_info *fninfo,
4179 unsigned max_workgroup_size)
4180 {
4181 int i;
4182
4183 si_llvm_create_func(ctx, name, returns, num_returns,
4184 fninfo->types, fninfo->num_params);
4185 ctx->return_value = LLVMGetUndef(ctx->return_type);
4186
4187 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4188 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4189
4190 /* The combination of:
4191 * - ByVal
4192 * - dereferenceable
4193 * - invariant.load
4194 * allows the optimization passes to move loads and reduces
4195 * SGPR spilling significantly.
4196 */
4197 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4198 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4199 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4200 ac_add_attr_dereferenceable(P, UINT64_MAX);
4201 } else
4202 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4203 }
4204
4205 for (i = 0; i < fninfo->num_params; ++i) {
4206 if (fninfo->assign[i])
4207 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4208 }
4209
4210 if (max_workgroup_size) {
4211 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4212 max_workgroup_size);
4213 }
4214 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4215 "no-signed-zeros-fp-math",
4216 "true");
4217
4218 if (ctx->screen->b.debug_flags & DBG(UNSAFE_MATH)) {
4219 /* These were copied from some LLVM test. */
4220 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4221 "less-precise-fpmad",
4222 "true");
4223 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4224 "no-infs-fp-math",
4225 "true");
4226 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4227 "no-nans-fp-math",
4228 "true");
4229 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4230 "unsafe-fp-math",
4231 "true");
4232 }
4233 }
4234
4235 static void declare_streamout_params(struct si_shader_context *ctx,
4236 struct pipe_stream_output_info *so,
4237 struct si_function_info *fninfo)
4238 {
4239 int i;
4240
4241 /* Streamout SGPRs. */
4242 if (so->num_outputs) {
4243 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4244 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4245 else
4246 ctx->param_streamout_config = fninfo->num_params - 1;
4247
4248 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4249 }
4250 /* A streamout buffer offset is loaded if the stride is non-zero. */
4251 for (i = 0; i < 4; i++) {
4252 if (!so->stride[i])
4253 continue;
4254
4255 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4256 }
4257 }
4258
4259 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4260 {
4261 switch (shader->selector->type) {
4262 case PIPE_SHADER_TESS_CTRL:
4263 /* Return this so that LLVM doesn't remove s_barrier
4264 * instructions on chips where we use s_barrier. */
4265 return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
4266
4267 case PIPE_SHADER_GEOMETRY:
4268 return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
4269
4270 case PIPE_SHADER_COMPUTE:
4271 break; /* see below */
4272
4273 default:
4274 return 0;
4275 }
4276
4277 const unsigned *properties = shader->selector->info.properties;
4278 unsigned max_work_group_size =
4279 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4280 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4281 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4282
4283 if (!max_work_group_size) {
4284 /* This is a variable group size compute shader,
4285 * compile it for the maximum possible group size.
4286 */
4287 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4288 }
4289 return max_work_group_size;
4290 }
4291
4292 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4293 struct si_function_info *fninfo,
4294 bool assign_params)
4295 {
4296 LLVMTypeRef const_shader_buf_type;
4297
4298 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4299 ctx->shader->selector->info.shader_buffers_declared == 0)
4300 const_shader_buf_type = ctx->f32;
4301 else
4302 const_shader_buf_type = ctx->v4i32;
4303
4304 unsigned const_and_shader_buffers =
4305 add_arg(fninfo, ARG_SGPR,
4306 si_const_array(const_shader_buf_type, 0));
4307
4308 unsigned samplers_and_images =
4309 add_arg(fninfo, ARG_SGPR,
4310 si_const_array(ctx->v8i32,
4311 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4312
4313 if (assign_params) {
4314 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4315 ctx->param_samplers_and_images = samplers_and_images;
4316 }
4317 }
4318
4319 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4320 struct si_function_info *fninfo)
4321 {
4322 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4323 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4324 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4325 si_const_array(ctx->v8i32, 0));
4326 }
4327
4328 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4329 struct si_function_info *fninfo)
4330 {
4331 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4332 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4333 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4334 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4335 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4336 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4337 }
4338
4339 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4340 struct si_function_info *fninfo,
4341 unsigned *num_prolog_vgprs)
4342 {
4343 struct si_shader *shader = ctx->shader;
4344
4345 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4346 if (shader->key.as_ls) {
4347 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4348 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4349 } else {
4350 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4351 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4352 }
4353 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4354
4355 if (!shader->is_gs_copy_shader) {
4356 /* Vertex load indices. */
4357 ctx->param_vertex_index0 = fninfo->num_params;
4358 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4359 add_arg(fninfo, ARG_VGPR, ctx->i32);
4360 *num_prolog_vgprs += shader->selector->info.num_inputs;
4361 }
4362 }
4363
4364 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4365 struct si_function_info *fninfo)
4366 {
4367 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4368 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4369 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4370 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4371 }
4372
4373 enum {
4374 /* Convenient merged shader definitions. */
4375 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4376 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4377 };
4378
4379 static void create_function(struct si_shader_context *ctx)
4380 {
4381 struct si_shader *shader = ctx->shader;
4382 struct si_function_info fninfo;
4383 LLVMTypeRef returns[16+32*4];
4384 unsigned i, num_return_sgprs;
4385 unsigned num_returns = 0;
4386 unsigned num_prolog_vgprs = 0;
4387 unsigned type = ctx->type;
4388 unsigned vs_blit_property =
4389 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4390
4391 si_init_function_info(&fninfo);
4392
4393 /* Set MERGED shaders. */
4394 if (ctx->screen->b.chip_class >= GFX9) {
4395 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4396 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4397 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4398 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4399 }
4400
4401 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4402
4403 switch (type) {
4404 case PIPE_SHADER_VERTEX:
4405 declare_global_desc_pointers(ctx, &fninfo);
4406
4407 if (vs_blit_property) {
4408 ctx->param_vs_blit_inputs = fninfo.num_params;
4409 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4410 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4411 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4412
4413 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4414 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4415 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4416 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4417 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4418 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4419 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4420 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4421 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4422 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4423 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4424 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4425 }
4426
4427 /* VGPRs */
4428 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4429 break;
4430 }
4431
4432 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4433 declare_vs_specific_input_sgprs(ctx, &fninfo);
4434
4435 if (shader->key.as_es) {
4436 assert(!shader->selector->nir);
4437 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4438 } else if (shader->key.as_ls) {
4439 assert(!shader->selector->nir);
4440 /* no extra parameters */
4441 } else {
4442 if (shader->is_gs_copy_shader) {
4443 fninfo.num_params = ctx->param_rw_buffers + 1;
4444 fninfo.num_sgpr_params = fninfo.num_params;
4445 }
4446
4447 /* The locations of the other parameters are assigned dynamically. */
4448 declare_streamout_params(ctx, &shader->selector->so,
4449 &fninfo);
4450 }
4451
4452 /* VGPRs */
4453 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4454 break;
4455
4456 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4457 declare_global_desc_pointers(ctx, &fninfo);
4458 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4459 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4460 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4461 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4462 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4463 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4464 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4465 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4466 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4467
4468 /* VGPRs */
4469 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4470 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4471
4472 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4473 * placed after the user SGPRs.
4474 */
4475 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4476 returns[num_returns++] = ctx->i32; /* SGPRs */
4477 for (i = 0; i < 11; i++)
4478 returns[num_returns++] = ctx->f32; /* VGPRs */
4479 break;
4480
4481 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4482 /* Merged stages have 8 system SGPRs at the beginning. */
4483 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4484 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4485 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4486 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4487 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4488 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4489 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4490 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4491
4492 declare_global_desc_pointers(ctx, &fninfo);
4493 declare_per_stage_desc_pointers(ctx, &fninfo,
4494 ctx->type == PIPE_SHADER_VERTEX);
4495 declare_vs_specific_input_sgprs(ctx, &fninfo);
4496
4497 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4498 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4499 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4500 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4501 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4502 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4503
4504 declare_per_stage_desc_pointers(ctx, &fninfo,
4505 ctx->type == PIPE_SHADER_TESS_CTRL);
4506
4507 /* VGPRs (first TCS, then VS) */
4508 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4509 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4510
4511 if (ctx->type == PIPE_SHADER_VERTEX) {
4512 declare_vs_input_vgprs(ctx, &fninfo,
4513 &num_prolog_vgprs);
4514
4515 /* LS return values are inputs to the TCS main shader part. */
4516 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4517 returns[num_returns++] = ctx->i32; /* SGPRs */
4518 for (i = 0; i < 2; i++)
4519 returns[num_returns++] = ctx->f32; /* VGPRs */
4520 } else {
4521 /* TCS return values are inputs to the TCS epilog.
4522 *
4523 * param_tcs_offchip_offset, param_tcs_factor_offset,
4524 * param_tcs_offchip_layout, and param_rw_buffers
4525 * should be passed to the epilog.
4526 */
4527 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4528 returns[num_returns++] = ctx->i32; /* SGPRs */
4529 for (i = 0; i < 11; i++)
4530 returns[num_returns++] = ctx->f32; /* VGPRs */
4531 }
4532 break;
4533
4534 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4535 /* Merged stages have 8 system SGPRs at the beginning. */
4536 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4537 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4538 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4539 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4540 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4541 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4542 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4543 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4544
4545 declare_global_desc_pointers(ctx, &fninfo);
4546 declare_per_stage_desc_pointers(ctx, &fninfo,
4547 (ctx->type == PIPE_SHADER_VERTEX ||
4548 ctx->type == PIPE_SHADER_TESS_EVAL));
4549 if (ctx->type == PIPE_SHADER_VERTEX) {
4550 declare_vs_specific_input_sgprs(ctx, &fninfo);
4551 } else {
4552 /* TESS_EVAL (and also GEOMETRY):
4553 * Declare as many input SGPRs as the VS has. */
4554 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4555 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4556 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4557 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4558 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4559 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4560 }
4561
4562 declare_per_stage_desc_pointers(ctx, &fninfo,
4563 ctx->type == PIPE_SHADER_GEOMETRY);
4564
4565 /* VGPRs (first GS, then VS/TES) */
4566 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4567 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4568 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4569 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4570 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4571
4572 if (ctx->type == PIPE_SHADER_VERTEX) {
4573 declare_vs_input_vgprs(ctx, &fninfo,
4574 &num_prolog_vgprs);
4575 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4576 declare_tes_input_vgprs(ctx, &fninfo);
4577 }
4578
4579 if (ctx->type == PIPE_SHADER_VERTEX ||
4580 ctx->type == PIPE_SHADER_TESS_EVAL) {
4581 /* ES return values are inputs to GS. */
4582 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4583 returns[num_returns++] = ctx->i32; /* SGPRs */
4584 for (i = 0; i < 5; i++)
4585 returns[num_returns++] = ctx->f32; /* VGPRs */
4586 }
4587 break;
4588
4589 case PIPE_SHADER_TESS_EVAL:
4590 declare_global_desc_pointers(ctx, &fninfo);
4591 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4592 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4593 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4594
4595 if (shader->key.as_es) {
4596 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4597 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4598 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4599 } else {
4600 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4601 declare_streamout_params(ctx, &shader->selector->so,
4602 &fninfo);
4603 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4604 }
4605
4606 /* VGPRs */
4607 declare_tes_input_vgprs(ctx, &fninfo);
4608 break;
4609
4610 case PIPE_SHADER_GEOMETRY:
4611 declare_global_desc_pointers(ctx, &fninfo);
4612 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4613 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4614 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4615
4616 /* VGPRs */
4617 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4618 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4619 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4620 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4621 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4622 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4623 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4624 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4625 break;
4626
4627 case PIPE_SHADER_FRAGMENT:
4628 declare_global_desc_pointers(ctx, &fninfo);
4629 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4630 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4631 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4632
4633 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4634 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4635 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4636 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4637 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4638 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4639 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4640 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4641 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4642 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4643 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4644 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4645 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4646 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4647 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4648 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4649 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4650 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4651 shader->info.face_vgpr_index = 20;
4652 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4653 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4654 shader->info.ancillary_vgpr_index = 21;
4655 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4656 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4657 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4658
4659 /* Color inputs from the prolog. */
4660 if (shader->selector->info.colors_read) {
4661 unsigned num_color_elements =
4662 util_bitcount(shader->selector->info.colors_read);
4663
4664 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4665 for (i = 0; i < num_color_elements; i++)
4666 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4667
4668 num_prolog_vgprs += num_color_elements;
4669 }
4670
4671 /* Outputs for the epilog. */
4672 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4673 num_returns =
4674 num_return_sgprs +
4675 util_bitcount(shader->selector->info.colors_written) * 4 +
4676 shader->selector->info.writes_z +
4677 shader->selector->info.writes_stencil +
4678 shader->selector->info.writes_samplemask +
4679 1 /* SampleMaskIn */;
4680
4681 num_returns = MAX2(num_returns,
4682 num_return_sgprs +
4683 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4684
4685 for (i = 0; i < num_return_sgprs; i++)
4686 returns[i] = ctx->i32;
4687 for (; i < num_returns; i++)
4688 returns[i] = ctx->f32;
4689 break;
4690
4691 case PIPE_SHADER_COMPUTE:
4692 declare_global_desc_pointers(ctx, &fninfo);
4693 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4694 if (shader->selector->info.uses_grid_size)
4695 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4696 if (shader->selector->info.uses_block_size)
4697 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4698
4699 for (i = 0; i < 3; i++) {
4700 ctx->param_block_id[i] = -1;
4701 if (shader->selector->info.uses_block_id[i])
4702 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4703 }
4704
4705 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4706 break;
4707 default:
4708 assert(0 && "unimplemented shader");
4709 return;
4710 }
4711
4712 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4713 si_get_max_workgroup_size(shader));
4714
4715 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4716 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4717 ctx->separate_prolog) {
4718 si_llvm_add_attribute(ctx->main_fn,
4719 "InitialPSInputAddr",
4720 S_0286D0_PERSP_SAMPLE_ENA(1) |
4721 S_0286D0_PERSP_CENTER_ENA(1) |
4722 S_0286D0_PERSP_CENTROID_ENA(1) |
4723 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4724 S_0286D0_LINEAR_CENTER_ENA(1) |
4725 S_0286D0_LINEAR_CENTROID_ENA(1) |
4726 S_0286D0_FRONT_FACE_ENA(1) |
4727 S_0286D0_ANCILLARY_ENA(1) |
4728 S_0286D0_POS_FIXED_PT_ENA(1));
4729 }
4730
4731 shader->info.num_input_sgprs = 0;
4732 shader->info.num_input_vgprs = 0;
4733
4734 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4735 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4736
4737 for (; i < fninfo.num_params; ++i)
4738 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4739
4740 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4741 shader->info.num_input_vgprs -= num_prolog_vgprs;
4742
4743 if (shader->key.as_ls ||
4744 ctx->type == PIPE_SHADER_TESS_CTRL ||
4745 /* GFX9 has the ESGS ring buffer in LDS. */
4746 (ctx->screen->b.chip_class >= GFX9 &&
4747 (shader->key.as_es ||
4748 ctx->type == PIPE_SHADER_GEOMETRY)))
4749 ac_declare_lds_as_pointer(&ctx->ac);
4750 }
4751
4752 /**
4753 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4754 * for later use.
4755 */
4756 static void preload_ring_buffers(struct si_shader_context *ctx)
4757 {
4758 LLVMBuilderRef builder = ctx->ac.builder;
4759
4760 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4761 ctx->param_rw_buffers);
4762
4763 if (ctx->screen->b.chip_class <= VI &&
4764 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4765 unsigned ring =
4766 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4767 : SI_ES_RING_ESGS;
4768 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4769
4770 ctx->esgs_ring =
4771 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4772 }
4773
4774 if (ctx->shader->is_gs_copy_shader) {
4775 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4776
4777 ctx->gsvs_ring[0] =
4778 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4779 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4780 const struct si_shader_selector *sel = ctx->shader->selector;
4781 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4782 LLVMValueRef base_ring;
4783
4784 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4785
4786 /* The conceptual layout of the GSVS ring is
4787 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4788 * but the real memory layout is swizzled across
4789 * threads:
4790 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4791 * t16v0c0 ..
4792 * Override the buffer descriptor accordingly.
4793 */
4794 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4795 uint64_t stream_offset = 0;
4796
4797 for (unsigned stream = 0; stream < 4; ++stream) {
4798 unsigned num_components;
4799 unsigned stride;
4800 unsigned num_records;
4801 LLVMValueRef ring, tmp;
4802
4803 num_components = sel->info.num_stream_output_components[stream];
4804 if (!num_components)
4805 continue;
4806
4807 stride = 4 * num_components * sel->gs_max_out_vertices;
4808
4809 /* Limit on the stride field for <= CIK. */
4810 assert(stride < (1 << 14));
4811
4812 num_records = 64;
4813
4814 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4815 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4816 tmp = LLVMBuildAdd(builder, tmp,
4817 LLVMConstInt(ctx->i64,
4818 stream_offset, 0), "");
4819 stream_offset += stride * 64;
4820
4821 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4822 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4823 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4824 tmp = LLVMBuildOr(builder, tmp,
4825 LLVMConstInt(ctx->i32,
4826 S_008F04_STRIDE(stride) |
4827 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4828 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4829 ring = LLVMBuildInsertElement(builder, ring,
4830 LLVMConstInt(ctx->i32, num_records, 0),
4831 LLVMConstInt(ctx->i32, 2, 0), "");
4832 ring = LLVMBuildInsertElement(builder, ring,
4833 LLVMConstInt(ctx->i32,
4834 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4835 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4836 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4837 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4838 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4839 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4840 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4841 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4842 S_008F0C_ADD_TID_ENABLE(1),
4843 0),
4844 LLVMConstInt(ctx->i32, 3, 0), "");
4845
4846 ctx->gsvs_ring[stream] = ring;
4847 }
4848 }
4849 }
4850
4851 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4852 LLVMValueRef param_rw_buffers,
4853 unsigned param_pos_fixed_pt)
4854 {
4855 LLVMBuilderRef builder = ctx->ac.builder;
4856 LLVMValueRef slot, desc, offset, row, bit, address[2];
4857
4858 /* Use the fixed-point gl_FragCoord input.
4859 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4860 * per coordinate to get the repeating effect.
4861 */
4862 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4863 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4864
4865 /* Load the buffer descriptor. */
4866 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4867 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4868
4869 /* The stipple pattern is 32x32, each row has 32 bits. */
4870 offset = LLVMBuildMul(builder, address[1],
4871 LLVMConstInt(ctx->i32, 4, 0), "");
4872 row = buffer_load_const(ctx, desc, offset);
4873 row = ac_to_integer(&ctx->ac, row);
4874 bit = LLVMBuildLShr(builder, row, address[0], "");
4875 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4876 ac_build_kill_if_false(&ctx->ac, bit);
4877 }
4878
4879 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4880 struct si_shader_config *conf,
4881 unsigned symbol_offset)
4882 {
4883 unsigned i;
4884 const unsigned char *config =
4885 ac_shader_binary_config_start(binary, symbol_offset);
4886 bool really_needs_scratch = false;
4887
4888 /* LLVM adds SGPR spills to the scratch size.
4889 * Find out if we really need the scratch buffer.
4890 */
4891 for (i = 0; i < binary->reloc_count; i++) {
4892 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4893
4894 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4895 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4896 really_needs_scratch = true;
4897 break;
4898 }
4899 }
4900
4901 /* XXX: We may be able to emit some of these values directly rather than
4902 * extracting fields to be emitted later.
4903 */
4904
4905 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4906 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4907 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4908 switch (reg) {
4909 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4910 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4911 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4912 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4913 case R_00B848_COMPUTE_PGM_RSRC1:
4914 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4915 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4916 conf->float_mode = G_00B028_FLOAT_MODE(value);
4917 conf->rsrc1 = value;
4918 break;
4919 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4920 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4921 break;
4922 case R_00B84C_COMPUTE_PGM_RSRC2:
4923 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4924 conf->rsrc2 = value;
4925 break;
4926 case R_0286CC_SPI_PS_INPUT_ENA:
4927 conf->spi_ps_input_ena = value;
4928 break;
4929 case R_0286D0_SPI_PS_INPUT_ADDR:
4930 conf->spi_ps_input_addr = value;
4931 break;
4932 case R_0286E8_SPI_TMPRING_SIZE:
4933 case R_00B860_COMPUTE_TMPRING_SIZE:
4934 /* WAVESIZE is in units of 256 dwords. */
4935 if (really_needs_scratch)
4936 conf->scratch_bytes_per_wave =
4937 G_00B860_WAVESIZE(value) * 256 * 4;
4938 break;
4939 case 0x4: /* SPILLED_SGPRS */
4940 conf->spilled_sgprs = value;
4941 break;
4942 case 0x8: /* SPILLED_VGPRS */
4943 conf->spilled_vgprs = value;
4944 break;
4945 default:
4946 {
4947 static bool printed;
4948
4949 if (!printed) {
4950 fprintf(stderr, "Warning: LLVM emitted unknown "
4951 "config register: 0x%x\n", reg);
4952 printed = true;
4953 }
4954 }
4955 break;
4956 }
4957 }
4958
4959 if (!conf->spi_ps_input_addr)
4960 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4961 }
4962
4963 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4964 uint64_t scratch_va)
4965 {
4966 unsigned i;
4967 uint32_t scratch_rsrc_dword0 = scratch_va;
4968 uint32_t scratch_rsrc_dword1 =
4969 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4970
4971 /* Enable scratch coalescing. */
4972 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4973
4974 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4975 const struct ac_shader_reloc *reloc =
4976 &shader->binary.relocs[i];
4977 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4978 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4979 &scratch_rsrc_dword0, 4);
4980 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4981 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4982 &scratch_rsrc_dword1, 4);
4983 }
4984 }
4985 }
4986
4987 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4988 {
4989 unsigned size = shader->binary.code_size;
4990
4991 if (shader->prolog)
4992 size += shader->prolog->binary.code_size;
4993 if (shader->previous_stage)
4994 size += shader->previous_stage->binary.code_size;
4995 if (shader->prolog2)
4996 size += shader->prolog2->binary.code_size;
4997 if (shader->epilog)
4998 size += shader->epilog->binary.code_size;
4999 return size;
5000 }
5001
5002 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5003 {
5004 const struct ac_shader_binary *prolog =
5005 shader->prolog ? &shader->prolog->binary : NULL;
5006 const struct ac_shader_binary *previous_stage =
5007 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5008 const struct ac_shader_binary *prolog2 =
5009 shader->prolog2 ? &shader->prolog2->binary : NULL;
5010 const struct ac_shader_binary *epilog =
5011 shader->epilog ? &shader->epilog->binary : NULL;
5012 const struct ac_shader_binary *mainb = &shader->binary;
5013 unsigned bo_size = si_get_shader_binary_size(shader) +
5014 (!epilog ? mainb->rodata_size : 0);
5015 unsigned char *ptr;
5016
5017 assert(!prolog || !prolog->rodata_size);
5018 assert(!previous_stage || !previous_stage->rodata_size);
5019 assert(!prolog2 || !prolog2->rodata_size);
5020 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5021 !mainb->rodata_size);
5022 assert(!epilog || !epilog->rodata_size);
5023
5024 r600_resource_reference(&shader->bo, NULL);
5025 shader->bo = (struct r600_resource*)
5026 pipe_buffer_create(&sscreen->b.b, 0,
5027 PIPE_USAGE_IMMUTABLE,
5028 align(bo_size, SI_CPDMA_ALIGNMENT));
5029 if (!shader->bo)
5030 return -ENOMEM;
5031
5032 /* Upload. */
5033 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5034 PIPE_TRANSFER_READ_WRITE |
5035 PIPE_TRANSFER_UNSYNCHRONIZED);
5036
5037 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5038 * endian-independent. */
5039 if (prolog) {
5040 memcpy(ptr, prolog->code, prolog->code_size);
5041 ptr += prolog->code_size;
5042 }
5043 if (previous_stage) {
5044 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5045 ptr += previous_stage->code_size;
5046 }
5047 if (prolog2) {
5048 memcpy(ptr, prolog2->code, prolog2->code_size);
5049 ptr += prolog2->code_size;
5050 }
5051
5052 memcpy(ptr, mainb->code, mainb->code_size);
5053 ptr += mainb->code_size;
5054
5055 if (epilog)
5056 memcpy(ptr, epilog->code, epilog->code_size);
5057 else if (mainb->rodata_size > 0)
5058 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5059
5060 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5061 return 0;
5062 }
5063
5064 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5065 struct pipe_debug_callback *debug,
5066 const char *name, FILE *file)
5067 {
5068 char *line, *p;
5069 unsigned i, count;
5070
5071 if (binary->disasm_string) {
5072 fprintf(file, "Shader %s disassembly:\n", name);
5073 fprintf(file, "%s", binary->disasm_string);
5074
5075 if (debug && debug->debug_message) {
5076 /* Very long debug messages are cut off, so send the
5077 * disassembly one line at a time. This causes more
5078 * overhead, but on the plus side it simplifies
5079 * parsing of resulting logs.
5080 */
5081 pipe_debug_message(debug, SHADER_INFO,
5082 "Shader Disassembly Begin");
5083
5084 line = binary->disasm_string;
5085 while (*line) {
5086 p = util_strchrnul(line, '\n');
5087 count = p - line;
5088
5089 if (count) {
5090 pipe_debug_message(debug, SHADER_INFO,
5091 "%.*s", count, line);
5092 }
5093
5094 if (!*p)
5095 break;
5096 line = p + 1;
5097 }
5098
5099 pipe_debug_message(debug, SHADER_INFO,
5100 "Shader Disassembly End");
5101 }
5102 } else {
5103 fprintf(file, "Shader %s binary:\n", name);
5104 for (i = 0; i < binary->code_size; i += 4) {
5105 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5106 binary->code[i + 3], binary->code[i + 2],
5107 binary->code[i + 1], binary->code[i]);
5108 }
5109 }
5110 }
5111
5112 static void si_shader_dump_stats(struct si_screen *sscreen,
5113 const struct si_shader *shader,
5114 struct pipe_debug_callback *debug,
5115 unsigned processor,
5116 FILE *file,
5117 bool check_debug_option)
5118 {
5119 const struct si_shader_config *conf = &shader->config;
5120 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5121 unsigned code_size = si_get_shader_binary_size(shader);
5122 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5123 unsigned lds_per_wave = 0;
5124 unsigned max_simd_waves;
5125
5126 switch (sscreen->b.family) {
5127 /* These always have 8 waves: */
5128 case CHIP_POLARIS10:
5129 case CHIP_POLARIS11:
5130 case CHIP_POLARIS12:
5131 max_simd_waves = 8;
5132 break;
5133 default:
5134 max_simd_waves = 10;
5135 }
5136
5137 /* Compute LDS usage for PS. */
5138 switch (processor) {
5139 case PIPE_SHADER_FRAGMENT:
5140 /* The minimum usage per wave is (num_inputs * 48). The maximum
5141 * usage is (num_inputs * 48 * 16).
5142 * We can get anything in between and it varies between waves.
5143 *
5144 * The 48 bytes per input for a single primitive is equal to
5145 * 4 bytes/component * 4 components/input * 3 points.
5146 *
5147 * Other stages don't know the size at compile time or don't
5148 * allocate LDS per wave, but instead they do it per thread group.
5149 */
5150 lds_per_wave = conf->lds_size * lds_increment +
5151 align(num_inputs * 48, lds_increment);
5152 break;
5153 case PIPE_SHADER_COMPUTE:
5154 if (shader->selector) {
5155 unsigned max_workgroup_size =
5156 si_get_max_workgroup_size(shader);
5157 lds_per_wave = (conf->lds_size * lds_increment) /
5158 DIV_ROUND_UP(max_workgroup_size, 64);
5159 }
5160 break;
5161 }
5162
5163 /* Compute the per-SIMD wave counts. */
5164 if (conf->num_sgprs) {
5165 if (sscreen->b.chip_class >= VI)
5166 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5167 else
5168 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5169 }
5170
5171 if (conf->num_vgprs)
5172 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5173
5174 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5175 * 16KB makes some SIMDs unoccupied). */
5176 if (lds_per_wave)
5177 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5178
5179 if (!check_debug_option ||
5180 si_can_dump_shader(&sscreen->b, processor)) {
5181 if (processor == PIPE_SHADER_FRAGMENT) {
5182 fprintf(file, "*** SHADER CONFIG ***\n"
5183 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5184 "SPI_PS_INPUT_ENA = 0x%04x\n",
5185 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5186 }
5187
5188 fprintf(file, "*** SHADER STATS ***\n"
5189 "SGPRS: %d\n"
5190 "VGPRS: %d\n"
5191 "Spilled SGPRs: %d\n"
5192 "Spilled VGPRs: %d\n"
5193 "Private memory VGPRs: %d\n"
5194 "Code Size: %d bytes\n"
5195 "LDS: %d blocks\n"
5196 "Scratch: %d bytes per wave\n"
5197 "Max Waves: %d\n"
5198 "********************\n\n\n",
5199 conf->num_sgprs, conf->num_vgprs,
5200 conf->spilled_sgprs, conf->spilled_vgprs,
5201 conf->private_mem_vgprs, code_size,
5202 conf->lds_size, conf->scratch_bytes_per_wave,
5203 max_simd_waves);
5204 }
5205
5206 pipe_debug_message(debug, SHADER_INFO,
5207 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5208 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5209 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5210 conf->num_sgprs, conf->num_vgprs, code_size,
5211 conf->lds_size, conf->scratch_bytes_per_wave,
5212 max_simd_waves, conf->spilled_sgprs,
5213 conf->spilled_vgprs, conf->private_mem_vgprs);
5214 }
5215
5216 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5217 {
5218 switch (processor) {
5219 case PIPE_SHADER_VERTEX:
5220 if (shader->key.as_es)
5221 return "Vertex Shader as ES";
5222 else if (shader->key.as_ls)
5223 return "Vertex Shader as LS";
5224 else
5225 return "Vertex Shader as VS";
5226 case PIPE_SHADER_TESS_CTRL:
5227 return "Tessellation Control Shader";
5228 case PIPE_SHADER_TESS_EVAL:
5229 if (shader->key.as_es)
5230 return "Tessellation Evaluation Shader as ES";
5231 else
5232 return "Tessellation Evaluation Shader as VS";
5233 case PIPE_SHADER_GEOMETRY:
5234 if (shader->is_gs_copy_shader)
5235 return "GS Copy Shader as VS";
5236 else
5237 return "Geometry Shader";
5238 case PIPE_SHADER_FRAGMENT:
5239 return "Pixel Shader";
5240 case PIPE_SHADER_COMPUTE:
5241 return "Compute Shader";
5242 default:
5243 return "Unknown Shader";
5244 }
5245 }
5246
5247 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5248 struct pipe_debug_callback *debug, unsigned processor,
5249 FILE *file, bool check_debug_option)
5250 {
5251 if (!check_debug_option ||
5252 si_can_dump_shader(&sscreen->b, processor))
5253 si_dump_shader_key(processor, shader, file);
5254
5255 if (!check_debug_option && shader->binary.llvm_ir_string) {
5256 if (shader->previous_stage &&
5257 shader->previous_stage->binary.llvm_ir_string) {
5258 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5259 si_get_shader_name(shader, processor));
5260 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5261 }
5262
5263 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5264 si_get_shader_name(shader, processor));
5265 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5266 }
5267
5268 if (!check_debug_option ||
5269 (si_can_dump_shader(&sscreen->b, processor) &&
5270 !(sscreen->b.debug_flags & DBG(NO_ASM)))) {
5271 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5272
5273 if (shader->prolog)
5274 si_shader_dump_disassembly(&shader->prolog->binary,
5275 debug, "prolog", file);
5276 if (shader->previous_stage)
5277 si_shader_dump_disassembly(&shader->previous_stage->binary,
5278 debug, "previous stage", file);
5279 if (shader->prolog2)
5280 si_shader_dump_disassembly(&shader->prolog2->binary,
5281 debug, "prolog2", file);
5282
5283 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5284
5285 if (shader->epilog)
5286 si_shader_dump_disassembly(&shader->epilog->binary,
5287 debug, "epilog", file);
5288 fprintf(file, "\n");
5289 }
5290
5291 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5292 check_debug_option);
5293 }
5294
5295 static int si_compile_llvm(struct si_screen *sscreen,
5296 struct ac_shader_binary *binary,
5297 struct si_shader_config *conf,
5298 LLVMTargetMachineRef tm,
5299 LLVMModuleRef mod,
5300 struct pipe_debug_callback *debug,
5301 unsigned processor,
5302 const char *name)
5303 {
5304 int r = 0;
5305 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5306
5307 if (si_can_dump_shader(&sscreen->b, processor)) {
5308 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5309
5310 if (!(sscreen->b.debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5311 fprintf(stderr, "%s LLVM IR:\n\n", name);
5312 ac_dump_module(mod);
5313 fprintf(stderr, "\n");
5314 }
5315 }
5316
5317 if (sscreen->record_llvm_ir) {
5318 char *ir = LLVMPrintModuleToString(mod);
5319 binary->llvm_ir_string = strdup(ir);
5320 LLVMDisposeMessage(ir);
5321 }
5322
5323 if (!si_replace_shader(count, binary)) {
5324 r = si_llvm_compile(mod, binary, tm, debug);
5325 if (r)
5326 return r;
5327 }
5328
5329 si_shader_binary_read_config(binary, conf, 0);
5330
5331 /* Enable 64-bit and 16-bit denormals, because there is no performance
5332 * cost.
5333 *
5334 * If denormals are enabled, all floating-point output modifiers are
5335 * ignored.
5336 *
5337 * Don't enable denormals for 32-bit floats, because:
5338 * - Floating-point output modifiers would be ignored by the hw.
5339 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5340 * have to stop using those.
5341 * - SI & CI would be very slow.
5342 */
5343 conf->float_mode |= V_00B028_FP_64_DENORMS;
5344
5345 FREE(binary->config);
5346 FREE(binary->global_symbol_offsets);
5347 binary->config = NULL;
5348 binary->global_symbol_offsets = NULL;
5349
5350 /* Some shaders can't have rodata because their binaries can be
5351 * concatenated.
5352 */
5353 if (binary->rodata_size &&
5354 (processor == PIPE_SHADER_VERTEX ||
5355 processor == PIPE_SHADER_TESS_CTRL ||
5356 processor == PIPE_SHADER_TESS_EVAL ||
5357 processor == PIPE_SHADER_FRAGMENT)) {
5358 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5359 return -EINVAL;
5360 }
5361
5362 return r;
5363 }
5364
5365 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5366 {
5367 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5368 LLVMBuildRetVoid(ctx->ac.builder);
5369 else
5370 LLVMBuildRet(ctx->ac.builder, ret);
5371 }
5372
5373 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5374 struct si_shader *
5375 si_generate_gs_copy_shader(struct si_screen *sscreen,
5376 LLVMTargetMachineRef tm,
5377 struct si_shader_selector *gs_selector,
5378 struct pipe_debug_callback *debug)
5379 {
5380 struct si_shader_context ctx;
5381 struct si_shader *shader;
5382 LLVMBuilderRef builder;
5383 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5384 struct lp_build_context *uint = &bld_base->uint_bld;
5385 struct si_shader_output_values *outputs;
5386 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5387 int i, r;
5388
5389 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5390
5391 if (!outputs)
5392 return NULL;
5393
5394 shader = CALLOC_STRUCT(si_shader);
5395 if (!shader) {
5396 FREE(outputs);
5397 return NULL;
5398 }
5399
5400 /* We can leave the fence as permanently signaled because the GS copy
5401 * shader only becomes visible globally after it has been compiled. */
5402 util_queue_fence_init(&shader->ready);
5403
5404 shader->selector = gs_selector;
5405 shader->is_gs_copy_shader = true;
5406
5407 si_init_shader_ctx(&ctx, sscreen, tm);
5408 ctx.shader = shader;
5409 ctx.type = PIPE_SHADER_VERTEX;
5410
5411 builder = ctx.ac.builder;
5412
5413 create_function(&ctx);
5414 preload_ring_buffers(&ctx);
5415
5416 LLVMValueRef voffset =
5417 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5418
5419 /* Fetch the vertex stream ID.*/
5420 LLVMValueRef stream_id;
5421
5422 if (gs_selector->so.num_outputs)
5423 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5424 else
5425 stream_id = ctx.i32_0;
5426
5427 /* Fill in output information. */
5428 for (i = 0; i < gsinfo->num_outputs; ++i) {
5429 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5430 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5431
5432 for (int chan = 0; chan < 4; chan++) {
5433 outputs[i].vertex_stream[chan] =
5434 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5435 }
5436 }
5437
5438 LLVMBasicBlockRef end_bb;
5439 LLVMValueRef switch_inst;
5440
5441 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5442 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5443
5444 for (int stream = 0; stream < 4; stream++) {
5445 LLVMBasicBlockRef bb;
5446 unsigned offset;
5447
5448 if (!gsinfo->num_stream_output_components[stream])
5449 continue;
5450
5451 if (stream > 0 && !gs_selector->so.num_outputs)
5452 continue;
5453
5454 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5455 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5456 LLVMPositionBuilderAtEnd(builder, bb);
5457
5458 /* Fetch vertex data from GSVS ring */
5459 offset = 0;
5460 for (i = 0; i < gsinfo->num_outputs; ++i) {
5461 for (unsigned chan = 0; chan < 4; chan++) {
5462 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5463 outputs[i].vertex_stream[chan] != stream) {
5464 outputs[i].values[chan] = ctx.bld_base.base.undef;
5465 continue;
5466 }
5467
5468 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5469 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5470 offset++;
5471
5472 outputs[i].values[chan] =
5473 ac_build_buffer_load(&ctx.ac,
5474 ctx.gsvs_ring[0], 1,
5475 ctx.i32_0, voffset,
5476 soffset, 0, 1, 1,
5477 true, false);
5478 }
5479 }
5480
5481 /* Streamout and exports. */
5482 if (gs_selector->so.num_outputs) {
5483 si_llvm_emit_streamout(&ctx, outputs,
5484 gsinfo->num_outputs,
5485 stream);
5486 }
5487
5488 if (stream == 0)
5489 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5490
5491 LLVMBuildBr(builder, end_bb);
5492 }
5493
5494 LLVMPositionBuilderAtEnd(builder, end_bb);
5495
5496 LLVMBuildRetVoid(ctx.ac.builder);
5497
5498 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5499 si_llvm_optimize_module(&ctx);
5500
5501 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5502 &ctx.shader->config, ctx.tm,
5503 ctx.gallivm.module,
5504 debug, PIPE_SHADER_GEOMETRY,
5505 "GS Copy Shader");
5506 if (!r) {
5507 if (si_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5508 fprintf(stderr, "GS Copy Shader:\n");
5509 si_shader_dump(sscreen, ctx.shader, debug,
5510 PIPE_SHADER_GEOMETRY, stderr, true);
5511 r = si_shader_binary_upload(sscreen, ctx.shader);
5512 }
5513
5514 si_llvm_dispose(&ctx);
5515
5516 FREE(outputs);
5517
5518 if (r != 0) {
5519 FREE(shader);
5520 shader = NULL;
5521 }
5522 return shader;
5523 }
5524
5525 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5526 const struct si_vs_prolog_bits *prolog,
5527 const char *prefix, FILE *f)
5528 {
5529 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5530 prefix, prolog->instance_divisor_is_one);
5531 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5532 prefix, prolog->instance_divisor_is_fetched);
5533 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5534 prefix, prolog->ls_vgpr_fix);
5535
5536 fprintf(f, " mono.vs.fix_fetch = {");
5537 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5538 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5539 fprintf(f, "}\n");
5540 }
5541
5542 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5543 FILE *f)
5544 {
5545 const struct si_shader_key *key = &shader->key;
5546
5547 fprintf(f, "SHADER KEY\n");
5548
5549 switch (processor) {
5550 case PIPE_SHADER_VERTEX:
5551 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5552 "part.vs.prolog", f);
5553 fprintf(f, " as_es = %u\n", key->as_es);
5554 fprintf(f, " as_ls = %u\n", key->as_ls);
5555 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5556 key->mono.u.vs_export_prim_id);
5557 break;
5558
5559 case PIPE_SHADER_TESS_CTRL:
5560 if (shader->selector->screen->b.chip_class >= GFX9) {
5561 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5562 "part.tcs.ls_prolog", f);
5563 }
5564 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5565 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5566 break;
5567
5568 case PIPE_SHADER_TESS_EVAL:
5569 fprintf(f, " as_es = %u\n", key->as_es);
5570 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5571 key->mono.u.vs_export_prim_id);
5572 break;
5573
5574 case PIPE_SHADER_GEOMETRY:
5575 if (shader->is_gs_copy_shader)
5576 break;
5577
5578 if (shader->selector->screen->b.chip_class >= GFX9 &&
5579 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5580 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5581 "part.gs.vs_prolog", f);
5582 }
5583 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5584 break;
5585
5586 case PIPE_SHADER_COMPUTE:
5587 break;
5588
5589 case PIPE_SHADER_FRAGMENT:
5590 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5591 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5592 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5593 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5594 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5595 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5596 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5597 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5598 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5599 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5600 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5601 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5602 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5603 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5604 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5605 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5606 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5607 break;
5608
5609 default:
5610 assert(0);
5611 }
5612
5613 if ((processor == PIPE_SHADER_GEOMETRY ||
5614 processor == PIPE_SHADER_TESS_EVAL ||
5615 processor == PIPE_SHADER_VERTEX) &&
5616 !key->as_es && !key->as_ls) {
5617 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5618 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5619 }
5620 }
5621
5622 static void si_init_shader_ctx(struct si_shader_context *ctx,
5623 struct si_screen *sscreen,
5624 LLVMTargetMachineRef tm)
5625 {
5626 struct lp_build_tgsi_context *bld_base;
5627
5628 si_llvm_context_init(ctx, sscreen, tm);
5629
5630 bld_base = &ctx->bld_base;
5631 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5632
5633 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5634 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5635 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5636
5637 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5638
5639 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5640
5641 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5642 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5643 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5644 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5645
5646 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5647 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5648 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5649 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5650 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5651 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5652 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5653 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5654 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5655
5656 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5657 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5658 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5659 }
5660
5661 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5662 {
5663 struct si_shader *shader = ctx->shader;
5664 struct tgsi_shader_info *info = &shader->selector->info;
5665
5666 if ((ctx->type != PIPE_SHADER_VERTEX &&
5667 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5668 shader->key.as_ls ||
5669 shader->key.as_es)
5670 return;
5671
5672 ac_optimize_vs_outputs(&ctx->ac,
5673 ctx->main_fn,
5674 shader->info.vs_output_param_offset,
5675 info->num_outputs,
5676 &shader->info.nr_param_exports);
5677 }
5678
5679 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5680 {
5681 ctx->shader->config.private_mem_vgprs = 0;
5682
5683 /* Process all LLVM instructions. */
5684 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5685 while (bb) {
5686 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5687
5688 while (next) {
5689 LLVMValueRef inst = next;
5690 next = LLVMGetNextInstruction(next);
5691
5692 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5693 continue;
5694
5695 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5696 /* No idea why LLVM aligns allocas to 4 elements. */
5697 unsigned alignment = LLVMGetAlignment(inst);
5698 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5699 ctx->shader->config.private_mem_vgprs += dw_size;
5700 }
5701 bb = LLVMGetNextBasicBlock(bb);
5702 }
5703 }
5704
5705 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5706 {
5707 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5708 lp_build_intrinsic(ctx->ac.builder,
5709 "llvm.amdgcn.init.exec", ctx->voidt,
5710 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5711 }
5712
5713 static void si_init_exec_from_input(struct si_shader_context *ctx,
5714 unsigned param, unsigned bitoffset)
5715 {
5716 LLVMValueRef args[] = {
5717 LLVMGetParam(ctx->main_fn, param),
5718 LLVMConstInt(ctx->i32, bitoffset, 0),
5719 };
5720 lp_build_intrinsic(ctx->ac.builder,
5721 "llvm.amdgcn.init.exec.from.input",
5722 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5723 }
5724
5725 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5726 const struct si_vs_prolog_bits *key)
5727 {
5728 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5729 * VS prolog. */
5730 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5731 }
5732
5733 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5734 bool is_monolithic)
5735 {
5736 struct si_shader *shader = ctx->shader;
5737 struct si_shader_selector *sel = shader->selector;
5738 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5739
5740 // TODO clean all this up!
5741 switch (ctx->type) {
5742 case PIPE_SHADER_VERTEX:
5743 ctx->load_input = declare_input_vs;
5744 if (shader->key.as_ls)
5745 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5746 else if (shader->key.as_es)
5747 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5748 else {
5749 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5750 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5751 }
5752 break;
5753 case PIPE_SHADER_TESS_CTRL:
5754 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5755 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5756 bld_base->emit_store = store_output_tcs;
5757 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5758 break;
5759 case PIPE_SHADER_TESS_EVAL:
5760 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5761 if (shader->key.as_es)
5762 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5763 else {
5764 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5765 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5766 }
5767 break;
5768 case PIPE_SHADER_GEOMETRY:
5769 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5770 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5771 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5772 break;
5773 case PIPE_SHADER_FRAGMENT:
5774 ctx->load_input = declare_input_fs;
5775 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5776 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5777 break;
5778 case PIPE_SHADER_COMPUTE:
5779 break;
5780 default:
5781 assert(!"Unsupported shader type");
5782 return false;
5783 }
5784
5785 ctx->abi.load_ubo = load_ubo;
5786 ctx->abi.load_ssbo = load_ssbo;
5787
5788 create_function(ctx);
5789 preload_ring_buffers(ctx);
5790
5791 /* For GFX9 merged shaders:
5792 * - Set EXEC for the first shader. If the prolog is present, set
5793 * EXEC there instead.
5794 * - Add a barrier before the second shader.
5795 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5796 * an if-statement. This is required for correctness in geometry
5797 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5798 * GS_CUT messages.
5799 *
5800 * For monolithic merged shaders, the first shader is wrapped in an
5801 * if-block together with its prolog in si_build_wrapper_function.
5802 */
5803 if (ctx->screen->b.chip_class >= GFX9) {
5804 if (!is_monolithic &&
5805 sel->info.num_instructions > 1 && /* not empty shader */
5806 (shader->key.as_es || shader->key.as_ls) &&
5807 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5808 (ctx->type == PIPE_SHADER_VERTEX &&
5809 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5810 si_init_exec_from_input(ctx,
5811 ctx->param_merged_wave_info, 0);
5812 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5813 ctx->type == PIPE_SHADER_GEOMETRY) {
5814 if (!is_monolithic)
5815 si_init_exec_full_mask(ctx);
5816
5817 /* The barrier must execute for all shaders in a
5818 * threadgroup.
5819 */
5820 si_llvm_emit_barrier(NULL, bld_base, NULL);
5821
5822 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5823 LLVMValueRef ena =
5824 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5825 ac_get_thread_id(&ctx->ac), num_threads, "");
5826 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5827 }
5828 }
5829
5830 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5831 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5832 for (unsigned i = 0; i < 6; i++) {
5833 ctx->invoc0_tess_factors[i] =
5834 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5835 }
5836 }
5837
5838 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5839 int i;
5840 for (i = 0; i < 4; i++) {
5841 ctx->gs_next_vertex[i] =
5842 lp_build_alloca(&ctx->gallivm,
5843 ctx->i32, "");
5844 }
5845 }
5846
5847 if (sel->force_correct_derivs_after_kill) {
5848 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5849 /* true = don't kill. */
5850 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5851 ctx->postponed_kill);
5852 }
5853
5854 if (sel->tokens) {
5855 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5856 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5857 return false;
5858 }
5859 } else {
5860 if (!si_nir_build_llvm(ctx, sel->nir)) {
5861 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5862 return false;
5863 }
5864 }
5865
5866 si_llvm_build_ret(ctx, ctx->return_value);
5867 return true;
5868 }
5869
5870 /**
5871 * Compute the VS prolog key, which contains all the information needed to
5872 * build the VS prolog function, and set shader->info bits where needed.
5873 *
5874 * \param info Shader info of the vertex shader.
5875 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5876 * \param prolog_key Key of the VS prolog
5877 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5878 * \param key Output shader part key.
5879 */
5880 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5881 unsigned num_input_sgprs,
5882 const struct si_vs_prolog_bits *prolog_key,
5883 struct si_shader *shader_out,
5884 union si_shader_part_key *key)
5885 {
5886 memset(key, 0, sizeof(*key));
5887 key->vs_prolog.states = *prolog_key;
5888 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5889 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5890 key->vs_prolog.as_ls = shader_out->key.as_ls;
5891 key->vs_prolog.as_es = shader_out->key.as_es;
5892
5893 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5894 key->vs_prolog.as_ls = 1;
5895 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5896 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5897 key->vs_prolog.as_es = 1;
5898 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5899 }
5900
5901 /* Enable loading the InstanceID VGPR. */
5902 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5903
5904 if ((key->vs_prolog.states.instance_divisor_is_one |
5905 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5906 shader_out->info.uses_instanceid = true;
5907 }
5908
5909 /**
5910 * Compute the PS prolog key, which contains all the information needed to
5911 * build the PS prolog function, and set related bits in shader->config.
5912 */
5913 static void si_get_ps_prolog_key(struct si_shader *shader,
5914 union si_shader_part_key *key,
5915 bool separate_prolog)
5916 {
5917 struct tgsi_shader_info *info = &shader->selector->info;
5918
5919 memset(key, 0, sizeof(*key));
5920 key->ps_prolog.states = shader->key.part.ps.prolog;
5921 key->ps_prolog.colors_read = info->colors_read;
5922 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5923 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5924 key->ps_prolog.wqm = info->uses_derivatives &&
5925 (key->ps_prolog.colors_read ||
5926 key->ps_prolog.states.force_persp_sample_interp ||
5927 key->ps_prolog.states.force_linear_sample_interp ||
5928 key->ps_prolog.states.force_persp_center_interp ||
5929 key->ps_prolog.states.force_linear_center_interp ||
5930 key->ps_prolog.states.bc_optimize_for_persp ||
5931 key->ps_prolog.states.bc_optimize_for_linear);
5932 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5933
5934 if (info->colors_read) {
5935 unsigned *color = shader->selector->color_attr_index;
5936
5937 if (shader->key.part.ps.prolog.color_two_side) {
5938 /* BCOLORs are stored after the last input. */
5939 key->ps_prolog.num_interp_inputs = info->num_inputs;
5940 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5941 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5942 }
5943
5944 for (unsigned i = 0; i < 2; i++) {
5945 unsigned interp = info->input_interpolate[color[i]];
5946 unsigned location = info->input_interpolate_loc[color[i]];
5947
5948 if (!(info->colors_read & (0xf << i*4)))
5949 continue;
5950
5951 key->ps_prolog.color_attr_index[i] = color[i];
5952
5953 if (shader->key.part.ps.prolog.flatshade_colors &&
5954 interp == TGSI_INTERPOLATE_COLOR)
5955 interp = TGSI_INTERPOLATE_CONSTANT;
5956
5957 switch (interp) {
5958 case TGSI_INTERPOLATE_CONSTANT:
5959 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5960 break;
5961 case TGSI_INTERPOLATE_PERSPECTIVE:
5962 case TGSI_INTERPOLATE_COLOR:
5963 /* Force the interpolation location for colors here. */
5964 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5965 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5966 if (shader->key.part.ps.prolog.force_persp_center_interp)
5967 location = TGSI_INTERPOLATE_LOC_CENTER;
5968
5969 switch (location) {
5970 case TGSI_INTERPOLATE_LOC_SAMPLE:
5971 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5972 shader->config.spi_ps_input_ena |=
5973 S_0286CC_PERSP_SAMPLE_ENA(1);
5974 break;
5975 case TGSI_INTERPOLATE_LOC_CENTER:
5976 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5977 shader->config.spi_ps_input_ena |=
5978 S_0286CC_PERSP_CENTER_ENA(1);
5979 break;
5980 case TGSI_INTERPOLATE_LOC_CENTROID:
5981 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5982 shader->config.spi_ps_input_ena |=
5983 S_0286CC_PERSP_CENTROID_ENA(1);
5984 break;
5985 default:
5986 assert(0);
5987 }
5988 break;
5989 case TGSI_INTERPOLATE_LINEAR:
5990 /* Force the interpolation location for colors here. */
5991 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5992 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5993 if (shader->key.part.ps.prolog.force_linear_center_interp)
5994 location = TGSI_INTERPOLATE_LOC_CENTER;
5995
5996 /* The VGPR assignment for non-monolithic shaders
5997 * works because InitialPSInputAddr is set on the
5998 * main shader and PERSP_PULL_MODEL is never used.
5999 */
6000 switch (location) {
6001 case TGSI_INTERPOLATE_LOC_SAMPLE:
6002 key->ps_prolog.color_interp_vgpr_index[i] =
6003 separate_prolog ? 6 : 9;
6004 shader->config.spi_ps_input_ena |=
6005 S_0286CC_LINEAR_SAMPLE_ENA(1);
6006 break;
6007 case TGSI_INTERPOLATE_LOC_CENTER:
6008 key->ps_prolog.color_interp_vgpr_index[i] =
6009 separate_prolog ? 8 : 11;
6010 shader->config.spi_ps_input_ena |=
6011 S_0286CC_LINEAR_CENTER_ENA(1);
6012 break;
6013 case TGSI_INTERPOLATE_LOC_CENTROID:
6014 key->ps_prolog.color_interp_vgpr_index[i] =
6015 separate_prolog ? 10 : 13;
6016 shader->config.spi_ps_input_ena |=
6017 S_0286CC_LINEAR_CENTROID_ENA(1);
6018 break;
6019 default:
6020 assert(0);
6021 }
6022 break;
6023 default:
6024 assert(0);
6025 }
6026 }
6027 }
6028 }
6029
6030 /**
6031 * Check whether a PS prolog is required based on the key.
6032 */
6033 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6034 {
6035 return key->ps_prolog.colors_read ||
6036 key->ps_prolog.states.force_persp_sample_interp ||
6037 key->ps_prolog.states.force_linear_sample_interp ||
6038 key->ps_prolog.states.force_persp_center_interp ||
6039 key->ps_prolog.states.force_linear_center_interp ||
6040 key->ps_prolog.states.bc_optimize_for_persp ||
6041 key->ps_prolog.states.bc_optimize_for_linear ||
6042 key->ps_prolog.states.poly_stipple ||
6043 key->ps_prolog.states.samplemask_log_ps_iter;
6044 }
6045
6046 /**
6047 * Compute the PS epilog key, which contains all the information needed to
6048 * build the PS epilog function.
6049 */
6050 static void si_get_ps_epilog_key(struct si_shader *shader,
6051 union si_shader_part_key *key)
6052 {
6053 struct tgsi_shader_info *info = &shader->selector->info;
6054 memset(key, 0, sizeof(*key));
6055 key->ps_epilog.colors_written = info->colors_written;
6056 key->ps_epilog.writes_z = info->writes_z;
6057 key->ps_epilog.writes_stencil = info->writes_stencil;
6058 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6059 key->ps_epilog.states = shader->key.part.ps.epilog;
6060 }
6061
6062 /**
6063 * Build the GS prolog function. Rotate the input vertices for triangle strips
6064 * with adjacency.
6065 */
6066 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6067 union si_shader_part_key *key)
6068 {
6069 unsigned num_sgprs, num_vgprs;
6070 struct si_function_info fninfo;
6071 LLVMBuilderRef builder = ctx->ac.builder;
6072 LLVMTypeRef returns[48];
6073 LLVMValueRef func, ret;
6074
6075 si_init_function_info(&fninfo);
6076
6077 if (ctx->screen->b.chip_class >= GFX9) {
6078 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6079 num_vgprs = 5; /* ES inputs are not needed by GS */
6080 } else {
6081 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6082 num_vgprs = 8;
6083 }
6084
6085 for (unsigned i = 0; i < num_sgprs; ++i) {
6086 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6087 returns[i] = ctx->i32;
6088 }
6089
6090 for (unsigned i = 0; i < num_vgprs; ++i) {
6091 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6092 returns[num_sgprs + i] = ctx->f32;
6093 }
6094
6095 /* Create the function. */
6096 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6097 &fninfo, 0);
6098 func = ctx->main_fn;
6099
6100 /* Set the full EXEC mask for the prolog, because we are only fiddling
6101 * with registers here. The main shader part will set the correct EXEC
6102 * mask.
6103 */
6104 if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6105 si_init_exec_full_mask(ctx);
6106
6107 /* Copy inputs to outputs. This should be no-op, as the registers match,
6108 * but it will prevent the compiler from overwriting them unintentionally.
6109 */
6110 ret = ctx->return_value;
6111 for (unsigned i = 0; i < num_sgprs; i++) {
6112 LLVMValueRef p = LLVMGetParam(func, i);
6113 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6114 }
6115 for (unsigned i = 0; i < num_vgprs; i++) {
6116 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6117 p = ac_to_float(&ctx->ac, p);
6118 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6119 }
6120
6121 if (key->gs_prolog.states.tri_strip_adj_fix) {
6122 /* Remap the input vertices for every other primitive. */
6123 const unsigned gfx6_vtx_params[6] = {
6124 num_sgprs,
6125 num_sgprs + 1,
6126 num_sgprs + 3,
6127 num_sgprs + 4,
6128 num_sgprs + 5,
6129 num_sgprs + 6
6130 };
6131 const unsigned gfx9_vtx_params[3] = {
6132 num_sgprs,
6133 num_sgprs + 1,
6134 num_sgprs + 4,
6135 };
6136 LLVMValueRef vtx_in[6], vtx_out[6];
6137 LLVMValueRef prim_id, rotate;
6138
6139 if (ctx->screen->b.chip_class >= GFX9) {
6140 for (unsigned i = 0; i < 3; i++) {
6141 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6142 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6143 }
6144 } else {
6145 for (unsigned i = 0; i < 6; i++)
6146 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6147 }
6148
6149 prim_id = LLVMGetParam(func, num_sgprs + 2);
6150 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6151
6152 for (unsigned i = 0; i < 6; ++i) {
6153 LLVMValueRef base, rotated;
6154 base = vtx_in[i];
6155 rotated = vtx_in[(i + 4) % 6];
6156 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6157 }
6158
6159 if (ctx->screen->b.chip_class >= GFX9) {
6160 for (unsigned i = 0; i < 3; i++) {
6161 LLVMValueRef hi, out;
6162
6163 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6164 LLVMConstInt(ctx->i32, 16, 0), "");
6165 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6166 out = ac_to_float(&ctx->ac, out);
6167 ret = LLVMBuildInsertValue(builder, ret, out,
6168 gfx9_vtx_params[i], "");
6169 }
6170 } else {
6171 for (unsigned i = 0; i < 6; i++) {
6172 LLVMValueRef out;
6173
6174 out = ac_to_float(&ctx->ac, vtx_out[i]);
6175 ret = LLVMBuildInsertValue(builder, ret, out,
6176 gfx6_vtx_params[i], "");
6177 }
6178 }
6179 }
6180
6181 LLVMBuildRet(builder, ret);
6182 }
6183
6184 /**
6185 * Given a list of shader part functions, build a wrapper function that
6186 * runs them in sequence to form a monolithic shader.
6187 */
6188 static void si_build_wrapper_function(struct si_shader_context *ctx,
6189 LLVMValueRef *parts,
6190 unsigned num_parts,
6191 unsigned main_part,
6192 unsigned next_shader_first_part)
6193 {
6194 LLVMBuilderRef builder = ctx->ac.builder;
6195 /* PS epilog has one arg per color component; gfx9 merged shader
6196 * prologs need to forward 32 user SGPRs.
6197 */
6198 struct si_function_info fninfo;
6199 LLVMValueRef initial[64], out[64];
6200 LLVMTypeRef function_type;
6201 unsigned num_first_params;
6202 unsigned num_out, initial_num_out;
6203 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6204 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6205 unsigned num_sgprs, num_vgprs;
6206 unsigned gprs;
6207 struct lp_build_if_state if_state;
6208
6209 si_init_function_info(&fninfo);
6210
6211 for (unsigned i = 0; i < num_parts; ++i) {
6212 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6213 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6214 }
6215
6216 /* The parameters of the wrapper function correspond to those of the
6217 * first part in terms of SGPRs and VGPRs, but we use the types of the
6218 * main part to get the right types. This is relevant for the
6219 * dereferenceable attribute on descriptor table pointers.
6220 */
6221 num_sgprs = 0;
6222 num_vgprs = 0;
6223
6224 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6225 num_first_params = LLVMCountParamTypes(function_type);
6226
6227 for (unsigned i = 0; i < num_first_params; ++i) {
6228 LLVMValueRef param = LLVMGetParam(parts[0], i);
6229
6230 if (ac_is_sgpr_param(param)) {
6231 assert(num_vgprs == 0);
6232 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6233 } else {
6234 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6235 }
6236 }
6237
6238 gprs = 0;
6239 while (gprs < num_sgprs + num_vgprs) {
6240 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6241 LLVMTypeRef type = LLVMTypeOf(param);
6242 unsigned size = ac_get_type_size(type) / 4;
6243
6244 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6245
6246 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6247 assert(gprs + size <= num_sgprs + num_vgprs &&
6248 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6249
6250 gprs += size;
6251 }
6252
6253 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6254 si_get_max_workgroup_size(ctx->shader));
6255
6256 if (is_merged_shader(ctx->shader))
6257 si_init_exec_full_mask(ctx);
6258
6259 /* Record the arguments of the function as if they were an output of
6260 * a previous part.
6261 */
6262 num_out = 0;
6263 num_out_sgpr = 0;
6264
6265 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6266 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6267 LLVMTypeRef param_type = LLVMTypeOf(param);
6268 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6269 unsigned size = ac_get_type_size(param_type) / 4;
6270
6271 if (size == 1) {
6272 if (param_type != out_type)
6273 param = LLVMBuildBitCast(builder, param, out_type, "");
6274 out[num_out++] = param;
6275 } else {
6276 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6277
6278 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6279 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6280 param_type = ctx->i64;
6281 }
6282
6283 if (param_type != vector_type)
6284 param = LLVMBuildBitCast(builder, param, vector_type, "");
6285
6286 for (unsigned j = 0; j < size; ++j)
6287 out[num_out++] = LLVMBuildExtractElement(
6288 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6289 }
6290
6291 if (i < fninfo.num_sgpr_params)
6292 num_out_sgpr = num_out;
6293 }
6294
6295 memcpy(initial, out, sizeof(out));
6296 initial_num_out = num_out;
6297 initial_num_out_sgpr = num_out_sgpr;
6298
6299 /* Now chain the parts. */
6300 for (unsigned part = 0; part < num_parts; ++part) {
6301 LLVMValueRef in[48];
6302 LLVMValueRef ret;
6303 LLVMTypeRef ret_type;
6304 unsigned out_idx = 0;
6305 unsigned num_params = LLVMCountParams(parts[part]);
6306
6307 /* Merged shaders are executed conditionally depending
6308 * on the number of enabled threads passed in the input SGPRs. */
6309 if (is_merged_shader(ctx->shader) && part == 0) {
6310 LLVMValueRef ena, count = initial[3];
6311
6312 count = LLVMBuildAnd(builder, count,
6313 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6314 ena = LLVMBuildICmp(builder, LLVMIntULT,
6315 ac_get_thread_id(&ctx->ac), count, "");
6316 lp_build_if(&if_state, &ctx->gallivm, ena);
6317 }
6318
6319 /* Derive arguments for the next part from outputs of the
6320 * previous one.
6321 */
6322 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6323 LLVMValueRef param;
6324 LLVMTypeRef param_type;
6325 bool is_sgpr;
6326 unsigned param_size;
6327 LLVMValueRef arg = NULL;
6328
6329 param = LLVMGetParam(parts[part], param_idx);
6330 param_type = LLVMTypeOf(param);
6331 param_size = ac_get_type_size(param_type) / 4;
6332 is_sgpr = ac_is_sgpr_param(param);
6333
6334 if (is_sgpr) {
6335 #if HAVE_LLVM < 0x0400
6336 LLVMRemoveAttribute(param, LLVMByValAttribute);
6337 #else
6338 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6339 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6340 #endif
6341 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6342 }
6343
6344 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6345 assert(is_sgpr || out_idx >= num_out_sgpr);
6346
6347 if (param_size == 1)
6348 arg = out[out_idx];
6349 else
6350 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6351
6352 if (LLVMTypeOf(arg) != param_type) {
6353 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6354 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6355 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6356 } else {
6357 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6358 }
6359 }
6360
6361 in[param_idx] = arg;
6362 out_idx += param_size;
6363 }
6364
6365 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6366
6367 if (is_merged_shader(ctx->shader) &&
6368 part + 1 == next_shader_first_part) {
6369 lp_build_endif(&if_state);
6370
6371 /* The second half of the merged shader should use
6372 * the inputs from the toplevel (wrapper) function,
6373 * not the return value from the last call.
6374 *
6375 * That's because the last call was executed condi-
6376 * tionally, so we can't consume it in the main
6377 * block.
6378 */
6379 memcpy(out, initial, sizeof(initial));
6380 num_out = initial_num_out;
6381 num_out_sgpr = initial_num_out_sgpr;
6382 continue;
6383 }
6384
6385 /* Extract the returned GPRs. */
6386 ret_type = LLVMTypeOf(ret);
6387 num_out = 0;
6388 num_out_sgpr = 0;
6389
6390 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6391 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6392
6393 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6394
6395 for (unsigned i = 0; i < ret_size; ++i) {
6396 LLVMValueRef val =
6397 LLVMBuildExtractValue(builder, ret, i, "");
6398
6399 assert(num_out < ARRAY_SIZE(out));
6400 out[num_out++] = val;
6401
6402 if (LLVMTypeOf(val) == ctx->i32) {
6403 assert(num_out_sgpr + 1 == num_out);
6404 num_out_sgpr = num_out;
6405 }
6406 }
6407 }
6408 }
6409
6410 LLVMBuildRetVoid(builder);
6411 }
6412
6413 int si_compile_tgsi_shader(struct si_screen *sscreen,
6414 LLVMTargetMachineRef tm,
6415 struct si_shader *shader,
6416 bool is_monolithic,
6417 struct pipe_debug_callback *debug)
6418 {
6419 struct si_shader_selector *sel = shader->selector;
6420 struct si_shader_context ctx;
6421 int r = -1;
6422
6423 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6424 * conversion fails. */
6425 if (si_can_dump_shader(&sscreen->b, sel->info.processor) &&
6426 !(sscreen->b.debug_flags & DBG(NO_TGSI))) {
6427 if (sel->tokens)
6428 tgsi_dump(sel->tokens, 0);
6429 else
6430 nir_print_shader(sel->nir, stderr);
6431 si_dump_streamout(&sel->so);
6432 }
6433
6434 si_init_shader_ctx(&ctx, sscreen, tm);
6435 si_llvm_context_set_tgsi(&ctx, shader);
6436 ctx.separate_prolog = !is_monolithic;
6437
6438 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6439 sizeof(shader->info.vs_output_param_offset));
6440
6441 shader->info.uses_instanceid = sel->info.uses_instanceid;
6442
6443 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6444 si_llvm_dispose(&ctx);
6445 return -1;
6446 }
6447
6448 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6449 LLVMValueRef parts[2];
6450 bool need_prolog = sel->vs_needs_prolog;
6451
6452 parts[1] = ctx.main_fn;
6453
6454 if (need_prolog) {
6455 union si_shader_part_key prolog_key;
6456 si_get_vs_prolog_key(&sel->info,
6457 shader->info.num_input_sgprs,
6458 &shader->key.part.vs.prolog,
6459 shader, &prolog_key);
6460 si_build_vs_prolog_function(&ctx, &prolog_key);
6461 parts[0] = ctx.main_fn;
6462 }
6463
6464 si_build_wrapper_function(&ctx, parts + !need_prolog,
6465 1 + need_prolog, need_prolog, 0);
6466 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6467 if (sscreen->b.chip_class >= GFX9) {
6468 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6469 LLVMValueRef parts[4];
6470 bool vs_needs_prolog =
6471 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6472
6473 /* TCS main part */
6474 parts[2] = ctx.main_fn;
6475
6476 /* TCS epilog */
6477 union si_shader_part_key tcs_epilog_key;
6478 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6479 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6480 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6481 parts[3] = ctx.main_fn;
6482
6483 /* VS prolog */
6484 if (vs_needs_prolog) {
6485 union si_shader_part_key vs_prolog_key;
6486 si_get_vs_prolog_key(&ls->info,
6487 shader->info.num_input_sgprs,
6488 &shader->key.part.tcs.ls_prolog,
6489 shader, &vs_prolog_key);
6490 vs_prolog_key.vs_prolog.is_monolithic = true;
6491 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6492 parts[0] = ctx.main_fn;
6493 }
6494
6495 /* VS as LS main part */
6496 struct si_shader shader_ls = {};
6497 shader_ls.selector = ls;
6498 shader_ls.key.as_ls = 1;
6499 shader_ls.key.mono = shader->key.mono;
6500 shader_ls.key.opt = shader->key.opt;
6501 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6502
6503 if (!si_compile_tgsi_main(&ctx, true)) {
6504 si_llvm_dispose(&ctx);
6505 return -1;
6506 }
6507 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6508 parts[1] = ctx.main_fn;
6509
6510 /* Reset the shader context. */
6511 ctx.shader = shader;
6512 ctx.type = PIPE_SHADER_TESS_CTRL;
6513
6514 si_build_wrapper_function(&ctx,
6515 parts + !vs_needs_prolog,
6516 4 - !vs_needs_prolog, 0,
6517 vs_needs_prolog ? 2 : 1);
6518 } else {
6519 LLVMValueRef parts[2];
6520 union si_shader_part_key epilog_key;
6521
6522 parts[0] = ctx.main_fn;
6523
6524 memset(&epilog_key, 0, sizeof(epilog_key));
6525 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6526 si_build_tcs_epilog_function(&ctx, &epilog_key);
6527 parts[1] = ctx.main_fn;
6528
6529 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6530 }
6531 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6532 if (ctx.screen->b.chip_class >= GFX9) {
6533 struct si_shader_selector *es = shader->key.part.gs.es;
6534 LLVMValueRef es_prolog = NULL;
6535 LLVMValueRef es_main = NULL;
6536 LLVMValueRef gs_prolog = NULL;
6537 LLVMValueRef gs_main = ctx.main_fn;
6538
6539 /* GS prolog */
6540 union si_shader_part_key gs_prolog_key;
6541 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6542 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6543 gs_prolog_key.gs_prolog.is_monolithic = true;
6544 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6545 gs_prolog = ctx.main_fn;
6546
6547 /* ES prolog */
6548 if (es->vs_needs_prolog) {
6549 union si_shader_part_key vs_prolog_key;
6550 si_get_vs_prolog_key(&es->info,
6551 shader->info.num_input_sgprs,
6552 &shader->key.part.gs.vs_prolog,
6553 shader, &vs_prolog_key);
6554 vs_prolog_key.vs_prolog.is_monolithic = true;
6555 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6556 es_prolog = ctx.main_fn;
6557 }
6558
6559 /* ES main part */
6560 struct si_shader shader_es = {};
6561 shader_es.selector = es;
6562 shader_es.key.as_es = 1;
6563 shader_es.key.mono = shader->key.mono;
6564 shader_es.key.opt = shader->key.opt;
6565 si_llvm_context_set_tgsi(&ctx, &shader_es);
6566
6567 if (!si_compile_tgsi_main(&ctx, true)) {
6568 si_llvm_dispose(&ctx);
6569 return -1;
6570 }
6571 shader->info.uses_instanceid |= es->info.uses_instanceid;
6572 es_main = ctx.main_fn;
6573
6574 /* Reset the shader context. */
6575 ctx.shader = shader;
6576 ctx.type = PIPE_SHADER_GEOMETRY;
6577
6578 /* Prepare the array of shader parts. */
6579 LLVMValueRef parts[4];
6580 unsigned num_parts = 0, main_part, next_first_part;
6581
6582 if (es_prolog)
6583 parts[num_parts++] = es_prolog;
6584
6585 parts[main_part = num_parts++] = es_main;
6586 parts[next_first_part = num_parts++] = gs_prolog;
6587 parts[num_parts++] = gs_main;
6588
6589 si_build_wrapper_function(&ctx, parts, num_parts,
6590 main_part, next_first_part);
6591 } else {
6592 LLVMValueRef parts[2];
6593 union si_shader_part_key prolog_key;
6594
6595 parts[1] = ctx.main_fn;
6596
6597 memset(&prolog_key, 0, sizeof(prolog_key));
6598 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6599 si_build_gs_prolog_function(&ctx, &prolog_key);
6600 parts[0] = ctx.main_fn;
6601
6602 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6603 }
6604 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6605 LLVMValueRef parts[3];
6606 union si_shader_part_key prolog_key;
6607 union si_shader_part_key epilog_key;
6608 bool need_prolog;
6609
6610 si_get_ps_prolog_key(shader, &prolog_key, false);
6611 need_prolog = si_need_ps_prolog(&prolog_key);
6612
6613 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6614
6615 if (need_prolog) {
6616 si_build_ps_prolog_function(&ctx, &prolog_key);
6617 parts[0] = ctx.main_fn;
6618 }
6619
6620 si_get_ps_epilog_key(shader, &epilog_key);
6621 si_build_ps_epilog_function(&ctx, &epilog_key);
6622 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6623
6624 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6625 need_prolog ? 1 : 0, 0);
6626 }
6627
6628 si_llvm_optimize_module(&ctx);
6629
6630 /* Post-optimization transformations and analysis. */
6631 si_optimize_vs_outputs(&ctx);
6632
6633 if ((debug && debug->debug_message) ||
6634 si_can_dump_shader(&sscreen->b, ctx.type))
6635 si_count_scratch_private_memory(&ctx);
6636
6637 /* Compile to bytecode. */
6638 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6639 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6640 si_llvm_dispose(&ctx);
6641 if (r) {
6642 fprintf(stderr, "LLVM failed to compile shader\n");
6643 return r;
6644 }
6645
6646 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6647 * LLVM 3.9svn has this bug.
6648 */
6649 if (sel->type == PIPE_SHADER_COMPUTE) {
6650 unsigned wave_size = 64;
6651 unsigned max_vgprs = 256;
6652 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6653 unsigned max_sgprs_per_wave = 128;
6654 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6655 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6656 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6657
6658 max_vgprs = max_vgprs / min_waves_per_simd;
6659 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6660
6661 if (shader->config.num_sgprs > max_sgprs ||
6662 shader->config.num_vgprs > max_vgprs) {
6663 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6664 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6665 shader->config.num_sgprs, shader->config.num_vgprs,
6666 max_sgprs, max_vgprs);
6667
6668 /* Just terminate the process, because dependent
6669 * shaders can hang due to bad input data, but use
6670 * the env var to allow shader-db to work.
6671 */
6672 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6673 abort();
6674 }
6675 }
6676
6677 /* Add the scratch offset to input SGPRs. */
6678 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6679 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6680
6681 /* Calculate the number of fragment input VGPRs. */
6682 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6683 shader->info.num_input_vgprs = 0;
6684 shader->info.face_vgpr_index = -1;
6685 shader->info.ancillary_vgpr_index = -1;
6686
6687 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6688 shader->info.num_input_vgprs += 2;
6689 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6690 shader->info.num_input_vgprs += 2;
6691 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6692 shader->info.num_input_vgprs += 2;
6693 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6694 shader->info.num_input_vgprs += 3;
6695 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6696 shader->info.num_input_vgprs += 2;
6697 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6698 shader->info.num_input_vgprs += 2;
6699 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6700 shader->info.num_input_vgprs += 2;
6701 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6702 shader->info.num_input_vgprs += 1;
6703 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6704 shader->info.num_input_vgprs += 1;
6705 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6706 shader->info.num_input_vgprs += 1;
6707 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6708 shader->info.num_input_vgprs += 1;
6709 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6710 shader->info.num_input_vgprs += 1;
6711 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6712 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6713 shader->info.num_input_vgprs += 1;
6714 }
6715 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6716 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6717 shader->info.num_input_vgprs += 1;
6718 }
6719 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6720 shader->info.num_input_vgprs += 1;
6721 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6722 shader->info.num_input_vgprs += 1;
6723 }
6724
6725 return 0;
6726 }
6727
6728 /**
6729 * Create, compile and return a shader part (prolog or epilog).
6730 *
6731 * \param sscreen screen
6732 * \param list list of shader parts of the same category
6733 * \param type shader type
6734 * \param key shader part key
6735 * \param prolog whether the part being requested is a prolog
6736 * \param tm LLVM target machine
6737 * \param debug debug callback
6738 * \param build the callback responsible for building the main function
6739 * \return non-NULL on success
6740 */
6741 static struct si_shader_part *
6742 si_get_shader_part(struct si_screen *sscreen,
6743 struct si_shader_part **list,
6744 enum pipe_shader_type type,
6745 bool prolog,
6746 union si_shader_part_key *key,
6747 LLVMTargetMachineRef tm,
6748 struct pipe_debug_callback *debug,
6749 void (*build)(struct si_shader_context *,
6750 union si_shader_part_key *),
6751 const char *name)
6752 {
6753 struct si_shader_part *result;
6754
6755 mtx_lock(&sscreen->shader_parts_mutex);
6756
6757 /* Find existing. */
6758 for (result = *list; result; result = result->next) {
6759 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6760 mtx_unlock(&sscreen->shader_parts_mutex);
6761 return result;
6762 }
6763 }
6764
6765 /* Compile a new one. */
6766 result = CALLOC_STRUCT(si_shader_part);
6767 result->key = *key;
6768
6769 struct si_shader shader = {};
6770 struct si_shader_context ctx;
6771
6772 si_init_shader_ctx(&ctx, sscreen, tm);
6773 ctx.shader = &shader;
6774 ctx.type = type;
6775
6776 switch (type) {
6777 case PIPE_SHADER_VERTEX:
6778 shader.key.as_ls = key->vs_prolog.as_ls;
6779 shader.key.as_es = key->vs_prolog.as_es;
6780 break;
6781 case PIPE_SHADER_TESS_CTRL:
6782 assert(!prolog);
6783 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6784 break;
6785 case PIPE_SHADER_GEOMETRY:
6786 assert(prolog);
6787 break;
6788 case PIPE_SHADER_FRAGMENT:
6789 if (prolog)
6790 shader.key.part.ps.prolog = key->ps_prolog.states;
6791 else
6792 shader.key.part.ps.epilog = key->ps_epilog.states;
6793 break;
6794 default:
6795 unreachable("bad shader part");
6796 }
6797
6798 build(&ctx, key);
6799
6800 /* Compile. */
6801 si_llvm_optimize_module(&ctx);
6802
6803 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6804 ctx.ac.module, debug, ctx.type, name)) {
6805 FREE(result);
6806 result = NULL;
6807 goto out;
6808 }
6809
6810 result->next = *list;
6811 *list = result;
6812
6813 out:
6814 si_llvm_dispose(&ctx);
6815 mtx_unlock(&sscreen->shader_parts_mutex);
6816 return result;
6817 }
6818
6819 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6820 {
6821 LLVMValueRef ptr[2], list;
6822 bool is_merged_shader =
6823 ctx->screen->b.chip_class >= GFX9 &&
6824 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6825 ctx->type == PIPE_SHADER_GEOMETRY ||
6826 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6827
6828 /* Get the pointer to rw buffers. */
6829 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6830 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6831 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6832 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6833 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6834 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6835 return list;
6836 }
6837
6838 /**
6839 * Build the vertex shader prolog function.
6840 *
6841 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6842 * All inputs are returned unmodified. The vertex load indices are
6843 * stored after them, which will be used by the API VS for fetching inputs.
6844 *
6845 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6846 * input_v0,
6847 * input_v1,
6848 * input_v2,
6849 * input_v3,
6850 * (VertexID + BaseVertex),
6851 * (InstanceID + StartInstance),
6852 * (InstanceID / 2 + StartInstance)
6853 */
6854 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6855 union si_shader_part_key *key)
6856 {
6857 struct si_function_info fninfo;
6858 LLVMTypeRef *returns;
6859 LLVMValueRef ret, func;
6860 int num_returns, i;
6861 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6862 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6863 LLVMValueRef input_vgprs[9];
6864 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6865 num_input_vgprs;
6866 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6867
6868 si_init_function_info(&fninfo);
6869
6870 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6871 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6872 sizeof(LLVMTypeRef));
6873 num_returns = 0;
6874
6875 /* Declare input and output SGPRs. */
6876 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6877 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6878 returns[num_returns++] = ctx->i32;
6879 }
6880
6881 /* Preloaded VGPRs (outputs must be floats) */
6882 for (i = 0; i < num_input_vgprs; i++) {
6883 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6884 returns[num_returns++] = ctx->f32;
6885 }
6886
6887 /* Vertex load indices. */
6888 for (i = 0; i <= key->vs_prolog.last_input; i++)
6889 returns[num_returns++] = ctx->f32;
6890
6891 /* Create the function. */
6892 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6893 func = ctx->main_fn;
6894
6895 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6896 if (!key->vs_prolog.is_monolithic)
6897 si_init_exec_from_input(ctx, 3, 0);
6898
6899 if (key->vs_prolog.as_ls &&
6900 ctx->screen->has_ls_vgpr_init_bug) {
6901 /* If there are no HS threads, SPI loads the LS VGPRs
6902 * starting at VGPR 0. Shift them back to where they
6903 * belong.
6904 */
6905 LLVMValueRef has_hs_threads =
6906 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6907 unpack_param(ctx, 3, 8, 8),
6908 ctx->i32_0, "");
6909
6910 for (i = 4; i > 0; --i) {
6911 input_vgprs[i + 1] =
6912 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6913 input_vgprs[i + 1],
6914 input_vgprs[i - 1], "");
6915 }
6916 }
6917 }
6918
6919 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6920 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6921
6922 /* Copy inputs to outputs. This should be no-op, as the registers match,
6923 * but it will prevent the compiler from overwriting them unintentionally.
6924 */
6925 ret = ctx->return_value;
6926 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6927 LLVMValueRef p = LLVMGetParam(func, i);
6928 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6929 }
6930 for (i = 0; i < num_input_vgprs; i++) {
6931 LLVMValueRef p = input_vgprs[i];
6932 p = ac_to_float(&ctx->ac, p);
6933 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6934 key->vs_prolog.num_input_sgprs + i, "");
6935 }
6936
6937 /* Compute vertex load indices from instance divisors. */
6938 LLVMValueRef instance_divisor_constbuf = NULL;
6939
6940 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6941 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6942 LLVMValueRef buf_index =
6943 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6944 instance_divisor_constbuf =
6945 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6946 }
6947
6948 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6949 bool divisor_is_one =
6950 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6951 bool divisor_is_fetched =
6952 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6953 LLVMValueRef index;
6954
6955 if (divisor_is_one || divisor_is_fetched) {
6956 LLVMValueRef divisor = ctx->i32_1;
6957
6958 if (divisor_is_fetched) {
6959 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6960 LLVMConstInt(ctx->i32, i * 4, 0));
6961 divisor = ac_to_integer(&ctx->ac, divisor);
6962 }
6963
6964 /* InstanceID / Divisor + StartInstance */
6965 index = get_instance_index_for_fetch(ctx,
6966 user_sgpr_base +
6967 SI_SGPR_START_INSTANCE,
6968 divisor);
6969 } else {
6970 /* VertexID + BaseVertex */
6971 index = LLVMBuildAdd(ctx->ac.builder,
6972 ctx->abi.vertex_id,
6973 LLVMGetParam(func, user_sgpr_base +
6974 SI_SGPR_BASE_VERTEX), "");
6975 }
6976
6977 index = ac_to_float(&ctx->ac, index);
6978 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6979 fninfo.num_params + i, "");
6980 }
6981
6982 si_llvm_build_ret(ctx, ret);
6983 }
6984
6985 static bool si_get_vs_prolog(struct si_screen *sscreen,
6986 LLVMTargetMachineRef tm,
6987 struct si_shader *shader,
6988 struct pipe_debug_callback *debug,
6989 struct si_shader *main_part,
6990 const struct si_vs_prolog_bits *key)
6991 {
6992 struct si_shader_selector *vs = main_part->selector;
6993
6994 if (!si_vs_needs_prolog(vs, key))
6995 return true;
6996
6997 /* Get the prolog. */
6998 union si_shader_part_key prolog_key;
6999 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7000 key, shader, &prolog_key);
7001
7002 shader->prolog =
7003 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7004 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7005 debug, si_build_vs_prolog_function,
7006 "Vertex Shader Prolog");
7007 return shader->prolog != NULL;
7008 }
7009
7010 /**
7011 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7012 */
7013 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7014 LLVMTargetMachineRef tm,
7015 struct si_shader *shader,
7016 struct pipe_debug_callback *debug)
7017 {
7018 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7019 &shader->key.part.vs.prolog);
7020 }
7021
7022 /**
7023 * Compile the TCS epilog function. This writes tesselation factors to memory
7024 * based on the output primitive type of the tesselator (determined by TES).
7025 */
7026 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7027 union si_shader_part_key *key)
7028 {
7029 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7030 struct si_function_info fninfo;
7031 LLVMValueRef func;
7032
7033 si_init_function_info(&fninfo);
7034
7035 if (ctx->screen->b.chip_class >= GFX9) {
7036 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7037 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7038 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7039 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7040 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7041 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7042 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7043 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7044 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7045 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7046 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7047 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7048 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7049 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7050 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7051 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7052 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7053 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7054 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7055 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7056 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7057 } else {
7058 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7059 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7060 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7061 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7062 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7063 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7064 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7065 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7066 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7067 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7068 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7069 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7070 }
7071
7072 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7073 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7074 unsigned tess_factors_idx =
7075 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7076 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7077 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7078
7079 for (unsigned i = 0; i < 6; i++)
7080 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7081
7082 /* Create the function. */
7083 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7084 ctx->screen->b.chip_class >= CIK ? 128 : 64);
7085 ac_declare_lds_as_pointer(&ctx->ac);
7086 func = ctx->main_fn;
7087
7088 LLVMValueRef invoc0_tess_factors[6];
7089 for (unsigned i = 0; i < 6; i++)
7090 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7091
7092 si_write_tess_factors(bld_base,
7093 LLVMGetParam(func, tess_factors_idx),
7094 LLVMGetParam(func, tess_factors_idx + 1),
7095 LLVMGetParam(func, tess_factors_idx + 2),
7096 invoc0_tess_factors, invoc0_tess_factors + 4);
7097
7098 LLVMBuildRetVoid(ctx->ac.builder);
7099 }
7100
7101 /**
7102 * Select and compile (or reuse) TCS parts (epilog).
7103 */
7104 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7105 LLVMTargetMachineRef tm,
7106 struct si_shader *shader,
7107 struct pipe_debug_callback *debug)
7108 {
7109 if (sscreen->b.chip_class >= GFX9) {
7110 struct si_shader *ls_main_part =
7111 shader->key.part.tcs.ls->main_shader_part_ls;
7112
7113 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7114 &shader->key.part.tcs.ls_prolog))
7115 return false;
7116
7117 shader->previous_stage = ls_main_part;
7118 }
7119
7120 /* Get the epilog. */
7121 union si_shader_part_key epilog_key;
7122 memset(&epilog_key, 0, sizeof(epilog_key));
7123 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7124
7125 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7126 PIPE_SHADER_TESS_CTRL, false,
7127 &epilog_key, tm, debug,
7128 si_build_tcs_epilog_function,
7129 "Tessellation Control Shader Epilog");
7130 return shader->epilog != NULL;
7131 }
7132
7133 /**
7134 * Select and compile (or reuse) GS parts (prolog).
7135 */
7136 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7137 LLVMTargetMachineRef tm,
7138 struct si_shader *shader,
7139 struct pipe_debug_callback *debug)
7140 {
7141 if (sscreen->b.chip_class >= GFX9) {
7142 struct si_shader *es_main_part =
7143 shader->key.part.gs.es->main_shader_part_es;
7144
7145 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7146 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7147 &shader->key.part.gs.vs_prolog))
7148 return false;
7149
7150 shader->previous_stage = es_main_part;
7151 }
7152
7153 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7154 return true;
7155
7156 union si_shader_part_key prolog_key;
7157 memset(&prolog_key, 0, sizeof(prolog_key));
7158 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7159
7160 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7161 PIPE_SHADER_GEOMETRY, true,
7162 &prolog_key, tm, debug,
7163 si_build_gs_prolog_function,
7164 "Geometry Shader Prolog");
7165 return shader->prolog2 != NULL;
7166 }
7167
7168 /**
7169 * Build the pixel shader prolog function. This handles:
7170 * - two-side color selection and interpolation
7171 * - overriding interpolation parameters for the API PS
7172 * - polygon stippling
7173 *
7174 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7175 * overriden by other states. (e.g. per-sample interpolation)
7176 * Interpolated colors are stored after the preloaded VGPRs.
7177 */
7178 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7179 union si_shader_part_key *key)
7180 {
7181 struct si_function_info fninfo;
7182 LLVMValueRef ret, func;
7183 int num_returns, i, num_color_channels;
7184
7185 assert(si_need_ps_prolog(key));
7186
7187 si_init_function_info(&fninfo);
7188
7189 /* Declare inputs. */
7190 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7191 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7192
7193 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7194 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7195
7196 /* Declare outputs (same as inputs + add colors if needed) */
7197 num_returns = fninfo.num_params;
7198 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7199 for (i = 0; i < num_color_channels; i++)
7200 fninfo.types[num_returns++] = ctx->f32;
7201
7202 /* Create the function. */
7203 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7204 &fninfo, 0);
7205 func = ctx->main_fn;
7206
7207 /* Copy inputs to outputs. This should be no-op, as the registers match,
7208 * but it will prevent the compiler from overwriting them unintentionally.
7209 */
7210 ret = ctx->return_value;
7211 for (i = 0; i < fninfo.num_params; i++) {
7212 LLVMValueRef p = LLVMGetParam(func, i);
7213 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7214 }
7215
7216 /* Polygon stippling. */
7217 if (key->ps_prolog.states.poly_stipple) {
7218 /* POS_FIXED_PT is always last. */
7219 unsigned pos = key->ps_prolog.num_input_sgprs +
7220 key->ps_prolog.num_input_vgprs - 1;
7221 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7222
7223 si_llvm_emit_polygon_stipple(ctx, list, pos);
7224 }
7225
7226 if (key->ps_prolog.states.bc_optimize_for_persp ||
7227 key->ps_prolog.states.bc_optimize_for_linear) {
7228 unsigned i, base = key->ps_prolog.num_input_sgprs;
7229 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7230
7231 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7232 * The hw doesn't compute CENTROID if the whole wave only
7233 * contains fully-covered quads.
7234 *
7235 * PRIM_MASK is after user SGPRs.
7236 */
7237 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7238 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7239 LLVMConstInt(ctx->i32, 31, 0), "");
7240 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7241 ctx->i1, "");
7242
7243 if (key->ps_prolog.states.bc_optimize_for_persp) {
7244 /* Read PERSP_CENTER. */
7245 for (i = 0; i < 2; i++)
7246 center[i] = LLVMGetParam(func, base + 2 + i);
7247 /* Read PERSP_CENTROID. */
7248 for (i = 0; i < 2; i++)
7249 centroid[i] = LLVMGetParam(func, base + 4 + i);
7250 /* Select PERSP_CENTROID. */
7251 for (i = 0; i < 2; i++) {
7252 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7253 center[i], centroid[i], "");
7254 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7255 tmp, base + 4 + i, "");
7256 }
7257 }
7258 if (key->ps_prolog.states.bc_optimize_for_linear) {
7259 /* Read LINEAR_CENTER. */
7260 for (i = 0; i < 2; i++)
7261 center[i] = LLVMGetParam(func, base + 8 + i);
7262 /* Read LINEAR_CENTROID. */
7263 for (i = 0; i < 2; i++)
7264 centroid[i] = LLVMGetParam(func, base + 10 + i);
7265 /* Select LINEAR_CENTROID. */
7266 for (i = 0; i < 2; i++) {
7267 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7268 center[i], centroid[i], "");
7269 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7270 tmp, base + 10 + i, "");
7271 }
7272 }
7273 }
7274
7275 /* Force per-sample interpolation. */
7276 if (key->ps_prolog.states.force_persp_sample_interp) {
7277 unsigned i, base = key->ps_prolog.num_input_sgprs;
7278 LLVMValueRef persp_sample[2];
7279
7280 /* Read PERSP_SAMPLE. */
7281 for (i = 0; i < 2; i++)
7282 persp_sample[i] = LLVMGetParam(func, base + i);
7283 /* Overwrite PERSP_CENTER. */
7284 for (i = 0; i < 2; i++)
7285 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7286 persp_sample[i], base + 2 + i, "");
7287 /* Overwrite PERSP_CENTROID. */
7288 for (i = 0; i < 2; i++)
7289 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7290 persp_sample[i], base + 4 + i, "");
7291 }
7292 if (key->ps_prolog.states.force_linear_sample_interp) {
7293 unsigned i, base = key->ps_prolog.num_input_sgprs;
7294 LLVMValueRef linear_sample[2];
7295
7296 /* Read LINEAR_SAMPLE. */
7297 for (i = 0; i < 2; i++)
7298 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7299 /* Overwrite LINEAR_CENTER. */
7300 for (i = 0; i < 2; i++)
7301 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7302 linear_sample[i], base + 8 + i, "");
7303 /* Overwrite LINEAR_CENTROID. */
7304 for (i = 0; i < 2; i++)
7305 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7306 linear_sample[i], base + 10 + i, "");
7307 }
7308
7309 /* Force center interpolation. */
7310 if (key->ps_prolog.states.force_persp_center_interp) {
7311 unsigned i, base = key->ps_prolog.num_input_sgprs;
7312 LLVMValueRef persp_center[2];
7313
7314 /* Read PERSP_CENTER. */
7315 for (i = 0; i < 2; i++)
7316 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7317 /* Overwrite PERSP_SAMPLE. */
7318 for (i = 0; i < 2; i++)
7319 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7320 persp_center[i], base + i, "");
7321 /* Overwrite PERSP_CENTROID. */
7322 for (i = 0; i < 2; i++)
7323 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7324 persp_center[i], base + 4 + i, "");
7325 }
7326 if (key->ps_prolog.states.force_linear_center_interp) {
7327 unsigned i, base = key->ps_prolog.num_input_sgprs;
7328 LLVMValueRef linear_center[2];
7329
7330 /* Read LINEAR_CENTER. */
7331 for (i = 0; i < 2; i++)
7332 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7333 /* Overwrite LINEAR_SAMPLE. */
7334 for (i = 0; i < 2; i++)
7335 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7336 linear_center[i], base + 6 + i, "");
7337 /* Overwrite LINEAR_CENTROID. */
7338 for (i = 0; i < 2; i++)
7339 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7340 linear_center[i], base + 10 + i, "");
7341 }
7342
7343 /* Interpolate colors. */
7344 unsigned color_out_idx = 0;
7345 for (i = 0; i < 2; i++) {
7346 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7347 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7348 key->ps_prolog.face_vgpr_index;
7349 LLVMValueRef interp[2], color[4];
7350 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7351
7352 if (!writemask)
7353 continue;
7354
7355 /* If the interpolation qualifier is not CONSTANT (-1). */
7356 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7357 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7358 key->ps_prolog.color_interp_vgpr_index[i];
7359
7360 /* Get the (i,j) updated by bc_optimize handling. */
7361 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7362 interp_vgpr, "");
7363 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7364 interp_vgpr + 1, "");
7365 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7366 }
7367
7368 /* Use the absolute location of the input. */
7369 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7370
7371 if (key->ps_prolog.states.color_two_side) {
7372 face = LLVMGetParam(func, face_vgpr);
7373 face = ac_to_integer(&ctx->ac, face);
7374 }
7375
7376 interp_fs_input(ctx,
7377 key->ps_prolog.color_attr_index[i],
7378 TGSI_SEMANTIC_COLOR, i,
7379 key->ps_prolog.num_interp_inputs,
7380 key->ps_prolog.colors_read, interp_ij,
7381 prim_mask, face, color);
7382
7383 while (writemask) {
7384 unsigned chan = u_bit_scan(&writemask);
7385 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7386 fninfo.num_params + color_out_idx++, "");
7387 }
7388 }
7389
7390 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7391 * says:
7392 *
7393 * "When per-sample shading is active due to the use of a fragment
7394 * input qualified by sample or due to the use of the gl_SampleID
7395 * or gl_SamplePosition variables, only the bit for the current
7396 * sample is set in gl_SampleMaskIn. When state specifies multiple
7397 * fragment shader invocations for a given fragment, the sample
7398 * mask for any single fragment shader invocation may specify a
7399 * subset of the covered samples for the fragment. In this case,
7400 * the bit corresponding to each covered sample will be set in
7401 * exactly one fragment shader invocation."
7402 *
7403 * The samplemask loaded by hardware is always the coverage of the
7404 * entire pixel/fragment, so mask bits out based on the sample ID.
7405 */
7406 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7407 /* The bit pattern matches that used by fixed function fragment
7408 * processing. */
7409 static const uint16_t ps_iter_masks[] = {
7410 0xffff, /* not used */
7411 0x5555,
7412 0x1111,
7413 0x0101,
7414 0x0001,
7415 };
7416 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7417
7418 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7419 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7420 key->ps_prolog.ancillary_vgpr_index;
7421 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7422 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7423
7424 samplemask = ac_to_integer(&ctx->ac, samplemask);
7425 samplemask = LLVMBuildAnd(
7426 ctx->ac.builder,
7427 samplemask,
7428 LLVMBuildShl(ctx->ac.builder,
7429 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7430 sampleid, ""),
7431 "");
7432 samplemask = ac_to_float(&ctx->ac, samplemask);
7433
7434 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7435 ancillary_vgpr + 1, "");
7436 }
7437
7438 /* Tell LLVM to insert WQM instruction sequence when needed. */
7439 if (key->ps_prolog.wqm) {
7440 LLVMAddTargetDependentFunctionAttr(func,
7441 "amdgpu-ps-wqm-outputs", "");
7442 }
7443
7444 si_llvm_build_ret(ctx, ret);
7445 }
7446
7447 /**
7448 * Build the pixel shader epilog function. This handles everything that must be
7449 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7450 */
7451 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7452 union si_shader_part_key *key)
7453 {
7454 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7455 struct si_function_info fninfo;
7456 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7457 int i;
7458 struct si_ps_exports exp = {};
7459
7460 si_init_function_info(&fninfo);
7461
7462 /* Declare input SGPRs. */
7463 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7464 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7465 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7466 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7467 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7468
7469 /* Declare input VGPRs. */
7470 unsigned required_num_params =
7471 fninfo.num_sgpr_params +
7472 util_bitcount(key->ps_epilog.colors_written) * 4 +
7473 key->ps_epilog.writes_z +
7474 key->ps_epilog.writes_stencil +
7475 key->ps_epilog.writes_samplemask;
7476
7477 required_num_params = MAX2(required_num_params,
7478 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7479
7480 while (fninfo.num_params < required_num_params)
7481 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7482
7483 /* Create the function. */
7484 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7485 /* Disable elimination of unused inputs. */
7486 si_llvm_add_attribute(ctx->main_fn,
7487 "InitialPSInputAddr", 0xffffff);
7488
7489 /* Process colors. */
7490 unsigned vgpr = fninfo.num_sgpr_params;
7491 unsigned colors_written = key->ps_epilog.colors_written;
7492 int last_color_export = -1;
7493
7494 /* Find the last color export. */
7495 if (!key->ps_epilog.writes_z &&
7496 !key->ps_epilog.writes_stencil &&
7497 !key->ps_epilog.writes_samplemask) {
7498 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7499
7500 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7501 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7502 /* Just set this if any of the colorbuffers are enabled. */
7503 if (spi_format &
7504 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7505 last_color_export = 0;
7506 } else {
7507 for (i = 0; i < 8; i++)
7508 if (colors_written & (1 << i) &&
7509 (spi_format >> (i * 4)) & 0xf)
7510 last_color_export = i;
7511 }
7512 }
7513
7514 while (colors_written) {
7515 LLVMValueRef color[4];
7516 int mrt = u_bit_scan(&colors_written);
7517
7518 for (i = 0; i < 4; i++)
7519 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7520
7521 si_export_mrt_color(bld_base, color, mrt,
7522 fninfo.num_params - 1,
7523 mrt == last_color_export, &exp);
7524 }
7525
7526 /* Process depth, stencil, samplemask. */
7527 if (key->ps_epilog.writes_z)
7528 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7529 if (key->ps_epilog.writes_stencil)
7530 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7531 if (key->ps_epilog.writes_samplemask)
7532 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7533
7534 if (depth || stencil || samplemask)
7535 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7536 else if (last_color_export == -1)
7537 si_export_null(bld_base);
7538
7539 if (exp.num)
7540 si_emit_ps_exports(ctx, &exp);
7541
7542 /* Compile. */
7543 LLVMBuildRetVoid(ctx->ac.builder);
7544 }
7545
7546 /**
7547 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7548 */
7549 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7550 LLVMTargetMachineRef tm,
7551 struct si_shader *shader,
7552 struct pipe_debug_callback *debug)
7553 {
7554 union si_shader_part_key prolog_key;
7555 union si_shader_part_key epilog_key;
7556
7557 /* Get the prolog. */
7558 si_get_ps_prolog_key(shader, &prolog_key, true);
7559
7560 /* The prolog is a no-op if these aren't set. */
7561 if (si_need_ps_prolog(&prolog_key)) {
7562 shader->prolog =
7563 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7564 PIPE_SHADER_FRAGMENT, true,
7565 &prolog_key, tm, debug,
7566 si_build_ps_prolog_function,
7567 "Fragment Shader Prolog");
7568 if (!shader->prolog)
7569 return false;
7570 }
7571
7572 /* Get the epilog. */
7573 si_get_ps_epilog_key(shader, &epilog_key);
7574
7575 shader->epilog =
7576 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7577 PIPE_SHADER_FRAGMENT, false,
7578 &epilog_key, tm, debug,
7579 si_build_ps_epilog_function,
7580 "Fragment Shader Epilog");
7581 if (!shader->epilog)
7582 return false;
7583
7584 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7585 if (shader->key.part.ps.prolog.poly_stipple) {
7586 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7587 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7588 }
7589
7590 /* Set up the enable bits for per-sample shading if needed. */
7591 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7592 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7593 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7594 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7595 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7596 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7597 }
7598 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7599 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7600 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7601 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7602 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7603 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7604 }
7605 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7606 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7607 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7608 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7609 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7610 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7611 }
7612 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7613 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7614 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7615 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7616 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7617 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7618 }
7619
7620 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7621 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7622 !(shader->config.spi_ps_input_ena & 0xf)) {
7623 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7624 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7625 }
7626
7627 /* At least one pair of interpolation weights must be enabled. */
7628 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7629 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7630 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7631 }
7632
7633 /* Samplemask fixup requires the sample ID. */
7634 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7635 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7636 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7637 }
7638
7639 /* The sample mask input is always enabled, because the API shader always
7640 * passes it through to the epilog. Disable it here if it's unused.
7641 */
7642 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7643 !shader->selector->info.reads_samplemask)
7644 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7645
7646 return true;
7647 }
7648
7649 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7650 unsigned *lds_size)
7651 {
7652 /* SPI barrier management bug:
7653 * Make sure we have at least 4k of LDS in use to avoid the bug.
7654 * It applies to workgroup sizes of more than one wavefront.
7655 */
7656 if (sscreen->b.family == CHIP_BONAIRE ||
7657 sscreen->b.family == CHIP_KABINI ||
7658 sscreen->b.family == CHIP_MULLINS)
7659 *lds_size = MAX2(*lds_size, 8);
7660 }
7661
7662 static void si_fix_resource_usage(struct si_screen *sscreen,
7663 struct si_shader *shader)
7664 {
7665 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7666
7667 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7668
7669 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7670 si_get_max_workgroup_size(shader) > 64) {
7671 si_multiwave_lds_size_workaround(sscreen,
7672 &shader->config.lds_size);
7673 }
7674 }
7675
7676 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7677 struct si_shader *shader,
7678 struct pipe_debug_callback *debug)
7679 {
7680 struct si_shader_selector *sel = shader->selector;
7681 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7682 int r;
7683
7684 /* LS, ES, VS are compiled on demand if the main part hasn't been
7685 * compiled for that stage.
7686 *
7687 * Vertex shaders are compiled on demand when a vertex fetch
7688 * workaround must be applied.
7689 */
7690 if (shader->is_monolithic) {
7691 /* Monolithic shader (compiled as a whole, has many variants,
7692 * may take a long time to compile).
7693 */
7694 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7695 if (r)
7696 return r;
7697 } else {
7698 /* The shader consists of several parts:
7699 *
7700 * - the middle part is the user shader, it has 1 variant only
7701 * and it was compiled during the creation of the shader
7702 * selector
7703 * - the prolog part is inserted at the beginning
7704 * - the epilog part is inserted at the end
7705 *
7706 * The prolog and epilog have many (but simple) variants.
7707 *
7708 * Starting with gfx9, geometry and tessellation control
7709 * shaders also contain the prolog and user shader parts of
7710 * the previous shader stage.
7711 */
7712
7713 if (!mainp)
7714 return -1;
7715
7716 /* Copy the compiled TGSI shader data over. */
7717 shader->is_binary_shared = true;
7718 shader->binary = mainp->binary;
7719 shader->config = mainp->config;
7720 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7721 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7722 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7723 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7724 memcpy(shader->info.vs_output_param_offset,
7725 mainp->info.vs_output_param_offset,
7726 sizeof(mainp->info.vs_output_param_offset));
7727 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7728 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7729 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7730
7731 /* Select prologs and/or epilogs. */
7732 switch (sel->type) {
7733 case PIPE_SHADER_VERTEX:
7734 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7735 return -1;
7736 break;
7737 case PIPE_SHADER_TESS_CTRL:
7738 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7739 return -1;
7740 break;
7741 case PIPE_SHADER_TESS_EVAL:
7742 break;
7743 case PIPE_SHADER_GEOMETRY:
7744 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7745 return -1;
7746 break;
7747 case PIPE_SHADER_FRAGMENT:
7748 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7749 return -1;
7750
7751 /* Make sure we have at least as many VGPRs as there
7752 * are allocated inputs.
7753 */
7754 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7755 shader->info.num_input_vgprs);
7756 break;
7757 }
7758
7759 /* Update SGPR and VGPR counts. */
7760 if (shader->prolog) {
7761 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7762 shader->prolog->config.num_sgprs);
7763 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7764 shader->prolog->config.num_vgprs);
7765 }
7766 if (shader->previous_stage) {
7767 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7768 shader->previous_stage->config.num_sgprs);
7769 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7770 shader->previous_stage->config.num_vgprs);
7771 shader->config.spilled_sgprs =
7772 MAX2(shader->config.spilled_sgprs,
7773 shader->previous_stage->config.spilled_sgprs);
7774 shader->config.spilled_vgprs =
7775 MAX2(shader->config.spilled_vgprs,
7776 shader->previous_stage->config.spilled_vgprs);
7777 shader->config.private_mem_vgprs =
7778 MAX2(shader->config.private_mem_vgprs,
7779 shader->previous_stage->config.private_mem_vgprs);
7780 shader->config.scratch_bytes_per_wave =
7781 MAX2(shader->config.scratch_bytes_per_wave,
7782 shader->previous_stage->config.scratch_bytes_per_wave);
7783 shader->info.uses_instanceid |=
7784 shader->previous_stage->info.uses_instanceid;
7785 }
7786 if (shader->prolog2) {
7787 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7788 shader->prolog2->config.num_sgprs);
7789 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7790 shader->prolog2->config.num_vgprs);
7791 }
7792 if (shader->epilog) {
7793 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7794 shader->epilog->config.num_sgprs);
7795 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7796 shader->epilog->config.num_vgprs);
7797 }
7798 }
7799
7800 si_fix_resource_usage(sscreen, shader);
7801 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7802 stderr, true);
7803
7804 /* Upload. */
7805 r = si_shader_binary_upload(sscreen, shader);
7806 if (r) {
7807 fprintf(stderr, "LLVM failed to upload shader\n");
7808 return r;
7809 }
7810
7811 return 0;
7812 }
7813
7814 void si_shader_destroy(struct si_shader *shader)
7815 {
7816 if (shader->scratch_bo)
7817 r600_resource_reference(&shader->scratch_bo, NULL);
7818
7819 r600_resource_reference(&shader->bo, NULL);
7820
7821 if (!shader->is_binary_shared)
7822 si_radeon_shader_binary_clean(&shader->binary);
7823
7824 free(shader->shader_log);
7825 }