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radeonsi: fix LLVM 3.9 - don't use non-matching attributes on declarations
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 /**
102 * Returns a unique index for a semantic name and index. The index must be
103 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
104 * calculated.
105 */
106 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
107 {
108 switch (semantic_name) {
109 case TGSI_SEMANTIC_POSITION:
110 return 0;
111 case TGSI_SEMANTIC_PSIZE:
112 return 1;
113 case TGSI_SEMANTIC_CLIPDIST:
114 assert(index <= 1);
115 return 2 + index;
116 case TGSI_SEMANTIC_GENERIC:
117 if (index <= 63-4)
118 return 4 + index;
119
120 assert(!"invalid generic index");
121 return 0;
122
123 /* patch indices are completely separate and thus start from 0 */
124 case TGSI_SEMANTIC_TESSOUTER:
125 return 0;
126 case TGSI_SEMANTIC_TESSINNER:
127 return 1;
128 case TGSI_SEMANTIC_PATCH:
129 return 2 + index;
130
131 default:
132 assert(!"invalid semantic name");
133 return 0;
134 }
135 }
136
137 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
138 {
139 switch (name) {
140 case TGSI_SEMANTIC_FOG:
141 return 0;
142 case TGSI_SEMANTIC_LAYER:
143 return 1;
144 case TGSI_SEMANTIC_VIEWPORT_INDEX:
145 return 2;
146 case TGSI_SEMANTIC_PRIMID:
147 return 3;
148 case TGSI_SEMANTIC_COLOR: /* these alias */
149 case TGSI_SEMANTIC_BCOLOR:
150 return 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 return 6 + index;
153 default:
154 assert(!"invalid semantic name");
155 return 0;
156 }
157 }
158
159 /**
160 * Get the value of a shader input parameter and extract a bitfield.
161 */
162 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
163 unsigned param, unsigned rshift,
164 unsigned bitwidth)
165 {
166 struct gallivm_state *gallivm = &ctx->gallivm;
167 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
168 param);
169
170 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
171 value = bitcast(&ctx->bld_base,
172 TGSI_TYPE_UNSIGNED, value);
173
174 if (rshift)
175 value = LLVMBuildLShr(gallivm->builder, value,
176 lp_build_const_int32(gallivm, rshift), "");
177
178 if (rshift + bitwidth < 32) {
179 unsigned mask = (1 << bitwidth) - 1;
180 value = LLVMBuildAnd(gallivm->builder, value,
181 lp_build_const_int32(gallivm, mask), "");
182 }
183
184 return value;
185 }
186
187 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
188 {
189 switch (ctx->type) {
190 case PIPE_SHADER_TESS_CTRL:
191 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
192
193 case PIPE_SHADER_TESS_EVAL:
194 return LLVMGetParam(ctx->main_fn,
195 ctx->param_tes_rel_patch_id);
196
197 default:
198 assert(0);
199 return NULL;
200 }
201 }
202
203 /* Tessellation shaders pass outputs to the next shader using LDS.
204 *
205 * LS outputs = TCS inputs
206 * TCS outputs = TES inputs
207 *
208 * The LDS layout is:
209 * - TCS inputs for patch 0
210 * - TCS inputs for patch 1
211 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
212 * - ...
213 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
214 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
215 * - TCS outputs for patch 1
216 * - Per-patch TCS outputs for patch 1
217 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
218 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * - ...
220 *
221 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 */
223
224 static LLVMValueRef
225 get_tcs_in_patch_stride(struct si_shader_context *ctx)
226 {
227 if (ctx->type == PIPE_SHADER_VERTEX)
228 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
229 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
230 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
231 else {
232 assert(0);
233 return NULL;
234 }
235 }
236
237 static LLVMValueRef
238 get_tcs_out_patch_stride(struct si_shader_context *ctx)
239 {
240 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
245 {
246 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
247 unpack_param(ctx,
248 SI_PARAM_TCS_OUT_OFFSETS,
249 0, 16),
250 4);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
255 {
256 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
257 unpack_param(ctx,
258 SI_PARAM_TCS_OUT_OFFSETS,
259 16, 16),
260 4);
261 }
262
263 static LLVMValueRef
264 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
265 {
266 struct gallivm_state *gallivm = &ctx->gallivm;
267 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
268 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
269
270 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
271 }
272
273 static LLVMValueRef
274 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
275 {
276 struct gallivm_state *gallivm = &ctx->gallivm;
277 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(gallivm->builder, patch0_offset,
282 LLVMBuildMul(gallivm->builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef
288 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
289 {
290 struct gallivm_state *gallivm = &ctx->gallivm;
291 LLVMValueRef patch0_patch_data_offset =
292 get_tcs_out_patch0_patch_data_offset(ctx);
293 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
294 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
295
296 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
297 LLVMBuildMul(gallivm->builder, patch_stride,
298 rel_patch_id, ""),
299 "");
300 }
301
302 static LLVMValueRef get_instance_index_for_fetch(
303 struct si_shader_context *radeon_bld,
304 unsigned param_start_instance, unsigned divisor)
305 {
306 struct si_shader_context *ctx =
307 si_shader_context(&radeon_bld->bld_base);
308 struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
309
310 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 lp_build_const_int32(gallivm, divisor), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct lp_build_context *base = &ctx->bld_base.base;
344 struct gallivm_state *gallivm = base->gallivm;
345
346 unsigned chan;
347 unsigned fix_fetch;
348 unsigned num_fetches;
349 unsigned fetch_stride;
350
351 LLVMValueRef t_list_ptr;
352 LLVMValueRef t_offset;
353 LLVMValueRef t_list;
354 LLVMValueRef vertex_index;
355 LLVMValueRef input[3];
356
357 /* Load the T list */
358 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
359
360 t_offset = lp_build_const_int32(gallivm, input_index);
361
362 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
363
364 vertex_index = LLVMGetParam(ctx->main_fn,
365 ctx->param_vertex_index0 +
366 input_index);
367
368 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
369
370 /* Do multiple loads for special formats. */
371 switch (fix_fetch) {
372 case SI_FIX_FETCH_RGB_64_FLOAT:
373 num_fetches = 3; /* 3 2-dword loads */
374 fetch_stride = 8;
375 break;
376 case SI_FIX_FETCH_RGBA_64_FLOAT:
377 num_fetches = 2; /* 2 4-dword loads */
378 fetch_stride = 16;
379 break;
380 case SI_FIX_FETCH_RGB_8:
381 case SI_FIX_FETCH_RGB_8_INT:
382 num_fetches = 3;
383 fetch_stride = 1;
384 break;
385 case SI_FIX_FETCH_RGB_16:
386 case SI_FIX_FETCH_RGB_16_INT:
387 num_fetches = 3;
388 fetch_stride = 2;
389 break;
390 default:
391 num_fetches = 1;
392 fetch_stride = 0;
393 }
394
395 for (unsigned i = 0; i < num_fetches; i++) {
396 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
397
398 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
399 vertex_index, voffset,
400 true);
401 }
402
403 /* Break up the vec4 into individual components */
404 for (chan = 0; chan < 4; chan++) {
405 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
406 out[chan] = LLVMBuildExtractElement(gallivm->builder,
407 input[0], llvm_chan, "");
408 }
409
410 switch (fix_fetch) {
411 case SI_FIX_FETCH_A2_SNORM:
412 case SI_FIX_FETCH_A2_SSCALED:
413 case SI_FIX_FETCH_A2_SINT: {
414 /* The hardware returns an unsigned value; convert it to a
415 * signed one.
416 */
417 LLVMValueRef tmp = out[3];
418 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
419
420 /* First, recover the sign-extended signed integer value. */
421 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
422 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
423 else
424 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
425
426 /* For the integer-like cases, do a natural sign extension.
427 *
428 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
429 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
430 * exponent.
431 */
432 tmp = LLVMBuildShl(gallivm->builder, tmp,
433 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
434 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
435 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
436
437 /* Convert back to the right type. */
438 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
439 LLVMValueRef clamp;
440 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
441 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
442 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
443 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
444 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
445 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
446 }
447
448 out[3] = tmp;
449 break;
450 }
451 case SI_FIX_FETCH_RGBA_32_UNORM:
452 case SI_FIX_FETCH_RGBX_32_UNORM:
453 for (chan = 0; chan < 4; chan++) {
454 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
455 ctx->i32, "");
456 out[chan] = LLVMBuildUIToFP(gallivm->builder,
457 out[chan], ctx->f32, "");
458 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
459 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
460 }
461 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
462 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
463 out[3] = LLVMConstReal(ctx->f32, 1);
464 break;
465 case SI_FIX_FETCH_RGBA_32_SNORM:
466 case SI_FIX_FETCH_RGBX_32_SNORM:
467 case SI_FIX_FETCH_RGBA_32_FIXED:
468 case SI_FIX_FETCH_RGBX_32_FIXED: {
469 double scale;
470 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
471 scale = 1.0 / 0x10000;
472 else
473 scale = 1.0 / INT_MAX;
474
475 for (chan = 0; chan < 4; chan++) {
476 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
477 ctx->i32, "");
478 out[chan] = LLVMBuildSIToFP(gallivm->builder,
479 out[chan], ctx->f32, "");
480 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
481 LLVMConstReal(ctx->f32, scale), "");
482 }
483 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
484 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
485 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
486 out[3] = LLVMConstReal(ctx->f32, 1);
487 break;
488 }
489 case SI_FIX_FETCH_RGBA_32_USCALED:
490 for (chan = 0; chan < 4; chan++) {
491 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
492 ctx->i32, "");
493 out[chan] = LLVMBuildUIToFP(gallivm->builder,
494 out[chan], ctx->f32, "");
495 }
496 break;
497 case SI_FIX_FETCH_RGBA_32_SSCALED:
498 for (chan = 0; chan < 4; chan++) {
499 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
500 ctx->i32, "");
501 out[chan] = LLVMBuildSIToFP(gallivm->builder,
502 out[chan], ctx->f32, "");
503 }
504 break;
505 case SI_FIX_FETCH_RG_64_FLOAT:
506 for (chan = 0; chan < 2; chan++)
507 out[chan] = extract_double_to_float(ctx, input[0], chan);
508
509 out[2] = LLVMConstReal(ctx->f32, 0);
510 out[3] = LLVMConstReal(ctx->f32, 1);
511 break;
512 case SI_FIX_FETCH_RGB_64_FLOAT:
513 for (chan = 0; chan < 3; chan++)
514 out[chan] = extract_double_to_float(ctx, input[chan], 0);
515
516 out[3] = LLVMConstReal(ctx->f32, 1);
517 break;
518 case SI_FIX_FETCH_RGBA_64_FLOAT:
519 for (chan = 0; chan < 4; chan++) {
520 out[chan] = extract_double_to_float(ctx, input[chan / 2],
521 chan % 2);
522 }
523 break;
524 case SI_FIX_FETCH_RGB_8:
525 case SI_FIX_FETCH_RGB_8_INT:
526 case SI_FIX_FETCH_RGB_16:
527 case SI_FIX_FETCH_RGB_16_INT:
528 for (chan = 0; chan < 3; chan++) {
529 out[chan] = LLVMBuildExtractElement(gallivm->builder,
530 input[chan],
531 ctx->i32_0, "");
532 }
533 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
534 fix_fetch == SI_FIX_FETCH_RGB_16) {
535 out[3] = LLVMConstReal(ctx->f32, 1);
536 } else {
537 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
538 ctx->f32, "");
539 }
540 break;
541 }
542 }
543
544 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
545 unsigned swizzle)
546 {
547 struct si_shader_context *ctx = si_shader_context(bld_base);
548
549 if (swizzle > 0)
550 return bld_base->uint_bld.zero;
551
552 switch (ctx->type) {
553 case PIPE_SHADER_VERTEX:
554 return LLVMGetParam(ctx->main_fn,
555 ctx->param_vs_prim_id);
556 case PIPE_SHADER_TESS_CTRL:
557 return LLVMGetParam(ctx->main_fn,
558 SI_PARAM_PATCH_ID);
559 case PIPE_SHADER_TESS_EVAL:
560 return LLVMGetParam(ctx->main_fn,
561 ctx->param_tes_patch_id);
562 case PIPE_SHADER_GEOMETRY:
563 return LLVMGetParam(ctx->main_fn,
564 SI_PARAM_PRIMITIVE_ID);
565 default:
566 assert(0);
567 return bld_base->uint_bld.zero;
568 }
569 }
570
571 /**
572 * Return the value of tgsi_ind_register for indexing.
573 * This is the indirect index with the constant offset added to it.
574 */
575 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
576 const struct tgsi_ind_register *ind,
577 int rel_index)
578 {
579 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
580 LLVMValueRef result;
581
582 result = ctx->addrs[ind->Index][ind->Swizzle];
583 result = LLVMBuildLoad(gallivm->builder, result, "");
584 result = LLVMBuildAdd(gallivm->builder, result,
585 lp_build_const_int32(gallivm, rel_index), "");
586 return result;
587 }
588
589 /**
590 * Like get_indirect_index, but restricts the return value to a (possibly
591 * undefined) value inside [0..num).
592 */
593 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
594 const struct tgsi_ind_register *ind,
595 int rel_index, unsigned num)
596 {
597 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
598
599 /* LLVM 3.8: If indirect resource indexing is used:
600 * - SI & CIK hang
601 * - VI crashes
602 */
603 if (HAVE_LLVM <= 0x0308)
604 return LLVMGetUndef(ctx->i32);
605
606 return si_llvm_bound_index(ctx, result, num);
607 }
608
609
610 /**
611 * Calculate a dword address given an input or output register and a stride.
612 */
613 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
614 const struct tgsi_full_dst_register *dst,
615 const struct tgsi_full_src_register *src,
616 LLVMValueRef vertex_dw_stride,
617 LLVMValueRef base_addr)
618 {
619 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
620 struct tgsi_shader_info *info = &ctx->shader->selector->info;
621 ubyte *name, *index, *array_first;
622 int first, param;
623 struct tgsi_full_dst_register reg;
624
625 /* Set the register description. The address computation is the same
626 * for sources and destinations. */
627 if (src) {
628 reg.Register.File = src->Register.File;
629 reg.Register.Index = src->Register.Index;
630 reg.Register.Indirect = src->Register.Indirect;
631 reg.Register.Dimension = src->Register.Dimension;
632 reg.Indirect = src->Indirect;
633 reg.Dimension = src->Dimension;
634 reg.DimIndirect = src->DimIndirect;
635 } else
636 reg = *dst;
637
638 /* If the register is 2-dimensional (e.g. an array of vertices
639 * in a primitive), calculate the base address of the vertex. */
640 if (reg.Register.Dimension) {
641 LLVMValueRef index;
642
643 if (reg.Dimension.Indirect)
644 index = get_indirect_index(ctx, &reg.DimIndirect,
645 reg.Dimension.Index);
646 else
647 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
648
649 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
650 LLVMBuildMul(gallivm->builder, index,
651 vertex_dw_stride, ""), "");
652 }
653
654 /* Get information about the register. */
655 if (reg.Register.File == TGSI_FILE_INPUT) {
656 name = info->input_semantic_name;
657 index = info->input_semantic_index;
658 array_first = info->input_array_first;
659 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
660 name = info->output_semantic_name;
661 index = info->output_semantic_index;
662 array_first = info->output_array_first;
663 } else {
664 assert(0);
665 return NULL;
666 }
667
668 if (reg.Register.Indirect) {
669 /* Add the relative address of the element. */
670 LLVMValueRef ind_index;
671
672 if (reg.Indirect.ArrayID)
673 first = array_first[reg.Indirect.ArrayID];
674 else
675 first = reg.Register.Index;
676
677 ind_index = get_indirect_index(ctx, &reg.Indirect,
678 reg.Register.Index - first);
679
680 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
681 LLVMBuildMul(gallivm->builder, ind_index,
682 lp_build_const_int32(gallivm, 4), ""), "");
683
684 param = si_shader_io_get_unique_index(name[first], index[first]);
685 } else {
686 param = si_shader_io_get_unique_index(name[reg.Register.Index],
687 index[reg.Register.Index]);
688 }
689
690 /* Add the base address of the element. */
691 return LLVMBuildAdd(gallivm->builder, base_addr,
692 lp_build_const_int32(gallivm, param * 4), "");
693 }
694
695 /* The offchip buffer layout for TCS->TES is
696 *
697 * - attribute 0 of patch 0 vertex 0
698 * - attribute 0 of patch 0 vertex 1
699 * - attribute 0 of patch 0 vertex 2
700 * ...
701 * - attribute 0 of patch 1 vertex 0
702 * - attribute 0 of patch 1 vertex 1
703 * ...
704 * - attribute 1 of patch 0 vertex 0
705 * - attribute 1 of patch 0 vertex 1
706 * ...
707 * - per patch attribute 0 of patch 0
708 * - per patch attribute 0 of patch 1
709 * ...
710 *
711 * Note that every attribute has 4 components.
712 */
713 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
714 LLVMValueRef rel_patch_id,
715 LLVMValueRef vertex_index,
716 LLVMValueRef param_index)
717 {
718 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
719 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
720 LLVMValueRef param_stride, constant16;
721
722 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
723 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
724 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
725 num_patches, "");
726
727 constant16 = lp_build_const_int32(gallivm, 16);
728 if (vertex_index) {
729 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
730 vertices_per_patch, "");
731
732 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
733 vertex_index, "");
734
735 param_stride = total_vertices;
736 } else {
737 base_addr = rel_patch_id;
738 param_stride = num_patches;
739 }
740
741 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
742 LLVMBuildMul(gallivm->builder, param_index,
743 param_stride, ""), "");
744
745 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
746
747 if (!vertex_index) {
748 LLVMValueRef patch_data_offset =
749 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
750
751 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
752 patch_data_offset, "");
753 }
754 return base_addr;
755 }
756
757 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
758 struct si_shader_context *ctx,
759 const struct tgsi_full_dst_register *dst,
760 const struct tgsi_full_src_register *src)
761 {
762 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
763 struct tgsi_shader_info *info = &ctx->shader->selector->info;
764 ubyte *name, *index, *array_first;
765 struct tgsi_full_src_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef param_index = NULL;
768 unsigned param_index_base, param_base;
769
770 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
771
772 if (reg.Register.Dimension) {
773
774 if (reg.Dimension.Indirect)
775 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
776 reg.Dimension.Index);
777 else
778 vertex_index = lp_build_const_int32(gallivm,
779 reg.Dimension.Index);
780 }
781
782 /* Get information about the register. */
783 if (reg.Register.File == TGSI_FILE_INPUT) {
784 name = info->input_semantic_name;
785 index = info->input_semantic_index;
786 array_first = info->input_array_first;
787 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
788 name = info->output_semantic_name;
789 index = info->output_semantic_index;
790 array_first = info->output_array_first;
791 } else {
792 assert(0);
793 return NULL;
794 }
795
796 if (reg.Register.Indirect) {
797 if (reg.Indirect.ArrayID)
798 param_base = array_first[reg.Indirect.ArrayID];
799 else
800 param_base = reg.Register.Index;
801
802 param_index = get_indirect_index(ctx, &reg.Indirect,
803 reg.Register.Index - param_base);
804
805 } else {
806 param_base = reg.Register.Index;
807 param_index = lp_build_const_int32(gallivm, 0);
808 }
809
810 param_index_base = si_shader_io_get_unique_index(name[param_base],
811 index[param_base]);
812
813 param_index = LLVMBuildAdd(gallivm->builder, param_index,
814 lp_build_const_int32(gallivm, param_index_base),
815 "");
816
817 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
818 vertex_index, param_index);
819 }
820
821 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
822 enum tgsi_opcode_type type, unsigned swizzle,
823 LLVMValueRef buffer, LLVMValueRef offset,
824 LLVMValueRef base, bool readonly_memory)
825 {
826 struct si_shader_context *ctx = si_shader_context(bld_base);
827 struct gallivm_state *gallivm = bld_base->base.gallivm;
828 LLVMValueRef value, value2;
829 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
830 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
831
832 if (swizzle == ~0) {
833 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
834 0, 1, 0, readonly_memory);
835
836 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
837 }
838
839 if (!tgsi_type_is_64bit(type)) {
840 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
841 0, 1, 0, readonly_memory);
842
843 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
844 return LLVMBuildExtractElement(gallivm->builder, value,
845 lp_build_const_int32(gallivm, swizzle), "");
846 }
847
848 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
849 swizzle * 4, 1, 0, readonly_memory);
850
851 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
852 swizzle * 4 + 4, 1, 0, readonly_memory);
853
854 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
855 }
856
857 /**
858 * Load from LDS.
859 *
860 * \param type output value type
861 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
862 * \param dw_addr address in dwords
863 */
864 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
865 enum tgsi_opcode_type type, unsigned swizzle,
866 LLVMValueRef dw_addr)
867 {
868 struct si_shader_context *ctx = si_shader_context(bld_base);
869 struct gallivm_state *gallivm = bld_base->base.gallivm;
870 LLVMValueRef value;
871
872 if (swizzle == ~0) {
873 LLVMValueRef values[TGSI_NUM_CHANNELS];
874
875 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
876 values[chan] = lds_load(bld_base, type, chan, dw_addr);
877
878 return lp_build_gather_values(bld_base->base.gallivm, values,
879 TGSI_NUM_CHANNELS);
880 }
881
882 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
883 lp_build_const_int32(gallivm, swizzle));
884
885 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
886 if (tgsi_type_is_64bit(type)) {
887 LLVMValueRef value2;
888 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
889 lp_build_const_int32(gallivm, 1));
890 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
891 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
892 }
893
894 return LLVMBuildBitCast(gallivm->builder, value,
895 tgsi2llvmtype(bld_base, type), "");
896 }
897
898 /**
899 * Store to LDS.
900 *
901 * \param swizzle offset (typically 0..3)
902 * \param dw_addr address in dwords
903 * \param value value to store
904 */
905 static void lds_store(struct lp_build_tgsi_context *bld_base,
906 unsigned swizzle, LLVMValueRef dw_addr,
907 LLVMValueRef value)
908 {
909 struct si_shader_context *ctx = si_shader_context(bld_base);
910 struct gallivm_state *gallivm = bld_base->base.gallivm;
911
912 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
913 lp_build_const_int32(gallivm, swizzle));
914
915 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
916 ac_build_indexed_store(&ctx->ac, ctx->lds,
917 dw_addr, value);
918 }
919
920 static LLVMValueRef fetch_input_tcs(
921 struct lp_build_tgsi_context *bld_base,
922 const struct tgsi_full_src_register *reg,
923 enum tgsi_opcode_type type, unsigned swizzle)
924 {
925 struct si_shader_context *ctx = si_shader_context(bld_base);
926 LLVMValueRef dw_addr, stride;
927
928 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
929 dw_addr = get_tcs_in_current_patch_offset(ctx);
930 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
931
932 return lds_load(bld_base, type, swizzle, dw_addr);
933 }
934
935 static LLVMValueRef fetch_output_tcs(
936 struct lp_build_tgsi_context *bld_base,
937 const struct tgsi_full_src_register *reg,
938 enum tgsi_opcode_type type, unsigned swizzle)
939 {
940 struct si_shader_context *ctx = si_shader_context(bld_base);
941 LLVMValueRef dw_addr, stride;
942
943 if (reg->Register.Dimension) {
944 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
945 dw_addr = get_tcs_out_current_patch_offset(ctx);
946 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
947 } else {
948 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
949 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
950 }
951
952 return lds_load(bld_base, type, swizzle, dw_addr);
953 }
954
955 static LLVMValueRef fetch_input_tes(
956 struct lp_build_tgsi_context *bld_base,
957 const struct tgsi_full_src_register *reg,
958 enum tgsi_opcode_type type, unsigned swizzle)
959 {
960 struct si_shader_context *ctx = si_shader_context(bld_base);
961 struct gallivm_state *gallivm = bld_base->base.gallivm;
962 LLVMValueRef rw_buffers, buffer, base, addr;
963
964 rw_buffers = LLVMGetParam(ctx->main_fn,
965 SI_PARAM_RW_BUFFERS);
966 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
967 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
968
969 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
970 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
971
972 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
973 }
974
975 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
976 const struct tgsi_full_instruction *inst,
977 const struct tgsi_opcode_info *info,
978 LLVMValueRef dst[4])
979 {
980 struct si_shader_context *ctx = si_shader_context(bld_base);
981 struct gallivm_state *gallivm = bld_base->base.gallivm;
982 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
983 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
984 unsigned chan_index;
985 LLVMValueRef dw_addr, stride;
986 LLVMValueRef rw_buffers, buffer, base, buf_addr;
987 LLVMValueRef values[4];
988 bool skip_lds_store;
989 bool is_tess_factor = false;
990
991 /* Only handle per-patch and per-vertex outputs here.
992 * Vectors will be lowered to scalars and this function will be called again.
993 */
994 if (reg->Register.File != TGSI_FILE_OUTPUT ||
995 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
996 si_llvm_emit_store(bld_base, inst, info, dst);
997 return;
998 }
999
1000 if (reg->Register.Dimension) {
1001 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1002 dw_addr = get_tcs_out_current_patch_offset(ctx);
1003 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1004 skip_lds_store = !sh_info->reads_pervertex_outputs;
1005 } else {
1006 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1007 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1008 skip_lds_store = !sh_info->reads_perpatch_outputs;
1009
1010 if (!reg->Register.Indirect) {
1011 int name = sh_info->output_semantic_name[reg->Register.Index];
1012
1013 /* Always write tess factors into LDS for the TCS epilog. */
1014 if (name == TGSI_SEMANTIC_TESSINNER ||
1015 name == TGSI_SEMANTIC_TESSOUTER) {
1016 skip_lds_store = false;
1017 is_tess_factor = true;
1018 }
1019 }
1020 }
1021
1022 rw_buffers = LLVMGetParam(ctx->main_fn,
1023 SI_PARAM_RW_BUFFERS);
1024 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1025 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1026
1027 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1028 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1029
1030
1031 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1032 LLVMValueRef value = dst[chan_index];
1033
1034 if (inst->Instruction.Saturate)
1035 value = ac_build_clamp(&ctx->ac, value);
1036
1037 /* Skip LDS stores if there is no LDS read of this output. */
1038 if (!skip_lds_store)
1039 lds_store(bld_base, chan_index, dw_addr, value);
1040
1041 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1042 values[chan_index] = value;
1043
1044 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1045 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1046 buf_addr, base,
1047 4 * chan_index, 1, 0, true, false);
1048 }
1049 }
1050
1051 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1052 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1053 values, 4);
1054 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1055 base, 0, 1, 0, true, false);
1056 }
1057 }
1058
1059 static LLVMValueRef fetch_input_gs(
1060 struct lp_build_tgsi_context *bld_base,
1061 const struct tgsi_full_src_register *reg,
1062 enum tgsi_opcode_type type,
1063 unsigned swizzle)
1064 {
1065 struct lp_build_context *base = &bld_base->base;
1066 struct si_shader_context *ctx = si_shader_context(bld_base);
1067 struct si_shader *shader = ctx->shader;
1068 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1069 struct gallivm_state *gallivm = base->gallivm;
1070 LLVMValueRef vtx_offset, soffset;
1071 unsigned vtx_offset_param;
1072 struct tgsi_shader_info *info = &shader->selector->info;
1073 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1074 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1075 unsigned param;
1076 LLVMValueRef value;
1077
1078 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1079 return get_primitive_id(bld_base, swizzle);
1080
1081 if (!reg->Register.Dimension)
1082 return NULL;
1083
1084 if (swizzle == ~0) {
1085 LLVMValueRef values[TGSI_NUM_CHANNELS];
1086 unsigned chan;
1087 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1088 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1089 }
1090 return lp_build_gather_values(bld_base->base.gallivm, values,
1091 TGSI_NUM_CHANNELS);
1092 }
1093
1094 /* Get the vertex offset parameter */
1095 vtx_offset_param = reg->Dimension.Index;
1096 if (vtx_offset_param < 2) {
1097 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1098 } else {
1099 assert(vtx_offset_param < 6);
1100 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1101 }
1102 vtx_offset = lp_build_mul_imm(uint,
1103 LLVMGetParam(ctx->main_fn,
1104 vtx_offset_param),
1105 4);
1106
1107 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1108 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1109
1110 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, uint->zero,
1111 vtx_offset, soffset, 0, 1, 0, true);
1112 if (tgsi_type_is_64bit(type)) {
1113 LLVMValueRef value2;
1114 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1115
1116 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1117 uint->zero, vtx_offset, soffset,
1118 0, 1, 0, true);
1119 return si_llvm_emit_fetch_64bit(bld_base, type,
1120 value, value2);
1121 }
1122 return LLVMBuildBitCast(gallivm->builder,
1123 value,
1124 tgsi2llvmtype(bld_base, type), "");
1125 }
1126
1127 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1128 {
1129 switch (interpolate) {
1130 case TGSI_INTERPOLATE_CONSTANT:
1131 return 0;
1132
1133 case TGSI_INTERPOLATE_LINEAR:
1134 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1135 return SI_PARAM_LINEAR_SAMPLE;
1136 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1137 return SI_PARAM_LINEAR_CENTROID;
1138 else
1139 return SI_PARAM_LINEAR_CENTER;
1140 break;
1141 case TGSI_INTERPOLATE_COLOR:
1142 case TGSI_INTERPOLATE_PERSPECTIVE:
1143 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1144 return SI_PARAM_PERSP_SAMPLE;
1145 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1146 return SI_PARAM_PERSP_CENTROID;
1147 else
1148 return SI_PARAM_PERSP_CENTER;
1149 break;
1150 default:
1151 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1152 return -1;
1153 }
1154 }
1155
1156 /**
1157 * Interpolate a fragment shader input.
1158 *
1159 * @param ctx context
1160 * @param input_index index of the input in hardware
1161 * @param semantic_name TGSI_SEMANTIC_*
1162 * @param semantic_index semantic index
1163 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1164 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1165 * @param interp_param interpolation weights (i,j)
1166 * @param prim_mask SI_PARAM_PRIM_MASK
1167 * @param face SI_PARAM_FRONT_FACE
1168 * @param result the return value (4 components)
1169 */
1170 static void interp_fs_input(struct si_shader_context *ctx,
1171 unsigned input_index,
1172 unsigned semantic_name,
1173 unsigned semantic_index,
1174 unsigned num_interp_inputs,
1175 unsigned colors_read_mask,
1176 LLVMValueRef interp_param,
1177 LLVMValueRef prim_mask,
1178 LLVMValueRef face,
1179 LLVMValueRef result[4])
1180 {
1181 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1182 struct lp_build_context *base = &bld_base->base;
1183 struct lp_build_context *uint = &bld_base->uint_bld;
1184 struct gallivm_state *gallivm = base->gallivm;
1185 LLVMValueRef attr_number;
1186 LLVMValueRef i, j;
1187
1188 unsigned chan;
1189
1190 /* fs.constant returns the param from the middle vertex, so it's not
1191 * really useful for flat shading. It's meant to be used for custom
1192 * interpolation (but the intrinsic can't fetch from the other two
1193 * vertices).
1194 *
1195 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1196 * to do the right thing. The only reason we use fs.constant is that
1197 * fs.interp cannot be used on integers, because they can be equal
1198 * to NaN.
1199 *
1200 * When interp is false we will use fs.constant or for newer llvm,
1201 * amdgcn.interp.mov.
1202 */
1203 bool interp = interp_param != NULL;
1204
1205 attr_number = lp_build_const_int32(gallivm, input_index);
1206
1207 if (interp) {
1208 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1209 LLVMVectorType(ctx->f32, 2), "");
1210
1211 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1212 uint->zero, "");
1213 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1214 uint->one, "");
1215 }
1216
1217 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1218 ctx->shader->key.part.ps.prolog.color_two_side) {
1219 LLVMValueRef is_face_positive;
1220 LLVMValueRef back_attr_number;
1221
1222 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1223 * otherwise it's at offset "num_inputs".
1224 */
1225 unsigned back_attr_offset = num_interp_inputs;
1226 if (semantic_index == 1 && colors_read_mask & 0xf)
1227 back_attr_offset += 1;
1228
1229 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1230
1231 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1232 face, uint->zero, "");
1233
1234 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1235 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1236 LLVMValueRef front, back;
1237
1238 if (interp) {
1239 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1240 attr_number, prim_mask,
1241 i, j);
1242 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1243 back_attr_number, prim_mask,
1244 i, j);
1245 } else {
1246 front = ac_build_fs_interp_mov(&ctx->ac,
1247 lp_build_const_int32(gallivm, 2), /* P0 */
1248 llvm_chan, attr_number, prim_mask);
1249 back = ac_build_fs_interp_mov(&ctx->ac,
1250 lp_build_const_int32(gallivm, 2), /* P0 */
1251 llvm_chan, back_attr_number, prim_mask);
1252 }
1253
1254 result[chan] = LLVMBuildSelect(gallivm->builder,
1255 is_face_positive,
1256 front,
1257 back,
1258 "");
1259 }
1260 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1261 if (interp) {
1262 result[0] = ac_build_fs_interp(&ctx->ac, uint->zero,
1263 attr_number, prim_mask, i, j);
1264 } else {
1265 result[0] = ac_build_fs_interp_mov(&ctx->ac, uint->zero,
1266 lp_build_const_int32(gallivm, 2), /* P0 */
1267 attr_number, prim_mask);
1268 }
1269 result[1] =
1270 result[2] = lp_build_const_float(gallivm, 0.0f);
1271 result[3] = lp_build_const_float(gallivm, 1.0f);
1272 } else {
1273 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1274 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1275
1276 if (interp) {
1277 result[chan] = ac_build_fs_interp(&ctx->ac,
1278 llvm_chan, attr_number, prim_mask, i, j);
1279 } else {
1280 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1281 lp_build_const_int32(gallivm, 2), /* P0 */
1282 llvm_chan, attr_number, prim_mask);
1283 }
1284 }
1285 }
1286 }
1287
1288 static void declare_input_fs(
1289 struct si_shader_context *radeon_bld,
1290 unsigned input_index,
1291 const struct tgsi_full_declaration *decl,
1292 LLVMValueRef out[4])
1293 {
1294 struct lp_build_context *base = &radeon_bld->bld_base.base;
1295 struct si_shader_context *ctx =
1296 si_shader_context(&radeon_bld->bld_base);
1297 struct si_shader *shader = ctx->shader;
1298 LLVMValueRef main_fn = radeon_bld->main_fn;
1299 LLVMValueRef interp_param = NULL;
1300 int interp_param_idx;
1301
1302 /* Get colors from input VGPRs (set by the prolog). */
1303 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1304 unsigned i = decl->Semantic.Index;
1305 unsigned colors_read = shader->selector->info.colors_read;
1306 unsigned mask = colors_read >> (i * 4);
1307 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1308 (i ? util_bitcount(colors_read & 0xf) : 0);
1309
1310 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1311 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1312 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1313 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1314 return;
1315 }
1316
1317 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1318 decl->Interp.Location);
1319 if (interp_param_idx == -1)
1320 return;
1321 else if (interp_param_idx) {
1322 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1323 }
1324
1325 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1326 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1327 ctx->shader->key.part.ps.prolog.flatshade_colors)
1328 interp_param = NULL; /* load the constant color */
1329
1330 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1331 decl->Semantic.Index, shader->selector->info.num_inputs,
1332 shader->selector->info.colors_read, interp_param,
1333 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1334 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1335 &out[0]);
1336 }
1337
1338 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1339 {
1340 return unpack_param(si_shader_context(&radeon_bld->bld_base),
1341 SI_PARAM_ANCILLARY, 8, 4);
1342 }
1343
1344
1345 /**
1346 * Load a dword from a constant buffer.
1347 */
1348 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1349 LLVMValueRef resource,
1350 LLVMValueRef offset)
1351 {
1352 LLVMBuilderRef builder = ctx->gallivm.builder;
1353 LLVMValueRef args[2] = {resource, offset};
1354
1355 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1356 LP_FUNC_ATTR_READNONE |
1357 LP_FUNC_ATTR_LEGACY);
1358 }
1359
1360 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1361 {
1362 struct si_shader_context *ctx =
1363 si_shader_context(&radeon_bld->bld_base);
1364 struct lp_build_context *uint_bld = &radeon_bld->bld_base.uint_bld;
1365 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1366 LLVMBuilderRef builder = gallivm->builder;
1367 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1368 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1369 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1370
1371 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1372 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1373 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1374
1375 LLVMValueRef pos[4] = {
1376 buffer_load_const(ctx, resource, offset0),
1377 buffer_load_const(ctx, resource, offset1),
1378 lp_build_const_float(gallivm, 0),
1379 lp_build_const_float(gallivm, 0)
1380 };
1381
1382 return lp_build_gather_values(gallivm, pos, 4);
1383 }
1384
1385 static void declare_system_value(
1386 struct si_shader_context *radeon_bld,
1387 unsigned index,
1388 const struct tgsi_full_declaration *decl)
1389 {
1390 struct si_shader_context *ctx =
1391 si_shader_context(&radeon_bld->bld_base);
1392 struct lp_build_context *bld = &radeon_bld->bld_base.base;
1393 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1394 LLVMValueRef value = 0;
1395
1396 switch (decl->Semantic.Name) {
1397 case TGSI_SEMANTIC_INSTANCEID:
1398 value = LLVMGetParam(radeon_bld->main_fn,
1399 ctx->param_instance_id);
1400 break;
1401
1402 case TGSI_SEMANTIC_VERTEXID:
1403 value = LLVMBuildAdd(gallivm->builder,
1404 LLVMGetParam(radeon_bld->main_fn,
1405 ctx->param_vertex_id),
1406 LLVMGetParam(radeon_bld->main_fn,
1407 SI_PARAM_BASE_VERTEX), "");
1408 break;
1409
1410 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1411 value = LLVMGetParam(radeon_bld->main_fn,
1412 ctx->param_vertex_id);
1413 break;
1414
1415 case TGSI_SEMANTIC_BASEVERTEX:
1416 value = LLVMGetParam(radeon_bld->main_fn,
1417 SI_PARAM_BASE_VERTEX);
1418 break;
1419
1420 case TGSI_SEMANTIC_BASEINSTANCE:
1421 value = LLVMGetParam(radeon_bld->main_fn,
1422 SI_PARAM_START_INSTANCE);
1423 break;
1424
1425 case TGSI_SEMANTIC_DRAWID:
1426 value = LLVMGetParam(radeon_bld->main_fn,
1427 SI_PARAM_DRAWID);
1428 break;
1429
1430 case TGSI_SEMANTIC_INVOCATIONID:
1431 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1432 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1433 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1434 value = LLVMGetParam(radeon_bld->main_fn,
1435 SI_PARAM_GS_INSTANCE_ID);
1436 else
1437 assert(!"INVOCATIONID not implemented");
1438 break;
1439
1440 case TGSI_SEMANTIC_POSITION:
1441 {
1442 LLVMValueRef pos[4] = {
1443 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1444 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1445 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1446 lp_build_emit_llvm_unary(&radeon_bld->bld_base, TGSI_OPCODE_RCP,
1447 LLVMGetParam(radeon_bld->main_fn,
1448 SI_PARAM_POS_W_FLOAT)),
1449 };
1450 value = lp_build_gather_values(gallivm, pos, 4);
1451 break;
1452 }
1453
1454 case TGSI_SEMANTIC_FACE:
1455 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1456 break;
1457
1458 case TGSI_SEMANTIC_SAMPLEID:
1459 value = get_sample_id(radeon_bld);
1460 break;
1461
1462 case TGSI_SEMANTIC_SAMPLEPOS: {
1463 LLVMValueRef pos[4] = {
1464 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1465 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1466 lp_build_const_float(gallivm, 0),
1467 lp_build_const_float(gallivm, 0)
1468 };
1469 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1470 TGSI_OPCODE_FRC, pos[0]);
1471 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1472 TGSI_OPCODE_FRC, pos[1]);
1473 value = lp_build_gather_values(gallivm, pos, 4);
1474 break;
1475 }
1476
1477 case TGSI_SEMANTIC_SAMPLEMASK:
1478 /* This can only occur with the OpenGL Core profile, which
1479 * doesn't support smoothing.
1480 */
1481 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1482 break;
1483
1484 case TGSI_SEMANTIC_TESSCOORD:
1485 {
1486 LLVMValueRef coord[4] = {
1487 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1488 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1489 bld->zero,
1490 bld->zero
1491 };
1492
1493 /* For triangles, the vector should be (u, v, 1-u-v). */
1494 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1495 PIPE_PRIM_TRIANGLES)
1496 coord[2] = lp_build_sub(bld, bld->one,
1497 lp_build_add(bld, coord[0], coord[1]));
1498
1499 value = lp_build_gather_values(gallivm, coord, 4);
1500 break;
1501 }
1502
1503 case TGSI_SEMANTIC_VERTICESIN:
1504 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1505 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1506 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1507 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1508 else
1509 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1510 break;
1511
1512 case TGSI_SEMANTIC_TESSINNER:
1513 case TGSI_SEMANTIC_TESSOUTER:
1514 {
1515 LLVMValueRef rw_buffers, buffer, base, addr;
1516 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1517
1518 rw_buffers = LLVMGetParam(ctx->main_fn,
1519 SI_PARAM_RW_BUFFERS);
1520 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1521 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1522
1523 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1524 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1525 lp_build_const_int32(gallivm, param));
1526
1527 value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
1528 ~0, buffer, base, addr, true);
1529
1530 break;
1531 }
1532
1533 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1534 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1535 {
1536 LLVMValueRef buf, slot, val[4];
1537 int i, offset;
1538
1539 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1540 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1541 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1542 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1543
1544 for (i = 0; i < 4; i++)
1545 val[i] = buffer_load_const(ctx, buf,
1546 lp_build_const_int32(gallivm, (offset + i) * 4));
1547 value = lp_build_gather_values(gallivm, val, 4);
1548 break;
1549 }
1550
1551 case TGSI_SEMANTIC_PRIMID:
1552 value = get_primitive_id(&radeon_bld->bld_base, 0);
1553 break;
1554
1555 case TGSI_SEMANTIC_GRID_SIZE:
1556 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1557 break;
1558
1559 case TGSI_SEMANTIC_BLOCK_SIZE:
1560 {
1561 LLVMValueRef values[3];
1562 unsigned i;
1563 unsigned *properties = ctx->shader->selector->info.properties;
1564
1565 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1566 unsigned sizes[3] = {
1567 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1568 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1569 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1570 };
1571
1572 for (i = 0; i < 3; ++i)
1573 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1574
1575 value = lp_build_gather_values(gallivm, values, 3);
1576 } else {
1577 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1578 }
1579 break;
1580 }
1581
1582 case TGSI_SEMANTIC_BLOCK_ID:
1583 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1584 break;
1585
1586 case TGSI_SEMANTIC_THREAD_ID:
1587 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1588 break;
1589
1590 case TGSI_SEMANTIC_HELPER_INVOCATION:
1591 if (HAVE_LLVM >= 0x0309) {
1592 value = lp_build_intrinsic(gallivm->builder,
1593 "llvm.amdgcn.ps.live",
1594 ctx->i1, NULL, 0,
1595 LP_FUNC_ATTR_READNONE);
1596 value = LLVMBuildNot(gallivm->builder, value, "");
1597 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1598 } else {
1599 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1600 return;
1601 }
1602 break;
1603
1604 default:
1605 assert(!"unknown system value");
1606 return;
1607 }
1608
1609 radeon_bld->system_values[index] = value;
1610 }
1611
1612 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1613 const struct tgsi_full_declaration *decl)
1614 {
1615 struct si_shader_context *ctx =
1616 si_shader_context(&radeon_bld->bld_base);
1617 struct si_shader_selector *sel = ctx->shader->selector;
1618 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1619
1620 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1621 LLVMValueRef var;
1622
1623 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1624 assert(decl->Range.First == decl->Range.Last);
1625 assert(!ctx->shared_memory);
1626
1627 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1628 LLVMArrayType(ctx->i8, sel->local_size),
1629 "compute_lds",
1630 LOCAL_ADDR_SPACE);
1631 LLVMSetAlignment(var, 4);
1632
1633 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1634 }
1635
1636 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1637 {
1638 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1639 SI_PARAM_CONST_BUFFERS);
1640
1641 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1642 LLVMConstInt(ctx->i32, i, 0));
1643 }
1644
1645 static LLVMValueRef fetch_constant(
1646 struct lp_build_tgsi_context *bld_base,
1647 const struct tgsi_full_src_register *reg,
1648 enum tgsi_opcode_type type,
1649 unsigned swizzle)
1650 {
1651 struct si_shader_context *ctx = si_shader_context(bld_base);
1652 struct lp_build_context *base = &bld_base->base;
1653 const struct tgsi_ind_register *ireg = &reg->Indirect;
1654 unsigned buf, idx;
1655
1656 LLVMValueRef addr, bufp;
1657 LLVMValueRef result;
1658
1659 if (swizzle == LP_CHAN_ALL) {
1660 unsigned chan;
1661 LLVMValueRef values[4];
1662 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1663 values[chan] = fetch_constant(bld_base, reg, type, chan);
1664
1665 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1666 }
1667
1668 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1669 idx = reg->Register.Index * 4 + swizzle;
1670
1671 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1672 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1673 LLVMValueRef index;
1674 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1675 reg->Dimension.Index,
1676 SI_NUM_CONST_BUFFERS);
1677 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1678 } else
1679 bufp = load_const_buffer_desc(ctx, buf);
1680
1681 if (reg->Register.Indirect) {
1682 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1683 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1684 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1685 addr = lp_build_add(&bld_base->uint_bld, addr,
1686 lp_build_const_int32(base->gallivm, idx * 4));
1687 } else {
1688 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1689 }
1690
1691 result = buffer_load_const(ctx, bufp, addr);
1692
1693 if (!tgsi_type_is_64bit(type))
1694 result = bitcast(bld_base, type, result);
1695 else {
1696 LLVMValueRef addr2, result2;
1697
1698 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1699 LLVMConstInt(ctx->i32, 4, 0));
1700 result2 = buffer_load_const(ctx, bufp, addr2);
1701
1702 result = si_llvm_emit_fetch_64bit(bld_base, type,
1703 result, result2);
1704 }
1705 return result;
1706 }
1707
1708 /* Upper 16 bits must be zero. */
1709 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1710 LLVMValueRef val[2])
1711 {
1712 return LLVMBuildOr(gallivm->builder, val[0],
1713 LLVMBuildShl(gallivm->builder, val[1],
1714 lp_build_const_int32(gallivm, 16),
1715 ""), "");
1716 }
1717
1718 /* Upper 16 bits are ignored and will be dropped. */
1719 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1720 LLVMValueRef val[2])
1721 {
1722 LLVMValueRef v[2] = {
1723 LLVMBuildAnd(gallivm->builder, val[0],
1724 lp_build_const_int32(gallivm, 0xffff), ""),
1725 val[1],
1726 };
1727 return si_llvm_pack_two_int16(gallivm, v);
1728 }
1729
1730 /* Initialize arguments for the shader export intrinsic */
1731 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1732 LLVMValueRef *values,
1733 unsigned target,
1734 struct ac_export_args *args)
1735 {
1736 struct si_shader_context *ctx = si_shader_context(bld_base);
1737 struct lp_build_context *base = &bld_base->base;
1738 struct gallivm_state *gallivm = base->gallivm;
1739 LLVMBuilderRef builder = base->gallivm->builder;
1740 LLVMValueRef val[4];
1741 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1742 unsigned chan;
1743 bool is_int8, is_int10;
1744
1745 /* Default is 0xf. Adjusted below depending on the format. */
1746 args->enabled_channels = 0xf; /* writemask */
1747
1748 /* Specify whether the EXEC mask represents the valid mask */
1749 args->valid_mask = 0;
1750
1751 /* Specify whether this is the last export */
1752 args->done = 0;
1753
1754 /* Specify the target we are exporting */
1755 args->target = target;
1756
1757 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1758 const struct si_shader_key *key = &ctx->shader->key;
1759 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1760 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1761
1762 assert(cbuf >= 0 && cbuf < 8);
1763 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1764 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1765 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1766 }
1767
1768 args->compr = false;
1769 args->out[0] = base->undef;
1770 args->out[1] = base->undef;
1771 args->out[2] = base->undef;
1772 args->out[3] = base->undef;
1773
1774 switch (spi_shader_col_format) {
1775 case V_028714_SPI_SHADER_ZERO:
1776 args->enabled_channels = 0; /* writemask */
1777 args->target = V_008DFC_SQ_EXP_NULL;
1778 break;
1779
1780 case V_028714_SPI_SHADER_32_R:
1781 args->enabled_channels = 1; /* writemask */
1782 args->out[0] = values[0];
1783 break;
1784
1785 case V_028714_SPI_SHADER_32_GR:
1786 args->enabled_channels = 0x3; /* writemask */
1787 args->out[0] = values[0];
1788 args->out[1] = values[1];
1789 break;
1790
1791 case V_028714_SPI_SHADER_32_AR:
1792 args->enabled_channels = 0x9; /* writemask */
1793 args->out[0] = values[0];
1794 args->out[3] = values[3];
1795 break;
1796
1797 case V_028714_SPI_SHADER_FP16_ABGR:
1798 args->compr = 1; /* COMPR flag */
1799
1800 for (chan = 0; chan < 2; chan++) {
1801 LLVMValueRef pack_args[2] = {
1802 values[2 * chan],
1803 values[2 * chan + 1]
1804 };
1805 LLVMValueRef packed;
1806
1807 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1808 args->out[chan] =
1809 LLVMBuildBitCast(base->gallivm->builder,
1810 packed, ctx->f32, "");
1811 }
1812 break;
1813
1814 case V_028714_SPI_SHADER_UNORM16_ABGR:
1815 for (chan = 0; chan < 4; chan++) {
1816 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1817 val[chan] = LLVMBuildFMul(builder, val[chan],
1818 lp_build_const_float(gallivm, 65535), "");
1819 val[chan] = LLVMBuildFAdd(builder, val[chan],
1820 lp_build_const_float(gallivm, 0.5), "");
1821 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1822 ctx->i32, "");
1823 }
1824
1825 args->compr = 1; /* COMPR flag */
1826 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1827 si_llvm_pack_two_int16(gallivm, val));
1828 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1829 si_llvm_pack_two_int16(gallivm, val+2));
1830 break;
1831
1832 case V_028714_SPI_SHADER_SNORM16_ABGR:
1833 for (chan = 0; chan < 4; chan++) {
1834 /* Clamp between [-1, 1]. */
1835 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1836 values[chan],
1837 lp_build_const_float(gallivm, 1));
1838 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1839 val[chan],
1840 lp_build_const_float(gallivm, -1));
1841 /* Convert to a signed integer in [-32767, 32767]. */
1842 val[chan] = LLVMBuildFMul(builder, val[chan],
1843 lp_build_const_float(gallivm, 32767), "");
1844 /* If positive, add 0.5, else add -0.5. */
1845 val[chan] = LLVMBuildFAdd(builder, val[chan],
1846 LLVMBuildSelect(builder,
1847 LLVMBuildFCmp(builder, LLVMRealOGE,
1848 val[chan], base->zero, ""),
1849 lp_build_const_float(gallivm, 0.5),
1850 lp_build_const_float(gallivm, -0.5), ""), "");
1851 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1852 }
1853
1854 args->compr = 1; /* COMPR flag */
1855 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1856 si_llvm_pack_two_int32_as_int16(gallivm, val));
1857 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1858 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1859 break;
1860
1861 case V_028714_SPI_SHADER_UINT16_ABGR: {
1862 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1863 is_int8 ? 255 : is_int10 ? 1023 : 65535);
1864 LLVMValueRef max_alpha =
1865 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 3);
1866
1867 /* Clamp. */
1868 for (chan = 0; chan < 4; chan++) {
1869 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1870 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1871 val[chan],
1872 chan == 3 ? max_alpha : max_rgb);
1873 }
1874
1875 args->compr = 1; /* COMPR flag */
1876 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1877 si_llvm_pack_two_int16(gallivm, val));
1878 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1879 si_llvm_pack_two_int16(gallivm, val+2));
1880 break;
1881 }
1882
1883 case V_028714_SPI_SHADER_SINT16_ABGR: {
1884 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1885 is_int8 ? 127 : is_int10 ? 511 : 32767);
1886 LLVMValueRef min_rgb = lp_build_const_int32(gallivm,
1887 is_int8 ? -128 : is_int10 ? -512 : -32768);
1888 LLVMValueRef max_alpha =
1889 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 1);
1890 LLVMValueRef min_alpha =
1891 !is_int10 ? min_rgb : lp_build_const_int32(gallivm, -2);
1892
1893 /* Clamp. */
1894 for (chan = 0; chan < 4; chan++) {
1895 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1896 val[chan] = lp_build_emit_llvm_binary(bld_base,
1897 TGSI_OPCODE_IMIN,
1898 val[chan], chan == 3 ? max_alpha : max_rgb);
1899 val[chan] = lp_build_emit_llvm_binary(bld_base,
1900 TGSI_OPCODE_IMAX,
1901 val[chan], chan == 3 ? min_alpha : min_rgb);
1902 }
1903
1904 args->compr = 1; /* COMPR flag */
1905 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1906 si_llvm_pack_two_int32_as_int16(gallivm, val));
1907 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1908 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1909 break;
1910 }
1911
1912 case V_028714_SPI_SHADER_32_ABGR:
1913 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1914 break;
1915 }
1916 }
1917
1918 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1919 LLVMValueRef alpha)
1920 {
1921 struct si_shader_context *ctx = si_shader_context(bld_base);
1922 struct gallivm_state *gallivm = bld_base->base.gallivm;
1923
1924 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1925 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1926 SI_PARAM_ALPHA_REF);
1927
1928 LLVMValueRef alpha_pass =
1929 lp_build_cmp(&bld_base->base,
1930 ctx->shader->key.part.ps.epilog.alpha_func,
1931 alpha, alpha_ref);
1932 LLVMValueRef arg =
1933 lp_build_select(&bld_base->base,
1934 alpha_pass,
1935 lp_build_const_float(gallivm, 1.0f),
1936 lp_build_const_float(gallivm, -1.0f));
1937
1938 ac_build_kill(&ctx->ac, arg);
1939 } else {
1940 ac_build_kill(&ctx->ac, NULL);
1941 }
1942 }
1943
1944 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1945 LLVMValueRef alpha,
1946 unsigned samplemask_param)
1947 {
1948 struct si_shader_context *ctx = si_shader_context(bld_base);
1949 struct gallivm_state *gallivm = bld_base->base.gallivm;
1950 LLVMValueRef coverage;
1951
1952 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1953 coverage = LLVMGetParam(ctx->main_fn,
1954 samplemask_param);
1955 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1956
1957 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1958 ctx->i32,
1959 &coverage, 1, LP_FUNC_ATTR_READNONE);
1960
1961 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1962 ctx->f32, "");
1963
1964 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1965 lp_build_const_float(gallivm,
1966 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1967
1968 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1969 }
1970
1971 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1972 struct ac_export_args *pos, LLVMValueRef *out_elts)
1973 {
1974 struct si_shader_context *ctx = si_shader_context(bld_base);
1975 struct lp_build_context *base = &bld_base->base;
1976 unsigned reg_index;
1977 unsigned chan;
1978 unsigned const_chan;
1979 LLVMValueRef base_elt;
1980 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1981 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1982 SI_VS_CONST_CLIP_PLANES);
1983 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
1984
1985 for (reg_index = 0; reg_index < 2; reg_index ++) {
1986 struct ac_export_args *args = &pos[2 + reg_index];
1987
1988 args->out[0] =
1989 args->out[1] =
1990 args->out[2] =
1991 args->out[3] = lp_build_const_float(base->gallivm, 0.0f);
1992
1993 /* Compute dot products of position and user clip plane vectors */
1994 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1995 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1996 LLVMValueRef addr =
1997 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
1998 const_chan) * 4, 0);
1999 base_elt = buffer_load_const(ctx, const_resource,
2000 addr);
2001 args->out[chan] =
2002 lp_build_add(base, args->out[chan],
2003 lp_build_mul(base, base_elt,
2004 out_elts[const_chan]));
2005 }
2006 }
2007
2008 args->enabled_channels = 0xf;
2009 args->valid_mask = 0;
2010 args->done = 0;
2011 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2012 args->compr = 0;
2013 }
2014 }
2015
2016 static void si_dump_streamout(struct pipe_stream_output_info *so)
2017 {
2018 unsigned i;
2019
2020 if (so->num_outputs)
2021 fprintf(stderr, "STREAMOUT\n");
2022
2023 for (i = 0; i < so->num_outputs; i++) {
2024 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2025 so->output[i].start_component;
2026 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2027 i, so->output[i].output_buffer,
2028 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2029 so->output[i].register_index,
2030 mask & 1 ? "x" : "",
2031 mask & 2 ? "y" : "",
2032 mask & 4 ? "z" : "",
2033 mask & 8 ? "w" : "");
2034 }
2035 }
2036
2037 static void emit_streamout_output(struct si_shader_context *ctx,
2038 LLVMValueRef const *so_buffers,
2039 LLVMValueRef const *so_write_offsets,
2040 struct pipe_stream_output *stream_out,
2041 struct si_shader_output_values *shader_out)
2042 {
2043 struct gallivm_state *gallivm = &ctx->gallivm;
2044 LLVMBuilderRef builder = gallivm->builder;
2045 unsigned buf_idx = stream_out->output_buffer;
2046 unsigned start = stream_out->start_component;
2047 unsigned num_comps = stream_out->num_components;
2048 LLVMValueRef out[4];
2049
2050 assert(num_comps && num_comps <= 4);
2051 if (!num_comps || num_comps > 4)
2052 return;
2053
2054 /* Load the output as int. */
2055 for (int j = 0; j < num_comps; j++) {
2056 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2057
2058 out[j] = LLVMBuildBitCast(builder,
2059 shader_out->values[start + j],
2060 ctx->i32, "");
2061 }
2062
2063 /* Pack the output. */
2064 LLVMValueRef vdata = NULL;
2065
2066 switch (num_comps) {
2067 case 1: /* as i32 */
2068 vdata = out[0];
2069 break;
2070 case 2: /* as v2i32 */
2071 case 3: /* as v4i32 (aligned to 4) */
2072 case 4: /* as v4i32 */
2073 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2074 for (int j = 0; j < num_comps; j++) {
2075 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2076 LLVMConstInt(ctx->i32, j, 0), "");
2077 }
2078 break;
2079 }
2080
2081 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2082 vdata, num_comps,
2083 so_write_offsets[buf_idx],
2084 LLVMConstInt(ctx->i32, 0, 0),
2085 stream_out->dst_offset * 4, 1, 1, true, false);
2086 }
2087
2088 /**
2089 * Write streamout data to buffers for vertex stream @p stream (different
2090 * vertex streams can occur for GS copy shaders).
2091 */
2092 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2093 struct si_shader_output_values *outputs,
2094 unsigned noutput, unsigned stream)
2095 {
2096 struct si_shader_selector *sel = ctx->shader->selector;
2097 struct pipe_stream_output_info *so = &sel->so;
2098 struct gallivm_state *gallivm = &ctx->gallivm;
2099 LLVMBuilderRef builder = gallivm->builder;
2100 int i;
2101 struct lp_build_if_state if_ctx;
2102
2103 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2104 LLVMValueRef so_vtx_count =
2105 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2106
2107 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2108
2109 /* can_emit = tid < so_vtx_count; */
2110 LLVMValueRef can_emit =
2111 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2112
2113 /* Emit the streamout code conditionally. This actually avoids
2114 * out-of-bounds buffer access. The hw tells us via the SGPR
2115 * (so_vtx_count) which threads are allowed to emit streamout data. */
2116 lp_build_if(&if_ctx, gallivm, can_emit);
2117 {
2118 /* The buffer offset is computed as follows:
2119 * ByteOffset = streamout_offset[buffer_id]*4 +
2120 * (streamout_write_index + thread_id)*stride[buffer_id] +
2121 * attrib_offset
2122 */
2123
2124 LLVMValueRef so_write_index =
2125 LLVMGetParam(ctx->main_fn,
2126 ctx->param_streamout_write_index);
2127
2128 /* Compute (streamout_write_index + thread_id). */
2129 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2130
2131 /* Load the descriptor and compute the write offset for each
2132 * enabled buffer. */
2133 LLVMValueRef so_write_offset[4] = {};
2134 LLVMValueRef so_buffers[4];
2135 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2136 SI_PARAM_RW_BUFFERS);
2137
2138 for (i = 0; i < 4; i++) {
2139 if (!so->stride[i])
2140 continue;
2141
2142 LLVMValueRef offset = lp_build_const_int32(gallivm,
2143 SI_VS_STREAMOUT_BUF0 + i);
2144
2145 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2146
2147 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2148 ctx->param_streamout_offset[i]);
2149 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2150
2151 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2152 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2153 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2154 }
2155
2156 /* Write streamout data. */
2157 for (i = 0; i < so->num_outputs; i++) {
2158 unsigned reg = so->output[i].register_index;
2159
2160 if (reg >= noutput)
2161 continue;
2162
2163 if (stream != so->output[i].stream)
2164 continue;
2165
2166 emit_streamout_output(ctx, so_buffers, so_write_offset,
2167 &so->output[i], &outputs[reg]);
2168 }
2169 }
2170 lp_build_endif(&if_ctx);
2171 }
2172
2173
2174 /* Generate export instructions for hardware VS shader stage */
2175 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2176 struct si_shader_output_values *outputs,
2177 unsigned noutput)
2178 {
2179 struct si_shader_context *ctx = si_shader_context(bld_base);
2180 struct si_shader *shader = ctx->shader;
2181 struct lp_build_context *base = &bld_base->base;
2182 struct ac_export_args args, pos_args[4] = {};
2183 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2184 unsigned semantic_name, semantic_index;
2185 unsigned target;
2186 unsigned param_count = 0;
2187 unsigned pos_idx;
2188 int i;
2189
2190 for (i = 0; i < noutput; i++) {
2191 semantic_name = outputs[i].semantic_name;
2192 semantic_index = outputs[i].semantic_index;
2193 bool export_param = true;
2194
2195 switch (semantic_name) {
2196 case TGSI_SEMANTIC_POSITION: /* ignore these */
2197 case TGSI_SEMANTIC_PSIZE:
2198 case TGSI_SEMANTIC_CLIPVERTEX:
2199 case TGSI_SEMANTIC_EDGEFLAG:
2200 break;
2201 case TGSI_SEMANTIC_GENERIC:
2202 case TGSI_SEMANTIC_CLIPDIST:
2203 if (shader->key.opt.hw_vs.kill_outputs &
2204 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2205 export_param = false;
2206 break;
2207 default:
2208 if (shader->key.opt.hw_vs.kill_outputs2 &
2209 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2210 export_param = false;
2211 break;
2212 }
2213
2214 if (outputs[i].vertex_stream[0] != 0 &&
2215 outputs[i].vertex_stream[1] != 0 &&
2216 outputs[i].vertex_stream[2] != 0 &&
2217 outputs[i].vertex_stream[3] != 0)
2218 export_param = false;
2219
2220 handle_semantic:
2221 /* Select the correct target */
2222 switch(semantic_name) {
2223 case TGSI_SEMANTIC_PSIZE:
2224 psize_value = outputs[i].values[0];
2225 continue;
2226 case TGSI_SEMANTIC_EDGEFLAG:
2227 edgeflag_value = outputs[i].values[0];
2228 continue;
2229 case TGSI_SEMANTIC_LAYER:
2230 layer_value = outputs[i].values[0];
2231 semantic_name = TGSI_SEMANTIC_GENERIC;
2232 goto handle_semantic;
2233 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2234 viewport_index_value = outputs[i].values[0];
2235 semantic_name = TGSI_SEMANTIC_GENERIC;
2236 goto handle_semantic;
2237 case TGSI_SEMANTIC_POSITION:
2238 target = V_008DFC_SQ_EXP_POS;
2239 break;
2240 case TGSI_SEMANTIC_CLIPDIST:
2241 if (shader->key.opt.hw_vs.clip_disable) {
2242 semantic_name = TGSI_SEMANTIC_GENERIC;
2243 goto handle_semantic;
2244 }
2245 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2246 break;
2247 case TGSI_SEMANTIC_CLIPVERTEX:
2248 if (shader->key.opt.hw_vs.clip_disable)
2249 continue;
2250 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2251 continue;
2252 case TGSI_SEMANTIC_COLOR:
2253 case TGSI_SEMANTIC_BCOLOR:
2254 case TGSI_SEMANTIC_PRIMID:
2255 case TGSI_SEMANTIC_FOG:
2256 case TGSI_SEMANTIC_TEXCOORD:
2257 case TGSI_SEMANTIC_GENERIC:
2258 if (!export_param)
2259 continue;
2260 target = V_008DFC_SQ_EXP_PARAM + param_count;
2261 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2262 shader->info.vs_output_param_offset[i] = param_count;
2263 param_count++;
2264 break;
2265 default:
2266 target = 0;
2267 fprintf(stderr,
2268 "Warning: SI unhandled vs output type:%d\n",
2269 semantic_name);
2270 }
2271
2272 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2273
2274 if (target >= V_008DFC_SQ_EXP_POS &&
2275 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2276 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2277 &args, sizeof(args));
2278 } else {
2279 ac_build_export(&ctx->ac, &args);
2280 }
2281
2282 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2283 semantic_name = TGSI_SEMANTIC_GENERIC;
2284 goto handle_semantic;
2285 }
2286 }
2287
2288 shader->info.nr_param_exports = param_count;
2289
2290 /* We need to add the position output manually if it's missing. */
2291 if (!pos_args[0].out[0]) {
2292 pos_args[0].enabled_channels = 0xf; /* writemask */
2293 pos_args[0].valid_mask = 0; /* EXEC mask */
2294 pos_args[0].done = 0; /* last export? */
2295 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2296 pos_args[0].compr = 0; /* COMPR flag */
2297 pos_args[0].out[0] = base->zero; /* X */
2298 pos_args[0].out[1] = base->zero; /* Y */
2299 pos_args[0].out[2] = base->zero; /* Z */
2300 pos_args[0].out[3] = base->one; /* W */
2301 }
2302
2303 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2304 if (shader->selector->info.writes_psize ||
2305 shader->selector->info.writes_edgeflag ||
2306 shader->selector->info.writes_viewport_index ||
2307 shader->selector->info.writes_layer) {
2308 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2309 (shader->selector->info.writes_edgeflag << 1) |
2310 (shader->selector->info.writes_layer << 2) |
2311 (shader->selector->info.writes_viewport_index << 3);
2312 pos_args[1].valid_mask = 0; /* EXEC mask */
2313 pos_args[1].done = 0; /* last export? */
2314 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2315 pos_args[1].compr = 0; /* COMPR flag */
2316 pos_args[1].out[0] = base->zero; /* X */
2317 pos_args[1].out[1] = base->zero; /* Y */
2318 pos_args[1].out[2] = base->zero; /* Z */
2319 pos_args[1].out[3] = base->zero; /* W */
2320
2321 if (shader->selector->info.writes_psize)
2322 pos_args[1].out[0] = psize_value;
2323
2324 if (shader->selector->info.writes_edgeflag) {
2325 /* The output is a float, but the hw expects an integer
2326 * with the first bit containing the edge flag. */
2327 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2328 edgeflag_value,
2329 ctx->i32, "");
2330 edgeflag_value = lp_build_min(&bld_base->int_bld,
2331 edgeflag_value,
2332 bld_base->int_bld.one);
2333
2334 /* The LLVM intrinsic expects a float. */
2335 pos_args[1].out[1] = LLVMBuildBitCast(base->gallivm->builder,
2336 edgeflag_value,
2337 ctx->f32, "");
2338 }
2339
2340 if (shader->selector->info.writes_layer)
2341 pos_args[1].out[2] = layer_value;
2342
2343 if (shader->selector->info.writes_viewport_index)
2344 pos_args[1].out[3] = viewport_index_value;
2345 }
2346
2347 for (i = 0; i < 4; i++)
2348 if (pos_args[i].out[0])
2349 shader->info.nr_pos_exports++;
2350
2351 pos_idx = 0;
2352 for (i = 0; i < 4; i++) {
2353 if (!pos_args[i].out[0])
2354 continue;
2355
2356 /* Specify the target we are exporting */
2357 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2358
2359 if (pos_idx == shader->info.nr_pos_exports)
2360 /* Specify that this is the last export */
2361 pos_args[i].done = 1;
2362
2363 ac_build_export(&ctx->ac, &pos_args[i]);
2364 }
2365 }
2366
2367 /**
2368 * Forward all outputs from the vertex shader to the TES. This is only used
2369 * for the fixed function TCS.
2370 */
2371 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2372 {
2373 struct si_shader_context *ctx = si_shader_context(bld_base);
2374 struct gallivm_state *gallivm = bld_base->base.gallivm;
2375 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2376 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2377 uint64_t inputs;
2378
2379 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2380
2381 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2382 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2383 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2384
2385 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2386
2387 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2388 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2389 lds_vertex_stride, "");
2390 lds_base = get_tcs_in_current_patch_offset(ctx);
2391 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2392
2393 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2394 while (inputs) {
2395 unsigned i = u_bit_scan64(&inputs);
2396
2397 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2398 lp_build_const_int32(gallivm, 4 * i),
2399 "");
2400
2401 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2402 get_rel_patch_id(ctx),
2403 invocation_id,
2404 lp_build_const_int32(gallivm, i));
2405
2406 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2407 lds_ptr);
2408
2409 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2410 buffer_offset, 0, 1, 0, true, false);
2411 }
2412 }
2413
2414 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2415 LLVMValueRef rel_patch_id,
2416 LLVMValueRef invocation_id,
2417 LLVMValueRef tcs_out_current_patch_data_offset)
2418 {
2419 struct si_shader_context *ctx = si_shader_context(bld_base);
2420 struct gallivm_state *gallivm = bld_base->base.gallivm;
2421 struct si_shader *shader = ctx->shader;
2422 unsigned tess_inner_index, tess_outer_index;
2423 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2424 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2425 unsigned stride, outer_comps, inner_comps, i;
2426 struct lp_build_if_state if_ctx, inner_if_ctx;
2427
2428 si_llvm_emit_barrier(NULL, bld_base, NULL);
2429
2430 /* Do this only for invocation 0, because the tess levels are per-patch,
2431 * not per-vertex.
2432 *
2433 * This can't jump, because invocation 0 executes this. It should
2434 * at least mask out the loads and stores for other invocations.
2435 */
2436 lp_build_if(&if_ctx, gallivm,
2437 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2438 invocation_id, bld_base->uint_bld.zero, ""));
2439
2440 /* Determine the layout of one tess factor element in the buffer. */
2441 switch (shader->key.part.tcs.epilog.prim_mode) {
2442 case PIPE_PRIM_LINES:
2443 stride = 2; /* 2 dwords, 1 vec2 store */
2444 outer_comps = 2;
2445 inner_comps = 0;
2446 break;
2447 case PIPE_PRIM_TRIANGLES:
2448 stride = 4; /* 4 dwords, 1 vec4 store */
2449 outer_comps = 3;
2450 inner_comps = 1;
2451 break;
2452 case PIPE_PRIM_QUADS:
2453 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2454 outer_comps = 4;
2455 inner_comps = 2;
2456 break;
2457 default:
2458 assert(0);
2459 return;
2460 }
2461
2462 /* Load tess_inner and tess_outer from LDS.
2463 * Any invocation can write them, so we can't get them from a temporary.
2464 */
2465 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2466 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2467
2468 lds_base = tcs_out_current_patch_data_offset;
2469 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2470 lp_build_const_int32(gallivm,
2471 tess_inner_index * 4), "");
2472 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2473 lp_build_const_int32(gallivm,
2474 tess_outer_index * 4), "");
2475
2476 for (i = 0; i < 4; i++) {
2477 inner[i] = LLVMGetUndef(ctx->i32);
2478 outer[i] = LLVMGetUndef(ctx->i32);
2479 }
2480
2481 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2482 /* For isolines, the hardware expects tess factors in the
2483 * reverse order from what GLSL / TGSI specify.
2484 */
2485 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2486 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2487 } else {
2488 for (i = 0; i < outer_comps; i++) {
2489 outer[i] = out[i] =
2490 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2491 }
2492 for (i = 0; i < inner_comps; i++) {
2493 inner[i] = out[outer_comps+i] =
2494 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2495 }
2496 }
2497
2498 /* Convert the outputs to vectors for stores. */
2499 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2500 vec1 = NULL;
2501
2502 if (stride > 4)
2503 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2504
2505 /* Get the buffer. */
2506 rw_buffers = LLVMGetParam(ctx->main_fn,
2507 SI_PARAM_RW_BUFFERS);
2508 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2509 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2510
2511 /* Get the offset. */
2512 tf_base = LLVMGetParam(ctx->main_fn,
2513 SI_PARAM_TESS_FACTOR_OFFSET);
2514 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2515 lp_build_const_int32(gallivm, 4 * stride), "");
2516
2517 lp_build_if(&inner_if_ctx, gallivm,
2518 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2519 rel_patch_id, bld_base->uint_bld.zero, ""));
2520
2521 /* Store the dynamic HS control word. */
2522 ac_build_buffer_store_dword(&ctx->ac, buffer,
2523 lp_build_const_int32(gallivm, 0x80000000),
2524 1, lp_build_const_int32(gallivm, 0), tf_base,
2525 0, 1, 0, true, false);
2526
2527 lp_build_endif(&inner_if_ctx);
2528
2529 /* Store the tessellation factors. */
2530 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2531 MIN2(stride, 4), byteoffset, tf_base,
2532 4, 1, 0, true, false);
2533 if (vec1)
2534 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2535 stride - 4, byteoffset, tf_base,
2536 20, 1, 0, true, false);
2537
2538 /* Store the tess factors into the offchip buffer if TES reads them. */
2539 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2540 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2541 LLVMValueRef tf_inner_offset;
2542 unsigned param_outer, param_inner;
2543
2544 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2545 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2546 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2547
2548 param_outer = si_shader_io_get_unique_index(
2549 TGSI_SEMANTIC_TESSOUTER, 0);
2550 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2551 LLVMConstInt(ctx->i32, param_outer, 0));
2552
2553 outer_vec = lp_build_gather_values(gallivm, outer,
2554 util_next_power_of_two(outer_comps));
2555
2556 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2557 outer_comps, tf_outer_offset,
2558 base, 0, 1, 0, true, false);
2559 if (inner_comps) {
2560 param_inner = si_shader_io_get_unique_index(
2561 TGSI_SEMANTIC_TESSINNER, 0);
2562 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2563 LLVMConstInt(ctx->i32, param_inner, 0));
2564
2565 inner_vec = inner_comps == 1 ? inner[0] :
2566 lp_build_gather_values(gallivm, inner, inner_comps);
2567 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2568 inner_comps, tf_inner_offset,
2569 base, 0, 1, 0, true, false);
2570 }
2571 }
2572
2573 lp_build_endif(&if_ctx);
2574 }
2575
2576 /* This only writes the tessellation factor levels. */
2577 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2578 {
2579 struct si_shader_context *ctx = si_shader_context(bld_base);
2580 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2581 LLVMValueRef offchip_soffset, offchip_layout;
2582
2583 si_copy_tcs_inputs(bld_base);
2584
2585 rel_patch_id = get_rel_patch_id(ctx);
2586 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2587 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2588
2589 /* Return epilog parameters from this function. */
2590 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2591 LLVMValueRef ret = ctx->return_value;
2592 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2593 unsigned vgpr;
2594
2595 /* RW_BUFFERS pointer */
2596 rw_buffers = LLVMGetParam(ctx->main_fn,
2597 SI_PARAM_RW_BUFFERS);
2598 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2599 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2600 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2601 bld_base->uint_bld.zero, "");
2602 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2603 bld_base->uint_bld.one, "");
2604 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2605 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2606
2607 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2608 offchip_layout = LLVMGetParam(ctx->main_fn,
2609 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2610 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2611 tf_soffset = LLVMGetParam(ctx->main_fn,
2612 SI_PARAM_TESS_FACTOR_OFFSET);
2613 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2614 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2615 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2616 SI_TCS_NUM_USER_SGPR, "");
2617 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2618 SI_TCS_NUM_USER_SGPR + 1, "");
2619
2620 /* VGPRs */
2621 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2622 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2623 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2624
2625 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2626 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2627 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2628 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2629 ctx->return_value = ret;
2630 }
2631
2632 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2633 {
2634 struct si_shader_context *ctx = si_shader_context(bld_base);
2635 struct si_shader *shader = ctx->shader;
2636 struct tgsi_shader_info *info = &shader->selector->info;
2637 struct gallivm_state *gallivm = bld_base->base.gallivm;
2638 unsigned i, chan;
2639 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2640 ctx->param_rel_auto_id);
2641 LLVMValueRef vertex_dw_stride =
2642 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2643 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2644 vertex_dw_stride, "");
2645
2646 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2647 * its inputs from it. */
2648 for (i = 0; i < info->num_outputs; i++) {
2649 LLVMValueRef *out_ptr = ctx->outputs[i];
2650 unsigned name = info->output_semantic_name[i];
2651 unsigned index = info->output_semantic_index[i];
2652 int param = si_shader_io_get_unique_index(name, index);
2653 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2654 lp_build_const_int32(gallivm, param * 4), "");
2655
2656 for (chan = 0; chan < 4; chan++) {
2657 lds_store(bld_base, chan, dw_addr,
2658 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2659 }
2660 }
2661 }
2662
2663 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2664 {
2665 struct si_shader_context *ctx = si_shader_context(bld_base);
2666 struct gallivm_state *gallivm = bld_base->base.gallivm;
2667 struct si_shader *es = ctx->shader;
2668 struct tgsi_shader_info *info = &es->selector->info;
2669 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2670 ctx->param_es2gs_offset);
2671 unsigned chan;
2672 int i;
2673
2674 for (i = 0; i < info->num_outputs; i++) {
2675 LLVMValueRef *out_ptr = ctx->outputs[i];
2676 int param_index;
2677
2678 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2679 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2680 continue;
2681
2682 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2683 info->output_semantic_index[i]);
2684
2685 for (chan = 0; chan < 4; chan++) {
2686 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2687 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2688
2689 ac_build_buffer_store_dword(&ctx->ac,
2690 ctx->esgs_ring,
2691 out_val, 1, NULL, soffset,
2692 (4 * param_index + chan) * 4,
2693 1, 1, true, true);
2694 }
2695 }
2696 }
2697
2698 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2699 {
2700 struct si_shader_context *ctx = si_shader_context(bld_base);
2701
2702 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2703 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2704 }
2705
2706 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2707 {
2708 struct si_shader_context *ctx = si_shader_context(bld_base);
2709 struct gallivm_state *gallivm = bld_base->base.gallivm;
2710 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2711 struct si_shader_output_values *outputs = NULL;
2712 int i,j;
2713
2714 assert(!ctx->shader->is_gs_copy_shader);
2715
2716 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2717
2718 /* Vertex color clamping.
2719 *
2720 * This uses a state constant loaded in a user data SGPR and
2721 * an IF statement is added that clamps all colors if the constant
2722 * is true.
2723 */
2724 if (ctx->type == PIPE_SHADER_VERTEX) {
2725 struct lp_build_if_state if_ctx;
2726 LLVMValueRef cond = NULL;
2727 LLVMValueRef addr, val;
2728
2729 for (i = 0; i < info->num_outputs; i++) {
2730 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2731 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2732 continue;
2733
2734 /* We've found a color. */
2735 if (!cond) {
2736 /* The state is in the first bit of the user SGPR. */
2737 cond = LLVMGetParam(ctx->main_fn,
2738 SI_PARAM_VS_STATE_BITS);
2739 cond = LLVMBuildTrunc(gallivm->builder, cond,
2740 ctx->i1, "");
2741 lp_build_if(&if_ctx, gallivm, cond);
2742 }
2743
2744 for (j = 0; j < 4; j++) {
2745 addr = ctx->outputs[i][j];
2746 val = LLVMBuildLoad(gallivm->builder, addr, "");
2747 val = ac_build_clamp(&ctx->ac, val);
2748 LLVMBuildStore(gallivm->builder, val, addr);
2749 }
2750 }
2751
2752 if (cond)
2753 lp_build_endif(&if_ctx);
2754 }
2755
2756 for (i = 0; i < info->num_outputs; i++) {
2757 outputs[i].semantic_name = info->output_semantic_name[i];
2758 outputs[i].semantic_index = info->output_semantic_index[i];
2759
2760 for (j = 0; j < 4; j++) {
2761 outputs[i].values[j] =
2762 LLVMBuildLoad(gallivm->builder,
2763 ctx->outputs[i][j],
2764 "");
2765 outputs[i].vertex_stream[j] =
2766 (info->output_streams[i] >> (2 * j)) & 3;
2767 }
2768
2769 }
2770
2771 /* Return the primitive ID from the LLVM function. */
2772 ctx->return_value =
2773 LLVMBuildInsertValue(gallivm->builder,
2774 ctx->return_value,
2775 bitcast(bld_base, TGSI_TYPE_FLOAT,
2776 get_primitive_id(bld_base, 0)),
2777 VS_EPILOG_PRIMID_LOC, "");
2778
2779 if (ctx->shader->selector->so.num_outputs)
2780 si_llvm_emit_streamout(ctx, outputs, i, 0);
2781 si_llvm_export_vs(bld_base, outputs, i);
2782 FREE(outputs);
2783 }
2784
2785 struct si_ps_exports {
2786 unsigned num;
2787 struct ac_export_args args[10];
2788 };
2789
2790 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2791 bool writes_samplemask)
2792 {
2793 if (writes_z) {
2794 /* Z needs 32 bits. */
2795 if (writes_samplemask)
2796 return V_028710_SPI_SHADER_32_ABGR;
2797 else if (writes_stencil)
2798 return V_028710_SPI_SHADER_32_GR;
2799 else
2800 return V_028710_SPI_SHADER_32_R;
2801 } else if (writes_stencil || writes_samplemask) {
2802 /* Both stencil and sample mask need only 16 bits. */
2803 return V_028710_SPI_SHADER_UINT16_ABGR;
2804 } else {
2805 return V_028710_SPI_SHADER_ZERO;
2806 }
2807 }
2808
2809 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2810 LLVMValueRef depth, LLVMValueRef stencil,
2811 LLVMValueRef samplemask, struct si_ps_exports *exp)
2812 {
2813 struct si_shader_context *ctx = si_shader_context(bld_base);
2814 struct lp_build_context *base = &bld_base->base;
2815 struct ac_export_args args;
2816 unsigned mask = 0;
2817 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2818 stencil != NULL,
2819 samplemask != NULL);
2820
2821 assert(depth || stencil || samplemask);
2822
2823 args.valid_mask = 1; /* whether the EXEC mask is valid */
2824 args.done = 1; /* DONE bit */
2825
2826 /* Specify the target we are exporting */
2827 args.target = V_008DFC_SQ_EXP_MRTZ;
2828
2829 args.compr = 0; /* COMP flag */
2830 args.out[0] = base->undef; /* R, depth */
2831 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2832 args.out[2] = base->undef; /* B, sample mask */
2833 args.out[3] = base->undef; /* A, alpha to mask */
2834
2835 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2836 assert(!depth);
2837 args.compr = 1; /* COMPR flag */
2838
2839 if (stencil) {
2840 /* Stencil should be in X[23:16]. */
2841 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2842 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2843 LLVMConstInt(ctx->i32, 16, 0), "");
2844 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2845 mask |= 0x3;
2846 }
2847 if (samplemask) {
2848 /* SampleMask should be in Y[15:0]. */
2849 args.out[1] = samplemask;
2850 mask |= 0xc;
2851 }
2852 } else {
2853 if (depth) {
2854 args.out[0] = depth;
2855 mask |= 0x1;
2856 }
2857 if (stencil) {
2858 args.out[1] = stencil;
2859 mask |= 0x2;
2860 }
2861 if (samplemask) {
2862 args.out[2] = samplemask;
2863 mask |= 0x4;
2864 }
2865 }
2866
2867 /* SI (except OLAND and HAINAN) has a bug that it only looks
2868 * at the X writemask component. */
2869 if (ctx->screen->b.chip_class == SI &&
2870 ctx->screen->b.family != CHIP_OLAND &&
2871 ctx->screen->b.family != CHIP_HAINAN)
2872 mask |= 0x1;
2873
2874 /* Specify which components to enable */
2875 args.enabled_channels = mask;
2876
2877 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2878 }
2879
2880 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2881 LLVMValueRef *color, unsigned index,
2882 unsigned samplemask_param,
2883 bool is_last, struct si_ps_exports *exp)
2884 {
2885 struct si_shader_context *ctx = si_shader_context(bld_base);
2886 struct lp_build_context *base = &bld_base->base;
2887 int i;
2888
2889 /* Clamp color */
2890 if (ctx->shader->key.part.ps.epilog.clamp_color)
2891 for (i = 0; i < 4; i++)
2892 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2893
2894 /* Alpha to one */
2895 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2896 color[3] = base->one;
2897
2898 /* Alpha test */
2899 if (index == 0 &&
2900 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2901 si_alpha_test(bld_base, color[3]);
2902
2903 /* Line & polygon smoothing */
2904 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2905 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2906 samplemask_param);
2907
2908 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2909 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2910 struct ac_export_args args[8];
2911 int c, last = -1;
2912
2913 /* Get the export arguments, also find out what the last one is. */
2914 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2915 si_llvm_init_export_args(bld_base, color,
2916 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2917 if (args[c].enabled_channels)
2918 last = c;
2919 }
2920
2921 /* Emit all exports. */
2922 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2923 if (is_last && last == c) {
2924 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2925 args[c].done = 1; /* DONE bit */
2926 } else if (!args[c].enabled_channels)
2927 continue; /* unnecessary NULL export */
2928
2929 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2930 }
2931 } else {
2932 struct ac_export_args args;
2933
2934 /* Export */
2935 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2936 &args);
2937 if (is_last) {
2938 args.valid_mask = 1; /* whether the EXEC mask is valid */
2939 args.done = 1; /* DONE bit */
2940 } else if (!args.enabled_channels)
2941 return; /* unnecessary NULL export */
2942
2943 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2944 }
2945 }
2946
2947 static void si_emit_ps_exports(struct si_shader_context *ctx,
2948 struct si_ps_exports *exp)
2949 {
2950 for (unsigned i = 0; i < exp->num; i++)
2951 ac_build_export(&ctx->ac, &exp->args[i]);
2952 }
2953
2954 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2955 {
2956 struct si_shader_context *ctx = si_shader_context(bld_base);
2957 struct lp_build_context *base = &bld_base->base;
2958 struct ac_export_args args;
2959
2960 args.enabled_channels = 0x0; /* enabled channels */
2961 args.valid_mask = 1; /* whether the EXEC mask is valid */
2962 args.done = 1; /* DONE bit */
2963 args.target = V_008DFC_SQ_EXP_NULL;
2964 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
2965 args.out[0] = base->undef; /* R */
2966 args.out[1] = base->undef; /* G */
2967 args.out[2] = base->undef; /* B */
2968 args.out[3] = base->undef; /* A */
2969
2970 ac_build_export(&ctx->ac, &args);
2971 }
2972
2973 /**
2974 * Return PS outputs in this order:
2975 *
2976 * v[0:3] = color0.xyzw
2977 * v[4:7] = color1.xyzw
2978 * ...
2979 * vN+0 = Depth
2980 * vN+1 = Stencil
2981 * vN+2 = SampleMask
2982 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2983 *
2984 * The alpha-ref SGPR is returned via its original location.
2985 */
2986 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2987 {
2988 struct si_shader_context *ctx = si_shader_context(bld_base);
2989 struct si_shader *shader = ctx->shader;
2990 struct lp_build_context *base = &bld_base->base;
2991 struct tgsi_shader_info *info = &shader->selector->info;
2992 LLVMBuilderRef builder = base->gallivm->builder;
2993 unsigned i, j, first_vgpr, vgpr;
2994
2995 LLVMValueRef color[8][4] = {};
2996 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2997 LLVMValueRef ret;
2998
2999 /* Read the output values. */
3000 for (i = 0; i < info->num_outputs; i++) {
3001 unsigned semantic_name = info->output_semantic_name[i];
3002 unsigned semantic_index = info->output_semantic_index[i];
3003
3004 switch (semantic_name) {
3005 case TGSI_SEMANTIC_COLOR:
3006 assert(semantic_index < 8);
3007 for (j = 0; j < 4; j++) {
3008 LLVMValueRef ptr = ctx->outputs[i][j];
3009 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3010 color[semantic_index][j] = result;
3011 }
3012 break;
3013 case TGSI_SEMANTIC_POSITION:
3014 depth = LLVMBuildLoad(builder,
3015 ctx->outputs[i][2], "");
3016 break;
3017 case TGSI_SEMANTIC_STENCIL:
3018 stencil = LLVMBuildLoad(builder,
3019 ctx->outputs[i][1], "");
3020 break;
3021 case TGSI_SEMANTIC_SAMPLEMASK:
3022 samplemask = LLVMBuildLoad(builder,
3023 ctx->outputs[i][0], "");
3024 break;
3025 default:
3026 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3027 semantic_name);
3028 }
3029 }
3030
3031 /* Fill the return structure. */
3032 ret = ctx->return_value;
3033
3034 /* Set SGPRs. */
3035 ret = LLVMBuildInsertValue(builder, ret,
3036 bitcast(bld_base, TGSI_TYPE_SIGNED,
3037 LLVMGetParam(ctx->main_fn,
3038 SI_PARAM_ALPHA_REF)),
3039 SI_SGPR_ALPHA_REF, "");
3040
3041 /* Set VGPRs */
3042 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3043 for (i = 0; i < ARRAY_SIZE(color); i++) {
3044 if (!color[i][0])
3045 continue;
3046
3047 for (j = 0; j < 4; j++)
3048 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3049 }
3050 if (depth)
3051 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3052 if (stencil)
3053 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3054 if (samplemask)
3055 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3056
3057 /* Add the input sample mask for smoothing at the end. */
3058 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3059 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3060 ret = LLVMBuildInsertValue(builder, ret,
3061 LLVMGetParam(ctx->main_fn,
3062 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3063
3064 ctx->return_value = ret;
3065 }
3066
3067 /**
3068 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3069 * buffer in number of elements and return it as an i32.
3070 */
3071 static LLVMValueRef get_buffer_size(
3072 struct lp_build_tgsi_context *bld_base,
3073 LLVMValueRef descriptor)
3074 {
3075 struct si_shader_context *ctx = si_shader_context(bld_base);
3076 struct gallivm_state *gallivm = bld_base->base.gallivm;
3077 LLVMBuilderRef builder = gallivm->builder;
3078 LLVMValueRef size =
3079 LLVMBuildExtractElement(builder, descriptor,
3080 lp_build_const_int32(gallivm, 2), "");
3081
3082 if (ctx->screen->b.chip_class >= VI) {
3083 /* On VI, the descriptor contains the size in bytes,
3084 * but TXQ must return the size in elements.
3085 * The stride is always non-zero for resources using TXQ.
3086 */
3087 LLVMValueRef stride =
3088 LLVMBuildExtractElement(builder, descriptor,
3089 lp_build_const_int32(gallivm, 1), "");
3090 stride = LLVMBuildLShr(builder, stride,
3091 lp_build_const_int32(gallivm, 16), "");
3092 stride = LLVMBuildAnd(builder, stride,
3093 lp_build_const_int32(gallivm, 0x3FFF), "");
3094
3095 size = LLVMBuildUDiv(builder, size, stride, "");
3096 }
3097
3098 return size;
3099 }
3100
3101 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3102 struct lp_build_tgsi_context *bld_base,
3103 struct lp_build_emit_data *emit_data);
3104
3105 /* Prevent optimizations (at least of memory accesses) across the current
3106 * point in the program by emitting empty inline assembly that is marked as
3107 * having side effects.
3108 */
3109 #if 0 /* unused currently */
3110 static void emit_optimization_barrier(struct si_shader_context *ctx)
3111 {
3112 LLVMBuilderRef builder = ctx->gallivm.builder;
3113 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3114 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3115 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3116 }
3117 #endif
3118
3119 /* Combine these with & instead of |. */
3120 #define NOOP_WAITCNT 0xf7f
3121 #define LGKM_CNT 0x07f
3122 #define VM_CNT 0xf70
3123
3124 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3125 {
3126 struct gallivm_state *gallivm = &ctx->gallivm;
3127 LLVMBuilderRef builder = gallivm->builder;
3128 LLVMValueRef args[1] = {
3129 lp_build_const_int32(gallivm, simm16)
3130 };
3131 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3132 ctx->voidt, args, 1, 0);
3133 }
3134
3135 static void membar_emit(
3136 const struct lp_build_tgsi_action *action,
3137 struct lp_build_tgsi_context *bld_base,
3138 struct lp_build_emit_data *emit_data)
3139 {
3140 struct si_shader_context *ctx = si_shader_context(bld_base);
3141 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3142 unsigned flags = LLVMConstIntGetZExtValue(src0);
3143 unsigned waitcnt = NOOP_WAITCNT;
3144
3145 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3146 waitcnt &= VM_CNT & LGKM_CNT;
3147
3148 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3149 TGSI_MEMBAR_SHADER_BUFFER |
3150 TGSI_MEMBAR_SHADER_IMAGE))
3151 waitcnt &= VM_CNT;
3152
3153 if (flags & TGSI_MEMBAR_SHARED)
3154 waitcnt &= LGKM_CNT;
3155
3156 if (waitcnt != NOOP_WAITCNT)
3157 emit_waitcnt(ctx, waitcnt);
3158 }
3159
3160 static LLVMValueRef
3161 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3162 const struct tgsi_full_src_register *reg)
3163 {
3164 LLVMValueRef index;
3165 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3166 SI_PARAM_SHADER_BUFFERS);
3167
3168 if (!reg->Register.Indirect)
3169 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3170 else
3171 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3172 reg->Register.Index,
3173 SI_NUM_SHADER_BUFFERS);
3174
3175 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3176 }
3177
3178 static bool tgsi_is_array_sampler(unsigned target)
3179 {
3180 return target == TGSI_TEXTURE_1D_ARRAY ||
3181 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3182 target == TGSI_TEXTURE_2D_ARRAY ||
3183 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3184 target == TGSI_TEXTURE_CUBE_ARRAY ||
3185 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3186 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3187 }
3188
3189 static bool tgsi_is_array_image(unsigned target)
3190 {
3191 return target == TGSI_TEXTURE_3D ||
3192 target == TGSI_TEXTURE_CUBE ||
3193 target == TGSI_TEXTURE_1D_ARRAY ||
3194 target == TGSI_TEXTURE_2D_ARRAY ||
3195 target == TGSI_TEXTURE_CUBE_ARRAY ||
3196 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3197 }
3198
3199 /**
3200 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3201 *
3202 * At least on Tonga, executing image stores on images with DCC enabled and
3203 * non-trivial can eventually lead to lockups. This can occur when an
3204 * application binds an image as read-only but then uses a shader that writes
3205 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3206 * program termination) in this case, but it doesn't cost much to be a bit
3207 * nicer: disabling DCC in the shader still leads to undefined results but
3208 * avoids the lockup.
3209 */
3210 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3211 LLVMValueRef rsrc)
3212 {
3213 if (ctx->screen->b.chip_class <= CIK) {
3214 return rsrc;
3215 } else {
3216 LLVMBuilderRef builder = ctx->gallivm.builder;
3217 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3218 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3219 LLVMValueRef tmp;
3220
3221 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3222 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3223 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3224 }
3225 }
3226
3227 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3228 {
3229 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3230 CONST_ADDR_SPACE);
3231 }
3232
3233 /**
3234 * Load the resource descriptor for \p image.
3235 */
3236 static void
3237 image_fetch_rsrc(
3238 struct lp_build_tgsi_context *bld_base,
3239 const struct tgsi_full_src_register *image,
3240 bool is_store, unsigned target,
3241 LLVMValueRef *rsrc)
3242 {
3243 struct si_shader_context *ctx = si_shader_context(bld_base);
3244 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3245 SI_PARAM_IMAGES);
3246 LLVMValueRef index, tmp;
3247 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3248
3249 assert(image->Register.File == TGSI_FILE_IMAGE);
3250
3251 if (!image->Register.Indirect) {
3252 const struct tgsi_shader_info *info = bld_base->info;
3253 unsigned images_writemask = info->images_store |
3254 info->images_atomic;
3255
3256 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3257
3258 if (images_writemask & (1 << image->Register.Index) &&
3259 target != TGSI_TEXTURE_BUFFER)
3260 dcc_off = true;
3261 } else {
3262 /* From the GL_ARB_shader_image_load_store extension spec:
3263 *
3264 * If a shader performs an image load, store, or atomic
3265 * operation using an image variable declared as an array,
3266 * and if the index used to select an individual element is
3267 * negative or greater than or equal to the size of the
3268 * array, the results of the operation are undefined but may
3269 * not lead to termination.
3270 */
3271 index = get_bounded_indirect_index(ctx, &image->Indirect,
3272 image->Register.Index,
3273 SI_NUM_IMAGES);
3274 }
3275
3276 if (target == TGSI_TEXTURE_BUFFER) {
3277 LLVMBuilderRef builder = ctx->gallivm.builder;
3278
3279 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3280 const_array(ctx->v4i32, 0), "");
3281 index = LLVMBuildMul(builder, index,
3282 LLVMConstInt(ctx->i32, 2, 0), "");
3283 index = LLVMBuildAdd(builder, index,
3284 LLVMConstInt(ctx->i32, 1, 0), "");
3285 *rsrc = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3286 return;
3287 }
3288
3289 tmp = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3290 if (dcc_off)
3291 tmp = force_dcc_off(ctx, tmp);
3292 *rsrc = tmp;
3293 }
3294
3295 static LLVMValueRef image_fetch_coords(
3296 struct lp_build_tgsi_context *bld_base,
3297 const struct tgsi_full_instruction *inst,
3298 unsigned src)
3299 {
3300 struct gallivm_state *gallivm = bld_base->base.gallivm;
3301 LLVMBuilderRef builder = gallivm->builder;
3302 unsigned target = inst->Memory.Texture;
3303 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3304 LLVMValueRef coords[4];
3305 LLVMValueRef tmp;
3306 int chan;
3307
3308 for (chan = 0; chan < num_coords; ++chan) {
3309 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3310 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3311 coords[chan] = tmp;
3312 }
3313
3314 if (num_coords == 1)
3315 return coords[0];
3316
3317 if (num_coords == 3) {
3318 /* LLVM has difficulties lowering 3-element vectors. */
3319 coords[3] = bld_base->uint_bld.undef;
3320 num_coords = 4;
3321 }
3322
3323 return lp_build_gather_values(gallivm, coords, num_coords);
3324 }
3325
3326 /**
3327 * Append the extra mode bits that are used by image load and store.
3328 */
3329 static void image_append_args(
3330 struct si_shader_context *ctx,
3331 struct lp_build_emit_data * emit_data,
3332 unsigned target,
3333 bool atomic,
3334 bool force_glc)
3335 {
3336 const struct tgsi_full_instruction *inst = emit_data->inst;
3337 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3338 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3339 LLVMValueRef r128 = i1false;
3340 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3341 LLVMValueRef glc =
3342 force_glc ||
3343 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3344 i1true : i1false;
3345 LLVMValueRef slc = i1false;
3346 LLVMValueRef lwe = i1false;
3347
3348 if (atomic || (HAVE_LLVM <= 0x0309)) {
3349 emit_data->args[emit_data->arg_count++] = r128;
3350 emit_data->args[emit_data->arg_count++] = da;
3351 if (!atomic) {
3352 emit_data->args[emit_data->arg_count++] = glc;
3353 }
3354 emit_data->args[emit_data->arg_count++] = slc;
3355 return;
3356 }
3357
3358 /* HAVE_LLVM >= 0x0400 */
3359 emit_data->args[emit_data->arg_count++] = glc;
3360 emit_data->args[emit_data->arg_count++] = slc;
3361 emit_data->args[emit_data->arg_count++] = lwe;
3362 emit_data->args[emit_data->arg_count++] = da;
3363 }
3364
3365 /**
3366 * Append the resource and indexing arguments for buffer intrinsics.
3367 *
3368 * \param rsrc the v4i32 buffer resource
3369 * \param index index into the buffer (stride-based)
3370 * \param offset byte offset into the buffer
3371 */
3372 static void buffer_append_args(
3373 struct si_shader_context *ctx,
3374 struct lp_build_emit_data *emit_data,
3375 LLVMValueRef rsrc,
3376 LLVMValueRef index,
3377 LLVMValueRef offset,
3378 bool atomic,
3379 bool force_glc)
3380 {
3381 const struct tgsi_full_instruction *inst = emit_data->inst;
3382 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3383 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3384
3385 emit_data->args[emit_data->arg_count++] = rsrc;
3386 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3387 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3388 if (!atomic) {
3389 emit_data->args[emit_data->arg_count++] =
3390 force_glc ||
3391 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3392 i1true : i1false; /* glc */
3393 }
3394 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3395 }
3396
3397 static void load_fetch_args(
3398 struct lp_build_tgsi_context * bld_base,
3399 struct lp_build_emit_data * emit_data)
3400 {
3401 struct si_shader_context *ctx = si_shader_context(bld_base);
3402 struct gallivm_state *gallivm = bld_base->base.gallivm;
3403 const struct tgsi_full_instruction * inst = emit_data->inst;
3404 unsigned target = inst->Memory.Texture;
3405 LLVMValueRef rsrc;
3406
3407 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3408
3409 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3410 LLVMBuilderRef builder = gallivm->builder;
3411 LLVMValueRef offset;
3412 LLVMValueRef tmp;
3413
3414 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3415
3416 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3417 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3418
3419 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3420 offset, false, false);
3421 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3422 LLVMValueRef coords;
3423
3424 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3425 coords = image_fetch_coords(bld_base, inst, 1);
3426
3427 if (target == TGSI_TEXTURE_BUFFER) {
3428 buffer_append_args(ctx, emit_data, rsrc, coords,
3429 bld_base->uint_bld.zero, false, false);
3430 } else {
3431 emit_data->args[0] = coords;
3432 emit_data->args[1] = rsrc;
3433 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3434 emit_data->arg_count = 3;
3435
3436 image_append_args(ctx, emit_data, target, false, false);
3437 }
3438 }
3439 }
3440
3441 static unsigned get_load_intr_attribs(bool readonly_memory)
3442 {
3443 /* READNONE means writes can't affect it, while READONLY means that
3444 * writes can affect it. */
3445 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3446 LP_FUNC_ATTR_READNONE :
3447 LP_FUNC_ATTR_READONLY;
3448 }
3449
3450 static unsigned get_store_intr_attribs(bool writeonly_memory)
3451 {
3452 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3453 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3454 LP_FUNC_ATTR_WRITEONLY;
3455 }
3456
3457 static void load_emit_buffer(struct si_shader_context *ctx,
3458 struct lp_build_emit_data *emit_data,
3459 bool readonly_memory)
3460 {
3461 const struct tgsi_full_instruction *inst = emit_data->inst;
3462 struct gallivm_state *gallivm = &ctx->gallivm;
3463 LLVMBuilderRef builder = gallivm->builder;
3464 uint writemask = inst->Dst[0].Register.WriteMask;
3465 uint count = util_last_bit(writemask);
3466 const char *intrinsic_name;
3467 LLVMTypeRef dst_type;
3468
3469 switch (count) {
3470 case 1:
3471 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3472 dst_type = ctx->f32;
3473 break;
3474 case 2:
3475 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3476 dst_type = LLVMVectorType(ctx->f32, 2);
3477 break;
3478 default: // 3 & 4
3479 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3480 dst_type = ctx->v4f32;
3481 count = 4;
3482 }
3483
3484 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3485 builder, intrinsic_name, dst_type,
3486 emit_data->args, emit_data->arg_count,
3487 get_load_intr_attribs(readonly_memory));
3488 }
3489
3490 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3491 const struct tgsi_full_instruction *inst,
3492 LLVMTypeRef type, int arg)
3493 {
3494 struct gallivm_state *gallivm = &ctx->gallivm;
3495 LLVMBuilderRef builder = gallivm->builder;
3496 LLVMValueRef offset, ptr;
3497 int addr_space;
3498
3499 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3500 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3501
3502 ptr = ctx->shared_memory;
3503 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3504 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3505 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3506
3507 return ptr;
3508 }
3509
3510 static void load_emit_memory(
3511 struct si_shader_context *ctx,
3512 struct lp_build_emit_data *emit_data)
3513 {
3514 const struct tgsi_full_instruction *inst = emit_data->inst;
3515 struct lp_build_context *base = &ctx->bld_base.base;
3516 struct gallivm_state *gallivm = &ctx->gallivm;
3517 LLVMBuilderRef builder = gallivm->builder;
3518 unsigned writemask = inst->Dst[0].Register.WriteMask;
3519 LLVMValueRef channels[4], ptr, derived_ptr, index;
3520 int chan;
3521
3522 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3523
3524 for (chan = 0; chan < 4; ++chan) {
3525 if (!(writemask & (1 << chan))) {
3526 channels[chan] = LLVMGetUndef(base->elem_type);
3527 continue;
3528 }
3529
3530 index = lp_build_const_int32(gallivm, chan);
3531 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3532 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3533 }
3534 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3535 }
3536
3537 static void get_image_intr_name(const char *base_name,
3538 LLVMTypeRef data_type,
3539 LLVMTypeRef coords_type,
3540 LLVMTypeRef rsrc_type,
3541 char *out_name, unsigned out_len)
3542 {
3543 char coords_type_name[8];
3544
3545 ac_build_type_name_for_intr(coords_type, coords_type_name,
3546 sizeof(coords_type_name));
3547
3548 if (HAVE_LLVM <= 0x0309) {
3549 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3550 } else {
3551 char data_type_name[8];
3552 char rsrc_type_name[8];
3553
3554 ac_build_type_name_for_intr(data_type, data_type_name,
3555 sizeof(data_type_name));
3556 ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
3557 sizeof(rsrc_type_name));
3558 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3559 data_type_name, coords_type_name, rsrc_type_name);
3560 }
3561 }
3562
3563 /**
3564 * Return true if the memory accessed by a LOAD or STORE instruction is
3565 * read-only or write-only, respectively.
3566 *
3567 * \param shader_buffers_reverse_access_mask
3568 * For LOAD, set this to (store | atomic) slot usage in the shader.
3569 * For STORE, set this to (load | atomic) slot usage in the shader.
3570 * \param images_reverse_access_mask Same as above, but for images.
3571 */
3572 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3573 const struct tgsi_shader_info *info,
3574 unsigned shader_buffers_reverse_access_mask,
3575 unsigned images_reverse_access_mask)
3576 {
3577 /* RESTRICT means NOALIAS.
3578 * If there are no writes, we can assume the accessed memory is read-only.
3579 * If there are no reads, we can assume the accessed memory is write-only.
3580 */
3581 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3582 unsigned reverse_access_mask;
3583
3584 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3585 reverse_access_mask = shader_buffers_reverse_access_mask;
3586 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3587 reverse_access_mask = info->images_buffers &
3588 images_reverse_access_mask;
3589 } else {
3590 reverse_access_mask = ~info->images_buffers &
3591 images_reverse_access_mask;
3592 }
3593
3594 if (inst->Src[0].Register.Indirect) {
3595 if (!reverse_access_mask)
3596 return true;
3597 } else {
3598 if (!(reverse_access_mask &
3599 (1u << inst->Src[0].Register.Index)))
3600 return true;
3601 }
3602 }
3603
3604 /* If there are no buffer writes (for both shader buffers & image
3605 * buffers), it implies that buffer memory is read-only.
3606 * If there are no buffer reads (for both shader buffers & image
3607 * buffers), it implies that buffer memory is write-only.
3608 *
3609 * Same for the case when there are no writes/reads for non-buffer
3610 * images.
3611 */
3612 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3613 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3614 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3615 if (!shader_buffers_reverse_access_mask &&
3616 !(info->images_buffers & images_reverse_access_mask))
3617 return true;
3618 } else {
3619 if (!(~info->images_buffers & images_reverse_access_mask))
3620 return true;
3621 }
3622 return false;
3623 }
3624
3625 static void load_emit(
3626 const struct lp_build_tgsi_action *action,
3627 struct lp_build_tgsi_context *bld_base,
3628 struct lp_build_emit_data *emit_data)
3629 {
3630 struct si_shader_context *ctx = si_shader_context(bld_base);
3631 struct gallivm_state *gallivm = bld_base->base.gallivm;
3632 LLVMBuilderRef builder = gallivm->builder;
3633 const struct tgsi_full_instruction * inst = emit_data->inst;
3634 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3635 char intrinsic_name[64];
3636 bool readonly_memory = false;
3637
3638 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3639 load_emit_memory(ctx, emit_data);
3640 return;
3641 }
3642
3643 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3644 emit_waitcnt(ctx, VM_CNT);
3645
3646 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3647 is_oneway_access_only(inst, info,
3648 info->shader_buffers_store |
3649 info->shader_buffers_atomic,
3650 info->images_store |
3651 info->images_atomic);
3652
3653 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3654 load_emit_buffer(ctx, emit_data, readonly_memory);
3655 return;
3656 }
3657
3658 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3659 emit_data->output[emit_data->chan] =
3660 lp_build_intrinsic(
3661 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3662 emit_data->args, emit_data->arg_count,
3663 get_load_intr_attribs(readonly_memory));
3664 } else {
3665 get_image_intr_name("llvm.amdgcn.image.load",
3666 emit_data->dst_type, /* vdata */
3667 LLVMTypeOf(emit_data->args[0]), /* coords */
3668 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3669 intrinsic_name, sizeof(intrinsic_name));
3670
3671 emit_data->output[emit_data->chan] =
3672 lp_build_intrinsic(
3673 builder, intrinsic_name, emit_data->dst_type,
3674 emit_data->args, emit_data->arg_count,
3675 get_load_intr_attribs(readonly_memory));
3676 }
3677 }
3678
3679 static void store_fetch_args(
3680 struct lp_build_tgsi_context * bld_base,
3681 struct lp_build_emit_data * emit_data)
3682 {
3683 struct si_shader_context *ctx = si_shader_context(bld_base);
3684 struct gallivm_state *gallivm = bld_base->base.gallivm;
3685 LLVMBuilderRef builder = gallivm->builder;
3686 const struct tgsi_full_instruction * inst = emit_data->inst;
3687 struct tgsi_full_src_register memory;
3688 LLVMValueRef chans[4];
3689 LLVMValueRef data;
3690 LLVMValueRef rsrc;
3691 unsigned chan;
3692
3693 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3694
3695 for (chan = 0; chan < 4; ++chan) {
3696 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3697 }
3698 data = lp_build_gather_values(gallivm, chans, 4);
3699
3700 emit_data->args[emit_data->arg_count++] = data;
3701
3702 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3703
3704 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3705 LLVMValueRef offset;
3706 LLVMValueRef tmp;
3707
3708 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3709
3710 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3711 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3712
3713 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3714 offset, false, false);
3715 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3716 unsigned target = inst->Memory.Texture;
3717 LLVMValueRef coords;
3718
3719 /* 8bit/16bit TC L1 write corruption bug on SI.
3720 * All store opcodes not aligned to a dword are affected.
3721 *
3722 * The only way to get unaligned stores in radeonsi is through
3723 * shader images.
3724 */
3725 bool force_glc = ctx->screen->b.chip_class == SI;
3726
3727 coords = image_fetch_coords(bld_base, inst, 0);
3728
3729 if (target == TGSI_TEXTURE_BUFFER) {
3730 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3731 buffer_append_args(ctx, emit_data, rsrc, coords,
3732 bld_base->uint_bld.zero, false, force_glc);
3733 } else {
3734 emit_data->args[1] = coords;
3735 image_fetch_rsrc(bld_base, &memory, true, target,
3736 &emit_data->args[2]);
3737 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3738 emit_data->arg_count = 4;
3739
3740 image_append_args(ctx, emit_data, target, false, force_glc);
3741 }
3742 }
3743 }
3744
3745 static void store_emit_buffer(
3746 struct si_shader_context *ctx,
3747 struct lp_build_emit_data *emit_data,
3748 bool writeonly_memory)
3749 {
3750 const struct tgsi_full_instruction *inst = emit_data->inst;
3751 struct gallivm_state *gallivm = &ctx->gallivm;
3752 LLVMBuilderRef builder = gallivm->builder;
3753 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
3754 LLVMValueRef base_data = emit_data->args[0];
3755 LLVMValueRef base_offset = emit_data->args[3];
3756 unsigned writemask = inst->Dst[0].Register.WriteMask;
3757
3758 while (writemask) {
3759 int start, count;
3760 const char *intrinsic_name;
3761 LLVMValueRef data;
3762 LLVMValueRef offset;
3763 LLVMValueRef tmp;
3764
3765 u_bit_scan_consecutive_range(&writemask, &start, &count);
3766
3767 /* Due to an LLVM limitation, split 3-element writes
3768 * into a 2-element and a 1-element write. */
3769 if (count == 3) {
3770 writemask |= 1 << (start + 2);
3771 count = 2;
3772 }
3773
3774 if (count == 4) {
3775 data = base_data;
3776 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3777 } else if (count == 2) {
3778 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3779
3780 tmp = LLVMBuildExtractElement(
3781 builder, base_data,
3782 lp_build_const_int32(gallivm, start), "");
3783 data = LLVMBuildInsertElement(
3784 builder, LLVMGetUndef(v2f32), tmp,
3785 uint_bld->zero, "");
3786
3787 tmp = LLVMBuildExtractElement(
3788 builder, base_data,
3789 lp_build_const_int32(gallivm, start + 1), "");
3790 data = LLVMBuildInsertElement(
3791 builder, data, tmp, uint_bld->one, "");
3792
3793 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3794 } else {
3795 assert(count == 1);
3796 data = LLVMBuildExtractElement(
3797 builder, base_data,
3798 lp_build_const_int32(gallivm, start), "");
3799 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3800 }
3801
3802 offset = base_offset;
3803 if (start != 0) {
3804 offset = LLVMBuildAdd(
3805 builder, offset,
3806 lp_build_const_int32(gallivm, start * 4), "");
3807 }
3808
3809 emit_data->args[0] = data;
3810 emit_data->args[3] = offset;
3811
3812 lp_build_intrinsic(
3813 builder, intrinsic_name, emit_data->dst_type,
3814 emit_data->args, emit_data->arg_count,
3815 get_store_intr_attribs(writeonly_memory));
3816 }
3817 }
3818
3819 static void store_emit_memory(
3820 struct si_shader_context *ctx,
3821 struct lp_build_emit_data *emit_data)
3822 {
3823 const struct tgsi_full_instruction *inst = emit_data->inst;
3824 struct gallivm_state *gallivm = &ctx->gallivm;
3825 struct lp_build_context *base = &ctx->bld_base.base;
3826 LLVMBuilderRef builder = gallivm->builder;
3827 unsigned writemask = inst->Dst[0].Register.WriteMask;
3828 LLVMValueRef ptr, derived_ptr, data, index;
3829 int chan;
3830
3831 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3832
3833 for (chan = 0; chan < 4; ++chan) {
3834 if (!(writemask & (1 << chan))) {
3835 continue;
3836 }
3837 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3838 index = lp_build_const_int32(gallivm, chan);
3839 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3840 LLVMBuildStore(builder, data, derived_ptr);
3841 }
3842 }
3843
3844 static void store_emit(
3845 const struct lp_build_tgsi_action *action,
3846 struct lp_build_tgsi_context *bld_base,
3847 struct lp_build_emit_data *emit_data)
3848 {
3849 struct si_shader_context *ctx = si_shader_context(bld_base);
3850 struct gallivm_state *gallivm = bld_base->base.gallivm;
3851 LLVMBuilderRef builder = gallivm->builder;
3852 const struct tgsi_full_instruction * inst = emit_data->inst;
3853 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3854 unsigned target = inst->Memory.Texture;
3855 char intrinsic_name[64];
3856 bool writeonly_memory = false;
3857
3858 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3859 store_emit_memory(ctx, emit_data);
3860 return;
3861 }
3862
3863 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3864 emit_waitcnt(ctx, VM_CNT);
3865
3866 writeonly_memory = is_oneway_access_only(inst, info,
3867 info->shader_buffers_load |
3868 info->shader_buffers_atomic,
3869 info->images_load |
3870 info->images_atomic);
3871
3872 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3873 store_emit_buffer(ctx, emit_data, writeonly_memory);
3874 return;
3875 }
3876
3877 if (target == TGSI_TEXTURE_BUFFER) {
3878 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3879 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3880 emit_data->dst_type, emit_data->args,
3881 emit_data->arg_count,
3882 get_store_intr_attribs(writeonly_memory));
3883 } else {
3884 get_image_intr_name("llvm.amdgcn.image.store",
3885 LLVMTypeOf(emit_data->args[0]), /* vdata */
3886 LLVMTypeOf(emit_data->args[1]), /* coords */
3887 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3888 intrinsic_name, sizeof(intrinsic_name));
3889
3890 emit_data->output[emit_data->chan] =
3891 lp_build_intrinsic(
3892 builder, intrinsic_name, emit_data->dst_type,
3893 emit_data->args, emit_data->arg_count,
3894 get_store_intr_attribs(writeonly_memory));
3895 }
3896 }
3897
3898 static void atomic_fetch_args(
3899 struct lp_build_tgsi_context * bld_base,
3900 struct lp_build_emit_data * emit_data)
3901 {
3902 struct si_shader_context *ctx = si_shader_context(bld_base);
3903 struct gallivm_state *gallivm = bld_base->base.gallivm;
3904 LLVMBuilderRef builder = gallivm->builder;
3905 const struct tgsi_full_instruction * inst = emit_data->inst;
3906 LLVMValueRef data1, data2;
3907 LLVMValueRef rsrc;
3908 LLVMValueRef tmp;
3909
3910 emit_data->dst_type = bld_base->base.elem_type;
3911
3912 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3913 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3914
3915 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3916 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3917 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3918 }
3919
3920 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3921 * of arguments, which is reversed relative to TGSI (and GLSL)
3922 */
3923 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3924 emit_data->args[emit_data->arg_count++] = data2;
3925 emit_data->args[emit_data->arg_count++] = data1;
3926
3927 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3928 LLVMValueRef offset;
3929
3930 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3931
3932 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3933 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3934
3935 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3936 offset, true, false);
3937 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3938 unsigned target = inst->Memory.Texture;
3939 LLVMValueRef coords;
3940
3941 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3942 coords = image_fetch_coords(bld_base, inst, 1);
3943
3944 if (target == TGSI_TEXTURE_BUFFER) {
3945 buffer_append_args(ctx, emit_data, rsrc, coords,
3946 bld_base->uint_bld.zero, true, false);
3947 } else {
3948 emit_data->args[emit_data->arg_count++] = coords;
3949 emit_data->args[emit_data->arg_count++] = rsrc;
3950
3951 image_append_args(ctx, emit_data, target, true, false);
3952 }
3953 }
3954 }
3955
3956 static void atomic_emit_memory(struct si_shader_context *ctx,
3957 struct lp_build_emit_data *emit_data) {
3958 struct gallivm_state *gallivm = &ctx->gallivm;
3959 LLVMBuilderRef builder = gallivm->builder;
3960 const struct tgsi_full_instruction * inst = emit_data->inst;
3961 LLVMValueRef ptr, result, arg;
3962
3963 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3964
3965 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
3966 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3967
3968 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3969 LLVMValueRef new_data;
3970 new_data = lp_build_emit_fetch(&ctx->bld_base,
3971 inst, 3, 0);
3972
3973 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3974
3975 #if HAVE_LLVM >= 0x309
3976 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3977 LLVMAtomicOrderingSequentiallyConsistent,
3978 LLVMAtomicOrderingSequentiallyConsistent,
3979 false);
3980 #endif
3981
3982 result = LLVMBuildExtractValue(builder, result, 0, "");
3983 } else {
3984 LLVMAtomicRMWBinOp op;
3985
3986 switch(inst->Instruction.Opcode) {
3987 case TGSI_OPCODE_ATOMUADD:
3988 op = LLVMAtomicRMWBinOpAdd;
3989 break;
3990 case TGSI_OPCODE_ATOMXCHG:
3991 op = LLVMAtomicRMWBinOpXchg;
3992 break;
3993 case TGSI_OPCODE_ATOMAND:
3994 op = LLVMAtomicRMWBinOpAnd;
3995 break;
3996 case TGSI_OPCODE_ATOMOR:
3997 op = LLVMAtomicRMWBinOpOr;
3998 break;
3999 case TGSI_OPCODE_ATOMXOR:
4000 op = LLVMAtomicRMWBinOpXor;
4001 break;
4002 case TGSI_OPCODE_ATOMUMIN:
4003 op = LLVMAtomicRMWBinOpUMin;
4004 break;
4005 case TGSI_OPCODE_ATOMUMAX:
4006 op = LLVMAtomicRMWBinOpUMax;
4007 break;
4008 case TGSI_OPCODE_ATOMIMIN:
4009 op = LLVMAtomicRMWBinOpMin;
4010 break;
4011 case TGSI_OPCODE_ATOMIMAX:
4012 op = LLVMAtomicRMWBinOpMax;
4013 break;
4014 default:
4015 unreachable("unknown atomic opcode");
4016 }
4017
4018 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4019 LLVMAtomicOrderingSequentiallyConsistent,
4020 false);
4021 }
4022 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4023 }
4024
4025 static void atomic_emit(
4026 const struct lp_build_tgsi_action *action,
4027 struct lp_build_tgsi_context *bld_base,
4028 struct lp_build_emit_data *emit_data)
4029 {
4030 struct si_shader_context *ctx = si_shader_context(bld_base);
4031 struct gallivm_state *gallivm = bld_base->base.gallivm;
4032 LLVMBuilderRef builder = gallivm->builder;
4033 const struct tgsi_full_instruction * inst = emit_data->inst;
4034 char intrinsic_name[40];
4035 LLVMValueRef tmp;
4036
4037 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4038 atomic_emit_memory(ctx, emit_data);
4039 return;
4040 }
4041
4042 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4043 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4044 snprintf(intrinsic_name, sizeof(intrinsic_name),
4045 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4046 } else {
4047 LLVMValueRef coords;
4048 char coords_type[8];
4049
4050 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4051 coords = emit_data->args[2];
4052 else
4053 coords = emit_data->args[1];
4054
4055 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4056 snprintf(intrinsic_name, sizeof(intrinsic_name),
4057 "llvm.amdgcn.image.atomic.%s.%s",
4058 action->intr_name, coords_type);
4059 }
4060
4061 tmp = lp_build_intrinsic(
4062 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4063 emit_data->args, emit_data->arg_count, 0);
4064 emit_data->output[emit_data->chan] =
4065 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4066 }
4067
4068 static void set_tex_fetch_args(struct si_shader_context *ctx,
4069 struct lp_build_emit_data *emit_data,
4070 unsigned target,
4071 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4072 LLVMValueRef *param, unsigned count,
4073 unsigned dmask)
4074 {
4075 struct gallivm_state *gallivm = &ctx->gallivm;
4076 struct ac_image_args args = {};
4077
4078 /* Pad to power of two vector */
4079 while (count < util_next_power_of_two(count))
4080 param[count++] = LLVMGetUndef(ctx->i32);
4081
4082 if (count > 1)
4083 args.addr = lp_build_gather_values(gallivm, param, count);
4084 else
4085 args.addr = param[0];
4086
4087 args.resource = res_ptr;
4088 args.sampler = samp_ptr;
4089 args.dmask = dmask;
4090 args.unorm = target == TGSI_TEXTURE_RECT ||
4091 target == TGSI_TEXTURE_SHADOWRECT;
4092 args.da = tgsi_is_array_sampler(target);
4093
4094 /* Ugly, but we seem to have no other choice right now. */
4095 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4096 memcpy(emit_data->args, &args, sizeof(args));
4097 }
4098
4099 static void resq_fetch_args(
4100 struct lp_build_tgsi_context * bld_base,
4101 struct lp_build_emit_data * emit_data)
4102 {
4103 struct si_shader_context *ctx = si_shader_context(bld_base);
4104 const struct tgsi_full_instruction *inst = emit_data->inst;
4105 const struct tgsi_full_src_register *reg = &inst->Src[0];
4106
4107 emit_data->dst_type = ctx->v4i32;
4108
4109 if (reg->Register.File == TGSI_FILE_BUFFER) {
4110 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4111 emit_data->arg_count = 1;
4112 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4113 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4114 &emit_data->args[0]);
4115 emit_data->arg_count = 1;
4116 } else {
4117 LLVMValueRef res_ptr;
4118 unsigned image_target;
4119
4120 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4121 image_target = TGSI_TEXTURE_2D_ARRAY;
4122 else
4123 image_target = inst->Memory.Texture;
4124
4125 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4126 &res_ptr);
4127 set_tex_fetch_args(ctx, emit_data, image_target,
4128 res_ptr, NULL, &bld_base->uint_bld.zero, 1,
4129 0xf);
4130 }
4131 }
4132
4133 static void resq_emit(
4134 const struct lp_build_tgsi_action *action,
4135 struct lp_build_tgsi_context *bld_base,
4136 struct lp_build_emit_data *emit_data)
4137 {
4138 struct si_shader_context *ctx = si_shader_context(bld_base);
4139 struct gallivm_state *gallivm = bld_base->base.gallivm;
4140 LLVMBuilderRef builder = gallivm->builder;
4141 const struct tgsi_full_instruction *inst = emit_data->inst;
4142 LLVMValueRef out;
4143
4144 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4145 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4146 lp_build_const_int32(gallivm, 2), "");
4147 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4148 out = get_buffer_size(bld_base, emit_data->args[0]);
4149 } else {
4150 struct ac_image_args args;
4151
4152 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4153 args.opcode = ac_image_get_resinfo;
4154 out = ac_build_image_opcode(&ctx->ac, &args);
4155
4156 /* Divide the number of layers by 6 to get the number of cubes. */
4157 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4158 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4159 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4160
4161 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4162 z = LLVMBuildSDiv(builder, z, imm6, "");
4163 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4164 }
4165 }
4166
4167 emit_data->output[emit_data->chan] = out;
4168 }
4169
4170 static const struct lp_build_tgsi_action tex_action;
4171
4172 enum desc_type {
4173 DESC_IMAGE,
4174 DESC_BUFFER,
4175 DESC_FMASK,
4176 DESC_SAMPLER,
4177 };
4178
4179 /**
4180 * Load an image view, fmask view. or sampler state descriptor.
4181 */
4182 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4183 LLVMValueRef list, LLVMValueRef index,
4184 enum desc_type type)
4185 {
4186 struct gallivm_state *gallivm = &ctx->gallivm;
4187 LLVMBuilderRef builder = gallivm->builder;
4188
4189 switch (type) {
4190 case DESC_IMAGE:
4191 /* The image is at [0:7]. */
4192 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4193 break;
4194 case DESC_BUFFER:
4195 /* The buffer is in [4:7]. */
4196 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4197 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4198 list = LLVMBuildPointerCast(builder, list,
4199 const_array(ctx->v4i32, 0), "");
4200 break;
4201 case DESC_FMASK:
4202 /* The FMASK is at [8:15]. */
4203 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4204 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4205 break;
4206 case DESC_SAMPLER:
4207 /* The sampler state is at [12:15]. */
4208 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4209 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4210 list = LLVMBuildPointerCast(builder, list,
4211 const_array(ctx->v4i32, 0), "");
4212 break;
4213 }
4214
4215 return ac_build_indexed_load_const(&ctx->ac, list, index);
4216 }
4217
4218 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4219 LLVMValueRef index, enum desc_type type)
4220 {
4221 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4222 SI_PARAM_SAMPLERS);
4223
4224 return load_sampler_desc_custom(ctx, list, index, type);
4225 }
4226
4227 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4228 *
4229 * SI-CI:
4230 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4231 * filtering manually. The driver sets img7 to a mask clearing
4232 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4233 * s_and_b32 samp0, samp0, img7
4234 *
4235 * VI:
4236 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4237 */
4238 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4239 LLVMValueRef res, LLVMValueRef samp)
4240 {
4241 LLVMBuilderRef builder = ctx->gallivm.builder;
4242 LLVMValueRef img7, samp0;
4243
4244 if (ctx->screen->b.chip_class >= VI)
4245 return samp;
4246
4247 img7 = LLVMBuildExtractElement(builder, res,
4248 LLVMConstInt(ctx->i32, 7, 0), "");
4249 samp0 = LLVMBuildExtractElement(builder, samp,
4250 LLVMConstInt(ctx->i32, 0, 0), "");
4251 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4252 return LLVMBuildInsertElement(builder, samp, samp0,
4253 LLVMConstInt(ctx->i32, 0, 0), "");
4254 }
4255
4256 static void tex_fetch_ptrs(
4257 struct lp_build_tgsi_context *bld_base,
4258 struct lp_build_emit_data *emit_data,
4259 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4260 {
4261 struct si_shader_context *ctx = si_shader_context(bld_base);
4262 const struct tgsi_full_instruction *inst = emit_data->inst;
4263 unsigned target = inst->Texture.Texture;
4264 unsigned sampler_src;
4265 unsigned sampler_index;
4266 LLVMValueRef index;
4267
4268 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4269 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4270
4271 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4272 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4273
4274 index = get_bounded_indirect_index(ctx,
4275 &reg->Indirect,
4276 reg->Register.Index,
4277 SI_NUM_SAMPLERS);
4278 } else {
4279 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4280 }
4281
4282 if (target == TGSI_TEXTURE_BUFFER)
4283 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4284 else
4285 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4286
4287 if (samp_ptr)
4288 *samp_ptr = NULL;
4289 if (fmask_ptr)
4290 *fmask_ptr = NULL;
4291
4292 if (target == TGSI_TEXTURE_2D_MSAA ||
4293 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4294 if (fmask_ptr)
4295 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4296 } else if (target != TGSI_TEXTURE_BUFFER) {
4297 if (samp_ptr) {
4298 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4299 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4300 }
4301 }
4302 }
4303
4304 static void txq_fetch_args(
4305 struct lp_build_tgsi_context *bld_base,
4306 struct lp_build_emit_data *emit_data)
4307 {
4308 struct si_shader_context *ctx = si_shader_context(bld_base);
4309 const struct tgsi_full_instruction *inst = emit_data->inst;
4310 unsigned target = inst->Texture.Texture;
4311 LLVMValueRef res_ptr;
4312 LLVMValueRef address;
4313
4314 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4315
4316 if (target == TGSI_TEXTURE_BUFFER) {
4317 /* Read the size from the buffer descriptor directly. */
4318 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4319 return;
4320 }
4321
4322 /* Textures - set the mip level. */
4323 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4324
4325 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4326 NULL, &address, 1, 0xf);
4327 }
4328
4329 static void txq_emit(const struct lp_build_tgsi_action *action,
4330 struct lp_build_tgsi_context *bld_base,
4331 struct lp_build_emit_data *emit_data)
4332 {
4333 struct si_shader_context *ctx = si_shader_context(bld_base);
4334 struct ac_image_args args;
4335 unsigned target = emit_data->inst->Texture.Texture;
4336
4337 if (target == TGSI_TEXTURE_BUFFER) {
4338 /* Just return the buffer size. */
4339 emit_data->output[emit_data->chan] = emit_data->args[0];
4340 return;
4341 }
4342
4343 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4344
4345 args.opcode = ac_image_get_resinfo;
4346 emit_data->output[emit_data->chan] =
4347 ac_build_image_opcode(&ctx->ac, &args);
4348
4349 /* Divide the number of layers by 6 to get the number of cubes. */
4350 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4351 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4352 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4353 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4354 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4355
4356 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4357 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4358 z = LLVMBuildSDiv(builder, z, six, "");
4359
4360 emit_data->output[emit_data->chan] =
4361 LLVMBuildInsertElement(builder, v4, z, two, "");
4362 }
4363 }
4364
4365 static void tex_fetch_args(
4366 struct lp_build_tgsi_context *bld_base,
4367 struct lp_build_emit_data *emit_data)
4368 {
4369 struct si_shader_context *ctx = si_shader_context(bld_base);
4370 struct gallivm_state *gallivm = bld_base->base.gallivm;
4371 const struct tgsi_full_instruction *inst = emit_data->inst;
4372 unsigned opcode = inst->Instruction.Opcode;
4373 unsigned target = inst->Texture.Texture;
4374 LLVMValueRef coords[5], derivs[6];
4375 LLVMValueRef address[16];
4376 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4377 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4378 unsigned count = 0;
4379 unsigned chan;
4380 unsigned num_deriv_channels = 0;
4381 bool has_offset = inst->Texture.NumOffsets > 0;
4382 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4383 unsigned dmask = 0xf;
4384
4385 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4386
4387 if (target == TGSI_TEXTURE_BUFFER) {
4388 emit_data->dst_type = ctx->v4f32;
4389 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4390 ctx->v16i8, "");
4391 emit_data->args[1] = bld_base->uint_bld.zero;
4392 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4393 emit_data->arg_count = 3;
4394 return;
4395 }
4396
4397 /* Fetch and project texture coordinates */
4398 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4399 for (chan = 0; chan < 3; chan++ ) {
4400 coords[chan] = lp_build_emit_fetch(bld_base,
4401 emit_data->inst, 0,
4402 chan);
4403 if (opcode == TGSI_OPCODE_TXP)
4404 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4405 TGSI_OPCODE_DIV,
4406 coords[chan],
4407 coords[3]);
4408 }
4409
4410 if (opcode == TGSI_OPCODE_TXP)
4411 coords[3] = bld_base->base.one;
4412
4413 /* Pack offsets. */
4414 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4415 /* The offsets are six-bit signed integers packed like this:
4416 * X=[5:0], Y=[13:8], and Z=[21:16].
4417 */
4418 LLVMValueRef offset[3], pack;
4419
4420 assert(inst->Texture.NumOffsets == 1);
4421
4422 for (chan = 0; chan < 3; chan++) {
4423 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4424 emit_data->inst, 0, chan);
4425 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4426 lp_build_const_int32(gallivm, 0x3f), "");
4427 if (chan)
4428 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4429 lp_build_const_int32(gallivm, chan*8), "");
4430 }
4431
4432 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4433 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4434 address[count++] = pack;
4435 }
4436
4437 /* Pack LOD bias value */
4438 if (opcode == TGSI_OPCODE_TXB)
4439 address[count++] = coords[3];
4440 if (opcode == TGSI_OPCODE_TXB2)
4441 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4442
4443 /* Pack depth comparison value */
4444 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4445 LLVMValueRef z;
4446
4447 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4448 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4449 } else {
4450 assert(ref_pos >= 0);
4451 z = coords[ref_pos];
4452 }
4453
4454 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4455 * so the depth comparison value isn't clamped for Z16 and
4456 * Z24 anymore. Do it manually here.
4457 *
4458 * It's unnecessary if the original texture format was
4459 * Z32_FLOAT, but we don't know that here.
4460 */
4461 if (ctx->screen->b.chip_class == VI)
4462 z = ac_build_clamp(&ctx->ac, z);
4463
4464 address[count++] = z;
4465 }
4466
4467 /* Pack user derivatives */
4468 if (opcode == TGSI_OPCODE_TXD) {
4469 int param, num_src_deriv_channels;
4470
4471 switch (target) {
4472 case TGSI_TEXTURE_3D:
4473 num_src_deriv_channels = 3;
4474 num_deriv_channels = 3;
4475 break;
4476 case TGSI_TEXTURE_2D:
4477 case TGSI_TEXTURE_SHADOW2D:
4478 case TGSI_TEXTURE_RECT:
4479 case TGSI_TEXTURE_SHADOWRECT:
4480 case TGSI_TEXTURE_2D_ARRAY:
4481 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4482 num_src_deriv_channels = 2;
4483 num_deriv_channels = 2;
4484 break;
4485 case TGSI_TEXTURE_CUBE:
4486 case TGSI_TEXTURE_SHADOWCUBE:
4487 case TGSI_TEXTURE_CUBE_ARRAY:
4488 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4489 /* Cube derivatives will be converted to 2D. */
4490 num_src_deriv_channels = 3;
4491 num_deriv_channels = 2;
4492 break;
4493 case TGSI_TEXTURE_1D:
4494 case TGSI_TEXTURE_SHADOW1D:
4495 case TGSI_TEXTURE_1D_ARRAY:
4496 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4497 num_src_deriv_channels = 1;
4498 num_deriv_channels = 1;
4499 break;
4500 default:
4501 unreachable("invalid target");
4502 }
4503
4504 for (param = 0; param < 2; param++)
4505 for (chan = 0; chan < num_src_deriv_channels; chan++)
4506 derivs[param * num_src_deriv_channels + chan] =
4507 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4508 }
4509
4510 if (target == TGSI_TEXTURE_CUBE ||
4511 target == TGSI_TEXTURE_CUBE_ARRAY ||
4512 target == TGSI_TEXTURE_SHADOWCUBE ||
4513 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4514 ac_prepare_cube_coords(&ctx->ac,
4515 opcode == TGSI_OPCODE_TXD,
4516 target == TGSI_TEXTURE_CUBE_ARRAY ||
4517 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4518 coords, derivs);
4519
4520 if (opcode == TGSI_OPCODE_TXD)
4521 for (int i = 0; i < num_deriv_channels * 2; i++)
4522 address[count++] = derivs[i];
4523
4524 /* Pack texture coordinates */
4525 address[count++] = coords[0];
4526 if (num_coords > 1)
4527 address[count++] = coords[1];
4528 if (num_coords > 2)
4529 address[count++] = coords[2];
4530
4531 /* Pack LOD or sample index */
4532 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4533 address[count++] = coords[3];
4534 else if (opcode == TGSI_OPCODE_TXL2)
4535 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4536
4537 if (count > 16) {
4538 assert(!"Cannot handle more than 16 texture address parameters");
4539 count = 16;
4540 }
4541
4542 for (chan = 0; chan < count; chan++ ) {
4543 address[chan] = LLVMBuildBitCast(gallivm->builder,
4544 address[chan], ctx->i32, "");
4545 }
4546
4547 /* Adjust the sample index according to FMASK.
4548 *
4549 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4550 * which is the identity mapping. Each nibble says which physical sample
4551 * should be fetched to get that sample.
4552 *
4553 * For example, 0x11111100 means there are only 2 samples stored and
4554 * the second sample covers 3/4 of the pixel. When reading samples 0
4555 * and 1, return physical sample 0 (determined by the first two 0s
4556 * in FMASK), otherwise return physical sample 1.
4557 *
4558 * The sample index should be adjusted as follows:
4559 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4560 */
4561 if (target == TGSI_TEXTURE_2D_MSAA ||
4562 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4563 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4564 struct lp_build_emit_data txf_emit_data = *emit_data;
4565 LLVMValueRef txf_address[4];
4566 /* We only need .xy for non-arrays, and .xyz for arrays. */
4567 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4568 struct tgsi_full_instruction inst = {};
4569
4570 memcpy(txf_address, address, sizeof(txf_address));
4571
4572 /* Read FMASK using TXF. */
4573 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4574 inst.Texture.Texture = target;
4575 txf_emit_data.inst = &inst;
4576 txf_emit_data.chan = 0;
4577 set_tex_fetch_args(ctx, &txf_emit_data,
4578 target, fmask_ptr, NULL,
4579 txf_address, txf_count, 0xf);
4580 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4581
4582 /* Initialize some constants. */
4583 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4584 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4585
4586 /* Apply the formula. */
4587 LLVMValueRef fmask =
4588 LLVMBuildExtractElement(gallivm->builder,
4589 txf_emit_data.output[0],
4590 uint_bld->zero, "");
4591
4592 unsigned sample_chan = txf_count; /* the sample index is last */
4593
4594 LLVMValueRef sample_index4 =
4595 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4596
4597 LLVMValueRef shifted_fmask =
4598 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4599
4600 LLVMValueRef final_sample =
4601 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4602
4603 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4604 * resource descriptor is 0 (invalid),
4605 */
4606 LLVMValueRef fmask_desc =
4607 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4608 ctx->v8i32, "");
4609
4610 LLVMValueRef fmask_word1 =
4611 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4612 uint_bld->one, "");
4613
4614 LLVMValueRef word1_is_nonzero =
4615 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4616 fmask_word1, uint_bld->zero, "");
4617
4618 /* Replace the MSAA sample index. */
4619 address[sample_chan] =
4620 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4621 final_sample, address[sample_chan], "");
4622 }
4623
4624 if (opcode == TGSI_OPCODE_TXF) {
4625 /* add tex offsets */
4626 if (inst->Texture.NumOffsets) {
4627 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4628 const struct tgsi_texture_offset *off = inst->TexOffsets;
4629
4630 assert(inst->Texture.NumOffsets == 1);
4631
4632 switch (target) {
4633 case TGSI_TEXTURE_3D:
4634 address[2] = lp_build_add(uint_bld, address[2],
4635 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4636 /* fall through */
4637 case TGSI_TEXTURE_2D:
4638 case TGSI_TEXTURE_SHADOW2D:
4639 case TGSI_TEXTURE_RECT:
4640 case TGSI_TEXTURE_SHADOWRECT:
4641 case TGSI_TEXTURE_2D_ARRAY:
4642 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4643 address[1] =
4644 lp_build_add(uint_bld, address[1],
4645 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4646 /* fall through */
4647 case TGSI_TEXTURE_1D:
4648 case TGSI_TEXTURE_SHADOW1D:
4649 case TGSI_TEXTURE_1D_ARRAY:
4650 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4651 address[0] =
4652 lp_build_add(uint_bld, address[0],
4653 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4654 break;
4655 /* texture offsets do not apply to other texture targets */
4656 }
4657 }
4658 }
4659
4660 if (opcode == TGSI_OPCODE_TG4) {
4661 unsigned gather_comp = 0;
4662
4663 /* DMASK was repurposed for GATHER4. 4 components are always
4664 * returned and DMASK works like a swizzle - it selects
4665 * the component to fetch. The only valid DMASK values are
4666 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4667 * (red,red,red,red) etc.) The ISA document doesn't mention
4668 * this.
4669 */
4670
4671 /* Get the component index from src1.x for Gather4. */
4672 if (!tgsi_is_shadow_target(target)) {
4673 LLVMValueRef comp_imm;
4674 struct tgsi_src_register src1 = inst->Src[1].Register;
4675
4676 assert(src1.File == TGSI_FILE_IMMEDIATE);
4677
4678 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4679 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4680 gather_comp = CLAMP(gather_comp, 0, 3);
4681 }
4682
4683 dmask = 1 << gather_comp;
4684 }
4685
4686 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4687 samp_ptr, address, count, dmask);
4688 }
4689
4690 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4691 * incorrectly forces nearest filtering if the texture format is integer.
4692 * The only effect it has on Gather4, which always returns 4 texels for
4693 * bilinear filtering, is that the final coordinates are off by 0.5 of
4694 * the texel size.
4695 *
4696 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4697 * or (0.5 / size) from the normalized coordinates.
4698 */
4699 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4700 struct ac_image_args *args,
4701 unsigned target)
4702 {
4703 LLVMBuilderRef builder = ctx->gallivm.builder;
4704 LLVMValueRef coord = args->addr;
4705 LLVMValueRef half_texel[2];
4706 /* Texture coordinates start after:
4707 * {offset, bias, z-compare, derivatives}
4708 * Only the offset and z-compare can occur here.
4709 */
4710 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4711 int c;
4712
4713 if (target == TGSI_TEXTURE_RECT ||
4714 target == TGSI_TEXTURE_SHADOWRECT) {
4715 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4716 } else {
4717 struct tgsi_full_instruction txq_inst = {};
4718 struct lp_build_emit_data txq_emit_data = {};
4719
4720 /* Query the texture size. */
4721 txq_inst.Texture.Texture = target;
4722 txq_emit_data.inst = &txq_inst;
4723 txq_emit_data.dst_type = ctx->v4i32;
4724 set_tex_fetch_args(ctx, &txq_emit_data, target,
4725 args->resource, NULL,
4726 &ctx->bld_base.uint_bld.zero,
4727 1, 0xf);
4728 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4729
4730 /* Compute -0.5 / size. */
4731 for (c = 0; c < 2; c++) {
4732 half_texel[c] =
4733 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4734 LLVMConstInt(ctx->i32, c, 0), "");
4735 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4736 half_texel[c] =
4737 lp_build_emit_llvm_unary(&ctx->bld_base,
4738 TGSI_OPCODE_RCP, half_texel[c]);
4739 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4740 LLVMConstReal(ctx->f32, -0.5), "");
4741 }
4742 }
4743
4744 for (c = 0; c < 2; c++) {
4745 LLVMValueRef tmp;
4746 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4747
4748 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4749 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4750 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4751 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4752 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4753 }
4754
4755 args->addr = coord;
4756 }
4757
4758 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4759 struct lp_build_tgsi_context *bld_base,
4760 struct lp_build_emit_data *emit_data)
4761 {
4762 struct si_shader_context *ctx = si_shader_context(bld_base);
4763 const struct tgsi_full_instruction *inst = emit_data->inst;
4764 struct ac_image_args args;
4765 unsigned opcode = inst->Instruction.Opcode;
4766 unsigned target = inst->Texture.Texture;
4767
4768 if (target == TGSI_TEXTURE_BUFFER) {
4769 emit_data->output[emit_data->chan] =
4770 ac_build_buffer_load_format(&ctx->ac,
4771 emit_data->args[0],
4772 emit_data->args[2],
4773 emit_data->args[1],
4774 true);
4775 return;
4776 }
4777
4778 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4779
4780 args.opcode = ac_image_sample;
4781 args.compare = tgsi_is_shadow_target(target);
4782 args.offset = inst->Texture.NumOffsets > 0;
4783
4784 switch (opcode) {
4785 case TGSI_OPCODE_TXF:
4786 args.opcode = target == TGSI_TEXTURE_2D_MSAA ||
4787 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4788 ac_image_load : ac_image_load_mip;
4789 args.compare = false;
4790 args.offset = false;
4791 break;
4792 case TGSI_OPCODE_LODQ:
4793 args.opcode = ac_image_get_lod;
4794 args.compare = false;
4795 args.offset = false;
4796 break;
4797 case TGSI_OPCODE_TEX:
4798 case TGSI_OPCODE_TEX2:
4799 case TGSI_OPCODE_TXP:
4800 if (ctx->type != PIPE_SHADER_FRAGMENT)
4801 args.level_zero = true;
4802 break;
4803 case TGSI_OPCODE_TXB:
4804 case TGSI_OPCODE_TXB2:
4805 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4806 args.bias = true;
4807 break;
4808 case TGSI_OPCODE_TXL:
4809 case TGSI_OPCODE_TXL2:
4810 args.lod = true;
4811 break;
4812 case TGSI_OPCODE_TXD:
4813 args.deriv = true;
4814 break;
4815 case TGSI_OPCODE_TG4:
4816 args.opcode = ac_image_gather4;
4817 args.level_zero = true;
4818 break;
4819 default:
4820 assert(0);
4821 return;
4822 }
4823
4824 /* The hardware needs special lowering for Gather4 with integer formats. */
4825 if (opcode == TGSI_OPCODE_TG4) {
4826 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4827 /* This will also work with non-constant indexing because of how
4828 * glsl_to_tgsi works and we intent to preserve that behavior.
4829 */
4830 const unsigned src_idx = 2;
4831 unsigned sampler = inst->Src[src_idx].Register.Index;
4832
4833 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4834
4835 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4836 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4837 si_lower_gather4_integer(ctx, &args, target);
4838 }
4839
4840 emit_data->output[emit_data->chan] =
4841 ac_build_image_opcode(&ctx->ac, &args);
4842 }
4843
4844 static void si_llvm_emit_txqs(
4845 const struct lp_build_tgsi_action *action,
4846 struct lp_build_tgsi_context *bld_base,
4847 struct lp_build_emit_data *emit_data)
4848 {
4849 struct si_shader_context *ctx = si_shader_context(bld_base);
4850 struct gallivm_state *gallivm = bld_base->base.gallivm;
4851 LLVMBuilderRef builder = gallivm->builder;
4852 LLVMValueRef res, samples;
4853 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4854
4855 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4856
4857
4858 /* Read the samples from the descriptor directly. */
4859 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4860 samples = LLVMBuildExtractElement(
4861 builder, res,
4862 lp_build_const_int32(gallivm, 3), "");
4863 samples = LLVMBuildLShr(builder, samples,
4864 lp_build_const_int32(gallivm, 16), "");
4865 samples = LLVMBuildAnd(builder, samples,
4866 lp_build_const_int32(gallivm, 0xf), "");
4867 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4868 samples, "");
4869
4870 emit_data->output[emit_data->chan] = samples;
4871 }
4872
4873 static void si_llvm_emit_ddxy(
4874 const struct lp_build_tgsi_action *action,
4875 struct lp_build_tgsi_context *bld_base,
4876 struct lp_build_emit_data *emit_data)
4877 {
4878 struct si_shader_context *ctx = si_shader_context(bld_base);
4879 struct gallivm_state *gallivm = bld_base->base.gallivm;
4880 unsigned opcode = emit_data->info->opcode;
4881 LLVMValueRef val;
4882 int idx;
4883 unsigned mask;
4884
4885 if (opcode == TGSI_OPCODE_DDX_FINE)
4886 mask = AC_TID_MASK_LEFT;
4887 else if (opcode == TGSI_OPCODE_DDY_FINE)
4888 mask = AC_TID_MASK_TOP;
4889 else
4890 mask = AC_TID_MASK_TOP_LEFT;
4891
4892 /* for DDX we want to next X pixel, DDY next Y pixel. */
4893 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4894
4895 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4896 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
4897 mask, idx, ctx->lds, val);
4898 emit_data->output[emit_data->chan] = val;
4899 }
4900
4901 /*
4902 * this takes an I,J coordinate pair,
4903 * and works out the X and Y derivatives.
4904 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4905 */
4906 static LLVMValueRef si_llvm_emit_ddxy_interp(
4907 struct lp_build_tgsi_context *bld_base,
4908 LLVMValueRef interp_ij)
4909 {
4910 struct si_shader_context *ctx = si_shader_context(bld_base);
4911 struct gallivm_state *gallivm = bld_base->base.gallivm;
4912 LLVMValueRef result[4], a;
4913 unsigned i;
4914
4915 for (i = 0; i < 2; i++) {
4916 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4917 LLVMConstInt(ctx->i32, i, 0), "");
4918 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4919 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4920 }
4921
4922 return lp_build_gather_values(gallivm, result, 4);
4923 }
4924
4925 static void interp_fetch_args(
4926 struct lp_build_tgsi_context *bld_base,
4927 struct lp_build_emit_data *emit_data)
4928 {
4929 struct si_shader_context *ctx = si_shader_context(bld_base);
4930 struct gallivm_state *gallivm = bld_base->base.gallivm;
4931 const struct tgsi_full_instruction *inst = emit_data->inst;
4932
4933 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4934 /* offset is in second src, first two channels */
4935 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4936 emit_data->inst, 1,
4937 TGSI_CHAN_X);
4938 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4939 emit_data->inst, 1,
4940 TGSI_CHAN_Y);
4941 emit_data->arg_count = 2;
4942 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4943 LLVMValueRef sample_position;
4944 LLVMValueRef sample_id;
4945 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4946
4947 /* fetch sample ID, then fetch its sample position,
4948 * and place into first two channels.
4949 */
4950 sample_id = lp_build_emit_fetch(bld_base,
4951 emit_data->inst, 1, TGSI_CHAN_X);
4952 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4953 ctx->i32, "");
4954 sample_position = load_sample_position(ctx, sample_id);
4955
4956 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4957 sample_position,
4958 lp_build_const_int32(gallivm, 0), "");
4959
4960 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4961 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4962 sample_position,
4963 lp_build_const_int32(gallivm, 1), "");
4964 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4965 emit_data->arg_count = 2;
4966 }
4967 }
4968
4969 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4970 struct lp_build_tgsi_context *bld_base,
4971 struct lp_build_emit_data *emit_data)
4972 {
4973 struct si_shader_context *ctx = si_shader_context(bld_base);
4974 struct si_shader *shader = ctx->shader;
4975 struct gallivm_state *gallivm = bld_base->base.gallivm;
4976 struct lp_build_context *uint = &bld_base->uint_bld;
4977 LLVMValueRef interp_param;
4978 const struct tgsi_full_instruction *inst = emit_data->inst;
4979 int input_index = inst->Src[0].Register.Index;
4980 int chan;
4981 int i;
4982 LLVMValueRef attr_number;
4983 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
4984 int interp_param_idx;
4985 unsigned interp = shader->selector->info.input_interpolate[input_index];
4986 unsigned location;
4987
4988 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4989
4990 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4991 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4992 location = TGSI_INTERPOLATE_LOC_CENTER;
4993 else
4994 location = TGSI_INTERPOLATE_LOC_CENTROID;
4995
4996 interp_param_idx = lookup_interp_param_index(interp, location);
4997 if (interp_param_idx == -1)
4998 return;
4999 else if (interp_param_idx)
5000 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5001 else
5002 interp_param = NULL;
5003
5004 attr_number = lp_build_const_int32(gallivm, input_index);
5005
5006 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5007 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5008 LLVMValueRef ij_out[2];
5009 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5010
5011 /*
5012 * take the I then J parameters, and the DDX/Y for it, and
5013 * calculate the IJ inputs for the interpolator.
5014 * temp1 = ddx * offset/sample.x + I;
5015 * interp_param.I = ddy * offset/sample.y + temp1;
5016 * temp1 = ddx * offset/sample.x + J;
5017 * interp_param.J = ddy * offset/sample.y + temp1;
5018 */
5019 for (i = 0; i < 2; i++) {
5020 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5021 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5022 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5023 ddxy_out, ix_ll, "");
5024 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5025 ddxy_out, iy_ll, "");
5026 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5027 interp_param, ix_ll, "");
5028 LLVMValueRef temp1, temp2;
5029
5030 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5031 ctx->f32, "");
5032
5033 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5034
5035 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5036
5037 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5038
5039 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5040 }
5041 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5042 }
5043
5044 for (chan = 0; chan < 4; chan++) {
5045 LLVMValueRef llvm_chan;
5046 unsigned schan;
5047
5048 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5049 llvm_chan = lp_build_const_int32(gallivm, schan);
5050
5051 if (interp_param) {
5052 interp_param = LLVMBuildBitCast(gallivm->builder,
5053 interp_param, LLVMVectorType(ctx->f32, 2), "");
5054 LLVMValueRef i = LLVMBuildExtractElement(
5055 gallivm->builder, interp_param, uint->zero, "");
5056 LLVMValueRef j = LLVMBuildExtractElement(
5057 gallivm->builder, interp_param, uint->one, "");
5058 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5059 llvm_chan, attr_number, params,
5060 i, j);
5061 } else {
5062 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5063 lp_build_const_int32(gallivm, 2), /* P0 */
5064 llvm_chan, attr_number, params);
5065 }
5066 }
5067 }
5068
5069 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5070 struct lp_build_emit_data *emit_data)
5071 {
5072 struct si_shader_context *ctx = si_shader_context(bld_base);
5073 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5074 LLVMValueRef imm;
5075 unsigned stream;
5076
5077 assert(src0.File == TGSI_FILE_IMMEDIATE);
5078
5079 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5080 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5081 return stream;
5082 }
5083
5084 /* Emit one vertex from the geometry shader */
5085 static void si_llvm_emit_vertex(
5086 const struct lp_build_tgsi_action *action,
5087 struct lp_build_tgsi_context *bld_base,
5088 struct lp_build_emit_data *emit_data)
5089 {
5090 struct si_shader_context *ctx = si_shader_context(bld_base);
5091 struct lp_build_context *uint = &bld_base->uint_bld;
5092 struct si_shader *shader = ctx->shader;
5093 struct tgsi_shader_info *info = &shader->selector->info;
5094 struct gallivm_state *gallivm = bld_base->base.gallivm;
5095 struct lp_build_if_state if_state;
5096 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5097 SI_PARAM_GS2VS_OFFSET);
5098 LLVMValueRef gs_next_vertex;
5099 LLVMValueRef can_emit, kill;
5100 unsigned chan, offset;
5101 int i;
5102 unsigned stream;
5103
5104 stream = si_llvm_get_stream(bld_base, emit_data);
5105
5106 /* Write vertex attribute values to GSVS ring */
5107 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5108 ctx->gs_next_vertex[stream],
5109 "");
5110
5111 /* If this thread has already emitted the declared maximum number of
5112 * vertices, skip the write: excessive vertex emissions are not
5113 * supposed to have any effect.
5114 *
5115 * If the shader has no writes to memory, kill it instead. This skips
5116 * further memory loads and may allow LLVM to skip to the end
5117 * altogether.
5118 */
5119 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5120 lp_build_const_int32(gallivm,
5121 shader->selector->gs_max_out_vertices), "");
5122
5123 bool use_kill = !info->writes_memory;
5124 if (use_kill) {
5125 kill = lp_build_select(&bld_base->base, can_emit,
5126 lp_build_const_float(gallivm, 1.0f),
5127 lp_build_const_float(gallivm, -1.0f));
5128
5129 ac_build_kill(&ctx->ac, kill);
5130 } else {
5131 lp_build_if(&if_state, gallivm, can_emit);
5132 }
5133
5134 offset = 0;
5135 for (i = 0; i < info->num_outputs; i++) {
5136 LLVMValueRef *out_ptr = ctx->outputs[i];
5137
5138 for (chan = 0; chan < 4; chan++) {
5139 if (!(info->output_usagemask[i] & (1 << chan)) ||
5140 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5141 continue;
5142
5143 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5144 LLVMValueRef voffset =
5145 lp_build_const_int32(gallivm, offset *
5146 shader->selector->gs_max_out_vertices);
5147 offset++;
5148
5149 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5150 voffset = lp_build_mul_imm(uint, voffset, 4);
5151
5152 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5153
5154 ac_build_buffer_store_dword(&ctx->ac,
5155 ctx->gsvs_ring[stream],
5156 out_val, 1,
5157 voffset, soffset, 0,
5158 1, 1, true, true);
5159 }
5160 }
5161
5162 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5163 lp_build_const_int32(gallivm, 1));
5164
5165 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5166
5167 /* Signal vertex emission */
5168 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5169 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5170 if (!use_kill)
5171 lp_build_endif(&if_state);
5172 }
5173
5174 /* Cut one primitive from the geometry shader */
5175 static void si_llvm_emit_primitive(
5176 const struct lp_build_tgsi_action *action,
5177 struct lp_build_tgsi_context *bld_base,
5178 struct lp_build_emit_data *emit_data)
5179 {
5180 struct si_shader_context *ctx = si_shader_context(bld_base);
5181 unsigned stream;
5182
5183 /* Signal primitive cut */
5184 stream = si_llvm_get_stream(bld_base, emit_data);
5185 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5186 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5187 }
5188
5189 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5190 struct lp_build_tgsi_context *bld_base,
5191 struct lp_build_emit_data *emit_data)
5192 {
5193 struct si_shader_context *ctx = si_shader_context(bld_base);
5194 struct gallivm_state *gallivm = bld_base->base.gallivm;
5195
5196 /* SI only (thanks to a hw bug workaround):
5197 * The real barrier instruction isn’t needed, because an entire patch
5198 * always fits into a single wave.
5199 */
5200 if (HAVE_LLVM >= 0x0309 &&
5201 ctx->screen->b.chip_class == SI &&
5202 ctx->type == PIPE_SHADER_TESS_CTRL) {
5203 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5204 return;
5205 }
5206
5207 lp_build_intrinsic(gallivm->builder,
5208 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5209 : "llvm.AMDGPU.barrier.local",
5210 ctx->voidt, NULL, 0, 0);
5211 }
5212
5213 static const struct lp_build_tgsi_action tex_action = {
5214 .fetch_args = tex_fetch_args,
5215 .emit = build_tex_intrinsic,
5216 };
5217
5218 static const struct lp_build_tgsi_action interp_action = {
5219 .fetch_args = interp_fetch_args,
5220 .emit = build_interp_intrinsic,
5221 };
5222
5223 static void si_create_function(struct si_shader_context *ctx,
5224 const char *name,
5225 LLVMTypeRef *returns, unsigned num_returns,
5226 LLVMTypeRef *params, unsigned num_params,
5227 int last_sgpr)
5228 {
5229 int i;
5230
5231 si_llvm_create_func(ctx, name, returns, num_returns,
5232 params, num_params);
5233 si_llvm_shader_type(ctx->main_fn, ctx->type);
5234 ctx->return_value = LLVMGetUndef(ctx->return_type);
5235
5236 for (i = 0; i <= last_sgpr; ++i) {
5237 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5238
5239 /* The combination of:
5240 * - ByVal
5241 * - dereferenceable
5242 * - invariant.load
5243 * allows the optimization passes to move loads and reduces
5244 * SGPR spilling significantly.
5245 */
5246 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5247 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5248 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5249 lp_add_attr_dereferenceable(P, UINT64_MAX);
5250 } else
5251 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5252 }
5253
5254 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5255 "no-signed-zeros-fp-math",
5256 "true");
5257
5258 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5259 /* These were copied from some LLVM test. */
5260 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5261 "less-precise-fpmad",
5262 "true");
5263 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5264 "no-infs-fp-math",
5265 "true");
5266 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5267 "no-nans-fp-math",
5268 "true");
5269 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5270 "unsafe-fp-math",
5271 "true");
5272 }
5273 }
5274
5275 static void declare_streamout_params(struct si_shader_context *ctx,
5276 struct pipe_stream_output_info *so,
5277 LLVMTypeRef *params, LLVMTypeRef i32,
5278 unsigned *num_params)
5279 {
5280 int i;
5281
5282 /* Streamout SGPRs. */
5283 if (so->num_outputs) {
5284 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5285 params[ctx->param_streamout_config = (*num_params)++] = i32;
5286 else
5287 ctx->param_streamout_config = *num_params - 1;
5288
5289 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5290 }
5291 /* A streamout buffer offset is loaded if the stride is non-zero. */
5292 for (i = 0; i < 4; i++) {
5293 if (!so->stride[i])
5294 continue;
5295
5296 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5297 }
5298 }
5299
5300 static unsigned llvm_get_type_size(LLVMTypeRef type)
5301 {
5302 LLVMTypeKind kind = LLVMGetTypeKind(type);
5303
5304 switch (kind) {
5305 case LLVMIntegerTypeKind:
5306 return LLVMGetIntTypeWidth(type) / 8;
5307 case LLVMFloatTypeKind:
5308 return 4;
5309 case LLVMPointerTypeKind:
5310 return 8;
5311 case LLVMVectorTypeKind:
5312 return LLVMGetVectorSize(type) *
5313 llvm_get_type_size(LLVMGetElementType(type));
5314 case LLVMArrayTypeKind:
5315 return LLVMGetArrayLength(type) *
5316 llvm_get_type_size(LLVMGetElementType(type));
5317 default:
5318 assert(0);
5319 return 0;
5320 }
5321 }
5322
5323 static void declare_tess_lds(struct si_shader_context *ctx)
5324 {
5325 struct gallivm_state *gallivm = &ctx->gallivm;
5326 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5327 struct lp_build_context *uint = &bld_base->uint_bld;
5328
5329 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5330 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5331 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5332 "tess_lds");
5333 }
5334
5335 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5336 {
5337 const unsigned *properties = shader->selector->info.properties;
5338 unsigned max_work_group_size =
5339 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5340 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5341 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5342
5343 if (!max_work_group_size) {
5344 /* This is a variable group size compute shader,
5345 * compile it for the maximum possible group size.
5346 */
5347 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5348 }
5349 return max_work_group_size;
5350 }
5351
5352 static void create_function(struct si_shader_context *ctx)
5353 {
5354 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5355 struct gallivm_state *gallivm = bld_base->base.gallivm;
5356 struct si_shader *shader = ctx->shader;
5357 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5358 LLVMTypeRef returns[16+32*4];
5359 unsigned i, last_sgpr, num_params, num_return_sgprs;
5360 unsigned num_returns = 0;
5361 unsigned num_prolog_vgprs = 0;
5362
5363 v3i32 = LLVMVectorType(ctx->i32, 3);
5364
5365 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5366 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5367 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5368 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5369 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5370
5371 switch (ctx->type) {
5372 case PIPE_SHADER_VERTEX:
5373 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5374 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5375 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5376 params[SI_PARAM_DRAWID] = ctx->i32;
5377 num_params = SI_PARAM_DRAWID+1;
5378
5379 if (shader->key.as_es) {
5380 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5381 } else if (shader->key.as_ls) {
5382 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5383 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5384 } else {
5385 if (shader->is_gs_copy_shader) {
5386 num_params = SI_PARAM_RW_BUFFERS+1;
5387 } else {
5388 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5389 num_params = SI_PARAM_VS_STATE_BITS+1;
5390 }
5391
5392 /* The locations of the other parameters are assigned dynamically. */
5393 declare_streamout_params(ctx, &shader->selector->so,
5394 params, ctx->i32, &num_params);
5395 }
5396
5397 last_sgpr = num_params-1;
5398
5399 /* VGPRs */
5400 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5401 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5402 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5403 params[ctx->param_instance_id = num_params++] = ctx->i32;
5404
5405 if (!shader->is_gs_copy_shader) {
5406 /* Vertex load indices. */
5407 ctx->param_vertex_index0 = num_params;
5408
5409 for (i = 0; i < shader->selector->info.num_inputs; i++)
5410 params[num_params++] = ctx->i32;
5411
5412 num_prolog_vgprs += shader->selector->info.num_inputs;
5413
5414 /* PrimitiveID output. */
5415 if (!shader->key.as_es && !shader->key.as_ls)
5416 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5417 returns[num_returns++] = ctx->f32;
5418 }
5419 break;
5420
5421 case PIPE_SHADER_TESS_CTRL:
5422 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5423 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5424 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5425 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5426 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5427 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5428 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5429
5430 /* VGPRs */
5431 params[SI_PARAM_PATCH_ID] = ctx->i32;
5432 params[SI_PARAM_REL_IDS] = ctx->i32;
5433 num_params = SI_PARAM_REL_IDS+1;
5434
5435 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5436 * placed after the user SGPRs.
5437 */
5438 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5439 returns[num_returns++] = ctx->i32; /* SGPRs */
5440
5441 for (i = 0; i < 3; i++)
5442 returns[num_returns++] = ctx->f32; /* VGPRs */
5443 break;
5444
5445 case PIPE_SHADER_TESS_EVAL:
5446 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5447 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5448
5449 if (shader->key.as_es) {
5450 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5451 params[num_params++] = ctx->i32;
5452 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5453 } else {
5454 params[num_params++] = ctx->i32;
5455 declare_streamout_params(ctx, &shader->selector->so,
5456 params, ctx->i32, &num_params);
5457 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5458 }
5459 last_sgpr = num_params - 1;
5460
5461 /* VGPRs */
5462 params[ctx->param_tes_u = num_params++] = ctx->f32;
5463 params[ctx->param_tes_v = num_params++] = ctx->f32;
5464 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5465 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5466
5467 /* PrimitiveID output. */
5468 if (!shader->key.as_es)
5469 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5470 returns[num_returns++] = ctx->f32;
5471 break;
5472
5473 case PIPE_SHADER_GEOMETRY:
5474 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5475 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5476 last_sgpr = SI_PARAM_GS_WAVE_ID;
5477
5478 /* VGPRs */
5479 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5480 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5481 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5482 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5483 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5484 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5485 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5486 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5487 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5488 break;
5489
5490 case PIPE_SHADER_FRAGMENT:
5491 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5492 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5493 last_sgpr = SI_PARAM_PRIM_MASK;
5494 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5495 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5496 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5497 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5498 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5499 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5500 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5501 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5502 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5503 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5504 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5505 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5506 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5507 shader->info.face_vgpr_index = 20;
5508 params[SI_PARAM_ANCILLARY] = ctx->i32;
5509 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5510 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5511 num_params = SI_PARAM_POS_FIXED_PT+1;
5512
5513 /* Color inputs from the prolog. */
5514 if (shader->selector->info.colors_read) {
5515 unsigned num_color_elements =
5516 util_bitcount(shader->selector->info.colors_read);
5517
5518 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5519 for (i = 0; i < num_color_elements; i++)
5520 params[num_params++] = ctx->f32;
5521
5522 num_prolog_vgprs += num_color_elements;
5523 }
5524
5525 /* Outputs for the epilog. */
5526 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5527 num_returns =
5528 num_return_sgprs +
5529 util_bitcount(shader->selector->info.colors_written) * 4 +
5530 shader->selector->info.writes_z +
5531 shader->selector->info.writes_stencil +
5532 shader->selector->info.writes_samplemask +
5533 1 /* SampleMaskIn */;
5534
5535 num_returns = MAX2(num_returns,
5536 num_return_sgprs +
5537 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5538
5539 for (i = 0; i < num_return_sgprs; i++)
5540 returns[i] = ctx->i32;
5541 for (; i < num_returns; i++)
5542 returns[i] = ctx->f32;
5543 break;
5544
5545 case PIPE_SHADER_COMPUTE:
5546 params[SI_PARAM_GRID_SIZE] = v3i32;
5547 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5548 params[SI_PARAM_BLOCK_ID] = v3i32;
5549 last_sgpr = SI_PARAM_BLOCK_ID;
5550
5551 params[SI_PARAM_THREAD_ID] = v3i32;
5552 num_params = SI_PARAM_THREAD_ID + 1;
5553 break;
5554 default:
5555 assert(0 && "unimplemented shader");
5556 return;
5557 }
5558
5559 assert(num_params <= ARRAY_SIZE(params));
5560
5561 si_create_function(ctx, "main", returns, num_returns, params,
5562 num_params, last_sgpr);
5563
5564 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5565 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5566 ctx->separate_prolog) {
5567 si_llvm_add_attribute(ctx->main_fn,
5568 "InitialPSInputAddr",
5569 S_0286D0_PERSP_SAMPLE_ENA(1) |
5570 S_0286D0_PERSP_CENTER_ENA(1) |
5571 S_0286D0_PERSP_CENTROID_ENA(1) |
5572 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5573 S_0286D0_LINEAR_CENTER_ENA(1) |
5574 S_0286D0_LINEAR_CENTROID_ENA(1) |
5575 S_0286D0_FRONT_FACE_ENA(1) |
5576 S_0286D0_POS_FIXED_PT_ENA(1));
5577 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5578 si_llvm_add_attribute(ctx->main_fn,
5579 "amdgpu-max-work-group-size",
5580 si_get_max_workgroup_size(shader));
5581 }
5582
5583 shader->info.num_input_sgprs = 0;
5584 shader->info.num_input_vgprs = 0;
5585
5586 for (i = 0; i <= last_sgpr; ++i)
5587 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5588
5589 for (; i < num_params; ++i)
5590 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5591
5592 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5593 shader->info.num_input_vgprs -= num_prolog_vgprs;
5594
5595 if (!ctx->screen->has_ds_bpermute &&
5596 bld_base->info &&
5597 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5598 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5599 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5600 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5601 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5602 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5603 ctx->lds =
5604 LLVMAddGlobalInAddressSpace(gallivm->module,
5605 LLVMArrayType(ctx->i32, 64),
5606 "ddxy_lds",
5607 LOCAL_ADDR_SPACE);
5608
5609 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5610 ctx->type == PIPE_SHADER_TESS_CTRL)
5611 declare_tess_lds(ctx);
5612 }
5613
5614 /**
5615 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5616 * for later use.
5617 */
5618 static void preload_ring_buffers(struct si_shader_context *ctx)
5619 {
5620 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5621 LLVMBuilderRef builder = gallivm->builder;
5622
5623 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5624 SI_PARAM_RW_BUFFERS);
5625
5626 if ((ctx->type == PIPE_SHADER_VERTEX &&
5627 ctx->shader->key.as_es) ||
5628 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5629 ctx->shader->key.as_es) ||
5630 ctx->type == PIPE_SHADER_GEOMETRY) {
5631 unsigned ring =
5632 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5633 : SI_ES_RING_ESGS;
5634 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5635
5636 ctx->esgs_ring =
5637 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5638 }
5639
5640 if (ctx->shader->is_gs_copy_shader) {
5641 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5642
5643 ctx->gsvs_ring[0] =
5644 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5645 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5646 const struct si_shader_selector *sel = ctx->shader->selector;
5647 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
5648 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5649 LLVMValueRef base_ring;
5650
5651 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5652
5653 /* The conceptual layout of the GSVS ring is
5654 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5655 * but the real memory layout is swizzled across
5656 * threads:
5657 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5658 * t16v0c0 ..
5659 * Override the buffer descriptor accordingly.
5660 */
5661 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5662 uint64_t stream_offset = 0;
5663
5664 for (unsigned stream = 0; stream < 4; ++stream) {
5665 unsigned num_components;
5666 unsigned stride;
5667 unsigned num_records;
5668 LLVMValueRef ring, tmp;
5669
5670 num_components = sel->info.num_stream_output_components[stream];
5671 if (!num_components)
5672 continue;
5673
5674 stride = 4 * num_components * sel->gs_max_out_vertices;
5675
5676 /* Limit on the stride field for <= CIK. */
5677 assert(stride < (1 << 14));
5678
5679 num_records = 64;
5680
5681 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5682 tmp = LLVMBuildExtractElement(builder, ring, uint->zero, "");
5683 tmp = LLVMBuildAdd(builder, tmp,
5684 LLVMConstInt(ctx->i64,
5685 stream_offset, 0), "");
5686 stream_offset += stride * 64;
5687
5688 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->zero, "");
5689 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5690 tmp = LLVMBuildExtractElement(builder, ring, uint->one, "");
5691 tmp = LLVMBuildOr(builder, tmp,
5692 LLVMConstInt(ctx->i32,
5693 S_008F04_STRIDE(stride) |
5694 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5695 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->one, "");
5696 ring = LLVMBuildInsertElement(builder, ring,
5697 LLVMConstInt(ctx->i32, num_records, 0),
5698 LLVMConstInt(ctx->i32, 2, 0), "");
5699 ring = LLVMBuildInsertElement(builder, ring,
5700 LLVMConstInt(ctx->i32,
5701 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5702 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5703 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5704 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5705 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5706 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5707 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5708 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5709 S_008F0C_ADD_TID_ENABLE(1),
5710 0),
5711 LLVMConstInt(ctx->i32, 3, 0), "");
5712 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5713
5714 ctx->gsvs_ring[stream] = ring;
5715 }
5716 }
5717 }
5718
5719 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5720 LLVMValueRef param_rw_buffers,
5721 unsigned param_pos_fixed_pt)
5722 {
5723 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5724 struct gallivm_state *gallivm = bld_base->base.gallivm;
5725 LLVMBuilderRef builder = gallivm->builder;
5726 LLVMValueRef slot, desc, offset, row, bit, address[2];
5727
5728 /* Use the fixed-point gl_FragCoord input.
5729 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5730 * per coordinate to get the repeating effect.
5731 */
5732 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5733 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5734
5735 /* Load the buffer descriptor. */
5736 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5737 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5738
5739 /* The stipple pattern is 32x32, each row has 32 bits. */
5740 offset = LLVMBuildMul(builder, address[1],
5741 LLVMConstInt(ctx->i32, 4, 0), "");
5742 row = buffer_load_const(ctx, desc, offset);
5743 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5744 bit = LLVMBuildLShr(builder, row, address[0], "");
5745 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5746
5747 /* The intrinsic kills the thread if arg < 0. */
5748 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5749 LLVMConstReal(ctx->f32, -1), "");
5750 ac_build_kill(&ctx->ac, bit);
5751 }
5752
5753 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5754 struct si_shader_config *conf,
5755 unsigned symbol_offset)
5756 {
5757 unsigned i;
5758 const unsigned char *config =
5759 ac_shader_binary_config_start(binary, symbol_offset);
5760 bool really_needs_scratch = false;
5761
5762 /* LLVM adds SGPR spills to the scratch size.
5763 * Find out if we really need the scratch buffer.
5764 */
5765 for (i = 0; i < binary->reloc_count; i++) {
5766 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5767
5768 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5769 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5770 really_needs_scratch = true;
5771 break;
5772 }
5773 }
5774
5775 /* XXX: We may be able to emit some of these values directly rather than
5776 * extracting fields to be emitted later.
5777 */
5778
5779 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5780 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5781 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5782 switch (reg) {
5783 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5784 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5785 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5786 case R_00B848_COMPUTE_PGM_RSRC1:
5787 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5788 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5789 conf->float_mode = G_00B028_FLOAT_MODE(value);
5790 conf->rsrc1 = value;
5791 break;
5792 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5793 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5794 break;
5795 case R_00B84C_COMPUTE_PGM_RSRC2:
5796 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5797 conf->rsrc2 = value;
5798 break;
5799 case R_0286CC_SPI_PS_INPUT_ENA:
5800 conf->spi_ps_input_ena = value;
5801 break;
5802 case R_0286D0_SPI_PS_INPUT_ADDR:
5803 conf->spi_ps_input_addr = value;
5804 break;
5805 case R_0286E8_SPI_TMPRING_SIZE:
5806 case R_00B860_COMPUTE_TMPRING_SIZE:
5807 /* WAVESIZE is in units of 256 dwords. */
5808 if (really_needs_scratch)
5809 conf->scratch_bytes_per_wave =
5810 G_00B860_WAVESIZE(value) * 256 * 4;
5811 break;
5812 case 0x4: /* SPILLED_SGPRS */
5813 conf->spilled_sgprs = value;
5814 break;
5815 case 0x8: /* SPILLED_VGPRS */
5816 conf->spilled_vgprs = value;
5817 break;
5818 default:
5819 {
5820 static bool printed;
5821
5822 if (!printed) {
5823 fprintf(stderr, "Warning: LLVM emitted unknown "
5824 "config register: 0x%x\n", reg);
5825 printed = true;
5826 }
5827 }
5828 break;
5829 }
5830 }
5831
5832 if (!conf->spi_ps_input_addr)
5833 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5834 }
5835
5836 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5837 struct si_shader *shader,
5838 struct si_shader_config *config,
5839 uint64_t scratch_va)
5840 {
5841 unsigned i;
5842 uint32_t scratch_rsrc_dword0 = scratch_va;
5843 uint32_t scratch_rsrc_dword1 =
5844 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5845
5846 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5847 * correctly.
5848 */
5849 if (HAVE_LLVM >= 0x0309)
5850 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5851 else
5852 scratch_rsrc_dword1 |=
5853 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5854
5855 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5856 const struct ac_shader_reloc *reloc =
5857 &shader->binary.relocs[i];
5858 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5859 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5860 &scratch_rsrc_dword0, 4);
5861 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5862 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5863 &scratch_rsrc_dword1, 4);
5864 }
5865 }
5866 }
5867
5868 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5869 {
5870 unsigned size = shader->binary.code_size;
5871
5872 if (shader->prolog)
5873 size += shader->prolog->binary.code_size;
5874 if (shader->epilog)
5875 size += shader->epilog->binary.code_size;
5876 return size;
5877 }
5878
5879 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5880 {
5881 const struct ac_shader_binary *prolog =
5882 shader->prolog ? &shader->prolog->binary : NULL;
5883 const struct ac_shader_binary *epilog =
5884 shader->epilog ? &shader->epilog->binary : NULL;
5885 const struct ac_shader_binary *mainb = &shader->binary;
5886 unsigned bo_size = si_get_shader_binary_size(shader) +
5887 (!epilog ? mainb->rodata_size : 0);
5888 unsigned char *ptr;
5889
5890 assert(!prolog || !prolog->rodata_size);
5891 assert((!prolog && !epilog) || !mainb->rodata_size);
5892 assert(!epilog || !epilog->rodata_size);
5893
5894 r600_resource_reference(&shader->bo, NULL);
5895 shader->bo = (struct r600_resource*)
5896 pipe_buffer_create(&sscreen->b.b, 0,
5897 PIPE_USAGE_IMMUTABLE,
5898 align(bo_size, SI_CPDMA_ALIGNMENT));
5899 if (!shader->bo)
5900 return -ENOMEM;
5901
5902 /* Upload. */
5903 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5904 PIPE_TRANSFER_READ_WRITE);
5905
5906 if (prolog) {
5907 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5908 ptr += prolog->code_size;
5909 }
5910
5911 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5912 ptr += mainb->code_size;
5913
5914 if (epilog)
5915 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5916 else if (mainb->rodata_size > 0)
5917 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5918
5919 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5920 return 0;
5921 }
5922
5923 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5924 struct pipe_debug_callback *debug,
5925 const char *name, FILE *file)
5926 {
5927 char *line, *p;
5928 unsigned i, count;
5929
5930 if (binary->disasm_string) {
5931 fprintf(file, "Shader %s disassembly:\n", name);
5932 fprintf(file, "%s", binary->disasm_string);
5933
5934 if (debug && debug->debug_message) {
5935 /* Very long debug messages are cut off, so send the
5936 * disassembly one line at a time. This causes more
5937 * overhead, but on the plus side it simplifies
5938 * parsing of resulting logs.
5939 */
5940 pipe_debug_message(debug, SHADER_INFO,
5941 "Shader Disassembly Begin");
5942
5943 line = binary->disasm_string;
5944 while (*line) {
5945 p = util_strchrnul(line, '\n');
5946 count = p - line;
5947
5948 if (count) {
5949 pipe_debug_message(debug, SHADER_INFO,
5950 "%.*s", count, line);
5951 }
5952
5953 if (!*p)
5954 break;
5955 line = p + 1;
5956 }
5957
5958 pipe_debug_message(debug, SHADER_INFO,
5959 "Shader Disassembly End");
5960 }
5961 } else {
5962 fprintf(file, "Shader %s binary:\n", name);
5963 for (i = 0; i < binary->code_size; i += 4) {
5964 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5965 binary->code[i + 3], binary->code[i + 2],
5966 binary->code[i + 1], binary->code[i]);
5967 }
5968 }
5969 }
5970
5971 static void si_shader_dump_stats(struct si_screen *sscreen,
5972 struct si_shader *shader,
5973 struct pipe_debug_callback *debug,
5974 unsigned processor,
5975 FILE *file,
5976 bool check_debug_option)
5977 {
5978 struct si_shader_config *conf = &shader->config;
5979 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5980 unsigned code_size = si_get_shader_binary_size(shader);
5981 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5982 unsigned lds_per_wave = 0;
5983 unsigned max_simd_waves = 10;
5984
5985 /* Compute LDS usage for PS. */
5986 switch (processor) {
5987 case PIPE_SHADER_FRAGMENT:
5988 /* The minimum usage per wave is (num_inputs * 48). The maximum
5989 * usage is (num_inputs * 48 * 16).
5990 * We can get anything in between and it varies between waves.
5991 *
5992 * The 48 bytes per input for a single primitive is equal to
5993 * 4 bytes/component * 4 components/input * 3 points.
5994 *
5995 * Other stages don't know the size at compile time or don't
5996 * allocate LDS per wave, but instead they do it per thread group.
5997 */
5998 lds_per_wave = conf->lds_size * lds_increment +
5999 align(num_inputs * 48, lds_increment);
6000 break;
6001 case PIPE_SHADER_COMPUTE:
6002 if (shader->selector) {
6003 unsigned max_workgroup_size =
6004 si_get_max_workgroup_size(shader);
6005 lds_per_wave = (conf->lds_size * lds_increment) /
6006 DIV_ROUND_UP(max_workgroup_size, 64);
6007 }
6008 break;
6009 }
6010
6011 /* Compute the per-SIMD wave counts. */
6012 if (conf->num_sgprs) {
6013 if (sscreen->b.chip_class >= VI)
6014 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6015 else
6016 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6017 }
6018
6019 if (conf->num_vgprs)
6020 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6021
6022 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6023 * 16KB makes some SIMDs unoccupied). */
6024 if (lds_per_wave)
6025 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6026
6027 if (!check_debug_option ||
6028 r600_can_dump_shader(&sscreen->b, processor)) {
6029 if (processor == PIPE_SHADER_FRAGMENT) {
6030 fprintf(file, "*** SHADER CONFIG ***\n"
6031 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6032 "SPI_PS_INPUT_ENA = 0x%04x\n",
6033 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6034 }
6035
6036 fprintf(file, "*** SHADER STATS ***\n"
6037 "SGPRS: %d\n"
6038 "VGPRS: %d\n"
6039 "Spilled SGPRs: %d\n"
6040 "Spilled VGPRs: %d\n"
6041 "Private memory VGPRs: %d\n"
6042 "Code Size: %d bytes\n"
6043 "LDS: %d blocks\n"
6044 "Scratch: %d bytes per wave\n"
6045 "Max Waves: %d\n"
6046 "********************\n\n\n",
6047 conf->num_sgprs, conf->num_vgprs,
6048 conf->spilled_sgprs, conf->spilled_vgprs,
6049 conf->private_mem_vgprs, code_size,
6050 conf->lds_size, conf->scratch_bytes_per_wave,
6051 max_simd_waves);
6052 }
6053
6054 pipe_debug_message(debug, SHADER_INFO,
6055 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6056 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6057 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6058 conf->num_sgprs, conf->num_vgprs, code_size,
6059 conf->lds_size, conf->scratch_bytes_per_wave,
6060 max_simd_waves, conf->spilled_sgprs,
6061 conf->spilled_vgprs, conf->private_mem_vgprs);
6062 }
6063
6064 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6065 {
6066 switch (processor) {
6067 case PIPE_SHADER_VERTEX:
6068 if (shader->key.as_es)
6069 return "Vertex Shader as ES";
6070 else if (shader->key.as_ls)
6071 return "Vertex Shader as LS";
6072 else
6073 return "Vertex Shader as VS";
6074 case PIPE_SHADER_TESS_CTRL:
6075 return "Tessellation Control Shader";
6076 case PIPE_SHADER_TESS_EVAL:
6077 if (shader->key.as_es)
6078 return "Tessellation Evaluation Shader as ES";
6079 else
6080 return "Tessellation Evaluation Shader as VS";
6081 case PIPE_SHADER_GEOMETRY:
6082 if (shader->is_gs_copy_shader)
6083 return "GS Copy Shader as VS";
6084 else
6085 return "Geometry Shader";
6086 case PIPE_SHADER_FRAGMENT:
6087 return "Pixel Shader";
6088 case PIPE_SHADER_COMPUTE:
6089 return "Compute Shader";
6090 default:
6091 return "Unknown Shader";
6092 }
6093 }
6094
6095 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6096 struct pipe_debug_callback *debug, unsigned processor,
6097 FILE *file, bool check_debug_option)
6098 {
6099 if (!check_debug_option ||
6100 r600_can_dump_shader(&sscreen->b, processor))
6101 si_dump_shader_key(processor, &shader->key, file);
6102
6103 if (!check_debug_option && shader->binary.llvm_ir_string) {
6104 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6105 si_get_shader_name(shader, processor));
6106 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6107 }
6108
6109 if (!check_debug_option ||
6110 (r600_can_dump_shader(&sscreen->b, processor) &&
6111 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6112 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6113
6114 if (shader->prolog)
6115 si_shader_dump_disassembly(&shader->prolog->binary,
6116 debug, "prolog", file);
6117
6118 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6119
6120 if (shader->epilog)
6121 si_shader_dump_disassembly(&shader->epilog->binary,
6122 debug, "epilog", file);
6123 fprintf(file, "\n");
6124 }
6125
6126 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6127 check_debug_option);
6128 }
6129
6130 int si_compile_llvm(struct si_screen *sscreen,
6131 struct ac_shader_binary *binary,
6132 struct si_shader_config *conf,
6133 LLVMTargetMachineRef tm,
6134 LLVMModuleRef mod,
6135 struct pipe_debug_callback *debug,
6136 unsigned processor,
6137 const char *name)
6138 {
6139 int r = 0;
6140 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6141
6142 if (r600_can_dump_shader(&sscreen->b, processor)) {
6143 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6144
6145 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6146 fprintf(stderr, "%s LLVM IR:\n\n", name);
6147 ac_dump_module(mod);
6148 fprintf(stderr, "\n");
6149 }
6150 }
6151
6152 if (sscreen->record_llvm_ir) {
6153 char *ir = LLVMPrintModuleToString(mod);
6154 binary->llvm_ir_string = strdup(ir);
6155 LLVMDisposeMessage(ir);
6156 }
6157
6158 if (!si_replace_shader(count, binary)) {
6159 r = si_llvm_compile(mod, binary, tm, debug);
6160 if (r)
6161 return r;
6162 }
6163
6164 si_shader_binary_read_config(binary, conf, 0);
6165
6166 /* Enable 64-bit and 16-bit denormals, because there is no performance
6167 * cost.
6168 *
6169 * If denormals are enabled, all floating-point output modifiers are
6170 * ignored.
6171 *
6172 * Don't enable denormals for 32-bit floats, because:
6173 * - Floating-point output modifiers would be ignored by the hw.
6174 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6175 * have to stop using those.
6176 * - SI & CI would be very slow.
6177 */
6178 conf->float_mode |= V_00B028_FP_64_DENORMS;
6179
6180 FREE(binary->config);
6181 FREE(binary->global_symbol_offsets);
6182 binary->config = NULL;
6183 binary->global_symbol_offsets = NULL;
6184
6185 /* Some shaders can't have rodata because their binaries can be
6186 * concatenated.
6187 */
6188 if (binary->rodata_size &&
6189 (processor == PIPE_SHADER_VERTEX ||
6190 processor == PIPE_SHADER_TESS_CTRL ||
6191 processor == PIPE_SHADER_TESS_EVAL ||
6192 processor == PIPE_SHADER_FRAGMENT)) {
6193 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6194 return -EINVAL;
6195 }
6196
6197 return r;
6198 }
6199
6200 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6201 {
6202 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6203 LLVMBuildRetVoid(ctx->gallivm.builder);
6204 else
6205 LLVMBuildRet(ctx->gallivm.builder, ret);
6206 }
6207
6208 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6209 struct si_shader *
6210 si_generate_gs_copy_shader(struct si_screen *sscreen,
6211 LLVMTargetMachineRef tm,
6212 struct si_shader_selector *gs_selector,
6213 struct pipe_debug_callback *debug)
6214 {
6215 struct si_shader_context ctx;
6216 struct si_shader *shader;
6217 struct gallivm_state *gallivm = &ctx.gallivm;
6218 LLVMBuilderRef builder;
6219 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6220 struct lp_build_context *uint = &bld_base->uint_bld;
6221 struct si_shader_output_values *outputs;
6222 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6223 int i, r;
6224
6225 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6226
6227 if (!outputs)
6228 return NULL;
6229
6230 shader = CALLOC_STRUCT(si_shader);
6231 if (!shader) {
6232 FREE(outputs);
6233 return NULL;
6234 }
6235
6236
6237 shader->selector = gs_selector;
6238 shader->is_gs_copy_shader = true;
6239
6240 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6241 ctx.type = PIPE_SHADER_VERTEX;
6242
6243 builder = gallivm->builder;
6244
6245 create_function(&ctx);
6246 preload_ring_buffers(&ctx);
6247
6248 LLVMValueRef voffset =
6249 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6250 ctx.param_vertex_id), 4);
6251
6252 /* Fetch the vertex stream ID.*/
6253 LLVMValueRef stream_id;
6254
6255 if (gs_selector->so.num_outputs)
6256 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6257 else
6258 stream_id = uint->zero;
6259
6260 /* Fill in output information. */
6261 for (i = 0; i < gsinfo->num_outputs; ++i) {
6262 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6263 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6264
6265 for (int chan = 0; chan < 4; chan++) {
6266 outputs[i].vertex_stream[chan] =
6267 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6268 }
6269 }
6270
6271 LLVMBasicBlockRef end_bb;
6272 LLVMValueRef switch_inst;
6273
6274 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6275 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6276
6277 for (int stream = 0; stream < 4; stream++) {
6278 LLVMBasicBlockRef bb;
6279 unsigned offset;
6280
6281 if (!gsinfo->num_stream_output_components[stream])
6282 continue;
6283
6284 if (stream > 0 && !gs_selector->so.num_outputs)
6285 continue;
6286
6287 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6288 LLVMAddCase(switch_inst, lp_build_const_int32(gallivm, stream), bb);
6289 LLVMPositionBuilderAtEnd(builder, bb);
6290
6291 /* Fetch vertex data from GSVS ring */
6292 offset = 0;
6293 for (i = 0; i < gsinfo->num_outputs; ++i) {
6294 for (unsigned chan = 0; chan < 4; chan++) {
6295 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6296 outputs[i].vertex_stream[chan] != stream) {
6297 outputs[i].values[chan] = ctx.bld_base.base.undef;
6298 continue;
6299 }
6300
6301 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6302 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6303 offset++;
6304
6305 outputs[i].values[chan] =
6306 ac_build_buffer_load(&ctx.ac,
6307 ctx.gsvs_ring[0], 1,
6308 uint->zero, voffset,
6309 soffset, 0, 1, 1, true);
6310 }
6311 }
6312
6313 /* Streamout and exports. */
6314 if (gs_selector->so.num_outputs) {
6315 si_llvm_emit_streamout(&ctx, outputs,
6316 gsinfo->num_outputs,
6317 stream);
6318 }
6319
6320 if (stream == 0)
6321 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6322
6323 LLVMBuildBr(builder, end_bb);
6324 }
6325
6326 LLVMPositionBuilderAtEnd(builder, end_bb);
6327
6328 LLVMBuildRetVoid(gallivm->builder);
6329
6330 /* Dump LLVM IR before any optimization passes */
6331 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6332 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6333 ac_dump_module(bld_base->base.gallivm->module);
6334
6335 si_llvm_finalize_module(&ctx,
6336 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6337
6338 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6339 &ctx.shader->config, ctx.tm,
6340 bld_base->base.gallivm->module,
6341 debug, PIPE_SHADER_GEOMETRY,
6342 "GS Copy Shader");
6343 if (!r) {
6344 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6345 fprintf(stderr, "GS Copy Shader:\n");
6346 si_shader_dump(sscreen, ctx.shader, debug,
6347 PIPE_SHADER_GEOMETRY, stderr, true);
6348 r = si_shader_binary_upload(sscreen, ctx.shader);
6349 }
6350
6351 si_llvm_dispose(&ctx);
6352
6353 FREE(outputs);
6354
6355 if (r != 0) {
6356 FREE(shader);
6357 shader = NULL;
6358 }
6359 return shader;
6360 }
6361
6362 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6363 FILE *f)
6364 {
6365 int i;
6366
6367 fprintf(f, "SHADER KEY\n");
6368
6369 switch (shader) {
6370 case PIPE_SHADER_VERTEX:
6371 fprintf(f, " part.vs.prolog.instance_divisors = {");
6372 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6373 fprintf(f, !i ? "%u" : ", %u",
6374 key->part.vs.prolog.instance_divisors[i]);
6375 fprintf(f, "}\n");
6376 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6377 fprintf(f, " as_es = %u\n", key->as_es);
6378 fprintf(f, " as_ls = %u\n", key->as_ls);
6379
6380 fprintf(f, " mono.vs.fix_fetch = {");
6381 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6382 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6383 fprintf(f, "}\n");
6384 break;
6385
6386 case PIPE_SHADER_TESS_CTRL:
6387 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6388 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6389 break;
6390
6391 case PIPE_SHADER_TESS_EVAL:
6392 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6393 fprintf(f, " as_es = %u\n", key->as_es);
6394 break;
6395
6396 case PIPE_SHADER_GEOMETRY:
6397 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6398 break;
6399
6400 case PIPE_SHADER_COMPUTE:
6401 break;
6402
6403 case PIPE_SHADER_FRAGMENT:
6404 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6405 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6406 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6407 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6408 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6409 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6410 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6411 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6412 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6413 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6414 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6415 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6416 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6417 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6418 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6419 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6420 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6421 break;
6422
6423 default:
6424 assert(0);
6425 }
6426
6427 if ((shader == PIPE_SHADER_GEOMETRY ||
6428 shader == PIPE_SHADER_TESS_EVAL ||
6429 shader == PIPE_SHADER_VERTEX) &&
6430 !key->as_es && !key->as_ls) {
6431 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6432 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6433 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6434 }
6435 }
6436
6437 static void si_init_shader_ctx(struct si_shader_context *ctx,
6438 struct si_screen *sscreen,
6439 struct si_shader *shader,
6440 LLVMTargetMachineRef tm)
6441 {
6442 struct lp_build_tgsi_context *bld_base;
6443 struct lp_build_tgsi_action tmpl = {};
6444
6445 si_llvm_context_init(ctx, sscreen, shader, tm,
6446 (shader && shader->selector) ? &shader->selector->info : NULL,
6447 (shader && shader->selector) ? shader->selector->tokens : NULL);
6448
6449 bld_base = &ctx->bld_base;
6450 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6451
6452 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6453 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6454 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6455
6456 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6457 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6458 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6459 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6460 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6461 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6462 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6463 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6464 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6465 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6466 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6467 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6468 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6469 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6470
6471 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6472 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6473 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6474 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6475 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6476 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6477
6478 tmpl.fetch_args = atomic_fetch_args;
6479 tmpl.emit = atomic_emit;
6480 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6481 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6482 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6483 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6484 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6485 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6486 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6487 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6488 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6489 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6490 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6491 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6492 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6493 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6494 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6495 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6496 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6497 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6498 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6499 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6500
6501 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6502
6503 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6504 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6505 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6506 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6507
6508 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6509 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6510 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6511 }
6512
6513 /* Return true if the PARAM export has been eliminated. */
6514 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6515 LLVMValueRef inst, unsigned offset)
6516 {
6517 struct si_shader *shader = ctx->shader;
6518 unsigned num_outputs = shader->selector->info.num_outputs;
6519 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6520 bool is_zero[4] = {}, is_one[4] = {};
6521
6522 for (i = 0; i < 4; i++) {
6523 LLVMBool loses_info;
6524 LLVMValueRef p = LLVMGetOperand(inst, (HAVE_LLVM >= 0x0500 ? 2 : 5) + i);
6525
6526 /* It's a constant expression. Undef outputs are eliminated too. */
6527 if (LLVMIsUndef(p)) {
6528 is_zero[i] = true;
6529 is_one[i] = true;
6530 } else if (LLVMIsAConstantFP(p)) {
6531 double a = LLVMConstRealGetDouble(p, &loses_info);
6532
6533 if (a == 0)
6534 is_zero[i] = true;
6535 else if (a == 1)
6536 is_one[i] = true;
6537 else
6538 return false; /* other constant */
6539 } else
6540 return false;
6541 }
6542
6543 /* Only certain combinations of 0 and 1 can be eliminated. */
6544 if (is_zero[0] && is_zero[1] && is_zero[2])
6545 default_val = is_zero[3] ? 0 : 1;
6546 else if (is_one[0] && is_one[1] && is_one[2])
6547 default_val = is_zero[3] ? 2 : 3;
6548 else
6549 return false;
6550
6551 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6552 LLVMInstructionEraseFromParent(inst);
6553
6554 /* Change OFFSET to DEFAULT_VAL. */
6555 for (i = 0; i < num_outputs; i++) {
6556 if (shader->info.vs_output_param_offset[i] == offset) {
6557 shader->info.vs_output_param_offset[i] =
6558 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6559 break;
6560 }
6561 }
6562 return true;
6563 }
6564
6565 struct si_vs_exports {
6566 unsigned num;
6567 unsigned offset[SI_MAX_VS_OUTPUTS];
6568 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6569 };
6570
6571 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6572 {
6573 struct si_shader *shader = ctx->shader;
6574 struct tgsi_shader_info *info = &shader->selector->info;
6575 LLVMBasicBlockRef bb;
6576 struct si_vs_exports exports;
6577 bool removed_any = false;
6578
6579 exports.num = 0;
6580
6581 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6582 ctx->type == PIPE_SHADER_COMPUTE ||
6583 shader->key.as_es ||
6584 shader->key.as_ls)
6585 return;
6586
6587 /* Process all LLVM instructions. */
6588 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6589 while (bb) {
6590 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6591
6592 while (inst) {
6593 LLVMValueRef cur = inst;
6594 inst = LLVMGetNextInstruction(inst);
6595
6596 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6597 continue;
6598
6599 LLVMValueRef callee = lp_get_called_value(cur);
6600
6601 if (!lp_is_function(callee))
6602 continue;
6603
6604 const char *name = LLVMGetValueName(callee);
6605 unsigned num_args = LLVMCountParams(callee);
6606
6607 /* Check if this is an export instruction. */
6608 if ((num_args != 9 && num_args != 8) ||
6609 (strcmp(name, "llvm.SI.export") &&
6610 strcmp(name, "llvm.amdgcn.exp.")))
6611 continue;
6612
6613 LLVMValueRef arg = LLVMGetOperand(cur, HAVE_LLVM >= 0x0500 ? 0 : 3);
6614 unsigned target = LLVMConstIntGetZExtValue(arg);
6615
6616 if (target < V_008DFC_SQ_EXP_PARAM)
6617 continue;
6618
6619 target -= V_008DFC_SQ_EXP_PARAM;
6620
6621 /* Eliminate constant value PARAM exports. */
6622 if (si_eliminate_const_output(ctx, cur, target)) {
6623 removed_any = true;
6624 } else {
6625 exports.offset[exports.num] = target;
6626 exports.inst[exports.num] = cur;
6627 exports.num++;
6628 }
6629 }
6630 bb = LLVMGetNextBasicBlock(bb);
6631 }
6632
6633 /* Remove holes in export memory due to removed PARAM exports.
6634 * This is done by renumbering all PARAM exports.
6635 */
6636 if (removed_any) {
6637 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6638 unsigned new_count = 0;
6639 unsigned out, i;
6640
6641 /* Make a copy of the offsets. We need the old version while
6642 * we are modifying some of them. */
6643 assert(sizeof(current_offset) ==
6644 sizeof(shader->info.vs_output_param_offset));
6645 memcpy(current_offset, shader->info.vs_output_param_offset,
6646 sizeof(current_offset));
6647
6648 for (i = 0; i < exports.num; i++) {
6649 unsigned offset = exports.offset[i];
6650
6651 for (out = 0; out < info->num_outputs; out++) {
6652 if (current_offset[out] != offset)
6653 continue;
6654
6655 LLVMSetOperand(exports.inst[i], 3,
6656 LLVMConstInt(ctx->i32,
6657 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6658 shader->info.vs_output_param_offset[out] = new_count;
6659 new_count++;
6660 break;
6661 }
6662 }
6663 shader->info.nr_param_exports = new_count;
6664 }
6665 }
6666
6667 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6668 {
6669 ctx->shader->config.private_mem_vgprs = 0;
6670
6671 /* Process all LLVM instructions. */
6672 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6673 while (bb) {
6674 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6675
6676 while (next) {
6677 LLVMValueRef inst = next;
6678 next = LLVMGetNextInstruction(next);
6679
6680 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6681 continue;
6682
6683 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6684 /* No idea why LLVM aligns allocas to 4 elements. */
6685 unsigned alignment = LLVMGetAlignment(inst);
6686 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6687 ctx->shader->config.private_mem_vgprs += dw_size;
6688 }
6689 bb = LLVMGetNextBasicBlock(bb);
6690 }
6691 }
6692
6693 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6694 struct si_shader *shader)
6695 {
6696 struct si_shader_selector *sel = shader->selector;
6697 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6698
6699 switch (ctx->type) {
6700 case PIPE_SHADER_VERTEX:
6701 ctx->load_input = declare_input_vs;
6702 if (shader->key.as_ls)
6703 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6704 else if (shader->key.as_es)
6705 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6706 else
6707 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6708 break;
6709 case PIPE_SHADER_TESS_CTRL:
6710 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6711 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6712 bld_base->emit_store = store_output_tcs;
6713 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6714 break;
6715 case PIPE_SHADER_TESS_EVAL:
6716 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6717 if (shader->key.as_es)
6718 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6719 else
6720 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6721 break;
6722 case PIPE_SHADER_GEOMETRY:
6723 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6724 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6725 break;
6726 case PIPE_SHADER_FRAGMENT:
6727 ctx->load_input = declare_input_fs;
6728 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6729 break;
6730 case PIPE_SHADER_COMPUTE:
6731 ctx->declare_memory_region = declare_compute_memory;
6732 break;
6733 default:
6734 assert(!"Unsupported shader type");
6735 return false;
6736 }
6737
6738 create_function(ctx);
6739 preload_ring_buffers(ctx);
6740
6741 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6742 int i;
6743 for (i = 0; i < 4; i++) {
6744 ctx->gs_next_vertex[i] =
6745 lp_build_alloca(bld_base->base.gallivm,
6746 ctx->i32, "");
6747 }
6748 }
6749
6750 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6751 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6752 return false;
6753 }
6754
6755 si_llvm_build_ret(ctx, ctx->return_value);
6756 return true;
6757 }
6758
6759 /**
6760 * Compute the VS prolog key, which contains all the information needed to
6761 * build the VS prolog function, and set shader->info bits where needed.
6762 */
6763 static void si_get_vs_prolog_key(struct si_shader *shader,
6764 union si_shader_part_key *key)
6765 {
6766 struct tgsi_shader_info *info = &shader->selector->info;
6767
6768 memset(key, 0, sizeof(*key));
6769 key->vs_prolog.states = shader->key.part.vs.prolog;
6770 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6771 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6772
6773 /* Set the instanceID flag. */
6774 for (unsigned i = 0; i < info->num_inputs; i++)
6775 if (key->vs_prolog.states.instance_divisors[i])
6776 shader->info.uses_instanceid = true;
6777 }
6778
6779 /**
6780 * Compute the VS epilog key, which contains all the information needed to
6781 * build the VS epilog function, and set the PrimitiveID output offset.
6782 */
6783 static void si_get_vs_epilog_key(struct si_shader *shader,
6784 struct si_vs_epilog_bits *states,
6785 union si_shader_part_key *key)
6786 {
6787 memset(key, 0, sizeof(*key));
6788 key->vs_epilog.states = *states;
6789
6790 /* Set up the PrimitiveID output. */
6791 if (shader->key.part.vs.epilog.export_prim_id) {
6792 unsigned index = shader->selector->info.num_outputs;
6793 unsigned offset = shader->info.nr_param_exports++;
6794
6795 key->vs_epilog.prim_id_param_offset = offset;
6796 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6797 shader->info.vs_output_param_offset[index] = offset;
6798 }
6799 }
6800
6801 /**
6802 * Compute the PS prolog key, which contains all the information needed to
6803 * build the PS prolog function, and set related bits in shader->config.
6804 */
6805 static void si_get_ps_prolog_key(struct si_shader *shader,
6806 union si_shader_part_key *key,
6807 bool separate_prolog)
6808 {
6809 struct tgsi_shader_info *info = &shader->selector->info;
6810
6811 memset(key, 0, sizeof(*key));
6812 key->ps_prolog.states = shader->key.part.ps.prolog;
6813 key->ps_prolog.colors_read = info->colors_read;
6814 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6815 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6816 key->ps_prolog.wqm = info->uses_derivatives &&
6817 (key->ps_prolog.colors_read ||
6818 key->ps_prolog.states.force_persp_sample_interp ||
6819 key->ps_prolog.states.force_linear_sample_interp ||
6820 key->ps_prolog.states.force_persp_center_interp ||
6821 key->ps_prolog.states.force_linear_center_interp ||
6822 key->ps_prolog.states.bc_optimize_for_persp ||
6823 key->ps_prolog.states.bc_optimize_for_linear);
6824
6825 if (info->colors_read) {
6826 unsigned *color = shader->selector->color_attr_index;
6827
6828 if (shader->key.part.ps.prolog.color_two_side) {
6829 /* BCOLORs are stored after the last input. */
6830 key->ps_prolog.num_interp_inputs = info->num_inputs;
6831 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6832 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6833 }
6834
6835 for (unsigned i = 0; i < 2; i++) {
6836 unsigned interp = info->input_interpolate[color[i]];
6837 unsigned location = info->input_interpolate_loc[color[i]];
6838
6839 if (!(info->colors_read & (0xf << i*4)))
6840 continue;
6841
6842 key->ps_prolog.color_attr_index[i] = color[i];
6843
6844 if (shader->key.part.ps.prolog.flatshade_colors &&
6845 interp == TGSI_INTERPOLATE_COLOR)
6846 interp = TGSI_INTERPOLATE_CONSTANT;
6847
6848 switch (interp) {
6849 case TGSI_INTERPOLATE_CONSTANT:
6850 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6851 break;
6852 case TGSI_INTERPOLATE_PERSPECTIVE:
6853 case TGSI_INTERPOLATE_COLOR:
6854 /* Force the interpolation location for colors here. */
6855 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6856 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6857 if (shader->key.part.ps.prolog.force_persp_center_interp)
6858 location = TGSI_INTERPOLATE_LOC_CENTER;
6859
6860 switch (location) {
6861 case TGSI_INTERPOLATE_LOC_SAMPLE:
6862 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6863 shader->config.spi_ps_input_ena |=
6864 S_0286CC_PERSP_SAMPLE_ENA(1);
6865 break;
6866 case TGSI_INTERPOLATE_LOC_CENTER:
6867 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6868 shader->config.spi_ps_input_ena |=
6869 S_0286CC_PERSP_CENTER_ENA(1);
6870 break;
6871 case TGSI_INTERPOLATE_LOC_CENTROID:
6872 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6873 shader->config.spi_ps_input_ena |=
6874 S_0286CC_PERSP_CENTROID_ENA(1);
6875 break;
6876 default:
6877 assert(0);
6878 }
6879 break;
6880 case TGSI_INTERPOLATE_LINEAR:
6881 /* Force the interpolation location for colors here. */
6882 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6883 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6884 if (shader->key.part.ps.prolog.force_linear_center_interp)
6885 location = TGSI_INTERPOLATE_LOC_CENTER;
6886
6887 /* The VGPR assignment for non-monolithic shaders
6888 * works because InitialPSInputAddr is set on the
6889 * main shader and PERSP_PULL_MODEL is never used.
6890 */
6891 switch (location) {
6892 case TGSI_INTERPOLATE_LOC_SAMPLE:
6893 key->ps_prolog.color_interp_vgpr_index[i] =
6894 separate_prolog ? 6 : 9;
6895 shader->config.spi_ps_input_ena |=
6896 S_0286CC_LINEAR_SAMPLE_ENA(1);
6897 break;
6898 case TGSI_INTERPOLATE_LOC_CENTER:
6899 key->ps_prolog.color_interp_vgpr_index[i] =
6900 separate_prolog ? 8 : 11;
6901 shader->config.spi_ps_input_ena |=
6902 S_0286CC_LINEAR_CENTER_ENA(1);
6903 break;
6904 case TGSI_INTERPOLATE_LOC_CENTROID:
6905 key->ps_prolog.color_interp_vgpr_index[i] =
6906 separate_prolog ? 10 : 13;
6907 shader->config.spi_ps_input_ena |=
6908 S_0286CC_LINEAR_CENTROID_ENA(1);
6909 break;
6910 default:
6911 assert(0);
6912 }
6913 break;
6914 default:
6915 assert(0);
6916 }
6917 }
6918 }
6919 }
6920
6921 /**
6922 * Check whether a PS prolog is required based on the key.
6923 */
6924 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6925 {
6926 return key->ps_prolog.colors_read ||
6927 key->ps_prolog.states.force_persp_sample_interp ||
6928 key->ps_prolog.states.force_linear_sample_interp ||
6929 key->ps_prolog.states.force_persp_center_interp ||
6930 key->ps_prolog.states.force_linear_center_interp ||
6931 key->ps_prolog.states.bc_optimize_for_persp ||
6932 key->ps_prolog.states.bc_optimize_for_linear ||
6933 key->ps_prolog.states.poly_stipple;
6934 }
6935
6936 /**
6937 * Compute the PS epilog key, which contains all the information needed to
6938 * build the PS epilog function.
6939 */
6940 static void si_get_ps_epilog_key(struct si_shader *shader,
6941 union si_shader_part_key *key)
6942 {
6943 struct tgsi_shader_info *info = &shader->selector->info;
6944 memset(key, 0, sizeof(*key));
6945 key->ps_epilog.colors_written = info->colors_written;
6946 key->ps_epilog.writes_z = info->writes_z;
6947 key->ps_epilog.writes_stencil = info->writes_stencil;
6948 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6949 key->ps_epilog.states = shader->key.part.ps.epilog;
6950 }
6951
6952 /**
6953 * Build the GS prolog function. Rotate the input vertices for triangle strips
6954 * with adjacency.
6955 */
6956 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6957 union si_shader_part_key *key)
6958 {
6959 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6960 const unsigned num_vgprs = 8;
6961 struct gallivm_state *gallivm = &ctx->gallivm;
6962 LLVMBuilderRef builder = gallivm->builder;
6963 LLVMTypeRef params[32];
6964 LLVMTypeRef returns[32];
6965 LLVMValueRef func, ret;
6966
6967 for (unsigned i = 0; i < num_sgprs; ++i) {
6968 params[i] = ctx->i32;
6969 returns[i] = ctx->i32;
6970 }
6971
6972 for (unsigned i = 0; i < num_vgprs; ++i) {
6973 params[num_sgprs + i] = ctx->i32;
6974 returns[num_sgprs + i] = ctx->f32;
6975 }
6976
6977 /* Create the function. */
6978 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6979 params, num_sgprs + num_vgprs, num_sgprs - 1);
6980 func = ctx->main_fn;
6981
6982 /* Copy inputs to outputs. This should be no-op, as the registers match,
6983 * but it will prevent the compiler from overwriting them unintentionally.
6984 */
6985 ret = ctx->return_value;
6986 for (unsigned i = 0; i < num_sgprs; i++) {
6987 LLVMValueRef p = LLVMGetParam(func, i);
6988 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6989 }
6990 for (unsigned i = 0; i < num_vgprs; i++) {
6991 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6992 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6993 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6994 }
6995
6996 if (key->gs_prolog.states.tri_strip_adj_fix) {
6997 /* Remap the input vertices for every other primitive. */
6998 const unsigned vtx_params[6] = {
6999 num_sgprs,
7000 num_sgprs + 1,
7001 num_sgprs + 3,
7002 num_sgprs + 4,
7003 num_sgprs + 5,
7004 num_sgprs + 6
7005 };
7006 LLVMValueRef prim_id, rotate;
7007
7008 prim_id = LLVMGetParam(func, num_sgprs + 2);
7009 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7010
7011 for (unsigned i = 0; i < 6; ++i) {
7012 LLVMValueRef base, rotated, actual;
7013 base = LLVMGetParam(func, vtx_params[i]);
7014 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7015 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7016 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7017 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7018 }
7019 }
7020
7021 LLVMBuildRet(builder, ret);
7022 }
7023
7024 /**
7025 * Given a list of shader part functions, build a wrapper function that
7026 * runs them in sequence to form a monolithic shader.
7027 */
7028 static void si_build_wrapper_function(struct si_shader_context *ctx,
7029 LLVMValueRef *parts,
7030 unsigned num_parts,
7031 unsigned main_part)
7032 {
7033 struct gallivm_state *gallivm = &ctx->gallivm;
7034 LLVMBuilderRef builder = ctx->gallivm.builder;
7035 /* PS epilog has one arg per color component */
7036 LLVMTypeRef param_types[48];
7037 LLVMValueRef out[48];
7038 LLVMTypeRef function_type;
7039 unsigned num_params;
7040 unsigned num_out;
7041 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7042 unsigned num_sgprs, num_vgprs;
7043 unsigned last_sgpr_param;
7044 unsigned gprs;
7045
7046 for (unsigned i = 0; i < num_parts; ++i) {
7047 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7048 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7049 }
7050
7051 /* The parameters of the wrapper function correspond to those of the
7052 * first part in terms of SGPRs and VGPRs, but we use the types of the
7053 * main part to get the right types. This is relevant for the
7054 * dereferenceable attribute on descriptor table pointers.
7055 */
7056 num_sgprs = 0;
7057 num_vgprs = 0;
7058
7059 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7060 num_params = LLVMCountParamTypes(function_type);
7061
7062 for (unsigned i = 0; i < num_params; ++i) {
7063 LLVMValueRef param = LLVMGetParam(parts[0], i);
7064
7065 if (ac_is_sgpr_param(param)) {
7066 assert(num_vgprs == 0);
7067 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7068 } else {
7069 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7070 }
7071 }
7072 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7073
7074 num_params = 0;
7075 last_sgpr_param = 0;
7076 gprs = 0;
7077 while (gprs < num_sgprs + num_vgprs) {
7078 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7079 unsigned size;
7080
7081 param_types[num_params] = LLVMTypeOf(param);
7082 if (gprs < num_sgprs)
7083 last_sgpr_param = num_params;
7084 size = llvm_get_type_size(param_types[num_params]) / 4;
7085 num_params++;
7086
7087 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7088 assert(gprs + size <= num_sgprs + num_vgprs &&
7089 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7090
7091 gprs += size;
7092 }
7093
7094 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7095
7096 /* Record the arguments of the function as if they were an output of
7097 * a previous part.
7098 */
7099 num_out = 0;
7100 num_out_sgpr = 0;
7101
7102 for (unsigned i = 0; i < num_params; ++i) {
7103 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7104 LLVMTypeRef param_type = LLVMTypeOf(param);
7105 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7106 unsigned size = llvm_get_type_size(param_type) / 4;
7107
7108 if (size == 1) {
7109 if (param_type != out_type)
7110 param = LLVMBuildBitCast(builder, param, out_type, "");
7111 out[num_out++] = param;
7112 } else {
7113 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7114
7115 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7116 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7117 param_type = ctx->i64;
7118 }
7119
7120 if (param_type != vector_type)
7121 param = LLVMBuildBitCast(builder, param, vector_type, "");
7122
7123 for (unsigned j = 0; j < size; ++j)
7124 out[num_out++] = LLVMBuildExtractElement(
7125 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7126 }
7127
7128 if (i <= last_sgpr_param)
7129 num_out_sgpr = num_out;
7130 }
7131
7132 /* Now chain the parts. */
7133 for (unsigned part = 0; part < num_parts; ++part) {
7134 LLVMValueRef in[48];
7135 LLVMValueRef ret;
7136 LLVMTypeRef ret_type;
7137 unsigned out_idx = 0;
7138
7139 num_params = LLVMCountParams(parts[part]);
7140 assert(num_params <= ARRAY_SIZE(param_types));
7141
7142 /* Derive arguments for the next part from outputs of the
7143 * previous one.
7144 */
7145 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7146 LLVMValueRef param;
7147 LLVMTypeRef param_type;
7148 bool is_sgpr;
7149 unsigned param_size;
7150 LLVMValueRef arg = NULL;
7151
7152 param = LLVMGetParam(parts[part], param_idx);
7153 param_type = LLVMTypeOf(param);
7154 param_size = llvm_get_type_size(param_type) / 4;
7155 is_sgpr = ac_is_sgpr_param(param);
7156
7157 if (is_sgpr) {
7158 #if HAVE_LLVM < 0x0400
7159 LLVMRemoveAttribute(param, LLVMByValAttribute);
7160 #else
7161 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7162 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7163 #endif
7164 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7165 }
7166
7167 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7168 assert(is_sgpr || out_idx >= num_out_sgpr);
7169
7170 if (param_size == 1)
7171 arg = out[out_idx];
7172 else
7173 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7174
7175 if (LLVMTypeOf(arg) != param_type) {
7176 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7177 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7178 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7179 } else {
7180 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7181 }
7182 }
7183
7184 in[param_idx] = arg;
7185 out_idx += param_size;
7186 }
7187
7188 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7189 ret_type = LLVMTypeOf(ret);
7190
7191 /* Extract the returned GPRs. */
7192 num_out = 0;
7193 num_out_sgpr = 0;
7194
7195 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7196 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7197
7198 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7199
7200 for (unsigned i = 0; i < ret_size; ++i) {
7201 LLVMValueRef val =
7202 LLVMBuildExtractValue(builder, ret, i, "");
7203
7204 out[num_out++] = val;
7205
7206 if (LLVMTypeOf(val) == ctx->i32) {
7207 assert(num_out_sgpr + 1 == num_out);
7208 num_out_sgpr = num_out;
7209 }
7210 }
7211 }
7212 }
7213
7214 LLVMBuildRetVoid(builder);
7215 }
7216
7217 int si_compile_tgsi_shader(struct si_screen *sscreen,
7218 LLVMTargetMachineRef tm,
7219 struct si_shader *shader,
7220 bool is_monolithic,
7221 struct pipe_debug_callback *debug)
7222 {
7223 struct si_shader_selector *sel = shader->selector;
7224 struct si_shader_context ctx;
7225 struct lp_build_tgsi_context *bld_base;
7226 LLVMModuleRef mod;
7227 int r = -1;
7228
7229 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7230 * conversion fails. */
7231 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7232 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7233 tgsi_dump(sel->tokens, 0);
7234 si_dump_streamout(&sel->so);
7235 }
7236
7237 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7238 ctx.separate_prolog = !is_monolithic;
7239
7240 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7241 sizeof(shader->info.vs_output_param_offset));
7242
7243 shader->info.uses_instanceid = sel->info.uses_instanceid;
7244
7245 bld_base = &ctx.bld_base;
7246 ctx.load_system_value = declare_system_value;
7247
7248 if (!si_compile_tgsi_main(&ctx, shader)) {
7249 si_llvm_dispose(&ctx);
7250 return -1;
7251 }
7252
7253 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7254 LLVMValueRef parts[3];
7255 bool need_prolog;
7256 bool need_epilog;
7257
7258 need_prolog = sel->info.num_inputs;
7259 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7260
7261 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7262
7263 if (need_prolog) {
7264 union si_shader_part_key prolog_key;
7265 si_get_vs_prolog_key(shader, &prolog_key);
7266 si_build_vs_prolog_function(&ctx, &prolog_key);
7267 parts[0] = ctx.main_fn;
7268 }
7269
7270 if (need_epilog) {
7271 union si_shader_part_key epilog_key;
7272 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7273 si_build_vs_epilog_function(&ctx, &epilog_key);
7274 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7275 }
7276
7277 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7278 need_prolog ? 1 : 0);
7279 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7280 LLVMValueRef parts[2];
7281 union si_shader_part_key epilog_key;
7282
7283 parts[0] = ctx.main_fn;
7284
7285 memset(&epilog_key, 0, sizeof(epilog_key));
7286 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7287 si_build_tcs_epilog_function(&ctx, &epilog_key);
7288 parts[1] = ctx.main_fn;
7289
7290 si_build_wrapper_function(&ctx, parts, 2, 0);
7291 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7292 !shader->key.as_es) {
7293 LLVMValueRef parts[2];
7294 union si_shader_part_key epilog_key;
7295
7296 parts[0] = ctx.main_fn;
7297
7298 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7299 si_build_vs_epilog_function(&ctx, &epilog_key);
7300 parts[1] = ctx.main_fn;
7301
7302 si_build_wrapper_function(&ctx, parts, 2, 0);
7303 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7304 LLVMValueRef parts[2];
7305 union si_shader_part_key prolog_key;
7306
7307 parts[1] = ctx.main_fn;
7308
7309 memset(&prolog_key, 0, sizeof(prolog_key));
7310 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7311 si_build_gs_prolog_function(&ctx, &prolog_key);
7312 parts[0] = ctx.main_fn;
7313
7314 si_build_wrapper_function(&ctx, parts, 2, 1);
7315 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7316 LLVMValueRef parts[3];
7317 union si_shader_part_key prolog_key;
7318 union si_shader_part_key epilog_key;
7319 bool need_prolog;
7320
7321 si_get_ps_prolog_key(shader, &prolog_key, false);
7322 need_prolog = si_need_ps_prolog(&prolog_key);
7323
7324 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7325
7326 if (need_prolog) {
7327 si_build_ps_prolog_function(&ctx, &prolog_key);
7328 parts[0] = ctx.main_fn;
7329 }
7330
7331 si_get_ps_epilog_key(shader, &epilog_key);
7332 si_build_ps_epilog_function(&ctx, &epilog_key);
7333 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7334
7335 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7336 }
7337
7338 mod = bld_base->base.gallivm->module;
7339
7340 /* Dump LLVM IR before any optimization passes */
7341 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7342 r600_can_dump_shader(&sscreen->b, ctx.type))
7343 ac_dump_module(mod);
7344
7345 si_llvm_finalize_module(&ctx,
7346 r600_extra_shader_checks(&sscreen->b, ctx.type));
7347
7348 /* Post-optimization transformations and analysis. */
7349 si_eliminate_const_vs_outputs(&ctx);
7350
7351 if ((debug && debug->debug_message) ||
7352 r600_can_dump_shader(&sscreen->b, ctx.type))
7353 si_count_scratch_private_memory(&ctx);
7354
7355 /* Compile to bytecode. */
7356 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7357 mod, debug, ctx.type, "TGSI shader");
7358 si_llvm_dispose(&ctx);
7359 if (r) {
7360 fprintf(stderr, "LLVM failed to compile shader\n");
7361 return r;
7362 }
7363
7364 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7365 * LLVM 3.9svn has this bug.
7366 */
7367 if (sel->type == PIPE_SHADER_COMPUTE) {
7368 unsigned wave_size = 64;
7369 unsigned max_vgprs = 256;
7370 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7371 unsigned max_sgprs_per_wave = 128;
7372 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7373 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7374 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7375
7376 max_vgprs = max_vgprs / min_waves_per_simd;
7377 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7378
7379 if (shader->config.num_sgprs > max_sgprs ||
7380 shader->config.num_vgprs > max_vgprs) {
7381 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7382 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7383 shader->config.num_sgprs, shader->config.num_vgprs,
7384 max_sgprs, max_vgprs);
7385
7386 /* Just terminate the process, because dependent
7387 * shaders can hang due to bad input data, but use
7388 * the env var to allow shader-db to work.
7389 */
7390 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7391 abort();
7392 }
7393 }
7394
7395 /* Add the scratch offset to input SGPRs. */
7396 if (shader->config.scratch_bytes_per_wave)
7397 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7398
7399 /* Calculate the number of fragment input VGPRs. */
7400 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7401 shader->info.num_input_vgprs = 0;
7402 shader->info.face_vgpr_index = -1;
7403
7404 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7405 shader->info.num_input_vgprs += 2;
7406 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7407 shader->info.num_input_vgprs += 2;
7408 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7409 shader->info.num_input_vgprs += 2;
7410 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7411 shader->info.num_input_vgprs += 3;
7412 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7413 shader->info.num_input_vgprs += 2;
7414 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7415 shader->info.num_input_vgprs += 2;
7416 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7417 shader->info.num_input_vgprs += 2;
7418 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7419 shader->info.num_input_vgprs += 1;
7420 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7421 shader->info.num_input_vgprs += 1;
7422 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7423 shader->info.num_input_vgprs += 1;
7424 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7425 shader->info.num_input_vgprs += 1;
7426 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7427 shader->info.num_input_vgprs += 1;
7428 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7429 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7430 shader->info.num_input_vgprs += 1;
7431 }
7432 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7433 shader->info.num_input_vgprs += 1;
7434 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7435 shader->info.num_input_vgprs += 1;
7436 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7437 shader->info.num_input_vgprs += 1;
7438 }
7439
7440 return 0;
7441 }
7442
7443 /**
7444 * Create, compile and return a shader part (prolog or epilog).
7445 *
7446 * \param sscreen screen
7447 * \param list list of shader parts of the same category
7448 * \param type shader type
7449 * \param key shader part key
7450 * \param prolog whether the part being requested is a prolog
7451 * \param tm LLVM target machine
7452 * \param debug debug callback
7453 * \param build the callback responsible for building the main function
7454 * \return non-NULL on success
7455 */
7456 static struct si_shader_part *
7457 si_get_shader_part(struct si_screen *sscreen,
7458 struct si_shader_part **list,
7459 enum pipe_shader_type type,
7460 bool prolog,
7461 union si_shader_part_key *key,
7462 LLVMTargetMachineRef tm,
7463 struct pipe_debug_callback *debug,
7464 void (*build)(struct si_shader_context *,
7465 union si_shader_part_key *),
7466 const char *name)
7467 {
7468 struct si_shader_part *result;
7469
7470 pipe_mutex_lock(sscreen->shader_parts_mutex);
7471
7472 /* Find existing. */
7473 for (result = *list; result; result = result->next) {
7474 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7475 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7476 return result;
7477 }
7478 }
7479
7480 /* Compile a new one. */
7481 result = CALLOC_STRUCT(si_shader_part);
7482 result->key = *key;
7483
7484 struct si_shader shader = {};
7485 struct si_shader_context ctx;
7486 struct gallivm_state *gallivm = &ctx.gallivm;
7487
7488 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7489 ctx.type = type;
7490
7491 switch (type) {
7492 case PIPE_SHADER_VERTEX:
7493 break;
7494 case PIPE_SHADER_TESS_CTRL:
7495 assert(!prolog);
7496 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7497 break;
7498 case PIPE_SHADER_GEOMETRY:
7499 assert(prolog);
7500 break;
7501 case PIPE_SHADER_FRAGMENT:
7502 if (prolog)
7503 shader.key.part.ps.prolog = key->ps_prolog.states;
7504 else
7505 shader.key.part.ps.epilog = key->ps_epilog.states;
7506 break;
7507 default:
7508 unreachable("bad shader part");
7509 }
7510
7511 build(&ctx, key);
7512
7513 /* Compile. */
7514 si_llvm_finalize_module(&ctx,
7515 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7516
7517 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7518 gallivm->module, debug, ctx.type, name)) {
7519 FREE(result);
7520 result = NULL;
7521 goto out;
7522 }
7523
7524 result->next = *list;
7525 *list = result;
7526
7527 out:
7528 si_llvm_dispose(&ctx);
7529 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7530 return result;
7531 }
7532
7533 /**
7534 * Build the vertex shader prolog function.
7535 *
7536 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7537 * All inputs are returned unmodified. The vertex load indices are
7538 * stored after them, which will be used by the API VS for fetching inputs.
7539 *
7540 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7541 * input_v0,
7542 * input_v1,
7543 * input_v2,
7544 * input_v3,
7545 * (VertexID + BaseVertex),
7546 * (InstanceID + StartInstance),
7547 * (InstanceID / 2 + StartInstance)
7548 */
7549 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7550 union si_shader_part_key *key)
7551 {
7552 struct gallivm_state *gallivm = &ctx->gallivm;
7553 LLVMTypeRef *params, *returns;
7554 LLVMValueRef ret, func;
7555 int last_sgpr, num_params, num_returns, i;
7556
7557 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7558 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7559
7560 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7561 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7562 sizeof(LLVMTypeRef));
7563 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7564 key->vs_prolog.last_input + 1) *
7565 sizeof(LLVMTypeRef));
7566 num_params = 0;
7567 num_returns = 0;
7568
7569 /* Declare input and output SGPRs. */
7570 num_params = 0;
7571 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7572 params[num_params++] = ctx->i32;
7573 returns[num_returns++] = ctx->i32;
7574 }
7575 last_sgpr = num_params - 1;
7576
7577 /* 4 preloaded VGPRs (outputs must be floats) */
7578 for (i = 0; i < 4; i++) {
7579 params[num_params++] = ctx->i32;
7580 returns[num_returns++] = ctx->f32;
7581 }
7582
7583 /* Vertex load indices. */
7584 for (i = 0; i <= key->vs_prolog.last_input; i++)
7585 returns[num_returns++] = ctx->f32;
7586
7587 /* Create the function. */
7588 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7589 num_params, last_sgpr);
7590 func = ctx->main_fn;
7591
7592 /* Copy inputs to outputs. This should be no-op, as the registers match,
7593 * but it will prevent the compiler from overwriting them unintentionally.
7594 */
7595 ret = ctx->return_value;
7596 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7597 LLVMValueRef p = LLVMGetParam(func, i);
7598 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7599 }
7600 for (i = num_params - 4; i < num_params; i++) {
7601 LLVMValueRef p = LLVMGetParam(func, i);
7602 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7603 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7604 }
7605
7606 /* Compute vertex load indices from instance divisors. */
7607 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7608 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7609 LLVMValueRef index;
7610
7611 if (divisor) {
7612 /* InstanceID / Divisor + StartInstance */
7613 index = get_instance_index_for_fetch(ctx,
7614 SI_SGPR_START_INSTANCE,
7615 divisor);
7616 } else {
7617 /* VertexID + BaseVertex */
7618 index = LLVMBuildAdd(gallivm->builder,
7619 LLVMGetParam(func, ctx->param_vertex_id),
7620 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7621 }
7622
7623 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7624 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7625 num_params++, "");
7626 }
7627
7628 si_llvm_build_ret(ctx, ret);
7629 }
7630
7631 /**
7632 * Build the vertex shader epilog function. This is also used by the tessellation
7633 * evaluation shader compiled as VS.
7634 *
7635 * The input is PrimitiveID.
7636 *
7637 * If PrimitiveID is required by the pixel shader, export it.
7638 * Otherwise, do nothing.
7639 */
7640 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7641 union si_shader_part_key *key)
7642 {
7643 struct gallivm_state *gallivm = &ctx->gallivm;
7644 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7645 LLVMTypeRef params[5];
7646 int num_params, i;
7647
7648 /* Declare input VGPRs. */
7649 num_params = key->vs_epilog.states.export_prim_id ?
7650 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7651 assert(num_params <= ARRAY_SIZE(params));
7652
7653 for (i = 0; i < num_params; i++)
7654 params[i] = ctx->f32;
7655
7656 /* Create the function. */
7657 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7658
7659 /* Emit exports. */
7660 if (key->vs_epilog.states.export_prim_id) {
7661 struct lp_build_context *base = &bld_base->base;
7662 struct ac_export_args args;
7663
7664 args.enabled_channels = 0x1; /* enabled channels */
7665 args.valid_mask = 0; /* whether the EXEC mask is valid */
7666 args.done = 0; /* DONE bit */
7667 args.target = V_008DFC_SQ_EXP_PARAM +
7668 key->vs_epilog.prim_id_param_offset;
7669 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7670 args.out[0] = LLVMGetParam(ctx->main_fn,
7671 VS_EPILOG_PRIMID_LOC); /* X */
7672 args.out[1] = base->undef; /* Y */
7673 args.out[2] = base->undef; /* Z */
7674 args.out[3] = base->undef; /* W */
7675
7676 ac_build_export(&ctx->ac, &args);
7677 }
7678
7679 LLVMBuildRetVoid(gallivm->builder);
7680 }
7681
7682 /**
7683 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7684 */
7685 static bool si_get_vs_epilog(struct si_screen *sscreen,
7686 LLVMTargetMachineRef tm,
7687 struct si_shader *shader,
7688 struct pipe_debug_callback *debug,
7689 struct si_vs_epilog_bits *states)
7690 {
7691 union si_shader_part_key epilog_key;
7692
7693 si_get_vs_epilog_key(shader, states, &epilog_key);
7694
7695 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7696 PIPE_SHADER_VERTEX, true,
7697 &epilog_key, tm, debug,
7698 si_build_vs_epilog_function,
7699 "Vertex Shader Epilog");
7700 return shader->epilog != NULL;
7701 }
7702
7703 /**
7704 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7705 */
7706 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7707 LLVMTargetMachineRef tm,
7708 struct si_shader *shader,
7709 struct pipe_debug_callback *debug)
7710 {
7711 struct tgsi_shader_info *info = &shader->selector->info;
7712 union si_shader_part_key prolog_key;
7713
7714 /* Get the prolog. */
7715 si_get_vs_prolog_key(shader, &prolog_key);
7716
7717 /* The prolog is a no-op if there are no inputs. */
7718 if (info->num_inputs) {
7719 shader->prolog =
7720 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7721 PIPE_SHADER_VERTEX, true,
7722 &prolog_key, tm, debug,
7723 si_build_vs_prolog_function,
7724 "Vertex Shader Prolog");
7725 if (!shader->prolog)
7726 return false;
7727 }
7728
7729 /* Get the epilog. */
7730 if (!shader->key.as_es && !shader->key.as_ls &&
7731 !si_get_vs_epilog(sscreen, tm, shader, debug,
7732 &shader->key.part.vs.epilog))
7733 return false;
7734
7735 return true;
7736 }
7737
7738 /**
7739 * Select and compile (or reuse) TES parts (epilog).
7740 */
7741 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7742 LLVMTargetMachineRef tm,
7743 struct si_shader *shader,
7744 struct pipe_debug_callback *debug)
7745 {
7746 if (shader->key.as_es)
7747 return true;
7748
7749 /* TES compiled as VS. */
7750 return si_get_vs_epilog(sscreen, tm, shader, debug,
7751 &shader->key.part.tes.epilog);
7752 }
7753
7754 /**
7755 * Compile the TCS epilog function. This writes tesselation factors to memory
7756 * based on the output primitive type of the tesselator (determined by TES).
7757 */
7758 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7759 union si_shader_part_key *key)
7760 {
7761 struct gallivm_state *gallivm = &ctx->gallivm;
7762 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7763 LLVMTypeRef params[16];
7764 LLVMValueRef func;
7765 int last_sgpr, num_params;
7766
7767 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7768 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7769 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7770 params[SI_PARAM_SAMPLERS] = ctx->i64;
7771 params[SI_PARAM_IMAGES] = ctx->i64;
7772 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7773 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7774 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7775 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7776 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7777 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7778 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7779 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7780 num_params = last_sgpr + 1;
7781
7782 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7783 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7784 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7785
7786 /* Create the function. */
7787 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7788 declare_tess_lds(ctx);
7789 func = ctx->main_fn;
7790
7791 si_write_tess_factors(bld_base,
7792 LLVMGetParam(func, last_sgpr + 1),
7793 LLVMGetParam(func, last_sgpr + 2),
7794 LLVMGetParam(func, last_sgpr + 3));
7795
7796 LLVMBuildRetVoid(gallivm->builder);
7797 }
7798
7799 /**
7800 * Select and compile (or reuse) TCS parts (epilog).
7801 */
7802 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7803 LLVMTargetMachineRef tm,
7804 struct si_shader *shader,
7805 struct pipe_debug_callback *debug)
7806 {
7807 union si_shader_part_key epilog_key;
7808
7809 /* Get the epilog. */
7810 memset(&epilog_key, 0, sizeof(epilog_key));
7811 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7812
7813 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7814 PIPE_SHADER_TESS_CTRL, false,
7815 &epilog_key, tm, debug,
7816 si_build_tcs_epilog_function,
7817 "Tessellation Control Shader Epilog");
7818 return shader->epilog != NULL;
7819 }
7820
7821 /**
7822 * Select and compile (or reuse) GS parts (prolog).
7823 */
7824 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7825 LLVMTargetMachineRef tm,
7826 struct si_shader *shader,
7827 struct pipe_debug_callback *debug)
7828 {
7829 union si_shader_part_key prolog_key;
7830
7831 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7832 return true;
7833
7834 memset(&prolog_key, 0, sizeof(prolog_key));
7835 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7836
7837 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7838 PIPE_SHADER_GEOMETRY, true,
7839 &prolog_key, tm, debug,
7840 si_build_gs_prolog_function,
7841 "Geometry Shader Prolog");
7842 return shader->prolog != NULL;
7843 }
7844
7845 /**
7846 * Build the pixel shader prolog function. This handles:
7847 * - two-side color selection and interpolation
7848 * - overriding interpolation parameters for the API PS
7849 * - polygon stippling
7850 *
7851 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7852 * overriden by other states. (e.g. per-sample interpolation)
7853 * Interpolated colors are stored after the preloaded VGPRs.
7854 */
7855 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7856 union si_shader_part_key *key)
7857 {
7858 struct gallivm_state *gallivm = &ctx->gallivm;
7859 LLVMTypeRef *params;
7860 LLVMValueRef ret, func;
7861 int last_sgpr, num_params, num_returns, i, num_color_channels;
7862
7863 assert(si_need_ps_prolog(key));
7864
7865 /* Number of inputs + 8 color elements. */
7866 params = alloca((key->ps_prolog.num_input_sgprs +
7867 key->ps_prolog.num_input_vgprs + 8) *
7868 sizeof(LLVMTypeRef));
7869
7870 /* Declare inputs. */
7871 num_params = 0;
7872 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7873 params[num_params++] = ctx->i32;
7874 last_sgpr = num_params - 1;
7875
7876 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7877 params[num_params++] = ctx->f32;
7878
7879 /* Declare outputs (same as inputs + add colors if needed) */
7880 num_returns = num_params;
7881 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7882 for (i = 0; i < num_color_channels; i++)
7883 params[num_returns++] = ctx->f32;
7884
7885 /* Create the function. */
7886 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7887 num_params, last_sgpr);
7888 func = ctx->main_fn;
7889
7890 /* Copy inputs to outputs. This should be no-op, as the registers match,
7891 * but it will prevent the compiler from overwriting them unintentionally.
7892 */
7893 ret = ctx->return_value;
7894 for (i = 0; i < num_params; i++) {
7895 LLVMValueRef p = LLVMGetParam(func, i);
7896 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7897 }
7898
7899 /* Polygon stippling. */
7900 if (key->ps_prolog.states.poly_stipple) {
7901 /* POS_FIXED_PT is always last. */
7902 unsigned pos = key->ps_prolog.num_input_sgprs +
7903 key->ps_prolog.num_input_vgprs - 1;
7904 LLVMValueRef ptr[2], list;
7905
7906 /* Get the pointer to rw buffers. */
7907 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7908 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7909 list = lp_build_gather_values(gallivm, ptr, 2);
7910 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7911 list = LLVMBuildIntToPtr(gallivm->builder, list,
7912 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7913
7914 si_llvm_emit_polygon_stipple(ctx, list, pos);
7915 }
7916
7917 if (key->ps_prolog.states.bc_optimize_for_persp ||
7918 key->ps_prolog.states.bc_optimize_for_linear) {
7919 unsigned i, base = key->ps_prolog.num_input_sgprs;
7920 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7921
7922 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7923 * The hw doesn't compute CENTROID if the whole wave only
7924 * contains fully-covered quads.
7925 *
7926 * PRIM_MASK is after user SGPRs.
7927 */
7928 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7929 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7930 LLVMConstInt(ctx->i32, 31, 0), "");
7931 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7932 ctx->i1, "");
7933
7934 if (key->ps_prolog.states.bc_optimize_for_persp) {
7935 /* Read PERSP_CENTER. */
7936 for (i = 0; i < 2; i++)
7937 center[i] = LLVMGetParam(func, base + 2 + i);
7938 /* Read PERSP_CENTROID. */
7939 for (i = 0; i < 2; i++)
7940 centroid[i] = LLVMGetParam(func, base + 4 + i);
7941 /* Select PERSP_CENTROID. */
7942 for (i = 0; i < 2; i++) {
7943 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7944 center[i], centroid[i], "");
7945 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7946 tmp, base + 4 + i, "");
7947 }
7948 }
7949 if (key->ps_prolog.states.bc_optimize_for_linear) {
7950 /* Read LINEAR_CENTER. */
7951 for (i = 0; i < 2; i++)
7952 center[i] = LLVMGetParam(func, base + 8 + i);
7953 /* Read LINEAR_CENTROID. */
7954 for (i = 0; i < 2; i++)
7955 centroid[i] = LLVMGetParam(func, base + 10 + i);
7956 /* Select LINEAR_CENTROID. */
7957 for (i = 0; i < 2; i++) {
7958 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7959 center[i], centroid[i], "");
7960 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7961 tmp, base + 10 + i, "");
7962 }
7963 }
7964 }
7965
7966 /* Force per-sample interpolation. */
7967 if (key->ps_prolog.states.force_persp_sample_interp) {
7968 unsigned i, base = key->ps_prolog.num_input_sgprs;
7969 LLVMValueRef persp_sample[2];
7970
7971 /* Read PERSP_SAMPLE. */
7972 for (i = 0; i < 2; i++)
7973 persp_sample[i] = LLVMGetParam(func, base + i);
7974 /* Overwrite PERSP_CENTER. */
7975 for (i = 0; i < 2; i++)
7976 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7977 persp_sample[i], base + 2 + i, "");
7978 /* Overwrite PERSP_CENTROID. */
7979 for (i = 0; i < 2; i++)
7980 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7981 persp_sample[i], base + 4 + i, "");
7982 }
7983 if (key->ps_prolog.states.force_linear_sample_interp) {
7984 unsigned i, base = key->ps_prolog.num_input_sgprs;
7985 LLVMValueRef linear_sample[2];
7986
7987 /* Read LINEAR_SAMPLE. */
7988 for (i = 0; i < 2; i++)
7989 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7990 /* Overwrite LINEAR_CENTER. */
7991 for (i = 0; i < 2; i++)
7992 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7993 linear_sample[i], base + 8 + i, "");
7994 /* Overwrite LINEAR_CENTROID. */
7995 for (i = 0; i < 2; i++)
7996 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7997 linear_sample[i], base + 10 + i, "");
7998 }
7999
8000 /* Force center interpolation. */
8001 if (key->ps_prolog.states.force_persp_center_interp) {
8002 unsigned i, base = key->ps_prolog.num_input_sgprs;
8003 LLVMValueRef persp_center[2];
8004
8005 /* Read PERSP_CENTER. */
8006 for (i = 0; i < 2; i++)
8007 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8008 /* Overwrite PERSP_SAMPLE. */
8009 for (i = 0; i < 2; i++)
8010 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8011 persp_center[i], base + i, "");
8012 /* Overwrite PERSP_CENTROID. */
8013 for (i = 0; i < 2; i++)
8014 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8015 persp_center[i], base + 4 + i, "");
8016 }
8017 if (key->ps_prolog.states.force_linear_center_interp) {
8018 unsigned i, base = key->ps_prolog.num_input_sgprs;
8019 LLVMValueRef linear_center[2];
8020
8021 /* Read LINEAR_CENTER. */
8022 for (i = 0; i < 2; i++)
8023 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8024 /* Overwrite LINEAR_SAMPLE. */
8025 for (i = 0; i < 2; i++)
8026 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8027 linear_center[i], base + 6 + i, "");
8028 /* Overwrite LINEAR_CENTROID. */
8029 for (i = 0; i < 2; i++)
8030 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8031 linear_center[i], base + 10 + i, "");
8032 }
8033
8034 /* Interpolate colors. */
8035 for (i = 0; i < 2; i++) {
8036 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8037 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8038 key->ps_prolog.face_vgpr_index;
8039 LLVMValueRef interp[2], color[4];
8040 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8041
8042 if (!writemask)
8043 continue;
8044
8045 /* If the interpolation qualifier is not CONSTANT (-1). */
8046 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8047 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8048 key->ps_prolog.color_interp_vgpr_index[i];
8049
8050 /* Get the (i,j) updated by bc_optimize handling. */
8051 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8052 interp_vgpr, "");
8053 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8054 interp_vgpr + 1, "");
8055 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8056 }
8057
8058 /* Use the absolute location of the input. */
8059 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8060
8061 if (key->ps_prolog.states.color_two_side) {
8062 face = LLVMGetParam(func, face_vgpr);
8063 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8064 }
8065
8066 interp_fs_input(ctx,
8067 key->ps_prolog.color_attr_index[i],
8068 TGSI_SEMANTIC_COLOR, i,
8069 key->ps_prolog.num_interp_inputs,
8070 key->ps_prolog.colors_read, interp_ij,
8071 prim_mask, face, color);
8072
8073 while (writemask) {
8074 unsigned chan = u_bit_scan(&writemask);
8075 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8076 num_params++, "");
8077 }
8078 }
8079
8080 /* Tell LLVM to insert WQM instruction sequence when needed. */
8081 if (key->ps_prolog.wqm) {
8082 LLVMAddTargetDependentFunctionAttr(func,
8083 "amdgpu-ps-wqm-outputs", "");
8084 }
8085
8086 si_llvm_build_ret(ctx, ret);
8087 }
8088
8089 /**
8090 * Build the pixel shader epilog function. This handles everything that must be
8091 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8092 */
8093 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8094 union si_shader_part_key *key)
8095 {
8096 struct gallivm_state *gallivm = &ctx->gallivm;
8097 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8098 LLVMTypeRef params[16+8*4+3];
8099 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8100 int last_sgpr, num_params, i;
8101 struct si_ps_exports exp = {};
8102
8103 /* Declare input SGPRs. */
8104 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8105 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8106 params[SI_PARAM_SAMPLERS] = ctx->i64;
8107 params[SI_PARAM_IMAGES] = ctx->i64;
8108 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8109 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8110 last_sgpr = SI_PARAM_ALPHA_REF;
8111
8112 /* Declare input VGPRs. */
8113 num_params = (last_sgpr + 1) +
8114 util_bitcount(key->ps_epilog.colors_written) * 4 +
8115 key->ps_epilog.writes_z +
8116 key->ps_epilog.writes_stencil +
8117 key->ps_epilog.writes_samplemask;
8118
8119 num_params = MAX2(num_params,
8120 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8121
8122 assert(num_params <= ARRAY_SIZE(params));
8123
8124 for (i = last_sgpr + 1; i < num_params; i++)
8125 params[i] = ctx->f32;
8126
8127 /* Create the function. */
8128 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8129 /* Disable elimination of unused inputs. */
8130 si_llvm_add_attribute(ctx->main_fn,
8131 "InitialPSInputAddr", 0xffffff);
8132
8133 /* Process colors. */
8134 unsigned vgpr = last_sgpr + 1;
8135 unsigned colors_written = key->ps_epilog.colors_written;
8136 int last_color_export = -1;
8137
8138 /* Find the last color export. */
8139 if (!key->ps_epilog.writes_z &&
8140 !key->ps_epilog.writes_stencil &&
8141 !key->ps_epilog.writes_samplemask) {
8142 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8143
8144 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8145 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8146 /* Just set this if any of the colorbuffers are enabled. */
8147 if (spi_format &
8148 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8149 last_color_export = 0;
8150 } else {
8151 for (i = 0; i < 8; i++)
8152 if (colors_written & (1 << i) &&
8153 (spi_format >> (i * 4)) & 0xf)
8154 last_color_export = i;
8155 }
8156 }
8157
8158 while (colors_written) {
8159 LLVMValueRef color[4];
8160 int mrt = u_bit_scan(&colors_written);
8161
8162 for (i = 0; i < 4; i++)
8163 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8164
8165 si_export_mrt_color(bld_base, color, mrt,
8166 num_params - 1,
8167 mrt == last_color_export, &exp);
8168 }
8169
8170 /* Process depth, stencil, samplemask. */
8171 if (key->ps_epilog.writes_z)
8172 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8173 if (key->ps_epilog.writes_stencil)
8174 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8175 if (key->ps_epilog.writes_samplemask)
8176 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8177
8178 if (depth || stencil || samplemask)
8179 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8180 else if (last_color_export == -1)
8181 si_export_null(bld_base);
8182
8183 if (exp.num)
8184 si_emit_ps_exports(ctx, &exp);
8185
8186 /* Compile. */
8187 LLVMBuildRetVoid(gallivm->builder);
8188 }
8189
8190 /**
8191 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8192 */
8193 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8194 LLVMTargetMachineRef tm,
8195 struct si_shader *shader,
8196 struct pipe_debug_callback *debug)
8197 {
8198 union si_shader_part_key prolog_key;
8199 union si_shader_part_key epilog_key;
8200
8201 /* Get the prolog. */
8202 si_get_ps_prolog_key(shader, &prolog_key, true);
8203
8204 /* The prolog is a no-op if these aren't set. */
8205 if (si_need_ps_prolog(&prolog_key)) {
8206 shader->prolog =
8207 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8208 PIPE_SHADER_FRAGMENT, true,
8209 &prolog_key, tm, debug,
8210 si_build_ps_prolog_function,
8211 "Fragment Shader Prolog");
8212 if (!shader->prolog)
8213 return false;
8214 }
8215
8216 /* Get the epilog. */
8217 si_get_ps_epilog_key(shader, &epilog_key);
8218
8219 shader->epilog =
8220 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8221 PIPE_SHADER_FRAGMENT, false,
8222 &epilog_key, tm, debug,
8223 si_build_ps_epilog_function,
8224 "Fragment Shader Epilog");
8225 if (!shader->epilog)
8226 return false;
8227
8228 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8229 if (shader->key.part.ps.prolog.poly_stipple) {
8230 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8231 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8232 }
8233
8234 /* Set up the enable bits for per-sample shading if needed. */
8235 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8236 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8237 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8238 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8239 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8240 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8241 }
8242 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8243 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8244 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8245 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8246 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8247 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8248 }
8249 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8250 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8251 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8252 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8253 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8254 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8255 }
8256 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8257 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8258 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8259 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8260 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8261 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8262 }
8263
8264 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8265 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8266 !(shader->config.spi_ps_input_ena & 0xf)) {
8267 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8268 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8269 }
8270
8271 /* At least one pair of interpolation weights must be enabled. */
8272 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8273 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8274 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8275 }
8276
8277 /* The sample mask input is always enabled, because the API shader always
8278 * passes it through to the epilog. Disable it here if it's unused.
8279 */
8280 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8281 !shader->selector->info.reads_samplemask)
8282 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8283
8284 return true;
8285 }
8286
8287 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8288 unsigned *lds_size)
8289 {
8290 /* SPI barrier management bug:
8291 * Make sure we have at least 4k of LDS in use to avoid the bug.
8292 * It applies to workgroup sizes of more than one wavefront.
8293 */
8294 if (sscreen->b.family == CHIP_BONAIRE ||
8295 sscreen->b.family == CHIP_KABINI ||
8296 sscreen->b.family == CHIP_MULLINS)
8297 *lds_size = MAX2(*lds_size, 8);
8298 }
8299
8300 static void si_fix_resource_usage(struct si_screen *sscreen,
8301 struct si_shader *shader)
8302 {
8303 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8304
8305 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8306
8307 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8308 si_get_max_workgroup_size(shader) > 64) {
8309 si_multiwave_lds_size_workaround(sscreen,
8310 &shader->config.lds_size);
8311 }
8312 }
8313
8314 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8315 struct si_shader *shader,
8316 struct pipe_debug_callback *debug)
8317 {
8318 struct si_shader_selector *sel = shader->selector;
8319 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8320 int r;
8321
8322 /* LS, ES, VS are compiled on demand if the main part hasn't been
8323 * compiled for that stage.
8324 *
8325 * Vertex shaders are compiled on demand when a vertex fetch
8326 * workaround must be applied.
8327 */
8328 if (shader->is_monolithic) {
8329 /* Monolithic shader (compiled as a whole, has many variants,
8330 * may take a long time to compile).
8331 */
8332 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8333 if (r)
8334 return r;
8335 } else {
8336 /* The shader consists of 2-3 parts:
8337 *
8338 * - the middle part is the user shader, it has 1 variant only
8339 * and it was compiled during the creation of the shader
8340 * selector
8341 * - the prolog part is inserted at the beginning
8342 * - the epilog part is inserted at the end
8343 *
8344 * The prolog and epilog have many (but simple) variants.
8345 */
8346
8347 /* Copy the compiled TGSI shader data over. */
8348 shader->is_binary_shared = true;
8349 shader->binary = mainp->binary;
8350 shader->config = mainp->config;
8351 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8352 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8353 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8354 memcpy(shader->info.vs_output_param_offset,
8355 mainp->info.vs_output_param_offset,
8356 sizeof(mainp->info.vs_output_param_offset));
8357 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8358 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8359 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8360
8361 /* Select prologs and/or epilogs. */
8362 switch (sel->type) {
8363 case PIPE_SHADER_VERTEX:
8364 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8365 return -1;
8366 break;
8367 case PIPE_SHADER_TESS_CTRL:
8368 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8369 return -1;
8370 break;
8371 case PIPE_SHADER_TESS_EVAL:
8372 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8373 return -1;
8374 break;
8375 case PIPE_SHADER_GEOMETRY:
8376 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8377 return -1;
8378 break;
8379 case PIPE_SHADER_FRAGMENT:
8380 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8381 return -1;
8382
8383 /* Make sure we have at least as many VGPRs as there
8384 * are allocated inputs.
8385 */
8386 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8387 shader->info.num_input_vgprs);
8388 break;
8389 }
8390
8391 /* Update SGPR and VGPR counts. */
8392 if (shader->prolog) {
8393 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8394 shader->prolog->config.num_sgprs);
8395 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8396 shader->prolog->config.num_vgprs);
8397 }
8398 if (shader->epilog) {
8399 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8400 shader->epilog->config.num_sgprs);
8401 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8402 shader->epilog->config.num_vgprs);
8403 }
8404 }
8405
8406 si_fix_resource_usage(sscreen, shader);
8407 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8408 stderr, true);
8409
8410 /* Upload. */
8411 r = si_shader_binary_upload(sscreen, shader);
8412 if (r) {
8413 fprintf(stderr, "LLVM failed to upload shader\n");
8414 return r;
8415 }
8416
8417 return 0;
8418 }
8419
8420 void si_shader_destroy(struct si_shader *shader)
8421 {
8422 if (shader->scratch_bo)
8423 r600_resource_reference(&shader->scratch_bo, NULL);
8424
8425 r600_resource_reference(&shader->bo, NULL);
8426
8427 if (!shader->is_binary_shared)
8428 radeon_shader_binary_clean(&shader->binary);
8429
8430 free(shader->shader_log);
8431 }