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radeonsi: remove always constant ballot_mask_bits from si_llvm_context_init
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <llvm/Config/llvm-config.h>
26
27 #include "util/u_memory.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_rtld.h"
34 #include "ac_llvm_util.h"
35 #include "si_shader_internal.h"
36 #include "si_pipe.h"
37 #include "sid.h"
38
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_serialize.h"
41
42 static const char scratch_rsrc_dword0_symbol[] =
43 "SCRATCH_RSRC_DWORD0";
44
45 static const char scratch_rsrc_dword1_symbol[] =
46 "SCRATCH_RSRC_DWORD1";
47
48 static void si_llvm_emit_barrier(struct si_shader_context *ctx);
49
50 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
51
52 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
53 union si_shader_part_key *key);
54 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
55 union si_shader_part_key *key);
56 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
57 union si_shader_part_key *key);
58 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
59 union si_shader_part_key *key);
60 static void si_fix_resource_usage(struct si_screen *sscreen,
61 struct si_shader *shader);
62
63 /* Ideally pass the sample mask input to the PS epilog as v14, which
64 * is its usual location, so that the shader doesn't have to add v_mov.
65 */
66 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
67
68 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
69 LLVMTypeRef type)
70 {
71 if (type == ctx->ac.i64 || type == ctx->ac.f64)
72 return true;
73
74 return false;
75 }
76
77 /** Whether the shader runs as a combination of multiple API shaders */
78 static bool is_multi_part_shader(struct si_shader_context *ctx)
79 {
80 if (ctx->screen->info.chip_class <= GFX8)
81 return false;
82
83 return ctx->shader->key.as_ls ||
84 ctx->shader->key.as_es ||
85 ctx->type == PIPE_SHADER_TESS_CTRL ||
86 ctx->type == PIPE_SHADER_GEOMETRY;
87 }
88
89 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
90 static bool is_merged_shader(struct si_shader_context *ctx)
91 {
92 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
93 }
94
95 /**
96 * Returns a unique index for a per-patch semantic name and index. The index
97 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
98 * can be calculated.
99 */
100 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
101 {
102 switch (semantic_name) {
103 case TGSI_SEMANTIC_TESSOUTER:
104 return 0;
105 case TGSI_SEMANTIC_TESSINNER:
106 return 1;
107 case TGSI_SEMANTIC_PATCH:
108 assert(index < 30);
109 return 2 + index;
110
111 default:
112 assert(!"invalid semantic name");
113 return 0;
114 }
115 }
116
117 /**
118 * Returns a unique index for a semantic name and index. The index must be
119 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
120 * calculated.
121 */
122 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
123 unsigned is_varying)
124 {
125 switch (semantic_name) {
126 case TGSI_SEMANTIC_POSITION:
127 return 0;
128 case TGSI_SEMANTIC_GENERIC:
129 /* Since some shader stages use the the highest used IO index
130 * to determine the size to allocate for inputs/outputs
131 * (in LDS, tess and GS rings). GENERIC should be placed right
132 * after POSITION to make that size as small as possible.
133 */
134 if (index < SI_MAX_IO_GENERIC)
135 return 1 + index;
136
137 assert(!"invalid generic index");
138 return 0;
139 case TGSI_SEMANTIC_FOG:
140 return SI_MAX_IO_GENERIC + 1;
141 case TGSI_SEMANTIC_COLOR:
142 assert(index < 2);
143 return SI_MAX_IO_GENERIC + 2 + index;
144 case TGSI_SEMANTIC_BCOLOR:
145 assert(index < 2);
146 /* If it's a varying, COLOR and BCOLOR alias. */
147 if (is_varying)
148 return SI_MAX_IO_GENERIC + 2 + index;
149 else
150 return SI_MAX_IO_GENERIC + 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 assert(index < 8);
153 return SI_MAX_IO_GENERIC + 6 + index;
154
155 /* These are rarely used between LS and HS or ES and GS. */
156 case TGSI_SEMANTIC_CLIPDIST:
157 assert(index < 2);
158 return SI_MAX_IO_GENERIC + 6 + 8 + index;
159 case TGSI_SEMANTIC_CLIPVERTEX:
160 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
161 case TGSI_SEMANTIC_PSIZE:
162 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
163
164 /* These can't be written by LS, HS, and ES. */
165 case TGSI_SEMANTIC_LAYER:
166 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
167 case TGSI_SEMANTIC_VIEWPORT_INDEX:
168 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
169 case TGSI_SEMANTIC_PRIMID:
170 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
171 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
172 default:
173 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
174 assert(!"invalid semantic name");
175 return 0;
176 }
177 }
178
179 /**
180 * Get the value of a shader input parameter and extract a bitfield.
181 */
182 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
183 LLVMValueRef value, unsigned rshift,
184 unsigned bitwidth)
185 {
186 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
187 value = ac_to_integer(&ctx->ac, value);
188
189 if (rshift)
190 value = LLVMBuildLShr(ctx->ac.builder, value,
191 LLVMConstInt(ctx->i32, rshift, 0), "");
192
193 if (rshift + bitwidth < 32) {
194 unsigned mask = (1 << bitwidth) - 1;
195 value = LLVMBuildAnd(ctx->ac.builder, value,
196 LLVMConstInt(ctx->i32, mask, 0), "");
197 }
198
199 return value;
200 }
201
202 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
203 struct ac_arg param, unsigned rshift,
204 unsigned bitwidth)
205 {
206 LLVMValueRef value = ac_get_arg(&ctx->ac, param);
207
208 return unpack_llvm_param(ctx, value, rshift, bitwidth);
209 }
210
211 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
212 {
213 switch (ctx->type) {
214 case PIPE_SHADER_TESS_CTRL:
215 return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8);
216
217 case PIPE_SHADER_TESS_EVAL:
218 return ac_get_arg(&ctx->ac, ctx->tes_rel_patch_id);
219
220 default:
221 assert(0);
222 return NULL;
223 }
224 }
225
226 /* Tessellation shaders pass outputs to the next shader using LDS.
227 *
228 * LS outputs = TCS inputs
229 * TCS outputs = TES inputs
230 *
231 * The LDS layout is:
232 * - TCS inputs for patch 0
233 * - TCS inputs for patch 1
234 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
235 * - ...
236 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
237 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
238 * - TCS outputs for patch 1
239 * - Per-patch TCS outputs for patch 1
240 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
241 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
242 * - ...
243 *
244 * All three shaders VS(LS), TCS, TES share the same LDS space.
245 */
246
247 static LLVMValueRef
248 get_tcs_in_patch_stride(struct si_shader_context *ctx)
249 {
250 return si_unpack_param(ctx, ctx->vs_state_bits, 8, 13);
251 }
252
253 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
254 {
255 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
256
257 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
258 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
259
260 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
261 }
262
263 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
264 {
265 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
266
267 return LLVMConstInt(ctx->i32, stride, 0);
268 }
269
270 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
271 {
272 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
273 return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);
274
275 const struct si_shader_info *info = &ctx->shader->selector->info;
276 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
277 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
278 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
279 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
280 num_patch_outputs * 4;
281 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
282 }
283
284 static LLVMValueRef
285 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
286 {
287 return LLVMBuildMul(ctx->ac.builder,
288 si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 0, 16),
289 LLVMConstInt(ctx->i32, 4, 0), "");
290 }
291
292 static LLVMValueRef
293 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
294 {
295 return LLVMBuildMul(ctx->ac.builder,
296 si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 16, 16),
297 LLVMConstInt(ctx->i32, 4, 0), "");
298 }
299
300 static LLVMValueRef
301 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
302 {
303 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
304 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
305
306 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
307 }
308
309 static LLVMValueRef
310 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
311 {
312 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
313 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
315
316 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
321 {
322 LLVMValueRef patch0_patch_data_offset =
323 get_tcs_out_patch0_patch_data_offset(ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
326
327 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
328 }
329
330 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
331 {
332 unsigned tcs_out_vertices =
333 ctx->shader->selector ?
334 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
335
336 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
337 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
338 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
339
340 return si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 6);
341 }
342
343 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
344 {
345 unsigned stride;
346
347 switch (ctx->type) {
348 case PIPE_SHADER_VERTEX:
349 stride = ctx->shader->selector->lshs_vertex_stride / 4;
350 return LLVMConstInt(ctx->i32, stride, 0);
351
352 case PIPE_SHADER_TESS_CTRL:
353 if (ctx->screen->info.chip_class >= GFX9 &&
354 ctx->shader->is_monolithic) {
355 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
356 return LLVMConstInt(ctx->i32, stride, 0);
357 }
358 return si_unpack_param(ctx, ctx->vs_state_bits, 24, 8);
359
360 default:
361 assert(0);
362 return NULL;
363 }
364 }
365
366 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
367 LLVMValueRef i32, unsigned index)
368 {
369 assert(index <= 1);
370
371 if (index == 1)
372 return LLVMBuildAShr(ctx->ac.builder, i32,
373 LLVMConstInt(ctx->i32, 16, 0), "");
374
375 return LLVMBuildSExt(ctx->ac.builder,
376 LLVMBuildTrunc(ctx->ac.builder, i32,
377 ctx->ac.i16, ""),
378 ctx->i32, "");
379 }
380
381 void si_llvm_load_input_vs(
382 struct si_shader_context *ctx,
383 unsigned input_index,
384 LLVMValueRef out[4])
385 {
386 const struct si_shader_info *info = &ctx->shader->selector->info;
387 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
388
389 if (vs_blit_property) {
390 LLVMValueRef vertex_id = ctx->abi.vertex_id;
391 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
392 LLVMIntULE, vertex_id,
393 ctx->i32_1, "");
394 /* Use LLVMIntNE, because we have 3 vertices and only
395 * the middle one should use y2.
396 */
397 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
398 LLVMIntNE, vertex_id,
399 ctx->i32_1, "");
400
401 unsigned param_vs_blit_inputs = ctx->vs_blit_inputs.arg_index;
402 if (input_index == 0) {
403 /* Position: */
404 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
405 param_vs_blit_inputs);
406 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
407 param_vs_blit_inputs + 1);
408
409 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
410 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
411 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
412 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
413
414 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
415 x1, x2, "");
416 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
417 y1, y2, "");
418
419 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
420 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
421 out[2] = LLVMGetParam(ctx->main_fn,
422 param_vs_blit_inputs + 2);
423 out[3] = ctx->ac.f32_1;
424 return;
425 }
426
427 /* Color or texture coordinates: */
428 assert(input_index == 1);
429
430 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
431 for (int i = 0; i < 4; i++) {
432 out[i] = LLVMGetParam(ctx->main_fn,
433 param_vs_blit_inputs + 3 + i);
434 }
435 } else {
436 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
437 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
438 param_vs_blit_inputs + 3);
439 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
440 param_vs_blit_inputs + 4);
441 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
442 param_vs_blit_inputs + 5);
443 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
444 param_vs_blit_inputs + 6);
445
446 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
447 x1, x2, "");
448 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
449 y1, y2, "");
450 out[2] = LLVMGetParam(ctx->main_fn,
451 param_vs_blit_inputs + 7);
452 out[3] = LLVMGetParam(ctx->main_fn,
453 param_vs_blit_inputs + 8);
454 }
455 return;
456 }
457
458 unsigned num_vbos_in_user_sgprs = ctx->shader->selector->num_vbos_in_user_sgprs;
459 union si_vs_fix_fetch fix_fetch;
460 LLVMValueRef vb_desc;
461 LLVMValueRef vertex_index;
462 LLVMValueRef tmp;
463
464 if (input_index < num_vbos_in_user_sgprs) {
465 vb_desc = ac_get_arg(&ctx->ac, ctx->vb_descriptors[input_index]);
466 } else {
467 unsigned index= input_index - num_vbos_in_user_sgprs;
468 vb_desc = ac_build_load_to_sgpr(&ctx->ac,
469 ac_get_arg(&ctx->ac, ctx->vertex_buffers),
470 LLVMConstInt(ctx->i32, index, 0));
471 }
472
473 vertex_index = LLVMGetParam(ctx->main_fn,
474 ctx->vertex_index0.arg_index +
475 input_index);
476
477 /* Use the open-coded implementation for all loads of doubles and
478 * of dword-sized data that needs fixups. We need to insert conversion
479 * code anyway, and the amd/common code does it for us.
480 *
481 * Note: On LLVM <= 8, we can only open-code formats with
482 * channel size >= 4 bytes.
483 */
484 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
485 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
486 if (opencode ||
487 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
488 (fix_fetch.u.log_size == 2)) {
489 tmp = ac_build_opencoded_load_format(
490 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
491 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
492 vb_desc, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
493 for (unsigned i = 0; i < 4; ++i)
494 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
495 return;
496 }
497
498 /* Do multiple loads for special formats. */
499 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
500 LLVMValueRef fetches[4];
501 unsigned num_fetches;
502 unsigned fetch_stride;
503 unsigned channels_per_fetch;
504
505 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
506 num_fetches = MIN2(required_channels, 3);
507 fetch_stride = 1 << fix_fetch.u.log_size;
508 channels_per_fetch = 1;
509 } else {
510 num_fetches = 1;
511 fetch_stride = 0;
512 channels_per_fetch = required_channels;
513 }
514
515 for (unsigned i = 0; i < num_fetches; ++i) {
516 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
517 fetches[i] = ac_build_buffer_load_format(&ctx->ac, vb_desc, vertex_index, voffset,
518 channels_per_fetch, 0, true);
519 }
520
521 if (num_fetches == 1 && channels_per_fetch > 1) {
522 LLVMValueRef fetch = fetches[0];
523 for (unsigned i = 0; i < channels_per_fetch; ++i) {
524 tmp = LLVMConstInt(ctx->i32, i, false);
525 fetches[i] = LLVMBuildExtractElement(
526 ctx->ac.builder, fetch, tmp, "");
527 }
528 num_fetches = channels_per_fetch;
529 channels_per_fetch = 1;
530 }
531
532 for (unsigned i = num_fetches; i < 4; ++i)
533 fetches[i] = LLVMGetUndef(ctx->f32);
534
535 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
536 required_channels == 4) {
537 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
538 fetches[3] = ctx->ac.i32_1;
539 else
540 fetches[3] = ctx->ac.f32_1;
541 } else if (fix_fetch.u.log_size == 3 &&
542 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
543 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
544 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
545 required_channels == 4) {
546 /* For 2_10_10_10, the hardware returns an unsigned value;
547 * convert it to a signed one.
548 */
549 LLVMValueRef tmp = fetches[3];
550 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
551
552 /* First, recover the sign-extended signed integer value. */
553 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
554 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
555 else
556 tmp = ac_to_integer(&ctx->ac, tmp);
557
558 /* For the integer-like cases, do a natural sign extension.
559 *
560 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
561 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
562 * exponent.
563 */
564 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
565 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
566 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
567 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
568
569 /* Convert back to the right type. */
570 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
571 LLVMValueRef clamp;
572 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
573 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
574 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
575 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
576 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
577 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
578 }
579
580 fetches[3] = tmp;
581 }
582
583 for (unsigned i = 0; i < 4; ++i)
584 out[i] = ac_to_float(&ctx->ac, fetches[i]);
585 }
586
587 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
588 unsigned swizzle)
589 {
590 if (swizzle > 0)
591 return ctx->i32_0;
592
593 switch (ctx->type) {
594 case PIPE_SHADER_VERTEX:
595 return ac_get_arg(&ctx->ac, ctx->vs_prim_id);
596 case PIPE_SHADER_TESS_CTRL:
597 return ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id);
598 case PIPE_SHADER_TESS_EVAL:
599 return ac_get_arg(&ctx->ac, ctx->args.tes_patch_id);
600 case PIPE_SHADER_GEOMETRY:
601 return ac_get_arg(&ctx->ac, ctx->args.gs_prim_id);
602 default:
603 assert(0);
604 return ctx->i32_0;
605 }
606 }
607
608 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
609 LLVMValueRef vertex_dw_stride,
610 LLVMValueRef base_addr,
611 LLVMValueRef vertex_index,
612 LLVMValueRef param_index,
613 ubyte name, ubyte index)
614 {
615 if (vertex_dw_stride) {
616 base_addr = ac_build_imad(&ctx->ac, vertex_index,
617 vertex_dw_stride, base_addr);
618 }
619
620 if (param_index) {
621 base_addr = ac_build_imad(&ctx->ac, param_index,
622 LLVMConstInt(ctx->i32, 4, 0), base_addr);
623 }
624
625 int param = name == TGSI_SEMANTIC_PATCH ||
626 name == TGSI_SEMANTIC_TESSINNER ||
627 name == TGSI_SEMANTIC_TESSOUTER ?
628 si_shader_io_get_unique_index_patch(name, index) :
629 si_shader_io_get_unique_index(name, index, false);
630
631 /* Add the base address of the element. */
632 return LLVMBuildAdd(ctx->ac.builder, base_addr,
633 LLVMConstInt(ctx->i32, param * 4, 0), "");
634 }
635
636 /* The offchip buffer layout for TCS->TES is
637 *
638 * - attribute 0 of patch 0 vertex 0
639 * - attribute 0 of patch 0 vertex 1
640 * - attribute 0 of patch 0 vertex 2
641 * ...
642 * - attribute 0 of patch 1 vertex 0
643 * - attribute 0 of patch 1 vertex 1
644 * ...
645 * - attribute 1 of patch 0 vertex 0
646 * - attribute 1 of patch 0 vertex 1
647 * ...
648 * - per patch attribute 0 of patch 0
649 * - per patch attribute 0 of patch 1
650 * ...
651 *
652 * Note that every attribute has 4 components.
653 */
654 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
655 LLVMValueRef rel_patch_id,
656 LLVMValueRef vertex_index,
657 LLVMValueRef param_index)
658 {
659 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
660 LLVMValueRef param_stride, constant16;
661
662 vertices_per_patch = get_num_tcs_out_vertices(ctx);
663 num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6);
664 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
665 num_patches, "");
666
667 constant16 = LLVMConstInt(ctx->i32, 16, 0);
668 if (vertex_index) {
669 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
670 vertices_per_patch, vertex_index);
671 param_stride = total_vertices;
672 } else {
673 base_addr = rel_patch_id;
674 param_stride = num_patches;
675 }
676
677 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
678 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
679
680 if (!vertex_index) {
681 LLVMValueRef patch_data_offset =
682 si_unpack_param(ctx, ctx->tcs_offchip_layout, 12, 20);
683
684 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
685 patch_data_offset, "");
686 }
687 return base_addr;
688 }
689
690 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
691 struct si_shader_context *ctx,
692 LLVMValueRef vertex_index,
693 LLVMValueRef param_index,
694 ubyte name, ubyte index)
695 {
696 unsigned param_index_base;
697
698 param_index_base = name == TGSI_SEMANTIC_PATCH ||
699 name == TGSI_SEMANTIC_TESSINNER ||
700 name == TGSI_SEMANTIC_TESSOUTER ?
701 si_shader_io_get_unique_index_patch(name, index) :
702 si_shader_io_get_unique_index(name, index, false);
703
704 if (param_index) {
705 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
706 LLVMConstInt(ctx->i32, param_index_base, 0),
707 "");
708 } else {
709 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
710 }
711
712 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
713 vertex_index, param_index);
714 }
715
716 static LLVMValueRef si_build_gather_64bit(struct si_shader_context *ctx,
717 LLVMTypeRef type,
718 LLVMValueRef val1,
719 LLVMValueRef val2)
720 {
721 LLVMValueRef values[2] = {
722 ac_to_integer(&ctx->ac, val1),
723 ac_to_integer(&ctx->ac, val2),
724 };
725 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
726 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
727 }
728
729 static LLVMValueRef buffer_load(struct si_shader_context *ctx,
730 LLVMTypeRef type, unsigned swizzle,
731 LLVMValueRef buffer, LLVMValueRef offset,
732 LLVMValueRef base, bool can_speculate)
733 {
734 LLVMValueRef value, value2;
735 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
736
737 if (swizzle == ~0) {
738 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
739 0, ac_glc, can_speculate, false);
740
741 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
742 }
743
744 if (!llvm_type_is_64bit(ctx, type)) {
745 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
746 0, ac_glc, can_speculate, false);
747
748 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
749 return LLVMBuildExtractElement(ctx->ac.builder, value,
750 LLVMConstInt(ctx->i32, swizzle, 0), "");
751 }
752
753 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
754 swizzle * 4, ac_glc, can_speculate, false);
755
756 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
757 swizzle * 4 + 4, ac_glc, can_speculate, false);
758
759 return si_build_gather_64bit(ctx, type, value, value2);
760 }
761
762 /**
763 * Load from LSHS LDS storage.
764 *
765 * \param type output value type
766 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
767 * \param dw_addr address in dwords
768 */
769 static LLVMValueRef lshs_lds_load(struct si_shader_context *ctx,
770 LLVMTypeRef type, unsigned swizzle,
771 LLVMValueRef dw_addr)
772 {
773 LLVMValueRef value;
774
775 if (swizzle == ~0) {
776 LLVMValueRef values[4];
777
778 for (unsigned chan = 0; chan < 4; chan++)
779 values[chan] = lshs_lds_load(ctx, type, chan, dw_addr);
780
781 return ac_build_gather_values(&ctx->ac, values, 4);
782 }
783
784 /* Split 64-bit loads. */
785 if (llvm_type_is_64bit(ctx, type)) {
786 LLVMValueRef lo, hi;
787
788 lo = lshs_lds_load(ctx, ctx->i32, swizzle, dw_addr);
789 hi = lshs_lds_load(ctx, ctx->i32, swizzle + 1, dw_addr);
790 return si_build_gather_64bit(ctx, type, lo, hi);
791 }
792
793 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
794 LLVMConstInt(ctx->i32, swizzle, 0), "");
795
796 value = ac_lds_load(&ctx->ac, dw_addr);
797
798 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
799 }
800
801 /**
802 * Store to LSHS LDS storage.
803 *
804 * \param swizzle offset (typically 0..3)
805 * \param dw_addr address in dwords
806 * \param value value to store
807 */
808 static void lshs_lds_store(struct si_shader_context *ctx,
809 unsigned dw_offset_imm, LLVMValueRef dw_addr,
810 LLVMValueRef value)
811 {
812 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
813 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
814
815 ac_lds_store(&ctx->ac, dw_addr, value);
816 }
817
818 enum si_tess_ring {
819 TCS_FACTOR_RING,
820 TESS_OFFCHIP_RING_TCS,
821 TESS_OFFCHIP_RING_TES,
822 };
823
824 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
825 enum si_tess_ring ring)
826 {
827 LLVMBuilderRef builder = ctx->ac.builder;
828 LLVMValueRef addr = ac_get_arg(&ctx->ac,
829 ring == TESS_OFFCHIP_RING_TES ?
830 ctx->tes_offchip_addr :
831 ctx->tcs_out_lds_layout);
832
833 /* TCS only receives high 13 bits of the address. */
834 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
835 addr = LLVMBuildAnd(builder, addr,
836 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
837 }
838
839 if (ring == TCS_FACTOR_RING) {
840 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
841 addr = LLVMBuildAdd(builder, addr,
842 LLVMConstInt(ctx->i32, tf_offset, 0), "");
843 }
844
845 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
846 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
847 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
848 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
849
850 if (ctx->screen->info.chip_class >= GFX10)
851 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
852 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
853 S_008F0C_RESOURCE_LEVEL(1);
854 else
855 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
856 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
857
858 LLVMValueRef desc[4];
859 desc[0] = addr;
860 desc[1] = LLVMConstInt(ctx->i32,
861 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
862 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
863 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
864
865 return ac_build_gather_values(&ctx->ac, desc, 4);
866 }
867
868 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
869 LLVMTypeRef type,
870 LLVMValueRef vertex_index,
871 LLVMValueRef param_index,
872 unsigned const_index,
873 unsigned location,
874 unsigned driver_location,
875 unsigned component,
876 unsigned num_components,
877 bool is_patch,
878 bool is_compact,
879 bool load_input)
880 {
881 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
882 struct si_shader_info *info = &ctx->shader->selector->info;
883 LLVMValueRef dw_addr, stride;
884 ubyte name, index;
885
886 driver_location = driver_location / 4;
887
888 if (load_input) {
889 name = info->input_semantic_name[driver_location];
890 index = info->input_semantic_index[driver_location];
891 } else {
892 name = info->output_semantic_name[driver_location];
893 index = info->output_semantic_index[driver_location];
894 }
895
896 assert((name == TGSI_SEMANTIC_PATCH ||
897 name == TGSI_SEMANTIC_TESSINNER ||
898 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
899
900 if (load_input) {
901 stride = get_tcs_in_vertex_dw_stride(ctx);
902 dw_addr = get_tcs_in_current_patch_offset(ctx);
903 } else {
904 if (is_patch) {
905 stride = NULL;
906 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
907 } else {
908 stride = get_tcs_out_vertex_dw_stride(ctx);
909 dw_addr = get_tcs_out_current_patch_offset(ctx);
910 }
911 }
912
913 if (!param_index) {
914 param_index = LLVMConstInt(ctx->i32, const_index, 0);
915 }
916
917 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
918 vertex_index, param_index,
919 name, index);
920
921 LLVMValueRef value[4];
922 for (unsigned i = 0; i < num_components; i++) {
923 unsigned offset = i;
924 if (llvm_type_is_64bit(ctx, type))
925 offset *= 2;
926
927 offset += component;
928 value[i + component] = lshs_lds_load(ctx, type, offset, dw_addr);
929 }
930
931 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
932 }
933
934 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
935 LLVMTypeRef type,
936 LLVMValueRef vertex_index,
937 LLVMValueRef param_index,
938 unsigned const_index,
939 unsigned location,
940 unsigned driver_location,
941 unsigned component,
942 unsigned num_components,
943 bool is_patch,
944 bool is_compact,
945 bool load_input)
946 {
947 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
948 struct si_shader_info *info = &ctx->shader->selector->info;
949 LLVMValueRef base, addr;
950
951 driver_location = driver_location / 4;
952 ubyte name = info->input_semantic_name[driver_location];
953 ubyte index = info->input_semantic_index[driver_location];
954
955 assert((name == TGSI_SEMANTIC_PATCH ||
956 name == TGSI_SEMANTIC_TESSINNER ||
957 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
958
959 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
960
961 if (!param_index) {
962 param_index = LLVMConstInt(ctx->i32, const_index, 0);
963 }
964
965 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
966 param_index,
967 name, index);
968
969 /* TODO: This will generate rather ordinary llvm code, although it
970 * should be easy for the optimiser to fix up. In future we might want
971 * to refactor buffer_load().
972 */
973 LLVMValueRef value[4];
974 for (unsigned i = 0; i < num_components; i++) {
975 unsigned offset = i;
976 if (llvm_type_is_64bit(ctx, type)) {
977 offset *= 2;
978 if (offset == 4) {
979 ubyte name = info->input_semantic_name[driver_location + 1];
980 ubyte index = info->input_semantic_index[driver_location + 1];
981 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
982 vertex_index,
983 param_index,
984 name, index);
985 }
986
987 offset = offset % 4;
988 }
989
990 offset += component;
991 value[i + component] = buffer_load(ctx, type, offset,
992 ctx->tess_offchip_ring, base, addr, true);
993 }
994
995 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
996 }
997
998 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
999 const struct nir_variable *var,
1000 LLVMValueRef vertex_index,
1001 LLVMValueRef param_index,
1002 unsigned const_index,
1003 LLVMValueRef src,
1004 unsigned writemask)
1005 {
1006 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1007 struct si_shader_info *info = &ctx->shader->selector->info;
1008 const unsigned component = var->data.location_frac;
1009 unsigned driver_location = var->data.driver_location;
1010 LLVMValueRef dw_addr, stride;
1011 LLVMValueRef buffer, base, addr;
1012 LLVMValueRef values[8];
1013 bool skip_lds_store;
1014 bool is_tess_factor = false, is_tess_inner = false;
1015
1016 driver_location = driver_location / 4;
1017 ubyte name = info->output_semantic_name[driver_location];
1018 ubyte index = info->output_semantic_index[driver_location];
1019
1020 bool is_const = !param_index;
1021 if (!param_index)
1022 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1023
1024 const bool is_patch = var->data.patch ||
1025 var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
1026 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER;
1027
1028 assert((name == TGSI_SEMANTIC_PATCH ||
1029 name == TGSI_SEMANTIC_TESSINNER ||
1030 name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
1031
1032 if (!is_patch) {
1033 stride = get_tcs_out_vertex_dw_stride(ctx);
1034 dw_addr = get_tcs_out_current_patch_offset(ctx);
1035 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1036 vertex_index, param_index,
1037 name, index);
1038
1039 skip_lds_store = !info->reads_pervertex_outputs;
1040 } else {
1041 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1042 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1043 vertex_index, param_index,
1044 name, index);
1045
1046 skip_lds_store = !info->reads_perpatch_outputs;
1047
1048 if (is_const && const_index == 0) {
1049 int name = info->output_semantic_name[driver_location];
1050
1051 /* Always write tess factors into LDS for the TCS epilog. */
1052 if (name == TGSI_SEMANTIC_TESSINNER ||
1053 name == TGSI_SEMANTIC_TESSOUTER) {
1054 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1055 skip_lds_store = !info->reads_tessfactor_outputs &&
1056 ctx->shader->selector->info.tessfactors_are_def_in_all_invocs;
1057 is_tess_factor = true;
1058 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1059 }
1060 }
1061 }
1062
1063 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1064
1065 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
1066
1067 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1068 param_index, name, index);
1069
1070 for (unsigned chan = component; chan < 8; chan++) {
1071 if (!(writemask & (1 << chan)))
1072 continue;
1073 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1074
1075 unsigned buffer_store_offset = chan % 4;
1076 if (chan == 4) {
1077 ubyte name = info->output_semantic_name[driver_location + 1];
1078 ubyte index = info->output_semantic_index[driver_location + 1];
1079 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1080 vertex_index,
1081 param_index,
1082 name, index);
1083 }
1084
1085 /* Skip LDS stores if there is no LDS read of this output. */
1086 if (!skip_lds_store)
1087 lshs_lds_store(ctx, chan, dw_addr, value);
1088
1089 value = ac_to_integer(&ctx->ac, value);
1090 values[chan] = value;
1091
1092 if (writemask != 0xF && !is_tess_factor) {
1093 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1094 addr, base,
1095 4 * buffer_store_offset,
1096 ac_glc);
1097 }
1098
1099 /* Write tess factors into VGPRs for the epilog. */
1100 if (is_tess_factor &&
1101 ctx->shader->selector->info.tessfactors_are_def_in_all_invocs) {
1102 if (!is_tess_inner) {
1103 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1104 ctx->invoc0_tess_factors[chan]);
1105 } else if (chan < 2) {
1106 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1107 ctx->invoc0_tess_factors[4 + chan]);
1108 }
1109 }
1110 }
1111
1112 if (writemask == 0xF && !is_tess_factor) {
1113 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1114 values, 4);
1115 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1116 base, 0, ac_glc);
1117 }
1118 }
1119
1120 static LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1121 unsigned input_index,
1122 unsigned vtx_offset_param,
1123 LLVMTypeRef type,
1124 unsigned swizzle)
1125 {
1126 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1127 struct si_shader *shader = ctx->shader;
1128 LLVMValueRef vtx_offset, soffset;
1129 struct si_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[input_index];
1131 unsigned semantic_index = info->input_semantic_index[input_index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1136
1137 /* GFX9 has the ESGS ring in LDS. */
1138 if (ctx->screen->info.chip_class >= GFX9) {
1139 unsigned index = vtx_offset_param;
1140
1141 switch (index / 2) {
1142 case 0:
1143 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx01_offset,
1144 index % 2 ? 16 : 0, 16);
1145 break;
1146 case 1:
1147 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx23_offset,
1148 index % 2 ? 16 : 0, 16);
1149 break;
1150 case 2:
1151 vtx_offset = si_unpack_param(ctx, ctx->gs_vtx45_offset,
1152 index % 2 ? 16 : 0, 16);
1153 break;
1154 default:
1155 assert(0);
1156 return NULL;
1157 }
1158
1159 unsigned offset = param * 4 + swizzle;
1160 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1161 LLVMConstInt(ctx->i32, offset, false), "");
1162
1163 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1164 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1165 if (llvm_type_is_64bit(ctx, type)) {
1166 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1167 &ctx->ac.i32_1, 1, "");
1168 LLVMValueRef values[2] = {
1169 value,
1170 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1171 };
1172 value = ac_build_gather_values(&ctx->ac, values, 2);
1173 }
1174 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1175 }
1176
1177 /* GFX6: input load from the ESGS ring in memory. */
1178 if (swizzle == ~0) {
1179 LLVMValueRef values[4];
1180 unsigned chan;
1181 for (chan = 0; chan < 4; chan++) {
1182 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1183 type, chan);
1184 }
1185 return ac_build_gather_values(&ctx->ac, values, 4);
1186 }
1187
1188 /* Get the vertex offset parameter on GFX6. */
1189 LLVMValueRef gs_vtx_offset = ac_get_arg(&ctx->ac,
1190 ctx->gs_vtx_offset[vtx_offset_param]);
1191
1192 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1193 LLVMConstInt(ctx->i32, 4, 0), "");
1194
1195 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1196
1197 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1198 vtx_offset, soffset, 0, ac_glc, true, false);
1199 if (llvm_type_is_64bit(ctx, type)) {
1200 LLVMValueRef value2;
1201 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1202
1203 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1204 ctx->i32_0, vtx_offset, soffset,
1205 0, ac_glc, true, false);
1206 return si_build_gather_64bit(ctx, type, value, value2);
1207 }
1208 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1209 }
1210
1211 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1212 unsigned location,
1213 unsigned driver_location,
1214 unsigned component,
1215 unsigned num_components,
1216 unsigned vertex_index,
1217 unsigned const_index,
1218 LLVMTypeRef type)
1219 {
1220 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1221
1222 LLVMValueRef value[4];
1223 for (unsigned i = 0; i < num_components; i++) {
1224 unsigned offset = i;
1225 if (llvm_type_is_64bit(ctx, type))
1226 offset *= 2;
1227
1228 offset += component;
1229 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4 + const_index,
1230 vertex_index, type, offset);
1231 }
1232
1233 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1234 }
1235
1236 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1237 unsigned attr_index, unsigned chan,
1238 LLVMValueRef prim_mask,
1239 LLVMValueRef i, LLVMValueRef j)
1240 {
1241 if (i || j) {
1242 return ac_build_fs_interp(&ctx->ac,
1243 LLVMConstInt(ctx->i32, chan, 0),
1244 LLVMConstInt(ctx->i32, attr_index, 0),
1245 prim_mask, i, j);
1246 }
1247 return ac_build_fs_interp_mov(&ctx->ac,
1248 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1249 LLVMConstInt(ctx->i32, chan, 0),
1250 LLVMConstInt(ctx->i32, attr_index, 0),
1251 prim_mask);
1252 }
1253
1254 /**
1255 * Interpolate a fragment shader input.
1256 *
1257 * @param ctx context
1258 * @param input_index index of the input in hardware
1259 * @param semantic_name TGSI_SEMANTIC_*
1260 * @param semantic_index semantic index
1261 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1262 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1263 * @param interp_param interpolation weights (i,j)
1264 * @param prim_mask SI_PARAM_PRIM_MASK
1265 * @param face SI_PARAM_FRONT_FACE
1266 * @param result the return value (4 components)
1267 */
1268 static void interp_fs_color(struct si_shader_context *ctx,
1269 unsigned input_index,
1270 unsigned semantic_index,
1271 unsigned num_interp_inputs,
1272 unsigned colors_read_mask,
1273 LLVMValueRef interp_param,
1274 LLVMValueRef prim_mask,
1275 LLVMValueRef face,
1276 LLVMValueRef result[4])
1277 {
1278 LLVMValueRef i = NULL, j = NULL;
1279 unsigned chan;
1280
1281 /* fs.constant returns the param from the middle vertex, so it's not
1282 * really useful for flat shading. It's meant to be used for custom
1283 * interpolation (but the intrinsic can't fetch from the other two
1284 * vertices).
1285 *
1286 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1287 * to do the right thing. The only reason we use fs.constant is that
1288 * fs.interp cannot be used on integers, because they can be equal
1289 * to NaN.
1290 *
1291 * When interp is false we will use fs.constant or for newer llvm,
1292 * amdgcn.interp.mov.
1293 */
1294 bool interp = interp_param != NULL;
1295
1296 if (interp) {
1297 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1298 LLVMVectorType(ctx->f32, 2), "");
1299
1300 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1301 ctx->i32_0, "");
1302 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1303 ctx->i32_1, "");
1304 }
1305
1306 if (ctx->shader->key.part.ps.prolog.color_two_side) {
1307 LLVMValueRef is_face_positive;
1308
1309 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1310 * otherwise it's at offset "num_inputs".
1311 */
1312 unsigned back_attr_offset = num_interp_inputs;
1313 if (semantic_index == 1 && colors_read_mask & 0xf)
1314 back_attr_offset += 1;
1315
1316 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1317 face, ctx->i32_0, "");
1318
1319 for (chan = 0; chan < 4; chan++) {
1320 LLVMValueRef front, back;
1321
1322 front = si_build_fs_interp(ctx,
1323 input_index, chan,
1324 prim_mask, i, j);
1325 back = si_build_fs_interp(ctx,
1326 back_attr_offset, chan,
1327 prim_mask, i, j);
1328
1329 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1330 is_face_positive,
1331 front,
1332 back,
1333 "");
1334 }
1335 } else {
1336 for (chan = 0; chan < 4; chan++) {
1337 result[chan] = si_build_fs_interp(ctx,
1338 input_index, chan,
1339 prim_mask, i, j);
1340 }
1341 }
1342 }
1343
1344 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1345 {
1346 return si_unpack_param(ctx, ctx->args.ancillary, 8, 4);
1347 }
1348
1349 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1350 {
1351 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1352
1353 /* For non-indexed draws, the base vertex set by the driver
1354 * (for direct draws) or the CP (for indirect draws) is the
1355 * first vertex ID, but GLSL expects 0 to be returned.
1356 */
1357 LLVMValueRef vs_state = ac_get_arg(&ctx->ac,
1358 ctx->vs_state_bits);
1359 LLVMValueRef indexed;
1360
1361 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1362 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1363
1364 return LLVMBuildSelect(ctx->ac.builder, indexed,
1365 ac_get_arg(&ctx->ac, ctx->args.base_vertex),
1366 ctx->i32_0, "");
1367 }
1368
1369 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1370 {
1371 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1372
1373 LLVMValueRef values[3];
1374 LLVMValueRef result;
1375 unsigned i;
1376 unsigned *properties = ctx->shader->selector->info.properties;
1377
1378 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1379 unsigned sizes[3] = {
1380 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1381 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1382 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1383 };
1384
1385 for (i = 0; i < 3; ++i)
1386 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1387
1388 result = ac_build_gather_values(&ctx->ac, values, 3);
1389 } else {
1390 result = ac_get_arg(&ctx->ac, ctx->block_size);
1391 }
1392
1393 return result;
1394 }
1395
1396 /**
1397 * Load a dword from a constant buffer.
1398 */
1399 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1400 LLVMValueRef resource,
1401 LLVMValueRef offset)
1402 {
1403 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1404 0, 0, true, true);
1405 }
1406
1407 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1408 {
1409 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1410 LLVMValueRef desc = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1411 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1412 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1413
1414 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1415 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1416 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1417
1418 LLVMValueRef pos[4] = {
1419 buffer_load_const(ctx, resource, offset0),
1420 buffer_load_const(ctx, resource, offset1),
1421 LLVMConstReal(ctx->f32, 0),
1422 LLVMConstReal(ctx->f32, 0)
1423 };
1424
1425 return ac_build_gather_values(&ctx->ac, pos, 4);
1426 }
1427
1428 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1429 {
1430 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1431 return ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.sample_coverage));
1432 }
1433
1434 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1435 {
1436 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1437 LLVMValueRef coord[4] = {
1438 ac_get_arg(&ctx->ac, ctx->tes_u),
1439 ac_get_arg(&ctx->ac, ctx->tes_v),
1440 ctx->ac.f32_0,
1441 ctx->ac.f32_0
1442 };
1443
1444 /* For triangles, the vector should be (u, v, 1-u-v). */
1445 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1446 PIPE_PRIM_TRIANGLES) {
1447 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1448 LLVMBuildFAdd(ctx->ac.builder,
1449 coord[0], coord[1], ""), "");
1450 }
1451 return ac_build_gather_values(&ctx->ac, coord, 4);
1452 }
1453
1454 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1455 unsigned semantic_name)
1456 {
1457 LLVMValueRef base, addr;
1458
1459 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1460
1461 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
1462 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1463 LLVMConstInt(ctx->i32, param, 0));
1464
1465 return buffer_load(ctx, ctx->f32,
1466 ~0, ctx->tess_offchip_ring, base, addr, true);
1467
1468 }
1469
1470 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1471 unsigned semantic_name)
1472 {
1473 LLVMValueRef buf, slot, val[4];
1474 int i, offset;
1475
1476 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1477 buf = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1478 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1479 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1480
1481 for (i = 0; i < 4; i++)
1482 val[i] = buffer_load_const(ctx, buf,
1483 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1484 return ac_build_gather_values(&ctx->ac, val, 4);
1485 }
1486
1487 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1488 unsigned varying_id,
1489 bool load_default_state)
1490 {
1491 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1492 unsigned semantic_name;
1493
1494 if (load_default_state) {
1495 switch (varying_id) {
1496 case VARYING_SLOT_TESS_LEVEL_INNER:
1497 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
1498 break;
1499 case VARYING_SLOT_TESS_LEVEL_OUTER:
1500 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
1501 break;
1502 default:
1503 unreachable("unknown tess level");
1504 }
1505 return load_tess_level_default(ctx, semantic_name);
1506 }
1507
1508 switch (varying_id) {
1509 case VARYING_SLOT_TESS_LEVEL_INNER:
1510 semantic_name = TGSI_SEMANTIC_TESSINNER;
1511 break;
1512 case VARYING_SLOT_TESS_LEVEL_OUTER:
1513 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1514 break;
1515 default:
1516 unreachable("unknown tess level");
1517 }
1518
1519 return load_tess_level(ctx, semantic_name);
1520
1521 }
1522
1523 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1524 {
1525 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1526 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1527 return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 13, 6);
1528 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1529 return get_num_tcs_out_vertices(ctx);
1530 else
1531 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1532 }
1533
1534 void si_declare_compute_memory(struct si_shader_context *ctx)
1535 {
1536 struct si_shader_selector *sel = ctx->shader->selector;
1537 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
1538
1539 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
1540 LLVMValueRef var;
1541
1542 assert(!ctx->ac.lds);
1543
1544 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1545 LLVMArrayType(ctx->i8, lds_size),
1546 "compute_lds",
1547 AC_ADDR_SPACE_LDS);
1548 LLVMSetAlignment(var, 64 * 1024);
1549
1550 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1551 }
1552
1553 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
1554 {
1555 LLVMValueRef ptr =
1556 ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
1557 struct si_shader_selector *sel = ctx->shader->selector;
1558
1559 /* Do the bounds checking with a descriptor, because
1560 * doing computation and manual bounds checking of 64-bit
1561 * addresses generates horrible VALU code with very high
1562 * VGPR usage and very low SIMD occupancy.
1563 */
1564 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
1565
1566 LLVMValueRef desc0, desc1;
1567 desc0 = ptr;
1568 desc1 = LLVMConstInt(ctx->i32,
1569 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1570
1571 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1572 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1573 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1574 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1575
1576 if (ctx->screen->info.chip_class >= GFX10)
1577 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1578 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
1579 S_008F0C_RESOURCE_LEVEL(1);
1580 else
1581 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1582 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1583
1584 LLVMValueRef desc_elems[] = {
1585 desc0,
1586 desc1,
1587 LLVMConstInt(ctx->i32, sel->info.constbuf0_num_slots * 16, 0),
1588 LLVMConstInt(ctx->i32, rsrc3, false)
1589 };
1590
1591 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
1592 }
1593
1594 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1595 {
1596 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1597 struct si_shader_selector *sel = ctx->shader->selector;
1598
1599 LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
1600
1601 if (sel->info.const_buffers_declared == 1 &&
1602 sel->info.shader_buffers_declared == 0) {
1603 return load_const_buffer_desc_fast_path(ctx);
1604 }
1605
1606 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1607 index = LLVMBuildAdd(ctx->ac.builder, index,
1608 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1609
1610 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1611 }
1612
1613 static LLVMValueRef
1614 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1615 {
1616 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1617 LLVMValueRef rsrc_ptr = ac_get_arg(&ctx->ac,
1618 ctx->const_and_shader_buffers);
1619
1620 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1621 index = LLVMBuildSub(ctx->ac.builder,
1622 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1623 index, "");
1624
1625 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1626 }
1627
1628 /* Initialize arguments for the shader export intrinsic */
1629 static void si_llvm_init_export_args(struct si_shader_context *ctx,
1630 LLVMValueRef *values,
1631 unsigned target,
1632 struct ac_export_args *args)
1633 {
1634 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
1635 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1636 unsigned chan;
1637 bool is_int8, is_int10;
1638
1639 /* Default is 0xf. Adjusted below depending on the format. */
1640 args->enabled_channels = 0xf; /* writemask */
1641
1642 /* Specify whether the EXEC mask represents the valid mask */
1643 args->valid_mask = 0;
1644
1645 /* Specify whether this is the last export */
1646 args->done = 0;
1647
1648 /* Specify the target we are exporting */
1649 args->target = target;
1650
1651 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1652 const struct si_shader_key *key = &ctx->shader->key;
1653 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1654 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1655
1656 assert(cbuf >= 0 && cbuf < 8);
1657 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1658 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1659 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1660 }
1661
1662 args->compr = false;
1663 args->out[0] = f32undef;
1664 args->out[1] = f32undef;
1665 args->out[2] = f32undef;
1666 args->out[3] = f32undef;
1667
1668 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1669 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1670 unsigned bits, bool hi) = NULL;
1671
1672 switch (spi_shader_col_format) {
1673 case V_028714_SPI_SHADER_ZERO:
1674 args->enabled_channels = 0; /* writemask */
1675 args->target = V_008DFC_SQ_EXP_NULL;
1676 break;
1677
1678 case V_028714_SPI_SHADER_32_R:
1679 args->enabled_channels = 1; /* writemask */
1680 args->out[0] = values[0];
1681 break;
1682
1683 case V_028714_SPI_SHADER_32_GR:
1684 args->enabled_channels = 0x3; /* writemask */
1685 args->out[0] = values[0];
1686 args->out[1] = values[1];
1687 break;
1688
1689 case V_028714_SPI_SHADER_32_AR:
1690 if (ctx->screen->info.chip_class >= GFX10) {
1691 args->enabled_channels = 0x3; /* writemask */
1692 args->out[0] = values[0];
1693 args->out[1] = values[3];
1694 } else {
1695 args->enabled_channels = 0x9; /* writemask */
1696 args->out[0] = values[0];
1697 args->out[3] = values[3];
1698 }
1699 break;
1700
1701 case V_028714_SPI_SHADER_FP16_ABGR:
1702 packf = ac_build_cvt_pkrtz_f16;
1703 break;
1704
1705 case V_028714_SPI_SHADER_UNORM16_ABGR:
1706 packf = ac_build_cvt_pknorm_u16;
1707 break;
1708
1709 case V_028714_SPI_SHADER_SNORM16_ABGR:
1710 packf = ac_build_cvt_pknorm_i16;
1711 break;
1712
1713 case V_028714_SPI_SHADER_UINT16_ABGR:
1714 packi = ac_build_cvt_pk_u16;
1715 break;
1716
1717 case V_028714_SPI_SHADER_SINT16_ABGR:
1718 packi = ac_build_cvt_pk_i16;
1719 break;
1720
1721 case V_028714_SPI_SHADER_32_ABGR:
1722 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1723 break;
1724 }
1725
1726 /* Pack f16 or norm_i16/u16. */
1727 if (packf) {
1728 for (chan = 0; chan < 2; chan++) {
1729 LLVMValueRef pack_args[2] = {
1730 values[2 * chan],
1731 values[2 * chan + 1]
1732 };
1733 LLVMValueRef packed;
1734
1735 packed = packf(&ctx->ac, pack_args);
1736 args->out[chan] = ac_to_float(&ctx->ac, packed);
1737 }
1738 args->compr = 1; /* COMPR flag */
1739 }
1740 /* Pack i16/u16. */
1741 if (packi) {
1742 for (chan = 0; chan < 2; chan++) {
1743 LLVMValueRef pack_args[2] = {
1744 ac_to_integer(&ctx->ac, values[2 * chan]),
1745 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1746 };
1747 LLVMValueRef packed;
1748
1749 packed = packi(&ctx->ac, pack_args,
1750 is_int8 ? 8 : is_int10 ? 10 : 16,
1751 chan == 1);
1752 args->out[chan] = ac_to_float(&ctx->ac, packed);
1753 }
1754 args->compr = 1; /* COMPR flag */
1755 }
1756 }
1757
1758 static void si_alpha_test(struct si_shader_context *ctx, LLVMValueRef alpha)
1759 {
1760 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1761 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
1762 [PIPE_FUNC_LESS] = LLVMRealOLT,
1763 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
1764 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
1765 [PIPE_FUNC_GREATER] = LLVMRealOGT,
1766 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
1767 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
1768 };
1769 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
1770 assert(cond);
1771
1772 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1773 SI_PARAM_ALPHA_REF);
1774 LLVMValueRef alpha_pass =
1775 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
1776 ac_build_kill_if_false(&ctx->ac, alpha_pass);
1777 } else {
1778 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
1779 }
1780 }
1781
1782 static LLVMValueRef si_scale_alpha_by_sample_mask(struct si_shader_context *ctx,
1783 LLVMValueRef alpha,
1784 unsigned samplemask_param)
1785 {
1786 LLVMValueRef coverage;
1787
1788 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1789 coverage = LLVMGetParam(ctx->main_fn,
1790 samplemask_param);
1791 coverage = ac_to_integer(&ctx->ac, coverage);
1792
1793 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
1794 ctx->i32,
1795 &coverage, 1, AC_FUNC_ATTR_READNONE);
1796
1797 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
1798 ctx->f32, "");
1799
1800 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
1801 LLVMConstReal(ctx->f32,
1802 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1803
1804 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
1805 }
1806
1807 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
1808 struct ac_export_args *pos, LLVMValueRef *out_elts)
1809 {
1810 unsigned reg_index;
1811 unsigned chan;
1812 unsigned const_chan;
1813 LLVMValueRef base_elt;
1814 LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1815 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
1816 SI_VS_CONST_CLIP_PLANES, 0);
1817 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
1818
1819 for (reg_index = 0; reg_index < 2; reg_index ++) {
1820 struct ac_export_args *args = &pos[2 + reg_index];
1821
1822 args->out[0] =
1823 args->out[1] =
1824 args->out[2] =
1825 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
1826
1827 /* Compute dot products of position and user clip plane vectors */
1828 for (chan = 0; chan < 4; chan++) {
1829 for (const_chan = 0; const_chan < 4; const_chan++) {
1830 LLVMValueRef addr =
1831 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
1832 const_chan) * 4, 0);
1833 base_elt = buffer_load_const(ctx, const_resource,
1834 addr);
1835 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
1836 out_elts[const_chan], args->out[chan]);
1837 }
1838 }
1839
1840 args->enabled_channels = 0xf;
1841 args->valid_mask = 0;
1842 args->done = 0;
1843 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
1844 args->compr = 0;
1845 }
1846 }
1847
1848 static void si_dump_streamout(struct pipe_stream_output_info *so)
1849 {
1850 unsigned i;
1851
1852 if (so->num_outputs)
1853 fprintf(stderr, "STREAMOUT\n");
1854
1855 for (i = 0; i < so->num_outputs; i++) {
1856 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1857 so->output[i].start_component;
1858 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1859 i, so->output[i].output_buffer,
1860 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1861 so->output[i].register_index,
1862 mask & 1 ? "x" : "",
1863 mask & 2 ? "y" : "",
1864 mask & 4 ? "z" : "",
1865 mask & 8 ? "w" : "");
1866 }
1867 }
1868
1869 void si_emit_streamout_output(struct si_shader_context *ctx,
1870 LLVMValueRef const *so_buffers,
1871 LLVMValueRef const *so_write_offsets,
1872 struct pipe_stream_output *stream_out,
1873 struct si_shader_output_values *shader_out)
1874 {
1875 unsigned buf_idx = stream_out->output_buffer;
1876 unsigned start = stream_out->start_component;
1877 unsigned num_comps = stream_out->num_components;
1878 LLVMValueRef out[4];
1879
1880 assert(num_comps && num_comps <= 4);
1881 if (!num_comps || num_comps > 4)
1882 return;
1883
1884 /* Load the output as int. */
1885 for (int j = 0; j < num_comps; j++) {
1886 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
1887
1888 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
1889 }
1890
1891 /* Pack the output. */
1892 LLVMValueRef vdata = NULL;
1893
1894 switch (num_comps) {
1895 case 1: /* as i32 */
1896 vdata = out[0];
1897 break;
1898 case 2: /* as v2i32 */
1899 case 3: /* as v3i32 */
1900 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
1901 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
1902 break;
1903 }
1904 /* as v4i32 (aligned to 4) */
1905 out[3] = LLVMGetUndef(ctx->i32);
1906 /* fall through */
1907 case 4: /* as v4i32 */
1908 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
1909 break;
1910 }
1911
1912 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
1913 vdata, num_comps,
1914 so_write_offsets[buf_idx],
1915 ctx->i32_0,
1916 stream_out->dst_offset * 4, ac_glc | ac_slc);
1917 }
1918
1919 /**
1920 * Write streamout data to buffers for vertex stream @p stream (different
1921 * vertex streams can occur for GS copy shaders).
1922 */
1923 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1924 struct si_shader_output_values *outputs,
1925 unsigned noutput, unsigned stream)
1926 {
1927 struct si_shader_selector *sel = ctx->shader->selector;
1928 struct pipe_stream_output_info *so = &sel->so;
1929 LLVMBuilderRef builder = ctx->ac.builder;
1930 int i;
1931
1932 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1933 LLVMValueRef so_vtx_count =
1934 si_unpack_param(ctx, ctx->streamout_config, 16, 7);
1935
1936 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1937
1938 /* can_emit = tid < so_vtx_count; */
1939 LLVMValueRef can_emit =
1940 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1941
1942 /* Emit the streamout code conditionally. This actually avoids
1943 * out-of-bounds buffer access. The hw tells us via the SGPR
1944 * (so_vtx_count) which threads are allowed to emit streamout data. */
1945 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1946 {
1947 /* The buffer offset is computed as follows:
1948 * ByteOffset = streamout_offset[buffer_id]*4 +
1949 * (streamout_write_index + thread_id)*stride[buffer_id] +
1950 * attrib_offset
1951 */
1952
1953 LLVMValueRef so_write_index =
1954 ac_get_arg(&ctx->ac,
1955 ctx->streamout_write_index);
1956
1957 /* Compute (streamout_write_index + thread_id). */
1958 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1959
1960 /* Load the descriptor and compute the write offset for each
1961 * enabled buffer. */
1962 LLVMValueRef so_write_offset[4] = {};
1963 LLVMValueRef so_buffers[4];
1964 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac,
1965 ctx->rw_buffers);
1966
1967 for (i = 0; i < 4; i++) {
1968 if (!so->stride[i])
1969 continue;
1970
1971 LLVMValueRef offset = LLVMConstInt(ctx->i32,
1972 SI_VS_STREAMOUT_BUF0 + i, 0);
1973
1974 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
1975
1976 LLVMValueRef so_offset = ac_get_arg(&ctx->ac,
1977 ctx->streamout_offset[i]);
1978 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1979
1980 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
1981 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
1982 so_offset);
1983 }
1984
1985 /* Write streamout data. */
1986 for (i = 0; i < so->num_outputs; i++) {
1987 unsigned reg = so->output[i].register_index;
1988
1989 if (reg >= noutput)
1990 continue;
1991
1992 if (stream != so->output[i].stream)
1993 continue;
1994
1995 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
1996 &so->output[i], &outputs[reg]);
1997 }
1998 }
1999 ac_build_endif(&ctx->ac, 6501);
2000 }
2001
2002 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2003 LLVMValueRef *values)
2004 {
2005 struct ac_export_args args;
2006
2007 si_llvm_init_export_args(ctx, values,
2008 V_008DFC_SQ_EXP_PARAM + index, &args);
2009 ac_build_export(&ctx->ac, &args);
2010 }
2011
2012 static void si_build_param_exports(struct si_shader_context *ctx,
2013 struct si_shader_output_values *outputs,
2014 unsigned noutput)
2015 {
2016 struct si_shader *shader = ctx->shader;
2017 unsigned param_count = 0;
2018
2019 for (unsigned i = 0; i < noutput; i++) {
2020 unsigned semantic_name = outputs[i].semantic_name;
2021 unsigned semantic_index = outputs[i].semantic_index;
2022
2023 if (outputs[i].vertex_stream[0] != 0 &&
2024 outputs[i].vertex_stream[1] != 0 &&
2025 outputs[i].vertex_stream[2] != 0 &&
2026 outputs[i].vertex_stream[3] != 0)
2027 continue;
2028
2029 switch (semantic_name) {
2030 case TGSI_SEMANTIC_LAYER:
2031 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2032 case TGSI_SEMANTIC_CLIPDIST:
2033 case TGSI_SEMANTIC_COLOR:
2034 case TGSI_SEMANTIC_BCOLOR:
2035 case TGSI_SEMANTIC_PRIMID:
2036 case TGSI_SEMANTIC_FOG:
2037 case TGSI_SEMANTIC_TEXCOORD:
2038 case TGSI_SEMANTIC_GENERIC:
2039 break;
2040 default:
2041 continue;
2042 }
2043
2044 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2045 semantic_index < SI_MAX_IO_GENERIC) &&
2046 shader->key.opt.kill_outputs &
2047 (1ull << si_shader_io_get_unique_index(semantic_name,
2048 semantic_index, true)))
2049 continue;
2050
2051 si_export_param(ctx, param_count, outputs[i].values);
2052
2053 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2054 shader->info.vs_output_param_offset[i] = param_count++;
2055 }
2056
2057 shader->info.nr_param_exports = param_count;
2058 }
2059
2060 /**
2061 * Vertex color clamping.
2062 *
2063 * This uses a state constant loaded in a user data SGPR and
2064 * an IF statement is added that clamps all colors if the constant
2065 * is true.
2066 */
2067 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2068 struct si_shader_output_values *outputs,
2069 unsigned noutput)
2070 {
2071 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2072 bool has_colors = false;
2073
2074 /* Store original colors to alloca variables. */
2075 for (unsigned i = 0; i < noutput; i++) {
2076 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2077 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2078 continue;
2079
2080 for (unsigned j = 0; j < 4; j++) {
2081 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2082 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2083 }
2084 has_colors = true;
2085 }
2086
2087 if (!has_colors)
2088 return;
2089
2090 /* The state is in the first bit of the user SGPR. */
2091 LLVMValueRef cond = ac_get_arg(&ctx->ac, ctx->vs_state_bits);
2092 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2093
2094 ac_build_ifcc(&ctx->ac, cond, 6502);
2095
2096 /* Store clamped colors to alloca variables within the conditional block. */
2097 for (unsigned i = 0; i < noutput; i++) {
2098 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2099 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2100 continue;
2101
2102 for (unsigned j = 0; j < 4; j++) {
2103 LLVMBuildStore(ctx->ac.builder,
2104 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2105 addr[i][j]);
2106 }
2107 }
2108 ac_build_endif(&ctx->ac, 6502);
2109
2110 /* Load clamped colors */
2111 for (unsigned i = 0; i < noutput; i++) {
2112 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2113 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2114 continue;
2115
2116 for (unsigned j = 0; j < 4; j++) {
2117 outputs[i].values[j] =
2118 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2119 }
2120 }
2121 }
2122
2123 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2124 * (position and parameter data only).
2125 */
2126 void si_llvm_export_vs(struct si_shader_context *ctx,
2127 struct si_shader_output_values *outputs,
2128 unsigned noutput)
2129 {
2130 struct si_shader *shader = ctx->shader;
2131 struct ac_export_args pos_args[4] = {};
2132 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2133 unsigned pos_idx;
2134 int i;
2135
2136 si_vertex_color_clamping(ctx, outputs, noutput);
2137
2138 /* Build position exports. */
2139 for (i = 0; i < noutput; i++) {
2140 switch (outputs[i].semantic_name) {
2141 case TGSI_SEMANTIC_POSITION:
2142 si_llvm_init_export_args(ctx, outputs[i].values,
2143 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2144 break;
2145 case TGSI_SEMANTIC_PSIZE:
2146 psize_value = outputs[i].values[0];
2147 break;
2148 case TGSI_SEMANTIC_LAYER:
2149 layer_value = outputs[i].values[0];
2150 break;
2151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2152 viewport_index_value = outputs[i].values[0];
2153 break;
2154 case TGSI_SEMANTIC_EDGEFLAG:
2155 edgeflag_value = outputs[i].values[0];
2156 break;
2157 case TGSI_SEMANTIC_CLIPDIST:
2158 if (!shader->key.opt.clip_disable) {
2159 unsigned index = 2 + outputs[i].semantic_index;
2160 si_llvm_init_export_args(ctx, outputs[i].values,
2161 V_008DFC_SQ_EXP_POS + index,
2162 &pos_args[index]);
2163 }
2164 break;
2165 case TGSI_SEMANTIC_CLIPVERTEX:
2166 if (!shader->key.opt.clip_disable) {
2167 si_llvm_emit_clipvertex(ctx, pos_args,
2168 outputs[i].values);
2169 }
2170 break;
2171 }
2172 }
2173
2174 /* We need to add the position output manually if it's missing. */
2175 if (!pos_args[0].out[0]) {
2176 pos_args[0].enabled_channels = 0xf; /* writemask */
2177 pos_args[0].valid_mask = 0; /* EXEC mask */
2178 pos_args[0].done = 0; /* last export? */
2179 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2180 pos_args[0].compr = 0; /* COMPR flag */
2181 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2182 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2183 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2184 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2185 }
2186
2187 bool pos_writes_edgeflag = shader->selector->info.writes_edgeflag &&
2188 !shader->key.as_ngg;
2189
2190 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2191 if (shader->selector->info.writes_psize ||
2192 pos_writes_edgeflag ||
2193 shader->selector->info.writes_viewport_index ||
2194 shader->selector->info.writes_layer) {
2195 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2196 (pos_writes_edgeflag << 1) |
2197 (shader->selector->info.writes_layer << 2);
2198
2199 pos_args[1].valid_mask = 0; /* EXEC mask */
2200 pos_args[1].done = 0; /* last export? */
2201 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2202 pos_args[1].compr = 0; /* COMPR flag */
2203 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2204 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2205 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2206 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2207
2208 if (shader->selector->info.writes_psize)
2209 pos_args[1].out[0] = psize_value;
2210
2211 if (pos_writes_edgeflag) {
2212 /* The output is a float, but the hw expects an integer
2213 * with the first bit containing the edge flag. */
2214 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2215 edgeflag_value,
2216 ctx->i32, "");
2217 edgeflag_value = ac_build_umin(&ctx->ac,
2218 edgeflag_value,
2219 ctx->i32_1);
2220
2221 /* The LLVM intrinsic expects a float. */
2222 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2223 }
2224
2225 if (ctx->screen->info.chip_class >= GFX9) {
2226 /* GFX9 has the layer in out.z[10:0] and the viewport
2227 * index in out.z[19:16].
2228 */
2229 if (shader->selector->info.writes_layer)
2230 pos_args[1].out[2] = layer_value;
2231
2232 if (shader->selector->info.writes_viewport_index) {
2233 LLVMValueRef v = viewport_index_value;
2234
2235 v = ac_to_integer(&ctx->ac, v);
2236 v = LLVMBuildShl(ctx->ac.builder, v,
2237 LLVMConstInt(ctx->i32, 16, 0), "");
2238 v = LLVMBuildOr(ctx->ac.builder, v,
2239 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2240 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2241 pos_args[1].enabled_channels |= 1 << 2;
2242 }
2243 } else {
2244 if (shader->selector->info.writes_layer)
2245 pos_args[1].out[2] = layer_value;
2246
2247 if (shader->selector->info.writes_viewport_index) {
2248 pos_args[1].out[3] = viewport_index_value;
2249 pos_args[1].enabled_channels |= 1 << 3;
2250 }
2251 }
2252 }
2253
2254 for (i = 0; i < 4; i++)
2255 if (pos_args[i].out[0])
2256 shader->info.nr_pos_exports++;
2257
2258 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2259 * Setting valid_mask=1 prevents it and has no other effect.
2260 */
2261 if (ctx->screen->info.family == CHIP_NAVI10 ||
2262 ctx->screen->info.family == CHIP_NAVI12 ||
2263 ctx->screen->info.family == CHIP_NAVI14)
2264 pos_args[0].valid_mask = 1;
2265
2266 pos_idx = 0;
2267 for (i = 0; i < 4; i++) {
2268 if (!pos_args[i].out[0])
2269 continue;
2270
2271 /* Specify the target we are exporting */
2272 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2273
2274 if (pos_idx == shader->info.nr_pos_exports)
2275 /* Specify that this is the last export */
2276 pos_args[i].done = 1;
2277
2278 ac_build_export(&ctx->ac, &pos_args[i]);
2279 }
2280
2281 /* Build parameter exports. */
2282 si_build_param_exports(ctx, outputs, noutput);
2283 }
2284
2285 /**
2286 * Forward all outputs from the vertex shader to the TES. This is only used
2287 * for the fixed function TCS.
2288 */
2289 static void si_copy_tcs_inputs(struct si_shader_context *ctx)
2290 {
2291 LLVMValueRef invocation_id, buffer, buffer_offset;
2292 LLVMValueRef lds_vertex_stride, lds_base;
2293 uint64_t inputs;
2294
2295 invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
2296 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
2297 buffer_offset = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
2298
2299 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2300 lds_base = get_tcs_in_current_patch_offset(ctx);
2301 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
2302 lds_base);
2303
2304 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2305 while (inputs) {
2306 unsigned i = u_bit_scan64(&inputs);
2307
2308 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2309 LLVMConstInt(ctx->i32, 4 * i, 0),
2310 "");
2311
2312 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2313 get_rel_patch_id(ctx),
2314 invocation_id,
2315 LLVMConstInt(ctx->i32, i, 0));
2316
2317 LLVMValueRef value = lshs_lds_load(ctx, ctx->ac.i32, ~0, lds_ptr);
2318
2319 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2320 buffer_offset, 0, ac_glc);
2321 }
2322 }
2323
2324 static void si_write_tess_factors(struct si_shader_context *ctx,
2325 LLVMValueRef rel_patch_id,
2326 LLVMValueRef invocation_id,
2327 LLVMValueRef tcs_out_current_patch_data_offset,
2328 LLVMValueRef invoc0_tf_outer[4],
2329 LLVMValueRef invoc0_tf_inner[2])
2330 {
2331 struct si_shader *shader = ctx->shader;
2332 unsigned tess_inner_index, tess_outer_index;
2333 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2334 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2335 unsigned stride, outer_comps, inner_comps, i, offset;
2336
2337 /* Add a barrier before loading tess factors from LDS. */
2338 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2339 si_llvm_emit_barrier(ctx);
2340
2341 /* Do this only for invocation 0, because the tess levels are per-patch,
2342 * not per-vertex.
2343 *
2344 * This can't jump, because invocation 0 executes this. It should
2345 * at least mask out the loads and stores for other invocations.
2346 */
2347 ac_build_ifcc(&ctx->ac,
2348 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2349 invocation_id, ctx->i32_0, ""), 6503);
2350
2351 /* Determine the layout of one tess factor element in the buffer. */
2352 switch (shader->key.part.tcs.epilog.prim_mode) {
2353 case PIPE_PRIM_LINES:
2354 stride = 2; /* 2 dwords, 1 vec2 store */
2355 outer_comps = 2;
2356 inner_comps = 0;
2357 break;
2358 case PIPE_PRIM_TRIANGLES:
2359 stride = 4; /* 4 dwords, 1 vec4 store */
2360 outer_comps = 3;
2361 inner_comps = 1;
2362 break;
2363 case PIPE_PRIM_QUADS:
2364 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2365 outer_comps = 4;
2366 inner_comps = 2;
2367 break;
2368 default:
2369 assert(0);
2370 return;
2371 }
2372
2373 for (i = 0; i < 4; i++) {
2374 inner[i] = LLVMGetUndef(ctx->i32);
2375 outer[i] = LLVMGetUndef(ctx->i32);
2376 }
2377
2378 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2379 /* Tess factors are in VGPRs. */
2380 for (i = 0; i < outer_comps; i++)
2381 outer[i] = out[i] = invoc0_tf_outer[i];
2382 for (i = 0; i < inner_comps; i++)
2383 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2384 } else {
2385 /* Load tess_inner and tess_outer from LDS.
2386 * Any invocation can write them, so we can't get them from a temporary.
2387 */
2388 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2389 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2390
2391 lds_base = tcs_out_current_patch_data_offset;
2392 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2393 LLVMConstInt(ctx->i32,
2394 tess_inner_index * 4, 0), "");
2395 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2396 LLVMConstInt(ctx->i32,
2397 tess_outer_index * 4, 0), "");
2398
2399 for (i = 0; i < outer_comps; i++) {
2400 outer[i] = out[i] =
2401 lshs_lds_load(ctx, ctx->ac.i32, i, lds_outer);
2402 }
2403 for (i = 0; i < inner_comps; i++) {
2404 inner[i] = out[outer_comps+i] =
2405 lshs_lds_load(ctx, ctx->ac.i32, i, lds_inner);
2406 }
2407 }
2408
2409 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2410 /* For isolines, the hardware expects tess factors in the
2411 * reverse order from what NIR specifies.
2412 */
2413 LLVMValueRef tmp = out[0];
2414 out[0] = out[1];
2415 out[1] = tmp;
2416 }
2417
2418 /* Convert the outputs to vectors for stores. */
2419 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2420 vec1 = NULL;
2421
2422 if (stride > 4)
2423 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
2424
2425 /* Get the buffer. */
2426 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
2427
2428 /* Get the offset. */
2429 tf_base = ac_get_arg(&ctx->ac,
2430 ctx->tcs_factor_offset);
2431 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2432 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2433
2434 ac_build_ifcc(&ctx->ac,
2435 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2436 rel_patch_id, ctx->i32_0, ""), 6504);
2437
2438 /* Store the dynamic HS control word. */
2439 offset = 0;
2440 if (ctx->screen->info.chip_class <= GFX8) {
2441 ac_build_buffer_store_dword(&ctx->ac, buffer,
2442 LLVMConstInt(ctx->i32, 0x80000000, 0),
2443 1, ctx->i32_0, tf_base,
2444 offset, ac_glc);
2445 offset += 4;
2446 }
2447
2448 ac_build_endif(&ctx->ac, 6504);
2449
2450 /* Store the tessellation factors. */
2451 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2452 MIN2(stride, 4), byteoffset, tf_base,
2453 offset, ac_glc);
2454 offset += 16;
2455 if (vec1)
2456 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2457 stride - 4, byteoffset, tf_base,
2458 offset, ac_glc);
2459
2460 /* Store the tess factors into the offchip buffer if TES reads them. */
2461 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2462 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2463 LLVMValueRef tf_inner_offset;
2464 unsigned param_outer, param_inner;
2465
2466 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
2467 base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
2468
2469 param_outer = si_shader_io_get_unique_index_patch(
2470 TGSI_SEMANTIC_TESSOUTER, 0);
2471 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2472 LLVMConstInt(ctx->i32, param_outer, 0));
2473
2474 unsigned outer_vec_size =
2475 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
2476 outer_comps : util_next_power_of_two(outer_comps);
2477 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
2478
2479 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2480 outer_comps, tf_outer_offset,
2481 base, 0, ac_glc);
2482 if (inner_comps) {
2483 param_inner = si_shader_io_get_unique_index_patch(
2484 TGSI_SEMANTIC_TESSINNER, 0);
2485 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2486 LLVMConstInt(ctx->i32, param_inner, 0));
2487
2488 inner_vec = inner_comps == 1 ? inner[0] :
2489 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2490 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2491 inner_comps, tf_inner_offset,
2492 base, 0, ac_glc);
2493 }
2494 }
2495
2496 ac_build_endif(&ctx->ac, 6503);
2497 }
2498
2499 static LLVMValueRef
2500 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2501 struct ac_arg param, unsigned return_index)
2502 {
2503 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2504 ac_get_arg(&ctx->ac, param),
2505 return_index, "");
2506 }
2507
2508 static LLVMValueRef
2509 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2510 struct ac_arg param, unsigned return_index)
2511 {
2512 LLVMBuilderRef builder = ctx->ac.builder;
2513 LLVMValueRef p = ac_get_arg(&ctx->ac, param);
2514
2515 return LLVMBuildInsertValue(builder, ret,
2516 ac_to_float(&ctx->ac, p),
2517 return_index, "");
2518 }
2519
2520 static LLVMValueRef
2521 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
2522 struct ac_arg param, unsigned return_index)
2523 {
2524 LLVMBuilderRef builder = ctx->ac.builder;
2525 LLVMValueRef ptr = ac_get_arg(&ctx->ac, param);
2526 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
2527 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
2528 }
2529
2530 /* This only writes the tessellation factor levels. */
2531 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
2532 unsigned max_outputs,
2533 LLVMValueRef *addrs)
2534 {
2535 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2536 LLVMBuilderRef builder = ctx->ac.builder;
2537 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2538
2539 si_copy_tcs_inputs(ctx);
2540
2541 rel_patch_id = get_rel_patch_id(ctx);
2542 invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
2543 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2544
2545 if (ctx->screen->info.chip_class >= GFX9) {
2546 LLVMBasicBlockRef blocks[2] = {
2547 LLVMGetInsertBlock(builder),
2548 ctx->merged_wrap_if_entry_block
2549 };
2550 LLVMValueRef values[2];
2551
2552 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
2553
2554 values[0] = rel_patch_id;
2555 values[1] = LLVMGetUndef(ctx->i32);
2556 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2557
2558 values[0] = tf_lds_offset;
2559 values[1] = LLVMGetUndef(ctx->i32);
2560 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2561
2562 values[0] = invocation_id;
2563 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2564 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2565 }
2566
2567 /* Return epilog parameters from this function. */
2568 LLVMValueRef ret = ctx->return_value;
2569 unsigned vgpr;
2570
2571 if (ctx->screen->info.chip_class >= GFX9) {
2572 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2573 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2574 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2575 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2576 /* Tess offchip and tess factor offsets are at the beginning. */
2577 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset, 2);
2578 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset, 4);
2579 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
2580 } else {
2581 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2582 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
2583 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2584 GFX6_SGPR_TCS_OUT_LAYOUT);
2585 /* Tess offchip and tess factor offsets are after user SGPRs. */
2586 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset,
2587 GFX6_TCS_NUM_USER_SGPR);
2588 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset,
2589 GFX6_TCS_NUM_USER_SGPR + 1);
2590 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
2591 }
2592
2593 /* VGPRs */
2594 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
2595 invocation_id = ac_to_float(&ctx->ac, invocation_id);
2596 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
2597
2598 /* Leave a hole corresponding to the two input VGPRs. This ensures that
2599 * the invocation_id output does not alias the tcs_rel_ids input,
2600 * which saves a V_MOV on gfx9.
2601 */
2602 vgpr += 2;
2603
2604 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2605 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2606
2607 if (ctx->shader->selector->info.tessfactors_are_def_in_all_invocs) {
2608 vgpr++; /* skip the tess factor LDS offset */
2609 for (unsigned i = 0; i < 6; i++) {
2610 LLVMValueRef value =
2611 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
2612 value = ac_to_float(&ctx->ac, value);
2613 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
2614 }
2615 } else {
2616 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2617 }
2618 ctx->return_value = ret;
2619 }
2620
2621 /* Pass TCS inputs from LS to TCS on GFX9. */
2622 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
2623 {
2624 LLVMValueRef ret = ctx->return_value;
2625
2626 ret = si_insert_input_ptr(ctx, ret, ctx->other_const_and_shader_buffers, 0);
2627 ret = si_insert_input_ptr(ctx, ret, ctx->other_samplers_and_images, 1);
2628 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset, 2);
2629 ret = si_insert_input_ret(ctx, ret, ctx->merged_wave_info, 3);
2630 ret = si_insert_input_ret(ctx, ret, ctx->tcs_factor_offset, 4);
2631 ret = si_insert_input_ret(ctx, ret, ctx->merged_scratch_offset, 5);
2632
2633 ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers,
2634 8 + SI_SGPR_RW_BUFFERS);
2635 ret = si_insert_input_ptr(ctx, ret,
2636 ctx->bindless_samplers_and_images,
2637 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
2638
2639 ret = si_insert_input_ret(ctx, ret, ctx->vs_state_bits,
2640 8 + SI_SGPR_VS_STATE_BITS);
2641
2642 ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout,
2643 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2644 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_offsets,
2645 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
2646 ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout,
2647 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2648
2649 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
2650 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
2651 ac_to_float(&ctx->ac,
2652 ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id)),
2653 vgpr++, "");
2654 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
2655 ac_to_float(&ctx->ac,
2656 ac_get_arg(&ctx->ac, ctx->args.tcs_rel_ids)),
2657 vgpr++, "");
2658 ctx->return_value = ret;
2659 }
2660
2661 /* Pass GS inputs from ES to GS on GFX9. */
2662 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
2663 {
2664 LLVMValueRef ret = ctx->return_value;
2665
2666 ret = si_insert_input_ptr(ctx, ret, ctx->other_const_and_shader_buffers, 0);
2667 ret = si_insert_input_ptr(ctx, ret, ctx->other_samplers_and_images, 1);
2668 if (ctx->shader->key.as_ngg)
2669 ret = si_insert_input_ptr(ctx, ret, ctx->gs_tg_info, 2);
2670 else
2671 ret = si_insert_input_ret(ctx, ret, ctx->gs2vs_offset, 2);
2672 ret = si_insert_input_ret(ctx, ret, ctx->merged_wave_info, 3);
2673 ret = si_insert_input_ret(ctx, ret, ctx->merged_scratch_offset, 5);
2674
2675 ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers,
2676 8 + SI_SGPR_RW_BUFFERS);
2677 ret = si_insert_input_ptr(ctx, ret,
2678 ctx->bindless_samplers_and_images,
2679 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
2680 if (ctx->screen->use_ngg) {
2681 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits,
2682 8 + SI_SGPR_VS_STATE_BITS);
2683 }
2684
2685 unsigned vgpr;
2686 if (ctx->type == PIPE_SHADER_VERTEX)
2687 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
2688 else
2689 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
2690
2691 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx01_offset, vgpr++);
2692 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx23_offset, vgpr++);
2693 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_prim_id, vgpr++);
2694 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_invocation_id, vgpr++);
2695 ret = si_insert_input_ret_float(ctx, ret, ctx->gs_vtx45_offset, vgpr++);
2696 ctx->return_value = ret;
2697 }
2698
2699 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
2700 unsigned max_outputs,
2701 LLVMValueRef *addrs)
2702 {
2703 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2704 struct si_shader *shader = ctx->shader;
2705 struct si_shader_info *info = &shader->selector->info;
2706 unsigned i, chan;
2707 LLVMValueRef vertex_id = ac_get_arg(&ctx->ac, ctx->rel_auto_id);
2708 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
2709 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2710 vertex_dw_stride, "");
2711
2712 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2713 * its inputs from it. */
2714 for (i = 0; i < info->num_outputs; i++) {
2715 unsigned name = info->output_semantic_name[i];
2716 unsigned index = info->output_semantic_index[i];
2717
2718 /* The ARB_shader_viewport_layer_array spec contains the
2719 * following issue:
2720 *
2721 * 2) What happens if gl_ViewportIndex or gl_Layer is
2722 * written in the vertex shader and a geometry shader is
2723 * present?
2724 *
2725 * RESOLVED: The value written by the last vertex processing
2726 * stage is used. If the last vertex processing stage
2727 * (vertex, tessellation evaluation or geometry) does not
2728 * statically assign to gl_ViewportIndex or gl_Layer, index
2729 * or layer zero is assumed.
2730 *
2731 * So writes to those outputs in VS-as-LS are simply ignored.
2732 */
2733 if (name == TGSI_SEMANTIC_LAYER ||
2734 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2735 continue;
2736
2737 int param = si_shader_io_get_unique_index(name, index, false);
2738 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2739 LLVMConstInt(ctx->i32, param * 4, 0), "");
2740
2741 for (chan = 0; chan < 4; chan++) {
2742 if (!(info->output_usagemask[i] & (1 << chan)))
2743 continue;
2744
2745 lshs_lds_store(ctx, chan, dw_addr,
2746 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
2747 }
2748 }
2749
2750 if (ctx->screen->info.chip_class >= GFX9)
2751 si_set_ls_return_value_for_tcs(ctx);
2752 }
2753
2754 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
2755 unsigned max_outputs,
2756 LLVMValueRef *addrs)
2757 {
2758 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2759 struct si_shader *es = ctx->shader;
2760 struct si_shader_info *info = &es->selector->info;
2761 LLVMValueRef lds_base = NULL;
2762 unsigned chan;
2763 int i;
2764
2765 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
2766 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
2767 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2768 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->merged_wave_info, 24, 4);
2769 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2770 LLVMBuildMul(ctx->ac.builder, wave_idx,
2771 LLVMConstInt(ctx->i32, ctx->ac.wave_size, false), ""), "");
2772 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2773 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
2774 }
2775
2776 for (i = 0; i < info->num_outputs; i++) {
2777 int param;
2778
2779 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2780 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2781 continue;
2782
2783 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
2784 info->output_semantic_index[i], false);
2785
2786 for (chan = 0; chan < 4; chan++) {
2787 if (!(info->output_usagemask[i] & (1 << chan)))
2788 continue;
2789
2790 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
2791 out_val = ac_to_integer(&ctx->ac, out_val);
2792
2793 /* GFX9 has the ESGS ring in LDS. */
2794 if (ctx->screen->info.chip_class >= GFX9) {
2795 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
2796 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
2797 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
2798 continue;
2799 }
2800
2801 ac_build_buffer_store_dword(&ctx->ac,
2802 ctx->esgs_ring,
2803 out_val, 1, NULL,
2804 ac_get_arg(&ctx->ac, ctx->es2gs_offset),
2805 (4 * param + chan) * 4,
2806 ac_glc | ac_slc | ac_swizzled);
2807 }
2808 }
2809
2810 if (ctx->screen->info.chip_class >= GFX9)
2811 si_set_es_return_value_for_gs(ctx);
2812 }
2813
2814 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
2815 {
2816 if (ctx->screen->info.chip_class >= GFX9)
2817 return si_unpack_param(ctx, ctx->merged_wave_info, 16, 8);
2818 else
2819 return ac_get_arg(&ctx->ac, ctx->gs_wave_id);
2820 }
2821
2822 static void emit_gs_epilogue(struct si_shader_context *ctx)
2823 {
2824 if (ctx->shader->key.as_ngg) {
2825 gfx10_ngg_gs_emit_epilogue(ctx);
2826 return;
2827 }
2828
2829 if (ctx->screen->info.chip_class >= GFX10)
2830 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
2831
2832 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2833 si_get_gs_wave_id(ctx));
2834
2835 if (ctx->screen->info.chip_class >= GFX9)
2836 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
2837 }
2838
2839 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
2840 unsigned max_outputs,
2841 LLVMValueRef *addrs)
2842 {
2843 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2844 struct si_shader_info UNUSED *info = &ctx->shader->selector->info;
2845
2846 assert(info->num_outputs <= max_outputs);
2847
2848 emit_gs_epilogue(ctx);
2849 }
2850
2851 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
2852 unsigned max_outputs,
2853 LLVMValueRef *addrs)
2854 {
2855 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2856 struct si_shader_info *info = &ctx->shader->selector->info;
2857 struct si_shader_output_values *outputs = NULL;
2858 int i,j;
2859
2860 assert(!ctx->shader->is_gs_copy_shader);
2861 assert(info->num_outputs <= max_outputs);
2862
2863 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 outputs[i].semantic_name = info->output_semantic_name[i];
2867 outputs[i].semantic_index = info->output_semantic_index[i];
2868
2869 for (j = 0; j < 4; j++) {
2870 outputs[i].values[j] =
2871 LLVMBuildLoad(ctx->ac.builder,
2872 addrs[4 * i + j],
2873 "");
2874 outputs[i].vertex_stream[j] =
2875 (info->output_streams[i] >> (2 * j)) & 3;
2876 }
2877 }
2878
2879 if (!ctx->screen->use_ngg_streamout &&
2880 ctx->shader->selector->so.num_outputs)
2881 si_llvm_emit_streamout(ctx, outputs, i, 0);
2882
2883 /* Export PrimitiveID. */
2884 if (ctx->shader->key.mono.u.vs_export_prim_id) {
2885 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
2886 outputs[i].semantic_index = 0;
2887 outputs[i].values[0] = ac_to_float(&ctx->ac, si_get_primitive_id(ctx, 0));
2888 for (j = 1; j < 4; j++)
2889 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
2890
2891 memset(outputs[i].vertex_stream, 0,
2892 sizeof(outputs[i].vertex_stream));
2893 i++;
2894 }
2895
2896 si_llvm_export_vs(ctx, outputs, i);
2897 FREE(outputs);
2898 }
2899
2900 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
2901 unsigned max_outputs,
2902 LLVMValueRef *addrs)
2903 {
2904 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2905 struct si_shader_info *info = &ctx->shader->selector->info;
2906 LLVMValueRef pos[4] = {};
2907
2908 assert(info->num_outputs <= max_outputs);
2909
2910 for (unsigned i = 0; i < info->num_outputs; i++) {
2911 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
2912 continue;
2913
2914 for (unsigned chan = 0; chan < 4; chan++)
2915 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
2916 break;
2917 }
2918 assert(pos[0] != NULL);
2919
2920 /* Return the position output. */
2921 LLVMValueRef ret = ctx->return_value;
2922 for (unsigned chan = 0; chan < 4; chan++)
2923 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
2924 ctx->return_value = ret;
2925 }
2926
2927 struct si_ps_exports {
2928 unsigned num;
2929 struct ac_export_args args[10];
2930 };
2931
2932 static void si_export_mrt_z(struct si_shader_context *ctx,
2933 LLVMValueRef depth, LLVMValueRef stencil,
2934 LLVMValueRef samplemask, struct si_ps_exports *exp)
2935 {
2936 struct ac_export_args args;
2937
2938 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2939
2940 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2941 }
2942
2943 static void si_export_mrt_color(struct si_shader_context *ctx,
2944 LLVMValueRef *color, unsigned index,
2945 unsigned samplemask_param,
2946 bool is_last, struct si_ps_exports *exp)
2947 {
2948 int i;
2949
2950 /* Clamp color */
2951 if (ctx->shader->key.part.ps.epilog.clamp_color)
2952 for (i = 0; i < 4; i++)
2953 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2954
2955 /* Alpha to one */
2956 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2957 color[3] = ctx->ac.f32_1;
2958
2959 /* Alpha test */
2960 if (index == 0 &&
2961 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2962 si_alpha_test(ctx, color[3]);
2963
2964 /* Line & polygon smoothing */
2965 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2966 color[3] = si_scale_alpha_by_sample_mask(ctx, color[3],
2967 samplemask_param);
2968
2969 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2970 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2971 struct ac_export_args args[8];
2972 int c, last = -1;
2973
2974 /* Get the export arguments, also find out what the last one is. */
2975 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2976 si_llvm_init_export_args(ctx, color,
2977 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2978 if (args[c].enabled_channels)
2979 last = c;
2980 }
2981
2982 /* Emit all exports. */
2983 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2984 if (is_last && last == c) {
2985 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2986 args[c].done = 1; /* DONE bit */
2987 } else if (!args[c].enabled_channels)
2988 continue; /* unnecessary NULL export */
2989
2990 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2991 }
2992 } else {
2993 struct ac_export_args args;
2994
2995 /* Export */
2996 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
2997 &args);
2998 if (is_last) {
2999 args.valid_mask = 1; /* whether the EXEC mask is valid */
3000 args.done = 1; /* DONE bit */
3001 } else if (!args.enabled_channels)
3002 return; /* unnecessary NULL export */
3003
3004 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3005 }
3006 }
3007
3008 static void si_emit_ps_exports(struct si_shader_context *ctx,
3009 struct si_ps_exports *exp)
3010 {
3011 for (unsigned i = 0; i < exp->num; i++)
3012 ac_build_export(&ctx->ac, &exp->args[i]);
3013 }
3014
3015 /**
3016 * Return PS outputs in this order:
3017 *
3018 * v[0:3] = color0.xyzw
3019 * v[4:7] = color1.xyzw
3020 * ...
3021 * vN+0 = Depth
3022 * vN+1 = Stencil
3023 * vN+2 = SampleMask
3024 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3025 *
3026 * The alpha-ref SGPR is returned via its original location.
3027 */
3028 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3029 unsigned max_outputs,
3030 LLVMValueRef *addrs)
3031 {
3032 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3033 struct si_shader *shader = ctx->shader;
3034 struct si_shader_info *info = &shader->selector->info;
3035 LLVMBuilderRef builder = ctx->ac.builder;
3036 unsigned i, j, first_vgpr, vgpr;
3037
3038 LLVMValueRef color[8][4] = {};
3039 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3040 LLVMValueRef ret;
3041
3042 if (ctx->postponed_kill)
3043 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3044
3045 /* Read the output values. */
3046 for (i = 0; i < info->num_outputs; i++) {
3047 unsigned semantic_name = info->output_semantic_name[i];
3048 unsigned semantic_index = info->output_semantic_index[i];
3049
3050 switch (semantic_name) {
3051 case TGSI_SEMANTIC_COLOR:
3052 assert(semantic_index < 8);
3053 for (j = 0; j < 4; j++) {
3054 LLVMValueRef ptr = addrs[4 * i + j];
3055 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3056 color[semantic_index][j] = result;
3057 }
3058 break;
3059 case TGSI_SEMANTIC_POSITION:
3060 depth = LLVMBuildLoad(builder,
3061 addrs[4 * i + 0], "");
3062 break;
3063 case TGSI_SEMANTIC_STENCIL:
3064 stencil = LLVMBuildLoad(builder,
3065 addrs[4 * i + 0], "");
3066 break;
3067 case TGSI_SEMANTIC_SAMPLEMASK:
3068 samplemask = LLVMBuildLoad(builder,
3069 addrs[4 * i + 0], "");
3070 break;
3071 default:
3072 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3073 semantic_name);
3074 }
3075 }
3076
3077 /* Fill the return structure. */
3078 ret = ctx->return_value;
3079
3080 /* Set SGPRs. */
3081 ret = LLVMBuildInsertValue(builder, ret,
3082 ac_to_integer(&ctx->ac,
3083 LLVMGetParam(ctx->main_fn,
3084 SI_PARAM_ALPHA_REF)),
3085 SI_SGPR_ALPHA_REF, "");
3086
3087 /* Set VGPRs */
3088 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3089 for (i = 0; i < ARRAY_SIZE(color); i++) {
3090 if (!color[i][0])
3091 continue;
3092
3093 for (j = 0; j < 4; j++)
3094 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3095 }
3096 if (depth)
3097 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3098 if (stencil)
3099 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3100 if (samplemask)
3101 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3102
3103 /* Add the input sample mask for smoothing at the end. */
3104 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3105 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3106 ret = LLVMBuildInsertValue(builder, ret,
3107 LLVMGetParam(ctx->main_fn,
3108 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3109
3110 ctx->return_value = ret;
3111 }
3112
3113 /* Emit one vertex from the geometry shader */
3114 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
3115 unsigned stream,
3116 LLVMValueRef *addrs)
3117 {
3118 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3119
3120 if (ctx->shader->key.as_ngg) {
3121 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
3122 return;
3123 }
3124
3125 struct si_shader_info *info = &ctx->shader->selector->info;
3126 struct si_shader *shader = ctx->shader;
3127 LLVMValueRef soffset = ac_get_arg(&ctx->ac, ctx->gs2vs_offset);
3128 LLVMValueRef gs_next_vertex;
3129 LLVMValueRef can_emit;
3130 unsigned chan, offset;
3131 int i;
3132
3133 /* Write vertex attribute values to GSVS ring */
3134 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
3135 ctx->gs_next_vertex[stream],
3136 "");
3137
3138 /* If this thread has already emitted the declared maximum number of
3139 * vertices, skip the write: excessive vertex emissions are not
3140 * supposed to have any effect.
3141 *
3142 * If the shader has no writes to memory, kill it instead. This skips
3143 * further memory loads and may allow LLVM to skip to the end
3144 * altogether.
3145 */
3146 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
3147 LLVMConstInt(ctx->i32,
3148 shader->selector->gs_max_out_vertices, 0), "");
3149
3150 bool use_kill = !info->writes_memory;
3151 if (use_kill) {
3152 ac_build_kill_if_false(&ctx->ac, can_emit);
3153 } else {
3154 ac_build_ifcc(&ctx->ac, can_emit, 6505);
3155 }
3156
3157 offset = 0;
3158 for (i = 0; i < info->num_outputs; i++) {
3159 for (chan = 0; chan < 4; chan++) {
3160 if (!(info->output_usagemask[i] & (1 << chan)) ||
3161 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
3162 continue;
3163
3164 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3165 LLVMValueRef voffset =
3166 LLVMConstInt(ctx->i32, offset *
3167 shader->selector->gs_max_out_vertices, 0);
3168 offset++;
3169
3170 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
3171 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
3172 LLVMConstInt(ctx->i32, 4, 0), "");
3173
3174 out_val = ac_to_integer(&ctx->ac, out_val);
3175
3176 ac_build_buffer_store_dword(&ctx->ac,
3177 ctx->gsvs_ring[stream],
3178 out_val, 1,
3179 voffset, soffset, 0,
3180 ac_glc | ac_slc | ac_swizzled);
3181 }
3182 }
3183
3184 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
3185 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
3186
3187 /* Signal vertex emission if vertex data was written. */
3188 if (offset) {
3189 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
3190 si_get_gs_wave_id(ctx));
3191 }
3192
3193 if (!use_kill)
3194 ac_build_endif(&ctx->ac, 6505);
3195 }
3196
3197 /* Cut one primitive from the geometry shader */
3198 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
3199 unsigned stream)
3200 {
3201 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3202
3203 if (ctx->shader->key.as_ngg) {
3204 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
3205 return;
3206 }
3207
3208 /* Signal primitive cut */
3209 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
3210 si_get_gs_wave_id(ctx));
3211 }
3212
3213 static void si_llvm_emit_barrier(struct si_shader_context *ctx)
3214 {
3215 /* GFX6 only (thanks to a hw bug workaround):
3216 * The real barrier instruction isn’t needed, because an entire patch
3217 * always fits into a single wave.
3218 */
3219 if (ctx->screen->info.chip_class == GFX6 &&
3220 ctx->type == PIPE_SHADER_TESS_CTRL) {
3221 ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE);
3222 return;
3223 }
3224
3225 ac_build_s_barrier(&ctx->ac);
3226 }
3227
3228 static void declare_streamout_params(struct si_shader_context *ctx,
3229 struct pipe_stream_output_info *so)
3230 {
3231 if (ctx->screen->use_ngg_streamout) {
3232 if (ctx->type == PIPE_SHADER_TESS_EVAL)
3233 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
3234 return;
3235 }
3236
3237 /* Streamout SGPRs. */
3238 if (so->num_outputs) {
3239 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->streamout_config);
3240 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->streamout_write_index);
3241 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
3242 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
3243 }
3244
3245 /* A streamout buffer offset is loaded if the stride is non-zero. */
3246 for (int i = 0; i < 4; i++) {
3247 if (!so->stride[i])
3248 continue;
3249
3250 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->streamout_offset[i]);
3251 }
3252 }
3253
3254 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
3255 {
3256 switch (shader->selector->type) {
3257 case PIPE_SHADER_VERTEX:
3258 case PIPE_SHADER_TESS_EVAL:
3259 return shader->key.as_ngg ? 128 : 0;
3260
3261 case PIPE_SHADER_TESS_CTRL:
3262 /* Return this so that LLVM doesn't remove s_barrier
3263 * instructions on chips where we use s_barrier. */
3264 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 0;
3265
3266 case PIPE_SHADER_GEOMETRY:
3267 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 0;
3268
3269 case PIPE_SHADER_COMPUTE:
3270 break; /* see below */
3271
3272 default:
3273 return 0;
3274 }
3275
3276 const unsigned *properties = shader->selector->info.properties;
3277 unsigned max_work_group_size =
3278 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
3279 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
3280 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
3281
3282 if (!max_work_group_size) {
3283 /* This is a variable group size compute shader,
3284 * compile it for the maximum possible group size.
3285 */
3286 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
3287 }
3288 return max_work_group_size;
3289 }
3290
3291 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
3292 bool assign_params)
3293 {
3294 enum ac_arg_type const_shader_buf_type;
3295
3296 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
3297 ctx->shader->selector->info.shader_buffers_declared == 0)
3298 const_shader_buf_type = AC_ARG_CONST_FLOAT_PTR;
3299 else
3300 const_shader_buf_type = AC_ARG_CONST_DESC_PTR;
3301
3302 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, const_shader_buf_type,
3303 assign_params ? &ctx->const_and_shader_buffers :
3304 &ctx->other_const_and_shader_buffers);
3305 }
3306
3307 static void declare_samplers_and_images(struct si_shader_context *ctx,
3308 bool assign_params)
3309 {
3310 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_IMAGE_PTR,
3311 assign_params ? &ctx->samplers_and_images :
3312 &ctx->other_samplers_and_images);
3313 }
3314
3315 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
3316 bool assign_params)
3317 {
3318 declare_const_and_shader_buffers(ctx, assign_params);
3319 declare_samplers_and_images(ctx, assign_params);
3320 }
3321
3322 static void declare_global_desc_pointers(struct si_shader_context *ctx)
3323 {
3324 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR,
3325 &ctx->rw_buffers);
3326 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_IMAGE_PTR,
3327 &ctx->bindless_samplers_and_images);
3328 }
3329
3330 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx)
3331 {
3332 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
3333 if (!ctx->shader->is_gs_copy_shader) {
3334 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.base_vertex);
3335 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.start_instance);
3336 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.draw_id);
3337 }
3338 }
3339
3340 static void declare_vb_descriptor_input_sgprs(struct si_shader_context *ctx)
3341 {
3342 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->vertex_buffers);
3343
3344 unsigned num_vbos_in_user_sgprs = ctx->shader->selector->num_vbos_in_user_sgprs;
3345 if (num_vbos_in_user_sgprs) {
3346 unsigned user_sgprs = ctx->args.num_sgprs_used;
3347
3348 if (is_merged_shader(ctx))
3349 user_sgprs -= 8;
3350 assert(user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST);
3351
3352 /* Declare unused SGPRs to align VB descriptors to 4 SGPRs (hw requirement). */
3353 for (unsigned i = user_sgprs; i < SI_SGPR_VS_VB_DESCRIPTOR_FIRST; i++)
3354 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */
3355
3356 assert(num_vbos_in_user_sgprs <= ARRAY_SIZE(ctx->vb_descriptors));
3357 for (unsigned i = 0; i < num_vbos_in_user_sgprs; i++)
3358 ac_add_arg(&ctx->args, AC_ARG_SGPR, 4, AC_ARG_INT, &ctx->vb_descriptors[i]);
3359 }
3360 }
3361
3362 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
3363 unsigned *num_prolog_vgprs)
3364 {
3365 struct si_shader *shader = ctx->shader;
3366
3367 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.vertex_id);
3368 if (shader->key.as_ls) {
3369 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->rel_auto_id);
3370 if (ctx->screen->info.chip_class >= GFX10) {
3371 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */
3372 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id);
3373 } else {
3374 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id);
3375 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
3376 }
3377 } else if (ctx->screen->info.chip_class >= GFX10) {
3378 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */
3379 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
3380 &ctx->vs_prim_id); /* user vgpr or PrimID (legacy) */
3381 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id);
3382 } else {
3383 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id);
3384 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->vs_prim_id);
3385 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */
3386 }
3387
3388 if (!shader->is_gs_copy_shader) {
3389 /* Vertex load indices. */
3390 if (shader->selector->info.num_inputs) {
3391 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
3392 &ctx->vertex_index0);
3393 for (unsigned i = 1; i < shader->selector->info.num_inputs; i++)
3394 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL);
3395 }
3396 *num_prolog_vgprs += shader->selector->info.num_inputs;
3397 }
3398 }
3399
3400 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
3401 unsigned vs_blit_property)
3402 {
3403 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
3404 &ctx->vs_blit_inputs); /* i16 x1, y1 */
3405 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* i16 x1, y1 */
3406 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* depth */
3407
3408 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
3409 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* color0 */
3410 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* color1 */
3411 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* color2 */
3412 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* color3 */
3413 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
3414 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.x1 */
3415 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.y1 */
3416 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.x2 */
3417 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.y2 */
3418 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.z */
3419 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, NULL); /* texcoord.w */
3420 }
3421 }
3422
3423 static void declare_tes_input_vgprs(struct si_shader_context *ctx)
3424 {
3425 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &ctx->tes_u);
3426 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT, &ctx->tes_v);
3427 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->tes_rel_patch_id);
3428 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tes_patch_id);
3429 }
3430
3431 enum {
3432 /* Convenient merged shader definitions. */
3433 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
3434 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
3435 };
3436
3437 static void add_arg_checked(struct ac_shader_args *args,
3438 enum ac_arg_regfile file,
3439 unsigned registers, enum ac_arg_type type,
3440 struct ac_arg *arg,
3441 unsigned idx)
3442 {
3443 assert(args->arg_count == idx);
3444 ac_add_arg(args, file, registers, type, arg);
3445 }
3446
3447 static void create_function(struct si_shader_context *ctx)
3448 {
3449 struct si_shader *shader = ctx->shader;
3450 LLVMTypeRef returns[AC_MAX_ARGS];
3451 unsigned i, num_return_sgprs;
3452 unsigned num_returns = 0;
3453 unsigned num_prolog_vgprs = 0;
3454 unsigned type = ctx->type;
3455 unsigned vs_blit_property =
3456 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
3457
3458 memset(&ctx->args, 0, sizeof(ctx->args));
3459
3460 /* Set MERGED shaders. */
3461 if (ctx->screen->info.chip_class >= GFX9) {
3462 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
3463 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
3464 else if (shader->key.as_es || shader->key.as_ngg || type == PIPE_SHADER_GEOMETRY)
3465 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
3466 }
3467
3468 switch (type) {
3469 case PIPE_SHADER_VERTEX:
3470 declare_global_desc_pointers(ctx);
3471
3472 if (vs_blit_property) {
3473 declare_vs_blit_inputs(ctx, vs_blit_property);
3474
3475 /* VGPRs */
3476 declare_vs_input_vgprs(ctx, &num_prolog_vgprs);
3477 break;
3478 }
3479
3480 declare_per_stage_desc_pointers(ctx, true);
3481 declare_vs_specific_input_sgprs(ctx);
3482 if (!shader->is_gs_copy_shader)
3483 declare_vb_descriptor_input_sgprs(ctx);
3484
3485 if (shader->key.as_es) {
3486 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
3487 &ctx->es2gs_offset);
3488 } else if (shader->key.as_ls) {
3489 /* no extra parameters */
3490 } else {
3491 /* The locations of the other parameters are assigned dynamically. */
3492 declare_streamout_params(ctx, &shader->selector->so);
3493 }
3494
3495 /* VGPRs */
3496 declare_vs_input_vgprs(ctx, &num_prolog_vgprs);
3497
3498 /* Return values */
3499 if (shader->key.opt.vs_as_prim_discard_cs) {
3500 for (i = 0; i < 4; i++)
3501 returns[num_returns++] = ctx->f32; /* VGPRs */
3502 }
3503 break;
3504
3505 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
3506 declare_global_desc_pointers(ctx);
3507 declare_per_stage_desc_pointers(ctx, true);
3508 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
3509 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_offsets);
3510 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_layout);
3511 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
3512 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset);
3513 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_factor_offset);
3514
3515 /* VGPRs */
3516 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_patch_id);
3517 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_rel_ids);
3518
3519 /* param_tcs_offchip_offset and param_tcs_factor_offset are
3520 * placed after the user SGPRs.
3521 */
3522 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
3523 returns[num_returns++] = ctx->i32; /* SGPRs */
3524 for (i = 0; i < 11; i++)
3525 returns[num_returns++] = ctx->f32; /* VGPRs */
3526 break;
3527
3528 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
3529 /* Merged stages have 8 system SGPRs at the beginning. */
3530 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
3531 declare_per_stage_desc_pointers(ctx,
3532 ctx->type == PIPE_SHADER_TESS_CTRL);
3533 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset);
3534 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->merged_wave_info);
3535 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_factor_offset);
3536 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->merged_scratch_offset);
3537 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */
3538 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */
3539
3540 declare_global_desc_pointers(ctx);
3541 declare_per_stage_desc_pointers(ctx,
3542 ctx->type == PIPE_SHADER_VERTEX);
3543 declare_vs_specific_input_sgprs(ctx);
3544
3545 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
3546 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_offsets);
3547 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_layout);
3548 declare_vb_descriptor_input_sgprs(ctx);
3549
3550 /* VGPRs (first TCS, then VS) */
3551 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_patch_id);
3552 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_rel_ids);
3553
3554 if (ctx->type == PIPE_SHADER_VERTEX) {
3555 declare_vs_input_vgprs(ctx, &num_prolog_vgprs);
3556
3557 /* LS return values are inputs to the TCS main shader part. */
3558 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
3559 returns[num_returns++] = ctx->i32; /* SGPRs */
3560 for (i = 0; i < 2; i++)
3561 returns[num_returns++] = ctx->f32; /* VGPRs */
3562 } else {
3563 /* TCS return values are inputs to the TCS epilog.
3564 *
3565 * param_tcs_offchip_offset, param_tcs_factor_offset,
3566 * param_tcs_offchip_layout, and param_rw_buffers
3567 * should be passed to the epilog.
3568 */
3569 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
3570 returns[num_returns++] = ctx->i32; /* SGPRs */
3571 for (i = 0; i < 11; i++)
3572 returns[num_returns++] = ctx->f32; /* VGPRs */
3573 }
3574 break;
3575
3576 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
3577 /* Merged stages have 8 system SGPRs at the beginning. */
3578 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
3579 declare_per_stage_desc_pointers(ctx,
3580 ctx->type == PIPE_SHADER_GEOMETRY);
3581
3582 if (ctx->shader->key.as_ngg)
3583 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs_tg_info);
3584 else
3585 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs2vs_offset);
3586
3587 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->merged_wave_info);
3588 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset);
3589 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->merged_scratch_offset);
3590 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
3591 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
3592
3593 declare_global_desc_pointers(ctx);
3594 if (ctx->type != PIPE_SHADER_VERTEX || !vs_blit_property) {
3595 declare_per_stage_desc_pointers(ctx,
3596 (ctx->type == PIPE_SHADER_VERTEX ||
3597 ctx->type == PIPE_SHADER_TESS_EVAL));
3598 }
3599
3600 if (ctx->type == PIPE_SHADER_VERTEX) {
3601 if (vs_blit_property)
3602 declare_vs_blit_inputs(ctx, vs_blit_property);
3603 else
3604 declare_vs_specific_input_sgprs(ctx);
3605 } else {
3606 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
3607 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
3608 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tes_offchip_addr);
3609 /* Declare as many input SGPRs as the VS has. */
3610 }
3611
3612 if (ctx->type == PIPE_SHADER_VERTEX)
3613 declare_vb_descriptor_input_sgprs(ctx);
3614
3615 /* VGPRs (first GS, then VS/TES) */
3616 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx01_offset);
3617 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx23_offset);
3618 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_prim_id);
3619 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_invocation_id);
3620 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx45_offset);
3621
3622 if (ctx->type == PIPE_SHADER_VERTEX) {
3623 declare_vs_input_vgprs(ctx, &num_prolog_vgprs);
3624 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
3625 declare_tes_input_vgprs(ctx);
3626 }
3627
3628 if (ctx->shader->key.as_es &&
3629 (ctx->type == PIPE_SHADER_VERTEX ||
3630 ctx->type == PIPE_SHADER_TESS_EVAL)) {
3631 unsigned num_user_sgprs;
3632
3633 if (ctx->type == PIPE_SHADER_VERTEX)
3634 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
3635 else
3636 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
3637
3638 /* ES return values are inputs to GS. */
3639 for (i = 0; i < 8 + num_user_sgprs; i++)
3640 returns[num_returns++] = ctx->i32; /* SGPRs */
3641 for (i = 0; i < 5; i++)
3642 returns[num_returns++] = ctx->f32; /* VGPRs */
3643 }
3644 break;
3645
3646 case PIPE_SHADER_TESS_EVAL:
3647 declare_global_desc_pointers(ctx);
3648 declare_per_stage_desc_pointers(ctx, true);
3649 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
3650 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
3651 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tes_offchip_addr);
3652
3653 if (shader->key.as_es) {
3654 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset);
3655 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
3656 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->es2gs_offset);
3657 } else {
3658 declare_streamout_params(ctx, &shader->selector->so);
3659 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset);
3660 }
3661
3662 /* VGPRs */
3663 declare_tes_input_vgprs(ctx);
3664 break;
3665
3666 case PIPE_SHADER_GEOMETRY:
3667 declare_global_desc_pointers(ctx);
3668 declare_per_stage_desc_pointers(ctx, true);
3669 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs2vs_offset);
3670 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs_wave_id);
3671
3672 /* VGPRs */
3673 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[0]);
3674 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[1]);
3675 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_prim_id);
3676 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[2]);
3677 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[3]);
3678 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[4]);
3679 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx_offset[5]);
3680 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_invocation_id);
3681 break;
3682
3683 case PIPE_SHADER_FRAGMENT:
3684 declare_global_desc_pointers(ctx);
3685 declare_per_stage_desc_pointers(ctx, true);
3686 add_arg_checked(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL,
3687 SI_PARAM_ALPHA_REF);
3688 add_arg_checked(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
3689 &ctx->args.prim_mask, SI_PARAM_PRIM_MASK);
3690
3691 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT, &ctx->args.persp_sample,
3692 SI_PARAM_PERSP_SAMPLE);
3693 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT,
3694 &ctx->args.persp_center, SI_PARAM_PERSP_CENTER);
3695 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT,
3696 &ctx->args.persp_centroid, SI_PARAM_PERSP_CENTROID);
3697 add_arg_checked(&ctx->args, AC_ARG_VGPR, 3, AC_ARG_INT,
3698 NULL, SI_PARAM_PERSP_PULL_MODEL);
3699 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT,
3700 &ctx->args.linear_sample, SI_PARAM_LINEAR_SAMPLE);
3701 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT,
3702 &ctx->args.linear_center, SI_PARAM_LINEAR_CENTER);
3703 add_arg_checked(&ctx->args, AC_ARG_VGPR, 2, AC_ARG_INT,
3704 &ctx->args.linear_centroid, SI_PARAM_LINEAR_CENTROID);
3705 add_arg_checked(&ctx->args, AC_ARG_VGPR, 3, AC_ARG_FLOAT,
3706 NULL, SI_PARAM_LINE_STIPPLE_TEX);
3707 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT,
3708 &ctx->args.frag_pos[0], SI_PARAM_POS_X_FLOAT);
3709 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT,
3710 &ctx->args.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
3711 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT,
3712 &ctx->args.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
3713 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT,
3714 &ctx->args.frag_pos[3], SI_PARAM_POS_W_FLOAT);
3715 shader->info.face_vgpr_index = ctx->args.num_vgprs_used;
3716 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
3717 &ctx->args.front_face, SI_PARAM_FRONT_FACE);
3718 shader->info.ancillary_vgpr_index = ctx->args.num_vgprs_used;
3719 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
3720 &ctx->args.ancillary, SI_PARAM_ANCILLARY);
3721 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT,
3722 &ctx->args.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
3723 add_arg_checked(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
3724 &ctx->pos_fixed_pt, SI_PARAM_POS_FIXED_PT);
3725
3726 /* Color inputs from the prolog. */
3727 if (shader->selector->info.colors_read) {
3728 unsigned num_color_elements =
3729 util_bitcount(shader->selector->info.colors_read);
3730
3731 for (i = 0; i < num_color_elements; i++)
3732 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT, NULL);
3733
3734 num_prolog_vgprs += num_color_elements;
3735 }
3736
3737 /* Outputs for the epilog. */
3738 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
3739 num_returns =
3740 num_return_sgprs +
3741 util_bitcount(shader->selector->info.colors_written) * 4 +
3742 shader->selector->info.writes_z +
3743 shader->selector->info.writes_stencil +
3744 shader->selector->info.writes_samplemask +
3745 1 /* SampleMaskIn */;
3746
3747 num_returns = MAX2(num_returns,
3748 num_return_sgprs +
3749 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
3750
3751 for (i = 0; i < num_return_sgprs; i++)
3752 returns[i] = ctx->i32;
3753 for (; i < num_returns; i++)
3754 returns[i] = ctx->f32;
3755 break;
3756
3757 case PIPE_SHADER_COMPUTE:
3758 declare_global_desc_pointers(ctx);
3759 declare_per_stage_desc_pointers(ctx, true);
3760 if (shader->selector->info.uses_grid_size)
3761 ac_add_arg(&ctx->args, AC_ARG_SGPR, 3, AC_ARG_INT,
3762 &ctx->args.num_work_groups);
3763 if (shader->selector->info.uses_block_size &&
3764 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
3765 ac_add_arg(&ctx->args, AC_ARG_SGPR, 3, AC_ARG_INT, &ctx->block_size);
3766
3767 unsigned cs_user_data_dwords =
3768 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
3769 if (cs_user_data_dwords) {
3770 ac_add_arg(&ctx->args, AC_ARG_SGPR, cs_user_data_dwords, AC_ARG_INT,
3771 &ctx->cs_user_data);
3772 }
3773
3774 /* Hardware SGPRs. */
3775 for (i = 0; i < 3; i++) {
3776 if (shader->selector->info.uses_block_id[i]) {
3777 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
3778 &ctx->args.workgroup_ids[i]);
3779 }
3780 }
3781 if (shader->selector->info.uses_subgroup_info)
3782 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tg_size);
3783
3784 /* Hardware VGPRs. */
3785 ac_add_arg(&ctx->args, AC_ARG_VGPR, 3, AC_ARG_INT,
3786 &ctx->args.local_invocation_ids);
3787 break;
3788 default:
3789 assert(0 && "unimplemented shader");
3790 return;
3791 }
3792
3793 si_llvm_create_func(ctx, "main", returns, num_returns,
3794 si_get_max_workgroup_size(shader));
3795
3796 /* Reserve register locations for VGPR inputs the PS prolog may need. */
3797 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
3798 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
3799 "InitialPSInputAddr",
3800 S_0286D0_PERSP_SAMPLE_ENA(1) |
3801 S_0286D0_PERSP_CENTER_ENA(1) |
3802 S_0286D0_PERSP_CENTROID_ENA(1) |
3803 S_0286D0_LINEAR_SAMPLE_ENA(1) |
3804 S_0286D0_LINEAR_CENTER_ENA(1) |
3805 S_0286D0_LINEAR_CENTROID_ENA(1) |
3806 S_0286D0_FRONT_FACE_ENA(1) |
3807 S_0286D0_ANCILLARY_ENA(1) |
3808 S_0286D0_POS_FIXED_PT_ENA(1));
3809 }
3810
3811 shader->info.num_input_sgprs = ctx->args.num_sgprs_used;
3812 shader->info.num_input_vgprs = ctx->args.num_vgprs_used;
3813
3814 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
3815 shader->info.num_input_vgprs -= num_prolog_vgprs;
3816
3817 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
3818 if (USE_LDS_SYMBOLS && LLVM_VERSION_MAJOR >= 9) {
3819 /* The LSHS size is not known until draw time, so we append it
3820 * at the end of whatever LDS use there may be in the rest of
3821 * the shader (currently none, unless LLVM decides to do its
3822 * own LDS-based lowering).
3823 */
3824 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
3825 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
3826 "__lds_end", AC_ADDR_SPACE_LDS);
3827 LLVMSetAlignment(ctx->ac.lds, 256);
3828 } else {
3829 ac_declare_lds_as_pointer(&ctx->ac);
3830 }
3831 }
3832
3833 /* Unlike radv, we override these arguments in the prolog, so to the
3834 * API shader they appear as normal arguments.
3835 */
3836 if (ctx->type == PIPE_SHADER_VERTEX) {
3837 ctx->abi.vertex_id = ac_get_arg(&ctx->ac, ctx->args.vertex_id);
3838 ctx->abi.instance_id = ac_get_arg(&ctx->ac, ctx->args.instance_id);
3839 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
3840 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args.persp_centroid);
3841 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args.linear_centroid);
3842 }
3843 }
3844
3845 /* Ensure that the esgs ring is declared.
3846 *
3847 * We declare it with 64KB alignment as a hint that the
3848 * pointer value will always be 0.
3849 */
3850 static void declare_esgs_ring(struct si_shader_context *ctx)
3851 {
3852 if (ctx->esgs_ring)
3853 return;
3854
3855 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3856
3857 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3858 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
3859 "esgs_ring",
3860 AC_ADDR_SPACE_LDS);
3861 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3862 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3863 }
3864
3865 /**
3866 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3867 * for later use.
3868 */
3869 static void preload_ring_buffers(struct si_shader_context *ctx)
3870 {
3871 LLVMBuilderRef builder = ctx->ac.builder;
3872
3873 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
3874
3875 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
3876 if (ctx->screen->info.chip_class <= GFX8) {
3877 unsigned ring =
3878 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
3879 : SI_ES_RING_ESGS;
3880 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
3881
3882 ctx->esgs_ring =
3883 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
3884 } else {
3885 if (USE_LDS_SYMBOLS && LLVM_VERSION_MAJOR >= 9) {
3886 /* Declare the ESGS ring as an explicit LDS symbol. */
3887 declare_esgs_ring(ctx);
3888 } else {
3889 ac_declare_lds_as_pointer(&ctx->ac);
3890 ctx->esgs_ring = ctx->ac.lds;
3891 }
3892 }
3893 }
3894
3895 if (ctx->shader->is_gs_copy_shader) {
3896 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
3897
3898 ctx->gsvs_ring[0] =
3899 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
3900 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
3901 const struct si_shader_selector *sel = ctx->shader->selector;
3902 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
3903 LLVMValueRef base_ring;
3904
3905 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
3906
3907 /* The conceptual layout of the GSVS ring is
3908 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3909 * but the real memory layout is swizzled across
3910 * threads:
3911 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3912 * t16v0c0 ..
3913 * Override the buffer descriptor accordingly.
3914 */
3915 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
3916 uint64_t stream_offset = 0;
3917
3918 for (unsigned stream = 0; stream < 4; ++stream) {
3919 unsigned num_components;
3920 unsigned stride;
3921 unsigned num_records;
3922 LLVMValueRef ring, tmp;
3923
3924 num_components = sel->info.num_stream_output_components[stream];
3925 if (!num_components)
3926 continue;
3927
3928 stride = 4 * num_components * sel->gs_max_out_vertices;
3929
3930 /* Limit on the stride field for <= GFX7. */
3931 assert(stride < (1 << 14));
3932
3933 num_records = ctx->ac.wave_size;
3934
3935 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
3936 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
3937 tmp = LLVMBuildAdd(builder, tmp,
3938 LLVMConstInt(ctx->i64,
3939 stream_offset, 0), "");
3940 stream_offset += stride * ctx->ac.wave_size;
3941
3942 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
3943 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
3944 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
3945 tmp = LLVMBuildOr(builder, tmp,
3946 LLVMConstInt(ctx->i32,
3947 S_008F04_STRIDE(stride) |
3948 S_008F04_SWIZZLE_ENABLE(1), 0), "");
3949 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
3950 ring = LLVMBuildInsertElement(builder, ring,
3951 LLVMConstInt(ctx->i32, num_records, 0),
3952 LLVMConstInt(ctx->i32, 2, 0), "");
3953
3954 uint32_t rsrc3 =
3955 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3956 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3957 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3958 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3959 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
3960 S_008F0C_ADD_TID_ENABLE(1);
3961
3962 if (ctx->ac.chip_class >= GFX10) {
3963 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3964 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3965 S_008F0C_RESOURCE_LEVEL(1);
3966 } else {
3967 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3968 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3969 S_008F0C_ELEMENT_SIZE(1); /* element_size = 4 (bytes) */
3970 }
3971
3972 ring = LLVMBuildInsertElement(builder, ring,
3973 LLVMConstInt(ctx->i32, rsrc3, false),
3974 LLVMConstInt(ctx->i32, 3, 0), "");
3975
3976 ctx->gsvs_ring[stream] = ring;
3977 }
3978 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
3979 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
3980 }
3981 }
3982
3983 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
3984 LLVMValueRef param_rw_buffers,
3985 struct ac_arg param_pos_fixed_pt)
3986 {
3987 LLVMBuilderRef builder = ctx->ac.builder;
3988 LLVMValueRef slot, desc, offset, row, bit, address[2];
3989
3990 /* Use the fixed-point gl_FragCoord input.
3991 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
3992 * per coordinate to get the repeating effect.
3993 */
3994 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
3995 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
3996
3997 /* Load the buffer descriptor. */
3998 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
3999 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4000
4001 /* The stipple pattern is 32x32, each row has 32 bits. */
4002 offset = LLVMBuildMul(builder, address[1],
4003 LLVMConstInt(ctx->i32, 4, 0), "");
4004 row = buffer_load_const(ctx, desc, offset);
4005 row = ac_to_integer(&ctx->ac, row);
4006 bit = LLVMBuildLShr(builder, row, address[0], "");
4007 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4008 ac_build_kill_if_false(&ctx->ac, bit);
4009 }
4010
4011 /* For the UMR disassembler. */
4012 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
4013 #define DEBUGGER_NUM_MARKERS 5
4014
4015 static bool si_shader_binary_open(struct si_screen *screen,
4016 struct si_shader *shader,
4017 struct ac_rtld_binary *rtld)
4018 {
4019 const struct si_shader_selector *sel = shader->selector;
4020 const char *part_elfs[5];
4021 size_t part_sizes[5];
4022 unsigned num_parts = 0;
4023
4024 #define add_part(shader_or_part) \
4025 if (shader_or_part) { \
4026 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
4027 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
4028 num_parts++; \
4029 }
4030
4031 add_part(shader->prolog);
4032 add_part(shader->previous_stage);
4033 add_part(shader->prolog2);
4034 add_part(shader);
4035 add_part(shader->epilog);
4036
4037 #undef add_part
4038
4039 struct ac_rtld_symbol lds_symbols[2];
4040 unsigned num_lds_symbols = 0;
4041
4042 if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
4043 (sel->type == PIPE_SHADER_GEOMETRY || shader->key.as_ngg)) {
4044 /* We add this symbol even on LLVM <= 8 to ensure that
4045 * shader->config.lds_size is set correctly below.
4046 */
4047 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
4048 sym->name = "esgs_ring";
4049 sym->size = shader->gs_info.esgs_ring_size;
4050 sym->align = 64 * 1024;
4051 }
4052
4053 if (shader->key.as_ngg && sel->type == PIPE_SHADER_GEOMETRY) {
4054 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
4055 sym->name = "ngg_emit";
4056 sym->size = shader->ngg.ngg_emit_size * 4;
4057 sym->align = 4;
4058 }
4059
4060 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
4061 .info = &screen->info,
4062 .options = {
4063 .halt_at_entry = screen->options.halt_shaders,
4064 },
4065 .shader_type = tgsi_processor_to_shader_stage(sel->type),
4066 .wave_size = si_get_shader_wave_size(shader),
4067 .num_parts = num_parts,
4068 .elf_ptrs = part_elfs,
4069 .elf_sizes = part_sizes,
4070 .num_shared_lds_symbols = num_lds_symbols,
4071 .shared_lds_symbols = lds_symbols });
4072
4073 if (rtld->lds_size > 0) {
4074 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
4075 shader->config.lds_size =
4076 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
4077 }
4078
4079 return ok;
4080 }
4081
4082 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
4083 {
4084 struct ac_rtld_binary rtld;
4085 si_shader_binary_open(screen, shader, &rtld);
4086 return rtld.exec_size;
4087 }
4088
4089 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
4090 {
4091 uint64_t *scratch_va = data;
4092
4093 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
4094 *value = (uint32_t)*scratch_va;
4095 return true;
4096 }
4097 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
4098 /* Enable scratch coalescing. */
4099 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
4100 S_008F04_SWIZZLE_ENABLE(1);
4101 return true;
4102 }
4103
4104 return false;
4105 }
4106
4107 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
4108 uint64_t scratch_va)
4109 {
4110 struct ac_rtld_binary binary;
4111 if (!si_shader_binary_open(sscreen, shader, &binary))
4112 return false;
4113
4114 si_resource_reference(&shader->bo, NULL);
4115 shader->bo = si_aligned_buffer_create(&sscreen->b,
4116 sscreen->info.cpdma_prefetch_writes_memory ?
4117 0 : SI_RESOURCE_FLAG_READ_ONLY,
4118 PIPE_USAGE_IMMUTABLE,
4119 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
4120 256);
4121 if (!shader->bo)
4122 return false;
4123
4124 /* Upload. */
4125 struct ac_rtld_upload_info u = {};
4126 u.binary = &binary;
4127 u.get_external_symbol = si_get_external_symbol;
4128 u.cb_data = &scratch_va;
4129 u.rx_va = shader->bo->gpu_address;
4130 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
4131 PIPE_TRANSFER_READ_WRITE |
4132 PIPE_TRANSFER_UNSYNCHRONIZED |
4133 RADEON_TRANSFER_TEMPORARY);
4134 if (!u.rx_ptr)
4135 return false;
4136
4137 bool ok = ac_rtld_upload(&u);
4138
4139 sscreen->ws->buffer_unmap(shader->bo->buf);
4140 ac_rtld_close(&binary);
4141
4142 return ok;
4143 }
4144
4145 static void si_shader_dump_disassembly(struct si_screen *screen,
4146 const struct si_shader_binary *binary,
4147 enum pipe_shader_type shader_type,
4148 unsigned wave_size,
4149 struct pipe_debug_callback *debug,
4150 const char *name, FILE *file)
4151 {
4152 struct ac_rtld_binary rtld_binary;
4153
4154 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
4155 .info = &screen->info,
4156 .shader_type = tgsi_processor_to_shader_stage(shader_type),
4157 .wave_size = wave_size,
4158 .num_parts = 1,
4159 .elf_ptrs = &binary->elf_buffer,
4160 .elf_sizes = &binary->elf_size }))
4161 return;
4162
4163 const char *disasm;
4164 size_t nbytes;
4165
4166 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
4167 goto out;
4168
4169 if (nbytes > INT_MAX)
4170 goto out;
4171
4172 if (debug && debug->debug_message) {
4173 /* Very long debug messages are cut off, so send the
4174 * disassembly one line at a time. This causes more
4175 * overhead, but on the plus side it simplifies
4176 * parsing of resulting logs.
4177 */
4178 pipe_debug_message(debug, SHADER_INFO,
4179 "Shader Disassembly Begin");
4180
4181 uint64_t line = 0;
4182 while (line < nbytes) {
4183 int count = nbytes - line;
4184 const char *nl = memchr(disasm + line, '\n', nbytes - line);
4185 if (nl)
4186 count = nl - (disasm + line);
4187
4188 if (count) {
4189 pipe_debug_message(debug, SHADER_INFO,
4190 "%.*s", count, disasm + line);
4191 }
4192
4193 line += count + 1;
4194 }
4195
4196 pipe_debug_message(debug, SHADER_INFO,
4197 "Shader Disassembly End");
4198 }
4199
4200 if (file) {
4201 fprintf(file, "Shader %s disassembly:\n", name);
4202 fprintf(file, "%*s", (int)nbytes, disasm);
4203 }
4204
4205 out:
4206 ac_rtld_close(&rtld_binary);
4207 }
4208
4209 static void si_calculate_max_simd_waves(struct si_shader *shader)
4210 {
4211 struct si_screen *sscreen = shader->selector->screen;
4212 struct ac_shader_config *conf = &shader->config;
4213 unsigned num_inputs = shader->selector->info.num_inputs;
4214 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
4215 unsigned lds_per_wave = 0;
4216 unsigned max_simd_waves;
4217
4218 max_simd_waves = sscreen->info.max_wave64_per_simd;
4219
4220 /* Compute LDS usage for PS. */
4221 switch (shader->selector->type) {
4222 case PIPE_SHADER_FRAGMENT:
4223 /* The minimum usage per wave is (num_inputs * 48). The maximum
4224 * usage is (num_inputs * 48 * 16).
4225 * We can get anything in between and it varies between waves.
4226 *
4227 * The 48 bytes per input for a single primitive is equal to
4228 * 4 bytes/component * 4 components/input * 3 points.
4229 *
4230 * Other stages don't know the size at compile time or don't
4231 * allocate LDS per wave, but instead they do it per thread group.
4232 */
4233 lds_per_wave = conf->lds_size * lds_increment +
4234 align(num_inputs * 48, lds_increment);
4235 break;
4236 case PIPE_SHADER_COMPUTE:
4237 if (shader->selector) {
4238 unsigned max_workgroup_size =
4239 si_get_max_workgroup_size(shader);
4240 lds_per_wave = (conf->lds_size * lds_increment) /
4241 DIV_ROUND_UP(max_workgroup_size,
4242 sscreen->compute_wave_size);
4243 }
4244 break;
4245 default:;
4246 }
4247
4248 /* Compute the per-SIMD wave counts. */
4249 if (conf->num_sgprs) {
4250 max_simd_waves =
4251 MIN2(max_simd_waves,
4252 sscreen->info.num_physical_sgprs_per_simd / conf->num_sgprs);
4253 }
4254
4255 if (conf->num_vgprs) {
4256 /* Always print wave limits as Wave64, so that we can compare
4257 * Wave32 and Wave64 with shader-db fairly. */
4258 unsigned max_vgprs = sscreen->info.num_physical_wave64_vgprs_per_simd;
4259 max_simd_waves = MIN2(max_simd_waves, max_vgprs / conf->num_vgprs);
4260 }
4261
4262 /* LDS is 64KB per CU (4 SIMDs) on GFX6-9, which is 16KB per SIMD (usage above
4263 * 16KB makes some SIMDs unoccupied).
4264 *
4265 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
4266 */
4267 unsigned max_lds_size = sscreen->info.chip_class >= GFX10 ? 128*1024 : 64*1024;
4268 unsigned max_lds_per_simd = max_lds_size / 4;
4269 if (lds_per_wave)
4270 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
4271
4272 shader->info.max_simd_waves = max_simd_waves;
4273 }
4274
4275 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
4276 struct si_shader *shader,
4277 struct pipe_debug_callback *debug)
4278 {
4279 const struct ac_shader_config *conf = &shader->config;
4280
4281 if (screen->options.debug_disassembly)
4282 si_shader_dump_disassembly(screen, &shader->binary,
4283 shader->selector->type,
4284 si_get_shader_wave_size(shader),
4285 debug, "main", NULL);
4286
4287 pipe_debug_message(debug, SHADER_INFO,
4288 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4289 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
4290 "Spilled VGPRs: %d PrivMem VGPRs: %d",
4291 conf->num_sgprs, conf->num_vgprs,
4292 si_get_shader_binary_size(screen, shader),
4293 conf->lds_size, conf->scratch_bytes_per_wave,
4294 shader->info.max_simd_waves, conf->spilled_sgprs,
4295 conf->spilled_vgprs, shader->info.private_mem_vgprs);
4296 }
4297
4298 static void si_shader_dump_stats(struct si_screen *sscreen,
4299 struct si_shader *shader,
4300 FILE *file,
4301 bool check_debug_option)
4302 {
4303 const struct ac_shader_config *conf = &shader->config;
4304
4305 if (!check_debug_option ||
4306 si_can_dump_shader(sscreen, shader->selector->type)) {
4307 if (shader->selector->type == PIPE_SHADER_FRAGMENT) {
4308 fprintf(file, "*** SHADER CONFIG ***\n"
4309 "SPI_PS_INPUT_ADDR = 0x%04x\n"
4310 "SPI_PS_INPUT_ENA = 0x%04x\n",
4311 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
4312 }
4313
4314 fprintf(file, "*** SHADER STATS ***\n"
4315 "SGPRS: %d\n"
4316 "VGPRS: %d\n"
4317 "Spilled SGPRs: %d\n"
4318 "Spilled VGPRs: %d\n"
4319 "Private memory VGPRs: %d\n"
4320 "Code Size: %d bytes\n"
4321 "LDS: %d blocks\n"
4322 "Scratch: %d bytes per wave\n"
4323 "Max Waves: %d\n"
4324 "********************\n\n\n",
4325 conf->num_sgprs, conf->num_vgprs,
4326 conf->spilled_sgprs, conf->spilled_vgprs,
4327 shader->info.private_mem_vgprs,
4328 si_get_shader_binary_size(sscreen, shader),
4329 conf->lds_size, conf->scratch_bytes_per_wave,
4330 shader->info.max_simd_waves);
4331 }
4332 }
4333
4334 const char *si_get_shader_name(const struct si_shader *shader)
4335 {
4336 switch (shader->selector->type) {
4337 case PIPE_SHADER_VERTEX:
4338 if (shader->key.as_es)
4339 return "Vertex Shader as ES";
4340 else if (shader->key.as_ls)
4341 return "Vertex Shader as LS";
4342 else if (shader->key.opt.vs_as_prim_discard_cs)
4343 return "Vertex Shader as Primitive Discard CS";
4344 else if (shader->key.as_ngg)
4345 return "Vertex Shader as ESGS";
4346 else
4347 return "Vertex Shader as VS";
4348 case PIPE_SHADER_TESS_CTRL:
4349 return "Tessellation Control Shader";
4350 case PIPE_SHADER_TESS_EVAL:
4351 if (shader->key.as_es)
4352 return "Tessellation Evaluation Shader as ES";
4353 else if (shader->key.as_ngg)
4354 return "Tessellation Evaluation Shader as ESGS";
4355 else
4356 return "Tessellation Evaluation Shader as VS";
4357 case PIPE_SHADER_GEOMETRY:
4358 if (shader->is_gs_copy_shader)
4359 return "GS Copy Shader as VS";
4360 else
4361 return "Geometry Shader";
4362 case PIPE_SHADER_FRAGMENT:
4363 return "Pixel Shader";
4364 case PIPE_SHADER_COMPUTE:
4365 return "Compute Shader";
4366 default:
4367 return "Unknown Shader";
4368 }
4369 }
4370
4371 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4372 struct pipe_debug_callback *debug,
4373 FILE *file, bool check_debug_option)
4374 {
4375 enum pipe_shader_type shader_type = shader->selector->type;
4376
4377 if (!check_debug_option ||
4378 si_can_dump_shader(sscreen, shader_type))
4379 si_dump_shader_key(shader, file);
4380
4381 if (!check_debug_option && shader->binary.llvm_ir_string) {
4382 if (shader->previous_stage &&
4383 shader->previous_stage->binary.llvm_ir_string) {
4384 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
4385 si_get_shader_name(shader));
4386 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
4387 }
4388
4389 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
4390 si_get_shader_name(shader));
4391 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
4392 }
4393
4394 if (!check_debug_option ||
4395 (si_can_dump_shader(sscreen, shader_type) &&
4396 !(sscreen->debug_flags & DBG(NO_ASM)))) {
4397 unsigned wave_size = si_get_shader_wave_size(shader);
4398
4399 fprintf(file, "\n%s:\n", si_get_shader_name(shader));
4400
4401 if (shader->prolog)
4402 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
4403 shader_type, wave_size, debug, "prolog", file);
4404 if (shader->previous_stage)
4405 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
4406 shader_type, wave_size, debug, "previous stage", file);
4407 if (shader->prolog2)
4408 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
4409 shader_type, wave_size, debug, "prolog2", file);
4410
4411 si_shader_dump_disassembly(sscreen, &shader->binary, shader_type,
4412 wave_size, debug, "main", file);
4413
4414 if (shader->epilog)
4415 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
4416 shader_type, wave_size, debug, "epilog", file);
4417 fprintf(file, "\n");
4418 }
4419
4420 si_shader_dump_stats(sscreen, shader, file, check_debug_option);
4421 }
4422
4423 static int si_compile_llvm(struct si_screen *sscreen,
4424 struct si_shader_binary *binary,
4425 struct ac_shader_config *conf,
4426 struct ac_llvm_compiler *compiler,
4427 LLVMModuleRef mod,
4428 struct pipe_debug_callback *debug,
4429 enum pipe_shader_type shader_type,
4430 unsigned wave_size,
4431 const char *name,
4432 bool less_optimized)
4433 {
4434 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
4435
4436 if (si_can_dump_shader(sscreen, shader_type)) {
4437 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4438
4439 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
4440 fprintf(stderr, "%s LLVM IR:\n\n", name);
4441 ac_dump_module(mod);
4442 fprintf(stderr, "\n");
4443 }
4444 }
4445
4446 if (sscreen->record_llvm_ir) {
4447 char *ir = LLVMPrintModuleToString(mod);
4448 binary->llvm_ir_string = strdup(ir);
4449 LLVMDisposeMessage(ir);
4450 }
4451
4452 if (!si_replace_shader(count, binary)) {
4453 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
4454 less_optimized, wave_size);
4455 if (r)
4456 return r;
4457 }
4458
4459 struct ac_rtld_binary rtld;
4460 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
4461 .info = &sscreen->info,
4462 .shader_type = tgsi_processor_to_shader_stage(shader_type),
4463 .wave_size = wave_size,
4464 .num_parts = 1,
4465 .elf_ptrs = &binary->elf_buffer,
4466 .elf_sizes = &binary->elf_size }))
4467 return -1;
4468
4469 bool ok = ac_rtld_read_config(&rtld, conf);
4470 ac_rtld_close(&rtld);
4471 if (!ok)
4472 return -1;
4473
4474 /* Enable 64-bit and 16-bit denormals, because there is no performance
4475 * cost.
4476 *
4477 * If denormals are enabled, all floating-point output modifiers are
4478 * ignored.
4479 *
4480 * Don't enable denormals for 32-bit floats, because:
4481 * - Floating-point output modifiers would be ignored by the hw.
4482 * - Some opcodes don't support denormals, such as v_mad_f32. We would
4483 * have to stop using those.
4484 * - GFX6 & GFX7 would be very slow.
4485 */
4486 conf->float_mode |= V_00B028_FP_64_DENORMS;
4487
4488 return 0;
4489 }
4490
4491 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
4492 {
4493 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
4494 LLVMBuildRetVoid(ctx->ac.builder);
4495 else
4496 LLVMBuildRet(ctx->ac.builder, ret);
4497 }
4498
4499 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4500 struct si_shader *
4501 si_generate_gs_copy_shader(struct si_screen *sscreen,
4502 struct ac_llvm_compiler *compiler,
4503 struct si_shader_selector *gs_selector,
4504 struct pipe_debug_callback *debug)
4505 {
4506 struct si_shader_context ctx;
4507 struct si_shader *shader;
4508 LLVMBuilderRef builder;
4509 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
4510 struct si_shader_info *gsinfo = &gs_selector->info;
4511 int i;
4512
4513
4514 shader = CALLOC_STRUCT(si_shader);
4515 if (!shader)
4516 return NULL;
4517
4518 /* We can leave the fence as permanently signaled because the GS copy
4519 * shader only becomes visible globally after it has been compiled. */
4520 util_queue_fence_init(&shader->ready);
4521
4522 shader->selector = gs_selector;
4523 shader->is_gs_copy_shader = true;
4524
4525 si_llvm_context_init(&ctx, sscreen, compiler,
4526 si_get_wave_size(sscreen, PIPE_SHADER_VERTEX, false, false));
4527 ctx.shader = shader;
4528 ctx.type = PIPE_SHADER_VERTEX;
4529
4530 builder = ctx.ac.builder;
4531
4532 create_function(&ctx);
4533 preload_ring_buffers(&ctx);
4534
4535 LLVMValueRef voffset =
4536 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
4537 LLVMConstInt(ctx.i32, 4, 0), "");
4538
4539 /* Fetch the vertex stream ID.*/
4540 LLVMValueRef stream_id;
4541
4542 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs)
4543 stream_id = si_unpack_param(&ctx, ctx.streamout_config, 24, 2);
4544 else
4545 stream_id = ctx.i32_0;
4546
4547 /* Fill in output information. */
4548 for (i = 0; i < gsinfo->num_outputs; ++i) {
4549 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
4550 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
4551
4552 for (int chan = 0; chan < 4; chan++) {
4553 outputs[i].vertex_stream[chan] =
4554 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
4555 }
4556 }
4557
4558 LLVMBasicBlockRef end_bb;
4559 LLVMValueRef switch_inst;
4560
4561 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
4562 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
4563
4564 for (int stream = 0; stream < 4; stream++) {
4565 LLVMBasicBlockRef bb;
4566 unsigned offset;
4567
4568 if (!gsinfo->num_stream_output_components[stream])
4569 continue;
4570
4571 if (stream > 0 && !gs_selector->so.num_outputs)
4572 continue;
4573
4574 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
4575 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
4576 LLVMPositionBuilderAtEnd(builder, bb);
4577
4578 /* Fetch vertex data from GSVS ring */
4579 offset = 0;
4580 for (i = 0; i < gsinfo->num_outputs; ++i) {
4581 for (unsigned chan = 0; chan < 4; chan++) {
4582 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
4583 outputs[i].vertex_stream[chan] != stream) {
4584 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
4585 continue;
4586 }
4587
4588 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
4589 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
4590 offset++;
4591
4592 outputs[i].values[chan] =
4593 ac_build_buffer_load(&ctx.ac,
4594 ctx.gsvs_ring[0], 1,
4595 ctx.i32_0, voffset,
4596 soffset, 0, ac_glc | ac_slc,
4597 true, false);
4598 }
4599 }
4600
4601 /* Streamout and exports. */
4602 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs) {
4603 si_llvm_emit_streamout(&ctx, outputs,
4604 gsinfo->num_outputs,
4605 stream);
4606 }
4607
4608 if (stream == 0)
4609 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
4610
4611 LLVMBuildBr(builder, end_bb);
4612 }
4613
4614 LLVMPositionBuilderAtEnd(builder, end_bb);
4615
4616 LLVMBuildRetVoid(ctx.ac.builder);
4617
4618 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
4619 si_llvm_optimize_module(&ctx);
4620
4621 bool ok = false;
4622 if (si_compile_llvm(sscreen, &ctx.shader->binary,
4623 &ctx.shader->config, ctx.compiler,
4624 ctx.ac.module,
4625 debug, PIPE_SHADER_GEOMETRY, ctx.ac.wave_size,
4626 "GS Copy Shader", false) == 0) {
4627 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
4628 fprintf(stderr, "GS Copy Shader:\n");
4629 si_shader_dump(sscreen, ctx.shader, debug, stderr, true);
4630
4631 if (!ctx.shader->config.scratch_bytes_per_wave)
4632 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
4633 else
4634 ok = true;
4635 }
4636
4637 si_llvm_dispose(&ctx);
4638
4639 if (!ok) {
4640 FREE(shader);
4641 shader = NULL;
4642 } else {
4643 si_fix_resource_usage(sscreen, shader);
4644 }
4645 return shader;
4646 }
4647
4648 static void si_dump_shader_key_vs(const struct si_shader_key *key,
4649 const struct si_vs_prolog_bits *prolog,
4650 const char *prefix, FILE *f)
4651 {
4652 fprintf(f, " %s.instance_divisor_is_one = %u\n",
4653 prefix, prolog->instance_divisor_is_one);
4654 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
4655 prefix, prolog->instance_divisor_is_fetched);
4656 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
4657 prefix, prolog->unpack_instance_id_from_vertex_id);
4658 fprintf(f, " %s.ls_vgpr_fix = %u\n",
4659 prefix, prolog->ls_vgpr_fix);
4660
4661 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
4662 fprintf(f, " mono.vs.fix_fetch = {");
4663 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
4664 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
4665 if (i)
4666 fprintf(f, ", ");
4667 if (!fix.bits)
4668 fprintf(f, "0");
4669 else
4670 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
4671 fix.u.num_channels_m1, fix.u.format);
4672 }
4673 fprintf(f, "}\n");
4674 }
4675
4676 static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
4677 {
4678 const struct si_shader_key *key = &shader->key;
4679 enum pipe_shader_type shader_type = shader->selector->type;
4680
4681 fprintf(f, "SHADER KEY\n");
4682
4683 switch (shader_type) {
4684 case PIPE_SHADER_VERTEX:
4685 si_dump_shader_key_vs(key, &key->part.vs.prolog,
4686 "part.vs.prolog", f);
4687 fprintf(f, " as_es = %u\n", key->as_es);
4688 fprintf(f, " as_ls = %u\n", key->as_ls);
4689 fprintf(f, " as_ngg = %u\n", key->as_ngg);
4690 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
4691 key->mono.u.vs_export_prim_id);
4692 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
4693 key->opt.vs_as_prim_discard_cs);
4694 fprintf(f, " opt.cs_prim_type = %s\n",
4695 tgsi_primitive_names[key->opt.cs_prim_type]);
4696 fprintf(f, " opt.cs_indexed = %u\n",
4697 key->opt.cs_indexed);
4698 fprintf(f, " opt.cs_instancing = %u\n",
4699 key->opt.cs_instancing);
4700 fprintf(f, " opt.cs_primitive_restart = %u\n",
4701 key->opt.cs_primitive_restart);
4702 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
4703 key->opt.cs_provoking_vertex_first);
4704 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
4705 key->opt.cs_need_correct_orientation);
4706 fprintf(f, " opt.cs_cull_front = %u\n",
4707 key->opt.cs_cull_front);
4708 fprintf(f, " opt.cs_cull_back = %u\n",
4709 key->opt.cs_cull_back);
4710 fprintf(f, " opt.cs_cull_z = %u\n",
4711 key->opt.cs_cull_z);
4712 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
4713 key->opt.cs_halfz_clip_space);
4714 break;
4715
4716 case PIPE_SHADER_TESS_CTRL:
4717 if (shader->selector->screen->info.chip_class >= GFX9) {
4718 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
4719 "part.tcs.ls_prolog", f);
4720 }
4721 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
4722 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
4723 break;
4724
4725 case PIPE_SHADER_TESS_EVAL:
4726 fprintf(f, " as_es = %u\n", key->as_es);
4727 fprintf(f, " as_ngg = %u\n", key->as_ngg);
4728 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
4729 key->mono.u.vs_export_prim_id);
4730 break;
4731
4732 case PIPE_SHADER_GEOMETRY:
4733 if (shader->is_gs_copy_shader)
4734 break;
4735
4736 if (shader->selector->screen->info.chip_class >= GFX9 &&
4737 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
4738 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
4739 "part.gs.vs_prolog", f);
4740 }
4741 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
4742 fprintf(f, " part.gs.prolog.gfx9_prev_is_vs = %u\n", key->part.gs.prolog.gfx9_prev_is_vs);
4743 fprintf(f, " as_ngg = %u\n", key->as_ngg);
4744 break;
4745
4746 case PIPE_SHADER_COMPUTE:
4747 break;
4748
4749 case PIPE_SHADER_FRAGMENT:
4750 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
4751 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
4752 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
4753 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
4754 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
4755 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
4756 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
4757 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
4758 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
4759 fprintf(f, " part.ps.prolog.samplemask_log_ps_iter = %u\n", key->part.ps.prolog.samplemask_log_ps_iter);
4760 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
4761 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
4762 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
4763 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
4764 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
4765 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
4766 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
4767 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
4768 fprintf(f, " mono.u.ps.interpolate_at_sample_force_center = %u\n", key->mono.u.ps.interpolate_at_sample_force_center);
4769 fprintf(f, " mono.u.ps.fbfetch_msaa = %u\n", key->mono.u.ps.fbfetch_msaa);
4770 fprintf(f, " mono.u.ps.fbfetch_is_1D = %u\n", key->mono.u.ps.fbfetch_is_1D);
4771 fprintf(f, " mono.u.ps.fbfetch_layered = %u\n", key->mono.u.ps.fbfetch_layered);
4772 break;
4773
4774 default:
4775 assert(0);
4776 }
4777
4778 if ((shader_type == PIPE_SHADER_GEOMETRY ||
4779 shader_type == PIPE_SHADER_TESS_EVAL ||
4780 shader_type == PIPE_SHADER_VERTEX) &&
4781 !key->as_es && !key->as_ls) {
4782 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
4783 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
4784 }
4785 }
4786
4787 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
4788 {
4789 struct si_shader *shader = ctx->shader;
4790 struct si_shader_info *info = &shader->selector->info;
4791
4792 if ((ctx->type != PIPE_SHADER_VERTEX &&
4793 ctx->type != PIPE_SHADER_TESS_EVAL) ||
4794 shader->key.as_ls ||
4795 shader->key.as_es)
4796 return;
4797
4798 ac_optimize_vs_outputs(&ctx->ac,
4799 ctx->main_fn,
4800 shader->info.vs_output_param_offset,
4801 info->num_outputs,
4802 &shader->info.nr_param_exports);
4803 }
4804
4805 static void si_init_exec_from_input(struct si_shader_context *ctx,
4806 struct ac_arg param, unsigned bitoffset)
4807 {
4808 LLVMValueRef args[] = {
4809 ac_get_arg(&ctx->ac, param),
4810 LLVMConstInt(ctx->i32, bitoffset, 0),
4811 };
4812 ac_build_intrinsic(&ctx->ac,
4813 "llvm.amdgcn.init.exec.from.input",
4814 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
4815 }
4816
4817 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
4818 const struct si_vs_prolog_bits *key)
4819 {
4820 /* VGPR initialization fixup for Vega10 and Raven is always done in the
4821 * VS prolog. */
4822 return sel->vs_needs_prolog ||
4823 key->ls_vgpr_fix ||
4824 key->unpack_instance_id_from_vertex_id;
4825 }
4826
4827 LLVMValueRef si_is_es_thread(struct si_shader_context *ctx)
4828 {
4829 /* Return true if the current thread should execute an ES thread. */
4830 return LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
4831 ac_get_thread_id(&ctx->ac),
4832 si_unpack_param(ctx, ctx->merged_wave_info, 0, 8), "");
4833 }
4834
4835 LLVMValueRef si_is_gs_thread(struct si_shader_context *ctx)
4836 {
4837 /* Return true if the current thread should execute a GS thread. */
4838 return LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
4839 ac_get_thread_id(&ctx->ac),
4840 si_unpack_param(ctx, ctx->merged_wave_info, 8, 8), "");
4841 }
4842
4843 static void si_llvm_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
4844 {
4845 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4846 LLVMBuilderRef builder = ctx->ac.builder;
4847
4848 if (ctx->shader->selector->force_correct_derivs_after_kill) {
4849 /* Kill immediately while maintaining WQM. */
4850 ac_build_kill_if_false(&ctx->ac,
4851 ac_build_wqm_vote(&ctx->ac, visible));
4852
4853 LLVMValueRef mask = LLVMBuildLoad(builder, ctx->postponed_kill, "");
4854 mask = LLVMBuildAnd(builder, mask, visible, "");
4855 LLVMBuildStore(builder, mask, ctx->postponed_kill);
4856 return;
4857 }
4858
4859 ac_build_kill_if_false(&ctx->ac, visible);
4860 }
4861
4862 static bool si_build_main_function(struct si_shader_context *ctx,
4863 struct nir_shader *nir, bool free_nir)
4864 {
4865 struct si_shader *shader = ctx->shader;
4866 struct si_shader_selector *sel = shader->selector;
4867
4868 // TODO clean all this up!
4869 switch (ctx->type) {
4870 case PIPE_SHADER_VERTEX:
4871 if (shader->key.as_ls)
4872 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
4873 else if (shader->key.as_es)
4874 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
4875 else if (shader->key.opt.vs_as_prim_discard_cs)
4876 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
4877 else if (shader->key.as_ngg)
4878 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
4879 else
4880 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
4881 ctx->abi.load_base_vertex = get_base_vertex;
4882 break;
4883 case PIPE_SHADER_TESS_CTRL:
4884 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
4885 ctx->abi.load_tess_level = si_load_tess_level;
4886 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
4887 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
4888 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
4889 break;
4890 case PIPE_SHADER_TESS_EVAL:
4891 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
4892 ctx->abi.load_tess_coord = si_load_tess_coord;
4893 ctx->abi.load_tess_level = si_load_tess_level;
4894 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
4895 if (shader->key.as_es)
4896 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
4897 else if (shader->key.as_ngg)
4898 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
4899 else
4900 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
4901 break;
4902 case PIPE_SHADER_GEOMETRY:
4903 ctx->abi.load_inputs = si_nir_load_input_gs;
4904 ctx->abi.emit_vertex = si_llvm_emit_vertex;
4905 ctx->abi.emit_primitive = si_llvm_emit_primitive;
4906 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
4907 break;
4908 case PIPE_SHADER_FRAGMENT:
4909 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
4910 ctx->abi.load_sample_position = load_sample_position;
4911 ctx->abi.load_sample_mask_in = load_sample_mask_in;
4912 ctx->abi.emit_fbfetch = si_nir_emit_fbfetch;
4913 ctx->abi.emit_kill = si_llvm_emit_kill;
4914 break;
4915 case PIPE_SHADER_COMPUTE:
4916 ctx->abi.load_local_group_size = get_block_size;
4917 break;
4918 default:
4919 assert(!"Unsupported shader type");
4920 return false;
4921 }
4922
4923 ctx->abi.load_ubo = load_ubo;
4924 ctx->abi.load_ssbo = load_ssbo;
4925
4926 create_function(ctx);
4927 preload_ring_buffers(ctx);
4928
4929 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
4930 sel->info.tessfactors_are_def_in_all_invocs) {
4931 for (unsigned i = 0; i < 6; i++) {
4932 ctx->invoc0_tess_factors[i] =
4933 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
4934 }
4935 }
4936
4937 if (ctx->type == PIPE_SHADER_GEOMETRY) {
4938 for (unsigned i = 0; i < 4; i++) {
4939 ctx->gs_next_vertex[i] =
4940 ac_build_alloca(&ctx->ac, ctx->i32, "");
4941 }
4942 if (shader->key.as_ngg) {
4943 for (unsigned i = 0; i < 4; ++i) {
4944 ctx->gs_curprim_verts[i] =
4945 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
4946 ctx->gs_generated_prims[i] =
4947 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
4948 }
4949
4950 unsigned scratch_size = 8;
4951 if (sel->so.num_outputs)
4952 scratch_size = 44;
4953
4954 LLVMTypeRef ai32 = LLVMArrayType(ctx->i32, scratch_size);
4955 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
4956 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4957 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(ai32));
4958 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
4959
4960 ctx->gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx->ac.module,
4961 LLVMArrayType(ctx->i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4962 LLVMSetLinkage(ctx->gs_ngg_emit, LLVMExternalLinkage);
4963 LLVMSetAlignment(ctx->gs_ngg_emit, 4);
4964 }
4965 }
4966
4967 if (ctx->type != PIPE_SHADER_GEOMETRY &&
4968 (shader->key.as_ngg && !shader->key.as_es)) {
4969 /* Unconditionally declare scratch space base for streamout and
4970 * vertex compaction. Whether space is actually allocated is
4971 * determined during linking / PM4 creation.
4972 *
4973 * Add an extra dword per vertex to ensure an odd stride, which
4974 * avoids bank conflicts for SoA accesses.
4975 */
4976 if (!gfx10_is_ngg_passthrough(shader))
4977 declare_esgs_ring(ctx);
4978
4979 /* This is really only needed when streamout and / or vertex
4980 * compaction is enabled.
4981 */
4982 if (sel->so.num_outputs && !ctx->gs_ngg_scratch) {
4983 LLVMTypeRef asi32 = LLVMArrayType(ctx->i32, 8);
4984 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
4985 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4986 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(asi32));
4987 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
4988 }
4989 }
4990
4991 /* For GFX9 merged shaders:
4992 * - Set EXEC for the first shader. If the prolog is present, set
4993 * EXEC there instead.
4994 * - Add a barrier before the second shader.
4995 * - In the second shader, reset EXEC to ~0 and wrap the main part in
4996 * an if-statement. This is required for correctness in geometry
4997 * shaders, to ensure that empty GS waves do not send GS_EMIT and
4998 * GS_CUT messages.
4999 *
5000 * For monolithic merged shaders, the first shader is wrapped in an
5001 * if-block together with its prolog in si_build_wrapper_function.
5002 *
5003 * NGG vertex and tess eval shaders running as the last
5004 * vertex/geometry stage handle execution explicitly using
5005 * if-statements.
5006 */
5007 if (ctx->screen->info.chip_class >= GFX9) {
5008 if (!shader->is_monolithic &&
5009 (shader->key.as_es || shader->key.as_ls) &&
5010 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5011 (ctx->type == PIPE_SHADER_VERTEX &&
5012 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5013 si_init_exec_from_input(ctx,
5014 ctx->merged_wave_info, 0);
5015 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5016 ctx->type == PIPE_SHADER_GEOMETRY ||
5017 (shader->key.as_ngg && !shader->key.as_es)) {
5018 LLVMValueRef thread_enabled;
5019 bool nested_barrier;
5020
5021 if (!shader->is_monolithic ||
5022 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5023 (shader->key.as_ngg && !shader->key.as_es)))
5024 ac_init_exec_full_mask(&ctx->ac);
5025
5026 if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5027 ctx->type == PIPE_SHADER_GEOMETRY) {
5028 if (ctx->type == PIPE_SHADER_GEOMETRY && shader->key.as_ngg) {
5029 gfx10_ngg_gs_emit_prologue(ctx);
5030 nested_barrier = false;
5031 } else {
5032 nested_barrier = true;
5033 }
5034
5035 thread_enabled = si_is_gs_thread(ctx);
5036 } else {
5037 thread_enabled = si_is_es_thread(ctx);
5038 nested_barrier = false;
5039 }
5040
5041 ctx->merged_wrap_if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
5042 ctx->merged_wrap_if_label = 11500;
5043 ac_build_ifcc(&ctx->ac, thread_enabled, ctx->merged_wrap_if_label);
5044
5045 if (nested_barrier) {
5046 /* Execute a barrier before the second shader in
5047 * a merged shader.
5048 *
5049 * Execute the barrier inside the conditional block,
5050 * so that empty waves can jump directly to s_endpgm,
5051 * which will also signal the barrier.
5052 *
5053 * This is possible in gfx9, because an empty wave
5054 * for the second shader does not participate in
5055 * the epilogue. With NGG, empty waves may still
5056 * be required to export data (e.g. GS output vertices),
5057 * so we cannot let them exit early.
5058 *
5059 * If the shader is TCS and the TCS epilog is present
5060 * and contains a barrier, it will wait there and then
5061 * reach s_endpgm.
5062 */
5063 si_llvm_emit_barrier(ctx);
5064 }
5065 }
5066 }
5067
5068 if (sel->force_correct_derivs_after_kill) {
5069 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
5070 /* true = don't kill. */
5071 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
5072 ctx->postponed_kill);
5073 }
5074
5075 bool success = si_nir_build_llvm(ctx, nir);
5076 if (free_nir)
5077 ralloc_free(nir);
5078 if (!success) {
5079 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5080 return false;
5081 }
5082
5083 si_llvm_build_ret(ctx, ctx->return_value);
5084 return true;
5085 }
5086
5087 /**
5088 * Compute the VS prolog key, which contains all the information needed to
5089 * build the VS prolog function, and set shader->info bits where needed.
5090 *
5091 * \param info Shader info of the vertex shader.
5092 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5093 * \param prolog_key Key of the VS prolog
5094 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5095 * \param key Output shader part key.
5096 */
5097 static void si_get_vs_prolog_key(const struct si_shader_info *info,
5098 unsigned num_input_sgprs,
5099 const struct si_vs_prolog_bits *prolog_key,
5100 struct si_shader *shader_out,
5101 union si_shader_part_key *key)
5102 {
5103 memset(key, 0, sizeof(*key));
5104 key->vs_prolog.states = *prolog_key;
5105 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5106 key->vs_prolog.num_inputs = info->num_inputs;
5107 key->vs_prolog.as_ls = shader_out->key.as_ls;
5108 key->vs_prolog.as_es = shader_out->key.as_es;
5109 key->vs_prolog.as_ngg = shader_out->key.as_ngg;
5110
5111 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5112 key->vs_prolog.as_ls = 1;
5113 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5114 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5115 key->vs_prolog.as_es = 1;
5116 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5117 } else if (shader_out->key.as_ngg) {
5118 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5119 }
5120
5121 /* Enable loading the InstanceID VGPR. */
5122 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5123
5124 if ((key->vs_prolog.states.instance_divisor_is_one |
5125 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5126 shader_out->info.uses_instanceid = true;
5127 }
5128
5129 /**
5130 * Compute the PS prolog key, which contains all the information needed to
5131 * build the PS prolog function, and set related bits in shader->config.
5132 */
5133 static void si_get_ps_prolog_key(struct si_shader *shader,
5134 union si_shader_part_key *key,
5135 bool separate_prolog)
5136 {
5137 struct si_shader_info *info = &shader->selector->info;
5138
5139 memset(key, 0, sizeof(*key));
5140 key->ps_prolog.states = shader->key.part.ps.prolog;
5141 key->ps_prolog.colors_read = info->colors_read;
5142 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5143 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5144 key->ps_prolog.wqm = info->uses_derivatives &&
5145 (key->ps_prolog.colors_read ||
5146 key->ps_prolog.states.force_persp_sample_interp ||
5147 key->ps_prolog.states.force_linear_sample_interp ||
5148 key->ps_prolog.states.force_persp_center_interp ||
5149 key->ps_prolog.states.force_linear_center_interp ||
5150 key->ps_prolog.states.bc_optimize_for_persp ||
5151 key->ps_prolog.states.bc_optimize_for_linear);
5152 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5153
5154 if (info->colors_read) {
5155 unsigned *color = shader->selector->color_attr_index;
5156
5157 if (shader->key.part.ps.prolog.color_two_side) {
5158 /* BCOLORs are stored after the last input. */
5159 key->ps_prolog.num_interp_inputs = info->num_inputs;
5160 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5161 if (separate_prolog)
5162 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5163 }
5164
5165 for (unsigned i = 0; i < 2; i++) {
5166 unsigned interp = info->input_interpolate[color[i]];
5167 unsigned location = info->input_interpolate_loc[color[i]];
5168
5169 if (!(info->colors_read & (0xf << i*4)))
5170 continue;
5171
5172 key->ps_prolog.color_attr_index[i] = color[i];
5173
5174 if (shader->key.part.ps.prolog.flatshade_colors &&
5175 interp == TGSI_INTERPOLATE_COLOR)
5176 interp = TGSI_INTERPOLATE_CONSTANT;
5177
5178 switch (interp) {
5179 case TGSI_INTERPOLATE_CONSTANT:
5180 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5181 break;
5182 case TGSI_INTERPOLATE_PERSPECTIVE:
5183 case TGSI_INTERPOLATE_COLOR:
5184 /* Force the interpolation location for colors here. */
5185 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5186 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5187 if (shader->key.part.ps.prolog.force_persp_center_interp)
5188 location = TGSI_INTERPOLATE_LOC_CENTER;
5189
5190 switch (location) {
5191 case TGSI_INTERPOLATE_LOC_SAMPLE:
5192 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5193 if (separate_prolog) {
5194 shader->config.spi_ps_input_ena |=
5195 S_0286CC_PERSP_SAMPLE_ENA(1);
5196 }
5197 break;
5198 case TGSI_INTERPOLATE_LOC_CENTER:
5199 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5200 if (separate_prolog) {
5201 shader->config.spi_ps_input_ena |=
5202 S_0286CC_PERSP_CENTER_ENA(1);
5203 }
5204 break;
5205 case TGSI_INTERPOLATE_LOC_CENTROID:
5206 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5207 if (separate_prolog) {
5208 shader->config.spi_ps_input_ena |=
5209 S_0286CC_PERSP_CENTROID_ENA(1);
5210 }
5211 break;
5212 default:
5213 assert(0);
5214 }
5215 break;
5216 case TGSI_INTERPOLATE_LINEAR:
5217 /* Force the interpolation location for colors here. */
5218 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5219 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5220 if (shader->key.part.ps.prolog.force_linear_center_interp)
5221 location = TGSI_INTERPOLATE_LOC_CENTER;
5222
5223 /* The VGPR assignment for non-monolithic shaders
5224 * works because InitialPSInputAddr is set on the
5225 * main shader and PERSP_PULL_MODEL is never used.
5226 */
5227 switch (location) {
5228 case TGSI_INTERPOLATE_LOC_SAMPLE:
5229 key->ps_prolog.color_interp_vgpr_index[i] =
5230 separate_prolog ? 6 : 9;
5231 if (separate_prolog) {
5232 shader->config.spi_ps_input_ena |=
5233 S_0286CC_LINEAR_SAMPLE_ENA(1);
5234 }
5235 break;
5236 case TGSI_INTERPOLATE_LOC_CENTER:
5237 key->ps_prolog.color_interp_vgpr_index[i] =
5238 separate_prolog ? 8 : 11;
5239 if (separate_prolog) {
5240 shader->config.spi_ps_input_ena |=
5241 S_0286CC_LINEAR_CENTER_ENA(1);
5242 }
5243 break;
5244 case TGSI_INTERPOLATE_LOC_CENTROID:
5245 key->ps_prolog.color_interp_vgpr_index[i] =
5246 separate_prolog ? 10 : 13;
5247 if (separate_prolog) {
5248 shader->config.spi_ps_input_ena |=
5249 S_0286CC_LINEAR_CENTROID_ENA(1);
5250 }
5251 break;
5252 default:
5253 assert(0);
5254 }
5255 break;
5256 default:
5257 assert(0);
5258 }
5259 }
5260 }
5261 }
5262
5263 /**
5264 * Check whether a PS prolog is required based on the key.
5265 */
5266 static bool si_need_ps_prolog(const union si_shader_part_key *key)
5267 {
5268 return key->ps_prolog.colors_read ||
5269 key->ps_prolog.states.force_persp_sample_interp ||
5270 key->ps_prolog.states.force_linear_sample_interp ||
5271 key->ps_prolog.states.force_persp_center_interp ||
5272 key->ps_prolog.states.force_linear_center_interp ||
5273 key->ps_prolog.states.bc_optimize_for_persp ||
5274 key->ps_prolog.states.bc_optimize_for_linear ||
5275 key->ps_prolog.states.poly_stipple ||
5276 key->ps_prolog.states.samplemask_log_ps_iter;
5277 }
5278
5279 /**
5280 * Compute the PS epilog key, which contains all the information needed to
5281 * build the PS epilog function.
5282 */
5283 static void si_get_ps_epilog_key(struct si_shader *shader,
5284 union si_shader_part_key *key)
5285 {
5286 struct si_shader_info *info = &shader->selector->info;
5287 memset(key, 0, sizeof(*key));
5288 key->ps_epilog.colors_written = info->colors_written;
5289 key->ps_epilog.writes_z = info->writes_z;
5290 key->ps_epilog.writes_stencil = info->writes_stencil;
5291 key->ps_epilog.writes_samplemask = info->writes_samplemask;
5292 key->ps_epilog.states = shader->key.part.ps.epilog;
5293 }
5294
5295 /**
5296 * Build the GS prolog function. Rotate the input vertices for triangle strips
5297 * with adjacency.
5298 */
5299 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
5300 union si_shader_part_key *key)
5301 {
5302 unsigned num_sgprs, num_vgprs;
5303 LLVMBuilderRef builder = ctx->ac.builder;
5304 LLVMTypeRef returns[AC_MAX_ARGS];
5305 LLVMValueRef func, ret;
5306
5307 memset(&ctx->args, 0, sizeof(ctx->args));
5308
5309 if (ctx->screen->info.chip_class >= GFX9) {
5310 if (key->gs_prolog.states.gfx9_prev_is_vs)
5311 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
5312 else
5313 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
5314 num_vgprs = 5; /* ES inputs are not needed by GS */
5315 } else {
5316 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
5317 num_vgprs = 8;
5318 }
5319
5320 for (unsigned i = 0; i < num_sgprs; ++i) {
5321 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
5322 returns[i] = ctx->i32;
5323 }
5324
5325 for (unsigned i = 0; i < num_vgprs; ++i) {
5326 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL);
5327 returns[num_sgprs + i] = ctx->f32;
5328 }
5329
5330 /* Create the function. */
5331 si_llvm_create_func(ctx, "gs_prolog", returns, num_sgprs + num_vgprs, 0);
5332 func = ctx->main_fn;
5333
5334 /* Set the full EXEC mask for the prolog, because we are only fiddling
5335 * with registers here. The main shader part will set the correct EXEC
5336 * mask.
5337 */
5338 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
5339 ac_init_exec_full_mask(&ctx->ac);
5340
5341 /* Copy inputs to outputs. This should be no-op, as the registers match,
5342 * but it will prevent the compiler from overwriting them unintentionally.
5343 */
5344 ret = ctx->return_value;
5345 for (unsigned i = 0; i < num_sgprs; i++) {
5346 LLVMValueRef p = LLVMGetParam(func, i);
5347 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
5348 }
5349 for (unsigned i = 0; i < num_vgprs; i++) {
5350 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
5351 p = ac_to_float(&ctx->ac, p);
5352 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
5353 }
5354
5355 if (key->gs_prolog.states.tri_strip_adj_fix) {
5356 /* Remap the input vertices for every other primitive. */
5357 const struct ac_arg gfx6_vtx_params[6] = {
5358 { .used = true, .arg_index = num_sgprs },
5359 { .used = true, .arg_index = num_sgprs + 1 },
5360 { .used = true, .arg_index = num_sgprs + 3 },
5361 { .used = true, .arg_index = num_sgprs + 4 },
5362 { .used = true, .arg_index = num_sgprs + 5 },
5363 { .used = true, .arg_index = num_sgprs + 6 },
5364 };
5365 const struct ac_arg gfx9_vtx_params[3] = {
5366 { .used = true, .arg_index = num_sgprs },
5367 { .used = true, .arg_index = num_sgprs + 1 },
5368 { .used = true, .arg_index = num_sgprs + 4 },
5369 };
5370 LLVMValueRef vtx_in[6], vtx_out[6];
5371 LLVMValueRef prim_id, rotate;
5372
5373 if (ctx->screen->info.chip_class >= GFX9) {
5374 for (unsigned i = 0; i < 3; i++) {
5375 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
5376 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
5377 }
5378 } else {
5379 for (unsigned i = 0; i < 6; i++)
5380 vtx_in[i] = ac_get_arg(&ctx->ac, gfx6_vtx_params[i]);
5381 }
5382
5383 prim_id = LLVMGetParam(func, num_sgprs + 2);
5384 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
5385
5386 for (unsigned i = 0; i < 6; ++i) {
5387 LLVMValueRef base, rotated;
5388 base = vtx_in[i];
5389 rotated = vtx_in[(i + 4) % 6];
5390 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
5391 }
5392
5393 if (ctx->screen->info.chip_class >= GFX9) {
5394 for (unsigned i = 0; i < 3; i++) {
5395 LLVMValueRef hi, out;
5396
5397 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
5398 LLVMConstInt(ctx->i32, 16, 0), "");
5399 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
5400 out = ac_to_float(&ctx->ac, out);
5401 ret = LLVMBuildInsertValue(builder, ret, out,
5402 gfx9_vtx_params[i].arg_index, "");
5403 }
5404 } else {
5405 for (unsigned i = 0; i < 6; i++) {
5406 LLVMValueRef out;
5407
5408 out = ac_to_float(&ctx->ac, vtx_out[i]);
5409 ret = LLVMBuildInsertValue(builder, ret, out,
5410 gfx6_vtx_params[i].arg_index, "");
5411 }
5412 }
5413 }
5414
5415 LLVMBuildRet(builder, ret);
5416 }
5417
5418 /**
5419 * Given a list of shader part functions, build a wrapper function that
5420 * runs them in sequence to form a monolithic shader.
5421 */
5422 static void si_build_wrapper_function(struct si_shader_context *ctx,
5423 LLVMValueRef *parts,
5424 unsigned num_parts,
5425 unsigned main_part,
5426 unsigned next_shader_first_part)
5427 {
5428 LLVMBuilderRef builder = ctx->ac.builder;
5429 /* PS epilog has one arg per color component; gfx9 merged shader
5430 * prologs need to forward 40 SGPRs.
5431 */
5432 LLVMValueRef initial[AC_MAX_ARGS], out[AC_MAX_ARGS];
5433 LLVMTypeRef function_type;
5434 unsigned num_first_params;
5435 unsigned num_out, initial_num_out;
5436 ASSERTED unsigned num_out_sgpr; /* used in debug checks */
5437 ASSERTED unsigned initial_num_out_sgpr; /* used in debug checks */
5438 unsigned num_sgprs, num_vgprs;
5439 unsigned gprs;
5440
5441 memset(&ctx->args, 0, sizeof(ctx->args));
5442
5443 for (unsigned i = 0; i < num_parts; ++i) {
5444 ac_add_function_attr(ctx->ac.context, parts[i], -1,
5445 AC_FUNC_ATTR_ALWAYSINLINE);
5446 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
5447 }
5448
5449 /* The parameters of the wrapper function correspond to those of the
5450 * first part in terms of SGPRs and VGPRs, but we use the types of the
5451 * main part to get the right types. This is relevant for the
5452 * dereferenceable attribute on descriptor table pointers.
5453 */
5454 num_sgprs = 0;
5455 num_vgprs = 0;
5456
5457 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
5458 num_first_params = LLVMCountParamTypes(function_type);
5459
5460 for (unsigned i = 0; i < num_first_params; ++i) {
5461 LLVMValueRef param = LLVMGetParam(parts[0], i);
5462
5463 if (ac_is_sgpr_param(param)) {
5464 assert(num_vgprs == 0);
5465 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
5466 } else {
5467 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
5468 }
5469 }
5470
5471 gprs = 0;
5472 while (gprs < num_sgprs + num_vgprs) {
5473 LLVMValueRef param = LLVMGetParam(parts[main_part], ctx->args.arg_count);
5474 LLVMTypeRef type = LLVMTypeOf(param);
5475 unsigned size = ac_get_type_size(type) / 4;
5476
5477 /* This is going to get casted anyways, so we don't have to
5478 * have the exact same type. But we do have to preserve the
5479 * pointer-ness so that LLVM knows about it.
5480 */
5481 enum ac_arg_type arg_type = AC_ARG_INT;
5482 if (LLVMGetTypeKind(type) == LLVMPointerTypeKind) {
5483 arg_type = AC_ARG_CONST_PTR;
5484 }
5485
5486 ac_add_arg(&ctx->args, gprs < num_sgprs ? AC_ARG_SGPR : AC_ARG_VGPR,
5487 size, arg_type, NULL);
5488
5489 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
5490 assert(gprs + size <= num_sgprs + num_vgprs &&
5491 (gprs >= num_sgprs || gprs + size <= num_sgprs));
5492
5493 gprs += size;
5494 }
5495
5496 /* Prepare the return type. */
5497 unsigned num_returns = 0;
5498 LLVMTypeRef returns[AC_MAX_ARGS], last_func_type, return_type;
5499
5500 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
5501 return_type = LLVMGetReturnType(last_func_type);
5502
5503 switch (LLVMGetTypeKind(return_type)) {
5504 case LLVMStructTypeKind:
5505 num_returns = LLVMCountStructElementTypes(return_type);
5506 assert(num_returns <= ARRAY_SIZE(returns));
5507 LLVMGetStructElementTypes(return_type, returns);
5508 break;
5509 case LLVMVoidTypeKind:
5510 break;
5511 default:
5512 unreachable("unexpected type");
5513 }
5514
5515 si_llvm_create_func(ctx, "wrapper", returns, num_returns,
5516 si_get_max_workgroup_size(ctx->shader));
5517
5518 if (is_merged_shader(ctx))
5519 ac_init_exec_full_mask(&ctx->ac);
5520
5521 /* Record the arguments of the function as if they were an output of
5522 * a previous part.
5523 */
5524 num_out = 0;
5525 num_out_sgpr = 0;
5526
5527 for (unsigned i = 0; i < ctx->args.arg_count; ++i) {
5528 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
5529 LLVMTypeRef param_type = LLVMTypeOf(param);
5530 LLVMTypeRef out_type = ctx->args.args[i].file == AC_ARG_SGPR ? ctx->i32 : ctx->f32;
5531 unsigned size = ac_get_type_size(param_type) / 4;
5532
5533 if (size == 1) {
5534 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
5535 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
5536 param_type = ctx->i32;
5537 }
5538
5539 if (param_type != out_type)
5540 param = LLVMBuildBitCast(builder, param, out_type, "");
5541 out[num_out++] = param;
5542 } else {
5543 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
5544
5545 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
5546 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
5547 param_type = ctx->i64;
5548 }
5549
5550 if (param_type != vector_type)
5551 param = LLVMBuildBitCast(builder, param, vector_type, "");
5552
5553 for (unsigned j = 0; j < size; ++j)
5554 out[num_out++] = LLVMBuildExtractElement(
5555 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
5556 }
5557
5558 if (ctx->args.args[i].file == AC_ARG_SGPR)
5559 num_out_sgpr = num_out;
5560 }
5561
5562 memcpy(initial, out, sizeof(out));
5563 initial_num_out = num_out;
5564 initial_num_out_sgpr = num_out_sgpr;
5565
5566 /* Now chain the parts. */
5567 LLVMValueRef ret = NULL;
5568 for (unsigned part = 0; part < num_parts; ++part) {
5569 LLVMValueRef in[AC_MAX_ARGS];
5570 LLVMTypeRef ret_type;
5571 unsigned out_idx = 0;
5572 unsigned num_params = LLVMCountParams(parts[part]);
5573
5574 /* Merged shaders are executed conditionally depending
5575 * on the number of enabled threads passed in the input SGPRs. */
5576 if (is_multi_part_shader(ctx) && part == 0) {
5577 LLVMValueRef ena, count = initial[3];
5578
5579 count = LLVMBuildAnd(builder, count,
5580 LLVMConstInt(ctx->i32, 0x7f, 0), "");
5581 ena = LLVMBuildICmp(builder, LLVMIntULT,
5582 ac_get_thread_id(&ctx->ac), count, "");
5583 ac_build_ifcc(&ctx->ac, ena, 6506);
5584 }
5585
5586 /* Derive arguments for the next part from outputs of the
5587 * previous one.
5588 */
5589 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
5590 LLVMValueRef param;
5591 LLVMTypeRef param_type;
5592 bool is_sgpr;
5593 unsigned param_size;
5594 LLVMValueRef arg = NULL;
5595
5596 param = LLVMGetParam(parts[part], param_idx);
5597 param_type = LLVMTypeOf(param);
5598 param_size = ac_get_type_size(param_type) / 4;
5599 is_sgpr = ac_is_sgpr_param(param);
5600
5601 if (is_sgpr) {
5602 ac_add_function_attr(ctx->ac.context, parts[part],
5603 param_idx + 1, AC_FUNC_ATTR_INREG);
5604 } else if (out_idx < num_out_sgpr) {
5605 /* Skip returned SGPRs the current part doesn't
5606 * declare on the input. */
5607 out_idx = num_out_sgpr;
5608 }
5609
5610 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
5611
5612 if (param_size == 1)
5613 arg = out[out_idx];
5614 else
5615 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
5616
5617 if (LLVMTypeOf(arg) != param_type) {
5618 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
5619 if (LLVMGetPointerAddressSpace(param_type) ==
5620 AC_ADDR_SPACE_CONST_32BIT) {
5621 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
5622 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
5623 } else {
5624 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
5625 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
5626 }
5627 } else {
5628 arg = LLVMBuildBitCast(builder, arg, param_type, "");
5629 }
5630 }
5631
5632 in[param_idx] = arg;
5633 out_idx += param_size;
5634 }
5635
5636 ret = ac_build_call(&ctx->ac, parts[part], in, num_params);
5637
5638 if (is_multi_part_shader(ctx) &&
5639 part + 1 == next_shader_first_part) {
5640 ac_build_endif(&ctx->ac, 6506);
5641
5642 /* The second half of the merged shader should use
5643 * the inputs from the toplevel (wrapper) function,
5644 * not the return value from the last call.
5645 *
5646 * That's because the last call was executed condi-
5647 * tionally, so we can't consume it in the main
5648 * block.
5649 */
5650 memcpy(out, initial, sizeof(initial));
5651 num_out = initial_num_out;
5652 num_out_sgpr = initial_num_out_sgpr;
5653 continue;
5654 }
5655
5656 /* Extract the returned GPRs. */
5657 ret_type = LLVMTypeOf(ret);
5658 num_out = 0;
5659 num_out_sgpr = 0;
5660
5661 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
5662 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
5663
5664 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
5665
5666 for (unsigned i = 0; i < ret_size; ++i) {
5667 LLVMValueRef val =
5668 LLVMBuildExtractValue(builder, ret, i, "");
5669
5670 assert(num_out < ARRAY_SIZE(out));
5671 out[num_out++] = val;
5672
5673 if (LLVMTypeOf(val) == ctx->i32) {
5674 assert(num_out_sgpr + 1 == num_out);
5675 num_out_sgpr = num_out;
5676 }
5677 }
5678 }
5679 }
5680
5681 /* Return the value from the last part. */
5682 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5683 LLVMBuildRetVoid(builder);
5684 else
5685 LLVMBuildRet(builder, ret);
5686 }
5687
5688 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
5689 struct si_shader_selector *sel)
5690 {
5691 if (!compiler->low_opt_passes)
5692 return false;
5693
5694 /* Assume a slow CPU. */
5695 assert(!sel->screen->info.has_dedicated_vram &&
5696 sel->screen->info.chip_class <= GFX8);
5697
5698 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
5699 * buffer stores. */
5700 return sel->type == PIPE_SHADER_COMPUTE &&
5701 sel->info.num_memory_instructions > 1000;
5702 }
5703
5704 static struct nir_shader *get_nir_shader(struct si_shader_selector *sel,
5705 bool *free_nir)
5706 {
5707 *free_nir = false;
5708
5709 if (sel->nir) {
5710 return sel->nir;
5711 } else if (sel->nir_binary) {
5712 struct pipe_screen *screen = &sel->screen->b;
5713 const void *options =
5714 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR,
5715 sel->type);
5716
5717 struct blob_reader blob_reader;
5718 blob_reader_init(&blob_reader, sel->nir_binary, sel->nir_size);
5719 *free_nir = true;
5720 return nir_deserialize(NULL, options, &blob_reader);
5721 }
5722 return NULL;
5723 }
5724
5725 int si_compile_shader(struct si_screen *sscreen,
5726 struct ac_llvm_compiler *compiler,
5727 struct si_shader *shader,
5728 struct pipe_debug_callback *debug)
5729 {
5730 struct si_shader_selector *sel = shader->selector;
5731 struct si_shader_context ctx;
5732 bool free_nir;
5733 struct nir_shader *nir = get_nir_shader(sel, &free_nir);
5734 int r = -1;
5735
5736 /* Dump NIR before doing NIR->LLVM conversion in case the
5737 * conversion fails. */
5738 if (si_can_dump_shader(sscreen, sel->type) &&
5739 !(sscreen->debug_flags & DBG(NO_NIR))) {
5740 nir_print_shader(nir, stderr);
5741 si_dump_streamout(&sel->so);
5742 }
5743
5744 si_llvm_context_init(&ctx, sscreen, compiler, si_get_shader_wave_size(shader));
5745 si_llvm_context_set_ir(&ctx, shader);
5746
5747 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5748 sizeof(shader->info.vs_output_param_offset));
5749
5750 shader->info.uses_instanceid = sel->info.uses_instanceid;
5751
5752 if (!si_build_main_function(&ctx, nir, free_nir)) {
5753 si_llvm_dispose(&ctx);
5754 return -1;
5755 }
5756
5757 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
5758 LLVMValueRef parts[2];
5759 bool need_prolog = si_vs_needs_prolog(sel, &shader->key.part.vs.prolog);
5760
5761 parts[1] = ctx.main_fn;
5762
5763 if (need_prolog) {
5764 union si_shader_part_key prolog_key;
5765 si_get_vs_prolog_key(&sel->info,
5766 shader->info.num_input_sgprs,
5767 &shader->key.part.vs.prolog,
5768 shader, &prolog_key);
5769 prolog_key.vs_prolog.is_monolithic = true;
5770 si_build_vs_prolog_function(&ctx, &prolog_key);
5771 parts[0] = ctx.main_fn;
5772 }
5773
5774 si_build_wrapper_function(&ctx, parts + !need_prolog,
5775 1 + need_prolog, need_prolog, 0);
5776
5777 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
5778 si_build_prim_discard_compute_shader(&ctx);
5779 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
5780 if (sscreen->info.chip_class >= GFX9) {
5781 struct si_shader_selector *ls = shader->key.part.tcs.ls;
5782 LLVMValueRef parts[4];
5783 bool vs_needs_prolog =
5784 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
5785
5786 /* TCS main part */
5787 parts[2] = ctx.main_fn;
5788
5789 /* TCS epilog */
5790 union si_shader_part_key tcs_epilog_key;
5791 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
5792 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
5793 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
5794 parts[3] = ctx.main_fn;
5795
5796 /* VS as LS main part */
5797 nir = get_nir_shader(ls, &free_nir);
5798 struct si_shader shader_ls = {};
5799 shader_ls.selector = ls;
5800 shader_ls.key.as_ls = 1;
5801 shader_ls.key.mono = shader->key.mono;
5802 shader_ls.key.opt = shader->key.opt;
5803 shader_ls.is_monolithic = true;
5804 si_llvm_context_set_ir(&ctx, &shader_ls);
5805
5806 if (!si_build_main_function(&ctx, nir, free_nir)) {
5807 si_llvm_dispose(&ctx);
5808 return -1;
5809 }
5810 shader->info.uses_instanceid |= ls->info.uses_instanceid;
5811 parts[1] = ctx.main_fn;
5812
5813 /* LS prolog */
5814 if (vs_needs_prolog) {
5815 union si_shader_part_key vs_prolog_key;
5816 si_get_vs_prolog_key(&ls->info,
5817 shader_ls.info.num_input_sgprs,
5818 &shader->key.part.tcs.ls_prolog,
5819 shader, &vs_prolog_key);
5820 vs_prolog_key.vs_prolog.is_monolithic = true;
5821 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
5822 parts[0] = ctx.main_fn;
5823 }
5824
5825 /* Reset the shader context. */
5826 ctx.shader = shader;
5827 ctx.type = PIPE_SHADER_TESS_CTRL;
5828
5829 si_build_wrapper_function(&ctx,
5830 parts + !vs_needs_prolog,
5831 4 - !vs_needs_prolog, vs_needs_prolog,
5832 vs_needs_prolog ? 2 : 1);
5833 } else {
5834 LLVMValueRef parts[2];
5835 union si_shader_part_key epilog_key;
5836
5837 parts[0] = ctx.main_fn;
5838
5839 memset(&epilog_key, 0, sizeof(epilog_key));
5840 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
5841 si_build_tcs_epilog_function(&ctx, &epilog_key);
5842 parts[1] = ctx.main_fn;
5843
5844 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
5845 }
5846 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
5847 if (ctx.screen->info.chip_class >= GFX9) {
5848 struct si_shader_selector *es = shader->key.part.gs.es;
5849 LLVMValueRef es_prolog = NULL;
5850 LLVMValueRef es_main = NULL;
5851 LLVMValueRef gs_prolog = NULL;
5852 LLVMValueRef gs_main = ctx.main_fn;
5853
5854 /* GS prolog */
5855 union si_shader_part_key gs_prolog_key;
5856 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
5857 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
5858 gs_prolog_key.gs_prolog.is_monolithic = true;
5859 gs_prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
5860 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
5861 gs_prolog = ctx.main_fn;
5862
5863 /* ES main part */
5864 nir = get_nir_shader(es, &free_nir);
5865 struct si_shader shader_es = {};
5866 shader_es.selector = es;
5867 shader_es.key.as_es = 1;
5868 shader_es.key.as_ngg = shader->key.as_ngg;
5869 shader_es.key.mono = shader->key.mono;
5870 shader_es.key.opt = shader->key.opt;
5871 shader_es.is_monolithic = true;
5872 si_llvm_context_set_ir(&ctx, &shader_es);
5873
5874 if (!si_build_main_function(&ctx, nir, free_nir)) {
5875 si_llvm_dispose(&ctx);
5876 return -1;
5877 }
5878 shader->info.uses_instanceid |= es->info.uses_instanceid;
5879 es_main = ctx.main_fn;
5880
5881 /* ES prolog */
5882 if (es->type == PIPE_SHADER_VERTEX &&
5883 si_vs_needs_prolog(es, &shader->key.part.gs.vs_prolog)) {
5884 union si_shader_part_key vs_prolog_key;
5885 si_get_vs_prolog_key(&es->info,
5886 shader_es.info.num_input_sgprs,
5887 &shader->key.part.gs.vs_prolog,
5888 shader, &vs_prolog_key);
5889 vs_prolog_key.vs_prolog.is_monolithic = true;
5890 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
5891 es_prolog = ctx.main_fn;
5892 }
5893
5894 /* Reset the shader context. */
5895 ctx.shader = shader;
5896 ctx.type = PIPE_SHADER_GEOMETRY;
5897
5898 /* Prepare the array of shader parts. */
5899 LLVMValueRef parts[4];
5900 unsigned num_parts = 0, main_part, next_first_part;
5901
5902 if (es_prolog)
5903 parts[num_parts++] = es_prolog;
5904
5905 parts[main_part = num_parts++] = es_main;
5906 parts[next_first_part = num_parts++] = gs_prolog;
5907 parts[num_parts++] = gs_main;
5908
5909 si_build_wrapper_function(&ctx, parts, num_parts,
5910 main_part, next_first_part);
5911 } else {
5912 LLVMValueRef parts[2];
5913 union si_shader_part_key prolog_key;
5914
5915 parts[1] = ctx.main_fn;
5916
5917 memset(&prolog_key, 0, sizeof(prolog_key));
5918 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
5919 si_build_gs_prolog_function(&ctx, &prolog_key);
5920 parts[0] = ctx.main_fn;
5921
5922 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
5923 }
5924 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
5925 LLVMValueRef parts[3];
5926 union si_shader_part_key prolog_key;
5927 union si_shader_part_key epilog_key;
5928 bool need_prolog;
5929
5930 si_get_ps_prolog_key(shader, &prolog_key, false);
5931 need_prolog = si_need_ps_prolog(&prolog_key);
5932
5933 parts[need_prolog ? 1 : 0] = ctx.main_fn;
5934
5935 if (need_prolog) {
5936 si_build_ps_prolog_function(&ctx, &prolog_key);
5937 parts[0] = ctx.main_fn;
5938 }
5939
5940 si_get_ps_epilog_key(shader, &epilog_key);
5941 si_build_ps_epilog_function(&ctx, &epilog_key);
5942 parts[need_prolog ? 2 : 1] = ctx.main_fn;
5943
5944 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
5945 need_prolog ? 1 : 0, 0);
5946 }
5947
5948 si_llvm_optimize_module(&ctx);
5949
5950 /* Post-optimization transformations and analysis. */
5951 si_optimize_vs_outputs(&ctx);
5952
5953 if ((debug && debug->debug_message) ||
5954 si_can_dump_shader(sscreen, ctx.type)) {
5955 ctx.shader->info.private_mem_vgprs =
5956 ac_count_scratch_private_memory(ctx.main_fn);
5957 }
5958
5959 /* Make sure the input is a pointer and not integer followed by inttoptr. */
5960 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
5961 LLVMPointerTypeKind);
5962
5963 /* Compile to bytecode. */
5964 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
5965 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
5966 si_get_shader_name(shader),
5967 si_should_optimize_less(compiler, shader->selector));
5968 si_llvm_dispose(&ctx);
5969 if (r) {
5970 fprintf(stderr, "LLVM failed to compile shader\n");
5971 return r;
5972 }
5973
5974 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
5975 * LLVM 3.9svn has this bug.
5976 */
5977 if (sel->type == PIPE_SHADER_COMPUTE) {
5978 unsigned wave_size = sscreen->compute_wave_size;
5979 unsigned max_vgprs = sscreen->info.num_physical_wave64_vgprs_per_simd *
5980 (wave_size == 32 ? 2 : 1);
5981 unsigned max_sgprs = sscreen->info.num_physical_sgprs_per_simd;
5982 unsigned max_sgprs_per_wave = 128;
5983 unsigned simds_per_tg = 4; /* assuming WGP mode on gfx10 */
5984 unsigned threads_per_tg = si_get_max_workgroup_size(shader);
5985 unsigned waves_per_tg = DIV_ROUND_UP(threads_per_tg, wave_size);
5986 unsigned waves_per_simd = DIV_ROUND_UP(waves_per_tg, simds_per_tg);
5987
5988 max_vgprs = max_vgprs / waves_per_simd;
5989 max_sgprs = MIN2(max_sgprs / waves_per_simd, max_sgprs_per_wave);
5990
5991 if (shader->config.num_sgprs > max_sgprs ||
5992 shader->config.num_vgprs > max_vgprs) {
5993 fprintf(stderr, "LLVM failed to compile a shader correctly: "
5994 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
5995 shader->config.num_sgprs, shader->config.num_vgprs,
5996 max_sgprs, max_vgprs);
5997
5998 /* Just terminate the process, because dependent
5999 * shaders can hang due to bad input data, but use
6000 * the env var to allow shader-db to work.
6001 */
6002 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6003 abort();
6004 }
6005 }
6006
6007 /* Add the scratch offset to input SGPRs. */
6008 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
6009 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6010
6011 /* Calculate the number of fragment input VGPRs. */
6012 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6013 shader->info.num_input_vgprs = ac_get_fs_input_vgpr_cnt(&shader->config,
6014 &shader->info.face_vgpr_index,
6015 &shader->info.ancillary_vgpr_index);
6016 }
6017
6018 si_calculate_max_simd_waves(shader);
6019 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
6020 return 0;
6021 }
6022
6023 /**
6024 * Create, compile and return a shader part (prolog or epilog).
6025 *
6026 * \param sscreen screen
6027 * \param list list of shader parts of the same category
6028 * \param type shader type
6029 * \param key shader part key
6030 * \param prolog whether the part being requested is a prolog
6031 * \param tm LLVM target machine
6032 * \param debug debug callback
6033 * \param build the callback responsible for building the main function
6034 * \return non-NULL on success
6035 */
6036 static struct si_shader_part *
6037 si_get_shader_part(struct si_screen *sscreen,
6038 struct si_shader_part **list,
6039 enum pipe_shader_type type,
6040 bool prolog,
6041 union si_shader_part_key *key,
6042 struct ac_llvm_compiler *compiler,
6043 struct pipe_debug_callback *debug,
6044 void (*build)(struct si_shader_context *,
6045 union si_shader_part_key *),
6046 const char *name)
6047 {
6048 struct si_shader_part *result;
6049
6050 simple_mtx_lock(&sscreen->shader_parts_mutex);
6051
6052 /* Find existing. */
6053 for (result = *list; result; result = result->next) {
6054 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6055 simple_mtx_unlock(&sscreen->shader_parts_mutex);
6056 return result;
6057 }
6058 }
6059
6060 /* Compile a new one. */
6061 result = CALLOC_STRUCT(si_shader_part);
6062 result->key = *key;
6063
6064 struct si_shader shader = {};
6065
6066 switch (type) {
6067 case PIPE_SHADER_VERTEX:
6068 shader.key.as_ls = key->vs_prolog.as_ls;
6069 shader.key.as_es = key->vs_prolog.as_es;
6070 shader.key.as_ngg = key->vs_prolog.as_ngg;
6071 break;
6072 case PIPE_SHADER_TESS_CTRL:
6073 assert(!prolog);
6074 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6075 break;
6076 case PIPE_SHADER_GEOMETRY:
6077 assert(prolog);
6078 shader.key.as_ngg = key->gs_prolog.as_ngg;
6079 break;
6080 case PIPE_SHADER_FRAGMENT:
6081 if (prolog)
6082 shader.key.part.ps.prolog = key->ps_prolog.states;
6083 else
6084 shader.key.part.ps.epilog = key->ps_epilog.states;
6085 break;
6086 default:
6087 unreachable("bad shader part");
6088 }
6089
6090 struct si_shader_context ctx;
6091 si_llvm_context_init(&ctx, sscreen, compiler,
6092 si_get_wave_size(sscreen, type, shader.key.as_ngg,
6093 shader.key.as_es));
6094 ctx.shader = &shader;
6095 ctx.type = type;
6096
6097 build(&ctx, key);
6098
6099 /* Compile. */
6100 si_llvm_optimize_module(&ctx);
6101
6102 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
6103 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
6104 name, false)) {
6105 FREE(result);
6106 result = NULL;
6107 goto out;
6108 }
6109
6110 result->next = *list;
6111 *list = result;
6112
6113 out:
6114 si_llvm_dispose(&ctx);
6115 simple_mtx_unlock(&sscreen->shader_parts_mutex);
6116 return result;
6117 }
6118
6119 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6120 {
6121 LLVMValueRef ptr[2], list;
6122 bool merged_shader = is_merged_shader(ctx);
6123
6124 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6125 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
6126 ac_array_in_const32_addr_space(ctx->v4i32), "");
6127 return list;
6128 }
6129
6130 /**
6131 * Build the vertex shader prolog function.
6132 *
6133 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6134 * All inputs are returned unmodified. The vertex load indices are
6135 * stored after them, which will be used by the API VS for fetching inputs.
6136 *
6137 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6138 * input_v0,
6139 * input_v1,
6140 * input_v2,
6141 * input_v3,
6142 * (VertexID + BaseVertex),
6143 * (InstanceID + StartInstance),
6144 * (InstanceID / 2 + StartInstance)
6145 */
6146 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6147 union si_shader_part_key *key)
6148 {
6149 LLVMTypeRef *returns;
6150 LLVMValueRef ret, func;
6151 int num_returns, i;
6152 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6153 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6154 struct ac_arg input_sgpr_param[key->vs_prolog.num_input_sgprs];
6155 struct ac_arg input_vgpr_param[9];
6156 LLVMValueRef input_vgprs[9];
6157 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6158 num_input_vgprs;
6159 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6160
6161 memset(&ctx->args, 0, sizeof(ctx->args));
6162
6163 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6164 returns = alloca((num_all_input_regs + key->vs_prolog.num_inputs) *
6165 sizeof(LLVMTypeRef));
6166 num_returns = 0;
6167
6168 /* Declare input and output SGPRs. */
6169 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6170 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6171 &input_sgpr_param[i]);
6172 returns[num_returns++] = ctx->i32;
6173 }
6174
6175 struct ac_arg merged_wave_info = input_sgpr_param[3];
6176
6177 /* Preloaded VGPRs (outputs must be floats) */
6178 for (i = 0; i < num_input_vgprs; i++) {
6179 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &input_vgpr_param[i]);
6180 returns[num_returns++] = ctx->f32;
6181 }
6182
6183 /* Vertex load indices. */
6184 for (i = 0; i < key->vs_prolog.num_inputs; i++)
6185 returns[num_returns++] = ctx->f32;
6186
6187 /* Create the function. */
6188 si_llvm_create_func(ctx, "vs_prolog", returns, num_returns, 0);
6189 func = ctx->main_fn;
6190
6191 for (i = 0; i < num_input_vgprs; i++) {
6192 input_vgprs[i] = ac_get_arg(&ctx->ac, input_vgpr_param[i]);
6193 }
6194
6195 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6196 if (!key->vs_prolog.is_monolithic)
6197 si_init_exec_from_input(ctx, merged_wave_info, 0);
6198
6199 if (key->vs_prolog.as_ls &&
6200 ctx->screen->info.has_ls_vgpr_init_bug) {
6201 /* If there are no HS threads, SPI loads the LS VGPRs
6202 * starting at VGPR 0. Shift them back to where they
6203 * belong.
6204 */
6205 LLVMValueRef has_hs_threads =
6206 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6207 si_unpack_param(ctx, input_sgpr_param[3], 8, 8),
6208 ctx->i32_0, "");
6209
6210 for (i = 4; i > 0; --i) {
6211 input_vgprs[i + 1] =
6212 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6213 input_vgprs[i + 1],
6214 input_vgprs[i - 1], "");
6215 }
6216 }
6217 }
6218
6219 unsigned vertex_id_vgpr = first_vs_vgpr;
6220 unsigned instance_id_vgpr =
6221 ctx->screen->info.chip_class >= GFX10 ?
6222 first_vs_vgpr + 3 :
6223 first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
6224
6225 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
6226 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
6227
6228 /* InstanceID = VertexID >> 16;
6229 * VertexID = VertexID & 0xffff;
6230 */
6231 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
6232 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
6233 LLVMConstInt(ctx->i32, 16, 0), "");
6234 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
6235 LLVMConstInt(ctx->i32, 0xffff, 0), "");
6236 }
6237
6238 /* Copy inputs to outputs. This should be no-op, as the registers match,
6239 * but it will prevent the compiler from overwriting them unintentionally.
6240 */
6241 ret = ctx->return_value;
6242 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6243 LLVMValueRef p = LLVMGetParam(func, i);
6244 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6245 }
6246 for (i = 0; i < num_input_vgprs; i++) {
6247 LLVMValueRef p = input_vgprs[i];
6248
6249 if (i == vertex_id_vgpr)
6250 p = ctx->abi.vertex_id;
6251 else if (i == instance_id_vgpr)
6252 p = ctx->abi.instance_id;
6253
6254 p = ac_to_float(&ctx->ac, p);
6255 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6256 key->vs_prolog.num_input_sgprs + i, "");
6257 }
6258
6259 /* Compute vertex load indices from instance divisors. */
6260 LLVMValueRef instance_divisor_constbuf = NULL;
6261
6262 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6263 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6264 LLVMValueRef buf_index =
6265 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6266 instance_divisor_constbuf =
6267 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6268 }
6269
6270 for (i = 0; i < key->vs_prolog.num_inputs; i++) {
6271 bool divisor_is_one =
6272 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6273 bool divisor_is_fetched =
6274 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6275 LLVMValueRef index = NULL;
6276
6277 if (divisor_is_one) {
6278 index = ctx->abi.instance_id;
6279 } else if (divisor_is_fetched) {
6280 LLVMValueRef udiv_factors[4];
6281
6282 for (unsigned j = 0; j < 4; j++) {
6283 udiv_factors[j] =
6284 buffer_load_const(ctx, instance_divisor_constbuf,
6285 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
6286 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
6287 }
6288 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
6289 * Such InstanceID might not be achievable in a reasonable time though.
6290 */
6291 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
6292 udiv_factors[0], udiv_factors[1],
6293 udiv_factors[2], udiv_factors[3]);
6294 }
6295
6296 if (divisor_is_one || divisor_is_fetched) {
6297 /* Add StartInstance. */
6298 index = LLVMBuildAdd(ctx->ac.builder, index,
6299 LLVMGetParam(ctx->main_fn, user_sgpr_base +
6300 SI_SGPR_START_INSTANCE), "");
6301 } else {
6302 /* VertexID + BaseVertex */
6303 index = LLVMBuildAdd(ctx->ac.builder,
6304 ctx->abi.vertex_id,
6305 LLVMGetParam(func, user_sgpr_base +
6306 SI_SGPR_BASE_VERTEX), "");
6307 }
6308
6309 index = ac_to_float(&ctx->ac, index);
6310 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6311 ctx->args.arg_count + i, "");
6312 }
6313
6314 si_llvm_build_ret(ctx, ret);
6315 }
6316
6317 static bool si_get_vs_prolog(struct si_screen *sscreen,
6318 struct ac_llvm_compiler *compiler,
6319 struct si_shader *shader,
6320 struct pipe_debug_callback *debug,
6321 struct si_shader *main_part,
6322 const struct si_vs_prolog_bits *key)
6323 {
6324 struct si_shader_selector *vs = main_part->selector;
6325
6326 if (!si_vs_needs_prolog(vs, key))
6327 return true;
6328
6329 /* Get the prolog. */
6330 union si_shader_part_key prolog_key;
6331 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6332 key, shader, &prolog_key);
6333
6334 shader->prolog =
6335 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6336 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
6337 debug, si_build_vs_prolog_function,
6338 "Vertex Shader Prolog");
6339 return shader->prolog != NULL;
6340 }
6341
6342 /**
6343 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6344 */
6345 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6346 struct ac_llvm_compiler *compiler,
6347 struct si_shader *shader,
6348 struct pipe_debug_callback *debug)
6349 {
6350 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
6351 &shader->key.part.vs.prolog);
6352 }
6353
6354 /**
6355 * Compile the TCS epilog function. This writes tesselation factors to memory
6356 * based on the output primitive type of the tesselator (determined by TES).
6357 */
6358 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
6359 union si_shader_part_key *key)
6360 {
6361 memset(&ctx->args, 0, sizeof(ctx->args));
6362
6363 if (ctx->screen->info.chip_class >= GFX9) {
6364 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6365 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6366 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6367 &ctx->tcs_offchip_offset);
6368 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* wave info */
6369 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6370 &ctx->tcs_factor_offset);
6371 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6372 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6373 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6374 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6375 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6376 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6377 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6378 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6379 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6380 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6381 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6382 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6383 &ctx->tcs_offchip_layout);
6384 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6385 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6386 &ctx->tcs_out_lds_layout);
6387 } else {
6388 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6389 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6390 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6391 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6392 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6393 &ctx->tcs_offchip_layout);
6394 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6395 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6396 &ctx->tcs_out_lds_layout);
6397 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6398 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6399 &ctx->tcs_offchip_offset);
6400 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6401 &ctx->tcs_factor_offset);
6402 }
6403
6404 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* VGPR gap */
6405 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* VGPR gap */
6406 struct ac_arg rel_patch_id; /* patch index within the wave (REL_PATCH_ID) */
6407 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &rel_patch_id);
6408 struct ac_arg invocation_id; /* invocation ID within the patch */
6409 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &invocation_id);
6410 struct ac_arg tcs_out_current_patch_data_offset; /* LDS offset where tess factors should be loaded from */
6411 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT,
6412 &tcs_out_current_patch_data_offset);
6413
6414 struct ac_arg tess_factors[6];
6415 for (unsigned i = 0; i < 6; i++)
6416 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &tess_factors[i]);
6417
6418 /* Create the function. */
6419 si_llvm_create_func(ctx, "tcs_epilog", NULL, 0,
6420 ctx->screen->info.chip_class >= GFX7 ? 128 : 0);
6421 ac_declare_lds_as_pointer(&ctx->ac);
6422
6423 LLVMValueRef invoc0_tess_factors[6];
6424 for (unsigned i = 0; i < 6; i++)
6425 invoc0_tess_factors[i] = ac_get_arg(&ctx->ac, tess_factors[i]);
6426
6427 si_write_tess_factors(ctx,
6428 ac_get_arg(&ctx->ac, rel_patch_id),
6429 ac_get_arg(&ctx->ac, invocation_id),
6430 ac_get_arg(&ctx->ac, tcs_out_current_patch_data_offset),
6431 invoc0_tess_factors, invoc0_tess_factors + 4);
6432
6433 LLVMBuildRetVoid(ctx->ac.builder);
6434 }
6435
6436 /**
6437 * Select and compile (or reuse) TCS parts (epilog).
6438 */
6439 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6440 struct ac_llvm_compiler *compiler,
6441 struct si_shader *shader,
6442 struct pipe_debug_callback *debug)
6443 {
6444 if (sscreen->info.chip_class >= GFX9) {
6445 struct si_shader *ls_main_part =
6446 shader->key.part.tcs.ls->main_shader_part_ls;
6447
6448 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
6449 &shader->key.part.tcs.ls_prolog))
6450 return false;
6451
6452 shader->previous_stage = ls_main_part;
6453 }
6454
6455 /* Get the epilog. */
6456 union si_shader_part_key epilog_key;
6457 memset(&epilog_key, 0, sizeof(epilog_key));
6458 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6459
6460 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6461 PIPE_SHADER_TESS_CTRL, false,
6462 &epilog_key, compiler, debug,
6463 si_build_tcs_epilog_function,
6464 "Tessellation Control Shader Epilog");
6465 return shader->epilog != NULL;
6466 }
6467
6468 /**
6469 * Select and compile (or reuse) GS parts (prolog).
6470 */
6471 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
6472 struct ac_llvm_compiler *compiler,
6473 struct si_shader *shader,
6474 struct pipe_debug_callback *debug)
6475 {
6476 if (sscreen->info.chip_class >= GFX9) {
6477 struct si_shader *es_main_part;
6478 enum pipe_shader_type es_type = shader->key.part.gs.es->type;
6479
6480 if (shader->key.as_ngg)
6481 es_main_part = shader->key.part.gs.es->main_shader_part_ngg_es;
6482 else
6483 es_main_part = shader->key.part.gs.es->main_shader_part_es;
6484
6485 if (es_type == PIPE_SHADER_VERTEX &&
6486 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
6487 &shader->key.part.gs.vs_prolog))
6488 return false;
6489
6490 shader->previous_stage = es_main_part;
6491 }
6492
6493 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
6494 return true;
6495
6496 union si_shader_part_key prolog_key;
6497 memset(&prolog_key, 0, sizeof(prolog_key));
6498 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6499 prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
6500
6501 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
6502 PIPE_SHADER_GEOMETRY, true,
6503 &prolog_key, compiler, debug,
6504 si_build_gs_prolog_function,
6505 "Geometry Shader Prolog");
6506 return shader->prolog2 != NULL;
6507 }
6508
6509 /**
6510 * Build the pixel shader prolog function. This handles:
6511 * - two-side color selection and interpolation
6512 * - overriding interpolation parameters for the API PS
6513 * - polygon stippling
6514 *
6515 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6516 * overriden by other states. (e.g. per-sample interpolation)
6517 * Interpolated colors are stored after the preloaded VGPRs.
6518 */
6519 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
6520 union si_shader_part_key *key)
6521 {
6522 LLVMValueRef ret, func;
6523 int num_returns, i, num_color_channels;
6524
6525 assert(si_need_ps_prolog(key));
6526
6527 memset(&ctx->args, 0, sizeof(ctx->args));
6528
6529 /* Declare inputs. */
6530 LLVMTypeRef return_types[AC_MAX_ARGS];
6531 num_returns = 0;
6532 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6533 assert(key->ps_prolog.num_input_sgprs +
6534 key->ps_prolog.num_input_vgprs +
6535 num_color_channels <= AC_MAX_ARGS);
6536 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++) {
6537 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
6538 return_types[num_returns++] = ctx->i32;
6539
6540 }
6541
6542 struct ac_arg pos_fixed_pt;
6543 struct ac_arg ancillary;
6544 struct ac_arg param_sample_mask;
6545 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++) {
6546 struct ac_arg *arg = NULL;
6547 if (i == key->ps_prolog.ancillary_vgpr_index) {
6548 arg = &ancillary;
6549 } else if (i == key->ps_prolog.ancillary_vgpr_index + 1) {
6550 arg = &param_sample_mask;
6551 } else if (i == key->ps_prolog.num_input_vgprs - 1) {
6552 /* POS_FIXED_PT is always last. */
6553 arg = &pos_fixed_pt;
6554 }
6555 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT, arg);
6556 return_types[num_returns++] = ctx->f32;
6557 }
6558
6559 /* Declare outputs (same as inputs + add colors if needed) */
6560 for (i = 0; i < num_color_channels; i++)
6561 return_types[num_returns++] = ctx->f32;
6562
6563 /* Create the function. */
6564 si_llvm_create_func(ctx, "ps_prolog", return_types, num_returns, 0);
6565 func = ctx->main_fn;
6566
6567 /* Copy inputs to outputs. This should be no-op, as the registers match,
6568 * but it will prevent the compiler from overwriting them unintentionally.
6569 */
6570 ret = ctx->return_value;
6571 for (i = 0; i < ctx->args.arg_count; i++) {
6572 LLVMValueRef p = LLVMGetParam(func, i);
6573 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6574 }
6575
6576 /* Polygon stippling. */
6577 if (key->ps_prolog.states.poly_stipple) {
6578 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6579
6580 si_llvm_emit_polygon_stipple(ctx, list, pos_fixed_pt);
6581 }
6582
6583 if (key->ps_prolog.states.bc_optimize_for_persp ||
6584 key->ps_prolog.states.bc_optimize_for_linear) {
6585 unsigned i, base = key->ps_prolog.num_input_sgprs;
6586 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
6587
6588 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
6589 * The hw doesn't compute CENTROID if the whole wave only
6590 * contains fully-covered quads.
6591 *
6592 * PRIM_MASK is after user SGPRs.
6593 */
6594 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6595 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
6596 LLVMConstInt(ctx->i32, 31, 0), "");
6597 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
6598 ctx->i1, "");
6599
6600 if (key->ps_prolog.states.bc_optimize_for_persp) {
6601 /* Read PERSP_CENTER. */
6602 for (i = 0; i < 2; i++)
6603 center[i] = LLVMGetParam(func, base + 2 + i);
6604 /* Read PERSP_CENTROID. */
6605 for (i = 0; i < 2; i++)
6606 centroid[i] = LLVMGetParam(func, base + 4 + i);
6607 /* Select PERSP_CENTROID. */
6608 for (i = 0; i < 2; i++) {
6609 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
6610 center[i], centroid[i], "");
6611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6612 tmp, base + 4 + i, "");
6613 }
6614 }
6615 if (key->ps_prolog.states.bc_optimize_for_linear) {
6616 /* Read LINEAR_CENTER. */
6617 for (i = 0; i < 2; i++)
6618 center[i] = LLVMGetParam(func, base + 8 + i);
6619 /* Read LINEAR_CENTROID. */
6620 for (i = 0; i < 2; i++)
6621 centroid[i] = LLVMGetParam(func, base + 10 + i);
6622 /* Select LINEAR_CENTROID. */
6623 for (i = 0; i < 2; i++) {
6624 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
6625 center[i], centroid[i], "");
6626 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6627 tmp, base + 10 + i, "");
6628 }
6629 }
6630 }
6631
6632 /* Force per-sample interpolation. */
6633 if (key->ps_prolog.states.force_persp_sample_interp) {
6634 unsigned i, base = key->ps_prolog.num_input_sgprs;
6635 LLVMValueRef persp_sample[2];
6636
6637 /* Read PERSP_SAMPLE. */
6638 for (i = 0; i < 2; i++)
6639 persp_sample[i] = LLVMGetParam(func, base + i);
6640 /* Overwrite PERSP_CENTER. */
6641 for (i = 0; i < 2; i++)
6642 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6643 persp_sample[i], base + 2 + i, "");
6644 /* Overwrite PERSP_CENTROID. */
6645 for (i = 0; i < 2; i++)
6646 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6647 persp_sample[i], base + 4 + i, "");
6648 }
6649 if (key->ps_prolog.states.force_linear_sample_interp) {
6650 unsigned i, base = key->ps_prolog.num_input_sgprs;
6651 LLVMValueRef linear_sample[2];
6652
6653 /* Read LINEAR_SAMPLE. */
6654 for (i = 0; i < 2; i++)
6655 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6656 /* Overwrite LINEAR_CENTER. */
6657 for (i = 0; i < 2; i++)
6658 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6659 linear_sample[i], base + 8 + i, "");
6660 /* Overwrite LINEAR_CENTROID. */
6661 for (i = 0; i < 2; i++)
6662 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6663 linear_sample[i], base + 10 + i, "");
6664 }
6665
6666 /* Force center interpolation. */
6667 if (key->ps_prolog.states.force_persp_center_interp) {
6668 unsigned i, base = key->ps_prolog.num_input_sgprs;
6669 LLVMValueRef persp_center[2];
6670
6671 /* Read PERSP_CENTER. */
6672 for (i = 0; i < 2; i++)
6673 persp_center[i] = LLVMGetParam(func, base + 2 + i);
6674 /* Overwrite PERSP_SAMPLE. */
6675 for (i = 0; i < 2; i++)
6676 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6677 persp_center[i], base + i, "");
6678 /* Overwrite PERSP_CENTROID. */
6679 for (i = 0; i < 2; i++)
6680 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6681 persp_center[i], base + 4 + i, "");
6682 }
6683 if (key->ps_prolog.states.force_linear_center_interp) {
6684 unsigned i, base = key->ps_prolog.num_input_sgprs;
6685 LLVMValueRef linear_center[2];
6686
6687 /* Read LINEAR_CENTER. */
6688 for (i = 0; i < 2; i++)
6689 linear_center[i] = LLVMGetParam(func, base + 8 + i);
6690 /* Overwrite LINEAR_SAMPLE. */
6691 for (i = 0; i < 2; i++)
6692 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6693 linear_center[i], base + 6 + i, "");
6694 /* Overwrite LINEAR_CENTROID. */
6695 for (i = 0; i < 2; i++)
6696 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
6697 linear_center[i], base + 10 + i, "");
6698 }
6699
6700 /* Interpolate colors. */
6701 unsigned color_out_idx = 0;
6702 for (i = 0; i < 2; i++) {
6703 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6704 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6705 key->ps_prolog.face_vgpr_index;
6706 LLVMValueRef interp[2], color[4];
6707 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6708
6709 if (!writemask)
6710 continue;
6711
6712 /* If the interpolation qualifier is not CONSTANT (-1). */
6713 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6714 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6715 key->ps_prolog.color_interp_vgpr_index[i];
6716
6717 /* Get the (i,j) updated by bc_optimize handling. */
6718 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
6719 interp_vgpr, "");
6720 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
6721 interp_vgpr + 1, "");
6722 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
6723 }
6724
6725 /* Use the absolute location of the input. */
6726 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6727
6728 if (key->ps_prolog.states.color_two_side) {
6729 face = LLVMGetParam(func, face_vgpr);
6730 face = ac_to_integer(&ctx->ac, face);
6731 }
6732
6733 interp_fs_color(ctx,
6734 key->ps_prolog.color_attr_index[i], i,
6735 key->ps_prolog.num_interp_inputs,
6736 key->ps_prolog.colors_read, interp_ij,
6737 prim_mask, face, color);
6738
6739 while (writemask) {
6740 unsigned chan = u_bit_scan(&writemask);
6741 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
6742 ctx->args.arg_count + color_out_idx++, "");
6743 }
6744 }
6745
6746 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
6747 * says:
6748 *
6749 * "When per-sample shading is active due to the use of a fragment
6750 * input qualified by sample or due to the use of the gl_SampleID
6751 * or gl_SamplePosition variables, only the bit for the current
6752 * sample is set in gl_SampleMaskIn. When state specifies multiple
6753 * fragment shader invocations for a given fragment, the sample
6754 * mask for any single fragment shader invocation may specify a
6755 * subset of the covered samples for the fragment. In this case,
6756 * the bit corresponding to each covered sample will be set in
6757 * exactly one fragment shader invocation."
6758 *
6759 * The samplemask loaded by hardware is always the coverage of the
6760 * entire pixel/fragment, so mask bits out based on the sample ID.
6761 */
6762 if (key->ps_prolog.states.samplemask_log_ps_iter) {
6763 /* The bit pattern matches that used by fixed function fragment
6764 * processing. */
6765 static const uint16_t ps_iter_masks[] = {
6766 0xffff, /* not used */
6767 0x5555,
6768 0x1111,
6769 0x0101,
6770 0x0001,
6771 };
6772 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
6773
6774 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
6775 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary, 8, 4);
6776 LLVMValueRef samplemask = ac_get_arg(&ctx->ac, param_sample_mask);
6777
6778 samplemask = ac_to_integer(&ctx->ac, samplemask);
6779 samplemask = LLVMBuildAnd(
6780 ctx->ac.builder,
6781 samplemask,
6782 LLVMBuildShl(ctx->ac.builder,
6783 LLVMConstInt(ctx->i32, ps_iter_mask, false),
6784 sampleid, ""),
6785 "");
6786 samplemask = ac_to_float(&ctx->ac, samplemask);
6787
6788 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
6789 param_sample_mask.arg_index, "");
6790 }
6791
6792 /* Tell LLVM to insert WQM instruction sequence when needed. */
6793 if (key->ps_prolog.wqm) {
6794 LLVMAddTargetDependentFunctionAttr(func,
6795 "amdgpu-ps-wqm-outputs", "");
6796 }
6797
6798 si_llvm_build_ret(ctx, ret);
6799 }
6800
6801 /**
6802 * Build the pixel shader epilog function. This handles everything that must be
6803 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6804 */
6805 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
6806 union si_shader_part_key *key)
6807 {
6808 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6809 int i;
6810 struct si_ps_exports exp = {};
6811
6812 memset(&ctx->args, 0, sizeof(ctx->args));
6813
6814 /* Declare input SGPRs. */
6815 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->rw_buffers);
6816 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6817 &ctx->bindless_samplers_and_images);
6818 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6819 &ctx->const_and_shader_buffers);
6820 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT,
6821 &ctx->samplers_and_images);
6822 add_arg_checked(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT,
6823 NULL, SI_PARAM_ALPHA_REF);
6824
6825 /* Declare input VGPRs. */
6826 unsigned required_num_params =
6827 ctx->args.num_sgprs_used +
6828 util_bitcount(key->ps_epilog.colors_written) * 4 +
6829 key->ps_epilog.writes_z +
6830 key->ps_epilog.writes_stencil +
6831 key->ps_epilog.writes_samplemask;
6832
6833 required_num_params = MAX2(required_num_params,
6834 ctx->args.num_sgprs_used + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6835
6836 while (ctx->args.arg_count < required_num_params)
6837 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_FLOAT, NULL);
6838
6839 /* Create the function. */
6840 si_llvm_create_func(ctx, "ps_epilog", NULL, 0, 0);
6841 /* Disable elimination of unused inputs. */
6842 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
6843 "InitialPSInputAddr", 0xffffff);
6844
6845 /* Process colors. */
6846 unsigned vgpr = ctx->args.num_sgprs_used;
6847 unsigned colors_written = key->ps_epilog.colors_written;
6848 int last_color_export = -1;
6849
6850 /* Find the last color export. */
6851 if (!key->ps_epilog.writes_z &&
6852 !key->ps_epilog.writes_stencil &&
6853 !key->ps_epilog.writes_samplemask) {
6854 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6855
6856 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6857 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6858 /* Just set this if any of the colorbuffers are enabled. */
6859 if (spi_format &
6860 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6861 last_color_export = 0;
6862 } else {
6863 for (i = 0; i < 8; i++)
6864 if (colors_written & (1 << i) &&
6865 (spi_format >> (i * 4)) & 0xf)
6866 last_color_export = i;
6867 }
6868 }
6869
6870 while (colors_written) {
6871 LLVMValueRef color[4];
6872 int mrt = u_bit_scan(&colors_written);
6873
6874 for (i = 0; i < 4; i++)
6875 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
6876
6877 si_export_mrt_color(ctx, color, mrt,
6878 ctx->args.arg_count - 1,
6879 mrt == last_color_export, &exp);
6880 }
6881
6882 /* Process depth, stencil, samplemask. */
6883 if (key->ps_epilog.writes_z)
6884 depth = LLVMGetParam(ctx->main_fn, vgpr++);
6885 if (key->ps_epilog.writes_stencil)
6886 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
6887 if (key->ps_epilog.writes_samplemask)
6888 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
6889
6890 if (depth || stencil || samplemask)
6891 si_export_mrt_z(ctx, depth, stencil, samplemask, &exp);
6892 else if (last_color_export == -1)
6893 ac_build_export_null(&ctx->ac);
6894
6895 if (exp.num)
6896 si_emit_ps_exports(ctx, &exp);
6897
6898 /* Compile. */
6899 LLVMBuildRetVoid(ctx->ac.builder);
6900 }
6901
6902 /**
6903 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6904 */
6905 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6906 struct ac_llvm_compiler *compiler,
6907 struct si_shader *shader,
6908 struct pipe_debug_callback *debug)
6909 {
6910 union si_shader_part_key prolog_key;
6911 union si_shader_part_key epilog_key;
6912
6913 /* Get the prolog. */
6914 si_get_ps_prolog_key(shader, &prolog_key, true);
6915
6916 /* The prolog is a no-op if these aren't set. */
6917 if (si_need_ps_prolog(&prolog_key)) {
6918 shader->prolog =
6919 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6920 PIPE_SHADER_FRAGMENT, true,
6921 &prolog_key, compiler, debug,
6922 si_build_ps_prolog_function,
6923 "Fragment Shader Prolog");
6924 if (!shader->prolog)
6925 return false;
6926 }
6927
6928 /* Get the epilog. */
6929 si_get_ps_epilog_key(shader, &epilog_key);
6930
6931 shader->epilog =
6932 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6933 PIPE_SHADER_FRAGMENT, false,
6934 &epilog_key, compiler, debug,
6935 si_build_ps_epilog_function,
6936 "Fragment Shader Epilog");
6937 if (!shader->epilog)
6938 return false;
6939
6940 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6941 if (shader->key.part.ps.prolog.poly_stipple) {
6942 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6943 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6944 }
6945
6946 /* Set up the enable bits for per-sample shading if needed. */
6947 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
6948 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6949 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
6950 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
6951 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6952 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
6953 }
6954 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
6955 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6956 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
6957 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
6958 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6959 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
6960 }
6961 if (shader->key.part.ps.prolog.force_persp_center_interp &&
6962 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
6963 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
6964 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
6965 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6966 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6967 }
6968 if (shader->key.part.ps.prolog.force_linear_center_interp &&
6969 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
6970 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
6971 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
6972 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6973 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6974 }
6975
6976 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
6977 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
6978 !(shader->config.spi_ps_input_ena & 0xf)) {
6979 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6980 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
6981 }
6982
6983 /* At least one pair of interpolation weights must be enabled. */
6984 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
6985 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6986 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
6987 }
6988
6989 /* Samplemask fixup requires the sample ID. */
6990 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
6991 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
6992 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
6993 }
6994
6995 /* The sample mask input is always enabled, because the API shader always
6996 * passes it through to the epilog. Disable it here if it's unused.
6997 */
6998 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
6999 !shader->selector->info.reads_samplemask)
7000 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7001
7002 return true;
7003 }
7004
7005 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7006 unsigned *lds_size)
7007 {
7008 /* If tessellation is all offchip and on-chip GS isn't used, this
7009 * workaround is not needed.
7010 */
7011 return;
7012
7013 /* SPI barrier management bug:
7014 * Make sure we have at least 4k of LDS in use to avoid the bug.
7015 * It applies to workgroup sizes of more than one wavefront.
7016 */
7017 if (sscreen->info.family == CHIP_BONAIRE ||
7018 sscreen->info.family == CHIP_KABINI)
7019 *lds_size = MAX2(*lds_size, 8);
7020 }
7021
7022 static void si_fix_resource_usage(struct si_screen *sscreen,
7023 struct si_shader *shader)
7024 {
7025 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7026
7027 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7028
7029 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7030 si_get_max_workgroup_size(shader) > sscreen->compute_wave_size) {
7031 si_multiwave_lds_size_workaround(sscreen,
7032 &shader->config.lds_size);
7033 }
7034 }
7035
7036 bool si_create_shader_variant(struct si_screen *sscreen,
7037 struct ac_llvm_compiler *compiler,
7038 struct si_shader *shader,
7039 struct pipe_debug_callback *debug)
7040 {
7041 struct si_shader_selector *sel = shader->selector;
7042 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7043 int r;
7044
7045 /* LS, ES, VS are compiled on demand if the main part hasn't been
7046 * compiled for that stage.
7047 *
7048 * GS are compiled on demand if the main part hasn't been compiled
7049 * for the chosen NGG-ness.
7050 *
7051 * Vertex shaders are compiled on demand when a vertex fetch
7052 * workaround must be applied.
7053 */
7054 if (shader->is_monolithic) {
7055 /* Monolithic shader (compiled as a whole, has many variants,
7056 * may take a long time to compile).
7057 */
7058 r = si_compile_shader(sscreen, compiler, shader, debug);
7059 if (r)
7060 return false;
7061 } else {
7062 /* The shader consists of several parts:
7063 *
7064 * - the middle part is the user shader, it has 1 variant only
7065 * and it was compiled during the creation of the shader
7066 * selector
7067 * - the prolog part is inserted at the beginning
7068 * - the epilog part is inserted at the end
7069 *
7070 * The prolog and epilog have many (but simple) variants.
7071 *
7072 * Starting with gfx9, geometry and tessellation control
7073 * shaders also contain the prolog and user shader parts of
7074 * the previous shader stage.
7075 */
7076
7077 if (!mainp)
7078 return false;
7079
7080 /* Copy the compiled shader data over. */
7081 shader->is_binary_shared = true;
7082 shader->binary = mainp->binary;
7083 shader->config = mainp->config;
7084 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7085 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7086 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7087 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7088 memcpy(shader->info.vs_output_param_offset,
7089 mainp->info.vs_output_param_offset,
7090 sizeof(mainp->info.vs_output_param_offset));
7091 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7092 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7093 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7094
7095 /* Select prologs and/or epilogs. */
7096 switch (sel->type) {
7097 case PIPE_SHADER_VERTEX:
7098 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
7099 return false;
7100 break;
7101 case PIPE_SHADER_TESS_CTRL:
7102 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
7103 return false;
7104 break;
7105 case PIPE_SHADER_TESS_EVAL:
7106 break;
7107 case PIPE_SHADER_GEOMETRY:
7108 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
7109 return false;
7110 break;
7111 case PIPE_SHADER_FRAGMENT:
7112 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
7113 return false;
7114
7115 /* Make sure we have at least as many VGPRs as there
7116 * are allocated inputs.
7117 */
7118 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7119 shader->info.num_input_vgprs);
7120 break;
7121 default:;
7122 }
7123
7124 /* Update SGPR and VGPR counts. */
7125 if (shader->prolog) {
7126 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7127 shader->prolog->config.num_sgprs);
7128 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7129 shader->prolog->config.num_vgprs);
7130 }
7131 if (shader->previous_stage) {
7132 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7133 shader->previous_stage->config.num_sgprs);
7134 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7135 shader->previous_stage->config.num_vgprs);
7136 shader->config.spilled_sgprs =
7137 MAX2(shader->config.spilled_sgprs,
7138 shader->previous_stage->config.spilled_sgprs);
7139 shader->config.spilled_vgprs =
7140 MAX2(shader->config.spilled_vgprs,
7141 shader->previous_stage->config.spilled_vgprs);
7142 shader->info.private_mem_vgprs =
7143 MAX2(shader->info.private_mem_vgprs,
7144 shader->previous_stage->info.private_mem_vgprs);
7145 shader->config.scratch_bytes_per_wave =
7146 MAX2(shader->config.scratch_bytes_per_wave,
7147 shader->previous_stage->config.scratch_bytes_per_wave);
7148 shader->info.uses_instanceid |=
7149 shader->previous_stage->info.uses_instanceid;
7150 }
7151 if (shader->prolog2) {
7152 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7153 shader->prolog2->config.num_sgprs);
7154 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7155 shader->prolog2->config.num_vgprs);
7156 }
7157 if (shader->epilog) {
7158 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7159 shader->epilog->config.num_sgprs);
7160 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7161 shader->epilog->config.num_vgprs);
7162 }
7163 si_calculate_max_simd_waves(shader);
7164 }
7165
7166 if (shader->key.as_ngg) {
7167 assert(!shader->key.as_es && !shader->key.as_ls);
7168 gfx10_ngg_calculate_subgroup_info(shader);
7169 } else if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY) {
7170 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
7171 }
7172
7173 si_fix_resource_usage(sscreen, shader);
7174 si_shader_dump(sscreen, shader, debug, stderr, true);
7175
7176 /* Upload. */
7177 if (!si_shader_binary_upload(sscreen, shader, 0)) {
7178 fprintf(stderr, "LLVM failed to upload shader\n");
7179 return false;
7180 }
7181
7182 return true;
7183 }
7184
7185 void si_shader_destroy(struct si_shader *shader)
7186 {
7187 if (shader->scratch_bo)
7188 si_resource_reference(&shader->scratch_bo, NULL);
7189
7190 si_resource_reference(&shader->bo, NULL);
7191
7192 if (!shader->is_binary_shared)
7193 si_shader_binary_clean(&shader->binary);
7194
7195 free(shader->shader_log);
7196 }