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radeonsi: move kill intrinsic building into amd/common
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 /**
102 * Returns a unique index for a semantic name and index. The index must be
103 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
104 * calculated.
105 */
106 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
107 {
108 switch (semantic_name) {
109 case TGSI_SEMANTIC_POSITION:
110 return 0;
111 case TGSI_SEMANTIC_PSIZE:
112 return 1;
113 case TGSI_SEMANTIC_CLIPDIST:
114 assert(index <= 1);
115 return 2 + index;
116 case TGSI_SEMANTIC_GENERIC:
117 if (index <= 63-4)
118 return 4 + index;
119
120 assert(!"invalid generic index");
121 return 0;
122
123 /* patch indices are completely separate and thus start from 0 */
124 case TGSI_SEMANTIC_TESSOUTER:
125 return 0;
126 case TGSI_SEMANTIC_TESSINNER:
127 return 1;
128 case TGSI_SEMANTIC_PATCH:
129 return 2 + index;
130
131 default:
132 assert(!"invalid semantic name");
133 return 0;
134 }
135 }
136
137 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
138 {
139 switch (name) {
140 case TGSI_SEMANTIC_FOG:
141 return 0;
142 case TGSI_SEMANTIC_LAYER:
143 return 1;
144 case TGSI_SEMANTIC_VIEWPORT_INDEX:
145 return 2;
146 case TGSI_SEMANTIC_PRIMID:
147 return 3;
148 case TGSI_SEMANTIC_COLOR: /* these alias */
149 case TGSI_SEMANTIC_BCOLOR:
150 return 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 return 6 + index;
153 default:
154 assert(!"invalid semantic name");
155 return 0;
156 }
157 }
158
159 /**
160 * Get the value of a shader input parameter and extract a bitfield.
161 */
162 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
163 unsigned param, unsigned rshift,
164 unsigned bitwidth)
165 {
166 struct gallivm_state *gallivm = &ctx->gallivm;
167 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
168 param);
169
170 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
171 value = bitcast(&ctx->bld_base,
172 TGSI_TYPE_UNSIGNED, value);
173
174 if (rshift)
175 value = LLVMBuildLShr(gallivm->builder, value,
176 lp_build_const_int32(gallivm, rshift), "");
177
178 if (rshift + bitwidth < 32) {
179 unsigned mask = (1 << bitwidth) - 1;
180 value = LLVMBuildAnd(gallivm->builder, value,
181 lp_build_const_int32(gallivm, mask), "");
182 }
183
184 return value;
185 }
186
187 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
188 {
189 switch (ctx->type) {
190 case PIPE_SHADER_TESS_CTRL:
191 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
192
193 case PIPE_SHADER_TESS_EVAL:
194 return LLVMGetParam(ctx->main_fn,
195 ctx->param_tes_rel_patch_id);
196
197 default:
198 assert(0);
199 return NULL;
200 }
201 }
202
203 /* Tessellation shaders pass outputs to the next shader using LDS.
204 *
205 * LS outputs = TCS inputs
206 * TCS outputs = TES inputs
207 *
208 * The LDS layout is:
209 * - TCS inputs for patch 0
210 * - TCS inputs for patch 1
211 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
212 * - ...
213 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
214 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
215 * - TCS outputs for patch 1
216 * - Per-patch TCS outputs for patch 1
217 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
218 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * - ...
220 *
221 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 */
223
224 static LLVMValueRef
225 get_tcs_in_patch_stride(struct si_shader_context *ctx)
226 {
227 if (ctx->type == PIPE_SHADER_VERTEX)
228 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
229 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
230 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
231 else {
232 assert(0);
233 return NULL;
234 }
235 }
236
237 static LLVMValueRef
238 get_tcs_out_patch_stride(struct si_shader_context *ctx)
239 {
240 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
245 {
246 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
247 unpack_param(ctx,
248 SI_PARAM_TCS_OUT_OFFSETS,
249 0, 16),
250 4);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
255 {
256 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
257 unpack_param(ctx,
258 SI_PARAM_TCS_OUT_OFFSETS,
259 16, 16),
260 4);
261 }
262
263 static LLVMValueRef
264 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
265 {
266 struct gallivm_state *gallivm = &ctx->gallivm;
267 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
268 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
269
270 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
271 }
272
273 static LLVMValueRef
274 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
275 {
276 struct gallivm_state *gallivm = &ctx->gallivm;
277 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(gallivm->builder, patch0_offset,
282 LLVMBuildMul(gallivm->builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef
288 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
289 {
290 struct gallivm_state *gallivm = &ctx->gallivm;
291 LLVMValueRef patch0_patch_data_offset =
292 get_tcs_out_patch0_patch_data_offset(ctx);
293 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
294 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
295
296 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
297 LLVMBuildMul(gallivm->builder, patch_stride,
298 rel_patch_id, ""),
299 "");
300 }
301
302 static LLVMValueRef get_instance_index_for_fetch(
303 struct si_shader_context *radeon_bld,
304 unsigned param_start_instance, unsigned divisor)
305 {
306 struct si_shader_context *ctx =
307 si_shader_context(&radeon_bld->bld_base);
308 struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
309
310 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 lp_build_const_int32(gallivm, divisor), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct lp_build_context *base = &ctx->bld_base.base;
344 struct gallivm_state *gallivm = base->gallivm;
345
346 unsigned chan;
347 unsigned fix_fetch;
348 unsigned num_fetches;
349 unsigned fetch_stride;
350
351 LLVMValueRef t_list_ptr;
352 LLVMValueRef t_offset;
353 LLVMValueRef t_list;
354 LLVMValueRef vertex_index;
355 LLVMValueRef args[3];
356 LLVMValueRef input[3];
357
358 /* Load the T list */
359 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
360
361 t_offset = lp_build_const_int32(gallivm, input_index);
362
363 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
364
365 vertex_index = LLVMGetParam(ctx->main_fn,
366 ctx->param_vertex_index0 +
367 input_index);
368
369 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
370
371 /* Do multiple loads for special formats. */
372 switch (fix_fetch) {
373 case SI_FIX_FETCH_RGB_64_FLOAT:
374 num_fetches = 3; /* 3 2-dword loads */
375 fetch_stride = 8;
376 break;
377 case SI_FIX_FETCH_RGBA_64_FLOAT:
378 num_fetches = 2; /* 2 4-dword loads */
379 fetch_stride = 16;
380 break;
381 case SI_FIX_FETCH_RGB_8:
382 case SI_FIX_FETCH_RGB_8_INT:
383 num_fetches = 3;
384 fetch_stride = 1;
385 break;
386 case SI_FIX_FETCH_RGB_16:
387 case SI_FIX_FETCH_RGB_16_INT:
388 num_fetches = 3;
389 fetch_stride = 2;
390 break;
391 default:
392 num_fetches = 1;
393 fetch_stride = 0;
394 }
395
396 args[0] = t_list;
397 args[2] = vertex_index;
398
399 for (unsigned i = 0; i < num_fetches; i++) {
400 args[1] = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
401
402 input[i] = lp_build_intrinsic(gallivm->builder,
403 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
404 LP_FUNC_ATTR_READNONE |
405 LP_FUNC_ATTR_LEGACY);
406 }
407
408 /* Break up the vec4 into individual components */
409 for (chan = 0; chan < 4; chan++) {
410 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
411 out[chan] = LLVMBuildExtractElement(gallivm->builder,
412 input[0], llvm_chan, "");
413 }
414
415 switch (fix_fetch) {
416 case SI_FIX_FETCH_A2_SNORM:
417 case SI_FIX_FETCH_A2_SSCALED:
418 case SI_FIX_FETCH_A2_SINT: {
419 /* The hardware returns an unsigned value; convert it to a
420 * signed one.
421 */
422 LLVMValueRef tmp = out[3];
423 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
424
425 /* First, recover the sign-extended signed integer value. */
426 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
427 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
428 else
429 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
430
431 /* For the integer-like cases, do a natural sign extension.
432 *
433 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
434 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
435 * exponent.
436 */
437 tmp = LLVMBuildShl(gallivm->builder, tmp,
438 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
439 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
440 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
441
442 /* Convert back to the right type. */
443 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
444 LLVMValueRef clamp;
445 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
446 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
447 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
448 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
449 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
450 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
451 }
452
453 out[3] = tmp;
454 break;
455 }
456 case SI_FIX_FETCH_RGBA_32_UNORM:
457 case SI_FIX_FETCH_RGBX_32_UNORM:
458 for (chan = 0; chan < 4; chan++) {
459 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
460 ctx->i32, "");
461 out[chan] = LLVMBuildUIToFP(gallivm->builder,
462 out[chan], ctx->f32, "");
463 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
464 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
465 }
466 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
467 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
468 out[3] = LLVMConstReal(ctx->f32, 1);
469 break;
470 case SI_FIX_FETCH_RGBA_32_SNORM:
471 case SI_FIX_FETCH_RGBX_32_SNORM:
472 case SI_FIX_FETCH_RGBA_32_FIXED:
473 case SI_FIX_FETCH_RGBX_32_FIXED: {
474 double scale;
475 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
476 scale = 1.0 / 0x10000;
477 else
478 scale = 1.0 / INT_MAX;
479
480 for (chan = 0; chan < 4; chan++) {
481 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
482 ctx->i32, "");
483 out[chan] = LLVMBuildSIToFP(gallivm->builder,
484 out[chan], ctx->f32, "");
485 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
486 LLVMConstReal(ctx->f32, scale), "");
487 }
488 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
489 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
490 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
491 out[3] = LLVMConstReal(ctx->f32, 1);
492 break;
493 }
494 case SI_FIX_FETCH_RGBA_32_USCALED:
495 for (chan = 0; chan < 4; chan++) {
496 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
497 ctx->i32, "");
498 out[chan] = LLVMBuildUIToFP(gallivm->builder,
499 out[chan], ctx->f32, "");
500 }
501 break;
502 case SI_FIX_FETCH_RGBA_32_SSCALED:
503 for (chan = 0; chan < 4; chan++) {
504 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
505 ctx->i32, "");
506 out[chan] = LLVMBuildSIToFP(gallivm->builder,
507 out[chan], ctx->f32, "");
508 }
509 break;
510 case SI_FIX_FETCH_RG_64_FLOAT:
511 for (chan = 0; chan < 2; chan++)
512 out[chan] = extract_double_to_float(ctx, input[0], chan);
513
514 out[2] = LLVMConstReal(ctx->f32, 0);
515 out[3] = LLVMConstReal(ctx->f32, 1);
516 break;
517 case SI_FIX_FETCH_RGB_64_FLOAT:
518 for (chan = 0; chan < 3; chan++)
519 out[chan] = extract_double_to_float(ctx, input[chan], 0);
520
521 out[3] = LLVMConstReal(ctx->f32, 1);
522 break;
523 case SI_FIX_FETCH_RGBA_64_FLOAT:
524 for (chan = 0; chan < 4; chan++) {
525 out[chan] = extract_double_to_float(ctx, input[chan / 2],
526 chan % 2);
527 }
528 break;
529 case SI_FIX_FETCH_RGB_8:
530 case SI_FIX_FETCH_RGB_8_INT:
531 case SI_FIX_FETCH_RGB_16:
532 case SI_FIX_FETCH_RGB_16_INT:
533 for (chan = 0; chan < 3; chan++) {
534 out[chan] = LLVMBuildExtractElement(gallivm->builder,
535 input[chan],
536 ctx->i32_0, "");
537 }
538 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
539 fix_fetch == SI_FIX_FETCH_RGB_16) {
540 out[3] = LLVMConstReal(ctx->f32, 1);
541 } else {
542 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
543 ctx->f32, "");
544 }
545 break;
546 }
547 }
548
549 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
550 unsigned swizzle)
551 {
552 struct si_shader_context *ctx = si_shader_context(bld_base);
553
554 if (swizzle > 0)
555 return bld_base->uint_bld.zero;
556
557 switch (ctx->type) {
558 case PIPE_SHADER_VERTEX:
559 return LLVMGetParam(ctx->main_fn,
560 ctx->param_vs_prim_id);
561 case PIPE_SHADER_TESS_CTRL:
562 return LLVMGetParam(ctx->main_fn,
563 SI_PARAM_PATCH_ID);
564 case PIPE_SHADER_TESS_EVAL:
565 return LLVMGetParam(ctx->main_fn,
566 ctx->param_tes_patch_id);
567 case PIPE_SHADER_GEOMETRY:
568 return LLVMGetParam(ctx->main_fn,
569 SI_PARAM_PRIMITIVE_ID);
570 default:
571 assert(0);
572 return bld_base->uint_bld.zero;
573 }
574 }
575
576 /**
577 * Return the value of tgsi_ind_register for indexing.
578 * This is the indirect index with the constant offset added to it.
579 */
580 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
581 const struct tgsi_ind_register *ind,
582 int rel_index)
583 {
584 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
585 LLVMValueRef result;
586
587 result = ctx->addrs[ind->Index][ind->Swizzle];
588 result = LLVMBuildLoad(gallivm->builder, result, "");
589 result = LLVMBuildAdd(gallivm->builder, result,
590 lp_build_const_int32(gallivm, rel_index), "");
591 return result;
592 }
593
594 /**
595 * Like get_indirect_index, but restricts the return value to a (possibly
596 * undefined) value inside [0..num).
597 */
598 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
599 const struct tgsi_ind_register *ind,
600 int rel_index, unsigned num)
601 {
602 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
603
604 /* LLVM 3.8: If indirect resource indexing is used:
605 * - SI & CIK hang
606 * - VI crashes
607 */
608 if (HAVE_LLVM <= 0x0308)
609 return LLVMGetUndef(ctx->i32);
610
611 return si_llvm_bound_index(ctx, result, num);
612 }
613
614
615 /**
616 * Calculate a dword address given an input or output register and a stride.
617 */
618 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
619 const struct tgsi_full_dst_register *dst,
620 const struct tgsi_full_src_register *src,
621 LLVMValueRef vertex_dw_stride,
622 LLVMValueRef base_addr)
623 {
624 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
625 struct tgsi_shader_info *info = &ctx->shader->selector->info;
626 ubyte *name, *index, *array_first;
627 int first, param;
628 struct tgsi_full_dst_register reg;
629
630 /* Set the register description. The address computation is the same
631 * for sources and destinations. */
632 if (src) {
633 reg.Register.File = src->Register.File;
634 reg.Register.Index = src->Register.Index;
635 reg.Register.Indirect = src->Register.Indirect;
636 reg.Register.Dimension = src->Register.Dimension;
637 reg.Indirect = src->Indirect;
638 reg.Dimension = src->Dimension;
639 reg.DimIndirect = src->DimIndirect;
640 } else
641 reg = *dst;
642
643 /* If the register is 2-dimensional (e.g. an array of vertices
644 * in a primitive), calculate the base address of the vertex. */
645 if (reg.Register.Dimension) {
646 LLVMValueRef index;
647
648 if (reg.Dimension.Indirect)
649 index = get_indirect_index(ctx, &reg.DimIndirect,
650 reg.Dimension.Index);
651 else
652 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
653
654 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
655 LLVMBuildMul(gallivm->builder, index,
656 vertex_dw_stride, ""), "");
657 }
658
659 /* Get information about the register. */
660 if (reg.Register.File == TGSI_FILE_INPUT) {
661 name = info->input_semantic_name;
662 index = info->input_semantic_index;
663 array_first = info->input_array_first;
664 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
665 name = info->output_semantic_name;
666 index = info->output_semantic_index;
667 array_first = info->output_array_first;
668 } else {
669 assert(0);
670 return NULL;
671 }
672
673 if (reg.Register.Indirect) {
674 /* Add the relative address of the element. */
675 LLVMValueRef ind_index;
676
677 if (reg.Indirect.ArrayID)
678 first = array_first[reg.Indirect.ArrayID];
679 else
680 first = reg.Register.Index;
681
682 ind_index = get_indirect_index(ctx, &reg.Indirect,
683 reg.Register.Index - first);
684
685 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
686 LLVMBuildMul(gallivm->builder, ind_index,
687 lp_build_const_int32(gallivm, 4), ""), "");
688
689 param = si_shader_io_get_unique_index(name[first], index[first]);
690 } else {
691 param = si_shader_io_get_unique_index(name[reg.Register.Index],
692 index[reg.Register.Index]);
693 }
694
695 /* Add the base address of the element. */
696 return LLVMBuildAdd(gallivm->builder, base_addr,
697 lp_build_const_int32(gallivm, param * 4), "");
698 }
699
700 /* The offchip buffer layout for TCS->TES is
701 *
702 * - attribute 0 of patch 0 vertex 0
703 * - attribute 0 of patch 0 vertex 1
704 * - attribute 0 of patch 0 vertex 2
705 * ...
706 * - attribute 0 of patch 1 vertex 0
707 * - attribute 0 of patch 1 vertex 1
708 * ...
709 * - attribute 1 of patch 0 vertex 0
710 * - attribute 1 of patch 0 vertex 1
711 * ...
712 * - per patch attribute 0 of patch 0
713 * - per patch attribute 0 of patch 1
714 * ...
715 *
716 * Note that every attribute has 4 components.
717 */
718 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
719 LLVMValueRef rel_patch_id,
720 LLVMValueRef vertex_index,
721 LLVMValueRef param_index)
722 {
723 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
724 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
725 LLVMValueRef param_stride, constant16;
726
727 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
728 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
729 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
730 num_patches, "");
731
732 constant16 = lp_build_const_int32(gallivm, 16);
733 if (vertex_index) {
734 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
735 vertices_per_patch, "");
736
737 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
738 vertex_index, "");
739
740 param_stride = total_vertices;
741 } else {
742 base_addr = rel_patch_id;
743 param_stride = num_patches;
744 }
745
746 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
747 LLVMBuildMul(gallivm->builder, param_index,
748 param_stride, ""), "");
749
750 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
751
752 if (!vertex_index) {
753 LLVMValueRef patch_data_offset =
754 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
755
756 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
757 patch_data_offset, "");
758 }
759 return base_addr;
760 }
761
762 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
763 struct si_shader_context *ctx,
764 const struct tgsi_full_dst_register *dst,
765 const struct tgsi_full_src_register *src)
766 {
767 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
768 struct tgsi_shader_info *info = &ctx->shader->selector->info;
769 ubyte *name, *index, *array_first;
770 struct tgsi_full_src_register reg;
771 LLVMValueRef vertex_index = NULL;
772 LLVMValueRef param_index = NULL;
773 unsigned param_index_base, param_base;
774
775 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
776
777 if (reg.Register.Dimension) {
778
779 if (reg.Dimension.Indirect)
780 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
781 reg.Dimension.Index);
782 else
783 vertex_index = lp_build_const_int32(gallivm,
784 reg.Dimension.Index);
785 }
786
787 /* Get information about the register. */
788 if (reg.Register.File == TGSI_FILE_INPUT) {
789 name = info->input_semantic_name;
790 index = info->input_semantic_index;
791 array_first = info->input_array_first;
792 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
793 name = info->output_semantic_name;
794 index = info->output_semantic_index;
795 array_first = info->output_array_first;
796 } else {
797 assert(0);
798 return NULL;
799 }
800
801 if (reg.Register.Indirect) {
802 if (reg.Indirect.ArrayID)
803 param_base = array_first[reg.Indirect.ArrayID];
804 else
805 param_base = reg.Register.Index;
806
807 param_index = get_indirect_index(ctx, &reg.Indirect,
808 reg.Register.Index - param_base);
809
810 } else {
811 param_base = reg.Register.Index;
812 param_index = lp_build_const_int32(gallivm, 0);
813 }
814
815 param_index_base = si_shader_io_get_unique_index(name[param_base],
816 index[param_base]);
817
818 param_index = LLVMBuildAdd(gallivm->builder, param_index,
819 lp_build_const_int32(gallivm, param_index_base),
820 "");
821
822 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
823 vertex_index, param_index);
824 }
825
826 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
827 enum tgsi_opcode_type type, unsigned swizzle,
828 LLVMValueRef buffer, LLVMValueRef offset,
829 LLVMValueRef base, bool readonly_memory)
830 {
831 struct si_shader_context *ctx = si_shader_context(bld_base);
832 struct gallivm_state *gallivm = bld_base->base.gallivm;
833 LLVMValueRef value, value2;
834 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
835 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
836
837 if (swizzle == ~0) {
838 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
839 0, 1, 0, readonly_memory);
840
841 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
842 }
843
844 if (!tgsi_type_is_64bit(type)) {
845 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
846 0, 1, 0, readonly_memory);
847
848 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
849 return LLVMBuildExtractElement(gallivm->builder, value,
850 lp_build_const_int32(gallivm, swizzle), "");
851 }
852
853 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
854 swizzle * 4, 1, 0, readonly_memory);
855
856 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
857 swizzle * 4 + 4, 1, 0, readonly_memory);
858
859 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
860 }
861
862 /**
863 * Load from LDS.
864 *
865 * \param type output value type
866 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
867 * \param dw_addr address in dwords
868 */
869 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
870 enum tgsi_opcode_type type, unsigned swizzle,
871 LLVMValueRef dw_addr)
872 {
873 struct si_shader_context *ctx = si_shader_context(bld_base);
874 struct gallivm_state *gallivm = bld_base->base.gallivm;
875 LLVMValueRef value;
876
877 if (swizzle == ~0) {
878 LLVMValueRef values[TGSI_NUM_CHANNELS];
879
880 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
881 values[chan] = lds_load(bld_base, type, chan, dw_addr);
882
883 return lp_build_gather_values(bld_base->base.gallivm, values,
884 TGSI_NUM_CHANNELS);
885 }
886
887 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
888 lp_build_const_int32(gallivm, swizzle));
889
890 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
891 if (tgsi_type_is_64bit(type)) {
892 LLVMValueRef value2;
893 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
894 lp_build_const_int32(gallivm, 1));
895 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
896 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
897 }
898
899 return LLVMBuildBitCast(gallivm->builder, value,
900 tgsi2llvmtype(bld_base, type), "");
901 }
902
903 /**
904 * Store to LDS.
905 *
906 * \param swizzle offset (typically 0..3)
907 * \param dw_addr address in dwords
908 * \param value value to store
909 */
910 static void lds_store(struct lp_build_tgsi_context *bld_base,
911 unsigned swizzle, LLVMValueRef dw_addr,
912 LLVMValueRef value)
913 {
914 struct si_shader_context *ctx = si_shader_context(bld_base);
915 struct gallivm_state *gallivm = bld_base->base.gallivm;
916
917 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
918 lp_build_const_int32(gallivm, swizzle));
919
920 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
921 ac_build_indexed_store(&ctx->ac, ctx->lds,
922 dw_addr, value);
923 }
924
925 static LLVMValueRef fetch_input_tcs(
926 struct lp_build_tgsi_context *bld_base,
927 const struct tgsi_full_src_register *reg,
928 enum tgsi_opcode_type type, unsigned swizzle)
929 {
930 struct si_shader_context *ctx = si_shader_context(bld_base);
931 LLVMValueRef dw_addr, stride;
932
933 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
934 dw_addr = get_tcs_in_current_patch_offset(ctx);
935 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
936
937 return lds_load(bld_base, type, swizzle, dw_addr);
938 }
939
940 static LLVMValueRef fetch_output_tcs(
941 struct lp_build_tgsi_context *bld_base,
942 const struct tgsi_full_src_register *reg,
943 enum tgsi_opcode_type type, unsigned swizzle)
944 {
945 struct si_shader_context *ctx = si_shader_context(bld_base);
946 LLVMValueRef dw_addr, stride;
947
948 if (reg->Register.Dimension) {
949 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
950 dw_addr = get_tcs_out_current_patch_offset(ctx);
951 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
952 } else {
953 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
954 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
955 }
956
957 return lds_load(bld_base, type, swizzle, dw_addr);
958 }
959
960 static LLVMValueRef fetch_input_tes(
961 struct lp_build_tgsi_context *bld_base,
962 const struct tgsi_full_src_register *reg,
963 enum tgsi_opcode_type type, unsigned swizzle)
964 {
965 struct si_shader_context *ctx = si_shader_context(bld_base);
966 struct gallivm_state *gallivm = bld_base->base.gallivm;
967 LLVMValueRef rw_buffers, buffer, base, addr;
968
969 rw_buffers = LLVMGetParam(ctx->main_fn,
970 SI_PARAM_RW_BUFFERS);
971 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
972 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
973
974 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
975 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
976
977 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
978 }
979
980 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
981 const struct tgsi_full_instruction *inst,
982 const struct tgsi_opcode_info *info,
983 LLVMValueRef dst[4])
984 {
985 struct si_shader_context *ctx = si_shader_context(bld_base);
986 struct gallivm_state *gallivm = bld_base->base.gallivm;
987 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
988 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
989 unsigned chan_index;
990 LLVMValueRef dw_addr, stride;
991 LLVMValueRef rw_buffers, buffer, base, buf_addr;
992 LLVMValueRef values[4];
993 bool skip_lds_store;
994 bool is_tess_factor = false;
995
996 /* Only handle per-patch and per-vertex outputs here.
997 * Vectors will be lowered to scalars and this function will be called again.
998 */
999 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1000 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1001 si_llvm_emit_store(bld_base, inst, info, dst);
1002 return;
1003 }
1004
1005 if (reg->Register.Dimension) {
1006 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1007 dw_addr = get_tcs_out_current_patch_offset(ctx);
1008 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1009 skip_lds_store = !sh_info->reads_pervertex_outputs;
1010 } else {
1011 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1012 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1013 skip_lds_store = !sh_info->reads_perpatch_outputs;
1014
1015 if (!reg->Register.Indirect) {
1016 int name = sh_info->output_semantic_name[reg->Register.Index];
1017
1018 /* Always write tess factors into LDS for the TCS epilog. */
1019 if (name == TGSI_SEMANTIC_TESSINNER ||
1020 name == TGSI_SEMANTIC_TESSOUTER) {
1021 skip_lds_store = false;
1022 is_tess_factor = true;
1023 }
1024 }
1025 }
1026
1027 rw_buffers = LLVMGetParam(ctx->main_fn,
1028 SI_PARAM_RW_BUFFERS);
1029 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1030 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1031
1032 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1033 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1034
1035
1036 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1037 LLVMValueRef value = dst[chan_index];
1038
1039 if (inst->Instruction.Saturate)
1040 value = ac_emit_clamp(&ctx->ac, value);
1041
1042 /* Skip LDS stores if there is no LDS read of this output. */
1043 if (!skip_lds_store)
1044 lds_store(bld_base, chan_index, dw_addr, value);
1045
1046 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1047 values[chan_index] = value;
1048
1049 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1050 ac_build_tbuffer_store_dwords(&ctx->ac, buffer, value, 1,
1051 buf_addr, base,
1052 4 * chan_index);
1053 }
1054 }
1055
1056 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1057 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1058 values, 4);
1059 ac_build_tbuffer_store_dwords(&ctx->ac, buffer, value, 4, buf_addr,
1060 base, 0);
1061 }
1062 }
1063
1064 static LLVMValueRef fetch_input_gs(
1065 struct lp_build_tgsi_context *bld_base,
1066 const struct tgsi_full_src_register *reg,
1067 enum tgsi_opcode_type type,
1068 unsigned swizzle)
1069 {
1070 struct lp_build_context *base = &bld_base->base;
1071 struct si_shader_context *ctx = si_shader_context(bld_base);
1072 struct si_shader *shader = ctx->shader;
1073 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1074 struct gallivm_state *gallivm = base->gallivm;
1075 LLVMValueRef vtx_offset, soffset;
1076 unsigned vtx_offset_param;
1077 struct tgsi_shader_info *info = &shader->selector->info;
1078 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1079 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1080 unsigned param;
1081 LLVMValueRef value;
1082
1083 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1084 return get_primitive_id(bld_base, swizzle);
1085
1086 if (!reg->Register.Dimension)
1087 return NULL;
1088
1089 if (swizzle == ~0) {
1090 LLVMValueRef values[TGSI_NUM_CHANNELS];
1091 unsigned chan;
1092 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1093 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1094 }
1095 return lp_build_gather_values(bld_base->base.gallivm, values,
1096 TGSI_NUM_CHANNELS);
1097 }
1098
1099 /* Get the vertex offset parameter */
1100 vtx_offset_param = reg->Dimension.Index;
1101 if (vtx_offset_param < 2) {
1102 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1103 } else {
1104 assert(vtx_offset_param < 6);
1105 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1106 }
1107 vtx_offset = lp_build_mul_imm(uint,
1108 LLVMGetParam(ctx->main_fn,
1109 vtx_offset_param),
1110 4);
1111
1112 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1113 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1114
1115 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, uint->zero,
1116 vtx_offset, soffset, 0, 1, 0, true);
1117 if (tgsi_type_is_64bit(type)) {
1118 LLVMValueRef value2;
1119 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1120
1121 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1122 uint->zero, vtx_offset, soffset,
1123 0, 1, 0, true);
1124 return si_llvm_emit_fetch_64bit(bld_base, type,
1125 value, value2);
1126 }
1127 return LLVMBuildBitCast(gallivm->builder,
1128 value,
1129 tgsi2llvmtype(bld_base, type), "");
1130 }
1131
1132 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1133 {
1134 switch (interpolate) {
1135 case TGSI_INTERPOLATE_CONSTANT:
1136 return 0;
1137
1138 case TGSI_INTERPOLATE_LINEAR:
1139 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1140 return SI_PARAM_LINEAR_SAMPLE;
1141 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1142 return SI_PARAM_LINEAR_CENTROID;
1143 else
1144 return SI_PARAM_LINEAR_CENTER;
1145 break;
1146 case TGSI_INTERPOLATE_COLOR:
1147 case TGSI_INTERPOLATE_PERSPECTIVE:
1148 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1149 return SI_PARAM_PERSP_SAMPLE;
1150 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1151 return SI_PARAM_PERSP_CENTROID;
1152 else
1153 return SI_PARAM_PERSP_CENTER;
1154 break;
1155 default:
1156 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1157 return -1;
1158 }
1159 }
1160
1161 /**
1162 * Interpolate a fragment shader input.
1163 *
1164 * @param ctx context
1165 * @param input_index index of the input in hardware
1166 * @param semantic_name TGSI_SEMANTIC_*
1167 * @param semantic_index semantic index
1168 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1169 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1170 * @param interp_param interpolation weights (i,j)
1171 * @param prim_mask SI_PARAM_PRIM_MASK
1172 * @param face SI_PARAM_FRONT_FACE
1173 * @param result the return value (4 components)
1174 */
1175 static void interp_fs_input(struct si_shader_context *ctx,
1176 unsigned input_index,
1177 unsigned semantic_name,
1178 unsigned semantic_index,
1179 unsigned num_interp_inputs,
1180 unsigned colors_read_mask,
1181 LLVMValueRef interp_param,
1182 LLVMValueRef prim_mask,
1183 LLVMValueRef face,
1184 LLVMValueRef result[4])
1185 {
1186 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1187 struct lp_build_context *base = &bld_base->base;
1188 struct lp_build_context *uint = &bld_base->uint_bld;
1189 struct gallivm_state *gallivm = base->gallivm;
1190 LLVMValueRef attr_number;
1191 LLVMValueRef i, j;
1192
1193 unsigned chan;
1194
1195 /* fs.constant returns the param from the middle vertex, so it's not
1196 * really useful for flat shading. It's meant to be used for custom
1197 * interpolation (but the intrinsic can't fetch from the other two
1198 * vertices).
1199 *
1200 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1201 * to do the right thing. The only reason we use fs.constant is that
1202 * fs.interp cannot be used on integers, because they can be equal
1203 * to NaN.
1204 *
1205 * When interp is false we will use fs.constant or for newer llvm,
1206 * amdgcn.interp.mov.
1207 */
1208 bool interp = interp_param != NULL;
1209
1210 attr_number = lp_build_const_int32(gallivm, input_index);
1211
1212 if (interp) {
1213 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1214 LLVMVectorType(ctx->f32, 2), "");
1215
1216 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1217 uint->zero, "");
1218 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1219 uint->one, "");
1220 }
1221
1222 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1223 ctx->shader->key.part.ps.prolog.color_two_side) {
1224 LLVMValueRef is_face_positive;
1225 LLVMValueRef back_attr_number;
1226
1227 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1228 * otherwise it's at offset "num_inputs".
1229 */
1230 unsigned back_attr_offset = num_interp_inputs;
1231 if (semantic_index == 1 && colors_read_mask & 0xf)
1232 back_attr_offset += 1;
1233
1234 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1235
1236 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1237 face, uint->zero, "");
1238
1239 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1240 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1241 LLVMValueRef front, back;
1242
1243 if (interp) {
1244 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1245 attr_number, prim_mask,
1246 i, j);
1247 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1248 back_attr_number, prim_mask,
1249 i, j);
1250 } else {
1251 front = ac_build_fs_interp_mov(&ctx->ac,
1252 lp_build_const_int32(gallivm, 2), /* P0 */
1253 llvm_chan, attr_number, prim_mask);
1254 back = ac_build_fs_interp_mov(&ctx->ac,
1255 lp_build_const_int32(gallivm, 2), /* P0 */
1256 llvm_chan, back_attr_number, prim_mask);
1257 }
1258
1259 result[chan] = LLVMBuildSelect(gallivm->builder,
1260 is_face_positive,
1261 front,
1262 back,
1263 "");
1264 }
1265 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1266 if (interp) {
1267 result[0] = ac_build_fs_interp(&ctx->ac, uint->zero,
1268 attr_number, prim_mask, i, j);
1269 } else {
1270 result[0] = ac_build_fs_interp_mov(&ctx->ac, uint->zero,
1271 lp_build_const_int32(gallivm, 2), /* P0 */
1272 attr_number, prim_mask);
1273 }
1274 result[1] =
1275 result[2] = lp_build_const_float(gallivm, 0.0f);
1276 result[3] = lp_build_const_float(gallivm, 1.0f);
1277 } else {
1278 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1279 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1280
1281 if (interp) {
1282 result[chan] = ac_build_fs_interp(&ctx->ac,
1283 llvm_chan, attr_number, prim_mask, i, j);
1284 } else {
1285 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1286 lp_build_const_int32(gallivm, 2), /* P0 */
1287 llvm_chan, attr_number, prim_mask);
1288 }
1289 }
1290 }
1291 }
1292
1293 static void declare_input_fs(
1294 struct si_shader_context *radeon_bld,
1295 unsigned input_index,
1296 const struct tgsi_full_declaration *decl,
1297 LLVMValueRef out[4])
1298 {
1299 struct lp_build_context *base = &radeon_bld->bld_base.base;
1300 struct si_shader_context *ctx =
1301 si_shader_context(&radeon_bld->bld_base);
1302 struct si_shader *shader = ctx->shader;
1303 LLVMValueRef main_fn = radeon_bld->main_fn;
1304 LLVMValueRef interp_param = NULL;
1305 int interp_param_idx;
1306
1307 /* Get colors from input VGPRs (set by the prolog). */
1308 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1309 unsigned i = decl->Semantic.Index;
1310 unsigned colors_read = shader->selector->info.colors_read;
1311 unsigned mask = colors_read >> (i * 4);
1312 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1313 (i ? util_bitcount(colors_read & 0xf) : 0);
1314
1315 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1316 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1317 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1318 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1319 return;
1320 }
1321
1322 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1323 decl->Interp.Location);
1324 if (interp_param_idx == -1)
1325 return;
1326 else if (interp_param_idx) {
1327 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1328 }
1329
1330 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1331 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1332 ctx->shader->key.part.ps.prolog.flatshade_colors)
1333 interp_param = NULL; /* load the constant color */
1334
1335 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1336 decl->Semantic.Index, shader->selector->info.num_inputs,
1337 shader->selector->info.colors_read, interp_param,
1338 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1339 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1340 &out[0]);
1341 }
1342
1343 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1344 {
1345 return unpack_param(si_shader_context(&radeon_bld->bld_base),
1346 SI_PARAM_ANCILLARY, 8, 4);
1347 }
1348
1349
1350 /**
1351 * Load a dword from a constant buffer.
1352 */
1353 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1354 LLVMValueRef resource,
1355 LLVMValueRef offset)
1356 {
1357 LLVMBuilderRef builder = ctx->gallivm.builder;
1358 LLVMValueRef args[2] = {resource, offset};
1359
1360 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1361 LP_FUNC_ATTR_READNONE |
1362 LP_FUNC_ATTR_LEGACY);
1363 }
1364
1365 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1366 {
1367 struct si_shader_context *ctx =
1368 si_shader_context(&radeon_bld->bld_base);
1369 struct lp_build_context *uint_bld = &radeon_bld->bld_base.uint_bld;
1370 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1371 LLVMBuilderRef builder = gallivm->builder;
1372 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1373 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1374 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1375
1376 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1377 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1378 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1379
1380 LLVMValueRef pos[4] = {
1381 buffer_load_const(ctx, resource, offset0),
1382 buffer_load_const(ctx, resource, offset1),
1383 lp_build_const_float(gallivm, 0),
1384 lp_build_const_float(gallivm, 0)
1385 };
1386
1387 return lp_build_gather_values(gallivm, pos, 4);
1388 }
1389
1390 static void declare_system_value(
1391 struct si_shader_context *radeon_bld,
1392 unsigned index,
1393 const struct tgsi_full_declaration *decl)
1394 {
1395 struct si_shader_context *ctx =
1396 si_shader_context(&radeon_bld->bld_base);
1397 struct lp_build_context *bld = &radeon_bld->bld_base.base;
1398 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1399 LLVMValueRef value = 0;
1400
1401 switch (decl->Semantic.Name) {
1402 case TGSI_SEMANTIC_INSTANCEID:
1403 value = LLVMGetParam(radeon_bld->main_fn,
1404 ctx->param_instance_id);
1405 break;
1406
1407 case TGSI_SEMANTIC_VERTEXID:
1408 value = LLVMBuildAdd(gallivm->builder,
1409 LLVMGetParam(radeon_bld->main_fn,
1410 ctx->param_vertex_id),
1411 LLVMGetParam(radeon_bld->main_fn,
1412 SI_PARAM_BASE_VERTEX), "");
1413 break;
1414
1415 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1416 value = LLVMGetParam(radeon_bld->main_fn,
1417 ctx->param_vertex_id);
1418 break;
1419
1420 case TGSI_SEMANTIC_BASEVERTEX:
1421 value = LLVMGetParam(radeon_bld->main_fn,
1422 SI_PARAM_BASE_VERTEX);
1423 break;
1424
1425 case TGSI_SEMANTIC_BASEINSTANCE:
1426 value = LLVMGetParam(radeon_bld->main_fn,
1427 SI_PARAM_START_INSTANCE);
1428 break;
1429
1430 case TGSI_SEMANTIC_DRAWID:
1431 value = LLVMGetParam(radeon_bld->main_fn,
1432 SI_PARAM_DRAWID);
1433 break;
1434
1435 case TGSI_SEMANTIC_INVOCATIONID:
1436 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1437 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1438 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1439 value = LLVMGetParam(radeon_bld->main_fn,
1440 SI_PARAM_GS_INSTANCE_ID);
1441 else
1442 assert(!"INVOCATIONID not implemented");
1443 break;
1444
1445 case TGSI_SEMANTIC_POSITION:
1446 {
1447 LLVMValueRef pos[4] = {
1448 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1449 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1450 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1451 lp_build_emit_llvm_unary(&radeon_bld->bld_base, TGSI_OPCODE_RCP,
1452 LLVMGetParam(radeon_bld->main_fn,
1453 SI_PARAM_POS_W_FLOAT)),
1454 };
1455 value = lp_build_gather_values(gallivm, pos, 4);
1456 break;
1457 }
1458
1459 case TGSI_SEMANTIC_FACE:
1460 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1461 break;
1462
1463 case TGSI_SEMANTIC_SAMPLEID:
1464 value = get_sample_id(radeon_bld);
1465 break;
1466
1467 case TGSI_SEMANTIC_SAMPLEPOS: {
1468 LLVMValueRef pos[4] = {
1469 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1470 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1471 lp_build_const_float(gallivm, 0),
1472 lp_build_const_float(gallivm, 0)
1473 };
1474 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1475 TGSI_OPCODE_FRC, pos[0]);
1476 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1477 TGSI_OPCODE_FRC, pos[1]);
1478 value = lp_build_gather_values(gallivm, pos, 4);
1479 break;
1480 }
1481
1482 case TGSI_SEMANTIC_SAMPLEMASK:
1483 /* This can only occur with the OpenGL Core profile, which
1484 * doesn't support smoothing.
1485 */
1486 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1487 break;
1488
1489 case TGSI_SEMANTIC_TESSCOORD:
1490 {
1491 LLVMValueRef coord[4] = {
1492 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1493 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1494 bld->zero,
1495 bld->zero
1496 };
1497
1498 /* For triangles, the vector should be (u, v, 1-u-v). */
1499 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1500 PIPE_PRIM_TRIANGLES)
1501 coord[2] = lp_build_sub(bld, bld->one,
1502 lp_build_add(bld, coord[0], coord[1]));
1503
1504 value = lp_build_gather_values(gallivm, coord, 4);
1505 break;
1506 }
1507
1508 case TGSI_SEMANTIC_VERTICESIN:
1509 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1510 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1511 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1512 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1513 else
1514 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1515 break;
1516
1517 case TGSI_SEMANTIC_TESSINNER:
1518 case TGSI_SEMANTIC_TESSOUTER:
1519 {
1520 LLVMValueRef rw_buffers, buffer, base, addr;
1521 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1522
1523 rw_buffers = LLVMGetParam(ctx->main_fn,
1524 SI_PARAM_RW_BUFFERS);
1525 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1526 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1527
1528 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1529 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1530 lp_build_const_int32(gallivm, param));
1531
1532 value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
1533 ~0, buffer, base, addr, true);
1534
1535 break;
1536 }
1537
1538 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1539 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1540 {
1541 LLVMValueRef buf, slot, val[4];
1542 int i, offset;
1543
1544 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1545 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1546 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1547 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1548
1549 for (i = 0; i < 4; i++)
1550 val[i] = buffer_load_const(ctx, buf,
1551 lp_build_const_int32(gallivm, (offset + i) * 4));
1552 value = lp_build_gather_values(gallivm, val, 4);
1553 break;
1554 }
1555
1556 case TGSI_SEMANTIC_PRIMID:
1557 value = get_primitive_id(&radeon_bld->bld_base, 0);
1558 break;
1559
1560 case TGSI_SEMANTIC_GRID_SIZE:
1561 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1562 break;
1563
1564 case TGSI_SEMANTIC_BLOCK_SIZE:
1565 {
1566 LLVMValueRef values[3];
1567 unsigned i;
1568 unsigned *properties = ctx->shader->selector->info.properties;
1569
1570 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1571 unsigned sizes[3] = {
1572 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1573 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1574 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1575 };
1576
1577 for (i = 0; i < 3; ++i)
1578 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1579
1580 value = lp_build_gather_values(gallivm, values, 3);
1581 } else {
1582 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1583 }
1584 break;
1585 }
1586
1587 case TGSI_SEMANTIC_BLOCK_ID:
1588 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1589 break;
1590
1591 case TGSI_SEMANTIC_THREAD_ID:
1592 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1593 break;
1594
1595 case TGSI_SEMANTIC_HELPER_INVOCATION:
1596 if (HAVE_LLVM >= 0x0309) {
1597 value = lp_build_intrinsic(gallivm->builder,
1598 "llvm.amdgcn.ps.live",
1599 ctx->i1, NULL, 0,
1600 LP_FUNC_ATTR_READNONE);
1601 value = LLVMBuildNot(gallivm->builder, value, "");
1602 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1603 } else {
1604 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1605 return;
1606 }
1607 break;
1608
1609 default:
1610 assert(!"unknown system value");
1611 return;
1612 }
1613
1614 radeon_bld->system_values[index] = value;
1615 }
1616
1617 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1618 const struct tgsi_full_declaration *decl)
1619 {
1620 struct si_shader_context *ctx =
1621 si_shader_context(&radeon_bld->bld_base);
1622 struct si_shader_selector *sel = ctx->shader->selector;
1623 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1624
1625 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1626 LLVMValueRef var;
1627
1628 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1629 assert(decl->Range.First == decl->Range.Last);
1630 assert(!ctx->shared_memory);
1631
1632 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1633 LLVMArrayType(ctx->i8, sel->local_size),
1634 "compute_lds",
1635 LOCAL_ADDR_SPACE);
1636 LLVMSetAlignment(var, 4);
1637
1638 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1639 }
1640
1641 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1642 {
1643 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1644 SI_PARAM_CONST_BUFFERS);
1645
1646 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1647 LLVMConstInt(ctx->i32, i, 0));
1648 }
1649
1650 static LLVMValueRef fetch_constant(
1651 struct lp_build_tgsi_context *bld_base,
1652 const struct tgsi_full_src_register *reg,
1653 enum tgsi_opcode_type type,
1654 unsigned swizzle)
1655 {
1656 struct si_shader_context *ctx = si_shader_context(bld_base);
1657 struct lp_build_context *base = &bld_base->base;
1658 const struct tgsi_ind_register *ireg = &reg->Indirect;
1659 unsigned buf, idx;
1660
1661 LLVMValueRef addr, bufp;
1662 LLVMValueRef result;
1663
1664 if (swizzle == LP_CHAN_ALL) {
1665 unsigned chan;
1666 LLVMValueRef values[4];
1667 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1668 values[chan] = fetch_constant(bld_base, reg, type, chan);
1669
1670 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1671 }
1672
1673 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1674 idx = reg->Register.Index * 4 + swizzle;
1675
1676 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1677 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1678 LLVMValueRef index;
1679 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1680 reg->Dimension.Index,
1681 SI_NUM_CONST_BUFFERS);
1682 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1683 } else
1684 bufp = load_const_buffer_desc(ctx, buf);
1685
1686 if (reg->Register.Indirect) {
1687 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1688 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1689 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1690 addr = lp_build_add(&bld_base->uint_bld, addr,
1691 lp_build_const_int32(base->gallivm, idx * 4));
1692 } else {
1693 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1694 }
1695
1696 result = buffer_load_const(ctx, bufp, addr);
1697
1698 if (!tgsi_type_is_64bit(type))
1699 result = bitcast(bld_base, type, result);
1700 else {
1701 LLVMValueRef addr2, result2;
1702
1703 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1704 LLVMConstInt(ctx->i32, 4, 0));
1705 result2 = buffer_load_const(ctx, bufp, addr2);
1706
1707 result = si_llvm_emit_fetch_64bit(bld_base, type,
1708 result, result2);
1709 }
1710 return result;
1711 }
1712
1713 /* Upper 16 bits must be zero. */
1714 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1715 LLVMValueRef val[2])
1716 {
1717 return LLVMBuildOr(gallivm->builder, val[0],
1718 LLVMBuildShl(gallivm->builder, val[1],
1719 lp_build_const_int32(gallivm, 16),
1720 ""), "");
1721 }
1722
1723 /* Upper 16 bits are ignored and will be dropped. */
1724 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1725 LLVMValueRef val[2])
1726 {
1727 LLVMValueRef v[2] = {
1728 LLVMBuildAnd(gallivm->builder, val[0],
1729 lp_build_const_int32(gallivm, 0xffff), ""),
1730 val[1],
1731 };
1732 return si_llvm_pack_two_int16(gallivm, v);
1733 }
1734
1735 /* Initialize arguments for the shader export intrinsic */
1736 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1737 LLVMValueRef *values,
1738 unsigned target,
1739 struct ac_export_args *args)
1740 {
1741 struct si_shader_context *ctx = si_shader_context(bld_base);
1742 struct lp_build_context *base = &bld_base->base;
1743 struct gallivm_state *gallivm = base->gallivm;
1744 LLVMBuilderRef builder = base->gallivm->builder;
1745 LLVMValueRef val[4];
1746 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1747 unsigned chan;
1748 bool is_int8, is_int10;
1749
1750 /* Default is 0xf. Adjusted below depending on the format. */
1751 args->enabled_channels = 0xf; /* writemask */
1752
1753 /* Specify whether the EXEC mask represents the valid mask */
1754 args->valid_mask = 0;
1755
1756 /* Specify whether this is the last export */
1757 args->done = 0;
1758
1759 /* Specify the target we are exporting */
1760 args->target = target;
1761
1762 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1763 const struct si_shader_key *key = &ctx->shader->key;
1764 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1765 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1766
1767 assert(cbuf >= 0 && cbuf < 8);
1768 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1769 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1770 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1771 }
1772
1773 args->compr = false;
1774 args->out[0] = base->undef;
1775 args->out[1] = base->undef;
1776 args->out[2] = base->undef;
1777 args->out[3] = base->undef;
1778
1779 switch (spi_shader_col_format) {
1780 case V_028714_SPI_SHADER_ZERO:
1781 args->enabled_channels = 0; /* writemask */
1782 args->target = V_008DFC_SQ_EXP_NULL;
1783 break;
1784
1785 case V_028714_SPI_SHADER_32_R:
1786 args->enabled_channels = 1; /* writemask */
1787 args->out[0] = values[0];
1788 break;
1789
1790 case V_028714_SPI_SHADER_32_GR:
1791 args->enabled_channels = 0x3; /* writemask */
1792 args->out[0] = values[0];
1793 args->out[1] = values[1];
1794 break;
1795
1796 case V_028714_SPI_SHADER_32_AR:
1797 args->enabled_channels = 0x9; /* writemask */
1798 args->out[0] = values[0];
1799 args->out[3] = values[3];
1800 break;
1801
1802 case V_028714_SPI_SHADER_FP16_ABGR:
1803 args->compr = 1; /* COMPR flag */
1804
1805 for (chan = 0; chan < 2; chan++) {
1806 LLVMValueRef pack_args[2] = {
1807 values[2 * chan],
1808 values[2 * chan + 1]
1809 };
1810 LLVMValueRef packed;
1811
1812 packed = ac_emit_cvt_pkrtz_f16(&ctx->ac, pack_args);
1813 args->out[chan] =
1814 LLVMBuildBitCast(base->gallivm->builder,
1815 packed, ctx->f32, "");
1816 }
1817 break;
1818
1819 case V_028714_SPI_SHADER_UNORM16_ABGR:
1820 for (chan = 0; chan < 4; chan++) {
1821 val[chan] = ac_emit_clamp(&ctx->ac, values[chan]);
1822 val[chan] = LLVMBuildFMul(builder, val[chan],
1823 lp_build_const_float(gallivm, 65535), "");
1824 val[chan] = LLVMBuildFAdd(builder, val[chan],
1825 lp_build_const_float(gallivm, 0.5), "");
1826 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1827 ctx->i32, "");
1828 }
1829
1830 args->compr = 1; /* COMPR flag */
1831 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1832 si_llvm_pack_two_int16(gallivm, val));
1833 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1834 si_llvm_pack_two_int16(gallivm, val+2));
1835 break;
1836
1837 case V_028714_SPI_SHADER_SNORM16_ABGR:
1838 for (chan = 0; chan < 4; chan++) {
1839 /* Clamp between [-1, 1]. */
1840 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1841 values[chan],
1842 lp_build_const_float(gallivm, 1));
1843 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1844 val[chan],
1845 lp_build_const_float(gallivm, -1));
1846 /* Convert to a signed integer in [-32767, 32767]. */
1847 val[chan] = LLVMBuildFMul(builder, val[chan],
1848 lp_build_const_float(gallivm, 32767), "");
1849 /* If positive, add 0.5, else add -0.5. */
1850 val[chan] = LLVMBuildFAdd(builder, val[chan],
1851 LLVMBuildSelect(builder,
1852 LLVMBuildFCmp(builder, LLVMRealOGE,
1853 val[chan], base->zero, ""),
1854 lp_build_const_float(gallivm, 0.5),
1855 lp_build_const_float(gallivm, -0.5), ""), "");
1856 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1857 }
1858
1859 args->compr = 1; /* COMPR flag */
1860 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1861 si_llvm_pack_two_int32_as_int16(gallivm, val));
1862 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1863 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1864 break;
1865
1866 case V_028714_SPI_SHADER_UINT16_ABGR: {
1867 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1868 is_int8 ? 255 : is_int10 ? 1023 : 65535);
1869 LLVMValueRef max_alpha =
1870 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 3);
1871
1872 /* Clamp. */
1873 for (chan = 0; chan < 4; chan++) {
1874 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1875 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1876 val[chan],
1877 chan == 3 ? max_alpha : max_rgb);
1878 }
1879
1880 args->compr = 1; /* COMPR flag */
1881 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1882 si_llvm_pack_two_int16(gallivm, val));
1883 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1884 si_llvm_pack_two_int16(gallivm, val+2));
1885 break;
1886 }
1887
1888 case V_028714_SPI_SHADER_SINT16_ABGR: {
1889 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1890 is_int8 ? 127 : is_int10 ? 511 : 32767);
1891 LLVMValueRef min_rgb = lp_build_const_int32(gallivm,
1892 is_int8 ? -128 : is_int10 ? -512 : -32768);
1893 LLVMValueRef max_alpha =
1894 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 1);
1895 LLVMValueRef min_alpha =
1896 !is_int10 ? min_rgb : lp_build_const_int32(gallivm, -2);
1897
1898 /* Clamp. */
1899 for (chan = 0; chan < 4; chan++) {
1900 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1901 val[chan] = lp_build_emit_llvm_binary(bld_base,
1902 TGSI_OPCODE_IMIN,
1903 val[chan], chan == 3 ? max_alpha : max_rgb);
1904 val[chan] = lp_build_emit_llvm_binary(bld_base,
1905 TGSI_OPCODE_IMAX,
1906 val[chan], chan == 3 ? min_alpha : min_rgb);
1907 }
1908
1909 args->compr = 1; /* COMPR flag */
1910 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1911 si_llvm_pack_two_int32_as_int16(gallivm, val));
1912 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1913 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1914 break;
1915 }
1916
1917 case V_028714_SPI_SHADER_32_ABGR:
1918 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1919 break;
1920 }
1921 }
1922
1923 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1924 LLVMValueRef alpha)
1925 {
1926 struct si_shader_context *ctx = si_shader_context(bld_base);
1927 struct gallivm_state *gallivm = bld_base->base.gallivm;
1928
1929 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1930 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1931 SI_PARAM_ALPHA_REF);
1932
1933 LLVMValueRef alpha_pass =
1934 lp_build_cmp(&bld_base->base,
1935 ctx->shader->key.part.ps.epilog.alpha_func,
1936 alpha, alpha_ref);
1937 LLVMValueRef arg =
1938 lp_build_select(&bld_base->base,
1939 alpha_pass,
1940 lp_build_const_float(gallivm, 1.0f),
1941 lp_build_const_float(gallivm, -1.0f));
1942
1943 ac_emit_kill(&ctx->ac, arg);
1944 } else {
1945 ac_emit_kill(&ctx->ac, NULL);
1946 }
1947 }
1948
1949 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1950 LLVMValueRef alpha,
1951 unsigned samplemask_param)
1952 {
1953 struct si_shader_context *ctx = si_shader_context(bld_base);
1954 struct gallivm_state *gallivm = bld_base->base.gallivm;
1955 LLVMValueRef coverage;
1956
1957 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1958 coverage = LLVMGetParam(ctx->main_fn,
1959 samplemask_param);
1960 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1961
1962 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1963 ctx->i32,
1964 &coverage, 1, LP_FUNC_ATTR_READNONE);
1965
1966 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1967 ctx->f32, "");
1968
1969 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1970 lp_build_const_float(gallivm,
1971 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1972
1973 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1974 }
1975
1976 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1977 struct ac_export_args *pos, LLVMValueRef *out_elts)
1978 {
1979 struct si_shader_context *ctx = si_shader_context(bld_base);
1980 struct lp_build_context *base = &bld_base->base;
1981 unsigned reg_index;
1982 unsigned chan;
1983 unsigned const_chan;
1984 LLVMValueRef base_elt;
1985 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1986 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1987 SI_VS_CONST_CLIP_PLANES);
1988 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
1989
1990 for (reg_index = 0; reg_index < 2; reg_index ++) {
1991 struct ac_export_args *args = &pos[2 + reg_index];
1992
1993 args->out[0] =
1994 args->out[1] =
1995 args->out[2] =
1996 args->out[3] = lp_build_const_float(base->gallivm, 0.0f);
1997
1998 /* Compute dot products of position and user clip plane vectors */
1999 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2000 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2001 LLVMValueRef addr =
2002 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2003 const_chan) * 4, 0);
2004 base_elt = buffer_load_const(ctx, const_resource,
2005 addr);
2006 args->out[chan] =
2007 lp_build_add(base, args->out[chan],
2008 lp_build_mul(base, base_elt,
2009 out_elts[const_chan]));
2010 }
2011 }
2012
2013 args->enabled_channels = 0xf;
2014 args->valid_mask = 0;
2015 args->done = 0;
2016 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2017 args->compr = 0;
2018 }
2019 }
2020
2021 static void si_dump_streamout(struct pipe_stream_output_info *so)
2022 {
2023 unsigned i;
2024
2025 if (so->num_outputs)
2026 fprintf(stderr, "STREAMOUT\n");
2027
2028 for (i = 0; i < so->num_outputs; i++) {
2029 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2030 so->output[i].start_component;
2031 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2032 i, so->output[i].output_buffer,
2033 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2034 so->output[i].register_index,
2035 mask & 1 ? "x" : "",
2036 mask & 2 ? "y" : "",
2037 mask & 4 ? "z" : "",
2038 mask & 8 ? "w" : "");
2039 }
2040 }
2041
2042 static void emit_streamout_output(struct si_shader_context *ctx,
2043 LLVMValueRef const *so_buffers,
2044 LLVMValueRef const *so_write_offsets,
2045 struct pipe_stream_output *stream_out,
2046 struct si_shader_output_values *shader_out)
2047 {
2048 struct gallivm_state *gallivm = &ctx->gallivm;
2049 LLVMBuilderRef builder = gallivm->builder;
2050 unsigned buf_idx = stream_out->output_buffer;
2051 unsigned start = stream_out->start_component;
2052 unsigned num_comps = stream_out->num_components;
2053 LLVMValueRef out[4];
2054
2055 assert(num_comps && num_comps <= 4);
2056 if (!num_comps || num_comps > 4)
2057 return;
2058
2059 /* Load the output as int. */
2060 for (int j = 0; j < num_comps; j++) {
2061 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2062
2063 out[j] = LLVMBuildBitCast(builder,
2064 shader_out->values[start + j],
2065 ctx->i32, "");
2066 }
2067
2068 /* Pack the output. */
2069 LLVMValueRef vdata = NULL;
2070
2071 switch (num_comps) {
2072 case 1: /* as i32 */
2073 vdata = out[0];
2074 break;
2075 case 2: /* as v2i32 */
2076 case 3: /* as v4i32 (aligned to 4) */
2077 case 4: /* as v4i32 */
2078 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2079 for (int j = 0; j < num_comps; j++) {
2080 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2081 LLVMConstInt(ctx->i32, j, 0), "");
2082 }
2083 break;
2084 }
2085
2086 ac_build_tbuffer_store_dwords(&ctx->ac, so_buffers[buf_idx],
2087 vdata, num_comps,
2088 so_write_offsets[buf_idx],
2089 LLVMConstInt(ctx->i32, 0, 0),
2090 stream_out->dst_offset * 4);
2091 }
2092
2093 /**
2094 * Write streamout data to buffers for vertex stream @p stream (different
2095 * vertex streams can occur for GS copy shaders).
2096 */
2097 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2098 struct si_shader_output_values *outputs,
2099 unsigned noutput, unsigned stream)
2100 {
2101 struct si_shader_selector *sel = ctx->shader->selector;
2102 struct pipe_stream_output_info *so = &sel->so;
2103 struct gallivm_state *gallivm = &ctx->gallivm;
2104 LLVMBuilderRef builder = gallivm->builder;
2105 int i;
2106 struct lp_build_if_state if_ctx;
2107
2108 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2109 LLVMValueRef so_vtx_count =
2110 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2111
2112 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2113
2114 /* can_emit = tid < so_vtx_count; */
2115 LLVMValueRef can_emit =
2116 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2117
2118 /* Emit the streamout code conditionally. This actually avoids
2119 * out-of-bounds buffer access. The hw tells us via the SGPR
2120 * (so_vtx_count) which threads are allowed to emit streamout data. */
2121 lp_build_if(&if_ctx, gallivm, can_emit);
2122 {
2123 /* The buffer offset is computed as follows:
2124 * ByteOffset = streamout_offset[buffer_id]*4 +
2125 * (streamout_write_index + thread_id)*stride[buffer_id] +
2126 * attrib_offset
2127 */
2128
2129 LLVMValueRef so_write_index =
2130 LLVMGetParam(ctx->main_fn,
2131 ctx->param_streamout_write_index);
2132
2133 /* Compute (streamout_write_index + thread_id). */
2134 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2135
2136 /* Load the descriptor and compute the write offset for each
2137 * enabled buffer. */
2138 LLVMValueRef so_write_offset[4] = {};
2139 LLVMValueRef so_buffers[4];
2140 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2141 SI_PARAM_RW_BUFFERS);
2142
2143 for (i = 0; i < 4; i++) {
2144 if (!so->stride[i])
2145 continue;
2146
2147 LLVMValueRef offset = lp_build_const_int32(gallivm,
2148 SI_VS_STREAMOUT_BUF0 + i);
2149
2150 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2151
2152 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2153 ctx->param_streamout_offset[i]);
2154 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2155
2156 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2157 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2158 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2159 }
2160
2161 /* Write streamout data. */
2162 for (i = 0; i < so->num_outputs; i++) {
2163 unsigned reg = so->output[i].register_index;
2164
2165 if (reg >= noutput)
2166 continue;
2167
2168 if (stream != so->output[i].stream)
2169 continue;
2170
2171 emit_streamout_output(ctx, so_buffers, so_write_offset,
2172 &so->output[i], &outputs[reg]);
2173 }
2174 }
2175 lp_build_endif(&if_ctx);
2176 }
2177
2178
2179 /* Generate export instructions for hardware VS shader stage */
2180 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2181 struct si_shader_output_values *outputs,
2182 unsigned noutput)
2183 {
2184 struct si_shader_context *ctx = si_shader_context(bld_base);
2185 struct si_shader *shader = ctx->shader;
2186 struct lp_build_context *base = &bld_base->base;
2187 struct ac_export_args args, pos_args[4] = {};
2188 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2189 unsigned semantic_name, semantic_index;
2190 unsigned target;
2191 unsigned param_count = 0;
2192 unsigned pos_idx;
2193 int i;
2194
2195 for (i = 0; i < noutput; i++) {
2196 semantic_name = outputs[i].semantic_name;
2197 semantic_index = outputs[i].semantic_index;
2198 bool export_param = true;
2199
2200 switch (semantic_name) {
2201 case TGSI_SEMANTIC_POSITION: /* ignore these */
2202 case TGSI_SEMANTIC_PSIZE:
2203 case TGSI_SEMANTIC_CLIPVERTEX:
2204 case TGSI_SEMANTIC_EDGEFLAG:
2205 break;
2206 case TGSI_SEMANTIC_GENERIC:
2207 case TGSI_SEMANTIC_CLIPDIST:
2208 if (shader->key.opt.hw_vs.kill_outputs &
2209 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2210 export_param = false;
2211 break;
2212 default:
2213 if (shader->key.opt.hw_vs.kill_outputs2 &
2214 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2215 export_param = false;
2216 break;
2217 }
2218
2219 if (outputs[i].vertex_stream[0] != 0 &&
2220 outputs[i].vertex_stream[1] != 0 &&
2221 outputs[i].vertex_stream[2] != 0 &&
2222 outputs[i].vertex_stream[3] != 0)
2223 export_param = false;
2224
2225 handle_semantic:
2226 /* Select the correct target */
2227 switch(semantic_name) {
2228 case TGSI_SEMANTIC_PSIZE:
2229 psize_value = outputs[i].values[0];
2230 continue;
2231 case TGSI_SEMANTIC_EDGEFLAG:
2232 edgeflag_value = outputs[i].values[0];
2233 continue;
2234 case TGSI_SEMANTIC_LAYER:
2235 layer_value = outputs[i].values[0];
2236 semantic_name = TGSI_SEMANTIC_GENERIC;
2237 goto handle_semantic;
2238 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2239 viewport_index_value = outputs[i].values[0];
2240 semantic_name = TGSI_SEMANTIC_GENERIC;
2241 goto handle_semantic;
2242 case TGSI_SEMANTIC_POSITION:
2243 target = V_008DFC_SQ_EXP_POS;
2244 break;
2245 case TGSI_SEMANTIC_CLIPDIST:
2246 if (shader->key.opt.hw_vs.clip_disable) {
2247 semantic_name = TGSI_SEMANTIC_GENERIC;
2248 goto handle_semantic;
2249 }
2250 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2251 break;
2252 case TGSI_SEMANTIC_CLIPVERTEX:
2253 if (shader->key.opt.hw_vs.clip_disable)
2254 continue;
2255 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2256 continue;
2257 case TGSI_SEMANTIC_COLOR:
2258 case TGSI_SEMANTIC_BCOLOR:
2259 case TGSI_SEMANTIC_PRIMID:
2260 case TGSI_SEMANTIC_FOG:
2261 case TGSI_SEMANTIC_TEXCOORD:
2262 case TGSI_SEMANTIC_GENERIC:
2263 if (!export_param)
2264 continue;
2265 target = V_008DFC_SQ_EXP_PARAM + param_count;
2266 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2267 shader->info.vs_output_param_offset[i] = param_count;
2268 param_count++;
2269 break;
2270 default:
2271 target = 0;
2272 fprintf(stderr,
2273 "Warning: SI unhandled vs output type:%d\n",
2274 semantic_name);
2275 }
2276
2277 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2278
2279 if (target >= V_008DFC_SQ_EXP_POS &&
2280 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2281 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2282 &args, sizeof(args));
2283 } else {
2284 ac_emit_export(&ctx->ac, &args);
2285 }
2286
2287 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2288 semantic_name = TGSI_SEMANTIC_GENERIC;
2289 goto handle_semantic;
2290 }
2291 }
2292
2293 shader->info.nr_param_exports = param_count;
2294
2295 /* We need to add the position output manually if it's missing. */
2296 if (!pos_args[0].out[0]) {
2297 pos_args[0].enabled_channels = 0xf; /* writemask */
2298 pos_args[0].valid_mask = 0; /* EXEC mask */
2299 pos_args[0].done = 0; /* last export? */
2300 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2301 pos_args[0].compr = 0; /* COMPR flag */
2302 pos_args[0].out[0] = base->zero; /* X */
2303 pos_args[0].out[1] = base->zero; /* Y */
2304 pos_args[0].out[2] = base->zero; /* Z */
2305 pos_args[0].out[3] = base->one; /* W */
2306 }
2307
2308 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2309 if (shader->selector->info.writes_psize ||
2310 shader->selector->info.writes_edgeflag ||
2311 shader->selector->info.writes_viewport_index ||
2312 shader->selector->info.writes_layer) {
2313 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2314 (shader->selector->info.writes_edgeflag << 1) |
2315 (shader->selector->info.writes_layer << 2) |
2316 (shader->selector->info.writes_viewport_index << 3);
2317 pos_args[1].valid_mask = 0; /* EXEC mask */
2318 pos_args[1].done = 0; /* last export? */
2319 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2320 pos_args[1].compr = 0; /* COMPR flag */
2321 pos_args[1].out[0] = base->zero; /* X */
2322 pos_args[1].out[1] = base->zero; /* Y */
2323 pos_args[1].out[2] = base->zero; /* Z */
2324 pos_args[1].out[3] = base->zero; /* W */
2325
2326 if (shader->selector->info.writes_psize)
2327 pos_args[1].out[0] = psize_value;
2328
2329 if (shader->selector->info.writes_edgeflag) {
2330 /* The output is a float, but the hw expects an integer
2331 * with the first bit containing the edge flag. */
2332 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2333 edgeflag_value,
2334 ctx->i32, "");
2335 edgeflag_value = lp_build_min(&bld_base->int_bld,
2336 edgeflag_value,
2337 bld_base->int_bld.one);
2338
2339 /* The LLVM intrinsic expects a float. */
2340 pos_args[1].out[1] = LLVMBuildBitCast(base->gallivm->builder,
2341 edgeflag_value,
2342 ctx->f32, "");
2343 }
2344
2345 if (shader->selector->info.writes_layer)
2346 pos_args[1].out[2] = layer_value;
2347
2348 if (shader->selector->info.writes_viewport_index)
2349 pos_args[1].out[3] = viewport_index_value;
2350 }
2351
2352 for (i = 0; i < 4; i++)
2353 if (pos_args[i].out[0])
2354 shader->info.nr_pos_exports++;
2355
2356 pos_idx = 0;
2357 for (i = 0; i < 4; i++) {
2358 if (!pos_args[i].out[0])
2359 continue;
2360
2361 /* Specify the target we are exporting */
2362 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2363
2364 if (pos_idx == shader->info.nr_pos_exports)
2365 /* Specify that this is the last export */
2366 pos_args[i].done = 1;
2367
2368 ac_emit_export(&ctx->ac, &pos_args[i]);
2369 }
2370 }
2371
2372 /**
2373 * Forward all outputs from the vertex shader to the TES. This is only used
2374 * for the fixed function TCS.
2375 */
2376 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2377 {
2378 struct si_shader_context *ctx = si_shader_context(bld_base);
2379 struct gallivm_state *gallivm = bld_base->base.gallivm;
2380 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2381 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2382 uint64_t inputs;
2383
2384 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2385
2386 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2387 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2388 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2389
2390 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2391
2392 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2393 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2394 lds_vertex_stride, "");
2395 lds_base = get_tcs_in_current_patch_offset(ctx);
2396 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2397
2398 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2399 while (inputs) {
2400 unsigned i = u_bit_scan64(&inputs);
2401
2402 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2403 lp_build_const_int32(gallivm, 4 * i),
2404 "");
2405
2406 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2407 get_rel_patch_id(ctx),
2408 invocation_id,
2409 lp_build_const_int32(gallivm, i));
2410
2411 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2412 lds_ptr);
2413
2414 ac_build_tbuffer_store_dwords(&ctx->ac, buffer, value, 4, buffer_addr,
2415 buffer_offset, 0);
2416 }
2417 }
2418
2419 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2420 LLVMValueRef rel_patch_id,
2421 LLVMValueRef invocation_id,
2422 LLVMValueRef tcs_out_current_patch_data_offset)
2423 {
2424 struct si_shader_context *ctx = si_shader_context(bld_base);
2425 struct gallivm_state *gallivm = bld_base->base.gallivm;
2426 struct si_shader *shader = ctx->shader;
2427 unsigned tess_inner_index, tess_outer_index;
2428 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2429 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2430 unsigned stride, outer_comps, inner_comps, i;
2431 struct lp_build_if_state if_ctx, inner_if_ctx;
2432
2433 si_llvm_emit_barrier(NULL, bld_base, NULL);
2434
2435 /* Do this only for invocation 0, because the tess levels are per-patch,
2436 * not per-vertex.
2437 *
2438 * This can't jump, because invocation 0 executes this. It should
2439 * at least mask out the loads and stores for other invocations.
2440 */
2441 lp_build_if(&if_ctx, gallivm,
2442 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2443 invocation_id, bld_base->uint_bld.zero, ""));
2444
2445 /* Determine the layout of one tess factor element in the buffer. */
2446 switch (shader->key.part.tcs.epilog.prim_mode) {
2447 case PIPE_PRIM_LINES:
2448 stride = 2; /* 2 dwords, 1 vec2 store */
2449 outer_comps = 2;
2450 inner_comps = 0;
2451 break;
2452 case PIPE_PRIM_TRIANGLES:
2453 stride = 4; /* 4 dwords, 1 vec4 store */
2454 outer_comps = 3;
2455 inner_comps = 1;
2456 break;
2457 case PIPE_PRIM_QUADS:
2458 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2459 outer_comps = 4;
2460 inner_comps = 2;
2461 break;
2462 default:
2463 assert(0);
2464 return;
2465 }
2466
2467 /* Load tess_inner and tess_outer from LDS.
2468 * Any invocation can write them, so we can't get them from a temporary.
2469 */
2470 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2471 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2472
2473 lds_base = tcs_out_current_patch_data_offset;
2474 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2475 lp_build_const_int32(gallivm,
2476 tess_inner_index * 4), "");
2477 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2478 lp_build_const_int32(gallivm,
2479 tess_outer_index * 4), "");
2480
2481 for (i = 0; i < 4; i++) {
2482 inner[i] = LLVMGetUndef(ctx->i32);
2483 outer[i] = LLVMGetUndef(ctx->i32);
2484 }
2485
2486 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2487 /* For isolines, the hardware expects tess factors in the
2488 * reverse order from what GLSL / TGSI specify.
2489 */
2490 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2491 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2492 } else {
2493 for (i = 0; i < outer_comps; i++) {
2494 outer[i] = out[i] =
2495 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2496 }
2497 for (i = 0; i < inner_comps; i++) {
2498 inner[i] = out[outer_comps+i] =
2499 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2500 }
2501 }
2502
2503 /* Convert the outputs to vectors for stores. */
2504 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2505 vec1 = NULL;
2506
2507 if (stride > 4)
2508 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2509
2510 /* Get the buffer. */
2511 rw_buffers = LLVMGetParam(ctx->main_fn,
2512 SI_PARAM_RW_BUFFERS);
2513 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2514 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2515
2516 /* Get the offset. */
2517 tf_base = LLVMGetParam(ctx->main_fn,
2518 SI_PARAM_TESS_FACTOR_OFFSET);
2519 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2520 lp_build_const_int32(gallivm, 4 * stride), "");
2521
2522 lp_build_if(&inner_if_ctx, gallivm,
2523 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2524 rel_patch_id, bld_base->uint_bld.zero, ""));
2525
2526 /* Store the dynamic HS control word. */
2527 ac_build_tbuffer_store_dwords(&ctx->ac, buffer,
2528 lp_build_const_int32(gallivm, 0x80000000),
2529 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2530
2531 lp_build_endif(&inner_if_ctx);
2532
2533 /* Store the tessellation factors. */
2534 ac_build_tbuffer_store_dwords(&ctx->ac, buffer, vec0,
2535 MIN2(stride, 4), byteoffset, tf_base, 4);
2536 if (vec1)
2537 ac_build_tbuffer_store_dwords(&ctx->ac, buffer, vec1,
2538 stride - 4, byteoffset, tf_base, 20);
2539
2540 /* Store the tess factors into the offchip buffer if TES reads them. */
2541 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2542 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2543 LLVMValueRef tf_inner_offset;
2544 unsigned param_outer, param_inner;
2545
2546 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2547 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2548 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2549
2550 param_outer = si_shader_io_get_unique_index(
2551 TGSI_SEMANTIC_TESSOUTER, 0);
2552 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2553 LLVMConstInt(ctx->i32, param_outer, 0));
2554
2555 outer_vec = lp_build_gather_values(gallivm, outer,
2556 util_next_power_of_two(outer_comps));
2557
2558 ac_build_tbuffer_store_dwords(&ctx->ac, buf, outer_vec,
2559 outer_comps, tf_outer_offset,
2560 base, 0);
2561 if (inner_comps) {
2562 param_inner = si_shader_io_get_unique_index(
2563 TGSI_SEMANTIC_TESSINNER, 0);
2564 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2565 LLVMConstInt(ctx->i32, param_inner, 0));
2566
2567 inner_vec = inner_comps == 1 ? inner[0] :
2568 lp_build_gather_values(gallivm, inner, inner_comps);
2569 ac_build_tbuffer_store_dwords(&ctx->ac, buf, inner_vec,
2570 inner_comps, tf_inner_offset,
2571 base, 0);
2572 }
2573 }
2574
2575 lp_build_endif(&if_ctx);
2576 }
2577
2578 /* This only writes the tessellation factor levels. */
2579 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2580 {
2581 struct si_shader_context *ctx = si_shader_context(bld_base);
2582 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2583 LLVMValueRef offchip_soffset, offchip_layout;
2584
2585 si_copy_tcs_inputs(bld_base);
2586
2587 rel_patch_id = get_rel_patch_id(ctx);
2588 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2589 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2590
2591 /* Return epilog parameters from this function. */
2592 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2593 LLVMValueRef ret = ctx->return_value;
2594 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2595 unsigned vgpr;
2596
2597 /* RW_BUFFERS pointer */
2598 rw_buffers = LLVMGetParam(ctx->main_fn,
2599 SI_PARAM_RW_BUFFERS);
2600 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2601 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2602 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2603 bld_base->uint_bld.zero, "");
2604 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2605 bld_base->uint_bld.one, "");
2606 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2607 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2608
2609 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2610 offchip_layout = LLVMGetParam(ctx->main_fn,
2611 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2612 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2613 tf_soffset = LLVMGetParam(ctx->main_fn,
2614 SI_PARAM_TESS_FACTOR_OFFSET);
2615 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2616 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2617 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2618 SI_TCS_NUM_USER_SGPR, "");
2619 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2620 SI_TCS_NUM_USER_SGPR + 1, "");
2621
2622 /* VGPRs */
2623 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2624 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2625 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2626
2627 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2628 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2629 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2630 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2631 ctx->return_value = ret;
2632 }
2633
2634 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2635 {
2636 struct si_shader_context *ctx = si_shader_context(bld_base);
2637 struct si_shader *shader = ctx->shader;
2638 struct tgsi_shader_info *info = &shader->selector->info;
2639 struct gallivm_state *gallivm = bld_base->base.gallivm;
2640 unsigned i, chan;
2641 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2642 ctx->param_rel_auto_id);
2643 LLVMValueRef vertex_dw_stride =
2644 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2645 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2646 vertex_dw_stride, "");
2647
2648 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2649 * its inputs from it. */
2650 for (i = 0; i < info->num_outputs; i++) {
2651 LLVMValueRef *out_ptr = ctx->outputs[i];
2652 unsigned name = info->output_semantic_name[i];
2653 unsigned index = info->output_semantic_index[i];
2654 int param = si_shader_io_get_unique_index(name, index);
2655 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2656 lp_build_const_int32(gallivm, param * 4), "");
2657
2658 for (chan = 0; chan < 4; chan++) {
2659 lds_store(bld_base, chan, dw_addr,
2660 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2661 }
2662 }
2663 }
2664
2665 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2666 {
2667 struct si_shader_context *ctx = si_shader_context(bld_base);
2668 struct gallivm_state *gallivm = bld_base->base.gallivm;
2669 struct si_shader *es = ctx->shader;
2670 struct tgsi_shader_info *info = &es->selector->info;
2671 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2672 ctx->param_es2gs_offset);
2673 unsigned chan;
2674 int i;
2675
2676 for (i = 0; i < info->num_outputs; i++) {
2677 LLVMValueRef *out_ptr = ctx->outputs[i];
2678 int param_index;
2679
2680 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2681 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2682 continue;
2683
2684 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2685 info->output_semantic_index[i]);
2686
2687 for (chan = 0; chan < 4; chan++) {
2688 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2689 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2690
2691 ac_build_tbuffer_store(&ctx->ac,
2692 ctx->esgs_ring,
2693 out_val, 1,
2694 LLVMGetUndef(ctx->i32), soffset,
2695 (4 * param_index + chan) * 4,
2696 V_008F0C_BUF_DATA_FORMAT_32,
2697 V_008F0C_BUF_NUM_FORMAT_UINT,
2698 0, 0, 1, 1, 0);
2699 }
2700 }
2701 }
2702
2703 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2704 {
2705 struct si_shader_context *ctx = si_shader_context(bld_base);
2706
2707 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2708 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2709 }
2710
2711 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2712 {
2713 struct si_shader_context *ctx = si_shader_context(bld_base);
2714 struct gallivm_state *gallivm = bld_base->base.gallivm;
2715 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2716 struct si_shader_output_values *outputs = NULL;
2717 int i,j;
2718
2719 assert(!ctx->shader->is_gs_copy_shader);
2720
2721 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2722
2723 /* Vertex color clamping.
2724 *
2725 * This uses a state constant loaded in a user data SGPR and
2726 * an IF statement is added that clamps all colors if the constant
2727 * is true.
2728 */
2729 if (ctx->type == PIPE_SHADER_VERTEX) {
2730 struct lp_build_if_state if_ctx;
2731 LLVMValueRef cond = NULL;
2732 LLVMValueRef addr, val;
2733
2734 for (i = 0; i < info->num_outputs; i++) {
2735 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2736 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2737 continue;
2738
2739 /* We've found a color. */
2740 if (!cond) {
2741 /* The state is in the first bit of the user SGPR. */
2742 cond = LLVMGetParam(ctx->main_fn,
2743 SI_PARAM_VS_STATE_BITS);
2744 cond = LLVMBuildTrunc(gallivm->builder, cond,
2745 ctx->i1, "");
2746 lp_build_if(&if_ctx, gallivm, cond);
2747 }
2748
2749 for (j = 0; j < 4; j++) {
2750 addr = ctx->outputs[i][j];
2751 val = LLVMBuildLoad(gallivm->builder, addr, "");
2752 val = ac_emit_clamp(&ctx->ac, val);
2753 LLVMBuildStore(gallivm->builder, val, addr);
2754 }
2755 }
2756
2757 if (cond)
2758 lp_build_endif(&if_ctx);
2759 }
2760
2761 for (i = 0; i < info->num_outputs; i++) {
2762 outputs[i].semantic_name = info->output_semantic_name[i];
2763 outputs[i].semantic_index = info->output_semantic_index[i];
2764
2765 for (j = 0; j < 4; j++) {
2766 outputs[i].values[j] =
2767 LLVMBuildLoad(gallivm->builder,
2768 ctx->outputs[i][j],
2769 "");
2770 outputs[i].vertex_stream[j] =
2771 (info->output_streams[i] >> (2 * j)) & 3;
2772 }
2773
2774 }
2775
2776 /* Return the primitive ID from the LLVM function. */
2777 ctx->return_value =
2778 LLVMBuildInsertValue(gallivm->builder,
2779 ctx->return_value,
2780 bitcast(bld_base, TGSI_TYPE_FLOAT,
2781 get_primitive_id(bld_base, 0)),
2782 VS_EPILOG_PRIMID_LOC, "");
2783
2784 if (ctx->shader->selector->so.num_outputs)
2785 si_llvm_emit_streamout(ctx, outputs, i, 0);
2786 si_llvm_export_vs(bld_base, outputs, i);
2787 FREE(outputs);
2788 }
2789
2790 struct si_ps_exports {
2791 unsigned num;
2792 struct ac_export_args args[10];
2793 };
2794
2795 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2796 bool writes_samplemask)
2797 {
2798 if (writes_z) {
2799 /* Z needs 32 bits. */
2800 if (writes_samplemask)
2801 return V_028710_SPI_SHADER_32_ABGR;
2802 else if (writes_stencil)
2803 return V_028710_SPI_SHADER_32_GR;
2804 else
2805 return V_028710_SPI_SHADER_32_R;
2806 } else if (writes_stencil || writes_samplemask) {
2807 /* Both stencil and sample mask need only 16 bits. */
2808 return V_028710_SPI_SHADER_UINT16_ABGR;
2809 } else {
2810 return V_028710_SPI_SHADER_ZERO;
2811 }
2812 }
2813
2814 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2815 LLVMValueRef depth, LLVMValueRef stencil,
2816 LLVMValueRef samplemask, struct si_ps_exports *exp)
2817 {
2818 struct si_shader_context *ctx = si_shader_context(bld_base);
2819 struct lp_build_context *base = &bld_base->base;
2820 struct ac_export_args args;
2821 unsigned mask = 0;
2822 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2823 stencil != NULL,
2824 samplemask != NULL);
2825
2826 assert(depth || stencil || samplemask);
2827
2828 args.valid_mask = 1; /* whether the EXEC mask is valid */
2829 args.done = 1; /* DONE bit */
2830
2831 /* Specify the target we are exporting */
2832 args.target = V_008DFC_SQ_EXP_MRTZ;
2833
2834 args.compr = 0; /* COMP flag */
2835 args.out[0] = base->undef; /* R, depth */
2836 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2837 args.out[2] = base->undef; /* B, sample mask */
2838 args.out[3] = base->undef; /* A, alpha to mask */
2839
2840 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2841 assert(!depth);
2842 args.compr = 1; /* COMPR flag */
2843
2844 if (stencil) {
2845 /* Stencil should be in X[23:16]. */
2846 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2847 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2848 LLVMConstInt(ctx->i32, 16, 0), "");
2849 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2850 mask |= 0x3;
2851 }
2852 if (samplemask) {
2853 /* SampleMask should be in Y[15:0]. */
2854 args.out[1] = samplemask;
2855 mask |= 0xc;
2856 }
2857 } else {
2858 if (depth) {
2859 args.out[0] = depth;
2860 mask |= 0x1;
2861 }
2862 if (stencil) {
2863 args.out[1] = stencil;
2864 mask |= 0x2;
2865 }
2866 if (samplemask) {
2867 args.out[2] = samplemask;
2868 mask |= 0x4;
2869 }
2870 }
2871
2872 /* SI (except OLAND and HAINAN) has a bug that it only looks
2873 * at the X writemask component. */
2874 if (ctx->screen->b.chip_class == SI &&
2875 ctx->screen->b.family != CHIP_OLAND &&
2876 ctx->screen->b.family != CHIP_HAINAN)
2877 mask |= 0x1;
2878
2879 /* Specify which components to enable */
2880 args.enabled_channels = mask;
2881
2882 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2883 }
2884
2885 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2886 LLVMValueRef *color, unsigned index,
2887 unsigned samplemask_param,
2888 bool is_last, struct si_ps_exports *exp)
2889 {
2890 struct si_shader_context *ctx = si_shader_context(bld_base);
2891 struct lp_build_context *base = &bld_base->base;
2892 int i;
2893
2894 /* Clamp color */
2895 if (ctx->shader->key.part.ps.epilog.clamp_color)
2896 for (i = 0; i < 4; i++)
2897 color[i] = ac_emit_clamp(&ctx->ac, color[i]);
2898
2899 /* Alpha to one */
2900 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2901 color[3] = base->one;
2902
2903 /* Alpha test */
2904 if (index == 0 &&
2905 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2906 si_alpha_test(bld_base, color[3]);
2907
2908 /* Line & polygon smoothing */
2909 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2910 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2911 samplemask_param);
2912
2913 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2914 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2915 struct ac_export_args args[8];
2916 int c, last = -1;
2917
2918 /* Get the export arguments, also find out what the last one is. */
2919 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2920 si_llvm_init_export_args(bld_base, color,
2921 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2922 if (args[c].enabled_channels)
2923 last = c;
2924 }
2925
2926 /* Emit all exports. */
2927 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2928 if (is_last && last == c) {
2929 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2930 args[c].done = 1; /* DONE bit */
2931 } else if (!args[c].enabled_channels)
2932 continue; /* unnecessary NULL export */
2933
2934 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2935 }
2936 } else {
2937 struct ac_export_args args;
2938
2939 /* Export */
2940 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2941 &args);
2942 if (is_last) {
2943 args.valid_mask = 1; /* whether the EXEC mask is valid */
2944 args.done = 1; /* DONE bit */
2945 } else if (!args.enabled_channels)
2946 return; /* unnecessary NULL export */
2947
2948 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2949 }
2950 }
2951
2952 static void si_emit_ps_exports(struct si_shader_context *ctx,
2953 struct si_ps_exports *exp)
2954 {
2955 for (unsigned i = 0; i < exp->num; i++)
2956 ac_emit_export(&ctx->ac, &exp->args[i]);
2957 }
2958
2959 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2960 {
2961 struct si_shader_context *ctx = si_shader_context(bld_base);
2962 struct lp_build_context *base = &bld_base->base;
2963 struct ac_export_args args;
2964
2965 args.enabled_channels = 0x0; /* enabled channels */
2966 args.valid_mask = 1; /* whether the EXEC mask is valid */
2967 args.done = 1; /* DONE bit */
2968 args.target = V_008DFC_SQ_EXP_NULL;
2969 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
2970 args.out[0] = base->undef; /* R */
2971 args.out[1] = base->undef; /* G */
2972 args.out[2] = base->undef; /* B */
2973 args.out[3] = base->undef; /* A */
2974
2975 ac_emit_export(&ctx->ac, &args);
2976 }
2977
2978 /**
2979 * Return PS outputs in this order:
2980 *
2981 * v[0:3] = color0.xyzw
2982 * v[4:7] = color1.xyzw
2983 * ...
2984 * vN+0 = Depth
2985 * vN+1 = Stencil
2986 * vN+2 = SampleMask
2987 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2988 *
2989 * The alpha-ref SGPR is returned via its original location.
2990 */
2991 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2992 {
2993 struct si_shader_context *ctx = si_shader_context(bld_base);
2994 struct si_shader *shader = ctx->shader;
2995 struct lp_build_context *base = &bld_base->base;
2996 struct tgsi_shader_info *info = &shader->selector->info;
2997 LLVMBuilderRef builder = base->gallivm->builder;
2998 unsigned i, j, first_vgpr, vgpr;
2999
3000 LLVMValueRef color[8][4] = {};
3001 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3002 LLVMValueRef ret;
3003
3004 /* Read the output values. */
3005 for (i = 0; i < info->num_outputs; i++) {
3006 unsigned semantic_name = info->output_semantic_name[i];
3007 unsigned semantic_index = info->output_semantic_index[i];
3008
3009 switch (semantic_name) {
3010 case TGSI_SEMANTIC_COLOR:
3011 assert(semantic_index < 8);
3012 for (j = 0; j < 4; j++) {
3013 LLVMValueRef ptr = ctx->outputs[i][j];
3014 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3015 color[semantic_index][j] = result;
3016 }
3017 break;
3018 case TGSI_SEMANTIC_POSITION:
3019 depth = LLVMBuildLoad(builder,
3020 ctx->outputs[i][2], "");
3021 break;
3022 case TGSI_SEMANTIC_STENCIL:
3023 stencil = LLVMBuildLoad(builder,
3024 ctx->outputs[i][1], "");
3025 break;
3026 case TGSI_SEMANTIC_SAMPLEMASK:
3027 samplemask = LLVMBuildLoad(builder,
3028 ctx->outputs[i][0], "");
3029 break;
3030 default:
3031 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3032 semantic_name);
3033 }
3034 }
3035
3036 /* Fill the return structure. */
3037 ret = ctx->return_value;
3038
3039 /* Set SGPRs. */
3040 ret = LLVMBuildInsertValue(builder, ret,
3041 bitcast(bld_base, TGSI_TYPE_SIGNED,
3042 LLVMGetParam(ctx->main_fn,
3043 SI_PARAM_ALPHA_REF)),
3044 SI_SGPR_ALPHA_REF, "");
3045
3046 /* Set VGPRs */
3047 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3048 for (i = 0; i < ARRAY_SIZE(color); i++) {
3049 if (!color[i][0])
3050 continue;
3051
3052 for (j = 0; j < 4; j++)
3053 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3054 }
3055 if (depth)
3056 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3057 if (stencil)
3058 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3059 if (samplemask)
3060 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3061
3062 /* Add the input sample mask for smoothing at the end. */
3063 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3064 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3065 ret = LLVMBuildInsertValue(builder, ret,
3066 LLVMGetParam(ctx->main_fn,
3067 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3068
3069 ctx->return_value = ret;
3070 }
3071
3072 /**
3073 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3074 * buffer in number of elements and return it as an i32.
3075 */
3076 static LLVMValueRef get_buffer_size(
3077 struct lp_build_tgsi_context *bld_base,
3078 LLVMValueRef descriptor)
3079 {
3080 struct si_shader_context *ctx = si_shader_context(bld_base);
3081 struct gallivm_state *gallivm = bld_base->base.gallivm;
3082 LLVMBuilderRef builder = gallivm->builder;
3083 LLVMValueRef size =
3084 LLVMBuildExtractElement(builder, descriptor,
3085 lp_build_const_int32(gallivm, 2), "");
3086
3087 if (ctx->screen->b.chip_class >= VI) {
3088 /* On VI, the descriptor contains the size in bytes,
3089 * but TXQ must return the size in elements.
3090 * The stride is always non-zero for resources using TXQ.
3091 */
3092 LLVMValueRef stride =
3093 LLVMBuildExtractElement(builder, descriptor,
3094 lp_build_const_int32(gallivm, 1), "");
3095 stride = LLVMBuildLShr(builder, stride,
3096 lp_build_const_int32(gallivm, 16), "");
3097 stride = LLVMBuildAnd(builder, stride,
3098 lp_build_const_int32(gallivm, 0x3FFF), "");
3099
3100 size = LLVMBuildUDiv(builder, size, stride, "");
3101 }
3102
3103 return size;
3104 }
3105
3106 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3107 struct lp_build_tgsi_context *bld_base,
3108 struct lp_build_emit_data *emit_data);
3109
3110 /* Prevent optimizations (at least of memory accesses) across the current
3111 * point in the program by emitting empty inline assembly that is marked as
3112 * having side effects.
3113 */
3114 #if 0 /* unused currently */
3115 static void emit_optimization_barrier(struct si_shader_context *ctx)
3116 {
3117 LLVMBuilderRef builder = ctx->gallivm.builder;
3118 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3119 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3120 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3121 }
3122 #endif
3123
3124 /* Combine these with & instead of |. */
3125 #define NOOP_WAITCNT 0xf7f
3126 #define LGKM_CNT 0x07f
3127 #define VM_CNT 0xf70
3128
3129 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3130 {
3131 struct gallivm_state *gallivm = &ctx->gallivm;
3132 LLVMBuilderRef builder = gallivm->builder;
3133 LLVMValueRef args[1] = {
3134 lp_build_const_int32(gallivm, simm16)
3135 };
3136 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3137 ctx->voidt, args, 1, 0);
3138 }
3139
3140 static void membar_emit(
3141 const struct lp_build_tgsi_action *action,
3142 struct lp_build_tgsi_context *bld_base,
3143 struct lp_build_emit_data *emit_data)
3144 {
3145 struct si_shader_context *ctx = si_shader_context(bld_base);
3146 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3147 unsigned flags = LLVMConstIntGetZExtValue(src0);
3148 unsigned waitcnt = NOOP_WAITCNT;
3149
3150 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3151 waitcnt &= VM_CNT & LGKM_CNT;
3152
3153 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3154 TGSI_MEMBAR_SHADER_BUFFER |
3155 TGSI_MEMBAR_SHADER_IMAGE))
3156 waitcnt &= VM_CNT;
3157
3158 if (flags & TGSI_MEMBAR_SHARED)
3159 waitcnt &= LGKM_CNT;
3160
3161 if (waitcnt != NOOP_WAITCNT)
3162 emit_waitcnt(ctx, waitcnt);
3163 }
3164
3165 static LLVMValueRef
3166 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3167 const struct tgsi_full_src_register *reg)
3168 {
3169 LLVMValueRef index;
3170 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3171 SI_PARAM_SHADER_BUFFERS);
3172
3173 if (!reg->Register.Indirect)
3174 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3175 else
3176 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3177 reg->Register.Index,
3178 SI_NUM_SHADER_BUFFERS);
3179
3180 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3181 }
3182
3183 static bool tgsi_is_array_sampler(unsigned target)
3184 {
3185 return target == TGSI_TEXTURE_1D_ARRAY ||
3186 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3187 target == TGSI_TEXTURE_2D_ARRAY ||
3188 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3189 target == TGSI_TEXTURE_CUBE_ARRAY ||
3190 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3191 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3192 }
3193
3194 static bool tgsi_is_array_image(unsigned target)
3195 {
3196 return target == TGSI_TEXTURE_3D ||
3197 target == TGSI_TEXTURE_CUBE ||
3198 target == TGSI_TEXTURE_1D_ARRAY ||
3199 target == TGSI_TEXTURE_2D_ARRAY ||
3200 target == TGSI_TEXTURE_CUBE_ARRAY ||
3201 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3202 }
3203
3204 /**
3205 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3206 *
3207 * At least on Tonga, executing image stores on images with DCC enabled and
3208 * non-trivial can eventually lead to lockups. This can occur when an
3209 * application binds an image as read-only but then uses a shader that writes
3210 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3211 * program termination) in this case, but it doesn't cost much to be a bit
3212 * nicer: disabling DCC in the shader still leads to undefined results but
3213 * avoids the lockup.
3214 */
3215 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3216 LLVMValueRef rsrc)
3217 {
3218 if (ctx->screen->b.chip_class <= CIK) {
3219 return rsrc;
3220 } else {
3221 LLVMBuilderRef builder = ctx->gallivm.builder;
3222 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3223 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3224 LLVMValueRef tmp;
3225
3226 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3227 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3228 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3229 }
3230 }
3231
3232 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3233 {
3234 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3235 CONST_ADDR_SPACE);
3236 }
3237
3238 /**
3239 * Load the resource descriptor for \p image.
3240 */
3241 static void
3242 image_fetch_rsrc(
3243 struct lp_build_tgsi_context *bld_base,
3244 const struct tgsi_full_src_register *image,
3245 bool is_store, unsigned target,
3246 LLVMValueRef *rsrc)
3247 {
3248 struct si_shader_context *ctx = si_shader_context(bld_base);
3249 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3250 SI_PARAM_IMAGES);
3251 LLVMValueRef index, tmp;
3252 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3253
3254 assert(image->Register.File == TGSI_FILE_IMAGE);
3255
3256 if (!image->Register.Indirect) {
3257 const struct tgsi_shader_info *info = bld_base->info;
3258 unsigned images_writemask = info->images_store |
3259 info->images_atomic;
3260
3261 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3262
3263 if (images_writemask & (1 << image->Register.Index) &&
3264 target != TGSI_TEXTURE_BUFFER)
3265 dcc_off = true;
3266 } else {
3267 /* From the GL_ARB_shader_image_load_store extension spec:
3268 *
3269 * If a shader performs an image load, store, or atomic
3270 * operation using an image variable declared as an array,
3271 * and if the index used to select an individual element is
3272 * negative or greater than or equal to the size of the
3273 * array, the results of the operation are undefined but may
3274 * not lead to termination.
3275 */
3276 index = get_bounded_indirect_index(ctx, &image->Indirect,
3277 image->Register.Index,
3278 SI_NUM_IMAGES);
3279 }
3280
3281 if (target == TGSI_TEXTURE_BUFFER) {
3282 LLVMBuilderRef builder = ctx->gallivm.builder;
3283
3284 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3285 const_array(ctx->v4i32, 0), "");
3286 index = LLVMBuildMul(builder, index,
3287 LLVMConstInt(ctx->i32, 2, 0), "");
3288 index = LLVMBuildAdd(builder, index,
3289 LLVMConstInt(ctx->i32, 1, 0), "");
3290 *rsrc = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3291 return;
3292 }
3293
3294 tmp = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3295 if (dcc_off)
3296 tmp = force_dcc_off(ctx, tmp);
3297 *rsrc = tmp;
3298 }
3299
3300 static LLVMValueRef image_fetch_coords(
3301 struct lp_build_tgsi_context *bld_base,
3302 const struct tgsi_full_instruction *inst,
3303 unsigned src)
3304 {
3305 struct gallivm_state *gallivm = bld_base->base.gallivm;
3306 LLVMBuilderRef builder = gallivm->builder;
3307 unsigned target = inst->Memory.Texture;
3308 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3309 LLVMValueRef coords[4];
3310 LLVMValueRef tmp;
3311 int chan;
3312
3313 for (chan = 0; chan < num_coords; ++chan) {
3314 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3315 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3316 coords[chan] = tmp;
3317 }
3318
3319 if (num_coords == 1)
3320 return coords[0];
3321
3322 if (num_coords == 3) {
3323 /* LLVM has difficulties lowering 3-element vectors. */
3324 coords[3] = bld_base->uint_bld.undef;
3325 num_coords = 4;
3326 }
3327
3328 return lp_build_gather_values(gallivm, coords, num_coords);
3329 }
3330
3331 /**
3332 * Append the extra mode bits that are used by image load and store.
3333 */
3334 static void image_append_args(
3335 struct si_shader_context *ctx,
3336 struct lp_build_emit_data * emit_data,
3337 unsigned target,
3338 bool atomic,
3339 bool force_glc)
3340 {
3341 const struct tgsi_full_instruction *inst = emit_data->inst;
3342 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3343 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3344 LLVMValueRef r128 = i1false;
3345 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3346 LLVMValueRef glc =
3347 force_glc ||
3348 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3349 i1true : i1false;
3350 LLVMValueRef slc = i1false;
3351 LLVMValueRef lwe = i1false;
3352
3353 if (atomic || (HAVE_LLVM <= 0x0309)) {
3354 emit_data->args[emit_data->arg_count++] = r128;
3355 emit_data->args[emit_data->arg_count++] = da;
3356 if (!atomic) {
3357 emit_data->args[emit_data->arg_count++] = glc;
3358 }
3359 emit_data->args[emit_data->arg_count++] = slc;
3360 return;
3361 }
3362
3363 /* HAVE_LLVM >= 0x0400 */
3364 emit_data->args[emit_data->arg_count++] = glc;
3365 emit_data->args[emit_data->arg_count++] = slc;
3366 emit_data->args[emit_data->arg_count++] = lwe;
3367 emit_data->args[emit_data->arg_count++] = da;
3368 }
3369
3370 /**
3371 * Append the resource and indexing arguments for buffer intrinsics.
3372 *
3373 * \param rsrc the v4i32 buffer resource
3374 * \param index index into the buffer (stride-based)
3375 * \param offset byte offset into the buffer
3376 */
3377 static void buffer_append_args(
3378 struct si_shader_context *ctx,
3379 struct lp_build_emit_data *emit_data,
3380 LLVMValueRef rsrc,
3381 LLVMValueRef index,
3382 LLVMValueRef offset,
3383 bool atomic,
3384 bool force_glc)
3385 {
3386 const struct tgsi_full_instruction *inst = emit_data->inst;
3387 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3388 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3389
3390 emit_data->args[emit_data->arg_count++] = rsrc;
3391 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3392 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3393 if (!atomic) {
3394 emit_data->args[emit_data->arg_count++] =
3395 force_glc ||
3396 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3397 i1true : i1false; /* glc */
3398 }
3399 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3400 }
3401
3402 static void load_fetch_args(
3403 struct lp_build_tgsi_context * bld_base,
3404 struct lp_build_emit_data * emit_data)
3405 {
3406 struct si_shader_context *ctx = si_shader_context(bld_base);
3407 struct gallivm_state *gallivm = bld_base->base.gallivm;
3408 const struct tgsi_full_instruction * inst = emit_data->inst;
3409 unsigned target = inst->Memory.Texture;
3410 LLVMValueRef rsrc;
3411
3412 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3413
3414 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3415 LLVMBuilderRef builder = gallivm->builder;
3416 LLVMValueRef offset;
3417 LLVMValueRef tmp;
3418
3419 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3420
3421 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3422 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3423
3424 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3425 offset, false, false);
3426 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3427 LLVMValueRef coords;
3428
3429 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3430 coords = image_fetch_coords(bld_base, inst, 1);
3431
3432 if (target == TGSI_TEXTURE_BUFFER) {
3433 buffer_append_args(ctx, emit_data, rsrc, coords,
3434 bld_base->uint_bld.zero, false, false);
3435 } else {
3436 emit_data->args[0] = coords;
3437 emit_data->args[1] = rsrc;
3438 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3439 emit_data->arg_count = 3;
3440
3441 image_append_args(ctx, emit_data, target, false, false);
3442 }
3443 }
3444 }
3445
3446 static void load_emit_buffer(struct si_shader_context *ctx,
3447 struct lp_build_emit_data *emit_data)
3448 {
3449 const struct tgsi_full_instruction *inst = emit_data->inst;
3450 struct gallivm_state *gallivm = &ctx->gallivm;
3451 LLVMBuilderRef builder = gallivm->builder;
3452 uint writemask = inst->Dst[0].Register.WriteMask;
3453 uint count = util_last_bit(writemask);
3454 const char *intrinsic_name;
3455 LLVMTypeRef dst_type;
3456
3457 switch (count) {
3458 case 1:
3459 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3460 dst_type = ctx->f32;
3461 break;
3462 case 2:
3463 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3464 dst_type = LLVMVectorType(ctx->f32, 2);
3465 break;
3466 default: // 3 & 4
3467 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3468 dst_type = ctx->v4f32;
3469 count = 4;
3470 }
3471
3472 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3473 builder, intrinsic_name, dst_type,
3474 emit_data->args, emit_data->arg_count,
3475 LP_FUNC_ATTR_READONLY);
3476 }
3477
3478 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3479 const struct tgsi_full_instruction *inst,
3480 LLVMTypeRef type, int arg)
3481 {
3482 struct gallivm_state *gallivm = &ctx->gallivm;
3483 LLVMBuilderRef builder = gallivm->builder;
3484 LLVMValueRef offset, ptr;
3485 int addr_space;
3486
3487 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3488 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3489
3490 ptr = ctx->shared_memory;
3491 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3492 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3493 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3494
3495 return ptr;
3496 }
3497
3498 static void load_emit_memory(
3499 struct si_shader_context *ctx,
3500 struct lp_build_emit_data *emit_data)
3501 {
3502 const struct tgsi_full_instruction *inst = emit_data->inst;
3503 struct lp_build_context *base = &ctx->bld_base.base;
3504 struct gallivm_state *gallivm = &ctx->gallivm;
3505 LLVMBuilderRef builder = gallivm->builder;
3506 unsigned writemask = inst->Dst[0].Register.WriteMask;
3507 LLVMValueRef channels[4], ptr, derived_ptr, index;
3508 int chan;
3509
3510 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3511
3512 for (chan = 0; chan < 4; ++chan) {
3513 if (!(writemask & (1 << chan))) {
3514 channels[chan] = LLVMGetUndef(base->elem_type);
3515 continue;
3516 }
3517
3518 index = lp_build_const_int32(gallivm, chan);
3519 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3520 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3521 }
3522 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3523 }
3524
3525 static void get_image_intr_name(const char *base_name,
3526 LLVMTypeRef data_type,
3527 LLVMTypeRef coords_type,
3528 LLVMTypeRef rsrc_type,
3529 char *out_name, unsigned out_len)
3530 {
3531 char coords_type_name[8];
3532
3533 ac_build_type_name_for_intr(coords_type, coords_type_name,
3534 sizeof(coords_type_name));
3535
3536 if (HAVE_LLVM <= 0x0309) {
3537 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3538 } else {
3539 char data_type_name[8];
3540 char rsrc_type_name[8];
3541
3542 ac_build_type_name_for_intr(data_type, data_type_name,
3543 sizeof(data_type_name));
3544 ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
3545 sizeof(rsrc_type_name));
3546 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3547 data_type_name, coords_type_name, rsrc_type_name);
3548 }
3549 }
3550
3551 static void load_emit(
3552 const struct lp_build_tgsi_action *action,
3553 struct lp_build_tgsi_context *bld_base,
3554 struct lp_build_emit_data *emit_data)
3555 {
3556 struct si_shader_context *ctx = si_shader_context(bld_base);
3557 struct gallivm_state *gallivm = bld_base->base.gallivm;
3558 LLVMBuilderRef builder = gallivm->builder;
3559 const struct tgsi_full_instruction * inst = emit_data->inst;
3560 char intrinsic_name[64];
3561
3562 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3563 load_emit_memory(ctx, emit_data);
3564 return;
3565 }
3566
3567 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3568 emit_waitcnt(ctx, VM_CNT);
3569
3570 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3571 load_emit_buffer(ctx, emit_data);
3572 return;
3573 }
3574
3575 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3576 emit_data->output[emit_data->chan] =
3577 lp_build_intrinsic(
3578 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3579 emit_data->args, emit_data->arg_count,
3580 LP_FUNC_ATTR_READONLY);
3581 } else {
3582 get_image_intr_name("llvm.amdgcn.image.load",
3583 emit_data->dst_type, /* vdata */
3584 LLVMTypeOf(emit_data->args[0]), /* coords */
3585 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3586 intrinsic_name, sizeof(intrinsic_name));
3587
3588 emit_data->output[emit_data->chan] =
3589 lp_build_intrinsic(
3590 builder, intrinsic_name, emit_data->dst_type,
3591 emit_data->args, emit_data->arg_count,
3592 LP_FUNC_ATTR_READONLY);
3593 }
3594 }
3595
3596 static void store_fetch_args(
3597 struct lp_build_tgsi_context * bld_base,
3598 struct lp_build_emit_data * emit_data)
3599 {
3600 struct si_shader_context *ctx = si_shader_context(bld_base);
3601 struct gallivm_state *gallivm = bld_base->base.gallivm;
3602 LLVMBuilderRef builder = gallivm->builder;
3603 const struct tgsi_full_instruction * inst = emit_data->inst;
3604 struct tgsi_full_src_register memory;
3605 LLVMValueRef chans[4];
3606 LLVMValueRef data;
3607 LLVMValueRef rsrc;
3608 unsigned chan;
3609
3610 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3611
3612 for (chan = 0; chan < 4; ++chan) {
3613 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3614 }
3615 data = lp_build_gather_values(gallivm, chans, 4);
3616
3617 emit_data->args[emit_data->arg_count++] = data;
3618
3619 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3620
3621 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3622 LLVMValueRef offset;
3623 LLVMValueRef tmp;
3624
3625 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3626
3627 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3628 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3629
3630 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3631 offset, false, false);
3632 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3633 unsigned target = inst->Memory.Texture;
3634 LLVMValueRef coords;
3635
3636 /* 8bit/16bit TC L1 write corruption bug on SI.
3637 * All store opcodes not aligned to a dword are affected.
3638 *
3639 * The only way to get unaligned stores in radeonsi is through
3640 * shader images.
3641 */
3642 bool force_glc = ctx->screen->b.chip_class == SI;
3643
3644 coords = image_fetch_coords(bld_base, inst, 0);
3645
3646 if (target == TGSI_TEXTURE_BUFFER) {
3647 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3648 buffer_append_args(ctx, emit_data, rsrc, coords,
3649 bld_base->uint_bld.zero, false, force_glc);
3650 } else {
3651 emit_data->args[1] = coords;
3652 image_fetch_rsrc(bld_base, &memory, true, target,
3653 &emit_data->args[2]);
3654 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3655 emit_data->arg_count = 4;
3656
3657 image_append_args(ctx, emit_data, target, false, force_glc);
3658 }
3659 }
3660 }
3661
3662 static void store_emit_buffer(
3663 struct si_shader_context *ctx,
3664 struct lp_build_emit_data *emit_data)
3665 {
3666 const struct tgsi_full_instruction *inst = emit_data->inst;
3667 struct gallivm_state *gallivm = &ctx->gallivm;
3668 LLVMBuilderRef builder = gallivm->builder;
3669 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
3670 LLVMValueRef base_data = emit_data->args[0];
3671 LLVMValueRef base_offset = emit_data->args[3];
3672 unsigned writemask = inst->Dst[0].Register.WriteMask;
3673
3674 while (writemask) {
3675 int start, count;
3676 const char *intrinsic_name;
3677 LLVMValueRef data;
3678 LLVMValueRef offset;
3679 LLVMValueRef tmp;
3680
3681 u_bit_scan_consecutive_range(&writemask, &start, &count);
3682
3683 /* Due to an LLVM limitation, split 3-element writes
3684 * into a 2-element and a 1-element write. */
3685 if (count == 3) {
3686 writemask |= 1 << (start + 2);
3687 count = 2;
3688 }
3689
3690 if (count == 4) {
3691 data = base_data;
3692 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3693 } else if (count == 2) {
3694 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3695
3696 tmp = LLVMBuildExtractElement(
3697 builder, base_data,
3698 lp_build_const_int32(gallivm, start), "");
3699 data = LLVMBuildInsertElement(
3700 builder, LLVMGetUndef(v2f32), tmp,
3701 uint_bld->zero, "");
3702
3703 tmp = LLVMBuildExtractElement(
3704 builder, base_data,
3705 lp_build_const_int32(gallivm, start + 1), "");
3706 data = LLVMBuildInsertElement(
3707 builder, data, tmp, uint_bld->one, "");
3708
3709 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3710 } else {
3711 assert(count == 1);
3712 data = LLVMBuildExtractElement(
3713 builder, base_data,
3714 lp_build_const_int32(gallivm, start), "");
3715 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3716 }
3717
3718 offset = base_offset;
3719 if (start != 0) {
3720 offset = LLVMBuildAdd(
3721 builder, offset,
3722 lp_build_const_int32(gallivm, start * 4), "");
3723 }
3724
3725 emit_data->args[0] = data;
3726 emit_data->args[3] = offset;
3727
3728 lp_build_intrinsic(
3729 builder, intrinsic_name, emit_data->dst_type,
3730 emit_data->args, emit_data->arg_count, 0);
3731 }
3732 }
3733
3734 static void store_emit_memory(
3735 struct si_shader_context *ctx,
3736 struct lp_build_emit_data *emit_data)
3737 {
3738 const struct tgsi_full_instruction *inst = emit_data->inst;
3739 struct gallivm_state *gallivm = &ctx->gallivm;
3740 struct lp_build_context *base = &ctx->bld_base.base;
3741 LLVMBuilderRef builder = gallivm->builder;
3742 unsigned writemask = inst->Dst[0].Register.WriteMask;
3743 LLVMValueRef ptr, derived_ptr, data, index;
3744 int chan;
3745
3746 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3747
3748 for (chan = 0; chan < 4; ++chan) {
3749 if (!(writemask & (1 << chan))) {
3750 continue;
3751 }
3752 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3753 index = lp_build_const_int32(gallivm, chan);
3754 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3755 LLVMBuildStore(builder, data, derived_ptr);
3756 }
3757 }
3758
3759 static void store_emit(
3760 const struct lp_build_tgsi_action *action,
3761 struct lp_build_tgsi_context *bld_base,
3762 struct lp_build_emit_data *emit_data)
3763 {
3764 struct si_shader_context *ctx = si_shader_context(bld_base);
3765 struct gallivm_state *gallivm = bld_base->base.gallivm;
3766 LLVMBuilderRef builder = gallivm->builder;
3767 const struct tgsi_full_instruction * inst = emit_data->inst;
3768 unsigned target = inst->Memory.Texture;
3769 char intrinsic_name[64];
3770
3771 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3772 store_emit_memory(ctx, emit_data);
3773 return;
3774 }
3775
3776 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3777 emit_waitcnt(ctx, VM_CNT);
3778
3779 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3780 store_emit_buffer(ctx, emit_data);
3781 return;
3782 }
3783
3784 if (target == TGSI_TEXTURE_BUFFER) {
3785 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3786 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3787 emit_data->dst_type, emit_data->args,
3788 emit_data->arg_count, 0);
3789 } else {
3790 get_image_intr_name("llvm.amdgcn.image.store",
3791 LLVMTypeOf(emit_data->args[0]), /* vdata */
3792 LLVMTypeOf(emit_data->args[1]), /* coords */
3793 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3794 intrinsic_name, sizeof(intrinsic_name));
3795
3796 emit_data->output[emit_data->chan] =
3797 lp_build_intrinsic(
3798 builder, intrinsic_name, emit_data->dst_type,
3799 emit_data->args, emit_data->arg_count, 0);
3800 }
3801 }
3802
3803 static void atomic_fetch_args(
3804 struct lp_build_tgsi_context * bld_base,
3805 struct lp_build_emit_data * emit_data)
3806 {
3807 struct si_shader_context *ctx = si_shader_context(bld_base);
3808 struct gallivm_state *gallivm = bld_base->base.gallivm;
3809 LLVMBuilderRef builder = gallivm->builder;
3810 const struct tgsi_full_instruction * inst = emit_data->inst;
3811 LLVMValueRef data1, data2;
3812 LLVMValueRef rsrc;
3813 LLVMValueRef tmp;
3814
3815 emit_data->dst_type = bld_base->base.elem_type;
3816
3817 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3818 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3819
3820 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3821 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3822 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3823 }
3824
3825 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3826 * of arguments, which is reversed relative to TGSI (and GLSL)
3827 */
3828 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3829 emit_data->args[emit_data->arg_count++] = data2;
3830 emit_data->args[emit_data->arg_count++] = data1;
3831
3832 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3833 LLVMValueRef offset;
3834
3835 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3836
3837 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3838 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3839
3840 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3841 offset, true, false);
3842 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3843 unsigned target = inst->Memory.Texture;
3844 LLVMValueRef coords;
3845
3846 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3847 coords = image_fetch_coords(bld_base, inst, 1);
3848
3849 if (target == TGSI_TEXTURE_BUFFER) {
3850 buffer_append_args(ctx, emit_data, rsrc, coords,
3851 bld_base->uint_bld.zero, true, false);
3852 } else {
3853 emit_data->args[emit_data->arg_count++] = coords;
3854 emit_data->args[emit_data->arg_count++] = rsrc;
3855
3856 image_append_args(ctx, emit_data, target, true, false);
3857 }
3858 }
3859 }
3860
3861 static void atomic_emit_memory(struct si_shader_context *ctx,
3862 struct lp_build_emit_data *emit_data) {
3863 struct gallivm_state *gallivm = &ctx->gallivm;
3864 LLVMBuilderRef builder = gallivm->builder;
3865 const struct tgsi_full_instruction * inst = emit_data->inst;
3866 LLVMValueRef ptr, result, arg;
3867
3868 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3869
3870 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
3871 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3872
3873 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3874 LLVMValueRef new_data;
3875 new_data = lp_build_emit_fetch(&ctx->bld_base,
3876 inst, 3, 0);
3877
3878 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3879
3880 #if HAVE_LLVM >= 0x309
3881 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3882 LLVMAtomicOrderingSequentiallyConsistent,
3883 LLVMAtomicOrderingSequentiallyConsistent,
3884 false);
3885 #endif
3886
3887 result = LLVMBuildExtractValue(builder, result, 0, "");
3888 } else {
3889 LLVMAtomicRMWBinOp op;
3890
3891 switch(inst->Instruction.Opcode) {
3892 case TGSI_OPCODE_ATOMUADD:
3893 op = LLVMAtomicRMWBinOpAdd;
3894 break;
3895 case TGSI_OPCODE_ATOMXCHG:
3896 op = LLVMAtomicRMWBinOpXchg;
3897 break;
3898 case TGSI_OPCODE_ATOMAND:
3899 op = LLVMAtomicRMWBinOpAnd;
3900 break;
3901 case TGSI_OPCODE_ATOMOR:
3902 op = LLVMAtomicRMWBinOpOr;
3903 break;
3904 case TGSI_OPCODE_ATOMXOR:
3905 op = LLVMAtomicRMWBinOpXor;
3906 break;
3907 case TGSI_OPCODE_ATOMUMIN:
3908 op = LLVMAtomicRMWBinOpUMin;
3909 break;
3910 case TGSI_OPCODE_ATOMUMAX:
3911 op = LLVMAtomicRMWBinOpUMax;
3912 break;
3913 case TGSI_OPCODE_ATOMIMIN:
3914 op = LLVMAtomicRMWBinOpMin;
3915 break;
3916 case TGSI_OPCODE_ATOMIMAX:
3917 op = LLVMAtomicRMWBinOpMax;
3918 break;
3919 default:
3920 unreachable("unknown atomic opcode");
3921 }
3922
3923 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 false);
3926 }
3927 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3928 }
3929
3930 static void atomic_emit(
3931 const struct lp_build_tgsi_action *action,
3932 struct lp_build_tgsi_context *bld_base,
3933 struct lp_build_emit_data *emit_data)
3934 {
3935 struct si_shader_context *ctx = si_shader_context(bld_base);
3936 struct gallivm_state *gallivm = bld_base->base.gallivm;
3937 LLVMBuilderRef builder = gallivm->builder;
3938 const struct tgsi_full_instruction * inst = emit_data->inst;
3939 char intrinsic_name[40];
3940 LLVMValueRef tmp;
3941
3942 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3943 atomic_emit_memory(ctx, emit_data);
3944 return;
3945 }
3946
3947 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3948 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3949 snprintf(intrinsic_name, sizeof(intrinsic_name),
3950 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3951 } else {
3952 LLVMValueRef coords;
3953 char coords_type[8];
3954
3955 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3956 coords = emit_data->args[2];
3957 else
3958 coords = emit_data->args[1];
3959
3960 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
3961 snprintf(intrinsic_name, sizeof(intrinsic_name),
3962 "llvm.amdgcn.image.atomic.%s.%s",
3963 action->intr_name, coords_type);
3964 }
3965
3966 tmp = lp_build_intrinsic(
3967 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3968 emit_data->args, emit_data->arg_count, 0);
3969 emit_data->output[emit_data->chan] =
3970 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3971 }
3972
3973 static void set_tex_fetch_args(struct si_shader_context *ctx,
3974 struct lp_build_emit_data *emit_data,
3975 unsigned target,
3976 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3977 LLVMValueRef *param, unsigned count,
3978 unsigned dmask)
3979 {
3980 struct gallivm_state *gallivm = &ctx->gallivm;
3981 struct ac_image_args args = {};
3982
3983 /* Pad to power of two vector */
3984 while (count < util_next_power_of_two(count))
3985 param[count++] = LLVMGetUndef(ctx->i32);
3986
3987 if (count > 1)
3988 args.addr = lp_build_gather_values(gallivm, param, count);
3989 else
3990 args.addr = param[0];
3991
3992 args.resource = res_ptr;
3993 args.sampler = samp_ptr;
3994 args.dmask = dmask;
3995 args.unorm = target == TGSI_TEXTURE_RECT ||
3996 target == TGSI_TEXTURE_SHADOWRECT;
3997 args.da = tgsi_is_array_sampler(target);
3998
3999 /* Ugly, but we seem to have no other choice right now. */
4000 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4001 memcpy(emit_data->args, &args, sizeof(args));
4002 }
4003
4004 static void resq_fetch_args(
4005 struct lp_build_tgsi_context * bld_base,
4006 struct lp_build_emit_data * emit_data)
4007 {
4008 struct si_shader_context *ctx = si_shader_context(bld_base);
4009 const struct tgsi_full_instruction *inst = emit_data->inst;
4010 const struct tgsi_full_src_register *reg = &inst->Src[0];
4011
4012 emit_data->dst_type = ctx->v4i32;
4013
4014 if (reg->Register.File == TGSI_FILE_BUFFER) {
4015 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4016 emit_data->arg_count = 1;
4017 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4018 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4019 &emit_data->args[0]);
4020 emit_data->arg_count = 1;
4021 } else {
4022 LLVMValueRef res_ptr;
4023 unsigned image_target;
4024
4025 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4026 image_target = TGSI_TEXTURE_2D_ARRAY;
4027 else
4028 image_target = inst->Memory.Texture;
4029
4030 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4031 &res_ptr);
4032 set_tex_fetch_args(ctx, emit_data, image_target,
4033 res_ptr, NULL, &bld_base->uint_bld.zero, 1,
4034 0xf);
4035 }
4036 }
4037
4038 static void resq_emit(
4039 const struct lp_build_tgsi_action *action,
4040 struct lp_build_tgsi_context *bld_base,
4041 struct lp_build_emit_data *emit_data)
4042 {
4043 struct si_shader_context *ctx = si_shader_context(bld_base);
4044 struct gallivm_state *gallivm = bld_base->base.gallivm;
4045 LLVMBuilderRef builder = gallivm->builder;
4046 const struct tgsi_full_instruction *inst = emit_data->inst;
4047 LLVMValueRef out;
4048
4049 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4050 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4051 lp_build_const_int32(gallivm, 2), "");
4052 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4053 out = get_buffer_size(bld_base, emit_data->args[0]);
4054 } else {
4055 struct ac_image_args args;
4056
4057 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4058 args.opcode = ac_image_get_resinfo;
4059 out = ac_emit_image_opcode(&ctx->ac, &args);
4060
4061 /* Divide the number of layers by 6 to get the number of cubes. */
4062 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4063 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4064 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4065
4066 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4067 z = LLVMBuildSDiv(builder, z, imm6, "");
4068 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4069 }
4070 }
4071
4072 emit_data->output[emit_data->chan] = out;
4073 }
4074
4075 static const struct lp_build_tgsi_action tex_action;
4076
4077 enum desc_type {
4078 DESC_IMAGE,
4079 DESC_BUFFER,
4080 DESC_FMASK,
4081 DESC_SAMPLER,
4082 };
4083
4084 /**
4085 * Load an image view, fmask view. or sampler state descriptor.
4086 */
4087 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4088 LLVMValueRef list, LLVMValueRef index,
4089 enum desc_type type)
4090 {
4091 struct gallivm_state *gallivm = &ctx->gallivm;
4092 LLVMBuilderRef builder = gallivm->builder;
4093
4094 switch (type) {
4095 case DESC_IMAGE:
4096 /* The image is at [0:7]. */
4097 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4098 break;
4099 case DESC_BUFFER:
4100 /* The buffer is in [4:7]. */
4101 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4102 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4103 list = LLVMBuildPointerCast(builder, list,
4104 const_array(ctx->v4i32, 0), "");
4105 break;
4106 case DESC_FMASK:
4107 /* The FMASK is at [8:15]. */
4108 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4109 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4110 break;
4111 case DESC_SAMPLER:
4112 /* The sampler state is at [12:15]. */
4113 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4114 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4115 list = LLVMBuildPointerCast(builder, list,
4116 const_array(ctx->v4i32, 0), "");
4117 break;
4118 }
4119
4120 return ac_build_indexed_load_const(&ctx->ac, list, index);
4121 }
4122
4123 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4124 LLVMValueRef index, enum desc_type type)
4125 {
4126 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4127 SI_PARAM_SAMPLERS);
4128
4129 return load_sampler_desc_custom(ctx, list, index, type);
4130 }
4131
4132 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4133 *
4134 * SI-CI:
4135 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4136 * filtering manually. The driver sets img7 to a mask clearing
4137 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4138 * s_and_b32 samp0, samp0, img7
4139 *
4140 * VI:
4141 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4142 */
4143 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4144 LLVMValueRef res, LLVMValueRef samp)
4145 {
4146 LLVMBuilderRef builder = ctx->gallivm.builder;
4147 LLVMValueRef img7, samp0;
4148
4149 if (ctx->screen->b.chip_class >= VI)
4150 return samp;
4151
4152 img7 = LLVMBuildExtractElement(builder, res,
4153 LLVMConstInt(ctx->i32, 7, 0), "");
4154 samp0 = LLVMBuildExtractElement(builder, samp,
4155 LLVMConstInt(ctx->i32, 0, 0), "");
4156 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4157 return LLVMBuildInsertElement(builder, samp, samp0,
4158 LLVMConstInt(ctx->i32, 0, 0), "");
4159 }
4160
4161 static void tex_fetch_ptrs(
4162 struct lp_build_tgsi_context *bld_base,
4163 struct lp_build_emit_data *emit_data,
4164 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4165 {
4166 struct si_shader_context *ctx = si_shader_context(bld_base);
4167 const struct tgsi_full_instruction *inst = emit_data->inst;
4168 unsigned target = inst->Texture.Texture;
4169 unsigned sampler_src;
4170 unsigned sampler_index;
4171 LLVMValueRef index;
4172
4173 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4174 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4175
4176 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4177 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4178
4179 index = get_bounded_indirect_index(ctx,
4180 &reg->Indirect,
4181 reg->Register.Index,
4182 SI_NUM_SAMPLERS);
4183 } else {
4184 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4185 }
4186
4187 if (target == TGSI_TEXTURE_BUFFER)
4188 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4189 else
4190 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4191
4192 if (samp_ptr)
4193 *samp_ptr = NULL;
4194 if (fmask_ptr)
4195 *fmask_ptr = NULL;
4196
4197 if (target == TGSI_TEXTURE_2D_MSAA ||
4198 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4199 if (fmask_ptr)
4200 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4201 } else if (target != TGSI_TEXTURE_BUFFER) {
4202 if (samp_ptr) {
4203 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4204 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4205 }
4206 }
4207 }
4208
4209 static void txq_fetch_args(
4210 struct lp_build_tgsi_context *bld_base,
4211 struct lp_build_emit_data *emit_data)
4212 {
4213 struct si_shader_context *ctx = si_shader_context(bld_base);
4214 const struct tgsi_full_instruction *inst = emit_data->inst;
4215 unsigned target = inst->Texture.Texture;
4216 LLVMValueRef res_ptr;
4217 LLVMValueRef address;
4218
4219 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4220
4221 if (target == TGSI_TEXTURE_BUFFER) {
4222 /* Read the size from the buffer descriptor directly. */
4223 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4224 return;
4225 }
4226
4227 /* Textures - set the mip level. */
4228 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4229
4230 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4231 NULL, &address, 1, 0xf);
4232 }
4233
4234 static void txq_emit(const struct lp_build_tgsi_action *action,
4235 struct lp_build_tgsi_context *bld_base,
4236 struct lp_build_emit_data *emit_data)
4237 {
4238 struct si_shader_context *ctx = si_shader_context(bld_base);
4239 struct ac_image_args args;
4240 unsigned target = emit_data->inst->Texture.Texture;
4241
4242 if (target == TGSI_TEXTURE_BUFFER) {
4243 /* Just return the buffer size. */
4244 emit_data->output[emit_data->chan] = emit_data->args[0];
4245 return;
4246 }
4247
4248 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4249
4250 args.opcode = ac_image_get_resinfo;
4251 emit_data->output[emit_data->chan] =
4252 ac_emit_image_opcode(&ctx->ac, &args);
4253
4254 /* Divide the number of layers by 6 to get the number of cubes. */
4255 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4256 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4257 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4258 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4259 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4260
4261 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4262 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4263 z = LLVMBuildSDiv(builder, z, six, "");
4264
4265 emit_data->output[emit_data->chan] =
4266 LLVMBuildInsertElement(builder, v4, z, two, "");
4267 }
4268 }
4269
4270 static void tex_fetch_args(
4271 struct lp_build_tgsi_context *bld_base,
4272 struct lp_build_emit_data *emit_data)
4273 {
4274 struct si_shader_context *ctx = si_shader_context(bld_base);
4275 struct gallivm_state *gallivm = bld_base->base.gallivm;
4276 const struct tgsi_full_instruction *inst = emit_data->inst;
4277 unsigned opcode = inst->Instruction.Opcode;
4278 unsigned target = inst->Texture.Texture;
4279 LLVMValueRef coords[5], derivs[6];
4280 LLVMValueRef address[16];
4281 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4282 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4283 unsigned count = 0;
4284 unsigned chan;
4285 unsigned num_deriv_channels = 0;
4286 bool has_offset = inst->Texture.NumOffsets > 0;
4287 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4288 unsigned dmask = 0xf;
4289
4290 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4291
4292 if (target == TGSI_TEXTURE_BUFFER) {
4293 emit_data->dst_type = ctx->v4f32;
4294 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4295 ctx->v16i8, "");
4296 emit_data->args[1] = bld_base->uint_bld.zero;
4297 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4298 emit_data->arg_count = 3;
4299 return;
4300 }
4301
4302 /* Fetch and project texture coordinates */
4303 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4304 for (chan = 0; chan < 3; chan++ ) {
4305 coords[chan] = lp_build_emit_fetch(bld_base,
4306 emit_data->inst, 0,
4307 chan);
4308 if (opcode == TGSI_OPCODE_TXP)
4309 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4310 TGSI_OPCODE_DIV,
4311 coords[chan],
4312 coords[3]);
4313 }
4314
4315 if (opcode == TGSI_OPCODE_TXP)
4316 coords[3] = bld_base->base.one;
4317
4318 /* Pack offsets. */
4319 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4320 /* The offsets are six-bit signed integers packed like this:
4321 * X=[5:0], Y=[13:8], and Z=[21:16].
4322 */
4323 LLVMValueRef offset[3], pack;
4324
4325 assert(inst->Texture.NumOffsets == 1);
4326
4327 for (chan = 0; chan < 3; chan++) {
4328 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4329 emit_data->inst, 0, chan);
4330 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4331 lp_build_const_int32(gallivm, 0x3f), "");
4332 if (chan)
4333 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4334 lp_build_const_int32(gallivm, chan*8), "");
4335 }
4336
4337 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4338 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4339 address[count++] = pack;
4340 }
4341
4342 /* Pack LOD bias value */
4343 if (opcode == TGSI_OPCODE_TXB)
4344 address[count++] = coords[3];
4345 if (opcode == TGSI_OPCODE_TXB2)
4346 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4347
4348 /* Pack depth comparison value */
4349 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4350 LLVMValueRef z;
4351
4352 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4353 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4354 } else {
4355 assert(ref_pos >= 0);
4356 z = coords[ref_pos];
4357 }
4358
4359 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4360 * so the depth comparison value isn't clamped for Z16 and
4361 * Z24 anymore. Do it manually here.
4362 *
4363 * It's unnecessary if the original texture format was
4364 * Z32_FLOAT, but we don't know that here.
4365 */
4366 if (ctx->screen->b.chip_class == VI)
4367 z = ac_emit_clamp(&ctx->ac, z);
4368
4369 address[count++] = z;
4370 }
4371
4372 /* Pack user derivatives */
4373 if (opcode == TGSI_OPCODE_TXD) {
4374 int param, num_src_deriv_channels;
4375
4376 switch (target) {
4377 case TGSI_TEXTURE_3D:
4378 num_src_deriv_channels = 3;
4379 num_deriv_channels = 3;
4380 break;
4381 case TGSI_TEXTURE_2D:
4382 case TGSI_TEXTURE_SHADOW2D:
4383 case TGSI_TEXTURE_RECT:
4384 case TGSI_TEXTURE_SHADOWRECT:
4385 case TGSI_TEXTURE_2D_ARRAY:
4386 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4387 num_src_deriv_channels = 2;
4388 num_deriv_channels = 2;
4389 break;
4390 case TGSI_TEXTURE_CUBE:
4391 case TGSI_TEXTURE_SHADOWCUBE:
4392 case TGSI_TEXTURE_CUBE_ARRAY:
4393 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4394 /* Cube derivatives will be converted to 2D. */
4395 num_src_deriv_channels = 3;
4396 num_deriv_channels = 2;
4397 break;
4398 case TGSI_TEXTURE_1D:
4399 case TGSI_TEXTURE_SHADOW1D:
4400 case TGSI_TEXTURE_1D_ARRAY:
4401 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4402 num_src_deriv_channels = 1;
4403 num_deriv_channels = 1;
4404 break;
4405 default:
4406 unreachable("invalid target");
4407 }
4408
4409 for (param = 0; param < 2; param++)
4410 for (chan = 0; chan < num_src_deriv_channels; chan++)
4411 derivs[param * num_src_deriv_channels + chan] =
4412 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4413 }
4414
4415 if (target == TGSI_TEXTURE_CUBE ||
4416 target == TGSI_TEXTURE_CUBE_ARRAY ||
4417 target == TGSI_TEXTURE_SHADOWCUBE ||
4418 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4419 ac_prepare_cube_coords(&ctx->ac,
4420 opcode == TGSI_OPCODE_TXD,
4421 target == TGSI_TEXTURE_CUBE_ARRAY ||
4422 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4423 coords, derivs);
4424
4425 if (opcode == TGSI_OPCODE_TXD)
4426 for (int i = 0; i < num_deriv_channels * 2; i++)
4427 address[count++] = derivs[i];
4428
4429 /* Pack texture coordinates */
4430 address[count++] = coords[0];
4431 if (num_coords > 1)
4432 address[count++] = coords[1];
4433 if (num_coords > 2)
4434 address[count++] = coords[2];
4435
4436 /* Pack LOD or sample index */
4437 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4438 address[count++] = coords[3];
4439 else if (opcode == TGSI_OPCODE_TXL2)
4440 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4441
4442 if (count > 16) {
4443 assert(!"Cannot handle more than 16 texture address parameters");
4444 count = 16;
4445 }
4446
4447 for (chan = 0; chan < count; chan++ ) {
4448 address[chan] = LLVMBuildBitCast(gallivm->builder,
4449 address[chan], ctx->i32, "");
4450 }
4451
4452 /* Adjust the sample index according to FMASK.
4453 *
4454 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4455 * which is the identity mapping. Each nibble says which physical sample
4456 * should be fetched to get that sample.
4457 *
4458 * For example, 0x11111100 means there are only 2 samples stored and
4459 * the second sample covers 3/4 of the pixel. When reading samples 0
4460 * and 1, return physical sample 0 (determined by the first two 0s
4461 * in FMASK), otherwise return physical sample 1.
4462 *
4463 * The sample index should be adjusted as follows:
4464 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4465 */
4466 if (target == TGSI_TEXTURE_2D_MSAA ||
4467 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4468 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4469 struct lp_build_emit_data txf_emit_data = *emit_data;
4470 LLVMValueRef txf_address[4];
4471 /* We only need .xy for non-arrays, and .xyz for arrays. */
4472 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4473 struct tgsi_full_instruction inst = {};
4474
4475 memcpy(txf_address, address, sizeof(txf_address));
4476
4477 /* Read FMASK using TXF. */
4478 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4479 inst.Texture.Texture = target;
4480 txf_emit_data.inst = &inst;
4481 txf_emit_data.chan = 0;
4482 set_tex_fetch_args(ctx, &txf_emit_data,
4483 target, fmask_ptr, NULL,
4484 txf_address, txf_count, 0xf);
4485 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4486
4487 /* Initialize some constants. */
4488 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4489 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4490
4491 /* Apply the formula. */
4492 LLVMValueRef fmask =
4493 LLVMBuildExtractElement(gallivm->builder,
4494 txf_emit_data.output[0],
4495 uint_bld->zero, "");
4496
4497 unsigned sample_chan = txf_count; /* the sample index is last */
4498
4499 LLVMValueRef sample_index4 =
4500 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4501
4502 LLVMValueRef shifted_fmask =
4503 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4504
4505 LLVMValueRef final_sample =
4506 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4507
4508 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4509 * resource descriptor is 0 (invalid),
4510 */
4511 LLVMValueRef fmask_desc =
4512 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4513 ctx->v8i32, "");
4514
4515 LLVMValueRef fmask_word1 =
4516 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4517 uint_bld->one, "");
4518
4519 LLVMValueRef word1_is_nonzero =
4520 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4521 fmask_word1, uint_bld->zero, "");
4522
4523 /* Replace the MSAA sample index. */
4524 address[sample_chan] =
4525 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4526 final_sample, address[sample_chan], "");
4527 }
4528
4529 if (opcode == TGSI_OPCODE_TXF) {
4530 /* add tex offsets */
4531 if (inst->Texture.NumOffsets) {
4532 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4533 const struct tgsi_texture_offset *off = inst->TexOffsets;
4534
4535 assert(inst->Texture.NumOffsets == 1);
4536
4537 switch (target) {
4538 case TGSI_TEXTURE_3D:
4539 address[2] = lp_build_add(uint_bld, address[2],
4540 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4541 /* fall through */
4542 case TGSI_TEXTURE_2D:
4543 case TGSI_TEXTURE_SHADOW2D:
4544 case TGSI_TEXTURE_RECT:
4545 case TGSI_TEXTURE_SHADOWRECT:
4546 case TGSI_TEXTURE_2D_ARRAY:
4547 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4548 address[1] =
4549 lp_build_add(uint_bld, address[1],
4550 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4551 /* fall through */
4552 case TGSI_TEXTURE_1D:
4553 case TGSI_TEXTURE_SHADOW1D:
4554 case TGSI_TEXTURE_1D_ARRAY:
4555 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4556 address[0] =
4557 lp_build_add(uint_bld, address[0],
4558 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4559 break;
4560 /* texture offsets do not apply to other texture targets */
4561 }
4562 }
4563 }
4564
4565 if (opcode == TGSI_OPCODE_TG4) {
4566 unsigned gather_comp = 0;
4567
4568 /* DMASK was repurposed for GATHER4. 4 components are always
4569 * returned and DMASK works like a swizzle - it selects
4570 * the component to fetch. The only valid DMASK values are
4571 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4572 * (red,red,red,red) etc.) The ISA document doesn't mention
4573 * this.
4574 */
4575
4576 /* Get the component index from src1.x for Gather4. */
4577 if (!tgsi_is_shadow_target(target)) {
4578 LLVMValueRef comp_imm;
4579 struct tgsi_src_register src1 = inst->Src[1].Register;
4580
4581 assert(src1.File == TGSI_FILE_IMMEDIATE);
4582
4583 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4584 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4585 gather_comp = CLAMP(gather_comp, 0, 3);
4586 }
4587
4588 dmask = 1 << gather_comp;
4589 }
4590
4591 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4592 samp_ptr, address, count, dmask);
4593 }
4594
4595 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4596 * incorrectly forces nearest filtering if the texture format is integer.
4597 * The only effect it has on Gather4, which always returns 4 texels for
4598 * bilinear filtering, is that the final coordinates are off by 0.5 of
4599 * the texel size.
4600 *
4601 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4602 * or (0.5 / size) from the normalized coordinates.
4603 */
4604 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4605 struct ac_image_args *args,
4606 unsigned target)
4607 {
4608 LLVMBuilderRef builder = ctx->gallivm.builder;
4609 LLVMValueRef coord = args->addr;
4610 LLVMValueRef half_texel[2];
4611 /* Texture coordinates start after:
4612 * {offset, bias, z-compare, derivatives}
4613 * Only the offset and z-compare can occur here.
4614 */
4615 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4616 int c;
4617
4618 if (target == TGSI_TEXTURE_RECT ||
4619 target == TGSI_TEXTURE_SHADOWRECT) {
4620 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4621 } else {
4622 struct tgsi_full_instruction txq_inst = {};
4623 struct lp_build_emit_data txq_emit_data = {};
4624
4625 /* Query the texture size. */
4626 txq_inst.Texture.Texture = target;
4627 txq_emit_data.inst = &txq_inst;
4628 txq_emit_data.dst_type = ctx->v4i32;
4629 set_tex_fetch_args(ctx, &txq_emit_data, target,
4630 args->resource, NULL,
4631 &ctx->bld_base.uint_bld.zero,
4632 1, 0xf);
4633 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4634
4635 /* Compute -0.5 / size. */
4636 for (c = 0; c < 2; c++) {
4637 half_texel[c] =
4638 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4639 LLVMConstInt(ctx->i32, c, 0), "");
4640 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4641 half_texel[c] =
4642 lp_build_emit_llvm_unary(&ctx->bld_base,
4643 TGSI_OPCODE_RCP, half_texel[c]);
4644 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4645 LLVMConstReal(ctx->f32, -0.5), "");
4646 }
4647 }
4648
4649 for (c = 0; c < 2; c++) {
4650 LLVMValueRef tmp;
4651 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4652
4653 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4654 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4655 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4656 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4657 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4658 }
4659
4660 args->addr = coord;
4661 }
4662
4663 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4664 struct lp_build_tgsi_context *bld_base,
4665 struct lp_build_emit_data *emit_data)
4666 {
4667 struct si_shader_context *ctx = si_shader_context(bld_base);
4668 struct lp_build_context *base = &bld_base->base;
4669 const struct tgsi_full_instruction *inst = emit_data->inst;
4670 struct ac_image_args args;
4671 unsigned opcode = inst->Instruction.Opcode;
4672 unsigned target = inst->Texture.Texture;
4673
4674 if (target == TGSI_TEXTURE_BUFFER) {
4675 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4676 base->gallivm->builder,
4677 "llvm.SI.vs.load.input", emit_data->dst_type,
4678 emit_data->args, emit_data->arg_count,
4679 LP_FUNC_ATTR_READNONE | LP_FUNC_ATTR_LEGACY);
4680 return;
4681 }
4682
4683 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4684
4685 args.opcode = ac_image_sample;
4686 args.compare = tgsi_is_shadow_target(target);
4687 args.offset = inst->Texture.NumOffsets > 0;
4688
4689 switch (opcode) {
4690 case TGSI_OPCODE_TXF:
4691 args.opcode = target == TGSI_TEXTURE_2D_MSAA ||
4692 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4693 ac_image_load : ac_image_load_mip;
4694 args.compare = false;
4695 args.offset = false;
4696 break;
4697 case TGSI_OPCODE_LODQ:
4698 args.opcode = ac_image_get_lod;
4699 args.compare = false;
4700 args.offset = false;
4701 break;
4702 case TGSI_OPCODE_TEX:
4703 case TGSI_OPCODE_TEX2:
4704 case TGSI_OPCODE_TXP:
4705 if (ctx->type != PIPE_SHADER_FRAGMENT)
4706 args.level_zero = true;
4707 break;
4708 case TGSI_OPCODE_TXB:
4709 case TGSI_OPCODE_TXB2:
4710 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4711 args.bias = true;
4712 break;
4713 case TGSI_OPCODE_TXL:
4714 case TGSI_OPCODE_TXL2:
4715 args.lod = true;
4716 break;
4717 case TGSI_OPCODE_TXD:
4718 args.deriv = true;
4719 break;
4720 case TGSI_OPCODE_TG4:
4721 args.opcode = ac_image_gather4;
4722 args.level_zero = true;
4723 break;
4724 default:
4725 assert(0);
4726 return;
4727 }
4728
4729 /* The hardware needs special lowering for Gather4 with integer formats. */
4730 if (opcode == TGSI_OPCODE_TG4) {
4731 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4732 /* This will also work with non-constant indexing because of how
4733 * glsl_to_tgsi works and we intent to preserve that behavior.
4734 */
4735 const unsigned src_idx = 2;
4736 unsigned sampler = inst->Src[src_idx].Register.Index;
4737
4738 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4739
4740 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4741 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4742 si_lower_gather4_integer(ctx, &args, target);
4743 }
4744
4745 emit_data->output[emit_data->chan] =
4746 ac_emit_image_opcode(&ctx->ac, &args);
4747 }
4748
4749 static void si_llvm_emit_txqs(
4750 const struct lp_build_tgsi_action *action,
4751 struct lp_build_tgsi_context *bld_base,
4752 struct lp_build_emit_data *emit_data)
4753 {
4754 struct si_shader_context *ctx = si_shader_context(bld_base);
4755 struct gallivm_state *gallivm = bld_base->base.gallivm;
4756 LLVMBuilderRef builder = gallivm->builder;
4757 LLVMValueRef res, samples;
4758 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4759
4760 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4761
4762
4763 /* Read the samples from the descriptor directly. */
4764 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4765 samples = LLVMBuildExtractElement(
4766 builder, res,
4767 lp_build_const_int32(gallivm, 3), "");
4768 samples = LLVMBuildLShr(builder, samples,
4769 lp_build_const_int32(gallivm, 16), "");
4770 samples = LLVMBuildAnd(builder, samples,
4771 lp_build_const_int32(gallivm, 0xf), "");
4772 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4773 samples, "");
4774
4775 emit_data->output[emit_data->chan] = samples;
4776 }
4777
4778 static void si_llvm_emit_ddxy(
4779 const struct lp_build_tgsi_action *action,
4780 struct lp_build_tgsi_context *bld_base,
4781 struct lp_build_emit_data *emit_data)
4782 {
4783 struct si_shader_context *ctx = si_shader_context(bld_base);
4784 struct gallivm_state *gallivm = bld_base->base.gallivm;
4785 unsigned opcode = emit_data->info->opcode;
4786 LLVMValueRef val;
4787 int idx;
4788 unsigned mask;
4789
4790 if (opcode == TGSI_OPCODE_DDX_FINE)
4791 mask = AC_TID_MASK_LEFT;
4792 else if (opcode == TGSI_OPCODE_DDY_FINE)
4793 mask = AC_TID_MASK_TOP;
4794 else
4795 mask = AC_TID_MASK_TOP_LEFT;
4796
4797 /* for DDX we want to next X pixel, DDY next Y pixel. */
4798 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4799
4800 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4801 val = ac_emit_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
4802 mask, idx, ctx->lds, val);
4803 emit_data->output[emit_data->chan] = val;
4804 }
4805
4806 /*
4807 * this takes an I,J coordinate pair,
4808 * and works out the X and Y derivatives.
4809 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4810 */
4811 static LLVMValueRef si_llvm_emit_ddxy_interp(
4812 struct lp_build_tgsi_context *bld_base,
4813 LLVMValueRef interp_ij)
4814 {
4815 struct si_shader_context *ctx = si_shader_context(bld_base);
4816 struct gallivm_state *gallivm = bld_base->base.gallivm;
4817 LLVMValueRef result[4], a;
4818 unsigned i;
4819
4820 for (i = 0; i < 2; i++) {
4821 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4822 LLVMConstInt(ctx->i32, i, 0), "");
4823 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4824 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4825 }
4826
4827 return lp_build_gather_values(gallivm, result, 4);
4828 }
4829
4830 static void interp_fetch_args(
4831 struct lp_build_tgsi_context *bld_base,
4832 struct lp_build_emit_data *emit_data)
4833 {
4834 struct si_shader_context *ctx = si_shader_context(bld_base);
4835 struct gallivm_state *gallivm = bld_base->base.gallivm;
4836 const struct tgsi_full_instruction *inst = emit_data->inst;
4837
4838 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4839 /* offset is in second src, first two channels */
4840 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4841 emit_data->inst, 1,
4842 TGSI_CHAN_X);
4843 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4844 emit_data->inst, 1,
4845 TGSI_CHAN_Y);
4846 emit_data->arg_count = 2;
4847 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4848 LLVMValueRef sample_position;
4849 LLVMValueRef sample_id;
4850 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4851
4852 /* fetch sample ID, then fetch its sample position,
4853 * and place into first two channels.
4854 */
4855 sample_id = lp_build_emit_fetch(bld_base,
4856 emit_data->inst, 1, TGSI_CHAN_X);
4857 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4858 ctx->i32, "");
4859 sample_position = load_sample_position(ctx, sample_id);
4860
4861 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4862 sample_position,
4863 lp_build_const_int32(gallivm, 0), "");
4864
4865 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4866 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4867 sample_position,
4868 lp_build_const_int32(gallivm, 1), "");
4869 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4870 emit_data->arg_count = 2;
4871 }
4872 }
4873
4874 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4875 struct lp_build_tgsi_context *bld_base,
4876 struct lp_build_emit_data *emit_data)
4877 {
4878 struct si_shader_context *ctx = si_shader_context(bld_base);
4879 struct si_shader *shader = ctx->shader;
4880 struct gallivm_state *gallivm = bld_base->base.gallivm;
4881 struct lp_build_context *uint = &bld_base->uint_bld;
4882 LLVMValueRef interp_param;
4883 const struct tgsi_full_instruction *inst = emit_data->inst;
4884 int input_index = inst->Src[0].Register.Index;
4885 int chan;
4886 int i;
4887 LLVMValueRef attr_number;
4888 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
4889 int interp_param_idx;
4890 unsigned interp = shader->selector->info.input_interpolate[input_index];
4891 unsigned location;
4892
4893 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4894
4895 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4896 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4897 location = TGSI_INTERPOLATE_LOC_CENTER;
4898 else
4899 location = TGSI_INTERPOLATE_LOC_CENTROID;
4900
4901 interp_param_idx = lookup_interp_param_index(interp, location);
4902 if (interp_param_idx == -1)
4903 return;
4904 else if (interp_param_idx)
4905 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4906 else
4907 interp_param = NULL;
4908
4909 attr_number = lp_build_const_int32(gallivm, input_index);
4910
4911 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4912 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4913 LLVMValueRef ij_out[2];
4914 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4915
4916 /*
4917 * take the I then J parameters, and the DDX/Y for it, and
4918 * calculate the IJ inputs for the interpolator.
4919 * temp1 = ddx * offset/sample.x + I;
4920 * interp_param.I = ddy * offset/sample.y + temp1;
4921 * temp1 = ddx * offset/sample.x + J;
4922 * interp_param.J = ddy * offset/sample.y + temp1;
4923 */
4924 for (i = 0; i < 2; i++) {
4925 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4926 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4927 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4928 ddxy_out, ix_ll, "");
4929 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4930 ddxy_out, iy_ll, "");
4931 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4932 interp_param, ix_ll, "");
4933 LLVMValueRef temp1, temp2;
4934
4935 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4936 ctx->f32, "");
4937
4938 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4939
4940 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4941
4942 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4943
4944 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4945 }
4946 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4947 }
4948
4949 for (chan = 0; chan < 4; chan++) {
4950 LLVMValueRef llvm_chan;
4951 unsigned schan;
4952
4953 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4954 llvm_chan = lp_build_const_int32(gallivm, schan);
4955
4956 if (interp_param) {
4957 interp_param = LLVMBuildBitCast(gallivm->builder,
4958 interp_param, LLVMVectorType(ctx->f32, 2), "");
4959 LLVMValueRef i = LLVMBuildExtractElement(
4960 gallivm->builder, interp_param, uint->zero, "");
4961 LLVMValueRef j = LLVMBuildExtractElement(
4962 gallivm->builder, interp_param, uint->one, "");
4963 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
4964 llvm_chan, attr_number, params,
4965 i, j);
4966 } else {
4967 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
4968 lp_build_const_int32(gallivm, 2), /* P0 */
4969 llvm_chan, attr_number, params);
4970 }
4971 }
4972 }
4973
4974 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4975 struct lp_build_emit_data *emit_data)
4976 {
4977 struct si_shader_context *ctx = si_shader_context(bld_base);
4978 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4979 LLVMValueRef imm;
4980 unsigned stream;
4981
4982 assert(src0.File == TGSI_FILE_IMMEDIATE);
4983
4984 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4985 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4986 return stream;
4987 }
4988
4989 /* Emit one vertex from the geometry shader */
4990 static void si_llvm_emit_vertex(
4991 const struct lp_build_tgsi_action *action,
4992 struct lp_build_tgsi_context *bld_base,
4993 struct lp_build_emit_data *emit_data)
4994 {
4995 struct si_shader_context *ctx = si_shader_context(bld_base);
4996 struct lp_build_context *uint = &bld_base->uint_bld;
4997 struct si_shader *shader = ctx->shader;
4998 struct tgsi_shader_info *info = &shader->selector->info;
4999 struct gallivm_state *gallivm = bld_base->base.gallivm;
5000 struct lp_build_if_state if_state;
5001 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5002 SI_PARAM_GS2VS_OFFSET);
5003 LLVMValueRef gs_next_vertex;
5004 LLVMValueRef can_emit, kill;
5005 unsigned chan, offset;
5006 int i;
5007 unsigned stream;
5008
5009 stream = si_llvm_get_stream(bld_base, emit_data);
5010
5011 /* Write vertex attribute values to GSVS ring */
5012 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5013 ctx->gs_next_vertex[stream],
5014 "");
5015
5016 /* If this thread has already emitted the declared maximum number of
5017 * vertices, skip the write: excessive vertex emissions are not
5018 * supposed to have any effect.
5019 *
5020 * If the shader has no writes to memory, kill it instead. This skips
5021 * further memory loads and may allow LLVM to skip to the end
5022 * altogether.
5023 */
5024 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5025 lp_build_const_int32(gallivm,
5026 shader->selector->gs_max_out_vertices), "");
5027
5028 bool use_kill = !info->writes_memory;
5029 if (use_kill) {
5030 kill = lp_build_select(&bld_base->base, can_emit,
5031 lp_build_const_float(gallivm, 1.0f),
5032 lp_build_const_float(gallivm, -1.0f));
5033
5034 ac_emit_kill(&ctx->ac, kill);
5035 } else {
5036 lp_build_if(&if_state, gallivm, can_emit);
5037 }
5038
5039 offset = 0;
5040 for (i = 0; i < info->num_outputs; i++) {
5041 LLVMValueRef *out_ptr = ctx->outputs[i];
5042
5043 for (chan = 0; chan < 4; chan++) {
5044 if (!(info->output_usagemask[i] & (1 << chan)) ||
5045 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5046 continue;
5047
5048 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5049 LLVMValueRef voffset =
5050 lp_build_const_int32(gallivm, offset *
5051 shader->selector->gs_max_out_vertices);
5052 offset++;
5053
5054 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5055 voffset = lp_build_mul_imm(uint, voffset, 4);
5056
5057 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5058
5059 ac_build_tbuffer_store(&ctx->ac,
5060 ctx->gsvs_ring[stream],
5061 out_val, 1,
5062 voffset, soffset, 0,
5063 V_008F0C_BUF_DATA_FORMAT_32,
5064 V_008F0C_BUF_NUM_FORMAT_UINT,
5065 1, 0, 1, 1, 0);
5066 }
5067 }
5068
5069 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5070 lp_build_const_int32(gallivm, 1));
5071
5072 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5073
5074 /* Signal vertex emission */
5075 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5076 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5077 if (!use_kill)
5078 lp_build_endif(&if_state);
5079 }
5080
5081 /* Cut one primitive from the geometry shader */
5082 static void si_llvm_emit_primitive(
5083 const struct lp_build_tgsi_action *action,
5084 struct lp_build_tgsi_context *bld_base,
5085 struct lp_build_emit_data *emit_data)
5086 {
5087 struct si_shader_context *ctx = si_shader_context(bld_base);
5088 unsigned stream;
5089
5090 /* Signal primitive cut */
5091 stream = si_llvm_get_stream(bld_base, emit_data);
5092 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5093 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5094 }
5095
5096 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5097 struct lp_build_tgsi_context *bld_base,
5098 struct lp_build_emit_data *emit_data)
5099 {
5100 struct si_shader_context *ctx = si_shader_context(bld_base);
5101 struct gallivm_state *gallivm = bld_base->base.gallivm;
5102
5103 /* SI only (thanks to a hw bug workaround):
5104 * The real barrier instruction isn’t needed, because an entire patch
5105 * always fits into a single wave.
5106 */
5107 if (HAVE_LLVM >= 0x0309 &&
5108 ctx->screen->b.chip_class == SI &&
5109 ctx->type == PIPE_SHADER_TESS_CTRL) {
5110 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5111 return;
5112 }
5113
5114 lp_build_intrinsic(gallivm->builder,
5115 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5116 : "llvm.AMDGPU.barrier.local",
5117 ctx->voidt, NULL, 0, 0);
5118 }
5119
5120 static const struct lp_build_tgsi_action tex_action = {
5121 .fetch_args = tex_fetch_args,
5122 .emit = build_tex_intrinsic,
5123 };
5124
5125 static const struct lp_build_tgsi_action interp_action = {
5126 .fetch_args = interp_fetch_args,
5127 .emit = build_interp_intrinsic,
5128 };
5129
5130 static void si_create_function(struct si_shader_context *ctx,
5131 const char *name,
5132 LLVMTypeRef *returns, unsigned num_returns,
5133 LLVMTypeRef *params, unsigned num_params,
5134 int last_sgpr)
5135 {
5136 int i;
5137
5138 si_llvm_create_func(ctx, name, returns, num_returns,
5139 params, num_params);
5140 si_llvm_shader_type(ctx->main_fn, ctx->type);
5141 ctx->return_value = LLVMGetUndef(ctx->return_type);
5142
5143 for (i = 0; i <= last_sgpr; ++i) {
5144 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5145
5146 /* The combination of:
5147 * - ByVal
5148 * - dereferenceable
5149 * - invariant.load
5150 * allows the optimization passes to move loads and reduces
5151 * SGPR spilling significantly.
5152 */
5153 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5154 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5155 lp_add_attr_dereferenceable(P, UINT64_MAX);
5156 } else
5157 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5158 }
5159
5160 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5161 "no-signed-zeros-fp-math",
5162 "true");
5163
5164 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5165 /* These were copied from some LLVM test. */
5166 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5167 "less-precise-fpmad",
5168 "true");
5169 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5170 "no-infs-fp-math",
5171 "true");
5172 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5173 "no-nans-fp-math",
5174 "true");
5175 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5176 "unsafe-fp-math",
5177 "true");
5178 }
5179 }
5180
5181 static void declare_streamout_params(struct si_shader_context *ctx,
5182 struct pipe_stream_output_info *so,
5183 LLVMTypeRef *params, LLVMTypeRef i32,
5184 unsigned *num_params)
5185 {
5186 int i;
5187
5188 /* Streamout SGPRs. */
5189 if (so->num_outputs) {
5190 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5191 params[ctx->param_streamout_config = (*num_params)++] = i32;
5192 else
5193 ctx->param_streamout_config = *num_params - 1;
5194
5195 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5196 }
5197 /* A streamout buffer offset is loaded if the stride is non-zero. */
5198 for (i = 0; i < 4; i++) {
5199 if (!so->stride[i])
5200 continue;
5201
5202 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5203 }
5204 }
5205
5206 static unsigned llvm_get_type_size(LLVMTypeRef type)
5207 {
5208 LLVMTypeKind kind = LLVMGetTypeKind(type);
5209
5210 switch (kind) {
5211 case LLVMIntegerTypeKind:
5212 return LLVMGetIntTypeWidth(type) / 8;
5213 case LLVMFloatTypeKind:
5214 return 4;
5215 case LLVMPointerTypeKind:
5216 return 8;
5217 case LLVMVectorTypeKind:
5218 return LLVMGetVectorSize(type) *
5219 llvm_get_type_size(LLVMGetElementType(type));
5220 case LLVMArrayTypeKind:
5221 return LLVMGetArrayLength(type) *
5222 llvm_get_type_size(LLVMGetElementType(type));
5223 default:
5224 assert(0);
5225 return 0;
5226 }
5227 }
5228
5229 static void declare_tess_lds(struct si_shader_context *ctx)
5230 {
5231 struct gallivm_state *gallivm = &ctx->gallivm;
5232 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5233 struct lp_build_context *uint = &bld_base->uint_bld;
5234
5235 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5236 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5237 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5238 "tess_lds");
5239 }
5240
5241 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5242 {
5243 const unsigned *properties = shader->selector->info.properties;
5244 unsigned max_work_group_size =
5245 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5246 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5247 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5248
5249 if (!max_work_group_size) {
5250 /* This is a variable group size compute shader,
5251 * compile it for the maximum possible group size.
5252 */
5253 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5254 }
5255 return max_work_group_size;
5256 }
5257
5258 static void create_function(struct si_shader_context *ctx)
5259 {
5260 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5261 struct gallivm_state *gallivm = bld_base->base.gallivm;
5262 struct si_shader *shader = ctx->shader;
5263 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5264 LLVMTypeRef returns[16+32*4];
5265 unsigned i, last_sgpr, num_params, num_return_sgprs;
5266 unsigned num_returns = 0;
5267 unsigned num_prolog_vgprs = 0;
5268
5269 v3i32 = LLVMVectorType(ctx->i32, 3);
5270
5271 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5272 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5273 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5274 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5275 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5276
5277 switch (ctx->type) {
5278 case PIPE_SHADER_VERTEX:
5279 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5280 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5281 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5282 params[SI_PARAM_DRAWID] = ctx->i32;
5283 num_params = SI_PARAM_DRAWID+1;
5284
5285 if (shader->key.as_es) {
5286 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5287 } else if (shader->key.as_ls) {
5288 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5289 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5290 } else {
5291 if (shader->is_gs_copy_shader) {
5292 num_params = SI_PARAM_RW_BUFFERS+1;
5293 } else {
5294 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5295 num_params = SI_PARAM_VS_STATE_BITS+1;
5296 }
5297
5298 /* The locations of the other parameters are assigned dynamically. */
5299 declare_streamout_params(ctx, &shader->selector->so,
5300 params, ctx->i32, &num_params);
5301 }
5302
5303 last_sgpr = num_params-1;
5304
5305 /* VGPRs */
5306 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5307 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5308 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5309 params[ctx->param_instance_id = num_params++] = ctx->i32;
5310
5311 if (!shader->is_gs_copy_shader) {
5312 /* Vertex load indices. */
5313 ctx->param_vertex_index0 = num_params;
5314
5315 for (i = 0; i < shader->selector->info.num_inputs; i++)
5316 params[num_params++] = ctx->i32;
5317
5318 num_prolog_vgprs += shader->selector->info.num_inputs;
5319
5320 /* PrimitiveID output. */
5321 if (!shader->key.as_es && !shader->key.as_ls)
5322 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5323 returns[num_returns++] = ctx->f32;
5324 }
5325 break;
5326
5327 case PIPE_SHADER_TESS_CTRL:
5328 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5329 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5330 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5331 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5332 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5333 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5334 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5335
5336 /* VGPRs */
5337 params[SI_PARAM_PATCH_ID] = ctx->i32;
5338 params[SI_PARAM_REL_IDS] = ctx->i32;
5339 num_params = SI_PARAM_REL_IDS+1;
5340
5341 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5342 * placed after the user SGPRs.
5343 */
5344 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5345 returns[num_returns++] = ctx->i32; /* SGPRs */
5346
5347 for (i = 0; i < 3; i++)
5348 returns[num_returns++] = ctx->f32; /* VGPRs */
5349 break;
5350
5351 case PIPE_SHADER_TESS_EVAL:
5352 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5353 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5354
5355 if (shader->key.as_es) {
5356 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5357 params[num_params++] = ctx->i32;
5358 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5359 } else {
5360 params[num_params++] = ctx->i32;
5361 declare_streamout_params(ctx, &shader->selector->so,
5362 params, ctx->i32, &num_params);
5363 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5364 }
5365 last_sgpr = num_params - 1;
5366
5367 /* VGPRs */
5368 params[ctx->param_tes_u = num_params++] = ctx->f32;
5369 params[ctx->param_tes_v = num_params++] = ctx->f32;
5370 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5371 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5372
5373 /* PrimitiveID output. */
5374 if (!shader->key.as_es)
5375 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5376 returns[num_returns++] = ctx->f32;
5377 break;
5378
5379 case PIPE_SHADER_GEOMETRY:
5380 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5381 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5382 last_sgpr = SI_PARAM_GS_WAVE_ID;
5383
5384 /* VGPRs */
5385 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5386 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5387 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5388 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5389 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5390 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5391 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5392 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5393 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5394 break;
5395
5396 case PIPE_SHADER_FRAGMENT:
5397 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5398 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5399 last_sgpr = SI_PARAM_PRIM_MASK;
5400 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5401 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5402 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5403 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5404 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5405 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5406 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5407 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5408 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5409 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5410 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5411 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5412 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5413 shader->info.face_vgpr_index = 20;
5414 params[SI_PARAM_ANCILLARY] = ctx->i32;
5415 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5416 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5417 num_params = SI_PARAM_POS_FIXED_PT+1;
5418
5419 /* Color inputs from the prolog. */
5420 if (shader->selector->info.colors_read) {
5421 unsigned num_color_elements =
5422 util_bitcount(shader->selector->info.colors_read);
5423
5424 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5425 for (i = 0; i < num_color_elements; i++)
5426 params[num_params++] = ctx->f32;
5427
5428 num_prolog_vgprs += num_color_elements;
5429 }
5430
5431 /* Outputs for the epilog. */
5432 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5433 num_returns =
5434 num_return_sgprs +
5435 util_bitcount(shader->selector->info.colors_written) * 4 +
5436 shader->selector->info.writes_z +
5437 shader->selector->info.writes_stencil +
5438 shader->selector->info.writes_samplemask +
5439 1 /* SampleMaskIn */;
5440
5441 num_returns = MAX2(num_returns,
5442 num_return_sgprs +
5443 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5444
5445 for (i = 0; i < num_return_sgprs; i++)
5446 returns[i] = ctx->i32;
5447 for (; i < num_returns; i++)
5448 returns[i] = ctx->f32;
5449 break;
5450
5451 case PIPE_SHADER_COMPUTE:
5452 params[SI_PARAM_GRID_SIZE] = v3i32;
5453 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5454 params[SI_PARAM_BLOCK_ID] = v3i32;
5455 last_sgpr = SI_PARAM_BLOCK_ID;
5456
5457 params[SI_PARAM_THREAD_ID] = v3i32;
5458 num_params = SI_PARAM_THREAD_ID + 1;
5459 break;
5460 default:
5461 assert(0 && "unimplemented shader");
5462 return;
5463 }
5464
5465 assert(num_params <= ARRAY_SIZE(params));
5466
5467 si_create_function(ctx, "main", returns, num_returns, params,
5468 num_params, last_sgpr);
5469
5470 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5471 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5472 ctx->separate_prolog) {
5473 si_llvm_add_attribute(ctx->main_fn,
5474 "InitialPSInputAddr",
5475 S_0286D0_PERSP_SAMPLE_ENA(1) |
5476 S_0286D0_PERSP_CENTER_ENA(1) |
5477 S_0286D0_PERSP_CENTROID_ENA(1) |
5478 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5479 S_0286D0_LINEAR_CENTER_ENA(1) |
5480 S_0286D0_LINEAR_CENTROID_ENA(1) |
5481 S_0286D0_FRONT_FACE_ENA(1) |
5482 S_0286D0_POS_FIXED_PT_ENA(1));
5483 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5484 si_llvm_add_attribute(ctx->main_fn,
5485 "amdgpu-max-work-group-size",
5486 si_get_max_workgroup_size(shader));
5487 }
5488
5489 shader->info.num_input_sgprs = 0;
5490 shader->info.num_input_vgprs = 0;
5491
5492 for (i = 0; i <= last_sgpr; ++i)
5493 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5494
5495 for (; i < num_params; ++i)
5496 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5497
5498 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5499 shader->info.num_input_vgprs -= num_prolog_vgprs;
5500
5501 if (!ctx->screen->has_ds_bpermute &&
5502 bld_base->info &&
5503 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5504 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5505 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5506 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5507 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5508 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5509 ctx->lds =
5510 LLVMAddGlobalInAddressSpace(gallivm->module,
5511 LLVMArrayType(ctx->i32, 64),
5512 "ddxy_lds",
5513 LOCAL_ADDR_SPACE);
5514
5515 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5516 ctx->type == PIPE_SHADER_TESS_CTRL)
5517 declare_tess_lds(ctx);
5518 }
5519
5520 /**
5521 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5522 * for later use.
5523 */
5524 static void preload_ring_buffers(struct si_shader_context *ctx)
5525 {
5526 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5527 LLVMBuilderRef builder = gallivm->builder;
5528
5529 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5530 SI_PARAM_RW_BUFFERS);
5531
5532 if ((ctx->type == PIPE_SHADER_VERTEX &&
5533 ctx->shader->key.as_es) ||
5534 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5535 ctx->shader->key.as_es) ||
5536 ctx->type == PIPE_SHADER_GEOMETRY) {
5537 unsigned ring =
5538 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5539 : SI_ES_RING_ESGS;
5540 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5541
5542 ctx->esgs_ring =
5543 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5544 }
5545
5546 if (ctx->shader->is_gs_copy_shader) {
5547 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5548
5549 ctx->gsvs_ring[0] =
5550 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5551 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5552 const struct si_shader_selector *sel = ctx->shader->selector;
5553 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
5554 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5555 LLVMValueRef base_ring;
5556
5557 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5558
5559 /* The conceptual layout of the GSVS ring is
5560 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5561 * but the real memory layout is swizzled across
5562 * threads:
5563 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5564 * t16v0c0 ..
5565 * Override the buffer descriptor accordingly.
5566 */
5567 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5568 uint64_t stream_offset = 0;
5569
5570 for (unsigned stream = 0; stream < 4; ++stream) {
5571 unsigned num_components;
5572 unsigned stride;
5573 unsigned num_records;
5574 LLVMValueRef ring, tmp;
5575
5576 num_components = sel->info.num_stream_output_components[stream];
5577 if (!num_components)
5578 continue;
5579
5580 stride = 4 * num_components * sel->gs_max_out_vertices;
5581
5582 /* Limit on the stride field for <= CIK. */
5583 assert(stride < (1 << 14));
5584
5585 num_records = 64;
5586
5587 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5588 tmp = LLVMBuildExtractElement(builder, ring, uint->zero, "");
5589 tmp = LLVMBuildAdd(builder, tmp,
5590 LLVMConstInt(ctx->i64,
5591 stream_offset, 0), "");
5592 stream_offset += stride * 64;
5593
5594 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->zero, "");
5595 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5596 tmp = LLVMBuildExtractElement(builder, ring, uint->one, "");
5597 tmp = LLVMBuildOr(builder, tmp,
5598 LLVMConstInt(ctx->i32,
5599 S_008F04_STRIDE(stride) |
5600 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5601 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->one, "");
5602 ring = LLVMBuildInsertElement(builder, ring,
5603 LLVMConstInt(ctx->i32, num_records, 0),
5604 LLVMConstInt(ctx->i32, 2, 0), "");
5605 ring = LLVMBuildInsertElement(builder, ring,
5606 LLVMConstInt(ctx->i32,
5607 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5608 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5609 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5610 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5611 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5612 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5613 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5614 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5615 S_008F0C_ADD_TID_ENABLE(1),
5616 0),
5617 LLVMConstInt(ctx->i32, 3, 0), "");
5618 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5619
5620 ctx->gsvs_ring[stream] = ring;
5621 }
5622 }
5623 }
5624
5625 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5626 LLVMValueRef param_rw_buffers,
5627 unsigned param_pos_fixed_pt)
5628 {
5629 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5630 struct gallivm_state *gallivm = bld_base->base.gallivm;
5631 LLVMBuilderRef builder = gallivm->builder;
5632 LLVMValueRef slot, desc, offset, row, bit, address[2];
5633
5634 /* Use the fixed-point gl_FragCoord input.
5635 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5636 * per coordinate to get the repeating effect.
5637 */
5638 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5639 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5640
5641 /* Load the buffer descriptor. */
5642 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5643 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5644
5645 /* The stipple pattern is 32x32, each row has 32 bits. */
5646 offset = LLVMBuildMul(builder, address[1],
5647 LLVMConstInt(ctx->i32, 4, 0), "");
5648 row = buffer_load_const(ctx, desc, offset);
5649 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5650 bit = LLVMBuildLShr(builder, row, address[0], "");
5651 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5652
5653 /* The intrinsic kills the thread if arg < 0. */
5654 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5655 LLVMConstReal(ctx->f32, -1), "");
5656 ac_emit_kill(&ctx->ac, bit);
5657 }
5658
5659 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5660 struct si_shader_config *conf,
5661 unsigned symbol_offset)
5662 {
5663 unsigned i;
5664 const unsigned char *config =
5665 ac_shader_binary_config_start(binary, symbol_offset);
5666 bool really_needs_scratch = false;
5667
5668 /* LLVM adds SGPR spills to the scratch size.
5669 * Find out if we really need the scratch buffer.
5670 */
5671 for (i = 0; i < binary->reloc_count; i++) {
5672 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5673
5674 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5675 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5676 really_needs_scratch = true;
5677 break;
5678 }
5679 }
5680
5681 /* XXX: We may be able to emit some of these values directly rather than
5682 * extracting fields to be emitted later.
5683 */
5684
5685 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5686 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5687 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5688 switch (reg) {
5689 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5690 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5691 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5692 case R_00B848_COMPUTE_PGM_RSRC1:
5693 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5694 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5695 conf->float_mode = G_00B028_FLOAT_MODE(value);
5696 conf->rsrc1 = value;
5697 break;
5698 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5699 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5700 break;
5701 case R_00B84C_COMPUTE_PGM_RSRC2:
5702 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5703 conf->rsrc2 = value;
5704 break;
5705 case R_0286CC_SPI_PS_INPUT_ENA:
5706 conf->spi_ps_input_ena = value;
5707 break;
5708 case R_0286D0_SPI_PS_INPUT_ADDR:
5709 conf->spi_ps_input_addr = value;
5710 break;
5711 case R_0286E8_SPI_TMPRING_SIZE:
5712 case R_00B860_COMPUTE_TMPRING_SIZE:
5713 /* WAVESIZE is in units of 256 dwords. */
5714 if (really_needs_scratch)
5715 conf->scratch_bytes_per_wave =
5716 G_00B860_WAVESIZE(value) * 256 * 4;
5717 break;
5718 case 0x4: /* SPILLED_SGPRS */
5719 conf->spilled_sgprs = value;
5720 break;
5721 case 0x8: /* SPILLED_VGPRS */
5722 conf->spilled_vgprs = value;
5723 break;
5724 default:
5725 {
5726 static bool printed;
5727
5728 if (!printed) {
5729 fprintf(stderr, "Warning: LLVM emitted unknown "
5730 "config register: 0x%x\n", reg);
5731 printed = true;
5732 }
5733 }
5734 break;
5735 }
5736 }
5737
5738 if (!conf->spi_ps_input_addr)
5739 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5740 }
5741
5742 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5743 struct si_shader *shader,
5744 struct si_shader_config *config,
5745 uint64_t scratch_va)
5746 {
5747 unsigned i;
5748 uint32_t scratch_rsrc_dword0 = scratch_va;
5749 uint32_t scratch_rsrc_dword1 =
5750 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5751
5752 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5753 * correctly.
5754 */
5755 if (HAVE_LLVM >= 0x0309)
5756 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5757 else
5758 scratch_rsrc_dword1 |=
5759 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5760
5761 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5762 const struct ac_shader_reloc *reloc =
5763 &shader->binary.relocs[i];
5764 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5765 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5766 &scratch_rsrc_dword0, 4);
5767 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5768 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5769 &scratch_rsrc_dword1, 4);
5770 }
5771 }
5772 }
5773
5774 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5775 {
5776 unsigned size = shader->binary.code_size;
5777
5778 if (shader->prolog)
5779 size += shader->prolog->binary.code_size;
5780 if (shader->epilog)
5781 size += shader->epilog->binary.code_size;
5782 return size;
5783 }
5784
5785 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5786 {
5787 const struct ac_shader_binary *prolog =
5788 shader->prolog ? &shader->prolog->binary : NULL;
5789 const struct ac_shader_binary *epilog =
5790 shader->epilog ? &shader->epilog->binary : NULL;
5791 const struct ac_shader_binary *mainb = &shader->binary;
5792 unsigned bo_size = si_get_shader_binary_size(shader) +
5793 (!epilog ? mainb->rodata_size : 0);
5794 unsigned char *ptr;
5795
5796 assert(!prolog || !prolog->rodata_size);
5797 assert((!prolog && !epilog) || !mainb->rodata_size);
5798 assert(!epilog || !epilog->rodata_size);
5799
5800 r600_resource_reference(&shader->bo, NULL);
5801 shader->bo = (struct r600_resource*)
5802 pipe_buffer_create(&sscreen->b.b, 0,
5803 PIPE_USAGE_IMMUTABLE,
5804 align(bo_size, SI_CPDMA_ALIGNMENT));
5805 if (!shader->bo)
5806 return -ENOMEM;
5807
5808 /* Upload. */
5809 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5810 PIPE_TRANSFER_READ_WRITE);
5811
5812 if (prolog) {
5813 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5814 ptr += prolog->code_size;
5815 }
5816
5817 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5818 ptr += mainb->code_size;
5819
5820 if (epilog)
5821 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5822 else if (mainb->rodata_size > 0)
5823 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5824
5825 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5826 return 0;
5827 }
5828
5829 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5830 struct pipe_debug_callback *debug,
5831 const char *name, FILE *file)
5832 {
5833 char *line, *p;
5834 unsigned i, count;
5835
5836 if (binary->disasm_string) {
5837 fprintf(file, "Shader %s disassembly:\n", name);
5838 fprintf(file, "%s", binary->disasm_string);
5839
5840 if (debug && debug->debug_message) {
5841 /* Very long debug messages are cut off, so send the
5842 * disassembly one line at a time. This causes more
5843 * overhead, but on the plus side it simplifies
5844 * parsing of resulting logs.
5845 */
5846 pipe_debug_message(debug, SHADER_INFO,
5847 "Shader Disassembly Begin");
5848
5849 line = binary->disasm_string;
5850 while (*line) {
5851 p = util_strchrnul(line, '\n');
5852 count = p - line;
5853
5854 if (count) {
5855 pipe_debug_message(debug, SHADER_INFO,
5856 "%.*s", count, line);
5857 }
5858
5859 if (!*p)
5860 break;
5861 line = p + 1;
5862 }
5863
5864 pipe_debug_message(debug, SHADER_INFO,
5865 "Shader Disassembly End");
5866 }
5867 } else {
5868 fprintf(file, "Shader %s binary:\n", name);
5869 for (i = 0; i < binary->code_size; i += 4) {
5870 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5871 binary->code[i + 3], binary->code[i + 2],
5872 binary->code[i + 1], binary->code[i]);
5873 }
5874 }
5875 }
5876
5877 static void si_shader_dump_stats(struct si_screen *sscreen,
5878 struct si_shader *shader,
5879 struct pipe_debug_callback *debug,
5880 unsigned processor,
5881 FILE *file,
5882 bool check_debug_option)
5883 {
5884 struct si_shader_config *conf = &shader->config;
5885 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5886 unsigned code_size = si_get_shader_binary_size(shader);
5887 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5888 unsigned lds_per_wave = 0;
5889 unsigned max_simd_waves = 10;
5890
5891 /* Compute LDS usage for PS. */
5892 switch (processor) {
5893 case PIPE_SHADER_FRAGMENT:
5894 /* The minimum usage per wave is (num_inputs * 48). The maximum
5895 * usage is (num_inputs * 48 * 16).
5896 * We can get anything in between and it varies between waves.
5897 *
5898 * The 48 bytes per input for a single primitive is equal to
5899 * 4 bytes/component * 4 components/input * 3 points.
5900 *
5901 * Other stages don't know the size at compile time or don't
5902 * allocate LDS per wave, but instead they do it per thread group.
5903 */
5904 lds_per_wave = conf->lds_size * lds_increment +
5905 align(num_inputs * 48, lds_increment);
5906 break;
5907 case PIPE_SHADER_COMPUTE:
5908 if (shader->selector) {
5909 unsigned max_workgroup_size =
5910 si_get_max_workgroup_size(shader);
5911 lds_per_wave = (conf->lds_size * lds_increment) /
5912 DIV_ROUND_UP(max_workgroup_size, 64);
5913 }
5914 break;
5915 }
5916
5917 /* Compute the per-SIMD wave counts. */
5918 if (conf->num_sgprs) {
5919 if (sscreen->b.chip_class >= VI)
5920 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5921 else
5922 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5923 }
5924
5925 if (conf->num_vgprs)
5926 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5927
5928 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5929 * 16KB makes some SIMDs unoccupied). */
5930 if (lds_per_wave)
5931 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5932
5933 if (!check_debug_option ||
5934 r600_can_dump_shader(&sscreen->b, processor)) {
5935 if (processor == PIPE_SHADER_FRAGMENT) {
5936 fprintf(file, "*** SHADER CONFIG ***\n"
5937 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5938 "SPI_PS_INPUT_ENA = 0x%04x\n",
5939 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5940 }
5941
5942 fprintf(file, "*** SHADER STATS ***\n"
5943 "SGPRS: %d\n"
5944 "VGPRS: %d\n"
5945 "Spilled SGPRs: %d\n"
5946 "Spilled VGPRs: %d\n"
5947 "Private memory VGPRs: %d\n"
5948 "Code Size: %d bytes\n"
5949 "LDS: %d blocks\n"
5950 "Scratch: %d bytes per wave\n"
5951 "Max Waves: %d\n"
5952 "********************\n\n\n",
5953 conf->num_sgprs, conf->num_vgprs,
5954 conf->spilled_sgprs, conf->spilled_vgprs,
5955 conf->private_mem_vgprs, code_size,
5956 conf->lds_size, conf->scratch_bytes_per_wave,
5957 max_simd_waves);
5958 }
5959
5960 pipe_debug_message(debug, SHADER_INFO,
5961 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5962 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5963 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5964 conf->num_sgprs, conf->num_vgprs, code_size,
5965 conf->lds_size, conf->scratch_bytes_per_wave,
5966 max_simd_waves, conf->spilled_sgprs,
5967 conf->spilled_vgprs, conf->private_mem_vgprs);
5968 }
5969
5970 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
5971 {
5972 switch (processor) {
5973 case PIPE_SHADER_VERTEX:
5974 if (shader->key.as_es)
5975 return "Vertex Shader as ES";
5976 else if (shader->key.as_ls)
5977 return "Vertex Shader as LS";
5978 else
5979 return "Vertex Shader as VS";
5980 case PIPE_SHADER_TESS_CTRL:
5981 return "Tessellation Control Shader";
5982 case PIPE_SHADER_TESS_EVAL:
5983 if (shader->key.as_es)
5984 return "Tessellation Evaluation Shader as ES";
5985 else
5986 return "Tessellation Evaluation Shader as VS";
5987 case PIPE_SHADER_GEOMETRY:
5988 if (shader->is_gs_copy_shader)
5989 return "GS Copy Shader as VS";
5990 else
5991 return "Geometry Shader";
5992 case PIPE_SHADER_FRAGMENT:
5993 return "Pixel Shader";
5994 case PIPE_SHADER_COMPUTE:
5995 return "Compute Shader";
5996 default:
5997 return "Unknown Shader";
5998 }
5999 }
6000
6001 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6002 struct pipe_debug_callback *debug, unsigned processor,
6003 FILE *file, bool check_debug_option)
6004 {
6005 if (!check_debug_option ||
6006 r600_can_dump_shader(&sscreen->b, processor))
6007 si_dump_shader_key(processor, &shader->key, file);
6008
6009 if (!check_debug_option && shader->binary.llvm_ir_string) {
6010 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6011 si_get_shader_name(shader, processor));
6012 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6013 }
6014
6015 if (!check_debug_option ||
6016 (r600_can_dump_shader(&sscreen->b, processor) &&
6017 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6018 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6019
6020 if (shader->prolog)
6021 si_shader_dump_disassembly(&shader->prolog->binary,
6022 debug, "prolog", file);
6023
6024 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6025
6026 if (shader->epilog)
6027 si_shader_dump_disassembly(&shader->epilog->binary,
6028 debug, "epilog", file);
6029 fprintf(file, "\n");
6030 }
6031
6032 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6033 check_debug_option);
6034 }
6035
6036 int si_compile_llvm(struct si_screen *sscreen,
6037 struct ac_shader_binary *binary,
6038 struct si_shader_config *conf,
6039 LLVMTargetMachineRef tm,
6040 LLVMModuleRef mod,
6041 struct pipe_debug_callback *debug,
6042 unsigned processor,
6043 const char *name)
6044 {
6045 int r = 0;
6046 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6047
6048 if (r600_can_dump_shader(&sscreen->b, processor)) {
6049 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6050
6051 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6052 fprintf(stderr, "%s LLVM IR:\n\n", name);
6053 ac_dump_module(mod);
6054 fprintf(stderr, "\n");
6055 }
6056 }
6057
6058 if (sscreen->record_llvm_ir) {
6059 char *ir = LLVMPrintModuleToString(mod);
6060 binary->llvm_ir_string = strdup(ir);
6061 LLVMDisposeMessage(ir);
6062 }
6063
6064 if (!si_replace_shader(count, binary)) {
6065 r = si_llvm_compile(mod, binary, tm, debug);
6066 if (r)
6067 return r;
6068 }
6069
6070 si_shader_binary_read_config(binary, conf, 0);
6071
6072 /* Enable 64-bit and 16-bit denormals, because there is no performance
6073 * cost.
6074 *
6075 * If denormals are enabled, all floating-point output modifiers are
6076 * ignored.
6077 *
6078 * Don't enable denormals for 32-bit floats, because:
6079 * - Floating-point output modifiers would be ignored by the hw.
6080 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6081 * have to stop using those.
6082 * - SI & CI would be very slow.
6083 */
6084 conf->float_mode |= V_00B028_FP_64_DENORMS;
6085
6086 FREE(binary->config);
6087 FREE(binary->global_symbol_offsets);
6088 binary->config = NULL;
6089 binary->global_symbol_offsets = NULL;
6090
6091 /* Some shaders can't have rodata because their binaries can be
6092 * concatenated.
6093 */
6094 if (binary->rodata_size &&
6095 (processor == PIPE_SHADER_VERTEX ||
6096 processor == PIPE_SHADER_TESS_CTRL ||
6097 processor == PIPE_SHADER_TESS_EVAL ||
6098 processor == PIPE_SHADER_FRAGMENT)) {
6099 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6100 return -EINVAL;
6101 }
6102
6103 return r;
6104 }
6105
6106 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6107 {
6108 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6109 LLVMBuildRetVoid(ctx->gallivm.builder);
6110 else
6111 LLVMBuildRet(ctx->gallivm.builder, ret);
6112 }
6113
6114 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6115 struct si_shader *
6116 si_generate_gs_copy_shader(struct si_screen *sscreen,
6117 LLVMTargetMachineRef tm,
6118 struct si_shader_selector *gs_selector,
6119 struct pipe_debug_callback *debug)
6120 {
6121 struct si_shader_context ctx;
6122 struct si_shader *shader;
6123 struct gallivm_state *gallivm = &ctx.gallivm;
6124 LLVMBuilderRef builder;
6125 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6126 struct lp_build_context *uint = &bld_base->uint_bld;
6127 struct si_shader_output_values *outputs;
6128 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6129 int i, r;
6130
6131 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6132
6133 if (!outputs)
6134 return NULL;
6135
6136 shader = CALLOC_STRUCT(si_shader);
6137 if (!shader) {
6138 FREE(outputs);
6139 return NULL;
6140 }
6141
6142
6143 shader->selector = gs_selector;
6144 shader->is_gs_copy_shader = true;
6145
6146 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6147 ctx.type = PIPE_SHADER_VERTEX;
6148
6149 builder = gallivm->builder;
6150
6151 create_function(&ctx);
6152 preload_ring_buffers(&ctx);
6153
6154 LLVMValueRef voffset =
6155 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6156 ctx.param_vertex_id), 4);
6157
6158 /* Fetch the vertex stream ID.*/
6159 LLVMValueRef stream_id;
6160
6161 if (gs_selector->so.num_outputs)
6162 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6163 else
6164 stream_id = uint->zero;
6165
6166 /* Fill in output information. */
6167 for (i = 0; i < gsinfo->num_outputs; ++i) {
6168 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6169 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6170
6171 for (int chan = 0; chan < 4; chan++) {
6172 outputs[i].vertex_stream[chan] =
6173 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6174 }
6175 }
6176
6177 LLVMBasicBlockRef end_bb;
6178 LLVMValueRef switch_inst;
6179
6180 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6181 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6182
6183 for (int stream = 0; stream < 4; stream++) {
6184 LLVMBasicBlockRef bb;
6185 unsigned offset;
6186
6187 if (!gsinfo->num_stream_output_components[stream])
6188 continue;
6189
6190 if (stream > 0 && !gs_selector->so.num_outputs)
6191 continue;
6192
6193 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6194 LLVMAddCase(switch_inst, lp_build_const_int32(gallivm, stream), bb);
6195 LLVMPositionBuilderAtEnd(builder, bb);
6196
6197 /* Fetch vertex data from GSVS ring */
6198 offset = 0;
6199 for (i = 0; i < gsinfo->num_outputs; ++i) {
6200 for (unsigned chan = 0; chan < 4; chan++) {
6201 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6202 outputs[i].vertex_stream[chan] != stream) {
6203 outputs[i].values[chan] = ctx.bld_base.base.undef;
6204 continue;
6205 }
6206
6207 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6208 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6209 offset++;
6210
6211 outputs[i].values[chan] =
6212 ac_build_buffer_load(&ctx.ac,
6213 ctx.gsvs_ring[0], 1,
6214 uint->zero, voffset,
6215 soffset, 0, 1, 1, true);
6216 }
6217 }
6218
6219 /* Streamout and exports. */
6220 if (gs_selector->so.num_outputs) {
6221 si_llvm_emit_streamout(&ctx, outputs,
6222 gsinfo->num_outputs,
6223 stream);
6224 }
6225
6226 if (stream == 0)
6227 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6228
6229 LLVMBuildBr(builder, end_bb);
6230 }
6231
6232 LLVMPositionBuilderAtEnd(builder, end_bb);
6233
6234 LLVMBuildRetVoid(gallivm->builder);
6235
6236 /* Dump LLVM IR before any optimization passes */
6237 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6238 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6239 ac_dump_module(bld_base->base.gallivm->module);
6240
6241 si_llvm_finalize_module(&ctx,
6242 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6243
6244 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6245 &ctx.shader->config, ctx.tm,
6246 bld_base->base.gallivm->module,
6247 debug, PIPE_SHADER_GEOMETRY,
6248 "GS Copy Shader");
6249 if (!r) {
6250 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6251 fprintf(stderr, "GS Copy Shader:\n");
6252 si_shader_dump(sscreen, ctx.shader, debug,
6253 PIPE_SHADER_GEOMETRY, stderr, true);
6254 r = si_shader_binary_upload(sscreen, ctx.shader);
6255 }
6256
6257 si_llvm_dispose(&ctx);
6258
6259 FREE(outputs);
6260
6261 if (r != 0) {
6262 FREE(shader);
6263 shader = NULL;
6264 }
6265 return shader;
6266 }
6267
6268 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6269 FILE *f)
6270 {
6271 int i;
6272
6273 fprintf(f, "SHADER KEY\n");
6274
6275 switch (shader) {
6276 case PIPE_SHADER_VERTEX:
6277 fprintf(f, " part.vs.prolog.instance_divisors = {");
6278 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6279 fprintf(f, !i ? "%u" : ", %u",
6280 key->part.vs.prolog.instance_divisors[i]);
6281 fprintf(f, "}\n");
6282 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6283 fprintf(f, " as_es = %u\n", key->as_es);
6284 fprintf(f, " as_ls = %u\n", key->as_ls);
6285
6286 fprintf(f, " mono.vs.fix_fetch = {");
6287 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6288 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6289 fprintf(f, "}\n");
6290 break;
6291
6292 case PIPE_SHADER_TESS_CTRL:
6293 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6294 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6295 break;
6296
6297 case PIPE_SHADER_TESS_EVAL:
6298 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6299 fprintf(f, " as_es = %u\n", key->as_es);
6300 break;
6301
6302 case PIPE_SHADER_GEOMETRY:
6303 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6304 break;
6305
6306 case PIPE_SHADER_COMPUTE:
6307 break;
6308
6309 case PIPE_SHADER_FRAGMENT:
6310 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6311 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6312 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6313 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6314 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6315 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6316 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6317 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6318 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6319 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6320 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6321 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6322 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6323 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6324 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6325 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6326 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6327 break;
6328
6329 default:
6330 assert(0);
6331 }
6332
6333 if ((shader == PIPE_SHADER_GEOMETRY ||
6334 shader == PIPE_SHADER_TESS_EVAL ||
6335 shader == PIPE_SHADER_VERTEX) &&
6336 !key->as_es && !key->as_ls) {
6337 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6338 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6339 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6340 }
6341 }
6342
6343 static void si_init_shader_ctx(struct si_shader_context *ctx,
6344 struct si_screen *sscreen,
6345 struct si_shader *shader,
6346 LLVMTargetMachineRef tm)
6347 {
6348 struct lp_build_tgsi_context *bld_base;
6349 struct lp_build_tgsi_action tmpl = {};
6350
6351 si_llvm_context_init(ctx, sscreen, shader, tm,
6352 (shader && shader->selector) ? &shader->selector->info : NULL,
6353 (shader && shader->selector) ? shader->selector->tokens : NULL);
6354
6355 bld_base = &ctx->bld_base;
6356 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6357
6358 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6359 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6360 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6361
6362 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6363 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6364 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6365 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6366 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6367 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6368 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6369 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6370 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6371 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6372 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6373 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6374 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6375 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6376
6377 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6378 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6379 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6380 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6381 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6382 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6383
6384 tmpl.fetch_args = atomic_fetch_args;
6385 tmpl.emit = atomic_emit;
6386 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6387 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6388 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6389 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6390 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6391 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6392 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6393 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6394 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6395 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6396 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6397 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6398 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6399 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6400 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6401 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6402 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6403 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6404 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6405 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6406
6407 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6408
6409 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6410 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6411 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6412 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6413
6414 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6415 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6416 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6417 }
6418
6419 /* Return true if the PARAM export has been eliminated. */
6420 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6421 LLVMValueRef inst, unsigned offset)
6422 {
6423 struct si_shader *shader = ctx->shader;
6424 unsigned num_outputs = shader->selector->info.num_outputs;
6425 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6426 bool is_zero[4] = {}, is_one[4] = {};
6427
6428 for (i = 0; i < 4; i++) {
6429 LLVMBool loses_info;
6430 LLVMValueRef p = LLVMGetOperand(inst, (HAVE_LLVM >= 0x0500 ? 2 : 5) + i);
6431
6432 /* It's a constant expression. Undef outputs are eliminated too. */
6433 if (LLVMIsUndef(p)) {
6434 is_zero[i] = true;
6435 is_one[i] = true;
6436 } else if (LLVMIsAConstantFP(p)) {
6437 double a = LLVMConstRealGetDouble(p, &loses_info);
6438
6439 if (a == 0)
6440 is_zero[i] = true;
6441 else if (a == 1)
6442 is_one[i] = true;
6443 else
6444 return false; /* other constant */
6445 } else
6446 return false;
6447 }
6448
6449 /* Only certain combinations of 0 and 1 can be eliminated. */
6450 if (is_zero[0] && is_zero[1] && is_zero[2])
6451 default_val = is_zero[3] ? 0 : 1;
6452 else if (is_one[0] && is_one[1] && is_one[2])
6453 default_val = is_zero[3] ? 2 : 3;
6454 else
6455 return false;
6456
6457 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6458 LLVMInstructionEraseFromParent(inst);
6459
6460 /* Change OFFSET to DEFAULT_VAL. */
6461 for (i = 0; i < num_outputs; i++) {
6462 if (shader->info.vs_output_param_offset[i] == offset) {
6463 shader->info.vs_output_param_offset[i] =
6464 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6465 break;
6466 }
6467 }
6468 return true;
6469 }
6470
6471 struct si_vs_exports {
6472 unsigned num;
6473 unsigned offset[SI_MAX_VS_OUTPUTS];
6474 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6475 };
6476
6477 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6478 {
6479 struct si_shader *shader = ctx->shader;
6480 struct tgsi_shader_info *info = &shader->selector->info;
6481 LLVMBasicBlockRef bb;
6482 struct si_vs_exports exports;
6483 bool removed_any = false;
6484
6485 exports.num = 0;
6486
6487 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6488 ctx->type == PIPE_SHADER_COMPUTE ||
6489 shader->key.as_es ||
6490 shader->key.as_ls)
6491 return;
6492
6493 /* Process all LLVM instructions. */
6494 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6495 while (bb) {
6496 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6497
6498 while (inst) {
6499 LLVMValueRef cur = inst;
6500 inst = LLVMGetNextInstruction(inst);
6501
6502 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6503 continue;
6504
6505 LLVMValueRef callee = lp_get_called_value(cur);
6506
6507 if (!lp_is_function(callee))
6508 continue;
6509
6510 const char *name = LLVMGetValueName(callee);
6511 unsigned num_args = LLVMCountParams(callee);
6512
6513 /* Check if this is an export instruction. */
6514 if ((num_args != 9 && num_args != 8) ||
6515 (strcmp(name, "llvm.SI.export") &&
6516 strcmp(name, "llvm.amdgcn.exp.")))
6517 continue;
6518
6519 LLVMValueRef arg = LLVMGetOperand(cur, HAVE_LLVM >= 0x0500 ? 0 : 3);
6520 unsigned target = LLVMConstIntGetZExtValue(arg);
6521
6522 if (target < V_008DFC_SQ_EXP_PARAM)
6523 continue;
6524
6525 target -= V_008DFC_SQ_EXP_PARAM;
6526
6527 /* Eliminate constant value PARAM exports. */
6528 if (si_eliminate_const_output(ctx, cur, target)) {
6529 removed_any = true;
6530 } else {
6531 exports.offset[exports.num] = target;
6532 exports.inst[exports.num] = cur;
6533 exports.num++;
6534 }
6535 }
6536 bb = LLVMGetNextBasicBlock(bb);
6537 }
6538
6539 /* Remove holes in export memory due to removed PARAM exports.
6540 * This is done by renumbering all PARAM exports.
6541 */
6542 if (removed_any) {
6543 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6544 unsigned new_count = 0;
6545 unsigned out, i;
6546
6547 /* Make a copy of the offsets. We need the old version while
6548 * we are modifying some of them. */
6549 assert(sizeof(current_offset) ==
6550 sizeof(shader->info.vs_output_param_offset));
6551 memcpy(current_offset, shader->info.vs_output_param_offset,
6552 sizeof(current_offset));
6553
6554 for (i = 0; i < exports.num; i++) {
6555 unsigned offset = exports.offset[i];
6556
6557 for (out = 0; out < info->num_outputs; out++) {
6558 if (current_offset[out] != offset)
6559 continue;
6560
6561 LLVMSetOperand(exports.inst[i], 3,
6562 LLVMConstInt(ctx->i32,
6563 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6564 shader->info.vs_output_param_offset[out] = new_count;
6565 new_count++;
6566 break;
6567 }
6568 }
6569 shader->info.nr_param_exports = new_count;
6570 }
6571 }
6572
6573 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6574 {
6575 ctx->shader->config.private_mem_vgprs = 0;
6576
6577 /* Process all LLVM instructions. */
6578 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6579 while (bb) {
6580 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6581
6582 while (next) {
6583 LLVMValueRef inst = next;
6584 next = LLVMGetNextInstruction(next);
6585
6586 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6587 continue;
6588
6589 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6590 /* No idea why LLVM aligns allocas to 4 elements. */
6591 unsigned alignment = LLVMGetAlignment(inst);
6592 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6593 ctx->shader->config.private_mem_vgprs += dw_size;
6594 }
6595 bb = LLVMGetNextBasicBlock(bb);
6596 }
6597 }
6598
6599 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6600 struct si_shader *shader)
6601 {
6602 struct si_shader_selector *sel = shader->selector;
6603 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6604
6605 switch (ctx->type) {
6606 case PIPE_SHADER_VERTEX:
6607 ctx->load_input = declare_input_vs;
6608 if (shader->key.as_ls)
6609 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6610 else if (shader->key.as_es)
6611 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6612 else
6613 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6614 break;
6615 case PIPE_SHADER_TESS_CTRL:
6616 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6617 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6618 bld_base->emit_store = store_output_tcs;
6619 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6620 break;
6621 case PIPE_SHADER_TESS_EVAL:
6622 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6623 if (shader->key.as_es)
6624 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6625 else
6626 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6627 break;
6628 case PIPE_SHADER_GEOMETRY:
6629 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6630 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6631 break;
6632 case PIPE_SHADER_FRAGMENT:
6633 ctx->load_input = declare_input_fs;
6634 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6635 break;
6636 case PIPE_SHADER_COMPUTE:
6637 ctx->declare_memory_region = declare_compute_memory;
6638 break;
6639 default:
6640 assert(!"Unsupported shader type");
6641 return false;
6642 }
6643
6644 create_function(ctx);
6645 preload_ring_buffers(ctx);
6646
6647 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6648 int i;
6649 for (i = 0; i < 4; i++) {
6650 ctx->gs_next_vertex[i] =
6651 lp_build_alloca(bld_base->base.gallivm,
6652 ctx->i32, "");
6653 }
6654 }
6655
6656 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6657 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6658 return false;
6659 }
6660
6661 si_llvm_build_ret(ctx, ctx->return_value);
6662 return true;
6663 }
6664
6665 /**
6666 * Compute the VS prolog key, which contains all the information needed to
6667 * build the VS prolog function, and set shader->info bits where needed.
6668 */
6669 static void si_get_vs_prolog_key(struct si_shader *shader,
6670 union si_shader_part_key *key)
6671 {
6672 struct tgsi_shader_info *info = &shader->selector->info;
6673
6674 memset(key, 0, sizeof(*key));
6675 key->vs_prolog.states = shader->key.part.vs.prolog;
6676 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6677 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6678
6679 /* Set the instanceID flag. */
6680 for (unsigned i = 0; i < info->num_inputs; i++)
6681 if (key->vs_prolog.states.instance_divisors[i])
6682 shader->info.uses_instanceid = true;
6683 }
6684
6685 /**
6686 * Compute the VS epilog key, which contains all the information needed to
6687 * build the VS epilog function, and set the PrimitiveID output offset.
6688 */
6689 static void si_get_vs_epilog_key(struct si_shader *shader,
6690 struct si_vs_epilog_bits *states,
6691 union si_shader_part_key *key)
6692 {
6693 memset(key, 0, sizeof(*key));
6694 key->vs_epilog.states = *states;
6695
6696 /* Set up the PrimitiveID output. */
6697 if (shader->key.part.vs.epilog.export_prim_id) {
6698 unsigned index = shader->selector->info.num_outputs;
6699 unsigned offset = shader->info.nr_param_exports++;
6700
6701 key->vs_epilog.prim_id_param_offset = offset;
6702 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6703 shader->info.vs_output_param_offset[index] = offset;
6704 }
6705 }
6706
6707 /**
6708 * Compute the PS prolog key, which contains all the information needed to
6709 * build the PS prolog function, and set related bits in shader->config.
6710 */
6711 static void si_get_ps_prolog_key(struct si_shader *shader,
6712 union si_shader_part_key *key,
6713 bool separate_prolog)
6714 {
6715 struct tgsi_shader_info *info = &shader->selector->info;
6716
6717 memset(key, 0, sizeof(*key));
6718 key->ps_prolog.states = shader->key.part.ps.prolog;
6719 key->ps_prolog.colors_read = info->colors_read;
6720 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6721 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6722 key->ps_prolog.wqm = info->uses_derivatives &&
6723 (key->ps_prolog.colors_read ||
6724 key->ps_prolog.states.force_persp_sample_interp ||
6725 key->ps_prolog.states.force_linear_sample_interp ||
6726 key->ps_prolog.states.force_persp_center_interp ||
6727 key->ps_prolog.states.force_linear_center_interp ||
6728 key->ps_prolog.states.bc_optimize_for_persp ||
6729 key->ps_prolog.states.bc_optimize_for_linear);
6730
6731 if (info->colors_read) {
6732 unsigned *color = shader->selector->color_attr_index;
6733
6734 if (shader->key.part.ps.prolog.color_two_side) {
6735 /* BCOLORs are stored after the last input. */
6736 key->ps_prolog.num_interp_inputs = info->num_inputs;
6737 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6738 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6739 }
6740
6741 for (unsigned i = 0; i < 2; i++) {
6742 unsigned interp = info->input_interpolate[color[i]];
6743 unsigned location = info->input_interpolate_loc[color[i]];
6744
6745 if (!(info->colors_read & (0xf << i*4)))
6746 continue;
6747
6748 key->ps_prolog.color_attr_index[i] = color[i];
6749
6750 if (shader->key.part.ps.prolog.flatshade_colors &&
6751 interp == TGSI_INTERPOLATE_COLOR)
6752 interp = TGSI_INTERPOLATE_CONSTANT;
6753
6754 switch (interp) {
6755 case TGSI_INTERPOLATE_CONSTANT:
6756 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6757 break;
6758 case TGSI_INTERPOLATE_PERSPECTIVE:
6759 case TGSI_INTERPOLATE_COLOR:
6760 /* Force the interpolation location for colors here. */
6761 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6762 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6763 if (shader->key.part.ps.prolog.force_persp_center_interp)
6764 location = TGSI_INTERPOLATE_LOC_CENTER;
6765
6766 switch (location) {
6767 case TGSI_INTERPOLATE_LOC_SAMPLE:
6768 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6769 shader->config.spi_ps_input_ena |=
6770 S_0286CC_PERSP_SAMPLE_ENA(1);
6771 break;
6772 case TGSI_INTERPOLATE_LOC_CENTER:
6773 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6774 shader->config.spi_ps_input_ena |=
6775 S_0286CC_PERSP_CENTER_ENA(1);
6776 break;
6777 case TGSI_INTERPOLATE_LOC_CENTROID:
6778 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6779 shader->config.spi_ps_input_ena |=
6780 S_0286CC_PERSP_CENTROID_ENA(1);
6781 break;
6782 default:
6783 assert(0);
6784 }
6785 break;
6786 case TGSI_INTERPOLATE_LINEAR:
6787 /* Force the interpolation location for colors here. */
6788 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6789 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6790 if (shader->key.part.ps.prolog.force_linear_center_interp)
6791 location = TGSI_INTERPOLATE_LOC_CENTER;
6792
6793 /* The VGPR assignment for non-monolithic shaders
6794 * works because InitialPSInputAddr is set on the
6795 * main shader and PERSP_PULL_MODEL is never used.
6796 */
6797 switch (location) {
6798 case TGSI_INTERPOLATE_LOC_SAMPLE:
6799 key->ps_prolog.color_interp_vgpr_index[i] =
6800 separate_prolog ? 6 : 9;
6801 shader->config.spi_ps_input_ena |=
6802 S_0286CC_LINEAR_SAMPLE_ENA(1);
6803 break;
6804 case TGSI_INTERPOLATE_LOC_CENTER:
6805 key->ps_prolog.color_interp_vgpr_index[i] =
6806 separate_prolog ? 8 : 11;
6807 shader->config.spi_ps_input_ena |=
6808 S_0286CC_LINEAR_CENTER_ENA(1);
6809 break;
6810 case TGSI_INTERPOLATE_LOC_CENTROID:
6811 key->ps_prolog.color_interp_vgpr_index[i] =
6812 separate_prolog ? 10 : 13;
6813 shader->config.spi_ps_input_ena |=
6814 S_0286CC_LINEAR_CENTROID_ENA(1);
6815 break;
6816 default:
6817 assert(0);
6818 }
6819 break;
6820 default:
6821 assert(0);
6822 }
6823 }
6824 }
6825 }
6826
6827 /**
6828 * Check whether a PS prolog is required based on the key.
6829 */
6830 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6831 {
6832 return key->ps_prolog.colors_read ||
6833 key->ps_prolog.states.force_persp_sample_interp ||
6834 key->ps_prolog.states.force_linear_sample_interp ||
6835 key->ps_prolog.states.force_persp_center_interp ||
6836 key->ps_prolog.states.force_linear_center_interp ||
6837 key->ps_prolog.states.bc_optimize_for_persp ||
6838 key->ps_prolog.states.bc_optimize_for_linear ||
6839 key->ps_prolog.states.poly_stipple;
6840 }
6841
6842 /**
6843 * Compute the PS epilog key, which contains all the information needed to
6844 * build the PS epilog function.
6845 */
6846 static void si_get_ps_epilog_key(struct si_shader *shader,
6847 union si_shader_part_key *key)
6848 {
6849 struct tgsi_shader_info *info = &shader->selector->info;
6850 memset(key, 0, sizeof(*key));
6851 key->ps_epilog.colors_written = info->colors_written;
6852 key->ps_epilog.writes_z = info->writes_z;
6853 key->ps_epilog.writes_stencil = info->writes_stencil;
6854 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6855 key->ps_epilog.states = shader->key.part.ps.epilog;
6856 }
6857
6858 /**
6859 * Build the GS prolog function. Rotate the input vertices for triangle strips
6860 * with adjacency.
6861 */
6862 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6863 union si_shader_part_key *key)
6864 {
6865 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6866 const unsigned num_vgprs = 8;
6867 struct gallivm_state *gallivm = &ctx->gallivm;
6868 LLVMBuilderRef builder = gallivm->builder;
6869 LLVMTypeRef params[32];
6870 LLVMTypeRef returns[32];
6871 LLVMValueRef func, ret;
6872
6873 for (unsigned i = 0; i < num_sgprs; ++i) {
6874 params[i] = ctx->i32;
6875 returns[i] = ctx->i32;
6876 }
6877
6878 for (unsigned i = 0; i < num_vgprs; ++i) {
6879 params[num_sgprs + i] = ctx->i32;
6880 returns[num_sgprs + i] = ctx->f32;
6881 }
6882
6883 /* Create the function. */
6884 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6885 params, num_sgprs + num_vgprs, num_sgprs - 1);
6886 func = ctx->main_fn;
6887
6888 /* Copy inputs to outputs. This should be no-op, as the registers match,
6889 * but it will prevent the compiler from overwriting them unintentionally.
6890 */
6891 ret = ctx->return_value;
6892 for (unsigned i = 0; i < num_sgprs; i++) {
6893 LLVMValueRef p = LLVMGetParam(func, i);
6894 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6895 }
6896 for (unsigned i = 0; i < num_vgprs; i++) {
6897 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6898 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6899 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6900 }
6901
6902 if (key->gs_prolog.states.tri_strip_adj_fix) {
6903 /* Remap the input vertices for every other primitive. */
6904 const unsigned vtx_params[6] = {
6905 num_sgprs,
6906 num_sgprs + 1,
6907 num_sgprs + 3,
6908 num_sgprs + 4,
6909 num_sgprs + 5,
6910 num_sgprs + 6
6911 };
6912 LLVMValueRef prim_id, rotate;
6913
6914 prim_id = LLVMGetParam(func, num_sgprs + 2);
6915 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6916
6917 for (unsigned i = 0; i < 6; ++i) {
6918 LLVMValueRef base, rotated, actual;
6919 base = LLVMGetParam(func, vtx_params[i]);
6920 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
6921 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
6922 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
6923 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
6924 }
6925 }
6926
6927 LLVMBuildRet(builder, ret);
6928 }
6929
6930 /**
6931 * Given a list of shader part functions, build a wrapper function that
6932 * runs them in sequence to form a monolithic shader.
6933 */
6934 static void si_build_wrapper_function(struct si_shader_context *ctx,
6935 LLVMValueRef *parts,
6936 unsigned num_parts,
6937 unsigned main_part)
6938 {
6939 struct gallivm_state *gallivm = &ctx->gallivm;
6940 LLVMBuilderRef builder = ctx->gallivm.builder;
6941 /* PS epilog has one arg per color component */
6942 LLVMTypeRef param_types[48];
6943 LLVMValueRef out[48];
6944 LLVMTypeRef function_type;
6945 unsigned num_params;
6946 unsigned num_out;
6947 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6948 unsigned num_sgprs, num_vgprs;
6949 unsigned last_sgpr_param;
6950 unsigned gprs;
6951
6952 for (unsigned i = 0; i < num_parts; ++i) {
6953 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6954 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6955 }
6956
6957 /* The parameters of the wrapper function correspond to those of the
6958 * first part in terms of SGPRs and VGPRs, but we use the types of the
6959 * main part to get the right types. This is relevant for the
6960 * dereferenceable attribute on descriptor table pointers.
6961 */
6962 num_sgprs = 0;
6963 num_vgprs = 0;
6964
6965 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6966 num_params = LLVMCountParamTypes(function_type);
6967
6968 for (unsigned i = 0; i < num_params; ++i) {
6969 LLVMValueRef param = LLVMGetParam(parts[0], i);
6970
6971 if (ac_is_sgpr_param(param)) {
6972 assert(num_vgprs == 0);
6973 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6974 } else {
6975 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6976 }
6977 }
6978 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
6979
6980 num_params = 0;
6981 last_sgpr_param = 0;
6982 gprs = 0;
6983 while (gprs < num_sgprs + num_vgprs) {
6984 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
6985 unsigned size;
6986
6987 param_types[num_params] = LLVMTypeOf(param);
6988 if (gprs < num_sgprs)
6989 last_sgpr_param = num_params;
6990 size = llvm_get_type_size(param_types[num_params]) / 4;
6991 num_params++;
6992
6993 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6994 assert(gprs + size <= num_sgprs + num_vgprs &&
6995 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6996
6997 gprs += size;
6998 }
6999
7000 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7001
7002 /* Record the arguments of the function as if they were an output of
7003 * a previous part.
7004 */
7005 num_out = 0;
7006 num_out_sgpr = 0;
7007
7008 for (unsigned i = 0; i < num_params; ++i) {
7009 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7010 LLVMTypeRef param_type = LLVMTypeOf(param);
7011 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7012 unsigned size = llvm_get_type_size(param_type) / 4;
7013
7014 if (size == 1) {
7015 if (param_type != out_type)
7016 param = LLVMBuildBitCast(builder, param, out_type, "");
7017 out[num_out++] = param;
7018 } else {
7019 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7020
7021 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7022 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7023 param_type = ctx->i64;
7024 }
7025
7026 if (param_type != vector_type)
7027 param = LLVMBuildBitCast(builder, param, vector_type, "");
7028
7029 for (unsigned j = 0; j < size; ++j)
7030 out[num_out++] = LLVMBuildExtractElement(
7031 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7032 }
7033
7034 if (i <= last_sgpr_param)
7035 num_out_sgpr = num_out;
7036 }
7037
7038 /* Now chain the parts. */
7039 for (unsigned part = 0; part < num_parts; ++part) {
7040 LLVMValueRef in[48];
7041 LLVMValueRef ret;
7042 LLVMTypeRef ret_type;
7043 unsigned out_idx = 0;
7044
7045 num_params = LLVMCountParams(parts[part]);
7046 assert(num_params <= ARRAY_SIZE(param_types));
7047
7048 /* Derive arguments for the next part from outputs of the
7049 * previous one.
7050 */
7051 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7052 LLVMValueRef param;
7053 LLVMTypeRef param_type;
7054 bool is_sgpr;
7055 unsigned param_size;
7056 LLVMValueRef arg = NULL;
7057
7058 param = LLVMGetParam(parts[part], param_idx);
7059 param_type = LLVMTypeOf(param);
7060 param_size = llvm_get_type_size(param_type) / 4;
7061 is_sgpr = ac_is_sgpr_param(param);
7062
7063 if (is_sgpr) {
7064 #if HAVE_LLVM < 0x0400
7065 LLVMRemoveAttribute(param, LLVMByValAttribute);
7066 #else
7067 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7068 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7069 #endif
7070 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7071 }
7072
7073 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7074 assert(is_sgpr || out_idx >= num_out_sgpr);
7075
7076 if (param_size == 1)
7077 arg = out[out_idx];
7078 else
7079 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7080
7081 if (LLVMTypeOf(arg) != param_type) {
7082 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7083 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7084 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7085 } else {
7086 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7087 }
7088 }
7089
7090 in[param_idx] = arg;
7091 out_idx += param_size;
7092 }
7093
7094 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7095 ret_type = LLVMTypeOf(ret);
7096
7097 /* Extract the returned GPRs. */
7098 num_out = 0;
7099 num_out_sgpr = 0;
7100
7101 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7102 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7103
7104 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7105
7106 for (unsigned i = 0; i < ret_size; ++i) {
7107 LLVMValueRef val =
7108 LLVMBuildExtractValue(builder, ret, i, "");
7109
7110 out[num_out++] = val;
7111
7112 if (LLVMTypeOf(val) == ctx->i32) {
7113 assert(num_out_sgpr + 1 == num_out);
7114 num_out_sgpr = num_out;
7115 }
7116 }
7117 }
7118 }
7119
7120 LLVMBuildRetVoid(builder);
7121 }
7122
7123 int si_compile_tgsi_shader(struct si_screen *sscreen,
7124 LLVMTargetMachineRef tm,
7125 struct si_shader *shader,
7126 bool is_monolithic,
7127 struct pipe_debug_callback *debug)
7128 {
7129 struct si_shader_selector *sel = shader->selector;
7130 struct si_shader_context ctx;
7131 struct lp_build_tgsi_context *bld_base;
7132 LLVMModuleRef mod;
7133 int r = -1;
7134
7135 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7136 * conversion fails. */
7137 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7138 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7139 tgsi_dump(sel->tokens, 0);
7140 si_dump_streamout(&sel->so);
7141 }
7142
7143 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7144 ctx.separate_prolog = !is_monolithic;
7145
7146 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7147 sizeof(shader->info.vs_output_param_offset));
7148
7149 shader->info.uses_instanceid = sel->info.uses_instanceid;
7150
7151 bld_base = &ctx.bld_base;
7152 ctx.load_system_value = declare_system_value;
7153
7154 if (!si_compile_tgsi_main(&ctx, shader)) {
7155 si_llvm_dispose(&ctx);
7156 return -1;
7157 }
7158
7159 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7160 LLVMValueRef parts[3];
7161 bool need_prolog;
7162 bool need_epilog;
7163
7164 need_prolog = sel->info.num_inputs;
7165 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7166
7167 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7168
7169 if (need_prolog) {
7170 union si_shader_part_key prolog_key;
7171 si_get_vs_prolog_key(shader, &prolog_key);
7172 si_build_vs_prolog_function(&ctx, &prolog_key);
7173 parts[0] = ctx.main_fn;
7174 }
7175
7176 if (need_epilog) {
7177 union si_shader_part_key epilog_key;
7178 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7179 si_build_vs_epilog_function(&ctx, &epilog_key);
7180 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7181 }
7182
7183 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7184 need_prolog ? 1 : 0);
7185 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7186 LLVMValueRef parts[2];
7187 union si_shader_part_key epilog_key;
7188
7189 parts[0] = ctx.main_fn;
7190
7191 memset(&epilog_key, 0, sizeof(epilog_key));
7192 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7193 si_build_tcs_epilog_function(&ctx, &epilog_key);
7194 parts[1] = ctx.main_fn;
7195
7196 si_build_wrapper_function(&ctx, parts, 2, 0);
7197 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7198 !shader->key.as_es) {
7199 LLVMValueRef parts[2];
7200 union si_shader_part_key epilog_key;
7201
7202 parts[0] = ctx.main_fn;
7203
7204 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7205 si_build_vs_epilog_function(&ctx, &epilog_key);
7206 parts[1] = ctx.main_fn;
7207
7208 si_build_wrapper_function(&ctx, parts, 2, 0);
7209 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7210 LLVMValueRef parts[2];
7211 union si_shader_part_key prolog_key;
7212
7213 parts[1] = ctx.main_fn;
7214
7215 memset(&prolog_key, 0, sizeof(prolog_key));
7216 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7217 si_build_gs_prolog_function(&ctx, &prolog_key);
7218 parts[0] = ctx.main_fn;
7219
7220 si_build_wrapper_function(&ctx, parts, 2, 1);
7221 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7222 LLVMValueRef parts[3];
7223 union si_shader_part_key prolog_key;
7224 union si_shader_part_key epilog_key;
7225 bool need_prolog;
7226
7227 si_get_ps_prolog_key(shader, &prolog_key, false);
7228 need_prolog = si_need_ps_prolog(&prolog_key);
7229
7230 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7231
7232 if (need_prolog) {
7233 si_build_ps_prolog_function(&ctx, &prolog_key);
7234 parts[0] = ctx.main_fn;
7235 }
7236
7237 si_get_ps_epilog_key(shader, &epilog_key);
7238 si_build_ps_epilog_function(&ctx, &epilog_key);
7239 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7240
7241 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7242 }
7243
7244 mod = bld_base->base.gallivm->module;
7245
7246 /* Dump LLVM IR before any optimization passes */
7247 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7248 r600_can_dump_shader(&sscreen->b, ctx.type))
7249 ac_dump_module(mod);
7250
7251 si_llvm_finalize_module(&ctx,
7252 r600_extra_shader_checks(&sscreen->b, ctx.type));
7253
7254 /* Post-optimization transformations and analysis. */
7255 si_eliminate_const_vs_outputs(&ctx);
7256
7257 if ((debug && debug->debug_message) ||
7258 r600_can_dump_shader(&sscreen->b, ctx.type))
7259 si_count_scratch_private_memory(&ctx);
7260
7261 /* Compile to bytecode. */
7262 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7263 mod, debug, ctx.type, "TGSI shader");
7264 si_llvm_dispose(&ctx);
7265 if (r) {
7266 fprintf(stderr, "LLVM failed to compile shader\n");
7267 return r;
7268 }
7269
7270 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7271 * LLVM 3.9svn has this bug.
7272 */
7273 if (sel->type == PIPE_SHADER_COMPUTE) {
7274 unsigned wave_size = 64;
7275 unsigned max_vgprs = 256;
7276 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7277 unsigned max_sgprs_per_wave = 128;
7278 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7279 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7280 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7281
7282 max_vgprs = max_vgprs / min_waves_per_simd;
7283 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7284
7285 if (shader->config.num_sgprs > max_sgprs ||
7286 shader->config.num_vgprs > max_vgprs) {
7287 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7288 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7289 shader->config.num_sgprs, shader->config.num_vgprs,
7290 max_sgprs, max_vgprs);
7291
7292 /* Just terminate the process, because dependent
7293 * shaders can hang due to bad input data, but use
7294 * the env var to allow shader-db to work.
7295 */
7296 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7297 abort();
7298 }
7299 }
7300
7301 /* Add the scratch offset to input SGPRs. */
7302 if (shader->config.scratch_bytes_per_wave)
7303 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7304
7305 /* Calculate the number of fragment input VGPRs. */
7306 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7307 shader->info.num_input_vgprs = 0;
7308 shader->info.face_vgpr_index = -1;
7309
7310 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7311 shader->info.num_input_vgprs += 2;
7312 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7313 shader->info.num_input_vgprs += 2;
7314 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7315 shader->info.num_input_vgprs += 2;
7316 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7317 shader->info.num_input_vgprs += 3;
7318 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7319 shader->info.num_input_vgprs += 2;
7320 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7321 shader->info.num_input_vgprs += 2;
7322 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7323 shader->info.num_input_vgprs += 2;
7324 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7325 shader->info.num_input_vgprs += 1;
7326 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7327 shader->info.num_input_vgprs += 1;
7328 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7329 shader->info.num_input_vgprs += 1;
7330 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7331 shader->info.num_input_vgprs += 1;
7332 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7333 shader->info.num_input_vgprs += 1;
7334 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7335 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7336 shader->info.num_input_vgprs += 1;
7337 }
7338 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7339 shader->info.num_input_vgprs += 1;
7340 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7341 shader->info.num_input_vgprs += 1;
7342 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7343 shader->info.num_input_vgprs += 1;
7344 }
7345
7346 return 0;
7347 }
7348
7349 /**
7350 * Create, compile and return a shader part (prolog or epilog).
7351 *
7352 * \param sscreen screen
7353 * \param list list of shader parts of the same category
7354 * \param type shader type
7355 * \param key shader part key
7356 * \param prolog whether the part being requested is a prolog
7357 * \param tm LLVM target machine
7358 * \param debug debug callback
7359 * \param build the callback responsible for building the main function
7360 * \return non-NULL on success
7361 */
7362 static struct si_shader_part *
7363 si_get_shader_part(struct si_screen *sscreen,
7364 struct si_shader_part **list,
7365 enum pipe_shader_type type,
7366 bool prolog,
7367 union si_shader_part_key *key,
7368 LLVMTargetMachineRef tm,
7369 struct pipe_debug_callback *debug,
7370 void (*build)(struct si_shader_context *,
7371 union si_shader_part_key *),
7372 const char *name)
7373 {
7374 struct si_shader_part *result;
7375
7376 pipe_mutex_lock(sscreen->shader_parts_mutex);
7377
7378 /* Find existing. */
7379 for (result = *list; result; result = result->next) {
7380 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7381 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7382 return result;
7383 }
7384 }
7385
7386 /* Compile a new one. */
7387 result = CALLOC_STRUCT(si_shader_part);
7388 result->key = *key;
7389
7390 struct si_shader shader = {};
7391 struct si_shader_context ctx;
7392 struct gallivm_state *gallivm = &ctx.gallivm;
7393
7394 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7395 ctx.type = type;
7396
7397 switch (type) {
7398 case PIPE_SHADER_VERTEX:
7399 break;
7400 case PIPE_SHADER_TESS_CTRL:
7401 assert(!prolog);
7402 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7403 break;
7404 case PIPE_SHADER_GEOMETRY:
7405 assert(prolog);
7406 break;
7407 case PIPE_SHADER_FRAGMENT:
7408 if (prolog)
7409 shader.key.part.ps.prolog = key->ps_prolog.states;
7410 else
7411 shader.key.part.ps.epilog = key->ps_epilog.states;
7412 break;
7413 default:
7414 unreachable("bad shader part");
7415 }
7416
7417 build(&ctx, key);
7418
7419 /* Compile. */
7420 si_llvm_finalize_module(&ctx,
7421 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7422
7423 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7424 gallivm->module, debug, ctx.type, name)) {
7425 FREE(result);
7426 result = NULL;
7427 goto out;
7428 }
7429
7430 result->next = *list;
7431 *list = result;
7432
7433 out:
7434 si_llvm_dispose(&ctx);
7435 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7436 return result;
7437 }
7438
7439 /**
7440 * Build the vertex shader prolog function.
7441 *
7442 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7443 * All inputs are returned unmodified. The vertex load indices are
7444 * stored after them, which will be used by the API VS for fetching inputs.
7445 *
7446 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7447 * input_v0,
7448 * input_v1,
7449 * input_v2,
7450 * input_v3,
7451 * (VertexID + BaseVertex),
7452 * (InstanceID + StartInstance),
7453 * (InstanceID / 2 + StartInstance)
7454 */
7455 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7456 union si_shader_part_key *key)
7457 {
7458 struct gallivm_state *gallivm = &ctx->gallivm;
7459 LLVMTypeRef *params, *returns;
7460 LLVMValueRef ret, func;
7461 int last_sgpr, num_params, num_returns, i;
7462
7463 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7464 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7465
7466 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7467 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7468 sizeof(LLVMTypeRef));
7469 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7470 key->vs_prolog.last_input + 1) *
7471 sizeof(LLVMTypeRef));
7472 num_params = 0;
7473 num_returns = 0;
7474
7475 /* Declare input and output SGPRs. */
7476 num_params = 0;
7477 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7478 params[num_params++] = ctx->i32;
7479 returns[num_returns++] = ctx->i32;
7480 }
7481 last_sgpr = num_params - 1;
7482
7483 /* 4 preloaded VGPRs (outputs must be floats) */
7484 for (i = 0; i < 4; i++) {
7485 params[num_params++] = ctx->i32;
7486 returns[num_returns++] = ctx->f32;
7487 }
7488
7489 /* Vertex load indices. */
7490 for (i = 0; i <= key->vs_prolog.last_input; i++)
7491 returns[num_returns++] = ctx->f32;
7492
7493 /* Create the function. */
7494 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7495 num_params, last_sgpr);
7496 func = ctx->main_fn;
7497
7498 /* Copy inputs to outputs. This should be no-op, as the registers match,
7499 * but it will prevent the compiler from overwriting them unintentionally.
7500 */
7501 ret = ctx->return_value;
7502 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7503 LLVMValueRef p = LLVMGetParam(func, i);
7504 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7505 }
7506 for (i = num_params - 4; i < num_params; i++) {
7507 LLVMValueRef p = LLVMGetParam(func, i);
7508 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7509 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7510 }
7511
7512 /* Compute vertex load indices from instance divisors. */
7513 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7514 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7515 LLVMValueRef index;
7516
7517 if (divisor) {
7518 /* InstanceID / Divisor + StartInstance */
7519 index = get_instance_index_for_fetch(ctx,
7520 SI_SGPR_START_INSTANCE,
7521 divisor);
7522 } else {
7523 /* VertexID + BaseVertex */
7524 index = LLVMBuildAdd(gallivm->builder,
7525 LLVMGetParam(func, ctx->param_vertex_id),
7526 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7527 }
7528
7529 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7530 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7531 num_params++, "");
7532 }
7533
7534 si_llvm_build_ret(ctx, ret);
7535 }
7536
7537 /**
7538 * Build the vertex shader epilog function. This is also used by the tessellation
7539 * evaluation shader compiled as VS.
7540 *
7541 * The input is PrimitiveID.
7542 *
7543 * If PrimitiveID is required by the pixel shader, export it.
7544 * Otherwise, do nothing.
7545 */
7546 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7547 union si_shader_part_key *key)
7548 {
7549 struct gallivm_state *gallivm = &ctx->gallivm;
7550 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7551 LLVMTypeRef params[5];
7552 int num_params, i;
7553
7554 /* Declare input VGPRs. */
7555 num_params = key->vs_epilog.states.export_prim_id ?
7556 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7557 assert(num_params <= ARRAY_SIZE(params));
7558
7559 for (i = 0; i < num_params; i++)
7560 params[i] = ctx->f32;
7561
7562 /* Create the function. */
7563 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7564
7565 /* Emit exports. */
7566 if (key->vs_epilog.states.export_prim_id) {
7567 struct lp_build_context *base = &bld_base->base;
7568 struct ac_export_args args;
7569
7570 args.enabled_channels = 0x1; /* enabled channels */
7571 args.valid_mask = 0; /* whether the EXEC mask is valid */
7572 args.done = 0; /* DONE bit */
7573 args.target = V_008DFC_SQ_EXP_PARAM +
7574 key->vs_epilog.prim_id_param_offset;
7575 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7576 args.out[0] = LLVMGetParam(ctx->main_fn,
7577 VS_EPILOG_PRIMID_LOC); /* X */
7578 args.out[1] = base->undef; /* Y */
7579 args.out[2] = base->undef; /* Z */
7580 args.out[3] = base->undef; /* W */
7581
7582 ac_emit_export(&ctx->ac, &args);
7583 }
7584
7585 LLVMBuildRetVoid(gallivm->builder);
7586 }
7587
7588 /**
7589 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7590 */
7591 static bool si_get_vs_epilog(struct si_screen *sscreen,
7592 LLVMTargetMachineRef tm,
7593 struct si_shader *shader,
7594 struct pipe_debug_callback *debug,
7595 struct si_vs_epilog_bits *states)
7596 {
7597 union si_shader_part_key epilog_key;
7598
7599 si_get_vs_epilog_key(shader, states, &epilog_key);
7600
7601 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7602 PIPE_SHADER_VERTEX, true,
7603 &epilog_key, tm, debug,
7604 si_build_vs_epilog_function,
7605 "Vertex Shader Epilog");
7606 return shader->epilog != NULL;
7607 }
7608
7609 /**
7610 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7611 */
7612 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7613 LLVMTargetMachineRef tm,
7614 struct si_shader *shader,
7615 struct pipe_debug_callback *debug)
7616 {
7617 struct tgsi_shader_info *info = &shader->selector->info;
7618 union si_shader_part_key prolog_key;
7619
7620 /* Get the prolog. */
7621 si_get_vs_prolog_key(shader, &prolog_key);
7622
7623 /* The prolog is a no-op if there are no inputs. */
7624 if (info->num_inputs) {
7625 shader->prolog =
7626 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7627 PIPE_SHADER_VERTEX, true,
7628 &prolog_key, tm, debug,
7629 si_build_vs_prolog_function,
7630 "Vertex Shader Prolog");
7631 if (!shader->prolog)
7632 return false;
7633 }
7634
7635 /* Get the epilog. */
7636 if (!shader->key.as_es && !shader->key.as_ls &&
7637 !si_get_vs_epilog(sscreen, tm, shader, debug,
7638 &shader->key.part.vs.epilog))
7639 return false;
7640
7641 return true;
7642 }
7643
7644 /**
7645 * Select and compile (or reuse) TES parts (epilog).
7646 */
7647 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7648 LLVMTargetMachineRef tm,
7649 struct si_shader *shader,
7650 struct pipe_debug_callback *debug)
7651 {
7652 if (shader->key.as_es)
7653 return true;
7654
7655 /* TES compiled as VS. */
7656 return si_get_vs_epilog(sscreen, tm, shader, debug,
7657 &shader->key.part.tes.epilog);
7658 }
7659
7660 /**
7661 * Compile the TCS epilog function. This writes tesselation factors to memory
7662 * based on the output primitive type of the tesselator (determined by TES).
7663 */
7664 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7665 union si_shader_part_key *key)
7666 {
7667 struct gallivm_state *gallivm = &ctx->gallivm;
7668 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7669 LLVMTypeRef params[16];
7670 LLVMValueRef func;
7671 int last_sgpr, num_params;
7672
7673 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7674 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7675 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7676 params[SI_PARAM_SAMPLERS] = ctx->i64;
7677 params[SI_PARAM_IMAGES] = ctx->i64;
7678 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7679 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7680 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7681 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7682 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7683 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7684 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7685 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7686 num_params = last_sgpr + 1;
7687
7688 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7689 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7690 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7691
7692 /* Create the function. */
7693 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7694 declare_tess_lds(ctx);
7695 func = ctx->main_fn;
7696
7697 si_write_tess_factors(bld_base,
7698 LLVMGetParam(func, last_sgpr + 1),
7699 LLVMGetParam(func, last_sgpr + 2),
7700 LLVMGetParam(func, last_sgpr + 3));
7701
7702 LLVMBuildRetVoid(gallivm->builder);
7703 }
7704
7705 /**
7706 * Select and compile (or reuse) TCS parts (epilog).
7707 */
7708 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7709 LLVMTargetMachineRef tm,
7710 struct si_shader *shader,
7711 struct pipe_debug_callback *debug)
7712 {
7713 union si_shader_part_key epilog_key;
7714
7715 /* Get the epilog. */
7716 memset(&epilog_key, 0, sizeof(epilog_key));
7717 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7718
7719 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7720 PIPE_SHADER_TESS_CTRL, false,
7721 &epilog_key, tm, debug,
7722 si_build_tcs_epilog_function,
7723 "Tessellation Control Shader Epilog");
7724 return shader->epilog != NULL;
7725 }
7726
7727 /**
7728 * Select and compile (or reuse) GS parts (prolog).
7729 */
7730 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7731 LLVMTargetMachineRef tm,
7732 struct si_shader *shader,
7733 struct pipe_debug_callback *debug)
7734 {
7735 union si_shader_part_key prolog_key;
7736
7737 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7738 return true;
7739
7740 memset(&prolog_key, 0, sizeof(prolog_key));
7741 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7742
7743 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7744 PIPE_SHADER_GEOMETRY, true,
7745 &prolog_key, tm, debug,
7746 si_build_gs_prolog_function,
7747 "Geometry Shader Prolog");
7748 return shader->prolog != NULL;
7749 }
7750
7751 /**
7752 * Build the pixel shader prolog function. This handles:
7753 * - two-side color selection and interpolation
7754 * - overriding interpolation parameters for the API PS
7755 * - polygon stippling
7756 *
7757 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7758 * overriden by other states. (e.g. per-sample interpolation)
7759 * Interpolated colors are stored after the preloaded VGPRs.
7760 */
7761 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7762 union si_shader_part_key *key)
7763 {
7764 struct gallivm_state *gallivm = &ctx->gallivm;
7765 LLVMTypeRef *params;
7766 LLVMValueRef ret, func;
7767 int last_sgpr, num_params, num_returns, i, num_color_channels;
7768
7769 assert(si_need_ps_prolog(key));
7770
7771 /* Number of inputs + 8 color elements. */
7772 params = alloca((key->ps_prolog.num_input_sgprs +
7773 key->ps_prolog.num_input_vgprs + 8) *
7774 sizeof(LLVMTypeRef));
7775
7776 /* Declare inputs. */
7777 num_params = 0;
7778 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7779 params[num_params++] = ctx->i32;
7780 last_sgpr = num_params - 1;
7781
7782 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7783 params[num_params++] = ctx->f32;
7784
7785 /* Declare outputs (same as inputs + add colors if needed) */
7786 num_returns = num_params;
7787 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7788 for (i = 0; i < num_color_channels; i++)
7789 params[num_returns++] = ctx->f32;
7790
7791 /* Create the function. */
7792 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7793 num_params, last_sgpr);
7794 func = ctx->main_fn;
7795
7796 /* Copy inputs to outputs. This should be no-op, as the registers match,
7797 * but it will prevent the compiler from overwriting them unintentionally.
7798 */
7799 ret = ctx->return_value;
7800 for (i = 0; i < num_params; i++) {
7801 LLVMValueRef p = LLVMGetParam(func, i);
7802 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7803 }
7804
7805 /* Polygon stippling. */
7806 if (key->ps_prolog.states.poly_stipple) {
7807 /* POS_FIXED_PT is always last. */
7808 unsigned pos = key->ps_prolog.num_input_sgprs +
7809 key->ps_prolog.num_input_vgprs - 1;
7810 LLVMValueRef ptr[2], list;
7811
7812 /* Get the pointer to rw buffers. */
7813 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7814 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7815 list = lp_build_gather_values(gallivm, ptr, 2);
7816 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7817 list = LLVMBuildIntToPtr(gallivm->builder, list,
7818 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7819
7820 si_llvm_emit_polygon_stipple(ctx, list, pos);
7821 }
7822
7823 if (key->ps_prolog.states.bc_optimize_for_persp ||
7824 key->ps_prolog.states.bc_optimize_for_linear) {
7825 unsigned i, base = key->ps_prolog.num_input_sgprs;
7826 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7827
7828 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7829 * The hw doesn't compute CENTROID if the whole wave only
7830 * contains fully-covered quads.
7831 *
7832 * PRIM_MASK is after user SGPRs.
7833 */
7834 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7835 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7836 LLVMConstInt(ctx->i32, 31, 0), "");
7837 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7838 ctx->i1, "");
7839
7840 if (key->ps_prolog.states.bc_optimize_for_persp) {
7841 /* Read PERSP_CENTER. */
7842 for (i = 0; i < 2; i++)
7843 center[i] = LLVMGetParam(func, base + 2 + i);
7844 /* Read PERSP_CENTROID. */
7845 for (i = 0; i < 2; i++)
7846 centroid[i] = LLVMGetParam(func, base + 4 + i);
7847 /* Select PERSP_CENTROID. */
7848 for (i = 0; i < 2; i++) {
7849 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7850 center[i], centroid[i], "");
7851 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7852 tmp, base + 4 + i, "");
7853 }
7854 }
7855 if (key->ps_prolog.states.bc_optimize_for_linear) {
7856 /* Read LINEAR_CENTER. */
7857 for (i = 0; i < 2; i++)
7858 center[i] = LLVMGetParam(func, base + 8 + i);
7859 /* Read LINEAR_CENTROID. */
7860 for (i = 0; i < 2; i++)
7861 centroid[i] = LLVMGetParam(func, base + 10 + i);
7862 /* Select LINEAR_CENTROID. */
7863 for (i = 0; i < 2; i++) {
7864 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7865 center[i], centroid[i], "");
7866 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7867 tmp, base + 10 + i, "");
7868 }
7869 }
7870 }
7871
7872 /* Force per-sample interpolation. */
7873 if (key->ps_prolog.states.force_persp_sample_interp) {
7874 unsigned i, base = key->ps_prolog.num_input_sgprs;
7875 LLVMValueRef persp_sample[2];
7876
7877 /* Read PERSP_SAMPLE. */
7878 for (i = 0; i < 2; i++)
7879 persp_sample[i] = LLVMGetParam(func, base + i);
7880 /* Overwrite PERSP_CENTER. */
7881 for (i = 0; i < 2; i++)
7882 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7883 persp_sample[i], base + 2 + i, "");
7884 /* Overwrite PERSP_CENTROID. */
7885 for (i = 0; i < 2; i++)
7886 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7887 persp_sample[i], base + 4 + i, "");
7888 }
7889 if (key->ps_prolog.states.force_linear_sample_interp) {
7890 unsigned i, base = key->ps_prolog.num_input_sgprs;
7891 LLVMValueRef linear_sample[2];
7892
7893 /* Read LINEAR_SAMPLE. */
7894 for (i = 0; i < 2; i++)
7895 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7896 /* Overwrite LINEAR_CENTER. */
7897 for (i = 0; i < 2; i++)
7898 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7899 linear_sample[i], base + 8 + i, "");
7900 /* Overwrite LINEAR_CENTROID. */
7901 for (i = 0; i < 2; i++)
7902 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7903 linear_sample[i], base + 10 + i, "");
7904 }
7905
7906 /* Force center interpolation. */
7907 if (key->ps_prolog.states.force_persp_center_interp) {
7908 unsigned i, base = key->ps_prolog.num_input_sgprs;
7909 LLVMValueRef persp_center[2];
7910
7911 /* Read PERSP_CENTER. */
7912 for (i = 0; i < 2; i++)
7913 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7914 /* Overwrite PERSP_SAMPLE. */
7915 for (i = 0; i < 2; i++)
7916 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7917 persp_center[i], base + i, "");
7918 /* Overwrite PERSP_CENTROID. */
7919 for (i = 0; i < 2; i++)
7920 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7921 persp_center[i], base + 4 + i, "");
7922 }
7923 if (key->ps_prolog.states.force_linear_center_interp) {
7924 unsigned i, base = key->ps_prolog.num_input_sgprs;
7925 LLVMValueRef linear_center[2];
7926
7927 /* Read LINEAR_CENTER. */
7928 for (i = 0; i < 2; i++)
7929 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7930 /* Overwrite LINEAR_SAMPLE. */
7931 for (i = 0; i < 2; i++)
7932 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7933 linear_center[i], base + 6 + i, "");
7934 /* Overwrite LINEAR_CENTROID. */
7935 for (i = 0; i < 2; i++)
7936 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7937 linear_center[i], base + 10 + i, "");
7938 }
7939
7940 /* Interpolate colors. */
7941 for (i = 0; i < 2; i++) {
7942 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7943 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7944 key->ps_prolog.face_vgpr_index;
7945 LLVMValueRef interp[2], color[4];
7946 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7947
7948 if (!writemask)
7949 continue;
7950
7951 /* If the interpolation qualifier is not CONSTANT (-1). */
7952 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7953 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7954 key->ps_prolog.color_interp_vgpr_index[i];
7955
7956 /* Get the (i,j) updated by bc_optimize handling. */
7957 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7958 interp_vgpr, "");
7959 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7960 interp_vgpr + 1, "");
7961 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7962 }
7963
7964 /* Use the absolute location of the input. */
7965 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7966
7967 if (key->ps_prolog.states.color_two_side) {
7968 face = LLVMGetParam(func, face_vgpr);
7969 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7970 }
7971
7972 interp_fs_input(ctx,
7973 key->ps_prolog.color_attr_index[i],
7974 TGSI_SEMANTIC_COLOR, i,
7975 key->ps_prolog.num_interp_inputs,
7976 key->ps_prolog.colors_read, interp_ij,
7977 prim_mask, face, color);
7978
7979 while (writemask) {
7980 unsigned chan = u_bit_scan(&writemask);
7981 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7982 num_params++, "");
7983 }
7984 }
7985
7986 /* Tell LLVM to insert WQM instruction sequence when needed. */
7987 if (key->ps_prolog.wqm) {
7988 LLVMAddTargetDependentFunctionAttr(func,
7989 "amdgpu-ps-wqm-outputs", "");
7990 }
7991
7992 si_llvm_build_ret(ctx, ret);
7993 }
7994
7995 /**
7996 * Build the pixel shader epilog function. This handles everything that must be
7997 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7998 */
7999 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8000 union si_shader_part_key *key)
8001 {
8002 struct gallivm_state *gallivm = &ctx->gallivm;
8003 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8004 LLVMTypeRef params[16+8*4+3];
8005 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8006 int last_sgpr, num_params, i;
8007 struct si_ps_exports exp = {};
8008
8009 /* Declare input SGPRs. */
8010 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8011 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8012 params[SI_PARAM_SAMPLERS] = ctx->i64;
8013 params[SI_PARAM_IMAGES] = ctx->i64;
8014 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8015 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8016 last_sgpr = SI_PARAM_ALPHA_REF;
8017
8018 /* Declare input VGPRs. */
8019 num_params = (last_sgpr + 1) +
8020 util_bitcount(key->ps_epilog.colors_written) * 4 +
8021 key->ps_epilog.writes_z +
8022 key->ps_epilog.writes_stencil +
8023 key->ps_epilog.writes_samplemask;
8024
8025 num_params = MAX2(num_params,
8026 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8027
8028 assert(num_params <= ARRAY_SIZE(params));
8029
8030 for (i = last_sgpr + 1; i < num_params; i++)
8031 params[i] = ctx->f32;
8032
8033 /* Create the function. */
8034 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8035 /* Disable elimination of unused inputs. */
8036 si_llvm_add_attribute(ctx->main_fn,
8037 "InitialPSInputAddr", 0xffffff);
8038
8039 /* Process colors. */
8040 unsigned vgpr = last_sgpr + 1;
8041 unsigned colors_written = key->ps_epilog.colors_written;
8042 int last_color_export = -1;
8043
8044 /* Find the last color export. */
8045 if (!key->ps_epilog.writes_z &&
8046 !key->ps_epilog.writes_stencil &&
8047 !key->ps_epilog.writes_samplemask) {
8048 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8049
8050 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8051 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8052 /* Just set this if any of the colorbuffers are enabled. */
8053 if (spi_format &
8054 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8055 last_color_export = 0;
8056 } else {
8057 for (i = 0; i < 8; i++)
8058 if (colors_written & (1 << i) &&
8059 (spi_format >> (i * 4)) & 0xf)
8060 last_color_export = i;
8061 }
8062 }
8063
8064 while (colors_written) {
8065 LLVMValueRef color[4];
8066 int mrt = u_bit_scan(&colors_written);
8067
8068 for (i = 0; i < 4; i++)
8069 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8070
8071 si_export_mrt_color(bld_base, color, mrt,
8072 num_params - 1,
8073 mrt == last_color_export, &exp);
8074 }
8075
8076 /* Process depth, stencil, samplemask. */
8077 if (key->ps_epilog.writes_z)
8078 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8079 if (key->ps_epilog.writes_stencil)
8080 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8081 if (key->ps_epilog.writes_samplemask)
8082 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8083
8084 if (depth || stencil || samplemask)
8085 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8086 else if (last_color_export == -1)
8087 si_export_null(bld_base);
8088
8089 if (exp.num)
8090 si_emit_ps_exports(ctx, &exp);
8091
8092 /* Compile. */
8093 LLVMBuildRetVoid(gallivm->builder);
8094 }
8095
8096 /**
8097 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8098 */
8099 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8100 LLVMTargetMachineRef tm,
8101 struct si_shader *shader,
8102 struct pipe_debug_callback *debug)
8103 {
8104 union si_shader_part_key prolog_key;
8105 union si_shader_part_key epilog_key;
8106
8107 /* Get the prolog. */
8108 si_get_ps_prolog_key(shader, &prolog_key, true);
8109
8110 /* The prolog is a no-op if these aren't set. */
8111 if (si_need_ps_prolog(&prolog_key)) {
8112 shader->prolog =
8113 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8114 PIPE_SHADER_FRAGMENT, true,
8115 &prolog_key, tm, debug,
8116 si_build_ps_prolog_function,
8117 "Fragment Shader Prolog");
8118 if (!shader->prolog)
8119 return false;
8120 }
8121
8122 /* Get the epilog. */
8123 si_get_ps_epilog_key(shader, &epilog_key);
8124
8125 shader->epilog =
8126 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8127 PIPE_SHADER_FRAGMENT, false,
8128 &epilog_key, tm, debug,
8129 si_build_ps_epilog_function,
8130 "Fragment Shader Epilog");
8131 if (!shader->epilog)
8132 return false;
8133
8134 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8135 if (shader->key.part.ps.prolog.poly_stipple) {
8136 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8137 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8138 }
8139
8140 /* Set up the enable bits for per-sample shading if needed. */
8141 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8142 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8143 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8144 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8145 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8146 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8147 }
8148 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8149 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8150 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8151 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8152 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8153 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8154 }
8155 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8156 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8157 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8158 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8159 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8160 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8161 }
8162 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8163 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8164 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8165 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8166 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8167 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8168 }
8169
8170 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8171 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8172 !(shader->config.spi_ps_input_ena & 0xf)) {
8173 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8174 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8175 }
8176
8177 /* At least one pair of interpolation weights must be enabled. */
8178 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8179 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8180 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8181 }
8182
8183 /* The sample mask input is always enabled, because the API shader always
8184 * passes it through to the epilog. Disable it here if it's unused.
8185 */
8186 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8187 !shader->selector->info.reads_samplemask)
8188 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8189
8190 return true;
8191 }
8192
8193 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8194 unsigned *lds_size)
8195 {
8196 /* SPI barrier management bug:
8197 * Make sure we have at least 4k of LDS in use to avoid the bug.
8198 * It applies to workgroup sizes of more than one wavefront.
8199 */
8200 if (sscreen->b.family == CHIP_BONAIRE ||
8201 sscreen->b.family == CHIP_KABINI ||
8202 sscreen->b.family == CHIP_MULLINS)
8203 *lds_size = MAX2(*lds_size, 8);
8204 }
8205
8206 static void si_fix_resource_usage(struct si_screen *sscreen,
8207 struct si_shader *shader)
8208 {
8209 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8210
8211 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8212
8213 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8214 si_get_max_workgroup_size(shader) > 64) {
8215 si_multiwave_lds_size_workaround(sscreen,
8216 &shader->config.lds_size);
8217 }
8218 }
8219
8220 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8221 struct si_shader *shader,
8222 struct pipe_debug_callback *debug)
8223 {
8224 struct si_shader_selector *sel = shader->selector;
8225 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8226 int r;
8227
8228 /* LS, ES, VS are compiled on demand if the main part hasn't been
8229 * compiled for that stage.
8230 *
8231 * Vertex shaders are compiled on demand when a vertex fetch
8232 * workaround must be applied.
8233 */
8234 if (shader->is_monolithic) {
8235 /* Monolithic shader (compiled as a whole, has many variants,
8236 * may take a long time to compile).
8237 */
8238 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8239 if (r)
8240 return r;
8241 } else {
8242 /* The shader consists of 2-3 parts:
8243 *
8244 * - the middle part is the user shader, it has 1 variant only
8245 * and it was compiled during the creation of the shader
8246 * selector
8247 * - the prolog part is inserted at the beginning
8248 * - the epilog part is inserted at the end
8249 *
8250 * The prolog and epilog have many (but simple) variants.
8251 */
8252
8253 /* Copy the compiled TGSI shader data over. */
8254 shader->is_binary_shared = true;
8255 shader->binary = mainp->binary;
8256 shader->config = mainp->config;
8257 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8258 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8259 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8260 memcpy(shader->info.vs_output_param_offset,
8261 mainp->info.vs_output_param_offset,
8262 sizeof(mainp->info.vs_output_param_offset));
8263 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8264 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8265 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8266
8267 /* Select prologs and/or epilogs. */
8268 switch (sel->type) {
8269 case PIPE_SHADER_VERTEX:
8270 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8271 return -1;
8272 break;
8273 case PIPE_SHADER_TESS_CTRL:
8274 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8275 return -1;
8276 break;
8277 case PIPE_SHADER_TESS_EVAL:
8278 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8279 return -1;
8280 break;
8281 case PIPE_SHADER_GEOMETRY:
8282 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8283 return -1;
8284 break;
8285 case PIPE_SHADER_FRAGMENT:
8286 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8287 return -1;
8288
8289 /* Make sure we have at least as many VGPRs as there
8290 * are allocated inputs.
8291 */
8292 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8293 shader->info.num_input_vgprs);
8294 break;
8295 }
8296
8297 /* Update SGPR and VGPR counts. */
8298 if (shader->prolog) {
8299 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8300 shader->prolog->config.num_sgprs);
8301 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8302 shader->prolog->config.num_vgprs);
8303 }
8304 if (shader->epilog) {
8305 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8306 shader->epilog->config.num_sgprs);
8307 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8308 shader->epilog->config.num_vgprs);
8309 }
8310 }
8311
8312 si_fix_resource_usage(sscreen, shader);
8313 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8314 stderr, true);
8315
8316 /* Upload. */
8317 r = si_shader_binary_upload(sscreen, shader);
8318 if (r) {
8319 fprintf(stderr, "LLVM failed to upload shader\n");
8320 return r;
8321 }
8322
8323 return 0;
8324 }
8325
8326 void si_shader_destroy(struct si_shader *shader)
8327 {
8328 if (shader->scratch_bo)
8329 r600_resource_reference(&shader->scratch_bo, NULL);
8330
8331 r600_resource_reference(&shader->bo, NULL);
8332
8333 if (!shader->is_binary_shared)
8334 radeon_shader_binary_clean(&shader->binary);
8335
8336 free(shader->shader_log);
8337 }