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radeonsi: remove shader.ps_conservative_z, set db_shader_control instead
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 unsigned usage;
55 };
56
57 struct si_shader_context
58 {
59 struct radeon_llvm_context radeon_bld;
60 struct tgsi_parse_context parse;
61 struct tgsi_token * tokens;
62 struct si_pipe_shader *shader;
63 struct si_shader *gs_for_vs;
64 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
65 int param_streamout_config;
66 int param_streamout_write_index;
67 int param_streamout_offset[4];
68 int param_vertex_id;
69 int param_instance_id;
70 LLVMValueRef const_md;
71 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
72 LLVMValueRef ddxy_lds;
73 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
74 LLVMValueRef *resources;
75 LLVMValueRef *samplers;
76 LLVMValueRef so_buffers[4];
77 LLVMValueRef gs_next_vertex;
78 };
79
80 static struct si_shader_context * si_shader_context(
81 struct lp_build_tgsi_context * bld_base)
82 {
83 return (struct si_shader_context *)bld_base;
84 }
85
86
87 #define PERSPECTIVE_BASE 0
88 #define LINEAR_BASE 9
89
90 #define SAMPLE_OFFSET 0
91 #define CENTER_OFFSET 2
92 #define CENTROID_OFSET 4
93
94 #define USE_SGPR_MAX_SUFFIX_LEN 5
95 #define CONST_ADDR_SPACE 2
96 #define LOCAL_ADDR_SPACE 3
97 #define USER_SGPR_ADDR_SPACE 8
98
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108
109 /**
110 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
111 *
112 * @param offset The offset parameter specifies the number of
113 * elements to offset, not the number of bytes or dwords. An element is the
114 * the type pointed to by the base_ptr parameter (e.g. int is the element of
115 * an int* pointer)
116 *
117 * When LLVM lowers the load instruction, it will convert the element offset
118 * into a dword offset automatically.
119 *
120 */
121 static LLVMValueRef build_indexed_load(
122 struct si_shader_context * si_shader_ctx,
123 LLVMValueRef base_ptr,
124 LLVMValueRef offset)
125 {
126 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
127
128 LLVMValueRef indices[2] = {
129 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
130 offset
131 };
132 LLVMValueRef computed_ptr = LLVMBuildGEP(
133 base->gallivm->builder, base_ptr, indices, 2, "");
134
135 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
136 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
137 return result;
138 }
139
140 static LLVMValueRef get_instance_index_for_fetch(
141 struct radeon_llvm_context * radeon_bld,
142 unsigned divisor)
143 {
144 struct si_shader_context *si_shader_ctx =
145 si_shader_context(&radeon_bld->soa.bld_base);
146 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
147
148 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
149 si_shader_ctx->param_instance_id);
150 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
151 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
152
153 if (divisor > 1)
154 result = LLVMBuildUDiv(gallivm->builder, result,
155 lp_build_const_int32(gallivm, divisor), "");
156
157 return result;
158 }
159
160 static int si_store_shader_io_attribs(struct si_shader *shader,
161 const struct tgsi_full_declaration *d)
162 {
163 int i = -1;
164
165 switch (d->Declaration.File) {
166 case TGSI_FILE_INPUT:
167 i = shader->ninput++;
168 assert(i < Elements(shader->input));
169 shader->input[i].name = d->Semantic.Name;
170 shader->input[i].sid = d->Semantic.Index;
171 shader->input[i].index = d->Range.First;
172 shader->input[i].interpolate = d->Interp.Interpolate;
173 shader->input[i].centroid = d->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID;
174 return -1;
175
176 case TGSI_FILE_OUTPUT:
177 i = shader->noutput++;
178 assert(i < Elements(shader->output));
179 shader->output[i].name = d->Semantic.Name;
180 shader->output[i].sid = d->Semantic.Index;
181 shader->output[i].index = d->Range.First;
182 shader->output[i].usage = d->Declaration.UsageMask;
183 break;
184 }
185
186 return i;
187 }
188
189 static void declare_input_vs(
190 struct radeon_llvm_context *radeon_bld,
191 unsigned input_index,
192 const struct tgsi_full_declaration *decl)
193 {
194 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
195 struct gallivm_state *gallivm = base->gallivm;
196 struct si_shader_context *si_shader_ctx =
197 si_shader_context(&radeon_bld->soa.bld_base);
198 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
199
200 unsigned chan;
201
202 LLVMValueRef t_list_ptr;
203 LLVMValueRef t_offset;
204 LLVMValueRef t_list;
205 LLVMValueRef attribute_offset;
206 LLVMValueRef buffer_index;
207 LLVMValueRef args[3];
208 LLVMTypeRef vec4_type;
209 LLVMValueRef input;
210
211 /* Load the T list */
212 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
213
214 t_offset = lp_build_const_int32(gallivm, input_index);
215
216 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
217
218 /* Build the attribute offset */
219 attribute_offset = lp_build_const_int32(gallivm, 0);
220
221 if (divisor) {
222 /* Build index from instance ID, start instance and divisor */
223 si_shader_ctx->shader->shader.uses_instanceid = true;
224 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
225 } else {
226 /* Load the buffer index for vertices. */
227 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
228 si_shader_ctx->param_vertex_id);
229 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
230 SI_PARAM_BASE_VERTEX);
231 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
232 }
233
234 vec4_type = LLVMVectorType(base->elem_type, 4);
235 args[0] = t_list;
236 args[1] = attribute_offset;
237 args[2] = buffer_index;
238 input = build_intrinsic(gallivm->builder,
239 "llvm.SI.vs.load.input", vec4_type, args, 3,
240 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
241
242 /* Break up the vec4 into individual components */
243 for (chan = 0; chan < 4; chan++) {
244 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
245 /* XXX: Use a helper function for this. There is one in
246 * tgsi_llvm.c. */
247 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
248 LLVMBuildExtractElement(gallivm->builder,
249 input, llvm_chan, "");
250 }
251 }
252
253 static void declare_input_gs(
254 struct radeon_llvm_context *radeon_bld,
255 unsigned input_index,
256 const struct tgsi_full_declaration *decl)
257 {
258 struct si_shader_context *si_shader_ctx =
259 si_shader_context(&radeon_bld->soa.bld_base);
260 struct si_shader *shader = &si_shader_ctx->shader->shader;
261
262 si_store_shader_io_attribs(shader, decl);
263
264 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID)
265 shader->input[input_index].param_offset = shader->nparam++;
266 }
267
268 static LLVMValueRef fetch_input_gs(
269 struct lp_build_tgsi_context *bld_base,
270 const struct tgsi_full_src_register *reg,
271 enum tgsi_opcode_type type,
272 unsigned swizzle)
273 {
274 struct lp_build_context *base = &bld_base->base;
275 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
276 struct si_shader *shader = &si_shader_ctx->shader->shader;
277 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
278 struct gallivm_state *gallivm = base->gallivm;
279 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
280 LLVMValueRef vtx_offset;
281 LLVMValueRef t_list_ptr;
282 LLVMValueRef t_list;
283 LLVMValueRef args[9];
284 unsigned vtx_offset_param;
285
286 if (swizzle != ~0 &&
287 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
288 if (swizzle == 0)
289 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
290 SI_PARAM_PRIMITIVE_ID);
291 else
292 return uint->zero;
293 }
294
295 if (!reg->Register.Dimension)
296 return NULL;
297
298 if (swizzle == ~0) {
299 LLVMValueRef values[TGSI_NUM_CHANNELS];
300 unsigned chan;
301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
302 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
303 }
304 return lp_build_gather_values(bld_base->base.gallivm, values,
305 TGSI_NUM_CHANNELS);
306 }
307
308 /* Get the vertex offset parameter */
309 vtx_offset_param = reg->Dimension.Index;
310 if (vtx_offset_param < 2) {
311 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
312 } else {
313 assert(vtx_offset_param < 6);
314 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
315 }
316 vtx_offset = lp_build_mul_imm(uint,
317 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
318 vtx_offset_param),
319 4);
320
321 /* Load the ESGS ring resource descriptor */
322 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
323 SI_PARAM_RW_BUFFERS);
324 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
325 lp_build_const_int32(gallivm, SI_RING_ESGS));
326
327 args[0] = t_list;
328 args[1] = vtx_offset;
329 args[2] = lp_build_const_int32(gallivm,
330 ((shader->input[reg->Register.Index].param_offset * 4) +
331 swizzle) * 256);
332 args[3] = uint->zero;
333 args[4] = uint->one; /* OFFEN */
334 args[5] = uint->zero; /* IDXEN */
335 args[6] = uint->one; /* GLC */
336 args[7] = uint->zero; /* SLC */
337 args[8] = uint->zero; /* TFE */
338
339 return LLVMBuildBitCast(gallivm->builder,
340 build_intrinsic(gallivm->builder,
341 "llvm.SI.buffer.load.dword.i32.i32",
342 i32, args, 9,
343 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
344 tgsi2llvmtype(bld_base, type), "");
345 }
346
347 static void declare_input_fs(
348 struct radeon_llvm_context *radeon_bld,
349 unsigned input_index,
350 const struct tgsi_full_declaration *decl)
351 {
352 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
353 struct si_shader_context *si_shader_ctx =
354 si_shader_context(&radeon_bld->soa.bld_base);
355 struct si_shader *shader = &si_shader_ctx->shader->shader;
356 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
357 struct gallivm_state *gallivm = base->gallivm;
358 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
359 LLVMValueRef main_fn = radeon_bld->main_fn;
360
361 LLVMValueRef interp_param;
362 const char * intr_name;
363
364 /* This value is:
365 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
366 * quad begins a new primitive. Bit 0 always needs
367 * to be unset)
368 * [32:16] ParamOffset
369 *
370 */
371 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
372 LLVMValueRef attr_number;
373
374 unsigned chan;
375
376 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
377 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
378 unsigned soa_index =
379 radeon_llvm_reg_index_soa(input_index, chan);
380 radeon_bld->inputs[soa_index] =
381 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
382
383 if (chan == 3)
384 /* RCP for fragcoord.w */
385 radeon_bld->inputs[soa_index] =
386 LLVMBuildFDiv(gallivm->builder,
387 lp_build_const_float(gallivm, 1.0f),
388 radeon_bld->inputs[soa_index],
389 "");
390 }
391 return;
392 }
393
394 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
395 LLVMValueRef face, is_face_positive;
396
397 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
398
399 is_face_positive = LLVMBuildFCmp(gallivm->builder,
400 LLVMRealUGT, face,
401 lp_build_const_float(gallivm, 0.0f),
402 "");
403
404 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
405 LLVMBuildSelect(gallivm->builder,
406 is_face_positive,
407 lp_build_const_float(gallivm, 1.0f),
408 lp_build_const_float(gallivm, 0.0f),
409 "");
410 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
411 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
412 lp_build_const_float(gallivm, 0.0f);
413 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
414 lp_build_const_float(gallivm, 1.0f);
415
416 return;
417 }
418
419 shader->input[input_index].param_offset = shader->nparam++;
420 attr_number = lp_build_const_int32(gallivm,
421 shader->input[input_index].param_offset);
422
423 switch (decl->Interp.Interpolate) {
424 case TGSI_INTERPOLATE_CONSTANT:
425 interp_param = 0;
426 break;
427 case TGSI_INTERPOLATE_LINEAR:
428 if (si_shader_ctx->shader->key.ps.interp_at_sample)
429 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
430 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
431 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
432 else
433 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
434 break;
435 case TGSI_INTERPOLATE_COLOR:
436 if (si_shader_ctx->shader->key.ps.flatshade) {
437 interp_param = 0;
438 break;
439 }
440 /* fall through to perspective */
441 case TGSI_INTERPOLATE_PERSPECTIVE:
442 if (si_shader_ctx->shader->key.ps.interp_at_sample)
443 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
444 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
445 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
446 else
447 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
448 break;
449 default:
450 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
451 return;
452 }
453
454 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
455
456 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
457 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
458 si_shader_ctx->shader->key.ps.color_two_side) {
459 LLVMValueRef args[4];
460 LLVMValueRef face, is_face_positive;
461 LLVMValueRef back_attr_number =
462 lp_build_const_int32(gallivm,
463 shader->input[input_index].param_offset + 1);
464
465 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
466
467 is_face_positive = LLVMBuildFCmp(gallivm->builder,
468 LLVMRealUGT, face,
469 lp_build_const_float(gallivm, 0.0f),
470 "");
471
472 args[2] = params;
473 args[3] = interp_param;
474 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
475 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
476 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
477 LLVMValueRef front, back;
478
479 args[0] = llvm_chan;
480 args[1] = attr_number;
481 front = build_intrinsic(gallivm->builder, intr_name,
482 input_type, args, args[3] ? 4 : 3,
483 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
484
485 args[1] = back_attr_number;
486 back = build_intrinsic(gallivm->builder, intr_name,
487 input_type, args, args[3] ? 4 : 3,
488 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
489
490 radeon_bld->inputs[soa_index] =
491 LLVMBuildSelect(gallivm->builder,
492 is_face_positive,
493 front,
494 back,
495 "");
496 }
497
498 shader->nparam++;
499 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
500 LLVMValueRef args[4];
501
502 args[0] = uint->zero;
503 args[1] = attr_number;
504 args[2] = params;
505 args[3] = interp_param;
506 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
507 build_intrinsic(gallivm->builder, intr_name,
508 input_type, args, args[3] ? 4 : 3,
509 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
511 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
512 lp_build_const_float(gallivm, 0.0f);
513 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
514 lp_build_const_float(gallivm, 1.0f);
515 } else {
516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
517 LLVMValueRef args[4];
518 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
519 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
520 args[0] = llvm_chan;
521 args[1] = attr_number;
522 args[2] = params;
523 args[3] = interp_param;
524 radeon_bld->inputs[soa_index] =
525 build_intrinsic(gallivm->builder, intr_name,
526 input_type, args, args[3] ? 4 : 3,
527 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
528 }
529 }
530 }
531
532 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
533 {
534 struct gallivm_state *gallivm = &radeon_bld->gallivm;
535 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
536 SI_PARAM_ANCILLARY);
537 value = LLVMBuildLShr(gallivm->builder, value,
538 lp_build_const_int32(gallivm, 8), "");
539 value = LLVMBuildAnd(gallivm->builder, value,
540 lp_build_const_int32(gallivm, 0xf), "");
541 return value;
542 }
543
544 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
545 LLVMValueRef offset, LLVMTypeRef return_type)
546 {
547 LLVMValueRef args[2] = {resource, offset};
548
549 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
550 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
551 }
552
553 static void declare_system_value(
554 struct radeon_llvm_context * radeon_bld,
555 unsigned index,
556 const struct tgsi_full_declaration *decl)
557 {
558 struct si_shader_context *si_shader_ctx =
559 si_shader_context(&radeon_bld->soa.bld_base);
560 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
561 struct gallivm_state *gallivm = &radeon_bld->gallivm;
562 LLVMValueRef value = 0;
563
564 switch (decl->Semantic.Name) {
565 case TGSI_SEMANTIC_INSTANCEID:
566 value = LLVMGetParam(radeon_bld->main_fn,
567 si_shader_ctx->param_instance_id);
568 break;
569
570 case TGSI_SEMANTIC_VERTEXID:
571 value = LLVMGetParam(radeon_bld->main_fn,
572 si_shader_ctx->param_vertex_id);
573 break;
574
575 case TGSI_SEMANTIC_SAMPLEID:
576 value = get_sample_id(radeon_bld);
577 break;
578
579 case TGSI_SEMANTIC_SAMPLEPOS:
580 {
581 LLVMBuilderRef builder = gallivm->builder;
582 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
583 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
584 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
585
586 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
587 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
588 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
589
590 LLVMValueRef pos[4] = {
591 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
592 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
593 lp_build_const_float(gallivm, 0),
594 lp_build_const_float(gallivm, 0)
595 };
596 value = lp_build_gather_values(gallivm, pos, 4);
597 break;
598 }
599
600 default:
601 assert(!"unknown system value");
602 return;
603 }
604
605 radeon_bld->system_values[index] = value;
606 }
607
608 static LLVMValueRef fetch_constant(
609 struct lp_build_tgsi_context * bld_base,
610 const struct tgsi_full_src_register *reg,
611 enum tgsi_opcode_type type,
612 unsigned swizzle)
613 {
614 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
615 struct lp_build_context * base = &bld_base->base;
616 const struct tgsi_ind_register *ireg = &reg->Indirect;
617 unsigned buf, idx;
618
619 LLVMValueRef addr;
620 LLVMValueRef result;
621
622 if (swizzle == LP_CHAN_ALL) {
623 unsigned chan;
624 LLVMValueRef values[4];
625 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
626 values[chan] = fetch_constant(bld_base, reg, type, chan);
627
628 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
629 }
630
631 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
632 idx = reg->Register.Index * 4 + swizzle;
633
634 if (!reg->Register.Indirect)
635 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
636
637 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
638 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
639 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
640 addr = lp_build_add(&bld_base->uint_bld, addr,
641 lp_build_const_int32(base->gallivm, idx * 4));
642
643 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
644 addr, base->elem_type);
645
646 return bitcast(bld_base, type, result);
647 }
648
649 /* Initialize arguments for the shader export intrinsic */
650 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
651 LLVMValueRef *values,
652 unsigned target,
653 LLVMValueRef *args)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct lp_build_context *uint =
657 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
658 struct lp_build_context *base = &bld_base->base;
659 unsigned compressed = 0;
660 unsigned chan;
661
662 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
663 int cbuf = target - V_008DFC_SQ_EXP_MRT;
664
665 if (cbuf >= 0 && cbuf < 8) {
666 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
667
668 if (compressed)
669 si_shader_ctx->shader->spi_shader_col_format |=
670 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
671 else
672 si_shader_ctx->shader->spi_shader_col_format |=
673 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
674
675 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
676 }
677 }
678
679 if (compressed) {
680 /* Pixel shader needs to pack output values before export */
681 for (chan = 0; chan < 2; chan++ ) {
682 args[0] = values[2 * chan];
683 args[1] = values[2 * chan + 1];
684 args[chan + 5] =
685 build_intrinsic(base->gallivm->builder,
686 "llvm.SI.packf16",
687 LLVMInt32TypeInContext(base->gallivm->context),
688 args, 2,
689 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
690 args[chan + 7] = args[chan + 5] =
691 LLVMBuildBitCast(base->gallivm->builder,
692 args[chan + 5],
693 LLVMFloatTypeInContext(base->gallivm->context),
694 "");
695 }
696
697 /* Set COMPR flag */
698 args[4] = uint->one;
699 } else {
700 for (chan = 0; chan < 4; chan++ )
701 /* +5 because the first output value will be
702 * the 6th argument to the intrinsic. */
703 args[chan + 5] = values[chan];
704
705 /* Clear COMPR flag */
706 args[4] = uint->zero;
707 }
708
709 /* XXX: This controls which components of the output
710 * registers actually get exported. (e.g bit 0 means export
711 * X component, bit 1 means export Y component, etc.) I'm
712 * hard coding this to 0xf for now. In the future, we might
713 * want to do something else. */
714 args[0] = lp_build_const_int32(base->gallivm, 0xf);
715
716 /* Specify whether the EXEC mask represents the valid mask */
717 args[1] = uint->zero;
718
719 /* Specify whether this is the last export */
720 args[2] = uint->zero;
721
722 /* Specify the target we are exporting */
723 args[3] = lp_build_const_int32(base->gallivm, target);
724
725 /* XXX: We probably need to keep track of the output
726 * values, so we know what we are passing to the next
727 * stage. */
728 }
729
730 /* Load from output pointers and initialize arguments for the shader export intrinsic */
731 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
732 LLVMValueRef *out_ptr,
733 unsigned target,
734 LLVMValueRef *args)
735 {
736 struct gallivm_state *gallivm = bld_base->base.gallivm;
737 LLVMValueRef values[4];
738 int i;
739
740 for (i = 0; i < 4; i++)
741 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
742
743 si_llvm_init_export_args(bld_base, values, target, args);
744 }
745
746 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
747 LLVMValueRef *out_ptr)
748 {
749 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
750 struct gallivm_state *gallivm = bld_base->base.gallivm;
751
752 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
753 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
754 SI_PARAM_ALPHA_REF);
755
756 LLVMValueRef alpha_pass =
757 lp_build_cmp(&bld_base->base,
758 si_shader_ctx->shader->key.ps.alpha_func,
759 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
760 alpha_ref);
761 LLVMValueRef arg =
762 lp_build_select(&bld_base->base,
763 alpha_pass,
764 lp_build_const_float(gallivm, 1.0f),
765 lp_build_const_float(gallivm, -1.0f));
766
767 build_intrinsic(gallivm->builder,
768 "llvm.AMDGPU.kill",
769 LLVMVoidTypeInContext(gallivm->context),
770 &arg, 1, 0);
771 } else {
772 build_intrinsic(gallivm->builder,
773 "llvm.AMDGPU.kilp",
774 LLVMVoidTypeInContext(gallivm->context),
775 NULL, 0, 0);
776 }
777 }
778
779 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
780 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
781 {
782 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
783 struct si_pipe_shader *shader = si_shader_ctx->shader;
784 struct lp_build_context *base = &bld_base->base;
785 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
786 unsigned reg_index;
787 unsigned chan;
788 unsigned const_chan;
789 LLVMValueRef base_elt;
790 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
791 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
792 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
793
794 for (reg_index = 0; reg_index < 2; reg_index ++) {
795 LLVMValueRef *args = pos[2 + reg_index];
796
797 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
798 continue;
799
800 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
801
802 args[5] =
803 args[6] =
804 args[7] =
805 args[8] = lp_build_const_float(base->gallivm, 0.0f);
806
807 /* Compute dot products of position and user clip plane vectors */
808 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
809 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
810 args[1] = lp_build_const_int32(base->gallivm,
811 ((reg_index * 4 + chan) * 4 +
812 const_chan) * 4);
813 base_elt = load_const(base->gallivm->builder, const_resource,
814 args[1], base->elem_type);
815 args[5 + chan] =
816 lp_build_add(base, args[5 + chan],
817 lp_build_mul(base, base_elt,
818 out_elts[const_chan]));
819 }
820 }
821
822 args[0] = lp_build_const_int32(base->gallivm, 0xf);
823 args[1] = uint->zero;
824 args[2] = uint->zero;
825 args[3] = lp_build_const_int32(base->gallivm,
826 V_008DFC_SQ_EXP_POS + 2 + reg_index);
827 args[4] = uint->zero;
828 }
829 }
830
831 static void si_dump_streamout(struct pipe_stream_output_info *so)
832 {
833 unsigned i;
834
835 if (so->num_outputs)
836 fprintf(stderr, "STREAMOUT\n");
837
838 for (i = 0; i < so->num_outputs; i++) {
839 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
840 so->output[i].start_component;
841 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
842 i, so->output[i].output_buffer,
843 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
844 so->output[i].register_index,
845 mask & 1 ? "x" : "",
846 mask & 2 ? "y" : "",
847 mask & 4 ? "z" : "",
848 mask & 8 ? "w" : "");
849 }
850 }
851
852 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
853 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
854 * or v4i32 (num_channels=3,4). */
855 static void build_tbuffer_store(struct si_shader_context *shader,
856 LLVMValueRef rsrc,
857 LLVMValueRef vdata,
858 unsigned num_channels,
859 LLVMValueRef vaddr,
860 LLVMValueRef soffset,
861 unsigned inst_offset,
862 unsigned dfmt,
863 unsigned nfmt,
864 unsigned offen,
865 unsigned idxen,
866 unsigned glc,
867 unsigned slc,
868 unsigned tfe)
869 {
870 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
871 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
872 LLVMValueRef args[] = {
873 rsrc,
874 vdata,
875 LLVMConstInt(i32, num_channels, 0),
876 vaddr,
877 soffset,
878 LLVMConstInt(i32, inst_offset, 0),
879 LLVMConstInt(i32, dfmt, 0),
880 LLVMConstInt(i32, nfmt, 0),
881 LLVMConstInt(i32, offen, 0),
882 LLVMConstInt(i32, idxen, 0),
883 LLVMConstInt(i32, glc, 0),
884 LLVMConstInt(i32, slc, 0),
885 LLVMConstInt(i32, tfe, 0)
886 };
887
888 /* The instruction offset field has 12 bits */
889 assert(offen || inst_offset < (1 << 12));
890
891 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
892 unsigned func = CLAMP(num_channels, 1, 3) - 1;
893 const char *types[] = {"i32", "v2i32", "v4i32"};
894 char name[256];
895 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
896
897 lp_build_intrinsic(gallivm->builder, name,
898 LLVMVoidTypeInContext(gallivm->context),
899 args, Elements(args));
900 }
901
902 static void build_streamout_store(struct si_shader_context *shader,
903 LLVMValueRef rsrc,
904 LLVMValueRef vdata,
905 unsigned num_channels,
906 LLVMValueRef vaddr,
907 LLVMValueRef soffset,
908 unsigned inst_offset)
909 {
910 static unsigned dfmt[] = {
911 V_008F0C_BUF_DATA_FORMAT_32,
912 V_008F0C_BUF_DATA_FORMAT_32_32,
913 V_008F0C_BUF_DATA_FORMAT_32_32_32,
914 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
915 };
916 assert(num_channels >= 1 && num_channels <= 4);
917
918 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
919 inst_offset, dfmt[num_channels-1],
920 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
921 }
922
923 /* On SI, the vertex shader is responsible for writing streamout data
924 * to buffers. */
925 static void si_llvm_emit_streamout(struct si_shader_context *shader,
926 struct si_shader_output_values *outputs,
927 unsigned noutput)
928 {
929 struct pipe_stream_output_info *so = &shader->shader->selector->so;
930 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
931 LLVMBuilderRef builder = gallivm->builder;
932 int i, j;
933 struct lp_build_if_state if_ctx;
934
935 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
936
937 LLVMValueRef so_param =
938 LLVMGetParam(shader->radeon_bld.main_fn,
939 shader->param_streamout_config);
940
941 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
942 LLVMValueRef so_vtx_count =
943 LLVMBuildAnd(builder,
944 LLVMBuildLShr(builder, so_param,
945 LLVMConstInt(i32, 16, 0), ""),
946 LLVMConstInt(i32, 127, 0), "");
947
948 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
949 NULL, 0, LLVMReadNoneAttribute);
950
951 /* can_emit = tid < so_vtx_count; */
952 LLVMValueRef can_emit =
953 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
954
955 /* Emit the streamout code conditionally. This actually avoids
956 * out-of-bounds buffer access. The hw tells us via the SGPR
957 * (so_vtx_count) which threads are allowed to emit streamout data. */
958 lp_build_if(&if_ctx, gallivm, can_emit);
959 {
960 /* The buffer offset is computed as follows:
961 * ByteOffset = streamout_offset[buffer_id]*4 +
962 * (streamout_write_index + thread_id)*stride[buffer_id] +
963 * attrib_offset
964 */
965
966 LLVMValueRef so_write_index =
967 LLVMGetParam(shader->radeon_bld.main_fn,
968 shader->param_streamout_write_index);
969
970 /* Compute (streamout_write_index + thread_id). */
971 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
972
973 /* Compute the write offset for each enabled buffer. */
974 LLVMValueRef so_write_offset[4] = {};
975 for (i = 0; i < 4; i++) {
976 if (!so->stride[i])
977 continue;
978
979 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
980 shader->param_streamout_offset[i]);
981 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
982
983 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
984 LLVMConstInt(i32, so->stride[i]*4, 0), "");
985 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
986 }
987
988 /* Write streamout data. */
989 for (i = 0; i < so->num_outputs; i++) {
990 unsigned buf_idx = so->output[i].output_buffer;
991 unsigned reg = so->output[i].register_index;
992 unsigned start = so->output[i].start_component;
993 unsigned num_comps = so->output[i].num_components;
994 LLVMValueRef out[4];
995
996 assert(num_comps && num_comps <= 4);
997 if (!num_comps || num_comps > 4)
998 continue;
999
1000 /* Load the output as int. */
1001 for (j = 0; j < num_comps; j++) {
1002 unsigned outidx = 0;
1003
1004 while (outidx < noutput && outputs[outidx].index != reg)
1005 outidx++;
1006
1007 if (outidx < noutput)
1008 out[j] = LLVMBuildBitCast(builder,
1009 outputs[outidx].values[start+j],
1010 i32, "");
1011 else
1012 out[j] = NULL;
1013 }
1014
1015 if (!out[0])
1016 continue;
1017
1018 /* Pack the output. */
1019 LLVMValueRef vdata = NULL;
1020
1021 switch (num_comps) {
1022 case 1: /* as i32 */
1023 vdata = out[0];
1024 break;
1025 case 2: /* as v2i32 */
1026 case 3: /* as v4i32 (aligned to 4) */
1027 case 4: /* as v4i32 */
1028 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1029 for (j = 0; j < num_comps; j++) {
1030 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1031 LLVMConstInt(i32, j, 0), "");
1032 }
1033 break;
1034 }
1035
1036 build_streamout_store(shader, shader->so_buffers[buf_idx],
1037 vdata, num_comps,
1038 so_write_offset[buf_idx],
1039 LLVMConstInt(i32, 0, 0),
1040 so->output[i].dst_offset*4);
1041 }
1042 }
1043 lp_build_endif(&if_ctx);
1044 }
1045
1046
1047 /* Generate export instructions for hardware VS shader stage */
1048 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1049 struct si_shader_output_values *outputs,
1050 unsigned noutput)
1051 {
1052 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1053 struct si_shader * shader = &si_shader_ctx->shader->shader;
1054 struct lp_build_context * base = &bld_base->base;
1055 struct lp_build_context * uint =
1056 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1057 LLVMValueRef args[9];
1058 LLVMValueRef pos_args[4][9] = { { 0 } };
1059 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1060 unsigned semantic_name, semantic_index, semantic_usage;
1061 unsigned target;
1062 unsigned param_count = 0;
1063 unsigned pos_idx;
1064 int i;
1065
1066 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1067 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1068 }
1069
1070 for (i = 0; i < noutput; i++) {
1071 semantic_name = outputs[i].name;
1072 semantic_index = outputs[i].sid;
1073 semantic_usage = outputs[i].usage;
1074
1075 handle_semantic:
1076 /* Select the correct target */
1077 switch(semantic_name) {
1078 case TGSI_SEMANTIC_PSIZE:
1079 shader->vs_out_misc_write = true;
1080 shader->vs_out_point_size = true;
1081 psize_value = outputs[i].values[0];
1082 continue;
1083 case TGSI_SEMANTIC_EDGEFLAG:
1084 shader->vs_out_misc_write = true;
1085 shader->vs_out_edgeflag = true;
1086 edgeflag_value = outputs[i].values[0];
1087 continue;
1088 case TGSI_SEMANTIC_LAYER:
1089 shader->vs_out_misc_write = true;
1090 shader->vs_out_layer = true;
1091 layer_value = outputs[i].values[0];
1092 continue;
1093 case TGSI_SEMANTIC_POSITION:
1094 target = V_008DFC_SQ_EXP_POS;
1095 break;
1096 case TGSI_SEMANTIC_COLOR:
1097 case TGSI_SEMANTIC_BCOLOR:
1098 target = V_008DFC_SQ_EXP_PARAM + param_count;
1099 shader->output[i].param_offset = param_count;
1100 param_count++;
1101 break;
1102 case TGSI_SEMANTIC_CLIPDIST:
1103 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1104 (1 << semantic_index)))
1105 continue;
1106 shader->clip_dist_write |=
1107 semantic_usage << (semantic_index << 2);
1108 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1109 break;
1110 case TGSI_SEMANTIC_CLIPVERTEX:
1111 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1112 continue;
1113 case TGSI_SEMANTIC_PRIMID:
1114 case TGSI_SEMANTIC_FOG:
1115 case TGSI_SEMANTIC_GENERIC:
1116 target = V_008DFC_SQ_EXP_PARAM + param_count;
1117 shader->output[i].param_offset = param_count;
1118 param_count++;
1119 break;
1120 default:
1121 target = 0;
1122 fprintf(stderr,
1123 "Warning: SI unhandled vs output type:%d\n",
1124 semantic_name);
1125 }
1126
1127 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1128
1129 if (target >= V_008DFC_SQ_EXP_POS &&
1130 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1131 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1132 args, sizeof(args));
1133 } else {
1134 lp_build_intrinsic(base->gallivm->builder,
1135 "llvm.SI.export",
1136 LLVMVoidTypeInContext(base->gallivm->context),
1137 args, 9);
1138 }
1139
1140 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1141 semantic_name = TGSI_SEMANTIC_GENERIC;
1142 goto handle_semantic;
1143 }
1144 }
1145
1146 /* We need to add the position output manually if it's missing. */
1147 if (!pos_args[0][0]) {
1148 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1149 pos_args[0][1] = uint->zero; /* EXEC mask */
1150 pos_args[0][2] = uint->zero; /* last export? */
1151 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1152 pos_args[0][4] = uint->zero; /* COMPR flag */
1153 pos_args[0][5] = base->zero; /* X */
1154 pos_args[0][6] = base->zero; /* Y */
1155 pos_args[0][7] = base->zero; /* Z */
1156 pos_args[0][8] = base->one; /* W */
1157 }
1158
1159 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1160 if (shader->vs_out_misc_write) {
1161 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1162 shader->vs_out_point_size |
1163 (shader->vs_out_edgeflag << 1) |
1164 (shader->vs_out_layer << 2));
1165 pos_args[1][1] = uint->zero; /* EXEC mask */
1166 pos_args[1][2] = uint->zero; /* last export? */
1167 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1168 pos_args[1][4] = uint->zero; /* COMPR flag */
1169 pos_args[1][5] = base->zero; /* X */
1170 pos_args[1][6] = base->zero; /* Y */
1171 pos_args[1][7] = base->zero; /* Z */
1172 pos_args[1][8] = base->zero; /* W */
1173
1174 if (shader->vs_out_point_size)
1175 pos_args[1][5] = psize_value;
1176
1177 if (shader->vs_out_edgeflag) {
1178 /* The output is a float, but the hw expects an integer
1179 * with the first bit containing the edge flag. */
1180 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1181 edgeflag_value,
1182 bld_base->uint_bld.elem_type, "");
1183 edgeflag_value = lp_build_min(&bld_base->int_bld,
1184 edgeflag_value,
1185 bld_base->int_bld.one);
1186
1187 /* The LLVM intrinsic expects a float. */
1188 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1189 edgeflag_value,
1190 base->elem_type, "");
1191 }
1192
1193 if (shader->vs_out_layer)
1194 pos_args[1][7] = layer_value;
1195 }
1196
1197 for (i = 0; i < 4; i++)
1198 if (pos_args[i][0])
1199 shader->nr_pos_exports++;
1200
1201 pos_idx = 0;
1202 for (i = 0; i < 4; i++) {
1203 if (!pos_args[i][0])
1204 continue;
1205
1206 /* Specify the target we are exporting */
1207 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1208
1209 if (pos_idx == shader->nr_pos_exports)
1210 /* Specify that this is the last export */
1211 pos_args[i][2] = uint->one;
1212
1213 lp_build_intrinsic(base->gallivm->builder,
1214 "llvm.SI.export",
1215 LLVMVoidTypeInContext(base->gallivm->context),
1216 pos_args[i], 9);
1217 }
1218 }
1219
1220 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1221 {
1222 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1223 struct gallivm_state *gallivm = bld_base->base.gallivm;
1224 struct si_shader *es = &si_shader_ctx->shader->shader;
1225 struct si_shader *gs = si_shader_ctx->gs_for_vs;
1226 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1227 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1228 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1229 SI_PARAM_ES2GS_OFFSET);
1230 LLVMValueRef t_list_ptr;
1231 LLVMValueRef t_list;
1232 unsigned chan;
1233 int i;
1234
1235 while (!tgsi_parse_end_of_tokens(parse)) {
1236 struct tgsi_full_declaration *d =
1237 &parse->FullToken.FullDeclaration;
1238
1239 tgsi_parse_token(parse);
1240
1241 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1242 continue;
1243
1244 si_store_shader_io_attribs(es, d);
1245 }
1246
1247 /* Load the ESGS ring resource descriptor */
1248 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1249 SI_PARAM_RW_BUFFERS);
1250 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1251 lp_build_const_int32(gallivm, SI_RING_ESGS));
1252
1253 for (i = 0; i < es->noutput; i++) {
1254 LLVMValueRef *out_ptr =
1255 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1256 int j;
1257
1258 for (j = 0; j < gs->ninput; j++) {
1259 if (gs->input[j].name == es->output[i].name &&
1260 gs->input[j].sid == es->output[i].sid)
1261 break;
1262 }
1263 if (j == gs->ninput)
1264 continue;
1265
1266 for (chan = 0; chan < 4; chan++) {
1267 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1268 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1269
1270 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1271 LLVMGetUndef(i32), soffset,
1272 (4 * gs->input[j].param_offset + chan) * 4,
1273 V_008F0C_BUF_DATA_FORMAT_32,
1274 V_008F0C_BUF_NUM_FORMAT_UINT,
1275 0, 0, 1, 1, 0);
1276 }
1277 }
1278 }
1279
1280 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1281 {
1282 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1283 struct gallivm_state *gallivm = bld_base->base.gallivm;
1284 LLVMValueRef args[2];
1285
1286 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1287 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1288 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1289 LLVMVoidTypeInContext(gallivm->context), args, 2,
1290 LLVMNoUnwindAttribute);
1291 }
1292
1293 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1294 {
1295 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1296 struct gallivm_state *gallivm = bld_base->base.gallivm;
1297 struct si_pipe_shader *shader = si_shader_ctx->shader;
1298 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1299 struct si_shader_output_values *outputs = NULL;
1300 unsigned noutput = 0;
1301 int i;
1302
1303 while (!tgsi_parse_end_of_tokens(parse)) {
1304 struct tgsi_full_declaration *d =
1305 &parse->FullToken.FullDeclaration;
1306 unsigned index;
1307
1308 tgsi_parse_token(parse);
1309
1310 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1311 continue;
1312
1313 i = si_store_shader_io_attribs(&shader->shader, d);
1314 if (i < 0)
1315 continue;
1316
1317 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1318 (noutput + 1) * sizeof(outputs[0]));
1319 for (index = d->Range.First; index <= d->Range.Last; index++) {
1320 outputs[noutput].index = index;
1321 outputs[noutput].name = d->Semantic.Name;
1322 outputs[noutput].sid = d->Semantic.Index;
1323 outputs[noutput].usage = d->Declaration.UsageMask;
1324
1325 for (i = 0; i < 4; i++)
1326 outputs[noutput].values[i] =
1327 LLVMBuildLoad(gallivm->builder,
1328 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1329 "");
1330 }
1331 noutput++;
1332 }
1333
1334 si_llvm_export_vs(bld_base, outputs, noutput);
1335 FREE(outputs);
1336 }
1337
1338 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1339 {
1340 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1341 struct si_shader * shader = &si_shader_ctx->shader->shader;
1342 struct lp_build_context * base = &bld_base->base;
1343 struct lp_build_context * uint =
1344 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1345 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1346 LLVMValueRef args[9];
1347 LLVMValueRef last_args[9] = { 0 };
1348 unsigned semantic_name;
1349 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1350 int i;
1351
1352 while (!tgsi_parse_end_of_tokens(parse)) {
1353 struct tgsi_full_declaration *d =
1354 &parse->FullToken.FullDeclaration;
1355 unsigned target;
1356 unsigned index;
1357
1358 tgsi_parse_token(parse);
1359
1360 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1361 parse->FullToken.FullProperty.Property.PropertyName ==
1362 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1363 shader->fs_write_all = TRUE;
1364
1365 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1366 continue;
1367
1368 i = si_store_shader_io_attribs(shader, d);
1369 if (i < 0)
1370 continue;
1371
1372 semantic_name = d->Semantic.Name;
1373 for (index = d->Range.First; index <= d->Range.Last; index++) {
1374 /* Select the correct target */
1375 switch(semantic_name) {
1376 case TGSI_SEMANTIC_POSITION:
1377 depth_index = index;
1378 continue;
1379 case TGSI_SEMANTIC_STENCIL:
1380 stencil_index = index;
1381 continue;
1382 case TGSI_SEMANTIC_SAMPLEMASK:
1383 samplemask_index = index;
1384 continue;
1385 case TGSI_SEMANTIC_COLOR:
1386 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1387 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1388 LLVMBuildStore(bld_base->base.gallivm->builder,
1389 bld_base->base.one,
1390 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1391
1392 if (d->Semantic.Index == 0 &&
1393 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1394 si_alpha_test(bld_base,
1395 si_shader_ctx->radeon_bld.soa.outputs[index]);
1396 break;
1397 default:
1398 target = 0;
1399 fprintf(stderr,
1400 "Warning: SI unhandled fs output type:%d\n",
1401 semantic_name);
1402 }
1403
1404 si_llvm_init_export_args_load(bld_base,
1405 si_shader_ctx->radeon_bld.soa.outputs[index],
1406 target, args);
1407
1408 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1409 /* If there is an export instruction waiting to be emitted, do so now. */
1410 if (last_args[0]) {
1411 lp_build_intrinsic(base->gallivm->builder,
1412 "llvm.SI.export",
1413 LLVMVoidTypeInContext(base->gallivm->context),
1414 last_args, 9);
1415 }
1416
1417 /* This instruction will be emitted at the end of the shader. */
1418 memcpy(last_args, args, sizeof(args));
1419
1420 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1421 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1422 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1423 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1424 si_llvm_init_export_args_load(bld_base,
1425 si_shader_ctx->radeon_bld.soa.outputs[index],
1426 V_008DFC_SQ_EXP_MRT + c, args);
1427 lp_build_intrinsic(base->gallivm->builder,
1428 "llvm.SI.export",
1429 LLVMVoidTypeInContext(base->gallivm->context),
1430 args, 9);
1431 }
1432 }
1433 } else {
1434 lp_build_intrinsic(base->gallivm->builder,
1435 "llvm.SI.export",
1436 LLVMVoidTypeInContext(base->gallivm->context),
1437 args, 9);
1438 }
1439 }
1440 }
1441
1442 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1443 LLVMValueRef out_ptr;
1444 unsigned mask = 0;
1445
1446 /* Specify the target we are exporting */
1447 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1448
1449 args[5] = base->zero; /* R, depth */
1450 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1451 args[7] = base->zero; /* B, sample mask */
1452 args[8] = base->zero; /* A, alpha to mask */
1453
1454 if (depth_index >= 0) {
1455 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1456 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1457 mask |= 0x1;
1458 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1459 }
1460
1461 if (stencil_index >= 0) {
1462 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1463 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1464 /* Only setting the stencil component bit (0x2) here
1465 * breaks some stencil piglit tests
1466 */
1467 mask |= 0x3;
1468 si_shader_ctx->shader->db_shader_control |=
1469 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1470 }
1471
1472 if (samplemask_index >= 0) {
1473 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1474 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1475 mask |= 0xf; /* Set all components. */
1476 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1477 }
1478
1479 if (samplemask_index >= 0)
1480 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1481 else if (stencil_index >= 0)
1482 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1483 else
1484 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1485
1486 /* Specify which components to enable */
1487 args[0] = lp_build_const_int32(base->gallivm, mask);
1488
1489 args[1] =
1490 args[2] =
1491 args[4] = uint->zero;
1492
1493 if (last_args[0])
1494 lp_build_intrinsic(base->gallivm->builder,
1495 "llvm.SI.export",
1496 LLVMVoidTypeInContext(base->gallivm->context),
1497 args, 9);
1498 else
1499 memcpy(last_args, args, sizeof(args));
1500 }
1501
1502 if (!last_args[0]) {
1503 /* Specify which components to enable */
1504 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1505
1506 /* Specify the target we are exporting */
1507 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1508
1509 /* Set COMPR flag to zero to export data as 32-bit */
1510 last_args[4] = uint->zero;
1511
1512 /* dummy bits */
1513 last_args[5]= uint->zero;
1514 last_args[6]= uint->zero;
1515 last_args[7]= uint->zero;
1516 last_args[8]= uint->zero;
1517 }
1518
1519 /* Specify whether the EXEC mask represents the valid mask */
1520 last_args[1] = uint->one;
1521
1522 /* Specify that this is the last export */
1523 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1524
1525 lp_build_intrinsic(base->gallivm->builder,
1526 "llvm.SI.export",
1527 LLVMVoidTypeInContext(base->gallivm->context),
1528 last_args, 9);
1529 }
1530
1531 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1532 struct lp_build_tgsi_context * bld_base,
1533 struct lp_build_emit_data * emit_data);
1534
1535 static bool tgsi_is_shadow_sampler(unsigned target)
1536 {
1537 return target == TGSI_TEXTURE_SHADOW1D ||
1538 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1539 target == TGSI_TEXTURE_SHADOW2D ||
1540 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1541 target == TGSI_TEXTURE_SHADOWCUBE ||
1542 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1543 target == TGSI_TEXTURE_SHADOWRECT;
1544 }
1545
1546 static const struct lp_build_tgsi_action tex_action;
1547
1548 static void tex_fetch_args(
1549 struct lp_build_tgsi_context * bld_base,
1550 struct lp_build_emit_data * emit_data)
1551 {
1552 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1553 struct gallivm_state *gallivm = bld_base->base.gallivm;
1554 const struct tgsi_full_instruction * inst = emit_data->inst;
1555 unsigned opcode = inst->Instruction.Opcode;
1556 unsigned target = inst->Texture.Texture;
1557 LLVMValueRef coords[4];
1558 LLVMValueRef address[16];
1559 int ref_pos;
1560 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1561 unsigned count = 0;
1562 unsigned chan;
1563 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1564 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1565 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1566
1567 if (target == TGSI_TEXTURE_BUFFER) {
1568 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1569 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1570 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1571 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1572
1573 /* Bitcast and truncate v8i32 to v16i8. */
1574 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1575 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1576 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1577 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1578
1579 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1580 emit_data->args[0] = res;
1581 emit_data->args[1] = bld_base->uint_bld.zero;
1582 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1583 emit_data->arg_count = 3;
1584 return;
1585 }
1586
1587 /* Fetch and project texture coordinates */
1588 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1589 for (chan = 0; chan < 3; chan++ ) {
1590 coords[chan] = lp_build_emit_fetch(bld_base,
1591 emit_data->inst, 0,
1592 chan);
1593 if (opcode == TGSI_OPCODE_TXP)
1594 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1595 TGSI_OPCODE_DIV,
1596 coords[chan],
1597 coords[3]);
1598 }
1599
1600 if (opcode == TGSI_OPCODE_TXP)
1601 coords[3] = bld_base->base.one;
1602
1603 /* Pack offsets. */
1604 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1605 /* The offsets are six-bit signed integers packed like this:
1606 * X=[5:0], Y=[13:8], and Z=[21:16].
1607 */
1608 LLVMValueRef offset[3], pack;
1609
1610 assert(inst->Texture.NumOffsets == 1);
1611
1612 for (chan = 0; chan < 3; chan++) {
1613 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1614 emit_data->inst, 0, chan);
1615 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1616 lp_build_const_int32(gallivm, 0x3f), "");
1617 if (chan)
1618 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1619 lp_build_const_int32(gallivm, chan*8), "");
1620 }
1621
1622 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1623 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1624 address[count++] = pack;
1625 }
1626
1627 /* Pack LOD bias value */
1628 if (opcode == TGSI_OPCODE_TXB)
1629 address[count++] = coords[3];
1630 if (opcode == TGSI_OPCODE_TXB2)
1631 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1632
1633 /* Pack depth comparison value */
1634 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1635 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1636 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1637 } else {
1638 assert(ref_pos >= 0);
1639 address[count++] = coords[ref_pos];
1640 }
1641 }
1642
1643 if (target == TGSI_TEXTURE_CUBE ||
1644 target == TGSI_TEXTURE_CUBE_ARRAY ||
1645 target == TGSI_TEXTURE_SHADOWCUBE ||
1646 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1647 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1648
1649 /* Pack user derivatives */
1650 if (opcode == TGSI_OPCODE_TXD) {
1651 int num_deriv_channels, param;
1652
1653 switch (target) {
1654 case TGSI_TEXTURE_3D:
1655 num_deriv_channels = 3;
1656 break;
1657 case TGSI_TEXTURE_2D:
1658 case TGSI_TEXTURE_SHADOW2D:
1659 case TGSI_TEXTURE_RECT:
1660 case TGSI_TEXTURE_SHADOWRECT:
1661 case TGSI_TEXTURE_2D_ARRAY:
1662 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1663 case TGSI_TEXTURE_CUBE:
1664 case TGSI_TEXTURE_SHADOWCUBE:
1665 case TGSI_TEXTURE_CUBE_ARRAY:
1666 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1667 num_deriv_channels = 2;
1668 break;
1669 case TGSI_TEXTURE_1D:
1670 case TGSI_TEXTURE_SHADOW1D:
1671 case TGSI_TEXTURE_1D_ARRAY:
1672 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1673 num_deriv_channels = 1;
1674 break;
1675 default:
1676 assert(0); /* no other targets are valid here */
1677 }
1678
1679 for (param = 1; param <= 2; param++)
1680 for (chan = 0; chan < num_deriv_channels; chan++)
1681 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1682 }
1683
1684 /* Pack texture coordinates */
1685 address[count++] = coords[0];
1686 if (num_coords > 1)
1687 address[count++] = coords[1];
1688 if (num_coords > 2)
1689 address[count++] = coords[2];
1690
1691 /* Pack LOD or sample index */
1692 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1693 address[count++] = coords[3];
1694 else if (opcode == TGSI_OPCODE_TXL2)
1695 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1696
1697 if (count > 16) {
1698 assert(!"Cannot handle more than 16 texture address parameters");
1699 count = 16;
1700 }
1701
1702 for (chan = 0; chan < count; chan++ ) {
1703 address[chan] = LLVMBuildBitCast(gallivm->builder,
1704 address[chan],
1705 LLVMInt32TypeInContext(gallivm->context),
1706 "");
1707 }
1708
1709 /* Adjust the sample index according to FMASK.
1710 *
1711 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1712 * which is the identity mapping. Each nibble says which physical sample
1713 * should be fetched to get that sample.
1714 *
1715 * For example, 0x11111100 means there are only 2 samples stored and
1716 * the second sample covers 3/4 of the pixel. When reading samples 0
1717 * and 1, return physical sample 0 (determined by the first two 0s
1718 * in FMASK), otherwise return physical sample 1.
1719 *
1720 * The sample index should be adjusted as follows:
1721 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1722 */
1723 if (target == TGSI_TEXTURE_2D_MSAA ||
1724 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1725 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1726 struct lp_build_emit_data txf_emit_data = *emit_data;
1727 LLVMValueRef txf_address[4];
1728 unsigned txf_count = count;
1729 struct tgsi_full_instruction inst = {};
1730
1731 memcpy(txf_address, address, sizeof(txf_address));
1732
1733 if (target == TGSI_TEXTURE_2D_MSAA) {
1734 txf_address[2] = bld_base->uint_bld.zero;
1735 }
1736 txf_address[3] = bld_base->uint_bld.zero;
1737
1738 /* Pad to a power-of-two size. */
1739 while (txf_count < util_next_power_of_two(txf_count))
1740 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1741
1742 /* Read FMASK using TXF. */
1743 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1744 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1745 txf_emit_data.inst = &inst;
1746 txf_emit_data.chan = 0;
1747 txf_emit_data.dst_type = LLVMVectorType(
1748 LLVMInt32TypeInContext(gallivm->context), 4);
1749 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1750 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1751 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1752 txf_emit_data.arg_count = 3;
1753
1754 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1755
1756 /* Initialize some constants. */
1757 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1758 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1759
1760 /* Apply the formula. */
1761 LLVMValueRef fmask =
1762 LLVMBuildExtractElement(gallivm->builder,
1763 txf_emit_data.output[0],
1764 uint_bld->zero, "");
1765
1766 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1767
1768 LLVMValueRef sample_index4 =
1769 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1770
1771 LLVMValueRef shifted_fmask =
1772 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1773
1774 LLVMValueRef final_sample =
1775 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1776
1777 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1778 * resource descriptor is 0 (invalid),
1779 */
1780 LLVMValueRef fmask_desc =
1781 LLVMBuildBitCast(gallivm->builder,
1782 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1783 LLVMVectorType(uint_bld->elem_type, 8), "");
1784
1785 LLVMValueRef fmask_word1 =
1786 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1787 uint_bld->one, "");
1788
1789 LLVMValueRef word1_is_nonzero =
1790 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1791 fmask_word1, uint_bld->zero, "");
1792
1793 /* Replace the MSAA sample index. */
1794 address[sample_chan] =
1795 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1796 final_sample, address[sample_chan], "");
1797 }
1798
1799 /* Resource */
1800 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1801
1802 if (opcode == TGSI_OPCODE_TXF) {
1803 /* add tex offsets */
1804 if (inst->Texture.NumOffsets) {
1805 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1806 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1807 const struct tgsi_texture_offset * off = inst->TexOffsets;
1808
1809 assert(inst->Texture.NumOffsets == 1);
1810
1811 switch (target) {
1812 case TGSI_TEXTURE_3D:
1813 address[2] = lp_build_add(uint_bld, address[2],
1814 bld->immediates[off->Index][off->SwizzleZ]);
1815 /* fall through */
1816 case TGSI_TEXTURE_2D:
1817 case TGSI_TEXTURE_SHADOW2D:
1818 case TGSI_TEXTURE_RECT:
1819 case TGSI_TEXTURE_SHADOWRECT:
1820 case TGSI_TEXTURE_2D_ARRAY:
1821 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1822 address[1] =
1823 lp_build_add(uint_bld, address[1],
1824 bld->immediates[off->Index][off->SwizzleY]);
1825 /* fall through */
1826 case TGSI_TEXTURE_1D:
1827 case TGSI_TEXTURE_SHADOW1D:
1828 case TGSI_TEXTURE_1D_ARRAY:
1829 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1830 address[0] =
1831 lp_build_add(uint_bld, address[0],
1832 bld->immediates[off->Index][off->SwizzleX]);
1833 break;
1834 /* texture offsets do not apply to other texture targets */
1835 }
1836 }
1837
1838 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1839 emit_data->arg_count = 3;
1840
1841 emit_data->dst_type = LLVMVectorType(
1842 LLVMInt32TypeInContext(gallivm->context),
1843 4);
1844 } else if (opcode == TGSI_OPCODE_TG4 ||
1845 opcode == TGSI_OPCODE_LODQ ||
1846 has_offset) {
1847 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1848 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1849 target == TGSI_TEXTURE_2D_ARRAY ||
1850 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1851 target == TGSI_TEXTURE_CUBE_ARRAY ||
1852 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1853 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1854 unsigned dmask = 0xf;
1855
1856 if (opcode == TGSI_OPCODE_TG4) {
1857 unsigned gather_comp = 0;
1858
1859 /* DMASK was repurposed for GATHER4. 4 components are always
1860 * returned and DMASK works like a swizzle - it selects
1861 * the component to fetch. The only valid DMASK values are
1862 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1863 * (red,red,red,red) etc.) The ISA document doesn't mention
1864 * this.
1865 */
1866
1867 /* Get the component index from src1.x for Gather4. */
1868 if (!tgsi_is_shadow_sampler(target)) {
1869 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1870 LLVMValueRef comp_imm;
1871 struct tgsi_src_register src1 = inst->Src[1].Register;
1872
1873 assert(src1.File == TGSI_FILE_IMMEDIATE);
1874
1875 comp_imm = imms[src1.Index][src1.SwizzleX];
1876 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1877 gather_comp = CLAMP(gather_comp, 0, 3);
1878 }
1879
1880 dmask = 1 << gather_comp;
1881 }
1882
1883 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1884 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1885 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1886 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1887 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1888 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1889 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1890 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1891 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1892
1893 emit_data->arg_count = 11;
1894
1895 emit_data->dst_type = LLVMVectorType(
1896 LLVMFloatTypeInContext(gallivm->context),
1897 4);
1898 } else {
1899 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1900 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1901 emit_data->arg_count = 4;
1902
1903 emit_data->dst_type = LLVMVectorType(
1904 LLVMFloatTypeInContext(gallivm->context),
1905 4);
1906 }
1907
1908 /* The fetch opcode has been converted to a 2D array fetch.
1909 * This simplifies the LLVM backend. */
1910 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1911 target = TGSI_TEXTURE_2D_ARRAY;
1912 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1913 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1914
1915 /* Pad to power of two vector */
1916 while (count < util_next_power_of_two(count))
1917 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1918
1919 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1920 }
1921
1922 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1923 struct lp_build_tgsi_context * bld_base,
1924 struct lp_build_emit_data * emit_data)
1925 {
1926 struct lp_build_context * base = &bld_base->base;
1927 unsigned opcode = emit_data->inst->Instruction.Opcode;
1928 unsigned target = emit_data->inst->Texture.Texture;
1929 char intr_name[127];
1930 bool has_offset = HAVE_LLVM >= 0x0305 ?
1931 emit_data->inst->Texture.NumOffsets > 0 : false;
1932
1933 if (target == TGSI_TEXTURE_BUFFER) {
1934 emit_data->output[emit_data->chan] = build_intrinsic(
1935 base->gallivm->builder,
1936 "llvm.SI.vs.load.input", emit_data->dst_type,
1937 emit_data->args, emit_data->arg_count,
1938 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1939 return;
1940 }
1941
1942 if (opcode == TGSI_OPCODE_TG4 ||
1943 opcode == TGSI_OPCODE_LODQ ||
1944 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1945 bool is_shadow = tgsi_is_shadow_sampler(target);
1946 const char *name = "llvm.SI.image.sample";
1947 const char *infix = "";
1948
1949 switch (opcode) {
1950 case TGSI_OPCODE_TEX:
1951 case TGSI_OPCODE_TEX2:
1952 case TGSI_OPCODE_TXP:
1953 break;
1954 case TGSI_OPCODE_TXB:
1955 case TGSI_OPCODE_TXB2:
1956 infix = ".b";
1957 break;
1958 case TGSI_OPCODE_TXL:
1959 case TGSI_OPCODE_TXL2:
1960 infix = ".l";
1961 break;
1962 case TGSI_OPCODE_TXD:
1963 infix = ".d";
1964 break;
1965 case TGSI_OPCODE_TG4:
1966 name = "llvm.SI.gather4";
1967 break;
1968 case TGSI_OPCODE_LODQ:
1969 name = "llvm.SI.getlod";
1970 is_shadow = false;
1971 has_offset = false;
1972 break;
1973 default:
1974 assert(0);
1975 return;
1976 }
1977
1978 /* Add the type and suffixes .c, .o if needed. */
1979 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1980 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1981 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1982
1983 emit_data->output[emit_data->chan] = build_intrinsic(
1984 base->gallivm->builder, intr_name, emit_data->dst_type,
1985 emit_data->args, emit_data->arg_count,
1986 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1987 } else {
1988 LLVMTypeRef i8, v16i8, v32i8;
1989 const char *name;
1990
1991 switch (opcode) {
1992 case TGSI_OPCODE_TEX:
1993 case TGSI_OPCODE_TEX2:
1994 case TGSI_OPCODE_TXP:
1995 name = "llvm.SI.sample";
1996 break;
1997 case TGSI_OPCODE_TXB:
1998 case TGSI_OPCODE_TXB2:
1999 name = "llvm.SI.sampleb";
2000 break;
2001 case TGSI_OPCODE_TXD:
2002 name = "llvm.SI.sampled";
2003 break;
2004 case TGSI_OPCODE_TXF:
2005 name = "llvm.SI.imageload";
2006 break;
2007 case TGSI_OPCODE_TXL:
2008 case TGSI_OPCODE_TXL2:
2009 name = "llvm.SI.samplel";
2010 break;
2011 default:
2012 assert(0);
2013 return;
2014 }
2015
2016 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2017 v16i8 = LLVMVectorType(i8, 16);
2018 v32i8 = LLVMVectorType(i8, 32);
2019
2020 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2021 emit_data->args[1], v32i8, "");
2022 if (opcode != TGSI_OPCODE_TXF) {
2023 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2024 emit_data->args[2], v16i8, "");
2025 }
2026
2027 sprintf(intr_name, "%s.v%ui32", name,
2028 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2029
2030 emit_data->output[emit_data->chan] = build_intrinsic(
2031 base->gallivm->builder, intr_name, emit_data->dst_type,
2032 emit_data->args, emit_data->arg_count,
2033 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2034 }
2035 }
2036
2037 static void txq_fetch_args(
2038 struct lp_build_tgsi_context * bld_base,
2039 struct lp_build_emit_data * emit_data)
2040 {
2041 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2042 const struct tgsi_full_instruction *inst = emit_data->inst;
2043 struct gallivm_state *gallivm = bld_base->base.gallivm;
2044 unsigned target = inst->Texture.Texture;
2045
2046 if (target == TGSI_TEXTURE_BUFFER) {
2047 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2048 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2049
2050 /* Read the size from the buffer descriptor directly. */
2051 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2052 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2053 size = LLVMBuildExtractElement(gallivm->builder, size,
2054 lp_build_const_int32(gallivm, 2), "");
2055 emit_data->args[0] = size;
2056 return;
2057 }
2058
2059 /* Mip level */
2060 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2061
2062 /* Resource */
2063 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2064
2065 /* Texture target */
2066 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2067 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2068 target = TGSI_TEXTURE_2D_ARRAY;
2069
2070 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2071 target);
2072
2073 emit_data->arg_count = 3;
2074
2075 emit_data->dst_type = LLVMVectorType(
2076 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2077 4);
2078 }
2079
2080 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2081 struct lp_build_tgsi_context * bld_base,
2082 struct lp_build_emit_data * emit_data)
2083 {
2084 unsigned target = emit_data->inst->Texture.Texture;
2085
2086 if (target == TGSI_TEXTURE_BUFFER) {
2087 /* Just return the buffer size. */
2088 emit_data->output[emit_data->chan] = emit_data->args[0];
2089 return;
2090 }
2091
2092 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2093
2094 /* Divide the number of layers by 6 to get the number of cubes. */
2095 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2096 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2097 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2098 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2099 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2100
2101 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2102 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2103 z = LLVMBuildSDiv(builder, z, six, "");
2104
2105 emit_data->output[emit_data->chan] =
2106 LLVMBuildInsertElement(builder, v4, z, two, "");
2107 }
2108 }
2109
2110 static void si_llvm_emit_ddxy(
2111 const struct lp_build_tgsi_action * action,
2112 struct lp_build_tgsi_context * bld_base,
2113 struct lp_build_emit_data * emit_data)
2114 {
2115 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2116 struct gallivm_state *gallivm = bld_base->base.gallivm;
2117 struct lp_build_context * base = &bld_base->base;
2118 const struct tgsi_full_instruction *inst = emit_data->inst;
2119 unsigned opcode = inst->Instruction.Opcode;
2120 LLVMValueRef indices[2];
2121 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2122 LLVMValueRef tl, trbl, result[4];
2123 LLVMTypeRef i32;
2124 unsigned swizzle[4];
2125 unsigned c;
2126
2127 i32 = LLVMInt32TypeInContext(gallivm->context);
2128
2129 indices[0] = bld_base->uint_bld.zero;
2130 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2131 NULL, 0, LLVMReadNoneAttribute);
2132 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2133 indices, 2, "");
2134
2135 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2136 lp_build_const_int32(gallivm, 0xfffffffc), "");
2137 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2138 indices, 2, "");
2139
2140 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2141 lp_build_const_int32(gallivm,
2142 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2143 "");
2144 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2145 indices, 2, "");
2146
2147 for (c = 0; c < 4; ++c) {
2148 unsigned i;
2149
2150 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2151 for (i = 0; i < c; ++i) {
2152 if (swizzle[i] == swizzle[c]) {
2153 result[c] = result[i];
2154 break;
2155 }
2156 }
2157 if (i != c)
2158 continue;
2159
2160 LLVMBuildStore(gallivm->builder,
2161 LLVMBuildBitCast(gallivm->builder,
2162 lp_build_emit_fetch(bld_base, inst, 0, c),
2163 i32, ""),
2164 store_ptr);
2165
2166 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2167 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2168
2169 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2170 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2171
2172 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2173 }
2174
2175 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2176 }
2177
2178 /* Emit one vertex from the geometry shader */
2179 static void si_llvm_emit_vertex(
2180 const struct lp_build_tgsi_action *action,
2181 struct lp_build_tgsi_context *bld_base,
2182 struct lp_build_emit_data *emit_data)
2183 {
2184 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2185 struct lp_build_context *uint = &bld_base->uint_bld;
2186 struct si_shader *shader = &si_shader_ctx->shader->shader;
2187 struct gallivm_state *gallivm = bld_base->base.gallivm;
2188 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2189 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2190 SI_PARAM_GS2VS_OFFSET);
2191 LLVMValueRef gs_next_vertex;
2192 LLVMValueRef can_emit, kill;
2193 LLVMValueRef t_list_ptr;
2194 LLVMValueRef t_list;
2195 LLVMValueRef args[2];
2196 unsigned chan;
2197 int i;
2198
2199 /* Load the GSVS ring resource descriptor */
2200 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2201 SI_PARAM_RW_BUFFERS);
2202 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2203 lp_build_const_int32(gallivm, SI_RING_GSVS));
2204
2205 if (shader->noutput == 0) {
2206 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
2207
2208 while (!tgsi_parse_end_of_tokens(parse)) {
2209 tgsi_parse_token(parse);
2210
2211 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
2212 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
2213
2214 if (d->Declaration.File == TGSI_FILE_OUTPUT)
2215 si_store_shader_io_attribs(shader, d);
2216 }
2217 }
2218 }
2219
2220 /* Write vertex attribute values to GSVS ring */
2221 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2222
2223 /* If this thread has already emitted the declared maximum number of
2224 * vertices, kill it: excessive vertex emissions are not supposed to
2225 * have any effect, and GS threads have no externally observable
2226 * effects other than emitting vertices.
2227 */
2228 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2229 lp_build_const_int32(gallivm,
2230 shader->gs_max_out_vertices), "");
2231 kill = lp_build_select(&bld_base->base, can_emit,
2232 lp_build_const_float(gallivm, 1.0f),
2233 lp_build_const_float(gallivm, -1.0f));
2234 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2235 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2236
2237 for (i = 0; i < shader->noutput; i++) {
2238 LLVMValueRef *out_ptr =
2239 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
2240
2241 for (chan = 0; chan < 4; chan++) {
2242 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2243 LLVMValueRef voffset =
2244 lp_build_const_int32(gallivm, (i * 4 + chan) *
2245 shader->gs_max_out_vertices);
2246
2247 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2248 voffset = lp_build_mul_imm(uint, voffset, 4);
2249
2250 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2251
2252 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2253 voffset, soffset, 0,
2254 V_008F0C_BUF_DATA_FORMAT_32,
2255 V_008F0C_BUF_NUM_FORMAT_UINT,
2256 1, 0, 1, 1, 0);
2257 }
2258 }
2259 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2260 lp_build_const_int32(gallivm, 1));
2261 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2262
2263 /* Signal vertex emission */
2264 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2265 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2266 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2267 LLVMVoidTypeInContext(gallivm->context), args, 2,
2268 LLVMNoUnwindAttribute);
2269 }
2270
2271 /* Cut one primitive from the geometry shader */
2272 static void si_llvm_emit_primitive(
2273 const struct lp_build_tgsi_action *action,
2274 struct lp_build_tgsi_context *bld_base,
2275 struct lp_build_emit_data *emit_data)
2276 {
2277 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2278 struct gallivm_state *gallivm = bld_base->base.gallivm;
2279 LLVMValueRef args[2];
2280
2281 /* Signal primitive cut */
2282 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2283 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2284 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2285 LLVMVoidTypeInContext(gallivm->context), args, 2,
2286 LLVMNoUnwindAttribute);
2287 }
2288
2289 static const struct lp_build_tgsi_action tex_action = {
2290 .fetch_args = tex_fetch_args,
2291 .emit = build_tex_intrinsic,
2292 };
2293
2294 static const struct lp_build_tgsi_action txq_action = {
2295 .fetch_args = txq_fetch_args,
2296 .emit = build_txq_intrinsic,
2297 .intr_name = "llvm.SI.resinfo"
2298 };
2299
2300 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2301 {
2302 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2303 LLVMValueRef args[3];
2304
2305 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2306 args[1] = 0;
2307 args[2] = lp_build_const_int32(gallivm, 1);
2308
2309 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2310 }
2311
2312 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2313 {
2314 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2315 CONST_ADDR_SPACE);
2316 }
2317
2318 static void create_function(struct si_shader_context *si_shader_ctx)
2319 {
2320 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2321 struct gallivm_state *gallivm = bld_base->base.gallivm;
2322 struct si_pipe_shader *shader = si_shader_ctx->shader;
2323 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2324 unsigned i, last_sgpr, num_params;
2325
2326 i8 = LLVMInt8TypeInContext(gallivm->context);
2327 i32 = LLVMInt32TypeInContext(gallivm->context);
2328 f32 = LLVMFloatTypeInContext(gallivm->context);
2329 v2i32 = LLVMVectorType(i32, 2);
2330 v3i32 = LLVMVectorType(i32, 3);
2331 v4i32 = LLVMVectorType(i32, 4);
2332 v8i32 = LLVMVectorType(i32, 8);
2333 v16i8 = LLVMVectorType(i8, 16);
2334
2335 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2336 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2337 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2338 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2339
2340 switch (si_shader_ctx->type) {
2341 case TGSI_PROCESSOR_VERTEX:
2342 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2343 params[SI_PARAM_BASE_VERTEX] = i32;
2344 params[SI_PARAM_START_INSTANCE] = i32;
2345 num_params = SI_PARAM_START_INSTANCE+1;
2346 if (shader->key.vs.as_es) {
2347 params[SI_PARAM_ES2GS_OFFSET] = i32;
2348 num_params++;
2349 } else {
2350 /* The locations of the other parameters are assigned dynamically. */
2351
2352 /* Streamout SGPRs. */
2353 if (shader->selector->so.num_outputs) {
2354 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2355 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2356 }
2357 /* A streamout buffer offset is loaded if the stride is non-zero. */
2358 for (i = 0; i < 4; i++) {
2359 if (!shader->selector->so.stride[i])
2360 continue;
2361
2362 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2363 }
2364 }
2365
2366 last_sgpr = num_params-1;
2367
2368 /* VGPRs */
2369 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2370 params[num_params++] = i32; /* unused*/
2371 params[num_params++] = i32; /* unused */
2372 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2373 break;
2374
2375 case TGSI_PROCESSOR_GEOMETRY:
2376 params[SI_PARAM_GS2VS_OFFSET] = i32;
2377 params[SI_PARAM_GS_WAVE_ID] = i32;
2378 last_sgpr = SI_PARAM_GS_WAVE_ID;
2379
2380 /* VGPRs */
2381 params[SI_PARAM_VTX0_OFFSET] = i32;
2382 params[SI_PARAM_VTX1_OFFSET] = i32;
2383 params[SI_PARAM_PRIMITIVE_ID] = i32;
2384 params[SI_PARAM_VTX2_OFFSET] = i32;
2385 params[SI_PARAM_VTX3_OFFSET] = i32;
2386 params[SI_PARAM_VTX4_OFFSET] = i32;
2387 params[SI_PARAM_VTX5_OFFSET] = i32;
2388 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2389 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2390 break;
2391
2392 case TGSI_PROCESSOR_FRAGMENT:
2393 params[SI_PARAM_ALPHA_REF] = f32;
2394 params[SI_PARAM_PRIM_MASK] = i32;
2395 last_sgpr = SI_PARAM_PRIM_MASK;
2396 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2397 params[SI_PARAM_PERSP_CENTER] = v2i32;
2398 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2399 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2400 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2401 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2402 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2403 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2404 params[SI_PARAM_POS_X_FLOAT] = f32;
2405 params[SI_PARAM_POS_Y_FLOAT] = f32;
2406 params[SI_PARAM_POS_Z_FLOAT] = f32;
2407 params[SI_PARAM_POS_W_FLOAT] = f32;
2408 params[SI_PARAM_FRONT_FACE] = f32;
2409 params[SI_PARAM_ANCILLARY] = i32;
2410 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2411 params[SI_PARAM_POS_FIXED_PT] = f32;
2412 num_params = SI_PARAM_POS_FIXED_PT+1;
2413 break;
2414
2415 default:
2416 assert(0 && "unimplemented shader");
2417 return;
2418 }
2419
2420 assert(num_params <= Elements(params));
2421 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2422 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2423
2424 for (i = 0; i <= last_sgpr; ++i) {
2425 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2426 switch (i) {
2427 default:
2428 LLVMAddAttribute(P, LLVMInRegAttribute);
2429 break;
2430 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2431 * to move load. Inputs are constant so this is fine. */
2432 case SI_PARAM_CONST:
2433 case SI_PARAM_SAMPLER:
2434 case SI_PARAM_RESOURCE:
2435 LLVMAddAttribute(P, LLVMByValAttribute);
2436 break;
2437 }
2438 }
2439
2440 if (bld_base->info &&
2441 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2442 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2443 si_shader_ctx->ddxy_lds =
2444 LLVMAddGlobalInAddressSpace(gallivm->module,
2445 LLVMArrayType(i32, 64),
2446 "ddxy_lds",
2447 LOCAL_ADDR_SPACE);
2448 }
2449
2450 static void preload_constants(struct si_shader_context *si_shader_ctx)
2451 {
2452 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2453 struct gallivm_state * gallivm = bld_base->base.gallivm;
2454 const struct tgsi_shader_info * info = bld_base->info;
2455 unsigned buf;
2456 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2457
2458 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2459 unsigned i, num_const = info->const_file_max[buf] + 1;
2460
2461 if (num_const == 0)
2462 continue;
2463
2464 /* Allocate space for the constant values */
2465 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2466
2467 /* Load the resource descriptor */
2468 si_shader_ctx->const_resource[buf] =
2469 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2470
2471 /* Load the constants, we rely on the code sinking to do the rest */
2472 for (i = 0; i < num_const * 4; ++i) {
2473 si_shader_ctx->constants[buf][i] =
2474 load_const(gallivm->builder,
2475 si_shader_ctx->const_resource[buf],
2476 lp_build_const_int32(gallivm, i * 4),
2477 bld_base->base.elem_type);
2478 }
2479 }
2480 }
2481
2482 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2483 {
2484 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2485 struct gallivm_state * gallivm = bld_base->base.gallivm;
2486 const struct tgsi_shader_info * info = bld_base->info;
2487
2488 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2489
2490 LLVMValueRef res_ptr, samp_ptr;
2491 LLVMValueRef offset;
2492
2493 if (num_samplers == 0)
2494 return;
2495
2496 /* Allocate space for the values */
2497 si_shader_ctx->resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2498 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2499
2500 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2501 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2502
2503 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2504 for (i = 0; i < num_samplers; ++i) {
2505 /* Resource */
2506 offset = lp_build_const_int32(gallivm, i);
2507 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2508
2509 /* Sampler */
2510 offset = lp_build_const_int32(gallivm, i);
2511 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2512
2513 /* FMASK resource */
2514 if (info->is_msaa_sampler[i]) {
2515 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2516 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2517 build_indexed_load(si_shader_ctx, res_ptr, offset);
2518 }
2519 }
2520 }
2521
2522 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2523 {
2524 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2525 struct gallivm_state * gallivm = bld_base->base.gallivm;
2526 unsigned i;
2527
2528 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2529 si_shader_ctx->shader->key.vs.as_es ||
2530 !si_shader_ctx->shader->selector->so.num_outputs)
2531 return;
2532
2533 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2534 SI_PARAM_RW_BUFFERS);
2535
2536 /* Load the resources, we rely on the code sinking to do the rest */
2537 for (i = 0; i < 4; ++i) {
2538 if (si_shader_ctx->shader->selector->so.stride[i]) {
2539 LLVMValueRef offset = lp_build_const_int32(gallivm,
2540 SI_SO_BUF_OFFSET + i);
2541
2542 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2543 }
2544 }
2545 }
2546
2547 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2548 LLVMModuleRef mod)
2549 {
2550 unsigned r; /* llvm_compile result */
2551 unsigned i;
2552 unsigned char *ptr;
2553 struct radeon_shader_binary binary;
2554 bool dump = r600_can_dump_shader(&sctx->screen->b,
2555 shader->selector ? shader->selector->tokens : NULL);
2556 const char * gpu_family = r600_get_llvm_processor_name(sctx->screen->b.family);
2557 unsigned code_size;
2558
2559 /* Use LLVM to compile shader */
2560 memset(&binary, 0, sizeof(binary));
2561 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2562
2563 /* Output binary dump if rscreen->debug_flags are set */
2564 if (dump && ! binary.disassembled) {
2565 fprintf(stderr, "SI CODE:\n");
2566 for (i = 0; i < binary.code_size; i+=4 ) {
2567 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2568 binary.code[i + 2], binary.code[i + 1],
2569 binary.code[i]);
2570 }
2571 }
2572
2573 /* XXX: We may be able to emit some of these values directly rather than
2574 * extracting fields to be emitted later.
2575 */
2576 /* Parse config data in compiled binary */
2577 for (i = 0; i < binary.config_size; i+= 8) {
2578 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2579 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2580 switch (reg) {
2581 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2582 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2583 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2584 case R_00B848_COMPUTE_PGM_RSRC1:
2585 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2586 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2587 break;
2588 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2589 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2590 break;
2591 case R_00B84C_COMPUTE_PGM_RSRC2:
2592 shader->lds_size = G_00B84C_LDS_SIZE(value);
2593 break;
2594 case R_0286CC_SPI_PS_INPUT_ENA:
2595 shader->spi_ps_input_ena = value;
2596 break;
2597 case R_00B860_COMPUTE_TMPRING_SIZE:
2598 /* WAVESIZE is in units of 256 dwords. */
2599 shader->scratch_bytes_per_wave =
2600 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2601 break;
2602 default:
2603 fprintf(stderr, "Warning: Compiler emitted unknown "
2604 "config register: 0x%x\n", reg);
2605 break;
2606 }
2607 }
2608
2609 /* copy new shader */
2610 code_size = binary.code_size + binary.rodata_size;
2611 r600_resource_reference(&shader->bo, NULL);
2612 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2613 code_size);
2614 if (shader->bo == NULL) {
2615 return -ENOMEM;
2616 }
2617
2618 ptr = sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2619 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2620 if (binary.rodata_size > 0) {
2621 ptr += binary.code_size;
2622 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2623 }
2624
2625 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2626
2627 free(binary.code);
2628 free(binary.config);
2629 free(binary.rodata);
2630
2631 return r;
2632 }
2633
2634 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2635 static int si_generate_gs_copy_shader(struct si_context *sctx,
2636 struct si_shader_context *si_shader_ctx,
2637 bool dump)
2638 {
2639 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2640 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2641 struct lp_build_context *base = &bld_base->base;
2642 struct lp_build_context *uint = &bld_base->uint_bld;
2643 struct si_shader *shader = &si_shader_ctx->shader->shader;
2644 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2645 struct si_shader_output_values *outputs;
2646 LLVMValueRef t_list_ptr, t_list;
2647 LLVMValueRef args[9];
2648 int i, r;
2649
2650 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2651
2652 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2653 si_shader_ctx->gs_for_vs = gs;
2654
2655 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2656
2657 create_meta_data(si_shader_ctx);
2658 create_function(si_shader_ctx);
2659 preload_streamout_buffers(si_shader_ctx);
2660
2661 /* Load the GSVS ring resource descriptor */
2662 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2663 SI_PARAM_RW_BUFFERS);
2664 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2665 lp_build_const_int32(gallivm, SI_RING_GSVS));
2666
2667 args[0] = t_list;
2668 args[1] = lp_build_mul_imm(uint,
2669 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2670 si_shader_ctx->param_vertex_id),
2671 4);
2672 args[3] = uint->zero;
2673 args[4] = uint->one; /* OFFEN */
2674 args[5] = uint->zero; /* IDXEN */
2675 args[6] = uint->one; /* GLC */
2676 args[7] = uint->one; /* SLC */
2677 args[8] = uint->zero; /* TFE */
2678
2679 /* Fetch vertex data from GSVS ring */
2680 for (i = 0; i < gs->noutput; ++i) {
2681 struct si_shader_output *out = gs->output + i;
2682 unsigned chan;
2683
2684 shader->output[i] = *out;
2685
2686 outputs[i].name = out->name;
2687 outputs[i].index = out->index;
2688 outputs[i].sid = out->sid;
2689 outputs[i].usage = out->usage;
2690
2691 for (chan = 0; chan < 4; chan++) {
2692 args[2] = lp_build_const_int32(gallivm,
2693 (i * 4 + chan) *
2694 gs->gs_max_out_vertices * 16 * 4);
2695
2696 outputs[i].values[chan] =
2697 LLVMBuildBitCast(gallivm->builder,
2698 build_intrinsic(gallivm->builder,
2699 "llvm.SI.buffer.load.dword.i32.i32",
2700 LLVMInt32TypeInContext(gallivm->context),
2701 args, 9,
2702 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2703 base->elem_type, "");
2704 }
2705 }
2706 shader->noutput = gs->noutput;
2707
2708 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2709
2710 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2711
2712 if (dump)
2713 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2714
2715 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2716 bld_base->base.gallivm->module);
2717
2718 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2719
2720 FREE(outputs);
2721 return r;
2722 }
2723
2724 int si_pipe_shader_create(
2725 struct pipe_context *ctx,
2726 struct si_pipe_shader *shader)
2727 {
2728 struct si_context *sctx = (struct si_context*)ctx;
2729 struct si_pipe_shader_selector *sel = shader->selector;
2730 struct si_shader_context si_shader_ctx;
2731 struct tgsi_shader_info shader_info;
2732 struct lp_build_tgsi_context * bld_base;
2733 LLVMModuleRef mod;
2734 int r = 0;
2735 bool dump = r600_can_dump_shader(&sctx->screen->b, sel->tokens);
2736
2737 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2738 * conversion fails. */
2739 if (dump) {
2740 tgsi_dump(sel->tokens, 0);
2741 si_dump_streamout(&sel->so);
2742 }
2743
2744 assert(shader->shader.noutput == 0);
2745 assert(shader->shader.nparam == 0);
2746 assert(shader->shader.ninput == 0);
2747
2748 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2749 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2750 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2751
2752 tgsi_scan_shader(sel->tokens, &shader_info);
2753
2754 shader->shader.uses_kill = shader_info.uses_kill;
2755 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2756 bld_base->info = &shader_info;
2757 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2758
2759 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2760 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2761 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2762 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2763 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2764 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2765 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2766 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2767 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2768 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2769 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2770 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2771
2772 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2773 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2774
2775 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2776 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2777
2778 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2779 si_shader_ctx.tokens = sel->tokens;
2780 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2781 si_shader_ctx.shader = shader;
2782 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2783
2784 switch (si_shader_ctx.type) {
2785 case TGSI_PROCESSOR_VERTEX:
2786 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2787 if (shader->key.vs.as_es) {
2788 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2789 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2790 } else {
2791 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2792 }
2793 break;
2794 case TGSI_PROCESSOR_GEOMETRY: {
2795 int i;
2796
2797 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2798 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2799 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2800
2801 for (i = 0; i < shader_info.num_properties; i++) {
2802 switch (shader_info.properties[i].name) {
2803 case TGSI_PROPERTY_GS_INPUT_PRIM:
2804 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2805 break;
2806 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2807 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2808 break;
2809 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2810 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2811 break;
2812 }
2813 }
2814 break;
2815 }
2816 case TGSI_PROCESSOR_FRAGMENT: {
2817 int i;
2818
2819 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2820 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2821
2822 for (i = 0; i < shader_info.num_properties; i++) {
2823 switch (shader_info.properties[i].name) {
2824 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2825 switch (shader_info.properties[i].data[0]) {
2826 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2827 shader->db_shader_control |=
2828 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2829 break;
2830 case TGSI_FS_DEPTH_LAYOUT_LESS:
2831 shader->db_shader_control |=
2832 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2833 break;
2834 }
2835 break;
2836 }
2837 }
2838 break;
2839 }
2840 default:
2841 assert(!"Unsupported shader type");
2842 return -1;
2843 }
2844
2845 create_meta_data(&si_shader_ctx);
2846 create_function(&si_shader_ctx);
2847 preload_constants(&si_shader_ctx);
2848 preload_samplers(&si_shader_ctx);
2849 preload_streamout_buffers(&si_shader_ctx);
2850
2851 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2852 si_shader_ctx.gs_next_vertex =
2853 lp_build_alloca(bld_base->base.gallivm,
2854 bld_base->uint_bld.elem_type, "");
2855 }
2856
2857 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2858 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2859 goto out;
2860 }
2861
2862 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2863
2864 mod = bld_base->base.gallivm->module;
2865 r = si_compile_llvm(sctx, shader, mod);
2866 if (r) {
2867 fprintf(stderr, "LLVM failed to compile shader\n");
2868 goto out;
2869 }
2870
2871 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2872
2873 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2874 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2875 shader->gs_copy_shader->selector = shader->selector;
2876 shader->gs_copy_shader->key = shader->key;
2877 si_shader_ctx.shader = shader->gs_copy_shader;
2878 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2879 free(shader->gs_copy_shader);
2880 shader->gs_copy_shader = NULL;
2881 goto out;
2882 }
2883 }
2884
2885 tgsi_parse_free(&si_shader_ctx.parse);
2886
2887 out:
2888 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2889 FREE(si_shader_ctx.constants[i]);
2890 FREE(si_shader_ctx.resources);
2891 FREE(si_shader_ctx.samplers);
2892
2893 return r;
2894 }
2895
2896 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2897 {
2898 r600_resource_reference(&shader->bo, NULL);
2899 }