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ac: import linear/perspective PS input parameters from radv/radeonsi
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_strings.h"
29 #include "tgsi/tgsi_util.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_from_mesa.h"
32
33 #include "ac_binary.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
36 #include "ac_rtld.h"
37 #include "ac_llvm_util.h"
38 #include "si_shader_internal.h"
39 #include "si_pipe.h"
40 #include "sid.h"
41
42 #include "compiler/nir/nir.h"
43
44 static const char scratch_rsrc_dword0_symbol[] =
45 "SCRATCH_RSRC_DWORD0";
46
47 static const char scratch_rsrc_dword1_symbol[] =
48 "SCRATCH_RSRC_DWORD1";
49
50 static void si_init_shader_ctx(struct si_shader_context *ctx,
51 struct si_screen *sscreen,
52 struct ac_llvm_compiler *compiler,
53 unsigned wave_size,
54 bool nir);
55
56 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
57 struct lp_build_tgsi_context *bld_base,
58 struct lp_build_emit_data *emit_data);
59
60 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
61
62 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
63 union si_shader_part_key *key);
64 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
65 union si_shader_part_key *key);
66 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
67 union si_shader_part_key *key);
68 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
69 union si_shader_part_key *key);
70 static void si_fix_resource_usage(struct si_screen *sscreen,
71 struct si_shader *shader);
72
73 /* Ideally pass the sample mask input to the PS epilog as v14, which
74 * is its usual location, so that the shader doesn't have to add v_mov.
75 */
76 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
77
78 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
79 LLVMTypeRef type)
80 {
81 if (type == ctx->ac.i64 || type == ctx->ac.f64)
82 return true;
83
84 return false;
85 }
86
87 /** Whether the shader runs as a combination of multiple API shaders */
88 static bool is_multi_part_shader(struct si_shader_context *ctx)
89 {
90 if (ctx->screen->info.chip_class <= GFX8)
91 return false;
92
93 return ctx->shader->key.as_ls ||
94 ctx->shader->key.as_es ||
95 ctx->type == PIPE_SHADER_TESS_CTRL ||
96 ctx->type == PIPE_SHADER_GEOMETRY;
97 }
98
99 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
100 static bool is_merged_shader(struct si_shader_context *ctx)
101 {
102 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
103 }
104
105 void si_init_function_info(struct si_function_info *fninfo)
106 {
107 fninfo->num_params = 0;
108 fninfo->num_sgpr_params = 0;
109 }
110
111 unsigned add_arg_assign(struct si_function_info *fninfo,
112 enum si_arg_regfile regfile, LLVMTypeRef type,
113 LLVMValueRef *assign)
114 {
115 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
116
117 unsigned idx = fninfo->num_params++;
118 assert(idx < ARRAY_SIZE(fninfo->types));
119
120 if (regfile == ARG_SGPR)
121 fninfo->num_sgpr_params = fninfo->num_params;
122
123 fninfo->types[idx] = type;
124 fninfo->assign[idx] = assign;
125 return idx;
126 }
127
128 static unsigned add_arg(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type)
130 {
131 return add_arg_assign(fninfo, regfile, type, NULL);
132 }
133
134 static void add_arg_assign_checked(struct si_function_info *fninfo,
135 enum si_arg_regfile regfile, LLVMTypeRef type,
136 LLVMValueRef *assign, unsigned idx)
137 {
138 ASSERTED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
139 assert(actual == idx);
140 }
141
142 static void add_arg_checked(struct si_function_info *fninfo,
143 enum si_arg_regfile regfile, LLVMTypeRef type,
144 unsigned idx)
145 {
146 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
147 }
148
149 /**
150 * Returns a unique index for a per-patch semantic name and index. The index
151 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
152 * can be calculated.
153 */
154 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
155 {
156 switch (semantic_name) {
157 case TGSI_SEMANTIC_TESSOUTER:
158 return 0;
159 case TGSI_SEMANTIC_TESSINNER:
160 return 1;
161 case TGSI_SEMANTIC_PATCH:
162 assert(index < 30);
163 return 2 + index;
164
165 default:
166 assert(!"invalid semantic name");
167 return 0;
168 }
169 }
170
171 /**
172 * Returns a unique index for a semantic name and index. The index must be
173 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
174 * calculated.
175 */
176 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
177 unsigned is_varying)
178 {
179 switch (semantic_name) {
180 case TGSI_SEMANTIC_POSITION:
181 return 0;
182 case TGSI_SEMANTIC_GENERIC:
183 /* Since some shader stages use the the highest used IO index
184 * to determine the size to allocate for inputs/outputs
185 * (in LDS, tess and GS rings). GENERIC should be placed right
186 * after POSITION to make that size as small as possible.
187 */
188 if (index < SI_MAX_IO_GENERIC)
189 return 1 + index;
190
191 assert(!"invalid generic index");
192 return 0;
193 case TGSI_SEMANTIC_FOG:
194 return SI_MAX_IO_GENERIC + 1;
195 case TGSI_SEMANTIC_COLOR:
196 assert(index < 2);
197 return SI_MAX_IO_GENERIC + 2 + index;
198 case TGSI_SEMANTIC_BCOLOR:
199 assert(index < 2);
200 /* If it's a varying, COLOR and BCOLOR alias. */
201 if (is_varying)
202 return SI_MAX_IO_GENERIC + 2 + index;
203 else
204 return SI_MAX_IO_GENERIC + 4 + index;
205 case TGSI_SEMANTIC_TEXCOORD:
206 assert(index < 8);
207 return SI_MAX_IO_GENERIC + 6 + index;
208
209 /* These are rarely used between LS and HS or ES and GS. */
210 case TGSI_SEMANTIC_CLIPDIST:
211 assert(index < 2);
212 return SI_MAX_IO_GENERIC + 6 + 8 + index;
213 case TGSI_SEMANTIC_CLIPVERTEX:
214 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
215 case TGSI_SEMANTIC_PSIZE:
216 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
217
218 /* These can't be written by LS, HS, and ES. */
219 case TGSI_SEMANTIC_LAYER:
220 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
221 case TGSI_SEMANTIC_VIEWPORT_INDEX:
222 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
223 case TGSI_SEMANTIC_PRIMID:
224 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
225 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
226 default:
227 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
228 assert(!"invalid semantic name");
229 return 0;
230 }
231 }
232
233 /**
234 * Get the value of a shader input parameter and extract a bitfield.
235 */
236 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
237 LLVMValueRef value, unsigned rshift,
238 unsigned bitwidth)
239 {
240 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
241 value = ac_to_integer(&ctx->ac, value);
242
243 if (rshift)
244 value = LLVMBuildLShr(ctx->ac.builder, value,
245 LLVMConstInt(ctx->i32, rshift, 0), "");
246
247 if (rshift + bitwidth < 32) {
248 unsigned mask = (1 << bitwidth) - 1;
249 value = LLVMBuildAnd(ctx->ac.builder, value,
250 LLVMConstInt(ctx->i32, mask, 0), "");
251 }
252
253 return value;
254 }
255
256 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
257 unsigned param, unsigned rshift,
258 unsigned bitwidth)
259 {
260 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
261
262 return unpack_llvm_param(ctx, value, rshift, bitwidth);
263 }
264
265 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
266 {
267 switch (ctx->type) {
268 case PIPE_SHADER_TESS_CTRL:
269 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
270
271 case PIPE_SHADER_TESS_EVAL:
272 return LLVMGetParam(ctx->main_fn,
273 ctx->param_tes_rel_patch_id);
274
275 default:
276 assert(0);
277 return NULL;
278 }
279 }
280
281 /* Tessellation shaders pass outputs to the next shader using LDS.
282 *
283 * LS outputs = TCS inputs
284 * TCS outputs = TES inputs
285 *
286 * The LDS layout is:
287 * - TCS inputs for patch 0
288 * - TCS inputs for patch 1
289 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
290 * - ...
291 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
292 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
293 * - TCS outputs for patch 1
294 * - Per-patch TCS outputs for patch 1
295 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
296 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
297 * - ...
298 *
299 * All three shaders VS(LS), TCS, TES share the same LDS space.
300 */
301
302 static LLVMValueRef
303 get_tcs_in_patch_stride(struct si_shader_context *ctx)
304 {
305 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
306 }
307
308 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
309 {
310 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
311
312 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
313 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
314
315 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
316 }
317
318 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
319 {
320 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
321
322 return LLVMConstInt(ctx->i32, stride, 0);
323 }
324
325 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
326 {
327 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
328 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
329
330 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
331 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
332 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
333 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
334 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
335 num_patch_outputs * 4;
336 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
337 }
338
339 static LLVMValueRef
340 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
341 {
342 return LLVMBuildMul(ctx->ac.builder,
343 si_unpack_param(ctx,
344 ctx->param_tcs_out_lds_offsets,
345 0, 16),
346 LLVMConstInt(ctx->i32, 4, 0), "");
347 }
348
349 static LLVMValueRef
350 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
351 {
352 return LLVMBuildMul(ctx->ac.builder,
353 si_unpack_param(ctx,
354 ctx->param_tcs_out_lds_offsets,
355 16, 16),
356 LLVMConstInt(ctx->i32, 4, 0), "");
357 }
358
359 static LLVMValueRef
360 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
361 {
362 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
363 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
364
365 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
366 }
367
368 static LLVMValueRef
369 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
370 {
371 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
376 }
377
378 static LLVMValueRef
379 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
380 {
381 LLVMValueRef patch0_patch_data_offset =
382 get_tcs_out_patch0_patch_data_offset(ctx);
383 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
384 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
385
386 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
387 }
388
389 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
390 {
391 unsigned tcs_out_vertices =
392 ctx->shader->selector ?
393 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
394
395 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
396 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
397 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
398
399 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
400 }
401
402 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
403 {
404 unsigned stride;
405
406 switch (ctx->type) {
407 case PIPE_SHADER_VERTEX:
408 stride = ctx->shader->selector->lshs_vertex_stride / 4;
409 return LLVMConstInt(ctx->i32, stride, 0);
410
411 case PIPE_SHADER_TESS_CTRL:
412 if (ctx->screen->info.chip_class >= GFX9 &&
413 ctx->shader->is_monolithic) {
414 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416 }
417 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
418
419 default:
420 assert(0);
421 return NULL;
422 }
423 }
424
425 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
426 LLVMValueRef i32, unsigned index)
427 {
428 assert(index <= 1);
429
430 if (index == 1)
431 return LLVMBuildAShr(ctx->ac.builder, i32,
432 LLVMConstInt(ctx->i32, 16, 0), "");
433
434 return LLVMBuildSExt(ctx->ac.builder,
435 LLVMBuildTrunc(ctx->ac.builder, i32,
436 ctx->ac.i16, ""),
437 ctx->i32, "");
438 }
439
440 void si_llvm_load_input_vs(
441 struct si_shader_context *ctx,
442 unsigned input_index,
443 LLVMValueRef out[4])
444 {
445 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
446 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
447
448 if (vs_blit_property) {
449 LLVMValueRef vertex_id = ctx->abi.vertex_id;
450 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
451 LLVMIntULE, vertex_id,
452 ctx->i32_1, "");
453 /* Use LLVMIntNE, because we have 3 vertices and only
454 * the middle one should use y2.
455 */
456 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
457 LLVMIntNE, vertex_id,
458 ctx->i32_1, "");
459
460 if (input_index == 0) {
461 /* Position: */
462 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
463 ctx->param_vs_blit_inputs);
464 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
465 ctx->param_vs_blit_inputs + 1);
466
467 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
468 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
469 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
470 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
471
472 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
473 x1, x2, "");
474 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
475 y1, y2, "");
476
477 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
478 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
479 out[2] = LLVMGetParam(ctx->main_fn,
480 ctx->param_vs_blit_inputs + 2);
481 out[3] = ctx->ac.f32_1;
482 return;
483 }
484
485 /* Color or texture coordinates: */
486 assert(input_index == 1);
487
488 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
489 for (int i = 0; i < 4; i++) {
490 out[i] = LLVMGetParam(ctx->main_fn,
491 ctx->param_vs_blit_inputs + 3 + i);
492 }
493 } else {
494 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
495 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
496 ctx->param_vs_blit_inputs + 3);
497 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
498 ctx->param_vs_blit_inputs + 4);
499 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs + 5);
501 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
502 ctx->param_vs_blit_inputs + 6);
503
504 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
505 x1, x2, "");
506 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
507 y1, y2, "");
508 out[2] = LLVMGetParam(ctx->main_fn,
509 ctx->param_vs_blit_inputs + 7);
510 out[3] = LLVMGetParam(ctx->main_fn,
511 ctx->param_vs_blit_inputs + 8);
512 }
513 return;
514 }
515
516 union si_vs_fix_fetch fix_fetch;
517 LLVMValueRef t_list_ptr;
518 LLVMValueRef t_offset;
519 LLVMValueRef t_list;
520 LLVMValueRef vertex_index;
521 LLVMValueRef tmp;
522
523 /* Load the T list */
524 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
525
526 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
527
528 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
529
530 vertex_index = LLVMGetParam(ctx->main_fn,
531 ctx->param_vertex_index0 +
532 input_index);
533
534 /* Use the open-coded implementation for all loads of doubles and
535 * of dword-sized data that needs fixups. We need to insert conversion
536 * code anyway, and the amd/common code does it for us.
537 *
538 * Note: On LLVM <= 8, we can only open-code formats with
539 * channel size >= 4 bytes.
540 */
541 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
542 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
543 if (opencode ||
544 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
545 (fix_fetch.u.log_size == 2)) {
546 tmp = ac_build_opencoded_load_format(
547 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
548 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
549 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
550 for (unsigned i = 0; i < 4; ++i)
551 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
552 return;
553 }
554
555 /* Do multiple loads for special formats. */
556 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
557 LLVMValueRef fetches[4];
558 unsigned num_fetches;
559 unsigned fetch_stride;
560 unsigned channels_per_fetch;
561
562 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
563 num_fetches = MIN2(required_channels, 3);
564 fetch_stride = 1 << fix_fetch.u.log_size;
565 channels_per_fetch = 1;
566 } else {
567 num_fetches = 1;
568 fetch_stride = 0;
569 channels_per_fetch = required_channels;
570 }
571
572 for (unsigned i = 0; i < num_fetches; ++i) {
573 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
574 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
575 channels_per_fetch, 0, true);
576 }
577
578 if (num_fetches == 1 && channels_per_fetch > 1) {
579 LLVMValueRef fetch = fetches[0];
580 for (unsigned i = 0; i < channels_per_fetch; ++i) {
581 tmp = LLVMConstInt(ctx->i32, i, false);
582 fetches[i] = LLVMBuildExtractElement(
583 ctx->ac.builder, fetch, tmp, "");
584 }
585 num_fetches = channels_per_fetch;
586 channels_per_fetch = 1;
587 }
588
589 for (unsigned i = num_fetches; i < 4; ++i)
590 fetches[i] = LLVMGetUndef(ctx->f32);
591
592 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
593 required_channels == 4) {
594 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
595 fetches[3] = ctx->ac.i32_1;
596 else
597 fetches[3] = ctx->ac.f32_1;
598 } else if (fix_fetch.u.log_size == 3 &&
599 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
600 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
601 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
602 required_channels == 4) {
603 /* For 2_10_10_10, the hardware returns an unsigned value;
604 * convert it to a signed one.
605 */
606 LLVMValueRef tmp = fetches[3];
607 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
608
609 /* First, recover the sign-extended signed integer value. */
610 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
611 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
612 else
613 tmp = ac_to_integer(&ctx->ac, tmp);
614
615 /* For the integer-like cases, do a natural sign extension.
616 *
617 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
618 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
619 * exponent.
620 */
621 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
622 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
623 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
624 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
625
626 /* Convert back to the right type. */
627 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
628 LLVMValueRef clamp;
629 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
630 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
631 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
632 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
633 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
634 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
635 }
636
637 fetches[3] = tmp;
638 }
639
640 for (unsigned i = 0; i < 4; ++i)
641 out[i] = ac_to_float(&ctx->ac, fetches[i]);
642 }
643
644 static void declare_input_vs(
645 struct si_shader_context *ctx,
646 unsigned input_index,
647 const struct tgsi_full_declaration *decl,
648 LLVMValueRef out[4])
649 {
650 si_llvm_load_input_vs(ctx, input_index, out);
651 }
652
653 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
654 unsigned swizzle)
655 {
656 if (swizzle > 0)
657 return ctx->i32_0;
658
659 switch (ctx->type) {
660 case PIPE_SHADER_VERTEX:
661 return LLVMGetParam(ctx->main_fn,
662 ctx->param_vs_prim_id);
663 case PIPE_SHADER_TESS_CTRL:
664 return ctx->abi.tcs_patch_id;
665 case PIPE_SHADER_TESS_EVAL:
666 return ctx->abi.tes_patch_id;
667 case PIPE_SHADER_GEOMETRY:
668 return ctx->abi.gs_prim_id;
669 default:
670 assert(0);
671 return ctx->i32_0;
672 }
673 }
674
675 /**
676 * Return the value of tgsi_ind_register for indexing.
677 * This is the indirect index with the constant offset added to it.
678 */
679 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
680 const struct tgsi_ind_register *ind,
681 unsigned addr_mul,
682 int rel_index)
683 {
684 LLVMValueRef result;
685
686 if (ind->File == TGSI_FILE_ADDRESS) {
687 result = ctx->addrs[ind->Index][ind->Swizzle];
688 result = LLVMBuildLoad(ctx->ac.builder, result, "");
689 } else {
690 struct tgsi_full_src_register src = {};
691
692 src.Register.File = ind->File;
693 src.Register.Index = ind->Index;
694
695 /* Set the second index to 0 for constants. */
696 if (ind->File == TGSI_FILE_CONSTANT)
697 src.Register.Dimension = 1;
698
699 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
700 TGSI_TYPE_SIGNED,
701 ind->Swizzle);
702 result = ac_to_integer(&ctx->ac, result);
703 }
704
705 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
706 LLVMConstInt(ctx->i32, rel_index, 0));
707 }
708
709 /**
710 * Like si_get_indirect_index, but restricts the return value to a (possibly
711 * undefined) value inside [0..num).
712 */
713 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
714 const struct tgsi_ind_register *ind,
715 int rel_index, unsigned num)
716 {
717 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
718
719 return si_llvm_bound_index(ctx, result, num);
720 }
721
722 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
723 LLVMValueRef vertex_dw_stride,
724 LLVMValueRef base_addr,
725 LLVMValueRef vertex_index,
726 LLVMValueRef param_index,
727 unsigned input_index,
728 ubyte *name,
729 ubyte *index,
730 bool is_patch)
731 {
732 if (vertex_dw_stride) {
733 base_addr = ac_build_imad(&ctx->ac, vertex_index,
734 vertex_dw_stride, base_addr);
735 }
736
737 if (param_index) {
738 base_addr = ac_build_imad(&ctx->ac, param_index,
739 LLVMConstInt(ctx->i32, 4, 0), base_addr);
740 }
741
742 int param = is_patch ?
743 si_shader_io_get_unique_index_patch(name[input_index],
744 index[input_index]) :
745 si_shader_io_get_unique_index(name[input_index],
746 index[input_index], false);
747
748 /* Add the base address of the element. */
749 return LLVMBuildAdd(ctx->ac.builder, base_addr,
750 LLVMConstInt(ctx->i32, param * 4, 0), "");
751 }
752
753 /**
754 * Calculate a dword address given an input or output register and a stride.
755 */
756 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
757 const struct tgsi_full_dst_register *dst,
758 const struct tgsi_full_src_register *src,
759 LLVMValueRef vertex_dw_stride,
760 LLVMValueRef base_addr)
761 {
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 int input_index;
765 struct tgsi_full_dst_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef ind_index = NULL;
768
769 /* Set the register description. The address computation is the same
770 * for sources and destinations. */
771 if (src) {
772 reg.Register.File = src->Register.File;
773 reg.Register.Index = src->Register.Index;
774 reg.Register.Indirect = src->Register.Indirect;
775 reg.Register.Dimension = src->Register.Dimension;
776 reg.Indirect = src->Indirect;
777 reg.Dimension = src->Dimension;
778 reg.DimIndirect = src->DimIndirect;
779 } else
780 reg = *dst;
781
782 /* If the register is 2-dimensional (e.g. an array of vertices
783 * in a primitive), calculate the base address of the vertex. */
784 if (reg.Register.Dimension) {
785 if (reg.Dimension.Indirect)
786 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
787 1, reg.Dimension.Index);
788 else
789 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
790 }
791
792 /* Get information about the register. */
793 if (reg.Register.File == TGSI_FILE_INPUT) {
794 name = info->input_semantic_name;
795 index = info->input_semantic_index;
796 array_first = info->input_array_first;
797 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
798 name = info->output_semantic_name;
799 index = info->output_semantic_index;
800 array_first = info->output_array_first;
801 } else {
802 assert(0);
803 return NULL;
804 }
805
806 if (reg.Register.Indirect) {
807 /* Add the relative address of the element. */
808 if (reg.Indirect.ArrayID)
809 input_index = array_first[reg.Indirect.ArrayID];
810 else
811 input_index = reg.Register.Index;
812
813 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
814 1, reg.Register.Index - input_index);
815 } else {
816 input_index = reg.Register.Index;
817 }
818
819 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
820 base_addr, vertex_index,
821 ind_index, input_index,
822 name, index,
823 !reg.Register.Dimension);
824 }
825
826 /* The offchip buffer layout for TCS->TES is
827 *
828 * - attribute 0 of patch 0 vertex 0
829 * - attribute 0 of patch 0 vertex 1
830 * - attribute 0 of patch 0 vertex 2
831 * ...
832 * - attribute 0 of patch 1 vertex 0
833 * - attribute 0 of patch 1 vertex 1
834 * ...
835 * - attribute 1 of patch 0 vertex 0
836 * - attribute 1 of patch 0 vertex 1
837 * ...
838 * - per patch attribute 0 of patch 0
839 * - per patch attribute 0 of patch 1
840 * ...
841 *
842 * Note that every attribute has 4 components.
843 */
844 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
845 LLVMValueRef rel_patch_id,
846 LLVMValueRef vertex_index,
847 LLVMValueRef param_index)
848 {
849 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
850 LLVMValueRef param_stride, constant16;
851
852 vertices_per_patch = get_num_tcs_out_vertices(ctx);
853 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
854 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
855 num_patches, "");
856
857 constant16 = LLVMConstInt(ctx->i32, 16, 0);
858 if (vertex_index) {
859 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
860 vertices_per_patch, vertex_index);
861 param_stride = total_vertices;
862 } else {
863 base_addr = rel_patch_id;
864 param_stride = num_patches;
865 }
866
867 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
868 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
869
870 if (!vertex_index) {
871 LLVMValueRef patch_data_offset =
872 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
873
874 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
875 patch_data_offset, "");
876 }
877 return base_addr;
878 }
879
880 /* This is a generic helper that can be shared by the NIR and TGSI backends */
881 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
882 struct si_shader_context *ctx,
883 LLVMValueRef vertex_index,
884 LLVMValueRef param_index,
885 unsigned param_base,
886 ubyte *name,
887 ubyte *index,
888 bool is_patch)
889 {
890 unsigned param_index_base;
891
892 param_index_base = is_patch ?
893 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
894 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
895
896 if (param_index) {
897 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
898 LLVMConstInt(ctx->i32, param_index_base, 0),
899 "");
900 } else {
901 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
902 }
903
904 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
905 vertex_index, param_index);
906 }
907
908 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
909 struct si_shader_context *ctx,
910 const struct tgsi_full_dst_register *dst,
911 const struct tgsi_full_src_register *src)
912 {
913 struct tgsi_shader_info *info = &ctx->shader->selector->info;
914 ubyte *name, *index, *array_first;
915 struct tgsi_full_src_register reg;
916 LLVMValueRef vertex_index = NULL;
917 LLVMValueRef param_index = NULL;
918 unsigned param_base;
919
920 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
921
922 if (reg.Register.Dimension) {
923
924 if (reg.Dimension.Indirect)
925 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
926 1, reg.Dimension.Index);
927 else
928 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
929 }
930
931 /* Get information about the register. */
932 if (reg.Register.File == TGSI_FILE_INPUT) {
933 name = info->input_semantic_name;
934 index = info->input_semantic_index;
935 array_first = info->input_array_first;
936 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
937 name = info->output_semantic_name;
938 index = info->output_semantic_index;
939 array_first = info->output_array_first;
940 } else {
941 assert(0);
942 return NULL;
943 }
944
945 if (reg.Register.Indirect) {
946 if (reg.Indirect.ArrayID)
947 param_base = array_first[reg.Indirect.ArrayID];
948 else
949 param_base = reg.Register.Index;
950
951 param_index = si_get_indirect_index(ctx, &reg.Indirect,
952 1, reg.Register.Index - param_base);
953
954 } else {
955 param_base = reg.Register.Index;
956 }
957
958 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
959 param_index, param_base,
960 name, index, !reg.Register.Dimension);
961 }
962
963 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
964 LLVMTypeRef type, unsigned swizzle,
965 LLVMValueRef buffer, LLVMValueRef offset,
966 LLVMValueRef base, bool can_speculate)
967 {
968 struct si_shader_context *ctx = si_shader_context(bld_base);
969 LLVMValueRef value, value2;
970 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
971
972 if (swizzle == ~0) {
973 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
974 0, ac_glc, can_speculate, false);
975
976 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
977 }
978
979 if (!llvm_type_is_64bit(ctx, type)) {
980 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
981 0, ac_glc, can_speculate, false);
982
983 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
984 return LLVMBuildExtractElement(ctx->ac.builder, value,
985 LLVMConstInt(ctx->i32, swizzle, 0), "");
986 }
987
988 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
989 swizzle * 4, ac_glc, can_speculate, false);
990
991 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
992 swizzle * 4 + 4, ac_glc, can_speculate, false);
993
994 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
995 }
996
997 /**
998 * Load from LSHS LDS storage.
999 *
1000 * \param type output value type
1001 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1002 * \param dw_addr address in dwords
1003 */
1004 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1005 LLVMTypeRef type, unsigned swizzle,
1006 LLVMValueRef dw_addr)
1007 {
1008 struct si_shader_context *ctx = si_shader_context(bld_base);
1009 LLVMValueRef value;
1010
1011 if (swizzle == ~0) {
1012 LLVMValueRef values[TGSI_NUM_CHANNELS];
1013
1014 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1015 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1016
1017 return ac_build_gather_values(&ctx->ac, values,
1018 TGSI_NUM_CHANNELS);
1019 }
1020
1021 /* Split 64-bit loads. */
1022 if (llvm_type_is_64bit(ctx, type)) {
1023 LLVMValueRef lo, hi;
1024
1025 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1026 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1027 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1028 }
1029
1030 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1031 LLVMConstInt(ctx->i32, swizzle, 0), "");
1032
1033 value = ac_lds_load(&ctx->ac, dw_addr);
1034
1035 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1036 }
1037
1038 /**
1039 * Store to LSHS LDS storage.
1040 *
1041 * \param swizzle offset (typically 0..3)
1042 * \param dw_addr address in dwords
1043 * \param value value to store
1044 */
1045 static void lshs_lds_store(struct si_shader_context *ctx,
1046 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1047 LLVMValueRef value)
1048 {
1049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1050 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1051
1052 ac_lds_store(&ctx->ac, dw_addr, value);
1053 }
1054
1055 enum si_tess_ring {
1056 TCS_FACTOR_RING,
1057 TESS_OFFCHIP_RING_TCS,
1058 TESS_OFFCHIP_RING_TES,
1059 };
1060
1061 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1062 enum si_tess_ring ring)
1063 {
1064 LLVMBuilderRef builder = ctx->ac.builder;
1065 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1066 ctx->param_tcs_out_lds_layout;
1067 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1068
1069 /* TCS only receives high 13 bits of the address. */
1070 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1071 addr = LLVMBuildAnd(builder, addr,
1072 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1073 }
1074
1075 if (ring == TCS_FACTOR_RING) {
1076 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1077 addr = LLVMBuildAdd(builder, addr,
1078 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1079 }
1080
1081 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1082 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1083 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1084 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1085
1086 if (ctx->screen->info.chip_class >= GFX10)
1087 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1088 S_008F0C_OOB_SELECT(3) |
1089 S_008F0C_RESOURCE_LEVEL(1);
1090 else
1091 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1092 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1093
1094 LLVMValueRef desc[4];
1095 desc[0] = addr;
1096 desc[1] = LLVMConstInt(ctx->i32,
1097 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1098 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1099 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1100
1101 return ac_build_gather_values(&ctx->ac, desc, 4);
1102 }
1103
1104 static LLVMValueRef fetch_input_tcs(
1105 struct lp_build_tgsi_context *bld_base,
1106 const struct tgsi_full_src_register *reg,
1107 enum tgsi_opcode_type type, unsigned swizzle_in)
1108 {
1109 struct si_shader_context *ctx = si_shader_context(bld_base);
1110 LLVMValueRef dw_addr, stride;
1111 unsigned swizzle = swizzle_in & 0xffff;
1112 stride = get_tcs_in_vertex_dw_stride(ctx);
1113 dw_addr = get_tcs_in_current_patch_offset(ctx);
1114 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1115
1116 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1117 }
1118
1119 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1120 LLVMTypeRef type,
1121 LLVMValueRef vertex_index,
1122 LLVMValueRef param_index,
1123 unsigned const_index,
1124 unsigned location,
1125 unsigned driver_location,
1126 unsigned component,
1127 unsigned num_components,
1128 bool is_patch,
1129 bool is_compact,
1130 bool load_input)
1131 {
1132 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1133 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1134 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1135 LLVMValueRef dw_addr, stride;
1136
1137 driver_location = driver_location / 4;
1138
1139 if (load_input) {
1140 stride = get_tcs_in_vertex_dw_stride(ctx);
1141 dw_addr = get_tcs_in_current_patch_offset(ctx);
1142 } else {
1143 if (is_patch) {
1144 stride = NULL;
1145 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1146 } else {
1147 stride = get_tcs_out_vertex_dw_stride(ctx);
1148 dw_addr = get_tcs_out_current_patch_offset(ctx);
1149 }
1150 }
1151
1152 if (!param_index) {
1153 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1154 }
1155
1156 ubyte *names;
1157 ubyte *indices;
1158 if (load_input) {
1159 names = info->input_semantic_name;
1160 indices = info->input_semantic_index;
1161 } else {
1162 names = info->output_semantic_name;
1163 indices = info->output_semantic_index;
1164 }
1165
1166 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1167 vertex_index, param_index,
1168 driver_location,
1169 names, indices,
1170 is_patch);
1171
1172 LLVMValueRef value[4];
1173 for (unsigned i = 0; i < num_components; i++) {
1174 unsigned offset = i;
1175 if (llvm_type_is_64bit(ctx, type))
1176 offset *= 2;
1177
1178 offset += component;
1179 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1180 }
1181
1182 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1183 }
1184
1185 static LLVMValueRef fetch_output_tcs(
1186 struct lp_build_tgsi_context *bld_base,
1187 const struct tgsi_full_src_register *reg,
1188 enum tgsi_opcode_type type, unsigned swizzle_in)
1189 {
1190 struct si_shader_context *ctx = si_shader_context(bld_base);
1191 LLVMValueRef dw_addr, stride;
1192 unsigned swizzle = (swizzle_in & 0xffff);
1193
1194 if (reg->Register.Dimension) {
1195 stride = get_tcs_out_vertex_dw_stride(ctx);
1196 dw_addr = get_tcs_out_current_patch_offset(ctx);
1197 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1198 } else {
1199 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1201 }
1202
1203 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1204 }
1205
1206 static LLVMValueRef fetch_input_tes(
1207 struct lp_build_tgsi_context *bld_base,
1208 const struct tgsi_full_src_register *reg,
1209 enum tgsi_opcode_type type, unsigned swizzle_in)
1210 {
1211 struct si_shader_context *ctx = si_shader_context(bld_base);
1212 LLVMValueRef base, addr;
1213 unsigned swizzle = (swizzle_in & 0xffff);
1214
1215 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1216 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1217
1218 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1219 ctx->tess_offchip_ring, base, addr, true);
1220 }
1221
1222 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1223 LLVMTypeRef type,
1224 LLVMValueRef vertex_index,
1225 LLVMValueRef param_index,
1226 unsigned const_index,
1227 unsigned location,
1228 unsigned driver_location,
1229 unsigned component,
1230 unsigned num_components,
1231 bool is_patch,
1232 bool is_compact,
1233 bool load_input)
1234 {
1235 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1236 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1237 LLVMValueRef base, addr;
1238
1239 driver_location = driver_location / 4;
1240
1241 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1242
1243 if (!param_index) {
1244 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1245 }
1246
1247 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1248 param_index, driver_location,
1249 info->input_semantic_name,
1250 info->input_semantic_index,
1251 is_patch);
1252
1253 /* TODO: This will generate rather ordinary llvm code, although it
1254 * should be easy for the optimiser to fix up. In future we might want
1255 * to refactor buffer_load(), but for now this maximises code sharing
1256 * between the NIR and TGSI backends.
1257 */
1258 LLVMValueRef value[4];
1259 for (unsigned i = 0; i < num_components; i++) {
1260 unsigned offset = i;
1261 if (llvm_type_is_64bit(ctx, type)) {
1262 offset *= 2;
1263 if (offset == 4) {
1264 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1265 vertex_index,
1266 param_index,
1267 driver_location + 1,
1268 info->input_semantic_name,
1269 info->input_semantic_index,
1270 is_patch);
1271 }
1272
1273 offset = offset % 4;
1274 }
1275
1276 offset += component;
1277 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1278 ctx->tess_offchip_ring, base, addr, true);
1279 }
1280
1281 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1282 }
1283
1284 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1285 const struct tgsi_full_instruction *inst,
1286 const struct tgsi_opcode_info *info,
1287 unsigned index,
1288 LLVMValueRef dst[4])
1289 {
1290 struct si_shader_context *ctx = si_shader_context(bld_base);
1291 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1292 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1293 unsigned chan_index;
1294 LLVMValueRef dw_addr, stride;
1295 LLVMValueRef buffer, base, buf_addr;
1296 LLVMValueRef values[4];
1297 bool skip_lds_store;
1298 bool is_tess_factor = false, is_tess_inner = false;
1299
1300 /* Only handle per-patch and per-vertex outputs here.
1301 * Vectors will be lowered to scalars and this function will be called again.
1302 */
1303 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1304 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1305 si_llvm_emit_store(bld_base, inst, info, index, dst);
1306 return;
1307 }
1308
1309 if (reg->Register.Dimension) {
1310 stride = get_tcs_out_vertex_dw_stride(ctx);
1311 dw_addr = get_tcs_out_current_patch_offset(ctx);
1312 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1313 skip_lds_store = !sh_info->reads_pervertex_outputs;
1314 } else {
1315 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1316 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1317 skip_lds_store = !sh_info->reads_perpatch_outputs;
1318
1319 if (!reg->Register.Indirect) {
1320 int name = sh_info->output_semantic_name[reg->Register.Index];
1321
1322 /* Always write tess factors into LDS for the TCS epilog. */
1323 if (name == TGSI_SEMANTIC_TESSINNER ||
1324 name == TGSI_SEMANTIC_TESSOUTER) {
1325 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1326 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1327 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1328 is_tess_factor = true;
1329 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1330 }
1331 }
1332 }
1333
1334 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1335
1336 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1337 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1338
1339 uint32_t writemask = reg->Register.WriteMask;
1340 while (writemask) {
1341 chan_index = u_bit_scan(&writemask);
1342 LLVMValueRef value = dst[chan_index];
1343
1344 if (inst->Instruction.Saturate)
1345 value = ac_build_clamp(&ctx->ac, value);
1346
1347 /* Skip LDS stores if there is no LDS read of this output. */
1348 if (!skip_lds_store)
1349 lshs_lds_store(ctx, chan_index, dw_addr, value);
1350
1351 value = ac_to_integer(&ctx->ac, value);
1352 values[chan_index] = value;
1353
1354 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1355 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1356 buf_addr, base,
1357 4 * chan_index, ac_glc, false);
1358 }
1359
1360 /* Write tess factors into VGPRs for the epilog. */
1361 if (is_tess_factor &&
1362 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1363 if (!is_tess_inner) {
1364 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1365 ctx->invoc0_tess_factors[chan_index]);
1366 } else if (chan_index < 2) {
1367 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1368 ctx->invoc0_tess_factors[4 + chan_index]);
1369 }
1370 }
1371 }
1372
1373 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1374 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1375 values, 4);
1376 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1377 base, 0, ac_glc, false);
1378 }
1379 }
1380
1381 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1382 const struct nir_variable *var,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef param_index,
1385 unsigned const_index,
1386 LLVMValueRef src,
1387 unsigned writemask)
1388 {
1389 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1390 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1391 const unsigned component = var->data.location_frac;
1392 const bool is_patch = var->data.patch;
1393 unsigned driver_location = var->data.driver_location;
1394 LLVMValueRef dw_addr, stride;
1395 LLVMValueRef buffer, base, addr;
1396 LLVMValueRef values[8];
1397 bool skip_lds_store;
1398 bool is_tess_factor = false, is_tess_inner = false;
1399
1400 driver_location = driver_location / 4;
1401
1402 bool is_const = !param_index;
1403 if (!param_index)
1404 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1405
1406 if (!is_patch) {
1407 stride = get_tcs_out_vertex_dw_stride(ctx);
1408 dw_addr = get_tcs_out_current_patch_offset(ctx);
1409 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1410 vertex_index, param_index,
1411 driver_location,
1412 info->output_semantic_name,
1413 info->output_semantic_index,
1414 is_patch);
1415
1416 skip_lds_store = !info->reads_pervertex_outputs;
1417 } else {
1418 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1419 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1420 vertex_index, param_index,
1421 driver_location,
1422 info->output_semantic_name,
1423 info->output_semantic_index,
1424 is_patch);
1425
1426 skip_lds_store = !info->reads_perpatch_outputs;
1427
1428 if (is_const && const_index == 0) {
1429 int name = info->output_semantic_name[driver_location];
1430
1431 /* Always write tess factors into LDS for the TCS epilog. */
1432 if (name == TGSI_SEMANTIC_TESSINNER ||
1433 name == TGSI_SEMANTIC_TESSOUTER) {
1434 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1435 skip_lds_store = !info->reads_tessfactor_outputs &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1437 is_tess_factor = true;
1438 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1439 }
1440 }
1441 }
1442
1443 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1444
1445 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1446
1447 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1448 param_index, driver_location,
1449 info->output_semantic_name,
1450 info->output_semantic_index,
1451 is_patch);
1452
1453 for (unsigned chan = 0; chan < 8; chan++) {
1454 if (!(writemask & (1 << chan)))
1455 continue;
1456 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1457
1458 unsigned buffer_store_offset = chan % 4;
1459 if (chan == 4) {
1460 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1461 vertex_index,
1462 param_index,
1463 driver_location + 1,
1464 info->output_semantic_name,
1465 info->output_semantic_index,
1466 is_patch);
1467 }
1468
1469 /* Skip LDS stores if there is no LDS read of this output. */
1470 if (!skip_lds_store)
1471 lshs_lds_store(ctx, chan, dw_addr, value);
1472
1473 value = ac_to_integer(&ctx->ac, value);
1474 values[chan] = value;
1475
1476 if (writemask != 0xF && !is_tess_factor) {
1477 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1478 addr, base,
1479 4 * buffer_store_offset,
1480 ac_glc, false);
1481 }
1482
1483 /* Write tess factors into VGPRs for the epilog. */
1484 if (is_tess_factor &&
1485 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1486 if (!is_tess_inner) {
1487 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1488 ctx->invoc0_tess_factors[chan]);
1489 } else if (chan < 2) {
1490 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1491 ctx->invoc0_tess_factors[4 + chan]);
1492 }
1493 }
1494 }
1495
1496 if (writemask == 0xF && !is_tess_factor) {
1497 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1498 values, 4);
1499 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1500 base, 0, ac_glc, false);
1501 }
1502 }
1503
1504 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1505 unsigned input_index,
1506 unsigned vtx_offset_param,
1507 LLVMTypeRef type,
1508 unsigned swizzle)
1509 {
1510 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1511 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1512 struct si_shader *shader = ctx->shader;
1513 LLVMValueRef vtx_offset, soffset;
1514 struct tgsi_shader_info *info = &shader->selector->info;
1515 unsigned semantic_name = info->input_semantic_name[input_index];
1516 unsigned semantic_index = info->input_semantic_index[input_index];
1517 unsigned param;
1518 LLVMValueRef value;
1519
1520 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1521
1522 /* GFX9 has the ESGS ring in LDS. */
1523 if (ctx->screen->info.chip_class >= GFX9) {
1524 unsigned index = vtx_offset_param;
1525
1526 switch (index / 2) {
1527 case 0:
1528 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1529 index % 2 ? 16 : 0, 16);
1530 break;
1531 case 1:
1532 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1533 index % 2 ? 16 : 0, 16);
1534 break;
1535 case 2:
1536 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1537 index % 2 ? 16 : 0, 16);
1538 break;
1539 default:
1540 assert(0);
1541 return NULL;
1542 }
1543
1544 unsigned offset = param * 4 + swizzle;
1545 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1546 LLVMConstInt(ctx->i32, offset, false), "");
1547
1548 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1549 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1550 if (llvm_type_is_64bit(ctx, type)) {
1551 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1552 &ctx->ac.i32_1, 1, "");
1553 LLVMValueRef values[2] = {
1554 value,
1555 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1556 };
1557 value = ac_build_gather_values(&ctx->ac, values, 2);
1558 }
1559 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1560 }
1561
1562 /* GFX6: input load from the ESGS ring in memory. */
1563 if (swizzle == ~0) {
1564 LLVMValueRef values[TGSI_NUM_CHANNELS];
1565 unsigned chan;
1566 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1567 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1568 type, chan);
1569 }
1570 return ac_build_gather_values(&ctx->ac, values,
1571 TGSI_NUM_CHANNELS);
1572 }
1573
1574 /* Get the vertex offset parameter on GFX6. */
1575 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1576
1577 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1578 LLVMConstInt(ctx->i32, 4, 0), "");
1579
1580 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1581
1582 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1583 vtx_offset, soffset, 0, ac_glc, true, false);
1584 if (llvm_type_is_64bit(ctx, type)) {
1585 LLVMValueRef value2;
1586 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1587
1588 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1589 ctx->i32_0, vtx_offset, soffset,
1590 0, ac_glc, true, false);
1591 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1592 }
1593 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1594 }
1595
1596 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1597 unsigned location,
1598 unsigned driver_location,
1599 unsigned component,
1600 unsigned num_components,
1601 unsigned vertex_index,
1602 unsigned const_index,
1603 LLVMTypeRef type)
1604 {
1605 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1606
1607 LLVMValueRef value[4];
1608 for (unsigned i = 0; i < num_components; i++) {
1609 unsigned offset = i;
1610 if (llvm_type_is_64bit(ctx, type))
1611 offset *= 2;
1612
1613 offset += component;
1614 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4 + const_index,
1615 vertex_index, type, offset);
1616 }
1617
1618 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1619 }
1620
1621 static LLVMValueRef fetch_input_gs(
1622 struct lp_build_tgsi_context *bld_base,
1623 const struct tgsi_full_src_register *reg,
1624 enum tgsi_opcode_type type,
1625 unsigned swizzle_in)
1626 {
1627 struct si_shader_context *ctx = si_shader_context(bld_base);
1628 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1629 unsigned swizzle = swizzle_in & 0xffff;
1630
1631 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1632 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1633 return si_get_primitive_id(ctx, swizzle);
1634
1635 if (!reg->Register.Dimension)
1636 return NULL;
1637
1638 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1639 reg->Dimension.Index,
1640 tgsi2llvmtype(bld_base, type),
1641 swizzle);
1642 }
1643
1644 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1645 {
1646 switch (interpolate) {
1647 case TGSI_INTERPOLATE_CONSTANT:
1648 return 0;
1649
1650 case TGSI_INTERPOLATE_LINEAR:
1651 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1652 return SI_PARAM_LINEAR_SAMPLE;
1653 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1654 return SI_PARAM_LINEAR_CENTROID;
1655 else
1656 return SI_PARAM_LINEAR_CENTER;
1657 break;
1658 case TGSI_INTERPOLATE_COLOR:
1659 case TGSI_INTERPOLATE_PERSPECTIVE:
1660 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1661 return SI_PARAM_PERSP_SAMPLE;
1662 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1663 return SI_PARAM_PERSP_CENTROID;
1664 else
1665 return SI_PARAM_PERSP_CENTER;
1666 break;
1667 default:
1668 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1669 return -1;
1670 }
1671 }
1672
1673 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1674 unsigned attr_index, unsigned chan,
1675 LLVMValueRef prim_mask,
1676 LLVMValueRef i, LLVMValueRef j)
1677 {
1678 if (i || j) {
1679 return ac_build_fs_interp(&ctx->ac,
1680 LLVMConstInt(ctx->i32, chan, 0),
1681 LLVMConstInt(ctx->i32, attr_index, 0),
1682 prim_mask, i, j);
1683 }
1684 return ac_build_fs_interp_mov(&ctx->ac,
1685 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1686 LLVMConstInt(ctx->i32, chan, 0),
1687 LLVMConstInt(ctx->i32, attr_index, 0),
1688 prim_mask);
1689 }
1690
1691 /**
1692 * Interpolate a fragment shader input.
1693 *
1694 * @param ctx context
1695 * @param input_index index of the input in hardware
1696 * @param semantic_name TGSI_SEMANTIC_*
1697 * @param semantic_index semantic index
1698 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1699 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1700 * @param interp_param interpolation weights (i,j)
1701 * @param prim_mask SI_PARAM_PRIM_MASK
1702 * @param face SI_PARAM_FRONT_FACE
1703 * @param result the return value (4 components)
1704 */
1705 static void interp_fs_input(struct si_shader_context *ctx,
1706 unsigned input_index,
1707 unsigned semantic_name,
1708 unsigned semantic_index,
1709 unsigned num_interp_inputs,
1710 unsigned colors_read_mask,
1711 LLVMValueRef interp_param,
1712 LLVMValueRef prim_mask,
1713 LLVMValueRef face,
1714 LLVMValueRef result[4])
1715 {
1716 LLVMValueRef i = NULL, j = NULL;
1717 unsigned chan;
1718
1719 /* fs.constant returns the param from the middle vertex, so it's not
1720 * really useful for flat shading. It's meant to be used for custom
1721 * interpolation (but the intrinsic can't fetch from the other two
1722 * vertices).
1723 *
1724 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1725 * to do the right thing. The only reason we use fs.constant is that
1726 * fs.interp cannot be used on integers, because they can be equal
1727 * to NaN.
1728 *
1729 * When interp is false we will use fs.constant or for newer llvm,
1730 * amdgcn.interp.mov.
1731 */
1732 bool interp = interp_param != NULL;
1733
1734 if (interp) {
1735 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1736 LLVMVectorType(ctx->f32, 2), "");
1737
1738 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1739 ctx->i32_0, "");
1740 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1741 ctx->i32_1, "");
1742 }
1743
1744 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1745 ctx->shader->key.part.ps.prolog.color_two_side) {
1746 LLVMValueRef is_face_positive;
1747
1748 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1749 * otherwise it's at offset "num_inputs".
1750 */
1751 unsigned back_attr_offset = num_interp_inputs;
1752 if (semantic_index == 1 && colors_read_mask & 0xf)
1753 back_attr_offset += 1;
1754
1755 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1756 face, ctx->i32_0, "");
1757
1758 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1759 LLVMValueRef front, back;
1760
1761 front = si_build_fs_interp(ctx,
1762 input_index, chan,
1763 prim_mask, i, j);
1764 back = si_build_fs_interp(ctx,
1765 back_attr_offset, chan,
1766 prim_mask, i, j);
1767
1768 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1769 is_face_positive,
1770 front,
1771 back,
1772 "");
1773 }
1774 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1775 result[0] = si_build_fs_interp(ctx, input_index,
1776 0, prim_mask, i, j);
1777 result[1] =
1778 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1779 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1780 } else {
1781 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1782 result[chan] = si_build_fs_interp(ctx,
1783 input_index, chan,
1784 prim_mask, i, j);
1785 }
1786 }
1787 }
1788
1789 void si_llvm_load_input_fs(
1790 struct si_shader_context *ctx,
1791 unsigned input_index,
1792 LLVMValueRef out[4])
1793 {
1794 struct si_shader *shader = ctx->shader;
1795 struct tgsi_shader_info *info = &shader->selector->info;
1796 LLVMValueRef main_fn = ctx->main_fn;
1797 LLVMValueRef interp_param = NULL;
1798 int interp_param_idx;
1799 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1800 unsigned semantic_index = info->input_semantic_index[input_index];
1801 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1802 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1803
1804 /* Get colors from input VGPRs (set by the prolog). */
1805 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1806 unsigned colors_read = shader->selector->info.colors_read;
1807 unsigned mask = colors_read >> (semantic_index * 4);
1808 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1809 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1810 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1811
1812 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1813 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1814 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1815 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1816 return;
1817 }
1818
1819 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1820 if (interp_param_idx == -1)
1821 return;
1822 else if (interp_param_idx) {
1823 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1824 }
1825
1826 interp_fs_input(ctx, input_index, semantic_name,
1827 semantic_index, 0, /* this param is unused */
1828 shader->selector->info.colors_read, interp_param,
1829 ctx->abi.prim_mask,
1830 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1831 &out[0]);
1832 }
1833
1834 static void declare_input_fs(
1835 struct si_shader_context *ctx,
1836 unsigned input_index,
1837 const struct tgsi_full_declaration *decl,
1838 LLVMValueRef out[4])
1839 {
1840 si_llvm_load_input_fs(ctx, input_index, out);
1841 }
1842
1843 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1844 {
1845 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1846 }
1847
1848 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1849 {
1850 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1851
1852 /* For non-indexed draws, the base vertex set by the driver
1853 * (for direct draws) or the CP (for indirect draws) is the
1854 * first vertex ID, but GLSL expects 0 to be returned.
1855 */
1856 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1857 ctx->param_vs_state_bits);
1858 LLVMValueRef indexed;
1859
1860 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1861 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1862
1863 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1864 ctx->i32_0, "");
1865 }
1866
1867 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1868 {
1869 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1870
1871 LLVMValueRef values[3];
1872 LLVMValueRef result;
1873 unsigned i;
1874 unsigned *properties = ctx->shader->selector->info.properties;
1875
1876 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1877 unsigned sizes[3] = {
1878 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1879 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1880 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1881 };
1882
1883 for (i = 0; i < 3; ++i)
1884 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1885
1886 result = ac_build_gather_values(&ctx->ac, values, 3);
1887 } else {
1888 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1889 }
1890
1891 return result;
1892 }
1893
1894 /**
1895 * Load a dword from a constant buffer.
1896 */
1897 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1898 LLVMValueRef resource,
1899 LLVMValueRef offset)
1900 {
1901 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1902 0, 0, true, true);
1903 }
1904
1905 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1906 {
1907 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1908 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1909 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1910 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1911
1912 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1913 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1914 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1915
1916 LLVMValueRef pos[4] = {
1917 buffer_load_const(ctx, resource, offset0),
1918 buffer_load_const(ctx, resource, offset1),
1919 LLVMConstReal(ctx->f32, 0),
1920 LLVMConstReal(ctx->f32, 0)
1921 };
1922
1923 return ac_build_gather_values(&ctx->ac, pos, 4);
1924 }
1925
1926 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1927 {
1928 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1929 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1930 }
1931
1932 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1933 {
1934 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1935 LLVMValueRef coord[4] = {
1936 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1937 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1938 ctx->ac.f32_0,
1939 ctx->ac.f32_0
1940 };
1941
1942 /* For triangles, the vector should be (u, v, 1-u-v). */
1943 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1944 PIPE_PRIM_TRIANGLES) {
1945 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1946 LLVMBuildFAdd(ctx->ac.builder,
1947 coord[0], coord[1], ""), "");
1948 }
1949 return ac_build_gather_values(&ctx->ac, coord, 4);
1950 }
1951
1952 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1953 unsigned semantic_name)
1954 {
1955 LLVMValueRef base, addr;
1956
1957 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1958
1959 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1960 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1961 LLVMConstInt(ctx->i32, param, 0));
1962
1963 return buffer_load(&ctx->bld_base, ctx->f32,
1964 ~0, ctx->tess_offchip_ring, base, addr, true);
1965
1966 }
1967
1968 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1969 unsigned semantic_name)
1970 {
1971 LLVMValueRef buf, slot, val[4];
1972 int i, offset;
1973
1974 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1975 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1976 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1977 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1978
1979 for (i = 0; i < 4; i++)
1980 val[i] = buffer_load_const(ctx, buf,
1981 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1982 return ac_build_gather_values(&ctx->ac, val, 4);
1983 }
1984
1985 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1986 unsigned varying_id,
1987 bool load_default_state)
1988 {
1989 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1990 unsigned semantic_name;
1991
1992 if (load_default_state) {
1993 switch (varying_id) {
1994 case VARYING_SLOT_TESS_LEVEL_INNER:
1995 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
1996 break;
1997 case VARYING_SLOT_TESS_LEVEL_OUTER:
1998 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
1999 break;
2000 default:
2001 unreachable("unknown tess level");
2002 }
2003 return load_tess_level_default(ctx, semantic_name);
2004 }
2005
2006 switch (varying_id) {
2007 case VARYING_SLOT_TESS_LEVEL_INNER:
2008 semantic_name = TGSI_SEMANTIC_TESSINNER;
2009 break;
2010 case VARYING_SLOT_TESS_LEVEL_OUTER:
2011 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2012 break;
2013 default:
2014 unreachable("unknown tess level");
2015 }
2016
2017 return load_tess_level(ctx, semantic_name);
2018
2019 }
2020
2021 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2022 {
2023 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2024 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2025 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2026 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2027 return get_num_tcs_out_vertices(ctx);
2028 else
2029 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2030 }
2031
2032 void si_load_system_value(struct si_shader_context *ctx,
2033 unsigned index,
2034 const struct tgsi_full_declaration *decl)
2035 {
2036 LLVMValueRef value = 0;
2037
2038 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2039
2040 switch (decl->Semantic.Name) {
2041 case TGSI_SEMANTIC_INSTANCEID:
2042 value = ctx->abi.instance_id;
2043 break;
2044
2045 case TGSI_SEMANTIC_VERTEXID:
2046 value = LLVMBuildAdd(ctx->ac.builder,
2047 ctx->abi.vertex_id,
2048 ctx->abi.base_vertex, "");
2049 break;
2050
2051 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2052 /* Unused. Clarify the meaning in indexed vs. non-indexed
2053 * draws if this is ever used again. */
2054 assert(false);
2055 break;
2056
2057 case TGSI_SEMANTIC_BASEVERTEX:
2058 value = get_base_vertex(&ctx->abi);
2059 break;
2060
2061 case TGSI_SEMANTIC_BASEINSTANCE:
2062 value = ctx->abi.start_instance;
2063 break;
2064
2065 case TGSI_SEMANTIC_DRAWID:
2066 value = ctx->abi.draw_id;
2067 break;
2068
2069 case TGSI_SEMANTIC_INVOCATIONID:
2070 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2071 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2072 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2073 if (ctx->screen->info.chip_class >= GFX10) {
2074 value = LLVMBuildAnd(ctx->ac.builder,
2075 ctx->abi.gs_invocation_id,
2076 LLVMConstInt(ctx->i32, 127, 0), "");
2077 } else {
2078 value = ctx->abi.gs_invocation_id;
2079 }
2080 } else {
2081 assert(!"INVOCATIONID not implemented");
2082 }
2083 break;
2084
2085 case TGSI_SEMANTIC_POSITION:
2086 {
2087 LLVMValueRef pos[4] = {
2088 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2089 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2090 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2091 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2092 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2093 };
2094 value = ac_build_gather_values(&ctx->ac, pos, 4);
2095 break;
2096 }
2097
2098 case TGSI_SEMANTIC_FACE:
2099 value = ctx->abi.front_face;
2100 break;
2101
2102 case TGSI_SEMANTIC_SAMPLEID:
2103 value = si_get_sample_id(ctx);
2104 break;
2105
2106 case TGSI_SEMANTIC_SAMPLEPOS: {
2107 LLVMValueRef pos[4] = {
2108 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2109 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2110 LLVMConstReal(ctx->f32, 0),
2111 LLVMConstReal(ctx->f32, 0)
2112 };
2113 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2114 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2115 value = ac_build_gather_values(&ctx->ac, pos, 4);
2116 break;
2117 }
2118
2119 case TGSI_SEMANTIC_SAMPLEMASK:
2120 /* This can only occur with the OpenGL Core profile, which
2121 * doesn't support smoothing.
2122 */
2123 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2124 break;
2125
2126 case TGSI_SEMANTIC_TESSCOORD:
2127 value = si_load_tess_coord(&ctx->abi);
2128 break;
2129
2130 case TGSI_SEMANTIC_VERTICESIN:
2131 value = si_load_patch_vertices_in(&ctx->abi);
2132 break;
2133
2134 case TGSI_SEMANTIC_TESSINNER:
2135 case TGSI_SEMANTIC_TESSOUTER:
2136 value = load_tess_level(ctx, decl->Semantic.Name);
2137 break;
2138
2139 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
2140 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
2141 value = load_tess_level_default(ctx, decl->Semantic.Name);
2142 break;
2143
2144 case TGSI_SEMANTIC_PRIMID:
2145 value = si_get_primitive_id(ctx, 0);
2146 break;
2147
2148 case TGSI_SEMANTIC_GRID_SIZE:
2149 value = ctx->abi.num_work_groups;
2150 break;
2151
2152 case TGSI_SEMANTIC_BLOCK_SIZE:
2153 value = get_block_size(&ctx->abi);
2154 break;
2155
2156 case TGSI_SEMANTIC_BLOCK_ID:
2157 {
2158 LLVMValueRef values[3];
2159
2160 for (int i = 0; i < 3; i++) {
2161 values[i] = ctx->i32_0;
2162 if (ctx->abi.workgroup_ids[i]) {
2163 values[i] = ctx->abi.workgroup_ids[i];
2164 }
2165 }
2166 value = ac_build_gather_values(&ctx->ac, values, 3);
2167 break;
2168 }
2169
2170 case TGSI_SEMANTIC_THREAD_ID:
2171 value = ctx->abi.local_invocation_ids;
2172 break;
2173
2174 case TGSI_SEMANTIC_HELPER_INVOCATION:
2175 value = ac_build_load_helper_invocation(&ctx->ac);
2176 break;
2177
2178 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2179 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2180 break;
2181
2182 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2183 value = ac_get_thread_id(&ctx->ac);
2184 break;
2185
2186 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2187 {
2188 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2189 if (ctx->ac.wave_size == 64)
2190 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2191 value = LLVMBuildShl(ctx->ac.builder,
2192 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2193 if (ctx->ac.wave_size == 32)
2194 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2195 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2196 break;
2197 }
2198
2199 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2200 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2201 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2202 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2203 {
2204 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2205 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2206 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2207 /* All bits set except LSB */
2208 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2209 } else {
2210 /* All bits set */
2211 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2212 }
2213 if (ctx->ac.wave_size == 64)
2214 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2215 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2216 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2217 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2218 value = LLVMBuildNot(ctx->ac.builder, value, "");
2219 if (ctx->ac.wave_size == 32)
2220 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2221 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2222 break;
2223 }
2224
2225 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
2226 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2227 break;
2228
2229 default:
2230 assert(!"unknown system value");
2231 return;
2232 }
2233
2234 ctx->system_values[index] = value;
2235 }
2236
2237 void si_declare_compute_memory(struct si_shader_context *ctx)
2238 {
2239 struct si_shader_selector *sel = ctx->shader->selector;
2240 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2241
2242 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2243 LLVMValueRef var;
2244
2245 assert(!ctx->ac.lds);
2246
2247 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2248 LLVMArrayType(ctx->i8, lds_size),
2249 "compute_lds",
2250 AC_ADDR_SPACE_LDS);
2251 LLVMSetAlignment(var, 64 * 1024);
2252
2253 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2254 }
2255
2256 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2257 const struct tgsi_full_declaration *decl)
2258 {
2259 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2260 assert(decl->Range.First == decl->Range.Last);
2261
2262 si_declare_compute_memory(ctx);
2263 }
2264
2265 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2266 {
2267 LLVMValueRef ptr =
2268 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2269 struct si_shader_selector *sel = ctx->shader->selector;
2270
2271 /* Do the bounds checking with a descriptor, because
2272 * doing computation and manual bounds checking of 64-bit
2273 * addresses generates horrible VALU code with very high
2274 * VGPR usage and very low SIMD occupancy.
2275 */
2276 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2277
2278 LLVMValueRef desc0, desc1;
2279 desc0 = ptr;
2280 desc1 = LLVMConstInt(ctx->i32,
2281 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2282
2283 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2287
2288 if (ctx->screen->info.chip_class >= GFX10)
2289 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2290 S_008F0C_OOB_SELECT(3) |
2291 S_008F0C_RESOURCE_LEVEL(1);
2292 else
2293 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2294 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2295
2296 LLVMValueRef desc_elems[] = {
2297 desc0,
2298 desc1,
2299 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2300 LLVMConstInt(ctx->i32, rsrc3, false)
2301 };
2302
2303 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2304 }
2305
2306 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2307 {
2308 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2309 ctx->param_const_and_shader_buffers);
2310
2311 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2312 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2313 }
2314
2315 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2316 {
2317 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2318 struct si_shader_selector *sel = ctx->shader->selector;
2319
2320 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2321
2322 if (sel->info.const_buffers_declared == 1 &&
2323 sel->info.shader_buffers_declared == 0) {
2324 return load_const_buffer_desc_fast_path(ctx);
2325 }
2326
2327 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2328 index = LLVMBuildAdd(ctx->ac.builder, index,
2329 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2330
2331 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2332 }
2333
2334 static LLVMValueRef
2335 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2336 {
2337 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2338 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2339 ctx->param_const_and_shader_buffers);
2340
2341 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2342 index = LLVMBuildSub(ctx->ac.builder,
2343 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2344 index, "");
2345
2346 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2347 }
2348
2349 static LLVMValueRef fetch_constant(
2350 struct lp_build_tgsi_context *bld_base,
2351 const struct tgsi_full_src_register *reg,
2352 enum tgsi_opcode_type type,
2353 unsigned swizzle_in)
2354 {
2355 struct si_shader_context *ctx = si_shader_context(bld_base);
2356 struct si_shader_selector *sel = ctx->shader->selector;
2357 const struct tgsi_ind_register *ireg = &reg->Indirect;
2358 unsigned buf, idx;
2359 unsigned swizzle = swizzle_in & 0xffff;
2360
2361 LLVMValueRef addr, bufp;
2362
2363 if (swizzle_in == LP_CHAN_ALL) {
2364 unsigned chan;
2365 LLVMValueRef values[4];
2366 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2367 values[chan] = fetch_constant(bld_base, reg, type, chan);
2368
2369 return ac_build_gather_values(&ctx->ac, values, 4);
2370 }
2371
2372 /* Split 64-bit loads. */
2373 if (tgsi_type_is_64bit(type)) {
2374 LLVMValueRef lo, hi;
2375
2376 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2377 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2378 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2379 lo, hi);
2380 }
2381
2382 idx = reg->Register.Index * 4 + swizzle;
2383 if (reg->Register.Indirect) {
2384 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2385 } else {
2386 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2387 }
2388
2389 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2390 if (sel->info.const_buffers_declared == 1 &&
2391 sel->info.shader_buffers_declared == 0) {
2392 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2393 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2394 return bitcast(bld_base, type, result);
2395 }
2396
2397 assert(reg->Register.Dimension);
2398 buf = reg->Dimension.Index;
2399
2400 if (reg->Dimension.Indirect) {
2401 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2402 LLVMValueRef index;
2403 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2404 reg->Dimension.Index,
2405 ctx->num_const_buffers);
2406 index = LLVMBuildAdd(ctx->ac.builder, index,
2407 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2408 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2409 } else
2410 bufp = load_const_buffer_desc(ctx, buf);
2411
2412 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2413 }
2414
2415 /* Initialize arguments for the shader export intrinsic */
2416 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2417 LLVMValueRef *values,
2418 unsigned target,
2419 struct ac_export_args *args)
2420 {
2421 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2422 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2423 unsigned chan;
2424 bool is_int8, is_int10;
2425
2426 /* Default is 0xf. Adjusted below depending on the format. */
2427 args->enabled_channels = 0xf; /* writemask */
2428
2429 /* Specify whether the EXEC mask represents the valid mask */
2430 args->valid_mask = 0;
2431
2432 /* Specify whether this is the last export */
2433 args->done = 0;
2434
2435 /* Specify the target we are exporting */
2436 args->target = target;
2437
2438 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2439 const struct si_shader_key *key = &ctx->shader->key;
2440 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2441 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2442
2443 assert(cbuf >= 0 && cbuf < 8);
2444 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2445 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2446 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2447 }
2448
2449 args->compr = false;
2450 args->out[0] = f32undef;
2451 args->out[1] = f32undef;
2452 args->out[2] = f32undef;
2453 args->out[3] = f32undef;
2454
2455 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2456 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2457 unsigned bits, bool hi) = NULL;
2458
2459 switch (spi_shader_col_format) {
2460 case V_028714_SPI_SHADER_ZERO:
2461 args->enabled_channels = 0; /* writemask */
2462 args->target = V_008DFC_SQ_EXP_NULL;
2463 break;
2464
2465 case V_028714_SPI_SHADER_32_R:
2466 args->enabled_channels = 1; /* writemask */
2467 args->out[0] = values[0];
2468 break;
2469
2470 case V_028714_SPI_SHADER_32_GR:
2471 args->enabled_channels = 0x3; /* writemask */
2472 args->out[0] = values[0];
2473 args->out[1] = values[1];
2474 break;
2475
2476 case V_028714_SPI_SHADER_32_AR:
2477 if (ctx->screen->info.chip_class >= GFX10) {
2478 args->enabled_channels = 0x3; /* writemask */
2479 args->out[0] = values[0];
2480 args->out[1] = values[3];
2481 } else {
2482 args->enabled_channels = 0x9; /* writemask */
2483 args->out[0] = values[0];
2484 args->out[3] = values[3];
2485 }
2486 break;
2487
2488 case V_028714_SPI_SHADER_FP16_ABGR:
2489 packf = ac_build_cvt_pkrtz_f16;
2490 break;
2491
2492 case V_028714_SPI_SHADER_UNORM16_ABGR:
2493 packf = ac_build_cvt_pknorm_u16;
2494 break;
2495
2496 case V_028714_SPI_SHADER_SNORM16_ABGR:
2497 packf = ac_build_cvt_pknorm_i16;
2498 break;
2499
2500 case V_028714_SPI_SHADER_UINT16_ABGR:
2501 packi = ac_build_cvt_pk_u16;
2502 break;
2503
2504 case V_028714_SPI_SHADER_SINT16_ABGR:
2505 packi = ac_build_cvt_pk_i16;
2506 break;
2507
2508 case V_028714_SPI_SHADER_32_ABGR:
2509 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2510 break;
2511 }
2512
2513 /* Pack f16 or norm_i16/u16. */
2514 if (packf) {
2515 for (chan = 0; chan < 2; chan++) {
2516 LLVMValueRef pack_args[2] = {
2517 values[2 * chan],
2518 values[2 * chan + 1]
2519 };
2520 LLVMValueRef packed;
2521
2522 packed = packf(&ctx->ac, pack_args);
2523 args->out[chan] = ac_to_float(&ctx->ac, packed);
2524 }
2525 args->compr = 1; /* COMPR flag */
2526 }
2527 /* Pack i16/u16. */
2528 if (packi) {
2529 for (chan = 0; chan < 2; chan++) {
2530 LLVMValueRef pack_args[2] = {
2531 ac_to_integer(&ctx->ac, values[2 * chan]),
2532 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2533 };
2534 LLVMValueRef packed;
2535
2536 packed = packi(&ctx->ac, pack_args,
2537 is_int8 ? 8 : is_int10 ? 10 : 16,
2538 chan == 1);
2539 args->out[chan] = ac_to_float(&ctx->ac, packed);
2540 }
2541 args->compr = 1; /* COMPR flag */
2542 }
2543 }
2544
2545 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2546 LLVMValueRef alpha)
2547 {
2548 struct si_shader_context *ctx = si_shader_context(bld_base);
2549
2550 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2551 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2552 [PIPE_FUNC_LESS] = LLVMRealOLT,
2553 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2554 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2555 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2556 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2557 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2558 };
2559 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2560 assert(cond);
2561
2562 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2563 SI_PARAM_ALPHA_REF);
2564 LLVMValueRef alpha_pass =
2565 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2566 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2567 } else {
2568 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2569 }
2570 }
2571
2572 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2573 LLVMValueRef alpha,
2574 unsigned samplemask_param)
2575 {
2576 struct si_shader_context *ctx = si_shader_context(bld_base);
2577 LLVMValueRef coverage;
2578
2579 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2580 coverage = LLVMGetParam(ctx->main_fn,
2581 samplemask_param);
2582 coverage = ac_to_integer(&ctx->ac, coverage);
2583
2584 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2585 ctx->i32,
2586 &coverage, 1, AC_FUNC_ATTR_READNONE);
2587
2588 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2589 ctx->f32, "");
2590
2591 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2592 LLVMConstReal(ctx->f32,
2593 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2594
2595 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2596 }
2597
2598 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2599 struct ac_export_args *pos, LLVMValueRef *out_elts)
2600 {
2601 unsigned reg_index;
2602 unsigned chan;
2603 unsigned const_chan;
2604 LLVMValueRef base_elt;
2605 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2606 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2607 SI_VS_CONST_CLIP_PLANES, 0);
2608 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2609
2610 for (reg_index = 0; reg_index < 2; reg_index ++) {
2611 struct ac_export_args *args = &pos[2 + reg_index];
2612
2613 args->out[0] =
2614 args->out[1] =
2615 args->out[2] =
2616 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2617
2618 /* Compute dot products of position and user clip plane vectors */
2619 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2620 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2621 LLVMValueRef addr =
2622 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2623 const_chan) * 4, 0);
2624 base_elt = buffer_load_const(ctx, const_resource,
2625 addr);
2626 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2627 out_elts[const_chan], args->out[chan]);
2628 }
2629 }
2630
2631 args->enabled_channels = 0xf;
2632 args->valid_mask = 0;
2633 args->done = 0;
2634 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2635 args->compr = 0;
2636 }
2637 }
2638
2639 static void si_dump_streamout(struct pipe_stream_output_info *so)
2640 {
2641 unsigned i;
2642
2643 if (so->num_outputs)
2644 fprintf(stderr, "STREAMOUT\n");
2645
2646 for (i = 0; i < so->num_outputs; i++) {
2647 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2648 so->output[i].start_component;
2649 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2650 i, so->output[i].output_buffer,
2651 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2652 so->output[i].register_index,
2653 mask & 1 ? "x" : "",
2654 mask & 2 ? "y" : "",
2655 mask & 4 ? "z" : "",
2656 mask & 8 ? "w" : "");
2657 }
2658 }
2659
2660 void si_emit_streamout_output(struct si_shader_context *ctx,
2661 LLVMValueRef const *so_buffers,
2662 LLVMValueRef const *so_write_offsets,
2663 struct pipe_stream_output *stream_out,
2664 struct si_shader_output_values *shader_out)
2665 {
2666 unsigned buf_idx = stream_out->output_buffer;
2667 unsigned start = stream_out->start_component;
2668 unsigned num_comps = stream_out->num_components;
2669 LLVMValueRef out[4];
2670
2671 assert(num_comps && num_comps <= 4);
2672 if (!num_comps || num_comps > 4)
2673 return;
2674
2675 /* Load the output as int. */
2676 for (int j = 0; j < num_comps; j++) {
2677 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2678
2679 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2680 }
2681
2682 /* Pack the output. */
2683 LLVMValueRef vdata = NULL;
2684
2685 switch (num_comps) {
2686 case 1: /* as i32 */
2687 vdata = out[0];
2688 break;
2689 case 2: /* as v2i32 */
2690 case 3: /* as v3i32 */
2691 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2692 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2693 break;
2694 }
2695 /* as v4i32 (aligned to 4) */
2696 out[3] = LLVMGetUndef(ctx->i32);
2697 /* fall through */
2698 case 4: /* as v4i32 */
2699 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2700 break;
2701 }
2702
2703 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2704 vdata, num_comps,
2705 so_write_offsets[buf_idx],
2706 ctx->i32_0,
2707 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2708 }
2709
2710 /**
2711 * Write streamout data to buffers for vertex stream @p stream (different
2712 * vertex streams can occur for GS copy shaders).
2713 */
2714 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2715 struct si_shader_output_values *outputs,
2716 unsigned noutput, unsigned stream)
2717 {
2718 struct si_shader_selector *sel = ctx->shader->selector;
2719 struct pipe_stream_output_info *so = &sel->so;
2720 LLVMBuilderRef builder = ctx->ac.builder;
2721 int i;
2722
2723 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2724 LLVMValueRef so_vtx_count =
2725 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2726
2727 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2728
2729 /* can_emit = tid < so_vtx_count; */
2730 LLVMValueRef can_emit =
2731 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2732
2733 /* Emit the streamout code conditionally. This actually avoids
2734 * out-of-bounds buffer access. The hw tells us via the SGPR
2735 * (so_vtx_count) which threads are allowed to emit streamout data. */
2736 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2737 {
2738 /* The buffer offset is computed as follows:
2739 * ByteOffset = streamout_offset[buffer_id]*4 +
2740 * (streamout_write_index + thread_id)*stride[buffer_id] +
2741 * attrib_offset
2742 */
2743
2744 LLVMValueRef so_write_index =
2745 LLVMGetParam(ctx->main_fn,
2746 ctx->param_streamout_write_index);
2747
2748 /* Compute (streamout_write_index + thread_id). */
2749 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2750
2751 /* Load the descriptor and compute the write offset for each
2752 * enabled buffer. */
2753 LLVMValueRef so_write_offset[4] = {};
2754 LLVMValueRef so_buffers[4];
2755 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2756 ctx->param_rw_buffers);
2757
2758 for (i = 0; i < 4; i++) {
2759 if (!so->stride[i])
2760 continue;
2761
2762 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2763 SI_VS_STREAMOUT_BUF0 + i, 0);
2764
2765 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2766
2767 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2768 ctx->param_streamout_offset[i]);
2769 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2770
2771 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2772 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2773 so_offset);
2774 }
2775
2776 /* Write streamout data. */
2777 for (i = 0; i < so->num_outputs; i++) {
2778 unsigned reg = so->output[i].register_index;
2779
2780 if (reg >= noutput)
2781 continue;
2782
2783 if (stream != so->output[i].stream)
2784 continue;
2785
2786 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2787 &so->output[i], &outputs[reg]);
2788 }
2789 }
2790 ac_build_endif(&ctx->ac, 6501);
2791 }
2792
2793 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2794 LLVMValueRef *values)
2795 {
2796 struct ac_export_args args;
2797
2798 si_llvm_init_export_args(ctx, values,
2799 V_008DFC_SQ_EXP_PARAM + index, &args);
2800 ac_build_export(&ctx->ac, &args);
2801 }
2802
2803 static void si_build_param_exports(struct si_shader_context *ctx,
2804 struct si_shader_output_values *outputs,
2805 unsigned noutput)
2806 {
2807 struct si_shader *shader = ctx->shader;
2808 unsigned param_count = 0;
2809
2810 for (unsigned i = 0; i < noutput; i++) {
2811 unsigned semantic_name = outputs[i].semantic_name;
2812 unsigned semantic_index = outputs[i].semantic_index;
2813
2814 if (outputs[i].vertex_stream[0] != 0 &&
2815 outputs[i].vertex_stream[1] != 0 &&
2816 outputs[i].vertex_stream[2] != 0 &&
2817 outputs[i].vertex_stream[3] != 0)
2818 continue;
2819
2820 switch (semantic_name) {
2821 case TGSI_SEMANTIC_LAYER:
2822 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2823 case TGSI_SEMANTIC_CLIPDIST:
2824 case TGSI_SEMANTIC_COLOR:
2825 case TGSI_SEMANTIC_BCOLOR:
2826 case TGSI_SEMANTIC_PRIMID:
2827 case TGSI_SEMANTIC_FOG:
2828 case TGSI_SEMANTIC_TEXCOORD:
2829 case TGSI_SEMANTIC_GENERIC:
2830 break;
2831 default:
2832 continue;
2833 }
2834
2835 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2836 semantic_index < SI_MAX_IO_GENERIC) &&
2837 shader->key.opt.kill_outputs &
2838 (1ull << si_shader_io_get_unique_index(semantic_name,
2839 semantic_index, true)))
2840 continue;
2841
2842 si_export_param(ctx, param_count, outputs[i].values);
2843
2844 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2845 shader->info.vs_output_param_offset[i] = param_count++;
2846 }
2847
2848 shader->info.nr_param_exports = param_count;
2849 }
2850
2851 /**
2852 * Vertex color clamping.
2853 *
2854 * This uses a state constant loaded in a user data SGPR and
2855 * an IF statement is added that clamps all colors if the constant
2856 * is true.
2857 */
2858 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2859 struct si_shader_output_values *outputs,
2860 unsigned noutput)
2861 {
2862 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2863 bool has_colors = false;
2864
2865 /* Store original colors to alloca variables. */
2866 for (unsigned i = 0; i < noutput; i++) {
2867 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2868 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2869 continue;
2870
2871 for (unsigned j = 0; j < 4; j++) {
2872 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2873 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2874 }
2875 has_colors = true;
2876 }
2877
2878 if (!has_colors)
2879 return;
2880
2881 /* The state is in the first bit of the user SGPR. */
2882 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2883 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2884
2885 ac_build_ifcc(&ctx->ac, cond, 6502);
2886
2887 /* Store clamped colors to alloca variables within the conditional block. */
2888 for (unsigned i = 0; i < noutput; i++) {
2889 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2890 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2891 continue;
2892
2893 for (unsigned j = 0; j < 4; j++) {
2894 LLVMBuildStore(ctx->ac.builder,
2895 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2896 addr[i][j]);
2897 }
2898 }
2899 ac_build_endif(&ctx->ac, 6502);
2900
2901 /* Load clamped colors */
2902 for (unsigned i = 0; i < noutput; i++) {
2903 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2904 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2905 continue;
2906
2907 for (unsigned j = 0; j < 4; j++) {
2908 outputs[i].values[j] =
2909 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2910 }
2911 }
2912 }
2913
2914 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2915 * (position and parameter data only).
2916 */
2917 void si_llvm_export_vs(struct si_shader_context *ctx,
2918 struct si_shader_output_values *outputs,
2919 unsigned noutput)
2920 {
2921 struct si_shader *shader = ctx->shader;
2922 struct ac_export_args pos_args[4] = {};
2923 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2924 unsigned pos_idx;
2925 int i;
2926
2927 si_vertex_color_clamping(ctx, outputs, noutput);
2928
2929 /* Build position exports. */
2930 for (i = 0; i < noutput; i++) {
2931 switch (outputs[i].semantic_name) {
2932 case TGSI_SEMANTIC_POSITION:
2933 si_llvm_init_export_args(ctx, outputs[i].values,
2934 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2935 break;
2936 case TGSI_SEMANTIC_PSIZE:
2937 psize_value = outputs[i].values[0];
2938 break;
2939 case TGSI_SEMANTIC_LAYER:
2940 layer_value = outputs[i].values[0];
2941 break;
2942 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2943 viewport_index_value = outputs[i].values[0];
2944 break;
2945 case TGSI_SEMANTIC_EDGEFLAG:
2946 edgeflag_value = outputs[i].values[0];
2947 break;
2948 case TGSI_SEMANTIC_CLIPDIST:
2949 if (!shader->key.opt.clip_disable) {
2950 unsigned index = 2 + outputs[i].semantic_index;
2951 si_llvm_init_export_args(ctx, outputs[i].values,
2952 V_008DFC_SQ_EXP_POS + index,
2953 &pos_args[index]);
2954 }
2955 break;
2956 case TGSI_SEMANTIC_CLIPVERTEX:
2957 if (!shader->key.opt.clip_disable) {
2958 si_llvm_emit_clipvertex(ctx, pos_args,
2959 outputs[i].values);
2960 }
2961 break;
2962 }
2963 }
2964
2965 /* We need to add the position output manually if it's missing. */
2966 if (!pos_args[0].out[0]) {
2967 pos_args[0].enabled_channels = 0xf; /* writemask */
2968 pos_args[0].valid_mask = 0; /* EXEC mask */
2969 pos_args[0].done = 0; /* last export? */
2970 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2971 pos_args[0].compr = 0; /* COMPR flag */
2972 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2973 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2974 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2975 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2976 }
2977
2978 bool pos_writes_edgeflag = shader->selector->info.writes_edgeflag &&
2979 !shader->key.as_ngg;
2980
2981 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2982 if (shader->selector->info.writes_psize ||
2983 pos_writes_edgeflag ||
2984 shader->selector->info.writes_viewport_index ||
2985 shader->selector->info.writes_layer) {
2986 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2987 (pos_writes_edgeflag << 1) |
2988 (shader->selector->info.writes_layer << 2);
2989
2990 pos_args[1].valid_mask = 0; /* EXEC mask */
2991 pos_args[1].done = 0; /* last export? */
2992 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2993 pos_args[1].compr = 0; /* COMPR flag */
2994 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2995 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2996 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2997 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2998
2999 if (shader->selector->info.writes_psize)
3000 pos_args[1].out[0] = psize_value;
3001
3002 if (pos_writes_edgeflag) {
3003 /* The output is a float, but the hw expects an integer
3004 * with the first bit containing the edge flag. */
3005 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
3006 edgeflag_value,
3007 ctx->i32, "");
3008 edgeflag_value = ac_build_umin(&ctx->ac,
3009 edgeflag_value,
3010 ctx->i32_1);
3011
3012 /* The LLVM intrinsic expects a float. */
3013 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3014 }
3015
3016 if (ctx->screen->info.chip_class >= GFX9) {
3017 /* GFX9 has the layer in out.z[10:0] and the viewport
3018 * index in out.z[19:16].
3019 */
3020 if (shader->selector->info.writes_layer)
3021 pos_args[1].out[2] = layer_value;
3022
3023 if (shader->selector->info.writes_viewport_index) {
3024 LLVMValueRef v = viewport_index_value;
3025
3026 v = ac_to_integer(&ctx->ac, v);
3027 v = LLVMBuildShl(ctx->ac.builder, v,
3028 LLVMConstInt(ctx->i32, 16, 0), "");
3029 v = LLVMBuildOr(ctx->ac.builder, v,
3030 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3031 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3032 pos_args[1].enabled_channels |= 1 << 2;
3033 }
3034 } else {
3035 if (shader->selector->info.writes_layer)
3036 pos_args[1].out[2] = layer_value;
3037
3038 if (shader->selector->info.writes_viewport_index) {
3039 pos_args[1].out[3] = viewport_index_value;
3040 pos_args[1].enabled_channels |= 1 << 3;
3041 }
3042 }
3043 }
3044
3045 for (i = 0; i < 4; i++)
3046 if (pos_args[i].out[0])
3047 shader->info.nr_pos_exports++;
3048
3049 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3050 * Setting valid_mask=1 prevents it and has no other effect.
3051 */
3052 if (ctx->screen->info.family == CHIP_NAVI10 ||
3053 ctx->screen->info.family == CHIP_NAVI12 ||
3054 ctx->screen->info.family == CHIP_NAVI14)
3055 pos_args[0].valid_mask = 1;
3056
3057 pos_idx = 0;
3058 for (i = 0; i < 4; i++) {
3059 if (!pos_args[i].out[0])
3060 continue;
3061
3062 /* Specify the target we are exporting */
3063 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3064
3065 if (pos_idx == shader->info.nr_pos_exports)
3066 /* Specify that this is the last export */
3067 pos_args[i].done = 1;
3068
3069 ac_build_export(&ctx->ac, &pos_args[i]);
3070 }
3071
3072 /* Build parameter exports. */
3073 si_build_param_exports(ctx, outputs, noutput);
3074 }
3075
3076 /**
3077 * Forward all outputs from the vertex shader to the TES. This is only used
3078 * for the fixed function TCS.
3079 */
3080 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3081 {
3082 struct si_shader_context *ctx = si_shader_context(bld_base);
3083 LLVMValueRef invocation_id, buffer, buffer_offset;
3084 LLVMValueRef lds_vertex_stride, lds_base;
3085 uint64_t inputs;
3086
3087 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3088 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3089 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3090
3091 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3092 lds_base = get_tcs_in_current_patch_offset(ctx);
3093 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3094 lds_base);
3095
3096 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3097 while (inputs) {
3098 unsigned i = u_bit_scan64(&inputs);
3099
3100 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3101 LLVMConstInt(ctx->i32, 4 * i, 0),
3102 "");
3103
3104 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3105 get_rel_patch_id(ctx),
3106 invocation_id,
3107 LLVMConstInt(ctx->i32, i, 0));
3108
3109 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3110
3111 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3112 buffer_offset, 0, ac_glc, false);
3113 }
3114 }
3115
3116 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3117 LLVMValueRef rel_patch_id,
3118 LLVMValueRef invocation_id,
3119 LLVMValueRef tcs_out_current_patch_data_offset,
3120 LLVMValueRef invoc0_tf_outer[4],
3121 LLVMValueRef invoc0_tf_inner[2])
3122 {
3123 struct si_shader_context *ctx = si_shader_context(bld_base);
3124 struct si_shader *shader = ctx->shader;
3125 unsigned tess_inner_index, tess_outer_index;
3126 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3127 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3128 unsigned stride, outer_comps, inner_comps, i, offset;
3129
3130 /* Add a barrier before loading tess factors from LDS. */
3131 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3132 si_llvm_emit_barrier(NULL, bld_base, NULL);
3133
3134 /* Do this only for invocation 0, because the tess levels are per-patch,
3135 * not per-vertex.
3136 *
3137 * This can't jump, because invocation 0 executes this. It should
3138 * at least mask out the loads and stores for other invocations.
3139 */
3140 ac_build_ifcc(&ctx->ac,
3141 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3142 invocation_id, ctx->i32_0, ""), 6503);
3143
3144 /* Determine the layout of one tess factor element in the buffer. */
3145 switch (shader->key.part.tcs.epilog.prim_mode) {
3146 case PIPE_PRIM_LINES:
3147 stride = 2; /* 2 dwords, 1 vec2 store */
3148 outer_comps = 2;
3149 inner_comps = 0;
3150 break;
3151 case PIPE_PRIM_TRIANGLES:
3152 stride = 4; /* 4 dwords, 1 vec4 store */
3153 outer_comps = 3;
3154 inner_comps = 1;
3155 break;
3156 case PIPE_PRIM_QUADS:
3157 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3158 outer_comps = 4;
3159 inner_comps = 2;
3160 break;
3161 default:
3162 assert(0);
3163 return;
3164 }
3165
3166 for (i = 0; i < 4; i++) {
3167 inner[i] = LLVMGetUndef(ctx->i32);
3168 outer[i] = LLVMGetUndef(ctx->i32);
3169 }
3170
3171 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3172 /* Tess factors are in VGPRs. */
3173 for (i = 0; i < outer_comps; i++)
3174 outer[i] = out[i] = invoc0_tf_outer[i];
3175 for (i = 0; i < inner_comps; i++)
3176 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3177 } else {
3178 /* Load tess_inner and tess_outer from LDS.
3179 * Any invocation can write them, so we can't get them from a temporary.
3180 */
3181 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3182 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3183
3184 lds_base = tcs_out_current_patch_data_offset;
3185 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3186 LLVMConstInt(ctx->i32,
3187 tess_inner_index * 4, 0), "");
3188 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3189 LLVMConstInt(ctx->i32,
3190 tess_outer_index * 4, 0), "");
3191
3192 for (i = 0; i < outer_comps; i++) {
3193 outer[i] = out[i] =
3194 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3195 }
3196 for (i = 0; i < inner_comps; i++) {
3197 inner[i] = out[outer_comps+i] =
3198 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3199 }
3200 }
3201
3202 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3203 /* For isolines, the hardware expects tess factors in the
3204 * reverse order from what GLSL / TGSI specify.
3205 */
3206 LLVMValueRef tmp = out[0];
3207 out[0] = out[1];
3208 out[1] = tmp;
3209 }
3210
3211 /* Convert the outputs to vectors for stores. */
3212 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3213 vec1 = NULL;
3214
3215 if (stride > 4)
3216 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3217
3218 /* Get the buffer. */
3219 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3220
3221 /* Get the offset. */
3222 tf_base = LLVMGetParam(ctx->main_fn,
3223 ctx->param_tcs_factor_offset);
3224 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3225 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3226
3227 ac_build_ifcc(&ctx->ac,
3228 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3229 rel_patch_id, ctx->i32_0, ""), 6504);
3230
3231 /* Store the dynamic HS control word. */
3232 offset = 0;
3233 if (ctx->screen->info.chip_class <= GFX8) {
3234 ac_build_buffer_store_dword(&ctx->ac, buffer,
3235 LLVMConstInt(ctx->i32, 0x80000000, 0),
3236 1, ctx->i32_0, tf_base,
3237 offset, ac_glc, false);
3238 offset += 4;
3239 }
3240
3241 ac_build_endif(&ctx->ac, 6504);
3242
3243 /* Store the tessellation factors. */
3244 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3245 MIN2(stride, 4), byteoffset, tf_base,
3246 offset, ac_glc, false);
3247 offset += 16;
3248 if (vec1)
3249 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3250 stride - 4, byteoffset, tf_base,
3251 offset, ac_glc, false);
3252
3253 /* Store the tess factors into the offchip buffer if TES reads them. */
3254 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3255 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3256 LLVMValueRef tf_inner_offset;
3257 unsigned param_outer, param_inner;
3258
3259 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3260 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3261
3262 param_outer = si_shader_io_get_unique_index_patch(
3263 TGSI_SEMANTIC_TESSOUTER, 0);
3264 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3265 LLVMConstInt(ctx->i32, param_outer, 0));
3266
3267 unsigned outer_vec_size =
3268 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3269 outer_comps : util_next_power_of_two(outer_comps);
3270 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3271
3272 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3273 outer_comps, tf_outer_offset,
3274 base, 0, ac_glc, false);
3275 if (inner_comps) {
3276 param_inner = si_shader_io_get_unique_index_patch(
3277 TGSI_SEMANTIC_TESSINNER, 0);
3278 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3279 LLVMConstInt(ctx->i32, param_inner, 0));
3280
3281 inner_vec = inner_comps == 1 ? inner[0] :
3282 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3283 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3284 inner_comps, tf_inner_offset,
3285 base, 0, ac_glc, false);
3286 }
3287 }
3288
3289 ac_build_endif(&ctx->ac, 6503);
3290 }
3291
3292 static LLVMValueRef
3293 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3294 unsigned param, unsigned return_index)
3295 {
3296 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3297 LLVMGetParam(ctx->main_fn, param),
3298 return_index, "");
3299 }
3300
3301 static LLVMValueRef
3302 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3303 unsigned param, unsigned return_index)
3304 {
3305 LLVMBuilderRef builder = ctx->ac.builder;
3306 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3307
3308 return LLVMBuildInsertValue(builder, ret,
3309 ac_to_float(&ctx->ac, p),
3310 return_index, "");
3311 }
3312
3313 static LLVMValueRef
3314 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3315 unsigned param, unsigned return_index)
3316 {
3317 LLVMBuilderRef builder = ctx->ac.builder;
3318 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3319 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3320 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3321 }
3322
3323 /* This only writes the tessellation factor levels. */
3324 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3325 unsigned max_outputs,
3326 LLVMValueRef *addrs)
3327 {
3328 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3329 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3330 LLVMBuilderRef builder = ctx->ac.builder;
3331 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3332
3333 si_copy_tcs_inputs(bld_base);
3334
3335 rel_patch_id = get_rel_patch_id(ctx);
3336 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3337 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3338
3339 if (ctx->screen->info.chip_class >= GFX9) {
3340 LLVMBasicBlockRef blocks[2] = {
3341 LLVMGetInsertBlock(builder),
3342 ctx->merged_wrap_if_entry_block
3343 };
3344 LLVMValueRef values[2];
3345
3346 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3347
3348 values[0] = rel_patch_id;
3349 values[1] = LLVMGetUndef(ctx->i32);
3350 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3351
3352 values[0] = tf_lds_offset;
3353 values[1] = LLVMGetUndef(ctx->i32);
3354 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3355
3356 values[0] = invocation_id;
3357 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3358 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3359 }
3360
3361 /* Return epilog parameters from this function. */
3362 LLVMValueRef ret = ctx->return_value;
3363 unsigned vgpr;
3364
3365 if (ctx->screen->info.chip_class >= GFX9) {
3366 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3367 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3368 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3369 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3370 /* Tess offchip and tess factor offsets are at the beginning. */
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3372 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3373 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3374 } else {
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3376 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3377 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3378 GFX6_SGPR_TCS_OUT_LAYOUT);
3379 /* Tess offchip and tess factor offsets are after user SGPRs. */
3380 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3381 GFX6_TCS_NUM_USER_SGPR);
3382 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3383 GFX6_TCS_NUM_USER_SGPR + 1);
3384 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3385 }
3386
3387 /* VGPRs */
3388 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3389 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3390 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3391
3392 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3393 * the invocation_id output does not alias the tcs_rel_ids input,
3394 * which saves a V_MOV on gfx9.
3395 */
3396 vgpr += 2;
3397
3398 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3399 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3400
3401 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3402 vgpr++; /* skip the tess factor LDS offset */
3403 for (unsigned i = 0; i < 6; i++) {
3404 LLVMValueRef value =
3405 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3406 value = ac_to_float(&ctx->ac, value);
3407 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3408 }
3409 } else {
3410 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3411 }
3412 ctx->return_value = ret;
3413 }
3414
3415 /* Pass TCS inputs from LS to TCS on GFX9. */
3416 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3417 {
3418 LLVMValueRef ret = ctx->return_value;
3419
3420 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3421 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3422 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3423 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3424 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3425 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3426
3427 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3428 8 + SI_SGPR_RW_BUFFERS);
3429 ret = si_insert_input_ptr(ctx, ret,
3430 ctx->param_bindless_samplers_and_images,
3431 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3432
3433 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3434 8 + SI_SGPR_VS_STATE_BITS);
3435
3436 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3437 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3438 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3439 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3440 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3441 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3442
3443 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3444 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3445 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3446 vgpr++, "");
3447 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3448 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3449 vgpr++, "");
3450 ctx->return_value = ret;
3451 }
3452
3453 /* Pass GS inputs from ES to GS on GFX9. */
3454 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3455 {
3456 LLVMBuilderRef builder = ctx->ac.builder;
3457 LLVMValueRef ret = ctx->return_value;
3458
3459 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3460 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3461 if (ctx->shader->key.as_ngg)
3462 ret = LLVMBuildInsertValue(builder, ret, ctx->gs_tg_info, 2, "");
3463 else
3464 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3465 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3466 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3467
3468 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3469 8 + SI_SGPR_RW_BUFFERS);
3470 ret = si_insert_input_ptr(ctx, ret,
3471 ctx->param_bindless_samplers_and_images,
3472 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3473 if (ctx->screen->use_ngg) {
3474 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits,
3475 8 + SI_SGPR_VS_STATE_BITS);
3476 }
3477
3478 unsigned vgpr;
3479 if (ctx->type == PIPE_SHADER_VERTEX)
3480 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3481 else
3482 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3483
3484 for (unsigned i = 0; i < 5; i++) {
3485 unsigned param = ctx->param_gs_vtx01_offset + i;
3486 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3487 }
3488 ctx->return_value = ret;
3489 }
3490
3491 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3492 unsigned max_outputs,
3493 LLVMValueRef *addrs)
3494 {
3495 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3496 struct si_shader *shader = ctx->shader;
3497 struct tgsi_shader_info *info = &shader->selector->info;
3498 unsigned i, chan;
3499 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3500 ctx->param_rel_auto_id);
3501 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3502 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3503 vertex_dw_stride, "");
3504
3505 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3506 * its inputs from it. */
3507 for (i = 0; i < info->num_outputs; i++) {
3508 unsigned name = info->output_semantic_name[i];
3509 unsigned index = info->output_semantic_index[i];
3510
3511 /* The ARB_shader_viewport_layer_array spec contains the
3512 * following issue:
3513 *
3514 * 2) What happens if gl_ViewportIndex or gl_Layer is
3515 * written in the vertex shader and a geometry shader is
3516 * present?
3517 *
3518 * RESOLVED: The value written by the last vertex processing
3519 * stage is used. If the last vertex processing stage
3520 * (vertex, tessellation evaluation or geometry) does not
3521 * statically assign to gl_ViewportIndex or gl_Layer, index
3522 * or layer zero is assumed.
3523 *
3524 * So writes to those outputs in VS-as-LS are simply ignored.
3525 */
3526 if (name == TGSI_SEMANTIC_LAYER ||
3527 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3528 continue;
3529
3530 int param = si_shader_io_get_unique_index(name, index, false);
3531 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3532 LLVMConstInt(ctx->i32, param * 4, 0), "");
3533
3534 for (chan = 0; chan < 4; chan++) {
3535 if (!(info->output_usagemask[i] & (1 << chan)))
3536 continue;
3537
3538 lshs_lds_store(ctx, chan, dw_addr,
3539 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3540 }
3541 }
3542
3543 if (ctx->screen->info.chip_class >= GFX9)
3544 si_set_ls_return_value_for_tcs(ctx);
3545 }
3546
3547 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3548 unsigned max_outputs,
3549 LLVMValueRef *addrs)
3550 {
3551 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3552 struct si_shader *es = ctx->shader;
3553 struct tgsi_shader_info *info = &es->selector->info;
3554 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3555 ctx->param_es2gs_offset);
3556 LLVMValueRef lds_base = NULL;
3557 unsigned chan;
3558 int i;
3559
3560 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3561 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3562 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3563 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3564 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3565 LLVMBuildMul(ctx->ac.builder, wave_idx,
3566 LLVMConstInt(ctx->i32, ctx->ac.wave_size, false), ""), "");
3567 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3568 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3569 }
3570
3571 for (i = 0; i < info->num_outputs; i++) {
3572 int param;
3573
3574 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3575 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3576 continue;
3577
3578 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3579 info->output_semantic_index[i], false);
3580
3581 for (chan = 0; chan < 4; chan++) {
3582 if (!(info->output_usagemask[i] & (1 << chan)))
3583 continue;
3584
3585 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3586 out_val = ac_to_integer(&ctx->ac, out_val);
3587
3588 /* GFX9 has the ESGS ring in LDS. */
3589 if (ctx->screen->info.chip_class >= GFX9) {
3590 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
3591 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
3592 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
3593 continue;
3594 }
3595
3596 ac_build_buffer_store_dword(&ctx->ac,
3597 ctx->esgs_ring,
3598 out_val, 1, NULL, soffset,
3599 (4 * param + chan) * 4,
3600 ac_glc | ac_slc, true);
3601 }
3602 }
3603
3604 if (ctx->screen->info.chip_class >= GFX9)
3605 si_set_es_return_value_for_gs(ctx);
3606 }
3607
3608 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3609 {
3610 if (ctx->screen->info.chip_class >= GFX9)
3611 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3612 else
3613 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3614 }
3615
3616 static void emit_gs_epilogue(struct si_shader_context *ctx)
3617 {
3618 if (ctx->shader->key.as_ngg) {
3619 gfx10_ngg_gs_emit_epilogue(ctx);
3620 return;
3621 }
3622
3623 if (ctx->screen->info.chip_class >= GFX10)
3624 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3625
3626 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3627 si_get_gs_wave_id(ctx));
3628
3629 if (ctx->screen->info.chip_class >= GFX9)
3630 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3631 }
3632
3633 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3634 unsigned max_outputs,
3635 LLVMValueRef *addrs)
3636 {
3637 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3638 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3639
3640 assert(info->num_outputs <= max_outputs);
3641
3642 emit_gs_epilogue(ctx);
3643 }
3644
3645 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3646 {
3647 struct si_shader_context *ctx = si_shader_context(bld_base);
3648 emit_gs_epilogue(ctx);
3649 }
3650
3651 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3652 unsigned max_outputs,
3653 LLVMValueRef *addrs)
3654 {
3655 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3656 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3657 struct si_shader_output_values *outputs = NULL;
3658 int i,j;
3659
3660 assert(!ctx->shader->is_gs_copy_shader);
3661 assert(info->num_outputs <= max_outputs);
3662
3663 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3664
3665 for (i = 0; i < info->num_outputs; i++) {
3666 outputs[i].semantic_name = info->output_semantic_name[i];
3667 outputs[i].semantic_index = info->output_semantic_index[i];
3668
3669 for (j = 0; j < 4; j++) {
3670 outputs[i].values[j] =
3671 LLVMBuildLoad(ctx->ac.builder,
3672 addrs[4 * i + j],
3673 "");
3674 outputs[i].vertex_stream[j] =
3675 (info->output_streams[i] >> (2 * j)) & 3;
3676 }
3677 }
3678
3679 if (!ctx->screen->use_ngg_streamout &&
3680 ctx->shader->selector->so.num_outputs)
3681 si_llvm_emit_streamout(ctx, outputs, i, 0);
3682
3683 /* Export PrimitiveID. */
3684 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3685 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3686 outputs[i].semantic_index = 0;
3687 outputs[i].values[0] = ac_to_float(&ctx->ac, si_get_primitive_id(ctx, 0));
3688 for (j = 1; j < 4; j++)
3689 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3690
3691 memset(outputs[i].vertex_stream, 0,
3692 sizeof(outputs[i].vertex_stream));
3693 i++;
3694 }
3695
3696 si_llvm_export_vs(ctx, outputs, i);
3697 FREE(outputs);
3698 }
3699
3700 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3701 unsigned max_outputs,
3702 LLVMValueRef *addrs)
3703 {
3704 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3705 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3706 LLVMValueRef pos[4] = {};
3707
3708 assert(info->num_outputs <= max_outputs);
3709
3710 for (unsigned i = 0; i < info->num_outputs; i++) {
3711 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3712 continue;
3713
3714 for (unsigned chan = 0; chan < 4; chan++)
3715 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3716 break;
3717 }
3718 assert(pos[0] != NULL);
3719
3720 /* Return the position output. */
3721 LLVMValueRef ret = ctx->return_value;
3722 for (unsigned chan = 0; chan < 4; chan++)
3723 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3724 ctx->return_value = ret;
3725 }
3726
3727 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3728 {
3729 struct si_shader_context *ctx = si_shader_context(bld_base);
3730
3731 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3732 &ctx->outputs[0][0]);
3733 }
3734
3735 struct si_ps_exports {
3736 unsigned num;
3737 struct ac_export_args args[10];
3738 };
3739
3740 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3741 LLVMValueRef depth, LLVMValueRef stencil,
3742 LLVMValueRef samplemask, struct si_ps_exports *exp)
3743 {
3744 struct si_shader_context *ctx = si_shader_context(bld_base);
3745 struct ac_export_args args;
3746
3747 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3748
3749 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3750 }
3751
3752 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3753 LLVMValueRef *color, unsigned index,
3754 unsigned samplemask_param,
3755 bool is_last, struct si_ps_exports *exp)
3756 {
3757 struct si_shader_context *ctx = si_shader_context(bld_base);
3758 int i;
3759
3760 /* Clamp color */
3761 if (ctx->shader->key.part.ps.epilog.clamp_color)
3762 for (i = 0; i < 4; i++)
3763 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3764
3765 /* Alpha to one */
3766 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3767 color[3] = ctx->ac.f32_1;
3768
3769 /* Alpha test */
3770 if (index == 0 &&
3771 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3772 si_alpha_test(bld_base, color[3]);
3773
3774 /* Line & polygon smoothing */
3775 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3776 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3777 samplemask_param);
3778
3779 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3780 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3781 struct ac_export_args args[8];
3782 int c, last = -1;
3783
3784 /* Get the export arguments, also find out what the last one is. */
3785 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3786 si_llvm_init_export_args(ctx, color,
3787 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3788 if (args[c].enabled_channels)
3789 last = c;
3790 }
3791
3792 /* Emit all exports. */
3793 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3794 if (is_last && last == c) {
3795 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3796 args[c].done = 1; /* DONE bit */
3797 } else if (!args[c].enabled_channels)
3798 continue; /* unnecessary NULL export */
3799
3800 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3801 }
3802 } else {
3803 struct ac_export_args args;
3804
3805 /* Export */
3806 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3807 &args);
3808 if (is_last) {
3809 args.valid_mask = 1; /* whether the EXEC mask is valid */
3810 args.done = 1; /* DONE bit */
3811 } else if (!args.enabled_channels)
3812 return; /* unnecessary NULL export */
3813
3814 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3815 }
3816 }
3817
3818 static void si_emit_ps_exports(struct si_shader_context *ctx,
3819 struct si_ps_exports *exp)
3820 {
3821 for (unsigned i = 0; i < exp->num; i++)
3822 ac_build_export(&ctx->ac, &exp->args[i]);
3823 }
3824
3825 /**
3826 * Return PS outputs in this order:
3827 *
3828 * v[0:3] = color0.xyzw
3829 * v[4:7] = color1.xyzw
3830 * ...
3831 * vN+0 = Depth
3832 * vN+1 = Stencil
3833 * vN+2 = SampleMask
3834 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3835 *
3836 * The alpha-ref SGPR is returned via its original location.
3837 */
3838 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3839 unsigned max_outputs,
3840 LLVMValueRef *addrs)
3841 {
3842 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3843 struct si_shader *shader = ctx->shader;
3844 struct tgsi_shader_info *info = &shader->selector->info;
3845 LLVMBuilderRef builder = ctx->ac.builder;
3846 unsigned i, j, first_vgpr, vgpr;
3847
3848 LLVMValueRef color[8][4] = {};
3849 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3850 LLVMValueRef ret;
3851
3852 if (ctx->postponed_kill)
3853 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3854
3855 /* Read the output values. */
3856 for (i = 0; i < info->num_outputs; i++) {
3857 unsigned semantic_name = info->output_semantic_name[i];
3858 unsigned semantic_index = info->output_semantic_index[i];
3859
3860 switch (semantic_name) {
3861 case TGSI_SEMANTIC_COLOR:
3862 assert(semantic_index < 8);
3863 for (j = 0; j < 4; j++) {
3864 LLVMValueRef ptr = addrs[4 * i + j];
3865 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3866 color[semantic_index][j] = result;
3867 }
3868 break;
3869 case TGSI_SEMANTIC_POSITION:
3870 depth = LLVMBuildLoad(builder,
3871 addrs[4 * i + 2], "");
3872 break;
3873 case TGSI_SEMANTIC_STENCIL:
3874 stencil = LLVMBuildLoad(builder,
3875 addrs[4 * i + 1], "");
3876 break;
3877 case TGSI_SEMANTIC_SAMPLEMASK:
3878 samplemask = LLVMBuildLoad(builder,
3879 addrs[4 * i + 0], "");
3880 break;
3881 default:
3882 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3883 semantic_name);
3884 }
3885 }
3886
3887 /* Fill the return structure. */
3888 ret = ctx->return_value;
3889
3890 /* Set SGPRs. */
3891 ret = LLVMBuildInsertValue(builder, ret,
3892 ac_to_integer(&ctx->ac,
3893 LLVMGetParam(ctx->main_fn,
3894 SI_PARAM_ALPHA_REF)),
3895 SI_SGPR_ALPHA_REF, "");
3896
3897 /* Set VGPRs */
3898 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3899 for (i = 0; i < ARRAY_SIZE(color); i++) {
3900 if (!color[i][0])
3901 continue;
3902
3903 for (j = 0; j < 4; j++)
3904 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3905 }
3906 if (depth)
3907 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3908 if (stencil)
3909 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3910 if (samplemask)
3911 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3912
3913 /* Add the input sample mask for smoothing at the end. */
3914 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3915 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3916 ret = LLVMBuildInsertValue(builder, ret,
3917 LLVMGetParam(ctx->main_fn,
3918 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3919
3920 ctx->return_value = ret;
3921 }
3922
3923 static void membar_emit(
3924 const struct lp_build_tgsi_action *action,
3925 struct lp_build_tgsi_context *bld_base,
3926 struct lp_build_emit_data *emit_data)
3927 {
3928 struct si_shader_context *ctx = si_shader_context(bld_base);
3929 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3930 unsigned flags = LLVMConstIntGetZExtValue(src0);
3931 unsigned wait_flags = 0;
3932
3933 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3934 wait_flags |= AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3935
3936 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3937 TGSI_MEMBAR_SHADER_BUFFER |
3938 TGSI_MEMBAR_SHADER_IMAGE))
3939 wait_flags |= AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3940
3941 if (flags & TGSI_MEMBAR_SHARED)
3942 wait_flags |= AC_WAIT_LGKM;
3943
3944 ac_build_waitcnt(&ctx->ac, wait_flags);
3945 }
3946
3947 static void clock_emit(
3948 const struct lp_build_tgsi_action *action,
3949 struct lp_build_tgsi_context *bld_base,
3950 struct lp_build_emit_data *emit_data)
3951 {
3952 struct si_shader_context *ctx = si_shader_context(bld_base);
3953 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3954
3955 emit_data->output[0] =
3956 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3957 emit_data->output[1] =
3958 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3959 }
3960
3961 static void si_llvm_emit_ddxy(
3962 const struct lp_build_tgsi_action *action,
3963 struct lp_build_tgsi_context *bld_base,
3964 struct lp_build_emit_data *emit_data)
3965 {
3966 struct si_shader_context *ctx = si_shader_context(bld_base);
3967 unsigned opcode = emit_data->info->opcode;
3968 LLVMValueRef val;
3969 int idx;
3970 unsigned mask;
3971
3972 if (opcode == TGSI_OPCODE_DDX_FINE)
3973 mask = AC_TID_MASK_LEFT;
3974 else if (opcode == TGSI_OPCODE_DDY_FINE)
3975 mask = AC_TID_MASK_TOP;
3976 else
3977 mask = AC_TID_MASK_TOP_LEFT;
3978
3979 /* for DDX we want to next X pixel, DDY next Y pixel. */
3980 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3981
3982 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3983 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3984 emit_data->output[emit_data->chan] = val;
3985 }
3986
3987 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3988 struct lp_build_tgsi_context *bld_base,
3989 struct lp_build_emit_data *emit_data)
3990 {
3991 struct si_shader_context *ctx = si_shader_context(bld_base);
3992 struct si_shader *shader = ctx->shader;
3993 const struct tgsi_shader_info *info = &shader->selector->info;
3994 LLVMValueRef interp_param;
3995 const struct tgsi_full_instruction *inst = emit_data->inst;
3996 const struct tgsi_full_src_register *input = &inst->Src[0];
3997 int input_base, input_array_size;
3998 int chan;
3999 int i;
4000 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4001 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
4002 int interp_param_idx;
4003 unsigned interp;
4004 unsigned location;
4005
4006 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4007 /* offset is in second src, first two channels */
4008 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4009 TGSI_CHAN_X);
4010 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4011 TGSI_CHAN_Y);
4012 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4013 LLVMValueRef sample_position;
4014 LLVMValueRef sample_id;
4015 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4016
4017 /* fetch sample ID, then fetch its sample position,
4018 * and place into first two channels.
4019 */
4020 sample_id = lp_build_emit_fetch(bld_base,
4021 emit_data->inst, 1, TGSI_CHAN_X);
4022 sample_id = ac_to_integer(&ctx->ac, sample_id);
4023
4024 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4025 * Language 4.50 spec says about interpolateAtSample:
4026 *
4027 * "Returns the value of the input interpolant variable at
4028 * the location of sample number sample. If multisample
4029 * buffers are not available, the input variable will be
4030 * evaluated at the center of the pixel. If sample sample
4031 * does not exist, the position used to interpolate the
4032 * input variable is undefined."
4033 *
4034 * This means that sample_id values outside of the valid are
4035 * in fact valid input, and the usual mechanism for loading the
4036 * sample position doesn't work.
4037 */
4038 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4039 LLVMValueRef center[4] = {
4040 LLVMConstReal(ctx->f32, 0.5),
4041 LLVMConstReal(ctx->f32, 0.5),
4042 ctx->ac.f32_0,
4043 ctx->ac.f32_0,
4044 };
4045
4046 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4047 } else {
4048 sample_position = load_sample_position(&ctx->abi, sample_id);
4049 }
4050
4051 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4052 ctx->i32_0, "");
4053
4054 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4055 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4056 ctx->i32_1, "");
4057 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4058 }
4059
4060 assert(input->Register.File == TGSI_FILE_INPUT);
4061
4062 if (input->Register.Indirect) {
4063 unsigned array_id = input->Indirect.ArrayID;
4064
4065 if (array_id) {
4066 input_base = info->input_array_first[array_id];
4067 input_array_size = info->input_array_last[array_id] - input_base + 1;
4068 } else {
4069 input_base = inst->Src[0].Register.Index;
4070 input_array_size = info->num_inputs - input_base;
4071 }
4072
4073 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4074 1, input->Register.Index - input_base);
4075 } else {
4076 input_base = inst->Src[0].Register.Index;
4077 input_array_size = 1;
4078 array_idx = ctx->i32_0;
4079 }
4080
4081 interp = shader->selector->info.input_interpolate[input_base];
4082
4083 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4084 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4085 location = TGSI_INTERPOLATE_LOC_CENTER;
4086 else
4087 location = TGSI_INTERPOLATE_LOC_CENTROID;
4088
4089 interp_param_idx = lookup_interp_param_index(interp, location);
4090 if (interp_param_idx == -1)
4091 return;
4092 else if (interp_param_idx)
4093 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4094 else
4095 interp_param = NULL;
4096
4097 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4098 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4099 LLVMValueRef ij_out[2];
4100 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4101
4102 /*
4103 * take the I then J parameters, and the DDX/Y for it, and
4104 * calculate the IJ inputs for the interpolator.
4105 * temp1 = ddx * offset/sample.x + I;
4106 * interp_param.I = ddy * offset/sample.y + temp1;
4107 * temp1 = ddx * offset/sample.x + J;
4108 * interp_param.J = ddy * offset/sample.y + temp1;
4109 */
4110 for (i = 0; i < 2; i++) {
4111 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4112 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4113 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4114 ddxy_out, ix_ll, "");
4115 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4116 ddxy_out, iy_ll, "");
4117 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4118 interp_param, ix_ll, "");
4119 LLVMValueRef temp;
4120
4121 interp_el = ac_to_float(&ctx->ac, interp_el);
4122
4123 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4124 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4125 }
4126 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4127 }
4128
4129 if (interp_param)
4130 interp_param = ac_to_float(&ctx->ac, interp_param);
4131
4132 for (chan = 0; chan < 4; chan++) {
4133 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4134 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4135
4136 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4137 LLVMValueRef v, i = NULL, j = NULL;
4138
4139 if (interp_param) {
4140 i = LLVMBuildExtractElement(
4141 ctx->ac.builder, interp_param, ctx->i32_0, "");
4142 j = LLVMBuildExtractElement(
4143 ctx->ac.builder, interp_param, ctx->i32_1, "");
4144 }
4145 v = si_build_fs_interp(ctx, input_base + idx, schan,
4146 prim_mask, i, j);
4147
4148 gather = LLVMBuildInsertElement(ctx->ac.builder,
4149 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4150 }
4151
4152 emit_data->output[chan] = LLVMBuildExtractElement(
4153 ctx->ac.builder, gather, array_idx, "");
4154 }
4155 }
4156
4157 static void vote_all_emit(
4158 const struct lp_build_tgsi_action *action,
4159 struct lp_build_tgsi_context *bld_base,
4160 struct lp_build_emit_data *emit_data)
4161 {
4162 struct si_shader_context *ctx = si_shader_context(bld_base);
4163
4164 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4165 emit_data->output[emit_data->chan] =
4166 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4167 }
4168
4169 static void vote_any_emit(
4170 const struct lp_build_tgsi_action *action,
4171 struct lp_build_tgsi_context *bld_base,
4172 struct lp_build_emit_data *emit_data)
4173 {
4174 struct si_shader_context *ctx = si_shader_context(bld_base);
4175
4176 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4177 emit_data->output[emit_data->chan] =
4178 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4179 }
4180
4181 static void vote_eq_emit(
4182 const struct lp_build_tgsi_action *action,
4183 struct lp_build_tgsi_context *bld_base,
4184 struct lp_build_emit_data *emit_data)
4185 {
4186 struct si_shader_context *ctx = si_shader_context(bld_base);
4187
4188 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4189 emit_data->output[emit_data->chan] =
4190 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4191 }
4192
4193 static void ballot_emit(
4194 const struct lp_build_tgsi_action *action,
4195 struct lp_build_tgsi_context *bld_base,
4196 struct lp_build_emit_data *emit_data)
4197 {
4198 struct si_shader_context *ctx = si_shader_context(bld_base);
4199 LLVMBuilderRef builder = ctx->ac.builder;
4200 LLVMValueRef tmp;
4201
4202 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4203 tmp = ac_build_ballot(&ctx->ac, tmp);
4204
4205 emit_data->output[0] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4206
4207 if (ctx->ac.wave_size == 32) {
4208 emit_data->output[1] = ctx->i32_0;
4209 } else {
4210 tmp = LLVMBuildLShr(builder, tmp, LLVMConstInt(ctx->i64, 32, 0), "");
4211 emit_data->output[1] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4212 }
4213 }
4214
4215 static void read_lane_emit(
4216 const struct lp_build_tgsi_action *action,
4217 struct lp_build_tgsi_context *bld_base,
4218 struct lp_build_emit_data *emit_data)
4219 {
4220 struct si_shader_context *ctx = si_shader_context(bld_base);
4221
4222 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4223 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4224 0, emit_data->src_chan);
4225
4226 /* Always read the source invocation (= lane) from the X channel. */
4227 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4228 1, TGSI_CHAN_X);
4229 emit_data->arg_count = 2;
4230 }
4231
4232 /* We currently have no other way to prevent LLVM from lifting the icmp
4233 * calls to a dominating basic block.
4234 */
4235 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4236
4237 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4238 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4239
4240 emit_data->output[emit_data->chan] =
4241 ac_build_intrinsic(&ctx->ac, action->intr_name,
4242 ctx->i32, emit_data->args, emit_data->arg_count,
4243 AC_FUNC_ATTR_READNONE |
4244 AC_FUNC_ATTR_CONVERGENT);
4245 }
4246
4247 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4248 struct lp_build_emit_data *emit_data)
4249 {
4250 struct si_shader_context *ctx = si_shader_context(bld_base);
4251 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4252 LLVMValueRef imm;
4253 unsigned stream;
4254
4255 assert(src0.File == TGSI_FILE_IMMEDIATE);
4256
4257 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4258 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4259 return stream;
4260 }
4261
4262 /* Emit one vertex from the geometry shader */
4263 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4264 unsigned stream,
4265 LLVMValueRef *addrs)
4266 {
4267 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4268
4269 if (ctx->shader->key.as_ngg) {
4270 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
4271 return;
4272 }
4273
4274 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4275 struct si_shader *shader = ctx->shader;
4276 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4277 ctx->param_gs2vs_offset);
4278 LLVMValueRef gs_next_vertex;
4279 LLVMValueRef can_emit;
4280 unsigned chan, offset;
4281 int i;
4282
4283 /* Write vertex attribute values to GSVS ring */
4284 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4285 ctx->gs_next_vertex[stream],
4286 "");
4287
4288 /* If this thread has already emitted the declared maximum number of
4289 * vertices, skip the write: excessive vertex emissions are not
4290 * supposed to have any effect.
4291 *
4292 * If the shader has no writes to memory, kill it instead. This skips
4293 * further memory loads and may allow LLVM to skip to the end
4294 * altogether.
4295 */
4296 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4297 LLVMConstInt(ctx->i32,
4298 shader->selector->gs_max_out_vertices, 0), "");
4299
4300 bool use_kill = !info->writes_memory;
4301 if (use_kill) {
4302 ac_build_kill_if_false(&ctx->ac, can_emit);
4303 } else {
4304 ac_build_ifcc(&ctx->ac, can_emit, 6505);
4305 }
4306
4307 offset = 0;
4308 for (i = 0; i < info->num_outputs; i++) {
4309 for (chan = 0; chan < 4; chan++) {
4310 if (!(info->output_usagemask[i] & (1 << chan)) ||
4311 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4312 continue;
4313
4314 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4315 LLVMValueRef voffset =
4316 LLVMConstInt(ctx->i32, offset *
4317 shader->selector->gs_max_out_vertices, 0);
4318 offset++;
4319
4320 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4321 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4322 LLVMConstInt(ctx->i32, 4, 0), "");
4323
4324 out_val = ac_to_integer(&ctx->ac, out_val);
4325
4326 ac_build_buffer_store_dword(&ctx->ac,
4327 ctx->gsvs_ring[stream],
4328 out_val, 1,
4329 voffset, soffset, 0,
4330 ac_glc | ac_slc, true);
4331 }
4332 }
4333
4334 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4335 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4336
4337 /* Signal vertex emission if vertex data was written. */
4338 if (offset) {
4339 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4340 si_get_gs_wave_id(ctx));
4341 }
4342
4343 if (!use_kill)
4344 ac_build_endif(&ctx->ac, 6505);
4345 }
4346
4347 /* Emit one vertex from the geometry shader */
4348 static void si_tgsi_emit_vertex(
4349 const struct lp_build_tgsi_action *action,
4350 struct lp_build_tgsi_context *bld_base,
4351 struct lp_build_emit_data *emit_data)
4352 {
4353 struct si_shader_context *ctx = si_shader_context(bld_base);
4354 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4355
4356 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4357 }
4358
4359 /* Cut one primitive from the geometry shader */
4360 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4361 unsigned stream)
4362 {
4363 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4364
4365 if (ctx->shader->key.as_ngg) {
4366 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
4367 return;
4368 }
4369
4370 /* Signal primitive cut */
4371 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4372 si_get_gs_wave_id(ctx));
4373 }
4374
4375 /* Cut one primitive from the geometry shader */
4376 static void si_tgsi_emit_primitive(
4377 const struct lp_build_tgsi_action *action,
4378 struct lp_build_tgsi_context *bld_base,
4379 struct lp_build_emit_data *emit_data)
4380 {
4381 struct si_shader_context *ctx = si_shader_context(bld_base);
4382
4383 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4384 }
4385
4386 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4387 struct lp_build_tgsi_context *bld_base,
4388 struct lp_build_emit_data *emit_data)
4389 {
4390 struct si_shader_context *ctx = si_shader_context(bld_base);
4391
4392 /* GFX6 only (thanks to a hw bug workaround):
4393 * The real barrier instruction isn’t needed, because an entire patch
4394 * always fits into a single wave.
4395 */
4396 if (ctx->screen->info.chip_class == GFX6 &&
4397 ctx->type == PIPE_SHADER_TESS_CTRL) {
4398 ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE);
4399 return;
4400 }
4401
4402 ac_build_s_barrier(&ctx->ac);
4403 }
4404
4405 void si_create_function(struct si_shader_context *ctx,
4406 const char *name,
4407 LLVMTypeRef *returns, unsigned num_returns,
4408 struct si_function_info *fninfo,
4409 unsigned max_workgroup_size)
4410 {
4411 int i;
4412
4413 si_llvm_create_func(ctx, name, returns, num_returns,
4414 fninfo->types, fninfo->num_params);
4415 ctx->return_value = LLVMGetUndef(ctx->return_type);
4416
4417 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4418 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4419
4420 /* The combination of:
4421 * - noalias
4422 * - dereferenceable
4423 * - invariant.load
4424 * allows the optimization passes to move loads and reduces
4425 * SGPR spilling significantly.
4426 */
4427 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4428 AC_FUNC_ATTR_INREG);
4429
4430 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4431 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4432 AC_FUNC_ATTR_NOALIAS);
4433 ac_add_attr_dereferenceable(P, UINT64_MAX);
4434 }
4435 }
4436
4437 for (i = 0; i < fninfo->num_params; ++i) {
4438 if (fninfo->assign[i])
4439 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4440 }
4441
4442 if (ctx->screen->info.address32_hi) {
4443 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4444 "amdgpu-32bit-address-high-bits",
4445 ctx->screen->info.address32_hi);
4446 }
4447
4448 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4449
4450 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4451 "no-signed-zeros-fp-math",
4452 "true");
4453 }
4454
4455 static void declare_streamout_params(struct si_shader_context *ctx,
4456 struct pipe_stream_output_info *so,
4457 struct si_function_info *fninfo)
4458 {
4459 if (ctx->screen->use_ngg_streamout)
4460 return;
4461
4462 /* Streamout SGPRs. */
4463 if (so->num_outputs) {
4464 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4465 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4466 else
4467 ctx->param_streamout_config = fninfo->num_params - 1;
4468
4469 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4470 }
4471 /* A streamout buffer offset is loaded if the stride is non-zero. */
4472 for (int i = 0; i < 4; i++) {
4473 if (!so->stride[i])
4474 continue;
4475
4476 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4477 }
4478 }
4479
4480 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4481 {
4482 switch (shader->selector->type) {
4483 case PIPE_SHADER_VERTEX:
4484 case PIPE_SHADER_TESS_EVAL:
4485 return shader->key.as_ngg ? 128 : 0;
4486
4487 case PIPE_SHADER_TESS_CTRL:
4488 /* Return this so that LLVM doesn't remove s_barrier
4489 * instructions on chips where we use s_barrier. */
4490 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 0;
4491
4492 case PIPE_SHADER_GEOMETRY:
4493 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 0;
4494
4495 case PIPE_SHADER_COMPUTE:
4496 break; /* see below */
4497
4498 default:
4499 return 0;
4500 }
4501
4502 const unsigned *properties = shader->selector->info.properties;
4503 unsigned max_work_group_size =
4504 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4505 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4506 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4507
4508 if (!max_work_group_size) {
4509 /* This is a variable group size compute shader,
4510 * compile it for the maximum possible group size.
4511 */
4512 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4513 }
4514 return max_work_group_size;
4515 }
4516
4517 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4518 struct si_function_info *fninfo,
4519 bool assign_params)
4520 {
4521 LLVMTypeRef const_shader_buf_type;
4522
4523 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4524 ctx->shader->selector->info.shader_buffers_declared == 0)
4525 const_shader_buf_type = ctx->f32;
4526 else
4527 const_shader_buf_type = ctx->v4i32;
4528
4529 unsigned const_and_shader_buffers =
4530 add_arg(fninfo, ARG_SGPR,
4531 ac_array_in_const32_addr_space(const_shader_buf_type));
4532
4533 if (assign_params)
4534 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4535 }
4536
4537 static void declare_samplers_and_images(struct si_shader_context *ctx,
4538 struct si_function_info *fninfo,
4539 bool assign_params)
4540 {
4541 unsigned samplers_and_images =
4542 add_arg(fninfo, ARG_SGPR,
4543 ac_array_in_const32_addr_space(ctx->v8i32));
4544
4545 if (assign_params)
4546 ctx->param_samplers_and_images = samplers_and_images;
4547 }
4548
4549 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4550 struct si_function_info *fninfo,
4551 bool assign_params)
4552 {
4553 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4554 declare_samplers_and_images(ctx, fninfo, assign_params);
4555 }
4556
4557 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4558 struct si_function_info *fninfo)
4559 {
4560 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4561 ac_array_in_const32_addr_space(ctx->v4i32));
4562 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4563 ac_array_in_const32_addr_space(ctx->v8i32));
4564 }
4565
4566 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4567 struct si_function_info *fninfo)
4568 {
4569 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4570 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4571 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4572 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4573 }
4574
4575 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4576 struct si_function_info *fninfo,
4577 unsigned *num_prolog_vgprs)
4578 {
4579 struct si_shader *shader = ctx->shader;
4580
4581 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4582 if (shader->key.as_ls) {
4583 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4584 if (ctx->screen->info.chip_class >= GFX10) {
4585 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user VGPR */
4586 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4587 } else {
4588 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4589 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4590 }
4591 } else if (ctx->screen->info.chip_class >= GFX10) {
4592 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr */
4593 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr or PrimID (legacy) */
4594 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4595 } else {
4596 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4597 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4598 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4599 }
4600
4601 if (!shader->is_gs_copy_shader) {
4602 /* Vertex load indices. */
4603 ctx->param_vertex_index0 = fninfo->num_params;
4604 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4605 add_arg(fninfo, ARG_VGPR, ctx->i32);
4606 *num_prolog_vgprs += shader->selector->info.num_inputs;
4607 }
4608 }
4609
4610 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4611 struct si_function_info *fninfo,
4612 unsigned vs_blit_property)
4613 {
4614 ctx->param_vs_blit_inputs = fninfo->num_params;
4615 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4616 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4617 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4618
4619 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4620 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4621 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4622 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4623 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4624 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4625 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4626 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4627 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4628 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4629 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4630 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4631 }
4632 }
4633
4634 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4635 struct si_function_info *fninfo)
4636 {
4637 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4638 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4639 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4640 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4641 }
4642
4643 enum {
4644 /* Convenient merged shader definitions. */
4645 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4646 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4647 };
4648
4649 static void create_function(struct si_shader_context *ctx)
4650 {
4651 struct si_shader *shader = ctx->shader;
4652 struct si_function_info fninfo;
4653 LLVMTypeRef returns[16+32*4];
4654 unsigned i, num_return_sgprs;
4655 unsigned num_returns = 0;
4656 unsigned num_prolog_vgprs = 0;
4657 unsigned type = ctx->type;
4658 unsigned vs_blit_property =
4659 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
4660
4661 si_init_function_info(&fninfo);
4662
4663 /* Set MERGED shaders. */
4664 if (ctx->screen->info.chip_class >= GFX9) {
4665 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4666 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4667 else if (shader->key.as_es || shader->key.as_ngg || type == PIPE_SHADER_GEOMETRY)
4668 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4669 }
4670
4671 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4672
4673 switch (type) {
4674 case PIPE_SHADER_VERTEX:
4675 declare_global_desc_pointers(ctx, &fninfo);
4676
4677 if (vs_blit_property) {
4678 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4679
4680 /* VGPRs */
4681 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4682 break;
4683 }
4684
4685 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4686 declare_vs_specific_input_sgprs(ctx, &fninfo);
4687 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4688 ac_array_in_const32_addr_space(ctx->v4i32));
4689
4690 if (shader->key.as_es) {
4691 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4692 } else if (shader->key.as_ls) {
4693 /* no extra parameters */
4694 } else {
4695 if (shader->is_gs_copy_shader) {
4696 fninfo.num_params = ctx->param_vs_state_bits + 1;
4697 fninfo.num_sgpr_params = fninfo.num_params;
4698 }
4699
4700 /* The locations of the other parameters are assigned dynamically. */
4701 declare_streamout_params(ctx, &shader->selector->so,
4702 &fninfo);
4703 }
4704
4705 /* VGPRs */
4706 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4707
4708 /* Return values */
4709 if (shader->key.opt.vs_as_prim_discard_cs) {
4710 for (i = 0; i < 4; i++)
4711 returns[num_returns++] = ctx->f32; /* VGPRs */
4712 }
4713 break;
4714
4715 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4716 declare_global_desc_pointers(ctx, &fninfo);
4717 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4718 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4719 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4720 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4722 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724
4725 /* VGPRs */
4726 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4727 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4728
4729 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4730 * placed after the user SGPRs.
4731 */
4732 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4733 returns[num_returns++] = ctx->i32; /* SGPRs */
4734 for (i = 0; i < 11; i++)
4735 returns[num_returns++] = ctx->f32; /* VGPRs */
4736 break;
4737
4738 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4739 /* Merged stages have 8 system SGPRs at the beginning. */
4740 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4741 declare_per_stage_desc_pointers(ctx, &fninfo,
4742 ctx->type == PIPE_SHADER_TESS_CTRL);
4743 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4745 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4746 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4747 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4748 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4749
4750 declare_global_desc_pointers(ctx, &fninfo);
4751 declare_per_stage_desc_pointers(ctx, &fninfo,
4752 ctx->type == PIPE_SHADER_VERTEX);
4753 declare_vs_specific_input_sgprs(ctx, &fninfo);
4754
4755 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4756 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4757 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4758 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4759 ac_array_in_const32_addr_space(ctx->v4i32));
4760
4761 /* VGPRs (first TCS, then VS) */
4762 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4763 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4764
4765 if (ctx->type == PIPE_SHADER_VERTEX) {
4766 declare_vs_input_vgprs(ctx, &fninfo,
4767 &num_prolog_vgprs);
4768
4769 /* LS return values are inputs to the TCS main shader part. */
4770 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4771 returns[num_returns++] = ctx->i32; /* SGPRs */
4772 for (i = 0; i < 2; i++)
4773 returns[num_returns++] = ctx->f32; /* VGPRs */
4774 } else {
4775 /* TCS return values are inputs to the TCS epilog.
4776 *
4777 * param_tcs_offchip_offset, param_tcs_factor_offset,
4778 * param_tcs_offchip_layout, and param_rw_buffers
4779 * should be passed to the epilog.
4780 */
4781 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4782 returns[num_returns++] = ctx->i32; /* SGPRs */
4783 for (i = 0; i < 11; i++)
4784 returns[num_returns++] = ctx->f32; /* VGPRs */
4785 }
4786 break;
4787
4788 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4789 /* Merged stages have 8 system SGPRs at the beginning. */
4790 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4791 declare_per_stage_desc_pointers(ctx, &fninfo,
4792 ctx->type == PIPE_SHADER_GEOMETRY);
4793
4794 if (ctx->shader->key.as_ngg)
4795 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->gs_tg_info);
4796 else
4797 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798
4799 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4800 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4801 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4802 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4803 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4804
4805 declare_global_desc_pointers(ctx, &fninfo);
4806 if (ctx->type != PIPE_SHADER_VERTEX || !vs_blit_property) {
4807 declare_per_stage_desc_pointers(ctx, &fninfo,
4808 (ctx->type == PIPE_SHADER_VERTEX ||
4809 ctx->type == PIPE_SHADER_TESS_EVAL));
4810 }
4811
4812 if (ctx->type == PIPE_SHADER_VERTEX) {
4813 if (vs_blit_property)
4814 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4815 else
4816 declare_vs_specific_input_sgprs(ctx, &fninfo);
4817 } else {
4818 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4819 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4820 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4821 /* Declare as many input SGPRs as the VS has. */
4822 }
4823
4824 if (ctx->type == PIPE_SHADER_VERTEX) {
4825 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4826 ac_array_in_const32_addr_space(ctx->v4i32));
4827 }
4828
4829 /* VGPRs (first GS, then VS/TES) */
4830 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4831 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4832 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4833 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4834 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4835
4836 if (ctx->type == PIPE_SHADER_VERTEX) {
4837 declare_vs_input_vgprs(ctx, &fninfo,
4838 &num_prolog_vgprs);
4839 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4840 declare_tes_input_vgprs(ctx, &fninfo);
4841 }
4842
4843 if (ctx->shader->key.as_es &&
4844 (ctx->type == PIPE_SHADER_VERTEX ||
4845 ctx->type == PIPE_SHADER_TESS_EVAL)) {
4846 unsigned num_user_sgprs;
4847
4848 if (ctx->type == PIPE_SHADER_VERTEX)
4849 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4850 else
4851 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4852
4853 /* ES return values are inputs to GS. */
4854 for (i = 0; i < 8 + num_user_sgprs; i++)
4855 returns[num_returns++] = ctx->i32; /* SGPRs */
4856 for (i = 0; i < 5; i++)
4857 returns[num_returns++] = ctx->f32; /* VGPRs */
4858 }
4859 break;
4860
4861 case PIPE_SHADER_TESS_EVAL:
4862 declare_global_desc_pointers(ctx, &fninfo);
4863 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4864 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4865 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4866 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4867
4868 if (shader->key.as_es) {
4869 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4870 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4871 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4872 } else {
4873 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4874 declare_streamout_params(ctx, &shader->selector->so,
4875 &fninfo);
4876 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4877 }
4878
4879 /* VGPRs */
4880 declare_tes_input_vgprs(ctx, &fninfo);
4881 break;
4882
4883 case PIPE_SHADER_GEOMETRY:
4884 declare_global_desc_pointers(ctx, &fninfo);
4885 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4886 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4887 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4888
4889 /* VGPRs */
4890 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4891 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4892 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4893 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4894 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4895 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4896 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4897 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4898 break;
4899
4900 case PIPE_SHADER_FRAGMENT:
4901 declare_global_desc_pointers(ctx, &fninfo);
4902 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4903 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4904 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4905 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4906
4907 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4908 &ctx->abi.persp_sample, SI_PARAM_PERSP_SAMPLE);
4909 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4910 &ctx->abi.persp_center, SI_PARAM_PERSP_CENTER);
4911 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4912 &ctx->abi.persp_centroid, SI_PARAM_PERSP_CENTROID);
4913 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4914 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4915 &ctx->abi.linear_sample, SI_PARAM_LINEAR_SAMPLE);
4916 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4917 &ctx->abi.linear_center, SI_PARAM_LINEAR_CENTER);
4918 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4919 &ctx->abi.linear_centroid, SI_PARAM_LINEAR_CENTROID);
4920 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4921 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4922 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4923 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4924 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4925 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4926 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4927 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4928 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4929 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4930 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4931 shader->info.face_vgpr_index = 20;
4932 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4933 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4934 shader->info.ancillary_vgpr_index = 21;
4935 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4936 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4937 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4938
4939 /* Color inputs from the prolog. */
4940 if (shader->selector->info.colors_read) {
4941 unsigned num_color_elements =
4942 util_bitcount(shader->selector->info.colors_read);
4943
4944 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4945 for (i = 0; i < num_color_elements; i++)
4946 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4947
4948 num_prolog_vgprs += num_color_elements;
4949 }
4950
4951 /* Outputs for the epilog. */
4952 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4953 num_returns =
4954 num_return_sgprs +
4955 util_bitcount(shader->selector->info.colors_written) * 4 +
4956 shader->selector->info.writes_z +
4957 shader->selector->info.writes_stencil +
4958 shader->selector->info.writes_samplemask +
4959 1 /* SampleMaskIn */;
4960
4961 num_returns = MAX2(num_returns,
4962 num_return_sgprs +
4963 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4964
4965 for (i = 0; i < num_return_sgprs; i++)
4966 returns[i] = ctx->i32;
4967 for (; i < num_returns; i++)
4968 returns[i] = ctx->f32;
4969 break;
4970
4971 case PIPE_SHADER_COMPUTE:
4972 declare_global_desc_pointers(ctx, &fninfo);
4973 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4974 if (shader->selector->info.uses_grid_size)
4975 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4976 if (shader->selector->info.uses_block_size &&
4977 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4978 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4979
4980 unsigned cs_user_data_dwords =
4981 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
4982 if (cs_user_data_dwords) {
4983 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4984 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4985 }
4986
4987 for (i = 0; i < 3; i++) {
4988 ctx->abi.workgroup_ids[i] = NULL;
4989 if (shader->selector->info.uses_block_id[i])
4990 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4991 }
4992
4993 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4994 break;
4995 default:
4996 assert(0 && "unimplemented shader");
4997 return;
4998 }
4999
5000 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5001 si_get_max_workgroup_size(shader));
5002
5003 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5004 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
5005 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5006 "InitialPSInputAddr",
5007 S_0286D0_PERSP_SAMPLE_ENA(1) |
5008 S_0286D0_PERSP_CENTER_ENA(1) |
5009 S_0286D0_PERSP_CENTROID_ENA(1) |
5010 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5011 S_0286D0_LINEAR_CENTER_ENA(1) |
5012 S_0286D0_LINEAR_CENTROID_ENA(1) |
5013 S_0286D0_FRONT_FACE_ENA(1) |
5014 S_0286D0_ANCILLARY_ENA(1) |
5015 S_0286D0_POS_FIXED_PT_ENA(1));
5016 }
5017
5018 shader->info.num_input_sgprs = 0;
5019 shader->info.num_input_vgprs = 0;
5020
5021 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5022 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5023
5024 for (; i < fninfo.num_params; ++i)
5025 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5026
5027 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5028 shader->info.num_input_vgprs -= num_prolog_vgprs;
5029
5030 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
5031 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
5032 /* The LSHS size is not known until draw time, so we append it
5033 * at the end of whatever LDS use there may be in the rest of
5034 * the shader (currently none, unless LLVM decides to do its
5035 * own LDS-based lowering).
5036 */
5037 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
5038 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5039 "__lds_end", AC_ADDR_SPACE_LDS);
5040 LLVMSetAlignment(ctx->ac.lds, 256);
5041 } else {
5042 ac_declare_lds_as_pointer(&ctx->ac);
5043 }
5044 }
5045 }
5046
5047 /* Ensure that the esgs ring is declared.
5048 *
5049 * We declare it with 64KB alignment as a hint that the
5050 * pointer value will always be 0.
5051 */
5052 static void declare_esgs_ring(struct si_shader_context *ctx)
5053 {
5054 if (ctx->esgs_ring)
5055 return;
5056
5057 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
5058
5059 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
5060 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5061 "esgs_ring",
5062 AC_ADDR_SPACE_LDS);
5063 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
5064 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
5065 }
5066
5067 /**
5068 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5069 * for later use.
5070 */
5071 static void preload_ring_buffers(struct si_shader_context *ctx)
5072 {
5073 LLVMBuilderRef builder = ctx->ac.builder;
5074
5075 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5076 ctx->param_rw_buffers);
5077
5078 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
5079 if (ctx->screen->info.chip_class <= GFX8) {
5080 unsigned ring =
5081 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5082 : SI_ES_RING_ESGS;
5083 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5084
5085 ctx->esgs_ring =
5086 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5087 } else {
5088 if (USE_LDS_SYMBOLS && HAVE_LLVM >= 0x0900) {
5089 /* Declare the ESGS ring as an explicit LDS symbol. */
5090 declare_esgs_ring(ctx);
5091 } else {
5092 ac_declare_lds_as_pointer(&ctx->ac);
5093 ctx->esgs_ring = ctx->ac.lds;
5094 }
5095 }
5096 }
5097
5098 if (ctx->shader->is_gs_copy_shader) {
5099 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5100
5101 ctx->gsvs_ring[0] =
5102 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5103 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5104 const struct si_shader_selector *sel = ctx->shader->selector;
5105 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5106 LLVMValueRef base_ring;
5107
5108 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5109
5110 /* The conceptual layout of the GSVS ring is
5111 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5112 * but the real memory layout is swizzled across
5113 * threads:
5114 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5115 * t16v0c0 ..
5116 * Override the buffer descriptor accordingly.
5117 */
5118 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5119 uint64_t stream_offset = 0;
5120
5121 for (unsigned stream = 0; stream < 4; ++stream) {
5122 unsigned num_components;
5123 unsigned stride;
5124 unsigned num_records;
5125 LLVMValueRef ring, tmp;
5126
5127 num_components = sel->info.num_stream_output_components[stream];
5128 if (!num_components)
5129 continue;
5130
5131 stride = 4 * num_components * sel->gs_max_out_vertices;
5132
5133 /* Limit on the stride field for <= GFX7. */
5134 assert(stride < (1 << 14));
5135
5136 num_records = ctx->ac.wave_size;
5137
5138 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5139 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5140 tmp = LLVMBuildAdd(builder, tmp,
5141 LLVMConstInt(ctx->i64,
5142 stream_offset, 0), "");
5143 stream_offset += stride * ctx->ac.wave_size;
5144
5145 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5146 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5147 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5148 tmp = LLVMBuildOr(builder, tmp,
5149 LLVMConstInt(ctx->i32,
5150 S_008F04_STRIDE(stride) |
5151 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5152 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5153 ring = LLVMBuildInsertElement(builder, ring,
5154 LLVMConstInt(ctx->i32, num_records, 0),
5155 LLVMConstInt(ctx->i32, 2, 0), "");
5156
5157 uint32_t rsrc3 =
5158 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5159 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5160 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5161 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5162 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5163 S_008F0C_ADD_TID_ENABLE(1);
5164
5165 if (ctx->ac.chip_class >= GFX10) {
5166 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5167 S_008F0C_OOB_SELECT(2) |
5168 S_008F0C_RESOURCE_LEVEL(1);
5169 } else {
5170 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5172 S_008F0C_ELEMENT_SIZE(1); /* element_size = 4 (bytes) */
5173 }
5174
5175 ring = LLVMBuildInsertElement(builder, ring,
5176 LLVMConstInt(ctx->i32, rsrc3, false),
5177 LLVMConstInt(ctx->i32, 3, 0), "");
5178
5179 ctx->gsvs_ring[stream] = ring;
5180 }
5181 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5182 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5183 }
5184 }
5185
5186 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5187 LLVMValueRef param_rw_buffers,
5188 unsigned param_pos_fixed_pt)
5189 {
5190 LLVMBuilderRef builder = ctx->ac.builder;
5191 LLVMValueRef slot, desc, offset, row, bit, address[2];
5192
5193 /* Use the fixed-point gl_FragCoord input.
5194 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5195 * per coordinate to get the repeating effect.
5196 */
5197 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5198 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5199
5200 /* Load the buffer descriptor. */
5201 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5202 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5203
5204 /* The stipple pattern is 32x32, each row has 32 bits. */
5205 offset = LLVMBuildMul(builder, address[1],
5206 LLVMConstInt(ctx->i32, 4, 0), "");
5207 row = buffer_load_const(ctx, desc, offset);
5208 row = ac_to_integer(&ctx->ac, row);
5209 bit = LLVMBuildLShr(builder, row, address[0], "");
5210 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5211 ac_build_kill_if_false(&ctx->ac, bit);
5212 }
5213
5214 /* For the UMR disassembler. */
5215 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5216 #define DEBUGGER_NUM_MARKERS 5
5217
5218 static bool si_shader_binary_open(struct si_screen *screen,
5219 struct si_shader *shader,
5220 struct ac_rtld_binary *rtld)
5221 {
5222 const struct si_shader_selector *sel = shader->selector;
5223 const char *part_elfs[5];
5224 size_t part_sizes[5];
5225 unsigned num_parts = 0;
5226
5227 #define add_part(shader_or_part) \
5228 if (shader_or_part) { \
5229 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5230 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5231 num_parts++; \
5232 }
5233
5234 add_part(shader->prolog);
5235 add_part(shader->previous_stage);
5236 add_part(shader->prolog2);
5237 add_part(shader);
5238 add_part(shader->epilog);
5239
5240 #undef add_part
5241
5242 struct ac_rtld_symbol lds_symbols[2];
5243 unsigned num_lds_symbols = 0;
5244
5245 if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
5246 (sel->type == PIPE_SHADER_GEOMETRY || shader->key.as_ngg)) {
5247 /* We add this symbol even on LLVM <= 8 to ensure that
5248 * shader->config.lds_size is set correctly below.
5249 */
5250 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5251 sym->name = "esgs_ring";
5252 sym->size = shader->gs_info.esgs_ring_size;
5253 sym->align = 64 * 1024;
5254 }
5255
5256 if (shader->key.as_ngg && sel->type == PIPE_SHADER_GEOMETRY) {
5257 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5258 sym->name = "ngg_emit";
5259 sym->size = shader->ngg.ngg_emit_size * 4;
5260 sym->align = 4;
5261 }
5262
5263 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
5264 .info = &screen->info,
5265 .options = {
5266 .halt_at_entry = screen->options.halt_shaders,
5267 },
5268 .shader_type = tgsi_processor_to_shader_stage(sel->type),
5269 .wave_size = si_get_shader_wave_size(shader),
5270 .num_parts = num_parts,
5271 .elf_ptrs = part_elfs,
5272 .elf_sizes = part_sizes,
5273 .num_shared_lds_symbols = num_lds_symbols,
5274 .shared_lds_symbols = lds_symbols });
5275
5276 if (rtld->lds_size > 0) {
5277 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
5278 shader->config.lds_size =
5279 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
5280 }
5281
5282 return ok;
5283 }
5284
5285 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
5286 {
5287 struct ac_rtld_binary rtld;
5288 si_shader_binary_open(screen, shader, &rtld);
5289 return rtld.rx_size;
5290 }
5291
5292 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
5293 {
5294 uint64_t *scratch_va = data;
5295
5296 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
5297 *value = (uint32_t)*scratch_va;
5298 return true;
5299 }
5300 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
5301 /* Enable scratch coalescing. */
5302 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
5303 S_008F04_SWIZZLE_ENABLE(1);
5304 return true;
5305 }
5306
5307 return false;
5308 }
5309
5310 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
5311 uint64_t scratch_va)
5312 {
5313 struct ac_rtld_binary binary;
5314 if (!si_shader_binary_open(sscreen, shader, &binary))
5315 return false;
5316
5317 si_resource_reference(&shader->bo, NULL);
5318 shader->bo = si_aligned_buffer_create(&sscreen->b,
5319 sscreen->info.cpdma_prefetch_writes_memory ?
5320 0 : SI_RESOURCE_FLAG_READ_ONLY,
5321 PIPE_USAGE_IMMUTABLE,
5322 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
5323 256);
5324 if (!shader->bo)
5325 return false;
5326
5327 /* Upload. */
5328 struct ac_rtld_upload_info u = {};
5329 u.binary = &binary;
5330 u.get_external_symbol = si_get_external_symbol;
5331 u.cb_data = &scratch_va;
5332 u.rx_va = shader->bo->gpu_address;
5333 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5334 PIPE_TRANSFER_READ_WRITE |
5335 PIPE_TRANSFER_UNSYNCHRONIZED |
5336 RADEON_TRANSFER_TEMPORARY);
5337 if (!u.rx_ptr)
5338 return false;
5339
5340 bool ok = ac_rtld_upload(&u);
5341
5342 sscreen->ws->buffer_unmap(shader->bo->buf);
5343 ac_rtld_close(&binary);
5344
5345 return ok;
5346 }
5347
5348 static void si_shader_dump_disassembly(struct si_screen *screen,
5349 const struct si_shader_binary *binary,
5350 enum pipe_shader_type shader_type,
5351 unsigned wave_size,
5352 struct pipe_debug_callback *debug,
5353 const char *name, FILE *file)
5354 {
5355 struct ac_rtld_binary rtld_binary;
5356
5357 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
5358 .info = &screen->info,
5359 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5360 .wave_size = wave_size,
5361 .num_parts = 1,
5362 .elf_ptrs = &binary->elf_buffer,
5363 .elf_sizes = &binary->elf_size }))
5364 return;
5365
5366 const char *disasm;
5367 size_t nbytes;
5368
5369 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
5370 goto out;
5371
5372 if (nbytes > INT_MAX)
5373 goto out;
5374
5375 if (debug && debug->debug_message) {
5376 /* Very long debug messages are cut off, so send the
5377 * disassembly one line at a time. This causes more
5378 * overhead, but on the plus side it simplifies
5379 * parsing of resulting logs.
5380 */
5381 pipe_debug_message(debug, SHADER_INFO,
5382 "Shader Disassembly Begin");
5383
5384 uint64_t line = 0;
5385 while (line < nbytes) {
5386 int count = nbytes - line;
5387 const char *nl = memchr(disasm + line, '\n', nbytes - line);
5388 if (nl)
5389 count = nl - (disasm + line);
5390
5391 if (count) {
5392 pipe_debug_message(debug, SHADER_INFO,
5393 "%.*s", count, disasm + line);
5394 }
5395
5396 line += count + 1;
5397 }
5398
5399 pipe_debug_message(debug, SHADER_INFO,
5400 "Shader Disassembly End");
5401 }
5402
5403 if (file) {
5404 fprintf(file, "Shader %s disassembly:\n", name);
5405 fprintf(file, "%*s", (int)nbytes, disasm);
5406 }
5407
5408 out:
5409 ac_rtld_close(&rtld_binary);
5410 }
5411
5412 static void si_calculate_max_simd_waves(struct si_shader *shader)
5413 {
5414 struct si_screen *sscreen = shader->selector->screen;
5415 struct ac_shader_config *conf = &shader->config;
5416 unsigned num_inputs = shader->selector->info.num_inputs;
5417 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5418 unsigned lds_per_wave = 0;
5419 unsigned max_simd_waves;
5420
5421 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5422
5423 /* Compute LDS usage for PS. */
5424 switch (shader->selector->type) {
5425 case PIPE_SHADER_FRAGMENT:
5426 /* The minimum usage per wave is (num_inputs * 48). The maximum
5427 * usage is (num_inputs * 48 * 16).
5428 * We can get anything in between and it varies between waves.
5429 *
5430 * The 48 bytes per input for a single primitive is equal to
5431 * 4 bytes/component * 4 components/input * 3 points.
5432 *
5433 * Other stages don't know the size at compile time or don't
5434 * allocate LDS per wave, but instead they do it per thread group.
5435 */
5436 lds_per_wave = conf->lds_size * lds_increment +
5437 align(num_inputs * 48, lds_increment);
5438 break;
5439 case PIPE_SHADER_COMPUTE:
5440 if (shader->selector) {
5441 unsigned max_workgroup_size =
5442 si_get_max_workgroup_size(shader);
5443 lds_per_wave = (conf->lds_size * lds_increment) /
5444 DIV_ROUND_UP(max_workgroup_size,
5445 sscreen->compute_wave_size);
5446 }
5447 break;
5448 default:;
5449 }
5450
5451 /* Compute the per-SIMD wave counts. */
5452 if (conf->num_sgprs) {
5453 max_simd_waves =
5454 MIN2(max_simd_waves,
5455 ac_get_num_physical_sgprs(sscreen->info.chip_class) / conf->num_sgprs);
5456 }
5457
5458 if (conf->num_vgprs)
5459 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5460
5461 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5462 * 16KB makes some SIMDs unoccupied). */
5463 if (lds_per_wave)
5464 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5465
5466 shader->info.max_simd_waves = max_simd_waves;
5467 }
5468
5469 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
5470 struct si_shader *shader,
5471 struct pipe_debug_callback *debug)
5472 {
5473 const struct ac_shader_config *conf = &shader->config;
5474
5475 if (screen->options.debug_disassembly)
5476 si_shader_dump_disassembly(screen, &shader->binary,
5477 shader->selector->type,
5478 si_get_shader_wave_size(shader),
5479 debug, "main", NULL);
5480
5481 pipe_debug_message(debug, SHADER_INFO,
5482 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5483 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5484 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5485 conf->num_sgprs, conf->num_vgprs,
5486 si_get_shader_binary_size(screen, shader),
5487 conf->lds_size, conf->scratch_bytes_per_wave,
5488 shader->info.max_simd_waves, conf->spilled_sgprs,
5489 conf->spilled_vgprs, shader->info.private_mem_vgprs);
5490 }
5491
5492 static void si_shader_dump_stats(struct si_screen *sscreen,
5493 struct si_shader *shader,
5494 FILE *file,
5495 bool check_debug_option)
5496 {
5497 const struct ac_shader_config *conf = &shader->config;
5498
5499 if (!check_debug_option ||
5500 si_can_dump_shader(sscreen, shader->selector->type)) {
5501 if (shader->selector->type == PIPE_SHADER_FRAGMENT) {
5502 fprintf(file, "*** SHADER CONFIG ***\n"
5503 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5504 "SPI_PS_INPUT_ENA = 0x%04x\n",
5505 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5506 }
5507
5508 fprintf(file, "*** SHADER STATS ***\n"
5509 "SGPRS: %d\n"
5510 "VGPRS: %d\n"
5511 "Spilled SGPRs: %d\n"
5512 "Spilled VGPRs: %d\n"
5513 "Private memory VGPRs: %d\n"
5514 "Code Size: %d bytes\n"
5515 "LDS: %d blocks\n"
5516 "Scratch: %d bytes per wave\n"
5517 "Max Waves: %d\n"
5518 "********************\n\n\n",
5519 conf->num_sgprs, conf->num_vgprs,
5520 conf->spilled_sgprs, conf->spilled_vgprs,
5521 shader->info.private_mem_vgprs,
5522 si_get_shader_binary_size(sscreen, shader),
5523 conf->lds_size, conf->scratch_bytes_per_wave,
5524 shader->info.max_simd_waves);
5525 }
5526 }
5527
5528 const char *si_get_shader_name(const struct si_shader *shader)
5529 {
5530 switch (shader->selector->type) {
5531 case PIPE_SHADER_VERTEX:
5532 if (shader->key.as_es)
5533 return "Vertex Shader as ES";
5534 else if (shader->key.as_ls)
5535 return "Vertex Shader as LS";
5536 else if (shader->key.opt.vs_as_prim_discard_cs)
5537 return "Vertex Shader as Primitive Discard CS";
5538 else if (shader->key.as_ngg)
5539 return "Vertex Shader as ESGS";
5540 else
5541 return "Vertex Shader as VS";
5542 case PIPE_SHADER_TESS_CTRL:
5543 return "Tessellation Control Shader";
5544 case PIPE_SHADER_TESS_EVAL:
5545 if (shader->key.as_es)
5546 return "Tessellation Evaluation Shader as ES";
5547 else if (shader->key.as_ngg)
5548 return "Tessellation Evaluation Shader as ESGS";
5549 else
5550 return "Tessellation Evaluation Shader as VS";
5551 case PIPE_SHADER_GEOMETRY:
5552 if (shader->is_gs_copy_shader)
5553 return "GS Copy Shader as VS";
5554 else
5555 return "Geometry Shader";
5556 case PIPE_SHADER_FRAGMENT:
5557 return "Pixel Shader";
5558 case PIPE_SHADER_COMPUTE:
5559 return "Compute Shader";
5560 default:
5561 return "Unknown Shader";
5562 }
5563 }
5564
5565 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5566 struct pipe_debug_callback *debug,
5567 FILE *file, bool check_debug_option)
5568 {
5569 enum pipe_shader_type shader_type = shader->selector->type;
5570
5571 if (!check_debug_option ||
5572 si_can_dump_shader(sscreen, shader_type))
5573 si_dump_shader_key(shader, file);
5574
5575 if (!check_debug_option && shader->binary.llvm_ir_string) {
5576 if (shader->previous_stage &&
5577 shader->previous_stage->binary.llvm_ir_string) {
5578 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5579 si_get_shader_name(shader));
5580 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5581 }
5582
5583 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5584 si_get_shader_name(shader));
5585 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5586 }
5587
5588 if (!check_debug_option ||
5589 (si_can_dump_shader(sscreen, shader_type) &&
5590 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5591 unsigned wave_size = si_get_shader_wave_size(shader);
5592
5593 fprintf(file, "\n%s:\n", si_get_shader_name(shader));
5594
5595 if (shader->prolog)
5596 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
5597 shader_type, wave_size, debug, "prolog", file);
5598 if (shader->previous_stage)
5599 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
5600 shader_type, wave_size, debug, "previous stage", file);
5601 if (shader->prolog2)
5602 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
5603 shader_type, wave_size, debug, "prolog2", file);
5604
5605 si_shader_dump_disassembly(sscreen, &shader->binary, shader_type,
5606 wave_size, debug, "main", file);
5607
5608 if (shader->epilog)
5609 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
5610 shader_type, wave_size, debug, "epilog", file);
5611 fprintf(file, "\n");
5612 }
5613
5614 si_shader_dump_stats(sscreen, shader, file, check_debug_option);
5615 }
5616
5617 static int si_compile_llvm(struct si_screen *sscreen,
5618 struct si_shader_binary *binary,
5619 struct ac_shader_config *conf,
5620 struct ac_llvm_compiler *compiler,
5621 LLVMModuleRef mod,
5622 struct pipe_debug_callback *debug,
5623 enum pipe_shader_type shader_type,
5624 unsigned wave_size,
5625 const char *name,
5626 bool less_optimized)
5627 {
5628 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5629
5630 if (si_can_dump_shader(sscreen, shader_type)) {
5631 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5632
5633 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5634 fprintf(stderr, "%s LLVM IR:\n\n", name);
5635 ac_dump_module(mod);
5636 fprintf(stderr, "\n");
5637 }
5638 }
5639
5640 if (sscreen->record_llvm_ir) {
5641 char *ir = LLVMPrintModuleToString(mod);
5642 binary->llvm_ir_string = strdup(ir);
5643 LLVMDisposeMessage(ir);
5644 }
5645
5646 if (!si_replace_shader(count, binary)) {
5647 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
5648 less_optimized, wave_size);
5649 if (r)
5650 return r;
5651 }
5652
5653 struct ac_rtld_binary rtld;
5654 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
5655 .info = &sscreen->info,
5656 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5657 .wave_size = wave_size,
5658 .num_parts = 1,
5659 .elf_ptrs = &binary->elf_buffer,
5660 .elf_sizes = &binary->elf_size }))
5661 return -1;
5662
5663 bool ok = ac_rtld_read_config(&rtld, conf);
5664 ac_rtld_close(&rtld);
5665 if (!ok)
5666 return -1;
5667
5668 /* Enable 64-bit and 16-bit denormals, because there is no performance
5669 * cost.
5670 *
5671 * If denormals are enabled, all floating-point output modifiers are
5672 * ignored.
5673 *
5674 * Don't enable denormals for 32-bit floats, because:
5675 * - Floating-point output modifiers would be ignored by the hw.
5676 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5677 * have to stop using those.
5678 * - GFX6 & GFX7 would be very slow.
5679 */
5680 conf->float_mode |= V_00B028_FP_64_DENORMS;
5681
5682 return 0;
5683 }
5684
5685 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5686 {
5687 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5688 LLVMBuildRetVoid(ctx->ac.builder);
5689 else
5690 LLVMBuildRet(ctx->ac.builder, ret);
5691 }
5692
5693 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5694 struct si_shader *
5695 si_generate_gs_copy_shader(struct si_screen *sscreen,
5696 struct ac_llvm_compiler *compiler,
5697 struct si_shader_selector *gs_selector,
5698 struct pipe_debug_callback *debug)
5699 {
5700 struct si_shader_context ctx;
5701 struct si_shader *shader;
5702 LLVMBuilderRef builder;
5703 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5704 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5705 int i;
5706
5707
5708 shader = CALLOC_STRUCT(si_shader);
5709 if (!shader)
5710 return NULL;
5711
5712 /* We can leave the fence as permanently signaled because the GS copy
5713 * shader only becomes visible globally after it has been compiled. */
5714 util_queue_fence_init(&shader->ready);
5715
5716 shader->selector = gs_selector;
5717 shader->is_gs_copy_shader = true;
5718
5719 si_init_shader_ctx(&ctx, sscreen, compiler,
5720 si_get_wave_size(sscreen, PIPE_SHADER_VERTEX, false, false),
5721 false);
5722 ctx.shader = shader;
5723 ctx.type = PIPE_SHADER_VERTEX;
5724
5725 builder = ctx.ac.builder;
5726
5727 create_function(&ctx);
5728 preload_ring_buffers(&ctx);
5729
5730 LLVMValueRef voffset =
5731 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5732 LLVMConstInt(ctx.i32, 4, 0), "");
5733
5734 /* Fetch the vertex stream ID.*/
5735 LLVMValueRef stream_id;
5736
5737 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs)
5738 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5739 else
5740 stream_id = ctx.i32_0;
5741
5742 /* Fill in output information. */
5743 for (i = 0; i < gsinfo->num_outputs; ++i) {
5744 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5745 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5746
5747 for (int chan = 0; chan < 4; chan++) {
5748 outputs[i].vertex_stream[chan] =
5749 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5750 }
5751 }
5752
5753 LLVMBasicBlockRef end_bb;
5754 LLVMValueRef switch_inst;
5755
5756 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5757 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5758
5759 for (int stream = 0; stream < 4; stream++) {
5760 LLVMBasicBlockRef bb;
5761 unsigned offset;
5762
5763 if (!gsinfo->num_stream_output_components[stream])
5764 continue;
5765
5766 if (stream > 0 && !gs_selector->so.num_outputs)
5767 continue;
5768
5769 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5770 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5771 LLVMPositionBuilderAtEnd(builder, bb);
5772
5773 /* Fetch vertex data from GSVS ring */
5774 offset = 0;
5775 for (i = 0; i < gsinfo->num_outputs; ++i) {
5776 for (unsigned chan = 0; chan < 4; chan++) {
5777 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5778 outputs[i].vertex_stream[chan] != stream) {
5779 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5780 continue;
5781 }
5782
5783 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5784 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5785 offset++;
5786
5787 outputs[i].values[chan] =
5788 ac_build_buffer_load(&ctx.ac,
5789 ctx.gsvs_ring[0], 1,
5790 ctx.i32_0, voffset,
5791 soffset, 0, ac_glc | ac_slc,
5792 true, false);
5793 }
5794 }
5795
5796 /* Streamout and exports. */
5797 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs) {
5798 si_llvm_emit_streamout(&ctx, outputs,
5799 gsinfo->num_outputs,
5800 stream);
5801 }
5802
5803 if (stream == 0)
5804 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5805
5806 LLVMBuildBr(builder, end_bb);
5807 }
5808
5809 LLVMPositionBuilderAtEnd(builder, end_bb);
5810
5811 LLVMBuildRetVoid(ctx.ac.builder);
5812
5813 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5814 si_llvm_optimize_module(&ctx);
5815
5816 bool ok = false;
5817 if (si_compile_llvm(sscreen, &ctx.shader->binary,
5818 &ctx.shader->config, ctx.compiler,
5819 ctx.ac.module,
5820 debug, PIPE_SHADER_GEOMETRY, ctx.ac.wave_size,
5821 "GS Copy Shader", false) == 0) {
5822 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5823 fprintf(stderr, "GS Copy Shader:\n");
5824 si_shader_dump(sscreen, ctx.shader, debug, stderr, true);
5825
5826 if (!ctx.shader->config.scratch_bytes_per_wave)
5827 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
5828 else
5829 ok = true;
5830 }
5831
5832 si_llvm_dispose(&ctx);
5833
5834 if (!ok) {
5835 FREE(shader);
5836 shader = NULL;
5837 } else {
5838 si_fix_resource_usage(sscreen, shader);
5839 }
5840 return shader;
5841 }
5842
5843 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5844 const struct si_vs_prolog_bits *prolog,
5845 const char *prefix, FILE *f)
5846 {
5847 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5848 prefix, prolog->instance_divisor_is_one);
5849 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5850 prefix, prolog->instance_divisor_is_fetched);
5851 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5852 prefix, prolog->unpack_instance_id_from_vertex_id);
5853 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5854 prefix, prolog->ls_vgpr_fix);
5855
5856 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5857 fprintf(f, " mono.vs.fix_fetch = {");
5858 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5859 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5860 if (i)
5861 fprintf(f, ", ");
5862 if (!fix.bits)
5863 fprintf(f, "0");
5864 else
5865 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5866 fix.u.num_channels_m1, fix.u.format);
5867 }
5868 fprintf(f, "}\n");
5869 }
5870
5871 static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
5872 {
5873 const struct si_shader_key *key = &shader->key;
5874 enum pipe_shader_type shader_type = shader->selector->type;
5875
5876 fprintf(f, "SHADER KEY\n");
5877
5878 switch (shader_type) {
5879 case PIPE_SHADER_VERTEX:
5880 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5881 "part.vs.prolog", f);
5882 fprintf(f, " as_es = %u\n", key->as_es);
5883 fprintf(f, " as_ls = %u\n", key->as_ls);
5884 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5885 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5886 key->mono.u.vs_export_prim_id);
5887 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5888 key->opt.vs_as_prim_discard_cs);
5889 fprintf(f, " opt.cs_prim_type = %s\n",
5890 tgsi_primitive_names[key->opt.cs_prim_type]);
5891 fprintf(f, " opt.cs_indexed = %u\n",
5892 key->opt.cs_indexed);
5893 fprintf(f, " opt.cs_instancing = %u\n",
5894 key->opt.cs_instancing);
5895 fprintf(f, " opt.cs_primitive_restart = %u\n",
5896 key->opt.cs_primitive_restart);
5897 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5898 key->opt.cs_provoking_vertex_first);
5899 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5900 key->opt.cs_need_correct_orientation);
5901 fprintf(f, " opt.cs_cull_front = %u\n",
5902 key->opt.cs_cull_front);
5903 fprintf(f, " opt.cs_cull_back = %u\n",
5904 key->opt.cs_cull_back);
5905 fprintf(f, " opt.cs_cull_z = %u\n",
5906 key->opt.cs_cull_z);
5907 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5908 key->opt.cs_halfz_clip_space);
5909 break;
5910
5911 case PIPE_SHADER_TESS_CTRL:
5912 if (shader->selector->screen->info.chip_class >= GFX9) {
5913 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5914 "part.tcs.ls_prolog", f);
5915 }
5916 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5917 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5918 break;
5919
5920 case PIPE_SHADER_TESS_EVAL:
5921 fprintf(f, " as_es = %u\n", key->as_es);
5922 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5923 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5924 key->mono.u.vs_export_prim_id);
5925 break;
5926
5927 case PIPE_SHADER_GEOMETRY:
5928 if (shader->is_gs_copy_shader)
5929 break;
5930
5931 if (shader->selector->screen->info.chip_class >= GFX9 &&
5932 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5933 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5934 "part.gs.vs_prolog", f);
5935 }
5936 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5937 fprintf(f, " part.gs.prolog.gfx9_prev_is_vs = %u\n", key->part.gs.prolog.gfx9_prev_is_vs);
5938 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5939 break;
5940
5941 case PIPE_SHADER_COMPUTE:
5942 break;
5943
5944 case PIPE_SHADER_FRAGMENT:
5945 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5946 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5947 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5948 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5949 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5950 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5951 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5952 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5953 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5954 fprintf(f, " part.ps.prolog.samplemask_log_ps_iter = %u\n", key->part.ps.prolog.samplemask_log_ps_iter);
5955 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5956 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5957 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5958 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5959 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5960 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5961 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5962 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5963 fprintf(f, " mono.u.ps.interpolate_at_sample_force_center = %u\n", key->mono.u.ps.interpolate_at_sample_force_center);
5964 fprintf(f, " mono.u.ps.fbfetch_msaa = %u\n", key->mono.u.ps.fbfetch_msaa);
5965 fprintf(f, " mono.u.ps.fbfetch_is_1D = %u\n", key->mono.u.ps.fbfetch_is_1D);
5966 fprintf(f, " mono.u.ps.fbfetch_layered = %u\n", key->mono.u.ps.fbfetch_layered);
5967 break;
5968
5969 default:
5970 assert(0);
5971 }
5972
5973 if ((shader_type == PIPE_SHADER_GEOMETRY ||
5974 shader_type == PIPE_SHADER_TESS_EVAL ||
5975 shader_type == PIPE_SHADER_VERTEX) &&
5976 !key->as_es && !key->as_ls) {
5977 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5978 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5979 }
5980 }
5981
5982 static void si_init_shader_ctx(struct si_shader_context *ctx,
5983 struct si_screen *sscreen,
5984 struct ac_llvm_compiler *compiler,
5985 unsigned wave_size,
5986 bool nir)
5987 {
5988 struct lp_build_tgsi_context *bld_base;
5989
5990 si_llvm_context_init(ctx, sscreen, compiler, wave_size,
5991 nir ? 64 : wave_size);
5992
5993 bld_base = &ctx->bld_base;
5994 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5995
5996 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5997 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5998 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5999
6000 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6001
6002 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6003
6004 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6005 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6006 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6007 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6008
6009 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6010 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6011 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6012 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6013 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6014 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6015 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6016 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6017
6018 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
6019 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
6020 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6021 }
6022
6023 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
6024 {
6025 struct si_shader *shader = ctx->shader;
6026 struct tgsi_shader_info *info = &shader->selector->info;
6027
6028 if ((ctx->type != PIPE_SHADER_VERTEX &&
6029 ctx->type != PIPE_SHADER_TESS_EVAL) ||
6030 shader->key.as_ls ||
6031 shader->key.as_es)
6032 return;
6033
6034 ac_optimize_vs_outputs(&ctx->ac,
6035 ctx->main_fn,
6036 shader->info.vs_output_param_offset,
6037 info->num_outputs,
6038 &shader->info.nr_param_exports);
6039 }
6040
6041 static void si_init_exec_from_input(struct si_shader_context *ctx,
6042 unsigned param, unsigned bitoffset)
6043 {
6044 LLVMValueRef args[] = {
6045 LLVMGetParam(ctx->main_fn, param),
6046 LLVMConstInt(ctx->i32, bitoffset, 0),
6047 };
6048 ac_build_intrinsic(&ctx->ac,
6049 "llvm.amdgcn.init.exec.from.input",
6050 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
6051 }
6052
6053 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6054 const struct si_vs_prolog_bits *key)
6055 {
6056 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6057 * VS prolog. */
6058 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6059 }
6060
6061 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
6062 {
6063 struct si_shader *shader = ctx->shader;
6064 struct si_shader_selector *sel = shader->selector;
6065 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6066
6067 // TODO clean all this up!
6068 switch (ctx->type) {
6069 case PIPE_SHADER_VERTEX:
6070 ctx->load_input = declare_input_vs;
6071 if (shader->key.as_ls)
6072 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6073 else if (shader->key.as_es)
6074 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6075 else if (shader->key.opt.vs_as_prim_discard_cs)
6076 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
6077 else if (shader->key.as_ngg)
6078 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6079 else
6080 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6081 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6082 ctx->abi.load_base_vertex = get_base_vertex;
6083 break;
6084 case PIPE_SHADER_TESS_CTRL:
6085 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6086 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6087 ctx->abi.load_tess_level = si_load_tess_level;
6088 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6089 bld_base->emit_store = store_output_tcs;
6090 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6091 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6092 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6093 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6094 break;
6095 case PIPE_SHADER_TESS_EVAL:
6096 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6097 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6098 ctx->abi.load_tess_coord = si_load_tess_coord;
6099 ctx->abi.load_tess_level = si_load_tess_level;
6100 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6101 if (shader->key.as_es)
6102 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6103 else if (shader->key.as_ngg)
6104 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6105 else
6106 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6107 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6108 break;
6109 case PIPE_SHADER_GEOMETRY:
6110 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6111 ctx->abi.load_inputs = si_nir_load_input_gs;
6112 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6113 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6114 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6115 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6116 break;
6117 case PIPE_SHADER_FRAGMENT:
6118 ctx->load_input = declare_input_fs;
6119 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6120 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6121 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6122 ctx->abi.load_sample_position = load_sample_position;
6123 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6124 ctx->abi.emit_fbfetch = si_nir_emit_fbfetch;
6125 ctx->abi.emit_kill = si_llvm_emit_kill;
6126 break;
6127 case PIPE_SHADER_COMPUTE:
6128 ctx->abi.load_local_group_size = get_block_size;
6129 break;
6130 default:
6131 assert(!"Unsupported shader type");
6132 return false;
6133 }
6134
6135 ctx->abi.load_ubo = load_ubo;
6136 ctx->abi.load_ssbo = load_ssbo;
6137
6138 create_function(ctx);
6139 preload_ring_buffers(ctx);
6140
6141 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6142 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6143 for (unsigned i = 0; i < 6; i++) {
6144 ctx->invoc0_tess_factors[i] =
6145 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6146 }
6147 }
6148
6149 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6150 for (unsigned i = 0; i < 4; i++) {
6151 ctx->gs_next_vertex[i] =
6152 ac_build_alloca(&ctx->ac, ctx->i32, "");
6153 }
6154 if (shader->key.as_ngg) {
6155 for (unsigned i = 0; i < 4; ++i) {
6156 ctx->gs_curprim_verts[i] =
6157 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6158 ctx->gs_generated_prims[i] =
6159 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6160 }
6161
6162 unsigned scratch_size = 8;
6163 if (sel->so.num_outputs)
6164 scratch_size = 44;
6165
6166 LLVMTypeRef ai32 = LLVMArrayType(ctx->i32, scratch_size);
6167 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6168 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6169 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(ai32));
6170 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6171
6172 ctx->gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6173 LLVMArrayType(ctx->i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
6174 LLVMSetLinkage(ctx->gs_ngg_emit, LLVMExternalLinkage);
6175 LLVMSetAlignment(ctx->gs_ngg_emit, 4);
6176 }
6177 }
6178
6179 if (ctx->type != PIPE_SHADER_GEOMETRY &&
6180 (shader->key.as_ngg && !shader->key.as_es)) {
6181 /* Unconditionally declare scratch space base for streamout and
6182 * vertex compaction. Whether space is actually allocated is
6183 * determined during linking / PM4 creation.
6184 *
6185 * Add an extra dword per vertex to ensure an odd stride, which
6186 * avoids bank conflicts for SoA accesses.
6187 */
6188 declare_esgs_ring(ctx);
6189
6190 /* This is really only needed when streamout and / or vertex
6191 * compaction is enabled.
6192 */
6193 LLVMTypeRef asi32 = LLVMArrayType(ctx->i32, 8);
6194 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6195 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6196 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(asi32));
6197 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6198 }
6199
6200 /* For GFX9 merged shaders:
6201 * - Set EXEC for the first shader. If the prolog is present, set
6202 * EXEC there instead.
6203 * - Add a barrier before the second shader.
6204 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6205 * an if-statement. This is required for correctness in geometry
6206 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6207 * GS_CUT messages.
6208 *
6209 * For monolithic merged shaders, the first shader is wrapped in an
6210 * if-block together with its prolog in si_build_wrapper_function.
6211 *
6212 * NGG vertex and tess eval shaders running as the last
6213 * vertex/geometry stage handle execution explicitly using
6214 * if-statements.
6215 */
6216 if (ctx->screen->info.chip_class >= GFX9) {
6217 if (!shader->is_monolithic &&
6218 sel->info.num_instructions > 1 && /* not empty shader */
6219 (shader->key.as_es || shader->key.as_ls) &&
6220 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6221 (ctx->type == PIPE_SHADER_VERTEX &&
6222 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6223 si_init_exec_from_input(ctx,
6224 ctx->param_merged_wave_info, 0);
6225 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6226 ctx->type == PIPE_SHADER_GEOMETRY ||
6227 (shader->key.as_ngg && !shader->key.as_es)) {
6228 LLVMValueRef num_threads;
6229 bool nested_barrier;
6230
6231 if (!shader->is_monolithic ||
6232 (ctx->type == PIPE_SHADER_TESS_EVAL &&
6233 (shader->key.as_ngg && !shader->key.as_es)))
6234 ac_init_exec_full_mask(&ctx->ac);
6235
6236 if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6237 ctx->type == PIPE_SHADER_GEOMETRY) {
6238 if (ctx->type == PIPE_SHADER_GEOMETRY && shader->key.as_ngg) {
6239 gfx10_ngg_gs_emit_prologue(ctx);
6240 nested_barrier = false;
6241 } else {
6242 nested_barrier = true;
6243 }
6244
6245 /* Number of patches / primitives */
6246 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6247 } else {
6248 /* Number of vertices */
6249 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 0, 8);
6250 nested_barrier = false;
6251 }
6252
6253 LLVMValueRef ena =
6254 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6255 ac_get_thread_id(&ctx->ac), num_threads, "");
6256
6257 ctx->merged_wrap_if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
6258 ctx->merged_wrap_if_label = 11500;
6259 ac_build_ifcc(&ctx->ac, ena, ctx->merged_wrap_if_label);
6260
6261 if (nested_barrier) {
6262 /* Execute a barrier before the second shader in
6263 * a merged shader.
6264 *
6265 * Execute the barrier inside the conditional block,
6266 * so that empty waves can jump directly to s_endpgm,
6267 * which will also signal the barrier.
6268 *
6269 * This is possible in gfx9, because an empty wave
6270 * for the second shader does not participate in
6271 * the epilogue. With NGG, empty waves may still
6272 * be required to export data (e.g. GS output vertices),
6273 * so we cannot let them exit early.
6274 *
6275 * If the shader is TCS and the TCS epilog is present
6276 * and contains a barrier, it will wait there and then
6277 * reach s_endpgm.
6278 */
6279 si_llvm_emit_barrier(NULL, bld_base, NULL);
6280 }
6281 }
6282 }
6283
6284 if (sel->force_correct_derivs_after_kill) {
6285 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6286 /* true = don't kill. */
6287 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6288 ctx->postponed_kill);
6289 }
6290
6291 if (sel->tokens) {
6292 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6293 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6294 return false;
6295 }
6296 } else {
6297 if (!si_nir_build_llvm(ctx, sel->nir)) {
6298 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6299 return false;
6300 }
6301 }
6302
6303 si_llvm_build_ret(ctx, ctx->return_value);
6304 return true;
6305 }
6306
6307 /**
6308 * Compute the VS prolog key, which contains all the information needed to
6309 * build the VS prolog function, and set shader->info bits where needed.
6310 *
6311 * \param info Shader info of the vertex shader.
6312 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6313 * \param prolog_key Key of the VS prolog
6314 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6315 * \param key Output shader part key.
6316 */
6317 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6318 unsigned num_input_sgprs,
6319 const struct si_vs_prolog_bits *prolog_key,
6320 struct si_shader *shader_out,
6321 union si_shader_part_key *key)
6322 {
6323 memset(key, 0, sizeof(*key));
6324 key->vs_prolog.states = *prolog_key;
6325 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6326 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6327 key->vs_prolog.as_ls = shader_out->key.as_ls;
6328 key->vs_prolog.as_es = shader_out->key.as_es;
6329 key->vs_prolog.as_ngg = shader_out->key.as_ngg;
6330
6331 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6332 key->vs_prolog.as_ls = 1;
6333 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6334 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6335 key->vs_prolog.as_es = 1;
6336 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6337 } else if (shader_out->key.as_ngg) {
6338 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6339 }
6340
6341 /* Enable loading the InstanceID VGPR. */
6342 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6343
6344 if ((key->vs_prolog.states.instance_divisor_is_one |
6345 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6346 shader_out->info.uses_instanceid = true;
6347 }
6348
6349 /**
6350 * Compute the PS prolog key, which contains all the information needed to
6351 * build the PS prolog function, and set related bits in shader->config.
6352 */
6353 static void si_get_ps_prolog_key(struct si_shader *shader,
6354 union si_shader_part_key *key,
6355 bool separate_prolog)
6356 {
6357 struct tgsi_shader_info *info = &shader->selector->info;
6358
6359 memset(key, 0, sizeof(*key));
6360 key->ps_prolog.states = shader->key.part.ps.prolog;
6361 key->ps_prolog.colors_read = info->colors_read;
6362 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6363 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6364 key->ps_prolog.wqm = info->uses_derivatives &&
6365 (key->ps_prolog.colors_read ||
6366 key->ps_prolog.states.force_persp_sample_interp ||
6367 key->ps_prolog.states.force_linear_sample_interp ||
6368 key->ps_prolog.states.force_persp_center_interp ||
6369 key->ps_prolog.states.force_linear_center_interp ||
6370 key->ps_prolog.states.bc_optimize_for_persp ||
6371 key->ps_prolog.states.bc_optimize_for_linear);
6372 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6373
6374 if (info->colors_read) {
6375 unsigned *color = shader->selector->color_attr_index;
6376
6377 if (shader->key.part.ps.prolog.color_two_side) {
6378 /* BCOLORs are stored after the last input. */
6379 key->ps_prolog.num_interp_inputs = info->num_inputs;
6380 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6381 if (separate_prolog)
6382 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6383 }
6384
6385 for (unsigned i = 0; i < 2; i++) {
6386 unsigned interp = info->input_interpolate[color[i]];
6387 unsigned location = info->input_interpolate_loc[color[i]];
6388
6389 if (!(info->colors_read & (0xf << i*4)))
6390 continue;
6391
6392 key->ps_prolog.color_attr_index[i] = color[i];
6393
6394 if (shader->key.part.ps.prolog.flatshade_colors &&
6395 interp == TGSI_INTERPOLATE_COLOR)
6396 interp = TGSI_INTERPOLATE_CONSTANT;
6397
6398 switch (interp) {
6399 case TGSI_INTERPOLATE_CONSTANT:
6400 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6401 break;
6402 case TGSI_INTERPOLATE_PERSPECTIVE:
6403 case TGSI_INTERPOLATE_COLOR:
6404 /* Force the interpolation location for colors here. */
6405 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6406 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6407 if (shader->key.part.ps.prolog.force_persp_center_interp)
6408 location = TGSI_INTERPOLATE_LOC_CENTER;
6409
6410 switch (location) {
6411 case TGSI_INTERPOLATE_LOC_SAMPLE:
6412 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6413 if (separate_prolog) {
6414 shader->config.spi_ps_input_ena |=
6415 S_0286CC_PERSP_SAMPLE_ENA(1);
6416 }
6417 break;
6418 case TGSI_INTERPOLATE_LOC_CENTER:
6419 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6420 if (separate_prolog) {
6421 shader->config.spi_ps_input_ena |=
6422 S_0286CC_PERSP_CENTER_ENA(1);
6423 }
6424 break;
6425 case TGSI_INTERPOLATE_LOC_CENTROID:
6426 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6427 if (separate_prolog) {
6428 shader->config.spi_ps_input_ena |=
6429 S_0286CC_PERSP_CENTROID_ENA(1);
6430 }
6431 break;
6432 default:
6433 assert(0);
6434 }
6435 break;
6436 case TGSI_INTERPOLATE_LINEAR:
6437 /* Force the interpolation location for colors here. */
6438 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6439 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6440 if (shader->key.part.ps.prolog.force_linear_center_interp)
6441 location = TGSI_INTERPOLATE_LOC_CENTER;
6442
6443 /* The VGPR assignment for non-monolithic shaders
6444 * works because InitialPSInputAddr is set on the
6445 * main shader and PERSP_PULL_MODEL is never used.
6446 */
6447 switch (location) {
6448 case TGSI_INTERPOLATE_LOC_SAMPLE:
6449 key->ps_prolog.color_interp_vgpr_index[i] =
6450 separate_prolog ? 6 : 9;
6451 if (separate_prolog) {
6452 shader->config.spi_ps_input_ena |=
6453 S_0286CC_LINEAR_SAMPLE_ENA(1);
6454 }
6455 break;
6456 case TGSI_INTERPOLATE_LOC_CENTER:
6457 key->ps_prolog.color_interp_vgpr_index[i] =
6458 separate_prolog ? 8 : 11;
6459 if (separate_prolog) {
6460 shader->config.spi_ps_input_ena |=
6461 S_0286CC_LINEAR_CENTER_ENA(1);
6462 }
6463 break;
6464 case TGSI_INTERPOLATE_LOC_CENTROID:
6465 key->ps_prolog.color_interp_vgpr_index[i] =
6466 separate_prolog ? 10 : 13;
6467 if (separate_prolog) {
6468 shader->config.spi_ps_input_ena |=
6469 S_0286CC_LINEAR_CENTROID_ENA(1);
6470 }
6471 break;
6472 default:
6473 assert(0);
6474 }
6475 break;
6476 default:
6477 assert(0);
6478 }
6479 }
6480 }
6481 }
6482
6483 /**
6484 * Check whether a PS prolog is required based on the key.
6485 */
6486 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6487 {
6488 return key->ps_prolog.colors_read ||
6489 key->ps_prolog.states.force_persp_sample_interp ||
6490 key->ps_prolog.states.force_linear_sample_interp ||
6491 key->ps_prolog.states.force_persp_center_interp ||
6492 key->ps_prolog.states.force_linear_center_interp ||
6493 key->ps_prolog.states.bc_optimize_for_persp ||
6494 key->ps_prolog.states.bc_optimize_for_linear ||
6495 key->ps_prolog.states.poly_stipple ||
6496 key->ps_prolog.states.samplemask_log_ps_iter;
6497 }
6498
6499 /**
6500 * Compute the PS epilog key, which contains all the information needed to
6501 * build the PS epilog function.
6502 */
6503 static void si_get_ps_epilog_key(struct si_shader *shader,
6504 union si_shader_part_key *key)
6505 {
6506 struct tgsi_shader_info *info = &shader->selector->info;
6507 memset(key, 0, sizeof(*key));
6508 key->ps_epilog.colors_written = info->colors_written;
6509 key->ps_epilog.writes_z = info->writes_z;
6510 key->ps_epilog.writes_stencil = info->writes_stencil;
6511 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6512 key->ps_epilog.states = shader->key.part.ps.epilog;
6513 }
6514
6515 /**
6516 * Build the GS prolog function. Rotate the input vertices for triangle strips
6517 * with adjacency.
6518 */
6519 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6520 union si_shader_part_key *key)
6521 {
6522 unsigned num_sgprs, num_vgprs;
6523 struct si_function_info fninfo;
6524 LLVMBuilderRef builder = ctx->ac.builder;
6525 LLVMTypeRef returns[48];
6526 LLVMValueRef func, ret;
6527
6528 si_init_function_info(&fninfo);
6529
6530 if (ctx->screen->info.chip_class >= GFX9) {
6531 if (key->gs_prolog.states.gfx9_prev_is_vs)
6532 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6533 else
6534 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6535 num_vgprs = 5; /* ES inputs are not needed by GS */
6536 } else {
6537 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6538 num_vgprs = 8;
6539 }
6540
6541 for (unsigned i = 0; i < num_sgprs; ++i) {
6542 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6543 returns[i] = ctx->i32;
6544 }
6545
6546 for (unsigned i = 0; i < num_vgprs; ++i) {
6547 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6548 returns[num_sgprs + i] = ctx->f32;
6549 }
6550
6551 /* Create the function. */
6552 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6553 &fninfo, 0);
6554 func = ctx->main_fn;
6555
6556 /* Set the full EXEC mask for the prolog, because we are only fiddling
6557 * with registers here. The main shader part will set the correct EXEC
6558 * mask.
6559 */
6560 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6561 ac_init_exec_full_mask(&ctx->ac);
6562
6563 /* Copy inputs to outputs. This should be no-op, as the registers match,
6564 * but it will prevent the compiler from overwriting them unintentionally.
6565 */
6566 ret = ctx->return_value;
6567 for (unsigned i = 0; i < num_sgprs; i++) {
6568 LLVMValueRef p = LLVMGetParam(func, i);
6569 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6570 }
6571 for (unsigned i = 0; i < num_vgprs; i++) {
6572 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6573 p = ac_to_float(&ctx->ac, p);
6574 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6575 }
6576
6577 if (key->gs_prolog.states.tri_strip_adj_fix) {
6578 /* Remap the input vertices for every other primitive. */
6579 const unsigned gfx6_vtx_params[6] = {
6580 num_sgprs,
6581 num_sgprs + 1,
6582 num_sgprs + 3,
6583 num_sgprs + 4,
6584 num_sgprs + 5,
6585 num_sgprs + 6
6586 };
6587 const unsigned gfx9_vtx_params[3] = {
6588 num_sgprs,
6589 num_sgprs + 1,
6590 num_sgprs + 4,
6591 };
6592 LLVMValueRef vtx_in[6], vtx_out[6];
6593 LLVMValueRef prim_id, rotate;
6594
6595 if (ctx->screen->info.chip_class >= GFX9) {
6596 for (unsigned i = 0; i < 3; i++) {
6597 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6598 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6599 }
6600 } else {
6601 for (unsigned i = 0; i < 6; i++)
6602 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6603 }
6604
6605 prim_id = LLVMGetParam(func, num_sgprs + 2);
6606 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6607
6608 for (unsigned i = 0; i < 6; ++i) {
6609 LLVMValueRef base, rotated;
6610 base = vtx_in[i];
6611 rotated = vtx_in[(i + 4) % 6];
6612 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6613 }
6614
6615 if (ctx->screen->info.chip_class >= GFX9) {
6616 for (unsigned i = 0; i < 3; i++) {
6617 LLVMValueRef hi, out;
6618
6619 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6620 LLVMConstInt(ctx->i32, 16, 0), "");
6621 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6622 out = ac_to_float(&ctx->ac, out);
6623 ret = LLVMBuildInsertValue(builder, ret, out,
6624 gfx9_vtx_params[i], "");
6625 }
6626 } else {
6627 for (unsigned i = 0; i < 6; i++) {
6628 LLVMValueRef out;
6629
6630 out = ac_to_float(&ctx->ac, vtx_out[i]);
6631 ret = LLVMBuildInsertValue(builder, ret, out,
6632 gfx6_vtx_params[i], "");
6633 }
6634 }
6635 }
6636
6637 LLVMBuildRet(builder, ret);
6638 }
6639
6640 /**
6641 * Given a list of shader part functions, build a wrapper function that
6642 * runs them in sequence to form a monolithic shader.
6643 */
6644 static void si_build_wrapper_function(struct si_shader_context *ctx,
6645 LLVMValueRef *parts,
6646 unsigned num_parts,
6647 unsigned main_part,
6648 unsigned next_shader_first_part)
6649 {
6650 LLVMBuilderRef builder = ctx->ac.builder;
6651 /* PS epilog has one arg per color component; gfx9 merged shader
6652 * prologs need to forward 32 user SGPRs.
6653 */
6654 struct si_function_info fninfo;
6655 LLVMValueRef initial[64], out[64];
6656 LLVMTypeRef function_type;
6657 unsigned num_first_params;
6658 unsigned num_out, initial_num_out;
6659 ASSERTED unsigned num_out_sgpr; /* used in debug checks */
6660 ASSERTED unsigned initial_num_out_sgpr; /* used in debug checks */
6661 unsigned num_sgprs, num_vgprs;
6662 unsigned gprs;
6663
6664 si_init_function_info(&fninfo);
6665
6666 for (unsigned i = 0; i < num_parts; ++i) {
6667 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6668 AC_FUNC_ATTR_ALWAYSINLINE);
6669 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6670 }
6671
6672 /* The parameters of the wrapper function correspond to those of the
6673 * first part in terms of SGPRs and VGPRs, but we use the types of the
6674 * main part to get the right types. This is relevant for the
6675 * dereferenceable attribute on descriptor table pointers.
6676 */
6677 num_sgprs = 0;
6678 num_vgprs = 0;
6679
6680 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6681 num_first_params = LLVMCountParamTypes(function_type);
6682
6683 for (unsigned i = 0; i < num_first_params; ++i) {
6684 LLVMValueRef param = LLVMGetParam(parts[0], i);
6685
6686 if (ac_is_sgpr_param(param)) {
6687 assert(num_vgprs == 0);
6688 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6689 } else {
6690 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6691 }
6692 }
6693
6694 gprs = 0;
6695 while (gprs < num_sgprs + num_vgprs) {
6696 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6697 LLVMTypeRef type = LLVMTypeOf(param);
6698 unsigned size = ac_get_type_size(type) / 4;
6699
6700 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6701
6702 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6703 assert(gprs + size <= num_sgprs + num_vgprs &&
6704 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6705
6706 gprs += size;
6707 }
6708
6709 /* Prepare the return type. */
6710 unsigned num_returns = 0;
6711 LLVMTypeRef returns[32], last_func_type, return_type;
6712
6713 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6714 return_type = LLVMGetReturnType(last_func_type);
6715
6716 switch (LLVMGetTypeKind(return_type)) {
6717 case LLVMStructTypeKind:
6718 num_returns = LLVMCountStructElementTypes(return_type);
6719 assert(num_returns <= ARRAY_SIZE(returns));
6720 LLVMGetStructElementTypes(return_type, returns);
6721 break;
6722 case LLVMVoidTypeKind:
6723 break;
6724 default:
6725 unreachable("unexpected type");
6726 }
6727
6728 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6729 si_get_max_workgroup_size(ctx->shader));
6730
6731 if (is_merged_shader(ctx))
6732 ac_init_exec_full_mask(&ctx->ac);
6733
6734 /* Record the arguments of the function as if they were an output of
6735 * a previous part.
6736 */
6737 num_out = 0;
6738 num_out_sgpr = 0;
6739
6740 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6741 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6742 LLVMTypeRef param_type = LLVMTypeOf(param);
6743 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6744 unsigned size = ac_get_type_size(param_type) / 4;
6745
6746 if (size == 1) {
6747 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6748 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6749 param_type = ctx->i32;
6750 }
6751
6752 if (param_type != out_type)
6753 param = LLVMBuildBitCast(builder, param, out_type, "");
6754 out[num_out++] = param;
6755 } else {
6756 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6757
6758 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6759 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6760 param_type = ctx->i64;
6761 }
6762
6763 if (param_type != vector_type)
6764 param = LLVMBuildBitCast(builder, param, vector_type, "");
6765
6766 for (unsigned j = 0; j < size; ++j)
6767 out[num_out++] = LLVMBuildExtractElement(
6768 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6769 }
6770
6771 if (i < fninfo.num_sgpr_params)
6772 num_out_sgpr = num_out;
6773 }
6774
6775 memcpy(initial, out, sizeof(out));
6776 initial_num_out = num_out;
6777 initial_num_out_sgpr = num_out_sgpr;
6778
6779 /* Now chain the parts. */
6780 LLVMValueRef ret = NULL;
6781 for (unsigned part = 0; part < num_parts; ++part) {
6782 LLVMValueRef in[48];
6783 LLVMTypeRef ret_type;
6784 unsigned out_idx = 0;
6785 unsigned num_params = LLVMCountParams(parts[part]);
6786
6787 /* Merged shaders are executed conditionally depending
6788 * on the number of enabled threads passed in the input SGPRs. */
6789 if (is_multi_part_shader(ctx) && part == 0) {
6790 LLVMValueRef ena, count = initial[3];
6791
6792 count = LLVMBuildAnd(builder, count,
6793 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6794 ena = LLVMBuildICmp(builder, LLVMIntULT,
6795 ac_get_thread_id(&ctx->ac), count, "");
6796 ac_build_ifcc(&ctx->ac, ena, 6506);
6797 }
6798
6799 /* Derive arguments for the next part from outputs of the
6800 * previous one.
6801 */
6802 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6803 LLVMValueRef param;
6804 LLVMTypeRef param_type;
6805 bool is_sgpr;
6806 unsigned param_size;
6807 LLVMValueRef arg = NULL;
6808
6809 param = LLVMGetParam(parts[part], param_idx);
6810 param_type = LLVMTypeOf(param);
6811 param_size = ac_get_type_size(param_type) / 4;
6812 is_sgpr = ac_is_sgpr_param(param);
6813
6814 if (is_sgpr) {
6815 ac_add_function_attr(ctx->ac.context, parts[part],
6816 param_idx + 1, AC_FUNC_ATTR_INREG);
6817 } else if (out_idx < num_out_sgpr) {
6818 /* Skip returned SGPRs the current part doesn't
6819 * declare on the input. */
6820 out_idx = num_out_sgpr;
6821 }
6822
6823 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6824
6825 if (param_size == 1)
6826 arg = out[out_idx];
6827 else
6828 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6829
6830 if (LLVMTypeOf(arg) != param_type) {
6831 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6832 if (LLVMGetPointerAddressSpace(param_type) ==
6833 AC_ADDR_SPACE_CONST_32BIT) {
6834 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6835 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6836 } else {
6837 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6838 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6839 }
6840 } else {
6841 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6842 }
6843 }
6844
6845 in[param_idx] = arg;
6846 out_idx += param_size;
6847 }
6848
6849 ret = ac_build_call(&ctx->ac, parts[part], in, num_params);
6850
6851 if (is_multi_part_shader(ctx) &&
6852 part + 1 == next_shader_first_part) {
6853 ac_build_endif(&ctx->ac, 6506);
6854
6855 /* The second half of the merged shader should use
6856 * the inputs from the toplevel (wrapper) function,
6857 * not the return value from the last call.
6858 *
6859 * That's because the last call was executed condi-
6860 * tionally, so we can't consume it in the main
6861 * block.
6862 */
6863 memcpy(out, initial, sizeof(initial));
6864 num_out = initial_num_out;
6865 num_out_sgpr = initial_num_out_sgpr;
6866 continue;
6867 }
6868
6869 /* Extract the returned GPRs. */
6870 ret_type = LLVMTypeOf(ret);
6871 num_out = 0;
6872 num_out_sgpr = 0;
6873
6874 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6875 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6876
6877 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6878
6879 for (unsigned i = 0; i < ret_size; ++i) {
6880 LLVMValueRef val =
6881 LLVMBuildExtractValue(builder, ret, i, "");
6882
6883 assert(num_out < ARRAY_SIZE(out));
6884 out[num_out++] = val;
6885
6886 if (LLVMTypeOf(val) == ctx->i32) {
6887 assert(num_out_sgpr + 1 == num_out);
6888 num_out_sgpr = num_out;
6889 }
6890 }
6891 }
6892 }
6893
6894 /* Return the value from the last part. */
6895 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6896 LLVMBuildRetVoid(builder);
6897 else
6898 LLVMBuildRet(builder, ret);
6899 }
6900
6901 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6902 struct si_shader_selector *sel)
6903 {
6904 if (!compiler->low_opt_passes)
6905 return false;
6906
6907 /* Assume a slow CPU. */
6908 assert(!sel->screen->info.has_dedicated_vram &&
6909 sel->screen->info.chip_class <= GFX8);
6910
6911 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6912 * buffer stores. */
6913 return sel->type == PIPE_SHADER_COMPUTE &&
6914 sel->info.num_memory_instructions > 1000;
6915 }
6916
6917 int si_compile_tgsi_shader(struct si_screen *sscreen,
6918 struct ac_llvm_compiler *compiler,
6919 struct si_shader *shader,
6920 struct pipe_debug_callback *debug)
6921 {
6922 struct si_shader_selector *sel = shader->selector;
6923 struct si_shader_context ctx;
6924 int r = -1;
6925
6926 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6927 * conversion fails. */
6928 if (si_can_dump_shader(sscreen, sel->type) &&
6929 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6930 if (sel->tokens)
6931 tgsi_dump(sel->tokens, 0);
6932 else
6933 nir_print_shader(sel->nir, stderr);
6934 si_dump_streamout(&sel->so);
6935 }
6936
6937 si_init_shader_ctx(&ctx, sscreen, compiler, si_get_shader_wave_size(shader),
6938 sel->nir != NULL);
6939 si_llvm_context_set_ir(&ctx, shader);
6940
6941 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6942 sizeof(shader->info.vs_output_param_offset));
6943
6944 shader->info.uses_instanceid = sel->info.uses_instanceid;
6945
6946 if (!si_compile_tgsi_main(&ctx)) {
6947 si_llvm_dispose(&ctx);
6948 return -1;
6949 }
6950
6951 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6952 LLVMValueRef parts[2];
6953 bool need_prolog = sel->vs_needs_prolog;
6954
6955 parts[1] = ctx.main_fn;
6956
6957 if (need_prolog) {
6958 union si_shader_part_key prolog_key;
6959 si_get_vs_prolog_key(&sel->info,
6960 shader->info.num_input_sgprs,
6961 &shader->key.part.vs.prolog,
6962 shader, &prolog_key);
6963 si_build_vs_prolog_function(&ctx, &prolog_key);
6964 parts[0] = ctx.main_fn;
6965 }
6966
6967 si_build_wrapper_function(&ctx, parts + !need_prolog,
6968 1 + need_prolog, need_prolog, 0);
6969
6970 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
6971 si_build_prim_discard_compute_shader(&ctx);
6972 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6973 if (sscreen->info.chip_class >= GFX9) {
6974 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6975 LLVMValueRef parts[4];
6976 bool vs_needs_prolog =
6977 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6978
6979 /* TCS main part */
6980 parts[2] = ctx.main_fn;
6981
6982 /* TCS epilog */
6983 union si_shader_part_key tcs_epilog_key;
6984 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6985 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6986 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6987 parts[3] = ctx.main_fn;
6988
6989 /* VS as LS main part */
6990 struct si_shader shader_ls = {};
6991 shader_ls.selector = ls;
6992 shader_ls.key.as_ls = 1;
6993 shader_ls.key.mono = shader->key.mono;
6994 shader_ls.key.opt = shader->key.opt;
6995 shader_ls.is_monolithic = true;
6996 si_llvm_context_set_ir(&ctx, &shader_ls);
6997
6998 if (!si_compile_tgsi_main(&ctx)) {
6999 si_llvm_dispose(&ctx);
7000 return -1;
7001 }
7002 shader->info.uses_instanceid |= ls->info.uses_instanceid;
7003 parts[1] = ctx.main_fn;
7004
7005 /* LS prolog */
7006 if (vs_needs_prolog) {
7007 union si_shader_part_key vs_prolog_key;
7008 si_get_vs_prolog_key(&ls->info,
7009 shader_ls.info.num_input_sgprs,
7010 &shader->key.part.tcs.ls_prolog,
7011 shader, &vs_prolog_key);
7012 vs_prolog_key.vs_prolog.is_monolithic = true;
7013 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7014 parts[0] = ctx.main_fn;
7015 }
7016
7017 /* Reset the shader context. */
7018 ctx.shader = shader;
7019 ctx.type = PIPE_SHADER_TESS_CTRL;
7020
7021 si_build_wrapper_function(&ctx,
7022 parts + !vs_needs_prolog,
7023 4 - !vs_needs_prolog, vs_needs_prolog,
7024 vs_needs_prolog ? 2 : 1);
7025 } else {
7026 LLVMValueRef parts[2];
7027 union si_shader_part_key epilog_key;
7028
7029 parts[0] = ctx.main_fn;
7030
7031 memset(&epilog_key, 0, sizeof(epilog_key));
7032 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7033 si_build_tcs_epilog_function(&ctx, &epilog_key);
7034 parts[1] = ctx.main_fn;
7035
7036 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
7037 }
7038 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7039 if (ctx.screen->info.chip_class >= GFX9) {
7040 struct si_shader_selector *es = shader->key.part.gs.es;
7041 LLVMValueRef es_prolog = NULL;
7042 LLVMValueRef es_main = NULL;
7043 LLVMValueRef gs_prolog = NULL;
7044 LLVMValueRef gs_main = ctx.main_fn;
7045
7046 /* GS prolog */
7047 union si_shader_part_key gs_prolog_key;
7048 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
7049 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7050 gs_prolog_key.gs_prolog.is_monolithic = true;
7051 gs_prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7052 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
7053 gs_prolog = ctx.main_fn;
7054
7055 /* ES main part */
7056 struct si_shader shader_es = {};
7057 shader_es.selector = es;
7058 shader_es.key.as_es = 1;
7059 shader_es.key.as_ngg = shader->key.as_ngg;
7060 shader_es.key.mono = shader->key.mono;
7061 shader_es.key.opt = shader->key.opt;
7062 shader_es.is_monolithic = true;
7063 si_llvm_context_set_ir(&ctx, &shader_es);
7064
7065 if (!si_compile_tgsi_main(&ctx)) {
7066 si_llvm_dispose(&ctx);
7067 return -1;
7068 }
7069 shader->info.uses_instanceid |= es->info.uses_instanceid;
7070 es_main = ctx.main_fn;
7071
7072 /* ES prolog */
7073 if (es->vs_needs_prolog) {
7074 union si_shader_part_key vs_prolog_key;
7075 si_get_vs_prolog_key(&es->info,
7076 shader_es.info.num_input_sgprs,
7077 &shader->key.part.gs.vs_prolog,
7078 shader, &vs_prolog_key);
7079 vs_prolog_key.vs_prolog.is_monolithic = true;
7080 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7081 es_prolog = ctx.main_fn;
7082 }
7083
7084 /* Reset the shader context. */
7085 ctx.shader = shader;
7086 ctx.type = PIPE_SHADER_GEOMETRY;
7087
7088 /* Prepare the array of shader parts. */
7089 LLVMValueRef parts[4];
7090 unsigned num_parts = 0, main_part, next_first_part;
7091
7092 if (es_prolog)
7093 parts[num_parts++] = es_prolog;
7094
7095 parts[main_part = num_parts++] = es_main;
7096 parts[next_first_part = num_parts++] = gs_prolog;
7097 parts[num_parts++] = gs_main;
7098
7099 si_build_wrapper_function(&ctx, parts, num_parts,
7100 main_part, next_first_part);
7101 } else {
7102 LLVMValueRef parts[2];
7103 union si_shader_part_key prolog_key;
7104
7105 parts[1] = ctx.main_fn;
7106
7107 memset(&prolog_key, 0, sizeof(prolog_key));
7108 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7109 si_build_gs_prolog_function(&ctx, &prolog_key);
7110 parts[0] = ctx.main_fn;
7111
7112 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
7113 }
7114 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7115 LLVMValueRef parts[3];
7116 union si_shader_part_key prolog_key;
7117 union si_shader_part_key epilog_key;
7118 bool need_prolog;
7119
7120 si_get_ps_prolog_key(shader, &prolog_key, false);
7121 need_prolog = si_need_ps_prolog(&prolog_key);
7122
7123 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7124
7125 if (need_prolog) {
7126 si_build_ps_prolog_function(&ctx, &prolog_key);
7127 parts[0] = ctx.main_fn;
7128 }
7129
7130 si_get_ps_epilog_key(shader, &epilog_key);
7131 si_build_ps_epilog_function(&ctx, &epilog_key);
7132 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7133
7134 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
7135 need_prolog ? 1 : 0, 0);
7136 }
7137
7138 si_llvm_optimize_module(&ctx);
7139
7140 /* Post-optimization transformations and analysis. */
7141 si_optimize_vs_outputs(&ctx);
7142
7143 if ((debug && debug->debug_message) ||
7144 si_can_dump_shader(sscreen, ctx.type)) {
7145 ctx.shader->info.private_mem_vgprs =
7146 ac_count_scratch_private_memory(ctx.main_fn);
7147 }
7148
7149 /* Make sure the input is a pointer and not integer followed by inttoptr. */
7150 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
7151 LLVMPointerTypeKind);
7152
7153 /* Compile to bytecode. */
7154 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
7155 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7156 si_get_shader_name(shader),
7157 si_should_optimize_less(compiler, shader->selector));
7158 si_llvm_dispose(&ctx);
7159 if (r) {
7160 fprintf(stderr, "LLVM failed to compile shader\n");
7161 return r;
7162 }
7163
7164 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7165 * LLVM 3.9svn has this bug.
7166 */
7167 if (sel->type == PIPE_SHADER_COMPUTE) {
7168 unsigned wave_size = sscreen->compute_wave_size;
7169 unsigned max_vgprs = 256;
7170 unsigned max_sgprs = sscreen->info.chip_class >= GFX8 ? 800 : 512;
7171 unsigned max_sgprs_per_wave = 128;
7172 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7173 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7174 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7175
7176 max_vgprs = max_vgprs / min_waves_per_simd;
7177 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7178
7179 if (shader->config.num_sgprs > max_sgprs ||
7180 shader->config.num_vgprs > max_vgprs) {
7181 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7182 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7183 shader->config.num_sgprs, shader->config.num_vgprs,
7184 max_sgprs, max_vgprs);
7185
7186 /* Just terminate the process, because dependent
7187 * shaders can hang due to bad input data, but use
7188 * the env var to allow shader-db to work.
7189 */
7190 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7191 abort();
7192 }
7193 }
7194
7195 /* Add the scratch offset to input SGPRs. */
7196 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
7197 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7198
7199 /* Calculate the number of fragment input VGPRs. */
7200 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7201 shader->info.num_input_vgprs = 0;
7202 shader->info.face_vgpr_index = -1;
7203 shader->info.ancillary_vgpr_index = -1;
7204
7205 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7206 shader->info.num_input_vgprs += 2;
7207 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7208 shader->info.num_input_vgprs += 2;
7209 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7210 shader->info.num_input_vgprs += 2;
7211 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7212 shader->info.num_input_vgprs += 3;
7213 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7214 shader->info.num_input_vgprs += 2;
7215 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7216 shader->info.num_input_vgprs += 2;
7217 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7218 shader->info.num_input_vgprs += 2;
7219 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7220 shader->info.num_input_vgprs += 1;
7221 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7222 shader->info.num_input_vgprs += 1;
7223 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7224 shader->info.num_input_vgprs += 1;
7225 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7226 shader->info.num_input_vgprs += 1;
7227 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7228 shader->info.num_input_vgprs += 1;
7229 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7230 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7231 shader->info.num_input_vgprs += 1;
7232 }
7233 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7234 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7235 shader->info.num_input_vgprs += 1;
7236 }
7237 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7238 shader->info.num_input_vgprs += 1;
7239 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7240 shader->info.num_input_vgprs += 1;
7241 }
7242
7243 si_calculate_max_simd_waves(shader);
7244 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
7245 return 0;
7246 }
7247
7248 /**
7249 * Create, compile and return a shader part (prolog or epilog).
7250 *
7251 * \param sscreen screen
7252 * \param list list of shader parts of the same category
7253 * \param type shader type
7254 * \param key shader part key
7255 * \param prolog whether the part being requested is a prolog
7256 * \param tm LLVM target machine
7257 * \param debug debug callback
7258 * \param build the callback responsible for building the main function
7259 * \return non-NULL on success
7260 */
7261 static struct si_shader_part *
7262 si_get_shader_part(struct si_screen *sscreen,
7263 struct si_shader_part **list,
7264 enum pipe_shader_type type,
7265 bool prolog,
7266 union si_shader_part_key *key,
7267 struct ac_llvm_compiler *compiler,
7268 struct pipe_debug_callback *debug,
7269 void (*build)(struct si_shader_context *,
7270 union si_shader_part_key *),
7271 const char *name)
7272 {
7273 struct si_shader_part *result;
7274
7275 mtx_lock(&sscreen->shader_parts_mutex);
7276
7277 /* Find existing. */
7278 for (result = *list; result; result = result->next) {
7279 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7280 mtx_unlock(&sscreen->shader_parts_mutex);
7281 return result;
7282 }
7283 }
7284
7285 /* Compile a new one. */
7286 result = CALLOC_STRUCT(si_shader_part);
7287 result->key = *key;
7288
7289 struct si_shader shader = {};
7290
7291 switch (type) {
7292 case PIPE_SHADER_VERTEX:
7293 shader.key.as_ls = key->vs_prolog.as_ls;
7294 shader.key.as_es = key->vs_prolog.as_es;
7295 shader.key.as_ngg = key->vs_prolog.as_ngg;
7296 break;
7297 case PIPE_SHADER_TESS_CTRL:
7298 assert(!prolog);
7299 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7300 break;
7301 case PIPE_SHADER_GEOMETRY:
7302 assert(prolog);
7303 shader.key.as_ngg = key->gs_prolog.as_ngg;
7304 break;
7305 case PIPE_SHADER_FRAGMENT:
7306 if (prolog)
7307 shader.key.part.ps.prolog = key->ps_prolog.states;
7308 else
7309 shader.key.part.ps.epilog = key->ps_epilog.states;
7310 break;
7311 default:
7312 unreachable("bad shader part");
7313 }
7314
7315 struct si_shader_context ctx;
7316 si_init_shader_ctx(&ctx, sscreen, compiler,
7317 si_get_wave_size(sscreen, type, shader.key.as_ngg,
7318 shader.key.as_es),
7319 false);
7320 ctx.shader = &shader;
7321 ctx.type = type;
7322
7323 build(&ctx, key);
7324
7325 /* Compile. */
7326 si_llvm_optimize_module(&ctx);
7327
7328 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7329 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7330 name, false)) {
7331 FREE(result);
7332 result = NULL;
7333 goto out;
7334 }
7335
7336 result->next = *list;
7337 *list = result;
7338
7339 out:
7340 si_llvm_dispose(&ctx);
7341 mtx_unlock(&sscreen->shader_parts_mutex);
7342 return result;
7343 }
7344
7345 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7346 {
7347 LLVMValueRef ptr[2], list;
7348 bool merged_shader = is_merged_shader(ctx);
7349
7350 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7351 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7352 ac_array_in_const32_addr_space(ctx->v4i32), "");
7353 return list;
7354 }
7355
7356 /**
7357 * Build the vertex shader prolog function.
7358 *
7359 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7360 * All inputs are returned unmodified. The vertex load indices are
7361 * stored after them, which will be used by the API VS for fetching inputs.
7362 *
7363 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7364 * input_v0,
7365 * input_v1,
7366 * input_v2,
7367 * input_v3,
7368 * (VertexID + BaseVertex),
7369 * (InstanceID + StartInstance),
7370 * (InstanceID / 2 + StartInstance)
7371 */
7372 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7373 union si_shader_part_key *key)
7374 {
7375 struct si_function_info fninfo;
7376 LLVMTypeRef *returns;
7377 LLVMValueRef ret, func;
7378 int num_returns, i;
7379 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7380 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7381 LLVMValueRef input_vgprs[9];
7382 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7383 num_input_vgprs;
7384 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7385
7386 si_init_function_info(&fninfo);
7387
7388 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7389 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7390 sizeof(LLVMTypeRef));
7391 num_returns = 0;
7392
7393 /* Declare input and output SGPRs. */
7394 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7395 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7396 returns[num_returns++] = ctx->i32;
7397 }
7398
7399 /* Preloaded VGPRs (outputs must be floats) */
7400 for (i = 0; i < num_input_vgprs; i++) {
7401 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7402 returns[num_returns++] = ctx->f32;
7403 }
7404
7405 /* Vertex load indices. */
7406 for (i = 0; i <= key->vs_prolog.last_input; i++)
7407 returns[num_returns++] = ctx->f32;
7408
7409 /* Create the function. */
7410 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7411 func = ctx->main_fn;
7412
7413 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7414 if (!key->vs_prolog.is_monolithic)
7415 si_init_exec_from_input(ctx, 3, 0);
7416
7417 if (key->vs_prolog.as_ls &&
7418 ctx->screen->info.has_ls_vgpr_init_bug) {
7419 /* If there are no HS threads, SPI loads the LS VGPRs
7420 * starting at VGPR 0. Shift them back to where they
7421 * belong.
7422 */
7423 LLVMValueRef has_hs_threads =
7424 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7425 si_unpack_param(ctx, 3, 8, 8),
7426 ctx->i32_0, "");
7427
7428 for (i = 4; i > 0; --i) {
7429 input_vgprs[i + 1] =
7430 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7431 input_vgprs[i + 1],
7432 input_vgprs[i - 1], "");
7433 }
7434 }
7435 }
7436
7437 unsigned vertex_id_vgpr = first_vs_vgpr;
7438 unsigned instance_id_vgpr =
7439 ctx->screen->info.chip_class >= GFX10 ?
7440 first_vs_vgpr + 3 :
7441 first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7442
7443 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7444 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7445
7446 /* InstanceID = VertexID >> 16;
7447 * VertexID = VertexID & 0xffff;
7448 */
7449 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7450 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7451 LLVMConstInt(ctx->i32, 16, 0), "");
7452 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7453 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7454 }
7455
7456 /* Copy inputs to outputs. This should be no-op, as the registers match,
7457 * but it will prevent the compiler from overwriting them unintentionally.
7458 */
7459 ret = ctx->return_value;
7460 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7461 LLVMValueRef p = LLVMGetParam(func, i);
7462 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7463 }
7464 for (i = 0; i < num_input_vgprs; i++) {
7465 LLVMValueRef p = input_vgprs[i];
7466
7467 if (i == vertex_id_vgpr)
7468 p = ctx->abi.vertex_id;
7469 else if (i == instance_id_vgpr)
7470 p = ctx->abi.instance_id;
7471
7472 p = ac_to_float(&ctx->ac, p);
7473 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7474 key->vs_prolog.num_input_sgprs + i, "");
7475 }
7476
7477 LLVMValueRef original_ret = ret;
7478 bool wrapped = false;
7479 LLVMBasicBlockRef if_entry_block = NULL;
7480
7481 if (key->vs_prolog.is_monolithic && key->vs_prolog.as_ngg) {
7482 LLVMValueRef num_threads;
7483 LLVMValueRef ena;
7484
7485 num_threads = si_unpack_param(ctx, 3, 0, 8);
7486 ena = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
7487 ac_get_thread_id(&ctx->ac), num_threads, "");
7488 if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
7489 ac_build_ifcc(&ctx->ac, ena, 11501);
7490 wrapped = true;
7491 }
7492
7493 /* Compute vertex load indices from instance divisors. */
7494 LLVMValueRef instance_divisor_constbuf = NULL;
7495
7496 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7497 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7498 LLVMValueRef buf_index =
7499 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7500 instance_divisor_constbuf =
7501 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7502 }
7503
7504 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7505 bool divisor_is_one =
7506 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7507 bool divisor_is_fetched =
7508 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7509 LLVMValueRef index = NULL;
7510
7511 if (divisor_is_one) {
7512 index = ctx->abi.instance_id;
7513 } else if (divisor_is_fetched) {
7514 LLVMValueRef udiv_factors[4];
7515
7516 for (unsigned j = 0; j < 4; j++) {
7517 udiv_factors[j] =
7518 buffer_load_const(ctx, instance_divisor_constbuf,
7519 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7520 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7521 }
7522 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7523 * Such InstanceID might not be achievable in a reasonable time though.
7524 */
7525 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7526 udiv_factors[0], udiv_factors[1],
7527 udiv_factors[2], udiv_factors[3]);
7528 }
7529
7530 if (divisor_is_one || divisor_is_fetched) {
7531 /* Add StartInstance. */
7532 index = LLVMBuildAdd(ctx->ac.builder, index,
7533 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7534 SI_SGPR_START_INSTANCE), "");
7535 } else {
7536 /* VertexID + BaseVertex */
7537 index = LLVMBuildAdd(ctx->ac.builder,
7538 ctx->abi.vertex_id,
7539 LLVMGetParam(func, user_sgpr_base +
7540 SI_SGPR_BASE_VERTEX), "");
7541 }
7542
7543 index = ac_to_float(&ctx->ac, index);
7544 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7545 fninfo.num_params + i, "");
7546 }
7547
7548 if (wrapped) {
7549 LLVMBasicBlockRef bbs[2] = {
7550 LLVMGetInsertBlock(ctx->ac.builder),
7551 if_entry_block,
7552 };
7553 ac_build_endif(&ctx->ac, 11501);
7554
7555 LLVMValueRef values[2] = {
7556 ret,
7557 original_ret
7558 };
7559 ret = ac_build_phi(&ctx->ac, LLVMTypeOf(ret), 2, values, bbs);
7560 }
7561
7562 si_llvm_build_ret(ctx, ret);
7563 }
7564
7565 static bool si_get_vs_prolog(struct si_screen *sscreen,
7566 struct ac_llvm_compiler *compiler,
7567 struct si_shader *shader,
7568 struct pipe_debug_callback *debug,
7569 struct si_shader *main_part,
7570 const struct si_vs_prolog_bits *key)
7571 {
7572 struct si_shader_selector *vs = main_part->selector;
7573
7574 if (!si_vs_needs_prolog(vs, key))
7575 return true;
7576
7577 /* Get the prolog. */
7578 union si_shader_part_key prolog_key;
7579 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7580 key, shader, &prolog_key);
7581
7582 shader->prolog =
7583 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7584 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7585 debug, si_build_vs_prolog_function,
7586 "Vertex Shader Prolog");
7587 return shader->prolog != NULL;
7588 }
7589
7590 /**
7591 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7592 */
7593 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7594 struct ac_llvm_compiler *compiler,
7595 struct si_shader *shader,
7596 struct pipe_debug_callback *debug)
7597 {
7598 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7599 &shader->key.part.vs.prolog);
7600 }
7601
7602 /**
7603 * Compile the TCS epilog function. This writes tesselation factors to memory
7604 * based on the output primitive type of the tesselator (determined by TES).
7605 */
7606 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7607 union si_shader_part_key *key)
7608 {
7609 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7610 struct si_function_info fninfo;
7611 LLVMValueRef func;
7612
7613 si_init_function_info(&fninfo);
7614
7615 if (ctx->screen->info.chip_class >= GFX9) {
7616 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7617 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7618 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7619 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7620 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7621 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7622 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7623 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7624 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7625 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7626 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7627 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7628 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7629 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7630 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7631 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7632 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7633 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7634 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7635 } else {
7636 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7637 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7638 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7639 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7640 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7641 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7642 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7643 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7644 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7645 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7646 }
7647
7648 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7649 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7650 unsigned tess_factors_idx =
7651 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7652 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7653 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7654
7655 for (unsigned i = 0; i < 6; i++)
7656 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7657
7658 /* Create the function. */
7659 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7660 ctx->screen->info.chip_class >= GFX7 ? 128 : 0);
7661 ac_declare_lds_as_pointer(&ctx->ac);
7662 func = ctx->main_fn;
7663
7664 LLVMValueRef invoc0_tess_factors[6];
7665 for (unsigned i = 0; i < 6; i++)
7666 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7667
7668 si_write_tess_factors(bld_base,
7669 LLVMGetParam(func, tess_factors_idx),
7670 LLVMGetParam(func, tess_factors_idx + 1),
7671 LLVMGetParam(func, tess_factors_idx + 2),
7672 invoc0_tess_factors, invoc0_tess_factors + 4);
7673
7674 LLVMBuildRetVoid(ctx->ac.builder);
7675 }
7676
7677 /**
7678 * Select and compile (or reuse) TCS parts (epilog).
7679 */
7680 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7681 struct ac_llvm_compiler *compiler,
7682 struct si_shader *shader,
7683 struct pipe_debug_callback *debug)
7684 {
7685 if (sscreen->info.chip_class >= GFX9) {
7686 struct si_shader *ls_main_part =
7687 shader->key.part.tcs.ls->main_shader_part_ls;
7688
7689 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7690 &shader->key.part.tcs.ls_prolog))
7691 return false;
7692
7693 shader->previous_stage = ls_main_part;
7694 }
7695
7696 /* Get the epilog. */
7697 union si_shader_part_key epilog_key;
7698 memset(&epilog_key, 0, sizeof(epilog_key));
7699 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7700
7701 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7702 PIPE_SHADER_TESS_CTRL, false,
7703 &epilog_key, compiler, debug,
7704 si_build_tcs_epilog_function,
7705 "Tessellation Control Shader Epilog");
7706 return shader->epilog != NULL;
7707 }
7708
7709 /**
7710 * Select and compile (or reuse) GS parts (prolog).
7711 */
7712 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7713 struct ac_llvm_compiler *compiler,
7714 struct si_shader *shader,
7715 struct pipe_debug_callback *debug)
7716 {
7717 if (sscreen->info.chip_class >= GFX9) {
7718 struct si_shader *es_main_part;
7719 enum pipe_shader_type es_type = shader->key.part.gs.es->type;
7720
7721 if (shader->key.as_ngg)
7722 es_main_part = shader->key.part.gs.es->main_shader_part_ngg_es;
7723 else
7724 es_main_part = shader->key.part.gs.es->main_shader_part_es;
7725
7726 if (es_type == PIPE_SHADER_VERTEX &&
7727 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7728 &shader->key.part.gs.vs_prolog))
7729 return false;
7730
7731 shader->previous_stage = es_main_part;
7732 }
7733
7734 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7735 return true;
7736
7737 union si_shader_part_key prolog_key;
7738 memset(&prolog_key, 0, sizeof(prolog_key));
7739 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7740 prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7741
7742 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7743 PIPE_SHADER_GEOMETRY, true,
7744 &prolog_key, compiler, debug,
7745 si_build_gs_prolog_function,
7746 "Geometry Shader Prolog");
7747 return shader->prolog2 != NULL;
7748 }
7749
7750 /**
7751 * Build the pixel shader prolog function. This handles:
7752 * - two-side color selection and interpolation
7753 * - overriding interpolation parameters for the API PS
7754 * - polygon stippling
7755 *
7756 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7757 * overriden by other states. (e.g. per-sample interpolation)
7758 * Interpolated colors are stored after the preloaded VGPRs.
7759 */
7760 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7761 union si_shader_part_key *key)
7762 {
7763 struct si_function_info fninfo;
7764 LLVMValueRef ret, func;
7765 int num_returns, i, num_color_channels;
7766
7767 assert(si_need_ps_prolog(key));
7768
7769 si_init_function_info(&fninfo);
7770
7771 /* Declare inputs. */
7772 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7773 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7774
7775 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7776 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7777
7778 /* Declare outputs (same as inputs + add colors if needed) */
7779 num_returns = fninfo.num_params;
7780 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7781 for (i = 0; i < num_color_channels; i++)
7782 fninfo.types[num_returns++] = ctx->f32;
7783
7784 /* Create the function. */
7785 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7786 &fninfo, 0);
7787 func = ctx->main_fn;
7788
7789 /* Copy inputs to outputs. This should be no-op, as the registers match,
7790 * but it will prevent the compiler from overwriting them unintentionally.
7791 */
7792 ret = ctx->return_value;
7793 for (i = 0; i < fninfo.num_params; i++) {
7794 LLVMValueRef p = LLVMGetParam(func, i);
7795 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7796 }
7797
7798 /* Polygon stippling. */
7799 if (key->ps_prolog.states.poly_stipple) {
7800 /* POS_FIXED_PT is always last. */
7801 unsigned pos = key->ps_prolog.num_input_sgprs +
7802 key->ps_prolog.num_input_vgprs - 1;
7803 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7804
7805 si_llvm_emit_polygon_stipple(ctx, list, pos);
7806 }
7807
7808 if (key->ps_prolog.states.bc_optimize_for_persp ||
7809 key->ps_prolog.states.bc_optimize_for_linear) {
7810 unsigned i, base = key->ps_prolog.num_input_sgprs;
7811 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7812
7813 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7814 * The hw doesn't compute CENTROID if the whole wave only
7815 * contains fully-covered quads.
7816 *
7817 * PRIM_MASK is after user SGPRs.
7818 */
7819 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7820 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7821 LLVMConstInt(ctx->i32, 31, 0), "");
7822 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7823 ctx->i1, "");
7824
7825 if (key->ps_prolog.states.bc_optimize_for_persp) {
7826 /* Read PERSP_CENTER. */
7827 for (i = 0; i < 2; i++)
7828 center[i] = LLVMGetParam(func, base + 2 + i);
7829 /* Read PERSP_CENTROID. */
7830 for (i = 0; i < 2; i++)
7831 centroid[i] = LLVMGetParam(func, base + 4 + i);
7832 /* Select PERSP_CENTROID. */
7833 for (i = 0; i < 2; i++) {
7834 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7835 center[i], centroid[i], "");
7836 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7837 tmp, base + 4 + i, "");
7838 }
7839 }
7840 if (key->ps_prolog.states.bc_optimize_for_linear) {
7841 /* Read LINEAR_CENTER. */
7842 for (i = 0; i < 2; i++)
7843 center[i] = LLVMGetParam(func, base + 8 + i);
7844 /* Read LINEAR_CENTROID. */
7845 for (i = 0; i < 2; i++)
7846 centroid[i] = LLVMGetParam(func, base + 10 + i);
7847 /* Select LINEAR_CENTROID. */
7848 for (i = 0; i < 2; i++) {
7849 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7850 center[i], centroid[i], "");
7851 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7852 tmp, base + 10 + i, "");
7853 }
7854 }
7855 }
7856
7857 /* Force per-sample interpolation. */
7858 if (key->ps_prolog.states.force_persp_sample_interp) {
7859 unsigned i, base = key->ps_prolog.num_input_sgprs;
7860 LLVMValueRef persp_sample[2];
7861
7862 /* Read PERSP_SAMPLE. */
7863 for (i = 0; i < 2; i++)
7864 persp_sample[i] = LLVMGetParam(func, base + i);
7865 /* Overwrite PERSP_CENTER. */
7866 for (i = 0; i < 2; i++)
7867 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7868 persp_sample[i], base + 2 + i, "");
7869 /* Overwrite PERSP_CENTROID. */
7870 for (i = 0; i < 2; i++)
7871 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7872 persp_sample[i], base + 4 + i, "");
7873 }
7874 if (key->ps_prolog.states.force_linear_sample_interp) {
7875 unsigned i, base = key->ps_prolog.num_input_sgprs;
7876 LLVMValueRef linear_sample[2];
7877
7878 /* Read LINEAR_SAMPLE. */
7879 for (i = 0; i < 2; i++)
7880 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7881 /* Overwrite LINEAR_CENTER. */
7882 for (i = 0; i < 2; i++)
7883 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7884 linear_sample[i], base + 8 + i, "");
7885 /* Overwrite LINEAR_CENTROID. */
7886 for (i = 0; i < 2; i++)
7887 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7888 linear_sample[i], base + 10 + i, "");
7889 }
7890
7891 /* Force center interpolation. */
7892 if (key->ps_prolog.states.force_persp_center_interp) {
7893 unsigned i, base = key->ps_prolog.num_input_sgprs;
7894 LLVMValueRef persp_center[2];
7895
7896 /* Read PERSP_CENTER. */
7897 for (i = 0; i < 2; i++)
7898 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7899 /* Overwrite PERSP_SAMPLE. */
7900 for (i = 0; i < 2; i++)
7901 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7902 persp_center[i], base + i, "");
7903 /* Overwrite PERSP_CENTROID. */
7904 for (i = 0; i < 2; i++)
7905 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7906 persp_center[i], base + 4 + i, "");
7907 }
7908 if (key->ps_prolog.states.force_linear_center_interp) {
7909 unsigned i, base = key->ps_prolog.num_input_sgprs;
7910 LLVMValueRef linear_center[2];
7911
7912 /* Read LINEAR_CENTER. */
7913 for (i = 0; i < 2; i++)
7914 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7915 /* Overwrite LINEAR_SAMPLE. */
7916 for (i = 0; i < 2; i++)
7917 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7918 linear_center[i], base + 6 + i, "");
7919 /* Overwrite LINEAR_CENTROID. */
7920 for (i = 0; i < 2; i++)
7921 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7922 linear_center[i], base + 10 + i, "");
7923 }
7924
7925 /* Interpolate colors. */
7926 unsigned color_out_idx = 0;
7927 for (i = 0; i < 2; i++) {
7928 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7929 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7930 key->ps_prolog.face_vgpr_index;
7931 LLVMValueRef interp[2], color[4];
7932 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7933
7934 if (!writemask)
7935 continue;
7936
7937 /* If the interpolation qualifier is not CONSTANT (-1). */
7938 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7939 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7940 key->ps_prolog.color_interp_vgpr_index[i];
7941
7942 /* Get the (i,j) updated by bc_optimize handling. */
7943 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7944 interp_vgpr, "");
7945 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7946 interp_vgpr + 1, "");
7947 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7948 }
7949
7950 /* Use the absolute location of the input. */
7951 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7952
7953 if (key->ps_prolog.states.color_two_side) {
7954 face = LLVMGetParam(func, face_vgpr);
7955 face = ac_to_integer(&ctx->ac, face);
7956 }
7957
7958 interp_fs_input(ctx,
7959 key->ps_prolog.color_attr_index[i],
7960 TGSI_SEMANTIC_COLOR, i,
7961 key->ps_prolog.num_interp_inputs,
7962 key->ps_prolog.colors_read, interp_ij,
7963 prim_mask, face, color);
7964
7965 while (writemask) {
7966 unsigned chan = u_bit_scan(&writemask);
7967 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7968 fninfo.num_params + color_out_idx++, "");
7969 }
7970 }
7971
7972 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7973 * says:
7974 *
7975 * "When per-sample shading is active due to the use of a fragment
7976 * input qualified by sample or due to the use of the gl_SampleID
7977 * or gl_SamplePosition variables, only the bit for the current
7978 * sample is set in gl_SampleMaskIn. When state specifies multiple
7979 * fragment shader invocations for a given fragment, the sample
7980 * mask for any single fragment shader invocation may specify a
7981 * subset of the covered samples for the fragment. In this case,
7982 * the bit corresponding to each covered sample will be set in
7983 * exactly one fragment shader invocation."
7984 *
7985 * The samplemask loaded by hardware is always the coverage of the
7986 * entire pixel/fragment, so mask bits out based on the sample ID.
7987 */
7988 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7989 /* The bit pattern matches that used by fixed function fragment
7990 * processing. */
7991 static const uint16_t ps_iter_masks[] = {
7992 0xffff, /* not used */
7993 0x5555,
7994 0x1111,
7995 0x0101,
7996 0x0001,
7997 };
7998 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7999
8000 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
8001 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
8002 key->ps_prolog.ancillary_vgpr_index;
8003 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
8004 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
8005
8006 samplemask = ac_to_integer(&ctx->ac, samplemask);
8007 samplemask = LLVMBuildAnd(
8008 ctx->ac.builder,
8009 samplemask,
8010 LLVMBuildShl(ctx->ac.builder,
8011 LLVMConstInt(ctx->i32, ps_iter_mask, false),
8012 sampleid, ""),
8013 "");
8014 samplemask = ac_to_float(&ctx->ac, samplemask);
8015
8016 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
8017 ancillary_vgpr + 1, "");
8018 }
8019
8020 /* Tell LLVM to insert WQM instruction sequence when needed. */
8021 if (key->ps_prolog.wqm) {
8022 LLVMAddTargetDependentFunctionAttr(func,
8023 "amdgpu-ps-wqm-outputs", "");
8024 }
8025
8026 si_llvm_build_ret(ctx, ret);
8027 }
8028
8029 /**
8030 * Build the pixel shader epilog function. This handles everything that must be
8031 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8032 */
8033 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8034 union si_shader_part_key *key)
8035 {
8036 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8037 struct si_function_info fninfo;
8038 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8039 int i;
8040 struct si_ps_exports exp = {};
8041
8042 si_init_function_info(&fninfo);
8043
8044 /* Declare input SGPRs. */
8045 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8046 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8047 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8048 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8049 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
8050
8051 /* Declare input VGPRs. */
8052 unsigned required_num_params =
8053 fninfo.num_sgpr_params +
8054 util_bitcount(key->ps_epilog.colors_written) * 4 +
8055 key->ps_epilog.writes_z +
8056 key->ps_epilog.writes_stencil +
8057 key->ps_epilog.writes_samplemask;
8058
8059 required_num_params = MAX2(required_num_params,
8060 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8061
8062 while (fninfo.num_params < required_num_params)
8063 add_arg(&fninfo, ARG_VGPR, ctx->f32);
8064
8065 /* Create the function. */
8066 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
8067 /* Disable elimination of unused inputs. */
8068 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
8069 "InitialPSInputAddr", 0xffffff);
8070
8071 /* Process colors. */
8072 unsigned vgpr = fninfo.num_sgpr_params;
8073 unsigned colors_written = key->ps_epilog.colors_written;
8074 int last_color_export = -1;
8075
8076 /* Find the last color export. */
8077 if (!key->ps_epilog.writes_z &&
8078 !key->ps_epilog.writes_stencil &&
8079 !key->ps_epilog.writes_samplemask) {
8080 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8081
8082 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8083 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8084 /* Just set this if any of the colorbuffers are enabled. */
8085 if (spi_format &
8086 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8087 last_color_export = 0;
8088 } else {
8089 for (i = 0; i < 8; i++)
8090 if (colors_written & (1 << i) &&
8091 (spi_format >> (i * 4)) & 0xf)
8092 last_color_export = i;
8093 }
8094 }
8095
8096 while (colors_written) {
8097 LLVMValueRef color[4];
8098 int mrt = u_bit_scan(&colors_written);
8099
8100 for (i = 0; i < 4; i++)
8101 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8102
8103 si_export_mrt_color(bld_base, color, mrt,
8104 fninfo.num_params - 1,
8105 mrt == last_color_export, &exp);
8106 }
8107
8108 /* Process depth, stencil, samplemask. */
8109 if (key->ps_epilog.writes_z)
8110 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8111 if (key->ps_epilog.writes_stencil)
8112 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8113 if (key->ps_epilog.writes_samplemask)
8114 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8115
8116 if (depth || stencil || samplemask)
8117 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8118 else if (last_color_export == -1)
8119 ac_build_export_null(&ctx->ac);
8120
8121 if (exp.num)
8122 si_emit_ps_exports(ctx, &exp);
8123
8124 /* Compile. */
8125 LLVMBuildRetVoid(ctx->ac.builder);
8126 }
8127
8128 /**
8129 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8130 */
8131 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8132 struct ac_llvm_compiler *compiler,
8133 struct si_shader *shader,
8134 struct pipe_debug_callback *debug)
8135 {
8136 union si_shader_part_key prolog_key;
8137 union si_shader_part_key epilog_key;
8138
8139 /* Get the prolog. */
8140 si_get_ps_prolog_key(shader, &prolog_key, true);
8141
8142 /* The prolog is a no-op if these aren't set. */
8143 if (si_need_ps_prolog(&prolog_key)) {
8144 shader->prolog =
8145 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8146 PIPE_SHADER_FRAGMENT, true,
8147 &prolog_key, compiler, debug,
8148 si_build_ps_prolog_function,
8149 "Fragment Shader Prolog");
8150 if (!shader->prolog)
8151 return false;
8152 }
8153
8154 /* Get the epilog. */
8155 si_get_ps_epilog_key(shader, &epilog_key);
8156
8157 shader->epilog =
8158 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8159 PIPE_SHADER_FRAGMENT, false,
8160 &epilog_key, compiler, debug,
8161 si_build_ps_epilog_function,
8162 "Fragment Shader Epilog");
8163 if (!shader->epilog)
8164 return false;
8165
8166 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8167 if (shader->key.part.ps.prolog.poly_stipple) {
8168 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8169 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8170 }
8171
8172 /* Set up the enable bits for per-sample shading if needed. */
8173 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8174 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8175 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8176 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8177 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8178 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8179 }
8180 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8181 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8182 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8183 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8184 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8185 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8186 }
8187 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8188 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8189 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8190 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8191 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8192 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8193 }
8194 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8195 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8196 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8197 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8198 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8199 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8200 }
8201
8202 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8203 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8204 !(shader->config.spi_ps_input_ena & 0xf)) {
8205 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8206 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8207 }
8208
8209 /* At least one pair of interpolation weights must be enabled. */
8210 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8211 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8212 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8213 }
8214
8215 /* Samplemask fixup requires the sample ID. */
8216 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
8217 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
8218 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
8219 }
8220
8221 /* The sample mask input is always enabled, because the API shader always
8222 * passes it through to the epilog. Disable it here if it's unused.
8223 */
8224 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8225 !shader->selector->info.reads_samplemask)
8226 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8227
8228 return true;
8229 }
8230
8231 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8232 unsigned *lds_size)
8233 {
8234 /* If tessellation is all offchip and on-chip GS isn't used, this
8235 * workaround is not needed.
8236 */
8237 return;
8238
8239 /* SPI barrier management bug:
8240 * Make sure we have at least 4k of LDS in use to avoid the bug.
8241 * It applies to workgroup sizes of more than one wavefront.
8242 */
8243 if (sscreen->info.family == CHIP_BONAIRE ||
8244 sscreen->info.family == CHIP_KABINI)
8245 *lds_size = MAX2(*lds_size, 8);
8246 }
8247
8248 static void si_fix_resource_usage(struct si_screen *sscreen,
8249 struct si_shader *shader)
8250 {
8251 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8252
8253 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8254
8255 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8256 si_get_max_workgroup_size(shader) > sscreen->compute_wave_size) {
8257 si_multiwave_lds_size_workaround(sscreen,
8258 &shader->config.lds_size);
8259 }
8260 }
8261
8262 bool si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
8263 struct si_shader *shader,
8264 struct pipe_debug_callback *debug)
8265 {
8266 struct si_shader_selector *sel = shader->selector;
8267 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8268 int r;
8269
8270 /* LS, ES, VS are compiled on demand if the main part hasn't been
8271 * compiled for that stage.
8272 *
8273 * GS are compiled on demand if the main part hasn't been compiled
8274 * for the chosen NGG-ness.
8275 *
8276 * Vertex shaders are compiled on demand when a vertex fetch
8277 * workaround must be applied.
8278 */
8279 if (shader->is_monolithic) {
8280 /* Monolithic shader (compiled as a whole, has many variants,
8281 * may take a long time to compile).
8282 */
8283 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
8284 if (r)
8285 return false;
8286 } else {
8287 /* The shader consists of several parts:
8288 *
8289 * - the middle part is the user shader, it has 1 variant only
8290 * and it was compiled during the creation of the shader
8291 * selector
8292 * - the prolog part is inserted at the beginning
8293 * - the epilog part is inserted at the end
8294 *
8295 * The prolog and epilog have many (but simple) variants.
8296 *
8297 * Starting with gfx9, geometry and tessellation control
8298 * shaders also contain the prolog and user shader parts of
8299 * the previous shader stage.
8300 */
8301
8302 if (!mainp)
8303 return false;
8304
8305 /* Copy the compiled TGSI shader data over. */
8306 shader->is_binary_shared = true;
8307 shader->binary = mainp->binary;
8308 shader->config = mainp->config;
8309 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8310 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8311 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8312 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8313 memcpy(shader->info.vs_output_param_offset,
8314 mainp->info.vs_output_param_offset,
8315 sizeof(mainp->info.vs_output_param_offset));
8316 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8317 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8318 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8319
8320 /* Select prologs and/or epilogs. */
8321 switch (sel->type) {
8322 case PIPE_SHADER_VERTEX:
8323 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8324 return false;
8325 break;
8326 case PIPE_SHADER_TESS_CTRL:
8327 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8328 return false;
8329 break;
8330 case PIPE_SHADER_TESS_EVAL:
8331 break;
8332 case PIPE_SHADER_GEOMETRY:
8333 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8334 return false;
8335 break;
8336 case PIPE_SHADER_FRAGMENT:
8337 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8338 return false;
8339
8340 /* Make sure we have at least as many VGPRs as there
8341 * are allocated inputs.
8342 */
8343 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8344 shader->info.num_input_vgprs);
8345 break;
8346 default:;
8347 }
8348
8349 /* Update SGPR and VGPR counts. */
8350 if (shader->prolog) {
8351 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8352 shader->prolog->config.num_sgprs);
8353 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8354 shader->prolog->config.num_vgprs);
8355 }
8356 if (shader->previous_stage) {
8357 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8358 shader->previous_stage->config.num_sgprs);
8359 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8360 shader->previous_stage->config.num_vgprs);
8361 shader->config.spilled_sgprs =
8362 MAX2(shader->config.spilled_sgprs,
8363 shader->previous_stage->config.spilled_sgprs);
8364 shader->config.spilled_vgprs =
8365 MAX2(shader->config.spilled_vgprs,
8366 shader->previous_stage->config.spilled_vgprs);
8367 shader->info.private_mem_vgprs =
8368 MAX2(shader->info.private_mem_vgprs,
8369 shader->previous_stage->info.private_mem_vgprs);
8370 shader->config.scratch_bytes_per_wave =
8371 MAX2(shader->config.scratch_bytes_per_wave,
8372 shader->previous_stage->config.scratch_bytes_per_wave);
8373 shader->info.uses_instanceid |=
8374 shader->previous_stage->info.uses_instanceid;
8375 }
8376 if (shader->prolog2) {
8377 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8378 shader->prolog2->config.num_sgprs);
8379 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8380 shader->prolog2->config.num_vgprs);
8381 }
8382 if (shader->epilog) {
8383 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8384 shader->epilog->config.num_sgprs);
8385 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8386 shader->epilog->config.num_vgprs);
8387 }
8388 si_calculate_max_simd_waves(shader);
8389 }
8390
8391 if (shader->key.as_ngg) {
8392 assert(!shader->key.as_es && !shader->key.as_ls);
8393 gfx10_ngg_calculate_subgroup_info(shader);
8394 } else if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY) {
8395 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
8396 }
8397
8398 si_fix_resource_usage(sscreen, shader);
8399 si_shader_dump(sscreen, shader, debug, stderr, true);
8400
8401 /* Upload. */
8402 if (!si_shader_binary_upload(sscreen, shader, 0)) {
8403 fprintf(stderr, "LLVM failed to upload shader\n");
8404 return false;
8405 }
8406
8407 return true;
8408 }
8409
8410 void si_shader_destroy(struct si_shader *shader)
8411 {
8412 if (shader->scratch_bo)
8413 si_resource_reference(&shader->scratch_bo, NULL);
8414
8415 si_resource_reference(&shader->bo, NULL);
8416
8417 if (!shader->is_binary_shared)
8418 si_shader_binary_clean(&shader->binary);
8419
8420 free(shader->shader_log);
8421 }