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radeonsi: process TGSI property NEXT_SHADER
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70
71 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
72 bool is_gs_copy_shader;
73
74 /* Whether to generate the optimized shader variant compiled as a whole
75 * (without a prolog and epilog)
76 */
77 bool is_monolithic;
78
79 int param_streamout_config;
80 int param_streamout_write_index;
81 int param_streamout_offset[4];
82 int param_vertex_id;
83 int param_rel_auto_id;
84 int param_vs_prim_id;
85 int param_instance_id;
86 int param_vertex_index0;
87 int param_tes_u;
88 int param_tes_v;
89 int param_tes_rel_patch_id;
90 int param_tes_patch_id;
91 int param_es2gs_offset;
92
93 LLVMTargetMachineRef tm;
94
95 LLVMValueRef const_md;
96 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
97 LLVMValueRef lds;
98 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
99 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
100 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
101 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
102 LLVMValueRef so_buffers[4];
103 LLVMValueRef esgs_ring;
104 LLVMValueRef gsvs_ring[4];
105 LLVMValueRef gs_next_vertex[4];
106 LLVMValueRef return_value;
107
108 LLVMTypeRef voidt;
109 LLVMTypeRef i1;
110 LLVMTypeRef i8;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef i128;
114 LLVMTypeRef f32;
115 LLVMTypeRef v16i8;
116 LLVMTypeRef v2i32;
117 LLVMTypeRef v4i32;
118 LLVMTypeRef v4f32;
119 LLVMTypeRef v8i32;
120 };
121
122 static struct si_shader_context *si_shader_context(
123 struct lp_build_tgsi_context *bld_base)
124 {
125 return (struct si_shader_context *)bld_base;
126 }
127
128 static void si_init_shader_ctx(struct si_shader_context *ctx,
129 struct si_screen *sscreen,
130 struct si_shader *shader,
131 LLVMTargetMachineRef tm);
132
133 /* Ideally pass the sample mask input to the PS epilog as v13, which
134 * is its usual location, so that the shader doesn't have to add v_mov.
135 */
136 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
137
138 /* The VS location of the PrimitiveID input is the same in the epilog,
139 * so that the main shader part doesn't have to move it.
140 */
141 #define VS_EPILOG_PRIMID_LOC 2
142
143 #define PERSPECTIVE_BASE 0
144 #define LINEAR_BASE 9
145
146 #define SAMPLE_OFFSET 0
147 #define CENTER_OFFSET 2
148 #define CENTROID_OFSET 4
149
150 #define USE_SGPR_MAX_SUFFIX_LEN 5
151 #define CONST_ADDR_SPACE 2
152 #define LOCAL_ADDR_SPACE 3
153 #define USER_SGPR_ADDR_SPACE 8
154
155
156 #define SENDMSG_GS 2
157 #define SENDMSG_GS_DONE 3
158
159 #define SENDMSG_GS_OP_NOP (0 << 4)
160 #define SENDMSG_GS_OP_CUT (1 << 4)
161 #define SENDMSG_GS_OP_EMIT (2 << 4)
162 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
163
164 /**
165 * Returns a unique index for a semantic name and index. The index must be
166 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
167 * calculated.
168 */
169 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
170 {
171 switch (semantic_name) {
172 case TGSI_SEMANTIC_POSITION:
173 return 0;
174 case TGSI_SEMANTIC_PSIZE:
175 return 1;
176 case TGSI_SEMANTIC_CLIPDIST:
177 assert(index <= 1);
178 return 2 + index;
179 case TGSI_SEMANTIC_GENERIC:
180 if (index <= 63-4)
181 return 4 + index;
182 else
183 /* same explanation as in the default statement,
184 * the only user hitting this is st/nine.
185 */
186 return 0;
187
188 /* patch indices are completely separate and thus start from 0 */
189 case TGSI_SEMANTIC_TESSOUTER:
190 return 0;
191 case TGSI_SEMANTIC_TESSINNER:
192 return 1;
193 case TGSI_SEMANTIC_PATCH:
194 return 2 + index;
195
196 default:
197 /* Don't fail here. The result of this function is only used
198 * for LS, TCS, TES, and GS, where legacy GL semantics can't
199 * occur, but this function is called for all vertex shaders
200 * before it's known whether LS will be compiled or not.
201 */
202 return 0;
203 }
204 }
205
206 /**
207 * Get the value of a shader input parameter and extract a bitfield.
208 */
209 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
210 unsigned param, unsigned rshift,
211 unsigned bitwidth)
212 {
213 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
214 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
215 param);
216
217 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
218 value = bitcast(&ctx->radeon_bld.soa.bld_base,
219 TGSI_TYPE_UNSIGNED, value);
220
221 if (rshift)
222 value = LLVMBuildLShr(gallivm->builder, value,
223 lp_build_const_int32(gallivm, rshift), "");
224
225 if (rshift + bitwidth < 32) {
226 unsigned mask = (1 << bitwidth) - 1;
227 value = LLVMBuildAnd(gallivm->builder, value,
228 lp_build_const_int32(gallivm, mask), "");
229 }
230
231 return value;
232 }
233
234 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
235 {
236 switch (ctx->type) {
237 case TGSI_PROCESSOR_TESS_CTRL:
238 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
239
240 case TGSI_PROCESSOR_TESS_EVAL:
241 return LLVMGetParam(ctx->radeon_bld.main_fn,
242 ctx->param_tes_rel_patch_id);
243
244 default:
245 assert(0);
246 return NULL;
247 }
248 }
249
250 /* Tessellation shaders pass outputs to the next shader using LDS.
251 *
252 * LS outputs = TCS inputs
253 * TCS outputs = TES inputs
254 *
255 * The LDS layout is:
256 * - TCS inputs for patch 0
257 * - TCS inputs for patch 1
258 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
259 * - ...
260 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
261 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
262 * - TCS outputs for patch 1
263 * - Per-patch TCS outputs for patch 1
264 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
265 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
266 * - ...
267 *
268 * All three shaders VS(LS), TCS, TES share the same LDS space.
269 */
270
271 static LLVMValueRef
272 get_tcs_in_patch_stride(struct si_shader_context *ctx)
273 {
274 if (ctx->type == TGSI_PROCESSOR_VERTEX)
275 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
276 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
277 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
278 else {
279 assert(0);
280 return NULL;
281 }
282 }
283
284 static LLVMValueRef
285 get_tcs_out_patch_stride(struct si_shader_context *ctx)
286 {
287 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
288 }
289
290 static LLVMValueRef
291 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
292 {
293 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
294 unpack_param(ctx,
295 SI_PARAM_TCS_OUT_OFFSETS,
296 0, 16),
297 4);
298 }
299
300 static LLVMValueRef
301 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
302 {
303 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
304 unpack_param(ctx,
305 SI_PARAM_TCS_OUT_OFFSETS,
306 16, 16),
307 4);
308 }
309
310 static LLVMValueRef
311 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
312 {
313 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
314 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
315 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
316
317 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
318 }
319
320 static LLVMValueRef
321 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
322 {
323 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
324 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
325 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
326 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
327
328 return LLVMBuildAdd(gallivm->builder, patch0_offset,
329 LLVMBuildMul(gallivm->builder, patch_stride,
330 rel_patch_id, ""),
331 "");
332 }
333
334 static LLVMValueRef
335 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
336 {
337 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
338 LLVMValueRef patch0_patch_data_offset =
339 get_tcs_out_patch0_patch_data_offset(ctx);
340 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
341 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
342
343 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
344 LLVMBuildMul(gallivm->builder, patch_stride,
345 rel_patch_id, ""),
346 "");
347 }
348
349 static void build_indexed_store(struct si_shader_context *ctx,
350 LLVMValueRef base_ptr, LLVMValueRef index,
351 LLVMValueRef value)
352 {
353 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
354 struct gallivm_state *gallivm = bld_base->base.gallivm;
355 LLVMValueRef indices[2], pointer;
356
357 indices[0] = bld_base->uint_bld.zero;
358 indices[1] = index;
359
360 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
361 LLVMBuildStore(gallivm->builder, value, pointer);
362 }
363
364 /**
365 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
366 * It's equivalent to doing a load from &base_ptr[index].
367 *
368 * \param base_ptr Where the array starts.
369 * \param index The element index into the array.
370 */
371 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
372 LLVMValueRef base_ptr, LLVMValueRef index)
373 {
374 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
375 struct gallivm_state *gallivm = bld_base->base.gallivm;
376 LLVMValueRef indices[2], pointer;
377
378 indices[0] = bld_base->uint_bld.zero;
379 indices[1] = index;
380
381 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
382 return LLVMBuildLoad(gallivm->builder, pointer, "");
383 }
384
385 /**
386 * Do a load from &base_ptr[index], but also add a flag that it's loading
387 * a constant.
388 */
389 static LLVMValueRef build_indexed_load_const(
390 struct si_shader_context *ctx,
391 LLVMValueRef base_ptr, LLVMValueRef index)
392 {
393 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
394 LLVMSetMetadata(result, 1, ctx->const_md);
395 return result;
396 }
397
398 static LLVMValueRef get_instance_index_for_fetch(
399 struct radeon_llvm_context *radeon_bld,
400 unsigned param_start_instance, unsigned divisor)
401 {
402 struct si_shader_context *ctx =
403 si_shader_context(&radeon_bld->soa.bld_base);
404 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
405
406 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
407 ctx->param_instance_id);
408
409 /* The division must be done before START_INSTANCE is added. */
410 if (divisor > 1)
411 result = LLVMBuildUDiv(gallivm->builder, result,
412 lp_build_const_int32(gallivm, divisor), "");
413
414 return LLVMBuildAdd(gallivm->builder, result,
415 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
416 }
417
418 static void declare_input_vs(
419 struct radeon_llvm_context *radeon_bld,
420 unsigned input_index,
421 const struct tgsi_full_declaration *decl)
422 {
423 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
424 struct gallivm_state *gallivm = base->gallivm;
425 struct si_shader_context *ctx =
426 si_shader_context(&radeon_bld->soa.bld_base);
427 unsigned divisor =
428 ctx->shader->key.vs.prolog.instance_divisors[input_index];
429
430 unsigned chan;
431
432 LLVMValueRef t_list_ptr;
433 LLVMValueRef t_offset;
434 LLVMValueRef t_list;
435 LLVMValueRef attribute_offset;
436 LLVMValueRef buffer_index;
437 LLVMValueRef args[3];
438 LLVMValueRef input;
439
440 /* Load the T list */
441 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
442
443 t_offset = lp_build_const_int32(gallivm, input_index);
444
445 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
446
447 /* Build the attribute offset */
448 attribute_offset = lp_build_const_int32(gallivm, 0);
449
450 if (!ctx->is_monolithic) {
451 buffer_index = LLVMGetParam(radeon_bld->main_fn,
452 ctx->param_vertex_index0 +
453 input_index);
454 } else if (divisor) {
455 /* Build index from instance ID, start instance and divisor */
456 ctx->shader->info.uses_instanceid = true;
457 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
458 SI_PARAM_START_INSTANCE,
459 divisor);
460 } else {
461 /* Load the buffer index for vertices. */
462 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
463 ctx->param_vertex_id);
464 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
465 SI_PARAM_BASE_VERTEX);
466 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
467 }
468
469 args[0] = t_list;
470 args[1] = attribute_offset;
471 args[2] = buffer_index;
472 input = lp_build_intrinsic(gallivm->builder,
473 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
474 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
475
476 /* Break up the vec4 into individual components */
477 for (chan = 0; chan < 4; chan++) {
478 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
479 /* XXX: Use a helper function for this. There is one in
480 * tgsi_llvm.c. */
481 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
482 LLVMBuildExtractElement(gallivm->builder,
483 input, llvm_chan, "");
484 }
485 }
486
487 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
488 unsigned swizzle)
489 {
490 struct si_shader_context *ctx = si_shader_context(bld_base);
491
492 if (swizzle > 0)
493 return bld_base->uint_bld.zero;
494
495 switch (ctx->type) {
496 case TGSI_PROCESSOR_VERTEX:
497 return LLVMGetParam(ctx->radeon_bld.main_fn,
498 ctx->param_vs_prim_id);
499 case TGSI_PROCESSOR_TESS_CTRL:
500 return LLVMGetParam(ctx->radeon_bld.main_fn,
501 SI_PARAM_PATCH_ID);
502 case TGSI_PROCESSOR_TESS_EVAL:
503 return LLVMGetParam(ctx->radeon_bld.main_fn,
504 ctx->param_tes_patch_id);
505 case TGSI_PROCESSOR_GEOMETRY:
506 return LLVMGetParam(ctx->radeon_bld.main_fn,
507 SI_PARAM_PRIMITIVE_ID);
508 default:
509 assert(0);
510 return bld_base->uint_bld.zero;
511 }
512 }
513
514 /**
515 * Return the value of tgsi_ind_register for indexing.
516 * This is the indirect index with the constant offset added to it.
517 */
518 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
519 const struct tgsi_ind_register *ind,
520 int rel_index)
521 {
522 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
523 LLVMValueRef result;
524
525 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
526 result = LLVMBuildLoad(gallivm->builder, result, "");
527 result = LLVMBuildAdd(gallivm->builder, result,
528 lp_build_const_int32(gallivm, rel_index), "");
529 return result;
530 }
531
532 /**
533 * Calculate a dword address given an input or output register and a stride.
534 */
535 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
536 const struct tgsi_full_dst_register *dst,
537 const struct tgsi_full_src_register *src,
538 LLVMValueRef vertex_dw_stride,
539 LLVMValueRef base_addr)
540 {
541 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
542 struct tgsi_shader_info *info = &ctx->shader->selector->info;
543 ubyte *name, *index, *array_first;
544 int first, param;
545 struct tgsi_full_dst_register reg;
546
547 /* Set the register description. The address computation is the same
548 * for sources and destinations. */
549 if (src) {
550 reg.Register.File = src->Register.File;
551 reg.Register.Index = src->Register.Index;
552 reg.Register.Indirect = src->Register.Indirect;
553 reg.Register.Dimension = src->Register.Dimension;
554 reg.Indirect = src->Indirect;
555 reg.Dimension = src->Dimension;
556 reg.DimIndirect = src->DimIndirect;
557 } else
558 reg = *dst;
559
560 /* If the register is 2-dimensional (e.g. an array of vertices
561 * in a primitive), calculate the base address of the vertex. */
562 if (reg.Register.Dimension) {
563 LLVMValueRef index;
564
565 if (reg.Dimension.Indirect)
566 index = get_indirect_index(ctx, &reg.DimIndirect,
567 reg.Dimension.Index);
568 else
569 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
570
571 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
572 LLVMBuildMul(gallivm->builder, index,
573 vertex_dw_stride, ""), "");
574 }
575
576 /* Get information about the register. */
577 if (reg.Register.File == TGSI_FILE_INPUT) {
578 name = info->input_semantic_name;
579 index = info->input_semantic_index;
580 array_first = info->input_array_first;
581 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
582 name = info->output_semantic_name;
583 index = info->output_semantic_index;
584 array_first = info->output_array_first;
585 } else {
586 assert(0);
587 return NULL;
588 }
589
590 if (reg.Register.Indirect) {
591 /* Add the relative address of the element. */
592 LLVMValueRef ind_index;
593
594 if (reg.Indirect.ArrayID)
595 first = array_first[reg.Indirect.ArrayID];
596 else
597 first = reg.Register.Index;
598
599 ind_index = get_indirect_index(ctx, &reg.Indirect,
600 reg.Register.Index - first);
601
602 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
603 LLVMBuildMul(gallivm->builder, ind_index,
604 lp_build_const_int32(gallivm, 4), ""), "");
605
606 param = si_shader_io_get_unique_index(name[first], index[first]);
607 } else {
608 param = si_shader_io_get_unique_index(name[reg.Register.Index],
609 index[reg.Register.Index]);
610 }
611
612 /* Add the base address of the element. */
613 return LLVMBuildAdd(gallivm->builder, base_addr,
614 lp_build_const_int32(gallivm, param * 4), "");
615 }
616
617 /**
618 * Load from LDS.
619 *
620 * \param type output value type
621 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
622 * \param dw_addr address in dwords
623 */
624 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
625 enum tgsi_opcode_type type, unsigned swizzle,
626 LLVMValueRef dw_addr)
627 {
628 struct si_shader_context *ctx = si_shader_context(bld_base);
629 struct gallivm_state *gallivm = bld_base->base.gallivm;
630 LLVMValueRef value;
631
632 if (swizzle == ~0) {
633 LLVMValueRef values[TGSI_NUM_CHANNELS];
634
635 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
636 values[chan] = lds_load(bld_base, type, chan, dw_addr);
637
638 return lp_build_gather_values(bld_base->base.gallivm, values,
639 TGSI_NUM_CHANNELS);
640 }
641
642 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
643 lp_build_const_int32(gallivm, swizzle));
644
645 value = build_indexed_load(ctx, ctx->lds, dw_addr);
646 if (type == TGSI_TYPE_DOUBLE) {
647 LLVMValueRef value2;
648 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
649 lp_build_const_int32(gallivm, swizzle + 1));
650 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
651 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
652 }
653
654 return LLVMBuildBitCast(gallivm->builder, value,
655 tgsi2llvmtype(bld_base, type), "");
656 }
657
658 /**
659 * Store to LDS.
660 *
661 * \param swizzle offset (typically 0..3)
662 * \param dw_addr address in dwords
663 * \param value value to store
664 */
665 static void lds_store(struct lp_build_tgsi_context *bld_base,
666 unsigned swizzle, LLVMValueRef dw_addr,
667 LLVMValueRef value)
668 {
669 struct si_shader_context *ctx = si_shader_context(bld_base);
670 struct gallivm_state *gallivm = bld_base->base.gallivm;
671
672 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
673 lp_build_const_int32(gallivm, swizzle));
674
675 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
676 build_indexed_store(ctx, ctx->lds,
677 dw_addr, value);
678 }
679
680 static LLVMValueRef fetch_input_tcs(
681 struct lp_build_tgsi_context *bld_base,
682 const struct tgsi_full_src_register *reg,
683 enum tgsi_opcode_type type, unsigned swizzle)
684 {
685 struct si_shader_context *ctx = si_shader_context(bld_base);
686 LLVMValueRef dw_addr, stride;
687
688 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
689 dw_addr = get_tcs_in_current_patch_offset(ctx);
690 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
691
692 return lds_load(bld_base, type, swizzle, dw_addr);
693 }
694
695 static LLVMValueRef fetch_output_tcs(
696 struct lp_build_tgsi_context *bld_base,
697 const struct tgsi_full_src_register *reg,
698 enum tgsi_opcode_type type, unsigned swizzle)
699 {
700 struct si_shader_context *ctx = si_shader_context(bld_base);
701 LLVMValueRef dw_addr, stride;
702
703 if (reg->Register.Dimension) {
704 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
705 dw_addr = get_tcs_out_current_patch_offset(ctx);
706 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
707 } else {
708 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
709 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
710 }
711
712 return lds_load(bld_base, type, swizzle, dw_addr);
713 }
714
715 static LLVMValueRef fetch_input_tes(
716 struct lp_build_tgsi_context *bld_base,
717 const struct tgsi_full_src_register *reg,
718 enum tgsi_opcode_type type, unsigned swizzle)
719 {
720 struct si_shader_context *ctx = si_shader_context(bld_base);
721 LLVMValueRef dw_addr, stride;
722
723 if (reg->Register.Dimension) {
724 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
725 dw_addr = get_tcs_out_current_patch_offset(ctx);
726 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
727 } else {
728 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
729 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
730 }
731
732 return lds_load(bld_base, type, swizzle, dw_addr);
733 }
734
735 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
736 const struct tgsi_full_instruction *inst,
737 const struct tgsi_opcode_info *info,
738 LLVMValueRef dst[4])
739 {
740 struct si_shader_context *ctx = si_shader_context(bld_base);
741 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
742 unsigned chan_index;
743 LLVMValueRef dw_addr, stride;
744
745 /* Only handle per-patch and per-vertex outputs here.
746 * Vectors will be lowered to scalars and this function will be called again.
747 */
748 if (reg->Register.File != TGSI_FILE_OUTPUT ||
749 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
750 radeon_llvm_emit_store(bld_base, inst, info, dst);
751 return;
752 }
753
754 if (reg->Register.Dimension) {
755 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
756 dw_addr = get_tcs_out_current_patch_offset(ctx);
757 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
758 } else {
759 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
760 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
761 }
762
763 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
764 LLVMValueRef value = dst[chan_index];
765
766 if (inst->Instruction.Saturate)
767 value = radeon_llvm_saturate(bld_base, value);
768
769 lds_store(bld_base, chan_index, dw_addr, value);
770 }
771 }
772
773 static LLVMValueRef fetch_input_gs(
774 struct lp_build_tgsi_context *bld_base,
775 const struct tgsi_full_src_register *reg,
776 enum tgsi_opcode_type type,
777 unsigned swizzle)
778 {
779 struct lp_build_context *base = &bld_base->base;
780 struct si_shader_context *ctx = si_shader_context(bld_base);
781 struct si_shader *shader = ctx->shader;
782 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
783 struct gallivm_state *gallivm = base->gallivm;
784 LLVMValueRef vtx_offset;
785 LLVMValueRef args[9];
786 unsigned vtx_offset_param;
787 struct tgsi_shader_info *info = &shader->selector->info;
788 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
789 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
790 unsigned param;
791 LLVMValueRef value;
792
793 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
794 return get_primitive_id(bld_base, swizzle);
795
796 if (!reg->Register.Dimension)
797 return NULL;
798
799 if (swizzle == ~0) {
800 LLVMValueRef values[TGSI_NUM_CHANNELS];
801 unsigned chan;
802 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
803 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
804 }
805 return lp_build_gather_values(bld_base->base.gallivm, values,
806 TGSI_NUM_CHANNELS);
807 }
808
809 /* Get the vertex offset parameter */
810 vtx_offset_param = reg->Dimension.Index;
811 if (vtx_offset_param < 2) {
812 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
813 } else {
814 assert(vtx_offset_param < 6);
815 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
816 }
817 vtx_offset = lp_build_mul_imm(uint,
818 LLVMGetParam(ctx->radeon_bld.main_fn,
819 vtx_offset_param),
820 4);
821
822 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
823 args[0] = ctx->esgs_ring;
824 args[1] = vtx_offset;
825 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
826 args[3] = uint->zero;
827 args[4] = uint->one; /* OFFEN */
828 args[5] = uint->zero; /* IDXEN */
829 args[6] = uint->one; /* GLC */
830 args[7] = uint->zero; /* SLC */
831 args[8] = uint->zero; /* TFE */
832
833 value = lp_build_intrinsic(gallivm->builder,
834 "llvm.SI.buffer.load.dword.i32.i32",
835 ctx->i32, args, 9,
836 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
837 if (type == TGSI_TYPE_DOUBLE) {
838 LLVMValueRef value2;
839 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
840 value2 = lp_build_intrinsic(gallivm->builder,
841 "llvm.SI.buffer.load.dword.i32.i32",
842 ctx->i32, args, 9,
843 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
844 return radeon_llvm_emit_fetch_double(bld_base,
845 value, value2);
846 }
847 return LLVMBuildBitCast(gallivm->builder,
848 value,
849 tgsi2llvmtype(bld_base, type), "");
850 }
851
852 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
853 {
854 switch (interpolate) {
855 case TGSI_INTERPOLATE_CONSTANT:
856 return 0;
857
858 case TGSI_INTERPOLATE_LINEAR:
859 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
860 return SI_PARAM_LINEAR_SAMPLE;
861 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
862 return SI_PARAM_LINEAR_CENTROID;
863 else
864 return SI_PARAM_LINEAR_CENTER;
865 break;
866 case TGSI_INTERPOLATE_COLOR:
867 case TGSI_INTERPOLATE_PERSPECTIVE:
868 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
869 return SI_PARAM_PERSP_SAMPLE;
870 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
871 return SI_PARAM_PERSP_CENTROID;
872 else
873 return SI_PARAM_PERSP_CENTER;
874 break;
875 default:
876 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
877 return -1;
878 }
879 }
880
881 /* This shouldn't be used by explicit INTERP opcodes. */
882 static unsigned select_interp_param(struct si_shader_context *ctx,
883 unsigned param)
884 {
885 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
886 !ctx->is_monolithic)
887 return param;
888
889 /* If the shader doesn't use center/centroid, just return the parameter.
890 *
891 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
892 * switch between center/centroid and sample without shader changes.
893 */
894 switch (param) {
895 case SI_PARAM_PERSP_CENTROID:
896 case SI_PARAM_PERSP_CENTER:
897 return SI_PARAM_PERSP_SAMPLE;
898
899 case SI_PARAM_LINEAR_CENTROID:
900 case SI_PARAM_LINEAR_CENTER:
901 return SI_PARAM_LINEAR_SAMPLE;
902
903 default:
904 return param;
905 }
906 }
907
908 /**
909 * Interpolate a fragment shader input.
910 *
911 * @param ctx context
912 * @param input_index index of the input in hardware
913 * @param semantic_name TGSI_SEMANTIC_*
914 * @param semantic_index semantic index
915 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
916 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
917 * @param interp_param interpolation weights (i,j)
918 * @param prim_mask SI_PARAM_PRIM_MASK
919 * @param face SI_PARAM_FRONT_FACE
920 * @param result the return value (4 components)
921 */
922 static void interp_fs_input(struct si_shader_context *ctx,
923 unsigned input_index,
924 unsigned semantic_name,
925 unsigned semantic_index,
926 unsigned num_interp_inputs,
927 unsigned colors_read_mask,
928 LLVMValueRef interp_param,
929 LLVMValueRef prim_mask,
930 LLVMValueRef face,
931 LLVMValueRef result[4])
932 {
933 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
934 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
935 struct gallivm_state *gallivm = base->gallivm;
936 const char *intr_name;
937 LLVMValueRef attr_number;
938
939 unsigned chan;
940
941 attr_number = lp_build_const_int32(gallivm, input_index);
942
943 /* fs.constant returns the param from the middle vertex, so it's not
944 * really useful for flat shading. It's meant to be used for custom
945 * interpolation (but the intrinsic can't fetch from the other two
946 * vertices).
947 *
948 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
949 * to do the right thing. The only reason we use fs.constant is that
950 * fs.interp cannot be used on integers, because they can be equal
951 * to NaN.
952 */
953 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
954
955 if (semantic_name == TGSI_SEMANTIC_COLOR &&
956 ctx->shader->key.ps.prolog.color_two_side) {
957 LLVMValueRef args[4];
958 LLVMValueRef is_face_positive;
959 LLVMValueRef back_attr_number;
960
961 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
962 * otherwise it's at offset "num_inputs".
963 */
964 unsigned back_attr_offset = num_interp_inputs;
965 if (semantic_index == 1 && colors_read_mask & 0xf)
966 back_attr_offset += 1;
967
968 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
969
970 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
971 face, uint->zero, "");
972
973 args[2] = prim_mask;
974 args[3] = interp_param;
975 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
976 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
977 LLVMValueRef front, back;
978
979 args[0] = llvm_chan;
980 args[1] = attr_number;
981 front = lp_build_intrinsic(gallivm->builder, intr_name,
982 ctx->f32, args, args[3] ? 4 : 3,
983 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
984
985 args[1] = back_attr_number;
986 back = lp_build_intrinsic(gallivm->builder, intr_name,
987 ctx->f32, args, args[3] ? 4 : 3,
988 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
989
990 result[chan] = LLVMBuildSelect(gallivm->builder,
991 is_face_positive,
992 front,
993 back,
994 "");
995 }
996 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
997 LLVMValueRef args[4];
998
999 args[0] = uint->zero;
1000 args[1] = attr_number;
1001 args[2] = prim_mask;
1002 args[3] = interp_param;
1003 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1004 ctx->f32, args, args[3] ? 4 : 3,
1005 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1006 result[1] =
1007 result[2] = lp_build_const_float(gallivm, 0.0f);
1008 result[3] = lp_build_const_float(gallivm, 1.0f);
1009 } else {
1010 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1011 LLVMValueRef args[4];
1012 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1013
1014 args[0] = llvm_chan;
1015 args[1] = attr_number;
1016 args[2] = prim_mask;
1017 args[3] = interp_param;
1018 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1019 ctx->f32, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021 }
1022 }
1023 }
1024
1025 static void declare_input_fs(
1026 struct radeon_llvm_context *radeon_bld,
1027 unsigned input_index,
1028 const struct tgsi_full_declaration *decl)
1029 {
1030 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1031 struct si_shader_context *ctx =
1032 si_shader_context(&radeon_bld->soa.bld_base);
1033 struct si_shader *shader = ctx->shader;
1034 LLVMValueRef main_fn = radeon_bld->main_fn;
1035 LLVMValueRef interp_param = NULL;
1036 int interp_param_idx;
1037
1038 /* Get colors from input VGPRs (set by the prolog). */
1039 if (!ctx->is_monolithic &&
1040 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1041 unsigned i = decl->Semantic.Index;
1042 unsigned colors_read = shader->selector->info.colors_read;
1043 unsigned mask = colors_read >> (i * 4);
1044 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1045 (i ? util_bitcount(colors_read & 0xf) : 0);
1046
1047 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1048 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1049 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1050 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1051 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1052 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1053 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1054 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1055 return;
1056 }
1057
1058 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1059 decl->Interp.Location);
1060 if (interp_param_idx == -1)
1061 return;
1062 else if (interp_param_idx) {
1063 interp_param_idx = select_interp_param(ctx,
1064 interp_param_idx);
1065 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1066 }
1067
1068 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1069 decl->Semantic.Index, shader->selector->info.num_inputs,
1070 shader->selector->info.colors_read, interp_param,
1071 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1072 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1073 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1074 }
1075
1076 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1077 {
1078 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1079 SI_PARAM_ANCILLARY, 8, 4);
1080 }
1081
1082 /**
1083 * Load a dword from a constant buffer.
1084 */
1085 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1086 LLVMValueRef offset, LLVMTypeRef return_type)
1087 {
1088 LLVMValueRef args[2] = {resource, offset};
1089
1090 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1091 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1092 }
1093
1094 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1095 {
1096 struct si_shader_context *ctx =
1097 si_shader_context(&radeon_bld->soa.bld_base);
1098 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1099 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1100 LLVMBuilderRef builder = gallivm->builder;
1101 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1102 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1103 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1104
1105 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1106 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1107 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1108
1109 LLVMValueRef pos[4] = {
1110 buffer_load_const(builder, resource, offset0, ctx->f32),
1111 buffer_load_const(builder, resource, offset1, ctx->f32),
1112 lp_build_const_float(gallivm, 0),
1113 lp_build_const_float(gallivm, 0)
1114 };
1115
1116 return lp_build_gather_values(gallivm, pos, 4);
1117 }
1118
1119 static void declare_system_value(
1120 struct radeon_llvm_context *radeon_bld,
1121 unsigned index,
1122 const struct tgsi_full_declaration *decl)
1123 {
1124 struct si_shader_context *ctx =
1125 si_shader_context(&radeon_bld->soa.bld_base);
1126 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1127 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1128 LLVMValueRef value = 0;
1129
1130 switch (decl->Semantic.Name) {
1131 case TGSI_SEMANTIC_INSTANCEID:
1132 value = LLVMGetParam(radeon_bld->main_fn,
1133 ctx->param_instance_id);
1134 break;
1135
1136 case TGSI_SEMANTIC_VERTEXID:
1137 value = LLVMBuildAdd(gallivm->builder,
1138 LLVMGetParam(radeon_bld->main_fn,
1139 ctx->param_vertex_id),
1140 LLVMGetParam(radeon_bld->main_fn,
1141 SI_PARAM_BASE_VERTEX), "");
1142 break;
1143
1144 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1145 value = LLVMGetParam(radeon_bld->main_fn,
1146 ctx->param_vertex_id);
1147 break;
1148
1149 case TGSI_SEMANTIC_BASEVERTEX:
1150 value = LLVMGetParam(radeon_bld->main_fn,
1151 SI_PARAM_BASE_VERTEX);
1152 break;
1153
1154 case TGSI_SEMANTIC_INVOCATIONID:
1155 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1156 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1157 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1158 value = LLVMGetParam(radeon_bld->main_fn,
1159 SI_PARAM_GS_INSTANCE_ID);
1160 else
1161 assert(!"INVOCATIONID not implemented");
1162 break;
1163
1164 case TGSI_SEMANTIC_POSITION:
1165 {
1166 LLVMValueRef pos[4] = {
1167 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1168 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1169 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1170 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1171 LLVMGetParam(radeon_bld->main_fn,
1172 SI_PARAM_POS_W_FLOAT)),
1173 };
1174 value = lp_build_gather_values(gallivm, pos, 4);
1175 break;
1176 }
1177
1178 case TGSI_SEMANTIC_FACE:
1179 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1180 break;
1181
1182 case TGSI_SEMANTIC_SAMPLEID:
1183 value = get_sample_id(radeon_bld);
1184 break;
1185
1186 case TGSI_SEMANTIC_SAMPLEPOS: {
1187 LLVMValueRef pos[4] = {
1188 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1189 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1190 lp_build_const_float(gallivm, 0),
1191 lp_build_const_float(gallivm, 0)
1192 };
1193 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1194 TGSI_OPCODE_FRC, pos[0]);
1195 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1196 TGSI_OPCODE_FRC, pos[1]);
1197 value = lp_build_gather_values(gallivm, pos, 4);
1198 break;
1199 }
1200
1201 case TGSI_SEMANTIC_SAMPLEMASK:
1202 /* This can only occur with the OpenGL Core profile, which
1203 * doesn't support smoothing.
1204 */
1205 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1206 break;
1207
1208 case TGSI_SEMANTIC_TESSCOORD:
1209 {
1210 LLVMValueRef coord[4] = {
1211 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1212 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1213 bld->zero,
1214 bld->zero
1215 };
1216
1217 /* For triangles, the vector should be (u, v, 1-u-v). */
1218 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1219 PIPE_PRIM_TRIANGLES)
1220 coord[2] = lp_build_sub(bld, bld->one,
1221 lp_build_add(bld, coord[0], coord[1]));
1222
1223 value = lp_build_gather_values(gallivm, coord, 4);
1224 break;
1225 }
1226
1227 case TGSI_SEMANTIC_VERTICESIN:
1228 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1229 break;
1230
1231 case TGSI_SEMANTIC_TESSINNER:
1232 case TGSI_SEMANTIC_TESSOUTER:
1233 {
1234 LLVMValueRef dw_addr;
1235 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1236
1237 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1238 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1239 lp_build_const_int32(gallivm, param * 4), "");
1240
1241 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1242 ~0, dw_addr);
1243 break;
1244 }
1245
1246 case TGSI_SEMANTIC_PRIMID:
1247 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1248 break;
1249
1250 default:
1251 assert(!"unknown system value");
1252 return;
1253 }
1254
1255 radeon_bld->system_values[index] = value;
1256 }
1257
1258 static LLVMValueRef fetch_constant(
1259 struct lp_build_tgsi_context *bld_base,
1260 const struct tgsi_full_src_register *reg,
1261 enum tgsi_opcode_type type,
1262 unsigned swizzle)
1263 {
1264 struct si_shader_context *ctx = si_shader_context(bld_base);
1265 struct lp_build_context *base = &bld_base->base;
1266 const struct tgsi_ind_register *ireg = &reg->Indirect;
1267 unsigned buf, idx;
1268
1269 LLVMValueRef addr, bufp;
1270 LLVMValueRef result;
1271
1272 if (swizzle == LP_CHAN_ALL) {
1273 unsigned chan;
1274 LLVMValueRef values[4];
1275 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1276 values[chan] = fetch_constant(bld_base, reg, type, chan);
1277
1278 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1279 }
1280
1281 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1282 idx = reg->Register.Index * 4 + swizzle;
1283
1284 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1285 if (type != TGSI_TYPE_DOUBLE)
1286 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1287 else {
1288 return radeon_llvm_emit_fetch_double(bld_base,
1289 ctx->constants[buf][idx],
1290 ctx->constants[buf][idx + 1]);
1291 }
1292 }
1293
1294 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1295 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1296 LLVMValueRef index;
1297 index = get_indirect_index(ctx, &reg->DimIndirect,
1298 reg->Dimension.Index);
1299 bufp = build_indexed_load_const(ctx, ptr, index);
1300 } else
1301 bufp = ctx->const_buffers[buf];
1302
1303 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1304 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1305 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1306 addr = lp_build_add(&bld_base->uint_bld, addr,
1307 lp_build_const_int32(base->gallivm, idx * 4));
1308
1309 result = buffer_load_const(base->gallivm->builder, bufp,
1310 addr, ctx->f32);
1311
1312 if (type != TGSI_TYPE_DOUBLE)
1313 result = bitcast(bld_base, type, result);
1314 else {
1315 LLVMValueRef addr2, result2;
1316 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1317 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1318 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1319 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1320 lp_build_const_int32(base->gallivm, idx * 4));
1321
1322 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1323 addr2, ctx->f32);
1324
1325 result = radeon_llvm_emit_fetch_double(bld_base,
1326 result, result2);
1327 }
1328 return result;
1329 }
1330
1331 /* Upper 16 bits must be zero. */
1332 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1333 LLVMValueRef val[2])
1334 {
1335 return LLVMBuildOr(gallivm->builder, val[0],
1336 LLVMBuildShl(gallivm->builder, val[1],
1337 lp_build_const_int32(gallivm, 16),
1338 ""), "");
1339 }
1340
1341 /* Upper 16 bits are ignored and will be dropped. */
1342 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1343 LLVMValueRef val[2])
1344 {
1345 LLVMValueRef v[2] = {
1346 LLVMBuildAnd(gallivm->builder, val[0],
1347 lp_build_const_int32(gallivm, 0xffff), ""),
1348 val[1],
1349 };
1350 return si_llvm_pack_two_int16(gallivm, v);
1351 }
1352
1353 /* Initialize arguments for the shader export intrinsic */
1354 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1355 LLVMValueRef *values,
1356 unsigned target,
1357 LLVMValueRef *args)
1358 {
1359 struct si_shader_context *ctx = si_shader_context(bld_base);
1360 struct lp_build_context *uint =
1361 &ctx->radeon_bld.soa.bld_base.uint_bld;
1362 struct lp_build_context *base = &bld_base->base;
1363 struct gallivm_state *gallivm = base->gallivm;
1364 LLVMBuilderRef builder = base->gallivm->builder;
1365 LLVMValueRef val[4];
1366 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1367 unsigned chan;
1368 bool is_int8;
1369
1370 /* Default is 0xf. Adjusted below depending on the format. */
1371 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1372
1373 /* Specify whether the EXEC mask represents the valid mask */
1374 args[1] = uint->zero;
1375
1376 /* Specify whether this is the last export */
1377 args[2] = uint->zero;
1378
1379 /* Specify the target we are exporting */
1380 args[3] = lp_build_const_int32(base->gallivm, target);
1381
1382 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1383 const union si_shader_key *key = &ctx->shader->key;
1384 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1385 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1386
1387 assert(cbuf >= 0 && cbuf < 8);
1388 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1389 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1390 }
1391
1392 args[4] = uint->zero; /* COMPR flag */
1393 args[5] = base->undef;
1394 args[6] = base->undef;
1395 args[7] = base->undef;
1396 args[8] = base->undef;
1397
1398 switch (spi_shader_col_format) {
1399 case V_028714_SPI_SHADER_ZERO:
1400 args[0] = uint->zero; /* writemask */
1401 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1402 break;
1403
1404 case V_028714_SPI_SHADER_32_R:
1405 args[0] = uint->one; /* writemask */
1406 args[5] = values[0];
1407 break;
1408
1409 case V_028714_SPI_SHADER_32_GR:
1410 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1411 args[5] = values[0];
1412 args[6] = values[1];
1413 break;
1414
1415 case V_028714_SPI_SHADER_32_AR:
1416 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1417 args[5] = values[0];
1418 args[8] = values[3];
1419 break;
1420
1421 case V_028714_SPI_SHADER_FP16_ABGR:
1422 args[4] = uint->one; /* COMPR flag */
1423
1424 for (chan = 0; chan < 2; chan++) {
1425 LLVMValueRef pack_args[2] = {
1426 values[2 * chan],
1427 values[2 * chan + 1]
1428 };
1429 LLVMValueRef packed;
1430
1431 packed = lp_build_intrinsic(base->gallivm->builder,
1432 "llvm.SI.packf16",
1433 ctx->i32, pack_args, 2,
1434 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1435 args[chan + 5] =
1436 LLVMBuildBitCast(base->gallivm->builder,
1437 packed, ctx->f32, "");
1438 }
1439 break;
1440
1441 case V_028714_SPI_SHADER_UNORM16_ABGR:
1442 for (chan = 0; chan < 4; chan++) {
1443 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1444 val[chan] = LLVMBuildFMul(builder, val[chan],
1445 lp_build_const_float(gallivm, 65535), "");
1446 val[chan] = LLVMBuildFAdd(builder, val[chan],
1447 lp_build_const_float(gallivm, 0.5), "");
1448 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1449 ctx->i32, "");
1450 }
1451
1452 args[4] = uint->one; /* COMPR flag */
1453 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1454 si_llvm_pack_two_int16(gallivm, val));
1455 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1456 si_llvm_pack_two_int16(gallivm, val+2));
1457 break;
1458
1459 case V_028714_SPI_SHADER_SNORM16_ABGR:
1460 for (chan = 0; chan < 4; chan++) {
1461 /* Clamp between [-1, 1]. */
1462 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1463 values[chan],
1464 lp_build_const_float(gallivm, 1));
1465 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1466 val[chan],
1467 lp_build_const_float(gallivm, -1));
1468 /* Convert to a signed integer in [-32767, 32767]. */
1469 val[chan] = LLVMBuildFMul(builder, val[chan],
1470 lp_build_const_float(gallivm, 32767), "");
1471 /* If positive, add 0.5, else add -0.5. */
1472 val[chan] = LLVMBuildFAdd(builder, val[chan],
1473 LLVMBuildSelect(builder,
1474 LLVMBuildFCmp(builder, LLVMRealOGE,
1475 val[chan], base->zero, ""),
1476 lp_build_const_float(gallivm, 0.5),
1477 lp_build_const_float(gallivm, -0.5), ""), "");
1478 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1479 }
1480
1481 args[4] = uint->one; /* COMPR flag */
1482 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1483 si_llvm_pack_two_int32_as_int16(gallivm, val));
1484 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1485 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1486 break;
1487
1488 case V_028714_SPI_SHADER_UINT16_ABGR: {
1489 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1490 255 : 65535);
1491 /* Clamp. */
1492 for (chan = 0; chan < 4; chan++) {
1493 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1494 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1495 val[chan], max);
1496 }
1497
1498 args[4] = uint->one; /* COMPR flag */
1499 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1500 si_llvm_pack_two_int16(gallivm, val));
1501 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1502 si_llvm_pack_two_int16(gallivm, val+2));
1503 break;
1504 }
1505
1506 case V_028714_SPI_SHADER_SINT16_ABGR: {
1507 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1508 127 : 32767);
1509 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1510 -128 : -32768);
1511 /* Clamp. */
1512 for (chan = 0; chan < 4; chan++) {
1513 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1514 val[chan] = lp_build_emit_llvm_binary(bld_base,
1515 TGSI_OPCODE_IMIN,
1516 val[chan], max);
1517 val[chan] = lp_build_emit_llvm_binary(bld_base,
1518 TGSI_OPCODE_IMAX,
1519 val[chan], min);
1520 }
1521
1522 args[4] = uint->one; /* COMPR flag */
1523 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1524 si_llvm_pack_two_int32_as_int16(gallivm, val));
1525 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1526 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1527 break;
1528 }
1529
1530 case V_028714_SPI_SHADER_32_ABGR:
1531 memcpy(&args[5], values, sizeof(values[0]) * 4);
1532 break;
1533 }
1534 }
1535
1536 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1537 LLVMValueRef alpha)
1538 {
1539 struct si_shader_context *ctx = si_shader_context(bld_base);
1540 struct gallivm_state *gallivm = bld_base->base.gallivm;
1541
1542 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1543 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1544 SI_PARAM_ALPHA_REF);
1545
1546 LLVMValueRef alpha_pass =
1547 lp_build_cmp(&bld_base->base,
1548 ctx->shader->key.ps.epilog.alpha_func,
1549 alpha, alpha_ref);
1550 LLVMValueRef arg =
1551 lp_build_select(&bld_base->base,
1552 alpha_pass,
1553 lp_build_const_float(gallivm, 1.0f),
1554 lp_build_const_float(gallivm, -1.0f));
1555
1556 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1557 ctx->voidt, &arg, 1, 0);
1558 } else {
1559 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1560 ctx->voidt, NULL, 0, 0);
1561 }
1562 }
1563
1564 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1565 LLVMValueRef alpha,
1566 unsigned samplemask_param)
1567 {
1568 struct si_shader_context *ctx = si_shader_context(bld_base);
1569 struct gallivm_state *gallivm = bld_base->base.gallivm;
1570 LLVMValueRef coverage;
1571
1572 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1573 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1574 samplemask_param);
1575 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1576
1577 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1578 ctx->i32,
1579 &coverage, 1, LLVMReadNoneAttribute);
1580
1581 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1582 ctx->f32, "");
1583
1584 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1585 lp_build_const_float(gallivm,
1586 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1587
1588 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1589 }
1590
1591 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1592 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1593 {
1594 struct si_shader_context *ctx = si_shader_context(bld_base);
1595 struct lp_build_context *base = &bld_base->base;
1596 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1597 unsigned reg_index;
1598 unsigned chan;
1599 unsigned const_chan;
1600 LLVMValueRef base_elt;
1601 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1602 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1603 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1604
1605 for (reg_index = 0; reg_index < 2; reg_index ++) {
1606 LLVMValueRef *args = pos[2 + reg_index];
1607
1608 args[5] =
1609 args[6] =
1610 args[7] =
1611 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1612
1613 /* Compute dot products of position and user clip plane vectors */
1614 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1615 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1616 args[1] = lp_build_const_int32(base->gallivm,
1617 ((reg_index * 4 + chan) * 4 +
1618 const_chan) * 4);
1619 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1620 args[1], ctx->f32);
1621 args[5 + chan] =
1622 lp_build_add(base, args[5 + chan],
1623 lp_build_mul(base, base_elt,
1624 out_elts[const_chan]));
1625 }
1626 }
1627
1628 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1629 args[1] = uint->zero;
1630 args[2] = uint->zero;
1631 args[3] = lp_build_const_int32(base->gallivm,
1632 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1633 args[4] = uint->zero;
1634 }
1635 }
1636
1637 static void si_dump_streamout(struct pipe_stream_output_info *so)
1638 {
1639 unsigned i;
1640
1641 if (so->num_outputs)
1642 fprintf(stderr, "STREAMOUT\n");
1643
1644 for (i = 0; i < so->num_outputs; i++) {
1645 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1646 so->output[i].start_component;
1647 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1648 i, so->output[i].output_buffer,
1649 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1650 so->output[i].register_index,
1651 mask & 1 ? "x" : "",
1652 mask & 2 ? "y" : "",
1653 mask & 4 ? "z" : "",
1654 mask & 8 ? "w" : "");
1655 }
1656 }
1657
1658 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1659 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1660 * or v4i32 (num_channels=3,4). */
1661 static void build_tbuffer_store(struct si_shader_context *ctx,
1662 LLVMValueRef rsrc,
1663 LLVMValueRef vdata,
1664 unsigned num_channels,
1665 LLVMValueRef vaddr,
1666 LLVMValueRef soffset,
1667 unsigned inst_offset,
1668 unsigned dfmt,
1669 unsigned nfmt,
1670 unsigned offen,
1671 unsigned idxen,
1672 unsigned glc,
1673 unsigned slc,
1674 unsigned tfe)
1675 {
1676 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1677 LLVMValueRef args[] = {
1678 rsrc,
1679 vdata,
1680 LLVMConstInt(ctx->i32, num_channels, 0),
1681 vaddr,
1682 soffset,
1683 LLVMConstInt(ctx->i32, inst_offset, 0),
1684 LLVMConstInt(ctx->i32, dfmt, 0),
1685 LLVMConstInt(ctx->i32, nfmt, 0),
1686 LLVMConstInt(ctx->i32, offen, 0),
1687 LLVMConstInt(ctx->i32, idxen, 0),
1688 LLVMConstInt(ctx->i32, glc, 0),
1689 LLVMConstInt(ctx->i32, slc, 0),
1690 LLVMConstInt(ctx->i32, tfe, 0)
1691 };
1692
1693 /* The instruction offset field has 12 bits */
1694 assert(offen || inst_offset < (1 << 12));
1695
1696 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1697 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1698 const char *types[] = {"i32", "v2i32", "v4i32"};
1699 char name[256];
1700 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1701
1702 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1703 args, Elements(args), 0);
1704 }
1705
1706 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1707 LLVMValueRef rsrc,
1708 LLVMValueRef vdata,
1709 unsigned num_channels,
1710 LLVMValueRef vaddr,
1711 LLVMValueRef soffset,
1712 unsigned inst_offset)
1713 {
1714 static unsigned dfmt[] = {
1715 V_008F0C_BUF_DATA_FORMAT_32,
1716 V_008F0C_BUF_DATA_FORMAT_32_32,
1717 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1718 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1719 };
1720 assert(num_channels >= 1 && num_channels <= 4);
1721
1722 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1723 inst_offset, dfmt[num_channels-1],
1724 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1725 }
1726
1727 /* On SI, the vertex shader is responsible for writing streamout data
1728 * to buffers. */
1729 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1730 struct si_shader_output_values *outputs,
1731 unsigned noutput)
1732 {
1733 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1734 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1735 LLVMBuilderRef builder = gallivm->builder;
1736 int i, j;
1737 struct lp_build_if_state if_ctx;
1738
1739 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1740 LLVMValueRef so_vtx_count =
1741 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1742
1743 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1744 NULL, 0, LLVMReadNoneAttribute);
1745
1746 /* can_emit = tid < so_vtx_count; */
1747 LLVMValueRef can_emit =
1748 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1749
1750 LLVMValueRef stream_id =
1751 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1752
1753 /* Emit the streamout code conditionally. This actually avoids
1754 * out-of-bounds buffer access. The hw tells us via the SGPR
1755 * (so_vtx_count) which threads are allowed to emit streamout data. */
1756 lp_build_if(&if_ctx, gallivm, can_emit);
1757 {
1758 /* The buffer offset is computed as follows:
1759 * ByteOffset = streamout_offset[buffer_id]*4 +
1760 * (streamout_write_index + thread_id)*stride[buffer_id] +
1761 * attrib_offset
1762 */
1763
1764 LLVMValueRef so_write_index =
1765 LLVMGetParam(ctx->radeon_bld.main_fn,
1766 ctx->param_streamout_write_index);
1767
1768 /* Compute (streamout_write_index + thread_id). */
1769 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1770
1771 /* Compute the write offset for each enabled buffer. */
1772 LLVMValueRef so_write_offset[4] = {};
1773 for (i = 0; i < 4; i++) {
1774 if (!so->stride[i])
1775 continue;
1776
1777 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1778 ctx->param_streamout_offset[i]);
1779 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1780
1781 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1782 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1783 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1784 }
1785
1786 /* Write streamout data. */
1787 for (i = 0; i < so->num_outputs; i++) {
1788 unsigned buf_idx = so->output[i].output_buffer;
1789 unsigned reg = so->output[i].register_index;
1790 unsigned start = so->output[i].start_component;
1791 unsigned num_comps = so->output[i].num_components;
1792 unsigned stream = so->output[i].stream;
1793 LLVMValueRef out[4];
1794 struct lp_build_if_state if_ctx_stream;
1795
1796 assert(num_comps && num_comps <= 4);
1797 if (!num_comps || num_comps > 4)
1798 continue;
1799
1800 if (reg >= noutput)
1801 continue;
1802
1803 /* Load the output as int. */
1804 for (j = 0; j < num_comps; j++) {
1805 out[j] = LLVMBuildBitCast(builder,
1806 outputs[reg].values[start+j],
1807 ctx->i32, "");
1808 }
1809
1810 /* Pack the output. */
1811 LLVMValueRef vdata = NULL;
1812
1813 switch (num_comps) {
1814 case 1: /* as i32 */
1815 vdata = out[0];
1816 break;
1817 case 2: /* as v2i32 */
1818 case 3: /* as v4i32 (aligned to 4) */
1819 case 4: /* as v4i32 */
1820 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1821 for (j = 0; j < num_comps; j++) {
1822 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1823 LLVMConstInt(ctx->i32, j, 0), "");
1824 }
1825 break;
1826 }
1827
1828 LLVMValueRef can_emit_stream =
1829 LLVMBuildICmp(builder, LLVMIntEQ,
1830 stream_id,
1831 lp_build_const_int32(gallivm, stream), "");
1832
1833 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1834 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1835 vdata, num_comps,
1836 so_write_offset[buf_idx],
1837 LLVMConstInt(ctx->i32, 0, 0),
1838 so->output[i].dst_offset*4);
1839 lp_build_endif(&if_ctx_stream);
1840 }
1841 }
1842 lp_build_endif(&if_ctx);
1843 }
1844
1845
1846 /* Generate export instructions for hardware VS shader stage */
1847 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1848 struct si_shader_output_values *outputs,
1849 unsigned noutput)
1850 {
1851 struct si_shader_context *ctx = si_shader_context(bld_base);
1852 struct si_shader *shader = ctx->shader;
1853 struct lp_build_context *base = &bld_base->base;
1854 struct lp_build_context *uint =
1855 &ctx->radeon_bld.soa.bld_base.uint_bld;
1856 LLVMValueRef args[9];
1857 LLVMValueRef pos_args[4][9] = { { 0 } };
1858 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1859 unsigned semantic_name, semantic_index;
1860 unsigned target;
1861 unsigned param_count = 0;
1862 unsigned pos_idx;
1863 int i;
1864
1865 if (outputs && ctx->shader->selector->so.num_outputs) {
1866 si_llvm_emit_streamout(ctx, outputs, noutput);
1867 }
1868
1869 for (i = 0; i < noutput; i++) {
1870 semantic_name = outputs[i].name;
1871 semantic_index = outputs[i].sid;
1872
1873 handle_semantic:
1874 /* Select the correct target */
1875 switch(semantic_name) {
1876 case TGSI_SEMANTIC_PSIZE:
1877 psize_value = outputs[i].values[0];
1878 continue;
1879 case TGSI_SEMANTIC_EDGEFLAG:
1880 edgeflag_value = outputs[i].values[0];
1881 continue;
1882 case TGSI_SEMANTIC_LAYER:
1883 layer_value = outputs[i].values[0];
1884 semantic_name = TGSI_SEMANTIC_GENERIC;
1885 goto handle_semantic;
1886 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1887 viewport_index_value = outputs[i].values[0];
1888 semantic_name = TGSI_SEMANTIC_GENERIC;
1889 goto handle_semantic;
1890 case TGSI_SEMANTIC_POSITION:
1891 target = V_008DFC_SQ_EXP_POS;
1892 break;
1893 case TGSI_SEMANTIC_COLOR:
1894 case TGSI_SEMANTIC_BCOLOR:
1895 target = V_008DFC_SQ_EXP_PARAM + param_count;
1896 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1897 shader->info.vs_output_param_offset[i] = param_count;
1898 param_count++;
1899 break;
1900 case TGSI_SEMANTIC_CLIPDIST:
1901 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1902 break;
1903 case TGSI_SEMANTIC_CLIPVERTEX:
1904 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1905 continue;
1906 case TGSI_SEMANTIC_PRIMID:
1907 case TGSI_SEMANTIC_FOG:
1908 case TGSI_SEMANTIC_TEXCOORD:
1909 case TGSI_SEMANTIC_GENERIC:
1910 target = V_008DFC_SQ_EXP_PARAM + param_count;
1911 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1912 shader->info.vs_output_param_offset[i] = param_count;
1913 param_count++;
1914 break;
1915 default:
1916 target = 0;
1917 fprintf(stderr,
1918 "Warning: SI unhandled vs output type:%d\n",
1919 semantic_name);
1920 }
1921
1922 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1923
1924 if (target >= V_008DFC_SQ_EXP_POS &&
1925 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1926 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1927 args, sizeof(args));
1928 } else {
1929 lp_build_intrinsic(base->gallivm->builder,
1930 "llvm.SI.export", ctx->voidt,
1931 args, 9, 0);
1932 }
1933
1934 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1935 semantic_name = TGSI_SEMANTIC_GENERIC;
1936 goto handle_semantic;
1937 }
1938 }
1939
1940 shader->info.nr_param_exports = param_count;
1941
1942 /* We need to add the position output manually if it's missing. */
1943 if (!pos_args[0][0]) {
1944 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1945 pos_args[0][1] = uint->zero; /* EXEC mask */
1946 pos_args[0][2] = uint->zero; /* last export? */
1947 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1948 pos_args[0][4] = uint->zero; /* COMPR flag */
1949 pos_args[0][5] = base->zero; /* X */
1950 pos_args[0][6] = base->zero; /* Y */
1951 pos_args[0][7] = base->zero; /* Z */
1952 pos_args[0][8] = base->one; /* W */
1953 }
1954
1955 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1956 if (shader->selector->info.writes_psize ||
1957 shader->selector->info.writes_edgeflag ||
1958 shader->selector->info.writes_viewport_index ||
1959 shader->selector->info.writes_layer) {
1960 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1961 shader->selector->info.writes_psize |
1962 (shader->selector->info.writes_edgeflag << 1) |
1963 (shader->selector->info.writes_layer << 2) |
1964 (shader->selector->info.writes_viewport_index << 3));
1965 pos_args[1][1] = uint->zero; /* EXEC mask */
1966 pos_args[1][2] = uint->zero; /* last export? */
1967 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1968 pos_args[1][4] = uint->zero; /* COMPR flag */
1969 pos_args[1][5] = base->zero; /* X */
1970 pos_args[1][6] = base->zero; /* Y */
1971 pos_args[1][7] = base->zero; /* Z */
1972 pos_args[1][8] = base->zero; /* W */
1973
1974 if (shader->selector->info.writes_psize)
1975 pos_args[1][5] = psize_value;
1976
1977 if (shader->selector->info.writes_edgeflag) {
1978 /* The output is a float, but the hw expects an integer
1979 * with the first bit containing the edge flag. */
1980 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1981 edgeflag_value,
1982 ctx->i32, "");
1983 edgeflag_value = lp_build_min(&bld_base->int_bld,
1984 edgeflag_value,
1985 bld_base->int_bld.one);
1986
1987 /* The LLVM intrinsic expects a float. */
1988 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1989 edgeflag_value,
1990 ctx->f32, "");
1991 }
1992
1993 if (shader->selector->info.writes_layer)
1994 pos_args[1][7] = layer_value;
1995
1996 if (shader->selector->info.writes_viewport_index)
1997 pos_args[1][8] = viewport_index_value;
1998 }
1999
2000 for (i = 0; i < 4; i++)
2001 if (pos_args[i][0])
2002 shader->info.nr_pos_exports++;
2003
2004 pos_idx = 0;
2005 for (i = 0; i < 4; i++) {
2006 if (!pos_args[i][0])
2007 continue;
2008
2009 /* Specify the target we are exporting */
2010 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2011
2012 if (pos_idx == shader->info.nr_pos_exports)
2013 /* Specify that this is the last export */
2014 pos_args[i][2] = uint->one;
2015
2016 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2017 ctx->voidt, pos_args[i], 9, 0);
2018 }
2019 }
2020
2021 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2022 LLVMValueRef rel_patch_id,
2023 LLVMValueRef invocation_id,
2024 LLVMValueRef tcs_out_current_patch_data_offset)
2025 {
2026 struct si_shader_context *ctx = si_shader_context(bld_base);
2027 struct gallivm_state *gallivm = bld_base->base.gallivm;
2028 struct si_shader *shader = ctx->shader;
2029 unsigned tess_inner_index, tess_outer_index;
2030 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2031 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2032 unsigned stride, outer_comps, inner_comps, i;
2033 struct lp_build_if_state if_ctx;
2034
2035 /* Do this only for invocation 0, because the tess levels are per-patch,
2036 * not per-vertex.
2037 *
2038 * This can't jump, because invocation 0 executes this. It should
2039 * at least mask out the loads and stores for other invocations.
2040 */
2041 lp_build_if(&if_ctx, gallivm,
2042 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2043 invocation_id, bld_base->uint_bld.zero, ""));
2044
2045 /* Determine the layout of one tess factor element in the buffer. */
2046 switch (shader->key.tcs.epilog.prim_mode) {
2047 case PIPE_PRIM_LINES:
2048 stride = 2; /* 2 dwords, 1 vec2 store */
2049 outer_comps = 2;
2050 inner_comps = 0;
2051 break;
2052 case PIPE_PRIM_TRIANGLES:
2053 stride = 4; /* 4 dwords, 1 vec4 store */
2054 outer_comps = 3;
2055 inner_comps = 1;
2056 break;
2057 case PIPE_PRIM_QUADS:
2058 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2059 outer_comps = 4;
2060 inner_comps = 2;
2061 break;
2062 default:
2063 assert(0);
2064 return;
2065 }
2066
2067 /* Load tess_inner and tess_outer from LDS.
2068 * Any invocation can write them, so we can't get them from a temporary.
2069 */
2070 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2071 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2072
2073 lds_base = tcs_out_current_patch_data_offset;
2074 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2075 lp_build_const_int32(gallivm,
2076 tess_inner_index * 4), "");
2077 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2078 lp_build_const_int32(gallivm,
2079 tess_outer_index * 4), "");
2080
2081 for (i = 0; i < outer_comps; i++)
2082 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2083 for (i = 0; i < inner_comps; i++)
2084 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2085
2086 /* Convert the outputs to vectors for stores. */
2087 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2088 vec1 = NULL;
2089
2090 if (stride > 4)
2091 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2092
2093 /* Get the buffer. */
2094 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2095 SI_PARAM_RW_BUFFERS);
2096 buffer = build_indexed_load_const(ctx, rw_buffers,
2097 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2098
2099 /* Get the offset. */
2100 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2101 SI_PARAM_TESS_FACTOR_OFFSET);
2102 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2103 lp_build_const_int32(gallivm, 4 * stride), "");
2104
2105 /* Store the outputs. */
2106 build_tbuffer_store_dwords(ctx, buffer, vec0,
2107 MIN2(stride, 4), byteoffset, tf_base, 0);
2108 if (vec1)
2109 build_tbuffer_store_dwords(ctx, buffer, vec1,
2110 stride - 4, byteoffset, tf_base, 16);
2111 lp_build_endif(&if_ctx);
2112 }
2113
2114 /* This only writes the tessellation factor levels. */
2115 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2116 {
2117 struct si_shader_context *ctx = si_shader_context(bld_base);
2118 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2119
2120 rel_patch_id = get_rel_patch_id(ctx);
2121 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2122 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2123
2124 if (!ctx->is_monolithic) {
2125 /* Return epilog parameters from this function. */
2126 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2127 LLVMValueRef ret = ctx->return_value;
2128 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2129 unsigned vgpr;
2130
2131 /* RW_BUFFERS pointer */
2132 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2133 SI_PARAM_RW_BUFFERS);
2134 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2135 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2136 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2137 bld_base->uint_bld.zero, "");
2138 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2139 bld_base->uint_bld.one, "");
2140 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2141 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2142
2143 /* Tess factor buffer soffset is after user SGPRs. */
2144 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2145 SI_PARAM_TESS_FACTOR_OFFSET);
2146 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2147 SI_TCS_NUM_USER_SGPR, "");
2148
2149 /* VGPRs */
2150 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2151 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2152 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2153
2154 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2155 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2156 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2157 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2158 ctx->return_value = ret;
2159 return;
2160 }
2161
2162 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2163 }
2164
2165 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2166 {
2167 struct si_shader_context *ctx = si_shader_context(bld_base);
2168 struct si_shader *shader = ctx->shader;
2169 struct tgsi_shader_info *info = &shader->selector->info;
2170 struct gallivm_state *gallivm = bld_base->base.gallivm;
2171 unsigned i, chan;
2172 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2173 ctx->param_rel_auto_id);
2174 LLVMValueRef vertex_dw_stride =
2175 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2176 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2177 vertex_dw_stride, "");
2178
2179 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2180 * its inputs from it. */
2181 for (i = 0; i < info->num_outputs; i++) {
2182 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2183 unsigned name = info->output_semantic_name[i];
2184 unsigned index = info->output_semantic_index[i];
2185 int param = si_shader_io_get_unique_index(name, index);
2186 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2187 lp_build_const_int32(gallivm, param * 4), "");
2188
2189 for (chan = 0; chan < 4; chan++) {
2190 lds_store(bld_base, chan, dw_addr,
2191 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2192 }
2193 }
2194 }
2195
2196 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2197 {
2198 struct si_shader_context *ctx = si_shader_context(bld_base);
2199 struct gallivm_state *gallivm = bld_base->base.gallivm;
2200 struct si_shader *es = ctx->shader;
2201 struct tgsi_shader_info *info = &es->selector->info;
2202 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2203 ctx->param_es2gs_offset);
2204 unsigned chan;
2205 int i;
2206
2207 for (i = 0; i < info->num_outputs; i++) {
2208 LLVMValueRef *out_ptr =
2209 ctx->radeon_bld.soa.outputs[i];
2210 int param_index;
2211
2212 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2213 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2214 continue;
2215
2216 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2217 info->output_semantic_index[i]);
2218
2219 for (chan = 0; chan < 4; chan++) {
2220 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2221 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2222
2223 build_tbuffer_store(ctx,
2224 ctx->esgs_ring,
2225 out_val, 1,
2226 LLVMGetUndef(ctx->i32), soffset,
2227 (4 * param_index + chan) * 4,
2228 V_008F0C_BUF_DATA_FORMAT_32,
2229 V_008F0C_BUF_NUM_FORMAT_UINT,
2230 0, 0, 1, 1, 0);
2231 }
2232 }
2233 }
2234
2235 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2236 {
2237 struct si_shader_context *ctx = si_shader_context(bld_base);
2238 struct gallivm_state *gallivm = bld_base->base.gallivm;
2239 LLVMValueRef args[2];
2240
2241 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2242 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2243 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2244 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2245 }
2246
2247 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2248 {
2249 struct si_shader_context *ctx = si_shader_context(bld_base);
2250 struct gallivm_state *gallivm = bld_base->base.gallivm;
2251 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2252 struct si_shader_output_values *outputs = NULL;
2253 int i,j;
2254
2255 assert(!ctx->is_gs_copy_shader);
2256
2257 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2258
2259 /* Vertex color clamping.
2260 *
2261 * This uses a state constant loaded in a user data SGPR and
2262 * an IF statement is added that clamps all colors if the constant
2263 * is true.
2264 */
2265 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2266 struct lp_build_if_state if_ctx;
2267 LLVMValueRef cond = NULL;
2268 LLVMValueRef addr, val;
2269
2270 for (i = 0; i < info->num_outputs; i++) {
2271 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2272 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2273 continue;
2274
2275 /* We've found a color. */
2276 if (!cond) {
2277 /* The state is in the first bit of the user SGPR. */
2278 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2279 SI_PARAM_VS_STATE_BITS);
2280 cond = LLVMBuildTrunc(gallivm->builder, cond,
2281 ctx->i1, "");
2282 lp_build_if(&if_ctx, gallivm, cond);
2283 }
2284
2285 for (j = 0; j < 4; j++) {
2286 addr = ctx->radeon_bld.soa.outputs[i][j];
2287 val = LLVMBuildLoad(gallivm->builder, addr, "");
2288 val = radeon_llvm_saturate(bld_base, val);
2289 LLVMBuildStore(gallivm->builder, val, addr);
2290 }
2291 }
2292
2293 if (cond)
2294 lp_build_endif(&if_ctx);
2295 }
2296
2297 for (i = 0; i < info->num_outputs; i++) {
2298 outputs[i].name = info->output_semantic_name[i];
2299 outputs[i].sid = info->output_semantic_index[i];
2300
2301 for (j = 0; j < 4; j++)
2302 outputs[i].values[j] =
2303 LLVMBuildLoad(gallivm->builder,
2304 ctx->radeon_bld.soa.outputs[i][j],
2305 "");
2306 }
2307
2308 if (ctx->is_monolithic) {
2309 /* Export PrimitiveID when PS needs it. */
2310 if (si_vs_exports_prim_id(ctx->shader)) {
2311 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2312 outputs[i].sid = 0;
2313 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2314 get_primitive_id(bld_base, 0));
2315 outputs[i].values[1] = bld_base->base.undef;
2316 outputs[i].values[2] = bld_base->base.undef;
2317 outputs[i].values[3] = bld_base->base.undef;
2318 i++;
2319 }
2320 } else {
2321 /* Return the primitive ID from the LLVM function. */
2322 ctx->return_value =
2323 LLVMBuildInsertValue(gallivm->builder,
2324 ctx->return_value,
2325 bitcast(bld_base, TGSI_TYPE_FLOAT,
2326 get_primitive_id(bld_base, 0)),
2327 VS_EPILOG_PRIMID_LOC, "");
2328 }
2329
2330 si_llvm_export_vs(bld_base, outputs, i);
2331 FREE(outputs);
2332 }
2333
2334 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2335 LLVMValueRef depth, LLVMValueRef stencil,
2336 LLVMValueRef samplemask)
2337 {
2338 struct si_shader_context *ctx = si_shader_context(bld_base);
2339 struct lp_build_context *base = &bld_base->base;
2340 struct lp_build_context *uint = &bld_base->uint_bld;
2341 LLVMValueRef args[9];
2342 unsigned mask = 0;
2343
2344 assert(depth || stencil || samplemask);
2345
2346 args[1] = uint->one; /* whether the EXEC mask is valid */
2347 args[2] = uint->one; /* DONE bit */
2348
2349 /* Specify the target we are exporting */
2350 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2351
2352 args[4] = uint->zero; /* COMP flag */
2353 args[5] = base->undef; /* R, depth */
2354 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2355 args[7] = base->undef; /* B, sample mask */
2356 args[8] = base->undef; /* A, alpha to mask */
2357
2358 if (depth) {
2359 args[5] = depth;
2360 mask |= 0x1;
2361 }
2362
2363 if (stencil) {
2364 args[6] = stencil;
2365 mask |= 0x2;
2366 }
2367
2368 if (samplemask) {
2369 args[7] = samplemask;
2370 mask |= 0x4;
2371 }
2372
2373 /* SI (except OLAND) has a bug that it only looks
2374 * at the X writemask component. */
2375 if (ctx->screen->b.chip_class == SI &&
2376 ctx->screen->b.family != CHIP_OLAND)
2377 mask |= 0x1;
2378
2379 /* Specify which components to enable */
2380 args[0] = lp_build_const_int32(base->gallivm, mask);
2381
2382 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2383 ctx->voidt, args, 9, 0);
2384 }
2385
2386 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2387 LLVMValueRef *color, unsigned index,
2388 unsigned samplemask_param,
2389 bool is_last)
2390 {
2391 struct si_shader_context *ctx = si_shader_context(bld_base);
2392 struct lp_build_context *base = &bld_base->base;
2393 int i;
2394
2395 /* Clamp color */
2396 if (ctx->shader->key.ps.epilog.clamp_color)
2397 for (i = 0; i < 4; i++)
2398 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2399
2400 /* Alpha to one */
2401 if (ctx->shader->key.ps.epilog.alpha_to_one)
2402 color[3] = base->one;
2403
2404 /* Alpha test */
2405 if (index == 0 &&
2406 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2407 si_alpha_test(bld_base, color[3]);
2408
2409 /* Line & polygon smoothing */
2410 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2411 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2412 samplemask_param);
2413
2414 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2415 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2416 LLVMValueRef args[8][9];
2417 int c, last = -1;
2418
2419 /* Get the export arguments, also find out what the last one is. */
2420 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2421 si_llvm_init_export_args(bld_base, color,
2422 V_008DFC_SQ_EXP_MRT + c, args[c]);
2423 if (args[c][0] != bld_base->uint_bld.zero)
2424 last = c;
2425 }
2426
2427 /* Emit all exports. */
2428 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2429 if (is_last && last == c) {
2430 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2431 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2432 } else if (args[c][0] == bld_base->uint_bld.zero)
2433 continue; /* unnecessary NULL export */
2434
2435 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2436 ctx->voidt, args[c], 9, 0);
2437 }
2438 } else {
2439 LLVMValueRef args[9];
2440
2441 /* Export */
2442 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2443 args);
2444 if (is_last) {
2445 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2446 args[2] = bld_base->uint_bld.one; /* DONE bit */
2447 } else if (args[0] == bld_base->uint_bld.zero)
2448 return; /* unnecessary NULL export */
2449
2450 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2451 ctx->voidt, args, 9, 0);
2452 }
2453 }
2454
2455 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2456 {
2457 struct si_shader_context *ctx = si_shader_context(bld_base);
2458 struct lp_build_context *base = &bld_base->base;
2459 struct lp_build_context *uint = &bld_base->uint_bld;
2460 LLVMValueRef args[9];
2461
2462 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2463 args[1] = uint->one; /* whether the EXEC mask is valid */
2464 args[2] = uint->one; /* DONE bit */
2465 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2466 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2467 args[5] = uint->undef; /* R */
2468 args[6] = uint->undef; /* G */
2469 args[7] = uint->undef; /* B */
2470 args[8] = uint->undef; /* A */
2471
2472 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2473 ctx->voidt, args, 9, 0);
2474 }
2475
2476 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2477 {
2478 struct si_shader_context *ctx = si_shader_context(bld_base);
2479 struct si_shader *shader = ctx->shader;
2480 struct lp_build_context *base = &bld_base->base;
2481 struct tgsi_shader_info *info = &shader->selector->info;
2482 LLVMBuilderRef builder = base->gallivm->builder;
2483 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2484 int last_color_export = -1;
2485 int i;
2486
2487 /* Determine the last export. If MRTZ is present, it's always last.
2488 * Otherwise, find the last color export.
2489 */
2490 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2491 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2492
2493 /* Don't export NULL and return if alpha-test is enabled. */
2494 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2495 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2496 (spi_format & 0xf) == 0)
2497 spi_format |= V_028714_SPI_SHADER_32_AR;
2498
2499 for (i = 0; i < info->num_outputs; i++) {
2500 unsigned index = info->output_semantic_index[i];
2501
2502 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2503 continue;
2504
2505 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2506 if (shader->key.ps.epilog.last_cbuf > 0) {
2507 /* Just set this if any of the colorbuffers are enabled. */
2508 if (spi_format &
2509 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2510 last_color_export = i;
2511 continue;
2512 }
2513
2514 if ((spi_format >> (index * 4)) & 0xf)
2515 last_color_export = i;
2516 }
2517
2518 /* If there are no outputs, export NULL. */
2519 if (last_color_export == -1) {
2520 si_export_null(bld_base);
2521 return;
2522 }
2523 }
2524
2525 for (i = 0; i < info->num_outputs; i++) {
2526 unsigned semantic_name = info->output_semantic_name[i];
2527 unsigned semantic_index = info->output_semantic_index[i];
2528 unsigned j;
2529 LLVMValueRef color[4] = {};
2530
2531 /* Select the correct target */
2532 switch (semantic_name) {
2533 case TGSI_SEMANTIC_POSITION:
2534 depth = LLVMBuildLoad(builder,
2535 ctx->radeon_bld.soa.outputs[i][2], "");
2536 break;
2537 case TGSI_SEMANTIC_STENCIL:
2538 stencil = LLVMBuildLoad(builder,
2539 ctx->radeon_bld.soa.outputs[i][1], "");
2540 break;
2541 case TGSI_SEMANTIC_SAMPLEMASK:
2542 samplemask = LLVMBuildLoad(builder,
2543 ctx->radeon_bld.soa.outputs[i][0], "");
2544 break;
2545 case TGSI_SEMANTIC_COLOR:
2546 for (j = 0; j < 4; j++)
2547 color[j] = LLVMBuildLoad(builder,
2548 ctx->radeon_bld.soa.outputs[i][j], "");
2549
2550 si_export_mrt_color(bld_base, color, semantic_index,
2551 SI_PARAM_SAMPLE_COVERAGE,
2552 last_color_export == i);
2553 break;
2554 default:
2555 fprintf(stderr,
2556 "Warning: SI unhandled fs output type:%d\n",
2557 semantic_name);
2558 }
2559 }
2560
2561 if (depth || stencil || samplemask)
2562 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2563 }
2564
2565 /**
2566 * Return PS outputs in this order:
2567 *
2568 * v[0:3] = color0.xyzw
2569 * v[4:7] = color1.xyzw
2570 * ...
2571 * vN+0 = Depth
2572 * vN+1 = Stencil
2573 * vN+2 = SampleMask
2574 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2575 *
2576 * The alpha-ref SGPR is returned via its original location.
2577 */
2578 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2579 {
2580 struct si_shader_context *ctx = si_shader_context(bld_base);
2581 struct si_shader *shader = ctx->shader;
2582 struct lp_build_context *base = &bld_base->base;
2583 struct tgsi_shader_info *info = &shader->selector->info;
2584 LLVMBuilderRef builder = base->gallivm->builder;
2585 unsigned i, j, first_vgpr, vgpr;
2586
2587 LLVMValueRef color[8][4] = {};
2588 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2589 LLVMValueRef ret;
2590
2591 /* Read the output values. */
2592 for (i = 0; i < info->num_outputs; i++) {
2593 unsigned semantic_name = info->output_semantic_name[i];
2594 unsigned semantic_index = info->output_semantic_index[i];
2595
2596 switch (semantic_name) {
2597 case TGSI_SEMANTIC_COLOR:
2598 assert(semantic_index < 8);
2599 for (j = 0; j < 4; j++) {
2600 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2601 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2602 color[semantic_index][j] = result;
2603 }
2604 break;
2605 case TGSI_SEMANTIC_POSITION:
2606 depth = LLVMBuildLoad(builder,
2607 ctx->radeon_bld.soa.outputs[i][2], "");
2608 break;
2609 case TGSI_SEMANTIC_STENCIL:
2610 stencil = LLVMBuildLoad(builder,
2611 ctx->radeon_bld.soa.outputs[i][1], "");
2612 break;
2613 case TGSI_SEMANTIC_SAMPLEMASK:
2614 samplemask = LLVMBuildLoad(builder,
2615 ctx->radeon_bld.soa.outputs[i][0], "");
2616 break;
2617 default:
2618 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2619 semantic_name);
2620 }
2621 }
2622
2623 /* Fill the return structure. */
2624 ret = ctx->return_value;
2625
2626 /* Set SGPRs. */
2627 ret = LLVMBuildInsertValue(builder, ret,
2628 bitcast(bld_base, TGSI_TYPE_SIGNED,
2629 LLVMGetParam(ctx->radeon_bld.main_fn,
2630 SI_PARAM_ALPHA_REF)),
2631 SI_SGPR_ALPHA_REF, "");
2632
2633 /* Set VGPRs */
2634 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2635 for (i = 0; i < ARRAY_SIZE(color); i++) {
2636 if (!color[i][0])
2637 continue;
2638
2639 for (j = 0; j < 4; j++)
2640 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2641 }
2642 if (depth)
2643 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2644 if (stencil)
2645 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2646 if (samplemask)
2647 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2648
2649 /* Add the input sample mask for smoothing at the end. */
2650 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2651 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2652 ret = LLVMBuildInsertValue(builder, ret,
2653 LLVMGetParam(ctx->radeon_bld.main_fn,
2654 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2655
2656 ctx->return_value = ret;
2657 }
2658
2659 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2660 struct lp_build_tgsi_context *bld_base,
2661 struct lp_build_emit_data *emit_data);
2662
2663 static bool tgsi_is_array_sampler(unsigned target)
2664 {
2665 return target == TGSI_TEXTURE_1D_ARRAY ||
2666 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2667 target == TGSI_TEXTURE_2D_ARRAY ||
2668 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2669 target == TGSI_TEXTURE_CUBE_ARRAY ||
2670 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2671 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2672 }
2673
2674 static void set_tex_fetch_args(struct si_shader_context *ctx,
2675 struct lp_build_emit_data *emit_data,
2676 unsigned opcode, unsigned target,
2677 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2678 LLVMValueRef *param, unsigned count,
2679 unsigned dmask)
2680 {
2681 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2682 unsigned num_args;
2683 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2684
2685 /* Pad to power of two vector */
2686 while (count < util_next_power_of_two(count))
2687 param[count++] = LLVMGetUndef(ctx->i32);
2688
2689 /* Texture coordinates. */
2690 if (count > 1)
2691 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2692 else
2693 emit_data->args[0] = param[0];
2694
2695 /* Resource. */
2696 emit_data->args[1] = res_ptr;
2697 num_args = 2;
2698
2699 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2700 emit_data->dst_type = ctx->v4i32;
2701 else {
2702 emit_data->dst_type = ctx->v4f32;
2703
2704 emit_data->args[num_args++] = samp_ptr;
2705 }
2706
2707 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2708 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2709 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2710 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2711 tgsi_is_array_sampler(target)); /* da */
2712 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2713 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2714 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2715 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2716
2717 emit_data->arg_count = num_args;
2718 }
2719
2720 static const struct lp_build_tgsi_action tex_action;
2721
2722 enum desc_type {
2723 DESC_IMAGE,
2724 DESC_FMASK,
2725 DESC_SAMPLER
2726 };
2727
2728 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2729 {
2730 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2731 CONST_ADDR_SPACE);
2732 }
2733
2734 /**
2735 * Load an image view, fmask view. or sampler state descriptor.
2736 */
2737 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
2738 LLVMValueRef list, LLVMValueRef index,
2739 enum desc_type type)
2740 {
2741 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2742 LLVMBuilderRef builder = gallivm->builder;
2743
2744 switch (type) {
2745 case DESC_IMAGE:
2746 /* The image is at [0:7]. */
2747 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
2748 break;
2749 case DESC_FMASK:
2750 /* The FMASK is at [8:15]. */
2751 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
2752 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
2753 break;
2754 case DESC_SAMPLER:
2755 /* The sampler state is at [12:15]. */
2756 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
2757 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
2758 list = LLVMBuildPointerCast(builder, list,
2759 const_array(ctx->v4i32, 0), "");
2760 break;
2761 }
2762
2763 return build_indexed_load_const(ctx, list, index);
2764 }
2765
2766 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
2767 LLVMValueRef index, enum desc_type type)
2768 {
2769 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
2770 SI_PARAM_SAMPLERS);
2771
2772 return get_sampler_desc_custom(ctx, list, index, type);
2773 }
2774
2775 static void tex_fetch_ptrs(
2776 struct lp_build_tgsi_context *bld_base,
2777 struct lp_build_emit_data *emit_data,
2778 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2779 {
2780 struct si_shader_context *ctx = si_shader_context(bld_base);
2781 const struct tgsi_full_instruction *inst = emit_data->inst;
2782 unsigned target = inst->Texture.Texture;
2783 unsigned sampler_src;
2784 unsigned sampler_index;
2785
2786 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2787 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2788
2789 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2790 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2791 LLVMValueRef ind_index;
2792
2793 ind_index = get_indirect_index(ctx, &reg->Indirect, reg->Register.Index);
2794
2795 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
2796
2797 if (target == TGSI_TEXTURE_2D_MSAA ||
2798 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2799 *samp_ptr = NULL;
2800 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
2801 } else {
2802 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
2803 *fmask_ptr = NULL;
2804 }
2805 } else {
2806 *res_ptr = ctx->sampler_views[sampler_index];
2807 *samp_ptr = ctx->sampler_states[sampler_index];
2808 *fmask_ptr = ctx->fmasks[sampler_index];
2809 }
2810 }
2811
2812 static void tex_fetch_args(
2813 struct lp_build_tgsi_context *bld_base,
2814 struct lp_build_emit_data *emit_data)
2815 {
2816 struct si_shader_context *ctx = si_shader_context(bld_base);
2817 struct gallivm_state *gallivm = bld_base->base.gallivm;
2818 LLVMBuilderRef builder = gallivm->builder;
2819 const struct tgsi_full_instruction *inst = emit_data->inst;
2820 unsigned opcode = inst->Instruction.Opcode;
2821 unsigned target = inst->Texture.Texture;
2822 LLVMValueRef coords[5], derivs[6];
2823 LLVMValueRef address[16];
2824 int ref_pos;
2825 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2826 unsigned count = 0;
2827 unsigned chan;
2828 unsigned num_deriv_channels = 0;
2829 bool has_offset = inst->Texture.NumOffsets > 0;
2830 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2831 unsigned dmask = 0xf;
2832
2833 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2834
2835 if (opcode == TGSI_OPCODE_TXQ) {
2836 if (target == TGSI_TEXTURE_BUFFER) {
2837 /* Read the size from the buffer descriptor directly. */
2838 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
2839 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2840 lp_build_const_int32(gallivm, 6), "");
2841
2842 if (ctx->screen->b.chip_class >= VI) {
2843 /* On VI, the descriptor contains the size in bytes,
2844 * but TXQ must return the size in elements.
2845 * The stride is always non-zero for resources using TXQ.
2846 */
2847 LLVMValueRef stride =
2848 LLVMBuildExtractElement(builder, res,
2849 lp_build_const_int32(gallivm, 5), "");
2850 stride = LLVMBuildLShr(builder, stride,
2851 lp_build_const_int32(gallivm, 16), "");
2852 stride = LLVMBuildAnd(builder, stride,
2853 lp_build_const_int32(gallivm, 0x3FFF), "");
2854
2855 size = LLVMBuildUDiv(builder, size, stride, "");
2856 }
2857
2858 emit_data->args[0] = size;
2859 return;
2860 }
2861
2862 /* Textures - set the mip level. */
2863 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2864
2865 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
2866 NULL, address, count, 0xf);
2867 return;
2868 }
2869
2870 if (target == TGSI_TEXTURE_BUFFER) {
2871 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
2872
2873 /* Bitcast and truncate v8i32 to v16i8. */
2874 LLVMValueRef res = res_ptr;
2875 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2876 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2877 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
2878
2879 emit_data->dst_type = ctx->v4f32;
2880 emit_data->args[0] = res;
2881 emit_data->args[1] = bld_base->uint_bld.zero;
2882 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2883 emit_data->arg_count = 3;
2884 return;
2885 }
2886
2887 /* Fetch and project texture coordinates */
2888 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2889 for (chan = 0; chan < 3; chan++ ) {
2890 coords[chan] = lp_build_emit_fetch(bld_base,
2891 emit_data->inst, 0,
2892 chan);
2893 if (opcode == TGSI_OPCODE_TXP)
2894 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2895 TGSI_OPCODE_DIV,
2896 coords[chan],
2897 coords[3]);
2898 }
2899
2900 if (opcode == TGSI_OPCODE_TXP)
2901 coords[3] = bld_base->base.one;
2902
2903 /* Pack offsets. */
2904 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2905 /* The offsets are six-bit signed integers packed like this:
2906 * X=[5:0], Y=[13:8], and Z=[21:16].
2907 */
2908 LLVMValueRef offset[3], pack;
2909
2910 assert(inst->Texture.NumOffsets == 1);
2911
2912 for (chan = 0; chan < 3; chan++) {
2913 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2914 emit_data->inst, 0, chan);
2915 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2916 lp_build_const_int32(gallivm, 0x3f), "");
2917 if (chan)
2918 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2919 lp_build_const_int32(gallivm, chan*8), "");
2920 }
2921
2922 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2923 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2924 address[count++] = pack;
2925 }
2926
2927 /* Pack LOD bias value */
2928 if (opcode == TGSI_OPCODE_TXB)
2929 address[count++] = coords[3];
2930 if (opcode == TGSI_OPCODE_TXB2)
2931 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2932
2933 /* Pack depth comparison value */
2934 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2935 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2936 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2937 } else {
2938 assert(ref_pos >= 0);
2939 address[count++] = coords[ref_pos];
2940 }
2941 }
2942
2943 /* Pack user derivatives */
2944 if (opcode == TGSI_OPCODE_TXD) {
2945 int param, num_src_deriv_channels;
2946
2947 switch (target) {
2948 case TGSI_TEXTURE_3D:
2949 num_src_deriv_channels = 3;
2950 num_deriv_channels = 3;
2951 break;
2952 case TGSI_TEXTURE_2D:
2953 case TGSI_TEXTURE_SHADOW2D:
2954 case TGSI_TEXTURE_RECT:
2955 case TGSI_TEXTURE_SHADOWRECT:
2956 case TGSI_TEXTURE_2D_ARRAY:
2957 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2958 num_src_deriv_channels = 2;
2959 num_deriv_channels = 2;
2960 break;
2961 case TGSI_TEXTURE_CUBE:
2962 case TGSI_TEXTURE_SHADOWCUBE:
2963 case TGSI_TEXTURE_CUBE_ARRAY:
2964 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2965 /* Cube derivatives will be converted to 2D. */
2966 num_src_deriv_channels = 3;
2967 num_deriv_channels = 2;
2968 break;
2969 case TGSI_TEXTURE_1D:
2970 case TGSI_TEXTURE_SHADOW1D:
2971 case TGSI_TEXTURE_1D_ARRAY:
2972 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2973 num_src_deriv_channels = 1;
2974 num_deriv_channels = 1;
2975 break;
2976 default:
2977 unreachable("invalid target");
2978 }
2979
2980 for (param = 0; param < 2; param++)
2981 for (chan = 0; chan < num_src_deriv_channels; chan++)
2982 derivs[param * num_src_deriv_channels + chan] =
2983 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2984 }
2985
2986 if (target == TGSI_TEXTURE_CUBE ||
2987 target == TGSI_TEXTURE_CUBE_ARRAY ||
2988 target == TGSI_TEXTURE_SHADOWCUBE ||
2989 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2990 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2991
2992 if (opcode == TGSI_OPCODE_TXD)
2993 for (int i = 0; i < num_deriv_channels * 2; i++)
2994 address[count++] = derivs[i];
2995
2996 /* Pack texture coordinates */
2997 address[count++] = coords[0];
2998 if (num_coords > 1)
2999 address[count++] = coords[1];
3000 if (num_coords > 2)
3001 address[count++] = coords[2];
3002
3003 /* Pack LOD or sample index */
3004 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
3005 address[count++] = coords[3];
3006 else if (opcode == TGSI_OPCODE_TXL2)
3007 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3008
3009 if (count > 16) {
3010 assert(!"Cannot handle more than 16 texture address parameters");
3011 count = 16;
3012 }
3013
3014 for (chan = 0; chan < count; chan++ ) {
3015 address[chan] = LLVMBuildBitCast(gallivm->builder,
3016 address[chan], ctx->i32, "");
3017 }
3018
3019 /* Adjust the sample index according to FMASK.
3020 *
3021 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3022 * which is the identity mapping. Each nibble says which physical sample
3023 * should be fetched to get that sample.
3024 *
3025 * For example, 0x11111100 means there are only 2 samples stored and
3026 * the second sample covers 3/4 of the pixel. When reading samples 0
3027 * and 1, return physical sample 0 (determined by the first two 0s
3028 * in FMASK), otherwise return physical sample 1.
3029 *
3030 * The sample index should be adjusted as follows:
3031 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3032 */
3033 if (target == TGSI_TEXTURE_2D_MSAA ||
3034 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3035 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3036 struct lp_build_emit_data txf_emit_data = *emit_data;
3037 LLVMValueRef txf_address[4];
3038 unsigned txf_count = count;
3039 struct tgsi_full_instruction inst = {};
3040
3041 memcpy(txf_address, address, sizeof(txf_address));
3042
3043 if (target == TGSI_TEXTURE_2D_MSAA) {
3044 txf_address[2] = bld_base->uint_bld.zero;
3045 }
3046 txf_address[3] = bld_base->uint_bld.zero;
3047
3048 /* Read FMASK using TXF. */
3049 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
3050 inst.Texture.Texture = target;
3051 txf_emit_data.inst = &inst;
3052 txf_emit_data.chan = 0;
3053 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
3054 target, fmask_ptr, NULL,
3055 txf_address, txf_count, 0xf);
3056 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
3057
3058 /* Initialize some constants. */
3059 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
3060 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
3061
3062 /* Apply the formula. */
3063 LLVMValueRef fmask =
3064 LLVMBuildExtractElement(gallivm->builder,
3065 txf_emit_data.output[0],
3066 uint_bld->zero, "");
3067
3068 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
3069
3070 LLVMValueRef sample_index4 =
3071 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
3072
3073 LLVMValueRef shifted_fmask =
3074 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
3075
3076 LLVMValueRef final_sample =
3077 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
3078
3079 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3080 * resource descriptor is 0 (invalid),
3081 */
3082 LLVMValueRef fmask_desc =
3083 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
3084 ctx->v8i32, "");
3085
3086 LLVMValueRef fmask_word1 =
3087 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
3088 uint_bld->one, "");
3089
3090 LLVMValueRef word1_is_nonzero =
3091 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3092 fmask_word1, uint_bld->zero, "");
3093
3094 /* Replace the MSAA sample index. */
3095 address[sample_chan] =
3096 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
3097 final_sample, address[sample_chan], "");
3098 }
3099
3100 if (opcode == TGSI_OPCODE_TXF) {
3101 /* add tex offsets */
3102 if (inst->Texture.NumOffsets) {
3103 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3104 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
3105 const struct tgsi_texture_offset *off = inst->TexOffsets;
3106
3107 assert(inst->Texture.NumOffsets == 1);
3108
3109 switch (target) {
3110 case TGSI_TEXTURE_3D:
3111 address[2] = lp_build_add(uint_bld, address[2],
3112 bld->immediates[off->Index][off->SwizzleZ]);
3113 /* fall through */
3114 case TGSI_TEXTURE_2D:
3115 case TGSI_TEXTURE_SHADOW2D:
3116 case TGSI_TEXTURE_RECT:
3117 case TGSI_TEXTURE_SHADOWRECT:
3118 case TGSI_TEXTURE_2D_ARRAY:
3119 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3120 address[1] =
3121 lp_build_add(uint_bld, address[1],
3122 bld->immediates[off->Index][off->SwizzleY]);
3123 /* fall through */
3124 case TGSI_TEXTURE_1D:
3125 case TGSI_TEXTURE_SHADOW1D:
3126 case TGSI_TEXTURE_1D_ARRAY:
3127 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3128 address[0] =
3129 lp_build_add(uint_bld, address[0],
3130 bld->immediates[off->Index][off->SwizzleX]);
3131 break;
3132 /* texture offsets do not apply to other texture targets */
3133 }
3134 }
3135 }
3136
3137 if (opcode == TGSI_OPCODE_TG4) {
3138 unsigned gather_comp = 0;
3139
3140 /* DMASK was repurposed for GATHER4. 4 components are always
3141 * returned and DMASK works like a swizzle - it selects
3142 * the component to fetch. The only valid DMASK values are
3143 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3144 * (red,red,red,red) etc.) The ISA document doesn't mention
3145 * this.
3146 */
3147
3148 /* Get the component index from src1.x for Gather4. */
3149 if (!tgsi_is_shadow_target(target)) {
3150 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3151 LLVMValueRef comp_imm;
3152 struct tgsi_src_register src1 = inst->Src[1].Register;
3153
3154 assert(src1.File == TGSI_FILE_IMMEDIATE);
3155
3156 comp_imm = imms[src1.Index][src1.SwizzleX];
3157 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
3158 gather_comp = CLAMP(gather_comp, 0, 3);
3159 }
3160
3161 dmask = 1 << gather_comp;
3162 }
3163
3164 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3165 samp_ptr, address, count, dmask);
3166 }
3167
3168 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3169 struct lp_build_tgsi_context *bld_base,
3170 struct lp_build_emit_data *emit_data)
3171 {
3172 struct lp_build_context *base = &bld_base->base;
3173 unsigned opcode = emit_data->inst->Instruction.Opcode;
3174 unsigned target = emit_data->inst->Texture.Texture;
3175 char intr_name[127];
3176 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
3177 bool is_shadow = tgsi_is_shadow_target(target);
3178 char type[64];
3179 const char *name = "llvm.SI.image.sample";
3180 const char *infix = "";
3181
3182 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
3183 /* Just return the buffer size. */
3184 emit_data->output[emit_data->chan] = emit_data->args[0];
3185 return;
3186 }
3187
3188 if (target == TGSI_TEXTURE_BUFFER) {
3189 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3190 base->gallivm->builder,
3191 "llvm.SI.vs.load.input", emit_data->dst_type,
3192 emit_data->args, emit_data->arg_count,
3193 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3194 return;
3195 }
3196
3197 switch (opcode) {
3198 case TGSI_OPCODE_TXF:
3199 name = target == TGSI_TEXTURE_2D_MSAA ||
3200 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
3201 "llvm.SI.image.load" :
3202 "llvm.SI.image.load.mip";
3203 is_shadow = false;
3204 has_offset = false;
3205 break;
3206 case TGSI_OPCODE_TXQ:
3207 name = "llvm.SI.getresinfo";
3208 is_shadow = false;
3209 has_offset = false;
3210 break;
3211 case TGSI_OPCODE_LODQ:
3212 name = "llvm.SI.getlod";
3213 is_shadow = false;
3214 has_offset = false;
3215 break;
3216 case TGSI_OPCODE_TEX:
3217 case TGSI_OPCODE_TEX2:
3218 case TGSI_OPCODE_TXP:
3219 break;
3220 case TGSI_OPCODE_TXB:
3221 case TGSI_OPCODE_TXB2:
3222 infix = ".b";
3223 break;
3224 case TGSI_OPCODE_TXL:
3225 case TGSI_OPCODE_TXL2:
3226 infix = ".l";
3227 break;
3228 case TGSI_OPCODE_TXD:
3229 infix = ".d";
3230 break;
3231 case TGSI_OPCODE_TG4:
3232 name = "llvm.SI.gather4";
3233 break;
3234 default:
3235 assert(0);
3236 return;
3237 }
3238
3239 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
3240 sprintf(type, ".v%ui32",
3241 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
3242 else
3243 strcpy(type, ".i32");
3244
3245 /* Add the type and suffixes .c, .o if needed. */
3246 sprintf(intr_name, "%s%s%s%s%s",
3247 name, is_shadow ? ".c" : "", infix,
3248 has_offset ? ".o" : "", type);
3249
3250 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3251 base->gallivm->builder, intr_name, emit_data->dst_type,
3252 emit_data->args, emit_data->arg_count,
3253 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3254
3255 /* Divide the number of layers by 6 to get the number of cubes. */
3256 if (opcode == TGSI_OPCODE_TXQ &&
3257 (target == TGSI_TEXTURE_CUBE_ARRAY ||
3258 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
3259 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
3260 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
3261 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
3262
3263 LLVMValueRef v4 = emit_data->output[emit_data->chan];
3264 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
3265 z = LLVMBuildSDiv(builder, z, six, "");
3266
3267 emit_data->output[emit_data->chan] =
3268 LLVMBuildInsertElement(builder, v4, z, two, "");
3269 }
3270 }
3271
3272 static void si_llvm_emit_txqs(
3273 const struct lp_build_tgsi_action *action,
3274 struct lp_build_tgsi_context *bld_base,
3275 struct lp_build_emit_data *emit_data)
3276 {
3277 struct si_shader_context *ctx = si_shader_context(bld_base);
3278 struct gallivm_state *gallivm = bld_base->base.gallivm;
3279 LLVMBuilderRef builder = gallivm->builder;
3280 LLVMValueRef res, samples;
3281 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3282
3283 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3284
3285
3286 /* Read the samples from the descriptor directly. */
3287 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3288 samples = LLVMBuildExtractElement(
3289 builder, res,
3290 lp_build_const_int32(gallivm, 3), "");
3291 samples = LLVMBuildLShr(builder, samples,
3292 lp_build_const_int32(gallivm, 16), "");
3293 samples = LLVMBuildAnd(builder, samples,
3294 lp_build_const_int32(gallivm, 0xf), "");
3295 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3296 samples, "");
3297
3298 emit_data->output[emit_data->chan] = samples;
3299 }
3300
3301 /*
3302 * SI implements derivatives using the local data store (LDS)
3303 * All writes to the LDS happen in all executing threads at
3304 * the same time. TID is the Thread ID for the current
3305 * thread and is a value between 0 and 63, representing
3306 * the thread's position in the wavefront.
3307 *
3308 * For the pixel shader threads are grouped into quads of four pixels.
3309 * The TIDs of the pixels of a quad are:
3310 *
3311 * +------+------+
3312 * |4n + 0|4n + 1|
3313 * +------+------+
3314 * |4n + 2|4n + 3|
3315 * +------+------+
3316 *
3317 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3318 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3319 * the current pixel's column, and masking with 0xfffffffe yields the TID
3320 * of the left pixel of the current pixel's row.
3321 *
3322 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3323 * adding 2 yields the TID of the pixel below the top pixel.
3324 */
3325 /* masks for thread ID. */
3326 #define TID_MASK_TOP_LEFT 0xfffffffc
3327 #define TID_MASK_TOP 0xfffffffd
3328 #define TID_MASK_LEFT 0xfffffffe
3329
3330 static void si_llvm_emit_ddxy(
3331 const struct lp_build_tgsi_action *action,
3332 struct lp_build_tgsi_context *bld_base,
3333 struct lp_build_emit_data *emit_data)
3334 {
3335 struct si_shader_context *ctx = si_shader_context(bld_base);
3336 struct gallivm_state *gallivm = bld_base->base.gallivm;
3337 const struct tgsi_full_instruction *inst = emit_data->inst;
3338 unsigned opcode = inst->Instruction.Opcode;
3339 LLVMValueRef indices[2];
3340 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3341 LLVMValueRef tl, trbl, result[4];
3342 unsigned swizzle[4];
3343 unsigned c;
3344 int idx;
3345 unsigned mask;
3346
3347 indices[0] = bld_base->uint_bld.zero;
3348 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3349 NULL, 0, LLVMReadNoneAttribute);
3350 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3351 indices, 2, "");
3352
3353 if (opcode == TGSI_OPCODE_DDX_FINE)
3354 mask = TID_MASK_LEFT;
3355 else if (opcode == TGSI_OPCODE_DDY_FINE)
3356 mask = TID_MASK_TOP;
3357 else
3358 mask = TID_MASK_TOP_LEFT;
3359
3360 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3361 lp_build_const_int32(gallivm, mask), "");
3362 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3363 indices, 2, "");
3364
3365 /* for DDX we want to next X pixel, DDY next Y pixel. */
3366 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3367 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3368 lp_build_const_int32(gallivm, idx), "");
3369 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3370 indices, 2, "");
3371
3372 for (c = 0; c < 4; ++c) {
3373 unsigned i;
3374
3375 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3376 for (i = 0; i < c; ++i) {
3377 if (swizzle[i] == swizzle[c]) {
3378 result[c] = result[i];
3379 break;
3380 }
3381 }
3382 if (i != c)
3383 continue;
3384
3385 LLVMBuildStore(gallivm->builder,
3386 LLVMBuildBitCast(gallivm->builder,
3387 lp_build_emit_fetch(bld_base, inst, 0, c),
3388 ctx->i32, ""),
3389 store_ptr);
3390
3391 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3392 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3393
3394 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3395 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
3396
3397 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3398 }
3399
3400 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3401 }
3402
3403 /*
3404 * this takes an I,J coordinate pair,
3405 * and works out the X and Y derivatives.
3406 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3407 */
3408 static LLVMValueRef si_llvm_emit_ddxy_interp(
3409 struct lp_build_tgsi_context *bld_base,
3410 LLVMValueRef interp_ij)
3411 {
3412 struct si_shader_context *ctx = si_shader_context(bld_base);
3413 struct gallivm_state *gallivm = bld_base->base.gallivm;
3414 LLVMValueRef indices[2];
3415 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3416 LLVMValueRef tl, tr, bl, result[4];
3417 unsigned c;
3418
3419 indices[0] = bld_base->uint_bld.zero;
3420 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3421 NULL, 0, LLVMReadNoneAttribute);
3422 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3423 indices, 2, "");
3424
3425 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3426 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3427
3428 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3429 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3430
3431 indices[1] = temp;
3432 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
3433 indices, 2, "");
3434
3435 indices[1] = temp2;
3436 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
3437 indices, 2, "");
3438
3439 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3440 lp_build_const_int32(gallivm, 1), "");
3441 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
3442 indices, 2, "");
3443
3444 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3445 lp_build_const_int32(gallivm, 2), "");
3446 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
3447 indices, 2, "");
3448
3449 for (c = 0; c < 2; ++c) {
3450 LLVMValueRef store_val;
3451 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3452
3453 store_val = LLVMBuildExtractElement(gallivm->builder,
3454 interp_ij, c_ll, "");
3455 LLVMBuildStore(gallivm->builder,
3456 store_val,
3457 store_ptr);
3458
3459 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3460 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3461
3462 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3463 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
3464
3465 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3466
3467 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3468 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3469
3470 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3471 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
3472
3473 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3474 }
3475
3476 return lp_build_gather_values(gallivm, result, 4);
3477 }
3478
3479 static void interp_fetch_args(
3480 struct lp_build_tgsi_context *bld_base,
3481 struct lp_build_emit_data *emit_data)
3482 {
3483 struct si_shader_context *ctx = si_shader_context(bld_base);
3484 struct gallivm_state *gallivm = bld_base->base.gallivm;
3485 const struct tgsi_full_instruction *inst = emit_data->inst;
3486
3487 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3488 /* offset is in second src, first two channels */
3489 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3490 emit_data->inst, 1,
3491 TGSI_CHAN_X);
3492 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3493 emit_data->inst, 1,
3494 TGSI_CHAN_Y);
3495 emit_data->arg_count = 2;
3496 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3497 LLVMValueRef sample_position;
3498 LLVMValueRef sample_id;
3499 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3500
3501 /* fetch sample ID, then fetch its sample position,
3502 * and place into first two channels.
3503 */
3504 sample_id = lp_build_emit_fetch(bld_base,
3505 emit_data->inst, 1, TGSI_CHAN_X);
3506 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3507 ctx->i32, "");
3508 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
3509
3510 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3511 sample_position,
3512 lp_build_const_int32(gallivm, 0), "");
3513
3514 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3515 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3516 sample_position,
3517 lp_build_const_int32(gallivm, 1), "");
3518 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3519 emit_data->arg_count = 2;
3520 }
3521 }
3522
3523 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3524 struct lp_build_tgsi_context *bld_base,
3525 struct lp_build_emit_data *emit_data)
3526 {
3527 struct si_shader_context *ctx = si_shader_context(bld_base);
3528 struct si_shader *shader = ctx->shader;
3529 struct gallivm_state *gallivm = bld_base->base.gallivm;
3530 LLVMValueRef interp_param;
3531 const struct tgsi_full_instruction *inst = emit_data->inst;
3532 const char *intr_name;
3533 int input_index = inst->Src[0].Register.Index;
3534 int chan;
3535 int i;
3536 LLVMValueRef attr_number;
3537 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3538 int interp_param_idx;
3539 unsigned interp = shader->selector->info.input_interpolate[input_index];
3540 unsigned location;
3541
3542 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3543
3544 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3545 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3546 location = TGSI_INTERPOLATE_LOC_CENTER;
3547 else
3548 location = TGSI_INTERPOLATE_LOC_CENTROID;
3549
3550 interp_param_idx = lookup_interp_param_index(interp, location);
3551 if (interp_param_idx == -1)
3552 return;
3553 else if (interp_param_idx)
3554 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
3555 else
3556 interp_param = NULL;
3557
3558 attr_number = lp_build_const_int32(gallivm, input_index);
3559
3560 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3561 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3562 LLVMValueRef ij_out[2];
3563 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3564
3565 /*
3566 * take the I then J parameters, and the DDX/Y for it, and
3567 * calculate the IJ inputs for the interpolator.
3568 * temp1 = ddx * offset/sample.x + I;
3569 * interp_param.I = ddy * offset/sample.y + temp1;
3570 * temp1 = ddx * offset/sample.x + J;
3571 * interp_param.J = ddy * offset/sample.y + temp1;
3572 */
3573 for (i = 0; i < 2; i++) {
3574 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3575 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3576 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3577 ddxy_out, ix_ll, "");
3578 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3579 ddxy_out, iy_ll, "");
3580 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3581 interp_param, ix_ll, "");
3582 LLVMValueRef temp1, temp2;
3583
3584 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3585 ctx->f32, "");
3586
3587 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3588
3589 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3590
3591 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3592
3593 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3594
3595 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3596 temp2, ctx->i32, "");
3597 }
3598 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3599 }
3600
3601 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3602 for (chan = 0; chan < 2; chan++) {
3603 LLVMValueRef args[4];
3604 LLVMValueRef llvm_chan;
3605 unsigned schan;
3606
3607 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3608 llvm_chan = lp_build_const_int32(gallivm, schan);
3609
3610 args[0] = llvm_chan;
3611 args[1] = attr_number;
3612 args[2] = params;
3613 args[3] = interp_param;
3614
3615 emit_data->output[chan] =
3616 lp_build_intrinsic(gallivm->builder, intr_name,
3617 ctx->f32, args, args[3] ? 4 : 3,
3618 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3619 }
3620 }
3621
3622 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3623 struct lp_build_emit_data *emit_data)
3624 {
3625 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3626 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3627 unsigned stream;
3628
3629 assert(src0.File == TGSI_FILE_IMMEDIATE);
3630
3631 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3632 return stream;
3633 }
3634
3635 /* Emit one vertex from the geometry shader */
3636 static void si_llvm_emit_vertex(
3637 const struct lp_build_tgsi_action *action,
3638 struct lp_build_tgsi_context *bld_base,
3639 struct lp_build_emit_data *emit_data)
3640 {
3641 struct si_shader_context *ctx = si_shader_context(bld_base);
3642 struct lp_build_context *uint = &bld_base->uint_bld;
3643 struct si_shader *shader = ctx->shader;
3644 struct tgsi_shader_info *info = &shader->selector->info;
3645 struct gallivm_state *gallivm = bld_base->base.gallivm;
3646 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
3647 SI_PARAM_GS2VS_OFFSET);
3648 LLVMValueRef gs_next_vertex;
3649 LLVMValueRef can_emit, kill;
3650 LLVMValueRef args[2];
3651 unsigned chan;
3652 int i;
3653 unsigned stream;
3654
3655 stream = si_llvm_get_stream(bld_base, emit_data);
3656
3657 /* Write vertex attribute values to GSVS ring */
3658 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3659 ctx->gs_next_vertex[stream],
3660 "");
3661
3662 /* If this thread has already emitted the declared maximum number of
3663 * vertices, kill it: excessive vertex emissions are not supposed to
3664 * have any effect, and GS threads have no externally observable
3665 * effects other than emitting vertices.
3666 */
3667 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3668 lp_build_const_int32(gallivm,
3669 shader->selector->gs_max_out_vertices), "");
3670 kill = lp_build_select(&bld_base->base, can_emit,
3671 lp_build_const_float(gallivm, 1.0f),
3672 lp_build_const_float(gallivm, -1.0f));
3673
3674 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3675 ctx->voidt, &kill, 1, 0);
3676
3677 for (i = 0; i < info->num_outputs; i++) {
3678 LLVMValueRef *out_ptr =
3679 ctx->radeon_bld.soa.outputs[i];
3680
3681 for (chan = 0; chan < 4; chan++) {
3682 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3683 LLVMValueRef voffset =
3684 lp_build_const_int32(gallivm, (i * 4 + chan) *
3685 shader->selector->gs_max_out_vertices);
3686
3687 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3688 voffset = lp_build_mul_imm(uint, voffset, 4);
3689
3690 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3691
3692 build_tbuffer_store(ctx,
3693 ctx->gsvs_ring[stream],
3694 out_val, 1,
3695 voffset, soffset, 0,
3696 V_008F0C_BUF_DATA_FORMAT_32,
3697 V_008F0C_BUF_NUM_FORMAT_UINT,
3698 1, 0, 1, 1, 0);
3699 }
3700 }
3701 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3702 lp_build_const_int32(gallivm, 1));
3703
3704 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
3705
3706 /* Signal vertex emission */
3707 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3708 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3709 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3710 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
3711 }
3712
3713 /* Cut one primitive from the geometry shader */
3714 static void si_llvm_emit_primitive(
3715 const struct lp_build_tgsi_action *action,
3716 struct lp_build_tgsi_context *bld_base,
3717 struct lp_build_emit_data *emit_data)
3718 {
3719 struct si_shader_context *ctx = si_shader_context(bld_base);
3720 struct gallivm_state *gallivm = bld_base->base.gallivm;
3721 LLVMValueRef args[2];
3722 unsigned stream;
3723
3724 /* Signal primitive cut */
3725 stream = si_llvm_get_stream(bld_base, emit_data);
3726 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3727 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3728 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3729 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
3730 }
3731
3732 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3733 struct lp_build_tgsi_context *bld_base,
3734 struct lp_build_emit_data *emit_data)
3735 {
3736 struct si_shader_context *ctx = si_shader_context(bld_base);
3737 struct gallivm_state *gallivm = bld_base->base.gallivm;
3738
3739 lp_build_intrinsic(gallivm->builder,
3740 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3741 : "llvm.AMDGPU.barrier.local",
3742 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
3743 }
3744
3745 static const struct lp_build_tgsi_action tex_action = {
3746 .fetch_args = tex_fetch_args,
3747 .emit = build_tex_intrinsic,
3748 };
3749
3750 static const struct lp_build_tgsi_action interp_action = {
3751 .fetch_args = interp_fetch_args,
3752 .emit = build_interp_intrinsic,
3753 };
3754
3755 static void si_create_function(struct si_shader_context *ctx,
3756 LLVMTypeRef *returns, unsigned num_returns,
3757 LLVMTypeRef *params, unsigned num_params,
3758 int last_array_pointer, int last_sgpr)
3759 {
3760 int i;
3761
3762 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
3763 params, num_params);
3764 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
3765 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
3766
3767 for (i = 0; i <= last_sgpr; ++i) {
3768 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
3769
3770 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3771 * to move load. Inputs are constant so this is fine. */
3772 if (i <= last_array_pointer)
3773 LLVMAddAttribute(P, LLVMByValAttribute);
3774 else
3775 LLVMAddAttribute(P, LLVMInRegAttribute);
3776 }
3777 }
3778
3779 static void create_meta_data(struct si_shader_context *ctx)
3780 {
3781 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
3782 LLVMValueRef args[3];
3783
3784 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3785 args[1] = 0;
3786 args[2] = lp_build_const_int32(gallivm, 1);
3787
3788 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3789 }
3790
3791 static void declare_streamout_params(struct si_shader_context *ctx,
3792 struct pipe_stream_output_info *so,
3793 LLVMTypeRef *params, LLVMTypeRef i32,
3794 unsigned *num_params)
3795 {
3796 int i;
3797
3798 /* Streamout SGPRs. */
3799 if (so->num_outputs) {
3800 params[ctx->param_streamout_config = (*num_params)++] = i32;
3801 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
3802 }
3803 /* A streamout buffer offset is loaded if the stride is non-zero. */
3804 for (i = 0; i < 4; i++) {
3805 if (!so->stride[i])
3806 continue;
3807
3808 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3809 }
3810 }
3811
3812 static unsigned llvm_get_type_size(LLVMTypeRef type)
3813 {
3814 LLVMTypeKind kind = LLVMGetTypeKind(type);
3815
3816 switch (kind) {
3817 case LLVMIntegerTypeKind:
3818 return LLVMGetIntTypeWidth(type) / 8;
3819 case LLVMFloatTypeKind:
3820 return 4;
3821 case LLVMPointerTypeKind:
3822 return 8;
3823 case LLVMVectorTypeKind:
3824 return LLVMGetVectorSize(type) *
3825 llvm_get_type_size(LLVMGetElementType(type));
3826 default:
3827 assert(0);
3828 return 0;
3829 }
3830 }
3831
3832 static void declare_tess_lds(struct si_shader_context *ctx)
3833 {
3834 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3835 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
3836
3837 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3838 unsigned vertex_data_dw_size = 32*32*4;
3839 unsigned patch_data_dw_size = 32*4;
3840 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3841 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3842 unsigned lds_dwords = patch_dw_size;
3843
3844 /* The actual size is computed outside of the shader to reduce
3845 * the number of shader variants. */
3846 ctx->lds =
3847 LLVMAddGlobalInAddressSpace(gallivm->module,
3848 LLVMArrayType(i32, lds_dwords),
3849 "tess_lds",
3850 LOCAL_ADDR_SPACE);
3851 }
3852
3853 static void create_function(struct si_shader_context *ctx)
3854 {
3855 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3856 struct gallivm_state *gallivm = bld_base->base.gallivm;
3857 struct si_shader *shader = ctx->shader;
3858 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
3859 LLVMTypeRef returns[16+32*4];
3860 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
3861 unsigned num_returns = 0;
3862
3863 v3i32 = LLVMVectorType(ctx->i32, 3);
3864
3865 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
3866 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
3867 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
3868 params[SI_PARAM_UNUSED] = LLVMPointerType(ctx->i32, CONST_ADDR_SPACE);
3869 last_array_pointer = SI_PARAM_UNUSED;
3870
3871 switch (ctx->type) {
3872 case TGSI_PROCESSOR_VERTEX:
3873 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
3874 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3875 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
3876 params[SI_PARAM_START_INSTANCE] = ctx->i32;
3877 num_params = SI_PARAM_START_INSTANCE+1;
3878
3879 if (shader->key.vs.as_es) {
3880 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
3881 } else if (shader->key.vs.as_ls) {
3882 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
3883 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3884 } else {
3885 if (ctx->is_gs_copy_shader) {
3886 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3887 num_params = SI_PARAM_CONST_BUFFERS+1;
3888 } else {
3889 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
3890 num_params = SI_PARAM_VS_STATE_BITS+1;
3891 }
3892
3893 /* The locations of the other parameters are assigned dynamically. */
3894 declare_streamout_params(ctx, &shader->selector->so,
3895 params, ctx->i32, &num_params);
3896 }
3897
3898 last_sgpr = num_params-1;
3899
3900 /* VGPRs */
3901 params[ctx->param_vertex_id = num_params++] = ctx->i32;
3902 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
3903 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
3904 params[ctx->param_instance_id = num_params++] = ctx->i32;
3905
3906 if (!ctx->is_monolithic &&
3907 !ctx->is_gs_copy_shader) {
3908 /* Vertex load indices. */
3909 ctx->param_vertex_index0 = num_params;
3910
3911 for (i = 0; i < shader->selector->info.num_inputs; i++)
3912 params[num_params++] = ctx->i32;
3913
3914 /* PrimitiveID output. */
3915 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
3916 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
3917 returns[num_returns++] = ctx->f32;
3918 }
3919 break;
3920
3921 case TGSI_PROCESSOR_TESS_CTRL:
3922 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
3923 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
3924 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
3925 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
3926 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3927
3928 /* VGPRs */
3929 params[SI_PARAM_PATCH_ID] = ctx->i32;
3930 params[SI_PARAM_REL_IDS] = ctx->i32;
3931 num_params = SI_PARAM_REL_IDS+1;
3932
3933 if (!ctx->is_monolithic) {
3934 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
3935 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
3936 returns[num_returns++] = ctx->i32; /* SGPRs */
3937
3938 for (i = 0; i < 3; i++)
3939 returns[num_returns++] = ctx->f32; /* VGPRs */
3940 }
3941 break;
3942
3943 case TGSI_PROCESSOR_TESS_EVAL:
3944 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
3945 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
3946 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3947
3948 if (shader->key.tes.as_es) {
3949 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
3950 } else {
3951 declare_streamout_params(ctx, &shader->selector->so,
3952 params, ctx->i32, &num_params);
3953 }
3954 last_sgpr = num_params - 1;
3955
3956 /* VGPRs */
3957 params[ctx->param_tes_u = num_params++] = ctx->f32;
3958 params[ctx->param_tes_v = num_params++] = ctx->f32;
3959 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
3960 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
3961
3962 /* PrimitiveID output. */
3963 if (!ctx->is_monolithic && !shader->key.tes.as_es)
3964 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
3965 returns[num_returns++] = ctx->f32;
3966 break;
3967
3968 case TGSI_PROCESSOR_GEOMETRY:
3969 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
3970 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
3971 last_sgpr = SI_PARAM_GS_WAVE_ID;
3972
3973 /* VGPRs */
3974 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
3975 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
3976 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
3977 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
3978 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
3979 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
3980 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
3981 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
3982 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3983 break;
3984
3985 case TGSI_PROCESSOR_FRAGMENT:
3986 params[SI_PARAM_ALPHA_REF] = ctx->f32;
3987 params[SI_PARAM_PRIM_MASK] = ctx->i32;
3988 last_sgpr = SI_PARAM_PRIM_MASK;
3989 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
3990 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
3991 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
3992 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3993 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
3994 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
3995 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
3996 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
3997 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
3998 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
3999 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
4000 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
4001 params[SI_PARAM_FRONT_FACE] = ctx->i32;
4002 params[SI_PARAM_ANCILLARY] = ctx->i32;
4003 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
4004 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
4005 num_params = SI_PARAM_POS_FIXED_PT+1;
4006
4007 if (!ctx->is_monolithic) {
4008 /* Color inputs from the prolog. */
4009 if (shader->selector->info.colors_read) {
4010 unsigned num_color_elements =
4011 util_bitcount(shader->selector->info.colors_read);
4012
4013 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
4014 for (i = 0; i < num_color_elements; i++)
4015 params[num_params++] = ctx->f32;
4016 }
4017
4018 /* Outputs for the epilog. */
4019 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4020 num_returns =
4021 num_return_sgprs +
4022 util_bitcount(shader->selector->info.colors_written) * 4 +
4023 shader->selector->info.writes_z +
4024 shader->selector->info.writes_stencil +
4025 shader->selector->info.writes_samplemask +
4026 1 /* SampleMaskIn */;
4027
4028 num_returns = MAX2(num_returns,
4029 num_return_sgprs +
4030 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4031
4032 for (i = 0; i < num_return_sgprs; i++)
4033 returns[i] = ctx->i32;
4034 for (; i < num_returns; i++)
4035 returns[i] = ctx->f32;
4036 }
4037 break;
4038
4039 default:
4040 assert(0 && "unimplemented shader");
4041 return;
4042 }
4043
4044 assert(num_params <= Elements(params));
4045
4046 si_create_function(ctx, returns, num_returns, params,
4047 num_params, last_array_pointer, last_sgpr);
4048
4049 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4050 if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
4051 !ctx->is_monolithic) {
4052 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
4053 "InitialPSInputAddr",
4054 S_0286D0_PERSP_SAMPLE_ENA(1) |
4055 S_0286D0_PERSP_CENTER_ENA(1) |
4056 S_0286D0_PERSP_CENTROID_ENA(1) |
4057 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4058 S_0286D0_LINEAR_CENTER_ENA(1) |
4059 S_0286D0_LINEAR_CENTROID_ENA(1) |
4060 S_0286D0_FRONT_FACE_ENA(1) |
4061 S_0286D0_POS_FIXED_PT_ENA(1));
4062 }
4063
4064 shader->info.num_input_sgprs = 0;
4065 shader->info.num_input_vgprs = 0;
4066
4067 for (i = 0; i <= last_sgpr; ++i)
4068 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
4069
4070 /* Unused fragment shader inputs are eliminated by the compiler,
4071 * so we don't know yet how many there will be.
4072 */
4073 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
4074 for (; i < num_params; ++i)
4075 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
4076
4077 if (bld_base->info &&
4078 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4079 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4080 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4081 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4082 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4083 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4084 ctx->lds =
4085 LLVMAddGlobalInAddressSpace(gallivm->module,
4086 LLVMArrayType(ctx->i32, 64),
4087 "ddxy_lds",
4088 LOCAL_ADDR_SPACE);
4089
4090 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
4091 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
4092 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
4093 declare_tess_lds(ctx);
4094 }
4095
4096 static void preload_constants(struct si_shader_context *ctx)
4097 {
4098 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4099 struct gallivm_state *gallivm = bld_base->base.gallivm;
4100 const struct tgsi_shader_info *info = bld_base->info;
4101 unsigned buf;
4102 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
4103
4104 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
4105 unsigned i, num_const = info->const_file_max[buf] + 1;
4106
4107 if (num_const == 0)
4108 continue;
4109
4110 /* Allocate space for the constant values */
4111 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
4112
4113 /* Load the resource descriptor */
4114 ctx->const_buffers[buf] =
4115 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
4116
4117 /* Load the constants, we rely on the code sinking to do the rest */
4118 for (i = 0; i < num_const * 4; ++i) {
4119 ctx->constants[buf][i] =
4120 buffer_load_const(gallivm->builder,
4121 ctx->const_buffers[buf],
4122 lp_build_const_int32(gallivm, i * 4),
4123 ctx->f32);
4124 }
4125 }
4126 }
4127
4128 static void preload_samplers(struct si_shader_context *ctx)
4129 {
4130 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4131 struct gallivm_state *gallivm = bld_base->base.gallivm;
4132 const struct tgsi_shader_info *info = bld_base->info;
4133 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
4134 LLVMValueRef offset;
4135
4136 if (num_samplers == 0)
4137 return;
4138
4139 /* Load the resources and samplers, we rely on the code sinking to do the rest */
4140 for (i = 0; i < num_samplers; ++i) {
4141 /* Resource */
4142 offset = lp_build_const_int32(gallivm, i);
4143 ctx->sampler_views[i] =
4144 get_sampler_desc(ctx, offset, DESC_IMAGE);
4145
4146 /* FMASK resource */
4147 if (info->is_msaa_sampler[i])
4148 ctx->fmasks[i] =
4149 get_sampler_desc(ctx, offset, DESC_FMASK);
4150 else
4151 ctx->sampler_states[i] =
4152 get_sampler_desc(ctx, offset, DESC_SAMPLER);
4153 }
4154 }
4155
4156 static void preload_streamout_buffers(struct si_shader_context *ctx)
4157 {
4158 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4159 struct gallivm_state *gallivm = bld_base->base.gallivm;
4160 unsigned i;
4161
4162 /* Streamout can only be used if the shader is compiled as VS. */
4163 if (!ctx->shader->selector->so.num_outputs ||
4164 (ctx->type == TGSI_PROCESSOR_VERTEX &&
4165 (ctx->shader->key.vs.as_es ||
4166 ctx->shader->key.vs.as_ls)) ||
4167 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4168 ctx->shader->key.tes.as_es))
4169 return;
4170
4171 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4172 SI_PARAM_RW_BUFFERS);
4173
4174 /* Load the resources, we rely on the code sinking to do the rest */
4175 for (i = 0; i < 4; ++i) {
4176 if (ctx->shader->selector->so.stride[i]) {
4177 LLVMValueRef offset = lp_build_const_int32(gallivm,
4178 SI_SO_BUF_OFFSET + i);
4179
4180 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
4181 }
4182 }
4183 }
4184
4185 /**
4186 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4187 * for later use.
4188 */
4189 static void preload_ring_buffers(struct si_shader_context *ctx)
4190 {
4191 struct gallivm_state *gallivm =
4192 ctx->radeon_bld.soa.bld_base.base.gallivm;
4193
4194 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4195 SI_PARAM_RW_BUFFERS);
4196
4197 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
4198 ctx->shader->key.vs.as_es) ||
4199 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4200 ctx->shader->key.tes.as_es) ||
4201 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4202 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
4203
4204 ctx->esgs_ring =
4205 build_indexed_load_const(ctx, buf_ptr, offset);
4206 }
4207
4208 if (ctx->is_gs_copy_shader) {
4209 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
4210
4211 ctx->gsvs_ring[0] =
4212 build_indexed_load_const(ctx, buf_ptr, offset);
4213 }
4214 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4215 int i;
4216 for (i = 0; i < 4; i++) {
4217 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
4218
4219 ctx->gsvs_ring[i] =
4220 build_indexed_load_const(ctx, buf_ptr, offset);
4221 }
4222 }
4223 }
4224
4225 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4226 LLVMValueRef param_sampler_views,
4227 unsigned param_pos_fixed_pt)
4228 {
4229 struct lp_build_tgsi_context *bld_base =
4230 &ctx->radeon_bld.soa.bld_base;
4231 struct gallivm_state *gallivm = bld_base->base.gallivm;
4232 struct lp_build_emit_data result = {};
4233 struct tgsi_full_instruction inst = {};
4234 LLVMValueRef desc, sampler_index, address[2], pix;
4235
4236 /* Use the fixed-point gl_FragCoord input.
4237 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4238 * per coordinate to get the repeating effect.
4239 */
4240 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4241 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4242
4243 /* Load the sampler view descriptor. */
4244 sampler_index = lp_build_const_int32(gallivm, SI_POLY_STIPPLE_SAMPLER);
4245 desc = get_sampler_desc_custom(ctx, param_sampler_views,
4246 sampler_index, DESC_IMAGE);
4247
4248 /* Load the texel. */
4249 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4250 inst.Texture.Texture = TGSI_TEXTURE_2D_MSAA; /* = use load, not load_mip */
4251 result.inst = &inst;
4252 set_tex_fetch_args(ctx, &result, TGSI_OPCODE_TXF,
4253 inst.Texture.Texture,
4254 desc, NULL, address, ARRAY_SIZE(address), 0xf);
4255 build_tex_intrinsic(&tex_action, bld_base, &result);
4256
4257 /* Kill the thread accordingly. */
4258 pix = LLVMBuildExtractElement(gallivm->builder, result.output[0],
4259 lp_build_const_int32(gallivm, 3), "");
4260 pix = bitcast(bld_base, TGSI_TYPE_FLOAT, pix);
4261 pix = LLVMBuildFNeg(gallivm->builder, pix, "");
4262
4263 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4264 LLVMVoidTypeInContext(gallivm->context),
4265 &pix, 1, 0);
4266 }
4267
4268 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
4269 struct si_shader_config *conf,
4270 unsigned symbol_offset)
4271 {
4272 unsigned i;
4273 const unsigned char *config =
4274 radeon_shader_binary_config_start(binary, symbol_offset);
4275
4276 /* XXX: We may be able to emit some of these values directly rather than
4277 * extracting fields to be emitted later.
4278 */
4279
4280 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4281 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4282 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4283 switch (reg) {
4284 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4285 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4286 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4287 case R_00B848_COMPUTE_PGM_RSRC1:
4288 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4289 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4290 conf->float_mode = G_00B028_FLOAT_MODE(value);
4291 conf->rsrc1 = value;
4292 break;
4293 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4294 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4295 break;
4296 case R_00B84C_COMPUTE_PGM_RSRC2:
4297 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4298 conf->rsrc2 = value;
4299 break;
4300 case R_0286CC_SPI_PS_INPUT_ENA:
4301 conf->spi_ps_input_ena = value;
4302 break;
4303 case R_0286D0_SPI_PS_INPUT_ADDR:
4304 conf->spi_ps_input_addr = value;
4305 break;
4306 case R_0286E8_SPI_TMPRING_SIZE:
4307 case R_00B860_COMPUTE_TMPRING_SIZE:
4308 /* WAVESIZE is in units of 256 dwords. */
4309 conf->scratch_bytes_per_wave =
4310 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
4311 break;
4312 default:
4313 {
4314 static bool printed;
4315
4316 if (!printed) {
4317 fprintf(stderr, "Warning: LLVM emitted unknown "
4318 "config register: 0x%x\n", reg);
4319 printed = true;
4320 }
4321 }
4322 break;
4323 }
4324
4325 if (!conf->spi_ps_input_addr)
4326 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4327 }
4328 }
4329
4330 void si_shader_apply_scratch_relocs(struct si_context *sctx,
4331 struct si_shader *shader,
4332 uint64_t scratch_va)
4333 {
4334 unsigned i;
4335 uint32_t scratch_rsrc_dword0 = scratch_va;
4336 uint32_t scratch_rsrc_dword1 =
4337 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
4338 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
4339
4340 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4341 const struct radeon_shader_reloc *reloc =
4342 &shader->binary.relocs[i];
4343 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4344 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4345 &scratch_rsrc_dword0, 4);
4346 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4347 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4348 &scratch_rsrc_dword1, 4);
4349 }
4350 }
4351 }
4352
4353 static unsigned si_get_shader_binary_size(struct si_shader *shader)
4354 {
4355 unsigned size = shader->binary.code_size;
4356
4357 if (shader->prolog)
4358 size += shader->prolog->binary.code_size;
4359 if (shader->epilog)
4360 size += shader->epilog->binary.code_size;
4361 return size;
4362 }
4363
4364 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4365 {
4366 const struct radeon_shader_binary *prolog =
4367 shader->prolog ? &shader->prolog->binary : NULL;
4368 const struct radeon_shader_binary *epilog =
4369 shader->epilog ? &shader->epilog->binary : NULL;
4370 const struct radeon_shader_binary *mainb = &shader->binary;
4371 unsigned bo_size = si_get_shader_binary_size(shader) +
4372 (!epilog ? mainb->rodata_size : 0);
4373 unsigned char *ptr;
4374
4375 assert(!prolog || !prolog->rodata_size);
4376 assert((!prolog && !epilog) || !mainb->rodata_size);
4377 assert(!epilog || !epilog->rodata_size);
4378
4379 r600_resource_reference(&shader->bo, NULL);
4380 shader->bo = si_resource_create_custom(&sscreen->b.b,
4381 PIPE_USAGE_IMMUTABLE,
4382 bo_size);
4383 if (!shader->bo)
4384 return -ENOMEM;
4385
4386 /* Upload. */
4387 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4388 PIPE_TRANSFER_READ_WRITE);
4389
4390 if (prolog) {
4391 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
4392 ptr += prolog->code_size;
4393 }
4394
4395 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
4396 ptr += mainb->code_size;
4397
4398 if (epilog)
4399 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
4400 else if (mainb->rodata_size > 0)
4401 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
4402
4403 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4404 return 0;
4405 }
4406
4407 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
4408 struct pipe_debug_callback *debug,
4409 const char *name, FILE *file)
4410 {
4411 char *line, *p;
4412 unsigned i, count;
4413
4414 if (binary->disasm_string) {
4415 fprintf(file, "Shader %s disassembly:\n", name);
4416 fprintf(file, "%s", binary->disasm_string);
4417
4418 if (debug && debug->debug_message) {
4419 /* Very long debug messages are cut off, so send the
4420 * disassembly one line at a time. This causes more
4421 * overhead, but on the plus side it simplifies
4422 * parsing of resulting logs.
4423 */
4424 pipe_debug_message(debug, SHADER_INFO,
4425 "Shader Disassembly Begin");
4426
4427 line = binary->disasm_string;
4428 while (*line) {
4429 p = strchrnul(line, '\n');
4430 count = p - line;
4431
4432 if (count) {
4433 pipe_debug_message(debug, SHADER_INFO,
4434 "%.*s", count, line);
4435 }
4436
4437 if (!*p)
4438 break;
4439 line = p + 1;
4440 }
4441
4442 pipe_debug_message(debug, SHADER_INFO,
4443 "Shader Disassembly End");
4444 }
4445 } else {
4446 fprintf(file, "Shader %s binary:\n", name);
4447 for (i = 0; i < binary->code_size; i += 4) {
4448 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4449 binary->code[i + 3], binary->code[i + 2],
4450 binary->code[i + 1], binary->code[i]);
4451 }
4452 }
4453 }
4454
4455 static void si_shader_dump_stats(struct si_screen *sscreen,
4456 struct si_shader_config *conf,
4457 unsigned num_inputs,
4458 unsigned code_size,
4459 struct pipe_debug_callback *debug,
4460 unsigned processor,
4461 FILE *file)
4462 {
4463 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4464 unsigned lds_per_wave = 0;
4465 unsigned max_simd_waves = 10;
4466
4467 /* Compute LDS usage for PS. */
4468 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4469 /* The minimum usage per wave is (num_inputs * 36). The maximum
4470 * usage is (num_inputs * 36 * 16).
4471 * We can get anything in between and it varies between waves.
4472 *
4473 * Other stages don't know the size at compile time or don't
4474 * allocate LDS per wave, but instead they do it per thread group.
4475 */
4476 lds_per_wave = conf->lds_size * lds_increment +
4477 align(num_inputs * 36, lds_increment);
4478 }
4479
4480 /* Compute the per-SIMD wave counts. */
4481 if (conf->num_sgprs) {
4482 if (sscreen->b.chip_class >= VI)
4483 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4484 else
4485 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4486 }
4487
4488 if (conf->num_vgprs)
4489 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4490
4491 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4492 * that PS can use.
4493 */
4494 if (lds_per_wave)
4495 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4496
4497 if (file != stderr ||
4498 r600_can_dump_shader(&sscreen->b, processor)) {
4499 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4500 fprintf(file, "*** SHADER CONFIG ***\n"
4501 "SPI_PS_INPUT_ADDR = 0x%04x\n"
4502 "SPI_PS_INPUT_ENA = 0x%04x\n",
4503 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
4504 }
4505
4506 fprintf(file, "*** SHADER STATS ***\n"
4507 "SGPRS: %d\n"
4508 "VGPRS: %d\n"
4509 "Code Size: %d bytes\n"
4510 "LDS: %d blocks\n"
4511 "Scratch: %d bytes per wave\n"
4512 "Max Waves: %d\n"
4513 "********************\n",
4514 conf->num_sgprs, conf->num_vgprs, code_size,
4515 conf->lds_size, conf->scratch_bytes_per_wave,
4516 max_simd_waves);
4517 }
4518
4519 pipe_debug_message(debug, SHADER_INFO,
4520 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4521 "LDS: %d Scratch: %d Max Waves: %d",
4522 conf->num_sgprs, conf->num_vgprs, code_size,
4523 conf->lds_size, conf->scratch_bytes_per_wave,
4524 max_simd_waves);
4525 }
4526
4527 static const char *si_get_shader_name(struct si_shader *shader,
4528 unsigned processor)
4529 {
4530 switch (processor) {
4531 case TGSI_PROCESSOR_VERTEX:
4532 if (shader->key.vs.as_es)
4533 return "Vertex Shader as ES";
4534 else if (shader->key.vs.as_ls)
4535 return "Vertex Shader as LS";
4536 else
4537 return "Vertex Shader as VS";
4538 case TGSI_PROCESSOR_TESS_CTRL:
4539 return "Tessellation Control Shader";
4540 case TGSI_PROCESSOR_TESS_EVAL:
4541 if (shader->key.tes.as_es)
4542 return "Tessellation Evaluation Shader as ES";
4543 else
4544 return "Tessellation Evaluation Shader as VS";
4545 case TGSI_PROCESSOR_GEOMETRY:
4546 if (shader->gs_copy_shader == NULL)
4547 return "GS Copy Shader as VS";
4548 else
4549 return "Geometry Shader";
4550 case TGSI_PROCESSOR_FRAGMENT:
4551 return "Pixel Shader";
4552 case TGSI_PROCESSOR_COMPUTE:
4553 return "Compute Shader";
4554 default:
4555 return "Unknown Shader";
4556 }
4557 }
4558
4559 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4560 struct pipe_debug_callback *debug, unsigned processor,
4561 FILE *file)
4562 {
4563 if (file != stderr ||
4564 (r600_can_dump_shader(&sscreen->b, processor) &&
4565 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
4566 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
4567
4568 if (shader->prolog)
4569 si_shader_dump_disassembly(&shader->prolog->binary,
4570 debug, "prolog", file);
4571
4572 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
4573
4574 if (shader->epilog)
4575 si_shader_dump_disassembly(&shader->epilog->binary,
4576 debug, "epilog", file);
4577 fprintf(file, "\n");
4578 }
4579
4580 si_shader_dump_stats(sscreen, &shader->config,
4581 shader->selector ? shader->selector->info.num_inputs : 0,
4582 si_get_shader_binary_size(shader), debug, processor,
4583 file);
4584 }
4585
4586 int si_compile_llvm(struct si_screen *sscreen,
4587 struct radeon_shader_binary *binary,
4588 struct si_shader_config *conf,
4589 LLVMTargetMachineRef tm,
4590 LLVMModuleRef mod,
4591 struct pipe_debug_callback *debug,
4592 unsigned processor,
4593 const char *name)
4594 {
4595 int r = 0;
4596 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4597
4598 if (r600_can_dump_shader(&sscreen->b, processor)) {
4599 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4600
4601 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
4602 fprintf(stderr, "%s LLVM IR:\n\n", name);
4603 LLVMDumpModule(mod);
4604 fprintf(stderr, "\n");
4605 }
4606 }
4607
4608 if (!si_replace_shader(count, binary)) {
4609 r = radeon_llvm_compile(mod, binary,
4610 r600_get_llvm_processor_name(sscreen->b.family), tm,
4611 debug);
4612 if (r)
4613 return r;
4614 }
4615
4616 si_shader_binary_read_config(binary, conf, 0);
4617
4618 /* Enable 64-bit and 16-bit denormals, because there is no performance
4619 * cost.
4620 *
4621 * If denormals are enabled, all floating-point output modifiers are
4622 * ignored.
4623 *
4624 * Don't enable denormals for 32-bit floats, because:
4625 * - Floating-point output modifiers would be ignored by the hw.
4626 * - Some opcodes don't support denormals, such as v_mad_f32. We would
4627 * have to stop using those.
4628 * - SI & CI would be very slow.
4629 */
4630 conf->float_mode |= V_00B028_FP_64_DENORMS;
4631
4632 FREE(binary->config);
4633 FREE(binary->global_symbol_offsets);
4634 binary->config = NULL;
4635 binary->global_symbol_offsets = NULL;
4636
4637 /* Some shaders can't have rodata because their binaries can be
4638 * concatenated.
4639 */
4640 if (binary->rodata_size &&
4641 (processor == TGSI_PROCESSOR_VERTEX ||
4642 processor == TGSI_PROCESSOR_TESS_CTRL ||
4643 processor == TGSI_PROCESSOR_TESS_EVAL ||
4644 processor == TGSI_PROCESSOR_FRAGMENT)) {
4645 fprintf(stderr, "radeonsi: The shader can't have rodata.");
4646 return -EINVAL;
4647 }
4648
4649 return r;
4650 }
4651
4652 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4653 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4654 struct si_shader_context *ctx,
4655 struct si_shader *gs,
4656 struct pipe_debug_callback *debug)
4657 {
4658 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4659 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4660 struct lp_build_context *uint = &bld_base->uint_bld;
4661 struct si_shader_output_values *outputs;
4662 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4663 LLVMValueRef args[9];
4664 int i, r;
4665
4666 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4667
4668 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
4669 ctx->type = TGSI_PROCESSOR_VERTEX;
4670 ctx->is_gs_copy_shader = true;
4671
4672 create_meta_data(ctx);
4673 create_function(ctx);
4674 preload_streamout_buffers(ctx);
4675 preload_ring_buffers(ctx);
4676
4677 args[0] = ctx->gsvs_ring[0];
4678 args[1] = lp_build_mul_imm(uint,
4679 LLVMGetParam(ctx->radeon_bld.main_fn,
4680 ctx->param_vertex_id),
4681 4);
4682 args[3] = uint->zero;
4683 args[4] = uint->one; /* OFFEN */
4684 args[5] = uint->zero; /* IDXEN */
4685 args[6] = uint->one; /* GLC */
4686 args[7] = uint->one; /* SLC */
4687 args[8] = uint->zero; /* TFE */
4688
4689 /* Fetch vertex data from GSVS ring */
4690 for (i = 0; i < gsinfo->num_outputs; ++i) {
4691 unsigned chan;
4692
4693 outputs[i].name = gsinfo->output_semantic_name[i];
4694 outputs[i].sid = gsinfo->output_semantic_index[i];
4695
4696 for (chan = 0; chan < 4; chan++) {
4697 args[2] = lp_build_const_int32(gallivm,
4698 (i * 4 + chan) *
4699 gs->selector->gs_max_out_vertices * 16 * 4);
4700
4701 outputs[i].values[chan] =
4702 LLVMBuildBitCast(gallivm->builder,
4703 lp_build_intrinsic(gallivm->builder,
4704 "llvm.SI.buffer.load.dword.i32.i32",
4705 ctx->i32, args, 9,
4706 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4707 ctx->f32, "");
4708 }
4709 }
4710
4711 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4712
4713 LLVMBuildRet(gallivm->builder, ctx->return_value);
4714
4715 /* Dump LLVM IR before any optimization passes */
4716 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4717 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4718 LLVMDumpModule(bld_base->base.gallivm->module);
4719
4720 radeon_llvm_finalize_module(&ctx->radeon_bld);
4721
4722 r = si_compile_llvm(sscreen, &ctx->shader->binary,
4723 &ctx->shader->config, ctx->tm,
4724 bld_base->base.gallivm->module,
4725 debug, TGSI_PROCESSOR_GEOMETRY,
4726 "GS Copy Shader");
4727 if (!r) {
4728 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4729 fprintf(stderr, "GS Copy Shader:\n");
4730 si_shader_dump(sscreen, ctx->shader, debug,
4731 TGSI_PROCESSOR_GEOMETRY, stderr);
4732 r = si_shader_binary_upload(sscreen, ctx->shader);
4733 }
4734
4735 radeon_llvm_dispose(&ctx->radeon_bld);
4736
4737 FREE(outputs);
4738 return r;
4739 }
4740
4741 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4742 {
4743 int i;
4744
4745 fprintf(f, "SHADER KEY\n");
4746
4747 switch (shader) {
4748 case PIPE_SHADER_VERTEX:
4749 fprintf(f, " instance_divisors = {");
4750 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
4751 fprintf(f, !i ? "%u" : ", %u",
4752 key->vs.prolog.instance_divisors[i]);
4753 fprintf(f, "}\n");
4754 fprintf(f, " as_es = %u\n", key->vs.as_es);
4755 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4756 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
4757 break;
4758
4759 case PIPE_SHADER_TESS_CTRL:
4760 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
4761 break;
4762
4763 case PIPE_SHADER_TESS_EVAL:
4764 fprintf(f, " as_es = %u\n", key->tes.as_es);
4765 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
4766 break;
4767
4768 case PIPE_SHADER_GEOMETRY:
4769 break;
4770
4771 case PIPE_SHADER_FRAGMENT:
4772 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
4773 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
4774 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
4775 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
4776 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
4777 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
4778 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
4779 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
4780 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
4781 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
4782 break;
4783
4784 default:
4785 assert(0);
4786 }
4787 }
4788
4789 static void si_init_shader_ctx(struct si_shader_context *ctx,
4790 struct si_screen *sscreen,
4791 struct si_shader *shader,
4792 LLVMTargetMachineRef tm)
4793 {
4794 struct lp_build_tgsi_context *bld_base;
4795
4796 memset(ctx, 0, sizeof(*ctx));
4797 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
4798 ctx->tm = tm;
4799 ctx->screen = sscreen;
4800 if (shader && shader->selector)
4801 ctx->type = shader->selector->info.processor;
4802 else
4803 ctx->type = -1;
4804 ctx->shader = shader;
4805
4806 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
4807 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
4808 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
4809 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
4810 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
4811 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
4812 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
4813 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
4814 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
4815 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
4816 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
4817 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
4818
4819 bld_base = &ctx->radeon_bld.soa.bld_base;
4820 if (shader && shader->selector)
4821 bld_base->info = &shader->selector->info;
4822 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4823
4824 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4825 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4826 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4827
4828 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4829 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4830 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4831 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4832 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4833 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4834 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4835 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4836 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4837 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4838 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4839 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4840 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4841
4842 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4843 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4844 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4845 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4846
4847 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4848 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4849 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4850
4851 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4852 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4853 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4854 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4855 }
4856
4857 int si_compile_tgsi_shader(struct si_screen *sscreen,
4858 LLVMTargetMachineRef tm,
4859 struct si_shader *shader,
4860 bool is_monolithic,
4861 struct pipe_debug_callback *debug)
4862 {
4863 struct si_shader_selector *sel = shader->selector;
4864 struct si_shader_context ctx;
4865 struct lp_build_tgsi_context *bld_base;
4866 LLVMModuleRef mod;
4867 int r = 0;
4868
4869 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4870 * conversion fails. */
4871 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
4872 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4873 si_dump_shader_key(sel->type, &shader->key, stderr);
4874 tgsi_dump(sel->tokens, 0);
4875 si_dump_streamout(&sel->so);
4876 }
4877
4878 si_init_shader_ctx(&ctx, sscreen, shader, tm);
4879 ctx.is_monolithic = is_monolithic;
4880
4881 shader->info.uses_instanceid = sel->info.uses_instanceid;
4882
4883 bld_base = &ctx.radeon_bld.soa.bld_base;
4884 ctx.radeon_bld.load_system_value = declare_system_value;
4885
4886 switch (ctx.type) {
4887 case TGSI_PROCESSOR_VERTEX:
4888 ctx.radeon_bld.load_input = declare_input_vs;
4889 if (shader->key.vs.as_ls)
4890 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4891 else if (shader->key.vs.as_es)
4892 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4893 else
4894 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4895 break;
4896 case TGSI_PROCESSOR_TESS_CTRL:
4897 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4898 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4899 bld_base->emit_store = store_output_tcs;
4900 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4901 break;
4902 case TGSI_PROCESSOR_TESS_EVAL:
4903 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4904 if (shader->key.tes.as_es)
4905 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4906 else
4907 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4908 break;
4909 case TGSI_PROCESSOR_GEOMETRY:
4910 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4911 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4912 break;
4913 case TGSI_PROCESSOR_FRAGMENT:
4914 ctx.radeon_bld.load_input = declare_input_fs;
4915 if (is_monolithic)
4916 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4917 else
4918 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
4919 break;
4920 default:
4921 assert(!"Unsupported shader type");
4922 return -1;
4923 }
4924
4925 create_meta_data(&ctx);
4926 create_function(&ctx);
4927 preload_constants(&ctx);
4928 preload_samplers(&ctx);
4929 preload_streamout_buffers(&ctx);
4930 preload_ring_buffers(&ctx);
4931
4932 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
4933 shader->key.ps.prolog.poly_stipple) {
4934 LLVMValueRef views = LLVMGetParam(ctx.radeon_bld.main_fn,
4935 SI_PARAM_SAMPLERS);
4936 si_llvm_emit_polygon_stipple(&ctx, views,
4937 SI_PARAM_POS_FIXED_PT);
4938 }
4939
4940 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4941 int i;
4942 for (i = 0; i < 4; i++) {
4943 ctx.gs_next_vertex[i] =
4944 lp_build_alloca(bld_base->base.gallivm,
4945 ctx.i32, "");
4946 }
4947 }
4948
4949 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
4950 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4951 goto out;
4952 }
4953
4954 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
4955 mod = bld_base->base.gallivm->module;
4956
4957 /* Dump LLVM IR before any optimization passes */
4958 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4959 r600_can_dump_shader(&sscreen->b, ctx.type))
4960 LLVMDumpModule(mod);
4961
4962 radeon_llvm_finalize_module(&ctx.radeon_bld);
4963
4964 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4965 mod, debug, ctx.type, "TGSI shader");
4966 if (r) {
4967 fprintf(stderr, "LLVM failed to compile shader\n");
4968 goto out;
4969 }
4970
4971 radeon_llvm_dispose(&ctx.radeon_bld);
4972
4973 /* Calculate the number of fragment input VGPRs. */
4974 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
4975 shader->info.num_input_vgprs = 0;
4976 shader->info.face_vgpr_index = -1;
4977
4978 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
4979 shader->info.num_input_vgprs += 2;
4980 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
4981 shader->info.num_input_vgprs += 2;
4982 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
4983 shader->info.num_input_vgprs += 2;
4984 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
4985 shader->info.num_input_vgprs += 3;
4986 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
4987 shader->info.num_input_vgprs += 2;
4988 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
4989 shader->info.num_input_vgprs += 2;
4990 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
4991 shader->info.num_input_vgprs += 2;
4992 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
4993 shader->info.num_input_vgprs += 1;
4994 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
4995 shader->info.num_input_vgprs += 1;
4996 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
4997 shader->info.num_input_vgprs += 1;
4998 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
4999 shader->info.num_input_vgprs += 1;
5000 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
5001 shader->info.num_input_vgprs += 1;
5002 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
5003 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
5004 shader->info.num_input_vgprs += 1;
5005 }
5006 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
5007 shader->info.num_input_vgprs += 1;
5008 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
5009 shader->info.num_input_vgprs += 1;
5010 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
5011 shader->info.num_input_vgprs += 1;
5012 }
5013
5014 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5015 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
5016 shader->gs_copy_shader->selector = shader->selector;
5017 ctx.shader = shader->gs_copy_shader;
5018 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
5019 shader, debug))) {
5020 free(shader->gs_copy_shader);
5021 shader->gs_copy_shader = NULL;
5022 goto out;
5023 }
5024 }
5025
5026 out:
5027 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
5028 FREE(ctx.constants[i]);
5029 return r;
5030 }
5031
5032 /**
5033 * Create, compile and return a shader part (prolog or epilog).
5034 *
5035 * \param sscreen screen
5036 * \param list list of shader parts of the same category
5037 * \param key shader part key
5038 * \param tm LLVM target machine
5039 * \param debug debug callback
5040 * \param compile the callback responsible for compilation
5041 * \return non-NULL on success
5042 */
5043 static struct si_shader_part *
5044 si_get_shader_part(struct si_screen *sscreen,
5045 struct si_shader_part **list,
5046 union si_shader_part_key *key,
5047 LLVMTargetMachineRef tm,
5048 struct pipe_debug_callback *debug,
5049 bool (*compile)(struct si_screen *,
5050 LLVMTargetMachineRef,
5051 struct pipe_debug_callback *,
5052 struct si_shader_part *))
5053 {
5054 struct si_shader_part *result;
5055
5056 pipe_mutex_lock(sscreen->shader_parts_mutex);
5057
5058 /* Find existing. */
5059 for (result = *list; result; result = result->next) {
5060 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
5061 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5062 return result;
5063 }
5064 }
5065
5066 /* Compile a new one. */
5067 result = CALLOC_STRUCT(si_shader_part);
5068 result->key = *key;
5069 if (!compile(sscreen, tm, debug, result)) {
5070 FREE(result);
5071 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5072 return NULL;
5073 }
5074
5075 result->next = *list;
5076 *list = result;
5077 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5078 return result;
5079 }
5080
5081 /**
5082 * Create a vertex shader prolog.
5083 *
5084 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
5085 * All inputs are returned unmodified. The vertex load indices are
5086 * stored after them, which will used by the API VS for fetching inputs.
5087 *
5088 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
5089 * input_v0,
5090 * input_v1,
5091 * input_v2,
5092 * input_v3,
5093 * (VertexID + BaseVertex),
5094 * (InstanceID + StartInstance),
5095 * (InstanceID / 2 + StartInstance)
5096 */
5097 static bool si_compile_vs_prolog(struct si_screen *sscreen,
5098 LLVMTargetMachineRef tm,
5099 struct pipe_debug_callback *debug,
5100 struct si_shader_part *out)
5101 {
5102 union si_shader_part_key *key = &out->key;
5103 struct si_shader shader = {};
5104 struct si_shader_context ctx;
5105 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5106 LLVMTypeRef *params, *returns;
5107 LLVMValueRef ret, func;
5108 int last_sgpr, num_params, num_returns, i;
5109 bool status = true;
5110
5111 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5112 ctx.type = TGSI_PROCESSOR_VERTEX;
5113 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
5114 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
5115
5116 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
5117 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
5118 sizeof(LLVMTypeRef));
5119 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
5120 key->vs_prolog.last_input + 1) *
5121 sizeof(LLVMTypeRef));
5122 num_params = 0;
5123 num_returns = 0;
5124
5125 /* Declare input and output SGPRs. */
5126 num_params = 0;
5127 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5128 params[num_params++] = ctx.i32;
5129 returns[num_returns++] = ctx.i32;
5130 }
5131 last_sgpr = num_params - 1;
5132
5133 /* 4 preloaded VGPRs (outputs must be floats) */
5134 for (i = 0; i < 4; i++) {
5135 params[num_params++] = ctx.i32;
5136 returns[num_returns++] = ctx.f32;
5137 }
5138
5139 /* Vertex load indices. */
5140 for (i = 0; i <= key->vs_prolog.last_input; i++)
5141 returns[num_returns++] = ctx.f32;
5142
5143 /* Create the function. */
5144 si_create_function(&ctx, returns, num_returns, params,
5145 num_params, -1, last_sgpr);
5146 func = ctx.radeon_bld.main_fn;
5147
5148 /* Copy inputs to outputs. This should be no-op, as the registers match,
5149 * but it will prevent the compiler from overwriting them unintentionally.
5150 */
5151 ret = ctx.return_value;
5152 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5153 LLVMValueRef p = LLVMGetParam(func, i);
5154 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5155 }
5156 for (i = num_params - 4; i < num_params; i++) {
5157 LLVMValueRef p = LLVMGetParam(func, i);
5158 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
5159 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5160 }
5161
5162 /* Compute vertex load indices from instance divisors. */
5163 for (i = 0; i <= key->vs_prolog.last_input; i++) {
5164 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
5165 LLVMValueRef index;
5166
5167 if (divisor) {
5168 /* InstanceID / Divisor + StartInstance */
5169 index = get_instance_index_for_fetch(&ctx.radeon_bld,
5170 SI_SGPR_START_INSTANCE,
5171 divisor);
5172 } else {
5173 /* VertexID + BaseVertex */
5174 index = LLVMBuildAdd(gallivm->builder,
5175 LLVMGetParam(func, ctx.param_vertex_id),
5176 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
5177 }
5178
5179 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
5180 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
5181 num_params++, "");
5182 }
5183
5184 /* Compile. */
5185 LLVMBuildRet(gallivm->builder, ret);
5186 radeon_llvm_finalize_module(&ctx.radeon_bld);
5187
5188 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5189 gallivm->module, debug, ctx.type,
5190 "Vertex Shader Prolog"))
5191 status = false;
5192
5193 radeon_llvm_dispose(&ctx.radeon_bld);
5194 return status;
5195 }
5196
5197 /**
5198 * Compile the vertex shader epilog. This is also used by the tessellation
5199 * evaluation shader compiled as VS.
5200 *
5201 * The input is PrimitiveID.
5202 *
5203 * If PrimitiveID is required by the pixel shader, export it.
5204 * Otherwise, do nothing.
5205 */
5206 static bool si_compile_vs_epilog(struct si_screen *sscreen,
5207 LLVMTargetMachineRef tm,
5208 struct pipe_debug_callback *debug,
5209 struct si_shader_part *out)
5210 {
5211 union si_shader_part_key *key = &out->key;
5212 struct si_shader_context ctx;
5213 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5214 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5215 LLVMTypeRef params[5];
5216 int num_params, i;
5217 bool status = true;
5218
5219 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
5220 ctx.type = TGSI_PROCESSOR_VERTEX;
5221
5222 /* Declare input VGPRs. */
5223 num_params = key->vs_epilog.states.export_prim_id ?
5224 (VS_EPILOG_PRIMID_LOC + 1) : 0;
5225 assert(num_params <= ARRAY_SIZE(params));
5226
5227 for (i = 0; i < num_params; i++)
5228 params[i] = ctx.f32;
5229
5230 /* Create the function. */
5231 si_create_function(&ctx, NULL, 0, params, num_params,
5232 -1, -1);
5233
5234 /* Emit exports. */
5235 if (key->vs_epilog.states.export_prim_id) {
5236 struct lp_build_context *base = &bld_base->base;
5237 struct lp_build_context *uint = &bld_base->uint_bld;
5238 LLVMValueRef args[9];
5239
5240 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
5241 args[1] = uint->zero; /* whether the EXEC mask is valid */
5242 args[2] = uint->zero; /* DONE bit */
5243 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
5244 key->vs_epilog.prim_id_param_offset);
5245 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
5246 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
5247 VS_EPILOG_PRIMID_LOC); /* X */
5248 args[6] = uint->undef; /* Y */
5249 args[7] = uint->undef; /* Z */
5250 args[8] = uint->undef; /* W */
5251
5252 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
5253 LLVMVoidTypeInContext(base->gallivm->context),
5254 args, 9, 0);
5255 }
5256
5257 /* Compile. */
5258 LLVMBuildRet(gallivm->builder, ctx.return_value);
5259 radeon_llvm_finalize_module(&ctx.radeon_bld);
5260
5261 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5262 gallivm->module, debug, ctx.type,
5263 "Vertex Shader Epilog"))
5264 status = false;
5265
5266 radeon_llvm_dispose(&ctx.radeon_bld);
5267 return status;
5268 }
5269
5270 /**
5271 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
5272 */
5273 static bool si_get_vs_epilog(struct si_screen *sscreen,
5274 LLVMTargetMachineRef tm,
5275 struct si_shader *shader,
5276 struct pipe_debug_callback *debug,
5277 struct si_vs_epilog_bits *states)
5278 {
5279 union si_shader_part_key epilog_key;
5280
5281 memset(&epilog_key, 0, sizeof(epilog_key));
5282 epilog_key.vs_epilog.states = *states;
5283
5284 /* Set up the PrimitiveID output. */
5285 if (shader->key.vs.epilog.export_prim_id) {
5286 unsigned index = shader->selector->info.num_outputs;
5287 unsigned offset = shader->info.nr_param_exports++;
5288
5289 epilog_key.vs_epilog.prim_id_param_offset = offset;
5290 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
5291 shader->info.vs_output_param_offset[index] = offset;
5292 }
5293
5294 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
5295 &epilog_key, tm, debug,
5296 si_compile_vs_epilog);
5297 return shader->epilog != NULL;
5298 }
5299
5300 /**
5301 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
5302 */
5303 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
5304 LLVMTargetMachineRef tm,
5305 struct si_shader *shader,
5306 struct pipe_debug_callback *debug)
5307 {
5308 struct tgsi_shader_info *info = &shader->selector->info;
5309 union si_shader_part_key prolog_key;
5310 unsigned i;
5311
5312 /* Get the prolog. */
5313 memset(&prolog_key, 0, sizeof(prolog_key));
5314 prolog_key.vs_prolog.states = shader->key.vs.prolog;
5315 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5316 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5317
5318 /* The prolog is a no-op if there are no inputs. */
5319 if (info->num_inputs) {
5320 shader->prolog =
5321 si_get_shader_part(sscreen, &sscreen->vs_prologs,
5322 &prolog_key, tm, debug,
5323 si_compile_vs_prolog);
5324 if (!shader->prolog)
5325 return false;
5326 }
5327
5328 /* Get the epilog. */
5329 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
5330 !si_get_vs_epilog(sscreen, tm, shader, debug,
5331 &shader->key.vs.epilog))
5332 return false;
5333
5334 /* Set the instanceID flag. */
5335 for (i = 0; i < info->num_inputs; i++)
5336 if (prolog_key.vs_prolog.states.instance_divisors[i])
5337 shader->info.uses_instanceid = true;
5338
5339 return true;
5340 }
5341
5342 /**
5343 * Select and compile (or reuse) TES parts (epilog).
5344 */
5345 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
5346 LLVMTargetMachineRef tm,
5347 struct si_shader *shader,
5348 struct pipe_debug_callback *debug)
5349 {
5350 if (shader->key.tes.as_es)
5351 return true;
5352
5353 /* TES compiled as VS. */
5354 return si_get_vs_epilog(sscreen, tm, shader, debug,
5355 &shader->key.tes.epilog);
5356 }
5357
5358 /**
5359 * Compile the TCS epilog. This writes tesselation factors to memory based on
5360 * the output primitive type of the tesselator (determined by TES).
5361 */
5362 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
5363 LLVMTargetMachineRef tm,
5364 struct pipe_debug_callback *debug,
5365 struct si_shader_part *out)
5366 {
5367 union si_shader_part_key *key = &out->key;
5368 struct si_shader shader = {};
5369 struct si_shader_context ctx;
5370 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5371 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5372 LLVMTypeRef params[16];
5373 LLVMValueRef func;
5374 int last_array_pointer, last_sgpr, num_params;
5375 bool status = true;
5376
5377 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5378 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
5379 shader.key.tcs.epilog = key->tcs_epilog.states;
5380
5381 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
5382 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
5383 last_array_pointer = SI_PARAM_RW_BUFFERS;
5384 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5385 params[SI_PARAM_SAMPLERS] = ctx.i64;
5386 params[SI_PARAM_UNUSED] = ctx.i64;
5387 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
5388 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
5389 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
5390 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
5391 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5392 num_params = last_sgpr + 1;
5393
5394 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
5395 params[num_params++] = ctx.i32; /* invocation ID within the patch */
5396 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
5397
5398 /* Create the function. */
5399 si_create_function(&ctx, NULL, 0, params, num_params,
5400 last_array_pointer, last_sgpr);
5401 declare_tess_lds(&ctx);
5402 func = ctx.radeon_bld.main_fn;
5403
5404 si_write_tess_factors(bld_base,
5405 LLVMGetParam(func, last_sgpr + 1),
5406 LLVMGetParam(func, last_sgpr + 2),
5407 LLVMGetParam(func, last_sgpr + 3));
5408
5409 /* Compile. */
5410 LLVMBuildRet(gallivm->builder, ctx.return_value);
5411 radeon_llvm_finalize_module(&ctx.radeon_bld);
5412
5413 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5414 gallivm->module, debug, ctx.type,
5415 "Tessellation Control Shader Epilog"))
5416 status = false;
5417
5418 radeon_llvm_dispose(&ctx.radeon_bld);
5419 return status;
5420 }
5421
5422 /**
5423 * Select and compile (or reuse) TCS parts (epilog).
5424 */
5425 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
5426 LLVMTargetMachineRef tm,
5427 struct si_shader *shader,
5428 struct pipe_debug_callback *debug)
5429 {
5430 union si_shader_part_key epilog_key;
5431
5432 /* Get the epilog. */
5433 memset(&epilog_key, 0, sizeof(epilog_key));
5434 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
5435
5436 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
5437 &epilog_key, tm, debug,
5438 si_compile_tcs_epilog);
5439 return shader->epilog != NULL;
5440 }
5441
5442 /**
5443 * Compile the pixel shader prolog. This handles:
5444 * - two-side color selection and interpolation
5445 * - overriding interpolation parameters for the API PS
5446 * - polygon stippling
5447 *
5448 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
5449 * overriden by other states. (e.g. per-sample interpolation)
5450 * Interpolated colors are stored after the preloaded VGPRs.
5451 */
5452 static bool si_compile_ps_prolog(struct si_screen *sscreen,
5453 LLVMTargetMachineRef tm,
5454 struct pipe_debug_callback *debug,
5455 struct si_shader_part *out)
5456 {
5457 union si_shader_part_key *key = &out->key;
5458 struct si_shader shader = {};
5459 struct si_shader_context ctx;
5460 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5461 LLVMTypeRef *params;
5462 LLVMValueRef ret, func;
5463 int last_sgpr, num_params, num_returns, i, num_color_channels;
5464 bool status = true;
5465
5466 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5467 ctx.type = TGSI_PROCESSOR_FRAGMENT;
5468 shader.key.ps.prolog = key->ps_prolog.states;
5469
5470 /* Number of inputs + 8 color elements. */
5471 params = alloca((key->ps_prolog.num_input_sgprs +
5472 key->ps_prolog.num_input_vgprs + 8) *
5473 sizeof(LLVMTypeRef));
5474
5475 /* Declare inputs. */
5476 num_params = 0;
5477 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
5478 params[num_params++] = ctx.i32;
5479 last_sgpr = num_params - 1;
5480
5481 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
5482 params[num_params++] = ctx.f32;
5483
5484 /* Declare outputs (same as inputs + add colors if needed) */
5485 num_returns = num_params;
5486 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
5487 for (i = 0; i < num_color_channels; i++)
5488 params[num_returns++] = ctx.f32;
5489
5490 /* Create the function. */
5491 si_create_function(&ctx, params, num_returns, params,
5492 num_params, -1, last_sgpr);
5493 func = ctx.radeon_bld.main_fn;
5494
5495 /* Copy inputs to outputs. This should be no-op, as the registers match,
5496 * but it will prevent the compiler from overwriting them unintentionally.
5497 */
5498 ret = ctx.return_value;
5499 for (i = 0; i < num_params; i++) {
5500 LLVMValueRef p = LLVMGetParam(func, i);
5501 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5502 }
5503
5504 /* Polygon stippling. */
5505 if (key->ps_prolog.states.poly_stipple) {
5506 /* POS_FIXED_PT is always last. */
5507 unsigned pos = key->ps_prolog.num_input_sgprs +
5508 key->ps_prolog.num_input_vgprs - 1;
5509 LLVMValueRef ptr[2], views;
5510
5511 /* Get the pointer to sampler views. */
5512 ptr[0] = LLVMGetParam(func, SI_SGPR_SAMPLERS);
5513 ptr[1] = LLVMGetParam(func, SI_SGPR_SAMPLERS+1);
5514 views = lp_build_gather_values(gallivm, ptr, 2);
5515 views = LLVMBuildBitCast(gallivm->builder, views, ctx.i64, "");
5516 views = LLVMBuildIntToPtr(gallivm->builder, views,
5517 const_array(ctx.v8i32, SI_NUM_SAMPLERS), "");
5518
5519 si_llvm_emit_polygon_stipple(&ctx, views, pos);
5520 }
5521
5522 /* Interpolate colors. */
5523 for (i = 0; i < 2; i++) {
5524 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
5525 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
5526 key->ps_prolog.face_vgpr_index;
5527 LLVMValueRef interp[2], color[4];
5528 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
5529
5530 if (!writemask)
5531 continue;
5532
5533 /* If the interpolation qualifier is not CONSTANT (-1). */
5534 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
5535 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
5536 key->ps_prolog.color_interp_vgpr_index[i];
5537
5538 interp[0] = LLVMGetParam(func, interp_vgpr);
5539 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
5540 interp_ij = lp_build_gather_values(gallivm, interp, 2);
5541 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
5542 ctx.v2i32, "");
5543 }
5544
5545 /* Use the absolute location of the input. */
5546 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
5547
5548 if (key->ps_prolog.states.color_two_side) {
5549 face = LLVMGetParam(func, face_vgpr);
5550 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
5551 }
5552
5553 interp_fs_input(&ctx,
5554 key->ps_prolog.color_attr_index[i],
5555 TGSI_SEMANTIC_COLOR, i,
5556 key->ps_prolog.num_interp_inputs,
5557 key->ps_prolog.colors_read, interp_ij,
5558 prim_mask, face, color);
5559
5560 while (writemask) {
5561 unsigned chan = u_bit_scan(&writemask);
5562 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
5563 num_params++, "");
5564 }
5565 }
5566
5567 /* Force per-sample interpolation. */
5568 if (key->ps_prolog.states.force_persample_interp) {
5569 unsigned i, base = key->ps_prolog.num_input_sgprs;
5570 LLVMValueRef persp_sample[2], linear_sample[2];
5571
5572 /* Read PERSP_SAMPLE. */
5573 for (i = 0; i < 2; i++)
5574 persp_sample[i] = LLVMGetParam(func, base + i);
5575 /* Overwrite PERSP_CENTER. */
5576 for (i = 0; i < 2; i++)
5577 ret = LLVMBuildInsertValue(gallivm->builder, ret,
5578 persp_sample[i], base + 2 + i, "");
5579 /* Overwrite PERSP_CENTROID. */
5580 for (i = 0; i < 2; i++)
5581 ret = LLVMBuildInsertValue(gallivm->builder, ret,
5582 persp_sample[i], base + 4 + i, "");
5583 /* Read LINEAR_SAMPLE. */
5584 for (i = 0; i < 2; i++)
5585 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
5586 /* Overwrite LINEAR_CENTER. */
5587 for (i = 0; i < 2; i++)
5588 ret = LLVMBuildInsertValue(gallivm->builder, ret,
5589 linear_sample[i], base + 8 + i, "");
5590 /* Overwrite LINEAR_CENTROID. */
5591 for (i = 0; i < 2; i++)
5592 ret = LLVMBuildInsertValue(gallivm->builder, ret,
5593 linear_sample[i], base + 10 + i, "");
5594 }
5595
5596 /* Compile. */
5597 LLVMBuildRet(gallivm->builder, ret);
5598 radeon_llvm_finalize_module(&ctx.radeon_bld);
5599
5600 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5601 gallivm->module, debug, ctx.type,
5602 "Fragment Shader Prolog"))
5603 status = false;
5604
5605 radeon_llvm_dispose(&ctx.radeon_bld);
5606 return status;
5607 }
5608
5609 /**
5610 * Compile the pixel shader epilog. This handles everything that must be
5611 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
5612 */
5613 static bool si_compile_ps_epilog(struct si_screen *sscreen,
5614 LLVMTargetMachineRef tm,
5615 struct pipe_debug_callback *debug,
5616 struct si_shader_part *out)
5617 {
5618 union si_shader_part_key *key = &out->key;
5619 struct si_shader shader = {};
5620 struct si_shader_context ctx;
5621 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5622 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5623 LLVMTypeRef params[16+8*4+3];
5624 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5625 int last_array_pointer, last_sgpr, num_params, i;
5626 bool status = true;
5627
5628 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5629 ctx.type = TGSI_PROCESSOR_FRAGMENT;
5630 shader.key.ps.epilog = key->ps_epilog.states;
5631
5632 /* Declare input SGPRs. */
5633 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
5634 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5635 params[SI_PARAM_SAMPLERS] = ctx.i64;
5636 params[SI_PARAM_UNUSED] = ctx.i64;
5637 params[SI_PARAM_ALPHA_REF] = ctx.f32;
5638 last_array_pointer = -1;
5639 last_sgpr = SI_PARAM_ALPHA_REF;
5640
5641 /* Declare input VGPRs. */
5642 num_params = (last_sgpr + 1) +
5643 util_bitcount(key->ps_epilog.colors_written) * 4 +
5644 key->ps_epilog.writes_z +
5645 key->ps_epilog.writes_stencil +
5646 key->ps_epilog.writes_samplemask;
5647
5648 num_params = MAX2(num_params,
5649 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5650
5651 assert(num_params <= ARRAY_SIZE(params));
5652
5653 for (i = last_sgpr + 1; i < num_params; i++)
5654 params[i] = ctx.f32;
5655
5656 /* Create the function. */
5657 si_create_function(&ctx, NULL, 0, params, num_params,
5658 last_array_pointer, last_sgpr);
5659 /* Disable elimination of unused inputs. */
5660 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
5661 "InitialPSInputAddr", 0xffffff);
5662
5663 /* Process colors. */
5664 unsigned vgpr = last_sgpr + 1;
5665 unsigned colors_written = key->ps_epilog.colors_written;
5666 int last_color_export = -1;
5667
5668 /* Find the last color export. */
5669 if (!key->ps_epilog.writes_z &&
5670 !key->ps_epilog.writes_stencil &&
5671 !key->ps_epilog.writes_samplemask) {
5672 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
5673
5674 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
5675 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
5676 /* Just set this if any of the colorbuffers are enabled. */
5677 if (spi_format &
5678 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
5679 last_color_export = 0;
5680 } else {
5681 for (i = 0; i < 8; i++)
5682 if (colors_written & (1 << i) &&
5683 (spi_format >> (i * 4)) & 0xf)
5684 last_color_export = i;
5685 }
5686 }
5687
5688 while (colors_written) {
5689 LLVMValueRef color[4];
5690 int mrt = u_bit_scan(&colors_written);
5691
5692 for (i = 0; i < 4; i++)
5693 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5694
5695 si_export_mrt_color(bld_base, color, mrt,
5696 num_params - 1,
5697 mrt == last_color_export);
5698 }
5699
5700 /* Process depth, stencil, samplemask. */
5701 if (key->ps_epilog.writes_z)
5702 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5703 if (key->ps_epilog.writes_stencil)
5704 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5705 if (key->ps_epilog.writes_samplemask)
5706 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
5707
5708 if (depth || stencil || samplemask)
5709 si_export_mrt_z(bld_base, depth, stencil, samplemask);
5710 else if (last_color_export == -1)
5711 si_export_null(bld_base);
5712
5713 /* Compile. */
5714 LLVMBuildRetVoid(gallivm->builder);
5715 radeon_llvm_finalize_module(&ctx.radeon_bld);
5716
5717 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5718 gallivm->module, debug, ctx.type,
5719 "Fragment Shader Epilog"))
5720 status = false;
5721
5722 radeon_llvm_dispose(&ctx.radeon_bld);
5723 return status;
5724 }
5725
5726 /**
5727 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
5728 */
5729 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
5730 LLVMTargetMachineRef tm,
5731 struct si_shader *shader,
5732 struct pipe_debug_callback *debug)
5733 {
5734 struct tgsi_shader_info *info = &shader->selector->info;
5735 union si_shader_part_key prolog_key;
5736 union si_shader_part_key epilog_key;
5737 unsigned i;
5738
5739 /* Get the prolog. */
5740 memset(&prolog_key, 0, sizeof(prolog_key));
5741 prolog_key.ps_prolog.states = shader->key.ps.prolog;
5742 prolog_key.ps_prolog.colors_read = info->colors_read;
5743 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5744 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5745
5746 if (info->colors_read) {
5747 unsigned *color = shader->selector->color_attr_index;
5748
5749 if (shader->key.ps.prolog.color_two_side) {
5750 /* BCOLORs are stored after the last input. */
5751 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
5752 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5753 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5754 }
5755
5756 for (i = 0; i < 2; i++) {
5757 unsigned location = info->input_interpolate_loc[color[i]];
5758
5759 if (!(info->colors_read & (0xf << i*4)))
5760 continue;
5761
5762 prolog_key.ps_prolog.color_attr_index[i] = color[i];
5763
5764 /* Force per-sample interpolation for the colors here. */
5765 if (shader->key.ps.prolog.force_persample_interp)
5766 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5767
5768 switch (info->input_interpolate[color[i]]) {
5769 case TGSI_INTERPOLATE_CONSTANT:
5770 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
5771 break;
5772 case TGSI_INTERPOLATE_PERSPECTIVE:
5773 case TGSI_INTERPOLATE_COLOR:
5774 switch (location) {
5775 case TGSI_INTERPOLATE_LOC_SAMPLE:
5776 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
5777 shader->config.spi_ps_input_ena |=
5778 S_0286CC_PERSP_SAMPLE_ENA(1);
5779 break;
5780 case TGSI_INTERPOLATE_LOC_CENTER:
5781 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
5782 shader->config.spi_ps_input_ena |=
5783 S_0286CC_PERSP_CENTER_ENA(1);
5784 break;
5785 case TGSI_INTERPOLATE_LOC_CENTROID:
5786 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
5787 shader->config.spi_ps_input_ena |=
5788 S_0286CC_PERSP_CENTROID_ENA(1);
5789 break;
5790 default:
5791 assert(0);
5792 }
5793 break;
5794 case TGSI_INTERPOLATE_LINEAR:
5795 switch (location) {
5796 case TGSI_INTERPOLATE_LOC_SAMPLE:
5797 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
5798 shader->config.spi_ps_input_ena |=
5799 S_0286CC_LINEAR_SAMPLE_ENA(1);
5800 break;
5801 case TGSI_INTERPOLATE_LOC_CENTER:
5802 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
5803 shader->config.spi_ps_input_ena |=
5804 S_0286CC_LINEAR_CENTER_ENA(1);
5805 break;
5806 case TGSI_INTERPOLATE_LOC_CENTROID:
5807 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
5808 shader->config.spi_ps_input_ena |=
5809 S_0286CC_LINEAR_CENTROID_ENA(1);
5810 break;
5811 default:
5812 assert(0);
5813 }
5814 break;
5815 default:
5816 assert(0);
5817 }
5818 }
5819 }
5820
5821 /* The prolog is a no-op if these aren't set. */
5822 if (prolog_key.ps_prolog.colors_read ||
5823 prolog_key.ps_prolog.states.force_persample_interp ||
5824 prolog_key.ps_prolog.states.poly_stipple) {
5825 shader->prolog =
5826 si_get_shader_part(sscreen, &sscreen->ps_prologs,
5827 &prolog_key, tm, debug,
5828 si_compile_ps_prolog);
5829 if (!shader->prolog)
5830 return false;
5831 }
5832
5833 /* Get the epilog. */
5834 memset(&epilog_key, 0, sizeof(epilog_key));
5835 epilog_key.ps_epilog.colors_written = info->colors_written;
5836 epilog_key.ps_epilog.writes_z = info->writes_z;
5837 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
5838 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
5839 epilog_key.ps_epilog.states = shader->key.ps.epilog;
5840
5841 shader->epilog =
5842 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
5843 &epilog_key, tm, debug,
5844 si_compile_ps_epilog);
5845 if (!shader->epilog)
5846 return false;
5847
5848 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
5849 if (shader->key.ps.prolog.poly_stipple) {
5850 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
5851 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
5852 }
5853
5854 /* Set up the enable bits for per-sample shading if needed. */
5855 if (shader->key.ps.prolog.force_persample_interp) {
5856 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
5857 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
5858 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
5859 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
5860 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
5861 }
5862 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
5863 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
5864 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
5865 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
5866 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
5867 }
5868 }
5869
5870 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
5871 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
5872 !(shader->config.spi_ps_input_ena & 0xf)) {
5873 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
5874 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
5875 }
5876
5877 /* At least one pair of interpolation weights must be enabled. */
5878 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
5879 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
5880 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
5881 }
5882
5883 /* The sample mask input is always enabled, because the API shader always
5884 * passes it through to the epilog. Disable it here if it's unused.
5885 */
5886 if (!shader->key.ps.epilog.poly_line_smoothing &&
5887 !shader->selector->info.reads_samplemask)
5888 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
5889
5890 return true;
5891 }
5892
5893 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
5894 struct si_shader *shader,
5895 struct pipe_debug_callback *debug)
5896 {
5897 struct si_shader *mainp = shader->selector->main_shader_part;
5898 int r;
5899
5900 /* LS, ES, VS are compiled on demand if the main part hasn't been
5901 * compiled for that stage.
5902 */
5903 if (!mainp ||
5904 (shader->selector->type == PIPE_SHADER_VERTEX &&
5905 (shader->key.vs.as_es != mainp->key.vs.as_es ||
5906 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
5907 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
5908 shader->key.tes.as_es != mainp->key.tes.as_es)) {
5909 /* Monolithic shader (compiled as a whole, has many variants,
5910 * may take a long time to compile).
5911 */
5912 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
5913 if (r)
5914 return r;
5915 } else {
5916 /* The shader consists of 2-3 parts:
5917 *
5918 * - the middle part is the user shader, it has 1 variant only
5919 * and it was compiled during the creation of the shader
5920 * selector
5921 * - the prolog part is inserted at the beginning
5922 * - the epilog part is inserted at the end
5923 *
5924 * The prolog and epilog have many (but simple) variants.
5925 */
5926
5927 /* Copy the compiled TGSI shader data over. */
5928 shader->is_binary_shared = true;
5929 shader->binary = mainp->binary;
5930 shader->config = mainp->config;
5931 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
5932 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
5933 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
5934 memcpy(shader->info.vs_output_param_offset,
5935 mainp->info.vs_output_param_offset,
5936 sizeof(mainp->info.vs_output_param_offset));
5937 shader->info.uses_instanceid = mainp->info.uses_instanceid;
5938 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
5939 shader->info.nr_param_exports = mainp->info.nr_param_exports;
5940
5941 /* Select prologs and/or epilogs. */
5942 switch (shader->selector->type) {
5943 case PIPE_SHADER_VERTEX:
5944 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
5945 return -1;
5946 break;
5947 case PIPE_SHADER_TESS_CTRL:
5948 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
5949 return -1;
5950 break;
5951 case PIPE_SHADER_TESS_EVAL:
5952 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
5953 return -1;
5954 break;
5955 case PIPE_SHADER_FRAGMENT:
5956 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
5957 return -1;
5958
5959 /* Make sure we have at least as many VGPRs as there
5960 * are allocated inputs.
5961 */
5962 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5963 shader->info.num_input_vgprs);
5964 break;
5965 }
5966
5967 /* Update SGPR and VGPR counts. */
5968 if (shader->prolog) {
5969 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
5970 shader->prolog->config.num_sgprs);
5971 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5972 shader->prolog->config.num_vgprs);
5973 }
5974 if (shader->epilog) {
5975 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
5976 shader->epilog->config.num_sgprs);
5977 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
5978 shader->epilog->config.num_vgprs);
5979 }
5980 }
5981
5982 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
5983 stderr);
5984
5985 /* Upload. */
5986 r = si_shader_binary_upload(sscreen, shader);
5987 if (r) {
5988 fprintf(stderr, "LLVM failed to upload shader\n");
5989 return r;
5990 }
5991
5992 return 0;
5993 }
5994
5995 void si_shader_destroy(struct si_shader *shader)
5996 {
5997 if (shader->gs_copy_shader) {
5998 si_shader_destroy(shader->gs_copy_shader);
5999 FREE(shader->gs_copy_shader);
6000 }
6001
6002 if (shader->scratch_bo)
6003 r600_resource_reference(&shader->scratch_bo, NULL);
6004
6005 r600_resource_reference(&shader->bo, NULL);
6006
6007 if (!shader->is_binary_shared)
6008 radeon_shader_binary_clean(&shader->binary);
6009 }