projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: Refactor image store/load intrinsic name creation
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_string.h"
41 #include "tgsi/tgsi_build.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 struct si_shader_context
63 {
64 struct radeon_llvm_context radeon_bld;
65 struct si_shader *shader;
66 struct si_screen *screen;
67
68 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
69 bool is_gs_copy_shader;
70
71 /* Whether to generate the optimized shader variant compiled as a whole
72 * (without a prolog and epilog)
73 */
74 bool is_monolithic;
75
76 int param_streamout_config;
77 int param_streamout_write_index;
78 int param_streamout_offset[4];
79 int param_vertex_id;
80 int param_rel_auto_id;
81 int param_vs_prim_id;
82 int param_instance_id;
83 int param_vertex_index0;
84 int param_tes_u;
85 int param_tes_v;
86 int param_tes_rel_patch_id;
87 int param_tes_patch_id;
88 int param_es2gs_offset;
89 int param_oc_lds;
90
91 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
92 * 0x800000 for VS, 0x1 for ES.
93 */
94 int param_tess_offchip;
95
96 LLVMTargetMachineRef tm;
97
98 unsigned invariant_load_md_kind;
99 unsigned range_md_kind;
100 unsigned uniform_md_kind;
101 LLVMValueRef empty_md;
102
103 /* Preloaded descriptors. */
104 LLVMValueRef esgs_ring;
105 LLVMValueRef gsvs_ring[4];
106
107 LLVMValueRef lds;
108 LLVMValueRef gs_next_vertex[4];
109 LLVMValueRef return_value;
110
111 LLVMTypeRef voidt;
112 LLVMTypeRef i1;
113 LLVMTypeRef i8;
114 LLVMTypeRef i32;
115 LLVMTypeRef i64;
116 LLVMTypeRef i128;
117 LLVMTypeRef f32;
118 LLVMTypeRef v16i8;
119 LLVMTypeRef v2i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v8i32;
123
124 LLVMValueRef shared_memory;
125 };
126
127 static struct si_shader_context *si_shader_context(
128 struct lp_build_tgsi_context *bld_base)
129 {
130 return (struct si_shader_context *)bld_base;
131 }
132
133 static void si_init_shader_ctx(struct si_shader_context *ctx,
134 struct si_screen *sscreen,
135 struct si_shader *shader,
136 LLVMTargetMachineRef tm);
137
138 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
139 struct lp_build_tgsi_context *bld_base,
140 struct lp_build_emit_data *emit_data);
141
142 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
143 FILE *f);
144
145 /* Ideally pass the sample mask input to the PS epilog as v13, which
146 * is its usual location, so that the shader doesn't have to add v_mov.
147 */
148 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
149
150 /* The VS location of the PrimitiveID input is the same in the epilog,
151 * so that the main shader part doesn't have to move it.
152 */
153 #define VS_EPILOG_PRIMID_LOC 2
154
155 enum {
156 CONST_ADDR_SPACE = 2,
157 LOCAL_ADDR_SPACE = 3,
158 };
159
160 #define SENDMSG_GS 2
161 #define SENDMSG_GS_DONE 3
162
163 #define SENDMSG_GS_OP_NOP (0 << 4)
164 #define SENDMSG_GS_OP_CUT (1 << 4)
165 #define SENDMSG_GS_OP_EMIT (2 << 4)
166 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
174 {
175 switch (semantic_name) {
176 case TGSI_SEMANTIC_POSITION:
177 return 0;
178 case TGSI_SEMANTIC_PSIZE:
179 return 1;
180 case TGSI_SEMANTIC_CLIPDIST:
181 assert(index <= 1);
182 return 2 + index;
183 case TGSI_SEMANTIC_GENERIC:
184 if (index <= 63-4)
185 return 4 + index;
186 else
187 /* same explanation as in the default statement,
188 * the only user hitting this is st/nine.
189 */
190 return 0;
191
192 /* patch indices are completely separate and thus start from 0 */
193 case TGSI_SEMANTIC_TESSOUTER:
194 return 0;
195 case TGSI_SEMANTIC_TESSINNER:
196 return 1;
197 case TGSI_SEMANTIC_PATCH:
198 return 2 + index;
199
200 default:
201 /* Don't fail here. The result of this function is only used
202 * for LS, TCS, TES, and GS, where legacy GL semantics can't
203 * occur, but this function is called for all vertex shaders
204 * before it's known whether LS will be compiled or not.
205 */
206 return 0;
207 }
208 }
209
210 /**
211 * Get the value of a shader input parameter and extract a bitfield.
212 */
213 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
214 unsigned param, unsigned rshift,
215 unsigned bitwidth)
216 {
217 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
218 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
219 param);
220
221 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
222 value = bitcast(&ctx->radeon_bld.soa.bld_base,
223 TGSI_TYPE_UNSIGNED, value);
224
225 if (rshift)
226 value = LLVMBuildLShr(gallivm->builder, value,
227 lp_build_const_int32(gallivm, rshift), "");
228
229 if (rshift + bitwidth < 32) {
230 unsigned mask = (1 << bitwidth) - 1;
231 value = LLVMBuildAnd(gallivm->builder, value,
232 lp_build_const_int32(gallivm, mask), "");
233 }
234
235 return value;
236 }
237
238 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
239 {
240 switch (ctx->type) {
241 case PIPE_SHADER_TESS_CTRL:
242 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
243
244 case PIPE_SHADER_TESS_EVAL:
245 return LLVMGetParam(ctx->radeon_bld.main_fn,
246 ctx->param_tes_rel_patch_id);
247
248 default:
249 assert(0);
250 return NULL;
251 }
252 }
253
254 /* Tessellation shaders pass outputs to the next shader using LDS.
255 *
256 * LS outputs = TCS inputs
257 * TCS outputs = TES inputs
258 *
259 * The LDS layout is:
260 * - TCS inputs for patch 0
261 * - TCS inputs for patch 1
262 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
263 * - ...
264 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
265 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
266 * - TCS outputs for patch 1
267 * - Per-patch TCS outputs for patch 1
268 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
269 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
270 * - ...
271 *
272 * All three shaders VS(LS), TCS, TES share the same LDS space.
273 */
274
275 static LLVMValueRef
276 get_tcs_in_patch_stride(struct si_shader_context *ctx)
277 {
278 if (ctx->type == PIPE_SHADER_VERTEX)
279 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
280 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
281 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
282 else {
283 assert(0);
284 return NULL;
285 }
286 }
287
288 static LLVMValueRef
289 get_tcs_out_patch_stride(struct si_shader_context *ctx)
290 {
291 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
292 }
293
294 static LLVMValueRef
295 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
296 {
297 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
298 unpack_param(ctx,
299 SI_PARAM_TCS_OUT_OFFSETS,
300 0, 16),
301 4);
302 }
303
304 static LLVMValueRef
305 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
306 {
307 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
308 unpack_param(ctx,
309 SI_PARAM_TCS_OUT_OFFSETS,
310 16, 16),
311 4);
312 }
313
314 static LLVMValueRef
315 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
316 {
317 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
318 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
319 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
320
321 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
322 }
323
324 static LLVMValueRef
325 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
326 {
327 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return LLVMBuildAdd(gallivm->builder, patch0_offset,
333 LLVMBuildMul(gallivm->builder, patch_stride,
334 rel_patch_id, ""),
335 "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_patch_data_offset =
343 get_tcs_out_patch0_patch_data_offset(ctx);
344 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
345 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
346
347 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
348 LLVMBuildMul(gallivm->builder, patch_stride,
349 rel_patch_id, ""),
350 "");
351 }
352
353 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
354 LLVMValueRef base_ptr, LLVMValueRef index)
355 {
356 LLVMValueRef indices[2] = {
357 LLVMConstInt(ctx->i32, 0, 0),
358 index,
359 };
360 return LLVMBuildGEP(ctx->radeon_bld.gallivm.builder, base_ptr,
361 indices, 2, "");
362 }
363
364 static void build_indexed_store(struct si_shader_context *ctx,
365 LLVMValueRef base_ptr, LLVMValueRef index,
366 LLVMValueRef value)
367 {
368 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
369 struct gallivm_state *gallivm = bld_base->base.gallivm;
370
371 LLVMBuildStore(gallivm->builder, value,
372 build_gep0(ctx, base_ptr, index));
373 }
374
375 /**
376 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
377 * It's equivalent to doing a load from &base_ptr[index].
378 *
379 * \param base_ptr Where the array starts.
380 * \param index The element index into the array.
381 * \param uniform Whether the base_ptr and index can be assumed to be
382 * dynamically uniform
383 */
384 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
385 LLVMValueRef base_ptr, LLVMValueRef index,
386 bool uniform)
387 {
388 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
389 struct gallivm_state *gallivm = bld_base->base.gallivm;
390 LLVMValueRef pointer;
391
392 pointer = build_gep0(ctx, base_ptr, index);
393 if (uniform)
394 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
395 return LLVMBuildLoad(gallivm->builder, pointer, "");
396 }
397
398 /**
399 * Do a load from &base_ptr[index], but also add a flag that it's loading
400 * a constant from a dynamically uniform index.
401 */
402 static LLVMValueRef build_indexed_load_const(
403 struct si_shader_context *ctx,
404 LLVMValueRef base_ptr, LLVMValueRef index)
405 {
406 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
407 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
408 return result;
409 }
410
411 static LLVMValueRef get_instance_index_for_fetch(
412 struct radeon_llvm_context *radeon_bld,
413 unsigned param_start_instance, unsigned divisor)
414 {
415 struct si_shader_context *ctx =
416 si_shader_context(&radeon_bld->soa.bld_base);
417 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
418
419 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
420 ctx->param_instance_id);
421
422 /* The division must be done before START_INSTANCE is added. */
423 if (divisor > 1)
424 result = LLVMBuildUDiv(gallivm->builder, result,
425 lp_build_const_int32(gallivm, divisor), "");
426
427 return LLVMBuildAdd(gallivm->builder, result,
428 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
429 }
430
431 static void declare_input_vs(
432 struct radeon_llvm_context *radeon_bld,
433 unsigned input_index,
434 const struct tgsi_full_declaration *decl,
435 LLVMValueRef out[4])
436 {
437 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
438 struct gallivm_state *gallivm = base->gallivm;
439 struct si_shader_context *ctx =
440 si_shader_context(&radeon_bld->soa.bld_base);
441 unsigned divisor =
442 ctx->shader->key.vs.prolog.instance_divisors[input_index];
443
444 unsigned chan;
445
446 LLVMValueRef t_list_ptr;
447 LLVMValueRef t_offset;
448 LLVMValueRef t_list;
449 LLVMValueRef attribute_offset;
450 LLVMValueRef buffer_index;
451 LLVMValueRef args[3];
452 LLVMValueRef input;
453
454 /* Load the T list */
455 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
456
457 t_offset = lp_build_const_int32(gallivm, input_index);
458
459 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
460
461 /* Build the attribute offset */
462 attribute_offset = lp_build_const_int32(gallivm, 0);
463
464 if (!ctx->is_monolithic) {
465 buffer_index = LLVMGetParam(radeon_bld->main_fn,
466 ctx->param_vertex_index0 +
467 input_index);
468 } else if (divisor) {
469 /* Build index from instance ID, start instance and divisor */
470 ctx->shader->info.uses_instanceid = true;
471 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
472 SI_PARAM_START_INSTANCE,
473 divisor);
474 } else {
475 /* Load the buffer index for vertices. */
476 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
477 ctx->param_vertex_id);
478 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
479 SI_PARAM_BASE_VERTEX);
480 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
481 }
482
483 args[0] = t_list;
484 args[1] = attribute_offset;
485 args[2] = buffer_index;
486 input = lp_build_intrinsic(gallivm->builder,
487 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
488 LLVMReadNoneAttribute);
489
490 /* Break up the vec4 into individual components */
491 for (chan = 0; chan < 4; chan++) {
492 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
493 out[chan] = LLVMBuildExtractElement(gallivm->builder,
494 input, llvm_chan, "");
495 }
496 }
497
498 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
499 unsigned swizzle)
500 {
501 struct si_shader_context *ctx = si_shader_context(bld_base);
502
503 if (swizzle > 0)
504 return bld_base->uint_bld.zero;
505
506 switch (ctx->type) {
507 case PIPE_SHADER_VERTEX:
508 return LLVMGetParam(ctx->radeon_bld.main_fn,
509 ctx->param_vs_prim_id);
510 case PIPE_SHADER_TESS_CTRL:
511 return LLVMGetParam(ctx->radeon_bld.main_fn,
512 SI_PARAM_PATCH_ID);
513 case PIPE_SHADER_TESS_EVAL:
514 return LLVMGetParam(ctx->radeon_bld.main_fn,
515 ctx->param_tes_patch_id);
516 case PIPE_SHADER_GEOMETRY:
517 return LLVMGetParam(ctx->radeon_bld.main_fn,
518 SI_PARAM_PRIMITIVE_ID);
519 default:
520 assert(0);
521 return bld_base->uint_bld.zero;
522 }
523 }
524
525 /**
526 * Return the value of tgsi_ind_register for indexing.
527 * This is the indirect index with the constant offset added to it.
528 */
529 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
530 const struct tgsi_ind_register *ind,
531 int rel_index)
532 {
533 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
534 LLVMValueRef result;
535
536 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
537 result = LLVMBuildLoad(gallivm->builder, result, "");
538 result = LLVMBuildAdd(gallivm->builder, result,
539 lp_build_const_int32(gallivm, rel_index), "");
540 return result;
541 }
542
543 /**
544 * Like get_indirect_index, but restricts the return value to a (possibly
545 * undefined) value inside [0..num).
546 */
547 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
548 const struct tgsi_ind_register *ind,
549 int rel_index, unsigned num)
550 {
551 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
552
553 /* LLVM 3.8: If indirect resource indexing is used:
554 * - SI & CIK hang
555 * - VI crashes
556 */
557 if (HAVE_LLVM <= 0x0308)
558 return LLVMGetUndef(ctx->i32);
559
560 return radeon_llvm_bound_index(&ctx->radeon_bld, result, num);
561 }
562
563
564 /**
565 * Calculate a dword address given an input or output register and a stride.
566 */
567 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
568 const struct tgsi_full_dst_register *dst,
569 const struct tgsi_full_src_register *src,
570 LLVMValueRef vertex_dw_stride,
571 LLVMValueRef base_addr)
572 {
573 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
574 struct tgsi_shader_info *info = &ctx->shader->selector->info;
575 ubyte *name, *index, *array_first;
576 int first, param;
577 struct tgsi_full_dst_register reg;
578
579 /* Set the register description. The address computation is the same
580 * for sources and destinations. */
581 if (src) {
582 reg.Register.File = src->Register.File;
583 reg.Register.Index = src->Register.Index;
584 reg.Register.Indirect = src->Register.Indirect;
585 reg.Register.Dimension = src->Register.Dimension;
586 reg.Indirect = src->Indirect;
587 reg.Dimension = src->Dimension;
588 reg.DimIndirect = src->DimIndirect;
589 } else
590 reg = *dst;
591
592 /* If the register is 2-dimensional (e.g. an array of vertices
593 * in a primitive), calculate the base address of the vertex. */
594 if (reg.Register.Dimension) {
595 LLVMValueRef index;
596
597 if (reg.Dimension.Indirect)
598 index = get_indirect_index(ctx, &reg.DimIndirect,
599 reg.Dimension.Index);
600 else
601 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
602
603 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
604 LLVMBuildMul(gallivm->builder, index,
605 vertex_dw_stride, ""), "");
606 }
607
608 /* Get information about the register. */
609 if (reg.Register.File == TGSI_FILE_INPUT) {
610 name = info->input_semantic_name;
611 index = info->input_semantic_index;
612 array_first = info->input_array_first;
613 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
614 name = info->output_semantic_name;
615 index = info->output_semantic_index;
616 array_first = info->output_array_first;
617 } else {
618 assert(0);
619 return NULL;
620 }
621
622 if (reg.Register.Indirect) {
623 /* Add the relative address of the element. */
624 LLVMValueRef ind_index;
625
626 if (reg.Indirect.ArrayID)
627 first = array_first[reg.Indirect.ArrayID];
628 else
629 first = reg.Register.Index;
630
631 ind_index = get_indirect_index(ctx, &reg.Indirect,
632 reg.Register.Index - first);
633
634 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
635 LLVMBuildMul(gallivm->builder, ind_index,
636 lp_build_const_int32(gallivm, 4), ""), "");
637
638 param = si_shader_io_get_unique_index(name[first], index[first]);
639 } else {
640 param = si_shader_io_get_unique_index(name[reg.Register.Index],
641 index[reg.Register.Index]);
642 }
643
644 /* Add the base address of the element. */
645 return LLVMBuildAdd(gallivm->builder, base_addr,
646 lp_build_const_int32(gallivm, param * 4), "");
647 }
648
649 /* The offchip buffer layout for TCS->TES is
650 *
651 * - attribute 0 of patch 0 vertex 0
652 * - attribute 0 of patch 0 vertex 1
653 * - attribute 0 of patch 0 vertex 2
654 * ...
655 * - attribute 0 of patch 1 vertex 0
656 * - attribute 0 of patch 1 vertex 1
657 * ...
658 * - attribute 1 of patch 0 vertex 0
659 * - attribute 1 of patch 0 vertex 1
660 * ...
661 * - per patch attribute 0 of patch 0
662 * - per patch attribute 0 of patch 1
663 * ...
664 *
665 * Note that every attribute has 4 components.
666 */
667 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
668 LLVMValueRef vertex_index,
669 LLVMValueRef param_index)
670 {
671 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
672 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
673 LLVMValueRef param_stride, constant16;
674
675 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
676 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
677 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
678 num_patches, "");
679
680 constant16 = lp_build_const_int32(gallivm, 16);
681 if (vertex_index) {
682 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
683 vertices_per_patch, "");
684
685 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
686 vertex_index, "");
687
688 param_stride = total_vertices;
689 } else {
690 base_addr = get_rel_patch_id(ctx);
691 param_stride = num_patches;
692 }
693
694 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
695 LLVMBuildMul(gallivm->builder, param_index,
696 param_stride, ""), "");
697
698 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
699
700 if (!vertex_index) {
701 LLVMValueRef patch_data_offset =
702 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
703
704 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
705 patch_data_offset, "");
706 }
707 return base_addr;
708 }
709
710 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
711 struct si_shader_context *ctx,
712 const struct tgsi_full_dst_register *dst,
713 const struct tgsi_full_src_register *src)
714 {
715 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
716 struct tgsi_shader_info *info = &ctx->shader->selector->info;
717 ubyte *name, *index, *array_first;
718 struct tgsi_full_src_register reg;
719 LLVMValueRef vertex_index = NULL;
720 LLVMValueRef param_index = NULL;
721 unsigned param_index_base, param_base;
722
723 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
724
725 if (reg.Register.Dimension) {
726
727 if (reg.Dimension.Indirect)
728 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
729 reg.Dimension.Index);
730 else
731 vertex_index = lp_build_const_int32(gallivm,
732 reg.Dimension.Index);
733 }
734
735 /* Get information about the register. */
736 if (reg.Register.File == TGSI_FILE_INPUT) {
737 name = info->input_semantic_name;
738 index = info->input_semantic_index;
739 array_first = info->input_array_first;
740 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
741 name = info->output_semantic_name;
742 index = info->output_semantic_index;
743 array_first = info->output_array_first;
744 } else {
745 assert(0);
746 return NULL;
747 }
748
749 if (reg.Register.Indirect) {
750 if (reg.Indirect.ArrayID)
751 param_base = array_first[reg.Indirect.ArrayID];
752 else
753 param_base = reg.Register.Index;
754
755 param_index = get_indirect_index(ctx, &reg.Indirect,
756 reg.Register.Index - param_base);
757
758 } else {
759 param_base = reg.Register.Index;
760 param_index = lp_build_const_int32(gallivm, 0);
761 }
762
763 param_index_base = si_shader_io_get_unique_index(name[param_base],
764 index[param_base]);
765
766 param_index = LLVMBuildAdd(gallivm->builder, param_index,
767 lp_build_const_int32(gallivm, param_index_base),
768 "");
769
770 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
771 }
772
773 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
774 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
775 * or v4i32 (num_channels=3,4). */
776 static void build_tbuffer_store(struct si_shader_context *ctx,
777 LLVMValueRef rsrc,
778 LLVMValueRef vdata,
779 unsigned num_channels,
780 LLVMValueRef vaddr,
781 LLVMValueRef soffset,
782 unsigned inst_offset,
783 unsigned dfmt,
784 unsigned nfmt,
785 unsigned offen,
786 unsigned idxen,
787 unsigned glc,
788 unsigned slc,
789 unsigned tfe)
790 {
791 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
792 LLVMValueRef args[] = {
793 rsrc,
794 vdata,
795 LLVMConstInt(ctx->i32, num_channels, 0),
796 vaddr,
797 soffset,
798 LLVMConstInt(ctx->i32, inst_offset, 0),
799 LLVMConstInt(ctx->i32, dfmt, 0),
800 LLVMConstInt(ctx->i32, nfmt, 0),
801 LLVMConstInt(ctx->i32, offen, 0),
802 LLVMConstInt(ctx->i32, idxen, 0),
803 LLVMConstInt(ctx->i32, glc, 0),
804 LLVMConstInt(ctx->i32, slc, 0),
805 LLVMConstInt(ctx->i32, tfe, 0)
806 };
807
808 /* The instruction offset field has 12 bits */
809 assert(offen || inst_offset < (1 << 12));
810
811 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
812 unsigned func = CLAMP(num_channels, 1, 3) - 1;
813 const char *types[] = {"i32", "v2i32", "v4i32"};
814 char name[256];
815 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
816
817 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
818 args, ARRAY_SIZE(args), 0);
819 }
820
821 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
822 LLVMValueRef rsrc,
823 LLVMValueRef vdata,
824 unsigned num_channels,
825 LLVMValueRef vaddr,
826 LLVMValueRef soffset,
827 unsigned inst_offset)
828 {
829 static unsigned dfmt[] = {
830 V_008F0C_BUF_DATA_FORMAT_32,
831 V_008F0C_BUF_DATA_FORMAT_32_32,
832 V_008F0C_BUF_DATA_FORMAT_32_32_32,
833 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
834 };
835 assert(num_channels >= 1 && num_channels <= 4);
836
837 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
838 inst_offset, dfmt[num_channels-1],
839 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
840 }
841
842 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
843 LLVMValueRef rsrc,
844 int num_channels,
845 LLVMValueRef vindex,
846 LLVMValueRef voffset,
847 LLVMValueRef soffset,
848 unsigned inst_offset,
849 unsigned glc,
850 unsigned slc)
851 {
852 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
853 unsigned func = CLAMP(num_channels, 1, 3) - 1;
854
855 if (HAVE_LLVM >= 0x309) {
856 LLVMValueRef args[] = {
857 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
858 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
859 LLVMConstInt(ctx->i32, inst_offset, 0),
860 LLVMConstInt(ctx->i1, glc, 0),
861 LLVMConstInt(ctx->i1, slc, 0)
862 };
863
864 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
865 ctx->v4f32};
866 const char *type_names[] = {"f32", "v2f32", "v4f32"};
867 char name[256];
868
869 if (voffset) {
870 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
871 "");
872 }
873
874 if (soffset) {
875 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
876 "");
877 }
878
879 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
880 type_names[func]);
881
882 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
883 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
884 } else {
885 LLVMValueRef args[] = {
886 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
887 voffset ? voffset : vindex,
888 soffset,
889 LLVMConstInt(ctx->i32, inst_offset, 0),
890 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
891 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
892 LLVMConstInt(ctx->i32, glc, 0),
893 LLVMConstInt(ctx->i32, slc, 0),
894 LLVMConstInt(ctx->i32, 0, 0), // TFE
895 };
896
897 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
898 ctx->v4i32};
899 const char *type_names[] = {"i32", "v2i32", "v4i32"};
900 const char *arg_type = "i32";
901 char name[256];
902
903 if (voffset && vindex) {
904 LLVMValueRef vaddr[] = {vindex, voffset};
905
906 arg_type = "v2i32";
907 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
908 }
909
910 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
911 type_names[func], arg_type);
912
913 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
914 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
915 }
916 }
917
918 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
919 enum tgsi_opcode_type type, unsigned swizzle,
920 LLVMValueRef buffer, LLVMValueRef offset,
921 LLVMValueRef base)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 struct gallivm_state *gallivm = bld_base->base.gallivm;
925 LLVMValueRef value, value2;
926 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
927 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
928
929 if (swizzle == ~0) {
930 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
931 0, 1, 0);
932
933 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
934 }
935
936 if (!tgsi_type_is_64bit(type)) {
937 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
938 0, 1, 0);
939
940 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
941 return LLVMBuildExtractElement(gallivm->builder, value,
942 lp_build_const_int32(gallivm, swizzle), "");
943 }
944
945 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
946 swizzle * 4, 1, 0);
947
948 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
949 swizzle * 4 + 4, 1, 0);
950
951 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
952 }
953
954 /**
955 * Load from LDS.
956 *
957 * \param type output value type
958 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
959 * \param dw_addr address in dwords
960 */
961 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
962 enum tgsi_opcode_type type, unsigned swizzle,
963 LLVMValueRef dw_addr)
964 {
965 struct si_shader_context *ctx = si_shader_context(bld_base);
966 struct gallivm_state *gallivm = bld_base->base.gallivm;
967 LLVMValueRef value;
968
969 if (swizzle == ~0) {
970 LLVMValueRef values[TGSI_NUM_CHANNELS];
971
972 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
973 values[chan] = lds_load(bld_base, type, chan, dw_addr);
974
975 return lp_build_gather_values(bld_base->base.gallivm, values,
976 TGSI_NUM_CHANNELS);
977 }
978
979 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
980 lp_build_const_int32(gallivm, swizzle));
981
982 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
983 if (tgsi_type_is_64bit(type)) {
984 LLVMValueRef value2;
985 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
986 lp_build_const_int32(gallivm, swizzle + 1));
987 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
988 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
989 }
990
991 return LLVMBuildBitCast(gallivm->builder, value,
992 tgsi2llvmtype(bld_base, type), "");
993 }
994
995 /**
996 * Store to LDS.
997 *
998 * \param swizzle offset (typically 0..3)
999 * \param dw_addr address in dwords
1000 * \param value value to store
1001 */
1002 static void lds_store(struct lp_build_tgsi_context *bld_base,
1003 unsigned swizzle, LLVMValueRef dw_addr,
1004 LLVMValueRef value)
1005 {
1006 struct si_shader_context *ctx = si_shader_context(bld_base);
1007 struct gallivm_state *gallivm = bld_base->base.gallivm;
1008
1009 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1010 lp_build_const_int32(gallivm, swizzle));
1011
1012 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1013 build_indexed_store(ctx, ctx->lds,
1014 dw_addr, value);
1015 }
1016
1017 static LLVMValueRef fetch_input_tcs(
1018 struct lp_build_tgsi_context *bld_base,
1019 const struct tgsi_full_src_register *reg,
1020 enum tgsi_opcode_type type, unsigned swizzle)
1021 {
1022 struct si_shader_context *ctx = si_shader_context(bld_base);
1023 LLVMValueRef dw_addr, stride;
1024
1025 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1026 dw_addr = get_tcs_in_current_patch_offset(ctx);
1027 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1028
1029 return lds_load(bld_base, type, swizzle, dw_addr);
1030 }
1031
1032 static LLVMValueRef fetch_output_tcs(
1033 struct lp_build_tgsi_context *bld_base,
1034 const struct tgsi_full_src_register *reg,
1035 enum tgsi_opcode_type type, unsigned swizzle)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 LLVMValueRef dw_addr, stride;
1039
1040 if (reg->Register.Dimension) {
1041 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1042 dw_addr = get_tcs_out_current_patch_offset(ctx);
1043 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1044 } else {
1045 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1046 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1047 }
1048
1049 return lds_load(bld_base, type, swizzle, dw_addr);
1050 }
1051
1052 static LLVMValueRef fetch_input_tes(
1053 struct lp_build_tgsi_context *bld_base,
1054 const struct tgsi_full_src_register *reg,
1055 enum tgsi_opcode_type type, unsigned swizzle)
1056 {
1057 struct si_shader_context *ctx = si_shader_context(bld_base);
1058 struct gallivm_state *gallivm = bld_base->base.gallivm;
1059 LLVMValueRef rw_buffers, buffer, base, addr;
1060
1061 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1062 SI_PARAM_RW_BUFFERS);
1063 buffer = build_indexed_load_const(ctx, rw_buffers,
1064 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1065
1066 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1067 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1068
1069 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1070 }
1071
1072 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1073 const struct tgsi_full_instruction *inst,
1074 const struct tgsi_opcode_info *info,
1075 LLVMValueRef dst[4])
1076 {
1077 struct si_shader_context *ctx = si_shader_context(bld_base);
1078 struct gallivm_state *gallivm = bld_base->base.gallivm;
1079 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1080 unsigned chan_index;
1081 LLVMValueRef dw_addr, stride;
1082 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1083 LLVMValueRef values[4];
1084
1085 /* Only handle per-patch and per-vertex outputs here.
1086 * Vectors will be lowered to scalars and this function will be called again.
1087 */
1088 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1089 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1090 radeon_llvm_emit_store(bld_base, inst, info, dst);
1091 return;
1092 }
1093
1094 if (reg->Register.Dimension) {
1095 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1096 dw_addr = get_tcs_out_current_patch_offset(ctx);
1097 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1098 } else {
1099 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1100 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1101 }
1102
1103 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1104 SI_PARAM_RW_BUFFERS);
1105 buffer = build_indexed_load_const(ctx, rw_buffers,
1106 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1107
1108 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1109 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1110
1111
1112 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1113 LLVMValueRef value = dst[chan_index];
1114
1115 if (inst->Instruction.Saturate)
1116 value = radeon_llvm_saturate(bld_base, value);
1117
1118 lds_store(bld_base, chan_index, dw_addr, value);
1119
1120 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1121 values[chan_index] = value;
1122
1123 if (inst->Dst[0].Register.WriteMask != 0xF) {
1124 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1125 buf_addr, base,
1126 4 * chan_index);
1127 }
1128 }
1129
1130 if (inst->Dst[0].Register.WriteMask == 0xF) {
1131 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1132 values, 4);
1133 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1134 base, 0);
1135 }
1136 }
1137
1138 static LLVMValueRef fetch_input_gs(
1139 struct lp_build_tgsi_context *bld_base,
1140 const struct tgsi_full_src_register *reg,
1141 enum tgsi_opcode_type type,
1142 unsigned swizzle)
1143 {
1144 struct lp_build_context *base = &bld_base->base;
1145 struct si_shader_context *ctx = si_shader_context(bld_base);
1146 struct si_shader *shader = ctx->shader;
1147 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1148 struct gallivm_state *gallivm = base->gallivm;
1149 LLVMValueRef vtx_offset;
1150 LLVMValueRef args[9];
1151 unsigned vtx_offset_param;
1152 struct tgsi_shader_info *info = &shader->selector->info;
1153 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1154 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1155 unsigned param;
1156 LLVMValueRef value;
1157
1158 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1159 return get_primitive_id(bld_base, swizzle);
1160
1161 if (!reg->Register.Dimension)
1162 return NULL;
1163
1164 if (swizzle == ~0) {
1165 LLVMValueRef values[TGSI_NUM_CHANNELS];
1166 unsigned chan;
1167 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1168 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1169 }
1170 return lp_build_gather_values(bld_base->base.gallivm, values,
1171 TGSI_NUM_CHANNELS);
1172 }
1173
1174 /* Get the vertex offset parameter */
1175 vtx_offset_param = reg->Dimension.Index;
1176 if (vtx_offset_param < 2) {
1177 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1178 } else {
1179 assert(vtx_offset_param < 6);
1180 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1181 }
1182 vtx_offset = lp_build_mul_imm(uint,
1183 LLVMGetParam(ctx->radeon_bld.main_fn,
1184 vtx_offset_param),
1185 4);
1186
1187 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1188 args[0] = ctx->esgs_ring;
1189 args[1] = vtx_offset;
1190 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1191 args[3] = uint->zero;
1192 args[4] = uint->one; /* OFFEN */
1193 args[5] = uint->zero; /* IDXEN */
1194 args[6] = uint->one; /* GLC */
1195 args[7] = uint->zero; /* SLC */
1196 args[8] = uint->zero; /* TFE */
1197
1198 value = lp_build_intrinsic(gallivm->builder,
1199 "llvm.SI.buffer.load.dword.i32.i32",
1200 ctx->i32, args, 9,
1201 LLVMReadOnlyAttribute);
1202 if (tgsi_type_is_64bit(type)) {
1203 LLVMValueRef value2;
1204 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1205 value2 = lp_build_intrinsic(gallivm->builder,
1206 "llvm.SI.buffer.load.dword.i32.i32",
1207 ctx->i32, args, 9,
1208 LLVMReadOnlyAttribute);
1209 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1210 value, value2);
1211 }
1212 return LLVMBuildBitCast(gallivm->builder,
1213 value,
1214 tgsi2llvmtype(bld_base, type), "");
1215 }
1216
1217 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1218 {
1219 switch (interpolate) {
1220 case TGSI_INTERPOLATE_CONSTANT:
1221 return 0;
1222
1223 case TGSI_INTERPOLATE_LINEAR:
1224 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1225 return SI_PARAM_LINEAR_SAMPLE;
1226 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1227 return SI_PARAM_LINEAR_CENTROID;
1228 else
1229 return SI_PARAM_LINEAR_CENTER;
1230 break;
1231 case TGSI_INTERPOLATE_COLOR:
1232 case TGSI_INTERPOLATE_PERSPECTIVE:
1233 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1234 return SI_PARAM_PERSP_SAMPLE;
1235 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1236 return SI_PARAM_PERSP_CENTROID;
1237 else
1238 return SI_PARAM_PERSP_CENTER;
1239 break;
1240 default:
1241 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1242 return -1;
1243 }
1244 }
1245
1246 /* This shouldn't be used by explicit INTERP opcodes. */
1247 static unsigned select_interp_param(struct si_shader_context *ctx,
1248 unsigned param)
1249 {
1250 if (!ctx->is_monolithic)
1251 return param;
1252
1253 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1254 switch (param) {
1255 case SI_PARAM_PERSP_CENTROID:
1256 case SI_PARAM_PERSP_CENTER:
1257 return SI_PARAM_PERSP_SAMPLE;
1258 }
1259 }
1260 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1261 switch (param) {
1262 case SI_PARAM_LINEAR_CENTROID:
1263 case SI_PARAM_LINEAR_CENTER:
1264 return SI_PARAM_LINEAR_SAMPLE;
1265 }
1266 }
1267 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1268 switch (param) {
1269 case SI_PARAM_PERSP_CENTROID:
1270 case SI_PARAM_PERSP_SAMPLE:
1271 return SI_PARAM_PERSP_CENTER;
1272 }
1273 }
1274 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1275 switch (param) {
1276 case SI_PARAM_LINEAR_CENTROID:
1277 case SI_PARAM_LINEAR_SAMPLE:
1278 return SI_PARAM_LINEAR_CENTER;
1279 }
1280 }
1281
1282 return param;
1283 }
1284
1285 /**
1286 * Interpolate a fragment shader input.
1287 *
1288 * @param ctx context
1289 * @param input_index index of the input in hardware
1290 * @param semantic_name TGSI_SEMANTIC_*
1291 * @param semantic_index semantic index
1292 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1293 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1294 * @param interp_param interpolation weights (i,j)
1295 * @param prim_mask SI_PARAM_PRIM_MASK
1296 * @param face SI_PARAM_FRONT_FACE
1297 * @param result the return value (4 components)
1298 */
1299 static void interp_fs_input(struct si_shader_context *ctx,
1300 unsigned input_index,
1301 unsigned semantic_name,
1302 unsigned semantic_index,
1303 unsigned num_interp_inputs,
1304 unsigned colors_read_mask,
1305 LLVMValueRef interp_param,
1306 LLVMValueRef prim_mask,
1307 LLVMValueRef face,
1308 LLVMValueRef result[4])
1309 {
1310 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1311 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1312 struct gallivm_state *gallivm = base->gallivm;
1313 const char *intr_name;
1314 LLVMValueRef attr_number;
1315
1316 unsigned chan;
1317
1318 attr_number = lp_build_const_int32(gallivm, input_index);
1319
1320 /* fs.constant returns the param from the middle vertex, so it's not
1321 * really useful for flat shading. It's meant to be used for custom
1322 * interpolation (but the intrinsic can't fetch from the other two
1323 * vertices).
1324 *
1325 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1326 * to do the right thing. The only reason we use fs.constant is that
1327 * fs.interp cannot be used on integers, because they can be equal
1328 * to NaN.
1329 */
1330 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1331
1332 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1333 ctx->shader->key.ps.prolog.color_two_side) {
1334 LLVMValueRef args[4];
1335 LLVMValueRef is_face_positive;
1336 LLVMValueRef back_attr_number;
1337
1338 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1339 * otherwise it's at offset "num_inputs".
1340 */
1341 unsigned back_attr_offset = num_interp_inputs;
1342 if (semantic_index == 1 && colors_read_mask & 0xf)
1343 back_attr_offset += 1;
1344
1345 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1346
1347 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1348 face, uint->zero, "");
1349
1350 args[2] = prim_mask;
1351 args[3] = interp_param;
1352 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1353 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1354 LLVMValueRef front, back;
1355
1356 args[0] = llvm_chan;
1357 args[1] = attr_number;
1358 front = lp_build_intrinsic(gallivm->builder, intr_name,
1359 ctx->f32, args, args[3] ? 4 : 3,
1360 LLVMReadNoneAttribute);
1361
1362 args[1] = back_attr_number;
1363 back = lp_build_intrinsic(gallivm->builder, intr_name,
1364 ctx->f32, args, args[3] ? 4 : 3,
1365 LLVMReadNoneAttribute);
1366
1367 result[chan] = LLVMBuildSelect(gallivm->builder,
1368 is_face_positive,
1369 front,
1370 back,
1371 "");
1372 }
1373 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1374 LLVMValueRef args[4];
1375
1376 args[0] = uint->zero;
1377 args[1] = attr_number;
1378 args[2] = prim_mask;
1379 args[3] = interp_param;
1380 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1381 ctx->f32, args, args[3] ? 4 : 3,
1382 LLVMReadNoneAttribute);
1383 result[1] =
1384 result[2] = lp_build_const_float(gallivm, 0.0f);
1385 result[3] = lp_build_const_float(gallivm, 1.0f);
1386 } else {
1387 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1388 LLVMValueRef args[4];
1389 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1390
1391 args[0] = llvm_chan;
1392 args[1] = attr_number;
1393 args[2] = prim_mask;
1394 args[3] = interp_param;
1395 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1396 ctx->f32, args, args[3] ? 4 : 3,
1397 LLVMReadNoneAttribute);
1398 }
1399 }
1400 }
1401
1402 /* LLVMGetParam with bc_optimize resolved. */
1403 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1404 int interp_param_idx)
1405 {
1406 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1407 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1408 LLVMValueRef param = NULL;
1409
1410 /* Handle PRIM_MASK[31] (bc_optimize). */
1411 if (ctx->is_monolithic &&
1412 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1413 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1414 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1415 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1416 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1417 * The hw doesn't compute CENTROID if the whole wave only
1418 * contains fully-covered quads.
1419 */
1420 LLVMValueRef bc_optimize =
1421 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1422 bc_optimize = LLVMBuildLShr(builder,
1423 bc_optimize,
1424 LLVMConstInt(ctx->i32, 31, 0), "");
1425 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1426
1427 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1428 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1429 param = LLVMBuildSelect(builder, bc_optimize,
1430 LLVMGetParam(main_fn,
1431 SI_PARAM_PERSP_CENTER),
1432 LLVMGetParam(main_fn,
1433 SI_PARAM_PERSP_CENTROID),
1434 "");
1435 }
1436 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1437 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1438 param = LLVMBuildSelect(builder, bc_optimize,
1439 LLVMGetParam(main_fn,
1440 SI_PARAM_LINEAR_CENTER),
1441 LLVMGetParam(main_fn,
1442 SI_PARAM_LINEAR_CENTROID),
1443 "");
1444 }
1445 }
1446
1447 if (!param)
1448 param = LLVMGetParam(main_fn, interp_param_idx);
1449 return param;
1450 }
1451
1452 static void declare_input_fs(
1453 struct radeon_llvm_context *radeon_bld,
1454 unsigned input_index,
1455 const struct tgsi_full_declaration *decl,
1456 LLVMValueRef out[4])
1457 {
1458 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1459 struct si_shader_context *ctx =
1460 si_shader_context(&radeon_bld->soa.bld_base);
1461 struct si_shader *shader = ctx->shader;
1462 LLVMValueRef main_fn = radeon_bld->main_fn;
1463 LLVMValueRef interp_param = NULL;
1464 int interp_param_idx;
1465
1466 /* Get colors from input VGPRs (set by the prolog). */
1467 if (!ctx->is_monolithic &&
1468 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1469 unsigned i = decl->Semantic.Index;
1470 unsigned colors_read = shader->selector->info.colors_read;
1471 unsigned mask = colors_read >> (i * 4);
1472 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1473 (i ? util_bitcount(colors_read & 0xf) : 0);
1474
1475 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1476 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1477 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1478 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1479 return;
1480 }
1481
1482 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1483 decl->Interp.Location);
1484 if (interp_param_idx == -1)
1485 return;
1486 else if (interp_param_idx) {
1487 interp_param_idx = select_interp_param(ctx,
1488 interp_param_idx);
1489 interp_param = get_interp_param(ctx, interp_param_idx);
1490 }
1491
1492 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1493 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1494 ctx->shader->key.ps.prolog.flatshade_colors)
1495 interp_param = NULL; /* load the constant color */
1496
1497 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1498 decl->Semantic.Index, shader->selector->info.num_inputs,
1499 shader->selector->info.colors_read, interp_param,
1500 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1501 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1502 &out[0]);
1503 }
1504
1505 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1506 {
1507 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1508 SI_PARAM_ANCILLARY, 8, 4);
1509 }
1510
1511 /**
1512 * Set range metadata on an instruction. This can only be used on load and
1513 * call instructions. If you know an instruction can only produce the values
1514 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1515 * \p lo is the minimum value inclusive.
1516 * \p hi is the maximum value exclusive.
1517 */
1518 static void set_range_metadata(struct si_shader_context *ctx,
1519 LLVMValueRef value, unsigned lo, unsigned hi)
1520 {
1521 LLVMValueRef range_md, md_args[2];
1522 LLVMTypeRef type = LLVMTypeOf(value);
1523 LLVMContextRef context = LLVMGetTypeContext(type);
1524
1525 md_args[0] = LLVMConstInt(type, lo, false);
1526 md_args[1] = LLVMConstInt(type, hi, false);
1527 range_md = LLVMMDNodeInContext(context, md_args, 2);
1528 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1529 }
1530
1531 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1532 {
1533 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1534 LLVMValueRef tid;
1535
1536 if (HAVE_LLVM < 0x0308) {
1537 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1538 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1539 } else {
1540 LLVMValueRef tid_args[2];
1541 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1542 tid_args[1] = lp_build_const_int32(gallivm, 0);
1543 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1544 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1545 tid_args, 2, LLVMReadNoneAttribute);
1546
1547 tid = lp_build_intrinsic(gallivm->builder,
1548 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1549 tid_args, 2, LLVMReadNoneAttribute);
1550 }
1551 set_range_metadata(ctx, tid, 0, 64);
1552 return tid;
1553 }
1554
1555 /**
1556 * Load a dword from a constant buffer.
1557 */
1558 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1559 LLVMValueRef resource,
1560 LLVMValueRef offset)
1561 {
1562 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1563 LLVMValueRef args[2] = {resource, offset};
1564
1565 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1566 LLVMReadNoneAttribute);
1567 }
1568
1569 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1570 {
1571 struct si_shader_context *ctx =
1572 si_shader_context(&radeon_bld->soa.bld_base);
1573 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1574 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1575 LLVMBuilderRef builder = gallivm->builder;
1576 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1577 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1578 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1579
1580 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1581 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1582 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1583
1584 LLVMValueRef pos[4] = {
1585 buffer_load_const(ctx, resource, offset0),
1586 buffer_load_const(ctx, resource, offset1),
1587 lp_build_const_float(gallivm, 0),
1588 lp_build_const_float(gallivm, 0)
1589 };
1590
1591 return lp_build_gather_values(gallivm, pos, 4);
1592 }
1593
1594 static void declare_system_value(
1595 struct radeon_llvm_context *radeon_bld,
1596 unsigned index,
1597 const struct tgsi_full_declaration *decl)
1598 {
1599 struct si_shader_context *ctx =
1600 si_shader_context(&radeon_bld->soa.bld_base);
1601 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1602 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1603 LLVMValueRef value = 0;
1604
1605 switch (decl->Semantic.Name) {
1606 case TGSI_SEMANTIC_INSTANCEID:
1607 value = LLVMGetParam(radeon_bld->main_fn,
1608 ctx->param_instance_id);
1609 break;
1610
1611 case TGSI_SEMANTIC_VERTEXID:
1612 value = LLVMBuildAdd(gallivm->builder,
1613 LLVMGetParam(radeon_bld->main_fn,
1614 ctx->param_vertex_id),
1615 LLVMGetParam(radeon_bld->main_fn,
1616 SI_PARAM_BASE_VERTEX), "");
1617 break;
1618
1619 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1620 value = LLVMGetParam(radeon_bld->main_fn,
1621 ctx->param_vertex_id);
1622 break;
1623
1624 case TGSI_SEMANTIC_BASEVERTEX:
1625 value = LLVMGetParam(radeon_bld->main_fn,
1626 SI_PARAM_BASE_VERTEX);
1627 break;
1628
1629 case TGSI_SEMANTIC_BASEINSTANCE:
1630 value = LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_START_INSTANCE);
1632 break;
1633
1634 case TGSI_SEMANTIC_DRAWID:
1635 value = LLVMGetParam(radeon_bld->main_fn,
1636 SI_PARAM_DRAWID);
1637 break;
1638
1639 case TGSI_SEMANTIC_INVOCATIONID:
1640 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1641 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1642 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1643 value = LLVMGetParam(radeon_bld->main_fn,
1644 SI_PARAM_GS_INSTANCE_ID);
1645 else
1646 assert(!"INVOCATIONID not implemented");
1647 break;
1648
1649 case TGSI_SEMANTIC_POSITION:
1650 {
1651 LLVMValueRef pos[4] = {
1652 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1653 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1654 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1655 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1656 LLVMGetParam(radeon_bld->main_fn,
1657 SI_PARAM_POS_W_FLOAT)),
1658 };
1659 value = lp_build_gather_values(gallivm, pos, 4);
1660 break;
1661 }
1662
1663 case TGSI_SEMANTIC_FACE:
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1665 break;
1666
1667 case TGSI_SEMANTIC_SAMPLEID:
1668 value = get_sample_id(radeon_bld);
1669 break;
1670
1671 case TGSI_SEMANTIC_SAMPLEPOS: {
1672 LLVMValueRef pos[4] = {
1673 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1674 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1675 lp_build_const_float(gallivm, 0),
1676 lp_build_const_float(gallivm, 0)
1677 };
1678 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1679 TGSI_OPCODE_FRC, pos[0]);
1680 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1681 TGSI_OPCODE_FRC, pos[1]);
1682 value = lp_build_gather_values(gallivm, pos, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_SAMPLEMASK:
1687 /* This can only occur with the OpenGL Core profile, which
1688 * doesn't support smoothing.
1689 */
1690 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1691 break;
1692
1693 case TGSI_SEMANTIC_TESSCOORD:
1694 {
1695 LLVMValueRef coord[4] = {
1696 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1697 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1698 bld->zero,
1699 bld->zero
1700 };
1701
1702 /* For triangles, the vector should be (u, v, 1-u-v). */
1703 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1704 PIPE_PRIM_TRIANGLES)
1705 coord[2] = lp_build_sub(bld, bld->one,
1706 lp_build_add(bld, coord[0], coord[1]));
1707
1708 value = lp_build_gather_values(gallivm, coord, 4);
1709 break;
1710 }
1711
1712 case TGSI_SEMANTIC_VERTICESIN:
1713 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1714 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1715 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1716 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1717 else
1718 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1719 break;
1720
1721 case TGSI_SEMANTIC_TESSINNER:
1722 case TGSI_SEMANTIC_TESSOUTER:
1723 {
1724 LLVMValueRef rw_buffers, buffer, base, addr;
1725 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1726
1727 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1728 SI_PARAM_RW_BUFFERS);
1729 buffer = build_indexed_load_const(ctx, rw_buffers,
1730 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1731
1732 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1733 addr = get_tcs_tes_buffer_address(ctx, NULL,
1734 lp_build_const_int32(gallivm, param));
1735
1736 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1737 ~0, buffer, base, addr);
1738
1739 break;
1740 }
1741
1742 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1743 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1744 {
1745 LLVMValueRef buf, slot, val[4];
1746 int i, offset;
1747
1748 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1749 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1750 buf = build_indexed_load_const(ctx, buf, slot);
1751 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1752
1753 for (i = 0; i < 4; i++)
1754 val[i] = buffer_load_const(ctx, buf,
1755 lp_build_const_int32(gallivm, (offset + i) * 4));
1756 value = lp_build_gather_values(gallivm, val, 4);
1757 break;
1758 }
1759
1760 case TGSI_SEMANTIC_PRIMID:
1761 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1762 break;
1763
1764 case TGSI_SEMANTIC_GRID_SIZE:
1765 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1766 break;
1767
1768 case TGSI_SEMANTIC_BLOCK_SIZE:
1769 {
1770 LLVMValueRef values[3];
1771 unsigned i;
1772 unsigned *properties = ctx->shader->selector->info.properties;
1773
1774 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1775 unsigned sizes[3] = {
1776 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1777 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1778 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1779 };
1780
1781 for (i = 0; i < 3; ++i)
1782 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1783
1784 value = lp_build_gather_values(gallivm, values, 3);
1785 } else {
1786 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1787 }
1788 break;
1789 }
1790
1791 case TGSI_SEMANTIC_BLOCK_ID:
1792 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1793 break;
1794
1795 case TGSI_SEMANTIC_THREAD_ID:
1796 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1797 break;
1798
1799 #if HAVE_LLVM >= 0x0309
1800 case TGSI_SEMANTIC_HELPER_INVOCATION:
1801 value = lp_build_intrinsic(gallivm->builder,
1802 "llvm.amdgcn.ps.live",
1803 ctx->i1, NULL, 0,
1804 LLVMReadNoneAttribute);
1805 value = LLVMBuildNot(gallivm->builder, value, "");
1806 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1807 break;
1808 #endif
1809
1810 default:
1811 assert(!"unknown system value");
1812 return;
1813 }
1814
1815 radeon_bld->system_values[index] = value;
1816 }
1817
1818 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1819 const struct tgsi_full_declaration *decl)
1820 {
1821 struct si_shader_context *ctx =
1822 si_shader_context(&radeon_bld->soa.bld_base);
1823 struct si_shader_selector *sel = ctx->shader->selector;
1824 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1825
1826 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1827 LLVMValueRef var;
1828
1829 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1830 assert(decl->Range.First == decl->Range.Last);
1831 assert(!ctx->shared_memory);
1832
1833 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1834 LLVMArrayType(ctx->i8, sel->local_size),
1835 "compute_lds",
1836 LOCAL_ADDR_SPACE);
1837 LLVMSetAlignment(var, 4);
1838
1839 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1840 }
1841
1842 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1843 {
1844 LLVMValueRef list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
1845 SI_PARAM_CONST_BUFFERS);
1846
1847 return build_indexed_load_const(ctx, list_ptr,
1848 LLVMConstInt(ctx->i32, i, 0));
1849 }
1850
1851 static LLVMValueRef fetch_constant(
1852 struct lp_build_tgsi_context *bld_base,
1853 const struct tgsi_full_src_register *reg,
1854 enum tgsi_opcode_type type,
1855 unsigned swizzle)
1856 {
1857 struct si_shader_context *ctx = si_shader_context(bld_base);
1858 struct lp_build_context *base = &bld_base->base;
1859 const struct tgsi_ind_register *ireg = &reg->Indirect;
1860 unsigned buf, idx;
1861
1862 LLVMValueRef addr, bufp;
1863 LLVMValueRef result;
1864
1865 if (swizzle == LP_CHAN_ALL) {
1866 unsigned chan;
1867 LLVMValueRef values[4];
1868 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1869 values[chan] = fetch_constant(bld_base, reg, type, chan);
1870
1871 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1872 }
1873
1874 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1875 idx = reg->Register.Index * 4 + swizzle;
1876
1877 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1878 LLVMValueRef c0, c1, desc;
1879
1880 desc = load_const_buffer_desc(ctx, buf);
1881 c0 = buffer_load_const(ctx, desc,
1882 LLVMConstInt(ctx->i32, idx * 4, 0));
1883
1884 if (!tgsi_type_is_64bit(type))
1885 return bitcast(bld_base, type, c0);
1886 else {
1887 c1 = buffer_load_const(ctx, desc,
1888 LLVMConstInt(ctx->i32,
1889 (idx + 1) * 4, 0));
1890 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1891 c0, c1);
1892 }
1893 }
1894
1895 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1896 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1897 LLVMValueRef index;
1898 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1899 reg->Dimension.Index,
1900 SI_NUM_CONST_BUFFERS);
1901 bufp = build_indexed_load_const(ctx, ptr, index);
1902 } else
1903 bufp = load_const_buffer_desc(ctx, buf);
1904
1905 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1906 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1907 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1908 addr = lp_build_add(&bld_base->uint_bld, addr,
1909 lp_build_const_int32(base->gallivm, idx * 4));
1910
1911 result = buffer_load_const(ctx, bufp, addr);
1912
1913 if (!tgsi_type_is_64bit(type))
1914 result = bitcast(bld_base, type, result);
1915 else {
1916 LLVMValueRef addr2, result2;
1917 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1918 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1919 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1920 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1921 lp_build_const_int32(base->gallivm, idx * 4));
1922
1923 result2 = buffer_load_const(ctx, bufp, addr2);
1924
1925 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1926 result, result2);
1927 }
1928 return result;
1929 }
1930
1931 /* Upper 16 bits must be zero. */
1932 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1933 LLVMValueRef val[2])
1934 {
1935 return LLVMBuildOr(gallivm->builder, val[0],
1936 LLVMBuildShl(gallivm->builder, val[1],
1937 lp_build_const_int32(gallivm, 16),
1938 ""), "");
1939 }
1940
1941 /* Upper 16 bits are ignored and will be dropped. */
1942 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1943 LLVMValueRef val[2])
1944 {
1945 LLVMValueRef v[2] = {
1946 LLVMBuildAnd(gallivm->builder, val[0],
1947 lp_build_const_int32(gallivm, 0xffff), ""),
1948 val[1],
1949 };
1950 return si_llvm_pack_two_int16(gallivm, v);
1951 }
1952
1953 /* Initialize arguments for the shader export intrinsic */
1954 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1955 LLVMValueRef *values,
1956 unsigned target,
1957 LLVMValueRef *args)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960 struct lp_build_context *uint =
1961 &ctx->radeon_bld.soa.bld_base.uint_bld;
1962 struct lp_build_context *base = &bld_base->base;
1963 struct gallivm_state *gallivm = base->gallivm;
1964 LLVMBuilderRef builder = base->gallivm->builder;
1965 LLVMValueRef val[4];
1966 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1967 unsigned chan;
1968 bool is_int8;
1969
1970 /* Default is 0xf. Adjusted below depending on the format. */
1971 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1972
1973 /* Specify whether the EXEC mask represents the valid mask */
1974 args[1] = uint->zero;
1975
1976 /* Specify whether this is the last export */
1977 args[2] = uint->zero;
1978
1979 /* Specify the target we are exporting */
1980 args[3] = lp_build_const_int32(base->gallivm, target);
1981
1982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1983 const union si_shader_key *key = &ctx->shader->key;
1984 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1985 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1986
1987 assert(cbuf >= 0 && cbuf < 8);
1988 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1989 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1990 }
1991
1992 args[4] = uint->zero; /* COMPR flag */
1993 args[5] = base->undef;
1994 args[6] = base->undef;
1995 args[7] = base->undef;
1996 args[8] = base->undef;
1997
1998 switch (spi_shader_col_format) {
1999 case V_028714_SPI_SHADER_ZERO:
2000 args[0] = uint->zero; /* writemask */
2001 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2002 break;
2003
2004 case V_028714_SPI_SHADER_32_R:
2005 args[0] = uint->one; /* writemask */
2006 args[5] = values[0];
2007 break;
2008
2009 case V_028714_SPI_SHADER_32_GR:
2010 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2011 args[5] = values[0];
2012 args[6] = values[1];
2013 break;
2014
2015 case V_028714_SPI_SHADER_32_AR:
2016 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2017 args[5] = values[0];
2018 args[8] = values[3];
2019 break;
2020
2021 case V_028714_SPI_SHADER_FP16_ABGR:
2022 args[4] = uint->one; /* COMPR flag */
2023
2024 for (chan = 0; chan < 2; chan++) {
2025 LLVMValueRef pack_args[2] = {
2026 values[2 * chan],
2027 values[2 * chan + 1]
2028 };
2029 LLVMValueRef packed;
2030
2031 packed = lp_build_intrinsic(base->gallivm->builder,
2032 "llvm.SI.packf16",
2033 ctx->i32, pack_args, 2,
2034 LLVMReadNoneAttribute);
2035 args[chan + 5] =
2036 LLVMBuildBitCast(base->gallivm->builder,
2037 packed, ctx->f32, "");
2038 }
2039 break;
2040
2041 case V_028714_SPI_SHADER_UNORM16_ABGR:
2042 for (chan = 0; chan < 4; chan++) {
2043 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2044 val[chan] = LLVMBuildFMul(builder, val[chan],
2045 lp_build_const_float(gallivm, 65535), "");
2046 val[chan] = LLVMBuildFAdd(builder, val[chan],
2047 lp_build_const_float(gallivm, 0.5), "");
2048 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2049 ctx->i32, "");
2050 }
2051
2052 args[4] = uint->one; /* COMPR flag */
2053 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2054 si_llvm_pack_two_int16(gallivm, val));
2055 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2056 si_llvm_pack_two_int16(gallivm, val+2));
2057 break;
2058
2059 case V_028714_SPI_SHADER_SNORM16_ABGR:
2060 for (chan = 0; chan < 4; chan++) {
2061 /* Clamp between [-1, 1]. */
2062 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2063 values[chan],
2064 lp_build_const_float(gallivm, 1));
2065 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2066 val[chan],
2067 lp_build_const_float(gallivm, -1));
2068 /* Convert to a signed integer in [-32767, 32767]. */
2069 val[chan] = LLVMBuildFMul(builder, val[chan],
2070 lp_build_const_float(gallivm, 32767), "");
2071 /* If positive, add 0.5, else add -0.5. */
2072 val[chan] = LLVMBuildFAdd(builder, val[chan],
2073 LLVMBuildSelect(builder,
2074 LLVMBuildFCmp(builder, LLVMRealOGE,
2075 val[chan], base->zero, ""),
2076 lp_build_const_float(gallivm, 0.5),
2077 lp_build_const_float(gallivm, -0.5), ""), "");
2078 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2079 }
2080
2081 args[4] = uint->one; /* COMPR flag */
2082 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val));
2084 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2085 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2086 break;
2087
2088 case V_028714_SPI_SHADER_UINT16_ABGR: {
2089 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2090 255 : 65535);
2091 /* Clamp. */
2092 for (chan = 0; chan < 4; chan++) {
2093 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2094 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2095 val[chan], max);
2096 }
2097
2098 args[4] = uint->one; /* COMPR flag */
2099 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2100 si_llvm_pack_two_int16(gallivm, val));
2101 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 si_llvm_pack_two_int16(gallivm, val+2));
2103 break;
2104 }
2105
2106 case V_028714_SPI_SHADER_SINT16_ABGR: {
2107 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2108 127 : 32767);
2109 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2110 -128 : -32768);
2111 /* Clamp. */
2112 for (chan = 0; chan < 4; chan++) {
2113 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2114 val[chan] = lp_build_emit_llvm_binary(bld_base,
2115 TGSI_OPCODE_IMIN,
2116 val[chan], max);
2117 val[chan] = lp_build_emit_llvm_binary(bld_base,
2118 TGSI_OPCODE_IMAX,
2119 val[chan], min);
2120 }
2121
2122 args[4] = uint->one; /* COMPR flag */
2123 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2124 si_llvm_pack_two_int32_as_int16(gallivm, val));
2125 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2126 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2127 break;
2128 }
2129
2130 case V_028714_SPI_SHADER_32_ABGR:
2131 memcpy(&args[5], values, sizeof(values[0]) * 4);
2132 break;
2133 }
2134 }
2135
2136 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2137 LLVMValueRef alpha)
2138 {
2139 struct si_shader_context *ctx = si_shader_context(bld_base);
2140 struct gallivm_state *gallivm = bld_base->base.gallivm;
2141
2142 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2143 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2144 SI_PARAM_ALPHA_REF);
2145
2146 LLVMValueRef alpha_pass =
2147 lp_build_cmp(&bld_base->base,
2148 ctx->shader->key.ps.epilog.alpha_func,
2149 alpha, alpha_ref);
2150 LLVMValueRef arg =
2151 lp_build_select(&bld_base->base,
2152 alpha_pass,
2153 lp_build_const_float(gallivm, 1.0f),
2154 lp_build_const_float(gallivm, -1.0f));
2155
2156 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2157 ctx->voidt, &arg, 1, 0);
2158 } else {
2159 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2160 ctx->voidt, NULL, 0, 0);
2161 }
2162 }
2163
2164 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2165 LLVMValueRef alpha,
2166 unsigned samplemask_param)
2167 {
2168 struct si_shader_context *ctx = si_shader_context(bld_base);
2169 struct gallivm_state *gallivm = bld_base->base.gallivm;
2170 LLVMValueRef coverage;
2171
2172 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2173 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2174 samplemask_param);
2175 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2176
2177 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2178 ctx->i32,
2179 &coverage, 1, LLVMReadNoneAttribute);
2180
2181 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2182 ctx->f32, "");
2183
2184 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2185 lp_build_const_float(gallivm,
2186 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2187
2188 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2189 }
2190
2191 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2192 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2193 {
2194 struct si_shader_context *ctx = si_shader_context(bld_base);
2195 struct lp_build_context *base = &bld_base->base;
2196 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2197 unsigned reg_index;
2198 unsigned chan;
2199 unsigned const_chan;
2200 LLVMValueRef base_elt;
2201 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2202 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2203 SI_VS_CONST_CLIP_PLANES);
2204 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2205
2206 for (reg_index = 0; reg_index < 2; reg_index ++) {
2207 LLVMValueRef *args = pos[2 + reg_index];
2208
2209 args[5] =
2210 args[6] =
2211 args[7] =
2212 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2213
2214 /* Compute dot products of position and user clip plane vectors */
2215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2216 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2217 args[1] = lp_build_const_int32(base->gallivm,
2218 ((reg_index * 4 + chan) * 4 +
2219 const_chan) * 4);
2220 base_elt = buffer_load_const(ctx, const_resource,
2221 args[1]);
2222 args[5 + chan] =
2223 lp_build_add(base, args[5 + chan],
2224 lp_build_mul(base, base_elt,
2225 out_elts[const_chan]));
2226 }
2227 }
2228
2229 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2230 args[1] = uint->zero;
2231 args[2] = uint->zero;
2232 args[3] = lp_build_const_int32(base->gallivm,
2233 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2234 args[4] = uint->zero;
2235 }
2236 }
2237
2238 static void si_dump_streamout(struct pipe_stream_output_info *so)
2239 {
2240 unsigned i;
2241
2242 if (so->num_outputs)
2243 fprintf(stderr, "STREAMOUT\n");
2244
2245 for (i = 0; i < so->num_outputs; i++) {
2246 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2247 so->output[i].start_component;
2248 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2249 i, so->output[i].output_buffer,
2250 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2251 so->output[i].register_index,
2252 mask & 1 ? "x" : "",
2253 mask & 2 ? "y" : "",
2254 mask & 4 ? "z" : "",
2255 mask & 8 ? "w" : "");
2256 }
2257 }
2258
2259 /* On SI, the vertex shader is responsible for writing streamout data
2260 * to buffers. */
2261 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2262 struct si_shader_output_values *outputs,
2263 unsigned noutput)
2264 {
2265 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2266 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2267 LLVMBuilderRef builder = gallivm->builder;
2268 int i, j;
2269 struct lp_build_if_state if_ctx;
2270 LLVMValueRef so_buffers[4];
2271 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2272 SI_PARAM_RW_BUFFERS);
2273
2274 /* Load the descriptors. */
2275 for (i = 0; i < 4; ++i) {
2276 if (ctx->shader->selector->so.stride[i]) {
2277 LLVMValueRef offset = lp_build_const_int32(gallivm,
2278 SI_VS_STREAMOUT_BUF0 + i);
2279
2280 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2281 }
2282 }
2283
2284 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2285 LLVMValueRef so_vtx_count =
2286 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2287
2288 LLVMValueRef tid = get_thread_id(ctx);
2289
2290 /* can_emit = tid < so_vtx_count; */
2291 LLVMValueRef can_emit =
2292 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2293
2294 LLVMValueRef stream_id =
2295 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2296
2297 /* Emit the streamout code conditionally. This actually avoids
2298 * out-of-bounds buffer access. The hw tells us via the SGPR
2299 * (so_vtx_count) which threads are allowed to emit streamout data. */
2300 lp_build_if(&if_ctx, gallivm, can_emit);
2301 {
2302 /* The buffer offset is computed as follows:
2303 * ByteOffset = streamout_offset[buffer_id]*4 +
2304 * (streamout_write_index + thread_id)*stride[buffer_id] +
2305 * attrib_offset
2306 */
2307
2308 LLVMValueRef so_write_index =
2309 LLVMGetParam(ctx->radeon_bld.main_fn,
2310 ctx->param_streamout_write_index);
2311
2312 /* Compute (streamout_write_index + thread_id). */
2313 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2314
2315 /* Compute the write offset for each enabled buffer. */
2316 LLVMValueRef so_write_offset[4] = {};
2317 for (i = 0; i < 4; i++) {
2318 if (!so->stride[i])
2319 continue;
2320
2321 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2322 ctx->param_streamout_offset[i]);
2323 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2324
2325 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2326 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2327 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2328 }
2329
2330 /* Write streamout data. */
2331 for (i = 0; i < so->num_outputs; i++) {
2332 unsigned buf_idx = so->output[i].output_buffer;
2333 unsigned reg = so->output[i].register_index;
2334 unsigned start = so->output[i].start_component;
2335 unsigned num_comps = so->output[i].num_components;
2336 unsigned stream = so->output[i].stream;
2337 LLVMValueRef out[4];
2338 struct lp_build_if_state if_ctx_stream;
2339
2340 assert(num_comps && num_comps <= 4);
2341 if (!num_comps || num_comps > 4)
2342 continue;
2343
2344 if (reg >= noutput)
2345 continue;
2346
2347 /* Load the output as int. */
2348 for (j = 0; j < num_comps; j++) {
2349 out[j] = LLVMBuildBitCast(builder,
2350 outputs[reg].values[start+j],
2351 ctx->i32, "");
2352 }
2353
2354 /* Pack the output. */
2355 LLVMValueRef vdata = NULL;
2356
2357 switch (num_comps) {
2358 case 1: /* as i32 */
2359 vdata = out[0];
2360 break;
2361 case 2: /* as v2i32 */
2362 case 3: /* as v4i32 (aligned to 4) */
2363 case 4: /* as v4i32 */
2364 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2365 for (j = 0; j < num_comps; j++) {
2366 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2367 LLVMConstInt(ctx->i32, j, 0), "");
2368 }
2369 break;
2370 }
2371
2372 LLVMValueRef can_emit_stream =
2373 LLVMBuildICmp(builder, LLVMIntEQ,
2374 stream_id,
2375 lp_build_const_int32(gallivm, stream), "");
2376
2377 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2378 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2379 vdata, num_comps,
2380 so_write_offset[buf_idx],
2381 LLVMConstInt(ctx->i32, 0, 0),
2382 so->output[i].dst_offset*4);
2383 lp_build_endif(&if_ctx_stream);
2384 }
2385 }
2386 lp_build_endif(&if_ctx);
2387 }
2388
2389
2390 /* Generate export instructions for hardware VS shader stage */
2391 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2392 struct si_shader_output_values *outputs,
2393 unsigned noutput)
2394 {
2395 struct si_shader_context *ctx = si_shader_context(bld_base);
2396 struct si_shader *shader = ctx->shader;
2397 struct lp_build_context *base = &bld_base->base;
2398 struct lp_build_context *uint =
2399 &ctx->radeon_bld.soa.bld_base.uint_bld;
2400 LLVMValueRef args[9];
2401 LLVMValueRef pos_args[4][9] = { { 0 } };
2402 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2403 unsigned semantic_name, semantic_index;
2404 unsigned target;
2405 unsigned param_count = 0;
2406 unsigned pos_idx;
2407 int i;
2408
2409 if (outputs && ctx->shader->selector->so.num_outputs) {
2410 si_llvm_emit_streamout(ctx, outputs, noutput);
2411 }
2412
2413 for (i = 0; i < noutput; i++) {
2414 semantic_name = outputs[i].name;
2415 semantic_index = outputs[i].sid;
2416
2417 handle_semantic:
2418 /* Select the correct target */
2419 switch(semantic_name) {
2420 case TGSI_SEMANTIC_PSIZE:
2421 psize_value = outputs[i].values[0];
2422 continue;
2423 case TGSI_SEMANTIC_EDGEFLAG:
2424 edgeflag_value = outputs[i].values[0];
2425 continue;
2426 case TGSI_SEMANTIC_LAYER:
2427 layer_value = outputs[i].values[0];
2428 semantic_name = TGSI_SEMANTIC_GENERIC;
2429 goto handle_semantic;
2430 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2431 viewport_index_value = outputs[i].values[0];
2432 semantic_name = TGSI_SEMANTIC_GENERIC;
2433 goto handle_semantic;
2434 case TGSI_SEMANTIC_POSITION:
2435 target = V_008DFC_SQ_EXP_POS;
2436 break;
2437 case TGSI_SEMANTIC_COLOR:
2438 case TGSI_SEMANTIC_BCOLOR:
2439 target = V_008DFC_SQ_EXP_PARAM + param_count;
2440 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2441 shader->info.vs_output_param_offset[i] = param_count;
2442 param_count++;
2443 break;
2444 case TGSI_SEMANTIC_CLIPDIST:
2445 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2446 break;
2447 case TGSI_SEMANTIC_CLIPVERTEX:
2448 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2449 continue;
2450 case TGSI_SEMANTIC_PRIMID:
2451 case TGSI_SEMANTIC_FOG:
2452 case TGSI_SEMANTIC_TEXCOORD:
2453 case TGSI_SEMANTIC_GENERIC:
2454 target = V_008DFC_SQ_EXP_PARAM + param_count;
2455 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2456 shader->info.vs_output_param_offset[i] = param_count;
2457 param_count++;
2458 break;
2459 default:
2460 target = 0;
2461 fprintf(stderr,
2462 "Warning: SI unhandled vs output type:%d\n",
2463 semantic_name);
2464 }
2465
2466 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2467
2468 if (target >= V_008DFC_SQ_EXP_POS &&
2469 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2470 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2471 args, sizeof(args));
2472 } else {
2473 lp_build_intrinsic(base->gallivm->builder,
2474 "llvm.SI.export", ctx->voidt,
2475 args, 9, 0);
2476 }
2477
2478 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2479 semantic_name = TGSI_SEMANTIC_GENERIC;
2480 goto handle_semantic;
2481 }
2482 }
2483
2484 shader->info.nr_param_exports = param_count;
2485
2486 /* We need to add the position output manually if it's missing. */
2487 if (!pos_args[0][0]) {
2488 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2489 pos_args[0][1] = uint->zero; /* EXEC mask */
2490 pos_args[0][2] = uint->zero; /* last export? */
2491 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2492 pos_args[0][4] = uint->zero; /* COMPR flag */
2493 pos_args[0][5] = base->zero; /* X */
2494 pos_args[0][6] = base->zero; /* Y */
2495 pos_args[0][7] = base->zero; /* Z */
2496 pos_args[0][8] = base->one; /* W */
2497 }
2498
2499 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2500 if (shader->selector->info.writes_psize ||
2501 shader->selector->info.writes_edgeflag ||
2502 shader->selector->info.writes_viewport_index ||
2503 shader->selector->info.writes_layer) {
2504 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2505 shader->selector->info.writes_psize |
2506 (shader->selector->info.writes_edgeflag << 1) |
2507 (shader->selector->info.writes_layer << 2) |
2508 (shader->selector->info.writes_viewport_index << 3));
2509 pos_args[1][1] = uint->zero; /* EXEC mask */
2510 pos_args[1][2] = uint->zero; /* last export? */
2511 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2512 pos_args[1][4] = uint->zero; /* COMPR flag */
2513 pos_args[1][5] = base->zero; /* X */
2514 pos_args[1][6] = base->zero; /* Y */
2515 pos_args[1][7] = base->zero; /* Z */
2516 pos_args[1][8] = base->zero; /* W */
2517
2518 if (shader->selector->info.writes_psize)
2519 pos_args[1][5] = psize_value;
2520
2521 if (shader->selector->info.writes_edgeflag) {
2522 /* The output is a float, but the hw expects an integer
2523 * with the first bit containing the edge flag. */
2524 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2525 edgeflag_value,
2526 ctx->i32, "");
2527 edgeflag_value = lp_build_min(&bld_base->int_bld,
2528 edgeflag_value,
2529 bld_base->int_bld.one);
2530
2531 /* The LLVM intrinsic expects a float. */
2532 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2533 edgeflag_value,
2534 ctx->f32, "");
2535 }
2536
2537 if (shader->selector->info.writes_layer)
2538 pos_args[1][7] = layer_value;
2539
2540 if (shader->selector->info.writes_viewport_index)
2541 pos_args[1][8] = viewport_index_value;
2542 }
2543
2544 for (i = 0; i < 4; i++)
2545 if (pos_args[i][0])
2546 shader->info.nr_pos_exports++;
2547
2548 pos_idx = 0;
2549 for (i = 0; i < 4; i++) {
2550 if (!pos_args[i][0])
2551 continue;
2552
2553 /* Specify the target we are exporting */
2554 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2555
2556 if (pos_idx == shader->info.nr_pos_exports)
2557 /* Specify that this is the last export */
2558 pos_args[i][2] = uint->one;
2559
2560 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2561 ctx->voidt, pos_args[i], 9, 0);
2562 }
2563 }
2564
2565 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2566 {
2567 struct si_shader_context *ctx = si_shader_context(bld_base);
2568 struct gallivm_state *gallivm = bld_base->base.gallivm;
2569 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2570 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2571 uint64_t inputs;
2572
2573 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2574
2575 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2576 buffer = build_indexed_load_const(ctx, rw_buffers,
2577 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2578
2579 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2580
2581 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2582 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2583 lds_vertex_stride, "");
2584 lds_base = get_tcs_in_current_patch_offset(ctx);
2585 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2586
2587 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2588 while (inputs) {
2589 unsigned i = u_bit_scan64(&inputs);
2590
2591 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2592 lp_build_const_int32(gallivm, 4 * i),
2593 "");
2594
2595 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2596 invocation_id,
2597 lp_build_const_int32(gallivm, i));
2598
2599 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2600 lds_ptr);
2601
2602 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2603 buffer_offset, 0);
2604 }
2605 }
2606
2607 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2608 LLVMValueRef rel_patch_id,
2609 LLVMValueRef invocation_id,
2610 LLVMValueRef tcs_out_current_patch_data_offset)
2611 {
2612 struct si_shader_context *ctx = si_shader_context(bld_base);
2613 struct gallivm_state *gallivm = bld_base->base.gallivm;
2614 struct si_shader *shader = ctx->shader;
2615 unsigned tess_inner_index, tess_outer_index;
2616 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2617 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2618 unsigned stride, outer_comps, inner_comps, i;
2619 struct lp_build_if_state if_ctx, inner_if_ctx;
2620
2621 si_llvm_emit_barrier(NULL, bld_base, NULL);
2622
2623 /* Do this only for invocation 0, because the tess levels are per-patch,
2624 * not per-vertex.
2625 *
2626 * This can't jump, because invocation 0 executes this. It should
2627 * at least mask out the loads and stores for other invocations.
2628 */
2629 lp_build_if(&if_ctx, gallivm,
2630 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2631 invocation_id, bld_base->uint_bld.zero, ""));
2632
2633 /* Determine the layout of one tess factor element in the buffer. */
2634 switch (shader->key.tcs.epilog.prim_mode) {
2635 case PIPE_PRIM_LINES:
2636 stride = 2; /* 2 dwords, 1 vec2 store */
2637 outer_comps = 2;
2638 inner_comps = 0;
2639 break;
2640 case PIPE_PRIM_TRIANGLES:
2641 stride = 4; /* 4 dwords, 1 vec4 store */
2642 outer_comps = 3;
2643 inner_comps = 1;
2644 break;
2645 case PIPE_PRIM_QUADS:
2646 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2647 outer_comps = 4;
2648 inner_comps = 2;
2649 break;
2650 default:
2651 assert(0);
2652 return;
2653 }
2654
2655 /* Load tess_inner and tess_outer from LDS.
2656 * Any invocation can write them, so we can't get them from a temporary.
2657 */
2658 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2659 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2660
2661 lds_base = tcs_out_current_patch_data_offset;
2662 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2663 lp_build_const_int32(gallivm,
2664 tess_inner_index * 4), "");
2665 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2666 lp_build_const_int32(gallivm,
2667 tess_outer_index * 4), "");
2668
2669 for (i = 0; i < outer_comps; i++)
2670 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2671 for (i = 0; i < inner_comps; i++)
2672 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2673
2674 /* Convert the outputs to vectors for stores. */
2675 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2676 vec1 = NULL;
2677
2678 if (stride > 4)
2679 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2680
2681 /* Get the buffer. */
2682 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2683 SI_PARAM_RW_BUFFERS);
2684 buffer = build_indexed_load_const(ctx, rw_buffers,
2685 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2686
2687 /* Get the offset. */
2688 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2689 SI_PARAM_TESS_FACTOR_OFFSET);
2690 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2691 lp_build_const_int32(gallivm, 4 * stride), "");
2692
2693 lp_build_if(&inner_if_ctx, gallivm,
2694 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2695 rel_patch_id, bld_base->uint_bld.zero, ""));
2696
2697 /* Store the dynamic HS control word. */
2698 build_tbuffer_store_dwords(ctx, buffer,
2699 lp_build_const_int32(gallivm, 0x80000000),
2700 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2701
2702 lp_build_endif(&inner_if_ctx);
2703
2704 /* Store the tessellation factors. */
2705 build_tbuffer_store_dwords(ctx, buffer, vec0,
2706 MIN2(stride, 4), byteoffset, tf_base, 4);
2707 if (vec1)
2708 build_tbuffer_store_dwords(ctx, buffer, vec1,
2709 stride - 4, byteoffset, tf_base, 20);
2710 lp_build_endif(&if_ctx);
2711 }
2712
2713 /* This only writes the tessellation factor levels. */
2714 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2715 {
2716 struct si_shader_context *ctx = si_shader_context(bld_base);
2717 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2718
2719 rel_patch_id = get_rel_patch_id(ctx);
2720 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2721 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2722
2723 if (!ctx->is_monolithic) {
2724 /* Return epilog parameters from this function. */
2725 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2726 LLVMValueRef ret = ctx->return_value;
2727 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2728 unsigned vgpr;
2729
2730 /* RW_BUFFERS pointer */
2731 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2732 SI_PARAM_RW_BUFFERS);
2733 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2734 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2735 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2736 bld_base->uint_bld.zero, "");
2737 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2738 bld_base->uint_bld.one, "");
2739 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2740 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2741
2742 /* Tess factor buffer soffset is after user SGPRs. */
2743 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2744 SI_PARAM_TESS_FACTOR_OFFSET);
2745 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2746 SI_TCS_NUM_USER_SGPR + 1, "");
2747
2748 /* VGPRs */
2749 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2750 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2751 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2752
2753 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2754 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2755 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2756 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2757 ctx->return_value = ret;
2758 return;
2759 }
2760
2761 si_copy_tcs_inputs(bld_base);
2762 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2763 }
2764
2765 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2766 {
2767 struct si_shader_context *ctx = si_shader_context(bld_base);
2768 struct si_shader *shader = ctx->shader;
2769 struct tgsi_shader_info *info = &shader->selector->info;
2770 struct gallivm_state *gallivm = bld_base->base.gallivm;
2771 unsigned i, chan;
2772 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2773 ctx->param_rel_auto_id);
2774 LLVMValueRef vertex_dw_stride =
2775 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2776 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2777 vertex_dw_stride, "");
2778
2779 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2780 * its inputs from it. */
2781 for (i = 0; i < info->num_outputs; i++) {
2782 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2783 unsigned name = info->output_semantic_name[i];
2784 unsigned index = info->output_semantic_index[i];
2785 int param = si_shader_io_get_unique_index(name, index);
2786 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2787 lp_build_const_int32(gallivm, param * 4), "");
2788
2789 for (chan = 0; chan < 4; chan++) {
2790 lds_store(bld_base, chan, dw_addr,
2791 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2792 }
2793 }
2794 }
2795
2796 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2797 {
2798 struct si_shader_context *ctx = si_shader_context(bld_base);
2799 struct gallivm_state *gallivm = bld_base->base.gallivm;
2800 struct si_shader *es = ctx->shader;
2801 struct tgsi_shader_info *info = &es->selector->info;
2802 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2803 ctx->param_es2gs_offset);
2804 unsigned chan;
2805 int i;
2806
2807 for (i = 0; i < info->num_outputs; i++) {
2808 LLVMValueRef *out_ptr =
2809 ctx->radeon_bld.soa.outputs[i];
2810 int param_index;
2811
2812 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2813 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2814 continue;
2815
2816 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2817 info->output_semantic_index[i]);
2818
2819 for (chan = 0; chan < 4; chan++) {
2820 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2821 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2822
2823 build_tbuffer_store(ctx,
2824 ctx->esgs_ring,
2825 out_val, 1,
2826 LLVMGetUndef(ctx->i32), soffset,
2827 (4 * param_index + chan) * 4,
2828 V_008F0C_BUF_DATA_FORMAT_32,
2829 V_008F0C_BUF_NUM_FORMAT_UINT,
2830 0, 0, 1, 1, 0);
2831 }
2832 }
2833 }
2834
2835 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2836 {
2837 struct si_shader_context *ctx = si_shader_context(bld_base);
2838 struct gallivm_state *gallivm = bld_base->base.gallivm;
2839 LLVMValueRef args[2];
2840
2841 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2842 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2843 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2844 ctx->voidt, args, 2, 0);
2845 }
2846
2847 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2848 {
2849 struct si_shader_context *ctx = si_shader_context(bld_base);
2850 struct gallivm_state *gallivm = bld_base->base.gallivm;
2851 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2852 struct si_shader_output_values *outputs = NULL;
2853 int i,j;
2854
2855 assert(!ctx->is_gs_copy_shader);
2856
2857 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2858
2859 /* Vertex color clamping.
2860 *
2861 * This uses a state constant loaded in a user data SGPR and
2862 * an IF statement is added that clamps all colors if the constant
2863 * is true.
2864 */
2865 if (ctx->type == PIPE_SHADER_VERTEX) {
2866 struct lp_build_if_state if_ctx;
2867 LLVMValueRef cond = NULL;
2868 LLVMValueRef addr, val;
2869
2870 for (i = 0; i < info->num_outputs; i++) {
2871 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2872 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2873 continue;
2874
2875 /* We've found a color. */
2876 if (!cond) {
2877 /* The state is in the first bit of the user SGPR. */
2878 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2879 SI_PARAM_VS_STATE_BITS);
2880 cond = LLVMBuildTrunc(gallivm->builder, cond,
2881 ctx->i1, "");
2882 lp_build_if(&if_ctx, gallivm, cond);
2883 }
2884
2885 for (j = 0; j < 4; j++) {
2886 addr = ctx->radeon_bld.soa.outputs[i][j];
2887 val = LLVMBuildLoad(gallivm->builder, addr, "");
2888 val = radeon_llvm_saturate(bld_base, val);
2889 LLVMBuildStore(gallivm->builder, val, addr);
2890 }
2891 }
2892
2893 if (cond)
2894 lp_build_endif(&if_ctx);
2895 }
2896
2897 for (i = 0; i < info->num_outputs; i++) {
2898 outputs[i].name = info->output_semantic_name[i];
2899 outputs[i].sid = info->output_semantic_index[i];
2900
2901 for (j = 0; j < 4; j++)
2902 outputs[i].values[j] =
2903 LLVMBuildLoad(gallivm->builder,
2904 ctx->radeon_bld.soa.outputs[i][j],
2905 "");
2906 }
2907
2908 if (ctx->is_monolithic) {
2909 /* Export PrimitiveID when PS needs it. */
2910 if (si_vs_exports_prim_id(ctx->shader)) {
2911 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2912 outputs[i].sid = 0;
2913 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2914 get_primitive_id(bld_base, 0));
2915 outputs[i].values[1] = bld_base->base.undef;
2916 outputs[i].values[2] = bld_base->base.undef;
2917 outputs[i].values[3] = bld_base->base.undef;
2918 i++;
2919 }
2920 } else {
2921 /* Return the primitive ID from the LLVM function. */
2922 ctx->return_value =
2923 LLVMBuildInsertValue(gallivm->builder,
2924 ctx->return_value,
2925 bitcast(bld_base, TGSI_TYPE_FLOAT,
2926 get_primitive_id(bld_base, 0)),
2927 VS_EPILOG_PRIMID_LOC, "");
2928 }
2929
2930 si_llvm_export_vs(bld_base, outputs, i);
2931 FREE(outputs);
2932 }
2933
2934 struct si_ps_exports {
2935 unsigned num;
2936 LLVMValueRef args[10][9];
2937 };
2938
2939 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2940 bool writes_samplemask)
2941 {
2942 if (writes_z) {
2943 /* Z needs 32 bits. */
2944 if (writes_samplemask)
2945 return V_028710_SPI_SHADER_32_ABGR;
2946 else if (writes_stencil)
2947 return V_028710_SPI_SHADER_32_GR;
2948 else
2949 return V_028710_SPI_SHADER_32_R;
2950 } else if (writes_stencil || writes_samplemask) {
2951 /* Both stencil and sample mask need only 16 bits. */
2952 return V_028710_SPI_SHADER_UINT16_ABGR;
2953 } else {
2954 return V_028710_SPI_SHADER_ZERO;
2955 }
2956 }
2957
2958 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2959 LLVMValueRef depth, LLVMValueRef stencil,
2960 LLVMValueRef samplemask, struct si_ps_exports *exp)
2961 {
2962 struct si_shader_context *ctx = si_shader_context(bld_base);
2963 struct lp_build_context *base = &bld_base->base;
2964 struct lp_build_context *uint = &bld_base->uint_bld;
2965 LLVMValueRef args[9];
2966 unsigned mask = 0;
2967 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2968 stencil != NULL,
2969 samplemask != NULL);
2970
2971 assert(depth || stencil || samplemask);
2972
2973 args[1] = uint->one; /* whether the EXEC mask is valid */
2974 args[2] = uint->one; /* DONE bit */
2975
2976 /* Specify the target we are exporting */
2977 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2978
2979 args[4] = uint->zero; /* COMP flag */
2980 args[5] = base->undef; /* R, depth */
2981 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2982 args[7] = base->undef; /* B, sample mask */
2983 args[8] = base->undef; /* A, alpha to mask */
2984
2985 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2986 assert(!depth);
2987 args[4] = uint->one; /* COMPR flag */
2988
2989 if (stencil) {
2990 /* Stencil should be in X[23:16]. */
2991 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2992 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2993 LLVMConstInt(ctx->i32, 16, 0), "");
2994 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2995 mask |= 0x3;
2996 }
2997 if (samplemask) {
2998 /* SampleMask should be in Y[15:0]. */
2999 args[6] = samplemask;
3000 mask |= 0xc;
3001 }
3002 } else {
3003 if (depth) {
3004 args[5] = depth;
3005 mask |= 0x1;
3006 }
3007 if (stencil) {
3008 args[6] = stencil;
3009 mask |= 0x2;
3010 }
3011 if (samplemask) {
3012 args[7] = samplemask;
3013 mask |= 0x4;
3014 }
3015 }
3016
3017 /* SI (except OLAND) has a bug that it only looks
3018 * at the X writemask component. */
3019 if (ctx->screen->b.chip_class == SI &&
3020 ctx->screen->b.family != CHIP_OLAND)
3021 mask |= 0x1;
3022
3023 /* Specify which components to enable */
3024 args[0] = lp_build_const_int32(base->gallivm, mask);
3025
3026 memcpy(exp->args[exp->num++], args, sizeof(args));
3027 }
3028
3029 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3030 LLVMValueRef *color, unsigned index,
3031 unsigned samplemask_param,
3032 bool is_last, struct si_ps_exports *exp)
3033 {
3034 struct si_shader_context *ctx = si_shader_context(bld_base);
3035 struct lp_build_context *base = &bld_base->base;
3036 int i;
3037
3038 /* Clamp color */
3039 if (ctx->shader->key.ps.epilog.clamp_color)
3040 for (i = 0; i < 4; i++)
3041 color[i] = radeon_llvm_saturate(bld_base, color[i]);
3042
3043 /* Alpha to one */
3044 if (ctx->shader->key.ps.epilog.alpha_to_one)
3045 color[3] = base->one;
3046
3047 /* Alpha test */
3048 if (index == 0 &&
3049 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3050 si_alpha_test(bld_base, color[3]);
3051
3052 /* Line & polygon smoothing */
3053 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
3054 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3055 samplemask_param);
3056
3057 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3058 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3059 LLVMValueRef args[8][9];
3060 int c, last = -1;
3061
3062 /* Get the export arguments, also find out what the last one is. */
3063 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3064 si_llvm_init_export_args(bld_base, color,
3065 V_008DFC_SQ_EXP_MRT + c, args[c]);
3066 if (args[c][0] != bld_base->uint_bld.zero)
3067 last = c;
3068 }
3069
3070 /* Emit all exports. */
3071 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3072 if (is_last && last == c) {
3073 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3074 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3075 } else if (args[c][0] == bld_base->uint_bld.zero)
3076 continue; /* unnecessary NULL export */
3077
3078 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3079 }
3080 } else {
3081 LLVMValueRef args[9];
3082
3083 /* Export */
3084 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3085 args);
3086 if (is_last) {
3087 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3088 args[2] = bld_base->uint_bld.one; /* DONE bit */
3089 } else if (args[0] == bld_base->uint_bld.zero)
3090 return; /* unnecessary NULL export */
3091
3092 memcpy(exp->args[exp->num++], args, sizeof(args));
3093 }
3094 }
3095
3096 static void si_emit_ps_exports(struct si_shader_context *ctx,
3097 struct si_ps_exports *exp)
3098 {
3099 for (unsigned i = 0; i < exp->num; i++)
3100 lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
3101 "llvm.SI.export", ctx->voidt,
3102 exp->args[i], 9, 0);
3103 }
3104
3105 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3106 {
3107 struct si_shader_context *ctx = si_shader_context(bld_base);
3108 struct lp_build_context *base = &bld_base->base;
3109 struct lp_build_context *uint = &bld_base->uint_bld;
3110 LLVMValueRef args[9];
3111
3112 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3113 args[1] = uint->one; /* whether the EXEC mask is valid */
3114 args[2] = uint->one; /* DONE bit */
3115 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3116 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3117 args[5] = base->undef; /* R */
3118 args[6] = base->undef; /* G */
3119 args[7] = base->undef; /* B */
3120 args[8] = base->undef; /* A */
3121
3122 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3123 ctx->voidt, args, 9, 0);
3124 }
3125
3126 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3127 {
3128 struct si_shader_context *ctx = si_shader_context(bld_base);
3129 struct si_shader *shader = ctx->shader;
3130 struct lp_build_context *base = &bld_base->base;
3131 struct tgsi_shader_info *info = &shader->selector->info;
3132 LLVMBuilderRef builder = base->gallivm->builder;
3133 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3134 int last_color_export = -1;
3135 int i;
3136 struct si_ps_exports exp = {};
3137
3138 /* Determine the last export. If MRTZ is present, it's always last.
3139 * Otherwise, find the last color export.
3140 */
3141 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3142 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3143
3144 /* Don't export NULL and return if alpha-test is enabled. */
3145 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3146 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3147 (spi_format & 0xf) == 0)
3148 spi_format |= V_028714_SPI_SHADER_32_AR;
3149
3150 for (i = 0; i < info->num_outputs; i++) {
3151 unsigned index = info->output_semantic_index[i];
3152
3153 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3154 continue;
3155
3156 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3157 if (shader->key.ps.epilog.last_cbuf > 0) {
3158 /* Just set this if any of the colorbuffers are enabled. */
3159 if (spi_format &
3160 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3161 last_color_export = i;
3162 continue;
3163 }
3164
3165 if ((spi_format >> (index * 4)) & 0xf)
3166 last_color_export = i;
3167 }
3168
3169 /* If there are no outputs, export NULL. */
3170 if (last_color_export == -1) {
3171 si_export_null(bld_base);
3172 return;
3173 }
3174 }
3175
3176 for (i = 0; i < info->num_outputs; i++) {
3177 unsigned semantic_name = info->output_semantic_name[i];
3178 unsigned semantic_index = info->output_semantic_index[i];
3179 unsigned j;
3180 LLVMValueRef color[4] = {};
3181
3182 /* Select the correct target */
3183 switch (semantic_name) {
3184 case TGSI_SEMANTIC_POSITION:
3185 depth = LLVMBuildLoad(builder,
3186 ctx->radeon_bld.soa.outputs[i][2], "");
3187 break;
3188 case TGSI_SEMANTIC_STENCIL:
3189 stencil = LLVMBuildLoad(builder,
3190 ctx->radeon_bld.soa.outputs[i][1], "");
3191 break;
3192 case TGSI_SEMANTIC_SAMPLEMASK:
3193 samplemask = LLVMBuildLoad(builder,
3194 ctx->radeon_bld.soa.outputs[i][0], "");
3195 break;
3196 case TGSI_SEMANTIC_COLOR:
3197 for (j = 0; j < 4; j++)
3198 color[j] = LLVMBuildLoad(builder,
3199 ctx->radeon_bld.soa.outputs[i][j], "");
3200
3201 si_export_mrt_color(bld_base, color, semantic_index,
3202 SI_PARAM_SAMPLE_COVERAGE,
3203 last_color_export == i, &exp);
3204 break;
3205 default:
3206 fprintf(stderr,
3207 "Warning: SI unhandled fs output type:%d\n",
3208 semantic_name);
3209 }
3210 }
3211
3212 if (depth || stencil || samplemask)
3213 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
3214
3215 si_emit_ps_exports(ctx, &exp);
3216 }
3217
3218 /**
3219 * Return PS outputs in this order:
3220 *
3221 * v[0:3] = color0.xyzw
3222 * v[4:7] = color1.xyzw
3223 * ...
3224 * vN+0 = Depth
3225 * vN+1 = Stencil
3226 * vN+2 = SampleMask
3227 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3228 *
3229 * The alpha-ref SGPR is returned via its original location.
3230 */
3231 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3232 {
3233 struct si_shader_context *ctx = si_shader_context(bld_base);
3234 struct si_shader *shader = ctx->shader;
3235 struct lp_build_context *base = &bld_base->base;
3236 struct tgsi_shader_info *info = &shader->selector->info;
3237 LLVMBuilderRef builder = base->gallivm->builder;
3238 unsigned i, j, first_vgpr, vgpr;
3239
3240 LLVMValueRef color[8][4] = {};
3241 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3242 LLVMValueRef ret;
3243
3244 /* Read the output values. */
3245 for (i = 0; i < info->num_outputs; i++) {
3246 unsigned semantic_name = info->output_semantic_name[i];
3247 unsigned semantic_index = info->output_semantic_index[i];
3248
3249 switch (semantic_name) {
3250 case TGSI_SEMANTIC_COLOR:
3251 assert(semantic_index < 8);
3252 for (j = 0; j < 4; j++) {
3253 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3254 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3255 color[semantic_index][j] = result;
3256 }
3257 break;
3258 case TGSI_SEMANTIC_POSITION:
3259 depth = LLVMBuildLoad(builder,
3260 ctx->radeon_bld.soa.outputs[i][2], "");
3261 break;
3262 case TGSI_SEMANTIC_STENCIL:
3263 stencil = LLVMBuildLoad(builder,
3264 ctx->radeon_bld.soa.outputs[i][1], "");
3265 break;
3266 case TGSI_SEMANTIC_SAMPLEMASK:
3267 samplemask = LLVMBuildLoad(builder,
3268 ctx->radeon_bld.soa.outputs[i][0], "");
3269 break;
3270 default:
3271 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3272 semantic_name);
3273 }
3274 }
3275
3276 /* Fill the return structure. */
3277 ret = ctx->return_value;
3278
3279 /* Set SGPRs. */
3280 ret = LLVMBuildInsertValue(builder, ret,
3281 bitcast(bld_base, TGSI_TYPE_SIGNED,
3282 LLVMGetParam(ctx->radeon_bld.main_fn,
3283 SI_PARAM_ALPHA_REF)),
3284 SI_SGPR_ALPHA_REF, "");
3285
3286 /* Set VGPRs */
3287 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3288 for (i = 0; i < ARRAY_SIZE(color); i++) {
3289 if (!color[i][0])
3290 continue;
3291
3292 for (j = 0; j < 4; j++)
3293 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3294 }
3295 if (depth)
3296 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3297 if (stencil)
3298 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3299 if (samplemask)
3300 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3301
3302 /* Add the input sample mask for smoothing at the end. */
3303 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3304 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3305 ret = LLVMBuildInsertValue(builder, ret,
3306 LLVMGetParam(ctx->radeon_bld.main_fn,
3307 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3308
3309 ctx->return_value = ret;
3310 }
3311
3312 /**
3313 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3314 * buffer in number of elements and return it as an i32.
3315 */
3316 static LLVMValueRef get_buffer_size(
3317 struct lp_build_tgsi_context *bld_base,
3318 LLVMValueRef descriptor)
3319 {
3320 struct si_shader_context *ctx = si_shader_context(bld_base);
3321 struct gallivm_state *gallivm = bld_base->base.gallivm;
3322 LLVMBuilderRef builder = gallivm->builder;
3323 LLVMValueRef size =
3324 LLVMBuildExtractElement(builder, descriptor,
3325 lp_build_const_int32(gallivm, 6), "");
3326
3327 if (ctx->screen->b.chip_class >= VI) {
3328 /* On VI, the descriptor contains the size in bytes,
3329 * but TXQ must return the size in elements.
3330 * The stride is always non-zero for resources using TXQ.
3331 */
3332 LLVMValueRef stride =
3333 LLVMBuildExtractElement(builder, descriptor,
3334 lp_build_const_int32(gallivm, 5), "");
3335 stride = LLVMBuildLShr(builder, stride,
3336 lp_build_const_int32(gallivm, 16), "");
3337 stride = LLVMBuildAnd(builder, stride,
3338 lp_build_const_int32(gallivm, 0x3FFF), "");
3339
3340 size = LLVMBuildUDiv(builder, size, stride, "");
3341 }
3342
3343 return size;
3344 }
3345
3346 /**
3347 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3348 * intrinsic names).
3349 */
3350 static void build_int_type_name(
3351 LLVMTypeRef type,
3352 char *buf, unsigned bufsize)
3353 {
3354 assert(bufsize >= 6);
3355
3356 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3357 snprintf(buf, bufsize, "v%ui32",
3358 LLVMGetVectorSize(type));
3359 else
3360 strcpy(buf, "i32");
3361 }
3362
3363 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3364 struct lp_build_tgsi_context *bld_base,
3365 struct lp_build_emit_data *emit_data);
3366
3367 /* Prevent optimizations (at least of memory accesses) across the current
3368 * point in the program by emitting empty inline assembly that is marked as
3369 * having side effects.
3370 */
3371 static void emit_optimization_barrier(struct si_shader_context *ctx)
3372 {
3373 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3374 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3375 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3376 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3377 }
3378
3379 static void emit_waitcnt(struct si_shader_context *ctx)
3380 {
3381 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3382 LLVMBuilderRef builder = gallivm->builder;
3383 LLVMValueRef args[1] = {
3384 lp_build_const_int32(gallivm, 0xf70)
3385 };
3386 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3387 ctx->voidt, args, 1, 0);
3388 }
3389
3390 static void membar_emit(
3391 const struct lp_build_tgsi_action *action,
3392 struct lp_build_tgsi_context *bld_base,
3393 struct lp_build_emit_data *emit_data)
3394 {
3395 struct si_shader_context *ctx = si_shader_context(bld_base);
3396
3397 emit_waitcnt(ctx);
3398 }
3399
3400 static LLVMValueRef
3401 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3402 const struct tgsi_full_src_register *reg)
3403 {
3404 LLVMValueRef index;
3405 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3406 SI_PARAM_SHADER_BUFFERS);
3407
3408 if (!reg->Register.Indirect)
3409 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3410 else
3411 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3412 reg->Register.Index,
3413 SI_NUM_SHADER_BUFFERS);
3414
3415 return build_indexed_load_const(ctx, rsrc_ptr, index);
3416 }
3417
3418 static bool tgsi_is_array_sampler(unsigned target)
3419 {
3420 return target == TGSI_TEXTURE_1D_ARRAY ||
3421 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3422 target == TGSI_TEXTURE_2D_ARRAY ||
3423 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3424 target == TGSI_TEXTURE_CUBE_ARRAY ||
3425 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3426 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3427 }
3428
3429 static bool tgsi_is_array_image(unsigned target)
3430 {
3431 return target == TGSI_TEXTURE_3D ||
3432 target == TGSI_TEXTURE_CUBE ||
3433 target == TGSI_TEXTURE_1D_ARRAY ||
3434 target == TGSI_TEXTURE_2D_ARRAY ||
3435 target == TGSI_TEXTURE_CUBE_ARRAY ||
3436 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3437 }
3438
3439 /**
3440 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3441 *
3442 * At least on Tonga, executing image stores on images with DCC enabled and
3443 * non-trivial can eventually lead to lockups. This can occur when an
3444 * application binds an image as read-only but then uses a shader that writes
3445 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3446 * program termination) in this case, but it doesn't cost much to be a bit
3447 * nicer: disabling DCC in the shader still leads to undefined results but
3448 * avoids the lockup.
3449 */
3450 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3451 LLVMValueRef rsrc)
3452 {
3453 if (ctx->screen->b.chip_class <= CIK) {
3454 return rsrc;
3455 } else {
3456 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3457 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3458 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3459 LLVMValueRef tmp;
3460
3461 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3462 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3463 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3464 }
3465 }
3466
3467 /**
3468 * Load the resource descriptor for \p image.
3469 */
3470 static void
3471 image_fetch_rsrc(
3472 struct lp_build_tgsi_context *bld_base,
3473 const struct tgsi_full_src_register *image,
3474 bool dcc_off,
3475 LLVMValueRef *rsrc)
3476 {
3477 struct si_shader_context *ctx = si_shader_context(bld_base);
3478 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3479 SI_PARAM_IMAGES);
3480 LLVMValueRef index, tmp;
3481
3482 assert(image->Register.File == TGSI_FILE_IMAGE);
3483
3484 if (!image->Register.Indirect) {
3485 const struct tgsi_shader_info *info = bld_base->info;
3486
3487 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3488
3489 if (info->images_writemask & (1 << image->Register.Index) &&
3490 !(info->images_buffers & (1 << image->Register.Index)))
3491 dcc_off = true;
3492 } else {
3493 /* From the GL_ARB_shader_image_load_store extension spec:
3494 *
3495 * If a shader performs an image load, store, or atomic
3496 * operation using an image variable declared as an array,
3497 * and if the index used to select an individual element is
3498 * negative or greater than or equal to the size of the
3499 * array, the results of the operation are undefined but may
3500 * not lead to termination.
3501 */
3502 index = get_bounded_indirect_index(ctx, &image->Indirect,
3503 image->Register.Index,
3504 SI_NUM_IMAGES);
3505 }
3506
3507 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3508 if (dcc_off)
3509 tmp = force_dcc_off(ctx, tmp);
3510 *rsrc = tmp;
3511 }
3512
3513 static LLVMValueRef image_fetch_coords(
3514 struct lp_build_tgsi_context *bld_base,
3515 const struct tgsi_full_instruction *inst,
3516 unsigned src)
3517 {
3518 struct gallivm_state *gallivm = bld_base->base.gallivm;
3519 LLVMBuilderRef builder = gallivm->builder;
3520 unsigned target = inst->Memory.Texture;
3521 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3522 LLVMValueRef coords[4];
3523 LLVMValueRef tmp;
3524 int chan;
3525
3526 for (chan = 0; chan < num_coords; ++chan) {
3527 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3528 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3529 coords[chan] = tmp;
3530 }
3531
3532 if (num_coords == 1)
3533 return coords[0];
3534
3535 if (num_coords == 3) {
3536 /* LLVM has difficulties lowering 3-element vectors. */
3537 coords[3] = bld_base->uint_bld.undef;
3538 num_coords = 4;
3539 }
3540
3541 return lp_build_gather_values(gallivm, coords, num_coords);
3542 }
3543
3544 /**
3545 * Append the extra mode bits that are used by image load and store.
3546 */
3547 static void image_append_args(
3548 struct si_shader_context *ctx,
3549 struct lp_build_emit_data * emit_data,
3550 unsigned target,
3551 bool atomic)
3552 {
3553 const struct tgsi_full_instruction *inst = emit_data->inst;
3554 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3555 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3556
3557 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3558 emit_data->args[emit_data->arg_count++] =
3559 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3560 if (!atomic) {
3561 emit_data->args[emit_data->arg_count++] =
3562 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3563 i1true : i1false; /* glc */
3564 }
3565 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3566 }
3567
3568 /**
3569 * Given a 256 bit resource, extract the top half (which stores the buffer
3570 * resource in the case of textures and images).
3571 */
3572 static LLVMValueRef extract_rsrc_top_half(
3573 struct si_shader_context *ctx,
3574 LLVMValueRef rsrc)
3575 {
3576 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3577 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3578 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3579
3580 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3581 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3582 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3583
3584 return rsrc;
3585 }
3586
3587 /**
3588 * Append the resource and indexing arguments for buffer intrinsics.
3589 *
3590 * \param rsrc the v4i32 buffer resource
3591 * \param index index into the buffer (stride-based)
3592 * \param offset byte offset into the buffer
3593 */
3594 static void buffer_append_args(
3595 struct si_shader_context *ctx,
3596 struct lp_build_emit_data *emit_data,
3597 LLVMValueRef rsrc,
3598 LLVMValueRef index,
3599 LLVMValueRef offset,
3600 bool atomic)
3601 {
3602 const struct tgsi_full_instruction *inst = emit_data->inst;
3603 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3604 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3605
3606 emit_data->args[emit_data->arg_count++] = rsrc;
3607 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3608 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3609 if (!atomic) {
3610 emit_data->args[emit_data->arg_count++] =
3611 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3612 i1true : i1false; /* glc */
3613 }
3614 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3615 }
3616
3617 static void load_fetch_args(
3618 struct lp_build_tgsi_context * bld_base,
3619 struct lp_build_emit_data * emit_data)
3620 {
3621 struct si_shader_context *ctx = si_shader_context(bld_base);
3622 struct gallivm_state *gallivm = bld_base->base.gallivm;
3623 const struct tgsi_full_instruction * inst = emit_data->inst;
3624 unsigned target = inst->Memory.Texture;
3625 LLVMValueRef rsrc;
3626
3627 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3628
3629 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3630 LLVMBuilderRef builder = gallivm->builder;
3631 LLVMValueRef offset;
3632 LLVMValueRef tmp;
3633
3634 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3635
3636 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3637 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3638
3639 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3640 offset, false);
3641 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3642 LLVMValueRef coords;
3643
3644 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3645 coords = image_fetch_coords(bld_base, inst, 1);
3646
3647 if (target == TGSI_TEXTURE_BUFFER) {
3648 rsrc = extract_rsrc_top_half(ctx, rsrc);
3649 buffer_append_args(ctx, emit_data, rsrc, coords,
3650 bld_base->uint_bld.zero, false);
3651 } else {
3652 emit_data->args[0] = coords;
3653 emit_data->args[1] = rsrc;
3654 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3655 emit_data->arg_count = 3;
3656
3657 image_append_args(ctx, emit_data, target, false);
3658 }
3659 }
3660 }
3661
3662 static void load_emit_buffer(struct si_shader_context *ctx,
3663 struct lp_build_emit_data *emit_data)
3664 {
3665 const struct tgsi_full_instruction *inst = emit_data->inst;
3666 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3667 LLVMBuilderRef builder = gallivm->builder;
3668 uint writemask = inst->Dst[0].Register.WriteMask;
3669 uint count = util_last_bit(writemask);
3670 const char *intrinsic_name;
3671 LLVMTypeRef dst_type;
3672
3673 switch (count) {
3674 case 1:
3675 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3676 dst_type = ctx->f32;
3677 break;
3678 case 2:
3679 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3680 dst_type = LLVMVectorType(ctx->f32, 2);
3681 break;
3682 default: // 3 & 4
3683 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3684 dst_type = ctx->v4f32;
3685 count = 4;
3686 }
3687
3688 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3689 builder, intrinsic_name, dst_type,
3690 emit_data->args, emit_data->arg_count,
3691 LLVMReadOnlyAttribute);
3692 }
3693
3694 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3695 const struct tgsi_full_instruction *inst,
3696 LLVMTypeRef type, int arg)
3697 {
3698 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3699 LLVMBuilderRef builder = gallivm->builder;
3700 LLVMValueRef offset, ptr;
3701 int addr_space;
3702
3703 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3704 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3705
3706 ptr = ctx->shared_memory;
3707 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3708 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3709 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3710
3711 return ptr;
3712 }
3713
3714 static void load_emit_memory(
3715 struct si_shader_context *ctx,
3716 struct lp_build_emit_data *emit_data)
3717 {
3718 const struct tgsi_full_instruction *inst = emit_data->inst;
3719 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3720 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3721 LLVMBuilderRef builder = gallivm->builder;
3722 unsigned writemask = inst->Dst[0].Register.WriteMask;
3723 LLVMValueRef channels[4], ptr, derived_ptr, index;
3724 int chan;
3725
3726 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3727
3728 for (chan = 0; chan < 4; ++chan) {
3729 if (!(writemask & (1 << chan))) {
3730 channels[chan] = LLVMGetUndef(base->elem_type);
3731 continue;
3732 }
3733
3734 index = lp_build_const_int32(gallivm, chan);
3735 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3736 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3737 }
3738 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3739 }
3740
3741 static void get_image_intr_name(const char *base_name,
3742 LLVMTypeRef coords_type,
3743 char *out_name, unsigned out_len)
3744 {
3745 char coords_type_name[8];
3746
3747 build_int_type_name(coords_type, coords_type_name,
3748 sizeof(coords_type_name));
3749
3750 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3751 }
3752
3753 static void load_emit(
3754 const struct lp_build_tgsi_action *action,
3755 struct lp_build_tgsi_context *bld_base,
3756 struct lp_build_emit_data *emit_data)
3757 {
3758 struct si_shader_context *ctx = si_shader_context(bld_base);
3759 struct gallivm_state *gallivm = bld_base->base.gallivm;
3760 LLVMBuilderRef builder = gallivm->builder;
3761 const struct tgsi_full_instruction * inst = emit_data->inst;
3762 char intrinsic_name[32];
3763
3764 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3765 load_emit_memory(ctx, emit_data);
3766 return;
3767 }
3768
3769 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3770 emit_waitcnt(ctx);
3771
3772 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3773 load_emit_buffer(ctx, emit_data);
3774 return;
3775 }
3776
3777 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3778 emit_data->output[emit_data->chan] =
3779 lp_build_intrinsic(
3780 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3781 emit_data->args, emit_data->arg_count,
3782 LLVMReadOnlyAttribute);
3783 } else {
3784 get_image_intr_name("llvm.amdgcn.image.load",
3785 LLVMTypeOf(emit_data->args[0]),
3786 intrinsic_name, sizeof(intrinsic_name));
3787
3788 emit_data->output[emit_data->chan] =
3789 lp_build_intrinsic(
3790 builder, intrinsic_name, emit_data->dst_type,
3791 emit_data->args, emit_data->arg_count,
3792 LLVMReadOnlyAttribute);
3793 }
3794 }
3795
3796 static void store_fetch_args(
3797 struct lp_build_tgsi_context * bld_base,
3798 struct lp_build_emit_data * emit_data)
3799 {
3800 struct si_shader_context *ctx = si_shader_context(bld_base);
3801 struct gallivm_state *gallivm = bld_base->base.gallivm;
3802 LLVMBuilderRef builder = gallivm->builder;
3803 const struct tgsi_full_instruction * inst = emit_data->inst;
3804 struct tgsi_full_src_register memory;
3805 LLVMValueRef chans[4];
3806 LLVMValueRef data;
3807 LLVMValueRef rsrc;
3808 unsigned chan;
3809
3810 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3811
3812 for (chan = 0; chan < 4; ++chan) {
3813 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3814 }
3815 data = lp_build_gather_values(gallivm, chans, 4);
3816
3817 emit_data->args[emit_data->arg_count++] = data;
3818
3819 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3820
3821 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3822 LLVMValueRef offset;
3823 LLVMValueRef tmp;
3824
3825 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3826
3827 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3828 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3829
3830 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3831 offset, false);
3832 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3833 unsigned target = inst->Memory.Texture;
3834 LLVMValueRef coords;
3835
3836 coords = image_fetch_coords(bld_base, inst, 0);
3837
3838 if (target == TGSI_TEXTURE_BUFFER) {
3839 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3840
3841 rsrc = extract_rsrc_top_half(ctx, rsrc);
3842 buffer_append_args(ctx, emit_data, rsrc, coords,
3843 bld_base->uint_bld.zero, false);
3844 } else {
3845 emit_data->args[1] = coords;
3846 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3847 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3848 emit_data->arg_count = 4;
3849
3850 image_append_args(ctx, emit_data, target, false);
3851 }
3852 }
3853 }
3854
3855 static void store_emit_buffer(
3856 struct si_shader_context *ctx,
3857 struct lp_build_emit_data *emit_data)
3858 {
3859 const struct tgsi_full_instruction *inst = emit_data->inst;
3860 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3861 LLVMBuilderRef builder = gallivm->builder;
3862 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3863 LLVMValueRef base_data = emit_data->args[0];
3864 LLVMValueRef base_offset = emit_data->args[3];
3865 unsigned writemask = inst->Dst[0].Register.WriteMask;
3866
3867 while (writemask) {
3868 int start, count;
3869 const char *intrinsic_name;
3870 LLVMValueRef data;
3871 LLVMValueRef offset;
3872 LLVMValueRef tmp;
3873
3874 u_bit_scan_consecutive_range(&writemask, &start, &count);
3875
3876 /* Due to an LLVM limitation, split 3-element writes
3877 * into a 2-element and a 1-element write. */
3878 if (count == 3) {
3879 writemask |= 1 << (start + 2);
3880 count = 2;
3881 }
3882
3883 if (count == 4) {
3884 data = base_data;
3885 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3886 } else if (count == 2) {
3887 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3888
3889 tmp = LLVMBuildExtractElement(
3890 builder, base_data,
3891 lp_build_const_int32(gallivm, start), "");
3892 data = LLVMBuildInsertElement(
3893 builder, LLVMGetUndef(v2f32), tmp,
3894 uint_bld->zero, "");
3895
3896 tmp = LLVMBuildExtractElement(
3897 builder, base_data,
3898 lp_build_const_int32(gallivm, start + 1), "");
3899 data = LLVMBuildInsertElement(
3900 builder, data, tmp, uint_bld->one, "");
3901
3902 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3903 } else {
3904 assert(count == 1);
3905 data = LLVMBuildExtractElement(
3906 builder, base_data,
3907 lp_build_const_int32(gallivm, start), "");
3908 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3909 }
3910
3911 offset = base_offset;
3912 if (start != 0) {
3913 offset = LLVMBuildAdd(
3914 builder, offset,
3915 lp_build_const_int32(gallivm, start * 4), "");
3916 }
3917
3918 emit_data->args[0] = data;
3919 emit_data->args[3] = offset;
3920
3921 lp_build_intrinsic(
3922 builder, intrinsic_name, emit_data->dst_type,
3923 emit_data->args, emit_data->arg_count, 0);
3924 }
3925 }
3926
3927 static void store_emit_memory(
3928 struct si_shader_context *ctx,
3929 struct lp_build_emit_data *emit_data)
3930 {
3931 const struct tgsi_full_instruction *inst = emit_data->inst;
3932 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3933 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3934 LLVMBuilderRef builder = gallivm->builder;
3935 unsigned writemask = inst->Dst[0].Register.WriteMask;
3936 LLVMValueRef ptr, derived_ptr, data, index;
3937 int chan;
3938
3939 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3940
3941 for (chan = 0; chan < 4; ++chan) {
3942 if (!(writemask & (1 << chan))) {
3943 continue;
3944 }
3945 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3946 index = lp_build_const_int32(gallivm, chan);
3947 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3948 LLVMBuildStore(builder, data, derived_ptr);
3949 }
3950 }
3951
3952 static void store_emit(
3953 const struct lp_build_tgsi_action *action,
3954 struct lp_build_tgsi_context *bld_base,
3955 struct lp_build_emit_data *emit_data)
3956 {
3957 struct si_shader_context *ctx = si_shader_context(bld_base);
3958 struct gallivm_state *gallivm = bld_base->base.gallivm;
3959 LLVMBuilderRef builder = gallivm->builder;
3960 const struct tgsi_full_instruction * inst = emit_data->inst;
3961 unsigned target = inst->Memory.Texture;
3962 char intrinsic_name[32];
3963
3964 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3965 store_emit_memory(ctx, emit_data);
3966 return;
3967 }
3968
3969 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3970 emit_waitcnt(ctx);
3971
3972 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3973 store_emit_buffer(ctx, emit_data);
3974 return;
3975 }
3976
3977 if (target == TGSI_TEXTURE_BUFFER) {
3978 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3979 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3980 emit_data->dst_type, emit_data->args,
3981 emit_data->arg_count, 0);
3982 } else {
3983 get_image_intr_name("llvm.amdgcn.image.store",
3984 LLVMTypeOf(emit_data->args[1]),
3985 intrinsic_name, sizeof(intrinsic_name));
3986
3987 emit_data->output[emit_data->chan] =
3988 lp_build_intrinsic(
3989 builder, intrinsic_name, emit_data->dst_type,
3990 emit_data->args, emit_data->arg_count, 0);
3991 }
3992 }
3993
3994 static void atomic_fetch_args(
3995 struct lp_build_tgsi_context * bld_base,
3996 struct lp_build_emit_data * emit_data)
3997 {
3998 struct si_shader_context *ctx = si_shader_context(bld_base);
3999 struct gallivm_state *gallivm = bld_base->base.gallivm;
4000 LLVMBuilderRef builder = gallivm->builder;
4001 const struct tgsi_full_instruction * inst = emit_data->inst;
4002 LLVMValueRef data1, data2;
4003 LLVMValueRef rsrc;
4004 LLVMValueRef tmp;
4005
4006 emit_data->dst_type = bld_base->base.elem_type;
4007
4008 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4009 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4010
4011 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4012 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4013 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4014 }
4015
4016 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4017 * of arguments, which is reversed relative to TGSI (and GLSL)
4018 */
4019 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4020 emit_data->args[emit_data->arg_count++] = data2;
4021 emit_data->args[emit_data->arg_count++] = data1;
4022
4023 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4024 LLVMValueRef offset;
4025
4026 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4027
4028 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4029 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4030
4031 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4032 offset, true);
4033 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4034 unsigned target = inst->Memory.Texture;
4035 LLVMValueRef coords;
4036
4037 image_fetch_rsrc(bld_base, &inst->Src[0],
4038 target != TGSI_TEXTURE_BUFFER, &rsrc);
4039 coords = image_fetch_coords(bld_base, inst, 1);
4040
4041 if (target == TGSI_TEXTURE_BUFFER) {
4042 rsrc = extract_rsrc_top_half(ctx, rsrc);
4043 buffer_append_args(ctx, emit_data, rsrc, coords,
4044 bld_base->uint_bld.zero, true);
4045 } else {
4046 emit_data->args[emit_data->arg_count++] = coords;
4047 emit_data->args[emit_data->arg_count++] = rsrc;
4048
4049 image_append_args(ctx, emit_data, target, true);
4050 }
4051 }
4052 }
4053
4054 static void atomic_emit_memory(struct si_shader_context *ctx,
4055 struct lp_build_emit_data *emit_data) {
4056 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4057 LLVMBuilderRef builder = gallivm->builder;
4058 const struct tgsi_full_instruction * inst = emit_data->inst;
4059 LLVMValueRef ptr, result, arg;
4060
4061 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4062
4063 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
4064 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4065
4066 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4067 LLVMValueRef new_data;
4068 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
4069 inst, 3, 0);
4070
4071 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4072
4073 #if HAVE_LLVM >= 0x309
4074 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4075 LLVMAtomicOrderingSequentiallyConsistent,
4076 LLVMAtomicOrderingSequentiallyConsistent,
4077 false);
4078 #endif
4079
4080 result = LLVMBuildExtractValue(builder, result, 0, "");
4081 } else {
4082 LLVMAtomicRMWBinOp op;
4083
4084 switch(inst->Instruction.Opcode) {
4085 case TGSI_OPCODE_ATOMUADD:
4086 op = LLVMAtomicRMWBinOpAdd;
4087 break;
4088 case TGSI_OPCODE_ATOMXCHG:
4089 op = LLVMAtomicRMWBinOpXchg;
4090 break;
4091 case TGSI_OPCODE_ATOMAND:
4092 op = LLVMAtomicRMWBinOpAnd;
4093 break;
4094 case TGSI_OPCODE_ATOMOR:
4095 op = LLVMAtomicRMWBinOpOr;
4096 break;
4097 case TGSI_OPCODE_ATOMXOR:
4098 op = LLVMAtomicRMWBinOpXor;
4099 break;
4100 case TGSI_OPCODE_ATOMUMIN:
4101 op = LLVMAtomicRMWBinOpUMin;
4102 break;
4103 case TGSI_OPCODE_ATOMUMAX:
4104 op = LLVMAtomicRMWBinOpUMax;
4105 break;
4106 case TGSI_OPCODE_ATOMIMIN:
4107 op = LLVMAtomicRMWBinOpMin;
4108 break;
4109 case TGSI_OPCODE_ATOMIMAX:
4110 op = LLVMAtomicRMWBinOpMax;
4111 break;
4112 default:
4113 unreachable("unknown atomic opcode");
4114 }
4115
4116 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4117 LLVMAtomicOrderingSequentiallyConsistent,
4118 false);
4119 }
4120 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4121 }
4122
4123 static void atomic_emit(
4124 const struct lp_build_tgsi_action *action,
4125 struct lp_build_tgsi_context *bld_base,
4126 struct lp_build_emit_data *emit_data)
4127 {
4128 struct si_shader_context *ctx = si_shader_context(bld_base);
4129 struct gallivm_state *gallivm = bld_base->base.gallivm;
4130 LLVMBuilderRef builder = gallivm->builder;
4131 const struct tgsi_full_instruction * inst = emit_data->inst;
4132 char intrinsic_name[40];
4133 LLVMValueRef tmp;
4134
4135 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4136 atomic_emit_memory(ctx, emit_data);
4137 return;
4138 }
4139
4140 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4141 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4142 snprintf(intrinsic_name, sizeof(intrinsic_name),
4143 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4144 } else {
4145 char coords_type[8];
4146
4147 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4148 coords_type, sizeof(coords_type));
4149 snprintf(intrinsic_name, sizeof(intrinsic_name),
4150 "llvm.amdgcn.image.atomic.%s.%s",
4151 action->intr_name, coords_type);
4152 }
4153
4154 tmp = lp_build_intrinsic(
4155 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4156 emit_data->args, emit_data->arg_count, 0);
4157 emit_data->output[emit_data->chan] =
4158 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4159 }
4160
4161 static void resq_fetch_args(
4162 struct lp_build_tgsi_context * bld_base,
4163 struct lp_build_emit_data * emit_data)
4164 {
4165 struct si_shader_context *ctx = si_shader_context(bld_base);
4166 struct gallivm_state *gallivm = bld_base->base.gallivm;
4167 const struct tgsi_full_instruction *inst = emit_data->inst;
4168 const struct tgsi_full_src_register *reg = &inst->Src[0];
4169
4170 emit_data->dst_type = ctx->v4i32;
4171
4172 if (reg->Register.File == TGSI_FILE_BUFFER) {
4173 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4174 emit_data->arg_count = 1;
4175 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4176 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4177 emit_data->arg_count = 1;
4178 } else {
4179 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4180 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4181 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4182 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4183 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4184 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4185 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4186 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4187 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4188 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4189 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4190 emit_data->arg_count = 10;
4191 }
4192 }
4193
4194 static void resq_emit(
4195 const struct lp_build_tgsi_action *action,
4196 struct lp_build_tgsi_context *bld_base,
4197 struct lp_build_emit_data *emit_data)
4198 {
4199 struct gallivm_state *gallivm = bld_base->base.gallivm;
4200 LLVMBuilderRef builder = gallivm->builder;
4201 const struct tgsi_full_instruction *inst = emit_data->inst;
4202 LLVMValueRef out;
4203
4204 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4205 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4206 lp_build_const_int32(gallivm, 2), "");
4207 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4208 out = get_buffer_size(bld_base, emit_data->args[0]);
4209 } else {
4210 out = lp_build_intrinsic(
4211 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4212 emit_data->args, emit_data->arg_count,
4213 LLVMReadNoneAttribute);
4214
4215 /* Divide the number of layers by 6 to get the number of cubes. */
4216 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4217 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4218 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4219
4220 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4221 z = LLVMBuildSDiv(builder, z, imm6, "");
4222 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4223 }
4224 }
4225
4226 emit_data->output[emit_data->chan] = out;
4227 }
4228
4229 static void set_tex_fetch_args(struct si_shader_context *ctx,
4230 struct lp_build_emit_data *emit_data,
4231 unsigned opcode, unsigned target,
4232 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4233 LLVMValueRef *param, unsigned count,
4234 unsigned dmask)
4235 {
4236 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4237 unsigned num_args;
4238 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4239
4240 /* Pad to power of two vector */
4241 while (count < util_next_power_of_two(count))
4242 param[count++] = LLVMGetUndef(ctx->i32);
4243
4244 /* Texture coordinates. */
4245 if (count > 1)
4246 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4247 else
4248 emit_data->args[0] = param[0];
4249
4250 /* Resource. */
4251 emit_data->args[1] = res_ptr;
4252 num_args = 2;
4253
4254 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4255 emit_data->dst_type = ctx->v4i32;
4256 else {
4257 emit_data->dst_type = ctx->v4f32;
4258
4259 emit_data->args[num_args++] = samp_ptr;
4260 }
4261
4262 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4263 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4264 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4265 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4266 tgsi_is_array_sampler(target)); /* da */
4267 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4268 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4269 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4270 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4271
4272 emit_data->arg_count = num_args;
4273 }
4274
4275 static const struct lp_build_tgsi_action tex_action;
4276
4277 enum desc_type {
4278 DESC_IMAGE,
4279 DESC_FMASK,
4280 DESC_SAMPLER
4281 };
4282
4283 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4284 {
4285 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4286 CONST_ADDR_SPACE);
4287 }
4288
4289 /**
4290 * Load an image view, fmask view. or sampler state descriptor.
4291 */
4292 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4293 LLVMValueRef list, LLVMValueRef index,
4294 enum desc_type type)
4295 {
4296 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4297 LLVMBuilderRef builder = gallivm->builder;
4298
4299 switch (type) {
4300 case DESC_IMAGE:
4301 /* The image is at [0:7]. */
4302 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4303 break;
4304 case DESC_FMASK:
4305 /* The FMASK is at [8:15]. */
4306 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4307 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4308 break;
4309 case DESC_SAMPLER:
4310 /* The sampler state is at [12:15]. */
4311 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4312 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4313 list = LLVMBuildPointerCast(builder, list,
4314 const_array(ctx->v4i32, 0), "");
4315 break;
4316 }
4317
4318 return build_indexed_load_const(ctx, list, index);
4319 }
4320
4321 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4322 LLVMValueRef index, enum desc_type type)
4323 {
4324 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4325 SI_PARAM_SAMPLERS);
4326
4327 return load_sampler_desc_custom(ctx, list, index, type);
4328 }
4329
4330 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4331 *
4332 * SI-CI:
4333 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4334 * filtering manually. The driver sets img7 to a mask clearing
4335 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4336 * s_and_b32 samp0, samp0, img7
4337 *
4338 * VI:
4339 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4340 */
4341 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4342 LLVMValueRef res, LLVMValueRef samp)
4343 {
4344 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4345 LLVMValueRef img7, samp0;
4346
4347 if (ctx->screen->b.chip_class >= VI)
4348 return samp;
4349
4350 img7 = LLVMBuildExtractElement(builder, res,
4351 LLVMConstInt(ctx->i32, 7, 0), "");
4352 samp0 = LLVMBuildExtractElement(builder, samp,
4353 LLVMConstInt(ctx->i32, 0, 0), "");
4354 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4355 return LLVMBuildInsertElement(builder, samp, samp0,
4356 LLVMConstInt(ctx->i32, 0, 0), "");
4357 }
4358
4359 static void tex_fetch_ptrs(
4360 struct lp_build_tgsi_context *bld_base,
4361 struct lp_build_emit_data *emit_data,
4362 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4363 {
4364 struct si_shader_context *ctx = si_shader_context(bld_base);
4365 const struct tgsi_full_instruction *inst = emit_data->inst;
4366 unsigned target = inst->Texture.Texture;
4367 unsigned sampler_src;
4368 unsigned sampler_index;
4369 LLVMValueRef index;
4370
4371 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4372 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4373
4374 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4375 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4376
4377 index = get_bounded_indirect_index(ctx,
4378 &reg->Indirect,
4379 reg->Register.Index,
4380 SI_NUM_SAMPLERS);
4381 } else {
4382 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4383 }
4384
4385 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4386
4387 if (target == TGSI_TEXTURE_2D_MSAA ||
4388 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4389 if (samp_ptr)
4390 *samp_ptr = NULL;
4391 if (fmask_ptr)
4392 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4393 } else {
4394 if (samp_ptr) {
4395 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4396 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4397 }
4398 if (fmask_ptr)
4399 *fmask_ptr = NULL;
4400 }
4401 }
4402
4403 static void txq_fetch_args(
4404 struct lp_build_tgsi_context *bld_base,
4405 struct lp_build_emit_data *emit_data)
4406 {
4407 struct si_shader_context *ctx = si_shader_context(bld_base);
4408 struct gallivm_state *gallivm = bld_base->base.gallivm;
4409 LLVMBuilderRef builder = gallivm->builder;
4410 const struct tgsi_full_instruction *inst = emit_data->inst;
4411 unsigned target = inst->Texture.Texture;
4412 LLVMValueRef res_ptr;
4413 LLVMValueRef address;
4414
4415 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4416
4417 if (target == TGSI_TEXTURE_BUFFER) {
4418 /* Read the size from the buffer descriptor directly. */
4419 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4420 emit_data->args[0] = get_buffer_size(bld_base, res);
4421 return;
4422 }
4423
4424 /* Textures - set the mip level. */
4425 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4426
4427 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4428 NULL, &address, 1, 0xf);
4429 }
4430
4431 static void txq_emit(const struct lp_build_tgsi_action *action,
4432 struct lp_build_tgsi_context *bld_base,
4433 struct lp_build_emit_data *emit_data)
4434 {
4435 struct lp_build_context *base = &bld_base->base;
4436 unsigned target = emit_data->inst->Texture.Texture;
4437
4438 if (target == TGSI_TEXTURE_BUFFER) {
4439 /* Just return the buffer size. */
4440 emit_data->output[emit_data->chan] = emit_data->args[0];
4441 return;
4442 }
4443
4444 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4445 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4446 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4447 LLVMReadNoneAttribute);
4448
4449 /* Divide the number of layers by 6 to get the number of cubes. */
4450 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4451 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4452 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4453 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4454 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4455
4456 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4457 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4458 z = LLVMBuildSDiv(builder, z, six, "");
4459
4460 emit_data->output[emit_data->chan] =
4461 LLVMBuildInsertElement(builder, v4, z, two, "");
4462 }
4463 }
4464
4465 static void tex_fetch_args(
4466 struct lp_build_tgsi_context *bld_base,
4467 struct lp_build_emit_data *emit_data)
4468 {
4469 struct si_shader_context *ctx = si_shader_context(bld_base);
4470 struct gallivm_state *gallivm = bld_base->base.gallivm;
4471 const struct tgsi_full_instruction *inst = emit_data->inst;
4472 unsigned opcode = inst->Instruction.Opcode;
4473 unsigned target = inst->Texture.Texture;
4474 LLVMValueRef coords[5], derivs[6];
4475 LLVMValueRef address[16];
4476 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4477 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4478 unsigned count = 0;
4479 unsigned chan;
4480 unsigned num_deriv_channels = 0;
4481 bool has_offset = inst->Texture.NumOffsets > 0;
4482 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4483 unsigned dmask = 0xf;
4484
4485 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4486
4487 if (target == TGSI_TEXTURE_BUFFER) {
4488 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4489
4490 /* Bitcast and truncate v8i32 to v16i8. */
4491 LLVMValueRef res = res_ptr;
4492 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4493 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4494 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4495
4496 emit_data->dst_type = ctx->v4f32;
4497 emit_data->args[0] = res;
4498 emit_data->args[1] = bld_base->uint_bld.zero;
4499 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4500 emit_data->arg_count = 3;
4501 return;
4502 }
4503
4504 /* Fetch and project texture coordinates */
4505 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4506 for (chan = 0; chan < 3; chan++ ) {
4507 coords[chan] = lp_build_emit_fetch(bld_base,
4508 emit_data->inst, 0,
4509 chan);
4510 if (opcode == TGSI_OPCODE_TXP)
4511 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4512 TGSI_OPCODE_DIV,
4513 coords[chan],
4514 coords[3]);
4515 }
4516
4517 if (opcode == TGSI_OPCODE_TXP)
4518 coords[3] = bld_base->base.one;
4519
4520 /* Pack offsets. */
4521 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4522 /* The offsets are six-bit signed integers packed like this:
4523 * X=[5:0], Y=[13:8], and Z=[21:16].
4524 */
4525 LLVMValueRef offset[3], pack;
4526
4527 assert(inst->Texture.NumOffsets == 1);
4528
4529 for (chan = 0; chan < 3; chan++) {
4530 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4531 emit_data->inst, 0, chan);
4532 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4533 lp_build_const_int32(gallivm, 0x3f), "");
4534 if (chan)
4535 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4536 lp_build_const_int32(gallivm, chan*8), "");
4537 }
4538
4539 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4540 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4541 address[count++] = pack;
4542 }
4543
4544 /* Pack LOD bias value */
4545 if (opcode == TGSI_OPCODE_TXB)
4546 address[count++] = coords[3];
4547 if (opcode == TGSI_OPCODE_TXB2)
4548 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4549
4550 /* Pack depth comparison value */
4551 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4552 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4553 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4554 } else {
4555 assert(ref_pos >= 0);
4556 address[count++] = coords[ref_pos];
4557 }
4558 }
4559
4560 /* Pack user derivatives */
4561 if (opcode == TGSI_OPCODE_TXD) {
4562 int param, num_src_deriv_channels;
4563
4564 switch (target) {
4565 case TGSI_TEXTURE_3D:
4566 num_src_deriv_channels = 3;
4567 num_deriv_channels = 3;
4568 break;
4569 case TGSI_TEXTURE_2D:
4570 case TGSI_TEXTURE_SHADOW2D:
4571 case TGSI_TEXTURE_RECT:
4572 case TGSI_TEXTURE_SHADOWRECT:
4573 case TGSI_TEXTURE_2D_ARRAY:
4574 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4575 num_src_deriv_channels = 2;
4576 num_deriv_channels = 2;
4577 break;
4578 case TGSI_TEXTURE_CUBE:
4579 case TGSI_TEXTURE_SHADOWCUBE:
4580 case TGSI_TEXTURE_CUBE_ARRAY:
4581 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4582 /* Cube derivatives will be converted to 2D. */
4583 num_src_deriv_channels = 3;
4584 num_deriv_channels = 2;
4585 break;
4586 case TGSI_TEXTURE_1D:
4587 case TGSI_TEXTURE_SHADOW1D:
4588 case TGSI_TEXTURE_1D_ARRAY:
4589 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4590 num_src_deriv_channels = 1;
4591 num_deriv_channels = 1;
4592 break;
4593 default:
4594 unreachable("invalid target");
4595 }
4596
4597 for (param = 0; param < 2; param++)
4598 for (chan = 0; chan < num_src_deriv_channels; chan++)
4599 derivs[param * num_src_deriv_channels + chan] =
4600 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4601 }
4602
4603 if (target == TGSI_TEXTURE_CUBE ||
4604 target == TGSI_TEXTURE_CUBE_ARRAY ||
4605 target == TGSI_TEXTURE_SHADOWCUBE ||
4606 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4607 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4608
4609 if (opcode == TGSI_OPCODE_TXD)
4610 for (int i = 0; i < num_deriv_channels * 2; i++)
4611 address[count++] = derivs[i];
4612
4613 /* Pack texture coordinates */
4614 address[count++] = coords[0];
4615 if (num_coords > 1)
4616 address[count++] = coords[1];
4617 if (num_coords > 2)
4618 address[count++] = coords[2];
4619
4620 /* Pack LOD or sample index */
4621 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4622 address[count++] = coords[3];
4623 else if (opcode == TGSI_OPCODE_TXL2)
4624 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4625
4626 if (count > 16) {
4627 assert(!"Cannot handle more than 16 texture address parameters");
4628 count = 16;
4629 }
4630
4631 for (chan = 0; chan < count; chan++ ) {
4632 address[chan] = LLVMBuildBitCast(gallivm->builder,
4633 address[chan], ctx->i32, "");
4634 }
4635
4636 /* Adjust the sample index according to FMASK.
4637 *
4638 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4639 * which is the identity mapping. Each nibble says which physical sample
4640 * should be fetched to get that sample.
4641 *
4642 * For example, 0x11111100 means there are only 2 samples stored and
4643 * the second sample covers 3/4 of the pixel. When reading samples 0
4644 * and 1, return physical sample 0 (determined by the first two 0s
4645 * in FMASK), otherwise return physical sample 1.
4646 *
4647 * The sample index should be adjusted as follows:
4648 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4649 */
4650 if (target == TGSI_TEXTURE_2D_MSAA ||
4651 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4652 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4653 struct lp_build_emit_data txf_emit_data = *emit_data;
4654 LLVMValueRef txf_address[4];
4655 unsigned txf_count = count;
4656 struct tgsi_full_instruction inst = {};
4657
4658 memcpy(txf_address, address, sizeof(txf_address));
4659
4660 if (target == TGSI_TEXTURE_2D_MSAA) {
4661 txf_address[2] = bld_base->uint_bld.zero;
4662 }
4663 txf_address[3] = bld_base->uint_bld.zero;
4664
4665 /* Read FMASK using TXF. */
4666 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4667 inst.Texture.Texture = target;
4668 txf_emit_data.inst = &inst;
4669 txf_emit_data.chan = 0;
4670 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4671 target, fmask_ptr, NULL,
4672 txf_address, txf_count, 0xf);
4673 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4674
4675 /* Initialize some constants. */
4676 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4677 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4678
4679 /* Apply the formula. */
4680 LLVMValueRef fmask =
4681 LLVMBuildExtractElement(gallivm->builder,
4682 txf_emit_data.output[0],
4683 uint_bld->zero, "");
4684
4685 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4686
4687 LLVMValueRef sample_index4 =
4688 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4689
4690 LLVMValueRef shifted_fmask =
4691 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4692
4693 LLVMValueRef final_sample =
4694 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4695
4696 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4697 * resource descriptor is 0 (invalid),
4698 */
4699 LLVMValueRef fmask_desc =
4700 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4701 ctx->v8i32, "");
4702
4703 LLVMValueRef fmask_word1 =
4704 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4705 uint_bld->one, "");
4706
4707 LLVMValueRef word1_is_nonzero =
4708 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4709 fmask_word1, uint_bld->zero, "");
4710
4711 /* Replace the MSAA sample index. */
4712 address[sample_chan] =
4713 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4714 final_sample, address[sample_chan], "");
4715 }
4716
4717 if (opcode == TGSI_OPCODE_TXF) {
4718 /* add tex offsets */
4719 if (inst->Texture.NumOffsets) {
4720 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4721 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4722 const struct tgsi_texture_offset *off = inst->TexOffsets;
4723
4724 assert(inst->Texture.NumOffsets == 1);
4725
4726 switch (target) {
4727 case TGSI_TEXTURE_3D:
4728 address[2] = lp_build_add(uint_bld, address[2],
4729 bld->immediates[off->Index][off->SwizzleZ]);
4730 /* fall through */
4731 case TGSI_TEXTURE_2D:
4732 case TGSI_TEXTURE_SHADOW2D:
4733 case TGSI_TEXTURE_RECT:
4734 case TGSI_TEXTURE_SHADOWRECT:
4735 case TGSI_TEXTURE_2D_ARRAY:
4736 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4737 address[1] =
4738 lp_build_add(uint_bld, address[1],
4739 bld->immediates[off->Index][off->SwizzleY]);
4740 /* fall through */
4741 case TGSI_TEXTURE_1D:
4742 case TGSI_TEXTURE_SHADOW1D:
4743 case TGSI_TEXTURE_1D_ARRAY:
4744 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4745 address[0] =
4746 lp_build_add(uint_bld, address[0],
4747 bld->immediates[off->Index][off->SwizzleX]);
4748 break;
4749 /* texture offsets do not apply to other texture targets */
4750 }
4751 }
4752 }
4753
4754 if (opcode == TGSI_OPCODE_TG4) {
4755 unsigned gather_comp = 0;
4756
4757 /* DMASK was repurposed for GATHER4. 4 components are always
4758 * returned and DMASK works like a swizzle - it selects
4759 * the component to fetch. The only valid DMASK values are
4760 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4761 * (red,red,red,red) etc.) The ISA document doesn't mention
4762 * this.
4763 */
4764
4765 /* Get the component index from src1.x for Gather4. */
4766 if (!tgsi_is_shadow_target(target)) {
4767 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4768 LLVMValueRef comp_imm;
4769 struct tgsi_src_register src1 = inst->Src[1].Register;
4770
4771 assert(src1.File == TGSI_FILE_IMMEDIATE);
4772
4773 comp_imm = imms[src1.Index][src1.SwizzleX];
4774 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4775 gather_comp = CLAMP(gather_comp, 0, 3);
4776 }
4777
4778 dmask = 1 << gather_comp;
4779 }
4780
4781 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4782 samp_ptr, address, count, dmask);
4783 }
4784
4785 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4786 * incorrectly forces nearest filtering if the texture format is integer.
4787 * The only effect it has on Gather4, which always returns 4 texels for
4788 * bilinear filtering, is that the final coordinates are off by 0.5 of
4789 * the texel size.
4790 *
4791 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4792 * or (0.5 / size) from the normalized coordinates.
4793 */
4794 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4795 struct lp_build_emit_data *emit_data,
4796 const char *intr_name,
4797 unsigned coord_vgpr_index)
4798 {
4799 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4800 LLVMValueRef coord = emit_data->args[0];
4801 LLVMValueRef half_texel[2];
4802 int c;
4803
4804 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4805 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4806 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4807 } else {
4808 struct tgsi_full_instruction txq_inst = {};
4809 struct lp_build_emit_data txq_emit_data = {};
4810
4811 /* Query the texture size. */
4812 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4813 txq_emit_data.inst = &txq_inst;
4814 txq_emit_data.dst_type = ctx->v4i32;
4815 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4816 txq_inst.Texture.Texture,
4817 emit_data->args[1], NULL,
4818 &ctx->radeon_bld.soa.bld_base.uint_bld.zero,
4819 1, 0xf);
4820 txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data);
4821
4822 /* Compute -0.5 / size. */
4823 for (c = 0; c < 2; c++) {
4824 half_texel[c] =
4825 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4826 LLVMConstInt(ctx->i32, c, 0), "");
4827 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4828 half_texel[c] =
4829 lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base,
4830 TGSI_OPCODE_RCP, half_texel[c]);
4831 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4832 LLVMConstReal(ctx->f32, -0.5), "");
4833 }
4834 }
4835
4836 for (c = 0; c < 2; c++) {
4837 LLVMValueRef tmp;
4838 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4839
4840 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4841 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4842 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4843 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4844 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4845 }
4846
4847 emit_data->args[0] = coord;
4848 emit_data->output[emit_data->chan] =
4849 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4850 emit_data->args, emit_data->arg_count,
4851 LLVMReadNoneAttribute);
4852 }
4853
4854 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4855 struct lp_build_tgsi_context *bld_base,
4856 struct lp_build_emit_data *emit_data)
4857 {
4858 struct si_shader_context *ctx = si_shader_context(bld_base);
4859 struct lp_build_context *base = &bld_base->base;
4860 const struct tgsi_full_instruction *inst = emit_data->inst;
4861 unsigned opcode = inst->Instruction.Opcode;
4862 unsigned target = inst->Texture.Texture;
4863 char intr_name[127];
4864 bool has_offset = inst->Texture.NumOffsets > 0;
4865 bool is_shadow = tgsi_is_shadow_target(target);
4866 char type[64];
4867 const char *name = "llvm.SI.image.sample";
4868 const char *infix = "";
4869
4870 if (target == TGSI_TEXTURE_BUFFER) {
4871 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4872 base->gallivm->builder,
4873 "llvm.SI.vs.load.input", emit_data->dst_type,
4874 emit_data->args, emit_data->arg_count,
4875 LLVMReadNoneAttribute);
4876 return;
4877 }
4878
4879 switch (opcode) {
4880 case TGSI_OPCODE_TXF:
4881 name = target == TGSI_TEXTURE_2D_MSAA ||
4882 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4883 "llvm.SI.image.load" :
4884 "llvm.SI.image.load.mip";
4885 is_shadow = false;
4886 has_offset = false;
4887 break;
4888 case TGSI_OPCODE_LODQ:
4889 name = "llvm.SI.getlod";
4890 is_shadow = false;
4891 has_offset = false;
4892 break;
4893 case TGSI_OPCODE_TEX:
4894 case TGSI_OPCODE_TEX2:
4895 case TGSI_OPCODE_TXP:
4896 if (ctx->type != PIPE_SHADER_FRAGMENT)
4897 infix = ".lz";
4898 break;
4899 case TGSI_OPCODE_TXB:
4900 case TGSI_OPCODE_TXB2:
4901 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4902 infix = ".b";
4903 break;
4904 case TGSI_OPCODE_TXL:
4905 case TGSI_OPCODE_TXL2:
4906 infix = ".l";
4907 break;
4908 case TGSI_OPCODE_TXD:
4909 infix = ".d";
4910 break;
4911 case TGSI_OPCODE_TG4:
4912 name = "llvm.SI.gather4";
4913 infix = ".lz";
4914 break;
4915 default:
4916 assert(0);
4917 return;
4918 }
4919
4920 /* Add the type and suffixes .c, .o if needed. */
4921 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4922 sprintf(intr_name, "%s%s%s%s.%s",
4923 name, is_shadow ? ".c" : "", infix,
4924 has_offset ? ".o" : "", type);
4925
4926 /* The hardware needs special lowering for Gather4 with integer formats. */
4927 if (opcode == TGSI_OPCODE_TG4) {
4928 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4929 /* This will also work with non-constant indexing because of how
4930 * glsl_to_tgsi works and we intent to preserve that behavior.
4931 */
4932 const unsigned src_idx = 2;
4933 unsigned sampler = inst->Src[src_idx].Register.Index;
4934
4935 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4936
4937 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4938 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4939 /* Texture coordinates start after:
4940 * {offset, bias, z-compare, derivatives}
4941 * Only the offset and z-compare can occur here.
4942 */
4943 si_lower_gather4_integer(ctx, emit_data, intr_name,
4944 (int)has_offset + (int)is_shadow);
4945 return;
4946 }
4947 }
4948
4949 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4950 base->gallivm->builder, intr_name, emit_data->dst_type,
4951 emit_data->args, emit_data->arg_count,
4952 LLVMReadNoneAttribute);
4953 }
4954
4955 static void si_llvm_emit_txqs(
4956 const struct lp_build_tgsi_action *action,
4957 struct lp_build_tgsi_context *bld_base,
4958 struct lp_build_emit_data *emit_data)
4959 {
4960 struct si_shader_context *ctx = si_shader_context(bld_base);
4961 struct gallivm_state *gallivm = bld_base->base.gallivm;
4962 LLVMBuilderRef builder = gallivm->builder;
4963 LLVMValueRef res, samples;
4964 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4965
4966 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4967
4968
4969 /* Read the samples from the descriptor directly. */
4970 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4971 samples = LLVMBuildExtractElement(
4972 builder, res,
4973 lp_build_const_int32(gallivm, 3), "");
4974 samples = LLVMBuildLShr(builder, samples,
4975 lp_build_const_int32(gallivm, 16), "");
4976 samples = LLVMBuildAnd(builder, samples,
4977 lp_build_const_int32(gallivm, 0xf), "");
4978 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4979 samples, "");
4980
4981 emit_data->output[emit_data->chan] = samples;
4982 }
4983
4984 /*
4985 * SI implements derivatives using the local data store (LDS)
4986 * All writes to the LDS happen in all executing threads at
4987 * the same time. TID is the Thread ID for the current
4988 * thread and is a value between 0 and 63, representing
4989 * the thread's position in the wavefront.
4990 *
4991 * For the pixel shader threads are grouped into quads of four pixels.
4992 * The TIDs of the pixels of a quad are:
4993 *
4994 * +------+------+
4995 * |4n + 0|4n + 1|
4996 * +------+------+
4997 * |4n + 2|4n + 3|
4998 * +------+------+
4999 *
5000 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
5001 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5002 * the current pixel's column, and masking with 0xfffffffe yields the TID
5003 * of the left pixel of the current pixel's row.
5004 *
5005 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5006 * adding 2 yields the TID of the pixel below the top pixel.
5007 */
5008 /* masks for thread ID. */
5009 #define TID_MASK_TOP_LEFT 0xfffffffc
5010 #define TID_MASK_TOP 0xfffffffd
5011 #define TID_MASK_LEFT 0xfffffffe
5012
5013 static void si_llvm_emit_ddxy(
5014 const struct lp_build_tgsi_action *action,
5015 struct lp_build_tgsi_context *bld_base,
5016 struct lp_build_emit_data *emit_data)
5017 {
5018 struct si_shader_context *ctx = si_shader_context(bld_base);
5019 struct gallivm_state *gallivm = bld_base->base.gallivm;
5020 unsigned opcode = emit_data->info->opcode;
5021 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
5022 int idx;
5023 unsigned mask;
5024
5025 thread_id = get_thread_id(ctx);
5026
5027 if (opcode == TGSI_OPCODE_DDX_FINE)
5028 mask = TID_MASK_LEFT;
5029 else if (opcode == TGSI_OPCODE_DDY_FINE)
5030 mask = TID_MASK_TOP;
5031 else
5032 mask = TID_MASK_TOP_LEFT;
5033
5034 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5035 lp_build_const_int32(gallivm, mask), "");
5036
5037 /* for DDX we want to next X pixel, DDY next Y pixel. */
5038 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5039 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5040 lp_build_const_int32(gallivm, idx), "");
5041
5042 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5043
5044 if (ctx->screen->has_ds_bpermute) {
5045 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5046 lp_build_const_int32(gallivm, 4), "");
5047 args[1] = val;
5048 tl = lp_build_intrinsic(gallivm->builder,
5049 "llvm.amdgcn.ds.bpermute", ctx->i32,
5050 args, 2, LLVMReadNoneAttribute);
5051
5052 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5053 lp_build_const_int32(gallivm, 4), "");
5054 trbl = lp_build_intrinsic(gallivm->builder,
5055 "llvm.amdgcn.ds.bpermute", ctx->i32,
5056 args, 2, LLVMReadNoneAttribute);
5057 } else {
5058 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5059
5060 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5061 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5062 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5063
5064 LLVMBuildStore(gallivm->builder, val, store_ptr);
5065 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5066 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5067 }
5068
5069 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5070 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5071
5072 emit_data->output[emit_data->chan] =
5073 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5074 }
5075
5076 /*
5077 * this takes an I,J coordinate pair,
5078 * and works out the X and Y derivatives.
5079 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5080 */
5081 static LLVMValueRef si_llvm_emit_ddxy_interp(
5082 struct lp_build_tgsi_context *bld_base,
5083 LLVMValueRef interp_ij)
5084 {
5085 struct si_shader_context *ctx = si_shader_context(bld_base);
5086 struct gallivm_state *gallivm = bld_base->base.gallivm;
5087 LLVMValueRef result[4], a;
5088 unsigned i;
5089
5090 for (i = 0; i < 2; i++) {
5091 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5092 LLVMConstInt(ctx->i32, i, 0), "");
5093 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5094 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5095 }
5096
5097 return lp_build_gather_values(gallivm, result, 4);
5098 }
5099
5100 static void interp_fetch_args(
5101 struct lp_build_tgsi_context *bld_base,
5102 struct lp_build_emit_data *emit_data)
5103 {
5104 struct si_shader_context *ctx = si_shader_context(bld_base);
5105 struct gallivm_state *gallivm = bld_base->base.gallivm;
5106 const struct tgsi_full_instruction *inst = emit_data->inst;
5107
5108 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5109 /* offset is in second src, first two channels */
5110 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5111 emit_data->inst, 1,
5112 TGSI_CHAN_X);
5113 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5114 emit_data->inst, 1,
5115 TGSI_CHAN_Y);
5116 emit_data->arg_count = 2;
5117 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5118 LLVMValueRef sample_position;
5119 LLVMValueRef sample_id;
5120 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5121
5122 /* fetch sample ID, then fetch its sample position,
5123 * and place into first two channels.
5124 */
5125 sample_id = lp_build_emit_fetch(bld_base,
5126 emit_data->inst, 1, TGSI_CHAN_X);
5127 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5128 ctx->i32, "");
5129 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5130
5131 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5132 sample_position,
5133 lp_build_const_int32(gallivm, 0), "");
5134
5135 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5136 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5137 sample_position,
5138 lp_build_const_int32(gallivm, 1), "");
5139 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5140 emit_data->arg_count = 2;
5141 }
5142 }
5143
5144 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5145 struct lp_build_tgsi_context *bld_base,
5146 struct lp_build_emit_data *emit_data)
5147 {
5148 struct si_shader_context *ctx = si_shader_context(bld_base);
5149 struct si_shader *shader = ctx->shader;
5150 struct gallivm_state *gallivm = bld_base->base.gallivm;
5151 LLVMValueRef interp_param;
5152 const struct tgsi_full_instruction *inst = emit_data->inst;
5153 const char *intr_name;
5154 int input_index = inst->Src[0].Register.Index;
5155 int chan;
5156 int i;
5157 LLVMValueRef attr_number;
5158 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5159 int interp_param_idx;
5160 unsigned interp = shader->selector->info.input_interpolate[input_index];
5161 unsigned location;
5162
5163 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5164
5165 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5166 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5167 location = TGSI_INTERPOLATE_LOC_CENTER;
5168 else
5169 location = TGSI_INTERPOLATE_LOC_CENTROID;
5170
5171 interp_param_idx = lookup_interp_param_index(interp, location);
5172 if (interp_param_idx == -1)
5173 return;
5174 else if (interp_param_idx)
5175 interp_param = get_interp_param(ctx, interp_param_idx);
5176 else
5177 interp_param = NULL;
5178
5179 attr_number = lp_build_const_int32(gallivm, input_index);
5180
5181 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5182 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5183 LLVMValueRef ij_out[2];
5184 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5185
5186 /*
5187 * take the I then J parameters, and the DDX/Y for it, and
5188 * calculate the IJ inputs for the interpolator.
5189 * temp1 = ddx * offset/sample.x + I;
5190 * interp_param.I = ddy * offset/sample.y + temp1;
5191 * temp1 = ddx * offset/sample.x + J;
5192 * interp_param.J = ddy * offset/sample.y + temp1;
5193 */
5194 for (i = 0; i < 2; i++) {
5195 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5196 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5197 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5198 ddxy_out, ix_ll, "");
5199 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5200 ddxy_out, iy_ll, "");
5201 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5202 interp_param, ix_ll, "");
5203 LLVMValueRef temp1, temp2;
5204
5205 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5206 ctx->f32, "");
5207
5208 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5209
5210 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5211
5212 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5213
5214 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5215
5216 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5217 temp2, ctx->i32, "");
5218 }
5219 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5220 }
5221
5222 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5223 for (chan = 0; chan < 4; chan++) {
5224 LLVMValueRef args[4];
5225 LLVMValueRef llvm_chan;
5226 unsigned schan;
5227
5228 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5229 llvm_chan = lp_build_const_int32(gallivm, schan);
5230
5231 args[0] = llvm_chan;
5232 args[1] = attr_number;
5233 args[2] = params;
5234 args[3] = interp_param;
5235
5236 emit_data->output[chan] =
5237 lp_build_intrinsic(gallivm->builder, intr_name,
5238 ctx->f32, args, args[3] ? 4 : 3,
5239 LLVMReadNoneAttribute);
5240 }
5241 }
5242
5243 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5244 struct lp_build_emit_data *emit_data)
5245 {
5246 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5247 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5248 unsigned stream;
5249
5250 assert(src0.File == TGSI_FILE_IMMEDIATE);
5251
5252 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5253 return stream;
5254 }
5255
5256 /* Emit one vertex from the geometry shader */
5257 static void si_llvm_emit_vertex(
5258 const struct lp_build_tgsi_action *action,
5259 struct lp_build_tgsi_context *bld_base,
5260 struct lp_build_emit_data *emit_data)
5261 {
5262 struct si_shader_context *ctx = si_shader_context(bld_base);
5263 struct lp_build_context *uint = &bld_base->uint_bld;
5264 struct si_shader *shader = ctx->shader;
5265 struct tgsi_shader_info *info = &shader->selector->info;
5266 struct gallivm_state *gallivm = bld_base->base.gallivm;
5267 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5268 SI_PARAM_GS2VS_OFFSET);
5269 LLVMValueRef gs_next_vertex;
5270 LLVMValueRef can_emit, kill;
5271 LLVMValueRef args[2];
5272 unsigned chan;
5273 int i;
5274 unsigned stream;
5275
5276 stream = si_llvm_get_stream(bld_base, emit_data);
5277
5278 /* Write vertex attribute values to GSVS ring */
5279 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5280 ctx->gs_next_vertex[stream],
5281 "");
5282
5283 /* If this thread has already emitted the declared maximum number of
5284 * vertices, kill it: excessive vertex emissions are not supposed to
5285 * have any effect, and GS threads have no externally observable
5286 * effects other than emitting vertices.
5287 */
5288 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5289 lp_build_const_int32(gallivm,
5290 shader->selector->gs_max_out_vertices), "");
5291 kill = lp_build_select(&bld_base->base, can_emit,
5292 lp_build_const_float(gallivm, 1.0f),
5293 lp_build_const_float(gallivm, -1.0f));
5294
5295 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5296 ctx->voidt, &kill, 1, 0);
5297
5298 for (i = 0; i < info->num_outputs; i++) {
5299 LLVMValueRef *out_ptr =
5300 ctx->radeon_bld.soa.outputs[i];
5301
5302 for (chan = 0; chan < 4; chan++) {
5303 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5304 LLVMValueRef voffset =
5305 lp_build_const_int32(gallivm, (i * 4 + chan) *
5306 shader->selector->gs_max_out_vertices);
5307
5308 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5309 voffset = lp_build_mul_imm(uint, voffset, 4);
5310
5311 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5312
5313 build_tbuffer_store(ctx,
5314 ctx->gsvs_ring[stream],
5315 out_val, 1,
5316 voffset, soffset, 0,
5317 V_008F0C_BUF_DATA_FORMAT_32,
5318 V_008F0C_BUF_NUM_FORMAT_UINT,
5319 1, 0, 1, 1, 0);
5320 }
5321 }
5322 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5323 lp_build_const_int32(gallivm, 1));
5324
5325 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5326
5327 /* Signal vertex emission */
5328 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5329 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5330 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5331 ctx->voidt, args, 2, 0);
5332 }
5333
5334 /* Cut one primitive from the geometry shader */
5335 static void si_llvm_emit_primitive(
5336 const struct lp_build_tgsi_action *action,
5337 struct lp_build_tgsi_context *bld_base,
5338 struct lp_build_emit_data *emit_data)
5339 {
5340 struct si_shader_context *ctx = si_shader_context(bld_base);
5341 struct gallivm_state *gallivm = bld_base->base.gallivm;
5342 LLVMValueRef args[2];
5343 unsigned stream;
5344
5345 /* Signal primitive cut */
5346 stream = si_llvm_get_stream(bld_base, emit_data);
5347 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5348 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5349 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5350 ctx->voidt, args, 2, 0);
5351 }
5352
5353 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5354 struct lp_build_tgsi_context *bld_base,
5355 struct lp_build_emit_data *emit_data)
5356 {
5357 struct si_shader_context *ctx = si_shader_context(bld_base);
5358 struct gallivm_state *gallivm = bld_base->base.gallivm;
5359
5360 /* The real barrier instruction isn’t needed, because an entire patch
5361 * always fits into a single wave.
5362 */
5363 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5364 emit_optimization_barrier(ctx);
5365 return;
5366 }
5367
5368 lp_build_intrinsic(gallivm->builder,
5369 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5370 : "llvm.AMDGPU.barrier.local",
5371 ctx->voidt, NULL, 0, 0);
5372 }
5373
5374 static const struct lp_build_tgsi_action tex_action = {
5375 .fetch_args = tex_fetch_args,
5376 .emit = build_tex_intrinsic,
5377 };
5378
5379 static const struct lp_build_tgsi_action interp_action = {
5380 .fetch_args = interp_fetch_args,
5381 .emit = build_interp_intrinsic,
5382 };
5383
5384 static void si_create_function(struct si_shader_context *ctx,
5385 LLVMTypeRef *returns, unsigned num_returns,
5386 LLVMTypeRef *params, unsigned num_params,
5387 int last_sgpr)
5388 {
5389 int i;
5390
5391 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5392 params, num_params);
5393 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5394 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5395
5396 for (i = 0; i <= last_sgpr; ++i) {
5397 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5398
5399 /* The combination of:
5400 * - ByVal
5401 * - dereferenceable
5402 * - invariant.load
5403 * allows the optimization passes to move loads and reduces
5404 * SGPR spilling significantly.
5405 */
5406 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5407 LLVMAddAttribute(P, LLVMByValAttribute);
5408 lp_add_attr_dereferenceable(P, UINT64_MAX);
5409 } else
5410 LLVMAddAttribute(P, LLVMInRegAttribute);
5411 }
5412
5413 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5414 /* These were copied from some LLVM test. */
5415 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5416 "less-precise-fpmad",
5417 "true");
5418 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5419 "no-infs-fp-math",
5420 "true");
5421 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5422 "no-nans-fp-math",
5423 "true");
5424 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5425 "unsafe-fp-math",
5426 "true");
5427 }
5428 }
5429
5430 static void create_meta_data(struct si_shader_context *ctx)
5431 {
5432 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5433
5434 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5435 "invariant.load", 14);
5436 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5437 "range", 5);
5438 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5439 "amdgpu.uniform", 14);
5440
5441 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5442 }
5443
5444 static void declare_streamout_params(struct si_shader_context *ctx,
5445 struct pipe_stream_output_info *so,
5446 LLVMTypeRef *params, LLVMTypeRef i32,
5447 unsigned *num_params)
5448 {
5449 int i;
5450
5451 /* Streamout SGPRs. */
5452 if (so->num_outputs) {
5453 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5454 params[ctx->param_streamout_config = (*num_params)++] = i32;
5455 else
5456 ctx->param_streamout_config = ctx->param_tess_offchip;
5457
5458 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5459 }
5460 /* A streamout buffer offset is loaded if the stride is non-zero. */
5461 for (i = 0; i < 4; i++) {
5462 if (!so->stride[i])
5463 continue;
5464
5465 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5466 }
5467 }
5468
5469 static unsigned llvm_get_type_size(LLVMTypeRef type)
5470 {
5471 LLVMTypeKind kind = LLVMGetTypeKind(type);
5472
5473 switch (kind) {
5474 case LLVMIntegerTypeKind:
5475 return LLVMGetIntTypeWidth(type) / 8;
5476 case LLVMFloatTypeKind:
5477 return 4;
5478 case LLVMPointerTypeKind:
5479 return 8;
5480 case LLVMVectorTypeKind:
5481 return LLVMGetVectorSize(type) *
5482 llvm_get_type_size(LLVMGetElementType(type));
5483 default:
5484 assert(0);
5485 return 0;
5486 }
5487 }
5488
5489 static void declare_tess_lds(struct si_shader_context *ctx)
5490 {
5491 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5492 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5493 struct lp_build_context *uint = &bld_base->uint_bld;
5494
5495 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5496 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5497 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5498 "tess_lds");
5499 }
5500
5501 static void create_function(struct si_shader_context *ctx)
5502 {
5503 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5504 struct gallivm_state *gallivm = bld_base->base.gallivm;
5505 struct si_shader *shader = ctx->shader;
5506 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5507 LLVMTypeRef returns[16+32*4];
5508 unsigned i, last_sgpr, num_params, num_return_sgprs;
5509 unsigned num_returns = 0;
5510
5511 v3i32 = LLVMVectorType(ctx->i32, 3);
5512
5513 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5514 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5515 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5516 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5517 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5518
5519 switch (ctx->type) {
5520 case PIPE_SHADER_VERTEX:
5521 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5522 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5523 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5524 params[SI_PARAM_DRAWID] = ctx->i32;
5525 num_params = SI_PARAM_DRAWID+1;
5526
5527 if (shader->key.vs.as_es) {
5528 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5529 } else if (shader->key.vs.as_ls) {
5530 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5531 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5532 } else {
5533 if (ctx->is_gs_copy_shader) {
5534 num_params = SI_PARAM_RW_BUFFERS+1;
5535 } else {
5536 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5537 num_params = SI_PARAM_VS_STATE_BITS+1;
5538 }
5539
5540 /* The locations of the other parameters are assigned dynamically. */
5541 declare_streamout_params(ctx, &shader->selector->so,
5542 params, ctx->i32, &num_params);
5543 }
5544
5545 last_sgpr = num_params-1;
5546
5547 /* VGPRs */
5548 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5549 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5550 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5551 params[ctx->param_instance_id = num_params++] = ctx->i32;
5552
5553 if (!ctx->is_monolithic &&
5554 !ctx->is_gs_copy_shader) {
5555 /* Vertex load indices. */
5556 ctx->param_vertex_index0 = num_params;
5557
5558 for (i = 0; i < shader->selector->info.num_inputs; i++)
5559 params[num_params++] = ctx->i32;
5560
5561 /* PrimitiveID output. */
5562 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5563 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5564 returns[num_returns++] = ctx->f32;
5565 }
5566 break;
5567
5568 case PIPE_SHADER_TESS_CTRL:
5569 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5570 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5571 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5572 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5573 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5574 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5575 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5576
5577 /* VGPRs */
5578 params[SI_PARAM_PATCH_ID] = ctx->i32;
5579 params[SI_PARAM_REL_IDS] = ctx->i32;
5580 num_params = SI_PARAM_REL_IDS+1;
5581
5582 if (!ctx->is_monolithic) {
5583 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5584 * placed after the user SGPRs.
5585 */
5586 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5587 returns[num_returns++] = ctx->i32; /* SGPRs */
5588
5589 for (i = 0; i < 3; i++)
5590 returns[num_returns++] = ctx->f32; /* VGPRs */
5591 }
5592 break;
5593
5594 case PIPE_SHADER_TESS_EVAL:
5595 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5596 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5597
5598 if (shader->key.tes.as_es) {
5599 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5600 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5601 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5602 } else {
5603 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5604 declare_streamout_params(ctx, &shader->selector->so,
5605 params, ctx->i32, &num_params);
5606 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5607 }
5608 last_sgpr = num_params - 1;
5609
5610 /* VGPRs */
5611 params[ctx->param_tes_u = num_params++] = ctx->f32;
5612 params[ctx->param_tes_v = num_params++] = ctx->f32;
5613 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5614 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5615
5616 /* PrimitiveID output. */
5617 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5618 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5619 returns[num_returns++] = ctx->f32;
5620 break;
5621
5622 case PIPE_SHADER_GEOMETRY:
5623 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5624 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5625 last_sgpr = SI_PARAM_GS_WAVE_ID;
5626
5627 /* VGPRs */
5628 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5629 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5630 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5631 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5632 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5633 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5634 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5635 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5636 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5637 break;
5638
5639 case PIPE_SHADER_FRAGMENT:
5640 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5641 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5642 last_sgpr = SI_PARAM_PRIM_MASK;
5643 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5644 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5645 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5646 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5647 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5648 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5649 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5650 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5651 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5652 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5653 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5654 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5655 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5656 params[SI_PARAM_ANCILLARY] = ctx->i32;
5657 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5658 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5659 num_params = SI_PARAM_POS_FIXED_PT+1;
5660
5661 if (!ctx->is_monolithic) {
5662 /* Color inputs from the prolog. */
5663 if (shader->selector->info.colors_read) {
5664 unsigned num_color_elements =
5665 util_bitcount(shader->selector->info.colors_read);
5666
5667 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5668 for (i = 0; i < num_color_elements; i++)
5669 params[num_params++] = ctx->f32;
5670 }
5671
5672 /* Outputs for the epilog. */
5673 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5674 num_returns =
5675 num_return_sgprs +
5676 util_bitcount(shader->selector->info.colors_written) * 4 +
5677 shader->selector->info.writes_z +
5678 shader->selector->info.writes_stencil +
5679 shader->selector->info.writes_samplemask +
5680 1 /* SampleMaskIn */;
5681
5682 num_returns = MAX2(num_returns,
5683 num_return_sgprs +
5684 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5685
5686 for (i = 0; i < num_return_sgprs; i++)
5687 returns[i] = ctx->i32;
5688 for (; i < num_returns; i++)
5689 returns[i] = ctx->f32;
5690 }
5691 break;
5692
5693 case PIPE_SHADER_COMPUTE:
5694 params[SI_PARAM_GRID_SIZE] = v3i32;
5695 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5696 params[SI_PARAM_BLOCK_ID] = v3i32;
5697 last_sgpr = SI_PARAM_BLOCK_ID;
5698
5699 params[SI_PARAM_THREAD_ID] = v3i32;
5700 num_params = SI_PARAM_THREAD_ID + 1;
5701 break;
5702 default:
5703 assert(0 && "unimplemented shader");
5704 return;
5705 }
5706
5707 assert(num_params <= ARRAY_SIZE(params));
5708
5709 si_create_function(ctx, returns, num_returns, params,
5710 num_params, last_sgpr);
5711
5712 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5713 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5714 !ctx->is_monolithic) {
5715 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5716 "InitialPSInputAddr",
5717 S_0286D0_PERSP_SAMPLE_ENA(1) |
5718 S_0286D0_PERSP_CENTER_ENA(1) |
5719 S_0286D0_PERSP_CENTROID_ENA(1) |
5720 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5721 S_0286D0_LINEAR_CENTER_ENA(1) |
5722 S_0286D0_LINEAR_CENTROID_ENA(1) |
5723 S_0286D0_FRONT_FACE_ENA(1) |
5724 S_0286D0_POS_FIXED_PT_ENA(1));
5725 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5726 const unsigned *properties = shader->selector->info.properties;
5727 unsigned max_work_group_size =
5728 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5729 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5730 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5731
5732 if (!max_work_group_size) {
5733 /* This is a variable group size compute shader,
5734 * compile it for the maximum possible group size.
5735 */
5736 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5737 }
5738
5739 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5740 "amdgpu-max-work-group-size",
5741 max_work_group_size);
5742 }
5743
5744 shader->info.num_input_sgprs = 0;
5745 shader->info.num_input_vgprs = 0;
5746
5747 for (i = 0; i <= last_sgpr; ++i)
5748 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5749
5750 /* Unused fragment shader inputs are eliminated by the compiler,
5751 * so we don't know yet how many there will be.
5752 */
5753 if (ctx->type != PIPE_SHADER_FRAGMENT)
5754 for (; i < num_params; ++i)
5755 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5756
5757 if (!ctx->screen->has_ds_bpermute &&
5758 bld_base->info &&
5759 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5760 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5761 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5762 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5763 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5764 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5765 ctx->lds =
5766 LLVMAddGlobalInAddressSpace(gallivm->module,
5767 LLVMArrayType(ctx->i32, 64),
5768 "ddxy_lds",
5769 LOCAL_ADDR_SPACE);
5770
5771 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5772 ctx->type == PIPE_SHADER_TESS_CTRL ||
5773 ctx->type == PIPE_SHADER_TESS_EVAL)
5774 declare_tess_lds(ctx);
5775 }
5776
5777 /**
5778 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5779 * for later use.
5780 */
5781 static void preload_ring_buffers(struct si_shader_context *ctx)
5782 {
5783 struct gallivm_state *gallivm =
5784 ctx->radeon_bld.soa.bld_base.base.gallivm;
5785
5786 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5787 SI_PARAM_RW_BUFFERS);
5788
5789 if ((ctx->type == PIPE_SHADER_VERTEX &&
5790 ctx->shader->key.vs.as_es) ||
5791 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5792 ctx->shader->key.tes.as_es) ||
5793 ctx->type == PIPE_SHADER_GEOMETRY) {
5794 unsigned ring =
5795 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5796 : SI_ES_RING_ESGS;
5797 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5798
5799 ctx->esgs_ring =
5800 build_indexed_load_const(ctx, buf_ptr, offset);
5801 }
5802
5803 if (ctx->is_gs_copy_shader) {
5804 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5805
5806 ctx->gsvs_ring[0] =
5807 build_indexed_load_const(ctx, buf_ptr, offset);
5808 }
5809 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5810 int i;
5811 for (i = 0; i < 4; i++) {
5812 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5813
5814 ctx->gsvs_ring[i] =
5815 build_indexed_load_const(ctx, buf_ptr, offset);
5816 }
5817 }
5818 }
5819
5820 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5821 LLVMValueRef param_rw_buffers,
5822 unsigned param_pos_fixed_pt)
5823 {
5824 struct lp_build_tgsi_context *bld_base =
5825 &ctx->radeon_bld.soa.bld_base;
5826 struct gallivm_state *gallivm = bld_base->base.gallivm;
5827 LLVMBuilderRef builder = gallivm->builder;
5828 LLVMValueRef slot, desc, offset, row, bit, address[2];
5829
5830 /* Use the fixed-point gl_FragCoord input.
5831 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5832 * per coordinate to get the repeating effect.
5833 */
5834 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5835 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5836
5837 /* Load the buffer descriptor. */
5838 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5839 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5840
5841 /* The stipple pattern is 32x32, each row has 32 bits. */
5842 offset = LLVMBuildMul(builder, address[1],
5843 LLVMConstInt(ctx->i32, 4, 0), "");
5844 row = buffer_load_const(ctx, desc, offset);
5845 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5846 bit = LLVMBuildLShr(builder, row, address[0], "");
5847 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5848
5849 /* The intrinsic kills the thread if arg < 0. */
5850 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5851 LLVMConstReal(ctx->f32, -1), "");
5852 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5853 }
5854
5855 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5856 struct si_shader_config *conf,
5857 unsigned symbol_offset)
5858 {
5859 unsigned i;
5860 const unsigned char *config =
5861 radeon_shader_binary_config_start(binary, symbol_offset);
5862 bool really_needs_scratch = false;
5863
5864 /* LLVM adds SGPR spills to the scratch size.
5865 * Find out if we really need the scratch buffer.
5866 */
5867 for (i = 0; i < binary->reloc_count; i++) {
5868 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5869
5870 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5871 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5872 really_needs_scratch = true;
5873 break;
5874 }
5875 }
5876
5877 /* XXX: We may be able to emit some of these values directly rather than
5878 * extracting fields to be emitted later.
5879 */
5880
5881 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5882 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5883 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5884 switch (reg) {
5885 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5886 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5887 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5888 case R_00B848_COMPUTE_PGM_RSRC1:
5889 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5890 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5891 conf->float_mode = G_00B028_FLOAT_MODE(value);
5892 conf->rsrc1 = value;
5893 break;
5894 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5895 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5896 break;
5897 case R_00B84C_COMPUTE_PGM_RSRC2:
5898 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5899 conf->rsrc2 = value;
5900 break;
5901 case R_0286CC_SPI_PS_INPUT_ENA:
5902 conf->spi_ps_input_ena = value;
5903 break;
5904 case R_0286D0_SPI_PS_INPUT_ADDR:
5905 conf->spi_ps_input_addr = value;
5906 break;
5907 case R_0286E8_SPI_TMPRING_SIZE:
5908 case R_00B860_COMPUTE_TMPRING_SIZE:
5909 /* WAVESIZE is in units of 256 dwords. */
5910 if (really_needs_scratch)
5911 conf->scratch_bytes_per_wave =
5912 G_00B860_WAVESIZE(value) * 256 * 4;
5913 break;
5914 case 0x4: /* SPILLED_SGPRS */
5915 conf->spilled_sgprs = value;
5916 break;
5917 case 0x8: /* SPILLED_VGPRS */
5918 conf->spilled_vgprs = value;
5919 break;
5920 default:
5921 {
5922 static bool printed;
5923
5924 if (!printed) {
5925 fprintf(stderr, "Warning: LLVM emitted unknown "
5926 "config register: 0x%x\n", reg);
5927 printed = true;
5928 }
5929 }
5930 break;
5931 }
5932 }
5933
5934 if (!conf->spi_ps_input_addr)
5935 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5936 }
5937
5938 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5939 struct si_shader *shader,
5940 struct si_shader_config *config,
5941 uint64_t scratch_va)
5942 {
5943 unsigned i;
5944 uint32_t scratch_rsrc_dword0 = scratch_va;
5945 uint32_t scratch_rsrc_dword1 =
5946 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5947
5948 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5949 * correctly.
5950 */
5951 if (HAVE_LLVM >= 0x0309)
5952 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5953 else
5954 scratch_rsrc_dword1 |=
5955 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5956
5957 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5958 const struct radeon_shader_reloc *reloc =
5959 &shader->binary.relocs[i];
5960 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5961 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5962 &scratch_rsrc_dword0, 4);
5963 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5964 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5965 &scratch_rsrc_dword1, 4);
5966 }
5967 }
5968 }
5969
5970 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5971 {
5972 unsigned size = shader->binary.code_size;
5973
5974 if (shader->prolog)
5975 size += shader->prolog->binary.code_size;
5976 if (shader->epilog)
5977 size += shader->epilog->binary.code_size;
5978 return size;
5979 }
5980
5981 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5982 {
5983 const struct radeon_shader_binary *prolog =
5984 shader->prolog ? &shader->prolog->binary : NULL;
5985 const struct radeon_shader_binary *epilog =
5986 shader->epilog ? &shader->epilog->binary : NULL;
5987 const struct radeon_shader_binary *mainb = &shader->binary;
5988 unsigned bo_size = si_get_shader_binary_size(shader) +
5989 (!epilog ? mainb->rodata_size : 0);
5990 unsigned char *ptr;
5991
5992 assert(!prolog || !prolog->rodata_size);
5993 assert((!prolog && !epilog) || !mainb->rodata_size);
5994 assert(!epilog || !epilog->rodata_size);
5995
5996 r600_resource_reference(&shader->bo, NULL);
5997 shader->bo = si_resource_create_custom(&sscreen->b.b,
5998 PIPE_USAGE_IMMUTABLE,
5999 bo_size);
6000 if (!shader->bo)
6001 return -ENOMEM;
6002
6003 /* Upload. */
6004 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6005 PIPE_TRANSFER_READ_WRITE);
6006
6007 if (prolog) {
6008 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6009 ptr += prolog->code_size;
6010 }
6011
6012 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6013 ptr += mainb->code_size;
6014
6015 if (epilog)
6016 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6017 else if (mainb->rodata_size > 0)
6018 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6019
6020 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6021 return 0;
6022 }
6023
6024 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6025 struct pipe_debug_callback *debug,
6026 const char *name, FILE *file)
6027 {
6028 char *line, *p;
6029 unsigned i, count;
6030
6031 if (binary->disasm_string) {
6032 fprintf(file, "Shader %s disassembly:\n", name);
6033 fprintf(file, "%s", binary->disasm_string);
6034
6035 if (debug && debug->debug_message) {
6036 /* Very long debug messages are cut off, so send the
6037 * disassembly one line at a time. This causes more
6038 * overhead, but on the plus side it simplifies
6039 * parsing of resulting logs.
6040 */
6041 pipe_debug_message(debug, SHADER_INFO,
6042 "Shader Disassembly Begin");
6043
6044 line = binary->disasm_string;
6045 while (*line) {
6046 p = util_strchrnul(line, '\n');
6047 count = p - line;
6048
6049 if (count) {
6050 pipe_debug_message(debug, SHADER_INFO,
6051 "%.*s", count, line);
6052 }
6053
6054 if (!*p)
6055 break;
6056 line = p + 1;
6057 }
6058
6059 pipe_debug_message(debug, SHADER_INFO,
6060 "Shader Disassembly End");
6061 }
6062 } else {
6063 fprintf(file, "Shader %s binary:\n", name);
6064 for (i = 0; i < binary->code_size; i += 4) {
6065 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6066 binary->code[i + 3], binary->code[i + 2],
6067 binary->code[i + 1], binary->code[i]);
6068 }
6069 }
6070 }
6071
6072 static void si_shader_dump_stats(struct si_screen *sscreen,
6073 struct si_shader_config *conf,
6074 unsigned num_inputs,
6075 unsigned code_size,
6076 struct pipe_debug_callback *debug,
6077 unsigned processor,
6078 FILE *file)
6079 {
6080 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6081 unsigned lds_per_wave = 0;
6082 unsigned max_simd_waves = 10;
6083
6084 /* Compute LDS usage for PS. */
6085 if (processor == PIPE_SHADER_FRAGMENT) {
6086 /* The minimum usage per wave is (num_inputs * 48). The maximum
6087 * usage is (num_inputs * 48 * 16).
6088 * We can get anything in between and it varies between waves.
6089 *
6090 * The 48 bytes per input for a single primitive is equal to
6091 * 4 bytes/component * 4 components/input * 3 points.
6092 *
6093 * Other stages don't know the size at compile time or don't
6094 * allocate LDS per wave, but instead they do it per thread group.
6095 */
6096 lds_per_wave = conf->lds_size * lds_increment +
6097 align(num_inputs * 48, lds_increment);
6098 }
6099
6100 /* Compute the per-SIMD wave counts. */
6101 if (conf->num_sgprs) {
6102 if (sscreen->b.chip_class >= VI)
6103 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6104 else
6105 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6106 }
6107
6108 if (conf->num_vgprs)
6109 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6110
6111 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6112 * that PS can use.
6113 */
6114 if (lds_per_wave)
6115 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6116
6117 if (file != stderr ||
6118 r600_can_dump_shader(&sscreen->b, processor)) {
6119 if (processor == PIPE_SHADER_FRAGMENT) {
6120 fprintf(file, "*** SHADER CONFIG ***\n"
6121 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6122 "SPI_PS_INPUT_ENA = 0x%04x\n",
6123 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6124 }
6125
6126 fprintf(file, "*** SHADER STATS ***\n"
6127 "SGPRS: %d\n"
6128 "VGPRS: %d\n"
6129 "Spilled SGPRs: %d\n"
6130 "Spilled VGPRs: %d\n"
6131 "Code Size: %d bytes\n"
6132 "LDS: %d blocks\n"
6133 "Scratch: %d bytes per wave\n"
6134 "Max Waves: %d\n"
6135 "********************\n\n\n",
6136 conf->num_sgprs, conf->num_vgprs,
6137 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
6138 conf->lds_size, conf->scratch_bytes_per_wave,
6139 max_simd_waves);
6140 }
6141
6142 pipe_debug_message(debug, SHADER_INFO,
6143 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6144 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6145 "Spilled VGPRs: %d",
6146 conf->num_sgprs, conf->num_vgprs, code_size,
6147 conf->lds_size, conf->scratch_bytes_per_wave,
6148 max_simd_waves, conf->spilled_sgprs,
6149 conf->spilled_vgprs);
6150 }
6151
6152 static const char *si_get_shader_name(struct si_shader *shader,
6153 unsigned processor)
6154 {
6155 switch (processor) {
6156 case PIPE_SHADER_VERTEX:
6157 if (shader->key.vs.as_es)
6158 return "Vertex Shader as ES";
6159 else if (shader->key.vs.as_ls)
6160 return "Vertex Shader as LS";
6161 else
6162 return "Vertex Shader as VS";
6163 case PIPE_SHADER_TESS_CTRL:
6164 return "Tessellation Control Shader";
6165 case PIPE_SHADER_TESS_EVAL:
6166 if (shader->key.tes.as_es)
6167 return "Tessellation Evaluation Shader as ES";
6168 else
6169 return "Tessellation Evaluation Shader as VS";
6170 case PIPE_SHADER_GEOMETRY:
6171 if (shader->gs_copy_shader == NULL)
6172 return "GS Copy Shader as VS";
6173 else
6174 return "Geometry Shader";
6175 case PIPE_SHADER_FRAGMENT:
6176 return "Pixel Shader";
6177 case PIPE_SHADER_COMPUTE:
6178 return "Compute Shader";
6179 default:
6180 return "Unknown Shader";
6181 }
6182 }
6183
6184 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6185 struct pipe_debug_callback *debug, unsigned processor,
6186 FILE *file)
6187 {
6188 if (file != stderr ||
6189 r600_can_dump_shader(&sscreen->b, processor))
6190 si_dump_shader_key(processor, &shader->key, file);
6191
6192 if (file != stderr && shader->binary.llvm_ir_string) {
6193 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6194 si_get_shader_name(shader, processor));
6195 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6196 }
6197
6198 if (file != stderr ||
6199 (r600_can_dump_shader(&sscreen->b, processor) &&
6200 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6201 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6202
6203 if (shader->prolog)
6204 si_shader_dump_disassembly(&shader->prolog->binary,
6205 debug, "prolog", file);
6206
6207 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6208
6209 if (shader->epilog)
6210 si_shader_dump_disassembly(&shader->epilog->binary,
6211 debug, "epilog", file);
6212 fprintf(file, "\n");
6213 }
6214
6215 si_shader_dump_stats(sscreen, &shader->config,
6216 shader->selector ? shader->selector->info.num_inputs : 0,
6217 si_get_shader_binary_size(shader), debug, processor,
6218 file);
6219 }
6220
6221 int si_compile_llvm(struct si_screen *sscreen,
6222 struct radeon_shader_binary *binary,
6223 struct si_shader_config *conf,
6224 LLVMTargetMachineRef tm,
6225 LLVMModuleRef mod,
6226 struct pipe_debug_callback *debug,
6227 unsigned processor,
6228 const char *name)
6229 {
6230 int r = 0;
6231 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6232
6233 if (r600_can_dump_shader(&sscreen->b, processor)) {
6234 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6235
6236 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6237 fprintf(stderr, "%s LLVM IR:\n\n", name);
6238 LLVMDumpModule(mod);
6239 fprintf(stderr, "\n");
6240 }
6241 }
6242
6243 if (sscreen->record_llvm_ir) {
6244 char *ir = LLVMPrintModuleToString(mod);
6245 binary->llvm_ir_string = strdup(ir);
6246 LLVMDisposeMessage(ir);
6247 }
6248
6249 if (!si_replace_shader(count, binary)) {
6250 r = radeon_llvm_compile(mod, binary, tm, debug);
6251 if (r)
6252 return r;
6253 }
6254
6255 si_shader_binary_read_config(binary, conf, 0);
6256
6257 /* Enable 64-bit and 16-bit denormals, because there is no performance
6258 * cost.
6259 *
6260 * If denormals are enabled, all floating-point output modifiers are
6261 * ignored.
6262 *
6263 * Don't enable denormals for 32-bit floats, because:
6264 * - Floating-point output modifiers would be ignored by the hw.
6265 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6266 * have to stop using those.
6267 * - SI & CI would be very slow.
6268 */
6269 conf->float_mode |= V_00B028_FP_64_DENORMS;
6270
6271 FREE(binary->config);
6272 FREE(binary->global_symbol_offsets);
6273 binary->config = NULL;
6274 binary->global_symbol_offsets = NULL;
6275
6276 /* Some shaders can't have rodata because their binaries can be
6277 * concatenated.
6278 */
6279 if (binary->rodata_size &&
6280 (processor == PIPE_SHADER_VERTEX ||
6281 processor == PIPE_SHADER_TESS_CTRL ||
6282 processor == PIPE_SHADER_TESS_EVAL ||
6283 processor == PIPE_SHADER_FRAGMENT)) {
6284 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6285 return -EINVAL;
6286 }
6287
6288 return r;
6289 }
6290
6291 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6292 {
6293 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6294 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6295 else
6296 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6297 }
6298
6299 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6300 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6301 struct si_shader_context *ctx,
6302 struct si_shader *gs,
6303 struct pipe_debug_callback *debug)
6304 {
6305 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6306 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6307 struct lp_build_context *uint = &bld_base->uint_bld;
6308 struct si_shader_output_values *outputs;
6309 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6310 LLVMValueRef args[9];
6311 int i, r;
6312
6313 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6314
6315 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6316 ctx->type = PIPE_SHADER_VERTEX;
6317 ctx->is_gs_copy_shader = true;
6318
6319 create_meta_data(ctx);
6320 create_function(ctx);
6321 preload_ring_buffers(ctx);
6322
6323 args[0] = ctx->gsvs_ring[0];
6324 args[1] = lp_build_mul_imm(uint,
6325 LLVMGetParam(ctx->radeon_bld.main_fn,
6326 ctx->param_vertex_id),
6327 4);
6328 args[3] = uint->zero;
6329 args[4] = uint->one; /* OFFEN */
6330 args[5] = uint->zero; /* IDXEN */
6331 args[6] = uint->one; /* GLC */
6332 args[7] = uint->one; /* SLC */
6333 args[8] = uint->zero; /* TFE */
6334
6335 /* Fetch vertex data from GSVS ring */
6336 for (i = 0; i < gsinfo->num_outputs; ++i) {
6337 unsigned chan;
6338
6339 outputs[i].name = gsinfo->output_semantic_name[i];
6340 outputs[i].sid = gsinfo->output_semantic_index[i];
6341
6342 for (chan = 0; chan < 4; chan++) {
6343 args[2] = lp_build_const_int32(gallivm,
6344 (i * 4 + chan) *
6345 gs->selector->gs_max_out_vertices * 16 * 4);
6346
6347 outputs[i].values[chan] =
6348 LLVMBuildBitCast(gallivm->builder,
6349 lp_build_intrinsic(gallivm->builder,
6350 "llvm.SI.buffer.load.dword.i32.i32",
6351 ctx->i32, args, 9,
6352 LLVMReadOnlyAttribute),
6353 ctx->f32, "");
6354 }
6355 }
6356
6357 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6358
6359 LLVMBuildRetVoid(gallivm->builder);
6360
6361 /* Dump LLVM IR before any optimization passes */
6362 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6363 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6364 LLVMDumpModule(bld_base->base.gallivm->module);
6365
6366 radeon_llvm_finalize_module(
6367 &ctx->radeon_bld,
6368 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6369
6370 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6371 &ctx->shader->config, ctx->tm,
6372 bld_base->base.gallivm->module,
6373 debug, PIPE_SHADER_GEOMETRY,
6374 "GS Copy Shader");
6375 if (!r) {
6376 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6377 fprintf(stderr, "GS Copy Shader:\n");
6378 si_shader_dump(sscreen, ctx->shader, debug,
6379 PIPE_SHADER_GEOMETRY, stderr);
6380 r = si_shader_binary_upload(sscreen, ctx->shader);
6381 }
6382
6383 radeon_llvm_dispose(&ctx->radeon_bld);
6384
6385 FREE(outputs);
6386 return r;
6387 }
6388
6389 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
6390 FILE *f)
6391 {
6392 int i;
6393
6394 fprintf(f, "SHADER KEY\n");
6395
6396 switch (shader) {
6397 case PIPE_SHADER_VERTEX:
6398 fprintf(f, " instance_divisors = {");
6399 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6400 fprintf(f, !i ? "%u" : ", %u",
6401 key->vs.prolog.instance_divisors[i]);
6402 fprintf(f, "}\n");
6403 fprintf(f, " as_es = %u\n", key->vs.as_es);
6404 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6405 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6406 break;
6407
6408 case PIPE_SHADER_TESS_CTRL:
6409 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6410 break;
6411
6412 case PIPE_SHADER_TESS_EVAL:
6413 fprintf(f, " as_es = %u\n", key->tes.as_es);
6414 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6415 break;
6416
6417 case PIPE_SHADER_GEOMETRY:
6418 case PIPE_SHADER_COMPUTE:
6419 break;
6420
6421 case PIPE_SHADER_FRAGMENT:
6422 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6423 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6424 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6425 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6426 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6427 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6428 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6429 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6430 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6431 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6432 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6433 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6434 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6435 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6436 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6437 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6438 break;
6439
6440 default:
6441 assert(0);
6442 }
6443 }
6444
6445 static void si_init_shader_ctx(struct si_shader_context *ctx,
6446 struct si_screen *sscreen,
6447 struct si_shader *shader,
6448 LLVMTargetMachineRef tm)
6449 {
6450 struct lp_build_tgsi_context *bld_base;
6451 struct lp_build_tgsi_action tmpl = {};
6452
6453 memset(ctx, 0, sizeof(*ctx));
6454 radeon_llvm_context_init(
6455 &ctx->radeon_bld, "amdgcn--",
6456 (shader && shader->selector) ? &shader->selector->info : NULL,
6457 (shader && shader->selector) ? shader->selector->tokens : NULL);
6458 ctx->tm = tm;
6459 ctx->screen = sscreen;
6460 if (shader && shader->selector)
6461 ctx->type = shader->selector->info.processor;
6462 else
6463 ctx->type = -1;
6464 ctx->shader = shader;
6465
6466 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6467 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6468 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6469 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6470 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6471 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6472 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6473 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6474 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6475 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6476 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6477 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6478
6479 bld_base = &ctx->radeon_bld.soa.bld_base;
6480 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6481
6482 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6483 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6484 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6485
6486 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6487 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6488 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6489 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6490 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6491 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6492 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6493 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6494 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6495 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6496 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6497 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6498 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6499 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6500
6501 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6502 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6503 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6504 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6505 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6506 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6507
6508 tmpl.fetch_args = atomic_fetch_args;
6509 tmpl.emit = atomic_emit;
6510 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6511 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6512 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6513 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6514 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6515 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6516 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6517 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6518 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6519 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6520 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6521 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6522 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6523 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6524 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6525 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6526 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6527 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6528 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6529 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6530
6531 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6532
6533 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6534 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6535 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6536 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6537
6538 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6539 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6540 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6541
6542 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6543 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6544 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6545 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6546 }
6547
6548 int si_compile_tgsi_shader(struct si_screen *sscreen,
6549 LLVMTargetMachineRef tm,
6550 struct si_shader *shader,
6551 bool is_monolithic,
6552 struct pipe_debug_callback *debug)
6553 {
6554 struct si_shader_selector *sel = shader->selector;
6555 struct si_shader_context ctx;
6556 struct lp_build_tgsi_context *bld_base;
6557 LLVMModuleRef mod;
6558 int r = 0;
6559
6560 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6561 * conversion fails. */
6562 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6563 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6564 tgsi_dump(sel->tokens, 0);
6565 si_dump_streamout(&sel->so);
6566 }
6567
6568 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6569 ctx.is_monolithic = is_monolithic;
6570
6571 shader->info.uses_instanceid = sel->info.uses_instanceid;
6572
6573 bld_base = &ctx.radeon_bld.soa.bld_base;
6574 ctx.radeon_bld.load_system_value = declare_system_value;
6575
6576 switch (ctx.type) {
6577 case PIPE_SHADER_VERTEX:
6578 ctx.radeon_bld.load_input = declare_input_vs;
6579 if (shader->key.vs.as_ls)
6580 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6581 else if (shader->key.vs.as_es)
6582 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6583 else
6584 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6585 break;
6586 case PIPE_SHADER_TESS_CTRL:
6587 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6588 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6589 bld_base->emit_store = store_output_tcs;
6590 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6591 break;
6592 case PIPE_SHADER_TESS_EVAL:
6593 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6594 if (shader->key.tes.as_es)
6595 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6596 else
6597 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6598 break;
6599 case PIPE_SHADER_GEOMETRY:
6600 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6601 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6602 break;
6603 case PIPE_SHADER_FRAGMENT:
6604 ctx.radeon_bld.load_input = declare_input_fs;
6605 if (is_monolithic)
6606 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6607 else
6608 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6609 break;
6610 case PIPE_SHADER_COMPUTE:
6611 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6612 break;
6613 default:
6614 assert(!"Unsupported shader type");
6615 return -1;
6616 }
6617
6618 create_meta_data(&ctx);
6619 create_function(&ctx);
6620 preload_ring_buffers(&ctx);
6621
6622 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6623 shader->key.ps.prolog.poly_stipple) {
6624 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6625 SI_PARAM_RW_BUFFERS);
6626 si_llvm_emit_polygon_stipple(&ctx, list,
6627 SI_PARAM_POS_FIXED_PT);
6628 }
6629
6630 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6631 int i;
6632 for (i = 0; i < 4; i++) {
6633 ctx.gs_next_vertex[i] =
6634 lp_build_alloca(bld_base->base.gallivm,
6635 ctx.i32, "");
6636 }
6637 }
6638
6639 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6640 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6641 goto out;
6642 }
6643
6644 si_llvm_build_ret(&ctx, ctx.return_value);
6645 mod = bld_base->base.gallivm->module;
6646
6647 /* Dump LLVM IR before any optimization passes */
6648 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6649 r600_can_dump_shader(&sscreen->b, ctx.type))
6650 LLVMDumpModule(mod);
6651
6652 radeon_llvm_finalize_module(
6653 &ctx.radeon_bld,
6654 r600_extra_shader_checks(&sscreen->b, ctx.type));
6655
6656 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6657 mod, debug, ctx.type, "TGSI shader");
6658 if (r) {
6659 fprintf(stderr, "LLVM failed to compile shader\n");
6660 goto out;
6661 }
6662
6663 radeon_llvm_dispose(&ctx.radeon_bld);
6664
6665 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6666 * LLVM 3.9svn has this bug.
6667 */
6668 if (sel->type == PIPE_SHADER_COMPUTE) {
6669 unsigned *props = sel->info.properties;
6670 unsigned wave_size = 64;
6671 unsigned max_vgprs = 256;
6672 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6673 unsigned max_sgprs_per_wave = 128;
6674 unsigned max_block_threads;
6675
6676 if (props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH])
6677 max_block_threads = props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
6678 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
6679 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
6680 else
6681 max_block_threads = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
6682
6683 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6684 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6685
6686 max_vgprs = max_vgprs / min_waves_per_simd;
6687 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6688
6689 if (shader->config.num_sgprs > max_sgprs ||
6690 shader->config.num_vgprs > max_vgprs) {
6691 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6692 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6693 shader->config.num_sgprs, shader->config.num_vgprs,
6694 max_sgprs, max_vgprs);
6695
6696 /* Just terminate the process, because dependent
6697 * shaders can hang due to bad input data, but use
6698 * the env var to allow shader-db to work.
6699 */
6700 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6701 abort();
6702 }
6703 }
6704
6705 /* Add the scratch offset to input SGPRs. */
6706 if (shader->config.scratch_bytes_per_wave)
6707 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6708
6709 /* Calculate the number of fragment input VGPRs. */
6710 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6711 shader->info.num_input_vgprs = 0;
6712 shader->info.face_vgpr_index = -1;
6713
6714 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6715 shader->info.num_input_vgprs += 2;
6716 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6717 shader->info.num_input_vgprs += 2;
6718 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6719 shader->info.num_input_vgprs += 2;
6720 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6721 shader->info.num_input_vgprs += 3;
6722 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6723 shader->info.num_input_vgprs += 2;
6724 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6725 shader->info.num_input_vgprs += 2;
6726 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6727 shader->info.num_input_vgprs += 2;
6728 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6729 shader->info.num_input_vgprs += 1;
6730 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6731 shader->info.num_input_vgprs += 1;
6732 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6733 shader->info.num_input_vgprs += 1;
6734 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6735 shader->info.num_input_vgprs += 1;
6736 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6737 shader->info.num_input_vgprs += 1;
6738 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6739 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6740 shader->info.num_input_vgprs += 1;
6741 }
6742 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6743 shader->info.num_input_vgprs += 1;
6744 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6745 shader->info.num_input_vgprs += 1;
6746 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6747 shader->info.num_input_vgprs += 1;
6748 }
6749
6750 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6751 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6752 shader->gs_copy_shader->selector = shader->selector;
6753 ctx.shader = shader->gs_copy_shader;
6754 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6755 shader, debug))) {
6756 free(shader->gs_copy_shader);
6757 shader->gs_copy_shader = NULL;
6758 goto out;
6759 }
6760 }
6761
6762 out:
6763 return r;
6764 }
6765
6766 /**
6767 * Create, compile and return a shader part (prolog or epilog).
6768 *
6769 * \param sscreen screen
6770 * \param list list of shader parts of the same category
6771 * \param key shader part key
6772 * \param tm LLVM target machine
6773 * \param debug debug callback
6774 * \param compile the callback responsible for compilation
6775 * \return non-NULL on success
6776 */
6777 static struct si_shader_part *
6778 si_get_shader_part(struct si_screen *sscreen,
6779 struct si_shader_part **list,
6780 union si_shader_part_key *key,
6781 LLVMTargetMachineRef tm,
6782 struct pipe_debug_callback *debug,
6783 bool (*compile)(struct si_screen *,
6784 LLVMTargetMachineRef,
6785 struct pipe_debug_callback *,
6786 struct si_shader_part *))
6787 {
6788 struct si_shader_part *result;
6789
6790 pipe_mutex_lock(sscreen->shader_parts_mutex);
6791
6792 /* Find existing. */
6793 for (result = *list; result; result = result->next) {
6794 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6795 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6796 return result;
6797 }
6798 }
6799
6800 /* Compile a new one. */
6801 result = CALLOC_STRUCT(si_shader_part);
6802 result->key = *key;
6803 if (!compile(sscreen, tm, debug, result)) {
6804 FREE(result);
6805 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6806 return NULL;
6807 }
6808
6809 result->next = *list;
6810 *list = result;
6811 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6812 return result;
6813 }
6814
6815 /**
6816 * Create a vertex shader prolog.
6817 *
6818 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6819 * All inputs are returned unmodified. The vertex load indices are
6820 * stored after them, which will used by the API VS for fetching inputs.
6821 *
6822 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6823 * input_v0,
6824 * input_v1,
6825 * input_v2,
6826 * input_v3,
6827 * (VertexID + BaseVertex),
6828 * (InstanceID + StartInstance),
6829 * (InstanceID / 2 + StartInstance)
6830 */
6831 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6832 LLVMTargetMachineRef tm,
6833 struct pipe_debug_callback *debug,
6834 struct si_shader_part *out)
6835 {
6836 union si_shader_part_key *key = &out->key;
6837 struct si_shader shader = {};
6838 struct si_shader_context ctx;
6839 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6840 LLVMTypeRef *params, *returns;
6841 LLVMValueRef ret, func;
6842 int last_sgpr, num_params, num_returns, i;
6843 bool status = true;
6844
6845 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6846 ctx.type = PIPE_SHADER_VERTEX;
6847 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6848 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6849
6850 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6851 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6852 sizeof(LLVMTypeRef));
6853 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6854 key->vs_prolog.last_input + 1) *
6855 sizeof(LLVMTypeRef));
6856 num_params = 0;
6857 num_returns = 0;
6858
6859 /* Declare input and output SGPRs. */
6860 num_params = 0;
6861 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6862 params[num_params++] = ctx.i32;
6863 returns[num_returns++] = ctx.i32;
6864 }
6865 last_sgpr = num_params - 1;
6866
6867 /* 4 preloaded VGPRs (outputs must be floats) */
6868 for (i = 0; i < 4; i++) {
6869 params[num_params++] = ctx.i32;
6870 returns[num_returns++] = ctx.f32;
6871 }
6872
6873 /* Vertex load indices. */
6874 for (i = 0; i <= key->vs_prolog.last_input; i++)
6875 returns[num_returns++] = ctx.f32;
6876
6877 /* Create the function. */
6878 si_create_function(&ctx, returns, num_returns, params,
6879 num_params, last_sgpr);
6880 func = ctx.radeon_bld.main_fn;
6881
6882 /* Copy inputs to outputs. This should be no-op, as the registers match,
6883 * but it will prevent the compiler from overwriting them unintentionally.
6884 */
6885 ret = ctx.return_value;
6886 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6887 LLVMValueRef p = LLVMGetParam(func, i);
6888 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6889 }
6890 for (i = num_params - 4; i < num_params; i++) {
6891 LLVMValueRef p = LLVMGetParam(func, i);
6892 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6893 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6894 }
6895
6896 /* Compute vertex load indices from instance divisors. */
6897 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6898 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6899 LLVMValueRef index;
6900
6901 if (divisor) {
6902 /* InstanceID / Divisor + StartInstance */
6903 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6904 SI_SGPR_START_INSTANCE,
6905 divisor);
6906 } else {
6907 /* VertexID + BaseVertex */
6908 index = LLVMBuildAdd(gallivm->builder,
6909 LLVMGetParam(func, ctx.param_vertex_id),
6910 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6911 }
6912
6913 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6914 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6915 num_params++, "");
6916 }
6917
6918 /* Compile. */
6919 si_llvm_build_ret(&ctx, ret);
6920 radeon_llvm_finalize_module(
6921 &ctx.radeon_bld,
6922 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
6923
6924 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6925 gallivm->module, debug, ctx.type,
6926 "Vertex Shader Prolog"))
6927 status = false;
6928
6929 radeon_llvm_dispose(&ctx.radeon_bld);
6930 return status;
6931 }
6932
6933 /**
6934 * Compile the vertex shader epilog. This is also used by the tessellation
6935 * evaluation shader compiled as VS.
6936 *
6937 * The input is PrimitiveID.
6938 *
6939 * If PrimitiveID is required by the pixel shader, export it.
6940 * Otherwise, do nothing.
6941 */
6942 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6943 LLVMTargetMachineRef tm,
6944 struct pipe_debug_callback *debug,
6945 struct si_shader_part *out)
6946 {
6947 union si_shader_part_key *key = &out->key;
6948 struct si_shader_context ctx;
6949 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6950 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6951 LLVMTypeRef params[5];
6952 int num_params, i;
6953 bool status = true;
6954
6955 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6956 ctx.type = PIPE_SHADER_VERTEX;
6957
6958 /* Declare input VGPRs. */
6959 num_params = key->vs_epilog.states.export_prim_id ?
6960 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6961 assert(num_params <= ARRAY_SIZE(params));
6962
6963 for (i = 0; i < num_params; i++)
6964 params[i] = ctx.f32;
6965
6966 /* Create the function. */
6967 si_create_function(&ctx, NULL, 0, params, num_params, -1);
6968
6969 /* Emit exports. */
6970 if (key->vs_epilog.states.export_prim_id) {
6971 struct lp_build_context *base = &bld_base->base;
6972 struct lp_build_context *uint = &bld_base->uint_bld;
6973 LLVMValueRef args[9];
6974
6975 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6976 args[1] = uint->zero; /* whether the EXEC mask is valid */
6977 args[2] = uint->zero; /* DONE bit */
6978 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6979 key->vs_epilog.prim_id_param_offset);
6980 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6981 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6982 VS_EPILOG_PRIMID_LOC); /* X */
6983 args[6] = uint->undef; /* Y */
6984 args[7] = uint->undef; /* Z */
6985 args[8] = uint->undef; /* W */
6986
6987 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6988 LLVMVoidTypeInContext(base->gallivm->context),
6989 args, 9, 0);
6990 }
6991
6992 /* Compile. */
6993 LLVMBuildRetVoid(gallivm->builder);
6994 radeon_llvm_finalize_module(
6995 &ctx.radeon_bld,
6996 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
6997
6998 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6999 gallivm->module, debug, ctx.type,
7000 "Vertex Shader Epilog"))
7001 status = false;
7002
7003 radeon_llvm_dispose(&ctx.radeon_bld);
7004 return status;
7005 }
7006
7007 /**
7008 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7009 */
7010 static bool si_get_vs_epilog(struct si_screen *sscreen,
7011 LLVMTargetMachineRef tm,
7012 struct si_shader *shader,
7013 struct pipe_debug_callback *debug,
7014 struct si_vs_epilog_bits *states)
7015 {
7016 union si_shader_part_key epilog_key;
7017
7018 memset(&epilog_key, 0, sizeof(epilog_key));
7019 epilog_key.vs_epilog.states = *states;
7020
7021 /* Set up the PrimitiveID output. */
7022 if (shader->key.vs.epilog.export_prim_id) {
7023 unsigned index = shader->selector->info.num_outputs;
7024 unsigned offset = shader->info.nr_param_exports++;
7025
7026 epilog_key.vs_epilog.prim_id_param_offset = offset;
7027 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7028 shader->info.vs_output_param_offset[index] = offset;
7029 }
7030
7031 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7032 &epilog_key, tm, debug,
7033 si_compile_vs_epilog);
7034 return shader->epilog != NULL;
7035 }
7036
7037 /**
7038 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7039 */
7040 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7041 LLVMTargetMachineRef tm,
7042 struct si_shader *shader,
7043 struct pipe_debug_callback *debug)
7044 {
7045 struct tgsi_shader_info *info = &shader->selector->info;
7046 union si_shader_part_key prolog_key;
7047 unsigned i;
7048
7049 /* Get the prolog. */
7050 memset(&prolog_key, 0, sizeof(prolog_key));
7051 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7052 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7053 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7054
7055 /* The prolog is a no-op if there are no inputs. */
7056 if (info->num_inputs) {
7057 shader->prolog =
7058 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7059 &prolog_key, tm, debug,
7060 si_compile_vs_prolog);
7061 if (!shader->prolog)
7062 return false;
7063 }
7064
7065 /* Get the epilog. */
7066 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7067 !si_get_vs_epilog(sscreen, tm, shader, debug,
7068 &shader->key.vs.epilog))
7069 return false;
7070
7071 /* Set the instanceID flag. */
7072 for (i = 0; i < info->num_inputs; i++)
7073 if (prolog_key.vs_prolog.states.instance_divisors[i])
7074 shader->info.uses_instanceid = true;
7075
7076 return true;
7077 }
7078
7079 /**
7080 * Select and compile (or reuse) TES parts (epilog).
7081 */
7082 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7083 LLVMTargetMachineRef tm,
7084 struct si_shader *shader,
7085 struct pipe_debug_callback *debug)
7086 {
7087 if (shader->key.tes.as_es)
7088 return true;
7089
7090 /* TES compiled as VS. */
7091 return si_get_vs_epilog(sscreen, tm, shader, debug,
7092 &shader->key.tes.epilog);
7093 }
7094
7095 /**
7096 * Compile the TCS epilog. This writes tesselation factors to memory based on
7097 * the output primitive type of the tesselator (determined by TES).
7098 */
7099 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7100 LLVMTargetMachineRef tm,
7101 struct pipe_debug_callback *debug,
7102 struct si_shader_part *out)
7103 {
7104 union si_shader_part_key *key = &out->key;
7105 struct si_shader shader = {};
7106 struct si_shader_context ctx;
7107 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7108 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7109 LLVMTypeRef params[16];
7110 LLVMValueRef func;
7111 int last_sgpr, num_params;
7112 bool status = true;
7113
7114 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7115 ctx.type = PIPE_SHADER_TESS_CTRL;
7116 shader.key.tcs.epilog = key->tcs_epilog.states;
7117
7118 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7119 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7120 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7121 params[SI_PARAM_SAMPLERS] = ctx.i64;
7122 params[SI_PARAM_IMAGES] = ctx.i64;
7123 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7124 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7125 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7126 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7127 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7128 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7129 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7130 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7131 num_params = last_sgpr + 1;
7132
7133 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7134 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7135 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7136
7137 /* Create the function. */
7138 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7139 declare_tess_lds(&ctx);
7140 func = ctx.radeon_bld.main_fn;
7141
7142 si_write_tess_factors(bld_base,
7143 LLVMGetParam(func, last_sgpr + 1),
7144 LLVMGetParam(func, last_sgpr + 2),
7145 LLVMGetParam(func, last_sgpr + 3));
7146
7147 /* Compile. */
7148 LLVMBuildRetVoid(gallivm->builder);
7149 radeon_llvm_finalize_module(
7150 &ctx.radeon_bld,
7151 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_TESS_CTRL));
7152
7153 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7154 gallivm->module, debug, ctx.type,
7155 "Tessellation Control Shader Epilog"))
7156 status = false;
7157
7158 radeon_llvm_dispose(&ctx.radeon_bld);
7159 return status;
7160 }
7161
7162 /**
7163 * Select and compile (or reuse) TCS parts (epilog).
7164 */
7165 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7166 LLVMTargetMachineRef tm,
7167 struct si_shader *shader,
7168 struct pipe_debug_callback *debug)
7169 {
7170 union si_shader_part_key epilog_key;
7171
7172 /* Get the epilog. */
7173 memset(&epilog_key, 0, sizeof(epilog_key));
7174 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7175
7176 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7177 &epilog_key, tm, debug,
7178 si_compile_tcs_epilog);
7179 return shader->epilog != NULL;
7180 }
7181
7182 /**
7183 * Compile the pixel shader prolog. This handles:
7184 * - two-side color selection and interpolation
7185 * - overriding interpolation parameters for the API PS
7186 * - polygon stippling
7187 *
7188 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7189 * overriden by other states. (e.g. per-sample interpolation)
7190 * Interpolated colors are stored after the preloaded VGPRs.
7191 */
7192 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7193 LLVMTargetMachineRef tm,
7194 struct pipe_debug_callback *debug,
7195 struct si_shader_part *out)
7196 {
7197 union si_shader_part_key *key = &out->key;
7198 struct si_shader shader = {};
7199 struct si_shader_context ctx;
7200 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7201 LLVMTypeRef *params;
7202 LLVMValueRef ret, func;
7203 int last_sgpr, num_params, num_returns, i, num_color_channels;
7204 bool status = true;
7205
7206 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7207 ctx.type = PIPE_SHADER_FRAGMENT;
7208 shader.key.ps.prolog = key->ps_prolog.states;
7209
7210 /* Number of inputs + 8 color elements. */
7211 params = alloca((key->ps_prolog.num_input_sgprs +
7212 key->ps_prolog.num_input_vgprs + 8) *
7213 sizeof(LLVMTypeRef));
7214
7215 /* Declare inputs. */
7216 num_params = 0;
7217 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7218 params[num_params++] = ctx.i32;
7219 last_sgpr = num_params - 1;
7220
7221 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7222 params[num_params++] = ctx.f32;
7223
7224 /* Declare outputs (same as inputs + add colors if needed) */
7225 num_returns = num_params;
7226 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7227 for (i = 0; i < num_color_channels; i++)
7228 params[num_returns++] = ctx.f32;
7229
7230 /* Create the function. */
7231 si_create_function(&ctx, params, num_returns, params,
7232 num_params, last_sgpr);
7233 func = ctx.radeon_bld.main_fn;
7234
7235 /* Copy inputs to outputs. This should be no-op, as the registers match,
7236 * but it will prevent the compiler from overwriting them unintentionally.
7237 */
7238 ret = ctx.return_value;
7239 for (i = 0; i < num_params; i++) {
7240 LLVMValueRef p = LLVMGetParam(func, i);
7241 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7242 }
7243
7244 /* Polygon stippling. */
7245 if (key->ps_prolog.states.poly_stipple) {
7246 /* POS_FIXED_PT is always last. */
7247 unsigned pos = key->ps_prolog.num_input_sgprs +
7248 key->ps_prolog.num_input_vgprs - 1;
7249 LLVMValueRef ptr[2], list;
7250
7251 /* Get the pointer to rw buffers. */
7252 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7253 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7254 list = lp_build_gather_values(gallivm, ptr, 2);
7255 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7256 list = LLVMBuildIntToPtr(gallivm->builder, list,
7257 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7258
7259 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7260 }
7261
7262 if (key->ps_prolog.states.bc_optimize_for_persp ||
7263 key->ps_prolog.states.bc_optimize_for_linear) {
7264 unsigned i, base = key->ps_prolog.num_input_sgprs;
7265 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7266
7267 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7268 * The hw doesn't compute CENTROID if the whole wave only
7269 * contains fully-covered quads.
7270 *
7271 * PRIM_MASK is after user SGPRs.
7272 */
7273 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7274 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7275 LLVMConstInt(ctx.i32, 31, 0), "");
7276 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7277 ctx.i1, "");
7278
7279 if (key->ps_prolog.states.bc_optimize_for_persp) {
7280 /* Read PERSP_CENTER. */
7281 for (i = 0; i < 2; i++)
7282 center[i] = LLVMGetParam(func, base + 2 + i);
7283 /* Read PERSP_CENTROID. */
7284 for (i = 0; i < 2; i++)
7285 centroid[i] = LLVMGetParam(func, base + 4 + i);
7286 /* Select PERSP_CENTROID. */
7287 for (i = 0; i < 2; i++) {
7288 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7289 center[i], centroid[i], "");
7290 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7291 tmp, base + 4 + i, "");
7292 }
7293 }
7294 if (key->ps_prolog.states.bc_optimize_for_linear) {
7295 /* Read LINEAR_CENTER. */
7296 for (i = 0; i < 2; i++)
7297 center[i] = LLVMGetParam(func, base + 8 + i);
7298 /* Read LINEAR_CENTROID. */
7299 for (i = 0; i < 2; i++)
7300 centroid[i] = LLVMGetParam(func, base + 10 + i);
7301 /* Select LINEAR_CENTROID. */
7302 for (i = 0; i < 2; i++) {
7303 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7304 center[i], centroid[i], "");
7305 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7306 tmp, base + 10 + i, "");
7307 }
7308 }
7309 }
7310
7311 /* Force per-sample interpolation. */
7312 if (key->ps_prolog.states.force_persp_sample_interp) {
7313 unsigned i, base = key->ps_prolog.num_input_sgprs;
7314 LLVMValueRef persp_sample[2];
7315
7316 /* Read PERSP_SAMPLE. */
7317 for (i = 0; i < 2; i++)
7318 persp_sample[i] = LLVMGetParam(func, base + i);
7319 /* Overwrite PERSP_CENTER. */
7320 for (i = 0; i < 2; i++)
7321 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7322 persp_sample[i], base + 2 + i, "");
7323 /* Overwrite PERSP_CENTROID. */
7324 for (i = 0; i < 2; i++)
7325 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7326 persp_sample[i], base + 4 + i, "");
7327 }
7328 if (key->ps_prolog.states.force_linear_sample_interp) {
7329 unsigned i, base = key->ps_prolog.num_input_sgprs;
7330 LLVMValueRef linear_sample[2];
7331
7332 /* Read LINEAR_SAMPLE. */
7333 for (i = 0; i < 2; i++)
7334 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7335 /* Overwrite LINEAR_CENTER. */
7336 for (i = 0; i < 2; i++)
7337 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7338 linear_sample[i], base + 8 + i, "");
7339 /* Overwrite LINEAR_CENTROID. */
7340 for (i = 0; i < 2; i++)
7341 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7342 linear_sample[i], base + 10 + i, "");
7343 }
7344
7345 /* Force center interpolation. */
7346 if (key->ps_prolog.states.force_persp_center_interp) {
7347 unsigned i, base = key->ps_prolog.num_input_sgprs;
7348 LLVMValueRef persp_center[2];
7349
7350 /* Read PERSP_CENTER. */
7351 for (i = 0; i < 2; i++)
7352 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7353 /* Overwrite PERSP_SAMPLE. */
7354 for (i = 0; i < 2; i++)
7355 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7356 persp_center[i], base + i, "");
7357 /* Overwrite PERSP_CENTROID. */
7358 for (i = 0; i < 2; i++)
7359 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7360 persp_center[i], base + 4 + i, "");
7361 }
7362 if (key->ps_prolog.states.force_linear_center_interp) {
7363 unsigned i, base = key->ps_prolog.num_input_sgprs;
7364 LLVMValueRef linear_center[2];
7365
7366 /* Read LINEAR_CENTER. */
7367 for (i = 0; i < 2; i++)
7368 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7369 /* Overwrite LINEAR_SAMPLE. */
7370 for (i = 0; i < 2; i++)
7371 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7372 linear_center[i], base + 6 + i, "");
7373 /* Overwrite LINEAR_CENTROID. */
7374 for (i = 0; i < 2; i++)
7375 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7376 linear_center[i], base + 10 + i, "");
7377 }
7378
7379 /* Interpolate colors. */
7380 for (i = 0; i < 2; i++) {
7381 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7382 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7383 key->ps_prolog.face_vgpr_index;
7384 LLVMValueRef interp[2], color[4];
7385 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7386
7387 if (!writemask)
7388 continue;
7389
7390 /* If the interpolation qualifier is not CONSTANT (-1). */
7391 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7392 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7393 key->ps_prolog.color_interp_vgpr_index[i];
7394
7395 /* Get the (i,j) updated by bc_optimize handling. */
7396 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7397 interp_vgpr, "");
7398 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7399 interp_vgpr + 1, "");
7400 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7401 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7402 ctx.v2i32, "");
7403 }
7404
7405 /* Use the absolute location of the input. */
7406 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7407
7408 if (key->ps_prolog.states.color_two_side) {
7409 face = LLVMGetParam(func, face_vgpr);
7410 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7411 }
7412
7413 interp_fs_input(&ctx,
7414 key->ps_prolog.color_attr_index[i],
7415 TGSI_SEMANTIC_COLOR, i,
7416 key->ps_prolog.num_interp_inputs,
7417 key->ps_prolog.colors_read, interp_ij,
7418 prim_mask, face, color);
7419
7420 while (writemask) {
7421 unsigned chan = u_bit_scan(&writemask);
7422 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7423 num_params++, "");
7424 }
7425 }
7426
7427 /* Tell LLVM to insert WQM instruction sequence when needed. */
7428 if (key->ps_prolog.wqm) {
7429 LLVMAddTargetDependentFunctionAttr(func,
7430 "amdgpu-ps-wqm-outputs", "");
7431 }
7432
7433 /* Compile. */
7434 si_llvm_build_ret(&ctx, ret);
7435 radeon_llvm_finalize_module(
7436 &ctx.radeon_bld,
7437 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7438
7439 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7440 gallivm->module, debug, ctx.type,
7441 "Fragment Shader Prolog"))
7442 status = false;
7443
7444 radeon_llvm_dispose(&ctx.radeon_bld);
7445 return status;
7446 }
7447
7448 /**
7449 * Compile the pixel shader epilog. This handles everything that must be
7450 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7451 */
7452 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7453 LLVMTargetMachineRef tm,
7454 struct pipe_debug_callback *debug,
7455 struct si_shader_part *out)
7456 {
7457 union si_shader_part_key *key = &out->key;
7458 struct si_shader shader = {};
7459 struct si_shader_context ctx;
7460 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7461 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7462 LLVMTypeRef params[16+8*4+3];
7463 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7464 int last_sgpr, num_params, i;
7465 bool status = true;
7466 struct si_ps_exports exp = {};
7467
7468 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7469 ctx.type = PIPE_SHADER_FRAGMENT;
7470 shader.key.ps.epilog = key->ps_epilog.states;
7471
7472 /* Declare input SGPRs. */
7473 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7474 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7475 params[SI_PARAM_SAMPLERS] = ctx.i64;
7476 params[SI_PARAM_IMAGES] = ctx.i64;
7477 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7478 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7479 last_sgpr = SI_PARAM_ALPHA_REF;
7480
7481 /* Declare input VGPRs. */
7482 num_params = (last_sgpr + 1) +
7483 util_bitcount(key->ps_epilog.colors_written) * 4 +
7484 key->ps_epilog.writes_z +
7485 key->ps_epilog.writes_stencil +
7486 key->ps_epilog.writes_samplemask;
7487
7488 num_params = MAX2(num_params,
7489 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7490
7491 assert(num_params <= ARRAY_SIZE(params));
7492
7493 for (i = last_sgpr + 1; i < num_params; i++)
7494 params[i] = ctx.f32;
7495
7496 /* Create the function. */
7497 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7498 /* Disable elimination of unused inputs. */
7499 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7500 "InitialPSInputAddr", 0xffffff);
7501
7502 /* Process colors. */
7503 unsigned vgpr = last_sgpr + 1;
7504 unsigned colors_written = key->ps_epilog.colors_written;
7505 int last_color_export = -1;
7506
7507 /* Find the last color export. */
7508 if (!key->ps_epilog.writes_z &&
7509 !key->ps_epilog.writes_stencil &&
7510 !key->ps_epilog.writes_samplemask) {
7511 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7512
7513 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7514 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7515 /* Just set this if any of the colorbuffers are enabled. */
7516 if (spi_format &
7517 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7518 last_color_export = 0;
7519 } else {
7520 for (i = 0; i < 8; i++)
7521 if (colors_written & (1 << i) &&
7522 (spi_format >> (i * 4)) & 0xf)
7523 last_color_export = i;
7524 }
7525 }
7526
7527 while (colors_written) {
7528 LLVMValueRef color[4];
7529 int mrt = u_bit_scan(&colors_written);
7530
7531 for (i = 0; i < 4; i++)
7532 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7533
7534 si_export_mrt_color(bld_base, color, mrt,
7535 num_params - 1,
7536 mrt == last_color_export, &exp);
7537 }
7538
7539 /* Process depth, stencil, samplemask. */
7540 if (key->ps_epilog.writes_z)
7541 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7542 if (key->ps_epilog.writes_stencil)
7543 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7544 if (key->ps_epilog.writes_samplemask)
7545 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7546
7547 if (depth || stencil || samplemask)
7548 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7549 else if (last_color_export == -1)
7550 si_export_null(bld_base);
7551
7552 if (exp.num)
7553 si_emit_ps_exports(&ctx, &exp);
7554
7555 /* Compile. */
7556 LLVMBuildRetVoid(gallivm->builder);
7557 radeon_llvm_finalize_module(
7558 &ctx.radeon_bld,
7559 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7560
7561 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7562 gallivm->module, debug, ctx.type,
7563 "Fragment Shader Epilog"))
7564 status = false;
7565
7566 radeon_llvm_dispose(&ctx.radeon_bld);
7567 return status;
7568 }
7569
7570 /**
7571 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7572 */
7573 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7574 LLVMTargetMachineRef tm,
7575 struct si_shader *shader,
7576 struct pipe_debug_callback *debug)
7577 {
7578 struct tgsi_shader_info *info = &shader->selector->info;
7579 union si_shader_part_key prolog_key;
7580 union si_shader_part_key epilog_key;
7581 unsigned i;
7582
7583 /* Get the prolog. */
7584 memset(&prolog_key, 0, sizeof(prolog_key));
7585 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7586 prolog_key.ps_prolog.colors_read = info->colors_read;
7587 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7588 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7589 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7590 (prolog_key.ps_prolog.colors_read ||
7591 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7592 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7593 prolog_key.ps_prolog.states.force_persp_center_interp ||
7594 prolog_key.ps_prolog.states.force_linear_center_interp ||
7595 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7596 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7597
7598 if (info->colors_read) {
7599 unsigned *color = shader->selector->color_attr_index;
7600
7601 if (shader->key.ps.prolog.color_two_side) {
7602 /* BCOLORs are stored after the last input. */
7603 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7604 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7605 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7606 }
7607
7608 for (i = 0; i < 2; i++) {
7609 unsigned interp = info->input_interpolate[color[i]];
7610 unsigned location = info->input_interpolate_loc[color[i]];
7611
7612 if (!(info->colors_read & (0xf << i*4)))
7613 continue;
7614
7615 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7616
7617 if (shader->key.ps.prolog.flatshade_colors &&
7618 interp == TGSI_INTERPOLATE_COLOR)
7619 interp = TGSI_INTERPOLATE_CONSTANT;
7620
7621 switch (interp) {
7622 case TGSI_INTERPOLATE_CONSTANT:
7623 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7624 break;
7625 case TGSI_INTERPOLATE_PERSPECTIVE:
7626 case TGSI_INTERPOLATE_COLOR:
7627 /* Force the interpolation location for colors here. */
7628 if (shader->key.ps.prolog.force_persp_sample_interp)
7629 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7630 if (shader->key.ps.prolog.force_persp_center_interp)
7631 location = TGSI_INTERPOLATE_LOC_CENTER;
7632
7633 switch (location) {
7634 case TGSI_INTERPOLATE_LOC_SAMPLE:
7635 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7636 shader->config.spi_ps_input_ena |=
7637 S_0286CC_PERSP_SAMPLE_ENA(1);
7638 break;
7639 case TGSI_INTERPOLATE_LOC_CENTER:
7640 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7641 shader->config.spi_ps_input_ena |=
7642 S_0286CC_PERSP_CENTER_ENA(1);
7643 break;
7644 case TGSI_INTERPOLATE_LOC_CENTROID:
7645 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7646 shader->config.spi_ps_input_ena |=
7647 S_0286CC_PERSP_CENTROID_ENA(1);
7648 break;
7649 default:
7650 assert(0);
7651 }
7652 break;
7653 case TGSI_INTERPOLATE_LINEAR:
7654 /* Force the interpolation location for colors here. */
7655 if (shader->key.ps.prolog.force_linear_sample_interp)
7656 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7657 if (shader->key.ps.prolog.force_linear_center_interp)
7658 location = TGSI_INTERPOLATE_LOC_CENTER;
7659
7660 switch (location) {
7661 case TGSI_INTERPOLATE_LOC_SAMPLE:
7662 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7663 shader->config.spi_ps_input_ena |=
7664 S_0286CC_LINEAR_SAMPLE_ENA(1);
7665 break;
7666 case TGSI_INTERPOLATE_LOC_CENTER:
7667 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7668 shader->config.spi_ps_input_ena |=
7669 S_0286CC_LINEAR_CENTER_ENA(1);
7670 break;
7671 case TGSI_INTERPOLATE_LOC_CENTROID:
7672 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7673 shader->config.spi_ps_input_ena |=
7674 S_0286CC_LINEAR_CENTROID_ENA(1);
7675 break;
7676 default:
7677 assert(0);
7678 }
7679 break;
7680 default:
7681 assert(0);
7682 }
7683 }
7684 }
7685
7686 /* The prolog is a no-op if these aren't set. */
7687 if (prolog_key.ps_prolog.colors_read ||
7688 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7689 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7690 prolog_key.ps_prolog.states.force_persp_center_interp ||
7691 prolog_key.ps_prolog.states.force_linear_center_interp ||
7692 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7693 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7694 prolog_key.ps_prolog.states.poly_stipple) {
7695 shader->prolog =
7696 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7697 &prolog_key, tm, debug,
7698 si_compile_ps_prolog);
7699 if (!shader->prolog)
7700 return false;
7701 }
7702
7703 /* Get the epilog. */
7704 memset(&epilog_key, 0, sizeof(epilog_key));
7705 epilog_key.ps_epilog.colors_written = info->colors_written;
7706 epilog_key.ps_epilog.writes_z = info->writes_z;
7707 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7708 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7709 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7710
7711 shader->epilog =
7712 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7713 &epilog_key, tm, debug,
7714 si_compile_ps_epilog);
7715 if (!shader->epilog)
7716 return false;
7717
7718 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7719 if (shader->key.ps.prolog.poly_stipple) {
7720 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7721 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7722 }
7723
7724 /* Set up the enable bits for per-sample shading if needed. */
7725 if (shader->key.ps.prolog.force_persp_sample_interp &&
7726 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7727 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7728 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7729 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7730 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7731 }
7732 if (shader->key.ps.prolog.force_linear_sample_interp &&
7733 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7734 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7735 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7736 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7737 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7738 }
7739 if (shader->key.ps.prolog.force_persp_center_interp &&
7740 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7741 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7742 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7743 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7744 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7745 }
7746 if (shader->key.ps.prolog.force_linear_center_interp &&
7747 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7748 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7749 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7750 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7751 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7752 }
7753
7754 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7755 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7756 !(shader->config.spi_ps_input_ena & 0xf)) {
7757 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7758 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7759 }
7760
7761 /* At least one pair of interpolation weights must be enabled. */
7762 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7763 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7764 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7765 }
7766
7767 /* The sample mask input is always enabled, because the API shader always
7768 * passes it through to the epilog. Disable it here if it's unused.
7769 */
7770 if (!shader->key.ps.epilog.poly_line_smoothing &&
7771 !shader->selector->info.reads_samplemask)
7772 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7773
7774 return true;
7775 }
7776
7777 static void si_fix_num_sgprs(struct si_shader *shader)
7778 {
7779 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7780
7781 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7782 }
7783
7784 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7785 struct si_shader *shader,
7786 struct pipe_debug_callback *debug)
7787 {
7788 struct si_shader *mainp = shader->selector->main_shader_part;
7789 int r;
7790
7791 /* LS, ES, VS are compiled on demand if the main part hasn't been
7792 * compiled for that stage.
7793 */
7794 if (!mainp ||
7795 (shader->selector->type == PIPE_SHADER_VERTEX &&
7796 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7797 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7798 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7799 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7800 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7801 shader->key.tcs.epilog.inputs_to_copy) ||
7802 shader->selector->type == PIPE_SHADER_COMPUTE) {
7803 /* Monolithic shader (compiled as a whole, has many variants,
7804 * may take a long time to compile).
7805 */
7806 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7807 if (r)
7808 return r;
7809 } else {
7810 /* The shader consists of 2-3 parts:
7811 *
7812 * - the middle part is the user shader, it has 1 variant only
7813 * and it was compiled during the creation of the shader
7814 * selector
7815 * - the prolog part is inserted at the beginning
7816 * - the epilog part is inserted at the end
7817 *
7818 * The prolog and epilog have many (but simple) variants.
7819 */
7820
7821 /* Copy the compiled TGSI shader data over. */
7822 shader->is_binary_shared = true;
7823 shader->binary = mainp->binary;
7824 shader->config = mainp->config;
7825 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7826 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7827 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7828 memcpy(shader->info.vs_output_param_offset,
7829 mainp->info.vs_output_param_offset,
7830 sizeof(mainp->info.vs_output_param_offset));
7831 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7832 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7833 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7834
7835 /* Select prologs and/or epilogs. */
7836 switch (shader->selector->type) {
7837 case PIPE_SHADER_VERTEX:
7838 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7839 return -1;
7840 break;
7841 case PIPE_SHADER_TESS_CTRL:
7842 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7843 return -1;
7844 break;
7845 case PIPE_SHADER_TESS_EVAL:
7846 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7847 return -1;
7848 break;
7849 case PIPE_SHADER_FRAGMENT:
7850 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7851 return -1;
7852
7853 /* Make sure we have at least as many VGPRs as there
7854 * are allocated inputs.
7855 */
7856 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7857 shader->info.num_input_vgprs);
7858 break;
7859 }
7860
7861 /* Update SGPR and VGPR counts. */
7862 if (shader->prolog) {
7863 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7864 shader->prolog->config.num_sgprs);
7865 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7866 shader->prolog->config.num_vgprs);
7867 }
7868 if (shader->epilog) {
7869 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7870 shader->epilog->config.num_sgprs);
7871 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7872 shader->epilog->config.num_vgprs);
7873 }
7874 }
7875
7876 si_fix_num_sgprs(shader);
7877 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7878 stderr);
7879
7880 /* Upload. */
7881 r = si_shader_binary_upload(sscreen, shader);
7882 if (r) {
7883 fprintf(stderr, "LLVM failed to upload shader\n");
7884 return r;
7885 }
7886
7887 return 0;
7888 }
7889
7890 void si_shader_destroy(struct si_shader *shader)
7891 {
7892 if (shader->gs_copy_shader) {
7893 si_shader_destroy(shader->gs_copy_shader);
7894 FREE(shader->gs_copy_shader);
7895 }
7896
7897 if (shader->scratch_bo)
7898 r600_resource_reference(&shader->scratch_bo, NULL);
7899
7900 r600_resource_reference(&shader->bo, NULL);
7901
7902 if (!shader->is_binary_shared)
7903 radeon_shader_binary_clean(&shader->binary);
7904
7905 free(shader->shader_log);
7906 }