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radeonsi: Avoid warning about LLVM generating R_0286D0_SPI_PS_INPUT_ADDR
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 if (type == TGSI_TYPE_DOUBLE) {
598 LLVMValueRef value2;
599 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
600 lp_build_const_int32(gallivm, swizzle + 1));
601 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
602 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
603 }
604
605 return LLVMBuildBitCast(gallivm->builder, value,
606 tgsi2llvmtype(bld_base, type), "");
607 }
608
609 /**
610 * Store to LDS.
611 *
612 * \param swizzle offset (typically 0..3)
613 * \param dw_addr address in dwords
614 * \param value value to store
615 */
616 static void lds_store(struct lp_build_tgsi_context * bld_base,
617 unsigned swizzle, LLVMValueRef dw_addr,
618 LLVMValueRef value)
619 {
620 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
621 struct gallivm_state *gallivm = bld_base->base.gallivm;
622
623 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
624 lp_build_const_int32(gallivm, swizzle));
625
626 value = LLVMBuildBitCast(gallivm->builder, value,
627 LLVMInt32TypeInContext(gallivm->context), "");
628 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
629 dw_addr, value);
630 }
631
632 static LLVMValueRef fetch_input_tcs(
633 struct lp_build_tgsi_context *bld_base,
634 const struct tgsi_full_src_register *reg,
635 enum tgsi_opcode_type type, unsigned swizzle)
636 {
637 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
638 LLVMValueRef dw_addr, stride;
639
640 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
641 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
642 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
643
644 return lds_load(bld_base, type, swizzle, dw_addr);
645 }
646
647 static LLVMValueRef fetch_output_tcs(
648 struct lp_build_tgsi_context *bld_base,
649 const struct tgsi_full_src_register *reg,
650 enum tgsi_opcode_type type, unsigned swizzle)
651 {
652 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
653 LLVMValueRef dw_addr, stride;
654
655 if (reg->Register.Dimension) {
656 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
657 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
658 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
659 } else {
660 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
661 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
662 }
663
664 return lds_load(bld_base, type, swizzle, dw_addr);
665 }
666
667 static LLVMValueRef fetch_input_tes(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 if (reg->Register.Dimension) {
676 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
677 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
678 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
679 } else {
680 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
681 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
682 }
683
684 return lds_load(bld_base, type, swizzle, dw_addr);
685 }
686
687 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
688 const struct tgsi_full_instruction * inst,
689 const struct tgsi_opcode_info * info,
690 LLVMValueRef dst[4])
691 {
692 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
693 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
694 unsigned chan_index;
695 LLVMValueRef dw_addr, stride;
696
697 /* Only handle per-patch and per-vertex outputs here.
698 * Vectors will be lowered to scalars and this function will be called again.
699 */
700 if (reg->Register.File != TGSI_FILE_OUTPUT ||
701 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
702 radeon_llvm_emit_store(bld_base, inst, info, dst);
703 return;
704 }
705
706 if (reg->Register.Dimension) {
707 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
708 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
709 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
710 } else {
711 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
712 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
713 }
714
715 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
716 LLVMValueRef value = dst[chan_index];
717
718 if (inst->Instruction.Saturate)
719 value = radeon_llvm_saturate(bld_base, value);
720
721 lds_store(bld_base, chan_index, dw_addr, value);
722 }
723 }
724
725 static LLVMValueRef fetch_input_gs(
726 struct lp_build_tgsi_context *bld_base,
727 const struct tgsi_full_src_register *reg,
728 enum tgsi_opcode_type type,
729 unsigned swizzle)
730 {
731 struct lp_build_context *base = &bld_base->base;
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct si_shader *shader = si_shader_ctx->shader;
734 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
735 struct gallivm_state *gallivm = base->gallivm;
736 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
737 LLVMValueRef vtx_offset;
738 LLVMValueRef args[9];
739 unsigned vtx_offset_param;
740 struct tgsi_shader_info *info = &shader->selector->info;
741 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
742 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
743 unsigned param;
744 LLVMValueRef value;
745
746 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
747 return get_primitive_id(bld_base, swizzle);
748
749 if (!reg->Register.Dimension)
750 return NULL;
751
752 if (swizzle == ~0) {
753 LLVMValueRef values[TGSI_NUM_CHANNELS];
754 unsigned chan;
755 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
756 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
757 }
758 return lp_build_gather_values(bld_base->base.gallivm, values,
759 TGSI_NUM_CHANNELS);
760 }
761
762 /* Get the vertex offset parameter */
763 vtx_offset_param = reg->Dimension.Index;
764 if (vtx_offset_param < 2) {
765 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
766 } else {
767 assert(vtx_offset_param < 6);
768 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
769 }
770 vtx_offset = lp_build_mul_imm(uint,
771 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
772 vtx_offset_param),
773 4);
774
775 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
776 args[0] = si_shader_ctx->esgs_ring;
777 args[1] = vtx_offset;
778 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
779 args[3] = uint->zero;
780 args[4] = uint->one; /* OFFEN */
781 args[5] = uint->zero; /* IDXEN */
782 args[6] = uint->one; /* GLC */
783 args[7] = uint->zero; /* SLC */
784 args[8] = uint->zero; /* TFE */
785
786 value = lp_build_intrinsic(gallivm->builder,
787 "llvm.SI.buffer.load.dword.i32.i32",
788 i32, args, 9,
789 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
790 if (type == TGSI_TYPE_DOUBLE) {
791 LLVMValueRef value2;
792 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
793 value2 = lp_build_intrinsic(gallivm->builder,
794 "llvm.SI.buffer.load.dword.i32.i32",
795 i32, args, 9,
796 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
797 return radeon_llvm_emit_fetch_double(bld_base,
798 value, value2);
799 }
800 return LLVMBuildBitCast(gallivm->builder,
801 value,
802 tgsi2llvmtype(bld_base, type), "");
803 }
804
805 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
806 {
807 switch (interpolate) {
808 case TGSI_INTERPOLATE_CONSTANT:
809 return 0;
810
811 case TGSI_INTERPOLATE_LINEAR:
812 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
813 return SI_PARAM_LINEAR_SAMPLE;
814 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
815 return SI_PARAM_LINEAR_CENTROID;
816 else
817 return SI_PARAM_LINEAR_CENTER;
818 break;
819 case TGSI_INTERPOLATE_COLOR:
820 case TGSI_INTERPOLATE_PERSPECTIVE:
821 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
822 return SI_PARAM_PERSP_SAMPLE;
823 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
824 return SI_PARAM_PERSP_CENTROID;
825 else
826 return SI_PARAM_PERSP_CENTER;
827 break;
828 default:
829 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
830 return -1;
831 }
832 }
833
834 /* This shouldn't be used by explicit INTERP opcodes. */
835 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
836 unsigned param)
837 {
838 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
839 unsigned sample_param = 0;
840 LLVMValueRef default_ij, sample_ij, force_sample;
841
842 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
843
844 /* If the shader doesn't use center/centroid, just return the parameter.
845 *
846 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
847 * switch between center/centroid and sample without shader changes.
848 */
849 switch (param) {
850 case SI_PARAM_PERSP_CENTROID:
851 case SI_PARAM_PERSP_CENTER:
852 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
853 return default_ij;
854
855 sample_param = SI_PARAM_PERSP_SAMPLE;
856 break;
857
858 case SI_PARAM_LINEAR_CENTROID:
859 case SI_PARAM_LINEAR_CENTER:
860 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
861 return default_ij;
862
863 sample_param = SI_PARAM_LINEAR_SAMPLE;
864 break;
865
866 default:
867 return default_ij;
868 }
869
870 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
871 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
872
873 /* TODO: this can be done more efficiently by switching between
874 * 2 prologs.
875 */
876 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
877 SI_PARAM_PS_STATE_BITS);
878 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
879 LLVMInt1TypeInContext(gallivm->context), "");
880 return LLVMBuildSelect(gallivm->builder, force_sample,
881 sample_ij, default_ij, "");
882 }
883
884 static void declare_input_fs(
885 struct radeon_llvm_context *radeon_bld,
886 unsigned input_index,
887 const struct tgsi_full_declaration *decl)
888 {
889 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
890 struct si_shader_context *si_shader_ctx =
891 si_shader_context(&radeon_bld->soa.bld_base);
892 struct si_shader *shader = si_shader_ctx->shader;
893 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
894 struct gallivm_state *gallivm = base->gallivm;
895 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
896 LLVMValueRef main_fn = radeon_bld->main_fn;
897
898 LLVMValueRef interp_param = NULL;
899 int interp_param_idx;
900 const char * intr_name;
901
902 /* This value is:
903 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
904 * quad begins a new primitive. Bit 0 always needs
905 * to be unset)
906 * [32:16] ParamOffset
907 *
908 */
909 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
910 LLVMValueRef attr_number;
911
912 unsigned chan;
913
914 shader->ps_input_param_offset[input_index] = shader->nparam++;
915 attr_number = lp_build_const_int32(gallivm,
916 shader->ps_input_param_offset[input_index]);
917
918 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
919 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
920 decl->Interp.Location);
921 if (interp_param_idx == -1)
922 return;
923 else if (interp_param_idx)
924 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
925
926 /* fs.constant returns the param from the middle vertex, so it's not
927 * really useful for flat shading. It's meant to be used for custom
928 * interpolation (but the intrinsic can't fetch from the other two
929 * vertices).
930 *
931 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
932 * to do the right thing. The only reason we use fs.constant is that
933 * fs.interp cannot be used on integers, because they can be equal
934 * to NaN.
935 */
936 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
937
938 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
939 si_shader_ctx->shader->key.ps.color_two_side) {
940 LLVMValueRef args[4];
941 LLVMValueRef face, is_face_positive;
942 LLVMValueRef back_attr_number =
943 lp_build_const_int32(gallivm,
944 shader->ps_input_param_offset[input_index] + 1);
945
946 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
947
948 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
949 face, uint->zero, "");
950
951 args[2] = params;
952 args[3] = interp_param;
953 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
954 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
955 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
956 LLVMValueRef front, back;
957
958 args[0] = llvm_chan;
959 args[1] = attr_number;
960 front = lp_build_intrinsic(gallivm->builder, intr_name,
961 input_type, args, args[3] ? 4 : 3,
962 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
963
964 args[1] = back_attr_number;
965 back = lp_build_intrinsic(gallivm->builder, intr_name,
966 input_type, args, args[3] ? 4 : 3,
967 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
968
969 radeon_bld->inputs[soa_index] =
970 LLVMBuildSelect(gallivm->builder,
971 is_face_positive,
972 front,
973 back,
974 "");
975 }
976
977 shader->nparam++;
978 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
979 LLVMValueRef args[4];
980
981 args[0] = uint->zero;
982 args[1] = attr_number;
983 args[2] = params;
984 args[3] = interp_param;
985 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
986 lp_build_intrinsic(gallivm->builder, intr_name,
987 input_type, args, args[3] ? 4 : 3,
988 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
989 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
990 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
991 lp_build_const_float(gallivm, 0.0f);
992 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
993 lp_build_const_float(gallivm, 1.0f);
994 } else {
995 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
996 LLVMValueRef args[4];
997 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
998 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
999 args[0] = llvm_chan;
1000 args[1] = attr_number;
1001 args[2] = params;
1002 args[3] = interp_param;
1003 radeon_bld->inputs[soa_index] =
1004 lp_build_intrinsic(gallivm->builder, intr_name,
1005 input_type, args, args[3] ? 4 : 3,
1006 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1007 }
1008 }
1009 }
1010
1011 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1012 {
1013 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1014 SI_PARAM_ANCILLARY, 8, 4);
1015 }
1016
1017 /**
1018 * Load a dword from a constant buffer.
1019 */
1020 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1021 LLVMValueRef offset, LLVMTypeRef return_type)
1022 {
1023 LLVMValueRef args[2] = {resource, offset};
1024
1025 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1026 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1027 }
1028
1029 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1030 {
1031 struct si_shader_context *si_shader_ctx =
1032 si_shader_context(&radeon_bld->soa.bld_base);
1033 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1034 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1035 LLVMBuilderRef builder = gallivm->builder;
1036 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1037 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1038 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1039
1040 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1041 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1042 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1043
1044 LLVMValueRef pos[4] = {
1045 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1046 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1047 lp_build_const_float(gallivm, 0),
1048 lp_build_const_float(gallivm, 0)
1049 };
1050
1051 return lp_build_gather_values(gallivm, pos, 4);
1052 }
1053
1054 static void declare_system_value(
1055 struct radeon_llvm_context * radeon_bld,
1056 unsigned index,
1057 const struct tgsi_full_declaration *decl)
1058 {
1059 struct si_shader_context *si_shader_ctx =
1060 si_shader_context(&radeon_bld->soa.bld_base);
1061 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1062 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1063 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1064 LLVMValueRef value = 0;
1065
1066 switch (decl->Semantic.Name) {
1067 case TGSI_SEMANTIC_INSTANCEID:
1068 value = LLVMGetParam(radeon_bld->main_fn,
1069 si_shader_ctx->param_instance_id);
1070 break;
1071
1072 case TGSI_SEMANTIC_VERTEXID:
1073 value = LLVMBuildAdd(gallivm->builder,
1074 LLVMGetParam(radeon_bld->main_fn,
1075 si_shader_ctx->param_vertex_id),
1076 LLVMGetParam(radeon_bld->main_fn,
1077 SI_PARAM_BASE_VERTEX), "");
1078 break;
1079
1080 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1081 value = LLVMGetParam(radeon_bld->main_fn,
1082 si_shader_ctx->param_vertex_id);
1083 break;
1084
1085 case TGSI_SEMANTIC_BASEVERTEX:
1086 value = LLVMGetParam(radeon_bld->main_fn,
1087 SI_PARAM_BASE_VERTEX);
1088 break;
1089
1090 case TGSI_SEMANTIC_INVOCATIONID:
1091 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1092 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1093 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1094 value = LLVMGetParam(radeon_bld->main_fn,
1095 SI_PARAM_GS_INSTANCE_ID);
1096 else
1097 assert(!"INVOCATIONID not implemented");
1098 break;
1099
1100 case TGSI_SEMANTIC_POSITION:
1101 {
1102 LLVMValueRef pos[4] = {
1103 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1104 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1105 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1106 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1107 LLVMGetParam(radeon_bld->main_fn,
1108 SI_PARAM_POS_W_FLOAT)),
1109 };
1110 value = lp_build_gather_values(gallivm, pos, 4);
1111 break;
1112 }
1113
1114 case TGSI_SEMANTIC_FACE:
1115 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1116 break;
1117
1118 case TGSI_SEMANTIC_SAMPLEID:
1119 value = get_sample_id(radeon_bld);
1120 break;
1121
1122 case TGSI_SEMANTIC_SAMPLEPOS:
1123 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1124 break;
1125
1126 case TGSI_SEMANTIC_SAMPLEMASK:
1127 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1128 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1129 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1130 value = uint_bld->one;
1131 else
1132 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1133 break;
1134
1135 case TGSI_SEMANTIC_TESSCOORD:
1136 {
1137 LLVMValueRef coord[4] = {
1138 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1139 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1140 bld->zero,
1141 bld->zero
1142 };
1143
1144 /* For triangles, the vector should be (u, v, 1-u-v). */
1145 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1146 PIPE_PRIM_TRIANGLES)
1147 coord[2] = lp_build_sub(bld, bld->one,
1148 lp_build_add(bld, coord[0], coord[1]));
1149
1150 value = lp_build_gather_values(gallivm, coord, 4);
1151 break;
1152 }
1153
1154 case TGSI_SEMANTIC_VERTICESIN:
1155 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1156 break;
1157
1158 case TGSI_SEMANTIC_TESSINNER:
1159 case TGSI_SEMANTIC_TESSOUTER:
1160 {
1161 LLVMValueRef dw_addr;
1162 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1163
1164 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1165 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1166 lp_build_const_int32(gallivm, param * 4), "");
1167
1168 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1169 ~0, dw_addr);
1170 break;
1171 }
1172
1173 case TGSI_SEMANTIC_PRIMID:
1174 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1175 break;
1176
1177 default:
1178 assert(!"unknown system value");
1179 return;
1180 }
1181
1182 radeon_bld->system_values[index] = value;
1183 }
1184
1185 static LLVMValueRef fetch_constant(
1186 struct lp_build_tgsi_context * bld_base,
1187 const struct tgsi_full_src_register *reg,
1188 enum tgsi_opcode_type type,
1189 unsigned swizzle)
1190 {
1191 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1192 struct lp_build_context * base = &bld_base->base;
1193 const struct tgsi_ind_register *ireg = &reg->Indirect;
1194 unsigned buf, idx;
1195
1196 LLVMValueRef addr, bufp;
1197 LLVMValueRef result;
1198
1199 if (swizzle == LP_CHAN_ALL) {
1200 unsigned chan;
1201 LLVMValueRef values[4];
1202 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1203 values[chan] = fetch_constant(bld_base, reg, type, chan);
1204
1205 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1206 }
1207
1208 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1209 idx = reg->Register.Index * 4 + swizzle;
1210
1211 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1212 if (type != TGSI_TYPE_DOUBLE)
1213 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1214 else {
1215 return radeon_llvm_emit_fetch_double(bld_base,
1216 si_shader_ctx->constants[buf][idx],
1217 si_shader_ctx->constants[buf][idx + 1]);
1218 }
1219 }
1220
1221 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1222 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1223 LLVMValueRef index;
1224 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1225 reg->Dimension.Index);
1226 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1227 } else
1228 bufp = si_shader_ctx->const_buffers[buf];
1229
1230 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1231 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1232 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1233 addr = lp_build_add(&bld_base->uint_bld, addr,
1234 lp_build_const_int32(base->gallivm, idx * 4));
1235
1236 result = buffer_load_const(base->gallivm->builder, bufp,
1237 addr, bld_base->base.elem_type);
1238
1239 if (type != TGSI_TYPE_DOUBLE)
1240 result = bitcast(bld_base, type, result);
1241 else {
1242 LLVMValueRef addr2, result2;
1243 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1244 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1245 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1246 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1247 lp_build_const_int32(base->gallivm, idx * 4));
1248
1249 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1250 addr2, bld_base->base.elem_type);
1251
1252 result = radeon_llvm_emit_fetch_double(bld_base,
1253 result, result2);
1254 }
1255 return result;
1256 }
1257
1258 /* Initialize arguments for the shader export intrinsic */
1259 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1260 LLVMValueRef *values,
1261 unsigned target,
1262 LLVMValueRef *args)
1263 {
1264 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1265 struct lp_build_context *uint =
1266 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1267 struct lp_build_context *base = &bld_base->base;
1268 unsigned compressed = 0;
1269 unsigned chan;
1270
1271 /* XXX: This controls which components of the output
1272 * registers actually get exported. (e.g bit 0 means export
1273 * X component, bit 1 means export Y component, etc.) I'm
1274 * hard coding this to 0xf for now. In the future, we might
1275 * want to do something else.
1276 */
1277 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1278
1279 /* Specify whether the EXEC mask represents the valid mask */
1280 args[1] = uint->zero;
1281
1282 /* Specify whether this is the last export */
1283 args[2] = uint->zero;
1284
1285 /* Specify the target we are exporting */
1286 args[3] = lp_build_const_int32(base->gallivm, target);
1287
1288 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1289 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1290
1291 if (cbuf >= 0 && cbuf < 8)
1292 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1293 }
1294
1295 /* Set COMPR flag */
1296 args[4] = compressed ? uint->one : uint->zero;
1297
1298 if (compressed) {
1299 /* Pixel shader needs to pack output values before export */
1300 for (chan = 0; chan < 2; chan++) {
1301 LLVMValueRef pack_args[2] = {
1302 values[2 * chan],
1303 values[2 * chan + 1]
1304 };
1305 LLVMValueRef packed;
1306
1307 packed = lp_build_intrinsic(base->gallivm->builder,
1308 "llvm.SI.packf16",
1309 LLVMInt32TypeInContext(base->gallivm->context),
1310 pack_args, 2,
1311 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1312 args[chan + 5] =
1313 LLVMBuildBitCast(base->gallivm->builder,
1314 packed,
1315 LLVMFloatTypeInContext(base->gallivm->context),
1316 "");
1317 args[chan + 7] = base->undef;
1318 }
1319 } else
1320 memcpy(&args[5], values, sizeof(values[0]) * 4);
1321 }
1322
1323 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1324 LLVMValueRef alpha)
1325 {
1326 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1327 struct gallivm_state *gallivm = bld_base->base.gallivm;
1328
1329 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1330 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1331 SI_PARAM_ALPHA_REF);
1332
1333 LLVMValueRef alpha_pass =
1334 lp_build_cmp(&bld_base->base,
1335 si_shader_ctx->shader->key.ps.alpha_func,
1336 alpha, alpha_ref);
1337 LLVMValueRef arg =
1338 lp_build_select(&bld_base->base,
1339 alpha_pass,
1340 lp_build_const_float(gallivm, 1.0f),
1341 lp_build_const_float(gallivm, -1.0f));
1342
1343 lp_build_intrinsic(gallivm->builder,
1344 "llvm.AMDGPU.kill",
1345 LLVMVoidTypeInContext(gallivm->context),
1346 &arg, 1, 0);
1347 } else {
1348 lp_build_intrinsic(gallivm->builder,
1349 "llvm.AMDGPU.kilp",
1350 LLVMVoidTypeInContext(gallivm->context),
1351 NULL, 0, 0);
1352 }
1353 }
1354
1355 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1356 LLVMValueRef alpha)
1357 {
1358 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1359 struct gallivm_state *gallivm = bld_base->base.gallivm;
1360 LLVMValueRef coverage;
1361
1362 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1363 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1364 SI_PARAM_SAMPLE_COVERAGE);
1365 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1366
1367 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1368 bld_base->int_bld.elem_type,
1369 &coverage, 1, LLVMReadNoneAttribute);
1370
1371 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1372 bld_base->base.elem_type, "");
1373
1374 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1375 lp_build_const_float(gallivm,
1376 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1377
1378 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1379 }
1380
1381 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1382 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1383 {
1384 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1385 struct lp_build_context *base = &bld_base->base;
1386 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1387 unsigned reg_index;
1388 unsigned chan;
1389 unsigned const_chan;
1390 LLVMValueRef base_elt;
1391 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1392 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1393 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1394
1395 for (reg_index = 0; reg_index < 2; reg_index ++) {
1396 LLVMValueRef *args = pos[2 + reg_index];
1397
1398 args[5] =
1399 args[6] =
1400 args[7] =
1401 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1402
1403 /* Compute dot products of position and user clip plane vectors */
1404 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1405 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1406 args[1] = lp_build_const_int32(base->gallivm,
1407 ((reg_index * 4 + chan) * 4 +
1408 const_chan) * 4);
1409 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1410 args[1], base->elem_type);
1411 args[5 + chan] =
1412 lp_build_add(base, args[5 + chan],
1413 lp_build_mul(base, base_elt,
1414 out_elts[const_chan]));
1415 }
1416 }
1417
1418 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1419 args[1] = uint->zero;
1420 args[2] = uint->zero;
1421 args[3] = lp_build_const_int32(base->gallivm,
1422 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1423 args[4] = uint->zero;
1424 }
1425 }
1426
1427 static void si_dump_streamout(struct pipe_stream_output_info *so)
1428 {
1429 unsigned i;
1430
1431 if (so->num_outputs)
1432 fprintf(stderr, "STREAMOUT\n");
1433
1434 for (i = 0; i < so->num_outputs; i++) {
1435 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1436 so->output[i].start_component;
1437 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1438 i, so->output[i].output_buffer,
1439 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1440 so->output[i].register_index,
1441 mask & 1 ? "x" : "",
1442 mask & 2 ? "y" : "",
1443 mask & 4 ? "z" : "",
1444 mask & 8 ? "w" : "");
1445 }
1446 }
1447
1448 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1449 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1450 * or v4i32 (num_channels=3,4). */
1451 static void build_tbuffer_store(struct si_shader_context *shader,
1452 LLVMValueRef rsrc,
1453 LLVMValueRef vdata,
1454 unsigned num_channels,
1455 LLVMValueRef vaddr,
1456 LLVMValueRef soffset,
1457 unsigned inst_offset,
1458 unsigned dfmt,
1459 unsigned nfmt,
1460 unsigned offen,
1461 unsigned idxen,
1462 unsigned glc,
1463 unsigned slc,
1464 unsigned tfe)
1465 {
1466 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1467 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1468 LLVMValueRef args[] = {
1469 rsrc,
1470 vdata,
1471 LLVMConstInt(i32, num_channels, 0),
1472 vaddr,
1473 soffset,
1474 LLVMConstInt(i32, inst_offset, 0),
1475 LLVMConstInt(i32, dfmt, 0),
1476 LLVMConstInt(i32, nfmt, 0),
1477 LLVMConstInt(i32, offen, 0),
1478 LLVMConstInt(i32, idxen, 0),
1479 LLVMConstInt(i32, glc, 0),
1480 LLVMConstInt(i32, slc, 0),
1481 LLVMConstInt(i32, tfe, 0)
1482 };
1483
1484 /* The instruction offset field has 12 bits */
1485 assert(offen || inst_offset < (1 << 12));
1486
1487 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1488 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1489 const char *types[] = {"i32", "v2i32", "v4i32"};
1490 char name[256];
1491 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1492
1493 lp_build_intrinsic(gallivm->builder, name,
1494 LLVMVoidTypeInContext(gallivm->context),
1495 args, Elements(args), 0);
1496 }
1497
1498 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1499 LLVMValueRef rsrc,
1500 LLVMValueRef vdata,
1501 unsigned num_channels,
1502 LLVMValueRef vaddr,
1503 LLVMValueRef soffset,
1504 unsigned inst_offset)
1505 {
1506 static unsigned dfmt[] = {
1507 V_008F0C_BUF_DATA_FORMAT_32,
1508 V_008F0C_BUF_DATA_FORMAT_32_32,
1509 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1510 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1511 };
1512 assert(num_channels >= 1 && num_channels <= 4);
1513
1514 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1515 inst_offset, dfmt[num_channels-1],
1516 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1517 }
1518
1519 /* On SI, the vertex shader is responsible for writing streamout data
1520 * to buffers. */
1521 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1522 struct si_shader_output_values *outputs,
1523 unsigned noutput)
1524 {
1525 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1526 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1527 LLVMBuilderRef builder = gallivm->builder;
1528 int i, j;
1529 struct lp_build_if_state if_ctx;
1530
1531 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1532
1533 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1534 LLVMValueRef so_vtx_count =
1535 unpack_param(shader, shader->param_streamout_config, 16, 7);
1536
1537 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1538 NULL, 0, LLVMReadNoneAttribute);
1539
1540 /* can_emit = tid < so_vtx_count; */
1541 LLVMValueRef can_emit =
1542 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1543
1544 LLVMValueRef stream_id =
1545 unpack_param(shader, shader->param_streamout_config, 24, 2);
1546
1547 /* Emit the streamout code conditionally. This actually avoids
1548 * out-of-bounds buffer access. The hw tells us via the SGPR
1549 * (so_vtx_count) which threads are allowed to emit streamout data. */
1550 lp_build_if(&if_ctx, gallivm, can_emit);
1551 {
1552 /* The buffer offset is computed as follows:
1553 * ByteOffset = streamout_offset[buffer_id]*4 +
1554 * (streamout_write_index + thread_id)*stride[buffer_id] +
1555 * attrib_offset
1556 */
1557
1558 LLVMValueRef so_write_index =
1559 LLVMGetParam(shader->radeon_bld.main_fn,
1560 shader->param_streamout_write_index);
1561
1562 /* Compute (streamout_write_index + thread_id). */
1563 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1564
1565 /* Compute the write offset for each enabled buffer. */
1566 LLVMValueRef so_write_offset[4] = {};
1567 for (i = 0; i < 4; i++) {
1568 if (!so->stride[i])
1569 continue;
1570
1571 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1572 shader->param_streamout_offset[i]);
1573 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1574
1575 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1576 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1577 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1578 }
1579
1580 /* Write streamout data. */
1581 for (i = 0; i < so->num_outputs; i++) {
1582 unsigned buf_idx = so->output[i].output_buffer;
1583 unsigned reg = so->output[i].register_index;
1584 unsigned start = so->output[i].start_component;
1585 unsigned num_comps = so->output[i].num_components;
1586 unsigned stream = so->output[i].stream;
1587 LLVMValueRef out[4];
1588 struct lp_build_if_state if_ctx_stream;
1589
1590 assert(num_comps && num_comps <= 4);
1591 if (!num_comps || num_comps > 4)
1592 continue;
1593
1594 if (reg >= noutput)
1595 continue;
1596
1597 /* Load the output as int. */
1598 for (j = 0; j < num_comps; j++) {
1599 out[j] = LLVMBuildBitCast(builder,
1600 outputs[reg].values[start+j],
1601 i32, "");
1602 }
1603
1604 /* Pack the output. */
1605 LLVMValueRef vdata = NULL;
1606
1607 switch (num_comps) {
1608 case 1: /* as i32 */
1609 vdata = out[0];
1610 break;
1611 case 2: /* as v2i32 */
1612 case 3: /* as v4i32 (aligned to 4) */
1613 case 4: /* as v4i32 */
1614 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1615 for (j = 0; j < num_comps; j++) {
1616 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1617 LLVMConstInt(i32, j, 0), "");
1618 }
1619 break;
1620 }
1621
1622 LLVMValueRef can_emit_stream =
1623 LLVMBuildICmp(builder, LLVMIntEQ,
1624 stream_id,
1625 lp_build_const_int32(gallivm, stream), "");
1626
1627 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1628 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1629 vdata, num_comps,
1630 so_write_offset[buf_idx],
1631 LLVMConstInt(i32, 0, 0),
1632 so->output[i].dst_offset*4);
1633 lp_build_endif(&if_ctx_stream);
1634 }
1635 }
1636 lp_build_endif(&if_ctx);
1637 }
1638
1639
1640 /* Generate export instructions for hardware VS shader stage */
1641 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1642 struct si_shader_output_values *outputs,
1643 unsigned noutput)
1644 {
1645 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1646 struct si_shader * shader = si_shader_ctx->shader;
1647 struct lp_build_context * base = &bld_base->base;
1648 struct lp_build_context * uint =
1649 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1650 LLVMValueRef args[9];
1651 LLVMValueRef pos_args[4][9] = { { 0 } };
1652 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1653 unsigned semantic_name, semantic_index;
1654 unsigned target;
1655 unsigned param_count = 0;
1656 unsigned pos_idx;
1657 int i;
1658
1659 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1660 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1661 }
1662
1663 for (i = 0; i < noutput; i++) {
1664 semantic_name = outputs[i].name;
1665 semantic_index = outputs[i].sid;
1666
1667 handle_semantic:
1668 /* Select the correct target */
1669 switch(semantic_name) {
1670 case TGSI_SEMANTIC_PSIZE:
1671 psize_value = outputs[i].values[0];
1672 continue;
1673 case TGSI_SEMANTIC_EDGEFLAG:
1674 edgeflag_value = outputs[i].values[0];
1675 continue;
1676 case TGSI_SEMANTIC_LAYER:
1677 layer_value = outputs[i].values[0];
1678 semantic_name = TGSI_SEMANTIC_GENERIC;
1679 goto handle_semantic;
1680 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1681 viewport_index_value = outputs[i].values[0];
1682 semantic_name = TGSI_SEMANTIC_GENERIC;
1683 goto handle_semantic;
1684 case TGSI_SEMANTIC_POSITION:
1685 target = V_008DFC_SQ_EXP_POS;
1686 break;
1687 case TGSI_SEMANTIC_COLOR:
1688 case TGSI_SEMANTIC_BCOLOR:
1689 target = V_008DFC_SQ_EXP_PARAM + param_count;
1690 shader->vs_output_param_offset[i] = param_count;
1691 param_count++;
1692 break;
1693 case TGSI_SEMANTIC_CLIPDIST:
1694 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1695 break;
1696 case TGSI_SEMANTIC_CLIPVERTEX:
1697 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1698 continue;
1699 case TGSI_SEMANTIC_PRIMID:
1700 case TGSI_SEMANTIC_FOG:
1701 case TGSI_SEMANTIC_TEXCOORD:
1702 case TGSI_SEMANTIC_GENERIC:
1703 target = V_008DFC_SQ_EXP_PARAM + param_count;
1704 shader->vs_output_param_offset[i] = param_count;
1705 param_count++;
1706 break;
1707 default:
1708 target = 0;
1709 fprintf(stderr,
1710 "Warning: SI unhandled vs output type:%d\n",
1711 semantic_name);
1712 }
1713
1714 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1715
1716 if (target >= V_008DFC_SQ_EXP_POS &&
1717 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1718 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1719 args, sizeof(args));
1720 } else {
1721 lp_build_intrinsic(base->gallivm->builder,
1722 "llvm.SI.export",
1723 LLVMVoidTypeInContext(base->gallivm->context),
1724 args, 9, 0);
1725 }
1726
1727 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1728 semantic_name = TGSI_SEMANTIC_GENERIC;
1729 goto handle_semantic;
1730 }
1731 }
1732
1733 shader->nr_param_exports = param_count;
1734
1735 /* We need to add the position output manually if it's missing. */
1736 if (!pos_args[0][0]) {
1737 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1738 pos_args[0][1] = uint->zero; /* EXEC mask */
1739 pos_args[0][2] = uint->zero; /* last export? */
1740 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1741 pos_args[0][4] = uint->zero; /* COMPR flag */
1742 pos_args[0][5] = base->zero; /* X */
1743 pos_args[0][6] = base->zero; /* Y */
1744 pos_args[0][7] = base->zero; /* Z */
1745 pos_args[0][8] = base->one; /* W */
1746 }
1747
1748 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1749 if (shader->selector->info.writes_psize ||
1750 shader->selector->info.writes_edgeflag ||
1751 shader->selector->info.writes_viewport_index ||
1752 shader->selector->info.writes_layer) {
1753 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1754 shader->selector->info.writes_psize |
1755 (shader->selector->info.writes_edgeflag << 1) |
1756 (shader->selector->info.writes_layer << 2) |
1757 (shader->selector->info.writes_viewport_index << 3));
1758 pos_args[1][1] = uint->zero; /* EXEC mask */
1759 pos_args[1][2] = uint->zero; /* last export? */
1760 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1761 pos_args[1][4] = uint->zero; /* COMPR flag */
1762 pos_args[1][5] = base->zero; /* X */
1763 pos_args[1][6] = base->zero; /* Y */
1764 pos_args[1][7] = base->zero; /* Z */
1765 pos_args[1][8] = base->zero; /* W */
1766
1767 if (shader->selector->info.writes_psize)
1768 pos_args[1][5] = psize_value;
1769
1770 if (shader->selector->info.writes_edgeflag) {
1771 /* The output is a float, but the hw expects an integer
1772 * with the first bit containing the edge flag. */
1773 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1774 edgeflag_value,
1775 bld_base->uint_bld.elem_type, "");
1776 edgeflag_value = lp_build_min(&bld_base->int_bld,
1777 edgeflag_value,
1778 bld_base->int_bld.one);
1779
1780 /* The LLVM intrinsic expects a float. */
1781 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1782 edgeflag_value,
1783 base->elem_type, "");
1784 }
1785
1786 if (shader->selector->info.writes_layer)
1787 pos_args[1][7] = layer_value;
1788
1789 if (shader->selector->info.writes_viewport_index)
1790 pos_args[1][8] = viewport_index_value;
1791 }
1792
1793 for (i = 0; i < 4; i++)
1794 if (pos_args[i][0])
1795 shader->nr_pos_exports++;
1796
1797 pos_idx = 0;
1798 for (i = 0; i < 4; i++) {
1799 if (!pos_args[i][0])
1800 continue;
1801
1802 /* Specify the target we are exporting */
1803 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1804
1805 if (pos_idx == shader->nr_pos_exports)
1806 /* Specify that this is the last export */
1807 pos_args[i][2] = uint->one;
1808
1809 lp_build_intrinsic(base->gallivm->builder,
1810 "llvm.SI.export",
1811 LLVMVoidTypeInContext(base->gallivm->context),
1812 pos_args[i], 9, 0);
1813 }
1814 }
1815
1816 /* This only writes the tessellation factor levels. */
1817 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1818 {
1819 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1820 struct gallivm_state *gallivm = bld_base->base.gallivm;
1821 struct si_shader *shader = si_shader_ctx->shader;
1822 unsigned tess_inner_index, tess_outer_index;
1823 LLVMValueRef lds_base, lds_inner, lds_outer;
1824 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1825 LLVMValueRef out[6], vec0, vec1, invocation_id;
1826 unsigned stride, outer_comps, inner_comps, i;
1827 struct lp_build_if_state if_ctx;
1828
1829 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1830
1831 /* Do this only for invocation 0, because the tess levels are per-patch,
1832 * not per-vertex.
1833 *
1834 * This can't jump, because invocation 0 executes this. It should
1835 * at least mask out the loads and stores for other invocations.
1836 */
1837 lp_build_if(&if_ctx, gallivm,
1838 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1839 invocation_id, bld_base->uint_bld.zero, ""));
1840
1841 /* Determine the layout of one tess factor element in the buffer. */
1842 switch (shader->key.tcs.prim_mode) {
1843 case PIPE_PRIM_LINES:
1844 stride = 2; /* 2 dwords, 1 vec2 store */
1845 outer_comps = 2;
1846 inner_comps = 0;
1847 break;
1848 case PIPE_PRIM_TRIANGLES:
1849 stride = 4; /* 4 dwords, 1 vec4 store */
1850 outer_comps = 3;
1851 inner_comps = 1;
1852 break;
1853 case PIPE_PRIM_QUADS:
1854 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1855 outer_comps = 4;
1856 inner_comps = 2;
1857 break;
1858 default:
1859 assert(0);
1860 return;
1861 }
1862
1863 /* Load tess_inner and tess_outer from LDS.
1864 * Any invocation can write them, so we can't get them from a temporary.
1865 */
1866 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1867 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1868
1869 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1870 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1871 lp_build_const_int32(gallivm,
1872 tess_inner_index * 4), "");
1873 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1874 lp_build_const_int32(gallivm,
1875 tess_outer_index * 4), "");
1876
1877 for (i = 0; i < outer_comps; i++)
1878 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1879 for (i = 0; i < inner_comps; i++)
1880 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1881
1882 /* Convert the outputs to vectors for stores. */
1883 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1884 vec1 = NULL;
1885
1886 if (stride > 4)
1887 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1888
1889 /* Get the buffer. */
1890 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1891 SI_PARAM_RW_BUFFERS);
1892 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1893 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1894
1895 /* Get the offset. */
1896 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1897 SI_PARAM_TESS_FACTOR_OFFSET);
1898 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1899 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1900 lp_build_const_int32(gallivm, 4 * stride), "");
1901
1902 /* Store the outputs. */
1903 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1904 MIN2(stride, 4), byteoffset, tf_base, 0);
1905 if (vec1)
1906 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1907 stride - 4, byteoffset, tf_base, 16);
1908 lp_build_endif(&if_ctx);
1909 }
1910
1911 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1912 {
1913 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1914 struct si_shader *shader = si_shader_ctx->shader;
1915 struct tgsi_shader_info *info = &shader->selector->info;
1916 struct gallivm_state *gallivm = bld_base->base.gallivm;
1917 unsigned i, chan;
1918 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1919 si_shader_ctx->param_rel_auto_id);
1920 LLVMValueRef vertex_dw_stride =
1921 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1922 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1923 vertex_dw_stride, "");
1924
1925 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1926 * its inputs from it. */
1927 for (i = 0; i < info->num_outputs; i++) {
1928 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1929 unsigned name = info->output_semantic_name[i];
1930 unsigned index = info->output_semantic_index[i];
1931 int param = si_shader_io_get_unique_index(name, index);
1932 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1933 lp_build_const_int32(gallivm, param * 4), "");
1934
1935 for (chan = 0; chan < 4; chan++) {
1936 lds_store(bld_base, chan, dw_addr,
1937 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1938 }
1939 }
1940 }
1941
1942 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1943 {
1944 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1945 struct gallivm_state *gallivm = bld_base->base.gallivm;
1946 struct si_shader *es = si_shader_ctx->shader;
1947 struct tgsi_shader_info *info = &es->selector->info;
1948 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1949 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1950 si_shader_ctx->param_es2gs_offset);
1951 unsigned chan;
1952 int i;
1953
1954 for (i = 0; i < info->num_outputs; i++) {
1955 LLVMValueRef *out_ptr =
1956 si_shader_ctx->radeon_bld.soa.outputs[i];
1957 int param_index;
1958
1959 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1960 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1961 continue;
1962
1963 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
1964 info->output_semantic_index[i]);
1965
1966 for (chan = 0; chan < 4; chan++) {
1967 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1968 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1969
1970 build_tbuffer_store(si_shader_ctx,
1971 si_shader_ctx->esgs_ring,
1972 out_val, 1,
1973 LLVMGetUndef(i32), soffset,
1974 (4 * param_index + chan) * 4,
1975 V_008F0C_BUF_DATA_FORMAT_32,
1976 V_008F0C_BUF_NUM_FORMAT_UINT,
1977 0, 0, 1, 1, 0);
1978 }
1979 }
1980 }
1981
1982 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1983 {
1984 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1985 struct gallivm_state *gallivm = bld_base->base.gallivm;
1986 LLVMValueRef args[2];
1987
1988 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1989 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1990 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1991 LLVMVoidTypeInContext(gallivm->context), args, 2,
1992 LLVMNoUnwindAttribute);
1993 }
1994
1995 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1996 {
1997 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1998 struct gallivm_state *gallivm = bld_base->base.gallivm;
1999 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2000 struct si_shader_output_values *outputs = NULL;
2001 int i,j;
2002
2003 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2004
2005 /* Vertex color clamping.
2006 *
2007 * This uses a state constant loaded in a user data SGPR and
2008 * an IF statement is added that clamps all colors if the constant
2009 * is true.
2010 */
2011 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2012 !si_shader_ctx->shader->is_gs_copy_shader) {
2013 struct lp_build_if_state if_ctx;
2014 LLVMValueRef cond = NULL;
2015 LLVMValueRef addr, val;
2016
2017 for (i = 0; i < info->num_outputs; i++) {
2018 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2019 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2020 continue;
2021
2022 /* We've found a color. */
2023 if (!cond) {
2024 /* The state is in the first bit of the user SGPR. */
2025 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2026 SI_PARAM_VS_STATE_BITS);
2027 cond = LLVMBuildTrunc(gallivm->builder, cond,
2028 LLVMInt1TypeInContext(gallivm->context), "");
2029 lp_build_if(&if_ctx, gallivm, cond);
2030 }
2031
2032 for (j = 0; j < 4; j++) {
2033 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2034 val = LLVMBuildLoad(gallivm->builder, addr, "");
2035 val = radeon_llvm_saturate(bld_base, val);
2036 LLVMBuildStore(gallivm->builder, val, addr);
2037 }
2038 }
2039
2040 if (cond)
2041 lp_build_endif(&if_ctx);
2042 }
2043
2044 for (i = 0; i < info->num_outputs; i++) {
2045 outputs[i].name = info->output_semantic_name[i];
2046 outputs[i].sid = info->output_semantic_index[i];
2047
2048 for (j = 0; j < 4; j++)
2049 outputs[i].values[j] =
2050 LLVMBuildLoad(gallivm->builder,
2051 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2052 "");
2053 }
2054
2055 /* Export PrimitiveID when PS needs it. */
2056 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2057 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2058 outputs[i].sid = 0;
2059 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2060 get_primitive_id(bld_base, 0));
2061 outputs[i].values[1] = bld_base->base.undef;
2062 outputs[i].values[2] = bld_base->base.undef;
2063 outputs[i].values[3] = bld_base->base.undef;
2064 i++;
2065 }
2066
2067 si_llvm_export_vs(bld_base, outputs, i);
2068 FREE(outputs);
2069 }
2070
2071 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2072 LLVMValueRef depth, LLVMValueRef stencil,
2073 LLVMValueRef samplemask)
2074 {
2075 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2076 struct lp_build_context *base = &bld_base->base;
2077 struct lp_build_context *uint = &bld_base->uint_bld;
2078 LLVMValueRef args[9];
2079 unsigned mask = 0;
2080
2081 assert(depth || stencil || samplemask);
2082
2083 args[1] = uint->one; /* whether the EXEC mask is valid */
2084 args[2] = uint->one; /* DONE bit */
2085
2086 /* Specify the target we are exporting */
2087 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2088
2089 args[4] = uint->zero; /* COMP flag */
2090 args[5] = base->undef; /* R, depth */
2091 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2092 args[7] = base->undef; /* B, sample mask */
2093 args[8] = base->undef; /* A, alpha to mask */
2094
2095 if (depth) {
2096 args[5] = depth;
2097 mask |= 0x1;
2098 }
2099
2100 if (stencil) {
2101 args[6] = stencil;
2102 mask |= 0x2;
2103 }
2104
2105 if (samplemask) {
2106 args[7] = samplemask;
2107 mask |= 0x4;
2108 }
2109
2110 /* SI (except OLAND) has a bug that it only looks
2111 * at the X writemask component. */
2112 if (sscreen->b.chip_class == SI &&
2113 sscreen->b.family != CHIP_OLAND)
2114 mask |= 0x1;
2115
2116 /* Specify which components to enable */
2117 args[0] = lp_build_const_int32(base->gallivm, mask);
2118
2119 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2120 LLVMVoidTypeInContext(base->gallivm->context),
2121 args, 9, 0);
2122 }
2123
2124 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2125 LLVMValueRef *color, unsigned index,
2126 bool is_last)
2127 {
2128 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2129 struct lp_build_context *base = &bld_base->base;
2130 LLVMValueRef args[9];
2131 int i;
2132
2133 /* Clamp color */
2134 if (si_shader_ctx->shader->key.ps.clamp_color)
2135 for (i = 0; i < 4; i++)
2136 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2137
2138 /* Alpha to one */
2139 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2140 color[3] = base->one;
2141
2142 /* Alpha test */
2143 if (index == 0 &&
2144 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2145 si_alpha_test(bld_base, color[3]);
2146
2147 /* Line & polygon smoothing */
2148 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2149 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2150
2151 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2152 if (index == 0 &&
2153 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2154 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2155 si_llvm_init_export_args(bld_base, color,
2156 V_008DFC_SQ_EXP_MRT + c, args);
2157 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2158 LLVMVoidTypeInContext(base->gallivm->context),
2159 args, 9, 0);
2160 }
2161 }
2162
2163 /* Export */
2164 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2165 args);
2166 if (is_last) {
2167 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2168 args[2] = bld_base->uint_bld.one; /* DONE bit */
2169 }
2170 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2171 LLVMVoidTypeInContext(base->gallivm->context),
2172 args, 9, 0);
2173 }
2174
2175 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2176 {
2177 struct lp_build_context *base = &bld_base->base;
2178 struct lp_build_context *uint = &bld_base->uint_bld;
2179 LLVMValueRef args[9];
2180
2181 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2182 args[1] = uint->one; /* whether the EXEC mask is valid */
2183 args[2] = uint->one; /* DONE bit */
2184 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2185 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2186 args[5] = uint->undef; /* R */
2187 args[6] = uint->undef; /* G */
2188 args[7] = uint->undef; /* B */
2189 args[8] = uint->undef; /* A */
2190
2191 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2192 LLVMVoidTypeInContext(base->gallivm->context),
2193 args, 9, 0);
2194 }
2195
2196 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2197 {
2198 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2199 struct si_shader * shader = si_shader_ctx->shader;
2200 struct lp_build_context * base = &bld_base->base;
2201 struct tgsi_shader_info *info = &shader->selector->info;
2202 LLVMBuilderRef builder = base->gallivm->builder;
2203 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2204 int last_color_export = -1;
2205 int i;
2206
2207 /* If there are no outputs, add a dummy export. */
2208 if (!info->num_outputs) {
2209 si_export_null(bld_base);
2210 return;
2211 }
2212
2213 /* Determine the last export. If MRTZ is present, it's always last.
2214 * Otherwise, find the last color export.
2215 */
2216 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2217 for (i = 0; i < info->num_outputs; i++)
2218 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2219 last_color_export = i;
2220
2221 for (i = 0; i < info->num_outputs; i++) {
2222 unsigned semantic_name = info->output_semantic_name[i];
2223 unsigned semantic_index = info->output_semantic_index[i];
2224 unsigned j;
2225 LLVMValueRef color[4] = {};
2226
2227 /* Select the correct target */
2228 switch (semantic_name) {
2229 case TGSI_SEMANTIC_POSITION:
2230 depth = LLVMBuildLoad(builder,
2231 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2232 break;
2233 case TGSI_SEMANTIC_STENCIL:
2234 stencil = LLVMBuildLoad(builder,
2235 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2236 break;
2237 case TGSI_SEMANTIC_SAMPLEMASK:
2238 samplemask = LLVMBuildLoad(builder,
2239 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2240 break;
2241 case TGSI_SEMANTIC_COLOR:
2242 for (j = 0; j < 4; j++)
2243 color[j] = LLVMBuildLoad(builder,
2244 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2245
2246 si_export_mrt_color(bld_base, color, semantic_index,
2247 last_color_export == i);
2248 break;
2249 default:
2250 fprintf(stderr,
2251 "Warning: SI unhandled fs output type:%d\n",
2252 semantic_name);
2253 }
2254 }
2255
2256 if (depth || stencil || samplemask)
2257 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2258 }
2259
2260 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2261 struct lp_build_tgsi_context * bld_base,
2262 struct lp_build_emit_data * emit_data);
2263
2264 static bool tgsi_is_array_sampler(unsigned target)
2265 {
2266 return target == TGSI_TEXTURE_1D_ARRAY ||
2267 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2268 target == TGSI_TEXTURE_2D_ARRAY ||
2269 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2270 target == TGSI_TEXTURE_CUBE_ARRAY ||
2271 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2272 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2273 }
2274
2275 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2276 struct lp_build_emit_data *emit_data,
2277 unsigned opcode, unsigned target,
2278 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2279 LLVMValueRef *param, unsigned count,
2280 unsigned dmask)
2281 {
2282 unsigned num_args;
2283 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2284 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2285
2286 /* Pad to power of two vector */
2287 while (count < util_next_power_of_two(count))
2288 param[count++] = LLVMGetUndef(i32);
2289
2290 /* Texture coordinates. */
2291 if (count > 1)
2292 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2293 else
2294 emit_data->args[0] = param[0];
2295
2296 /* Resource. */
2297 emit_data->args[1] = res_ptr;
2298 num_args = 2;
2299
2300 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2301 emit_data->dst_type = LLVMVectorType(i32, 4);
2302 else {
2303 emit_data->dst_type = LLVMVectorType(
2304 LLVMFloatTypeInContext(gallivm->context), 4);
2305
2306 emit_data->args[num_args++] = samp_ptr;
2307 }
2308
2309 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2310 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2311 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2312 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2313 tgsi_is_array_sampler(target)); /* da */
2314 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2315 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2316 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2317 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2318
2319 emit_data->arg_count = num_args;
2320 }
2321
2322 static const struct lp_build_tgsi_action tex_action;
2323
2324 static void tex_fetch_ptrs(
2325 struct lp_build_tgsi_context * bld_base,
2326 struct lp_build_emit_data * emit_data,
2327 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2328 {
2329 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2330 struct gallivm_state *gallivm = bld_base->base.gallivm;
2331 const struct tgsi_full_instruction * inst = emit_data->inst;
2332 unsigned target = inst->Texture.Texture;
2333 unsigned sampler_src;
2334 unsigned sampler_index;
2335
2336 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2337 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2338
2339 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2340 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2341 LLVMValueRef ind_index;
2342
2343 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2344
2345 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2346 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2347
2348 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2349 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2350
2351 if (target == TGSI_TEXTURE_2D_MSAA ||
2352 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2353 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2354 lp_build_const_int32(gallivm,
2355 SI_FMASK_TEX_OFFSET), "");
2356 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2357 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2358 }
2359 } else {
2360 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2361 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2362 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2363 }
2364 }
2365
2366 static void tex_fetch_args(
2367 struct lp_build_tgsi_context * bld_base,
2368 struct lp_build_emit_data * emit_data)
2369 {
2370 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2371 struct gallivm_state *gallivm = bld_base->base.gallivm;
2372 LLVMBuilderRef builder = gallivm->builder;
2373 const struct tgsi_full_instruction * inst = emit_data->inst;
2374 unsigned opcode = inst->Instruction.Opcode;
2375 unsigned target = inst->Texture.Texture;
2376 LLVMValueRef coords[5], derivs[6];
2377 LLVMValueRef address[16];
2378 int ref_pos;
2379 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2380 unsigned count = 0;
2381 unsigned chan;
2382 unsigned num_deriv_channels = 0;
2383 bool has_offset = inst->Texture.NumOffsets > 0;
2384 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2385 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2386 unsigned dmask = 0xf;
2387
2388 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2389
2390 if (opcode == TGSI_OPCODE_TXQ) {
2391 if (target == TGSI_TEXTURE_BUFFER) {
2392 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2393
2394 /* Read the size from the buffer descriptor directly. */
2395 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2396 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2397 lp_build_const_int32(gallivm, 6), "");
2398
2399 if (si_shader_ctx->screen->b.chip_class >= VI) {
2400 /* On VI, the descriptor contains the size in bytes,
2401 * but TXQ must return the size in elements.
2402 * The stride is always non-zero for resources using TXQ.
2403 */
2404 LLVMValueRef stride =
2405 LLVMBuildExtractElement(builder, res,
2406 lp_build_const_int32(gallivm, 5), "");
2407 stride = LLVMBuildLShr(builder, stride,
2408 lp_build_const_int32(gallivm, 16), "");
2409 stride = LLVMBuildAnd(builder, stride,
2410 lp_build_const_int32(gallivm, 0x3FFF), "");
2411
2412 size = LLVMBuildUDiv(builder, size, stride, "");
2413 }
2414
2415 emit_data->args[0] = size;
2416 return;
2417 }
2418
2419 /* Textures - set the mip level. */
2420 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2421
2422 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2423 NULL, address, count, 0xf);
2424 return;
2425 }
2426
2427 if (target == TGSI_TEXTURE_BUFFER) {
2428 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2429 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2430 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2431 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2432
2433 /* Bitcast and truncate v8i32 to v16i8. */
2434 LLVMValueRef res = res_ptr;
2435 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2436 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2437 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2438
2439 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2440 emit_data->args[0] = res;
2441 emit_data->args[1] = bld_base->uint_bld.zero;
2442 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2443 emit_data->arg_count = 3;
2444 return;
2445 }
2446
2447 /* Fetch and project texture coordinates */
2448 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2449 for (chan = 0; chan < 3; chan++ ) {
2450 coords[chan] = lp_build_emit_fetch(bld_base,
2451 emit_data->inst, 0,
2452 chan);
2453 if (opcode == TGSI_OPCODE_TXP)
2454 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2455 TGSI_OPCODE_DIV,
2456 coords[chan],
2457 coords[3]);
2458 }
2459
2460 if (opcode == TGSI_OPCODE_TXP)
2461 coords[3] = bld_base->base.one;
2462
2463 /* Pack offsets. */
2464 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2465 /* The offsets are six-bit signed integers packed like this:
2466 * X=[5:0], Y=[13:8], and Z=[21:16].
2467 */
2468 LLVMValueRef offset[3], pack;
2469
2470 assert(inst->Texture.NumOffsets == 1);
2471
2472 for (chan = 0; chan < 3; chan++) {
2473 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2474 emit_data->inst, 0, chan);
2475 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2476 lp_build_const_int32(gallivm, 0x3f), "");
2477 if (chan)
2478 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2479 lp_build_const_int32(gallivm, chan*8), "");
2480 }
2481
2482 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2483 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2484 address[count++] = pack;
2485 }
2486
2487 /* Pack LOD bias value */
2488 if (opcode == TGSI_OPCODE_TXB)
2489 address[count++] = coords[3];
2490 if (opcode == TGSI_OPCODE_TXB2)
2491 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2492
2493 /* Pack depth comparison value */
2494 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2495 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2496 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2497 } else {
2498 assert(ref_pos >= 0);
2499 address[count++] = coords[ref_pos];
2500 }
2501 }
2502
2503 /* Pack user derivatives */
2504 if (opcode == TGSI_OPCODE_TXD) {
2505 int param, num_src_deriv_channels;
2506
2507 switch (target) {
2508 case TGSI_TEXTURE_3D:
2509 num_src_deriv_channels = 3;
2510 num_deriv_channels = 3;
2511 break;
2512 case TGSI_TEXTURE_2D:
2513 case TGSI_TEXTURE_SHADOW2D:
2514 case TGSI_TEXTURE_RECT:
2515 case TGSI_TEXTURE_SHADOWRECT:
2516 case TGSI_TEXTURE_2D_ARRAY:
2517 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2518 num_src_deriv_channels = 2;
2519 num_deriv_channels = 2;
2520 break;
2521 case TGSI_TEXTURE_CUBE:
2522 case TGSI_TEXTURE_SHADOWCUBE:
2523 case TGSI_TEXTURE_CUBE_ARRAY:
2524 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2525 /* Cube derivatives will be converted to 2D. */
2526 num_src_deriv_channels = 3;
2527 num_deriv_channels = 2;
2528 break;
2529 case TGSI_TEXTURE_1D:
2530 case TGSI_TEXTURE_SHADOW1D:
2531 case TGSI_TEXTURE_1D_ARRAY:
2532 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2533 num_src_deriv_channels = 1;
2534 num_deriv_channels = 1;
2535 break;
2536 default:
2537 unreachable("invalid target");
2538 }
2539
2540 for (param = 0; param < 2; param++)
2541 for (chan = 0; chan < num_src_deriv_channels; chan++)
2542 derivs[param * num_src_deriv_channels + chan] =
2543 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2544 }
2545
2546 if (target == TGSI_TEXTURE_CUBE ||
2547 target == TGSI_TEXTURE_CUBE_ARRAY ||
2548 target == TGSI_TEXTURE_SHADOWCUBE ||
2549 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2550 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2551
2552 if (opcode == TGSI_OPCODE_TXD)
2553 for (int i = 0; i < num_deriv_channels * 2; i++)
2554 address[count++] = derivs[i];
2555
2556 /* Pack texture coordinates */
2557 address[count++] = coords[0];
2558 if (num_coords > 1)
2559 address[count++] = coords[1];
2560 if (num_coords > 2)
2561 address[count++] = coords[2];
2562
2563 /* Pack LOD or sample index */
2564 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2565 address[count++] = coords[3];
2566 else if (opcode == TGSI_OPCODE_TXL2)
2567 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2568
2569 if (count > 16) {
2570 assert(!"Cannot handle more than 16 texture address parameters");
2571 count = 16;
2572 }
2573
2574 for (chan = 0; chan < count; chan++ ) {
2575 address[chan] = LLVMBuildBitCast(gallivm->builder,
2576 address[chan], i32, "");
2577 }
2578
2579 /* Adjust the sample index according to FMASK.
2580 *
2581 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2582 * which is the identity mapping. Each nibble says which physical sample
2583 * should be fetched to get that sample.
2584 *
2585 * For example, 0x11111100 means there are only 2 samples stored and
2586 * the second sample covers 3/4 of the pixel. When reading samples 0
2587 * and 1, return physical sample 0 (determined by the first two 0s
2588 * in FMASK), otherwise return physical sample 1.
2589 *
2590 * The sample index should be adjusted as follows:
2591 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2592 */
2593 if (target == TGSI_TEXTURE_2D_MSAA ||
2594 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2595 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2596 struct lp_build_emit_data txf_emit_data = *emit_data;
2597 LLVMValueRef txf_address[4];
2598 unsigned txf_count = count;
2599 struct tgsi_full_instruction inst = {};
2600
2601 memcpy(txf_address, address, sizeof(txf_address));
2602
2603 if (target == TGSI_TEXTURE_2D_MSAA) {
2604 txf_address[2] = bld_base->uint_bld.zero;
2605 }
2606 txf_address[3] = bld_base->uint_bld.zero;
2607
2608 /* Read FMASK using TXF. */
2609 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2610 inst.Texture.Texture = target;
2611 txf_emit_data.inst = &inst;
2612 txf_emit_data.chan = 0;
2613 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2614 target, fmask_ptr, NULL,
2615 txf_address, txf_count, 0xf);
2616 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2617
2618 /* Initialize some constants. */
2619 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2620 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2621
2622 /* Apply the formula. */
2623 LLVMValueRef fmask =
2624 LLVMBuildExtractElement(gallivm->builder,
2625 txf_emit_data.output[0],
2626 uint_bld->zero, "");
2627
2628 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2629
2630 LLVMValueRef sample_index4 =
2631 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2632
2633 LLVMValueRef shifted_fmask =
2634 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2635
2636 LLVMValueRef final_sample =
2637 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2638
2639 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2640 * resource descriptor is 0 (invalid),
2641 */
2642 LLVMValueRef fmask_desc =
2643 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2644 LLVMVectorType(uint_bld->elem_type, 8), "");
2645
2646 LLVMValueRef fmask_word1 =
2647 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2648 uint_bld->one, "");
2649
2650 LLVMValueRef word1_is_nonzero =
2651 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2652 fmask_word1, uint_bld->zero, "");
2653
2654 /* Replace the MSAA sample index. */
2655 address[sample_chan] =
2656 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2657 final_sample, address[sample_chan], "");
2658 }
2659
2660 if (opcode == TGSI_OPCODE_TXF) {
2661 /* add tex offsets */
2662 if (inst->Texture.NumOffsets) {
2663 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2664 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2665 const struct tgsi_texture_offset * off = inst->TexOffsets;
2666
2667 assert(inst->Texture.NumOffsets == 1);
2668
2669 switch (target) {
2670 case TGSI_TEXTURE_3D:
2671 address[2] = lp_build_add(uint_bld, address[2],
2672 bld->immediates[off->Index][off->SwizzleZ]);
2673 /* fall through */
2674 case TGSI_TEXTURE_2D:
2675 case TGSI_TEXTURE_SHADOW2D:
2676 case TGSI_TEXTURE_RECT:
2677 case TGSI_TEXTURE_SHADOWRECT:
2678 case TGSI_TEXTURE_2D_ARRAY:
2679 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2680 address[1] =
2681 lp_build_add(uint_bld, address[1],
2682 bld->immediates[off->Index][off->SwizzleY]);
2683 /* fall through */
2684 case TGSI_TEXTURE_1D:
2685 case TGSI_TEXTURE_SHADOW1D:
2686 case TGSI_TEXTURE_1D_ARRAY:
2687 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2688 address[0] =
2689 lp_build_add(uint_bld, address[0],
2690 bld->immediates[off->Index][off->SwizzleX]);
2691 break;
2692 /* texture offsets do not apply to other texture targets */
2693 }
2694 }
2695 }
2696
2697 if (opcode == TGSI_OPCODE_TG4) {
2698 unsigned gather_comp = 0;
2699
2700 /* DMASK was repurposed for GATHER4. 4 components are always
2701 * returned and DMASK works like a swizzle - it selects
2702 * the component to fetch. The only valid DMASK values are
2703 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2704 * (red,red,red,red) etc.) The ISA document doesn't mention
2705 * this.
2706 */
2707
2708 /* Get the component index from src1.x for Gather4. */
2709 if (!tgsi_is_shadow_target(target)) {
2710 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2711 LLVMValueRef comp_imm;
2712 struct tgsi_src_register src1 = inst->Src[1].Register;
2713
2714 assert(src1.File == TGSI_FILE_IMMEDIATE);
2715
2716 comp_imm = imms[src1.Index][src1.SwizzleX];
2717 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2718 gather_comp = CLAMP(gather_comp, 0, 3);
2719 }
2720
2721 dmask = 1 << gather_comp;
2722 }
2723
2724 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2725 samp_ptr, address, count, dmask);
2726 }
2727
2728 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2729 struct lp_build_tgsi_context * bld_base,
2730 struct lp_build_emit_data * emit_data)
2731 {
2732 struct lp_build_context * base = &bld_base->base;
2733 unsigned opcode = emit_data->inst->Instruction.Opcode;
2734 unsigned target = emit_data->inst->Texture.Texture;
2735 char intr_name[127];
2736 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2737 bool is_shadow = tgsi_is_shadow_target(target);
2738 char type[64];
2739 const char *name = "llvm.SI.image.sample";
2740 const char *infix = "";
2741
2742 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2743 /* Just return the buffer size. */
2744 emit_data->output[emit_data->chan] = emit_data->args[0];
2745 return;
2746 }
2747
2748 if (target == TGSI_TEXTURE_BUFFER) {
2749 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2750 base->gallivm->builder,
2751 "llvm.SI.vs.load.input", emit_data->dst_type,
2752 emit_data->args, emit_data->arg_count,
2753 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2754 return;
2755 }
2756
2757 switch (opcode) {
2758 case TGSI_OPCODE_TXF:
2759 name = target == TGSI_TEXTURE_2D_MSAA ||
2760 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2761 "llvm.SI.image.load" :
2762 "llvm.SI.image.load.mip";
2763 is_shadow = false;
2764 has_offset = false;
2765 break;
2766 case TGSI_OPCODE_TXQ:
2767 name = "llvm.SI.getresinfo";
2768 is_shadow = false;
2769 has_offset = false;
2770 break;
2771 case TGSI_OPCODE_LODQ:
2772 name = "llvm.SI.getlod";
2773 is_shadow = false;
2774 has_offset = false;
2775 break;
2776 case TGSI_OPCODE_TEX:
2777 case TGSI_OPCODE_TEX2:
2778 case TGSI_OPCODE_TXP:
2779 break;
2780 case TGSI_OPCODE_TXB:
2781 case TGSI_OPCODE_TXB2:
2782 infix = ".b";
2783 break;
2784 case TGSI_OPCODE_TXL:
2785 case TGSI_OPCODE_TXL2:
2786 infix = ".l";
2787 break;
2788 case TGSI_OPCODE_TXD:
2789 infix = ".d";
2790 break;
2791 case TGSI_OPCODE_TG4:
2792 name = "llvm.SI.gather4";
2793 break;
2794 default:
2795 assert(0);
2796 return;
2797 }
2798
2799 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2800 sprintf(type, ".v%ui32",
2801 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2802 else
2803 strcpy(type, ".i32");
2804
2805 /* Add the type and suffixes .c, .o if needed. */
2806 sprintf(intr_name, "%s%s%s%s%s",
2807 name, is_shadow ? ".c" : "", infix,
2808 has_offset ? ".o" : "", type);
2809
2810 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2811 base->gallivm->builder, intr_name, emit_data->dst_type,
2812 emit_data->args, emit_data->arg_count,
2813 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2814
2815 /* Divide the number of layers by 6 to get the number of cubes. */
2816 if (opcode == TGSI_OPCODE_TXQ &&
2817 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2818 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2819 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2820 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2821 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2822
2823 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2824 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2825 z = LLVMBuildSDiv(builder, z, six, "");
2826
2827 emit_data->output[emit_data->chan] =
2828 LLVMBuildInsertElement(builder, v4, z, two, "");
2829 }
2830 }
2831
2832 static void si_llvm_emit_txqs(
2833 const struct lp_build_tgsi_action * action,
2834 struct lp_build_tgsi_context * bld_base,
2835 struct lp_build_emit_data * emit_data)
2836 {
2837 struct gallivm_state *gallivm = bld_base->base.gallivm;
2838 LLVMBuilderRef builder = gallivm->builder;
2839 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2840 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2841 LLVMValueRef res, samples;
2842 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2843
2844 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2845
2846
2847 /* Read the samples from the descriptor directly. */
2848 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2849 samples = LLVMBuildExtractElement(
2850 builder, res,
2851 lp_build_const_int32(gallivm, 3), "");
2852 samples = LLVMBuildLShr(builder, samples,
2853 lp_build_const_int32(gallivm, 16), "");
2854 samples = LLVMBuildAnd(builder, samples,
2855 lp_build_const_int32(gallivm, 0xf), "");
2856 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2857 samples, "");
2858
2859 emit_data->output[emit_data->chan] = samples;
2860 }
2861
2862 /*
2863 * SI implements derivatives using the local data store (LDS)
2864 * All writes to the LDS happen in all executing threads at
2865 * the same time. TID is the Thread ID for the current
2866 * thread and is a value between 0 and 63, representing
2867 * the thread's position in the wavefront.
2868 *
2869 * For the pixel shader threads are grouped into quads of four pixels.
2870 * The TIDs of the pixels of a quad are:
2871 *
2872 * +------+------+
2873 * |4n + 0|4n + 1|
2874 * +------+------+
2875 * |4n + 2|4n + 3|
2876 * +------+------+
2877 *
2878 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2879 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2880 * the current pixel's column, and masking with 0xfffffffe yields the TID
2881 * of the left pixel of the current pixel's row.
2882 *
2883 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2884 * adding 2 yields the TID of the pixel below the top pixel.
2885 */
2886 /* masks for thread ID. */
2887 #define TID_MASK_TOP_LEFT 0xfffffffc
2888 #define TID_MASK_TOP 0xfffffffd
2889 #define TID_MASK_LEFT 0xfffffffe
2890
2891 static void si_llvm_emit_ddxy(
2892 const struct lp_build_tgsi_action * action,
2893 struct lp_build_tgsi_context * bld_base,
2894 struct lp_build_emit_data * emit_data)
2895 {
2896 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2897 struct gallivm_state *gallivm = bld_base->base.gallivm;
2898 struct lp_build_context * base = &bld_base->base;
2899 const struct tgsi_full_instruction *inst = emit_data->inst;
2900 unsigned opcode = inst->Instruction.Opcode;
2901 LLVMValueRef indices[2];
2902 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2903 LLVMValueRef tl, trbl, result[4];
2904 LLVMTypeRef i32;
2905 unsigned swizzle[4];
2906 unsigned c;
2907 int idx;
2908 unsigned mask;
2909
2910 i32 = LLVMInt32TypeInContext(gallivm->context);
2911
2912 indices[0] = bld_base->uint_bld.zero;
2913 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2914 NULL, 0, LLVMReadNoneAttribute);
2915 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2916 indices, 2, "");
2917
2918 if (opcode == TGSI_OPCODE_DDX_FINE)
2919 mask = TID_MASK_LEFT;
2920 else if (opcode == TGSI_OPCODE_DDY_FINE)
2921 mask = TID_MASK_TOP;
2922 else
2923 mask = TID_MASK_TOP_LEFT;
2924
2925 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2926 lp_build_const_int32(gallivm, mask), "");
2927 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2928 indices, 2, "");
2929
2930 /* for DDX we want to next X pixel, DDY next Y pixel. */
2931 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2932 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2933 lp_build_const_int32(gallivm, idx), "");
2934 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2935 indices, 2, "");
2936
2937 for (c = 0; c < 4; ++c) {
2938 unsigned i;
2939
2940 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2941 for (i = 0; i < c; ++i) {
2942 if (swizzle[i] == swizzle[c]) {
2943 result[c] = result[i];
2944 break;
2945 }
2946 }
2947 if (i != c)
2948 continue;
2949
2950 LLVMBuildStore(gallivm->builder,
2951 LLVMBuildBitCast(gallivm->builder,
2952 lp_build_emit_fetch(bld_base, inst, 0, c),
2953 i32, ""),
2954 store_ptr);
2955
2956 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2957 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2958
2959 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2960 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2961
2962 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2963 }
2964
2965 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2966 }
2967
2968 /*
2969 * this takes an I,J coordinate pair,
2970 * and works out the X and Y derivatives.
2971 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
2972 */
2973 static LLVMValueRef si_llvm_emit_ddxy_interp(
2974 struct lp_build_tgsi_context *bld_base,
2975 LLVMValueRef interp_ij)
2976 {
2977 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2978 struct gallivm_state *gallivm = bld_base->base.gallivm;
2979 struct lp_build_context *base = &bld_base->base;
2980 LLVMValueRef indices[2];
2981 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
2982 LLVMValueRef tl, tr, bl, result[4];
2983 LLVMTypeRef i32;
2984 unsigned c;
2985
2986 i32 = LLVMInt32TypeInContext(gallivm->context);
2987
2988 indices[0] = bld_base->uint_bld.zero;
2989 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2990 NULL, 0, LLVMReadNoneAttribute);
2991 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2992 indices, 2, "");
2993
2994 temp = LLVMBuildAnd(gallivm->builder, indices[1],
2995 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
2996
2997 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
2998 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
2999
3000 indices[1] = temp;
3001 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3002 indices, 2, "");
3003
3004 indices[1] = temp2;
3005 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3006 indices, 2, "");
3007
3008 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3009 lp_build_const_int32(gallivm, 1), "");
3010 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3011 indices, 2, "");
3012
3013 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3014 lp_build_const_int32(gallivm, 2), "");
3015 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3016 indices, 2, "");
3017
3018 for (c = 0; c < 2; ++c) {
3019 LLVMValueRef store_val;
3020 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3021
3022 store_val = LLVMBuildExtractElement(gallivm->builder,
3023 interp_ij, c_ll, "");
3024 LLVMBuildStore(gallivm->builder,
3025 store_val,
3026 store_ptr);
3027
3028 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3029 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3030
3031 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3032 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3033
3034 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3035
3036 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3037 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3038
3039 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3040 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3041
3042 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3043 }
3044
3045 return lp_build_gather_values(gallivm, result, 4);
3046 }
3047
3048 static void interp_fetch_args(
3049 struct lp_build_tgsi_context *bld_base,
3050 struct lp_build_emit_data *emit_data)
3051 {
3052 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3053 struct gallivm_state *gallivm = bld_base->base.gallivm;
3054 const struct tgsi_full_instruction *inst = emit_data->inst;
3055
3056 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3057 /* offset is in second src, first two channels */
3058 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3059 emit_data->inst, 1,
3060 TGSI_CHAN_X);
3061 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3062 emit_data->inst, 1,
3063 TGSI_CHAN_Y);
3064 emit_data->arg_count = 2;
3065 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3066 LLVMValueRef sample_position;
3067 LLVMValueRef sample_id;
3068 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3069
3070 /* fetch sample ID, then fetch its sample position,
3071 * and place into first two channels.
3072 */
3073 sample_id = lp_build_emit_fetch(bld_base,
3074 emit_data->inst, 1, TGSI_CHAN_X);
3075 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3076 LLVMInt32TypeInContext(gallivm->context),
3077 "");
3078 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3079
3080 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3081 sample_position,
3082 lp_build_const_int32(gallivm, 0), "");
3083
3084 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3085 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3086 sample_position,
3087 lp_build_const_int32(gallivm, 1), "");
3088 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3089 emit_data->arg_count = 2;
3090 }
3091 }
3092
3093 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3094 struct lp_build_tgsi_context *bld_base,
3095 struct lp_build_emit_data *emit_data)
3096 {
3097 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3098 struct si_shader *shader = si_shader_ctx->shader;
3099 struct gallivm_state *gallivm = bld_base->base.gallivm;
3100 LLVMValueRef interp_param;
3101 const struct tgsi_full_instruction *inst = emit_data->inst;
3102 const char *intr_name;
3103 int input_index;
3104 int chan;
3105 int i;
3106 LLVMValueRef attr_number;
3107 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3108 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3109 int interp_param_idx;
3110 unsigned location;
3111
3112 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3113 input_index = inst->Src[0].Register.Index;
3114
3115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3116 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3117 location = TGSI_INTERPOLATE_LOC_CENTER;
3118 else
3119 location = TGSI_INTERPOLATE_LOC_CENTROID;
3120
3121 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3122 location);
3123 if (interp_param_idx == -1)
3124 return;
3125 else if (interp_param_idx)
3126 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3127 else
3128 interp_param = NULL;
3129
3130 attr_number = lp_build_const_int32(gallivm,
3131 shader->ps_input_param_offset[input_index]);
3132
3133 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3134 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3135 LLVMValueRef ij_out[2];
3136 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3137
3138 /*
3139 * take the I then J parameters, and the DDX/Y for it, and
3140 * calculate the IJ inputs for the interpolator.
3141 * temp1 = ddx * offset/sample.x + I;
3142 * interp_param.I = ddy * offset/sample.y + temp1;
3143 * temp1 = ddx * offset/sample.x + J;
3144 * interp_param.J = ddy * offset/sample.y + temp1;
3145 */
3146 for (i = 0; i < 2; i++) {
3147 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3148 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3149 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3150 ddxy_out, ix_ll, "");
3151 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3152 ddxy_out, iy_ll, "");
3153 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3154 interp_param, ix_ll, "");
3155 LLVMValueRef temp1, temp2;
3156
3157 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3158 LLVMFloatTypeInContext(gallivm->context), "");
3159
3160 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3161
3162 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3163
3164 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3165
3166 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3167
3168 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3169 temp2,
3170 LLVMIntTypeInContext(gallivm->context, 32), "");
3171 }
3172 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3173 }
3174
3175 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3176 for (chan = 0; chan < 2; chan++) {
3177 LLVMValueRef args[4];
3178 LLVMValueRef llvm_chan;
3179 unsigned schan;
3180
3181 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3182 llvm_chan = lp_build_const_int32(gallivm, schan);
3183
3184 args[0] = llvm_chan;
3185 args[1] = attr_number;
3186 args[2] = params;
3187 args[3] = interp_param;
3188
3189 emit_data->output[chan] =
3190 lp_build_intrinsic(gallivm->builder, intr_name,
3191 input_type, args, args[3] ? 4 : 3,
3192 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3193 }
3194 }
3195
3196 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3197 struct lp_build_emit_data *emit_data)
3198 {
3199 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3200 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3201 unsigned stream;
3202
3203 assert(src0.File == TGSI_FILE_IMMEDIATE);
3204
3205 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3206 return stream;
3207 }
3208
3209 /* Emit one vertex from the geometry shader */
3210 static void si_llvm_emit_vertex(
3211 const struct lp_build_tgsi_action *action,
3212 struct lp_build_tgsi_context *bld_base,
3213 struct lp_build_emit_data *emit_data)
3214 {
3215 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3216 struct lp_build_context *uint = &bld_base->uint_bld;
3217 struct si_shader *shader = si_shader_ctx->shader;
3218 struct tgsi_shader_info *info = &shader->selector->info;
3219 struct gallivm_state *gallivm = bld_base->base.gallivm;
3220 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3221 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3222 SI_PARAM_GS2VS_OFFSET);
3223 LLVMValueRef gs_next_vertex;
3224 LLVMValueRef can_emit, kill;
3225 LLVMValueRef args[2];
3226 unsigned chan;
3227 int i;
3228 unsigned stream;
3229
3230 stream = si_llvm_get_stream(bld_base, emit_data);
3231
3232 /* Write vertex attribute values to GSVS ring */
3233 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3234 si_shader_ctx->gs_next_vertex[stream],
3235 "");
3236
3237 /* If this thread has already emitted the declared maximum number of
3238 * vertices, kill it: excessive vertex emissions are not supposed to
3239 * have any effect, and GS threads have no externally observable
3240 * effects other than emitting vertices.
3241 */
3242 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3243 lp_build_const_int32(gallivm,
3244 shader->selector->gs_max_out_vertices), "");
3245 kill = lp_build_select(&bld_base->base, can_emit,
3246 lp_build_const_float(gallivm, 1.0f),
3247 lp_build_const_float(gallivm, -1.0f));
3248
3249 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3250 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3251
3252 for (i = 0; i < info->num_outputs; i++) {
3253 LLVMValueRef *out_ptr =
3254 si_shader_ctx->radeon_bld.soa.outputs[i];
3255
3256 for (chan = 0; chan < 4; chan++) {
3257 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3258 LLVMValueRef voffset =
3259 lp_build_const_int32(gallivm, (i * 4 + chan) *
3260 shader->selector->gs_max_out_vertices);
3261
3262 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3263 voffset = lp_build_mul_imm(uint, voffset, 4);
3264
3265 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3266
3267 build_tbuffer_store(si_shader_ctx,
3268 si_shader_ctx->gsvs_ring[stream],
3269 out_val, 1,
3270 voffset, soffset, 0,
3271 V_008F0C_BUF_DATA_FORMAT_32,
3272 V_008F0C_BUF_NUM_FORMAT_UINT,
3273 1, 0, 1, 1, 0);
3274 }
3275 }
3276 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3277 lp_build_const_int32(gallivm, 1));
3278
3279 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3280
3281 /* Signal vertex emission */
3282 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3283 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3284 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3285 LLVMVoidTypeInContext(gallivm->context), args, 2,
3286 LLVMNoUnwindAttribute);
3287 }
3288
3289 /* Cut one primitive from the geometry shader */
3290 static void si_llvm_emit_primitive(
3291 const struct lp_build_tgsi_action *action,
3292 struct lp_build_tgsi_context *bld_base,
3293 struct lp_build_emit_data *emit_data)
3294 {
3295 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3296 struct gallivm_state *gallivm = bld_base->base.gallivm;
3297 LLVMValueRef args[2];
3298 unsigned stream;
3299
3300 /* Signal primitive cut */
3301 stream = si_llvm_get_stream(bld_base, emit_data);
3302 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3303 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3304 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3305 LLVMVoidTypeInContext(gallivm->context), args, 2,
3306 LLVMNoUnwindAttribute);
3307 }
3308
3309 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3310 struct lp_build_tgsi_context *bld_base,
3311 struct lp_build_emit_data *emit_data)
3312 {
3313 struct gallivm_state *gallivm = bld_base->base.gallivm;
3314
3315 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3316 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3317 LLVMNoUnwindAttribute);
3318 }
3319
3320 static const struct lp_build_tgsi_action tex_action = {
3321 .fetch_args = tex_fetch_args,
3322 .emit = build_tex_intrinsic,
3323 };
3324
3325 static const struct lp_build_tgsi_action interp_action = {
3326 .fetch_args = interp_fetch_args,
3327 .emit = build_interp_intrinsic,
3328 };
3329
3330 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3331 {
3332 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3333 LLVMValueRef args[3];
3334
3335 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3336 args[1] = 0;
3337 args[2] = lp_build_const_int32(gallivm, 1);
3338
3339 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3340 }
3341
3342 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3343 {
3344 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3345 CONST_ADDR_SPACE);
3346 }
3347
3348 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3349 struct pipe_stream_output_info *so,
3350 LLVMTypeRef *params, LLVMTypeRef i32,
3351 unsigned *num_params)
3352 {
3353 int i;
3354
3355 /* Streamout SGPRs. */
3356 if (so->num_outputs) {
3357 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3358 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3359 }
3360 /* A streamout buffer offset is loaded if the stride is non-zero. */
3361 for (i = 0; i < 4; i++) {
3362 if (!so->stride[i])
3363 continue;
3364
3365 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3366 }
3367 }
3368
3369 static void create_function(struct si_shader_context *si_shader_ctx)
3370 {
3371 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3372 struct gallivm_state *gallivm = bld_base->base.gallivm;
3373 struct si_shader *shader = si_shader_ctx->shader;
3374 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3375 unsigned i, last_array_pointer, last_sgpr, num_params;
3376
3377 i8 = LLVMInt8TypeInContext(gallivm->context);
3378 i32 = LLVMInt32TypeInContext(gallivm->context);
3379 f32 = LLVMFloatTypeInContext(gallivm->context);
3380 v2i32 = LLVMVectorType(i32, 2);
3381 v3i32 = LLVMVectorType(i32, 3);
3382 v4i32 = LLVMVectorType(i32, 4);
3383 v8i32 = LLVMVectorType(i32, 8);
3384 v16i8 = LLVMVectorType(i8, 16);
3385
3386 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3387 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3388 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3389 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3390 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3391
3392 switch (si_shader_ctx->type) {
3393 case TGSI_PROCESSOR_VERTEX:
3394 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3395 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3396 params[SI_PARAM_BASE_VERTEX] = i32;
3397 params[SI_PARAM_START_INSTANCE] = i32;
3398 num_params = SI_PARAM_START_INSTANCE+1;
3399
3400 if (shader->key.vs.as_es) {
3401 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3402 } else if (shader->key.vs.as_ls) {
3403 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3404 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3405 } else {
3406 if (shader->is_gs_copy_shader) {
3407 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3408 num_params = SI_PARAM_CONST_BUFFERS+1;
3409 } else {
3410 params[SI_PARAM_VS_STATE_BITS] = i32;
3411 num_params = SI_PARAM_VS_STATE_BITS+1;
3412 }
3413
3414 /* The locations of the other parameters are assigned dynamically. */
3415 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3416 params, i32, &num_params);
3417 }
3418
3419 last_sgpr = num_params-1;
3420
3421 /* VGPRs */
3422 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3423 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3424 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3425 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3426 break;
3427
3428 case TGSI_PROCESSOR_TESS_CTRL:
3429 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3430 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3431 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3432 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3433 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3434
3435 /* VGPRs */
3436 params[SI_PARAM_PATCH_ID] = i32;
3437 params[SI_PARAM_REL_IDS] = i32;
3438 num_params = SI_PARAM_REL_IDS+1;
3439 break;
3440
3441 case TGSI_PROCESSOR_TESS_EVAL:
3442 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3443 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3444 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3445
3446 if (shader->key.tes.as_es) {
3447 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3448 } else {
3449 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3450 params, i32, &num_params);
3451 }
3452 last_sgpr = num_params - 1;
3453
3454 /* VGPRs */
3455 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3456 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3457 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3458 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3459 break;
3460
3461 case TGSI_PROCESSOR_GEOMETRY:
3462 params[SI_PARAM_GS2VS_OFFSET] = i32;
3463 params[SI_PARAM_GS_WAVE_ID] = i32;
3464 last_sgpr = SI_PARAM_GS_WAVE_ID;
3465
3466 /* VGPRs */
3467 params[SI_PARAM_VTX0_OFFSET] = i32;
3468 params[SI_PARAM_VTX1_OFFSET] = i32;
3469 params[SI_PARAM_PRIMITIVE_ID] = i32;
3470 params[SI_PARAM_VTX2_OFFSET] = i32;
3471 params[SI_PARAM_VTX3_OFFSET] = i32;
3472 params[SI_PARAM_VTX4_OFFSET] = i32;
3473 params[SI_PARAM_VTX5_OFFSET] = i32;
3474 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3475 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3476 break;
3477
3478 case TGSI_PROCESSOR_FRAGMENT:
3479 params[SI_PARAM_ALPHA_REF] = f32;
3480 params[SI_PARAM_PS_STATE_BITS] = i32;
3481 params[SI_PARAM_PRIM_MASK] = i32;
3482 last_sgpr = SI_PARAM_PRIM_MASK;
3483 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3484 params[SI_PARAM_PERSP_CENTER] = v2i32;
3485 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3486 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3487 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3488 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3489 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3490 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3491 params[SI_PARAM_POS_X_FLOAT] = f32;
3492 params[SI_PARAM_POS_Y_FLOAT] = f32;
3493 params[SI_PARAM_POS_Z_FLOAT] = f32;
3494 params[SI_PARAM_POS_W_FLOAT] = f32;
3495 params[SI_PARAM_FRONT_FACE] = i32;
3496 params[SI_PARAM_ANCILLARY] = i32;
3497 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3498 params[SI_PARAM_POS_FIXED_PT] = f32;
3499 num_params = SI_PARAM_POS_FIXED_PT+1;
3500 break;
3501
3502 default:
3503 assert(0 && "unimplemented shader");
3504 return;
3505 }
3506
3507 assert(num_params <= Elements(params));
3508 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3509 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3510
3511 if (shader->dx10_clamp_mode)
3512 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3513 "enable-no-nans-fp-math", "true");
3514
3515 for (i = 0; i <= last_sgpr; ++i) {
3516 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3517
3518 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3519 * to move load. Inputs are constant so this is fine. */
3520 if (i <= last_array_pointer)
3521 LLVMAddAttribute(P, LLVMByValAttribute);
3522 else
3523 LLVMAddAttribute(P, LLVMInRegAttribute);
3524 }
3525
3526 if (bld_base->info &&
3527 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3528 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3529 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3530 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3531 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3532 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3533 si_shader_ctx->lds =
3534 LLVMAddGlobalInAddressSpace(gallivm->module,
3535 LLVMArrayType(i32, 64),
3536 "ddxy_lds",
3537 LOCAL_ADDR_SPACE);
3538
3539 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3540 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3541 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3542 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3543 unsigned vertex_data_dw_size = 32*32*4;
3544 unsigned patch_data_dw_size = 32*4;
3545 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3546 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3547 unsigned lds_dwords = patch_dw_size;
3548
3549 /* The actual size is computed outside of the shader to reduce
3550 * the number of shader variants. */
3551 si_shader_ctx->lds =
3552 LLVMAddGlobalInAddressSpace(gallivm->module,
3553 LLVMArrayType(i32, lds_dwords),
3554 "tess_lds",
3555 LOCAL_ADDR_SPACE);
3556 }
3557 }
3558
3559 static void preload_constants(struct si_shader_context *si_shader_ctx)
3560 {
3561 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3562 struct gallivm_state * gallivm = bld_base->base.gallivm;
3563 const struct tgsi_shader_info * info = bld_base->info;
3564 unsigned buf;
3565 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3566
3567 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3568 unsigned i, num_const = info->const_file_max[buf] + 1;
3569
3570 if (num_const == 0)
3571 continue;
3572
3573 /* Allocate space for the constant values */
3574 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3575
3576 /* Load the resource descriptor */
3577 si_shader_ctx->const_buffers[buf] =
3578 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3579
3580 /* Load the constants, we rely on the code sinking to do the rest */
3581 for (i = 0; i < num_const * 4; ++i) {
3582 si_shader_ctx->constants[buf][i] =
3583 buffer_load_const(gallivm->builder,
3584 si_shader_ctx->const_buffers[buf],
3585 lp_build_const_int32(gallivm, i * 4),
3586 bld_base->base.elem_type);
3587 }
3588 }
3589 }
3590
3591 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3592 {
3593 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3594 struct gallivm_state * gallivm = bld_base->base.gallivm;
3595 const struct tgsi_shader_info * info = bld_base->info;
3596
3597 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3598
3599 LLVMValueRef res_ptr, samp_ptr;
3600 LLVMValueRef offset;
3601
3602 if (num_samplers == 0)
3603 return;
3604
3605 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3606 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3607
3608 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3609 for (i = 0; i < num_samplers; ++i) {
3610 /* Resource */
3611 offset = lp_build_const_int32(gallivm, i);
3612 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3613
3614 /* Sampler */
3615 offset = lp_build_const_int32(gallivm, i);
3616 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3617
3618 /* FMASK resource */
3619 if (info->is_msaa_sampler[i]) {
3620 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3621 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3622 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3623 }
3624 }
3625 }
3626
3627 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3628 {
3629 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3630 struct gallivm_state * gallivm = bld_base->base.gallivm;
3631 unsigned i;
3632
3633 /* Streamout can only be used if the shader is compiled as VS. */
3634 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3635 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3636 (si_shader_ctx->shader->key.vs.as_es ||
3637 si_shader_ctx->shader->key.vs.as_ls)) ||
3638 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3639 si_shader_ctx->shader->key.tes.as_es))
3640 return;
3641
3642 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3643 SI_PARAM_RW_BUFFERS);
3644
3645 /* Load the resources, we rely on the code sinking to do the rest */
3646 for (i = 0; i < 4; ++i) {
3647 if (si_shader_ctx->shader->selector->so.stride[i]) {
3648 LLVMValueRef offset = lp_build_const_int32(gallivm,
3649 SI_SO_BUF_OFFSET + i);
3650
3651 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3652 }
3653 }
3654 }
3655
3656 /**
3657 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3658 * for later use.
3659 */
3660 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3661 {
3662 struct gallivm_state *gallivm =
3663 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3664
3665 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3666 SI_PARAM_RW_BUFFERS);
3667
3668 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3669 si_shader_ctx->shader->key.vs.as_es) ||
3670 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3671 si_shader_ctx->shader->key.tes.as_es) ||
3672 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3673 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3674
3675 si_shader_ctx->esgs_ring =
3676 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3677 }
3678
3679 if (si_shader_ctx->shader->is_gs_copy_shader) {
3680 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3681
3682 si_shader_ctx->gsvs_ring[0] =
3683 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3684 }
3685 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3686 int i;
3687 for (i = 0; i < 4; i++) {
3688 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3689
3690 si_shader_ctx->gsvs_ring[i] =
3691 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3692 }
3693 }
3694 }
3695
3696 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3697 struct si_shader_config *conf,
3698 unsigned symbol_offset)
3699 {
3700 unsigned i;
3701 const unsigned char *config =
3702 radeon_shader_binary_config_start(binary, symbol_offset);
3703
3704 /* XXX: We may be able to emit some of these values directly rather than
3705 * extracting fields to be emitted later.
3706 */
3707
3708 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3709 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3710 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3711 switch (reg) {
3712 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3713 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3714 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3715 case R_00B848_COMPUTE_PGM_RSRC1:
3716 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3717 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3718 conf->float_mode = G_00B028_FLOAT_MODE(value);
3719 conf->rsrc1 = value;
3720 break;
3721 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3722 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3723 break;
3724 case R_00B84C_COMPUTE_PGM_RSRC2:
3725 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3726 conf->rsrc2 = value;
3727 break;
3728 case R_0286CC_SPI_PS_INPUT_ENA:
3729 conf->spi_ps_input_ena = value;
3730 break;
3731 case R_0286D0_SPI_PS_INPUT_ADDR:
3732 /* Not used yet, but will be in the future */
3733 break;
3734 case R_0286E8_SPI_TMPRING_SIZE:
3735 case R_00B860_COMPUTE_TMPRING_SIZE:
3736 /* WAVESIZE is in units of 256 dwords. */
3737 conf->scratch_bytes_per_wave =
3738 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3739 break;
3740 default:
3741 {
3742 static bool printed;
3743
3744 if (!printed) {
3745 fprintf(stderr, "Warning: LLVM emitted unknown "
3746 "config register: 0x%x\n", reg);
3747 printed = true;
3748 }
3749 }
3750 break;
3751 }
3752 }
3753 }
3754
3755 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3756 struct si_shader *shader,
3757 uint64_t scratch_va)
3758 {
3759 unsigned i;
3760 uint32_t scratch_rsrc_dword0 = scratch_va;
3761 uint32_t scratch_rsrc_dword1 =
3762 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3763 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3764
3765 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3766 const struct radeon_shader_reloc *reloc =
3767 &shader->binary.relocs[i];
3768 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3769 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3770 &scratch_rsrc_dword0, 4);
3771 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3772 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3773 &scratch_rsrc_dword1, 4);
3774 }
3775 }
3776 }
3777
3778 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3779 {
3780 const struct radeon_shader_binary *binary = &shader->binary;
3781 unsigned code_size = binary->code_size + binary->rodata_size;
3782 unsigned char *ptr;
3783
3784 r600_resource_reference(&shader->bo, NULL);
3785 shader->bo = si_resource_create_custom(&sscreen->b.b,
3786 PIPE_USAGE_IMMUTABLE,
3787 code_size);
3788 if (!shader->bo)
3789 return -ENOMEM;
3790
3791 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3792 PIPE_TRANSFER_READ_WRITE);
3793 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3794 if (binary->rodata_size > 0) {
3795 ptr += binary->code_size;
3796 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3797 binary->rodata_size);
3798 }
3799
3800 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3801 return 0;
3802 }
3803
3804 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3805 struct pipe_debug_callback *debug)
3806 {
3807 char *line, *p;
3808 unsigned i, count;
3809
3810 if (binary->disasm_string) {
3811 fprintf(stderr, "\nShader Disassembly:\n\n");
3812 fprintf(stderr, "%s\n", binary->disasm_string);
3813
3814 if (debug && debug->debug_message) {
3815 /* Very long debug messages are cut off, so send the
3816 * disassembly one line at a time. This causes more
3817 * overhead, but on the plus side it simplifies
3818 * parsing of resulting logs.
3819 */
3820 pipe_debug_message(debug, SHADER_INFO,
3821 "Shader Disassembly Begin");
3822
3823 line = binary->disasm_string;
3824 while (*line) {
3825 p = strchrnul(line, '\n');
3826 count = p - line;
3827
3828 if (count) {
3829 pipe_debug_message(debug, SHADER_INFO,
3830 "%.*s", count, line);
3831 }
3832
3833 if (!*p)
3834 break;
3835 line = p + 1;
3836 }
3837
3838 pipe_debug_message(debug, SHADER_INFO,
3839 "Shader Disassembly End");
3840 }
3841 } else {
3842 fprintf(stderr, "SI CODE:\n");
3843 for (i = 0; i < binary->code_size; i += 4) {
3844 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3845 binary->code[i + 3], binary->code[i + 2],
3846 binary->code[i + 1], binary->code[i]);
3847 }
3848 }
3849 }
3850
3851 static void si_shader_dump_stats(struct si_screen *sscreen,
3852 struct si_shader_config *conf,
3853 unsigned code_size,
3854 struct pipe_debug_callback *debug,
3855 unsigned processor)
3856 {
3857 if (r600_can_dump_shader(&sscreen->b, processor)) {
3858 fprintf(stderr, "*** SHADER STATS ***\n"
3859 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3860 "Scratch: %d bytes per wave\n********************\n",
3861 conf->num_sgprs, conf->num_vgprs, code_size,
3862 conf->lds_size, conf->scratch_bytes_per_wave);
3863 }
3864
3865 pipe_debug_message(debug, SHADER_INFO,
3866 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
3867 conf->num_sgprs, conf->num_vgprs, code_size,
3868 conf->lds_size, conf->scratch_bytes_per_wave);
3869 }
3870
3871 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
3872 struct pipe_debug_callback *debug, unsigned processor)
3873 {
3874 if (r600_can_dump_shader(&sscreen->b, processor))
3875 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
3876 si_shader_dump_disassembly(&shader->binary, debug);
3877
3878 si_shader_dump_stats(sscreen, &shader->config,
3879 shader->binary.code_size, debug, processor);
3880 }
3881
3882 int si_compile_llvm(struct si_screen *sscreen,
3883 struct radeon_shader_binary *binary,
3884 struct si_shader_config *conf,
3885 LLVMTargetMachineRef tm,
3886 LLVMModuleRef mod,
3887 struct pipe_debug_callback *debug,
3888 unsigned processor)
3889 {
3890 int r = 0;
3891 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
3892
3893 if (r600_can_dump_shader(&sscreen->b, processor)) {
3894 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
3895
3896 if (!(sscreen->b.debug_flags & DBG_NO_IR))
3897 LLVMDumpModule(mod);
3898 }
3899
3900 if (!si_replace_shader(count, binary)) {
3901 r = radeon_llvm_compile(mod, binary,
3902 r600_get_llvm_processor_name(sscreen->b.family), tm,
3903 debug);
3904 if (r)
3905 return r;
3906 }
3907
3908 si_shader_binary_read_config(binary, conf, 0);
3909
3910 FREE(binary->config);
3911 FREE(binary->global_symbol_offsets);
3912 binary->config = NULL;
3913 binary->global_symbol_offsets = NULL;
3914 return r;
3915 }
3916
3917 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3918 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3919 struct si_shader_context *si_shader_ctx,
3920 struct si_shader *gs, bool dump,
3921 struct pipe_debug_callback *debug)
3922 {
3923 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3924 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3925 struct lp_build_context *base = &bld_base->base;
3926 struct lp_build_context *uint = &bld_base->uint_bld;
3927 struct si_shader *shader = si_shader_ctx->shader;
3928 struct si_shader_output_values *outputs;
3929 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3930 LLVMValueRef args[9];
3931 int i, r;
3932
3933 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3934
3935 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3936 shader->is_gs_copy_shader = true;
3937
3938 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3939
3940 create_meta_data(si_shader_ctx);
3941 create_function(si_shader_ctx);
3942 preload_streamout_buffers(si_shader_ctx);
3943 preload_ring_buffers(si_shader_ctx);
3944
3945 args[0] = si_shader_ctx->gsvs_ring[0];
3946 args[1] = lp_build_mul_imm(uint,
3947 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3948 si_shader_ctx->param_vertex_id),
3949 4);
3950 args[3] = uint->zero;
3951 args[4] = uint->one; /* OFFEN */
3952 args[5] = uint->zero; /* IDXEN */
3953 args[6] = uint->one; /* GLC */
3954 args[7] = uint->one; /* SLC */
3955 args[8] = uint->zero; /* TFE */
3956
3957 /* Fetch vertex data from GSVS ring */
3958 for (i = 0; i < gsinfo->num_outputs; ++i) {
3959 unsigned chan;
3960
3961 outputs[i].name = gsinfo->output_semantic_name[i];
3962 outputs[i].sid = gsinfo->output_semantic_index[i];
3963
3964 for (chan = 0; chan < 4; chan++) {
3965 args[2] = lp_build_const_int32(gallivm,
3966 (i * 4 + chan) *
3967 gs->selector->gs_max_out_vertices * 16 * 4);
3968
3969 outputs[i].values[chan] =
3970 LLVMBuildBitCast(gallivm->builder,
3971 lp_build_intrinsic(gallivm->builder,
3972 "llvm.SI.buffer.load.dword.i32.i32",
3973 LLVMInt32TypeInContext(gallivm->context),
3974 args, 9,
3975 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3976 base->elem_type, "");
3977 }
3978 }
3979
3980 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3981
3982 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3983
3984 if (dump)
3985 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3986
3987 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
3988 &si_shader_ctx->shader->config, si_shader_ctx->tm,
3989 bld_base->base.gallivm->module,
3990 debug, TGSI_PROCESSOR_GEOMETRY);
3991 if (!r) {
3992 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
3993 TGSI_PROCESSOR_GEOMETRY);
3994 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
3995 }
3996
3997 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3998
3999 FREE(outputs);
4000 return r;
4001 }
4002
4003 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4004 {
4005 int i;
4006
4007 fprintf(f, "SHADER KEY\n");
4008
4009 switch (shader) {
4010 case PIPE_SHADER_VERTEX:
4011 fprintf(f, " instance_divisors = {");
4012 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4013 fprintf(f, !i ? "%u" : ", %u",
4014 key->vs.instance_divisors[i]);
4015 fprintf(f, "}\n");
4016 fprintf(f, " as_es = %u\n", key->vs.as_es);
4017 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4018 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4019 break;
4020
4021 case PIPE_SHADER_TESS_CTRL:
4022 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4023 break;
4024
4025 case PIPE_SHADER_TESS_EVAL:
4026 fprintf(f, " as_es = %u\n", key->tes.as_es);
4027 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4028 break;
4029
4030 case PIPE_SHADER_GEOMETRY:
4031 break;
4032
4033 case PIPE_SHADER_FRAGMENT:
4034 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4035 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4036 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4037 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4038 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4039 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4040 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4041 break;
4042
4043 default:
4044 assert(0);
4045 }
4046 }
4047
4048 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4049 struct si_shader *shader,
4050 struct pipe_debug_callback *debug)
4051 {
4052 struct si_shader_selector *sel = shader->selector;
4053 struct tgsi_token *tokens = sel->tokens;
4054 struct si_shader_context si_shader_ctx;
4055 struct lp_build_tgsi_context * bld_base;
4056 struct tgsi_shader_info stipple_shader_info;
4057 LLVMModuleRef mod;
4058 int r = 0;
4059 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4060 shader->key.ps.poly_stipple;
4061 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4062
4063 if (poly_stipple) {
4064 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4065 SI_POLY_STIPPLE_SAMPLER,
4066 TGSI_FILE_SYSTEM_VALUE);
4067 tgsi_scan_shader(tokens, &stipple_shader_info);
4068 }
4069
4070 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4071 * conversion fails. */
4072 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4073 si_dump_shader_key(sel->type, &shader->key, stderr);
4074 tgsi_dump(tokens, 0);
4075 si_dump_streamout(&sel->so);
4076 }
4077
4078 assert(shader->nparam == 0);
4079
4080 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4081 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4082 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4083
4084 if (sel->type != PIPE_SHADER_COMPUTE)
4085 shader->dx10_clamp_mode = true;
4086
4087 shader->uses_instanceid = sel->info.uses_instanceid;
4088 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4089 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4090
4091 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4092 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4093 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4094
4095 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4096 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4097 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4098 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4099 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4100 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4101 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4102 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4103 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4104 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4105 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4106 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4107 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4108
4109 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4110 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4111 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4112 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4113
4114 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4115 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4116 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4117
4118 if (HAVE_LLVM >= 0x0306) {
4119 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4120 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4121 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4122 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4123 }
4124
4125 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4126 si_shader_ctx.shader = shader;
4127 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4128 si_shader_ctx.screen = sscreen;
4129 si_shader_ctx.tm = tm;
4130
4131 switch (si_shader_ctx.type) {
4132 case TGSI_PROCESSOR_VERTEX:
4133 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4134 if (shader->key.vs.as_ls)
4135 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4136 else if (shader->key.vs.as_es)
4137 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4138 else
4139 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4140 break;
4141 case TGSI_PROCESSOR_TESS_CTRL:
4142 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4143 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4144 bld_base->emit_store = store_output_tcs;
4145 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4146 break;
4147 case TGSI_PROCESSOR_TESS_EVAL:
4148 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4149 if (shader->key.tes.as_es)
4150 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4151 else
4152 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4153 break;
4154 case TGSI_PROCESSOR_GEOMETRY:
4155 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4156 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4157 break;
4158 case TGSI_PROCESSOR_FRAGMENT:
4159 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4160 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4161 break;
4162 default:
4163 assert(!"Unsupported shader type");
4164 return -1;
4165 }
4166
4167 create_meta_data(&si_shader_ctx);
4168 create_function(&si_shader_ctx);
4169 preload_constants(&si_shader_ctx);
4170 preload_samplers(&si_shader_ctx);
4171 preload_streamout_buffers(&si_shader_ctx);
4172 preload_ring_buffers(&si_shader_ctx);
4173
4174 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4175 int i;
4176 for (i = 0; i < 4; i++) {
4177 si_shader_ctx.gs_next_vertex[i] =
4178 lp_build_alloca(bld_base->base.gallivm,
4179 bld_base->uint_bld.elem_type, "");
4180 }
4181 }
4182
4183 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4184 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4185 goto out;
4186 }
4187
4188 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4189
4190 mod = bld_base->base.gallivm->module;
4191 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4192 mod, debug, si_shader_ctx.type);
4193 if (r) {
4194 fprintf(stderr, "LLVM failed to compile shader\n");
4195 goto out;
4196 }
4197
4198 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4199
4200 r = si_shader_binary_upload(sscreen, shader);
4201 if (r) {
4202 fprintf(stderr, "LLVM failed to upload shader\n");
4203 goto out;
4204 }
4205
4206 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4207
4208 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4209 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4210 shader->gs_copy_shader->selector = shader->selector;
4211 shader->gs_copy_shader->key = shader->key;
4212 si_shader_ctx.shader = shader->gs_copy_shader;
4213 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4214 shader, dump, debug))) {
4215 free(shader->gs_copy_shader);
4216 shader->gs_copy_shader = NULL;
4217 goto out;
4218 }
4219 }
4220
4221 out:
4222 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4223 FREE(si_shader_ctx.constants[i]);
4224 if (poly_stipple)
4225 tgsi_free_tokens(tokens);
4226 return r;
4227 }
4228
4229 void si_shader_destroy_binary(struct radeon_shader_binary *binary)
4230 {
4231 FREE(binary->code);
4232 FREE(binary->rodata);
4233 FREE(binary->relocs);
4234 FREE(binary->disasm_string);
4235 }
4236
4237 void si_shader_destroy(struct si_shader *shader)
4238 {
4239 if (shader->gs_copy_shader) {
4240 si_shader_destroy(shader->gs_copy_shader);
4241 FREE(shader->gs_copy_shader);
4242 }
4243
4244 if (shader->scratch_bo)
4245 r600_resource_reference(&shader->scratch_bo, NULL);
4246
4247 r600_resource_reference(&shader->bo, NULL);
4248 si_shader_destroy_binary(&shader->binary);
4249 }