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radeonsi: fix elimination of literal VS outputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
76 union si_shader_part_key *key);
77 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85
86 /* Ideally pass the sample mask input to the PS epilog as v13, which
87 * is its usual location, so that the shader doesn't have to add v_mov.
88 */
89 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
90
91 /* The VS location of the PrimitiveID input is the same in the epilog,
92 * so that the main shader part doesn't have to move it.
93 */
94 #define VS_EPILOG_PRIMID_LOC 2
95
96 enum {
97 CONST_ADDR_SPACE = 2,
98 LOCAL_ADDR_SPACE = 3,
99 };
100
101 /**
102 * Returns a unique index for a semantic name and index. The index must be
103 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
104 * calculated.
105 */
106 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
107 {
108 switch (semantic_name) {
109 case TGSI_SEMANTIC_POSITION:
110 return 0;
111 case TGSI_SEMANTIC_PSIZE:
112 return 1;
113 case TGSI_SEMANTIC_CLIPDIST:
114 assert(index <= 1);
115 return 2 + index;
116 case TGSI_SEMANTIC_GENERIC:
117 if (index <= 63-4)
118 return 4 + index;
119
120 assert(!"invalid generic index");
121 return 0;
122
123 /* patch indices are completely separate and thus start from 0 */
124 case TGSI_SEMANTIC_TESSOUTER:
125 return 0;
126 case TGSI_SEMANTIC_TESSINNER:
127 return 1;
128 case TGSI_SEMANTIC_PATCH:
129 return 2 + index;
130
131 default:
132 assert(!"invalid semantic name");
133 return 0;
134 }
135 }
136
137 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
138 {
139 switch (name) {
140 case TGSI_SEMANTIC_FOG:
141 return 0;
142 case TGSI_SEMANTIC_LAYER:
143 return 1;
144 case TGSI_SEMANTIC_VIEWPORT_INDEX:
145 return 2;
146 case TGSI_SEMANTIC_PRIMID:
147 return 3;
148 case TGSI_SEMANTIC_COLOR: /* these alias */
149 case TGSI_SEMANTIC_BCOLOR:
150 return 4 + index;
151 case TGSI_SEMANTIC_TEXCOORD:
152 return 6 + index;
153 default:
154 assert(!"invalid semantic name");
155 return 0;
156 }
157 }
158
159 /**
160 * Get the value of a shader input parameter and extract a bitfield.
161 */
162 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
163 unsigned param, unsigned rshift,
164 unsigned bitwidth)
165 {
166 struct gallivm_state *gallivm = &ctx->gallivm;
167 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
168 param);
169
170 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
171 value = bitcast(&ctx->bld_base,
172 TGSI_TYPE_UNSIGNED, value);
173
174 if (rshift)
175 value = LLVMBuildLShr(gallivm->builder, value,
176 lp_build_const_int32(gallivm, rshift), "");
177
178 if (rshift + bitwidth < 32) {
179 unsigned mask = (1 << bitwidth) - 1;
180 value = LLVMBuildAnd(gallivm->builder, value,
181 lp_build_const_int32(gallivm, mask), "");
182 }
183
184 return value;
185 }
186
187 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
188 {
189 switch (ctx->type) {
190 case PIPE_SHADER_TESS_CTRL:
191 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
192
193 case PIPE_SHADER_TESS_EVAL:
194 return LLVMGetParam(ctx->main_fn,
195 ctx->param_tes_rel_patch_id);
196
197 default:
198 assert(0);
199 return NULL;
200 }
201 }
202
203 /* Tessellation shaders pass outputs to the next shader using LDS.
204 *
205 * LS outputs = TCS inputs
206 * TCS outputs = TES inputs
207 *
208 * The LDS layout is:
209 * - TCS inputs for patch 0
210 * - TCS inputs for patch 1
211 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
212 * - ...
213 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
214 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
215 * - TCS outputs for patch 1
216 * - Per-patch TCS outputs for patch 1
217 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
218 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * - ...
220 *
221 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 */
223
224 static LLVMValueRef
225 get_tcs_in_patch_stride(struct si_shader_context *ctx)
226 {
227 if (ctx->type == PIPE_SHADER_VERTEX)
228 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
229 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
230 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
231 else {
232 assert(0);
233 return NULL;
234 }
235 }
236
237 static LLVMValueRef
238 get_tcs_out_patch_stride(struct si_shader_context *ctx)
239 {
240 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
241 }
242
243 static LLVMValueRef
244 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
245 {
246 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
247 unpack_param(ctx,
248 SI_PARAM_TCS_OUT_OFFSETS,
249 0, 16),
250 4);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
255 {
256 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
257 unpack_param(ctx,
258 SI_PARAM_TCS_OUT_OFFSETS,
259 16, 16),
260 4);
261 }
262
263 static LLVMValueRef
264 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
265 {
266 struct gallivm_state *gallivm = &ctx->gallivm;
267 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
268 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
269
270 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
271 }
272
273 static LLVMValueRef
274 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
275 {
276 struct gallivm_state *gallivm = &ctx->gallivm;
277 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
278 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
279 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
280
281 return LLVMBuildAdd(gallivm->builder, patch0_offset,
282 LLVMBuildMul(gallivm->builder, patch_stride,
283 rel_patch_id, ""),
284 "");
285 }
286
287 static LLVMValueRef
288 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
289 {
290 struct gallivm_state *gallivm = &ctx->gallivm;
291 LLVMValueRef patch0_patch_data_offset =
292 get_tcs_out_patch0_patch_data_offset(ctx);
293 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
294 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
295
296 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
297 LLVMBuildMul(gallivm->builder, patch_stride,
298 rel_patch_id, ""),
299 "");
300 }
301
302 static LLVMValueRef get_instance_index_for_fetch(
303 struct si_shader_context *radeon_bld,
304 unsigned param_start_instance, unsigned divisor)
305 {
306 struct si_shader_context *ctx =
307 si_shader_context(&radeon_bld->bld_base);
308 struct gallivm_state *gallivm = radeon_bld->bld_base.base.gallivm;
309
310 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 lp_build_const_int32(gallivm, divisor), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct lp_build_context *base = &ctx->bld_base.base;
344 struct gallivm_state *gallivm = base->gallivm;
345
346 unsigned chan;
347 unsigned fix_fetch;
348 unsigned num_fetches;
349 unsigned fetch_stride;
350
351 LLVMValueRef t_list_ptr;
352 LLVMValueRef t_offset;
353 LLVMValueRef t_list;
354 LLVMValueRef vertex_index;
355 LLVMValueRef input[3];
356
357 /* Load the T list */
358 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
359
360 t_offset = lp_build_const_int32(gallivm, input_index);
361
362 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
363
364 vertex_index = LLVMGetParam(ctx->main_fn,
365 ctx->param_vertex_index0 +
366 input_index);
367
368 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
369
370 /* Do multiple loads for special formats. */
371 switch (fix_fetch) {
372 case SI_FIX_FETCH_RGB_64_FLOAT:
373 num_fetches = 3; /* 3 2-dword loads */
374 fetch_stride = 8;
375 break;
376 case SI_FIX_FETCH_RGBA_64_FLOAT:
377 num_fetches = 2; /* 2 4-dword loads */
378 fetch_stride = 16;
379 break;
380 case SI_FIX_FETCH_RGB_8:
381 case SI_FIX_FETCH_RGB_8_INT:
382 num_fetches = 3;
383 fetch_stride = 1;
384 break;
385 case SI_FIX_FETCH_RGB_16:
386 case SI_FIX_FETCH_RGB_16_INT:
387 num_fetches = 3;
388 fetch_stride = 2;
389 break;
390 default:
391 num_fetches = 1;
392 fetch_stride = 0;
393 }
394
395 for (unsigned i = 0; i < num_fetches; i++) {
396 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
397
398 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
399 vertex_index, voffset,
400 true);
401 }
402
403 /* Break up the vec4 into individual components */
404 for (chan = 0; chan < 4; chan++) {
405 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
406 out[chan] = LLVMBuildExtractElement(gallivm->builder,
407 input[0], llvm_chan, "");
408 }
409
410 switch (fix_fetch) {
411 case SI_FIX_FETCH_A2_SNORM:
412 case SI_FIX_FETCH_A2_SSCALED:
413 case SI_FIX_FETCH_A2_SINT: {
414 /* The hardware returns an unsigned value; convert it to a
415 * signed one.
416 */
417 LLVMValueRef tmp = out[3];
418 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
419
420 /* First, recover the sign-extended signed integer value. */
421 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
422 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
423 else
424 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
425
426 /* For the integer-like cases, do a natural sign extension.
427 *
428 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
429 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
430 * exponent.
431 */
432 tmp = LLVMBuildShl(gallivm->builder, tmp,
433 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
434 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
435 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
436
437 /* Convert back to the right type. */
438 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
439 LLVMValueRef clamp;
440 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
441 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
442 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
443 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
444 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
445 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
446 }
447
448 out[3] = tmp;
449 break;
450 }
451 case SI_FIX_FETCH_RGBA_32_UNORM:
452 case SI_FIX_FETCH_RGBX_32_UNORM:
453 for (chan = 0; chan < 4; chan++) {
454 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
455 ctx->i32, "");
456 out[chan] = LLVMBuildUIToFP(gallivm->builder,
457 out[chan], ctx->f32, "");
458 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
459 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
460 }
461 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
462 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
463 out[3] = LLVMConstReal(ctx->f32, 1);
464 break;
465 case SI_FIX_FETCH_RGBA_32_SNORM:
466 case SI_FIX_FETCH_RGBX_32_SNORM:
467 case SI_FIX_FETCH_RGBA_32_FIXED:
468 case SI_FIX_FETCH_RGBX_32_FIXED: {
469 double scale;
470 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
471 scale = 1.0 / 0x10000;
472 else
473 scale = 1.0 / INT_MAX;
474
475 for (chan = 0; chan < 4; chan++) {
476 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
477 ctx->i32, "");
478 out[chan] = LLVMBuildSIToFP(gallivm->builder,
479 out[chan], ctx->f32, "");
480 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
481 LLVMConstReal(ctx->f32, scale), "");
482 }
483 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
484 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
485 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
486 out[3] = LLVMConstReal(ctx->f32, 1);
487 break;
488 }
489 case SI_FIX_FETCH_RGBA_32_USCALED:
490 for (chan = 0; chan < 4; chan++) {
491 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
492 ctx->i32, "");
493 out[chan] = LLVMBuildUIToFP(gallivm->builder,
494 out[chan], ctx->f32, "");
495 }
496 break;
497 case SI_FIX_FETCH_RGBA_32_SSCALED:
498 for (chan = 0; chan < 4; chan++) {
499 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
500 ctx->i32, "");
501 out[chan] = LLVMBuildSIToFP(gallivm->builder,
502 out[chan], ctx->f32, "");
503 }
504 break;
505 case SI_FIX_FETCH_RG_64_FLOAT:
506 for (chan = 0; chan < 2; chan++)
507 out[chan] = extract_double_to_float(ctx, input[0], chan);
508
509 out[2] = LLVMConstReal(ctx->f32, 0);
510 out[3] = LLVMConstReal(ctx->f32, 1);
511 break;
512 case SI_FIX_FETCH_RGB_64_FLOAT:
513 for (chan = 0; chan < 3; chan++)
514 out[chan] = extract_double_to_float(ctx, input[chan], 0);
515
516 out[3] = LLVMConstReal(ctx->f32, 1);
517 break;
518 case SI_FIX_FETCH_RGBA_64_FLOAT:
519 for (chan = 0; chan < 4; chan++) {
520 out[chan] = extract_double_to_float(ctx, input[chan / 2],
521 chan % 2);
522 }
523 break;
524 case SI_FIX_FETCH_RGB_8:
525 case SI_FIX_FETCH_RGB_8_INT:
526 case SI_FIX_FETCH_RGB_16:
527 case SI_FIX_FETCH_RGB_16_INT:
528 for (chan = 0; chan < 3; chan++) {
529 out[chan] = LLVMBuildExtractElement(gallivm->builder,
530 input[chan],
531 ctx->i32_0, "");
532 }
533 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
534 fix_fetch == SI_FIX_FETCH_RGB_16) {
535 out[3] = LLVMConstReal(ctx->f32, 1);
536 } else {
537 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
538 ctx->f32, "");
539 }
540 break;
541 }
542 }
543
544 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
545 unsigned swizzle)
546 {
547 struct si_shader_context *ctx = si_shader_context(bld_base);
548
549 if (swizzle > 0)
550 return bld_base->uint_bld.zero;
551
552 switch (ctx->type) {
553 case PIPE_SHADER_VERTEX:
554 return LLVMGetParam(ctx->main_fn,
555 ctx->param_vs_prim_id);
556 case PIPE_SHADER_TESS_CTRL:
557 return LLVMGetParam(ctx->main_fn,
558 SI_PARAM_PATCH_ID);
559 case PIPE_SHADER_TESS_EVAL:
560 return LLVMGetParam(ctx->main_fn,
561 ctx->param_tes_patch_id);
562 case PIPE_SHADER_GEOMETRY:
563 return LLVMGetParam(ctx->main_fn,
564 SI_PARAM_PRIMITIVE_ID);
565 default:
566 assert(0);
567 return bld_base->uint_bld.zero;
568 }
569 }
570
571 /**
572 * Return the value of tgsi_ind_register for indexing.
573 * This is the indirect index with the constant offset added to it.
574 */
575 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
576 const struct tgsi_ind_register *ind,
577 int rel_index)
578 {
579 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
580 LLVMValueRef result;
581
582 result = ctx->addrs[ind->Index][ind->Swizzle];
583 result = LLVMBuildLoad(gallivm->builder, result, "");
584 result = LLVMBuildAdd(gallivm->builder, result,
585 lp_build_const_int32(gallivm, rel_index), "");
586 return result;
587 }
588
589 /**
590 * Like get_indirect_index, but restricts the return value to a (possibly
591 * undefined) value inside [0..num).
592 */
593 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
594 const struct tgsi_ind_register *ind,
595 int rel_index, unsigned num)
596 {
597 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
598
599 /* LLVM 3.8: If indirect resource indexing is used:
600 * - SI & CIK hang
601 * - VI crashes
602 */
603 if (HAVE_LLVM == 0x0308)
604 return LLVMGetUndef(ctx->i32);
605
606 return si_llvm_bound_index(ctx, result, num);
607 }
608
609
610 /**
611 * Calculate a dword address given an input or output register and a stride.
612 */
613 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
614 const struct tgsi_full_dst_register *dst,
615 const struct tgsi_full_src_register *src,
616 LLVMValueRef vertex_dw_stride,
617 LLVMValueRef base_addr)
618 {
619 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
620 struct tgsi_shader_info *info = &ctx->shader->selector->info;
621 ubyte *name, *index, *array_first;
622 int first, param;
623 struct tgsi_full_dst_register reg;
624
625 /* Set the register description. The address computation is the same
626 * for sources and destinations. */
627 if (src) {
628 reg.Register.File = src->Register.File;
629 reg.Register.Index = src->Register.Index;
630 reg.Register.Indirect = src->Register.Indirect;
631 reg.Register.Dimension = src->Register.Dimension;
632 reg.Indirect = src->Indirect;
633 reg.Dimension = src->Dimension;
634 reg.DimIndirect = src->DimIndirect;
635 } else
636 reg = *dst;
637
638 /* If the register is 2-dimensional (e.g. an array of vertices
639 * in a primitive), calculate the base address of the vertex. */
640 if (reg.Register.Dimension) {
641 LLVMValueRef index;
642
643 if (reg.Dimension.Indirect)
644 index = get_indirect_index(ctx, &reg.DimIndirect,
645 reg.Dimension.Index);
646 else
647 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
648
649 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
650 LLVMBuildMul(gallivm->builder, index,
651 vertex_dw_stride, ""), "");
652 }
653
654 /* Get information about the register. */
655 if (reg.Register.File == TGSI_FILE_INPUT) {
656 name = info->input_semantic_name;
657 index = info->input_semantic_index;
658 array_first = info->input_array_first;
659 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
660 name = info->output_semantic_name;
661 index = info->output_semantic_index;
662 array_first = info->output_array_first;
663 } else {
664 assert(0);
665 return NULL;
666 }
667
668 if (reg.Register.Indirect) {
669 /* Add the relative address of the element. */
670 LLVMValueRef ind_index;
671
672 if (reg.Indirect.ArrayID)
673 first = array_first[reg.Indirect.ArrayID];
674 else
675 first = reg.Register.Index;
676
677 ind_index = get_indirect_index(ctx, &reg.Indirect,
678 reg.Register.Index - first);
679
680 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
681 LLVMBuildMul(gallivm->builder, ind_index,
682 lp_build_const_int32(gallivm, 4), ""), "");
683
684 param = si_shader_io_get_unique_index(name[first], index[first]);
685 } else {
686 param = si_shader_io_get_unique_index(name[reg.Register.Index],
687 index[reg.Register.Index]);
688 }
689
690 /* Add the base address of the element. */
691 return LLVMBuildAdd(gallivm->builder, base_addr,
692 lp_build_const_int32(gallivm, param * 4), "");
693 }
694
695 /* The offchip buffer layout for TCS->TES is
696 *
697 * - attribute 0 of patch 0 vertex 0
698 * - attribute 0 of patch 0 vertex 1
699 * - attribute 0 of patch 0 vertex 2
700 * ...
701 * - attribute 0 of patch 1 vertex 0
702 * - attribute 0 of patch 1 vertex 1
703 * ...
704 * - attribute 1 of patch 0 vertex 0
705 * - attribute 1 of patch 0 vertex 1
706 * ...
707 * - per patch attribute 0 of patch 0
708 * - per patch attribute 0 of patch 1
709 * ...
710 *
711 * Note that every attribute has 4 components.
712 */
713 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
714 LLVMValueRef rel_patch_id,
715 LLVMValueRef vertex_index,
716 LLVMValueRef param_index)
717 {
718 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
719 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
720 LLVMValueRef param_stride, constant16;
721
722 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
723 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
724 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
725 num_patches, "");
726
727 constant16 = lp_build_const_int32(gallivm, 16);
728 if (vertex_index) {
729 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
730 vertices_per_patch, "");
731
732 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
733 vertex_index, "");
734
735 param_stride = total_vertices;
736 } else {
737 base_addr = rel_patch_id;
738 param_stride = num_patches;
739 }
740
741 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
742 LLVMBuildMul(gallivm->builder, param_index,
743 param_stride, ""), "");
744
745 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
746
747 if (!vertex_index) {
748 LLVMValueRef patch_data_offset =
749 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
750
751 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
752 patch_data_offset, "");
753 }
754 return base_addr;
755 }
756
757 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
758 struct si_shader_context *ctx,
759 const struct tgsi_full_dst_register *dst,
760 const struct tgsi_full_src_register *src)
761 {
762 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
763 struct tgsi_shader_info *info = &ctx->shader->selector->info;
764 ubyte *name, *index, *array_first;
765 struct tgsi_full_src_register reg;
766 LLVMValueRef vertex_index = NULL;
767 LLVMValueRef param_index = NULL;
768 unsigned param_index_base, param_base;
769
770 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
771
772 if (reg.Register.Dimension) {
773
774 if (reg.Dimension.Indirect)
775 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
776 reg.Dimension.Index);
777 else
778 vertex_index = lp_build_const_int32(gallivm,
779 reg.Dimension.Index);
780 }
781
782 /* Get information about the register. */
783 if (reg.Register.File == TGSI_FILE_INPUT) {
784 name = info->input_semantic_name;
785 index = info->input_semantic_index;
786 array_first = info->input_array_first;
787 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
788 name = info->output_semantic_name;
789 index = info->output_semantic_index;
790 array_first = info->output_array_first;
791 } else {
792 assert(0);
793 return NULL;
794 }
795
796 if (reg.Register.Indirect) {
797 if (reg.Indirect.ArrayID)
798 param_base = array_first[reg.Indirect.ArrayID];
799 else
800 param_base = reg.Register.Index;
801
802 param_index = get_indirect_index(ctx, &reg.Indirect,
803 reg.Register.Index - param_base);
804
805 } else {
806 param_base = reg.Register.Index;
807 param_index = lp_build_const_int32(gallivm, 0);
808 }
809
810 param_index_base = si_shader_io_get_unique_index(name[param_base],
811 index[param_base]);
812
813 param_index = LLVMBuildAdd(gallivm->builder, param_index,
814 lp_build_const_int32(gallivm, param_index_base),
815 "");
816
817 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
818 vertex_index, param_index);
819 }
820
821 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
822 enum tgsi_opcode_type type, unsigned swizzle,
823 LLVMValueRef buffer, LLVMValueRef offset,
824 LLVMValueRef base, bool readonly_memory)
825 {
826 struct si_shader_context *ctx = si_shader_context(bld_base);
827 struct gallivm_state *gallivm = bld_base->base.gallivm;
828 LLVMValueRef value, value2;
829 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
830 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
831
832 if (swizzle == ~0) {
833 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
834 0, 1, 0, readonly_memory);
835
836 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
837 }
838
839 if (!tgsi_type_is_64bit(type)) {
840 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
841 0, 1, 0, readonly_memory);
842
843 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
844 return LLVMBuildExtractElement(gallivm->builder, value,
845 lp_build_const_int32(gallivm, swizzle), "");
846 }
847
848 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
849 swizzle * 4, 1, 0, readonly_memory);
850
851 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
852 swizzle * 4 + 4, 1, 0, readonly_memory);
853
854 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
855 }
856
857 /**
858 * Load from LDS.
859 *
860 * \param type output value type
861 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
862 * \param dw_addr address in dwords
863 */
864 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
865 enum tgsi_opcode_type type, unsigned swizzle,
866 LLVMValueRef dw_addr)
867 {
868 struct si_shader_context *ctx = si_shader_context(bld_base);
869 struct gallivm_state *gallivm = bld_base->base.gallivm;
870 LLVMValueRef value;
871
872 if (swizzle == ~0) {
873 LLVMValueRef values[TGSI_NUM_CHANNELS];
874
875 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
876 values[chan] = lds_load(bld_base, type, chan, dw_addr);
877
878 return lp_build_gather_values(bld_base->base.gallivm, values,
879 TGSI_NUM_CHANNELS);
880 }
881
882 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
883 lp_build_const_int32(gallivm, swizzle));
884
885 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
886 if (tgsi_type_is_64bit(type)) {
887 LLVMValueRef value2;
888 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
889 lp_build_const_int32(gallivm, 1));
890 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
891 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
892 }
893
894 return LLVMBuildBitCast(gallivm->builder, value,
895 tgsi2llvmtype(bld_base, type), "");
896 }
897
898 /**
899 * Store to LDS.
900 *
901 * \param swizzle offset (typically 0..3)
902 * \param dw_addr address in dwords
903 * \param value value to store
904 */
905 static void lds_store(struct lp_build_tgsi_context *bld_base,
906 unsigned swizzle, LLVMValueRef dw_addr,
907 LLVMValueRef value)
908 {
909 struct si_shader_context *ctx = si_shader_context(bld_base);
910 struct gallivm_state *gallivm = bld_base->base.gallivm;
911
912 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
913 lp_build_const_int32(gallivm, swizzle));
914
915 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
916 ac_build_indexed_store(&ctx->ac, ctx->lds,
917 dw_addr, value);
918 }
919
920 static LLVMValueRef fetch_input_tcs(
921 struct lp_build_tgsi_context *bld_base,
922 const struct tgsi_full_src_register *reg,
923 enum tgsi_opcode_type type, unsigned swizzle)
924 {
925 struct si_shader_context *ctx = si_shader_context(bld_base);
926 LLVMValueRef dw_addr, stride;
927
928 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
929 dw_addr = get_tcs_in_current_patch_offset(ctx);
930 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
931
932 return lds_load(bld_base, type, swizzle, dw_addr);
933 }
934
935 static LLVMValueRef fetch_output_tcs(
936 struct lp_build_tgsi_context *bld_base,
937 const struct tgsi_full_src_register *reg,
938 enum tgsi_opcode_type type, unsigned swizzle)
939 {
940 struct si_shader_context *ctx = si_shader_context(bld_base);
941 LLVMValueRef dw_addr, stride;
942
943 if (reg->Register.Dimension) {
944 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
945 dw_addr = get_tcs_out_current_patch_offset(ctx);
946 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
947 } else {
948 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
949 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
950 }
951
952 return lds_load(bld_base, type, swizzle, dw_addr);
953 }
954
955 static LLVMValueRef fetch_input_tes(
956 struct lp_build_tgsi_context *bld_base,
957 const struct tgsi_full_src_register *reg,
958 enum tgsi_opcode_type type, unsigned swizzle)
959 {
960 struct si_shader_context *ctx = si_shader_context(bld_base);
961 struct gallivm_state *gallivm = bld_base->base.gallivm;
962 LLVMValueRef rw_buffers, buffer, base, addr;
963
964 rw_buffers = LLVMGetParam(ctx->main_fn,
965 SI_PARAM_RW_BUFFERS);
966 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
967 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
968
969 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
970 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
971
972 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
973 }
974
975 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
976 const struct tgsi_full_instruction *inst,
977 const struct tgsi_opcode_info *info,
978 LLVMValueRef dst[4])
979 {
980 struct si_shader_context *ctx = si_shader_context(bld_base);
981 struct gallivm_state *gallivm = bld_base->base.gallivm;
982 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
983 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
984 unsigned chan_index;
985 LLVMValueRef dw_addr, stride;
986 LLVMValueRef rw_buffers, buffer, base, buf_addr;
987 LLVMValueRef values[4];
988 bool skip_lds_store;
989 bool is_tess_factor = false;
990
991 /* Only handle per-patch and per-vertex outputs here.
992 * Vectors will be lowered to scalars and this function will be called again.
993 */
994 if (reg->Register.File != TGSI_FILE_OUTPUT ||
995 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
996 si_llvm_emit_store(bld_base, inst, info, dst);
997 return;
998 }
999
1000 if (reg->Register.Dimension) {
1001 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1002 dw_addr = get_tcs_out_current_patch_offset(ctx);
1003 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1004 skip_lds_store = !sh_info->reads_pervertex_outputs;
1005 } else {
1006 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1007 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1008 skip_lds_store = !sh_info->reads_perpatch_outputs;
1009
1010 if (!reg->Register.Indirect) {
1011 int name = sh_info->output_semantic_name[reg->Register.Index];
1012
1013 /* Always write tess factors into LDS for the TCS epilog. */
1014 if (name == TGSI_SEMANTIC_TESSINNER ||
1015 name == TGSI_SEMANTIC_TESSOUTER) {
1016 skip_lds_store = false;
1017 is_tess_factor = true;
1018 }
1019 }
1020 }
1021
1022 rw_buffers = LLVMGetParam(ctx->main_fn,
1023 SI_PARAM_RW_BUFFERS);
1024 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1025 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1026
1027 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1028 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1029
1030
1031 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1032 LLVMValueRef value = dst[chan_index];
1033
1034 if (inst->Instruction.Saturate)
1035 value = ac_build_clamp(&ctx->ac, value);
1036
1037 /* Skip LDS stores if there is no LDS read of this output. */
1038 if (!skip_lds_store)
1039 lds_store(bld_base, chan_index, dw_addr, value);
1040
1041 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1042 values[chan_index] = value;
1043
1044 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1045 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1046 buf_addr, base,
1047 4 * chan_index, 1, 0, true, false);
1048 }
1049 }
1050
1051 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1052 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1053 values, 4);
1054 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1055 base, 0, 1, 0, true, false);
1056 }
1057 }
1058
1059 static LLVMValueRef fetch_input_gs(
1060 struct lp_build_tgsi_context *bld_base,
1061 const struct tgsi_full_src_register *reg,
1062 enum tgsi_opcode_type type,
1063 unsigned swizzle)
1064 {
1065 struct lp_build_context *base = &bld_base->base;
1066 struct si_shader_context *ctx = si_shader_context(bld_base);
1067 struct si_shader *shader = ctx->shader;
1068 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1069 struct gallivm_state *gallivm = base->gallivm;
1070 LLVMValueRef vtx_offset, soffset;
1071 unsigned vtx_offset_param;
1072 struct tgsi_shader_info *info = &shader->selector->info;
1073 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1074 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1075 unsigned param;
1076 LLVMValueRef value;
1077
1078 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1079 return get_primitive_id(bld_base, swizzle);
1080
1081 if (!reg->Register.Dimension)
1082 return NULL;
1083
1084 if (swizzle == ~0) {
1085 LLVMValueRef values[TGSI_NUM_CHANNELS];
1086 unsigned chan;
1087 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1088 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1089 }
1090 return lp_build_gather_values(bld_base->base.gallivm, values,
1091 TGSI_NUM_CHANNELS);
1092 }
1093
1094 /* Get the vertex offset parameter */
1095 vtx_offset_param = reg->Dimension.Index;
1096 if (vtx_offset_param < 2) {
1097 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1098 } else {
1099 assert(vtx_offset_param < 6);
1100 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1101 }
1102 vtx_offset = lp_build_mul_imm(uint,
1103 LLVMGetParam(ctx->main_fn,
1104 vtx_offset_param),
1105 4);
1106
1107 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1108 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1109
1110 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, uint->zero,
1111 vtx_offset, soffset, 0, 1, 0, true);
1112 if (tgsi_type_is_64bit(type)) {
1113 LLVMValueRef value2;
1114 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1115
1116 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1117 uint->zero, vtx_offset, soffset,
1118 0, 1, 0, true);
1119 return si_llvm_emit_fetch_64bit(bld_base, type,
1120 value, value2);
1121 }
1122 return LLVMBuildBitCast(gallivm->builder,
1123 value,
1124 tgsi2llvmtype(bld_base, type), "");
1125 }
1126
1127 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1128 {
1129 switch (interpolate) {
1130 case TGSI_INTERPOLATE_CONSTANT:
1131 return 0;
1132
1133 case TGSI_INTERPOLATE_LINEAR:
1134 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1135 return SI_PARAM_LINEAR_SAMPLE;
1136 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1137 return SI_PARAM_LINEAR_CENTROID;
1138 else
1139 return SI_PARAM_LINEAR_CENTER;
1140 break;
1141 case TGSI_INTERPOLATE_COLOR:
1142 case TGSI_INTERPOLATE_PERSPECTIVE:
1143 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1144 return SI_PARAM_PERSP_SAMPLE;
1145 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1146 return SI_PARAM_PERSP_CENTROID;
1147 else
1148 return SI_PARAM_PERSP_CENTER;
1149 break;
1150 default:
1151 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1152 return -1;
1153 }
1154 }
1155
1156 /**
1157 * Interpolate a fragment shader input.
1158 *
1159 * @param ctx context
1160 * @param input_index index of the input in hardware
1161 * @param semantic_name TGSI_SEMANTIC_*
1162 * @param semantic_index semantic index
1163 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1164 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1165 * @param interp_param interpolation weights (i,j)
1166 * @param prim_mask SI_PARAM_PRIM_MASK
1167 * @param face SI_PARAM_FRONT_FACE
1168 * @param result the return value (4 components)
1169 */
1170 static void interp_fs_input(struct si_shader_context *ctx,
1171 unsigned input_index,
1172 unsigned semantic_name,
1173 unsigned semantic_index,
1174 unsigned num_interp_inputs,
1175 unsigned colors_read_mask,
1176 LLVMValueRef interp_param,
1177 LLVMValueRef prim_mask,
1178 LLVMValueRef face,
1179 LLVMValueRef result[4])
1180 {
1181 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1182 struct lp_build_context *base = &bld_base->base;
1183 struct lp_build_context *uint = &bld_base->uint_bld;
1184 struct gallivm_state *gallivm = base->gallivm;
1185 LLVMValueRef attr_number;
1186 LLVMValueRef i, j;
1187
1188 unsigned chan;
1189
1190 /* fs.constant returns the param from the middle vertex, so it's not
1191 * really useful for flat shading. It's meant to be used for custom
1192 * interpolation (but the intrinsic can't fetch from the other two
1193 * vertices).
1194 *
1195 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1196 * to do the right thing. The only reason we use fs.constant is that
1197 * fs.interp cannot be used on integers, because they can be equal
1198 * to NaN.
1199 *
1200 * When interp is false we will use fs.constant or for newer llvm,
1201 * amdgcn.interp.mov.
1202 */
1203 bool interp = interp_param != NULL;
1204
1205 attr_number = lp_build_const_int32(gallivm, input_index);
1206
1207 if (interp) {
1208 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1209 LLVMVectorType(ctx->f32, 2), "");
1210
1211 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1212 uint->zero, "");
1213 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1214 uint->one, "");
1215 }
1216
1217 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1218 ctx->shader->key.part.ps.prolog.color_two_side) {
1219 LLVMValueRef is_face_positive;
1220 LLVMValueRef back_attr_number;
1221
1222 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1223 * otherwise it's at offset "num_inputs".
1224 */
1225 unsigned back_attr_offset = num_interp_inputs;
1226 if (semantic_index == 1 && colors_read_mask & 0xf)
1227 back_attr_offset += 1;
1228
1229 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1230
1231 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1232 face, uint->zero, "");
1233
1234 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1235 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1236 LLVMValueRef front, back;
1237
1238 if (interp) {
1239 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1240 attr_number, prim_mask,
1241 i, j);
1242 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1243 back_attr_number, prim_mask,
1244 i, j);
1245 } else {
1246 front = ac_build_fs_interp_mov(&ctx->ac,
1247 lp_build_const_int32(gallivm, 2), /* P0 */
1248 llvm_chan, attr_number, prim_mask);
1249 back = ac_build_fs_interp_mov(&ctx->ac,
1250 lp_build_const_int32(gallivm, 2), /* P0 */
1251 llvm_chan, back_attr_number, prim_mask);
1252 }
1253
1254 result[chan] = LLVMBuildSelect(gallivm->builder,
1255 is_face_positive,
1256 front,
1257 back,
1258 "");
1259 }
1260 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1261 if (interp) {
1262 result[0] = ac_build_fs_interp(&ctx->ac, uint->zero,
1263 attr_number, prim_mask, i, j);
1264 } else {
1265 result[0] = ac_build_fs_interp_mov(&ctx->ac, uint->zero,
1266 lp_build_const_int32(gallivm, 2), /* P0 */
1267 attr_number, prim_mask);
1268 }
1269 result[1] =
1270 result[2] = lp_build_const_float(gallivm, 0.0f);
1271 result[3] = lp_build_const_float(gallivm, 1.0f);
1272 } else {
1273 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1274 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1275
1276 if (interp) {
1277 result[chan] = ac_build_fs_interp(&ctx->ac,
1278 llvm_chan, attr_number, prim_mask, i, j);
1279 } else {
1280 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1281 lp_build_const_int32(gallivm, 2), /* P0 */
1282 llvm_chan, attr_number, prim_mask);
1283 }
1284 }
1285 }
1286 }
1287
1288 static void declare_input_fs(
1289 struct si_shader_context *radeon_bld,
1290 unsigned input_index,
1291 const struct tgsi_full_declaration *decl,
1292 LLVMValueRef out[4])
1293 {
1294 struct lp_build_context *base = &radeon_bld->bld_base.base;
1295 struct si_shader_context *ctx =
1296 si_shader_context(&radeon_bld->bld_base);
1297 struct si_shader *shader = ctx->shader;
1298 LLVMValueRef main_fn = radeon_bld->main_fn;
1299 LLVMValueRef interp_param = NULL;
1300 int interp_param_idx;
1301
1302 /* Get colors from input VGPRs (set by the prolog). */
1303 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1304 unsigned i = decl->Semantic.Index;
1305 unsigned colors_read = shader->selector->info.colors_read;
1306 unsigned mask = colors_read >> (i * 4);
1307 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1308 (i ? util_bitcount(colors_read & 0xf) : 0);
1309
1310 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1311 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1312 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1313 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1314 return;
1315 }
1316
1317 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1318 decl->Interp.Location);
1319 if (interp_param_idx == -1)
1320 return;
1321 else if (interp_param_idx) {
1322 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1323 }
1324
1325 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1326 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1327 ctx->shader->key.part.ps.prolog.flatshade_colors)
1328 interp_param = NULL; /* load the constant color */
1329
1330 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1331 decl->Semantic.Index, shader->selector->info.num_inputs,
1332 shader->selector->info.colors_read, interp_param,
1333 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1334 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1335 &out[0]);
1336 }
1337
1338 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1339 {
1340 return unpack_param(si_shader_context(&radeon_bld->bld_base),
1341 SI_PARAM_ANCILLARY, 8, 4);
1342 }
1343
1344
1345 /**
1346 * Load a dword from a constant buffer.
1347 */
1348 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1349 LLVMValueRef resource,
1350 LLVMValueRef offset)
1351 {
1352 LLVMBuilderRef builder = ctx->gallivm.builder;
1353 LLVMValueRef args[2] = {resource, offset};
1354
1355 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1356 LP_FUNC_ATTR_READNONE |
1357 LP_FUNC_ATTR_LEGACY);
1358 }
1359
1360 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1361 {
1362 struct si_shader_context *ctx =
1363 si_shader_context(&radeon_bld->bld_base);
1364 struct lp_build_context *uint_bld = &radeon_bld->bld_base.uint_bld;
1365 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1366 LLVMBuilderRef builder = gallivm->builder;
1367 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1368 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1369 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1370
1371 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1372 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1373 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1374
1375 LLVMValueRef pos[4] = {
1376 buffer_load_const(ctx, resource, offset0),
1377 buffer_load_const(ctx, resource, offset1),
1378 lp_build_const_float(gallivm, 0),
1379 lp_build_const_float(gallivm, 0)
1380 };
1381
1382 return lp_build_gather_values(gallivm, pos, 4);
1383 }
1384
1385 static void declare_system_value(
1386 struct si_shader_context *radeon_bld,
1387 unsigned index,
1388 const struct tgsi_full_declaration *decl)
1389 {
1390 struct si_shader_context *ctx =
1391 si_shader_context(&radeon_bld->bld_base);
1392 struct lp_build_context *bld = &radeon_bld->bld_base.base;
1393 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1394 LLVMValueRef value = 0;
1395
1396 switch (decl->Semantic.Name) {
1397 case TGSI_SEMANTIC_INSTANCEID:
1398 value = LLVMGetParam(radeon_bld->main_fn,
1399 ctx->param_instance_id);
1400 break;
1401
1402 case TGSI_SEMANTIC_VERTEXID:
1403 value = LLVMBuildAdd(gallivm->builder,
1404 LLVMGetParam(radeon_bld->main_fn,
1405 ctx->param_vertex_id),
1406 LLVMGetParam(radeon_bld->main_fn,
1407 SI_PARAM_BASE_VERTEX), "");
1408 break;
1409
1410 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1411 value = LLVMGetParam(radeon_bld->main_fn,
1412 ctx->param_vertex_id);
1413 break;
1414
1415 case TGSI_SEMANTIC_BASEVERTEX:
1416 value = LLVMGetParam(radeon_bld->main_fn,
1417 SI_PARAM_BASE_VERTEX);
1418 break;
1419
1420 case TGSI_SEMANTIC_BASEINSTANCE:
1421 value = LLVMGetParam(radeon_bld->main_fn,
1422 SI_PARAM_START_INSTANCE);
1423 break;
1424
1425 case TGSI_SEMANTIC_DRAWID:
1426 value = LLVMGetParam(radeon_bld->main_fn,
1427 SI_PARAM_DRAWID);
1428 break;
1429
1430 case TGSI_SEMANTIC_INVOCATIONID:
1431 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1432 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1433 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1434 value = LLVMGetParam(radeon_bld->main_fn,
1435 SI_PARAM_GS_INSTANCE_ID);
1436 else
1437 assert(!"INVOCATIONID not implemented");
1438 break;
1439
1440 case TGSI_SEMANTIC_POSITION:
1441 {
1442 LLVMValueRef pos[4] = {
1443 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1444 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1445 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1446 lp_build_emit_llvm_unary(&radeon_bld->bld_base, TGSI_OPCODE_RCP,
1447 LLVMGetParam(radeon_bld->main_fn,
1448 SI_PARAM_POS_W_FLOAT)),
1449 };
1450 value = lp_build_gather_values(gallivm, pos, 4);
1451 break;
1452 }
1453
1454 case TGSI_SEMANTIC_FACE:
1455 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1456 break;
1457
1458 case TGSI_SEMANTIC_SAMPLEID:
1459 value = get_sample_id(radeon_bld);
1460 break;
1461
1462 case TGSI_SEMANTIC_SAMPLEPOS: {
1463 LLVMValueRef pos[4] = {
1464 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1465 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1466 lp_build_const_float(gallivm, 0),
1467 lp_build_const_float(gallivm, 0)
1468 };
1469 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1470 TGSI_OPCODE_FRC, pos[0]);
1471 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->bld_base,
1472 TGSI_OPCODE_FRC, pos[1]);
1473 value = lp_build_gather_values(gallivm, pos, 4);
1474 break;
1475 }
1476
1477 case TGSI_SEMANTIC_SAMPLEMASK:
1478 /* This can only occur with the OpenGL Core profile, which
1479 * doesn't support smoothing.
1480 */
1481 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1482 break;
1483
1484 case TGSI_SEMANTIC_TESSCOORD:
1485 {
1486 LLVMValueRef coord[4] = {
1487 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1488 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1489 bld->zero,
1490 bld->zero
1491 };
1492
1493 /* For triangles, the vector should be (u, v, 1-u-v). */
1494 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1495 PIPE_PRIM_TRIANGLES)
1496 coord[2] = lp_build_sub(bld, bld->one,
1497 lp_build_add(bld, coord[0], coord[1]));
1498
1499 value = lp_build_gather_values(gallivm, coord, 4);
1500 break;
1501 }
1502
1503 case TGSI_SEMANTIC_VERTICESIN:
1504 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1505 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1506 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1507 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1508 else
1509 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1510 break;
1511
1512 case TGSI_SEMANTIC_TESSINNER:
1513 case TGSI_SEMANTIC_TESSOUTER:
1514 {
1515 LLVMValueRef rw_buffers, buffer, base, addr;
1516 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1517
1518 rw_buffers = LLVMGetParam(ctx->main_fn,
1519 SI_PARAM_RW_BUFFERS);
1520 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1521 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1522
1523 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1524 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1525 lp_build_const_int32(gallivm, param));
1526
1527 value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
1528 ~0, buffer, base, addr, true);
1529
1530 break;
1531 }
1532
1533 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1534 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1535 {
1536 LLVMValueRef buf, slot, val[4];
1537 int i, offset;
1538
1539 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1540 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1541 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1542 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1543
1544 for (i = 0; i < 4; i++)
1545 val[i] = buffer_load_const(ctx, buf,
1546 lp_build_const_int32(gallivm, (offset + i) * 4));
1547 value = lp_build_gather_values(gallivm, val, 4);
1548 break;
1549 }
1550
1551 case TGSI_SEMANTIC_PRIMID:
1552 value = get_primitive_id(&radeon_bld->bld_base, 0);
1553 break;
1554
1555 case TGSI_SEMANTIC_GRID_SIZE:
1556 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1557 break;
1558
1559 case TGSI_SEMANTIC_BLOCK_SIZE:
1560 {
1561 LLVMValueRef values[3];
1562 unsigned i;
1563 unsigned *properties = ctx->shader->selector->info.properties;
1564
1565 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1566 unsigned sizes[3] = {
1567 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1568 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1569 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1570 };
1571
1572 for (i = 0; i < 3; ++i)
1573 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1574
1575 value = lp_build_gather_values(gallivm, values, 3);
1576 } else {
1577 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1578 }
1579 break;
1580 }
1581
1582 case TGSI_SEMANTIC_BLOCK_ID:
1583 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1584 break;
1585
1586 case TGSI_SEMANTIC_THREAD_ID:
1587 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1588 break;
1589
1590 case TGSI_SEMANTIC_HELPER_INVOCATION:
1591 if (HAVE_LLVM >= 0x0309) {
1592 value = lp_build_intrinsic(gallivm->builder,
1593 "llvm.amdgcn.ps.live",
1594 ctx->i1, NULL, 0,
1595 LP_FUNC_ATTR_READNONE);
1596 value = LLVMBuildNot(gallivm->builder, value, "");
1597 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1598 } else {
1599 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1600 return;
1601 }
1602 break;
1603
1604 default:
1605 assert(!"unknown system value");
1606 return;
1607 }
1608
1609 radeon_bld->system_values[index] = value;
1610 }
1611
1612 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1613 const struct tgsi_full_declaration *decl)
1614 {
1615 struct si_shader_context *ctx =
1616 si_shader_context(&radeon_bld->bld_base);
1617 struct si_shader_selector *sel = ctx->shader->selector;
1618 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1619
1620 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1621 LLVMValueRef var;
1622
1623 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1624 assert(decl->Range.First == decl->Range.Last);
1625 assert(!ctx->shared_memory);
1626
1627 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1628 LLVMArrayType(ctx->i8, sel->local_size),
1629 "compute_lds",
1630 LOCAL_ADDR_SPACE);
1631 LLVMSetAlignment(var, 4);
1632
1633 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1634 }
1635
1636 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1637 {
1638 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1639 SI_PARAM_CONST_BUFFERS);
1640
1641 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1642 LLVMConstInt(ctx->i32, i, 0));
1643 }
1644
1645 static LLVMValueRef fetch_constant(
1646 struct lp_build_tgsi_context *bld_base,
1647 const struct tgsi_full_src_register *reg,
1648 enum tgsi_opcode_type type,
1649 unsigned swizzle)
1650 {
1651 struct si_shader_context *ctx = si_shader_context(bld_base);
1652 struct lp_build_context *base = &bld_base->base;
1653 const struct tgsi_ind_register *ireg = &reg->Indirect;
1654 unsigned buf, idx;
1655
1656 LLVMValueRef addr, bufp;
1657 LLVMValueRef result;
1658
1659 if (swizzle == LP_CHAN_ALL) {
1660 unsigned chan;
1661 LLVMValueRef values[4];
1662 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1663 values[chan] = fetch_constant(bld_base, reg, type, chan);
1664
1665 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1666 }
1667
1668 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1669 idx = reg->Register.Index * 4 + swizzle;
1670
1671 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1672 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1673 LLVMValueRef index;
1674 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1675 reg->Dimension.Index,
1676 SI_NUM_CONST_BUFFERS);
1677 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1678 } else
1679 bufp = load_const_buffer_desc(ctx, buf);
1680
1681 if (reg->Register.Indirect) {
1682 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1683 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1684 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1685 addr = lp_build_add(&bld_base->uint_bld, addr,
1686 lp_build_const_int32(base->gallivm, idx * 4));
1687 } else {
1688 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1689 }
1690
1691 result = buffer_load_const(ctx, bufp, addr);
1692
1693 if (!tgsi_type_is_64bit(type))
1694 result = bitcast(bld_base, type, result);
1695 else {
1696 LLVMValueRef addr2, result2;
1697
1698 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1699 LLVMConstInt(ctx->i32, 4, 0));
1700 result2 = buffer_load_const(ctx, bufp, addr2);
1701
1702 result = si_llvm_emit_fetch_64bit(bld_base, type,
1703 result, result2);
1704 }
1705 return result;
1706 }
1707
1708 /* Upper 16 bits must be zero. */
1709 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1710 LLVMValueRef val[2])
1711 {
1712 return LLVMBuildOr(gallivm->builder, val[0],
1713 LLVMBuildShl(gallivm->builder, val[1],
1714 lp_build_const_int32(gallivm, 16),
1715 ""), "");
1716 }
1717
1718 /* Upper 16 bits are ignored and will be dropped. */
1719 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1720 LLVMValueRef val[2])
1721 {
1722 LLVMValueRef v[2] = {
1723 LLVMBuildAnd(gallivm->builder, val[0],
1724 lp_build_const_int32(gallivm, 0xffff), ""),
1725 val[1],
1726 };
1727 return si_llvm_pack_two_int16(gallivm, v);
1728 }
1729
1730 /* Initialize arguments for the shader export intrinsic */
1731 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1732 LLVMValueRef *values,
1733 unsigned target,
1734 struct ac_export_args *args)
1735 {
1736 struct si_shader_context *ctx = si_shader_context(bld_base);
1737 struct lp_build_context *base = &bld_base->base;
1738 struct gallivm_state *gallivm = base->gallivm;
1739 LLVMBuilderRef builder = base->gallivm->builder;
1740 LLVMValueRef val[4];
1741 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1742 unsigned chan;
1743 bool is_int8, is_int10;
1744
1745 /* Default is 0xf. Adjusted below depending on the format. */
1746 args->enabled_channels = 0xf; /* writemask */
1747
1748 /* Specify whether the EXEC mask represents the valid mask */
1749 args->valid_mask = 0;
1750
1751 /* Specify whether this is the last export */
1752 args->done = 0;
1753
1754 /* Specify the target we are exporting */
1755 args->target = target;
1756
1757 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1758 const struct si_shader_key *key = &ctx->shader->key;
1759 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1760 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1761
1762 assert(cbuf >= 0 && cbuf < 8);
1763 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1764 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1765 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1766 }
1767
1768 args->compr = false;
1769 args->out[0] = base->undef;
1770 args->out[1] = base->undef;
1771 args->out[2] = base->undef;
1772 args->out[3] = base->undef;
1773
1774 switch (spi_shader_col_format) {
1775 case V_028714_SPI_SHADER_ZERO:
1776 args->enabled_channels = 0; /* writemask */
1777 args->target = V_008DFC_SQ_EXP_NULL;
1778 break;
1779
1780 case V_028714_SPI_SHADER_32_R:
1781 args->enabled_channels = 1; /* writemask */
1782 args->out[0] = values[0];
1783 break;
1784
1785 case V_028714_SPI_SHADER_32_GR:
1786 args->enabled_channels = 0x3; /* writemask */
1787 args->out[0] = values[0];
1788 args->out[1] = values[1];
1789 break;
1790
1791 case V_028714_SPI_SHADER_32_AR:
1792 args->enabled_channels = 0x9; /* writemask */
1793 args->out[0] = values[0];
1794 args->out[3] = values[3];
1795 break;
1796
1797 case V_028714_SPI_SHADER_FP16_ABGR:
1798 args->compr = 1; /* COMPR flag */
1799
1800 for (chan = 0; chan < 2; chan++) {
1801 LLVMValueRef pack_args[2] = {
1802 values[2 * chan],
1803 values[2 * chan + 1]
1804 };
1805 LLVMValueRef packed;
1806
1807 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1808 args->out[chan] =
1809 LLVMBuildBitCast(base->gallivm->builder,
1810 packed, ctx->f32, "");
1811 }
1812 break;
1813
1814 case V_028714_SPI_SHADER_UNORM16_ABGR:
1815 for (chan = 0; chan < 4; chan++) {
1816 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1817 val[chan] = LLVMBuildFMul(builder, val[chan],
1818 lp_build_const_float(gallivm, 65535), "");
1819 val[chan] = LLVMBuildFAdd(builder, val[chan],
1820 lp_build_const_float(gallivm, 0.5), "");
1821 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1822 ctx->i32, "");
1823 }
1824
1825 args->compr = 1; /* COMPR flag */
1826 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1827 si_llvm_pack_two_int16(gallivm, val));
1828 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1829 si_llvm_pack_two_int16(gallivm, val+2));
1830 break;
1831
1832 case V_028714_SPI_SHADER_SNORM16_ABGR:
1833 for (chan = 0; chan < 4; chan++) {
1834 /* Clamp between [-1, 1]. */
1835 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1836 values[chan],
1837 lp_build_const_float(gallivm, 1));
1838 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1839 val[chan],
1840 lp_build_const_float(gallivm, -1));
1841 /* Convert to a signed integer in [-32767, 32767]. */
1842 val[chan] = LLVMBuildFMul(builder, val[chan],
1843 lp_build_const_float(gallivm, 32767), "");
1844 /* If positive, add 0.5, else add -0.5. */
1845 val[chan] = LLVMBuildFAdd(builder, val[chan],
1846 LLVMBuildSelect(builder,
1847 LLVMBuildFCmp(builder, LLVMRealOGE,
1848 val[chan], base->zero, ""),
1849 lp_build_const_float(gallivm, 0.5),
1850 lp_build_const_float(gallivm, -0.5), ""), "");
1851 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1852 }
1853
1854 args->compr = 1; /* COMPR flag */
1855 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1856 si_llvm_pack_two_int32_as_int16(gallivm, val));
1857 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1858 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1859 break;
1860
1861 case V_028714_SPI_SHADER_UINT16_ABGR: {
1862 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1863 is_int8 ? 255 : is_int10 ? 1023 : 65535);
1864 LLVMValueRef max_alpha =
1865 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 3);
1866
1867 /* Clamp. */
1868 for (chan = 0; chan < 4; chan++) {
1869 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1870 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1871 val[chan],
1872 chan == 3 ? max_alpha : max_rgb);
1873 }
1874
1875 args->compr = 1; /* COMPR flag */
1876 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1877 si_llvm_pack_two_int16(gallivm, val));
1878 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1879 si_llvm_pack_two_int16(gallivm, val+2));
1880 break;
1881 }
1882
1883 case V_028714_SPI_SHADER_SINT16_ABGR: {
1884 LLVMValueRef max_rgb = lp_build_const_int32(gallivm,
1885 is_int8 ? 127 : is_int10 ? 511 : 32767);
1886 LLVMValueRef min_rgb = lp_build_const_int32(gallivm,
1887 is_int8 ? -128 : is_int10 ? -512 : -32768);
1888 LLVMValueRef max_alpha =
1889 !is_int10 ? max_rgb : lp_build_const_int32(gallivm, 1);
1890 LLVMValueRef min_alpha =
1891 !is_int10 ? min_rgb : lp_build_const_int32(gallivm, -2);
1892
1893 /* Clamp. */
1894 for (chan = 0; chan < 4; chan++) {
1895 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1896 val[chan] = lp_build_emit_llvm_binary(bld_base,
1897 TGSI_OPCODE_IMIN,
1898 val[chan], chan == 3 ? max_alpha : max_rgb);
1899 val[chan] = lp_build_emit_llvm_binary(bld_base,
1900 TGSI_OPCODE_IMAX,
1901 val[chan], chan == 3 ? min_alpha : min_rgb);
1902 }
1903
1904 args->compr = 1; /* COMPR flag */
1905 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1906 si_llvm_pack_two_int32_as_int16(gallivm, val));
1907 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1908 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1909 break;
1910 }
1911
1912 case V_028714_SPI_SHADER_32_ABGR:
1913 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1914 break;
1915 }
1916 }
1917
1918 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1919 LLVMValueRef alpha)
1920 {
1921 struct si_shader_context *ctx = si_shader_context(bld_base);
1922 struct gallivm_state *gallivm = bld_base->base.gallivm;
1923
1924 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1925 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1926 SI_PARAM_ALPHA_REF);
1927
1928 LLVMValueRef alpha_pass =
1929 lp_build_cmp(&bld_base->base,
1930 ctx->shader->key.part.ps.epilog.alpha_func,
1931 alpha, alpha_ref);
1932 LLVMValueRef arg =
1933 lp_build_select(&bld_base->base,
1934 alpha_pass,
1935 lp_build_const_float(gallivm, 1.0f),
1936 lp_build_const_float(gallivm, -1.0f));
1937
1938 ac_build_kill(&ctx->ac, arg);
1939 } else {
1940 ac_build_kill(&ctx->ac, NULL);
1941 }
1942 }
1943
1944 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1945 LLVMValueRef alpha,
1946 unsigned samplemask_param)
1947 {
1948 struct si_shader_context *ctx = si_shader_context(bld_base);
1949 struct gallivm_state *gallivm = bld_base->base.gallivm;
1950 LLVMValueRef coverage;
1951
1952 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1953 coverage = LLVMGetParam(ctx->main_fn,
1954 samplemask_param);
1955 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1956
1957 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1958 ctx->i32,
1959 &coverage, 1, LP_FUNC_ATTR_READNONE);
1960
1961 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1962 ctx->f32, "");
1963
1964 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1965 lp_build_const_float(gallivm,
1966 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1967
1968 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1969 }
1970
1971 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1972 struct ac_export_args *pos, LLVMValueRef *out_elts)
1973 {
1974 struct si_shader_context *ctx = si_shader_context(bld_base);
1975 struct lp_build_context *base = &bld_base->base;
1976 unsigned reg_index;
1977 unsigned chan;
1978 unsigned const_chan;
1979 LLVMValueRef base_elt;
1980 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1981 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1982 SI_VS_CONST_CLIP_PLANES);
1983 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
1984
1985 for (reg_index = 0; reg_index < 2; reg_index ++) {
1986 struct ac_export_args *args = &pos[2 + reg_index];
1987
1988 args->out[0] =
1989 args->out[1] =
1990 args->out[2] =
1991 args->out[3] = lp_build_const_float(base->gallivm, 0.0f);
1992
1993 /* Compute dot products of position and user clip plane vectors */
1994 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1995 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1996 LLVMValueRef addr =
1997 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
1998 const_chan) * 4, 0);
1999 base_elt = buffer_load_const(ctx, const_resource,
2000 addr);
2001 args->out[chan] =
2002 lp_build_add(base, args->out[chan],
2003 lp_build_mul(base, base_elt,
2004 out_elts[const_chan]));
2005 }
2006 }
2007
2008 args->enabled_channels = 0xf;
2009 args->valid_mask = 0;
2010 args->done = 0;
2011 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2012 args->compr = 0;
2013 }
2014 }
2015
2016 static void si_dump_streamout(struct pipe_stream_output_info *so)
2017 {
2018 unsigned i;
2019
2020 if (so->num_outputs)
2021 fprintf(stderr, "STREAMOUT\n");
2022
2023 for (i = 0; i < so->num_outputs; i++) {
2024 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2025 so->output[i].start_component;
2026 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2027 i, so->output[i].output_buffer,
2028 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2029 so->output[i].register_index,
2030 mask & 1 ? "x" : "",
2031 mask & 2 ? "y" : "",
2032 mask & 4 ? "z" : "",
2033 mask & 8 ? "w" : "");
2034 }
2035 }
2036
2037 static void emit_streamout_output(struct si_shader_context *ctx,
2038 LLVMValueRef const *so_buffers,
2039 LLVMValueRef const *so_write_offsets,
2040 struct pipe_stream_output *stream_out,
2041 struct si_shader_output_values *shader_out)
2042 {
2043 struct gallivm_state *gallivm = &ctx->gallivm;
2044 LLVMBuilderRef builder = gallivm->builder;
2045 unsigned buf_idx = stream_out->output_buffer;
2046 unsigned start = stream_out->start_component;
2047 unsigned num_comps = stream_out->num_components;
2048 LLVMValueRef out[4];
2049
2050 assert(num_comps && num_comps <= 4);
2051 if (!num_comps || num_comps > 4)
2052 return;
2053
2054 /* Load the output as int. */
2055 for (int j = 0; j < num_comps; j++) {
2056 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2057
2058 out[j] = LLVMBuildBitCast(builder,
2059 shader_out->values[start + j],
2060 ctx->i32, "");
2061 }
2062
2063 /* Pack the output. */
2064 LLVMValueRef vdata = NULL;
2065
2066 switch (num_comps) {
2067 case 1: /* as i32 */
2068 vdata = out[0];
2069 break;
2070 case 2: /* as v2i32 */
2071 case 3: /* as v4i32 (aligned to 4) */
2072 case 4: /* as v4i32 */
2073 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2074 for (int j = 0; j < num_comps; j++) {
2075 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2076 LLVMConstInt(ctx->i32, j, 0), "");
2077 }
2078 break;
2079 }
2080
2081 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2082 vdata, num_comps,
2083 so_write_offsets[buf_idx],
2084 LLVMConstInt(ctx->i32, 0, 0),
2085 stream_out->dst_offset * 4, 1, 1, true, false);
2086 }
2087
2088 /**
2089 * Write streamout data to buffers for vertex stream @p stream (different
2090 * vertex streams can occur for GS copy shaders).
2091 */
2092 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2093 struct si_shader_output_values *outputs,
2094 unsigned noutput, unsigned stream)
2095 {
2096 struct si_shader_selector *sel = ctx->shader->selector;
2097 struct pipe_stream_output_info *so = &sel->so;
2098 struct gallivm_state *gallivm = &ctx->gallivm;
2099 LLVMBuilderRef builder = gallivm->builder;
2100 int i;
2101 struct lp_build_if_state if_ctx;
2102
2103 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2104 LLVMValueRef so_vtx_count =
2105 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2106
2107 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2108
2109 /* can_emit = tid < so_vtx_count; */
2110 LLVMValueRef can_emit =
2111 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2112
2113 /* Emit the streamout code conditionally. This actually avoids
2114 * out-of-bounds buffer access. The hw tells us via the SGPR
2115 * (so_vtx_count) which threads are allowed to emit streamout data. */
2116 lp_build_if(&if_ctx, gallivm, can_emit);
2117 {
2118 /* The buffer offset is computed as follows:
2119 * ByteOffset = streamout_offset[buffer_id]*4 +
2120 * (streamout_write_index + thread_id)*stride[buffer_id] +
2121 * attrib_offset
2122 */
2123
2124 LLVMValueRef so_write_index =
2125 LLVMGetParam(ctx->main_fn,
2126 ctx->param_streamout_write_index);
2127
2128 /* Compute (streamout_write_index + thread_id). */
2129 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2130
2131 /* Load the descriptor and compute the write offset for each
2132 * enabled buffer. */
2133 LLVMValueRef so_write_offset[4] = {};
2134 LLVMValueRef so_buffers[4];
2135 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2136 SI_PARAM_RW_BUFFERS);
2137
2138 for (i = 0; i < 4; i++) {
2139 if (!so->stride[i])
2140 continue;
2141
2142 LLVMValueRef offset = lp_build_const_int32(gallivm,
2143 SI_VS_STREAMOUT_BUF0 + i);
2144
2145 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2146
2147 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2148 ctx->param_streamout_offset[i]);
2149 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2150
2151 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2152 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2153 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2154 }
2155
2156 /* Write streamout data. */
2157 for (i = 0; i < so->num_outputs; i++) {
2158 unsigned reg = so->output[i].register_index;
2159
2160 if (reg >= noutput)
2161 continue;
2162
2163 if (stream != so->output[i].stream)
2164 continue;
2165
2166 emit_streamout_output(ctx, so_buffers, so_write_offset,
2167 &so->output[i], &outputs[reg]);
2168 }
2169 }
2170 lp_build_endif(&if_ctx);
2171 }
2172
2173
2174 /* Generate export instructions for hardware VS shader stage */
2175 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2176 struct si_shader_output_values *outputs,
2177 unsigned noutput)
2178 {
2179 struct si_shader_context *ctx = si_shader_context(bld_base);
2180 struct si_shader *shader = ctx->shader;
2181 struct lp_build_context *base = &bld_base->base;
2182 struct ac_export_args args, pos_args[4] = {};
2183 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2184 unsigned semantic_name, semantic_index;
2185 unsigned target;
2186 unsigned param_count = 0;
2187 unsigned pos_idx;
2188 int i;
2189
2190 for (i = 0; i < noutput; i++) {
2191 semantic_name = outputs[i].semantic_name;
2192 semantic_index = outputs[i].semantic_index;
2193 bool export_param = true;
2194
2195 switch (semantic_name) {
2196 case TGSI_SEMANTIC_POSITION: /* ignore these */
2197 case TGSI_SEMANTIC_PSIZE:
2198 case TGSI_SEMANTIC_CLIPVERTEX:
2199 case TGSI_SEMANTIC_EDGEFLAG:
2200 break;
2201 case TGSI_SEMANTIC_GENERIC:
2202 case TGSI_SEMANTIC_CLIPDIST:
2203 if (shader->key.opt.hw_vs.kill_outputs &
2204 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2205 export_param = false;
2206 break;
2207 default:
2208 if (shader->key.opt.hw_vs.kill_outputs2 &
2209 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2210 export_param = false;
2211 break;
2212 }
2213
2214 if (outputs[i].vertex_stream[0] != 0 &&
2215 outputs[i].vertex_stream[1] != 0 &&
2216 outputs[i].vertex_stream[2] != 0 &&
2217 outputs[i].vertex_stream[3] != 0)
2218 export_param = false;
2219
2220 handle_semantic:
2221 /* Select the correct target */
2222 switch(semantic_name) {
2223 case TGSI_SEMANTIC_PSIZE:
2224 psize_value = outputs[i].values[0];
2225 continue;
2226 case TGSI_SEMANTIC_EDGEFLAG:
2227 edgeflag_value = outputs[i].values[0];
2228 continue;
2229 case TGSI_SEMANTIC_LAYER:
2230 layer_value = outputs[i].values[0];
2231 semantic_name = TGSI_SEMANTIC_GENERIC;
2232 goto handle_semantic;
2233 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2234 viewport_index_value = outputs[i].values[0];
2235 semantic_name = TGSI_SEMANTIC_GENERIC;
2236 goto handle_semantic;
2237 case TGSI_SEMANTIC_POSITION:
2238 target = V_008DFC_SQ_EXP_POS;
2239 break;
2240 case TGSI_SEMANTIC_CLIPDIST:
2241 if (shader->key.opt.hw_vs.clip_disable) {
2242 semantic_name = TGSI_SEMANTIC_GENERIC;
2243 goto handle_semantic;
2244 }
2245 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2246 break;
2247 case TGSI_SEMANTIC_CLIPVERTEX:
2248 if (shader->key.opt.hw_vs.clip_disable)
2249 continue;
2250 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2251 continue;
2252 case TGSI_SEMANTIC_COLOR:
2253 case TGSI_SEMANTIC_BCOLOR:
2254 case TGSI_SEMANTIC_PRIMID:
2255 case TGSI_SEMANTIC_FOG:
2256 case TGSI_SEMANTIC_TEXCOORD:
2257 case TGSI_SEMANTIC_GENERIC:
2258 if (!export_param)
2259 continue;
2260 target = V_008DFC_SQ_EXP_PARAM + param_count;
2261 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2262 shader->info.vs_output_param_offset[i] = param_count;
2263 param_count++;
2264 break;
2265 default:
2266 target = 0;
2267 fprintf(stderr,
2268 "Warning: SI unhandled vs output type:%d\n",
2269 semantic_name);
2270 }
2271
2272 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2273
2274 if (target >= V_008DFC_SQ_EXP_POS &&
2275 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2276 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2277 &args, sizeof(args));
2278 } else {
2279 ac_build_export(&ctx->ac, &args);
2280 }
2281
2282 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2283 semantic_name = TGSI_SEMANTIC_GENERIC;
2284 goto handle_semantic;
2285 }
2286 }
2287
2288 shader->info.nr_param_exports = param_count;
2289
2290 /* We need to add the position output manually if it's missing. */
2291 if (!pos_args[0].out[0]) {
2292 pos_args[0].enabled_channels = 0xf; /* writemask */
2293 pos_args[0].valid_mask = 0; /* EXEC mask */
2294 pos_args[0].done = 0; /* last export? */
2295 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2296 pos_args[0].compr = 0; /* COMPR flag */
2297 pos_args[0].out[0] = base->zero; /* X */
2298 pos_args[0].out[1] = base->zero; /* Y */
2299 pos_args[0].out[2] = base->zero; /* Z */
2300 pos_args[0].out[3] = base->one; /* W */
2301 }
2302
2303 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2304 if (shader->selector->info.writes_psize ||
2305 shader->selector->info.writes_edgeflag ||
2306 shader->selector->info.writes_viewport_index ||
2307 shader->selector->info.writes_layer) {
2308 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2309 (shader->selector->info.writes_edgeflag << 1) |
2310 (shader->selector->info.writes_layer << 2) |
2311 (shader->selector->info.writes_viewport_index << 3);
2312 pos_args[1].valid_mask = 0; /* EXEC mask */
2313 pos_args[1].done = 0; /* last export? */
2314 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2315 pos_args[1].compr = 0; /* COMPR flag */
2316 pos_args[1].out[0] = base->zero; /* X */
2317 pos_args[1].out[1] = base->zero; /* Y */
2318 pos_args[1].out[2] = base->zero; /* Z */
2319 pos_args[1].out[3] = base->zero; /* W */
2320
2321 if (shader->selector->info.writes_psize)
2322 pos_args[1].out[0] = psize_value;
2323
2324 if (shader->selector->info.writes_edgeflag) {
2325 /* The output is a float, but the hw expects an integer
2326 * with the first bit containing the edge flag. */
2327 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2328 edgeflag_value,
2329 ctx->i32, "");
2330 edgeflag_value = lp_build_min(&bld_base->int_bld,
2331 edgeflag_value,
2332 bld_base->int_bld.one);
2333
2334 /* The LLVM intrinsic expects a float. */
2335 pos_args[1].out[1] = LLVMBuildBitCast(base->gallivm->builder,
2336 edgeflag_value,
2337 ctx->f32, "");
2338 }
2339
2340 if (shader->selector->info.writes_layer)
2341 pos_args[1].out[2] = layer_value;
2342
2343 if (shader->selector->info.writes_viewport_index)
2344 pos_args[1].out[3] = viewport_index_value;
2345 }
2346
2347 for (i = 0; i < 4; i++)
2348 if (pos_args[i].out[0])
2349 shader->info.nr_pos_exports++;
2350
2351 pos_idx = 0;
2352 for (i = 0; i < 4; i++) {
2353 if (!pos_args[i].out[0])
2354 continue;
2355
2356 /* Specify the target we are exporting */
2357 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2358
2359 if (pos_idx == shader->info.nr_pos_exports)
2360 /* Specify that this is the last export */
2361 pos_args[i].done = 1;
2362
2363 ac_build_export(&ctx->ac, &pos_args[i]);
2364 }
2365 }
2366
2367 /**
2368 * Forward all outputs from the vertex shader to the TES. This is only used
2369 * for the fixed function TCS.
2370 */
2371 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2372 {
2373 struct si_shader_context *ctx = si_shader_context(bld_base);
2374 struct gallivm_state *gallivm = bld_base->base.gallivm;
2375 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2376 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2377 uint64_t inputs;
2378
2379 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2380
2381 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2382 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2383 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2384
2385 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2386
2387 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2388 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2389 lds_vertex_stride, "");
2390 lds_base = get_tcs_in_current_patch_offset(ctx);
2391 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2392
2393 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2394 while (inputs) {
2395 unsigned i = u_bit_scan64(&inputs);
2396
2397 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2398 lp_build_const_int32(gallivm, 4 * i),
2399 "");
2400
2401 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2402 get_rel_patch_id(ctx),
2403 invocation_id,
2404 lp_build_const_int32(gallivm, i));
2405
2406 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2407 lds_ptr);
2408
2409 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2410 buffer_offset, 0, 1, 0, true, false);
2411 }
2412 }
2413
2414 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2415 LLVMValueRef rel_patch_id,
2416 LLVMValueRef invocation_id,
2417 LLVMValueRef tcs_out_current_patch_data_offset)
2418 {
2419 struct si_shader_context *ctx = si_shader_context(bld_base);
2420 struct gallivm_state *gallivm = bld_base->base.gallivm;
2421 struct si_shader *shader = ctx->shader;
2422 unsigned tess_inner_index, tess_outer_index;
2423 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2424 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2425 unsigned stride, outer_comps, inner_comps, i;
2426 struct lp_build_if_state if_ctx, inner_if_ctx;
2427
2428 si_llvm_emit_barrier(NULL, bld_base, NULL);
2429
2430 /* Do this only for invocation 0, because the tess levels are per-patch,
2431 * not per-vertex.
2432 *
2433 * This can't jump, because invocation 0 executes this. It should
2434 * at least mask out the loads and stores for other invocations.
2435 */
2436 lp_build_if(&if_ctx, gallivm,
2437 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2438 invocation_id, bld_base->uint_bld.zero, ""));
2439
2440 /* Determine the layout of one tess factor element in the buffer. */
2441 switch (shader->key.part.tcs.epilog.prim_mode) {
2442 case PIPE_PRIM_LINES:
2443 stride = 2; /* 2 dwords, 1 vec2 store */
2444 outer_comps = 2;
2445 inner_comps = 0;
2446 break;
2447 case PIPE_PRIM_TRIANGLES:
2448 stride = 4; /* 4 dwords, 1 vec4 store */
2449 outer_comps = 3;
2450 inner_comps = 1;
2451 break;
2452 case PIPE_PRIM_QUADS:
2453 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2454 outer_comps = 4;
2455 inner_comps = 2;
2456 break;
2457 default:
2458 assert(0);
2459 return;
2460 }
2461
2462 /* Load tess_inner and tess_outer from LDS.
2463 * Any invocation can write them, so we can't get them from a temporary.
2464 */
2465 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2466 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2467
2468 lds_base = tcs_out_current_patch_data_offset;
2469 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2470 lp_build_const_int32(gallivm,
2471 tess_inner_index * 4), "");
2472 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2473 lp_build_const_int32(gallivm,
2474 tess_outer_index * 4), "");
2475
2476 for (i = 0; i < 4; i++) {
2477 inner[i] = LLVMGetUndef(ctx->i32);
2478 outer[i] = LLVMGetUndef(ctx->i32);
2479 }
2480
2481 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2482 /* For isolines, the hardware expects tess factors in the
2483 * reverse order from what GLSL / TGSI specify.
2484 */
2485 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2486 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2487 } else {
2488 for (i = 0; i < outer_comps; i++) {
2489 outer[i] = out[i] =
2490 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2491 }
2492 for (i = 0; i < inner_comps; i++) {
2493 inner[i] = out[outer_comps+i] =
2494 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2495 }
2496 }
2497
2498 /* Convert the outputs to vectors for stores. */
2499 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2500 vec1 = NULL;
2501
2502 if (stride > 4)
2503 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2504
2505 /* Get the buffer. */
2506 rw_buffers = LLVMGetParam(ctx->main_fn,
2507 SI_PARAM_RW_BUFFERS);
2508 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2509 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2510
2511 /* Get the offset. */
2512 tf_base = LLVMGetParam(ctx->main_fn,
2513 SI_PARAM_TESS_FACTOR_OFFSET);
2514 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2515 lp_build_const_int32(gallivm, 4 * stride), "");
2516
2517 lp_build_if(&inner_if_ctx, gallivm,
2518 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2519 rel_patch_id, bld_base->uint_bld.zero, ""));
2520
2521 /* Store the dynamic HS control word. */
2522 ac_build_buffer_store_dword(&ctx->ac, buffer,
2523 lp_build_const_int32(gallivm, 0x80000000),
2524 1, lp_build_const_int32(gallivm, 0), tf_base,
2525 0, 1, 0, true, false);
2526
2527 lp_build_endif(&inner_if_ctx);
2528
2529 /* Store the tessellation factors. */
2530 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2531 MIN2(stride, 4), byteoffset, tf_base,
2532 4, 1, 0, true, false);
2533 if (vec1)
2534 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2535 stride - 4, byteoffset, tf_base,
2536 20, 1, 0, true, false);
2537
2538 /* Store the tess factors into the offchip buffer if TES reads them. */
2539 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2540 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2541 LLVMValueRef tf_inner_offset;
2542 unsigned param_outer, param_inner;
2543
2544 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2545 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2546 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2547
2548 param_outer = si_shader_io_get_unique_index(
2549 TGSI_SEMANTIC_TESSOUTER, 0);
2550 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2551 LLVMConstInt(ctx->i32, param_outer, 0));
2552
2553 outer_vec = lp_build_gather_values(gallivm, outer,
2554 util_next_power_of_two(outer_comps));
2555
2556 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2557 outer_comps, tf_outer_offset,
2558 base, 0, 1, 0, true, false);
2559 if (inner_comps) {
2560 param_inner = si_shader_io_get_unique_index(
2561 TGSI_SEMANTIC_TESSINNER, 0);
2562 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2563 LLVMConstInt(ctx->i32, param_inner, 0));
2564
2565 inner_vec = inner_comps == 1 ? inner[0] :
2566 lp_build_gather_values(gallivm, inner, inner_comps);
2567 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2568 inner_comps, tf_inner_offset,
2569 base, 0, 1, 0, true, false);
2570 }
2571 }
2572
2573 lp_build_endif(&if_ctx);
2574 }
2575
2576 /* This only writes the tessellation factor levels. */
2577 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2578 {
2579 struct si_shader_context *ctx = si_shader_context(bld_base);
2580 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2581 LLVMValueRef offchip_soffset, offchip_layout;
2582
2583 si_copy_tcs_inputs(bld_base);
2584
2585 rel_patch_id = get_rel_patch_id(ctx);
2586 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2587 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2588
2589 /* Return epilog parameters from this function. */
2590 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2591 LLVMValueRef ret = ctx->return_value;
2592 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2593 unsigned vgpr;
2594
2595 /* RW_BUFFERS pointer */
2596 rw_buffers = LLVMGetParam(ctx->main_fn,
2597 SI_PARAM_RW_BUFFERS);
2598 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2599 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2600 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2601 bld_base->uint_bld.zero, "");
2602 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2603 bld_base->uint_bld.one, "");
2604 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2605 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2606
2607 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2608 offchip_layout = LLVMGetParam(ctx->main_fn,
2609 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2610 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2611 tf_soffset = LLVMGetParam(ctx->main_fn,
2612 SI_PARAM_TESS_FACTOR_OFFSET);
2613 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2614 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2615 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2616 SI_TCS_NUM_USER_SGPR, "");
2617 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2618 SI_TCS_NUM_USER_SGPR + 1, "");
2619
2620 /* VGPRs */
2621 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2622 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2623 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2624
2625 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2626 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2627 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2628 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2629 ctx->return_value = ret;
2630 }
2631
2632 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2633 {
2634 struct si_shader_context *ctx = si_shader_context(bld_base);
2635 struct si_shader *shader = ctx->shader;
2636 struct tgsi_shader_info *info = &shader->selector->info;
2637 struct gallivm_state *gallivm = bld_base->base.gallivm;
2638 unsigned i, chan;
2639 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2640 ctx->param_rel_auto_id);
2641 LLVMValueRef vertex_dw_stride =
2642 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2643 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2644 vertex_dw_stride, "");
2645
2646 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2647 * its inputs from it. */
2648 for (i = 0; i < info->num_outputs; i++) {
2649 LLVMValueRef *out_ptr = ctx->outputs[i];
2650 unsigned name = info->output_semantic_name[i];
2651 unsigned index = info->output_semantic_index[i];
2652 int param = si_shader_io_get_unique_index(name, index);
2653 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2654 lp_build_const_int32(gallivm, param * 4), "");
2655
2656 for (chan = 0; chan < 4; chan++) {
2657 lds_store(bld_base, chan, dw_addr,
2658 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2659 }
2660 }
2661 }
2662
2663 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2664 {
2665 struct si_shader_context *ctx = si_shader_context(bld_base);
2666 struct gallivm_state *gallivm = bld_base->base.gallivm;
2667 struct si_shader *es = ctx->shader;
2668 struct tgsi_shader_info *info = &es->selector->info;
2669 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2670 ctx->param_es2gs_offset);
2671 unsigned chan;
2672 int i;
2673
2674 for (i = 0; i < info->num_outputs; i++) {
2675 LLVMValueRef *out_ptr = ctx->outputs[i];
2676 int param_index;
2677
2678 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2679 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2680 continue;
2681
2682 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2683 info->output_semantic_index[i]);
2684
2685 for (chan = 0; chan < 4; chan++) {
2686 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2687 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2688
2689 ac_build_buffer_store_dword(&ctx->ac,
2690 ctx->esgs_ring,
2691 out_val, 1, NULL, soffset,
2692 (4 * param_index + chan) * 4,
2693 1, 1, true, true);
2694 }
2695 }
2696 }
2697
2698 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2699 {
2700 struct si_shader_context *ctx = si_shader_context(bld_base);
2701
2702 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2703 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2704 }
2705
2706 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2707 {
2708 struct si_shader_context *ctx = si_shader_context(bld_base);
2709 struct gallivm_state *gallivm = bld_base->base.gallivm;
2710 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2711 struct si_shader_output_values *outputs = NULL;
2712 int i,j;
2713
2714 assert(!ctx->shader->is_gs_copy_shader);
2715
2716 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2717
2718 /* Vertex color clamping.
2719 *
2720 * This uses a state constant loaded in a user data SGPR and
2721 * an IF statement is added that clamps all colors if the constant
2722 * is true.
2723 */
2724 if (ctx->type == PIPE_SHADER_VERTEX) {
2725 struct lp_build_if_state if_ctx;
2726 LLVMValueRef cond = NULL;
2727 LLVMValueRef addr, val;
2728
2729 for (i = 0; i < info->num_outputs; i++) {
2730 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2731 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2732 continue;
2733
2734 /* We've found a color. */
2735 if (!cond) {
2736 /* The state is in the first bit of the user SGPR. */
2737 cond = LLVMGetParam(ctx->main_fn,
2738 SI_PARAM_VS_STATE_BITS);
2739 cond = LLVMBuildTrunc(gallivm->builder, cond,
2740 ctx->i1, "");
2741 lp_build_if(&if_ctx, gallivm, cond);
2742 }
2743
2744 for (j = 0; j < 4; j++) {
2745 addr = ctx->outputs[i][j];
2746 val = LLVMBuildLoad(gallivm->builder, addr, "");
2747 val = ac_build_clamp(&ctx->ac, val);
2748 LLVMBuildStore(gallivm->builder, val, addr);
2749 }
2750 }
2751
2752 if (cond)
2753 lp_build_endif(&if_ctx);
2754 }
2755
2756 for (i = 0; i < info->num_outputs; i++) {
2757 outputs[i].semantic_name = info->output_semantic_name[i];
2758 outputs[i].semantic_index = info->output_semantic_index[i];
2759
2760 for (j = 0; j < 4; j++) {
2761 outputs[i].values[j] =
2762 LLVMBuildLoad(gallivm->builder,
2763 ctx->outputs[i][j],
2764 "");
2765 outputs[i].vertex_stream[j] =
2766 (info->output_streams[i] >> (2 * j)) & 3;
2767 }
2768
2769 }
2770
2771 /* Return the primitive ID from the LLVM function. */
2772 ctx->return_value =
2773 LLVMBuildInsertValue(gallivm->builder,
2774 ctx->return_value,
2775 bitcast(bld_base, TGSI_TYPE_FLOAT,
2776 get_primitive_id(bld_base, 0)),
2777 VS_EPILOG_PRIMID_LOC, "");
2778
2779 if (ctx->shader->selector->so.num_outputs)
2780 si_llvm_emit_streamout(ctx, outputs, i, 0);
2781 si_llvm_export_vs(bld_base, outputs, i);
2782 FREE(outputs);
2783 }
2784
2785 struct si_ps_exports {
2786 unsigned num;
2787 struct ac_export_args args[10];
2788 };
2789
2790 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2791 bool writes_samplemask)
2792 {
2793 if (writes_z) {
2794 /* Z needs 32 bits. */
2795 if (writes_samplemask)
2796 return V_028710_SPI_SHADER_32_ABGR;
2797 else if (writes_stencil)
2798 return V_028710_SPI_SHADER_32_GR;
2799 else
2800 return V_028710_SPI_SHADER_32_R;
2801 } else if (writes_stencil || writes_samplemask) {
2802 /* Both stencil and sample mask need only 16 bits. */
2803 return V_028710_SPI_SHADER_UINT16_ABGR;
2804 } else {
2805 return V_028710_SPI_SHADER_ZERO;
2806 }
2807 }
2808
2809 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2810 LLVMValueRef depth, LLVMValueRef stencil,
2811 LLVMValueRef samplemask, struct si_ps_exports *exp)
2812 {
2813 struct si_shader_context *ctx = si_shader_context(bld_base);
2814 struct lp_build_context *base = &bld_base->base;
2815 struct ac_export_args args;
2816 unsigned mask = 0;
2817 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2818 stencil != NULL,
2819 samplemask != NULL);
2820
2821 assert(depth || stencil || samplemask);
2822
2823 args.valid_mask = 1; /* whether the EXEC mask is valid */
2824 args.done = 1; /* DONE bit */
2825
2826 /* Specify the target we are exporting */
2827 args.target = V_008DFC_SQ_EXP_MRTZ;
2828
2829 args.compr = 0; /* COMP flag */
2830 args.out[0] = base->undef; /* R, depth */
2831 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2832 args.out[2] = base->undef; /* B, sample mask */
2833 args.out[3] = base->undef; /* A, alpha to mask */
2834
2835 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2836 assert(!depth);
2837 args.compr = 1; /* COMPR flag */
2838
2839 if (stencil) {
2840 /* Stencil should be in X[23:16]. */
2841 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2842 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2843 LLVMConstInt(ctx->i32, 16, 0), "");
2844 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2845 mask |= 0x3;
2846 }
2847 if (samplemask) {
2848 /* SampleMask should be in Y[15:0]. */
2849 args.out[1] = samplemask;
2850 mask |= 0xc;
2851 }
2852 } else {
2853 if (depth) {
2854 args.out[0] = depth;
2855 mask |= 0x1;
2856 }
2857 if (stencil) {
2858 args.out[1] = stencil;
2859 mask |= 0x2;
2860 }
2861 if (samplemask) {
2862 args.out[2] = samplemask;
2863 mask |= 0x4;
2864 }
2865 }
2866
2867 /* SI (except OLAND and HAINAN) has a bug that it only looks
2868 * at the X writemask component. */
2869 if (ctx->screen->b.chip_class == SI &&
2870 ctx->screen->b.family != CHIP_OLAND &&
2871 ctx->screen->b.family != CHIP_HAINAN)
2872 mask |= 0x1;
2873
2874 /* Specify which components to enable */
2875 args.enabled_channels = mask;
2876
2877 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2878 }
2879
2880 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2881 LLVMValueRef *color, unsigned index,
2882 unsigned samplemask_param,
2883 bool is_last, struct si_ps_exports *exp)
2884 {
2885 struct si_shader_context *ctx = si_shader_context(bld_base);
2886 struct lp_build_context *base = &bld_base->base;
2887 int i;
2888
2889 /* Clamp color */
2890 if (ctx->shader->key.part.ps.epilog.clamp_color)
2891 for (i = 0; i < 4; i++)
2892 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2893
2894 /* Alpha to one */
2895 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2896 color[3] = base->one;
2897
2898 /* Alpha test */
2899 if (index == 0 &&
2900 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2901 si_alpha_test(bld_base, color[3]);
2902
2903 /* Line & polygon smoothing */
2904 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2905 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2906 samplemask_param);
2907
2908 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2909 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2910 struct ac_export_args args[8];
2911 int c, last = -1;
2912
2913 /* Get the export arguments, also find out what the last one is. */
2914 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2915 si_llvm_init_export_args(bld_base, color,
2916 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2917 if (args[c].enabled_channels)
2918 last = c;
2919 }
2920
2921 /* Emit all exports. */
2922 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2923 if (is_last && last == c) {
2924 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2925 args[c].done = 1; /* DONE bit */
2926 } else if (!args[c].enabled_channels)
2927 continue; /* unnecessary NULL export */
2928
2929 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2930 }
2931 } else {
2932 struct ac_export_args args;
2933
2934 /* Export */
2935 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2936 &args);
2937 if (is_last) {
2938 args.valid_mask = 1; /* whether the EXEC mask is valid */
2939 args.done = 1; /* DONE bit */
2940 } else if (!args.enabled_channels)
2941 return; /* unnecessary NULL export */
2942
2943 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2944 }
2945 }
2946
2947 static void si_emit_ps_exports(struct si_shader_context *ctx,
2948 struct si_ps_exports *exp)
2949 {
2950 for (unsigned i = 0; i < exp->num; i++)
2951 ac_build_export(&ctx->ac, &exp->args[i]);
2952 }
2953
2954 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2955 {
2956 struct si_shader_context *ctx = si_shader_context(bld_base);
2957 struct lp_build_context *base = &bld_base->base;
2958 struct ac_export_args args;
2959
2960 args.enabled_channels = 0x0; /* enabled channels */
2961 args.valid_mask = 1; /* whether the EXEC mask is valid */
2962 args.done = 1; /* DONE bit */
2963 args.target = V_008DFC_SQ_EXP_NULL;
2964 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
2965 args.out[0] = base->undef; /* R */
2966 args.out[1] = base->undef; /* G */
2967 args.out[2] = base->undef; /* B */
2968 args.out[3] = base->undef; /* A */
2969
2970 ac_build_export(&ctx->ac, &args);
2971 }
2972
2973 /**
2974 * Return PS outputs in this order:
2975 *
2976 * v[0:3] = color0.xyzw
2977 * v[4:7] = color1.xyzw
2978 * ...
2979 * vN+0 = Depth
2980 * vN+1 = Stencil
2981 * vN+2 = SampleMask
2982 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2983 *
2984 * The alpha-ref SGPR is returned via its original location.
2985 */
2986 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2987 {
2988 struct si_shader_context *ctx = si_shader_context(bld_base);
2989 struct si_shader *shader = ctx->shader;
2990 struct lp_build_context *base = &bld_base->base;
2991 struct tgsi_shader_info *info = &shader->selector->info;
2992 LLVMBuilderRef builder = base->gallivm->builder;
2993 unsigned i, j, first_vgpr, vgpr;
2994
2995 LLVMValueRef color[8][4] = {};
2996 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2997 LLVMValueRef ret;
2998
2999 /* Read the output values. */
3000 for (i = 0; i < info->num_outputs; i++) {
3001 unsigned semantic_name = info->output_semantic_name[i];
3002 unsigned semantic_index = info->output_semantic_index[i];
3003
3004 switch (semantic_name) {
3005 case TGSI_SEMANTIC_COLOR:
3006 assert(semantic_index < 8);
3007 for (j = 0; j < 4; j++) {
3008 LLVMValueRef ptr = ctx->outputs[i][j];
3009 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3010 color[semantic_index][j] = result;
3011 }
3012 break;
3013 case TGSI_SEMANTIC_POSITION:
3014 depth = LLVMBuildLoad(builder,
3015 ctx->outputs[i][2], "");
3016 break;
3017 case TGSI_SEMANTIC_STENCIL:
3018 stencil = LLVMBuildLoad(builder,
3019 ctx->outputs[i][1], "");
3020 break;
3021 case TGSI_SEMANTIC_SAMPLEMASK:
3022 samplemask = LLVMBuildLoad(builder,
3023 ctx->outputs[i][0], "");
3024 break;
3025 default:
3026 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3027 semantic_name);
3028 }
3029 }
3030
3031 /* Fill the return structure. */
3032 ret = ctx->return_value;
3033
3034 /* Set SGPRs. */
3035 ret = LLVMBuildInsertValue(builder, ret,
3036 bitcast(bld_base, TGSI_TYPE_SIGNED,
3037 LLVMGetParam(ctx->main_fn,
3038 SI_PARAM_ALPHA_REF)),
3039 SI_SGPR_ALPHA_REF, "");
3040
3041 /* Set VGPRs */
3042 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3043 for (i = 0; i < ARRAY_SIZE(color); i++) {
3044 if (!color[i][0])
3045 continue;
3046
3047 for (j = 0; j < 4; j++)
3048 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3049 }
3050 if (depth)
3051 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3052 if (stencil)
3053 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3054 if (samplemask)
3055 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3056
3057 /* Add the input sample mask for smoothing at the end. */
3058 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3059 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3060 ret = LLVMBuildInsertValue(builder, ret,
3061 LLVMGetParam(ctx->main_fn,
3062 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3063
3064 ctx->return_value = ret;
3065 }
3066
3067 /**
3068 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3069 * buffer in number of elements and return it as an i32.
3070 */
3071 static LLVMValueRef get_buffer_size(
3072 struct lp_build_tgsi_context *bld_base,
3073 LLVMValueRef descriptor)
3074 {
3075 struct si_shader_context *ctx = si_shader_context(bld_base);
3076 struct gallivm_state *gallivm = bld_base->base.gallivm;
3077 LLVMBuilderRef builder = gallivm->builder;
3078 LLVMValueRef size =
3079 LLVMBuildExtractElement(builder, descriptor,
3080 lp_build_const_int32(gallivm, 2), "");
3081
3082 if (ctx->screen->b.chip_class >= VI) {
3083 /* On VI, the descriptor contains the size in bytes,
3084 * but TXQ must return the size in elements.
3085 * The stride is always non-zero for resources using TXQ.
3086 */
3087 LLVMValueRef stride =
3088 LLVMBuildExtractElement(builder, descriptor,
3089 lp_build_const_int32(gallivm, 1), "");
3090 stride = LLVMBuildLShr(builder, stride,
3091 lp_build_const_int32(gallivm, 16), "");
3092 stride = LLVMBuildAnd(builder, stride,
3093 lp_build_const_int32(gallivm, 0x3FFF), "");
3094
3095 size = LLVMBuildUDiv(builder, size, stride, "");
3096 }
3097
3098 return size;
3099 }
3100
3101 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3102 struct lp_build_tgsi_context *bld_base,
3103 struct lp_build_emit_data *emit_data);
3104
3105 /* Prevent optimizations (at least of memory accesses) across the current
3106 * point in the program by emitting empty inline assembly that is marked as
3107 * having side effects.
3108 */
3109 #if 0 /* unused currently */
3110 static void emit_optimization_barrier(struct si_shader_context *ctx)
3111 {
3112 LLVMBuilderRef builder = ctx->gallivm.builder;
3113 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3114 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3115 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3116 }
3117 #endif
3118
3119 /* Combine these with & instead of |. */
3120 #define NOOP_WAITCNT 0xf7f
3121 #define LGKM_CNT 0x07f
3122 #define VM_CNT 0xf70
3123
3124 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3125 {
3126 struct gallivm_state *gallivm = &ctx->gallivm;
3127 LLVMBuilderRef builder = gallivm->builder;
3128 LLVMValueRef args[1] = {
3129 lp_build_const_int32(gallivm, simm16)
3130 };
3131 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3132 ctx->voidt, args, 1, 0);
3133 }
3134
3135 static void membar_emit(
3136 const struct lp_build_tgsi_action *action,
3137 struct lp_build_tgsi_context *bld_base,
3138 struct lp_build_emit_data *emit_data)
3139 {
3140 struct si_shader_context *ctx = si_shader_context(bld_base);
3141 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3142 unsigned flags = LLVMConstIntGetZExtValue(src0);
3143 unsigned waitcnt = NOOP_WAITCNT;
3144
3145 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3146 waitcnt &= VM_CNT & LGKM_CNT;
3147
3148 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3149 TGSI_MEMBAR_SHADER_BUFFER |
3150 TGSI_MEMBAR_SHADER_IMAGE))
3151 waitcnt &= VM_CNT;
3152
3153 if (flags & TGSI_MEMBAR_SHARED)
3154 waitcnt &= LGKM_CNT;
3155
3156 if (waitcnt != NOOP_WAITCNT)
3157 emit_waitcnt(ctx, waitcnt);
3158 }
3159
3160 static LLVMValueRef
3161 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3162 const struct tgsi_full_src_register *reg)
3163 {
3164 LLVMValueRef index;
3165 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3166 SI_PARAM_SHADER_BUFFERS);
3167
3168 if (!reg->Register.Indirect)
3169 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3170 else
3171 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3172 reg->Register.Index,
3173 SI_NUM_SHADER_BUFFERS);
3174
3175 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3176 }
3177
3178 static bool tgsi_is_array_sampler(unsigned target)
3179 {
3180 return target == TGSI_TEXTURE_1D_ARRAY ||
3181 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3182 target == TGSI_TEXTURE_2D_ARRAY ||
3183 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3184 target == TGSI_TEXTURE_CUBE_ARRAY ||
3185 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3186 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3187 }
3188
3189 static bool tgsi_is_array_image(unsigned target)
3190 {
3191 return target == TGSI_TEXTURE_3D ||
3192 target == TGSI_TEXTURE_CUBE ||
3193 target == TGSI_TEXTURE_1D_ARRAY ||
3194 target == TGSI_TEXTURE_2D_ARRAY ||
3195 target == TGSI_TEXTURE_CUBE_ARRAY ||
3196 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3197 }
3198
3199 /**
3200 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3201 *
3202 * At least on Tonga, executing image stores on images with DCC enabled and
3203 * non-trivial can eventually lead to lockups. This can occur when an
3204 * application binds an image as read-only but then uses a shader that writes
3205 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3206 * program termination) in this case, but it doesn't cost much to be a bit
3207 * nicer: disabling DCC in the shader still leads to undefined results but
3208 * avoids the lockup.
3209 */
3210 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3211 LLVMValueRef rsrc)
3212 {
3213 if (ctx->screen->b.chip_class <= CIK) {
3214 return rsrc;
3215 } else {
3216 LLVMBuilderRef builder = ctx->gallivm.builder;
3217 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3218 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3219 LLVMValueRef tmp;
3220
3221 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3222 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3223 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3224 }
3225 }
3226
3227 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3228 {
3229 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3230 CONST_ADDR_SPACE);
3231 }
3232
3233 /**
3234 * Load the resource descriptor for \p image.
3235 */
3236 static void
3237 image_fetch_rsrc(
3238 struct lp_build_tgsi_context *bld_base,
3239 const struct tgsi_full_src_register *image,
3240 bool is_store, unsigned target,
3241 LLVMValueRef *rsrc)
3242 {
3243 struct si_shader_context *ctx = si_shader_context(bld_base);
3244 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3245 SI_PARAM_IMAGES);
3246 LLVMValueRef index, tmp;
3247 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3248
3249 assert(image->Register.File == TGSI_FILE_IMAGE);
3250
3251 if (!image->Register.Indirect) {
3252 const struct tgsi_shader_info *info = bld_base->info;
3253 unsigned images_writemask = info->images_store |
3254 info->images_atomic;
3255
3256 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3257
3258 if (images_writemask & (1 << image->Register.Index) &&
3259 target != TGSI_TEXTURE_BUFFER)
3260 dcc_off = true;
3261 } else {
3262 /* From the GL_ARB_shader_image_load_store extension spec:
3263 *
3264 * If a shader performs an image load, store, or atomic
3265 * operation using an image variable declared as an array,
3266 * and if the index used to select an individual element is
3267 * negative or greater than or equal to the size of the
3268 * array, the results of the operation are undefined but may
3269 * not lead to termination.
3270 */
3271 index = get_bounded_indirect_index(ctx, &image->Indirect,
3272 image->Register.Index,
3273 SI_NUM_IMAGES);
3274 }
3275
3276 if (target == TGSI_TEXTURE_BUFFER) {
3277 LLVMBuilderRef builder = ctx->gallivm.builder;
3278
3279 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3280 const_array(ctx->v4i32, 0), "");
3281 index = LLVMBuildMul(builder, index,
3282 LLVMConstInt(ctx->i32, 2, 0), "");
3283 index = LLVMBuildAdd(builder, index,
3284 LLVMConstInt(ctx->i32, 1, 0), "");
3285 *rsrc = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3286 return;
3287 }
3288
3289 tmp = ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3290 if (dcc_off)
3291 tmp = force_dcc_off(ctx, tmp);
3292 *rsrc = tmp;
3293 }
3294
3295 static LLVMValueRef image_fetch_coords(
3296 struct lp_build_tgsi_context *bld_base,
3297 const struct tgsi_full_instruction *inst,
3298 unsigned src)
3299 {
3300 struct gallivm_state *gallivm = bld_base->base.gallivm;
3301 LLVMBuilderRef builder = gallivm->builder;
3302 unsigned target = inst->Memory.Texture;
3303 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3304 LLVMValueRef coords[4];
3305 LLVMValueRef tmp;
3306 int chan;
3307
3308 for (chan = 0; chan < num_coords; ++chan) {
3309 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3310 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3311 coords[chan] = tmp;
3312 }
3313
3314 if (num_coords == 1)
3315 return coords[0];
3316
3317 if (num_coords == 3) {
3318 /* LLVM has difficulties lowering 3-element vectors. */
3319 coords[3] = bld_base->uint_bld.undef;
3320 num_coords = 4;
3321 }
3322
3323 return lp_build_gather_values(gallivm, coords, num_coords);
3324 }
3325
3326 /**
3327 * Append the extra mode bits that are used by image load and store.
3328 */
3329 static void image_append_args(
3330 struct si_shader_context *ctx,
3331 struct lp_build_emit_data * emit_data,
3332 unsigned target,
3333 bool atomic,
3334 bool force_glc)
3335 {
3336 const struct tgsi_full_instruction *inst = emit_data->inst;
3337 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3338 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3339 LLVMValueRef r128 = i1false;
3340 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3341 LLVMValueRef glc =
3342 force_glc ||
3343 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3344 i1true : i1false;
3345 LLVMValueRef slc = i1false;
3346 LLVMValueRef lwe = i1false;
3347
3348 if (atomic || (HAVE_LLVM <= 0x0309)) {
3349 emit_data->args[emit_data->arg_count++] = r128;
3350 emit_data->args[emit_data->arg_count++] = da;
3351 if (!atomic) {
3352 emit_data->args[emit_data->arg_count++] = glc;
3353 }
3354 emit_data->args[emit_data->arg_count++] = slc;
3355 return;
3356 }
3357
3358 /* HAVE_LLVM >= 0x0400 */
3359 emit_data->args[emit_data->arg_count++] = glc;
3360 emit_data->args[emit_data->arg_count++] = slc;
3361 emit_data->args[emit_data->arg_count++] = lwe;
3362 emit_data->args[emit_data->arg_count++] = da;
3363 }
3364
3365 /**
3366 * Append the resource and indexing arguments for buffer intrinsics.
3367 *
3368 * \param rsrc the v4i32 buffer resource
3369 * \param index index into the buffer (stride-based)
3370 * \param offset byte offset into the buffer
3371 */
3372 static void buffer_append_args(
3373 struct si_shader_context *ctx,
3374 struct lp_build_emit_data *emit_data,
3375 LLVMValueRef rsrc,
3376 LLVMValueRef index,
3377 LLVMValueRef offset,
3378 bool atomic,
3379 bool force_glc)
3380 {
3381 const struct tgsi_full_instruction *inst = emit_data->inst;
3382 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3383 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3384
3385 emit_data->args[emit_data->arg_count++] = rsrc;
3386 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3387 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3388 if (!atomic) {
3389 emit_data->args[emit_data->arg_count++] =
3390 force_glc ||
3391 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3392 i1true : i1false; /* glc */
3393 }
3394 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3395 }
3396
3397 static void load_fetch_args(
3398 struct lp_build_tgsi_context * bld_base,
3399 struct lp_build_emit_data * emit_data)
3400 {
3401 struct si_shader_context *ctx = si_shader_context(bld_base);
3402 struct gallivm_state *gallivm = bld_base->base.gallivm;
3403 const struct tgsi_full_instruction * inst = emit_data->inst;
3404 unsigned target = inst->Memory.Texture;
3405 LLVMValueRef rsrc;
3406
3407 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3408
3409 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3410 LLVMBuilderRef builder = gallivm->builder;
3411 LLVMValueRef offset;
3412 LLVMValueRef tmp;
3413
3414 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3415
3416 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3417 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3418
3419 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3420 offset, false, false);
3421 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3422 LLVMValueRef coords;
3423
3424 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3425 coords = image_fetch_coords(bld_base, inst, 1);
3426
3427 if (target == TGSI_TEXTURE_BUFFER) {
3428 buffer_append_args(ctx, emit_data, rsrc, coords,
3429 bld_base->uint_bld.zero, false, false);
3430 } else {
3431 emit_data->args[0] = coords;
3432 emit_data->args[1] = rsrc;
3433 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3434 emit_data->arg_count = 3;
3435
3436 image_append_args(ctx, emit_data, target, false, false);
3437 }
3438 }
3439 }
3440
3441 static unsigned get_load_intr_attribs(bool readonly_memory)
3442 {
3443 /* READNONE means writes can't affect it, while READONLY means that
3444 * writes can affect it. */
3445 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3446 LP_FUNC_ATTR_READNONE :
3447 LP_FUNC_ATTR_READONLY;
3448 }
3449
3450 static unsigned get_store_intr_attribs(bool writeonly_memory)
3451 {
3452 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3453 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3454 LP_FUNC_ATTR_WRITEONLY;
3455 }
3456
3457 static void load_emit_buffer(struct si_shader_context *ctx,
3458 struct lp_build_emit_data *emit_data,
3459 bool readonly_memory)
3460 {
3461 const struct tgsi_full_instruction *inst = emit_data->inst;
3462 struct gallivm_state *gallivm = &ctx->gallivm;
3463 LLVMBuilderRef builder = gallivm->builder;
3464 uint writemask = inst->Dst[0].Register.WriteMask;
3465 uint count = util_last_bit(writemask);
3466 const char *intrinsic_name;
3467 LLVMTypeRef dst_type;
3468
3469 switch (count) {
3470 case 1:
3471 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3472 dst_type = ctx->f32;
3473 break;
3474 case 2:
3475 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3476 dst_type = LLVMVectorType(ctx->f32, 2);
3477 break;
3478 default: // 3 & 4
3479 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3480 dst_type = ctx->v4f32;
3481 count = 4;
3482 }
3483
3484 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3485 builder, intrinsic_name, dst_type,
3486 emit_data->args, emit_data->arg_count,
3487 get_load_intr_attribs(readonly_memory));
3488 }
3489
3490 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3491 const struct tgsi_full_instruction *inst,
3492 LLVMTypeRef type, int arg)
3493 {
3494 struct gallivm_state *gallivm = &ctx->gallivm;
3495 LLVMBuilderRef builder = gallivm->builder;
3496 LLVMValueRef offset, ptr;
3497 int addr_space;
3498
3499 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3500 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3501
3502 ptr = ctx->shared_memory;
3503 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3504 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3505 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3506
3507 return ptr;
3508 }
3509
3510 static void load_emit_memory(
3511 struct si_shader_context *ctx,
3512 struct lp_build_emit_data *emit_data)
3513 {
3514 const struct tgsi_full_instruction *inst = emit_data->inst;
3515 struct lp_build_context *base = &ctx->bld_base.base;
3516 struct gallivm_state *gallivm = &ctx->gallivm;
3517 LLVMBuilderRef builder = gallivm->builder;
3518 unsigned writemask = inst->Dst[0].Register.WriteMask;
3519 LLVMValueRef channels[4], ptr, derived_ptr, index;
3520 int chan;
3521
3522 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3523
3524 for (chan = 0; chan < 4; ++chan) {
3525 if (!(writemask & (1 << chan))) {
3526 channels[chan] = LLVMGetUndef(base->elem_type);
3527 continue;
3528 }
3529
3530 index = lp_build_const_int32(gallivm, chan);
3531 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3532 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3533 }
3534 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3535 }
3536
3537 /**
3538 * Return true if the memory accessed by a LOAD or STORE instruction is
3539 * read-only or write-only, respectively.
3540 *
3541 * \param shader_buffers_reverse_access_mask
3542 * For LOAD, set this to (store | atomic) slot usage in the shader.
3543 * For STORE, set this to (load | atomic) slot usage in the shader.
3544 * \param images_reverse_access_mask Same as above, but for images.
3545 */
3546 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3547 const struct tgsi_shader_info *info,
3548 unsigned shader_buffers_reverse_access_mask,
3549 unsigned images_reverse_access_mask)
3550 {
3551 /* RESTRICT means NOALIAS.
3552 * If there are no writes, we can assume the accessed memory is read-only.
3553 * If there are no reads, we can assume the accessed memory is write-only.
3554 */
3555 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3556 unsigned reverse_access_mask;
3557
3558 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3559 reverse_access_mask = shader_buffers_reverse_access_mask;
3560 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3561 reverse_access_mask = info->images_buffers &
3562 images_reverse_access_mask;
3563 } else {
3564 reverse_access_mask = ~info->images_buffers &
3565 images_reverse_access_mask;
3566 }
3567
3568 if (inst->Src[0].Register.Indirect) {
3569 if (!reverse_access_mask)
3570 return true;
3571 } else {
3572 if (!(reverse_access_mask &
3573 (1u << inst->Src[0].Register.Index)))
3574 return true;
3575 }
3576 }
3577
3578 /* If there are no buffer writes (for both shader buffers & image
3579 * buffers), it implies that buffer memory is read-only.
3580 * If there are no buffer reads (for both shader buffers & image
3581 * buffers), it implies that buffer memory is write-only.
3582 *
3583 * Same for the case when there are no writes/reads for non-buffer
3584 * images.
3585 */
3586 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3587 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3588 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3589 if (!shader_buffers_reverse_access_mask &&
3590 !(info->images_buffers & images_reverse_access_mask))
3591 return true;
3592 } else {
3593 if (!(~info->images_buffers & images_reverse_access_mask))
3594 return true;
3595 }
3596 return false;
3597 }
3598
3599 static void load_emit(
3600 const struct lp_build_tgsi_action *action,
3601 struct lp_build_tgsi_context *bld_base,
3602 struct lp_build_emit_data *emit_data)
3603 {
3604 struct si_shader_context *ctx = si_shader_context(bld_base);
3605 struct gallivm_state *gallivm = bld_base->base.gallivm;
3606 LLVMBuilderRef builder = gallivm->builder;
3607 const struct tgsi_full_instruction * inst = emit_data->inst;
3608 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3609 char intrinsic_name[64];
3610 bool readonly_memory = false;
3611
3612 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3613 load_emit_memory(ctx, emit_data);
3614 return;
3615 }
3616
3617 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3618 emit_waitcnt(ctx, VM_CNT);
3619
3620 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3621 is_oneway_access_only(inst, info,
3622 info->shader_buffers_store |
3623 info->shader_buffers_atomic,
3624 info->images_store |
3625 info->images_atomic);
3626
3627 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3628 load_emit_buffer(ctx, emit_data, readonly_memory);
3629 return;
3630 }
3631
3632 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3633 emit_data->output[emit_data->chan] =
3634 lp_build_intrinsic(
3635 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3636 emit_data->args, emit_data->arg_count,
3637 get_load_intr_attribs(readonly_memory));
3638 } else {
3639 ac_get_image_intr_name("llvm.amdgcn.image.load",
3640 emit_data->dst_type, /* vdata */
3641 LLVMTypeOf(emit_data->args[0]), /* coords */
3642 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3643 intrinsic_name, sizeof(intrinsic_name));
3644
3645 emit_data->output[emit_data->chan] =
3646 lp_build_intrinsic(
3647 builder, intrinsic_name, emit_data->dst_type,
3648 emit_data->args, emit_data->arg_count,
3649 get_load_intr_attribs(readonly_memory));
3650 }
3651 }
3652
3653 static void store_fetch_args(
3654 struct lp_build_tgsi_context * bld_base,
3655 struct lp_build_emit_data * emit_data)
3656 {
3657 struct si_shader_context *ctx = si_shader_context(bld_base);
3658 struct gallivm_state *gallivm = bld_base->base.gallivm;
3659 LLVMBuilderRef builder = gallivm->builder;
3660 const struct tgsi_full_instruction * inst = emit_data->inst;
3661 struct tgsi_full_src_register memory;
3662 LLVMValueRef chans[4];
3663 LLVMValueRef data;
3664 LLVMValueRef rsrc;
3665 unsigned chan;
3666
3667 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3668
3669 for (chan = 0; chan < 4; ++chan) {
3670 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3671 }
3672 data = lp_build_gather_values(gallivm, chans, 4);
3673
3674 emit_data->args[emit_data->arg_count++] = data;
3675
3676 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3677
3678 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3679 LLVMValueRef offset;
3680 LLVMValueRef tmp;
3681
3682 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3683
3684 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3685 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3686
3687 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3688 offset, false, false);
3689 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3690 unsigned target = inst->Memory.Texture;
3691 LLVMValueRef coords;
3692
3693 /* 8bit/16bit TC L1 write corruption bug on SI.
3694 * All store opcodes not aligned to a dword are affected.
3695 *
3696 * The only way to get unaligned stores in radeonsi is through
3697 * shader images.
3698 */
3699 bool force_glc = ctx->screen->b.chip_class == SI;
3700
3701 coords = image_fetch_coords(bld_base, inst, 0);
3702
3703 if (target == TGSI_TEXTURE_BUFFER) {
3704 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3705 buffer_append_args(ctx, emit_data, rsrc, coords,
3706 bld_base->uint_bld.zero, false, force_glc);
3707 } else {
3708 emit_data->args[1] = coords;
3709 image_fetch_rsrc(bld_base, &memory, true, target,
3710 &emit_data->args[2]);
3711 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3712 emit_data->arg_count = 4;
3713
3714 image_append_args(ctx, emit_data, target, false, force_glc);
3715 }
3716 }
3717 }
3718
3719 static void store_emit_buffer(
3720 struct si_shader_context *ctx,
3721 struct lp_build_emit_data *emit_data,
3722 bool writeonly_memory)
3723 {
3724 const struct tgsi_full_instruction *inst = emit_data->inst;
3725 struct gallivm_state *gallivm = &ctx->gallivm;
3726 LLVMBuilderRef builder = gallivm->builder;
3727 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
3728 LLVMValueRef base_data = emit_data->args[0];
3729 LLVMValueRef base_offset = emit_data->args[3];
3730 unsigned writemask = inst->Dst[0].Register.WriteMask;
3731
3732 while (writemask) {
3733 int start, count;
3734 const char *intrinsic_name;
3735 LLVMValueRef data;
3736 LLVMValueRef offset;
3737 LLVMValueRef tmp;
3738
3739 u_bit_scan_consecutive_range(&writemask, &start, &count);
3740
3741 /* Due to an LLVM limitation, split 3-element writes
3742 * into a 2-element and a 1-element write. */
3743 if (count == 3) {
3744 writemask |= 1 << (start + 2);
3745 count = 2;
3746 }
3747
3748 if (count == 4) {
3749 data = base_data;
3750 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3751 } else if (count == 2) {
3752 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3753
3754 tmp = LLVMBuildExtractElement(
3755 builder, base_data,
3756 lp_build_const_int32(gallivm, start), "");
3757 data = LLVMBuildInsertElement(
3758 builder, LLVMGetUndef(v2f32), tmp,
3759 uint_bld->zero, "");
3760
3761 tmp = LLVMBuildExtractElement(
3762 builder, base_data,
3763 lp_build_const_int32(gallivm, start + 1), "");
3764 data = LLVMBuildInsertElement(
3765 builder, data, tmp, uint_bld->one, "");
3766
3767 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3768 } else {
3769 assert(count == 1);
3770 data = LLVMBuildExtractElement(
3771 builder, base_data,
3772 lp_build_const_int32(gallivm, start), "");
3773 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3774 }
3775
3776 offset = base_offset;
3777 if (start != 0) {
3778 offset = LLVMBuildAdd(
3779 builder, offset,
3780 lp_build_const_int32(gallivm, start * 4), "");
3781 }
3782
3783 emit_data->args[0] = data;
3784 emit_data->args[3] = offset;
3785
3786 lp_build_intrinsic(
3787 builder, intrinsic_name, emit_data->dst_type,
3788 emit_data->args, emit_data->arg_count,
3789 get_store_intr_attribs(writeonly_memory));
3790 }
3791 }
3792
3793 static void store_emit_memory(
3794 struct si_shader_context *ctx,
3795 struct lp_build_emit_data *emit_data)
3796 {
3797 const struct tgsi_full_instruction *inst = emit_data->inst;
3798 struct gallivm_state *gallivm = &ctx->gallivm;
3799 struct lp_build_context *base = &ctx->bld_base.base;
3800 LLVMBuilderRef builder = gallivm->builder;
3801 unsigned writemask = inst->Dst[0].Register.WriteMask;
3802 LLVMValueRef ptr, derived_ptr, data, index;
3803 int chan;
3804
3805 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3806
3807 for (chan = 0; chan < 4; ++chan) {
3808 if (!(writemask & (1 << chan))) {
3809 continue;
3810 }
3811 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3812 index = lp_build_const_int32(gallivm, chan);
3813 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3814 LLVMBuildStore(builder, data, derived_ptr);
3815 }
3816 }
3817
3818 static void store_emit(
3819 const struct lp_build_tgsi_action *action,
3820 struct lp_build_tgsi_context *bld_base,
3821 struct lp_build_emit_data *emit_data)
3822 {
3823 struct si_shader_context *ctx = si_shader_context(bld_base);
3824 struct gallivm_state *gallivm = bld_base->base.gallivm;
3825 LLVMBuilderRef builder = gallivm->builder;
3826 const struct tgsi_full_instruction * inst = emit_data->inst;
3827 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3828 unsigned target = inst->Memory.Texture;
3829 char intrinsic_name[64];
3830 bool writeonly_memory = false;
3831
3832 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3833 store_emit_memory(ctx, emit_data);
3834 return;
3835 }
3836
3837 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3838 emit_waitcnt(ctx, VM_CNT);
3839
3840 writeonly_memory = is_oneway_access_only(inst, info,
3841 info->shader_buffers_load |
3842 info->shader_buffers_atomic,
3843 info->images_load |
3844 info->images_atomic);
3845
3846 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3847 store_emit_buffer(ctx, emit_data, writeonly_memory);
3848 return;
3849 }
3850
3851 if (target == TGSI_TEXTURE_BUFFER) {
3852 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3853 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3854 emit_data->dst_type, emit_data->args,
3855 emit_data->arg_count,
3856 get_store_intr_attribs(writeonly_memory));
3857 } else {
3858 ac_get_image_intr_name("llvm.amdgcn.image.store",
3859 LLVMTypeOf(emit_data->args[0]), /* vdata */
3860 LLVMTypeOf(emit_data->args[1]), /* coords */
3861 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3862 intrinsic_name, sizeof(intrinsic_name));
3863
3864 emit_data->output[emit_data->chan] =
3865 lp_build_intrinsic(
3866 builder, intrinsic_name, emit_data->dst_type,
3867 emit_data->args, emit_data->arg_count,
3868 get_store_intr_attribs(writeonly_memory));
3869 }
3870 }
3871
3872 static void atomic_fetch_args(
3873 struct lp_build_tgsi_context * bld_base,
3874 struct lp_build_emit_data * emit_data)
3875 {
3876 struct si_shader_context *ctx = si_shader_context(bld_base);
3877 struct gallivm_state *gallivm = bld_base->base.gallivm;
3878 LLVMBuilderRef builder = gallivm->builder;
3879 const struct tgsi_full_instruction * inst = emit_data->inst;
3880 LLVMValueRef data1, data2;
3881 LLVMValueRef rsrc;
3882 LLVMValueRef tmp;
3883
3884 emit_data->dst_type = bld_base->base.elem_type;
3885
3886 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3887 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3888
3889 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3890 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3891 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3892 }
3893
3894 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3895 * of arguments, which is reversed relative to TGSI (and GLSL)
3896 */
3897 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3898 emit_data->args[emit_data->arg_count++] = data2;
3899 emit_data->args[emit_data->arg_count++] = data1;
3900
3901 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3902 LLVMValueRef offset;
3903
3904 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3905
3906 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3907 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3908
3909 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3910 offset, true, false);
3911 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3912 unsigned target = inst->Memory.Texture;
3913 LLVMValueRef coords;
3914
3915 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3916 coords = image_fetch_coords(bld_base, inst, 1);
3917
3918 if (target == TGSI_TEXTURE_BUFFER) {
3919 buffer_append_args(ctx, emit_data, rsrc, coords,
3920 bld_base->uint_bld.zero, true, false);
3921 } else {
3922 emit_data->args[emit_data->arg_count++] = coords;
3923 emit_data->args[emit_data->arg_count++] = rsrc;
3924
3925 image_append_args(ctx, emit_data, target, true, false);
3926 }
3927 }
3928 }
3929
3930 static void atomic_emit_memory(struct si_shader_context *ctx,
3931 struct lp_build_emit_data *emit_data) {
3932 struct gallivm_state *gallivm = &ctx->gallivm;
3933 LLVMBuilderRef builder = gallivm->builder;
3934 const struct tgsi_full_instruction * inst = emit_data->inst;
3935 LLVMValueRef ptr, result, arg;
3936
3937 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3938
3939 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
3940 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3941
3942 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3943 LLVMValueRef new_data;
3944 new_data = lp_build_emit_fetch(&ctx->bld_base,
3945 inst, 3, 0);
3946
3947 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3948
3949 #if HAVE_LLVM >= 0x309
3950 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3951 LLVMAtomicOrderingSequentiallyConsistent,
3952 LLVMAtomicOrderingSequentiallyConsistent,
3953 false);
3954 #endif
3955
3956 result = LLVMBuildExtractValue(builder, result, 0, "");
3957 } else {
3958 LLVMAtomicRMWBinOp op;
3959
3960 switch(inst->Instruction.Opcode) {
3961 case TGSI_OPCODE_ATOMUADD:
3962 op = LLVMAtomicRMWBinOpAdd;
3963 break;
3964 case TGSI_OPCODE_ATOMXCHG:
3965 op = LLVMAtomicRMWBinOpXchg;
3966 break;
3967 case TGSI_OPCODE_ATOMAND:
3968 op = LLVMAtomicRMWBinOpAnd;
3969 break;
3970 case TGSI_OPCODE_ATOMOR:
3971 op = LLVMAtomicRMWBinOpOr;
3972 break;
3973 case TGSI_OPCODE_ATOMXOR:
3974 op = LLVMAtomicRMWBinOpXor;
3975 break;
3976 case TGSI_OPCODE_ATOMUMIN:
3977 op = LLVMAtomicRMWBinOpUMin;
3978 break;
3979 case TGSI_OPCODE_ATOMUMAX:
3980 op = LLVMAtomicRMWBinOpUMax;
3981 break;
3982 case TGSI_OPCODE_ATOMIMIN:
3983 op = LLVMAtomicRMWBinOpMin;
3984 break;
3985 case TGSI_OPCODE_ATOMIMAX:
3986 op = LLVMAtomicRMWBinOpMax;
3987 break;
3988 default:
3989 unreachable("unknown atomic opcode");
3990 }
3991
3992 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3993 LLVMAtomicOrderingSequentiallyConsistent,
3994 false);
3995 }
3996 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3997 }
3998
3999 static void atomic_emit(
4000 const struct lp_build_tgsi_action *action,
4001 struct lp_build_tgsi_context *bld_base,
4002 struct lp_build_emit_data *emit_data)
4003 {
4004 struct si_shader_context *ctx = si_shader_context(bld_base);
4005 struct gallivm_state *gallivm = bld_base->base.gallivm;
4006 LLVMBuilderRef builder = gallivm->builder;
4007 const struct tgsi_full_instruction * inst = emit_data->inst;
4008 char intrinsic_name[40];
4009 LLVMValueRef tmp;
4010
4011 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4012 atomic_emit_memory(ctx, emit_data);
4013 return;
4014 }
4015
4016 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4017 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4018 snprintf(intrinsic_name, sizeof(intrinsic_name),
4019 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4020 } else {
4021 LLVMValueRef coords;
4022 char coords_type[8];
4023
4024 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4025 coords = emit_data->args[2];
4026 else
4027 coords = emit_data->args[1];
4028
4029 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4030 snprintf(intrinsic_name, sizeof(intrinsic_name),
4031 "llvm.amdgcn.image.atomic.%s.%s",
4032 action->intr_name, coords_type);
4033 }
4034
4035 tmp = lp_build_intrinsic(
4036 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4037 emit_data->args, emit_data->arg_count, 0);
4038 emit_data->output[emit_data->chan] =
4039 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4040 }
4041
4042 static void set_tex_fetch_args(struct si_shader_context *ctx,
4043 struct lp_build_emit_data *emit_data,
4044 unsigned target,
4045 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4046 LLVMValueRef *param, unsigned count,
4047 unsigned dmask)
4048 {
4049 struct gallivm_state *gallivm = &ctx->gallivm;
4050 struct ac_image_args args = {};
4051
4052 /* Pad to power of two vector */
4053 while (count < util_next_power_of_two(count))
4054 param[count++] = LLVMGetUndef(ctx->i32);
4055
4056 if (count > 1)
4057 args.addr = lp_build_gather_values(gallivm, param, count);
4058 else
4059 args.addr = param[0];
4060
4061 args.resource = res_ptr;
4062 args.sampler = samp_ptr;
4063 args.dmask = dmask;
4064 args.unorm = target == TGSI_TEXTURE_RECT ||
4065 target == TGSI_TEXTURE_SHADOWRECT;
4066 args.da = tgsi_is_array_sampler(target);
4067
4068 /* Ugly, but we seem to have no other choice right now. */
4069 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4070 memcpy(emit_data->args, &args, sizeof(args));
4071 }
4072
4073 static void resq_fetch_args(
4074 struct lp_build_tgsi_context * bld_base,
4075 struct lp_build_emit_data * emit_data)
4076 {
4077 struct si_shader_context *ctx = si_shader_context(bld_base);
4078 const struct tgsi_full_instruction *inst = emit_data->inst;
4079 const struct tgsi_full_src_register *reg = &inst->Src[0];
4080
4081 emit_data->dst_type = ctx->v4i32;
4082
4083 if (reg->Register.File == TGSI_FILE_BUFFER) {
4084 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4085 emit_data->arg_count = 1;
4086 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4087 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4088 &emit_data->args[0]);
4089 emit_data->arg_count = 1;
4090 } else {
4091 LLVMValueRef res_ptr;
4092 unsigned image_target;
4093
4094 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4095 image_target = TGSI_TEXTURE_2D_ARRAY;
4096 else
4097 image_target = inst->Memory.Texture;
4098
4099 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4100 &res_ptr);
4101 set_tex_fetch_args(ctx, emit_data, image_target,
4102 res_ptr, NULL, &bld_base->uint_bld.zero, 1,
4103 0xf);
4104 }
4105 }
4106
4107 static void resq_emit(
4108 const struct lp_build_tgsi_action *action,
4109 struct lp_build_tgsi_context *bld_base,
4110 struct lp_build_emit_data *emit_data)
4111 {
4112 struct si_shader_context *ctx = si_shader_context(bld_base);
4113 struct gallivm_state *gallivm = bld_base->base.gallivm;
4114 LLVMBuilderRef builder = gallivm->builder;
4115 const struct tgsi_full_instruction *inst = emit_data->inst;
4116 LLVMValueRef out;
4117
4118 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4119 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4120 lp_build_const_int32(gallivm, 2), "");
4121 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4122 out = get_buffer_size(bld_base, emit_data->args[0]);
4123 } else {
4124 struct ac_image_args args;
4125
4126 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4127 args.opcode = ac_image_get_resinfo;
4128 out = ac_build_image_opcode(&ctx->ac, &args);
4129
4130 /* Divide the number of layers by 6 to get the number of cubes. */
4131 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4132 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4133 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4134
4135 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4136 z = LLVMBuildSDiv(builder, z, imm6, "");
4137 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4138 }
4139 }
4140
4141 emit_data->output[emit_data->chan] = out;
4142 }
4143
4144 static const struct lp_build_tgsi_action tex_action;
4145
4146 enum desc_type {
4147 DESC_IMAGE,
4148 DESC_BUFFER,
4149 DESC_FMASK,
4150 DESC_SAMPLER,
4151 };
4152
4153 /**
4154 * Load an image view, fmask view. or sampler state descriptor.
4155 */
4156 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4157 LLVMValueRef list, LLVMValueRef index,
4158 enum desc_type type)
4159 {
4160 struct gallivm_state *gallivm = &ctx->gallivm;
4161 LLVMBuilderRef builder = gallivm->builder;
4162
4163 switch (type) {
4164 case DESC_IMAGE:
4165 /* The image is at [0:7]. */
4166 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4167 break;
4168 case DESC_BUFFER:
4169 /* The buffer is in [4:7]. */
4170 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4171 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4172 list = LLVMBuildPointerCast(builder, list,
4173 const_array(ctx->v4i32, 0), "");
4174 break;
4175 case DESC_FMASK:
4176 /* The FMASK is at [8:15]. */
4177 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4178 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4179 break;
4180 case DESC_SAMPLER:
4181 /* The sampler state is at [12:15]. */
4182 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4183 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4184 list = LLVMBuildPointerCast(builder, list,
4185 const_array(ctx->v4i32, 0), "");
4186 break;
4187 }
4188
4189 return ac_build_indexed_load_const(&ctx->ac, list, index);
4190 }
4191
4192 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4193 LLVMValueRef index, enum desc_type type)
4194 {
4195 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4196 SI_PARAM_SAMPLERS);
4197
4198 return load_sampler_desc_custom(ctx, list, index, type);
4199 }
4200
4201 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4202 *
4203 * SI-CI:
4204 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4205 * filtering manually. The driver sets img7 to a mask clearing
4206 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4207 * s_and_b32 samp0, samp0, img7
4208 *
4209 * VI:
4210 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4211 */
4212 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4213 LLVMValueRef res, LLVMValueRef samp)
4214 {
4215 LLVMBuilderRef builder = ctx->gallivm.builder;
4216 LLVMValueRef img7, samp0;
4217
4218 if (ctx->screen->b.chip_class >= VI)
4219 return samp;
4220
4221 img7 = LLVMBuildExtractElement(builder, res,
4222 LLVMConstInt(ctx->i32, 7, 0), "");
4223 samp0 = LLVMBuildExtractElement(builder, samp,
4224 LLVMConstInt(ctx->i32, 0, 0), "");
4225 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4226 return LLVMBuildInsertElement(builder, samp, samp0,
4227 LLVMConstInt(ctx->i32, 0, 0), "");
4228 }
4229
4230 static void tex_fetch_ptrs(
4231 struct lp_build_tgsi_context *bld_base,
4232 struct lp_build_emit_data *emit_data,
4233 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 const struct tgsi_full_instruction *inst = emit_data->inst;
4237 unsigned target = inst->Texture.Texture;
4238 unsigned sampler_src;
4239 unsigned sampler_index;
4240 LLVMValueRef index;
4241
4242 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4243 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4244
4245 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4246 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4247
4248 index = get_bounded_indirect_index(ctx,
4249 &reg->Indirect,
4250 reg->Register.Index,
4251 SI_NUM_SAMPLERS);
4252 } else {
4253 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4254 }
4255
4256 if (target == TGSI_TEXTURE_BUFFER)
4257 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4258 else
4259 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4260
4261 if (samp_ptr)
4262 *samp_ptr = NULL;
4263 if (fmask_ptr)
4264 *fmask_ptr = NULL;
4265
4266 if (target == TGSI_TEXTURE_2D_MSAA ||
4267 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4268 if (fmask_ptr)
4269 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4270 } else if (target != TGSI_TEXTURE_BUFFER) {
4271 if (samp_ptr) {
4272 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4273 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4274 }
4275 }
4276 }
4277
4278 static void txq_fetch_args(
4279 struct lp_build_tgsi_context *bld_base,
4280 struct lp_build_emit_data *emit_data)
4281 {
4282 struct si_shader_context *ctx = si_shader_context(bld_base);
4283 const struct tgsi_full_instruction *inst = emit_data->inst;
4284 unsigned target = inst->Texture.Texture;
4285 LLVMValueRef res_ptr;
4286 LLVMValueRef address;
4287
4288 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4289
4290 if (target == TGSI_TEXTURE_BUFFER) {
4291 /* Read the size from the buffer descriptor directly. */
4292 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4293 return;
4294 }
4295
4296 /* Textures - set the mip level. */
4297 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4298
4299 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4300 NULL, &address, 1, 0xf);
4301 }
4302
4303 static void txq_emit(const struct lp_build_tgsi_action *action,
4304 struct lp_build_tgsi_context *bld_base,
4305 struct lp_build_emit_data *emit_data)
4306 {
4307 struct si_shader_context *ctx = si_shader_context(bld_base);
4308 struct ac_image_args args;
4309 unsigned target = emit_data->inst->Texture.Texture;
4310
4311 if (target == TGSI_TEXTURE_BUFFER) {
4312 /* Just return the buffer size. */
4313 emit_data->output[emit_data->chan] = emit_data->args[0];
4314 return;
4315 }
4316
4317 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4318
4319 args.opcode = ac_image_get_resinfo;
4320 emit_data->output[emit_data->chan] =
4321 ac_build_image_opcode(&ctx->ac, &args);
4322
4323 /* Divide the number of layers by 6 to get the number of cubes. */
4324 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4325 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4326 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4327 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4328 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4329
4330 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4331 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4332 z = LLVMBuildSDiv(builder, z, six, "");
4333
4334 emit_data->output[emit_data->chan] =
4335 LLVMBuildInsertElement(builder, v4, z, two, "");
4336 }
4337 }
4338
4339 static void tex_fetch_args(
4340 struct lp_build_tgsi_context *bld_base,
4341 struct lp_build_emit_data *emit_data)
4342 {
4343 struct si_shader_context *ctx = si_shader_context(bld_base);
4344 struct gallivm_state *gallivm = bld_base->base.gallivm;
4345 const struct tgsi_full_instruction *inst = emit_data->inst;
4346 unsigned opcode = inst->Instruction.Opcode;
4347 unsigned target = inst->Texture.Texture;
4348 LLVMValueRef coords[5], derivs[6];
4349 LLVMValueRef address[16];
4350 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4351 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4352 unsigned count = 0;
4353 unsigned chan;
4354 unsigned num_deriv_channels = 0;
4355 bool has_offset = inst->Texture.NumOffsets > 0;
4356 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4357 unsigned dmask = 0xf;
4358
4359 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4360
4361 if (target == TGSI_TEXTURE_BUFFER) {
4362 emit_data->dst_type = ctx->v4f32;
4363 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4364 ctx->v16i8, "");
4365 emit_data->args[1] = bld_base->uint_bld.zero;
4366 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4367 emit_data->arg_count = 3;
4368 return;
4369 }
4370
4371 /* Fetch and project texture coordinates */
4372 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4373 for (chan = 0; chan < 3; chan++ ) {
4374 coords[chan] = lp_build_emit_fetch(bld_base,
4375 emit_data->inst, 0,
4376 chan);
4377 if (opcode == TGSI_OPCODE_TXP)
4378 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4379 TGSI_OPCODE_DIV,
4380 coords[chan],
4381 coords[3]);
4382 }
4383
4384 if (opcode == TGSI_OPCODE_TXP)
4385 coords[3] = bld_base->base.one;
4386
4387 /* Pack offsets. */
4388 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4389 /* The offsets are six-bit signed integers packed like this:
4390 * X=[5:0], Y=[13:8], and Z=[21:16].
4391 */
4392 LLVMValueRef offset[3], pack;
4393
4394 assert(inst->Texture.NumOffsets == 1);
4395
4396 for (chan = 0; chan < 3; chan++) {
4397 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4398 emit_data->inst, 0, chan);
4399 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4400 lp_build_const_int32(gallivm, 0x3f), "");
4401 if (chan)
4402 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4403 lp_build_const_int32(gallivm, chan*8), "");
4404 }
4405
4406 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4407 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4408 address[count++] = pack;
4409 }
4410
4411 /* Pack LOD bias value */
4412 if (opcode == TGSI_OPCODE_TXB)
4413 address[count++] = coords[3];
4414 if (opcode == TGSI_OPCODE_TXB2)
4415 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4416
4417 /* Pack depth comparison value */
4418 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4419 LLVMValueRef z;
4420
4421 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4422 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4423 } else {
4424 assert(ref_pos >= 0);
4425 z = coords[ref_pos];
4426 }
4427
4428 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4429 * so the depth comparison value isn't clamped for Z16 and
4430 * Z24 anymore. Do it manually here.
4431 *
4432 * It's unnecessary if the original texture format was
4433 * Z32_FLOAT, but we don't know that here.
4434 */
4435 if (ctx->screen->b.chip_class == VI)
4436 z = ac_build_clamp(&ctx->ac, z);
4437
4438 address[count++] = z;
4439 }
4440
4441 /* Pack user derivatives */
4442 if (opcode == TGSI_OPCODE_TXD) {
4443 int param, num_src_deriv_channels;
4444
4445 switch (target) {
4446 case TGSI_TEXTURE_3D:
4447 num_src_deriv_channels = 3;
4448 num_deriv_channels = 3;
4449 break;
4450 case TGSI_TEXTURE_2D:
4451 case TGSI_TEXTURE_SHADOW2D:
4452 case TGSI_TEXTURE_RECT:
4453 case TGSI_TEXTURE_SHADOWRECT:
4454 case TGSI_TEXTURE_2D_ARRAY:
4455 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4456 num_src_deriv_channels = 2;
4457 num_deriv_channels = 2;
4458 break;
4459 case TGSI_TEXTURE_CUBE:
4460 case TGSI_TEXTURE_SHADOWCUBE:
4461 case TGSI_TEXTURE_CUBE_ARRAY:
4462 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4463 /* Cube derivatives will be converted to 2D. */
4464 num_src_deriv_channels = 3;
4465 num_deriv_channels = 2;
4466 break;
4467 case TGSI_TEXTURE_1D:
4468 case TGSI_TEXTURE_SHADOW1D:
4469 case TGSI_TEXTURE_1D_ARRAY:
4470 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4471 num_src_deriv_channels = 1;
4472 num_deriv_channels = 1;
4473 break;
4474 default:
4475 unreachable("invalid target");
4476 }
4477
4478 for (param = 0; param < 2; param++)
4479 for (chan = 0; chan < num_src_deriv_channels; chan++)
4480 derivs[param * num_src_deriv_channels + chan] =
4481 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4482 }
4483
4484 if (target == TGSI_TEXTURE_CUBE ||
4485 target == TGSI_TEXTURE_CUBE_ARRAY ||
4486 target == TGSI_TEXTURE_SHADOWCUBE ||
4487 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4488 ac_prepare_cube_coords(&ctx->ac,
4489 opcode == TGSI_OPCODE_TXD,
4490 target == TGSI_TEXTURE_CUBE_ARRAY ||
4491 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4492 coords, derivs);
4493
4494 if (opcode == TGSI_OPCODE_TXD)
4495 for (int i = 0; i < num_deriv_channels * 2; i++)
4496 address[count++] = derivs[i];
4497
4498 /* Pack texture coordinates */
4499 address[count++] = coords[0];
4500 if (num_coords > 1)
4501 address[count++] = coords[1];
4502 if (num_coords > 2)
4503 address[count++] = coords[2];
4504
4505 /* Pack LOD or sample index */
4506 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4507 address[count++] = coords[3];
4508 else if (opcode == TGSI_OPCODE_TXL2)
4509 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4510
4511 if (count > 16) {
4512 assert(!"Cannot handle more than 16 texture address parameters");
4513 count = 16;
4514 }
4515
4516 for (chan = 0; chan < count; chan++ ) {
4517 address[chan] = LLVMBuildBitCast(gallivm->builder,
4518 address[chan], ctx->i32, "");
4519 }
4520
4521 /* Adjust the sample index according to FMASK.
4522 *
4523 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4524 * which is the identity mapping. Each nibble says which physical sample
4525 * should be fetched to get that sample.
4526 *
4527 * For example, 0x11111100 means there are only 2 samples stored and
4528 * the second sample covers 3/4 of the pixel. When reading samples 0
4529 * and 1, return physical sample 0 (determined by the first two 0s
4530 * in FMASK), otherwise return physical sample 1.
4531 *
4532 * The sample index should be adjusted as follows:
4533 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4534 */
4535 if (target == TGSI_TEXTURE_2D_MSAA ||
4536 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4537 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4538 struct lp_build_emit_data txf_emit_data = *emit_data;
4539 LLVMValueRef txf_address[4];
4540 /* We only need .xy for non-arrays, and .xyz for arrays. */
4541 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4542 struct tgsi_full_instruction inst = {};
4543
4544 memcpy(txf_address, address, sizeof(txf_address));
4545
4546 /* Read FMASK using TXF. */
4547 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4548 inst.Texture.Texture = target;
4549 txf_emit_data.inst = &inst;
4550 txf_emit_data.chan = 0;
4551 set_tex_fetch_args(ctx, &txf_emit_data,
4552 target, fmask_ptr, NULL,
4553 txf_address, txf_count, 0xf);
4554 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4555
4556 /* Initialize some constants. */
4557 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4558 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4559
4560 /* Apply the formula. */
4561 LLVMValueRef fmask =
4562 LLVMBuildExtractElement(gallivm->builder,
4563 txf_emit_data.output[0],
4564 uint_bld->zero, "");
4565
4566 unsigned sample_chan = txf_count; /* the sample index is last */
4567
4568 LLVMValueRef sample_index4 =
4569 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4570
4571 LLVMValueRef shifted_fmask =
4572 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4573
4574 LLVMValueRef final_sample =
4575 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4576
4577 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4578 * resource descriptor is 0 (invalid),
4579 */
4580 LLVMValueRef fmask_desc =
4581 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4582 ctx->v8i32, "");
4583
4584 LLVMValueRef fmask_word1 =
4585 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4586 uint_bld->one, "");
4587
4588 LLVMValueRef word1_is_nonzero =
4589 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4590 fmask_word1, uint_bld->zero, "");
4591
4592 /* Replace the MSAA sample index. */
4593 address[sample_chan] =
4594 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4595 final_sample, address[sample_chan], "");
4596 }
4597
4598 if (opcode == TGSI_OPCODE_TXF) {
4599 /* add tex offsets */
4600 if (inst->Texture.NumOffsets) {
4601 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4602 const struct tgsi_texture_offset *off = inst->TexOffsets;
4603
4604 assert(inst->Texture.NumOffsets == 1);
4605
4606 switch (target) {
4607 case TGSI_TEXTURE_3D:
4608 address[2] = lp_build_add(uint_bld, address[2],
4609 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4610 /* fall through */
4611 case TGSI_TEXTURE_2D:
4612 case TGSI_TEXTURE_SHADOW2D:
4613 case TGSI_TEXTURE_RECT:
4614 case TGSI_TEXTURE_SHADOWRECT:
4615 case TGSI_TEXTURE_2D_ARRAY:
4616 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4617 address[1] =
4618 lp_build_add(uint_bld, address[1],
4619 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4620 /* fall through */
4621 case TGSI_TEXTURE_1D:
4622 case TGSI_TEXTURE_SHADOW1D:
4623 case TGSI_TEXTURE_1D_ARRAY:
4624 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4625 address[0] =
4626 lp_build_add(uint_bld, address[0],
4627 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4628 break;
4629 /* texture offsets do not apply to other texture targets */
4630 }
4631 }
4632 }
4633
4634 if (opcode == TGSI_OPCODE_TG4) {
4635 unsigned gather_comp = 0;
4636
4637 /* DMASK was repurposed for GATHER4. 4 components are always
4638 * returned and DMASK works like a swizzle - it selects
4639 * the component to fetch. The only valid DMASK values are
4640 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4641 * (red,red,red,red) etc.) The ISA document doesn't mention
4642 * this.
4643 */
4644
4645 /* Get the component index from src1.x for Gather4. */
4646 if (!tgsi_is_shadow_target(target)) {
4647 LLVMValueRef comp_imm;
4648 struct tgsi_src_register src1 = inst->Src[1].Register;
4649
4650 assert(src1.File == TGSI_FILE_IMMEDIATE);
4651
4652 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4653 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4654 gather_comp = CLAMP(gather_comp, 0, 3);
4655 }
4656
4657 dmask = 1 << gather_comp;
4658 }
4659
4660 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4661 samp_ptr, address, count, dmask);
4662 }
4663
4664 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4665 * incorrectly forces nearest filtering if the texture format is integer.
4666 * The only effect it has on Gather4, which always returns 4 texels for
4667 * bilinear filtering, is that the final coordinates are off by 0.5 of
4668 * the texel size.
4669 *
4670 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4671 * or (0.5 / size) from the normalized coordinates.
4672 */
4673 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4674 struct ac_image_args *args,
4675 unsigned target)
4676 {
4677 LLVMBuilderRef builder = ctx->gallivm.builder;
4678 LLVMValueRef coord = args->addr;
4679 LLVMValueRef half_texel[2];
4680 /* Texture coordinates start after:
4681 * {offset, bias, z-compare, derivatives}
4682 * Only the offset and z-compare can occur here.
4683 */
4684 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4685 int c;
4686
4687 if (target == TGSI_TEXTURE_RECT ||
4688 target == TGSI_TEXTURE_SHADOWRECT) {
4689 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4690 } else {
4691 struct tgsi_full_instruction txq_inst = {};
4692 struct lp_build_emit_data txq_emit_data = {};
4693
4694 /* Query the texture size. */
4695 txq_inst.Texture.Texture = target;
4696 txq_emit_data.inst = &txq_inst;
4697 txq_emit_data.dst_type = ctx->v4i32;
4698 set_tex_fetch_args(ctx, &txq_emit_data, target,
4699 args->resource, NULL,
4700 &ctx->bld_base.uint_bld.zero,
4701 1, 0xf);
4702 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4703
4704 /* Compute -0.5 / size. */
4705 for (c = 0; c < 2; c++) {
4706 half_texel[c] =
4707 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4708 LLVMConstInt(ctx->i32, c, 0), "");
4709 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4710 half_texel[c] =
4711 lp_build_emit_llvm_unary(&ctx->bld_base,
4712 TGSI_OPCODE_RCP, half_texel[c]);
4713 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4714 LLVMConstReal(ctx->f32, -0.5), "");
4715 }
4716 }
4717
4718 for (c = 0; c < 2; c++) {
4719 LLVMValueRef tmp;
4720 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4721
4722 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4723 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4724 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4725 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4726 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4727 }
4728
4729 args->addr = coord;
4730 }
4731
4732 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4733 struct lp_build_tgsi_context *bld_base,
4734 struct lp_build_emit_data *emit_data)
4735 {
4736 struct si_shader_context *ctx = si_shader_context(bld_base);
4737 const struct tgsi_full_instruction *inst = emit_data->inst;
4738 struct ac_image_args args;
4739 unsigned opcode = inst->Instruction.Opcode;
4740 unsigned target = inst->Texture.Texture;
4741
4742 if (target == TGSI_TEXTURE_BUFFER) {
4743 emit_data->output[emit_data->chan] =
4744 ac_build_buffer_load_format(&ctx->ac,
4745 emit_data->args[0],
4746 emit_data->args[2],
4747 emit_data->args[1],
4748 true);
4749 return;
4750 }
4751
4752 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4753
4754 args.opcode = ac_image_sample;
4755 args.compare = tgsi_is_shadow_target(target);
4756 args.offset = inst->Texture.NumOffsets > 0;
4757
4758 switch (opcode) {
4759 case TGSI_OPCODE_TXF:
4760 args.opcode = target == TGSI_TEXTURE_2D_MSAA ||
4761 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4762 ac_image_load : ac_image_load_mip;
4763 args.compare = false;
4764 args.offset = false;
4765 break;
4766 case TGSI_OPCODE_LODQ:
4767 args.opcode = ac_image_get_lod;
4768 args.compare = false;
4769 args.offset = false;
4770 break;
4771 case TGSI_OPCODE_TEX:
4772 case TGSI_OPCODE_TEX2:
4773 case TGSI_OPCODE_TXP:
4774 if (ctx->type != PIPE_SHADER_FRAGMENT)
4775 args.level_zero = true;
4776 break;
4777 case TGSI_OPCODE_TXB:
4778 case TGSI_OPCODE_TXB2:
4779 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4780 args.bias = true;
4781 break;
4782 case TGSI_OPCODE_TXL:
4783 case TGSI_OPCODE_TXL2:
4784 args.lod = true;
4785 break;
4786 case TGSI_OPCODE_TXD:
4787 args.deriv = true;
4788 break;
4789 case TGSI_OPCODE_TG4:
4790 args.opcode = ac_image_gather4;
4791 args.level_zero = true;
4792 break;
4793 default:
4794 assert(0);
4795 return;
4796 }
4797
4798 /* The hardware needs special lowering for Gather4 with integer formats. */
4799 if (opcode == TGSI_OPCODE_TG4) {
4800 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4801 /* This will also work with non-constant indexing because of how
4802 * glsl_to_tgsi works and we intent to preserve that behavior.
4803 */
4804 const unsigned src_idx = 2;
4805 unsigned sampler = inst->Src[src_idx].Register.Index;
4806
4807 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4808
4809 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4810 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4811 si_lower_gather4_integer(ctx, &args, target);
4812 }
4813
4814 emit_data->output[emit_data->chan] =
4815 ac_build_image_opcode(&ctx->ac, &args);
4816 }
4817
4818 static void si_llvm_emit_txqs(
4819 const struct lp_build_tgsi_action *action,
4820 struct lp_build_tgsi_context *bld_base,
4821 struct lp_build_emit_data *emit_data)
4822 {
4823 struct si_shader_context *ctx = si_shader_context(bld_base);
4824 struct gallivm_state *gallivm = bld_base->base.gallivm;
4825 LLVMBuilderRef builder = gallivm->builder;
4826 LLVMValueRef res, samples;
4827 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4828
4829 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4830
4831
4832 /* Read the samples from the descriptor directly. */
4833 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4834 samples = LLVMBuildExtractElement(
4835 builder, res,
4836 lp_build_const_int32(gallivm, 3), "");
4837 samples = LLVMBuildLShr(builder, samples,
4838 lp_build_const_int32(gallivm, 16), "");
4839 samples = LLVMBuildAnd(builder, samples,
4840 lp_build_const_int32(gallivm, 0xf), "");
4841 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4842 samples, "");
4843
4844 emit_data->output[emit_data->chan] = samples;
4845 }
4846
4847 static void si_llvm_emit_ddxy(
4848 const struct lp_build_tgsi_action *action,
4849 struct lp_build_tgsi_context *bld_base,
4850 struct lp_build_emit_data *emit_data)
4851 {
4852 struct si_shader_context *ctx = si_shader_context(bld_base);
4853 struct gallivm_state *gallivm = bld_base->base.gallivm;
4854 unsigned opcode = emit_data->info->opcode;
4855 LLVMValueRef val;
4856 int idx;
4857 unsigned mask;
4858
4859 if (opcode == TGSI_OPCODE_DDX_FINE)
4860 mask = AC_TID_MASK_LEFT;
4861 else if (opcode == TGSI_OPCODE_DDY_FINE)
4862 mask = AC_TID_MASK_TOP;
4863 else
4864 mask = AC_TID_MASK_TOP_LEFT;
4865
4866 /* for DDX we want to next X pixel, DDY next Y pixel. */
4867 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4868
4869 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4870 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
4871 mask, idx, ctx->lds, val);
4872 emit_data->output[emit_data->chan] = val;
4873 }
4874
4875 /*
4876 * this takes an I,J coordinate pair,
4877 * and works out the X and Y derivatives.
4878 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4879 */
4880 static LLVMValueRef si_llvm_emit_ddxy_interp(
4881 struct lp_build_tgsi_context *bld_base,
4882 LLVMValueRef interp_ij)
4883 {
4884 struct si_shader_context *ctx = si_shader_context(bld_base);
4885 struct gallivm_state *gallivm = bld_base->base.gallivm;
4886 LLVMValueRef result[4], a;
4887 unsigned i;
4888
4889 for (i = 0; i < 2; i++) {
4890 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4891 LLVMConstInt(ctx->i32, i, 0), "");
4892 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4893 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4894 }
4895
4896 return lp_build_gather_values(gallivm, result, 4);
4897 }
4898
4899 static void interp_fetch_args(
4900 struct lp_build_tgsi_context *bld_base,
4901 struct lp_build_emit_data *emit_data)
4902 {
4903 struct si_shader_context *ctx = si_shader_context(bld_base);
4904 struct gallivm_state *gallivm = bld_base->base.gallivm;
4905 const struct tgsi_full_instruction *inst = emit_data->inst;
4906
4907 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4908 /* offset is in second src, first two channels */
4909 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4910 emit_data->inst, 1,
4911 TGSI_CHAN_X);
4912 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4913 emit_data->inst, 1,
4914 TGSI_CHAN_Y);
4915 emit_data->arg_count = 2;
4916 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4917 LLVMValueRef sample_position;
4918 LLVMValueRef sample_id;
4919 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4920
4921 /* fetch sample ID, then fetch its sample position,
4922 * and place into first two channels.
4923 */
4924 sample_id = lp_build_emit_fetch(bld_base,
4925 emit_data->inst, 1, TGSI_CHAN_X);
4926 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4927 ctx->i32, "");
4928 sample_position = load_sample_position(ctx, sample_id);
4929
4930 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4931 sample_position,
4932 lp_build_const_int32(gallivm, 0), "");
4933
4934 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4935 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4936 sample_position,
4937 lp_build_const_int32(gallivm, 1), "");
4938 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4939 emit_data->arg_count = 2;
4940 }
4941 }
4942
4943 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4944 struct lp_build_tgsi_context *bld_base,
4945 struct lp_build_emit_data *emit_data)
4946 {
4947 struct si_shader_context *ctx = si_shader_context(bld_base);
4948 struct si_shader *shader = ctx->shader;
4949 struct gallivm_state *gallivm = bld_base->base.gallivm;
4950 struct lp_build_context *uint = &bld_base->uint_bld;
4951 LLVMValueRef interp_param;
4952 const struct tgsi_full_instruction *inst = emit_data->inst;
4953 int input_index = inst->Src[0].Register.Index;
4954 int chan;
4955 int i;
4956 LLVMValueRef attr_number;
4957 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
4958 int interp_param_idx;
4959 unsigned interp = shader->selector->info.input_interpolate[input_index];
4960 unsigned location;
4961
4962 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4963
4964 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4965 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4966 location = TGSI_INTERPOLATE_LOC_CENTER;
4967 else
4968 location = TGSI_INTERPOLATE_LOC_CENTROID;
4969
4970 interp_param_idx = lookup_interp_param_index(interp, location);
4971 if (interp_param_idx == -1)
4972 return;
4973 else if (interp_param_idx)
4974 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4975 else
4976 interp_param = NULL;
4977
4978 attr_number = lp_build_const_int32(gallivm, input_index);
4979
4980 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4981 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4982 LLVMValueRef ij_out[2];
4983 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4984
4985 /*
4986 * take the I then J parameters, and the DDX/Y for it, and
4987 * calculate the IJ inputs for the interpolator.
4988 * temp1 = ddx * offset/sample.x + I;
4989 * interp_param.I = ddy * offset/sample.y + temp1;
4990 * temp1 = ddx * offset/sample.x + J;
4991 * interp_param.J = ddy * offset/sample.y + temp1;
4992 */
4993 for (i = 0; i < 2; i++) {
4994 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4995 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4996 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4997 ddxy_out, ix_ll, "");
4998 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4999 ddxy_out, iy_ll, "");
5000 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5001 interp_param, ix_ll, "");
5002 LLVMValueRef temp1, temp2;
5003
5004 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5005 ctx->f32, "");
5006
5007 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5008
5009 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5010
5011 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5012
5013 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5014 }
5015 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5016 }
5017
5018 for (chan = 0; chan < 4; chan++) {
5019 LLVMValueRef llvm_chan;
5020 unsigned schan;
5021
5022 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5023 llvm_chan = lp_build_const_int32(gallivm, schan);
5024
5025 if (interp_param) {
5026 interp_param = LLVMBuildBitCast(gallivm->builder,
5027 interp_param, LLVMVectorType(ctx->f32, 2), "");
5028 LLVMValueRef i = LLVMBuildExtractElement(
5029 gallivm->builder, interp_param, uint->zero, "");
5030 LLVMValueRef j = LLVMBuildExtractElement(
5031 gallivm->builder, interp_param, uint->one, "");
5032 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5033 llvm_chan, attr_number, params,
5034 i, j);
5035 } else {
5036 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5037 lp_build_const_int32(gallivm, 2), /* P0 */
5038 llvm_chan, attr_number, params);
5039 }
5040 }
5041 }
5042
5043 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5044 struct lp_build_emit_data *emit_data)
5045 {
5046 struct si_shader_context *ctx = si_shader_context(bld_base);
5047 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5048 LLVMValueRef imm;
5049 unsigned stream;
5050
5051 assert(src0.File == TGSI_FILE_IMMEDIATE);
5052
5053 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5054 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5055 return stream;
5056 }
5057
5058 /* Emit one vertex from the geometry shader */
5059 static void si_llvm_emit_vertex(
5060 const struct lp_build_tgsi_action *action,
5061 struct lp_build_tgsi_context *bld_base,
5062 struct lp_build_emit_data *emit_data)
5063 {
5064 struct si_shader_context *ctx = si_shader_context(bld_base);
5065 struct lp_build_context *uint = &bld_base->uint_bld;
5066 struct si_shader *shader = ctx->shader;
5067 struct tgsi_shader_info *info = &shader->selector->info;
5068 struct gallivm_state *gallivm = bld_base->base.gallivm;
5069 struct lp_build_if_state if_state;
5070 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5071 SI_PARAM_GS2VS_OFFSET);
5072 LLVMValueRef gs_next_vertex;
5073 LLVMValueRef can_emit, kill;
5074 unsigned chan, offset;
5075 int i;
5076 unsigned stream;
5077
5078 stream = si_llvm_get_stream(bld_base, emit_data);
5079
5080 /* Write vertex attribute values to GSVS ring */
5081 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5082 ctx->gs_next_vertex[stream],
5083 "");
5084
5085 /* If this thread has already emitted the declared maximum number of
5086 * vertices, skip the write: excessive vertex emissions are not
5087 * supposed to have any effect.
5088 *
5089 * If the shader has no writes to memory, kill it instead. This skips
5090 * further memory loads and may allow LLVM to skip to the end
5091 * altogether.
5092 */
5093 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5094 lp_build_const_int32(gallivm,
5095 shader->selector->gs_max_out_vertices), "");
5096
5097 bool use_kill = !info->writes_memory;
5098 if (use_kill) {
5099 kill = lp_build_select(&bld_base->base, can_emit,
5100 lp_build_const_float(gallivm, 1.0f),
5101 lp_build_const_float(gallivm, -1.0f));
5102
5103 ac_build_kill(&ctx->ac, kill);
5104 } else {
5105 lp_build_if(&if_state, gallivm, can_emit);
5106 }
5107
5108 offset = 0;
5109 for (i = 0; i < info->num_outputs; i++) {
5110 LLVMValueRef *out_ptr = ctx->outputs[i];
5111
5112 for (chan = 0; chan < 4; chan++) {
5113 if (!(info->output_usagemask[i] & (1 << chan)) ||
5114 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5115 continue;
5116
5117 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5118 LLVMValueRef voffset =
5119 lp_build_const_int32(gallivm, offset *
5120 shader->selector->gs_max_out_vertices);
5121 offset++;
5122
5123 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5124 voffset = lp_build_mul_imm(uint, voffset, 4);
5125
5126 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5127
5128 ac_build_buffer_store_dword(&ctx->ac,
5129 ctx->gsvs_ring[stream],
5130 out_val, 1,
5131 voffset, soffset, 0,
5132 1, 1, true, true);
5133 }
5134 }
5135
5136 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5137 lp_build_const_int32(gallivm, 1));
5138
5139 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5140
5141 /* Signal vertex emission */
5142 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5143 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5144 if (!use_kill)
5145 lp_build_endif(&if_state);
5146 }
5147
5148 /* Cut one primitive from the geometry shader */
5149 static void si_llvm_emit_primitive(
5150 const struct lp_build_tgsi_action *action,
5151 struct lp_build_tgsi_context *bld_base,
5152 struct lp_build_emit_data *emit_data)
5153 {
5154 struct si_shader_context *ctx = si_shader_context(bld_base);
5155 unsigned stream;
5156
5157 /* Signal primitive cut */
5158 stream = si_llvm_get_stream(bld_base, emit_data);
5159 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5160 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5161 }
5162
5163 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5164 struct lp_build_tgsi_context *bld_base,
5165 struct lp_build_emit_data *emit_data)
5166 {
5167 struct si_shader_context *ctx = si_shader_context(bld_base);
5168 struct gallivm_state *gallivm = bld_base->base.gallivm;
5169
5170 /* SI only (thanks to a hw bug workaround):
5171 * The real barrier instruction isn’t needed, because an entire patch
5172 * always fits into a single wave.
5173 */
5174 if (HAVE_LLVM >= 0x0309 &&
5175 ctx->screen->b.chip_class == SI &&
5176 ctx->type == PIPE_SHADER_TESS_CTRL) {
5177 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5178 return;
5179 }
5180
5181 lp_build_intrinsic(gallivm->builder,
5182 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5183 : "llvm.AMDGPU.barrier.local",
5184 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
5185 }
5186
5187 static const struct lp_build_tgsi_action tex_action = {
5188 .fetch_args = tex_fetch_args,
5189 .emit = build_tex_intrinsic,
5190 };
5191
5192 static const struct lp_build_tgsi_action interp_action = {
5193 .fetch_args = interp_fetch_args,
5194 .emit = build_interp_intrinsic,
5195 };
5196
5197 static void si_create_function(struct si_shader_context *ctx,
5198 const char *name,
5199 LLVMTypeRef *returns, unsigned num_returns,
5200 LLVMTypeRef *params, unsigned num_params,
5201 int last_sgpr)
5202 {
5203 int i;
5204
5205 si_llvm_create_func(ctx, name, returns, num_returns,
5206 params, num_params);
5207 si_llvm_shader_type(ctx->main_fn, ctx->type);
5208 ctx->return_value = LLVMGetUndef(ctx->return_type);
5209
5210 for (i = 0; i <= last_sgpr; ++i) {
5211 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5212
5213 /* The combination of:
5214 * - ByVal
5215 * - dereferenceable
5216 * - invariant.load
5217 * allows the optimization passes to move loads and reduces
5218 * SGPR spilling significantly.
5219 */
5220 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5221 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5222 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5223 lp_add_attr_dereferenceable(P, UINT64_MAX);
5224 } else
5225 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5226 }
5227
5228 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5229 "no-signed-zeros-fp-math",
5230 "true");
5231
5232 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5233 /* These were copied from some LLVM test. */
5234 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5235 "less-precise-fpmad",
5236 "true");
5237 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5238 "no-infs-fp-math",
5239 "true");
5240 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5241 "no-nans-fp-math",
5242 "true");
5243 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5244 "unsafe-fp-math",
5245 "true");
5246 }
5247 }
5248
5249 static void declare_streamout_params(struct si_shader_context *ctx,
5250 struct pipe_stream_output_info *so,
5251 LLVMTypeRef *params, LLVMTypeRef i32,
5252 unsigned *num_params)
5253 {
5254 int i;
5255
5256 /* Streamout SGPRs. */
5257 if (so->num_outputs) {
5258 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5259 params[ctx->param_streamout_config = (*num_params)++] = i32;
5260 else
5261 ctx->param_streamout_config = *num_params - 1;
5262
5263 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5264 }
5265 /* A streamout buffer offset is loaded if the stride is non-zero. */
5266 for (i = 0; i < 4; i++) {
5267 if (!so->stride[i])
5268 continue;
5269
5270 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5271 }
5272 }
5273
5274 static unsigned llvm_get_type_size(LLVMTypeRef type)
5275 {
5276 LLVMTypeKind kind = LLVMGetTypeKind(type);
5277
5278 switch (kind) {
5279 case LLVMIntegerTypeKind:
5280 return LLVMGetIntTypeWidth(type) / 8;
5281 case LLVMFloatTypeKind:
5282 return 4;
5283 case LLVMPointerTypeKind:
5284 return 8;
5285 case LLVMVectorTypeKind:
5286 return LLVMGetVectorSize(type) *
5287 llvm_get_type_size(LLVMGetElementType(type));
5288 case LLVMArrayTypeKind:
5289 return LLVMGetArrayLength(type) *
5290 llvm_get_type_size(LLVMGetElementType(type));
5291 default:
5292 assert(0);
5293 return 0;
5294 }
5295 }
5296
5297 static void declare_tess_lds(struct si_shader_context *ctx)
5298 {
5299 struct gallivm_state *gallivm = &ctx->gallivm;
5300 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5301 struct lp_build_context *uint = &bld_base->uint_bld;
5302
5303 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5304 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5305 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5306 "tess_lds");
5307 }
5308
5309 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5310 {
5311 const unsigned *properties = shader->selector->info.properties;
5312 unsigned max_work_group_size =
5313 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5314 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5315 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5316
5317 if (!max_work_group_size) {
5318 /* This is a variable group size compute shader,
5319 * compile it for the maximum possible group size.
5320 */
5321 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5322 }
5323 return max_work_group_size;
5324 }
5325
5326 static void create_function(struct si_shader_context *ctx)
5327 {
5328 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5329 struct gallivm_state *gallivm = bld_base->base.gallivm;
5330 struct si_shader *shader = ctx->shader;
5331 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5332 LLVMTypeRef returns[16+32*4];
5333 unsigned i, last_sgpr, num_params, num_return_sgprs;
5334 unsigned num_returns = 0;
5335 unsigned num_prolog_vgprs = 0;
5336
5337 v3i32 = LLVMVectorType(ctx->i32, 3);
5338
5339 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5340 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5341 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5342 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5343 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5344
5345 switch (ctx->type) {
5346 case PIPE_SHADER_VERTEX:
5347 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5348 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5349 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5350 params[SI_PARAM_DRAWID] = ctx->i32;
5351 num_params = SI_PARAM_DRAWID+1;
5352
5353 if (shader->key.as_es) {
5354 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5355 } else if (shader->key.as_ls) {
5356 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5357 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5358 } else {
5359 if (shader->is_gs_copy_shader) {
5360 num_params = SI_PARAM_RW_BUFFERS+1;
5361 } else {
5362 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5363 num_params = SI_PARAM_VS_STATE_BITS+1;
5364 }
5365
5366 /* The locations of the other parameters are assigned dynamically. */
5367 declare_streamout_params(ctx, &shader->selector->so,
5368 params, ctx->i32, &num_params);
5369 }
5370
5371 last_sgpr = num_params-1;
5372
5373 /* VGPRs */
5374 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5375 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5376 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5377 params[ctx->param_instance_id = num_params++] = ctx->i32;
5378
5379 if (!shader->is_gs_copy_shader) {
5380 /* Vertex load indices. */
5381 ctx->param_vertex_index0 = num_params;
5382
5383 for (i = 0; i < shader->selector->info.num_inputs; i++)
5384 params[num_params++] = ctx->i32;
5385
5386 num_prolog_vgprs += shader->selector->info.num_inputs;
5387
5388 /* PrimitiveID output. */
5389 if (!shader->key.as_es && !shader->key.as_ls)
5390 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5391 returns[num_returns++] = ctx->f32;
5392 }
5393 break;
5394
5395 case PIPE_SHADER_TESS_CTRL:
5396 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5397 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5398 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5399 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5400 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5401 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5402 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5403
5404 /* VGPRs */
5405 params[SI_PARAM_PATCH_ID] = ctx->i32;
5406 params[SI_PARAM_REL_IDS] = ctx->i32;
5407 num_params = SI_PARAM_REL_IDS+1;
5408
5409 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5410 * placed after the user SGPRs.
5411 */
5412 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5413 returns[num_returns++] = ctx->i32; /* SGPRs */
5414
5415 for (i = 0; i < 3; i++)
5416 returns[num_returns++] = ctx->f32; /* VGPRs */
5417 break;
5418
5419 case PIPE_SHADER_TESS_EVAL:
5420 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5421 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5422
5423 if (shader->key.as_es) {
5424 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5425 params[num_params++] = ctx->i32;
5426 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5427 } else {
5428 params[num_params++] = ctx->i32;
5429 declare_streamout_params(ctx, &shader->selector->so,
5430 params, ctx->i32, &num_params);
5431 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5432 }
5433 last_sgpr = num_params - 1;
5434
5435 /* VGPRs */
5436 params[ctx->param_tes_u = num_params++] = ctx->f32;
5437 params[ctx->param_tes_v = num_params++] = ctx->f32;
5438 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5439 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5440
5441 /* PrimitiveID output. */
5442 if (!shader->key.as_es)
5443 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5444 returns[num_returns++] = ctx->f32;
5445 break;
5446
5447 case PIPE_SHADER_GEOMETRY:
5448 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5449 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5450 last_sgpr = SI_PARAM_GS_WAVE_ID;
5451
5452 /* VGPRs */
5453 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5454 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5455 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5456 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5457 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5458 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5459 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5460 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5461 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5462 break;
5463
5464 case PIPE_SHADER_FRAGMENT:
5465 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5466 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5467 last_sgpr = SI_PARAM_PRIM_MASK;
5468 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5469 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5470 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5471 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5472 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5473 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5474 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5475 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5476 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5477 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5478 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5479 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5480 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5481 shader->info.face_vgpr_index = 20;
5482 params[SI_PARAM_ANCILLARY] = ctx->i32;
5483 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5484 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5485 num_params = SI_PARAM_POS_FIXED_PT+1;
5486
5487 /* Color inputs from the prolog. */
5488 if (shader->selector->info.colors_read) {
5489 unsigned num_color_elements =
5490 util_bitcount(shader->selector->info.colors_read);
5491
5492 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5493 for (i = 0; i < num_color_elements; i++)
5494 params[num_params++] = ctx->f32;
5495
5496 num_prolog_vgprs += num_color_elements;
5497 }
5498
5499 /* Outputs for the epilog. */
5500 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5501 num_returns =
5502 num_return_sgprs +
5503 util_bitcount(shader->selector->info.colors_written) * 4 +
5504 shader->selector->info.writes_z +
5505 shader->selector->info.writes_stencil +
5506 shader->selector->info.writes_samplemask +
5507 1 /* SampleMaskIn */;
5508
5509 num_returns = MAX2(num_returns,
5510 num_return_sgprs +
5511 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5512
5513 for (i = 0; i < num_return_sgprs; i++)
5514 returns[i] = ctx->i32;
5515 for (; i < num_returns; i++)
5516 returns[i] = ctx->f32;
5517 break;
5518
5519 case PIPE_SHADER_COMPUTE:
5520 params[SI_PARAM_GRID_SIZE] = v3i32;
5521 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5522 params[SI_PARAM_BLOCK_ID] = v3i32;
5523 last_sgpr = SI_PARAM_BLOCK_ID;
5524
5525 params[SI_PARAM_THREAD_ID] = v3i32;
5526 num_params = SI_PARAM_THREAD_ID + 1;
5527 break;
5528 default:
5529 assert(0 && "unimplemented shader");
5530 return;
5531 }
5532
5533 assert(num_params <= ARRAY_SIZE(params));
5534
5535 si_create_function(ctx, "main", returns, num_returns, params,
5536 num_params, last_sgpr);
5537
5538 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5539 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5540 ctx->separate_prolog) {
5541 si_llvm_add_attribute(ctx->main_fn,
5542 "InitialPSInputAddr",
5543 S_0286D0_PERSP_SAMPLE_ENA(1) |
5544 S_0286D0_PERSP_CENTER_ENA(1) |
5545 S_0286D0_PERSP_CENTROID_ENA(1) |
5546 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5547 S_0286D0_LINEAR_CENTER_ENA(1) |
5548 S_0286D0_LINEAR_CENTROID_ENA(1) |
5549 S_0286D0_FRONT_FACE_ENA(1) |
5550 S_0286D0_POS_FIXED_PT_ENA(1));
5551 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5552 si_llvm_add_attribute(ctx->main_fn,
5553 "amdgpu-max-work-group-size",
5554 si_get_max_workgroup_size(shader));
5555 }
5556
5557 shader->info.num_input_sgprs = 0;
5558 shader->info.num_input_vgprs = 0;
5559
5560 for (i = 0; i <= last_sgpr; ++i)
5561 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5562
5563 for (; i < num_params; ++i)
5564 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5565
5566 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5567 shader->info.num_input_vgprs -= num_prolog_vgprs;
5568
5569 if (!ctx->screen->has_ds_bpermute &&
5570 bld_base->info &&
5571 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5572 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5573 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5574 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5575 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5576 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5577 ctx->lds =
5578 LLVMAddGlobalInAddressSpace(gallivm->module,
5579 LLVMArrayType(ctx->i32, 64),
5580 "ddxy_lds",
5581 LOCAL_ADDR_SPACE);
5582
5583 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5584 ctx->type == PIPE_SHADER_TESS_CTRL)
5585 declare_tess_lds(ctx);
5586 }
5587
5588 /**
5589 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5590 * for later use.
5591 */
5592 static void preload_ring_buffers(struct si_shader_context *ctx)
5593 {
5594 struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
5595 LLVMBuilderRef builder = gallivm->builder;
5596
5597 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5598 SI_PARAM_RW_BUFFERS);
5599
5600 if ((ctx->type == PIPE_SHADER_VERTEX &&
5601 ctx->shader->key.as_es) ||
5602 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5603 ctx->shader->key.as_es) ||
5604 ctx->type == PIPE_SHADER_GEOMETRY) {
5605 unsigned ring =
5606 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5607 : SI_ES_RING_ESGS;
5608 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5609
5610 ctx->esgs_ring =
5611 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5612 }
5613
5614 if (ctx->shader->is_gs_copy_shader) {
5615 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5616
5617 ctx->gsvs_ring[0] =
5618 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5619 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5620 const struct si_shader_selector *sel = ctx->shader->selector;
5621 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
5622 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
5623 LLVMValueRef base_ring;
5624
5625 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5626
5627 /* The conceptual layout of the GSVS ring is
5628 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5629 * but the real memory layout is swizzled across
5630 * threads:
5631 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5632 * t16v0c0 ..
5633 * Override the buffer descriptor accordingly.
5634 */
5635 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5636 uint64_t stream_offset = 0;
5637
5638 for (unsigned stream = 0; stream < 4; ++stream) {
5639 unsigned num_components;
5640 unsigned stride;
5641 unsigned num_records;
5642 LLVMValueRef ring, tmp;
5643
5644 num_components = sel->info.num_stream_output_components[stream];
5645 if (!num_components)
5646 continue;
5647
5648 stride = 4 * num_components * sel->gs_max_out_vertices;
5649
5650 /* Limit on the stride field for <= CIK. */
5651 assert(stride < (1 << 14));
5652
5653 num_records = 64;
5654
5655 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5656 tmp = LLVMBuildExtractElement(builder, ring, uint->zero, "");
5657 tmp = LLVMBuildAdd(builder, tmp,
5658 LLVMConstInt(ctx->i64,
5659 stream_offset, 0), "");
5660 stream_offset += stride * 64;
5661
5662 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->zero, "");
5663 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5664 tmp = LLVMBuildExtractElement(builder, ring, uint->one, "");
5665 tmp = LLVMBuildOr(builder, tmp,
5666 LLVMConstInt(ctx->i32,
5667 S_008F04_STRIDE(stride) |
5668 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5669 ring = LLVMBuildInsertElement(builder, ring, tmp, uint->one, "");
5670 ring = LLVMBuildInsertElement(builder, ring,
5671 LLVMConstInt(ctx->i32, num_records, 0),
5672 LLVMConstInt(ctx->i32, 2, 0), "");
5673 ring = LLVMBuildInsertElement(builder, ring,
5674 LLVMConstInt(ctx->i32,
5675 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5676 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5677 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5678 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5679 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5680 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5681 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5682 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5683 S_008F0C_ADD_TID_ENABLE(1),
5684 0),
5685 LLVMConstInt(ctx->i32, 3, 0), "");
5686 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5687
5688 ctx->gsvs_ring[stream] = ring;
5689 }
5690 }
5691 }
5692
5693 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5694 LLVMValueRef param_rw_buffers,
5695 unsigned param_pos_fixed_pt)
5696 {
5697 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5698 struct gallivm_state *gallivm = bld_base->base.gallivm;
5699 LLVMBuilderRef builder = gallivm->builder;
5700 LLVMValueRef slot, desc, offset, row, bit, address[2];
5701
5702 /* Use the fixed-point gl_FragCoord input.
5703 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5704 * per coordinate to get the repeating effect.
5705 */
5706 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5707 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5708
5709 /* Load the buffer descriptor. */
5710 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5711 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5712
5713 /* The stipple pattern is 32x32, each row has 32 bits. */
5714 offset = LLVMBuildMul(builder, address[1],
5715 LLVMConstInt(ctx->i32, 4, 0), "");
5716 row = buffer_load_const(ctx, desc, offset);
5717 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5718 bit = LLVMBuildLShr(builder, row, address[0], "");
5719 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5720
5721 /* The intrinsic kills the thread if arg < 0. */
5722 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5723 LLVMConstReal(ctx->f32, -1), "");
5724 ac_build_kill(&ctx->ac, bit);
5725 }
5726
5727 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5728 struct si_shader_config *conf,
5729 unsigned symbol_offset)
5730 {
5731 unsigned i;
5732 const unsigned char *config =
5733 ac_shader_binary_config_start(binary, symbol_offset);
5734 bool really_needs_scratch = false;
5735
5736 /* LLVM adds SGPR spills to the scratch size.
5737 * Find out if we really need the scratch buffer.
5738 */
5739 for (i = 0; i < binary->reloc_count; i++) {
5740 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5741
5742 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5743 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5744 really_needs_scratch = true;
5745 break;
5746 }
5747 }
5748
5749 /* XXX: We may be able to emit some of these values directly rather than
5750 * extracting fields to be emitted later.
5751 */
5752
5753 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5754 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5755 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5756 switch (reg) {
5757 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5758 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5759 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5760 case R_00B848_COMPUTE_PGM_RSRC1:
5761 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5762 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5763 conf->float_mode = G_00B028_FLOAT_MODE(value);
5764 conf->rsrc1 = value;
5765 break;
5766 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5767 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5768 break;
5769 case R_00B84C_COMPUTE_PGM_RSRC2:
5770 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5771 conf->rsrc2 = value;
5772 break;
5773 case R_0286CC_SPI_PS_INPUT_ENA:
5774 conf->spi_ps_input_ena = value;
5775 break;
5776 case R_0286D0_SPI_PS_INPUT_ADDR:
5777 conf->spi_ps_input_addr = value;
5778 break;
5779 case R_0286E8_SPI_TMPRING_SIZE:
5780 case R_00B860_COMPUTE_TMPRING_SIZE:
5781 /* WAVESIZE is in units of 256 dwords. */
5782 if (really_needs_scratch)
5783 conf->scratch_bytes_per_wave =
5784 G_00B860_WAVESIZE(value) * 256 * 4;
5785 break;
5786 case 0x4: /* SPILLED_SGPRS */
5787 conf->spilled_sgprs = value;
5788 break;
5789 case 0x8: /* SPILLED_VGPRS */
5790 conf->spilled_vgprs = value;
5791 break;
5792 default:
5793 {
5794 static bool printed;
5795
5796 if (!printed) {
5797 fprintf(stderr, "Warning: LLVM emitted unknown "
5798 "config register: 0x%x\n", reg);
5799 printed = true;
5800 }
5801 }
5802 break;
5803 }
5804 }
5805
5806 if (!conf->spi_ps_input_addr)
5807 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5808 }
5809
5810 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5811 struct si_shader *shader,
5812 struct si_shader_config *config,
5813 uint64_t scratch_va)
5814 {
5815 unsigned i;
5816 uint32_t scratch_rsrc_dword0 = scratch_va;
5817 uint32_t scratch_rsrc_dword1 =
5818 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5819
5820 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5821 * correctly.
5822 */
5823 if (HAVE_LLVM >= 0x0309)
5824 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5825 else
5826 scratch_rsrc_dword1 |=
5827 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5828
5829 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5830 const struct ac_shader_reloc *reloc =
5831 &shader->binary.relocs[i];
5832 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5833 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5834 &scratch_rsrc_dword0, 4);
5835 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5836 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5837 &scratch_rsrc_dword1, 4);
5838 }
5839 }
5840 }
5841
5842 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5843 {
5844 unsigned size = shader->binary.code_size;
5845
5846 if (shader->prolog)
5847 size += shader->prolog->binary.code_size;
5848 if (shader->epilog)
5849 size += shader->epilog->binary.code_size;
5850 return size;
5851 }
5852
5853 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5854 {
5855 const struct ac_shader_binary *prolog =
5856 shader->prolog ? &shader->prolog->binary : NULL;
5857 const struct ac_shader_binary *epilog =
5858 shader->epilog ? &shader->epilog->binary : NULL;
5859 const struct ac_shader_binary *mainb = &shader->binary;
5860 unsigned bo_size = si_get_shader_binary_size(shader) +
5861 (!epilog ? mainb->rodata_size : 0);
5862 unsigned char *ptr;
5863
5864 assert(!prolog || !prolog->rodata_size);
5865 assert((!prolog && !epilog) || !mainb->rodata_size);
5866 assert(!epilog || !epilog->rodata_size);
5867
5868 r600_resource_reference(&shader->bo, NULL);
5869 shader->bo = (struct r600_resource*)
5870 pipe_buffer_create(&sscreen->b.b, 0,
5871 PIPE_USAGE_IMMUTABLE,
5872 align(bo_size, SI_CPDMA_ALIGNMENT));
5873 if (!shader->bo)
5874 return -ENOMEM;
5875
5876 /* Upload. */
5877 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5878 PIPE_TRANSFER_READ_WRITE);
5879
5880 if (prolog) {
5881 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5882 ptr += prolog->code_size;
5883 }
5884
5885 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5886 ptr += mainb->code_size;
5887
5888 if (epilog)
5889 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5890 else if (mainb->rodata_size > 0)
5891 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5892
5893 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5894 return 0;
5895 }
5896
5897 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5898 struct pipe_debug_callback *debug,
5899 const char *name, FILE *file)
5900 {
5901 char *line, *p;
5902 unsigned i, count;
5903
5904 if (binary->disasm_string) {
5905 fprintf(file, "Shader %s disassembly:\n", name);
5906 fprintf(file, "%s", binary->disasm_string);
5907
5908 if (debug && debug->debug_message) {
5909 /* Very long debug messages are cut off, so send the
5910 * disassembly one line at a time. This causes more
5911 * overhead, but on the plus side it simplifies
5912 * parsing of resulting logs.
5913 */
5914 pipe_debug_message(debug, SHADER_INFO,
5915 "Shader Disassembly Begin");
5916
5917 line = binary->disasm_string;
5918 while (*line) {
5919 p = util_strchrnul(line, '\n');
5920 count = p - line;
5921
5922 if (count) {
5923 pipe_debug_message(debug, SHADER_INFO,
5924 "%.*s", count, line);
5925 }
5926
5927 if (!*p)
5928 break;
5929 line = p + 1;
5930 }
5931
5932 pipe_debug_message(debug, SHADER_INFO,
5933 "Shader Disassembly End");
5934 }
5935 } else {
5936 fprintf(file, "Shader %s binary:\n", name);
5937 for (i = 0; i < binary->code_size; i += 4) {
5938 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5939 binary->code[i + 3], binary->code[i + 2],
5940 binary->code[i + 1], binary->code[i]);
5941 }
5942 }
5943 }
5944
5945 static void si_shader_dump_stats(struct si_screen *sscreen,
5946 struct si_shader *shader,
5947 struct pipe_debug_callback *debug,
5948 unsigned processor,
5949 FILE *file,
5950 bool check_debug_option)
5951 {
5952 struct si_shader_config *conf = &shader->config;
5953 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5954 unsigned code_size = si_get_shader_binary_size(shader);
5955 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5956 unsigned lds_per_wave = 0;
5957 unsigned max_simd_waves = 10;
5958
5959 /* Compute LDS usage for PS. */
5960 switch (processor) {
5961 case PIPE_SHADER_FRAGMENT:
5962 /* The minimum usage per wave is (num_inputs * 48). The maximum
5963 * usage is (num_inputs * 48 * 16).
5964 * We can get anything in between and it varies between waves.
5965 *
5966 * The 48 bytes per input for a single primitive is equal to
5967 * 4 bytes/component * 4 components/input * 3 points.
5968 *
5969 * Other stages don't know the size at compile time or don't
5970 * allocate LDS per wave, but instead they do it per thread group.
5971 */
5972 lds_per_wave = conf->lds_size * lds_increment +
5973 align(num_inputs * 48, lds_increment);
5974 break;
5975 case PIPE_SHADER_COMPUTE:
5976 if (shader->selector) {
5977 unsigned max_workgroup_size =
5978 si_get_max_workgroup_size(shader);
5979 lds_per_wave = (conf->lds_size * lds_increment) /
5980 DIV_ROUND_UP(max_workgroup_size, 64);
5981 }
5982 break;
5983 }
5984
5985 /* Compute the per-SIMD wave counts. */
5986 if (conf->num_sgprs) {
5987 if (sscreen->b.chip_class >= VI)
5988 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5989 else
5990 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5991 }
5992
5993 if (conf->num_vgprs)
5994 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5995
5996 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5997 * 16KB makes some SIMDs unoccupied). */
5998 if (lds_per_wave)
5999 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6000
6001 if (!check_debug_option ||
6002 r600_can_dump_shader(&sscreen->b, processor)) {
6003 if (processor == PIPE_SHADER_FRAGMENT) {
6004 fprintf(file, "*** SHADER CONFIG ***\n"
6005 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6006 "SPI_PS_INPUT_ENA = 0x%04x\n",
6007 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6008 }
6009
6010 fprintf(file, "*** SHADER STATS ***\n"
6011 "SGPRS: %d\n"
6012 "VGPRS: %d\n"
6013 "Spilled SGPRs: %d\n"
6014 "Spilled VGPRs: %d\n"
6015 "Private memory VGPRs: %d\n"
6016 "Code Size: %d bytes\n"
6017 "LDS: %d blocks\n"
6018 "Scratch: %d bytes per wave\n"
6019 "Max Waves: %d\n"
6020 "********************\n\n\n",
6021 conf->num_sgprs, conf->num_vgprs,
6022 conf->spilled_sgprs, conf->spilled_vgprs,
6023 conf->private_mem_vgprs, code_size,
6024 conf->lds_size, conf->scratch_bytes_per_wave,
6025 max_simd_waves);
6026 }
6027
6028 pipe_debug_message(debug, SHADER_INFO,
6029 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6030 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6031 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6032 conf->num_sgprs, conf->num_vgprs, code_size,
6033 conf->lds_size, conf->scratch_bytes_per_wave,
6034 max_simd_waves, conf->spilled_sgprs,
6035 conf->spilled_vgprs, conf->private_mem_vgprs);
6036 }
6037
6038 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6039 {
6040 switch (processor) {
6041 case PIPE_SHADER_VERTEX:
6042 if (shader->key.as_es)
6043 return "Vertex Shader as ES";
6044 else if (shader->key.as_ls)
6045 return "Vertex Shader as LS";
6046 else
6047 return "Vertex Shader as VS";
6048 case PIPE_SHADER_TESS_CTRL:
6049 return "Tessellation Control Shader";
6050 case PIPE_SHADER_TESS_EVAL:
6051 if (shader->key.as_es)
6052 return "Tessellation Evaluation Shader as ES";
6053 else
6054 return "Tessellation Evaluation Shader as VS";
6055 case PIPE_SHADER_GEOMETRY:
6056 if (shader->is_gs_copy_shader)
6057 return "GS Copy Shader as VS";
6058 else
6059 return "Geometry Shader";
6060 case PIPE_SHADER_FRAGMENT:
6061 return "Pixel Shader";
6062 case PIPE_SHADER_COMPUTE:
6063 return "Compute Shader";
6064 default:
6065 return "Unknown Shader";
6066 }
6067 }
6068
6069 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6070 struct pipe_debug_callback *debug, unsigned processor,
6071 FILE *file, bool check_debug_option)
6072 {
6073 if (!check_debug_option ||
6074 r600_can_dump_shader(&sscreen->b, processor))
6075 si_dump_shader_key(processor, &shader->key, file);
6076
6077 if (!check_debug_option && shader->binary.llvm_ir_string) {
6078 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6079 si_get_shader_name(shader, processor));
6080 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6081 }
6082
6083 if (!check_debug_option ||
6084 (r600_can_dump_shader(&sscreen->b, processor) &&
6085 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6086 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6087
6088 if (shader->prolog)
6089 si_shader_dump_disassembly(&shader->prolog->binary,
6090 debug, "prolog", file);
6091
6092 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6093
6094 if (shader->epilog)
6095 si_shader_dump_disassembly(&shader->epilog->binary,
6096 debug, "epilog", file);
6097 fprintf(file, "\n");
6098 }
6099
6100 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6101 check_debug_option);
6102 }
6103
6104 int si_compile_llvm(struct si_screen *sscreen,
6105 struct ac_shader_binary *binary,
6106 struct si_shader_config *conf,
6107 LLVMTargetMachineRef tm,
6108 LLVMModuleRef mod,
6109 struct pipe_debug_callback *debug,
6110 unsigned processor,
6111 const char *name)
6112 {
6113 int r = 0;
6114 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6115
6116 if (r600_can_dump_shader(&sscreen->b, processor)) {
6117 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6118
6119 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6120 fprintf(stderr, "%s LLVM IR:\n\n", name);
6121 ac_dump_module(mod);
6122 fprintf(stderr, "\n");
6123 }
6124 }
6125
6126 if (sscreen->record_llvm_ir) {
6127 char *ir = LLVMPrintModuleToString(mod);
6128 binary->llvm_ir_string = strdup(ir);
6129 LLVMDisposeMessage(ir);
6130 }
6131
6132 if (!si_replace_shader(count, binary)) {
6133 r = si_llvm_compile(mod, binary, tm, debug);
6134 if (r)
6135 return r;
6136 }
6137
6138 si_shader_binary_read_config(binary, conf, 0);
6139
6140 /* Enable 64-bit and 16-bit denormals, because there is no performance
6141 * cost.
6142 *
6143 * If denormals are enabled, all floating-point output modifiers are
6144 * ignored.
6145 *
6146 * Don't enable denormals for 32-bit floats, because:
6147 * - Floating-point output modifiers would be ignored by the hw.
6148 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6149 * have to stop using those.
6150 * - SI & CI would be very slow.
6151 */
6152 conf->float_mode |= V_00B028_FP_64_DENORMS;
6153
6154 FREE(binary->config);
6155 FREE(binary->global_symbol_offsets);
6156 binary->config = NULL;
6157 binary->global_symbol_offsets = NULL;
6158
6159 /* Some shaders can't have rodata because their binaries can be
6160 * concatenated.
6161 */
6162 if (binary->rodata_size &&
6163 (processor == PIPE_SHADER_VERTEX ||
6164 processor == PIPE_SHADER_TESS_CTRL ||
6165 processor == PIPE_SHADER_TESS_EVAL ||
6166 processor == PIPE_SHADER_FRAGMENT)) {
6167 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6168 return -EINVAL;
6169 }
6170
6171 return r;
6172 }
6173
6174 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6175 {
6176 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6177 LLVMBuildRetVoid(ctx->gallivm.builder);
6178 else
6179 LLVMBuildRet(ctx->gallivm.builder, ret);
6180 }
6181
6182 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6183 struct si_shader *
6184 si_generate_gs_copy_shader(struct si_screen *sscreen,
6185 LLVMTargetMachineRef tm,
6186 struct si_shader_selector *gs_selector,
6187 struct pipe_debug_callback *debug)
6188 {
6189 struct si_shader_context ctx;
6190 struct si_shader *shader;
6191 struct gallivm_state *gallivm = &ctx.gallivm;
6192 LLVMBuilderRef builder;
6193 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6194 struct lp_build_context *uint = &bld_base->uint_bld;
6195 struct si_shader_output_values *outputs;
6196 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6197 int i, r;
6198
6199 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6200
6201 if (!outputs)
6202 return NULL;
6203
6204 shader = CALLOC_STRUCT(si_shader);
6205 if (!shader) {
6206 FREE(outputs);
6207 return NULL;
6208 }
6209
6210
6211 shader->selector = gs_selector;
6212 shader->is_gs_copy_shader = true;
6213
6214 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6215 ctx.type = PIPE_SHADER_VERTEX;
6216
6217 builder = gallivm->builder;
6218
6219 create_function(&ctx);
6220 preload_ring_buffers(&ctx);
6221
6222 LLVMValueRef voffset =
6223 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6224 ctx.param_vertex_id), 4);
6225
6226 /* Fetch the vertex stream ID.*/
6227 LLVMValueRef stream_id;
6228
6229 if (gs_selector->so.num_outputs)
6230 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6231 else
6232 stream_id = uint->zero;
6233
6234 /* Fill in output information. */
6235 for (i = 0; i < gsinfo->num_outputs; ++i) {
6236 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6237 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6238
6239 for (int chan = 0; chan < 4; chan++) {
6240 outputs[i].vertex_stream[chan] =
6241 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6242 }
6243 }
6244
6245 LLVMBasicBlockRef end_bb;
6246 LLVMValueRef switch_inst;
6247
6248 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6249 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6250
6251 for (int stream = 0; stream < 4; stream++) {
6252 LLVMBasicBlockRef bb;
6253 unsigned offset;
6254
6255 if (!gsinfo->num_stream_output_components[stream])
6256 continue;
6257
6258 if (stream > 0 && !gs_selector->so.num_outputs)
6259 continue;
6260
6261 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6262 LLVMAddCase(switch_inst, lp_build_const_int32(gallivm, stream), bb);
6263 LLVMPositionBuilderAtEnd(builder, bb);
6264
6265 /* Fetch vertex data from GSVS ring */
6266 offset = 0;
6267 for (i = 0; i < gsinfo->num_outputs; ++i) {
6268 for (unsigned chan = 0; chan < 4; chan++) {
6269 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6270 outputs[i].vertex_stream[chan] != stream) {
6271 outputs[i].values[chan] = ctx.bld_base.base.undef;
6272 continue;
6273 }
6274
6275 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6276 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6277 offset++;
6278
6279 outputs[i].values[chan] =
6280 ac_build_buffer_load(&ctx.ac,
6281 ctx.gsvs_ring[0], 1,
6282 uint->zero, voffset,
6283 soffset, 0, 1, 1, true);
6284 }
6285 }
6286
6287 /* Streamout and exports. */
6288 if (gs_selector->so.num_outputs) {
6289 si_llvm_emit_streamout(&ctx, outputs,
6290 gsinfo->num_outputs,
6291 stream);
6292 }
6293
6294 if (stream == 0)
6295 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6296
6297 LLVMBuildBr(builder, end_bb);
6298 }
6299
6300 LLVMPositionBuilderAtEnd(builder, end_bb);
6301
6302 LLVMBuildRetVoid(gallivm->builder);
6303
6304 /* Dump LLVM IR before any optimization passes */
6305 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6306 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6307 ac_dump_module(bld_base->base.gallivm->module);
6308
6309 si_llvm_finalize_module(&ctx,
6310 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6311
6312 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6313 &ctx.shader->config, ctx.tm,
6314 bld_base->base.gallivm->module,
6315 debug, PIPE_SHADER_GEOMETRY,
6316 "GS Copy Shader");
6317 if (!r) {
6318 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6319 fprintf(stderr, "GS Copy Shader:\n");
6320 si_shader_dump(sscreen, ctx.shader, debug,
6321 PIPE_SHADER_GEOMETRY, stderr, true);
6322 r = si_shader_binary_upload(sscreen, ctx.shader);
6323 }
6324
6325 si_llvm_dispose(&ctx);
6326
6327 FREE(outputs);
6328
6329 if (r != 0) {
6330 FREE(shader);
6331 shader = NULL;
6332 }
6333 return shader;
6334 }
6335
6336 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6337 FILE *f)
6338 {
6339 int i;
6340
6341 fprintf(f, "SHADER KEY\n");
6342
6343 switch (shader) {
6344 case PIPE_SHADER_VERTEX:
6345 fprintf(f, " part.vs.prolog.instance_divisors = {");
6346 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6347 fprintf(f, !i ? "%u" : ", %u",
6348 key->part.vs.prolog.instance_divisors[i]);
6349 fprintf(f, "}\n");
6350 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6351 fprintf(f, " as_es = %u\n", key->as_es);
6352 fprintf(f, " as_ls = %u\n", key->as_ls);
6353
6354 fprintf(f, " mono.vs.fix_fetch = {");
6355 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6356 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6357 fprintf(f, "}\n");
6358 break;
6359
6360 case PIPE_SHADER_TESS_CTRL:
6361 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6362 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6363 break;
6364
6365 case PIPE_SHADER_TESS_EVAL:
6366 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6367 fprintf(f, " as_es = %u\n", key->as_es);
6368 break;
6369
6370 case PIPE_SHADER_GEOMETRY:
6371 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6372 break;
6373
6374 case PIPE_SHADER_COMPUTE:
6375 break;
6376
6377 case PIPE_SHADER_FRAGMENT:
6378 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6379 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6380 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6381 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6382 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6383 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6384 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6385 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6386 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6387 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6388 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6389 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6390 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6391 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6392 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6393 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6394 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6395 break;
6396
6397 default:
6398 assert(0);
6399 }
6400
6401 if ((shader == PIPE_SHADER_GEOMETRY ||
6402 shader == PIPE_SHADER_TESS_EVAL ||
6403 shader == PIPE_SHADER_VERTEX) &&
6404 !key->as_es && !key->as_ls) {
6405 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6406 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6407 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6408 }
6409 }
6410
6411 static void si_init_shader_ctx(struct si_shader_context *ctx,
6412 struct si_screen *sscreen,
6413 struct si_shader *shader,
6414 LLVMTargetMachineRef tm)
6415 {
6416 struct lp_build_tgsi_context *bld_base;
6417 struct lp_build_tgsi_action tmpl = {};
6418
6419 si_llvm_context_init(ctx, sscreen, shader, tm,
6420 (shader && shader->selector) ? &shader->selector->info : NULL,
6421 (shader && shader->selector) ? shader->selector->tokens : NULL);
6422
6423 bld_base = &ctx->bld_base;
6424 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6425
6426 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6427 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6428 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6429
6430 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6431 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6432 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6433 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6434 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6435 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6436 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6437 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6438 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6439 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6440 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6441 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6442 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6443 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6444
6445 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6446 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6447 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6448 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6449 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6450 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6451
6452 tmpl.fetch_args = atomic_fetch_args;
6453 tmpl.emit = atomic_emit;
6454 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6455 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6456 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6457 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6458 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6459 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6460 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6461 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6462 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6463 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6464 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6465 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6466 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6467 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6468 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6469 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6470 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6471 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6472 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6473 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6474
6475 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6476
6477 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6478 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6479 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6480 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6481
6482 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6483 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6484 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6485 }
6486
6487 #define EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
6488 #define EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
6489
6490 /* Return true if the PARAM export has been eliminated. */
6491 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6492 LLVMValueRef inst, unsigned offset)
6493 {
6494 struct si_shader *shader = ctx->shader;
6495 unsigned num_outputs = shader->selector->info.num_outputs;
6496 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6497 bool is_zero[4] = {}, is_one[4] = {};
6498
6499 for (i = 0; i < 4; i++) {
6500 LLVMBool loses_info;
6501 LLVMValueRef p = LLVMGetOperand(inst, EXP_OUT0 + i);
6502
6503 /* It's a constant expression. Undef outputs are eliminated too. */
6504 if (LLVMIsUndef(p)) {
6505 is_zero[i] = true;
6506 is_one[i] = true;
6507 } else if (LLVMIsAConstantFP(p)) {
6508 double a = LLVMConstRealGetDouble(p, &loses_info);
6509
6510 if (a == 0)
6511 is_zero[i] = true;
6512 else if (a == 1)
6513 is_one[i] = true;
6514 else
6515 return false; /* other constant */
6516 } else
6517 return false;
6518 }
6519
6520 /* Only certain combinations of 0 and 1 can be eliminated. */
6521 if (is_zero[0] && is_zero[1] && is_zero[2])
6522 default_val = is_zero[3] ? 0 : 1;
6523 else if (is_one[0] && is_one[1] && is_one[2])
6524 default_val = is_zero[3] ? 2 : 3;
6525 else
6526 return false;
6527
6528 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6529 LLVMInstructionEraseFromParent(inst);
6530
6531 /* Change OFFSET to DEFAULT_VAL. */
6532 for (i = 0; i < num_outputs; i++) {
6533 if (shader->info.vs_output_param_offset[i] == offset) {
6534 shader->info.vs_output_param_offset[i] =
6535 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6536 break;
6537 }
6538 }
6539 return true;
6540 }
6541
6542 struct si_vs_exports {
6543 unsigned num;
6544 unsigned offset[SI_MAX_VS_OUTPUTS];
6545 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6546 };
6547
6548 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6549 {
6550 struct si_shader *shader = ctx->shader;
6551 struct tgsi_shader_info *info = &shader->selector->info;
6552 LLVMBasicBlockRef bb;
6553 struct si_vs_exports exports;
6554 bool removed_any = false;
6555
6556 exports.num = 0;
6557
6558 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6559 ctx->type == PIPE_SHADER_COMPUTE ||
6560 shader->key.as_es ||
6561 shader->key.as_ls)
6562 return;
6563
6564 /* Process all LLVM instructions. */
6565 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6566 while (bb) {
6567 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6568
6569 while (inst) {
6570 LLVMValueRef cur = inst;
6571 inst = LLVMGetNextInstruction(inst);
6572
6573 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6574 continue;
6575
6576 LLVMValueRef callee = lp_get_called_value(cur);
6577
6578 if (!lp_is_function(callee))
6579 continue;
6580
6581 const char *name = LLVMGetValueName(callee);
6582 unsigned num_args = LLVMCountParams(callee);
6583
6584 /* Check if this is an export instruction. */
6585 if ((num_args != 9 && num_args != 8) ||
6586 (strcmp(name, "llvm.SI.export") &&
6587 strcmp(name, "llvm.amdgcn.exp.f32")))
6588 continue;
6589
6590 LLVMValueRef arg = LLVMGetOperand(cur, EXP_TARGET);
6591 unsigned target = LLVMConstIntGetZExtValue(arg);
6592
6593 if (target < V_008DFC_SQ_EXP_PARAM)
6594 continue;
6595
6596 target -= V_008DFC_SQ_EXP_PARAM;
6597
6598 /* Eliminate constant value PARAM exports. */
6599 if (si_eliminate_const_output(ctx, cur, target)) {
6600 removed_any = true;
6601 } else {
6602 exports.offset[exports.num] = target;
6603 exports.inst[exports.num] = cur;
6604 exports.num++;
6605 }
6606 }
6607 bb = LLVMGetNextBasicBlock(bb);
6608 }
6609
6610 /* Remove holes in export memory due to removed PARAM exports.
6611 * This is done by renumbering all PARAM exports.
6612 */
6613 if (removed_any) {
6614 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6615 unsigned new_count = 0;
6616 unsigned out, i;
6617
6618 /* Make a copy of the offsets. We need the old version while
6619 * we are modifying some of them. */
6620 assert(sizeof(current_offset) ==
6621 sizeof(shader->info.vs_output_param_offset));
6622 memcpy(current_offset, shader->info.vs_output_param_offset,
6623 sizeof(current_offset));
6624
6625 for (i = 0; i < exports.num; i++) {
6626 unsigned offset = exports.offset[i];
6627
6628 for (out = 0; out < info->num_outputs; out++) {
6629 if (current_offset[out] != offset)
6630 continue;
6631
6632 LLVMSetOperand(exports.inst[i], EXP_TARGET,
6633 LLVMConstInt(ctx->i32,
6634 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6635 shader->info.vs_output_param_offset[out] = new_count;
6636 new_count++;
6637 break;
6638 }
6639 }
6640 shader->info.nr_param_exports = new_count;
6641 }
6642 }
6643
6644 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6645 {
6646 ctx->shader->config.private_mem_vgprs = 0;
6647
6648 /* Process all LLVM instructions. */
6649 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6650 while (bb) {
6651 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6652
6653 while (next) {
6654 LLVMValueRef inst = next;
6655 next = LLVMGetNextInstruction(next);
6656
6657 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6658 continue;
6659
6660 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6661 /* No idea why LLVM aligns allocas to 4 elements. */
6662 unsigned alignment = LLVMGetAlignment(inst);
6663 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6664 ctx->shader->config.private_mem_vgprs += dw_size;
6665 }
6666 bb = LLVMGetNextBasicBlock(bb);
6667 }
6668 }
6669
6670 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6671 struct si_shader *shader)
6672 {
6673 struct si_shader_selector *sel = shader->selector;
6674 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6675
6676 switch (ctx->type) {
6677 case PIPE_SHADER_VERTEX:
6678 ctx->load_input = declare_input_vs;
6679 if (shader->key.as_ls)
6680 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6681 else if (shader->key.as_es)
6682 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6683 else
6684 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6685 break;
6686 case PIPE_SHADER_TESS_CTRL:
6687 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6688 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6689 bld_base->emit_store = store_output_tcs;
6690 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6691 break;
6692 case PIPE_SHADER_TESS_EVAL:
6693 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6694 if (shader->key.as_es)
6695 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6696 else
6697 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6698 break;
6699 case PIPE_SHADER_GEOMETRY:
6700 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6701 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6702 break;
6703 case PIPE_SHADER_FRAGMENT:
6704 ctx->load_input = declare_input_fs;
6705 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6706 break;
6707 case PIPE_SHADER_COMPUTE:
6708 ctx->declare_memory_region = declare_compute_memory;
6709 break;
6710 default:
6711 assert(!"Unsupported shader type");
6712 return false;
6713 }
6714
6715 create_function(ctx);
6716 preload_ring_buffers(ctx);
6717
6718 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6719 int i;
6720 for (i = 0; i < 4; i++) {
6721 ctx->gs_next_vertex[i] =
6722 lp_build_alloca(bld_base->base.gallivm,
6723 ctx->i32, "");
6724 }
6725 }
6726
6727 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6728 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6729 return false;
6730 }
6731
6732 si_llvm_build_ret(ctx, ctx->return_value);
6733 return true;
6734 }
6735
6736 /**
6737 * Compute the VS prolog key, which contains all the information needed to
6738 * build the VS prolog function, and set shader->info bits where needed.
6739 */
6740 static void si_get_vs_prolog_key(struct si_shader *shader,
6741 union si_shader_part_key *key)
6742 {
6743 struct tgsi_shader_info *info = &shader->selector->info;
6744
6745 memset(key, 0, sizeof(*key));
6746 key->vs_prolog.states = shader->key.part.vs.prolog;
6747 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6748 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6749
6750 /* Set the instanceID flag. */
6751 for (unsigned i = 0; i < info->num_inputs; i++)
6752 if (key->vs_prolog.states.instance_divisors[i])
6753 shader->info.uses_instanceid = true;
6754 }
6755
6756 /**
6757 * Compute the VS epilog key, which contains all the information needed to
6758 * build the VS epilog function, and set the PrimitiveID output offset.
6759 */
6760 static void si_get_vs_epilog_key(struct si_shader *shader,
6761 struct si_vs_epilog_bits *states,
6762 union si_shader_part_key *key)
6763 {
6764 memset(key, 0, sizeof(*key));
6765 key->vs_epilog.states = *states;
6766
6767 /* Set up the PrimitiveID output. */
6768 if (shader->key.part.vs.epilog.export_prim_id) {
6769 unsigned index = shader->selector->info.num_outputs;
6770 unsigned offset = shader->info.nr_param_exports++;
6771
6772 key->vs_epilog.prim_id_param_offset = offset;
6773 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6774 shader->info.vs_output_param_offset[index] = offset;
6775 }
6776 }
6777
6778 /**
6779 * Compute the PS prolog key, which contains all the information needed to
6780 * build the PS prolog function, and set related bits in shader->config.
6781 */
6782 static void si_get_ps_prolog_key(struct si_shader *shader,
6783 union si_shader_part_key *key,
6784 bool separate_prolog)
6785 {
6786 struct tgsi_shader_info *info = &shader->selector->info;
6787
6788 memset(key, 0, sizeof(*key));
6789 key->ps_prolog.states = shader->key.part.ps.prolog;
6790 key->ps_prolog.colors_read = info->colors_read;
6791 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6792 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6793 key->ps_prolog.wqm = info->uses_derivatives &&
6794 (key->ps_prolog.colors_read ||
6795 key->ps_prolog.states.force_persp_sample_interp ||
6796 key->ps_prolog.states.force_linear_sample_interp ||
6797 key->ps_prolog.states.force_persp_center_interp ||
6798 key->ps_prolog.states.force_linear_center_interp ||
6799 key->ps_prolog.states.bc_optimize_for_persp ||
6800 key->ps_prolog.states.bc_optimize_for_linear);
6801
6802 if (info->colors_read) {
6803 unsigned *color = shader->selector->color_attr_index;
6804
6805 if (shader->key.part.ps.prolog.color_two_side) {
6806 /* BCOLORs are stored after the last input. */
6807 key->ps_prolog.num_interp_inputs = info->num_inputs;
6808 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6809 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6810 }
6811
6812 for (unsigned i = 0; i < 2; i++) {
6813 unsigned interp = info->input_interpolate[color[i]];
6814 unsigned location = info->input_interpolate_loc[color[i]];
6815
6816 if (!(info->colors_read & (0xf << i*4)))
6817 continue;
6818
6819 key->ps_prolog.color_attr_index[i] = color[i];
6820
6821 if (shader->key.part.ps.prolog.flatshade_colors &&
6822 interp == TGSI_INTERPOLATE_COLOR)
6823 interp = TGSI_INTERPOLATE_CONSTANT;
6824
6825 switch (interp) {
6826 case TGSI_INTERPOLATE_CONSTANT:
6827 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6828 break;
6829 case TGSI_INTERPOLATE_PERSPECTIVE:
6830 case TGSI_INTERPOLATE_COLOR:
6831 /* Force the interpolation location for colors here. */
6832 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6833 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6834 if (shader->key.part.ps.prolog.force_persp_center_interp)
6835 location = TGSI_INTERPOLATE_LOC_CENTER;
6836
6837 switch (location) {
6838 case TGSI_INTERPOLATE_LOC_SAMPLE:
6839 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6840 shader->config.spi_ps_input_ena |=
6841 S_0286CC_PERSP_SAMPLE_ENA(1);
6842 break;
6843 case TGSI_INTERPOLATE_LOC_CENTER:
6844 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6845 shader->config.spi_ps_input_ena |=
6846 S_0286CC_PERSP_CENTER_ENA(1);
6847 break;
6848 case TGSI_INTERPOLATE_LOC_CENTROID:
6849 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6850 shader->config.spi_ps_input_ena |=
6851 S_0286CC_PERSP_CENTROID_ENA(1);
6852 break;
6853 default:
6854 assert(0);
6855 }
6856 break;
6857 case TGSI_INTERPOLATE_LINEAR:
6858 /* Force the interpolation location for colors here. */
6859 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6860 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6861 if (shader->key.part.ps.prolog.force_linear_center_interp)
6862 location = TGSI_INTERPOLATE_LOC_CENTER;
6863
6864 /* The VGPR assignment for non-monolithic shaders
6865 * works because InitialPSInputAddr is set on the
6866 * main shader and PERSP_PULL_MODEL is never used.
6867 */
6868 switch (location) {
6869 case TGSI_INTERPOLATE_LOC_SAMPLE:
6870 key->ps_prolog.color_interp_vgpr_index[i] =
6871 separate_prolog ? 6 : 9;
6872 shader->config.spi_ps_input_ena |=
6873 S_0286CC_LINEAR_SAMPLE_ENA(1);
6874 break;
6875 case TGSI_INTERPOLATE_LOC_CENTER:
6876 key->ps_prolog.color_interp_vgpr_index[i] =
6877 separate_prolog ? 8 : 11;
6878 shader->config.spi_ps_input_ena |=
6879 S_0286CC_LINEAR_CENTER_ENA(1);
6880 break;
6881 case TGSI_INTERPOLATE_LOC_CENTROID:
6882 key->ps_prolog.color_interp_vgpr_index[i] =
6883 separate_prolog ? 10 : 13;
6884 shader->config.spi_ps_input_ena |=
6885 S_0286CC_LINEAR_CENTROID_ENA(1);
6886 break;
6887 default:
6888 assert(0);
6889 }
6890 break;
6891 default:
6892 assert(0);
6893 }
6894 }
6895 }
6896 }
6897
6898 /**
6899 * Check whether a PS prolog is required based on the key.
6900 */
6901 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6902 {
6903 return key->ps_prolog.colors_read ||
6904 key->ps_prolog.states.force_persp_sample_interp ||
6905 key->ps_prolog.states.force_linear_sample_interp ||
6906 key->ps_prolog.states.force_persp_center_interp ||
6907 key->ps_prolog.states.force_linear_center_interp ||
6908 key->ps_prolog.states.bc_optimize_for_persp ||
6909 key->ps_prolog.states.bc_optimize_for_linear ||
6910 key->ps_prolog.states.poly_stipple;
6911 }
6912
6913 /**
6914 * Compute the PS epilog key, which contains all the information needed to
6915 * build the PS epilog function.
6916 */
6917 static void si_get_ps_epilog_key(struct si_shader *shader,
6918 union si_shader_part_key *key)
6919 {
6920 struct tgsi_shader_info *info = &shader->selector->info;
6921 memset(key, 0, sizeof(*key));
6922 key->ps_epilog.colors_written = info->colors_written;
6923 key->ps_epilog.writes_z = info->writes_z;
6924 key->ps_epilog.writes_stencil = info->writes_stencil;
6925 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6926 key->ps_epilog.states = shader->key.part.ps.epilog;
6927 }
6928
6929 /**
6930 * Build the GS prolog function. Rotate the input vertices for triangle strips
6931 * with adjacency.
6932 */
6933 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6934 union si_shader_part_key *key)
6935 {
6936 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6937 const unsigned num_vgprs = 8;
6938 struct gallivm_state *gallivm = &ctx->gallivm;
6939 LLVMBuilderRef builder = gallivm->builder;
6940 LLVMTypeRef params[32];
6941 LLVMTypeRef returns[32];
6942 LLVMValueRef func, ret;
6943
6944 for (unsigned i = 0; i < num_sgprs; ++i) {
6945 params[i] = ctx->i32;
6946 returns[i] = ctx->i32;
6947 }
6948
6949 for (unsigned i = 0; i < num_vgprs; ++i) {
6950 params[num_sgprs + i] = ctx->i32;
6951 returns[num_sgprs + i] = ctx->f32;
6952 }
6953
6954 /* Create the function. */
6955 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6956 params, num_sgprs + num_vgprs, num_sgprs - 1);
6957 func = ctx->main_fn;
6958
6959 /* Copy inputs to outputs. This should be no-op, as the registers match,
6960 * but it will prevent the compiler from overwriting them unintentionally.
6961 */
6962 ret = ctx->return_value;
6963 for (unsigned i = 0; i < num_sgprs; i++) {
6964 LLVMValueRef p = LLVMGetParam(func, i);
6965 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6966 }
6967 for (unsigned i = 0; i < num_vgprs; i++) {
6968 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6969 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6970 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6971 }
6972
6973 if (key->gs_prolog.states.tri_strip_adj_fix) {
6974 /* Remap the input vertices for every other primitive. */
6975 const unsigned vtx_params[6] = {
6976 num_sgprs,
6977 num_sgprs + 1,
6978 num_sgprs + 3,
6979 num_sgprs + 4,
6980 num_sgprs + 5,
6981 num_sgprs + 6
6982 };
6983 LLVMValueRef prim_id, rotate;
6984
6985 prim_id = LLVMGetParam(func, num_sgprs + 2);
6986 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6987
6988 for (unsigned i = 0; i < 6; ++i) {
6989 LLVMValueRef base, rotated, actual;
6990 base = LLVMGetParam(func, vtx_params[i]);
6991 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
6992 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
6993 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
6994 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
6995 }
6996 }
6997
6998 LLVMBuildRet(builder, ret);
6999 }
7000
7001 /**
7002 * Given a list of shader part functions, build a wrapper function that
7003 * runs them in sequence to form a monolithic shader.
7004 */
7005 static void si_build_wrapper_function(struct si_shader_context *ctx,
7006 LLVMValueRef *parts,
7007 unsigned num_parts,
7008 unsigned main_part)
7009 {
7010 struct gallivm_state *gallivm = &ctx->gallivm;
7011 LLVMBuilderRef builder = ctx->gallivm.builder;
7012 /* PS epilog has one arg per color component */
7013 LLVMTypeRef param_types[48];
7014 LLVMValueRef out[48];
7015 LLVMTypeRef function_type;
7016 unsigned num_params;
7017 unsigned num_out;
7018 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7019 unsigned num_sgprs, num_vgprs;
7020 unsigned last_sgpr_param;
7021 unsigned gprs;
7022
7023 for (unsigned i = 0; i < num_parts; ++i) {
7024 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7025 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7026 }
7027
7028 /* The parameters of the wrapper function correspond to those of the
7029 * first part in terms of SGPRs and VGPRs, but we use the types of the
7030 * main part to get the right types. This is relevant for the
7031 * dereferenceable attribute on descriptor table pointers.
7032 */
7033 num_sgprs = 0;
7034 num_vgprs = 0;
7035
7036 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7037 num_params = LLVMCountParamTypes(function_type);
7038
7039 for (unsigned i = 0; i < num_params; ++i) {
7040 LLVMValueRef param = LLVMGetParam(parts[0], i);
7041
7042 if (ac_is_sgpr_param(param)) {
7043 assert(num_vgprs == 0);
7044 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7045 } else {
7046 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7047 }
7048 }
7049 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7050
7051 num_params = 0;
7052 last_sgpr_param = 0;
7053 gprs = 0;
7054 while (gprs < num_sgprs + num_vgprs) {
7055 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7056 unsigned size;
7057
7058 param_types[num_params] = LLVMTypeOf(param);
7059 if (gprs < num_sgprs)
7060 last_sgpr_param = num_params;
7061 size = llvm_get_type_size(param_types[num_params]) / 4;
7062 num_params++;
7063
7064 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7065 assert(gprs + size <= num_sgprs + num_vgprs &&
7066 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7067
7068 gprs += size;
7069 }
7070
7071 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7072
7073 /* Record the arguments of the function as if they were an output of
7074 * a previous part.
7075 */
7076 num_out = 0;
7077 num_out_sgpr = 0;
7078
7079 for (unsigned i = 0; i < num_params; ++i) {
7080 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7081 LLVMTypeRef param_type = LLVMTypeOf(param);
7082 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7083 unsigned size = llvm_get_type_size(param_type) / 4;
7084
7085 if (size == 1) {
7086 if (param_type != out_type)
7087 param = LLVMBuildBitCast(builder, param, out_type, "");
7088 out[num_out++] = param;
7089 } else {
7090 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7091
7092 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7093 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7094 param_type = ctx->i64;
7095 }
7096
7097 if (param_type != vector_type)
7098 param = LLVMBuildBitCast(builder, param, vector_type, "");
7099
7100 for (unsigned j = 0; j < size; ++j)
7101 out[num_out++] = LLVMBuildExtractElement(
7102 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7103 }
7104
7105 if (i <= last_sgpr_param)
7106 num_out_sgpr = num_out;
7107 }
7108
7109 /* Now chain the parts. */
7110 for (unsigned part = 0; part < num_parts; ++part) {
7111 LLVMValueRef in[48];
7112 LLVMValueRef ret;
7113 LLVMTypeRef ret_type;
7114 unsigned out_idx = 0;
7115
7116 num_params = LLVMCountParams(parts[part]);
7117 assert(num_params <= ARRAY_SIZE(param_types));
7118
7119 /* Derive arguments for the next part from outputs of the
7120 * previous one.
7121 */
7122 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7123 LLVMValueRef param;
7124 LLVMTypeRef param_type;
7125 bool is_sgpr;
7126 unsigned param_size;
7127 LLVMValueRef arg = NULL;
7128
7129 param = LLVMGetParam(parts[part], param_idx);
7130 param_type = LLVMTypeOf(param);
7131 param_size = llvm_get_type_size(param_type) / 4;
7132 is_sgpr = ac_is_sgpr_param(param);
7133
7134 if (is_sgpr) {
7135 #if HAVE_LLVM < 0x0400
7136 LLVMRemoveAttribute(param, LLVMByValAttribute);
7137 #else
7138 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7139 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7140 #endif
7141 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7142 }
7143
7144 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7145 assert(is_sgpr || out_idx >= num_out_sgpr);
7146
7147 if (param_size == 1)
7148 arg = out[out_idx];
7149 else
7150 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7151
7152 if (LLVMTypeOf(arg) != param_type) {
7153 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7154 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7155 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7156 } else {
7157 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7158 }
7159 }
7160
7161 in[param_idx] = arg;
7162 out_idx += param_size;
7163 }
7164
7165 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7166 ret_type = LLVMTypeOf(ret);
7167
7168 /* Extract the returned GPRs. */
7169 num_out = 0;
7170 num_out_sgpr = 0;
7171
7172 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7173 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7174
7175 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7176
7177 for (unsigned i = 0; i < ret_size; ++i) {
7178 LLVMValueRef val =
7179 LLVMBuildExtractValue(builder, ret, i, "");
7180
7181 out[num_out++] = val;
7182
7183 if (LLVMTypeOf(val) == ctx->i32) {
7184 assert(num_out_sgpr + 1 == num_out);
7185 num_out_sgpr = num_out;
7186 }
7187 }
7188 }
7189 }
7190
7191 LLVMBuildRetVoid(builder);
7192 }
7193
7194 int si_compile_tgsi_shader(struct si_screen *sscreen,
7195 LLVMTargetMachineRef tm,
7196 struct si_shader *shader,
7197 bool is_monolithic,
7198 struct pipe_debug_callback *debug)
7199 {
7200 struct si_shader_selector *sel = shader->selector;
7201 struct si_shader_context ctx;
7202 struct lp_build_tgsi_context *bld_base;
7203 LLVMModuleRef mod;
7204 int r = -1;
7205
7206 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7207 * conversion fails. */
7208 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7209 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7210 tgsi_dump(sel->tokens, 0);
7211 si_dump_streamout(&sel->so);
7212 }
7213
7214 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7215 ctx.separate_prolog = !is_monolithic;
7216
7217 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7218 sizeof(shader->info.vs_output_param_offset));
7219
7220 shader->info.uses_instanceid = sel->info.uses_instanceid;
7221
7222 bld_base = &ctx.bld_base;
7223 ctx.load_system_value = declare_system_value;
7224
7225 if (!si_compile_tgsi_main(&ctx, shader)) {
7226 si_llvm_dispose(&ctx);
7227 return -1;
7228 }
7229
7230 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7231 LLVMValueRef parts[3];
7232 bool need_prolog;
7233 bool need_epilog;
7234
7235 need_prolog = sel->info.num_inputs;
7236 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7237
7238 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7239
7240 if (need_prolog) {
7241 union si_shader_part_key prolog_key;
7242 si_get_vs_prolog_key(shader, &prolog_key);
7243 si_build_vs_prolog_function(&ctx, &prolog_key);
7244 parts[0] = ctx.main_fn;
7245 }
7246
7247 if (need_epilog) {
7248 union si_shader_part_key epilog_key;
7249 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7250 si_build_vs_epilog_function(&ctx, &epilog_key);
7251 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7252 }
7253
7254 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7255 need_prolog ? 1 : 0);
7256 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7257 LLVMValueRef parts[2];
7258 union si_shader_part_key epilog_key;
7259
7260 parts[0] = ctx.main_fn;
7261
7262 memset(&epilog_key, 0, sizeof(epilog_key));
7263 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7264 si_build_tcs_epilog_function(&ctx, &epilog_key);
7265 parts[1] = ctx.main_fn;
7266
7267 si_build_wrapper_function(&ctx, parts, 2, 0);
7268 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7269 !shader->key.as_es) {
7270 LLVMValueRef parts[2];
7271 union si_shader_part_key epilog_key;
7272
7273 parts[0] = ctx.main_fn;
7274
7275 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7276 si_build_vs_epilog_function(&ctx, &epilog_key);
7277 parts[1] = ctx.main_fn;
7278
7279 si_build_wrapper_function(&ctx, parts, 2, 0);
7280 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7281 LLVMValueRef parts[2];
7282 union si_shader_part_key prolog_key;
7283
7284 parts[1] = ctx.main_fn;
7285
7286 memset(&prolog_key, 0, sizeof(prolog_key));
7287 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7288 si_build_gs_prolog_function(&ctx, &prolog_key);
7289 parts[0] = ctx.main_fn;
7290
7291 si_build_wrapper_function(&ctx, parts, 2, 1);
7292 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7293 LLVMValueRef parts[3];
7294 union si_shader_part_key prolog_key;
7295 union si_shader_part_key epilog_key;
7296 bool need_prolog;
7297
7298 si_get_ps_prolog_key(shader, &prolog_key, false);
7299 need_prolog = si_need_ps_prolog(&prolog_key);
7300
7301 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7302
7303 if (need_prolog) {
7304 si_build_ps_prolog_function(&ctx, &prolog_key);
7305 parts[0] = ctx.main_fn;
7306 }
7307
7308 si_get_ps_epilog_key(shader, &epilog_key);
7309 si_build_ps_epilog_function(&ctx, &epilog_key);
7310 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7311
7312 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7313 }
7314
7315 mod = bld_base->base.gallivm->module;
7316
7317 /* Dump LLVM IR before any optimization passes */
7318 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7319 r600_can_dump_shader(&sscreen->b, ctx.type))
7320 ac_dump_module(mod);
7321
7322 si_llvm_finalize_module(&ctx,
7323 r600_extra_shader_checks(&sscreen->b, ctx.type));
7324
7325 /* Post-optimization transformations and analysis. */
7326 si_eliminate_const_vs_outputs(&ctx);
7327
7328 if ((debug && debug->debug_message) ||
7329 r600_can_dump_shader(&sscreen->b, ctx.type))
7330 si_count_scratch_private_memory(&ctx);
7331
7332 /* Compile to bytecode. */
7333 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7334 mod, debug, ctx.type, "TGSI shader");
7335 si_llvm_dispose(&ctx);
7336 if (r) {
7337 fprintf(stderr, "LLVM failed to compile shader\n");
7338 return r;
7339 }
7340
7341 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7342 * LLVM 3.9svn has this bug.
7343 */
7344 if (sel->type == PIPE_SHADER_COMPUTE) {
7345 unsigned wave_size = 64;
7346 unsigned max_vgprs = 256;
7347 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7348 unsigned max_sgprs_per_wave = 128;
7349 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7350 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7351 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7352
7353 max_vgprs = max_vgprs / min_waves_per_simd;
7354 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7355
7356 if (shader->config.num_sgprs > max_sgprs ||
7357 shader->config.num_vgprs > max_vgprs) {
7358 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7359 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7360 shader->config.num_sgprs, shader->config.num_vgprs,
7361 max_sgprs, max_vgprs);
7362
7363 /* Just terminate the process, because dependent
7364 * shaders can hang due to bad input data, but use
7365 * the env var to allow shader-db to work.
7366 */
7367 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7368 abort();
7369 }
7370 }
7371
7372 /* Add the scratch offset to input SGPRs. */
7373 if (shader->config.scratch_bytes_per_wave)
7374 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7375
7376 /* Calculate the number of fragment input VGPRs. */
7377 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7378 shader->info.num_input_vgprs = 0;
7379 shader->info.face_vgpr_index = -1;
7380
7381 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7382 shader->info.num_input_vgprs += 2;
7383 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7384 shader->info.num_input_vgprs += 2;
7385 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7386 shader->info.num_input_vgprs += 2;
7387 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7388 shader->info.num_input_vgprs += 3;
7389 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7390 shader->info.num_input_vgprs += 2;
7391 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7392 shader->info.num_input_vgprs += 2;
7393 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7394 shader->info.num_input_vgprs += 2;
7395 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7396 shader->info.num_input_vgprs += 1;
7397 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7398 shader->info.num_input_vgprs += 1;
7399 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7400 shader->info.num_input_vgprs += 1;
7401 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7402 shader->info.num_input_vgprs += 1;
7403 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7404 shader->info.num_input_vgprs += 1;
7405 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7406 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7407 shader->info.num_input_vgprs += 1;
7408 }
7409 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7410 shader->info.num_input_vgprs += 1;
7411 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7412 shader->info.num_input_vgprs += 1;
7413 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7414 shader->info.num_input_vgprs += 1;
7415 }
7416
7417 return 0;
7418 }
7419
7420 /**
7421 * Create, compile and return a shader part (prolog or epilog).
7422 *
7423 * \param sscreen screen
7424 * \param list list of shader parts of the same category
7425 * \param type shader type
7426 * \param key shader part key
7427 * \param prolog whether the part being requested is a prolog
7428 * \param tm LLVM target machine
7429 * \param debug debug callback
7430 * \param build the callback responsible for building the main function
7431 * \return non-NULL on success
7432 */
7433 static struct si_shader_part *
7434 si_get_shader_part(struct si_screen *sscreen,
7435 struct si_shader_part **list,
7436 enum pipe_shader_type type,
7437 bool prolog,
7438 union si_shader_part_key *key,
7439 LLVMTargetMachineRef tm,
7440 struct pipe_debug_callback *debug,
7441 void (*build)(struct si_shader_context *,
7442 union si_shader_part_key *),
7443 const char *name)
7444 {
7445 struct si_shader_part *result;
7446
7447 mtx_lock(&sscreen->shader_parts_mutex);
7448
7449 /* Find existing. */
7450 for (result = *list; result; result = result->next) {
7451 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7452 mtx_unlock(&sscreen->shader_parts_mutex);
7453 return result;
7454 }
7455 }
7456
7457 /* Compile a new one. */
7458 result = CALLOC_STRUCT(si_shader_part);
7459 result->key = *key;
7460
7461 struct si_shader shader = {};
7462 struct si_shader_context ctx;
7463 struct gallivm_state *gallivm = &ctx.gallivm;
7464
7465 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7466 ctx.type = type;
7467
7468 switch (type) {
7469 case PIPE_SHADER_VERTEX:
7470 break;
7471 case PIPE_SHADER_TESS_CTRL:
7472 assert(!prolog);
7473 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7474 break;
7475 case PIPE_SHADER_GEOMETRY:
7476 assert(prolog);
7477 break;
7478 case PIPE_SHADER_FRAGMENT:
7479 if (prolog)
7480 shader.key.part.ps.prolog = key->ps_prolog.states;
7481 else
7482 shader.key.part.ps.epilog = key->ps_epilog.states;
7483 break;
7484 default:
7485 unreachable("bad shader part");
7486 }
7487
7488 build(&ctx, key);
7489
7490 /* Compile. */
7491 si_llvm_finalize_module(&ctx,
7492 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7493
7494 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7495 gallivm->module, debug, ctx.type, name)) {
7496 FREE(result);
7497 result = NULL;
7498 goto out;
7499 }
7500
7501 result->next = *list;
7502 *list = result;
7503
7504 out:
7505 si_llvm_dispose(&ctx);
7506 mtx_unlock(&sscreen->shader_parts_mutex);
7507 return result;
7508 }
7509
7510 /**
7511 * Build the vertex shader prolog function.
7512 *
7513 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7514 * All inputs are returned unmodified. The vertex load indices are
7515 * stored after them, which will be used by the API VS for fetching inputs.
7516 *
7517 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7518 * input_v0,
7519 * input_v1,
7520 * input_v2,
7521 * input_v3,
7522 * (VertexID + BaseVertex),
7523 * (InstanceID + StartInstance),
7524 * (InstanceID / 2 + StartInstance)
7525 */
7526 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7527 union si_shader_part_key *key)
7528 {
7529 struct gallivm_state *gallivm = &ctx->gallivm;
7530 LLVMTypeRef *params, *returns;
7531 LLVMValueRef ret, func;
7532 int last_sgpr, num_params, num_returns, i;
7533
7534 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7535 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7536
7537 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7538 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7539 sizeof(LLVMTypeRef));
7540 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7541 key->vs_prolog.last_input + 1) *
7542 sizeof(LLVMTypeRef));
7543 num_params = 0;
7544 num_returns = 0;
7545
7546 /* Declare input and output SGPRs. */
7547 num_params = 0;
7548 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7549 params[num_params++] = ctx->i32;
7550 returns[num_returns++] = ctx->i32;
7551 }
7552 last_sgpr = num_params - 1;
7553
7554 /* 4 preloaded VGPRs (outputs must be floats) */
7555 for (i = 0; i < 4; i++) {
7556 params[num_params++] = ctx->i32;
7557 returns[num_returns++] = ctx->f32;
7558 }
7559
7560 /* Vertex load indices. */
7561 for (i = 0; i <= key->vs_prolog.last_input; i++)
7562 returns[num_returns++] = ctx->f32;
7563
7564 /* Create the function. */
7565 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7566 num_params, last_sgpr);
7567 func = ctx->main_fn;
7568
7569 /* Copy inputs to outputs. This should be no-op, as the registers match,
7570 * but it will prevent the compiler from overwriting them unintentionally.
7571 */
7572 ret = ctx->return_value;
7573 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7574 LLVMValueRef p = LLVMGetParam(func, i);
7575 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7576 }
7577 for (i = num_params - 4; i < num_params; i++) {
7578 LLVMValueRef p = LLVMGetParam(func, i);
7579 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7580 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7581 }
7582
7583 /* Compute vertex load indices from instance divisors. */
7584 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7585 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7586 LLVMValueRef index;
7587
7588 if (divisor) {
7589 /* InstanceID / Divisor + StartInstance */
7590 index = get_instance_index_for_fetch(ctx,
7591 SI_SGPR_START_INSTANCE,
7592 divisor);
7593 } else {
7594 /* VertexID + BaseVertex */
7595 index = LLVMBuildAdd(gallivm->builder,
7596 LLVMGetParam(func, ctx->param_vertex_id),
7597 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7598 }
7599
7600 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7601 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7602 num_params++, "");
7603 }
7604
7605 si_llvm_build_ret(ctx, ret);
7606 }
7607
7608 /**
7609 * Build the vertex shader epilog function. This is also used by the tessellation
7610 * evaluation shader compiled as VS.
7611 *
7612 * The input is PrimitiveID.
7613 *
7614 * If PrimitiveID is required by the pixel shader, export it.
7615 * Otherwise, do nothing.
7616 */
7617 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7618 union si_shader_part_key *key)
7619 {
7620 struct gallivm_state *gallivm = &ctx->gallivm;
7621 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7622 LLVMTypeRef params[5];
7623 int num_params, i;
7624
7625 /* Declare input VGPRs. */
7626 num_params = key->vs_epilog.states.export_prim_id ?
7627 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7628 assert(num_params <= ARRAY_SIZE(params));
7629
7630 for (i = 0; i < num_params; i++)
7631 params[i] = ctx->f32;
7632
7633 /* Create the function. */
7634 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7635
7636 /* Emit exports. */
7637 if (key->vs_epilog.states.export_prim_id) {
7638 struct lp_build_context *base = &bld_base->base;
7639 struct ac_export_args args;
7640
7641 args.enabled_channels = 0x1; /* enabled channels */
7642 args.valid_mask = 0; /* whether the EXEC mask is valid */
7643 args.done = 0; /* DONE bit */
7644 args.target = V_008DFC_SQ_EXP_PARAM +
7645 key->vs_epilog.prim_id_param_offset;
7646 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7647 args.out[0] = LLVMGetParam(ctx->main_fn,
7648 VS_EPILOG_PRIMID_LOC); /* X */
7649 args.out[1] = base->undef; /* Y */
7650 args.out[2] = base->undef; /* Z */
7651 args.out[3] = base->undef; /* W */
7652
7653 ac_build_export(&ctx->ac, &args);
7654 }
7655
7656 LLVMBuildRetVoid(gallivm->builder);
7657 }
7658
7659 /**
7660 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7661 */
7662 static bool si_get_vs_epilog(struct si_screen *sscreen,
7663 LLVMTargetMachineRef tm,
7664 struct si_shader *shader,
7665 struct pipe_debug_callback *debug,
7666 struct si_vs_epilog_bits *states)
7667 {
7668 union si_shader_part_key epilog_key;
7669
7670 si_get_vs_epilog_key(shader, states, &epilog_key);
7671
7672 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7673 PIPE_SHADER_VERTEX, true,
7674 &epilog_key, tm, debug,
7675 si_build_vs_epilog_function,
7676 "Vertex Shader Epilog");
7677 return shader->epilog != NULL;
7678 }
7679
7680 /**
7681 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7682 */
7683 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7684 LLVMTargetMachineRef tm,
7685 struct si_shader *shader,
7686 struct pipe_debug_callback *debug)
7687 {
7688 struct tgsi_shader_info *info = &shader->selector->info;
7689 union si_shader_part_key prolog_key;
7690
7691 /* Get the prolog. */
7692 si_get_vs_prolog_key(shader, &prolog_key);
7693
7694 /* The prolog is a no-op if there are no inputs. */
7695 if (info->num_inputs) {
7696 shader->prolog =
7697 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7698 PIPE_SHADER_VERTEX, true,
7699 &prolog_key, tm, debug,
7700 si_build_vs_prolog_function,
7701 "Vertex Shader Prolog");
7702 if (!shader->prolog)
7703 return false;
7704 }
7705
7706 /* Get the epilog. */
7707 if (!shader->key.as_es && !shader->key.as_ls &&
7708 !si_get_vs_epilog(sscreen, tm, shader, debug,
7709 &shader->key.part.vs.epilog))
7710 return false;
7711
7712 return true;
7713 }
7714
7715 /**
7716 * Select and compile (or reuse) TES parts (epilog).
7717 */
7718 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7719 LLVMTargetMachineRef tm,
7720 struct si_shader *shader,
7721 struct pipe_debug_callback *debug)
7722 {
7723 if (shader->key.as_es)
7724 return true;
7725
7726 /* TES compiled as VS. */
7727 return si_get_vs_epilog(sscreen, tm, shader, debug,
7728 &shader->key.part.tes.epilog);
7729 }
7730
7731 /**
7732 * Compile the TCS epilog function. This writes tesselation factors to memory
7733 * based on the output primitive type of the tesselator (determined by TES).
7734 */
7735 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7736 union si_shader_part_key *key)
7737 {
7738 struct gallivm_state *gallivm = &ctx->gallivm;
7739 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7740 LLVMTypeRef params[16];
7741 LLVMValueRef func;
7742 int last_sgpr, num_params;
7743
7744 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7745 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7746 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7747 params[SI_PARAM_SAMPLERS] = ctx->i64;
7748 params[SI_PARAM_IMAGES] = ctx->i64;
7749 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7750 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7751 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7752 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7753 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7754 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7755 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7756 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7757 num_params = last_sgpr + 1;
7758
7759 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7760 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7761 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7762
7763 /* Create the function. */
7764 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7765 declare_tess_lds(ctx);
7766 func = ctx->main_fn;
7767
7768 si_write_tess_factors(bld_base,
7769 LLVMGetParam(func, last_sgpr + 1),
7770 LLVMGetParam(func, last_sgpr + 2),
7771 LLVMGetParam(func, last_sgpr + 3));
7772
7773 LLVMBuildRetVoid(gallivm->builder);
7774 }
7775
7776 /**
7777 * Select and compile (or reuse) TCS parts (epilog).
7778 */
7779 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7780 LLVMTargetMachineRef tm,
7781 struct si_shader *shader,
7782 struct pipe_debug_callback *debug)
7783 {
7784 union si_shader_part_key epilog_key;
7785
7786 /* Get the epilog. */
7787 memset(&epilog_key, 0, sizeof(epilog_key));
7788 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7789
7790 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7791 PIPE_SHADER_TESS_CTRL, false,
7792 &epilog_key, tm, debug,
7793 si_build_tcs_epilog_function,
7794 "Tessellation Control Shader Epilog");
7795 return shader->epilog != NULL;
7796 }
7797
7798 /**
7799 * Select and compile (or reuse) GS parts (prolog).
7800 */
7801 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7802 LLVMTargetMachineRef tm,
7803 struct si_shader *shader,
7804 struct pipe_debug_callback *debug)
7805 {
7806 union si_shader_part_key prolog_key;
7807
7808 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7809 return true;
7810
7811 memset(&prolog_key, 0, sizeof(prolog_key));
7812 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7813
7814 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7815 PIPE_SHADER_GEOMETRY, true,
7816 &prolog_key, tm, debug,
7817 si_build_gs_prolog_function,
7818 "Geometry Shader Prolog");
7819 return shader->prolog != NULL;
7820 }
7821
7822 /**
7823 * Build the pixel shader prolog function. This handles:
7824 * - two-side color selection and interpolation
7825 * - overriding interpolation parameters for the API PS
7826 * - polygon stippling
7827 *
7828 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7829 * overriden by other states. (e.g. per-sample interpolation)
7830 * Interpolated colors are stored after the preloaded VGPRs.
7831 */
7832 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7833 union si_shader_part_key *key)
7834 {
7835 struct gallivm_state *gallivm = &ctx->gallivm;
7836 LLVMTypeRef *params;
7837 LLVMValueRef ret, func;
7838 int last_sgpr, num_params, num_returns, i, num_color_channels;
7839
7840 assert(si_need_ps_prolog(key));
7841
7842 /* Number of inputs + 8 color elements. */
7843 params = alloca((key->ps_prolog.num_input_sgprs +
7844 key->ps_prolog.num_input_vgprs + 8) *
7845 sizeof(LLVMTypeRef));
7846
7847 /* Declare inputs. */
7848 num_params = 0;
7849 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7850 params[num_params++] = ctx->i32;
7851 last_sgpr = num_params - 1;
7852
7853 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7854 params[num_params++] = ctx->f32;
7855
7856 /* Declare outputs (same as inputs + add colors if needed) */
7857 num_returns = num_params;
7858 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7859 for (i = 0; i < num_color_channels; i++)
7860 params[num_returns++] = ctx->f32;
7861
7862 /* Create the function. */
7863 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7864 num_params, last_sgpr);
7865 func = ctx->main_fn;
7866
7867 /* Copy inputs to outputs. This should be no-op, as the registers match,
7868 * but it will prevent the compiler from overwriting them unintentionally.
7869 */
7870 ret = ctx->return_value;
7871 for (i = 0; i < num_params; i++) {
7872 LLVMValueRef p = LLVMGetParam(func, i);
7873 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7874 }
7875
7876 /* Polygon stippling. */
7877 if (key->ps_prolog.states.poly_stipple) {
7878 /* POS_FIXED_PT is always last. */
7879 unsigned pos = key->ps_prolog.num_input_sgprs +
7880 key->ps_prolog.num_input_vgprs - 1;
7881 LLVMValueRef ptr[2], list;
7882
7883 /* Get the pointer to rw buffers. */
7884 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7885 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7886 list = lp_build_gather_values(gallivm, ptr, 2);
7887 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7888 list = LLVMBuildIntToPtr(gallivm->builder, list,
7889 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7890
7891 si_llvm_emit_polygon_stipple(ctx, list, pos);
7892 }
7893
7894 if (key->ps_prolog.states.bc_optimize_for_persp ||
7895 key->ps_prolog.states.bc_optimize_for_linear) {
7896 unsigned i, base = key->ps_prolog.num_input_sgprs;
7897 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7898
7899 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7900 * The hw doesn't compute CENTROID if the whole wave only
7901 * contains fully-covered quads.
7902 *
7903 * PRIM_MASK is after user SGPRs.
7904 */
7905 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7906 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7907 LLVMConstInt(ctx->i32, 31, 0), "");
7908 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7909 ctx->i1, "");
7910
7911 if (key->ps_prolog.states.bc_optimize_for_persp) {
7912 /* Read PERSP_CENTER. */
7913 for (i = 0; i < 2; i++)
7914 center[i] = LLVMGetParam(func, base + 2 + i);
7915 /* Read PERSP_CENTROID. */
7916 for (i = 0; i < 2; i++)
7917 centroid[i] = LLVMGetParam(func, base + 4 + i);
7918 /* Select PERSP_CENTROID. */
7919 for (i = 0; i < 2; i++) {
7920 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7921 center[i], centroid[i], "");
7922 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7923 tmp, base + 4 + i, "");
7924 }
7925 }
7926 if (key->ps_prolog.states.bc_optimize_for_linear) {
7927 /* Read LINEAR_CENTER. */
7928 for (i = 0; i < 2; i++)
7929 center[i] = LLVMGetParam(func, base + 8 + i);
7930 /* Read LINEAR_CENTROID. */
7931 for (i = 0; i < 2; i++)
7932 centroid[i] = LLVMGetParam(func, base + 10 + i);
7933 /* Select LINEAR_CENTROID. */
7934 for (i = 0; i < 2; i++) {
7935 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7936 center[i], centroid[i], "");
7937 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7938 tmp, base + 10 + i, "");
7939 }
7940 }
7941 }
7942
7943 /* Force per-sample interpolation. */
7944 if (key->ps_prolog.states.force_persp_sample_interp) {
7945 unsigned i, base = key->ps_prolog.num_input_sgprs;
7946 LLVMValueRef persp_sample[2];
7947
7948 /* Read PERSP_SAMPLE. */
7949 for (i = 0; i < 2; i++)
7950 persp_sample[i] = LLVMGetParam(func, base + i);
7951 /* Overwrite PERSP_CENTER. */
7952 for (i = 0; i < 2; i++)
7953 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7954 persp_sample[i], base + 2 + i, "");
7955 /* Overwrite PERSP_CENTROID. */
7956 for (i = 0; i < 2; i++)
7957 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7958 persp_sample[i], base + 4 + i, "");
7959 }
7960 if (key->ps_prolog.states.force_linear_sample_interp) {
7961 unsigned i, base = key->ps_prolog.num_input_sgprs;
7962 LLVMValueRef linear_sample[2];
7963
7964 /* Read LINEAR_SAMPLE. */
7965 for (i = 0; i < 2; i++)
7966 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7967 /* Overwrite LINEAR_CENTER. */
7968 for (i = 0; i < 2; i++)
7969 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7970 linear_sample[i], base + 8 + i, "");
7971 /* Overwrite LINEAR_CENTROID. */
7972 for (i = 0; i < 2; i++)
7973 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7974 linear_sample[i], base + 10 + i, "");
7975 }
7976
7977 /* Force center interpolation. */
7978 if (key->ps_prolog.states.force_persp_center_interp) {
7979 unsigned i, base = key->ps_prolog.num_input_sgprs;
7980 LLVMValueRef persp_center[2];
7981
7982 /* Read PERSP_CENTER. */
7983 for (i = 0; i < 2; i++)
7984 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7985 /* Overwrite PERSP_SAMPLE. */
7986 for (i = 0; i < 2; i++)
7987 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7988 persp_center[i], base + i, "");
7989 /* Overwrite PERSP_CENTROID. */
7990 for (i = 0; i < 2; i++)
7991 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7992 persp_center[i], base + 4 + i, "");
7993 }
7994 if (key->ps_prolog.states.force_linear_center_interp) {
7995 unsigned i, base = key->ps_prolog.num_input_sgprs;
7996 LLVMValueRef linear_center[2];
7997
7998 /* Read LINEAR_CENTER. */
7999 for (i = 0; i < 2; i++)
8000 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8001 /* Overwrite LINEAR_SAMPLE. */
8002 for (i = 0; i < 2; i++)
8003 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8004 linear_center[i], base + 6 + i, "");
8005 /* Overwrite LINEAR_CENTROID. */
8006 for (i = 0; i < 2; i++)
8007 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8008 linear_center[i], base + 10 + i, "");
8009 }
8010
8011 /* Interpolate colors. */
8012 for (i = 0; i < 2; i++) {
8013 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8014 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8015 key->ps_prolog.face_vgpr_index;
8016 LLVMValueRef interp[2], color[4];
8017 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8018
8019 if (!writemask)
8020 continue;
8021
8022 /* If the interpolation qualifier is not CONSTANT (-1). */
8023 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8024 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8025 key->ps_prolog.color_interp_vgpr_index[i];
8026
8027 /* Get the (i,j) updated by bc_optimize handling. */
8028 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8029 interp_vgpr, "");
8030 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8031 interp_vgpr + 1, "");
8032 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8033 }
8034
8035 /* Use the absolute location of the input. */
8036 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8037
8038 if (key->ps_prolog.states.color_two_side) {
8039 face = LLVMGetParam(func, face_vgpr);
8040 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8041 }
8042
8043 interp_fs_input(ctx,
8044 key->ps_prolog.color_attr_index[i],
8045 TGSI_SEMANTIC_COLOR, i,
8046 key->ps_prolog.num_interp_inputs,
8047 key->ps_prolog.colors_read, interp_ij,
8048 prim_mask, face, color);
8049
8050 while (writemask) {
8051 unsigned chan = u_bit_scan(&writemask);
8052 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8053 num_params++, "");
8054 }
8055 }
8056
8057 /* Tell LLVM to insert WQM instruction sequence when needed. */
8058 if (key->ps_prolog.wqm) {
8059 LLVMAddTargetDependentFunctionAttr(func,
8060 "amdgpu-ps-wqm-outputs", "");
8061 }
8062
8063 si_llvm_build_ret(ctx, ret);
8064 }
8065
8066 /**
8067 * Build the pixel shader epilog function. This handles everything that must be
8068 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8069 */
8070 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8071 union si_shader_part_key *key)
8072 {
8073 struct gallivm_state *gallivm = &ctx->gallivm;
8074 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8075 LLVMTypeRef params[16+8*4+3];
8076 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8077 int last_sgpr, num_params, i;
8078 struct si_ps_exports exp = {};
8079
8080 /* Declare input SGPRs. */
8081 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8082 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8083 params[SI_PARAM_SAMPLERS] = ctx->i64;
8084 params[SI_PARAM_IMAGES] = ctx->i64;
8085 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8086 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8087 last_sgpr = SI_PARAM_ALPHA_REF;
8088
8089 /* Declare input VGPRs. */
8090 num_params = (last_sgpr + 1) +
8091 util_bitcount(key->ps_epilog.colors_written) * 4 +
8092 key->ps_epilog.writes_z +
8093 key->ps_epilog.writes_stencil +
8094 key->ps_epilog.writes_samplemask;
8095
8096 num_params = MAX2(num_params,
8097 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8098
8099 assert(num_params <= ARRAY_SIZE(params));
8100
8101 for (i = last_sgpr + 1; i < num_params; i++)
8102 params[i] = ctx->f32;
8103
8104 /* Create the function. */
8105 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8106 /* Disable elimination of unused inputs. */
8107 si_llvm_add_attribute(ctx->main_fn,
8108 "InitialPSInputAddr", 0xffffff);
8109
8110 /* Process colors. */
8111 unsigned vgpr = last_sgpr + 1;
8112 unsigned colors_written = key->ps_epilog.colors_written;
8113 int last_color_export = -1;
8114
8115 /* Find the last color export. */
8116 if (!key->ps_epilog.writes_z &&
8117 !key->ps_epilog.writes_stencil &&
8118 !key->ps_epilog.writes_samplemask) {
8119 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8120
8121 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8122 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8123 /* Just set this if any of the colorbuffers are enabled. */
8124 if (spi_format &
8125 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8126 last_color_export = 0;
8127 } else {
8128 for (i = 0; i < 8; i++)
8129 if (colors_written & (1 << i) &&
8130 (spi_format >> (i * 4)) & 0xf)
8131 last_color_export = i;
8132 }
8133 }
8134
8135 while (colors_written) {
8136 LLVMValueRef color[4];
8137 int mrt = u_bit_scan(&colors_written);
8138
8139 for (i = 0; i < 4; i++)
8140 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8141
8142 si_export_mrt_color(bld_base, color, mrt,
8143 num_params - 1,
8144 mrt == last_color_export, &exp);
8145 }
8146
8147 /* Process depth, stencil, samplemask. */
8148 if (key->ps_epilog.writes_z)
8149 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8150 if (key->ps_epilog.writes_stencil)
8151 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8152 if (key->ps_epilog.writes_samplemask)
8153 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8154
8155 if (depth || stencil || samplemask)
8156 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8157 else if (last_color_export == -1)
8158 si_export_null(bld_base);
8159
8160 if (exp.num)
8161 si_emit_ps_exports(ctx, &exp);
8162
8163 /* Compile. */
8164 LLVMBuildRetVoid(gallivm->builder);
8165 }
8166
8167 /**
8168 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8169 */
8170 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8171 LLVMTargetMachineRef tm,
8172 struct si_shader *shader,
8173 struct pipe_debug_callback *debug)
8174 {
8175 union si_shader_part_key prolog_key;
8176 union si_shader_part_key epilog_key;
8177
8178 /* Get the prolog. */
8179 si_get_ps_prolog_key(shader, &prolog_key, true);
8180
8181 /* The prolog is a no-op if these aren't set. */
8182 if (si_need_ps_prolog(&prolog_key)) {
8183 shader->prolog =
8184 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8185 PIPE_SHADER_FRAGMENT, true,
8186 &prolog_key, tm, debug,
8187 si_build_ps_prolog_function,
8188 "Fragment Shader Prolog");
8189 if (!shader->prolog)
8190 return false;
8191 }
8192
8193 /* Get the epilog. */
8194 si_get_ps_epilog_key(shader, &epilog_key);
8195
8196 shader->epilog =
8197 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8198 PIPE_SHADER_FRAGMENT, false,
8199 &epilog_key, tm, debug,
8200 si_build_ps_epilog_function,
8201 "Fragment Shader Epilog");
8202 if (!shader->epilog)
8203 return false;
8204
8205 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8206 if (shader->key.part.ps.prolog.poly_stipple) {
8207 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8208 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8209 }
8210
8211 /* Set up the enable bits for per-sample shading if needed. */
8212 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8213 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8214 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8215 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8216 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8217 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8218 }
8219 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8220 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8221 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8222 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8223 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8224 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8225 }
8226 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8227 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8228 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8229 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8230 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8231 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8232 }
8233 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8234 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8235 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8236 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8237 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8238 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8239 }
8240
8241 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8242 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8243 !(shader->config.spi_ps_input_ena & 0xf)) {
8244 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8245 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8246 }
8247
8248 /* At least one pair of interpolation weights must be enabled. */
8249 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8250 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8251 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8252 }
8253
8254 /* The sample mask input is always enabled, because the API shader always
8255 * passes it through to the epilog. Disable it here if it's unused.
8256 */
8257 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8258 !shader->selector->info.reads_samplemask)
8259 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8260
8261 return true;
8262 }
8263
8264 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8265 unsigned *lds_size)
8266 {
8267 /* SPI barrier management bug:
8268 * Make sure we have at least 4k of LDS in use to avoid the bug.
8269 * It applies to workgroup sizes of more than one wavefront.
8270 */
8271 if (sscreen->b.family == CHIP_BONAIRE ||
8272 sscreen->b.family == CHIP_KABINI ||
8273 sscreen->b.family == CHIP_MULLINS)
8274 *lds_size = MAX2(*lds_size, 8);
8275 }
8276
8277 static void si_fix_resource_usage(struct si_screen *sscreen,
8278 struct si_shader *shader)
8279 {
8280 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8281
8282 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8283
8284 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8285 si_get_max_workgroup_size(shader) > 64) {
8286 si_multiwave_lds_size_workaround(sscreen,
8287 &shader->config.lds_size);
8288 }
8289 }
8290
8291 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8292 struct si_shader *shader,
8293 struct pipe_debug_callback *debug)
8294 {
8295 struct si_shader_selector *sel = shader->selector;
8296 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8297 int r;
8298
8299 /* LS, ES, VS are compiled on demand if the main part hasn't been
8300 * compiled for that stage.
8301 *
8302 * Vertex shaders are compiled on demand when a vertex fetch
8303 * workaround must be applied.
8304 */
8305 if (shader->is_monolithic) {
8306 /* Monolithic shader (compiled as a whole, has many variants,
8307 * may take a long time to compile).
8308 */
8309 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8310 if (r)
8311 return r;
8312 } else {
8313 /* The shader consists of 2-3 parts:
8314 *
8315 * - the middle part is the user shader, it has 1 variant only
8316 * and it was compiled during the creation of the shader
8317 * selector
8318 * - the prolog part is inserted at the beginning
8319 * - the epilog part is inserted at the end
8320 *
8321 * The prolog and epilog have many (but simple) variants.
8322 */
8323
8324 /* Copy the compiled TGSI shader data over. */
8325 shader->is_binary_shared = true;
8326 shader->binary = mainp->binary;
8327 shader->config = mainp->config;
8328 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8329 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8330 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8331 memcpy(shader->info.vs_output_param_offset,
8332 mainp->info.vs_output_param_offset,
8333 sizeof(mainp->info.vs_output_param_offset));
8334 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8335 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8336 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8337
8338 /* Select prologs and/or epilogs. */
8339 switch (sel->type) {
8340 case PIPE_SHADER_VERTEX:
8341 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8342 return -1;
8343 break;
8344 case PIPE_SHADER_TESS_CTRL:
8345 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8346 return -1;
8347 break;
8348 case PIPE_SHADER_TESS_EVAL:
8349 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8350 return -1;
8351 break;
8352 case PIPE_SHADER_GEOMETRY:
8353 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8354 return -1;
8355 break;
8356 case PIPE_SHADER_FRAGMENT:
8357 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8358 return -1;
8359
8360 /* Make sure we have at least as many VGPRs as there
8361 * are allocated inputs.
8362 */
8363 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8364 shader->info.num_input_vgprs);
8365 break;
8366 }
8367
8368 /* Update SGPR and VGPR counts. */
8369 if (shader->prolog) {
8370 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8371 shader->prolog->config.num_sgprs);
8372 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8373 shader->prolog->config.num_vgprs);
8374 }
8375 if (shader->epilog) {
8376 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8377 shader->epilog->config.num_sgprs);
8378 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8379 shader->epilog->config.num_vgprs);
8380 }
8381 }
8382
8383 si_fix_resource_usage(sscreen, shader);
8384 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8385 stderr, true);
8386
8387 /* Upload. */
8388 r = si_shader_binary_upload(sscreen, shader);
8389 if (r) {
8390 fprintf(stderr, "LLVM failed to upload shader\n");
8391 return r;
8392 }
8393
8394 return 0;
8395 }
8396
8397 void si_shader_destroy(struct si_shader *shader)
8398 {
8399 if (shader->scratch_bo)
8400 r600_resource_reference(&shader->scratch_bo, NULL);
8401
8402 r600_resource_reference(&shader->bo, NULL);
8403
8404 if (!shader->is_binary_shared)
8405 radeon_shader_binary_clean(&shader->binary);
8406
8407 free(shader->shader_log);
8408 }