projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: load streamout buffer descriptors before use (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "gallivm/lp_bld_misc.h"
37 #include "radeon/r600_cs.h"
38 #include "radeon/radeon_llvm.h"
39 #include "radeon/radeon_elf_util.h"
40 #include "radeon/radeon_llvm_emit.h"
41 #include "util/u_memory.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94 int param_oc_lds;
95
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
98 */
99 int param_tess_offchip;
100
101 LLVMTargetMachineRef tm;
102
103 unsigned invariant_load_md_kind;
104 unsigned range_md_kind;
105 unsigned uniform_md_kind;
106 LLVMValueRef empty_md;
107
108 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
109 LLVMValueRef lds;
110 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
111 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
112 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
113 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
114 LLVMValueRef images[SI_NUM_IMAGES];
115 LLVMValueRef esgs_ring;
116 LLVMValueRef gsvs_ring[4];
117 LLVMValueRef gs_next_vertex[4];
118 LLVMValueRef return_value;
119
120 LLVMTypeRef voidt;
121 LLVMTypeRef i1;
122 LLVMTypeRef i8;
123 LLVMTypeRef i32;
124 LLVMTypeRef i64;
125 LLVMTypeRef i128;
126 LLVMTypeRef f32;
127 LLVMTypeRef v16i8;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v4i32;
130 LLVMTypeRef v4f32;
131 LLVMTypeRef v8i32;
132
133 LLVMValueRef shared_memory;
134 };
135
136 static struct si_shader_context *si_shader_context(
137 struct lp_build_tgsi_context *bld_base)
138 {
139 return (struct si_shader_context *)bld_base;
140 }
141
142 static void si_init_shader_ctx(struct si_shader_context *ctx,
143 struct si_screen *sscreen,
144 struct si_shader *shader,
145 LLVMTargetMachineRef tm);
146
147 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
148 struct lp_build_tgsi_context *bld_base,
149 struct lp_build_emit_data *emit_data);
150
151 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
152 FILE *f);
153
154 /* Ideally pass the sample mask input to the PS epilog as v13, which
155 * is its usual location, so that the shader doesn't have to add v_mov.
156 */
157 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
158
159 /* The VS location of the PrimitiveID input is the same in the epilog,
160 * so that the main shader part doesn't have to move it.
161 */
162 #define VS_EPILOG_PRIMID_LOC 2
163
164 #define PERSPECTIVE_BASE 0
165 #define LINEAR_BASE 9
166
167 #define SAMPLE_OFFSET 0
168 #define CENTER_OFFSET 2
169 #define CENTROID_OFSET 4
170
171 #define USE_SGPR_MAX_SUFFIX_LEN 5
172 #define CONST_ADDR_SPACE 2
173 #define LOCAL_ADDR_SPACE 3
174 #define USER_SGPR_ADDR_SPACE 8
175
176
177 #define SENDMSG_GS 2
178 #define SENDMSG_GS_DONE 3
179
180 #define SENDMSG_GS_OP_NOP (0 << 4)
181 #define SENDMSG_GS_OP_CUT (1 << 4)
182 #define SENDMSG_GS_OP_EMIT (2 << 4)
183 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
184
185 /**
186 * Returns a unique index for a semantic name and index. The index must be
187 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
188 * calculated.
189 */
190 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
191 {
192 switch (semantic_name) {
193 case TGSI_SEMANTIC_POSITION:
194 return 0;
195 case TGSI_SEMANTIC_PSIZE:
196 return 1;
197 case TGSI_SEMANTIC_CLIPDIST:
198 assert(index <= 1);
199 return 2 + index;
200 case TGSI_SEMANTIC_GENERIC:
201 if (index <= 63-4)
202 return 4 + index;
203 else
204 /* same explanation as in the default statement,
205 * the only user hitting this is st/nine.
206 */
207 return 0;
208
209 /* patch indices are completely separate and thus start from 0 */
210 case TGSI_SEMANTIC_TESSOUTER:
211 return 0;
212 case TGSI_SEMANTIC_TESSINNER:
213 return 1;
214 case TGSI_SEMANTIC_PATCH:
215 return 2 + index;
216
217 default:
218 /* Don't fail here. The result of this function is only used
219 * for LS, TCS, TES, and GS, where legacy GL semantics can't
220 * occur, but this function is called for all vertex shaders
221 * before it's known whether LS will be compiled or not.
222 */
223 return 0;
224 }
225 }
226
227 /**
228 * Get the value of a shader input parameter and extract a bitfield.
229 */
230 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
231 unsigned param, unsigned rshift,
232 unsigned bitwidth)
233 {
234 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
235 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
236 param);
237
238 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
239 value = bitcast(&ctx->radeon_bld.soa.bld_base,
240 TGSI_TYPE_UNSIGNED, value);
241
242 if (rshift)
243 value = LLVMBuildLShr(gallivm->builder, value,
244 lp_build_const_int32(gallivm, rshift), "");
245
246 if (rshift + bitwidth < 32) {
247 unsigned mask = (1 << bitwidth) - 1;
248 value = LLVMBuildAnd(gallivm->builder, value,
249 lp_build_const_int32(gallivm, mask), "");
250 }
251
252 return value;
253 }
254
255 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
256 {
257 switch (ctx->type) {
258 case PIPE_SHADER_TESS_CTRL:
259 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
260
261 case PIPE_SHADER_TESS_EVAL:
262 return LLVMGetParam(ctx->radeon_bld.main_fn,
263 ctx->param_tes_rel_patch_id);
264
265 default:
266 assert(0);
267 return NULL;
268 }
269 }
270
271 /* Tessellation shaders pass outputs to the next shader using LDS.
272 *
273 * LS outputs = TCS inputs
274 * TCS outputs = TES inputs
275 *
276 * The LDS layout is:
277 * - TCS inputs for patch 0
278 * - TCS inputs for patch 1
279 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
280 * - ...
281 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
282 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
283 * - TCS outputs for patch 1
284 * - Per-patch TCS outputs for patch 1
285 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
286 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
287 * - ...
288 *
289 * All three shaders VS(LS), TCS, TES share the same LDS space.
290 */
291
292 static LLVMValueRef
293 get_tcs_in_patch_stride(struct si_shader_context *ctx)
294 {
295 if (ctx->type == PIPE_SHADER_VERTEX)
296 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
297 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
298 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
299 else {
300 assert(0);
301 return NULL;
302 }
303 }
304
305 static LLVMValueRef
306 get_tcs_out_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
309 }
310
311 static LLVMValueRef
312 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
313 {
314 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
315 unpack_param(ctx,
316 SI_PARAM_TCS_OUT_OFFSETS,
317 0, 16),
318 4);
319 }
320
321 static LLVMValueRef
322 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
323 {
324 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
325 unpack_param(ctx,
326 SI_PARAM_TCS_OUT_OFFSETS,
327 16, 16),
328 4);
329 }
330
331 static LLVMValueRef
332 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
333 {
334 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
335 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
336 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
337
338 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
339 }
340
341 static LLVMValueRef
342 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
343 {
344 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
345 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
346 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildAdd(gallivm->builder, patch0_offset,
350 LLVMBuildMul(gallivm->builder, patch_stride,
351 rel_patch_id, ""),
352 "");
353 }
354
355 static LLVMValueRef
356 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
357 {
358 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
359 LLVMValueRef patch0_patch_data_offset =
360 get_tcs_out_patch0_patch_data_offset(ctx);
361 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
362 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
363
364 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
365 LLVMBuildMul(gallivm->builder, patch_stride,
366 rel_patch_id, ""),
367 "");
368 }
369
370 static void build_indexed_store(struct si_shader_context *ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index,
372 LLVMValueRef value)
373 {
374 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
375 struct gallivm_state *gallivm = bld_base->base.gallivm;
376 LLVMValueRef indices[2], pointer;
377
378 indices[0] = bld_base->uint_bld.zero;
379 indices[1] = index;
380
381 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
382 LLVMBuildStore(gallivm->builder, value, pointer);
383 }
384
385 /**
386 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
387 * It's equivalent to doing a load from &base_ptr[index].
388 *
389 * \param base_ptr Where the array starts.
390 * \param index The element index into the array.
391 * \param uniform Whether the base_ptr and index can be assumed to be
392 * dynamically uniform
393 */
394 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
395 LLVMValueRef base_ptr, LLVMValueRef index,
396 bool uniform)
397 {
398 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
399 struct gallivm_state *gallivm = bld_base->base.gallivm;
400 LLVMValueRef indices[2], pointer;
401
402 indices[0] = bld_base->uint_bld.zero;
403 indices[1] = index;
404
405 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
406 if (uniform)
407 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
408 return LLVMBuildLoad(gallivm->builder, pointer, "");
409 }
410
411 /**
412 * Do a load from &base_ptr[index], but also add a flag that it's loading
413 * a constant from a dynamically uniform index.
414 */
415 static LLVMValueRef build_indexed_load_const(
416 struct si_shader_context *ctx,
417 LLVMValueRef base_ptr, LLVMValueRef index)
418 {
419 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
420 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
421 return result;
422 }
423
424 static LLVMValueRef get_instance_index_for_fetch(
425 struct radeon_llvm_context *radeon_bld,
426 unsigned param_start_instance, unsigned divisor)
427 {
428 struct si_shader_context *ctx =
429 si_shader_context(&radeon_bld->soa.bld_base);
430 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
431
432 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
433 ctx->param_instance_id);
434
435 /* The division must be done before START_INSTANCE is added. */
436 if (divisor > 1)
437 result = LLVMBuildUDiv(gallivm->builder, result,
438 lp_build_const_int32(gallivm, divisor), "");
439
440 return LLVMBuildAdd(gallivm->builder, result,
441 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
442 }
443
444 static void declare_input_vs(
445 struct radeon_llvm_context *radeon_bld,
446 unsigned input_index,
447 const struct tgsi_full_declaration *decl)
448 {
449 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
450 struct gallivm_state *gallivm = base->gallivm;
451 struct si_shader_context *ctx =
452 si_shader_context(&radeon_bld->soa.bld_base);
453 unsigned divisor =
454 ctx->shader->key.vs.prolog.instance_divisors[input_index];
455
456 unsigned chan;
457
458 LLVMValueRef t_list_ptr;
459 LLVMValueRef t_offset;
460 LLVMValueRef t_list;
461 LLVMValueRef attribute_offset;
462 LLVMValueRef buffer_index;
463 LLVMValueRef args[3];
464 LLVMValueRef input;
465
466 /* Load the T list */
467 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
468
469 t_offset = lp_build_const_int32(gallivm, input_index);
470
471 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
472
473 /* Build the attribute offset */
474 attribute_offset = lp_build_const_int32(gallivm, 0);
475
476 if (!ctx->is_monolithic) {
477 buffer_index = LLVMGetParam(radeon_bld->main_fn,
478 ctx->param_vertex_index0 +
479 input_index);
480 } else if (divisor) {
481 /* Build index from instance ID, start instance and divisor */
482 ctx->shader->info.uses_instanceid = true;
483 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
484 SI_PARAM_START_INSTANCE,
485 divisor);
486 } else {
487 /* Load the buffer index for vertices. */
488 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
489 ctx->param_vertex_id);
490 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
491 SI_PARAM_BASE_VERTEX);
492 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
493 }
494
495 args[0] = t_list;
496 args[1] = attribute_offset;
497 args[2] = buffer_index;
498 input = lp_build_intrinsic(gallivm->builder,
499 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
500 LLVMReadNoneAttribute);
501
502 /* Break up the vec4 into individual components */
503 for (chan = 0; chan < 4; chan++) {
504 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
505 /* XXX: Use a helper function for this. There is one in
506 * tgsi_llvm.c. */
507 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
508 LLVMBuildExtractElement(gallivm->builder,
509 input, llvm_chan, "");
510 }
511 }
512
513 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
514 unsigned swizzle)
515 {
516 struct si_shader_context *ctx = si_shader_context(bld_base);
517
518 if (swizzle > 0)
519 return bld_base->uint_bld.zero;
520
521 switch (ctx->type) {
522 case PIPE_SHADER_VERTEX:
523 return LLVMGetParam(ctx->radeon_bld.main_fn,
524 ctx->param_vs_prim_id);
525 case PIPE_SHADER_TESS_CTRL:
526 return LLVMGetParam(ctx->radeon_bld.main_fn,
527 SI_PARAM_PATCH_ID);
528 case PIPE_SHADER_TESS_EVAL:
529 return LLVMGetParam(ctx->radeon_bld.main_fn,
530 ctx->param_tes_patch_id);
531 case PIPE_SHADER_GEOMETRY:
532 return LLVMGetParam(ctx->radeon_bld.main_fn,
533 SI_PARAM_PRIMITIVE_ID);
534 default:
535 assert(0);
536 return bld_base->uint_bld.zero;
537 }
538 }
539
540 /**
541 * Return the value of tgsi_ind_register for indexing.
542 * This is the indirect index with the constant offset added to it.
543 */
544 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
545 const struct tgsi_ind_register *ind,
546 int rel_index)
547 {
548 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
549 LLVMValueRef result;
550
551 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
552 result = LLVMBuildLoad(gallivm->builder, result, "");
553 result = LLVMBuildAdd(gallivm->builder, result,
554 lp_build_const_int32(gallivm, rel_index), "");
555 return result;
556 }
557
558 /**
559 * Like get_indirect_index, but restricts the return value to a (possibly
560 * undefined) value inside [0..num).
561 */
562 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
563 const struct tgsi_ind_register *ind,
564 int rel_index, unsigned num)
565 {
566 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
567
568 /* LLVM 3.8: If indirect resource indexing is used:
569 * - SI & CIK hang
570 * - VI crashes
571 */
572 if (HAVE_LLVM <= 0x0308)
573 return LLVMGetUndef(ctx->i32);
574
575 return radeon_llvm_bound_index(&ctx->radeon_bld, result, num);
576 }
577
578
579 /**
580 * Calculate a dword address given an input or output register and a stride.
581 */
582 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
583 const struct tgsi_full_dst_register *dst,
584 const struct tgsi_full_src_register *src,
585 LLVMValueRef vertex_dw_stride,
586 LLVMValueRef base_addr)
587 {
588 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
589 struct tgsi_shader_info *info = &ctx->shader->selector->info;
590 ubyte *name, *index, *array_first;
591 int first, param;
592 struct tgsi_full_dst_register reg;
593
594 /* Set the register description. The address computation is the same
595 * for sources and destinations. */
596 if (src) {
597 reg.Register.File = src->Register.File;
598 reg.Register.Index = src->Register.Index;
599 reg.Register.Indirect = src->Register.Indirect;
600 reg.Register.Dimension = src->Register.Dimension;
601 reg.Indirect = src->Indirect;
602 reg.Dimension = src->Dimension;
603 reg.DimIndirect = src->DimIndirect;
604 } else
605 reg = *dst;
606
607 /* If the register is 2-dimensional (e.g. an array of vertices
608 * in a primitive), calculate the base address of the vertex. */
609 if (reg.Register.Dimension) {
610 LLVMValueRef index;
611
612 if (reg.Dimension.Indirect)
613 index = get_indirect_index(ctx, &reg.DimIndirect,
614 reg.Dimension.Index);
615 else
616 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
617
618 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
619 LLVMBuildMul(gallivm->builder, index,
620 vertex_dw_stride, ""), "");
621 }
622
623 /* Get information about the register. */
624 if (reg.Register.File == TGSI_FILE_INPUT) {
625 name = info->input_semantic_name;
626 index = info->input_semantic_index;
627 array_first = info->input_array_first;
628 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
629 name = info->output_semantic_name;
630 index = info->output_semantic_index;
631 array_first = info->output_array_first;
632 } else {
633 assert(0);
634 return NULL;
635 }
636
637 if (reg.Register.Indirect) {
638 /* Add the relative address of the element. */
639 LLVMValueRef ind_index;
640
641 if (reg.Indirect.ArrayID)
642 first = array_first[reg.Indirect.ArrayID];
643 else
644 first = reg.Register.Index;
645
646 ind_index = get_indirect_index(ctx, &reg.Indirect,
647 reg.Register.Index - first);
648
649 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
650 LLVMBuildMul(gallivm->builder, ind_index,
651 lp_build_const_int32(gallivm, 4), ""), "");
652
653 param = si_shader_io_get_unique_index(name[first], index[first]);
654 } else {
655 param = si_shader_io_get_unique_index(name[reg.Register.Index],
656 index[reg.Register.Index]);
657 }
658
659 /* Add the base address of the element. */
660 return LLVMBuildAdd(gallivm->builder, base_addr,
661 lp_build_const_int32(gallivm, param * 4), "");
662 }
663
664 /* The offchip buffer layout for TCS->TES is
665 *
666 * - attribute 0 of patch 0 vertex 0
667 * - attribute 0 of patch 0 vertex 1
668 * - attribute 0 of patch 0 vertex 2
669 * ...
670 * - attribute 0 of patch 1 vertex 0
671 * - attribute 0 of patch 1 vertex 1
672 * ...
673 * - attribute 1 of patch 0 vertex 0
674 * - attribute 1 of patch 0 vertex 1
675 * ...
676 * - per patch attribute 0 of patch 0
677 * - per patch attribute 0 of patch 1
678 * ...
679 *
680 * Note that every attribute has 4 components.
681 */
682 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
683 LLVMValueRef vertex_index,
684 LLVMValueRef param_index)
685 {
686 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
687 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
688 LLVMValueRef param_stride, constant16;
689
690 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
691 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
692 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
693 num_patches, "");
694
695 constant16 = lp_build_const_int32(gallivm, 16);
696 if (vertex_index) {
697 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
698 vertices_per_patch, "");
699
700 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
701 vertex_index, "");
702
703 param_stride = total_vertices;
704 } else {
705 base_addr = get_rel_patch_id(ctx);
706 param_stride = num_patches;
707 }
708
709 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
710 LLVMBuildMul(gallivm->builder, param_index,
711 param_stride, ""), "");
712
713 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
714
715 if (!vertex_index) {
716 LLVMValueRef patch_data_offset =
717 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
718
719 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
720 patch_data_offset, "");
721 }
722 return base_addr;
723 }
724
725 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
726 struct si_shader_context *ctx,
727 const struct tgsi_full_dst_register *dst,
728 const struct tgsi_full_src_register *src)
729 {
730 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
731 struct tgsi_shader_info *info = &ctx->shader->selector->info;
732 ubyte *name, *index, *array_first;
733 struct tgsi_full_src_register reg;
734 LLVMValueRef vertex_index = NULL;
735 LLVMValueRef param_index = NULL;
736 unsigned param_index_base, param_base;
737
738 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
739
740 if (reg.Register.Dimension) {
741
742 if (reg.Dimension.Indirect)
743 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
744 reg.Dimension.Index);
745 else
746 vertex_index = lp_build_const_int32(gallivm,
747 reg.Dimension.Index);
748 }
749
750 /* Get information about the register. */
751 if (reg.Register.File == TGSI_FILE_INPUT) {
752 name = info->input_semantic_name;
753 index = info->input_semantic_index;
754 array_first = info->input_array_first;
755 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
756 name = info->output_semantic_name;
757 index = info->output_semantic_index;
758 array_first = info->output_array_first;
759 } else {
760 assert(0);
761 return NULL;
762 }
763
764 if (reg.Register.Indirect) {
765 if (reg.Indirect.ArrayID)
766 param_base = array_first[reg.Indirect.ArrayID];
767 else
768 param_base = reg.Register.Index;
769
770 param_index = get_indirect_index(ctx, &reg.Indirect,
771 reg.Register.Index - param_base);
772
773 } else {
774 param_base = reg.Register.Index;
775 param_index = lp_build_const_int32(gallivm, 0);
776 }
777
778 param_index_base = si_shader_io_get_unique_index(name[param_base],
779 index[param_base]);
780
781 param_index = LLVMBuildAdd(gallivm->builder, param_index,
782 lp_build_const_int32(gallivm, param_index_base),
783 "");
784
785 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
786 }
787
788 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
789 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
790 * or v4i32 (num_channels=3,4). */
791 static void build_tbuffer_store(struct si_shader_context *ctx,
792 LLVMValueRef rsrc,
793 LLVMValueRef vdata,
794 unsigned num_channels,
795 LLVMValueRef vaddr,
796 LLVMValueRef soffset,
797 unsigned inst_offset,
798 unsigned dfmt,
799 unsigned nfmt,
800 unsigned offen,
801 unsigned idxen,
802 unsigned glc,
803 unsigned slc,
804 unsigned tfe)
805 {
806 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
807 LLVMValueRef args[] = {
808 rsrc,
809 vdata,
810 LLVMConstInt(ctx->i32, num_channels, 0),
811 vaddr,
812 soffset,
813 LLVMConstInt(ctx->i32, inst_offset, 0),
814 LLVMConstInt(ctx->i32, dfmt, 0),
815 LLVMConstInt(ctx->i32, nfmt, 0),
816 LLVMConstInt(ctx->i32, offen, 0),
817 LLVMConstInt(ctx->i32, idxen, 0),
818 LLVMConstInt(ctx->i32, glc, 0),
819 LLVMConstInt(ctx->i32, slc, 0),
820 LLVMConstInt(ctx->i32, tfe, 0)
821 };
822
823 /* The instruction offset field has 12 bits */
824 assert(offen || inst_offset < (1 << 12));
825
826 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
827 unsigned func = CLAMP(num_channels, 1, 3) - 1;
828 const char *types[] = {"i32", "v2i32", "v4i32"};
829 char name[256];
830 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
831
832 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
833 args, ARRAY_SIZE(args), 0);
834 }
835
836 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
837 LLVMValueRef rsrc,
838 LLVMValueRef vdata,
839 unsigned num_channels,
840 LLVMValueRef vaddr,
841 LLVMValueRef soffset,
842 unsigned inst_offset)
843 {
844 static unsigned dfmt[] = {
845 V_008F0C_BUF_DATA_FORMAT_32,
846 V_008F0C_BUF_DATA_FORMAT_32_32,
847 V_008F0C_BUF_DATA_FORMAT_32_32_32,
848 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
849 };
850 assert(num_channels >= 1 && num_channels <= 4);
851
852 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
853 inst_offset, dfmt[num_channels-1],
854 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
855 }
856
857 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
858 LLVMValueRef rsrc,
859 int num_channels,
860 LLVMValueRef vindex,
861 LLVMValueRef voffset,
862 LLVMValueRef soffset,
863 unsigned inst_offset,
864 unsigned glc,
865 unsigned slc)
866 {
867 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
868 unsigned func = CLAMP(num_channels, 1, 3) - 1;
869
870 if (HAVE_LLVM >= 0x309) {
871 LLVMValueRef args[] = {
872 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
873 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
874 LLVMConstInt(ctx->i32, inst_offset, 0),
875 LLVMConstInt(ctx->i1, glc, 0),
876 LLVMConstInt(ctx->i1, slc, 0)
877 };
878
879 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
880 ctx->v4f32};
881 const char *type_names[] = {"f32", "v2f32", "v4f32"};
882 char name[256];
883
884 if (voffset) {
885 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
886 "");
887 }
888
889 if (soffset) {
890 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
891 "");
892 }
893
894 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
895 type_names[func]);
896
897 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
898 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
899 } else {
900 LLVMValueRef args[] = {
901 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
902 voffset ? voffset : vindex,
903 soffset,
904 LLVMConstInt(ctx->i32, inst_offset, 0),
905 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
906 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
907 LLVMConstInt(ctx->i32, glc, 0),
908 LLVMConstInt(ctx->i32, slc, 0),
909 LLVMConstInt(ctx->i32, 0, 0), // TFE
910 };
911
912 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
913 ctx->v4i32};
914 const char *type_names[] = {"i32", "v2i32", "v4i32"};
915 const char *arg_type = "i32";
916 char name[256];
917
918 if (voffset && vindex) {
919 LLVMValueRef vaddr[] = {vindex, voffset};
920
921 arg_type = "v2i32";
922 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
923 }
924
925 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
926 type_names[func], arg_type);
927
928 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
929 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
930 }
931 }
932
933 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
934 enum tgsi_opcode_type type, unsigned swizzle,
935 LLVMValueRef buffer, LLVMValueRef offset,
936 LLVMValueRef base)
937 {
938 struct si_shader_context *ctx = si_shader_context(bld_base);
939 struct gallivm_state *gallivm = bld_base->base.gallivm;
940 LLVMValueRef value, value2;
941 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
942 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
943
944 if (swizzle == ~0) {
945 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
946 0, 1, 0);
947
948 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
949 }
950
951 if (!tgsi_type_is_64bit(type)) {
952 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
953 0, 1, 0);
954
955 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
956 return LLVMBuildExtractElement(gallivm->builder, value,
957 lp_build_const_int32(gallivm, swizzle), "");
958 }
959
960 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
961 swizzle * 4, 1, 0);
962
963 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
964 swizzle * 4 + 4, 1, 0);
965
966 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
967 }
968
969 /**
970 * Load from LDS.
971 *
972 * \param type output value type
973 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
974 * \param dw_addr address in dwords
975 */
976 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
977 enum tgsi_opcode_type type, unsigned swizzle,
978 LLVMValueRef dw_addr)
979 {
980 struct si_shader_context *ctx = si_shader_context(bld_base);
981 struct gallivm_state *gallivm = bld_base->base.gallivm;
982 LLVMValueRef value;
983
984 if (swizzle == ~0) {
985 LLVMValueRef values[TGSI_NUM_CHANNELS];
986
987 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
988 values[chan] = lds_load(bld_base, type, chan, dw_addr);
989
990 return lp_build_gather_values(bld_base->base.gallivm, values,
991 TGSI_NUM_CHANNELS);
992 }
993
994 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
995 lp_build_const_int32(gallivm, swizzle));
996
997 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
998 if (tgsi_type_is_64bit(type)) {
999 LLVMValueRef value2;
1000 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1001 lp_build_const_int32(gallivm, swizzle + 1));
1002 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1003 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1004 }
1005
1006 return LLVMBuildBitCast(gallivm->builder, value,
1007 tgsi2llvmtype(bld_base, type), "");
1008 }
1009
1010 /**
1011 * Store to LDS.
1012 *
1013 * \param swizzle offset (typically 0..3)
1014 * \param dw_addr address in dwords
1015 * \param value value to store
1016 */
1017 static void lds_store(struct lp_build_tgsi_context *bld_base,
1018 unsigned swizzle, LLVMValueRef dw_addr,
1019 LLVMValueRef value)
1020 {
1021 struct si_shader_context *ctx = si_shader_context(bld_base);
1022 struct gallivm_state *gallivm = bld_base->base.gallivm;
1023
1024 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1025 lp_build_const_int32(gallivm, swizzle));
1026
1027 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1028 build_indexed_store(ctx, ctx->lds,
1029 dw_addr, value);
1030 }
1031
1032 static LLVMValueRef fetch_input_tcs(
1033 struct lp_build_tgsi_context *bld_base,
1034 const struct tgsi_full_src_register *reg,
1035 enum tgsi_opcode_type type, unsigned swizzle)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 LLVMValueRef dw_addr, stride;
1039
1040 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1041 dw_addr = get_tcs_in_current_patch_offset(ctx);
1042 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1043
1044 return lds_load(bld_base, type, swizzle, dw_addr);
1045 }
1046
1047 static LLVMValueRef fetch_output_tcs(
1048 struct lp_build_tgsi_context *bld_base,
1049 const struct tgsi_full_src_register *reg,
1050 enum tgsi_opcode_type type, unsigned swizzle)
1051 {
1052 struct si_shader_context *ctx = si_shader_context(bld_base);
1053 LLVMValueRef dw_addr, stride;
1054
1055 if (reg->Register.Dimension) {
1056 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1057 dw_addr = get_tcs_out_current_patch_offset(ctx);
1058 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1059 } else {
1060 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1061 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1062 }
1063
1064 return lds_load(bld_base, type, swizzle, dw_addr);
1065 }
1066
1067 static LLVMValueRef fetch_input_tes(
1068 struct lp_build_tgsi_context *bld_base,
1069 const struct tgsi_full_src_register *reg,
1070 enum tgsi_opcode_type type, unsigned swizzle)
1071 {
1072 struct si_shader_context *ctx = si_shader_context(bld_base);
1073 struct gallivm_state *gallivm = bld_base->base.gallivm;
1074 LLVMValueRef rw_buffers, buffer, base, addr;
1075
1076 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1077 SI_PARAM_RW_BUFFERS);
1078 buffer = build_indexed_load_const(ctx, rw_buffers,
1079 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1080
1081 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1082 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1083
1084 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1085 }
1086
1087 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1088 const struct tgsi_full_instruction *inst,
1089 const struct tgsi_opcode_info *info,
1090 LLVMValueRef dst[4])
1091 {
1092 struct si_shader_context *ctx = si_shader_context(bld_base);
1093 struct gallivm_state *gallivm = bld_base->base.gallivm;
1094 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1095 unsigned chan_index;
1096 LLVMValueRef dw_addr, stride;
1097 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1098 LLVMValueRef values[4];
1099
1100 /* Only handle per-patch and per-vertex outputs here.
1101 * Vectors will be lowered to scalars and this function will be called again.
1102 */
1103 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1104 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1105 radeon_llvm_emit_store(bld_base, inst, info, dst);
1106 return;
1107 }
1108
1109 if (reg->Register.Dimension) {
1110 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1111 dw_addr = get_tcs_out_current_patch_offset(ctx);
1112 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1113 } else {
1114 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1115 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1116 }
1117
1118 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1119 SI_PARAM_RW_BUFFERS);
1120 buffer = build_indexed_load_const(ctx, rw_buffers,
1121 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1122
1123 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1124 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1125
1126
1127 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1128 LLVMValueRef value = dst[chan_index];
1129
1130 if (inst->Instruction.Saturate)
1131 value = radeon_llvm_saturate(bld_base, value);
1132
1133 lds_store(bld_base, chan_index, dw_addr, value);
1134
1135 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1136 values[chan_index] = value;
1137
1138 if (inst->Dst[0].Register.WriteMask != 0xF) {
1139 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1140 buf_addr, base,
1141 4 * chan_index);
1142 }
1143 }
1144
1145 if (inst->Dst[0].Register.WriteMask == 0xF) {
1146 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1147 values, 4);
1148 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1149 base, 0);
1150 }
1151 }
1152
1153 static LLVMValueRef fetch_input_gs(
1154 struct lp_build_tgsi_context *bld_base,
1155 const struct tgsi_full_src_register *reg,
1156 enum tgsi_opcode_type type,
1157 unsigned swizzle)
1158 {
1159 struct lp_build_context *base = &bld_base->base;
1160 struct si_shader_context *ctx = si_shader_context(bld_base);
1161 struct si_shader *shader = ctx->shader;
1162 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1163 struct gallivm_state *gallivm = base->gallivm;
1164 LLVMValueRef vtx_offset;
1165 LLVMValueRef args[9];
1166 unsigned vtx_offset_param;
1167 struct tgsi_shader_info *info = &shader->selector->info;
1168 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1169 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1170 unsigned param;
1171 LLVMValueRef value;
1172
1173 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1174 return get_primitive_id(bld_base, swizzle);
1175
1176 if (!reg->Register.Dimension)
1177 return NULL;
1178
1179 if (swizzle == ~0) {
1180 LLVMValueRef values[TGSI_NUM_CHANNELS];
1181 unsigned chan;
1182 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1183 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1184 }
1185 return lp_build_gather_values(bld_base->base.gallivm, values,
1186 TGSI_NUM_CHANNELS);
1187 }
1188
1189 /* Get the vertex offset parameter */
1190 vtx_offset_param = reg->Dimension.Index;
1191 if (vtx_offset_param < 2) {
1192 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1193 } else {
1194 assert(vtx_offset_param < 6);
1195 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1196 }
1197 vtx_offset = lp_build_mul_imm(uint,
1198 LLVMGetParam(ctx->radeon_bld.main_fn,
1199 vtx_offset_param),
1200 4);
1201
1202 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1203 args[0] = ctx->esgs_ring;
1204 args[1] = vtx_offset;
1205 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1206 args[3] = uint->zero;
1207 args[4] = uint->one; /* OFFEN */
1208 args[5] = uint->zero; /* IDXEN */
1209 args[6] = uint->one; /* GLC */
1210 args[7] = uint->zero; /* SLC */
1211 args[8] = uint->zero; /* TFE */
1212
1213 value = lp_build_intrinsic(gallivm->builder,
1214 "llvm.SI.buffer.load.dword.i32.i32",
1215 ctx->i32, args, 9,
1216 LLVMReadOnlyAttribute);
1217 if (tgsi_type_is_64bit(type)) {
1218 LLVMValueRef value2;
1219 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1220 value2 = lp_build_intrinsic(gallivm->builder,
1221 "llvm.SI.buffer.load.dword.i32.i32",
1222 ctx->i32, args, 9,
1223 LLVMReadOnlyAttribute);
1224 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1225 value, value2);
1226 }
1227 return LLVMBuildBitCast(gallivm->builder,
1228 value,
1229 tgsi2llvmtype(bld_base, type), "");
1230 }
1231
1232 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1233 {
1234 switch (interpolate) {
1235 case TGSI_INTERPOLATE_CONSTANT:
1236 return 0;
1237
1238 case TGSI_INTERPOLATE_LINEAR:
1239 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1240 return SI_PARAM_LINEAR_SAMPLE;
1241 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1242 return SI_PARAM_LINEAR_CENTROID;
1243 else
1244 return SI_PARAM_LINEAR_CENTER;
1245 break;
1246 case TGSI_INTERPOLATE_COLOR:
1247 case TGSI_INTERPOLATE_PERSPECTIVE:
1248 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1249 return SI_PARAM_PERSP_SAMPLE;
1250 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1251 return SI_PARAM_PERSP_CENTROID;
1252 else
1253 return SI_PARAM_PERSP_CENTER;
1254 break;
1255 default:
1256 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1257 return -1;
1258 }
1259 }
1260
1261 /* This shouldn't be used by explicit INTERP opcodes. */
1262 static unsigned select_interp_param(struct si_shader_context *ctx,
1263 unsigned param)
1264 {
1265 if (!ctx->is_monolithic)
1266 return param;
1267
1268 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1269 switch (param) {
1270 case SI_PARAM_PERSP_CENTROID:
1271 case SI_PARAM_PERSP_CENTER:
1272 return SI_PARAM_PERSP_SAMPLE;
1273 }
1274 }
1275 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1276 switch (param) {
1277 case SI_PARAM_LINEAR_CENTROID:
1278 case SI_PARAM_LINEAR_CENTER:
1279 return SI_PARAM_LINEAR_SAMPLE;
1280 }
1281 }
1282 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1283 switch (param) {
1284 case SI_PARAM_PERSP_CENTROID:
1285 case SI_PARAM_PERSP_SAMPLE:
1286 return SI_PARAM_PERSP_CENTER;
1287 }
1288 }
1289 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1290 switch (param) {
1291 case SI_PARAM_LINEAR_CENTROID:
1292 case SI_PARAM_LINEAR_SAMPLE:
1293 return SI_PARAM_LINEAR_CENTER;
1294 }
1295 }
1296
1297 return param;
1298 }
1299
1300 /**
1301 * Interpolate a fragment shader input.
1302 *
1303 * @param ctx context
1304 * @param input_index index of the input in hardware
1305 * @param semantic_name TGSI_SEMANTIC_*
1306 * @param semantic_index semantic index
1307 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1308 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1309 * @param interp_param interpolation weights (i,j)
1310 * @param prim_mask SI_PARAM_PRIM_MASK
1311 * @param face SI_PARAM_FRONT_FACE
1312 * @param result the return value (4 components)
1313 */
1314 static void interp_fs_input(struct si_shader_context *ctx,
1315 unsigned input_index,
1316 unsigned semantic_name,
1317 unsigned semantic_index,
1318 unsigned num_interp_inputs,
1319 unsigned colors_read_mask,
1320 LLVMValueRef interp_param,
1321 LLVMValueRef prim_mask,
1322 LLVMValueRef face,
1323 LLVMValueRef result[4])
1324 {
1325 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1326 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1327 struct gallivm_state *gallivm = base->gallivm;
1328 const char *intr_name;
1329 LLVMValueRef attr_number;
1330
1331 unsigned chan;
1332
1333 attr_number = lp_build_const_int32(gallivm, input_index);
1334
1335 /* fs.constant returns the param from the middle vertex, so it's not
1336 * really useful for flat shading. It's meant to be used for custom
1337 * interpolation (but the intrinsic can't fetch from the other two
1338 * vertices).
1339 *
1340 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1341 * to do the right thing. The only reason we use fs.constant is that
1342 * fs.interp cannot be used on integers, because they can be equal
1343 * to NaN.
1344 */
1345 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1346
1347 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1348 ctx->shader->key.ps.prolog.color_two_side) {
1349 LLVMValueRef args[4];
1350 LLVMValueRef is_face_positive;
1351 LLVMValueRef back_attr_number;
1352
1353 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1354 * otherwise it's at offset "num_inputs".
1355 */
1356 unsigned back_attr_offset = num_interp_inputs;
1357 if (semantic_index == 1 && colors_read_mask & 0xf)
1358 back_attr_offset += 1;
1359
1360 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1361
1362 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1363 face, uint->zero, "");
1364
1365 args[2] = prim_mask;
1366 args[3] = interp_param;
1367 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1368 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1369 LLVMValueRef front, back;
1370
1371 args[0] = llvm_chan;
1372 args[1] = attr_number;
1373 front = lp_build_intrinsic(gallivm->builder, intr_name,
1374 ctx->f32, args, args[3] ? 4 : 3,
1375 LLVMReadNoneAttribute);
1376
1377 args[1] = back_attr_number;
1378 back = lp_build_intrinsic(gallivm->builder, intr_name,
1379 ctx->f32, args, args[3] ? 4 : 3,
1380 LLVMReadNoneAttribute);
1381
1382 result[chan] = LLVMBuildSelect(gallivm->builder,
1383 is_face_positive,
1384 front,
1385 back,
1386 "");
1387 }
1388 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1389 LLVMValueRef args[4];
1390
1391 args[0] = uint->zero;
1392 args[1] = attr_number;
1393 args[2] = prim_mask;
1394 args[3] = interp_param;
1395 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1396 ctx->f32, args, args[3] ? 4 : 3,
1397 LLVMReadNoneAttribute);
1398 result[1] =
1399 result[2] = lp_build_const_float(gallivm, 0.0f);
1400 result[3] = lp_build_const_float(gallivm, 1.0f);
1401 } else {
1402 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1403 LLVMValueRef args[4];
1404 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1405
1406 args[0] = llvm_chan;
1407 args[1] = attr_number;
1408 args[2] = prim_mask;
1409 args[3] = interp_param;
1410 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1411 ctx->f32, args, args[3] ? 4 : 3,
1412 LLVMReadNoneAttribute);
1413 }
1414 }
1415 }
1416
1417 /* LLVMGetParam with bc_optimize resolved. */
1418 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1419 int interp_param_idx)
1420 {
1421 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1422 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1423 LLVMValueRef param = NULL;
1424
1425 /* Handle PRIM_MASK[31] (bc_optimize). */
1426 if (ctx->is_monolithic &&
1427 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1428 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1429 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1430 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1431 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1432 * The hw doesn't compute CENTROID if the whole wave only
1433 * contains fully-covered quads.
1434 */
1435 LLVMValueRef bc_optimize =
1436 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1437 bc_optimize = LLVMBuildLShr(builder,
1438 bc_optimize,
1439 LLVMConstInt(ctx->i32, 31, 0), "");
1440 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1441
1442 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1443 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1444 param = LLVMBuildSelect(builder, bc_optimize,
1445 LLVMGetParam(main_fn,
1446 SI_PARAM_PERSP_CENTER),
1447 LLVMGetParam(main_fn,
1448 SI_PARAM_PERSP_CENTROID),
1449 "");
1450 }
1451 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1452 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1453 param = LLVMBuildSelect(builder, bc_optimize,
1454 LLVMGetParam(main_fn,
1455 SI_PARAM_LINEAR_CENTER),
1456 LLVMGetParam(main_fn,
1457 SI_PARAM_LINEAR_CENTROID),
1458 "");
1459 }
1460 }
1461
1462 if (!param)
1463 param = LLVMGetParam(main_fn, interp_param_idx);
1464 return param;
1465 }
1466
1467 static void declare_input_fs(
1468 struct radeon_llvm_context *radeon_bld,
1469 unsigned input_index,
1470 const struct tgsi_full_declaration *decl)
1471 {
1472 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1473 struct si_shader_context *ctx =
1474 si_shader_context(&radeon_bld->soa.bld_base);
1475 struct si_shader *shader = ctx->shader;
1476 LLVMValueRef main_fn = radeon_bld->main_fn;
1477 LLVMValueRef interp_param = NULL;
1478 int interp_param_idx;
1479
1480 /* Get colors from input VGPRs (set by the prolog). */
1481 if (!ctx->is_monolithic &&
1482 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1483 unsigned i = decl->Semantic.Index;
1484 unsigned colors_read = shader->selector->info.colors_read;
1485 unsigned mask = colors_read >> (i * 4);
1486 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1487 (i ? util_bitcount(colors_read & 0xf) : 0);
1488
1489 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1490 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1491 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1492 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1493 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1494 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1495 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1496 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1497 return;
1498 }
1499
1500 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1501 decl->Interp.Location);
1502 if (interp_param_idx == -1)
1503 return;
1504 else if (interp_param_idx) {
1505 interp_param_idx = select_interp_param(ctx,
1506 interp_param_idx);
1507 interp_param = get_interp_param(ctx, interp_param_idx);
1508 }
1509
1510 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1511 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1512 ctx->shader->key.ps.prolog.flatshade_colors)
1513 interp_param = NULL; /* load the constant color */
1514
1515 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1516 decl->Semantic.Index, shader->selector->info.num_inputs,
1517 shader->selector->info.colors_read, interp_param,
1518 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1519 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1520 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1521 }
1522
1523 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1524 {
1525 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1526 SI_PARAM_ANCILLARY, 8, 4);
1527 }
1528
1529 /**
1530 * Set range metadata on an instruction. This can only be used on load and
1531 * call instructions. If you know an instruction can only produce the values
1532 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1533 * \p lo is the minimum value inclusive.
1534 * \p hi is the maximum value exclusive.
1535 */
1536 static void set_range_metadata(struct si_shader_context *ctx,
1537 LLVMValueRef value, unsigned lo, unsigned hi)
1538 {
1539 LLVMValueRef range_md, md_args[2];
1540 LLVMTypeRef type = LLVMTypeOf(value);
1541 LLVMContextRef context = LLVMGetTypeContext(type);
1542
1543 md_args[0] = LLVMConstInt(type, lo, false);
1544 md_args[1] = LLVMConstInt(type, hi, false);
1545 range_md = LLVMMDNodeInContext(context, md_args, 2);
1546 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1547 }
1548
1549 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1550 {
1551 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1552 LLVMValueRef tid;
1553
1554 if (HAVE_LLVM < 0x0308) {
1555 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1556 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1557 } else {
1558 LLVMValueRef tid_args[2];
1559 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1560 tid_args[1] = lp_build_const_int32(gallivm, 0);
1561 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1562 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1563 tid_args, 2, LLVMReadNoneAttribute);
1564
1565 tid = lp_build_intrinsic(gallivm->builder,
1566 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1567 tid_args, 2, LLVMReadNoneAttribute);
1568 }
1569 set_range_metadata(ctx, tid, 0, 64);
1570 return tid;
1571 }
1572
1573 /**
1574 * Load a dword from a constant buffer.
1575 */
1576 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1577 LLVMValueRef resource,
1578 LLVMValueRef offset)
1579 {
1580 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1581 LLVMValueRef args[2] = {resource, offset};
1582
1583 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1584 LLVMReadNoneAttribute);
1585 }
1586
1587 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1588 {
1589 struct si_shader_context *ctx =
1590 si_shader_context(&radeon_bld->soa.bld_base);
1591 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1592 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1593 LLVMBuilderRef builder = gallivm->builder;
1594 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1595 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1596 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1597
1598 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1599 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1600 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1601
1602 LLVMValueRef pos[4] = {
1603 buffer_load_const(ctx, resource, offset0),
1604 buffer_load_const(ctx, resource, offset1),
1605 lp_build_const_float(gallivm, 0),
1606 lp_build_const_float(gallivm, 0)
1607 };
1608
1609 return lp_build_gather_values(gallivm, pos, 4);
1610 }
1611
1612 static void declare_system_value(
1613 struct radeon_llvm_context *radeon_bld,
1614 unsigned index,
1615 const struct tgsi_full_declaration *decl)
1616 {
1617 struct si_shader_context *ctx =
1618 si_shader_context(&radeon_bld->soa.bld_base);
1619 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1620 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1621 LLVMValueRef value = 0;
1622
1623 switch (decl->Semantic.Name) {
1624 case TGSI_SEMANTIC_INSTANCEID:
1625 value = LLVMGetParam(radeon_bld->main_fn,
1626 ctx->param_instance_id);
1627 break;
1628
1629 case TGSI_SEMANTIC_VERTEXID:
1630 value = LLVMBuildAdd(gallivm->builder,
1631 LLVMGetParam(radeon_bld->main_fn,
1632 ctx->param_vertex_id),
1633 LLVMGetParam(radeon_bld->main_fn,
1634 SI_PARAM_BASE_VERTEX), "");
1635 break;
1636
1637 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1638 value = LLVMGetParam(radeon_bld->main_fn,
1639 ctx->param_vertex_id);
1640 break;
1641
1642 case TGSI_SEMANTIC_BASEVERTEX:
1643 value = LLVMGetParam(radeon_bld->main_fn,
1644 SI_PARAM_BASE_VERTEX);
1645 break;
1646
1647 case TGSI_SEMANTIC_BASEINSTANCE:
1648 value = LLVMGetParam(radeon_bld->main_fn,
1649 SI_PARAM_START_INSTANCE);
1650 break;
1651
1652 case TGSI_SEMANTIC_DRAWID:
1653 value = LLVMGetParam(radeon_bld->main_fn,
1654 SI_PARAM_DRAWID);
1655 break;
1656
1657 case TGSI_SEMANTIC_INVOCATIONID:
1658 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1659 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1660 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1661 value = LLVMGetParam(radeon_bld->main_fn,
1662 SI_PARAM_GS_INSTANCE_ID);
1663 else
1664 assert(!"INVOCATIONID not implemented");
1665 break;
1666
1667 case TGSI_SEMANTIC_POSITION:
1668 {
1669 LLVMValueRef pos[4] = {
1670 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1671 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1672 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1673 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1674 LLVMGetParam(radeon_bld->main_fn,
1675 SI_PARAM_POS_W_FLOAT)),
1676 };
1677 value = lp_build_gather_values(gallivm, pos, 4);
1678 break;
1679 }
1680
1681 case TGSI_SEMANTIC_FACE:
1682 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1683 break;
1684
1685 case TGSI_SEMANTIC_SAMPLEID:
1686 value = get_sample_id(radeon_bld);
1687 break;
1688
1689 case TGSI_SEMANTIC_SAMPLEPOS: {
1690 LLVMValueRef pos[4] = {
1691 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1692 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1693 lp_build_const_float(gallivm, 0),
1694 lp_build_const_float(gallivm, 0)
1695 };
1696 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1697 TGSI_OPCODE_FRC, pos[0]);
1698 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1699 TGSI_OPCODE_FRC, pos[1]);
1700 value = lp_build_gather_values(gallivm, pos, 4);
1701 break;
1702 }
1703
1704 case TGSI_SEMANTIC_SAMPLEMASK:
1705 /* This can only occur with the OpenGL Core profile, which
1706 * doesn't support smoothing.
1707 */
1708 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1709 break;
1710
1711 case TGSI_SEMANTIC_TESSCOORD:
1712 {
1713 LLVMValueRef coord[4] = {
1714 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1715 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1716 bld->zero,
1717 bld->zero
1718 };
1719
1720 /* For triangles, the vector should be (u, v, 1-u-v). */
1721 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1722 PIPE_PRIM_TRIANGLES)
1723 coord[2] = lp_build_sub(bld, bld->one,
1724 lp_build_add(bld, coord[0], coord[1]));
1725
1726 value = lp_build_gather_values(gallivm, coord, 4);
1727 break;
1728 }
1729
1730 case TGSI_SEMANTIC_VERTICESIN:
1731 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1732 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1733 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1734 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1735 else
1736 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1737 break;
1738
1739 case TGSI_SEMANTIC_TESSINNER:
1740 case TGSI_SEMANTIC_TESSOUTER:
1741 {
1742 LLVMValueRef rw_buffers, buffer, base, addr;
1743 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1744
1745 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1746 SI_PARAM_RW_BUFFERS);
1747 buffer = build_indexed_load_const(ctx, rw_buffers,
1748 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1749
1750 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1751 addr = get_tcs_tes_buffer_address(ctx, NULL,
1752 lp_build_const_int32(gallivm, param));
1753
1754 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1755 ~0, buffer, base, addr);
1756
1757 break;
1758 }
1759
1760 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1761 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1762 {
1763 LLVMValueRef buf, slot, val[4];
1764 int i, offset;
1765
1766 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1767 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1768 buf = build_indexed_load_const(ctx, buf, slot);
1769 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1770
1771 for (i = 0; i < 4; i++)
1772 val[i] = buffer_load_const(ctx, buf,
1773 lp_build_const_int32(gallivm, (offset + i) * 4));
1774 value = lp_build_gather_values(gallivm, val, 4);
1775 break;
1776 }
1777
1778 case TGSI_SEMANTIC_PRIMID:
1779 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1780 break;
1781
1782 case TGSI_SEMANTIC_GRID_SIZE:
1783 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1784 break;
1785
1786 case TGSI_SEMANTIC_BLOCK_SIZE:
1787 {
1788 LLVMValueRef values[3];
1789 unsigned i;
1790 unsigned *properties = ctx->shader->selector->info.properties;
1791 unsigned sizes[3] = {
1792 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1793 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1794 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1795 };
1796
1797 for (i = 0; i < 3; ++i)
1798 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1799
1800 value = lp_build_gather_values(gallivm, values, 3);
1801 break;
1802 }
1803
1804 case TGSI_SEMANTIC_BLOCK_ID:
1805 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1806 break;
1807
1808 case TGSI_SEMANTIC_THREAD_ID:
1809 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1810 break;
1811
1812 #if HAVE_LLVM >= 0x0309
1813 case TGSI_SEMANTIC_HELPER_INVOCATION:
1814 value = lp_build_intrinsic(gallivm->builder,
1815 "llvm.amdgcn.ps.live",
1816 ctx->i1, NULL, 0,
1817 LLVMReadNoneAttribute);
1818 value = LLVMBuildNot(gallivm->builder, value, "");
1819 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1820 break;
1821 #endif
1822
1823 default:
1824 assert(!"unknown system value");
1825 return;
1826 }
1827
1828 radeon_bld->system_values[index] = value;
1829 }
1830
1831 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1832 const struct tgsi_full_declaration *decl)
1833 {
1834 struct si_shader_context *ctx =
1835 si_shader_context(&radeon_bld->soa.bld_base);
1836 struct si_shader_selector *sel = ctx->shader->selector;
1837 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1838
1839 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1840 LLVMValueRef var;
1841
1842 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1843 assert(decl->Range.First == decl->Range.Last);
1844 assert(!ctx->shared_memory);
1845
1846 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1847 LLVMArrayType(ctx->i8, sel->local_size),
1848 "compute_lds",
1849 LOCAL_ADDR_SPACE);
1850 LLVMSetAlignment(var, 4);
1851
1852 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1853 }
1854
1855 static LLVMValueRef fetch_constant(
1856 struct lp_build_tgsi_context *bld_base,
1857 const struct tgsi_full_src_register *reg,
1858 enum tgsi_opcode_type type,
1859 unsigned swizzle)
1860 {
1861 struct si_shader_context *ctx = si_shader_context(bld_base);
1862 struct lp_build_context *base = &bld_base->base;
1863 const struct tgsi_ind_register *ireg = &reg->Indirect;
1864 unsigned buf, idx;
1865
1866 LLVMValueRef addr, bufp;
1867 LLVMValueRef result;
1868
1869 if (swizzle == LP_CHAN_ALL) {
1870 unsigned chan;
1871 LLVMValueRef values[4];
1872 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1873 values[chan] = fetch_constant(bld_base, reg, type, chan);
1874
1875 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1876 }
1877
1878 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1879 idx = reg->Register.Index * 4 + swizzle;
1880
1881 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1882 LLVMValueRef c0, c1;
1883
1884 c0 = buffer_load_const(ctx, ctx->const_buffers[buf],
1885 LLVMConstInt(ctx->i32, idx * 4, 0));
1886
1887 if (!tgsi_type_is_64bit(type))
1888 return bitcast(bld_base, type, c0);
1889 else {
1890 c1 = buffer_load_const(ctx, ctx->const_buffers[buf],
1891 LLVMConstInt(ctx->i32,
1892 (idx + 1) * 4, 0));
1893 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1894 c0, c1);
1895 }
1896 }
1897
1898 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1899 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1900 LLVMValueRef index;
1901 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1902 reg->Dimension.Index,
1903 SI_NUM_CONST_BUFFERS);
1904 bufp = build_indexed_load_const(ctx, ptr, index);
1905 } else
1906 bufp = ctx->const_buffers[buf];
1907
1908 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1909 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1910 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1911 addr = lp_build_add(&bld_base->uint_bld, addr,
1912 lp_build_const_int32(base->gallivm, idx * 4));
1913
1914 result = buffer_load_const(ctx, bufp, addr);
1915
1916 if (!tgsi_type_is_64bit(type))
1917 result = bitcast(bld_base, type, result);
1918 else {
1919 LLVMValueRef addr2, result2;
1920 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1921 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1922 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1923 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1924 lp_build_const_int32(base->gallivm, idx * 4));
1925
1926 result2 = buffer_load_const(ctx, bufp, addr2);
1927
1928 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1929 result, result2);
1930 }
1931 return result;
1932 }
1933
1934 /* Upper 16 bits must be zero. */
1935 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1936 LLVMValueRef val[2])
1937 {
1938 return LLVMBuildOr(gallivm->builder, val[0],
1939 LLVMBuildShl(gallivm->builder, val[1],
1940 lp_build_const_int32(gallivm, 16),
1941 ""), "");
1942 }
1943
1944 /* Upper 16 bits are ignored and will be dropped. */
1945 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1946 LLVMValueRef val[2])
1947 {
1948 LLVMValueRef v[2] = {
1949 LLVMBuildAnd(gallivm->builder, val[0],
1950 lp_build_const_int32(gallivm, 0xffff), ""),
1951 val[1],
1952 };
1953 return si_llvm_pack_two_int16(gallivm, v);
1954 }
1955
1956 /* Initialize arguments for the shader export intrinsic */
1957 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1958 LLVMValueRef *values,
1959 unsigned target,
1960 LLVMValueRef *args)
1961 {
1962 struct si_shader_context *ctx = si_shader_context(bld_base);
1963 struct lp_build_context *uint =
1964 &ctx->radeon_bld.soa.bld_base.uint_bld;
1965 struct lp_build_context *base = &bld_base->base;
1966 struct gallivm_state *gallivm = base->gallivm;
1967 LLVMBuilderRef builder = base->gallivm->builder;
1968 LLVMValueRef val[4];
1969 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1970 unsigned chan;
1971 bool is_int8;
1972
1973 /* Default is 0xf. Adjusted below depending on the format. */
1974 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1975
1976 /* Specify whether the EXEC mask represents the valid mask */
1977 args[1] = uint->zero;
1978
1979 /* Specify whether this is the last export */
1980 args[2] = uint->zero;
1981
1982 /* Specify the target we are exporting */
1983 args[3] = lp_build_const_int32(base->gallivm, target);
1984
1985 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1986 const union si_shader_key *key = &ctx->shader->key;
1987 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1988 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1989
1990 assert(cbuf >= 0 && cbuf < 8);
1991 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1992 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1993 }
1994
1995 args[4] = uint->zero; /* COMPR flag */
1996 args[5] = base->undef;
1997 args[6] = base->undef;
1998 args[7] = base->undef;
1999 args[8] = base->undef;
2000
2001 switch (spi_shader_col_format) {
2002 case V_028714_SPI_SHADER_ZERO:
2003 args[0] = uint->zero; /* writemask */
2004 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2005 break;
2006
2007 case V_028714_SPI_SHADER_32_R:
2008 args[0] = uint->one; /* writemask */
2009 args[5] = values[0];
2010 break;
2011
2012 case V_028714_SPI_SHADER_32_GR:
2013 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2014 args[5] = values[0];
2015 args[6] = values[1];
2016 break;
2017
2018 case V_028714_SPI_SHADER_32_AR:
2019 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2020 args[5] = values[0];
2021 args[8] = values[3];
2022 break;
2023
2024 case V_028714_SPI_SHADER_FP16_ABGR:
2025 args[4] = uint->one; /* COMPR flag */
2026
2027 for (chan = 0; chan < 2; chan++) {
2028 LLVMValueRef pack_args[2] = {
2029 values[2 * chan],
2030 values[2 * chan + 1]
2031 };
2032 LLVMValueRef packed;
2033
2034 packed = lp_build_intrinsic(base->gallivm->builder,
2035 "llvm.SI.packf16",
2036 ctx->i32, pack_args, 2,
2037 LLVMReadNoneAttribute);
2038 args[chan + 5] =
2039 LLVMBuildBitCast(base->gallivm->builder,
2040 packed, ctx->f32, "");
2041 }
2042 break;
2043
2044 case V_028714_SPI_SHADER_UNORM16_ABGR:
2045 for (chan = 0; chan < 4; chan++) {
2046 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2047 val[chan] = LLVMBuildFMul(builder, val[chan],
2048 lp_build_const_float(gallivm, 65535), "");
2049 val[chan] = LLVMBuildFAdd(builder, val[chan],
2050 lp_build_const_float(gallivm, 0.5), "");
2051 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2052 ctx->i32, "");
2053 }
2054
2055 args[4] = uint->one; /* COMPR flag */
2056 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2057 si_llvm_pack_two_int16(gallivm, val));
2058 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2059 si_llvm_pack_two_int16(gallivm, val+2));
2060 break;
2061
2062 case V_028714_SPI_SHADER_SNORM16_ABGR:
2063 for (chan = 0; chan < 4; chan++) {
2064 /* Clamp between [-1, 1]. */
2065 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2066 values[chan],
2067 lp_build_const_float(gallivm, 1));
2068 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2069 val[chan],
2070 lp_build_const_float(gallivm, -1));
2071 /* Convert to a signed integer in [-32767, 32767]. */
2072 val[chan] = LLVMBuildFMul(builder, val[chan],
2073 lp_build_const_float(gallivm, 32767), "");
2074 /* If positive, add 0.5, else add -0.5. */
2075 val[chan] = LLVMBuildFAdd(builder, val[chan],
2076 LLVMBuildSelect(builder,
2077 LLVMBuildFCmp(builder, LLVMRealOGE,
2078 val[chan], base->zero, ""),
2079 lp_build_const_float(gallivm, 0.5),
2080 lp_build_const_float(gallivm, -0.5), ""), "");
2081 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2082 }
2083
2084 args[4] = uint->one; /* COMPR flag */
2085 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2086 si_llvm_pack_two_int32_as_int16(gallivm, val));
2087 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2088 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2089 break;
2090
2091 case V_028714_SPI_SHADER_UINT16_ABGR: {
2092 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2093 255 : 65535);
2094 /* Clamp. */
2095 for (chan = 0; chan < 4; chan++) {
2096 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2097 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2098 val[chan], max);
2099 }
2100
2101 args[4] = uint->one; /* COMPR flag */
2102 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2103 si_llvm_pack_two_int16(gallivm, val));
2104 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2105 si_llvm_pack_two_int16(gallivm, val+2));
2106 break;
2107 }
2108
2109 case V_028714_SPI_SHADER_SINT16_ABGR: {
2110 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2111 127 : 32767);
2112 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2113 -128 : -32768);
2114 /* Clamp. */
2115 for (chan = 0; chan < 4; chan++) {
2116 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2117 val[chan] = lp_build_emit_llvm_binary(bld_base,
2118 TGSI_OPCODE_IMIN,
2119 val[chan], max);
2120 val[chan] = lp_build_emit_llvm_binary(bld_base,
2121 TGSI_OPCODE_IMAX,
2122 val[chan], min);
2123 }
2124
2125 args[4] = uint->one; /* COMPR flag */
2126 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2127 si_llvm_pack_two_int32_as_int16(gallivm, val));
2128 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2129 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2130 break;
2131 }
2132
2133 case V_028714_SPI_SHADER_32_ABGR:
2134 memcpy(&args[5], values, sizeof(values[0]) * 4);
2135 break;
2136 }
2137 }
2138
2139 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2140 LLVMValueRef alpha)
2141 {
2142 struct si_shader_context *ctx = si_shader_context(bld_base);
2143 struct gallivm_state *gallivm = bld_base->base.gallivm;
2144
2145 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2146 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2147 SI_PARAM_ALPHA_REF);
2148
2149 LLVMValueRef alpha_pass =
2150 lp_build_cmp(&bld_base->base,
2151 ctx->shader->key.ps.epilog.alpha_func,
2152 alpha, alpha_ref);
2153 LLVMValueRef arg =
2154 lp_build_select(&bld_base->base,
2155 alpha_pass,
2156 lp_build_const_float(gallivm, 1.0f),
2157 lp_build_const_float(gallivm, -1.0f));
2158
2159 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2160 ctx->voidt, &arg, 1, 0);
2161 } else {
2162 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2163 ctx->voidt, NULL, 0, 0);
2164 }
2165 }
2166
2167 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2168 LLVMValueRef alpha,
2169 unsigned samplemask_param)
2170 {
2171 struct si_shader_context *ctx = si_shader_context(bld_base);
2172 struct gallivm_state *gallivm = bld_base->base.gallivm;
2173 LLVMValueRef coverage;
2174
2175 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2176 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2177 samplemask_param);
2178 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2179
2180 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2181 ctx->i32,
2182 &coverage, 1, LLVMReadNoneAttribute);
2183
2184 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2185 ctx->f32, "");
2186
2187 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2188 lp_build_const_float(gallivm,
2189 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2190
2191 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2192 }
2193
2194 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2195 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2196 {
2197 struct si_shader_context *ctx = si_shader_context(bld_base);
2198 struct lp_build_context *base = &bld_base->base;
2199 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2200 unsigned reg_index;
2201 unsigned chan;
2202 unsigned const_chan;
2203 LLVMValueRef base_elt;
2204 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2205 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2206 SI_VS_CONST_CLIP_PLANES);
2207 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2208
2209 for (reg_index = 0; reg_index < 2; reg_index ++) {
2210 LLVMValueRef *args = pos[2 + reg_index];
2211
2212 args[5] =
2213 args[6] =
2214 args[7] =
2215 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2216
2217 /* Compute dot products of position and user clip plane vectors */
2218 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2219 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2220 args[1] = lp_build_const_int32(base->gallivm,
2221 ((reg_index * 4 + chan) * 4 +
2222 const_chan) * 4);
2223 base_elt = buffer_load_const(ctx, const_resource,
2224 args[1]);
2225 args[5 + chan] =
2226 lp_build_add(base, args[5 + chan],
2227 lp_build_mul(base, base_elt,
2228 out_elts[const_chan]));
2229 }
2230 }
2231
2232 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2233 args[1] = uint->zero;
2234 args[2] = uint->zero;
2235 args[3] = lp_build_const_int32(base->gallivm,
2236 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2237 args[4] = uint->zero;
2238 }
2239 }
2240
2241 static void si_dump_streamout(struct pipe_stream_output_info *so)
2242 {
2243 unsigned i;
2244
2245 if (so->num_outputs)
2246 fprintf(stderr, "STREAMOUT\n");
2247
2248 for (i = 0; i < so->num_outputs; i++) {
2249 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2250 so->output[i].start_component;
2251 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2252 i, so->output[i].output_buffer,
2253 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2254 so->output[i].register_index,
2255 mask & 1 ? "x" : "",
2256 mask & 2 ? "y" : "",
2257 mask & 4 ? "z" : "",
2258 mask & 8 ? "w" : "");
2259 }
2260 }
2261
2262 /* On SI, the vertex shader is responsible for writing streamout data
2263 * to buffers. */
2264 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2265 struct si_shader_output_values *outputs,
2266 unsigned noutput)
2267 {
2268 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2269 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2270 LLVMBuilderRef builder = gallivm->builder;
2271 int i, j;
2272 struct lp_build_if_state if_ctx;
2273 LLVMValueRef so_buffers[4];
2274 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2275 SI_PARAM_RW_BUFFERS);
2276
2277 /* Load the descriptors. */
2278 for (i = 0; i < 4; ++i) {
2279 if (ctx->shader->selector->so.stride[i]) {
2280 LLVMValueRef offset = lp_build_const_int32(gallivm,
2281 SI_VS_STREAMOUT_BUF0 + i);
2282
2283 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2284 }
2285 }
2286
2287 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2288 LLVMValueRef so_vtx_count =
2289 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2290
2291 LLVMValueRef tid = get_thread_id(ctx);
2292
2293 /* can_emit = tid < so_vtx_count; */
2294 LLVMValueRef can_emit =
2295 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2296
2297 LLVMValueRef stream_id =
2298 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2299
2300 /* Emit the streamout code conditionally. This actually avoids
2301 * out-of-bounds buffer access. The hw tells us via the SGPR
2302 * (so_vtx_count) which threads are allowed to emit streamout data. */
2303 lp_build_if(&if_ctx, gallivm, can_emit);
2304 {
2305 /* The buffer offset is computed as follows:
2306 * ByteOffset = streamout_offset[buffer_id]*4 +
2307 * (streamout_write_index + thread_id)*stride[buffer_id] +
2308 * attrib_offset
2309 */
2310
2311 LLVMValueRef so_write_index =
2312 LLVMGetParam(ctx->radeon_bld.main_fn,
2313 ctx->param_streamout_write_index);
2314
2315 /* Compute (streamout_write_index + thread_id). */
2316 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2317
2318 /* Compute the write offset for each enabled buffer. */
2319 LLVMValueRef so_write_offset[4] = {};
2320 for (i = 0; i < 4; i++) {
2321 if (!so->stride[i])
2322 continue;
2323
2324 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2325 ctx->param_streamout_offset[i]);
2326 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2327
2328 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2329 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2330 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2331 }
2332
2333 /* Write streamout data. */
2334 for (i = 0; i < so->num_outputs; i++) {
2335 unsigned buf_idx = so->output[i].output_buffer;
2336 unsigned reg = so->output[i].register_index;
2337 unsigned start = so->output[i].start_component;
2338 unsigned num_comps = so->output[i].num_components;
2339 unsigned stream = so->output[i].stream;
2340 LLVMValueRef out[4];
2341 struct lp_build_if_state if_ctx_stream;
2342
2343 assert(num_comps && num_comps <= 4);
2344 if (!num_comps || num_comps > 4)
2345 continue;
2346
2347 if (reg >= noutput)
2348 continue;
2349
2350 /* Load the output as int. */
2351 for (j = 0; j < num_comps; j++) {
2352 out[j] = LLVMBuildBitCast(builder,
2353 outputs[reg].values[start+j],
2354 ctx->i32, "");
2355 }
2356
2357 /* Pack the output. */
2358 LLVMValueRef vdata = NULL;
2359
2360 switch (num_comps) {
2361 case 1: /* as i32 */
2362 vdata = out[0];
2363 break;
2364 case 2: /* as v2i32 */
2365 case 3: /* as v4i32 (aligned to 4) */
2366 case 4: /* as v4i32 */
2367 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2368 for (j = 0; j < num_comps; j++) {
2369 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2370 LLVMConstInt(ctx->i32, j, 0), "");
2371 }
2372 break;
2373 }
2374
2375 LLVMValueRef can_emit_stream =
2376 LLVMBuildICmp(builder, LLVMIntEQ,
2377 stream_id,
2378 lp_build_const_int32(gallivm, stream), "");
2379
2380 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2381 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2382 vdata, num_comps,
2383 so_write_offset[buf_idx],
2384 LLVMConstInt(ctx->i32, 0, 0),
2385 so->output[i].dst_offset*4);
2386 lp_build_endif(&if_ctx_stream);
2387 }
2388 }
2389 lp_build_endif(&if_ctx);
2390 }
2391
2392
2393 /* Generate export instructions for hardware VS shader stage */
2394 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2395 struct si_shader_output_values *outputs,
2396 unsigned noutput)
2397 {
2398 struct si_shader_context *ctx = si_shader_context(bld_base);
2399 struct si_shader *shader = ctx->shader;
2400 struct lp_build_context *base = &bld_base->base;
2401 struct lp_build_context *uint =
2402 &ctx->radeon_bld.soa.bld_base.uint_bld;
2403 LLVMValueRef args[9];
2404 LLVMValueRef pos_args[4][9] = { { 0 } };
2405 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2406 unsigned semantic_name, semantic_index;
2407 unsigned target;
2408 unsigned param_count = 0;
2409 unsigned pos_idx;
2410 int i;
2411
2412 if (outputs && ctx->shader->selector->so.num_outputs) {
2413 si_llvm_emit_streamout(ctx, outputs, noutput);
2414 }
2415
2416 for (i = 0; i < noutput; i++) {
2417 semantic_name = outputs[i].name;
2418 semantic_index = outputs[i].sid;
2419
2420 handle_semantic:
2421 /* Select the correct target */
2422 switch(semantic_name) {
2423 case TGSI_SEMANTIC_PSIZE:
2424 psize_value = outputs[i].values[0];
2425 continue;
2426 case TGSI_SEMANTIC_EDGEFLAG:
2427 edgeflag_value = outputs[i].values[0];
2428 continue;
2429 case TGSI_SEMANTIC_LAYER:
2430 layer_value = outputs[i].values[0];
2431 semantic_name = TGSI_SEMANTIC_GENERIC;
2432 goto handle_semantic;
2433 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2434 viewport_index_value = outputs[i].values[0];
2435 semantic_name = TGSI_SEMANTIC_GENERIC;
2436 goto handle_semantic;
2437 case TGSI_SEMANTIC_POSITION:
2438 target = V_008DFC_SQ_EXP_POS;
2439 break;
2440 case TGSI_SEMANTIC_COLOR:
2441 case TGSI_SEMANTIC_BCOLOR:
2442 target = V_008DFC_SQ_EXP_PARAM + param_count;
2443 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2444 shader->info.vs_output_param_offset[i] = param_count;
2445 param_count++;
2446 break;
2447 case TGSI_SEMANTIC_CLIPDIST:
2448 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2449 break;
2450 case TGSI_SEMANTIC_CLIPVERTEX:
2451 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2452 continue;
2453 case TGSI_SEMANTIC_PRIMID:
2454 case TGSI_SEMANTIC_FOG:
2455 case TGSI_SEMANTIC_TEXCOORD:
2456 case TGSI_SEMANTIC_GENERIC:
2457 target = V_008DFC_SQ_EXP_PARAM + param_count;
2458 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2459 shader->info.vs_output_param_offset[i] = param_count;
2460 param_count++;
2461 break;
2462 default:
2463 target = 0;
2464 fprintf(stderr,
2465 "Warning: SI unhandled vs output type:%d\n",
2466 semantic_name);
2467 }
2468
2469 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2470
2471 if (target >= V_008DFC_SQ_EXP_POS &&
2472 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2473 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2474 args, sizeof(args));
2475 } else {
2476 lp_build_intrinsic(base->gallivm->builder,
2477 "llvm.SI.export", ctx->voidt,
2478 args, 9, 0);
2479 }
2480
2481 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2482 semantic_name = TGSI_SEMANTIC_GENERIC;
2483 goto handle_semantic;
2484 }
2485 }
2486
2487 shader->info.nr_param_exports = param_count;
2488
2489 /* We need to add the position output manually if it's missing. */
2490 if (!pos_args[0][0]) {
2491 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2492 pos_args[0][1] = uint->zero; /* EXEC mask */
2493 pos_args[0][2] = uint->zero; /* last export? */
2494 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2495 pos_args[0][4] = uint->zero; /* COMPR flag */
2496 pos_args[0][5] = base->zero; /* X */
2497 pos_args[0][6] = base->zero; /* Y */
2498 pos_args[0][7] = base->zero; /* Z */
2499 pos_args[0][8] = base->one; /* W */
2500 }
2501
2502 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2503 if (shader->selector->info.writes_psize ||
2504 shader->selector->info.writes_edgeflag ||
2505 shader->selector->info.writes_viewport_index ||
2506 shader->selector->info.writes_layer) {
2507 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2508 shader->selector->info.writes_psize |
2509 (shader->selector->info.writes_edgeflag << 1) |
2510 (shader->selector->info.writes_layer << 2) |
2511 (shader->selector->info.writes_viewport_index << 3));
2512 pos_args[1][1] = uint->zero; /* EXEC mask */
2513 pos_args[1][2] = uint->zero; /* last export? */
2514 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2515 pos_args[1][4] = uint->zero; /* COMPR flag */
2516 pos_args[1][5] = base->zero; /* X */
2517 pos_args[1][6] = base->zero; /* Y */
2518 pos_args[1][7] = base->zero; /* Z */
2519 pos_args[1][8] = base->zero; /* W */
2520
2521 if (shader->selector->info.writes_psize)
2522 pos_args[1][5] = psize_value;
2523
2524 if (shader->selector->info.writes_edgeflag) {
2525 /* The output is a float, but the hw expects an integer
2526 * with the first bit containing the edge flag. */
2527 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2528 edgeflag_value,
2529 ctx->i32, "");
2530 edgeflag_value = lp_build_min(&bld_base->int_bld,
2531 edgeflag_value,
2532 bld_base->int_bld.one);
2533
2534 /* The LLVM intrinsic expects a float. */
2535 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2536 edgeflag_value,
2537 ctx->f32, "");
2538 }
2539
2540 if (shader->selector->info.writes_layer)
2541 pos_args[1][7] = layer_value;
2542
2543 if (shader->selector->info.writes_viewport_index)
2544 pos_args[1][8] = viewport_index_value;
2545 }
2546
2547 for (i = 0; i < 4; i++)
2548 if (pos_args[i][0])
2549 shader->info.nr_pos_exports++;
2550
2551 pos_idx = 0;
2552 for (i = 0; i < 4; i++) {
2553 if (!pos_args[i][0])
2554 continue;
2555
2556 /* Specify the target we are exporting */
2557 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2558
2559 if (pos_idx == shader->info.nr_pos_exports)
2560 /* Specify that this is the last export */
2561 pos_args[i][2] = uint->one;
2562
2563 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2564 ctx->voidt, pos_args[i], 9, 0);
2565 }
2566 }
2567
2568 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2569 {
2570 struct si_shader_context *ctx = si_shader_context(bld_base);
2571 struct gallivm_state *gallivm = bld_base->base.gallivm;
2572 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2573 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2574 uint64_t inputs;
2575
2576 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2577
2578 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2579 buffer = build_indexed_load_const(ctx, rw_buffers,
2580 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2581
2582 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2583
2584 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2585 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2586 lds_vertex_stride, "");
2587 lds_base = get_tcs_in_current_patch_offset(ctx);
2588 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2589
2590 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2591 while (inputs) {
2592 unsigned i = u_bit_scan64(&inputs);
2593
2594 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2595 lp_build_const_int32(gallivm, 4 * i),
2596 "");
2597
2598 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2599 invocation_id,
2600 lp_build_const_int32(gallivm, i));
2601
2602 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2603 lds_ptr);
2604
2605 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2606 buffer_offset, 0);
2607 }
2608 }
2609
2610 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2611 LLVMValueRef rel_patch_id,
2612 LLVMValueRef invocation_id,
2613 LLVMValueRef tcs_out_current_patch_data_offset)
2614 {
2615 struct si_shader_context *ctx = si_shader_context(bld_base);
2616 struct gallivm_state *gallivm = bld_base->base.gallivm;
2617 struct si_shader *shader = ctx->shader;
2618 unsigned tess_inner_index, tess_outer_index;
2619 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2620 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2621 unsigned stride, outer_comps, inner_comps, i;
2622 struct lp_build_if_state if_ctx, inner_if_ctx;
2623
2624 si_llvm_emit_barrier(NULL, bld_base, NULL);
2625
2626 /* Do this only for invocation 0, because the tess levels are per-patch,
2627 * not per-vertex.
2628 *
2629 * This can't jump, because invocation 0 executes this. It should
2630 * at least mask out the loads and stores for other invocations.
2631 */
2632 lp_build_if(&if_ctx, gallivm,
2633 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2634 invocation_id, bld_base->uint_bld.zero, ""));
2635
2636 /* Determine the layout of one tess factor element in the buffer. */
2637 switch (shader->key.tcs.epilog.prim_mode) {
2638 case PIPE_PRIM_LINES:
2639 stride = 2; /* 2 dwords, 1 vec2 store */
2640 outer_comps = 2;
2641 inner_comps = 0;
2642 break;
2643 case PIPE_PRIM_TRIANGLES:
2644 stride = 4; /* 4 dwords, 1 vec4 store */
2645 outer_comps = 3;
2646 inner_comps = 1;
2647 break;
2648 case PIPE_PRIM_QUADS:
2649 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2650 outer_comps = 4;
2651 inner_comps = 2;
2652 break;
2653 default:
2654 assert(0);
2655 return;
2656 }
2657
2658 /* Load tess_inner and tess_outer from LDS.
2659 * Any invocation can write them, so we can't get them from a temporary.
2660 */
2661 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2662 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2663
2664 lds_base = tcs_out_current_patch_data_offset;
2665 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2666 lp_build_const_int32(gallivm,
2667 tess_inner_index * 4), "");
2668 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2669 lp_build_const_int32(gallivm,
2670 tess_outer_index * 4), "");
2671
2672 for (i = 0; i < outer_comps; i++)
2673 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2674 for (i = 0; i < inner_comps; i++)
2675 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2676
2677 /* Convert the outputs to vectors for stores. */
2678 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2679 vec1 = NULL;
2680
2681 if (stride > 4)
2682 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2683
2684 /* Get the buffer. */
2685 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2686 SI_PARAM_RW_BUFFERS);
2687 buffer = build_indexed_load_const(ctx, rw_buffers,
2688 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2689
2690 /* Get the offset. */
2691 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2692 SI_PARAM_TESS_FACTOR_OFFSET);
2693 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2694 lp_build_const_int32(gallivm, 4 * stride), "");
2695
2696 lp_build_if(&inner_if_ctx, gallivm,
2697 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2698 rel_patch_id, bld_base->uint_bld.zero, ""));
2699
2700 /* Store the dynamic HS control word. */
2701 build_tbuffer_store_dwords(ctx, buffer,
2702 lp_build_const_int32(gallivm, 0x80000000),
2703 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2704
2705 lp_build_endif(&inner_if_ctx);
2706
2707 /* Store the tessellation factors. */
2708 build_tbuffer_store_dwords(ctx, buffer, vec0,
2709 MIN2(stride, 4), byteoffset, tf_base, 4);
2710 if (vec1)
2711 build_tbuffer_store_dwords(ctx, buffer, vec1,
2712 stride - 4, byteoffset, tf_base, 20);
2713 lp_build_endif(&if_ctx);
2714 }
2715
2716 /* This only writes the tessellation factor levels. */
2717 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2718 {
2719 struct si_shader_context *ctx = si_shader_context(bld_base);
2720 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2721
2722 rel_patch_id = get_rel_patch_id(ctx);
2723 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2724 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2725
2726 if (!ctx->is_monolithic) {
2727 /* Return epilog parameters from this function. */
2728 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2729 LLVMValueRef ret = ctx->return_value;
2730 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2731 unsigned vgpr;
2732
2733 /* RW_BUFFERS pointer */
2734 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2735 SI_PARAM_RW_BUFFERS);
2736 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2737 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2738 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2739 bld_base->uint_bld.zero, "");
2740 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2741 bld_base->uint_bld.one, "");
2742 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2743 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2744
2745 /* Tess factor buffer soffset is after user SGPRs. */
2746 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2747 SI_PARAM_TESS_FACTOR_OFFSET);
2748 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2749 SI_TCS_NUM_USER_SGPR + 1, "");
2750
2751 /* VGPRs */
2752 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2753 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2754 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2755
2756 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2757 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2758 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2759 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2760 ctx->return_value = ret;
2761 return;
2762 }
2763
2764 si_copy_tcs_inputs(bld_base);
2765 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2766 }
2767
2768 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2769 {
2770 struct si_shader_context *ctx = si_shader_context(bld_base);
2771 struct si_shader *shader = ctx->shader;
2772 struct tgsi_shader_info *info = &shader->selector->info;
2773 struct gallivm_state *gallivm = bld_base->base.gallivm;
2774 unsigned i, chan;
2775 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2776 ctx->param_rel_auto_id);
2777 LLVMValueRef vertex_dw_stride =
2778 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2779 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2780 vertex_dw_stride, "");
2781
2782 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2783 * its inputs from it. */
2784 for (i = 0; i < info->num_outputs; i++) {
2785 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2786 unsigned name = info->output_semantic_name[i];
2787 unsigned index = info->output_semantic_index[i];
2788 int param = si_shader_io_get_unique_index(name, index);
2789 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2790 lp_build_const_int32(gallivm, param * 4), "");
2791
2792 for (chan = 0; chan < 4; chan++) {
2793 lds_store(bld_base, chan, dw_addr,
2794 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2795 }
2796 }
2797 }
2798
2799 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2800 {
2801 struct si_shader_context *ctx = si_shader_context(bld_base);
2802 struct gallivm_state *gallivm = bld_base->base.gallivm;
2803 struct si_shader *es = ctx->shader;
2804 struct tgsi_shader_info *info = &es->selector->info;
2805 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2806 ctx->param_es2gs_offset);
2807 unsigned chan;
2808 int i;
2809
2810 for (i = 0; i < info->num_outputs; i++) {
2811 LLVMValueRef *out_ptr =
2812 ctx->radeon_bld.soa.outputs[i];
2813 int param_index;
2814
2815 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2816 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2817 continue;
2818
2819 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2820 info->output_semantic_index[i]);
2821
2822 for (chan = 0; chan < 4; chan++) {
2823 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2824 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2825
2826 build_tbuffer_store(ctx,
2827 ctx->esgs_ring,
2828 out_val, 1,
2829 LLVMGetUndef(ctx->i32), soffset,
2830 (4 * param_index + chan) * 4,
2831 V_008F0C_BUF_DATA_FORMAT_32,
2832 V_008F0C_BUF_NUM_FORMAT_UINT,
2833 0, 0, 1, 1, 0);
2834 }
2835 }
2836 }
2837
2838 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2839 {
2840 struct si_shader_context *ctx = si_shader_context(bld_base);
2841 struct gallivm_state *gallivm = bld_base->base.gallivm;
2842 LLVMValueRef args[2];
2843
2844 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2845 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2846 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2847 ctx->voidt, args, 2, 0);
2848 }
2849
2850 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2851 {
2852 struct si_shader_context *ctx = si_shader_context(bld_base);
2853 struct gallivm_state *gallivm = bld_base->base.gallivm;
2854 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2855 struct si_shader_output_values *outputs = NULL;
2856 int i,j;
2857
2858 assert(!ctx->is_gs_copy_shader);
2859
2860 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2861
2862 /* Vertex color clamping.
2863 *
2864 * This uses a state constant loaded in a user data SGPR and
2865 * an IF statement is added that clamps all colors if the constant
2866 * is true.
2867 */
2868 if (ctx->type == PIPE_SHADER_VERTEX) {
2869 struct lp_build_if_state if_ctx;
2870 LLVMValueRef cond = NULL;
2871 LLVMValueRef addr, val;
2872
2873 for (i = 0; i < info->num_outputs; i++) {
2874 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2875 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2876 continue;
2877
2878 /* We've found a color. */
2879 if (!cond) {
2880 /* The state is in the first bit of the user SGPR. */
2881 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2882 SI_PARAM_VS_STATE_BITS);
2883 cond = LLVMBuildTrunc(gallivm->builder, cond,
2884 ctx->i1, "");
2885 lp_build_if(&if_ctx, gallivm, cond);
2886 }
2887
2888 for (j = 0; j < 4; j++) {
2889 addr = ctx->radeon_bld.soa.outputs[i][j];
2890 val = LLVMBuildLoad(gallivm->builder, addr, "");
2891 val = radeon_llvm_saturate(bld_base, val);
2892 LLVMBuildStore(gallivm->builder, val, addr);
2893 }
2894 }
2895
2896 if (cond)
2897 lp_build_endif(&if_ctx);
2898 }
2899
2900 for (i = 0; i < info->num_outputs; i++) {
2901 outputs[i].name = info->output_semantic_name[i];
2902 outputs[i].sid = info->output_semantic_index[i];
2903
2904 for (j = 0; j < 4; j++)
2905 outputs[i].values[j] =
2906 LLVMBuildLoad(gallivm->builder,
2907 ctx->radeon_bld.soa.outputs[i][j],
2908 "");
2909 }
2910
2911 if (ctx->is_monolithic) {
2912 /* Export PrimitiveID when PS needs it. */
2913 if (si_vs_exports_prim_id(ctx->shader)) {
2914 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2915 outputs[i].sid = 0;
2916 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2917 get_primitive_id(bld_base, 0));
2918 outputs[i].values[1] = bld_base->base.undef;
2919 outputs[i].values[2] = bld_base->base.undef;
2920 outputs[i].values[3] = bld_base->base.undef;
2921 i++;
2922 }
2923 } else {
2924 /* Return the primitive ID from the LLVM function. */
2925 ctx->return_value =
2926 LLVMBuildInsertValue(gallivm->builder,
2927 ctx->return_value,
2928 bitcast(bld_base, TGSI_TYPE_FLOAT,
2929 get_primitive_id(bld_base, 0)),
2930 VS_EPILOG_PRIMID_LOC, "");
2931 }
2932
2933 si_llvm_export_vs(bld_base, outputs, i);
2934 FREE(outputs);
2935 }
2936
2937 struct si_ps_exports {
2938 unsigned num;
2939 LLVMValueRef args[10][9];
2940 };
2941
2942 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2943 bool writes_samplemask)
2944 {
2945 if (writes_z) {
2946 /* Z needs 32 bits. */
2947 if (writes_samplemask)
2948 return V_028710_SPI_SHADER_32_ABGR;
2949 else if (writes_stencil)
2950 return V_028710_SPI_SHADER_32_GR;
2951 else
2952 return V_028710_SPI_SHADER_32_R;
2953 } else if (writes_stencil || writes_samplemask) {
2954 /* Both stencil and sample mask need only 16 bits. */
2955 return V_028710_SPI_SHADER_UINT16_ABGR;
2956 } else {
2957 return V_028710_SPI_SHADER_ZERO;
2958 }
2959 }
2960
2961 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2962 LLVMValueRef depth, LLVMValueRef stencil,
2963 LLVMValueRef samplemask, struct si_ps_exports *exp)
2964 {
2965 struct si_shader_context *ctx = si_shader_context(bld_base);
2966 struct lp_build_context *base = &bld_base->base;
2967 struct lp_build_context *uint = &bld_base->uint_bld;
2968 LLVMValueRef args[9];
2969 unsigned mask = 0;
2970 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2971 stencil != NULL,
2972 samplemask != NULL);
2973
2974 assert(depth || stencil || samplemask);
2975
2976 args[1] = uint->one; /* whether the EXEC mask is valid */
2977 args[2] = uint->one; /* DONE bit */
2978
2979 /* Specify the target we are exporting */
2980 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2981
2982 args[4] = uint->zero; /* COMP flag */
2983 args[5] = base->undef; /* R, depth */
2984 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2985 args[7] = base->undef; /* B, sample mask */
2986 args[8] = base->undef; /* A, alpha to mask */
2987
2988 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2989 assert(!depth);
2990 args[4] = uint->one; /* COMPR flag */
2991
2992 if (stencil) {
2993 /* Stencil should be in X[23:16]. */
2994 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2995 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2996 LLVMConstInt(ctx->i32, 16, 0), "");
2997 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2998 mask |= 0x3;
2999 }
3000 if (samplemask) {
3001 /* SampleMask should be in Y[15:0]. */
3002 args[6] = samplemask;
3003 mask |= 0xc;
3004 }
3005 } else {
3006 if (depth) {
3007 args[5] = depth;
3008 mask |= 0x1;
3009 }
3010 if (stencil) {
3011 args[6] = stencil;
3012 mask |= 0x2;
3013 }
3014 if (samplemask) {
3015 args[7] = samplemask;
3016 mask |= 0x4;
3017 }
3018 }
3019
3020 /* SI (except OLAND) has a bug that it only looks
3021 * at the X writemask component. */
3022 if (ctx->screen->b.chip_class == SI &&
3023 ctx->screen->b.family != CHIP_OLAND)
3024 mask |= 0x1;
3025
3026 /* Specify which components to enable */
3027 args[0] = lp_build_const_int32(base->gallivm, mask);
3028
3029 memcpy(exp->args[exp->num++], args, sizeof(args));
3030 }
3031
3032 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3033 LLVMValueRef *color, unsigned index,
3034 unsigned samplemask_param,
3035 bool is_last, struct si_ps_exports *exp)
3036 {
3037 struct si_shader_context *ctx = si_shader_context(bld_base);
3038 struct lp_build_context *base = &bld_base->base;
3039 int i;
3040
3041 /* Clamp color */
3042 if (ctx->shader->key.ps.epilog.clamp_color)
3043 for (i = 0; i < 4; i++)
3044 color[i] = radeon_llvm_saturate(bld_base, color[i]);
3045
3046 /* Alpha to one */
3047 if (ctx->shader->key.ps.epilog.alpha_to_one)
3048 color[3] = base->one;
3049
3050 /* Alpha test */
3051 if (index == 0 &&
3052 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3053 si_alpha_test(bld_base, color[3]);
3054
3055 /* Line & polygon smoothing */
3056 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
3057 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3058 samplemask_param);
3059
3060 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3061 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3062 LLVMValueRef args[8][9];
3063 int c, last = -1;
3064
3065 /* Get the export arguments, also find out what the last one is. */
3066 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3067 si_llvm_init_export_args(bld_base, color,
3068 V_008DFC_SQ_EXP_MRT + c, args[c]);
3069 if (args[c][0] != bld_base->uint_bld.zero)
3070 last = c;
3071 }
3072
3073 /* Emit all exports. */
3074 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3075 if (is_last && last == c) {
3076 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3077 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3078 } else if (args[c][0] == bld_base->uint_bld.zero)
3079 continue; /* unnecessary NULL export */
3080
3081 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3082 }
3083 } else {
3084 LLVMValueRef args[9];
3085
3086 /* Export */
3087 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3088 args);
3089 if (is_last) {
3090 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3091 args[2] = bld_base->uint_bld.one; /* DONE bit */
3092 } else if (args[0] == bld_base->uint_bld.zero)
3093 return; /* unnecessary NULL export */
3094
3095 memcpy(exp->args[exp->num++], args, sizeof(args));
3096 }
3097 }
3098
3099 static void si_emit_ps_exports(struct si_shader_context *ctx,
3100 struct si_ps_exports *exp)
3101 {
3102 for (unsigned i = 0; i < exp->num; i++)
3103 lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
3104 "llvm.SI.export", ctx->voidt,
3105 exp->args[i], 9, 0);
3106 }
3107
3108 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3109 {
3110 struct si_shader_context *ctx = si_shader_context(bld_base);
3111 struct lp_build_context *base = &bld_base->base;
3112 struct lp_build_context *uint = &bld_base->uint_bld;
3113 LLVMValueRef args[9];
3114
3115 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3116 args[1] = uint->one; /* whether the EXEC mask is valid */
3117 args[2] = uint->one; /* DONE bit */
3118 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3119 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3120 args[5] = base->undef; /* R */
3121 args[6] = base->undef; /* G */
3122 args[7] = base->undef; /* B */
3123 args[8] = base->undef; /* A */
3124
3125 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3126 ctx->voidt, args, 9, 0);
3127 }
3128
3129 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3130 {
3131 struct si_shader_context *ctx = si_shader_context(bld_base);
3132 struct si_shader *shader = ctx->shader;
3133 struct lp_build_context *base = &bld_base->base;
3134 struct tgsi_shader_info *info = &shader->selector->info;
3135 LLVMBuilderRef builder = base->gallivm->builder;
3136 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3137 int last_color_export = -1;
3138 int i;
3139 struct si_ps_exports exp = {};
3140
3141 /* Determine the last export. If MRTZ is present, it's always last.
3142 * Otherwise, find the last color export.
3143 */
3144 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3145 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3146
3147 /* Don't export NULL and return if alpha-test is enabled. */
3148 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3149 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3150 (spi_format & 0xf) == 0)
3151 spi_format |= V_028714_SPI_SHADER_32_AR;
3152
3153 for (i = 0; i < info->num_outputs; i++) {
3154 unsigned index = info->output_semantic_index[i];
3155
3156 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3157 continue;
3158
3159 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3160 if (shader->key.ps.epilog.last_cbuf > 0) {
3161 /* Just set this if any of the colorbuffers are enabled. */
3162 if (spi_format &
3163 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3164 last_color_export = i;
3165 continue;
3166 }
3167
3168 if ((spi_format >> (index * 4)) & 0xf)
3169 last_color_export = i;
3170 }
3171
3172 /* If there are no outputs, export NULL. */
3173 if (last_color_export == -1) {
3174 si_export_null(bld_base);
3175 return;
3176 }
3177 }
3178
3179 for (i = 0; i < info->num_outputs; i++) {
3180 unsigned semantic_name = info->output_semantic_name[i];
3181 unsigned semantic_index = info->output_semantic_index[i];
3182 unsigned j;
3183 LLVMValueRef color[4] = {};
3184
3185 /* Select the correct target */
3186 switch (semantic_name) {
3187 case TGSI_SEMANTIC_POSITION:
3188 depth = LLVMBuildLoad(builder,
3189 ctx->radeon_bld.soa.outputs[i][2], "");
3190 break;
3191 case TGSI_SEMANTIC_STENCIL:
3192 stencil = LLVMBuildLoad(builder,
3193 ctx->radeon_bld.soa.outputs[i][1], "");
3194 break;
3195 case TGSI_SEMANTIC_SAMPLEMASK:
3196 samplemask = LLVMBuildLoad(builder,
3197 ctx->radeon_bld.soa.outputs[i][0], "");
3198 break;
3199 case TGSI_SEMANTIC_COLOR:
3200 for (j = 0; j < 4; j++)
3201 color[j] = LLVMBuildLoad(builder,
3202 ctx->radeon_bld.soa.outputs[i][j], "");
3203
3204 si_export_mrt_color(bld_base, color, semantic_index,
3205 SI_PARAM_SAMPLE_COVERAGE,
3206 last_color_export == i, &exp);
3207 break;
3208 default:
3209 fprintf(stderr,
3210 "Warning: SI unhandled fs output type:%d\n",
3211 semantic_name);
3212 }
3213 }
3214
3215 if (depth || stencil || samplemask)
3216 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
3217
3218 si_emit_ps_exports(ctx, &exp);
3219 }
3220
3221 /**
3222 * Return PS outputs in this order:
3223 *
3224 * v[0:3] = color0.xyzw
3225 * v[4:7] = color1.xyzw
3226 * ...
3227 * vN+0 = Depth
3228 * vN+1 = Stencil
3229 * vN+2 = SampleMask
3230 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3231 *
3232 * The alpha-ref SGPR is returned via its original location.
3233 */
3234 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3235 {
3236 struct si_shader_context *ctx = si_shader_context(bld_base);
3237 struct si_shader *shader = ctx->shader;
3238 struct lp_build_context *base = &bld_base->base;
3239 struct tgsi_shader_info *info = &shader->selector->info;
3240 LLVMBuilderRef builder = base->gallivm->builder;
3241 unsigned i, j, first_vgpr, vgpr;
3242
3243 LLVMValueRef color[8][4] = {};
3244 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3245 LLVMValueRef ret;
3246
3247 /* Read the output values. */
3248 for (i = 0; i < info->num_outputs; i++) {
3249 unsigned semantic_name = info->output_semantic_name[i];
3250 unsigned semantic_index = info->output_semantic_index[i];
3251
3252 switch (semantic_name) {
3253 case TGSI_SEMANTIC_COLOR:
3254 assert(semantic_index < 8);
3255 for (j = 0; j < 4; j++) {
3256 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3257 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3258 color[semantic_index][j] = result;
3259 }
3260 break;
3261 case TGSI_SEMANTIC_POSITION:
3262 depth = LLVMBuildLoad(builder,
3263 ctx->radeon_bld.soa.outputs[i][2], "");
3264 break;
3265 case TGSI_SEMANTIC_STENCIL:
3266 stencil = LLVMBuildLoad(builder,
3267 ctx->radeon_bld.soa.outputs[i][1], "");
3268 break;
3269 case TGSI_SEMANTIC_SAMPLEMASK:
3270 samplemask = LLVMBuildLoad(builder,
3271 ctx->radeon_bld.soa.outputs[i][0], "");
3272 break;
3273 default:
3274 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3275 semantic_name);
3276 }
3277 }
3278
3279 /* Fill the return structure. */
3280 ret = ctx->return_value;
3281
3282 /* Set SGPRs. */
3283 ret = LLVMBuildInsertValue(builder, ret,
3284 bitcast(bld_base, TGSI_TYPE_SIGNED,
3285 LLVMGetParam(ctx->radeon_bld.main_fn,
3286 SI_PARAM_ALPHA_REF)),
3287 SI_SGPR_ALPHA_REF, "");
3288
3289 /* Set VGPRs */
3290 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3291 for (i = 0; i < ARRAY_SIZE(color); i++) {
3292 if (!color[i][0])
3293 continue;
3294
3295 for (j = 0; j < 4; j++)
3296 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3297 }
3298 if (depth)
3299 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3300 if (stencil)
3301 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3302 if (samplemask)
3303 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3304
3305 /* Add the input sample mask for smoothing at the end. */
3306 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3307 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3308 ret = LLVMBuildInsertValue(builder, ret,
3309 LLVMGetParam(ctx->radeon_bld.main_fn,
3310 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3311
3312 ctx->return_value = ret;
3313 }
3314
3315 /**
3316 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3317 * buffer in number of elements and return it as an i32.
3318 */
3319 static LLVMValueRef get_buffer_size(
3320 struct lp_build_tgsi_context *bld_base,
3321 LLVMValueRef descriptor)
3322 {
3323 struct si_shader_context *ctx = si_shader_context(bld_base);
3324 struct gallivm_state *gallivm = bld_base->base.gallivm;
3325 LLVMBuilderRef builder = gallivm->builder;
3326 LLVMValueRef size =
3327 LLVMBuildExtractElement(builder, descriptor,
3328 lp_build_const_int32(gallivm, 6), "");
3329
3330 if (ctx->screen->b.chip_class >= VI) {
3331 /* On VI, the descriptor contains the size in bytes,
3332 * but TXQ must return the size in elements.
3333 * The stride is always non-zero for resources using TXQ.
3334 */
3335 LLVMValueRef stride =
3336 LLVMBuildExtractElement(builder, descriptor,
3337 lp_build_const_int32(gallivm, 5), "");
3338 stride = LLVMBuildLShr(builder, stride,
3339 lp_build_const_int32(gallivm, 16), "");
3340 stride = LLVMBuildAnd(builder, stride,
3341 lp_build_const_int32(gallivm, 0x3FFF), "");
3342
3343 size = LLVMBuildUDiv(builder, size, stride, "");
3344 }
3345
3346 return size;
3347 }
3348
3349 /**
3350 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3351 * intrinsic names).
3352 */
3353 static void build_int_type_name(
3354 LLVMTypeRef type,
3355 char *buf, unsigned bufsize)
3356 {
3357 assert(bufsize >= 6);
3358
3359 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3360 snprintf(buf, bufsize, "v%ui32",
3361 LLVMGetVectorSize(type));
3362 else
3363 strcpy(buf, "i32");
3364 }
3365
3366 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3367 struct lp_build_tgsi_context *bld_base,
3368 struct lp_build_emit_data *emit_data);
3369
3370 /* Prevent optimizations (at least of memory accesses) across the current
3371 * point in the program by emitting empty inline assembly that is marked as
3372 * having side effects.
3373 */
3374 static void emit_optimization_barrier(struct si_shader_context *ctx)
3375 {
3376 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3377 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3378 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3379 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3380 }
3381
3382 static void emit_waitcnt(struct si_shader_context *ctx)
3383 {
3384 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3385 LLVMBuilderRef builder = gallivm->builder;
3386 LLVMValueRef args[1] = {
3387 lp_build_const_int32(gallivm, 0xf70)
3388 };
3389 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3390 ctx->voidt, args, 1, 0);
3391 }
3392
3393 static void membar_emit(
3394 const struct lp_build_tgsi_action *action,
3395 struct lp_build_tgsi_context *bld_base,
3396 struct lp_build_emit_data *emit_data)
3397 {
3398 struct si_shader_context *ctx = si_shader_context(bld_base);
3399
3400 emit_waitcnt(ctx);
3401 }
3402
3403 static LLVMValueRef
3404 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3405 const struct tgsi_full_src_register *reg)
3406 {
3407 LLVMValueRef ind_index;
3408 LLVMValueRef rsrc_ptr;
3409
3410 if (!reg->Register.Indirect)
3411 return ctx->shader_buffers[reg->Register.Index];
3412
3413 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3414 reg->Register.Index,
3415 SI_NUM_SHADER_BUFFERS);
3416
3417 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3418 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3419 }
3420
3421 static bool tgsi_is_array_sampler(unsigned target)
3422 {
3423 return target == TGSI_TEXTURE_1D_ARRAY ||
3424 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3425 target == TGSI_TEXTURE_2D_ARRAY ||
3426 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3427 target == TGSI_TEXTURE_CUBE_ARRAY ||
3428 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3429 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3430 }
3431
3432 static bool tgsi_is_array_image(unsigned target)
3433 {
3434 return target == TGSI_TEXTURE_3D ||
3435 target == TGSI_TEXTURE_CUBE ||
3436 target == TGSI_TEXTURE_1D_ARRAY ||
3437 target == TGSI_TEXTURE_2D_ARRAY ||
3438 target == TGSI_TEXTURE_CUBE_ARRAY ||
3439 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3440 }
3441
3442 /**
3443 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3444 *
3445 * At least on Tonga, executing image stores on images with DCC enabled and
3446 * non-trivial can eventually lead to lockups. This can occur when an
3447 * application binds an image as read-only but then uses a shader that writes
3448 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3449 * program termination) in this case, but it doesn't cost much to be a bit
3450 * nicer: disabling DCC in the shader still leads to undefined results but
3451 * avoids the lockup.
3452 */
3453 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3454 LLVMValueRef rsrc)
3455 {
3456 if (ctx->screen->b.chip_class <= CIK) {
3457 return rsrc;
3458 } else {
3459 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3460 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3461 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3462 LLVMValueRef tmp;
3463
3464 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3465 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3466 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3467 }
3468 }
3469
3470 /**
3471 * Load the resource descriptor for \p image.
3472 */
3473 static void
3474 image_fetch_rsrc(
3475 struct lp_build_tgsi_context *bld_base,
3476 const struct tgsi_full_src_register *image,
3477 bool dcc_off,
3478 LLVMValueRef *rsrc)
3479 {
3480 struct si_shader_context *ctx = si_shader_context(bld_base);
3481
3482 assert(image->Register.File == TGSI_FILE_IMAGE);
3483
3484 if (!image->Register.Indirect) {
3485 /* Fast path: use preloaded resources */
3486 *rsrc = ctx->images[image->Register.Index];
3487 } else {
3488 /* Indexing and manual load */
3489 LLVMValueRef ind_index;
3490 LLVMValueRef rsrc_ptr;
3491 LLVMValueRef tmp;
3492
3493 /* From the GL_ARB_shader_image_load_store extension spec:
3494 *
3495 * If a shader performs an image load, store, or atomic
3496 * operation using an image variable declared as an array,
3497 * and if the index used to select an individual element is
3498 * negative or greater than or equal to the size of the
3499 * array, the results of the operation are undefined but may
3500 * not lead to termination.
3501 */
3502 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3503 image->Register.Index,
3504 SI_NUM_IMAGES);
3505
3506 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3507 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3508 if (dcc_off)
3509 tmp = force_dcc_off(ctx, tmp);
3510 *rsrc = tmp;
3511 }
3512 }
3513
3514 static LLVMValueRef image_fetch_coords(
3515 struct lp_build_tgsi_context *bld_base,
3516 const struct tgsi_full_instruction *inst,
3517 unsigned src)
3518 {
3519 struct gallivm_state *gallivm = bld_base->base.gallivm;
3520 LLVMBuilderRef builder = gallivm->builder;
3521 unsigned target = inst->Memory.Texture;
3522 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3523 LLVMValueRef coords[4];
3524 LLVMValueRef tmp;
3525 int chan;
3526
3527 for (chan = 0; chan < num_coords; ++chan) {
3528 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3529 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3530 coords[chan] = tmp;
3531 }
3532
3533 if (num_coords == 1)
3534 return coords[0];
3535
3536 if (num_coords == 3) {
3537 /* LLVM has difficulties lowering 3-element vectors. */
3538 coords[3] = bld_base->uint_bld.undef;
3539 num_coords = 4;
3540 }
3541
3542 return lp_build_gather_values(gallivm, coords, num_coords);
3543 }
3544
3545 /**
3546 * Append the extra mode bits that are used by image load and store.
3547 */
3548 static void image_append_args(
3549 struct si_shader_context *ctx,
3550 struct lp_build_emit_data * emit_data,
3551 unsigned target,
3552 bool atomic)
3553 {
3554 const struct tgsi_full_instruction *inst = emit_data->inst;
3555 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3556 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3557
3558 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3559 emit_data->args[emit_data->arg_count++] =
3560 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3561 if (!atomic) {
3562 emit_data->args[emit_data->arg_count++] =
3563 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3564 i1true : i1false; /* glc */
3565 }
3566 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3567 }
3568
3569 /**
3570 * Given a 256 bit resource, extract the top half (which stores the buffer
3571 * resource in the case of textures and images).
3572 */
3573 static LLVMValueRef extract_rsrc_top_half(
3574 struct si_shader_context *ctx,
3575 LLVMValueRef rsrc)
3576 {
3577 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3578 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3579 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3580
3581 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3582 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3583 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3584
3585 return rsrc;
3586 }
3587
3588 /**
3589 * Append the resource and indexing arguments for buffer intrinsics.
3590 *
3591 * \param rsrc the v4i32 buffer resource
3592 * \param index index into the buffer (stride-based)
3593 * \param offset byte offset into the buffer
3594 */
3595 static void buffer_append_args(
3596 struct si_shader_context *ctx,
3597 struct lp_build_emit_data *emit_data,
3598 LLVMValueRef rsrc,
3599 LLVMValueRef index,
3600 LLVMValueRef offset,
3601 bool atomic)
3602 {
3603 const struct tgsi_full_instruction *inst = emit_data->inst;
3604 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3605 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3606
3607 emit_data->args[emit_data->arg_count++] = rsrc;
3608 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3609 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3610 if (!atomic) {
3611 emit_data->args[emit_data->arg_count++] =
3612 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3613 i1true : i1false; /* glc */
3614 }
3615 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3616 }
3617
3618 static void load_fetch_args(
3619 struct lp_build_tgsi_context * bld_base,
3620 struct lp_build_emit_data * emit_data)
3621 {
3622 struct si_shader_context *ctx = si_shader_context(bld_base);
3623 struct gallivm_state *gallivm = bld_base->base.gallivm;
3624 const struct tgsi_full_instruction * inst = emit_data->inst;
3625 unsigned target = inst->Memory.Texture;
3626 LLVMValueRef rsrc;
3627
3628 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3629
3630 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3631 LLVMBuilderRef builder = gallivm->builder;
3632 LLVMValueRef offset;
3633 LLVMValueRef tmp;
3634
3635 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3636
3637 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3638 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3639
3640 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3641 offset, false);
3642 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3643 LLVMValueRef coords;
3644
3645 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3646 coords = image_fetch_coords(bld_base, inst, 1);
3647
3648 if (target == TGSI_TEXTURE_BUFFER) {
3649 rsrc = extract_rsrc_top_half(ctx, rsrc);
3650 buffer_append_args(ctx, emit_data, rsrc, coords,
3651 bld_base->uint_bld.zero, false);
3652 } else {
3653 emit_data->args[0] = coords;
3654 emit_data->args[1] = rsrc;
3655 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3656 emit_data->arg_count = 3;
3657
3658 image_append_args(ctx, emit_data, target, false);
3659 }
3660 }
3661 }
3662
3663 static void load_emit_buffer(struct si_shader_context *ctx,
3664 struct lp_build_emit_data *emit_data)
3665 {
3666 const struct tgsi_full_instruction *inst = emit_data->inst;
3667 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3668 LLVMBuilderRef builder = gallivm->builder;
3669 uint writemask = inst->Dst[0].Register.WriteMask;
3670 uint count = util_last_bit(writemask);
3671 const char *intrinsic_name;
3672 LLVMTypeRef dst_type;
3673
3674 switch (count) {
3675 case 1:
3676 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3677 dst_type = ctx->f32;
3678 break;
3679 case 2:
3680 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3681 dst_type = LLVMVectorType(ctx->f32, 2);
3682 break;
3683 default: // 3 & 4
3684 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3685 dst_type = ctx->v4f32;
3686 count = 4;
3687 }
3688
3689 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3690 builder, intrinsic_name, dst_type,
3691 emit_data->args, emit_data->arg_count,
3692 LLVMReadOnlyAttribute);
3693 }
3694
3695 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3696 const struct tgsi_full_instruction *inst,
3697 LLVMTypeRef type, int arg)
3698 {
3699 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3700 LLVMBuilderRef builder = gallivm->builder;
3701 LLVMValueRef offset, ptr;
3702 int addr_space;
3703
3704 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3705 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3706
3707 ptr = ctx->shared_memory;
3708 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3709 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3710 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3711
3712 return ptr;
3713 }
3714
3715 static void load_emit_memory(
3716 struct si_shader_context *ctx,
3717 struct lp_build_emit_data *emit_data)
3718 {
3719 const struct tgsi_full_instruction *inst = emit_data->inst;
3720 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3721 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3722 LLVMBuilderRef builder = gallivm->builder;
3723 unsigned writemask = inst->Dst[0].Register.WriteMask;
3724 LLVMValueRef channels[4], ptr, derived_ptr, index;
3725 int chan;
3726
3727 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3728
3729 for (chan = 0; chan < 4; ++chan) {
3730 if (!(writemask & (1 << chan))) {
3731 channels[chan] = LLVMGetUndef(base->elem_type);
3732 continue;
3733 }
3734
3735 index = lp_build_const_int32(gallivm, chan);
3736 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3737 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3738 }
3739 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3740 }
3741
3742 static void load_emit(
3743 const struct lp_build_tgsi_action *action,
3744 struct lp_build_tgsi_context *bld_base,
3745 struct lp_build_emit_data *emit_data)
3746 {
3747 struct si_shader_context *ctx = si_shader_context(bld_base);
3748 struct gallivm_state *gallivm = bld_base->base.gallivm;
3749 LLVMBuilderRef builder = gallivm->builder;
3750 const struct tgsi_full_instruction * inst = emit_data->inst;
3751 char intrinsic_name[32];
3752 char coords_type[8];
3753
3754 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3755 load_emit_memory(ctx, emit_data);
3756 return;
3757 }
3758
3759 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3760 emit_waitcnt(ctx);
3761
3762 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3763 load_emit_buffer(ctx, emit_data);
3764 return;
3765 }
3766
3767 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3768 emit_data->output[emit_data->chan] =
3769 lp_build_intrinsic(
3770 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3771 emit_data->args, emit_data->arg_count,
3772 LLVMReadOnlyAttribute);
3773 } else {
3774 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3775 coords_type, sizeof(coords_type));
3776
3777 snprintf(intrinsic_name, sizeof(intrinsic_name),
3778 "llvm.amdgcn.image.load.%s", coords_type);
3779
3780 emit_data->output[emit_data->chan] =
3781 lp_build_intrinsic(
3782 builder, intrinsic_name, emit_data->dst_type,
3783 emit_data->args, emit_data->arg_count,
3784 LLVMReadOnlyAttribute);
3785 }
3786 }
3787
3788 static void store_fetch_args(
3789 struct lp_build_tgsi_context * bld_base,
3790 struct lp_build_emit_data * emit_data)
3791 {
3792 struct si_shader_context *ctx = si_shader_context(bld_base);
3793 struct gallivm_state *gallivm = bld_base->base.gallivm;
3794 LLVMBuilderRef builder = gallivm->builder;
3795 const struct tgsi_full_instruction * inst = emit_data->inst;
3796 struct tgsi_full_src_register memory;
3797 LLVMValueRef chans[4];
3798 LLVMValueRef data;
3799 LLVMValueRef rsrc;
3800 unsigned chan;
3801
3802 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3803
3804 for (chan = 0; chan < 4; ++chan) {
3805 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3806 }
3807 data = lp_build_gather_values(gallivm, chans, 4);
3808
3809 emit_data->args[emit_data->arg_count++] = data;
3810
3811 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3812
3813 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3814 LLVMValueRef offset;
3815 LLVMValueRef tmp;
3816
3817 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3818
3819 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3820 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3821
3822 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3823 offset, false);
3824 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3825 unsigned target = inst->Memory.Texture;
3826 LLVMValueRef coords;
3827
3828 coords = image_fetch_coords(bld_base, inst, 0);
3829
3830 if (target == TGSI_TEXTURE_BUFFER) {
3831 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3832
3833 rsrc = extract_rsrc_top_half(ctx, rsrc);
3834 buffer_append_args(ctx, emit_data, rsrc, coords,
3835 bld_base->uint_bld.zero, false);
3836 } else {
3837 emit_data->args[1] = coords;
3838 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3839 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3840 emit_data->arg_count = 4;
3841
3842 image_append_args(ctx, emit_data, target, false);
3843 }
3844 }
3845 }
3846
3847 static void store_emit_buffer(
3848 struct si_shader_context *ctx,
3849 struct lp_build_emit_data *emit_data)
3850 {
3851 const struct tgsi_full_instruction *inst = emit_data->inst;
3852 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3853 LLVMBuilderRef builder = gallivm->builder;
3854 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3855 LLVMValueRef base_data = emit_data->args[0];
3856 LLVMValueRef base_offset = emit_data->args[3];
3857 unsigned writemask = inst->Dst[0].Register.WriteMask;
3858
3859 while (writemask) {
3860 int start, count;
3861 const char *intrinsic_name;
3862 LLVMValueRef data;
3863 LLVMValueRef offset;
3864 LLVMValueRef tmp;
3865
3866 u_bit_scan_consecutive_range(&writemask, &start, &count);
3867
3868 /* Due to an LLVM limitation, split 3-element writes
3869 * into a 2-element and a 1-element write. */
3870 if (count == 3) {
3871 writemask |= 1 << (start + 2);
3872 count = 2;
3873 }
3874
3875 if (count == 4) {
3876 data = base_data;
3877 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3878 } else if (count == 2) {
3879 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3880
3881 tmp = LLVMBuildExtractElement(
3882 builder, base_data,
3883 lp_build_const_int32(gallivm, start), "");
3884 data = LLVMBuildInsertElement(
3885 builder, LLVMGetUndef(v2f32), tmp,
3886 uint_bld->zero, "");
3887
3888 tmp = LLVMBuildExtractElement(
3889 builder, base_data,
3890 lp_build_const_int32(gallivm, start + 1), "");
3891 data = LLVMBuildInsertElement(
3892 builder, data, tmp, uint_bld->one, "");
3893
3894 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3895 } else {
3896 assert(count == 1);
3897 data = LLVMBuildExtractElement(
3898 builder, base_data,
3899 lp_build_const_int32(gallivm, start), "");
3900 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3901 }
3902
3903 offset = base_offset;
3904 if (start != 0) {
3905 offset = LLVMBuildAdd(
3906 builder, offset,
3907 lp_build_const_int32(gallivm, start * 4), "");
3908 }
3909
3910 emit_data->args[0] = data;
3911 emit_data->args[3] = offset;
3912
3913 lp_build_intrinsic(
3914 builder, intrinsic_name, emit_data->dst_type,
3915 emit_data->args, emit_data->arg_count, 0);
3916 }
3917 }
3918
3919 static void store_emit_memory(
3920 struct si_shader_context *ctx,
3921 struct lp_build_emit_data *emit_data)
3922 {
3923 const struct tgsi_full_instruction *inst = emit_data->inst;
3924 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3925 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3926 LLVMBuilderRef builder = gallivm->builder;
3927 unsigned writemask = inst->Dst[0].Register.WriteMask;
3928 LLVMValueRef ptr, derived_ptr, data, index;
3929 int chan;
3930
3931 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3932
3933 for (chan = 0; chan < 4; ++chan) {
3934 if (!(writemask & (1 << chan))) {
3935 continue;
3936 }
3937 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3938 index = lp_build_const_int32(gallivm, chan);
3939 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3940 LLVMBuildStore(builder, data, derived_ptr);
3941 }
3942 }
3943
3944 static void store_emit(
3945 const struct lp_build_tgsi_action *action,
3946 struct lp_build_tgsi_context *bld_base,
3947 struct lp_build_emit_data *emit_data)
3948 {
3949 struct si_shader_context *ctx = si_shader_context(bld_base);
3950 struct gallivm_state *gallivm = bld_base->base.gallivm;
3951 LLVMBuilderRef builder = gallivm->builder;
3952 const struct tgsi_full_instruction * inst = emit_data->inst;
3953 unsigned target = inst->Memory.Texture;
3954 char intrinsic_name[32];
3955 char coords_type[8];
3956
3957 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3958 store_emit_memory(ctx, emit_data);
3959 return;
3960 }
3961
3962 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3963 emit_waitcnt(ctx);
3964
3965 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3966 store_emit_buffer(ctx, emit_data);
3967 return;
3968 }
3969
3970 if (target == TGSI_TEXTURE_BUFFER) {
3971 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3972 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3973 emit_data->dst_type, emit_data->args,
3974 emit_data->arg_count, 0);
3975 } else {
3976 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3977 coords_type, sizeof(coords_type));
3978 snprintf(intrinsic_name, sizeof(intrinsic_name),
3979 "llvm.amdgcn.image.store.%s", coords_type);
3980
3981 emit_data->output[emit_data->chan] =
3982 lp_build_intrinsic(
3983 builder, intrinsic_name, emit_data->dst_type,
3984 emit_data->args, emit_data->arg_count, 0);
3985 }
3986 }
3987
3988 static void atomic_fetch_args(
3989 struct lp_build_tgsi_context * bld_base,
3990 struct lp_build_emit_data * emit_data)
3991 {
3992 struct si_shader_context *ctx = si_shader_context(bld_base);
3993 struct gallivm_state *gallivm = bld_base->base.gallivm;
3994 LLVMBuilderRef builder = gallivm->builder;
3995 const struct tgsi_full_instruction * inst = emit_data->inst;
3996 LLVMValueRef data1, data2;
3997 LLVMValueRef rsrc;
3998 LLVMValueRef tmp;
3999
4000 emit_data->dst_type = bld_base->base.elem_type;
4001
4002 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4003 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4004
4005 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4006 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4007 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4008 }
4009
4010 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4011 * of arguments, which is reversed relative to TGSI (and GLSL)
4012 */
4013 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4014 emit_data->args[emit_data->arg_count++] = data2;
4015 emit_data->args[emit_data->arg_count++] = data1;
4016
4017 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4018 LLVMValueRef offset;
4019
4020 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4021
4022 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4023 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4024
4025 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4026 offset, true);
4027 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4028 unsigned target = inst->Memory.Texture;
4029 LLVMValueRef coords;
4030
4031 image_fetch_rsrc(bld_base, &inst->Src[0],
4032 target != TGSI_TEXTURE_BUFFER, &rsrc);
4033 coords = image_fetch_coords(bld_base, inst, 1);
4034
4035 if (target == TGSI_TEXTURE_BUFFER) {
4036 rsrc = extract_rsrc_top_half(ctx, rsrc);
4037 buffer_append_args(ctx, emit_data, rsrc, coords,
4038 bld_base->uint_bld.zero, true);
4039 } else {
4040 emit_data->args[emit_data->arg_count++] = coords;
4041 emit_data->args[emit_data->arg_count++] = rsrc;
4042
4043 image_append_args(ctx, emit_data, target, true);
4044 }
4045 }
4046 }
4047
4048 static void atomic_emit_memory(struct si_shader_context *ctx,
4049 struct lp_build_emit_data *emit_data) {
4050 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4051 LLVMBuilderRef builder = gallivm->builder;
4052 const struct tgsi_full_instruction * inst = emit_data->inst;
4053 LLVMValueRef ptr, result, arg;
4054
4055 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4056
4057 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
4058 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4059
4060 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4061 LLVMValueRef new_data;
4062 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
4063 inst, 3, 0);
4064
4065 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4066
4067 #if HAVE_LLVM >= 0x309
4068 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4069 LLVMAtomicOrderingSequentiallyConsistent,
4070 LLVMAtomicOrderingSequentiallyConsistent,
4071 false);
4072 #endif
4073
4074 result = LLVMBuildExtractValue(builder, result, 0, "");
4075 } else {
4076 LLVMAtomicRMWBinOp op;
4077
4078 switch(inst->Instruction.Opcode) {
4079 case TGSI_OPCODE_ATOMUADD:
4080 op = LLVMAtomicRMWBinOpAdd;
4081 break;
4082 case TGSI_OPCODE_ATOMXCHG:
4083 op = LLVMAtomicRMWBinOpXchg;
4084 break;
4085 case TGSI_OPCODE_ATOMAND:
4086 op = LLVMAtomicRMWBinOpAnd;
4087 break;
4088 case TGSI_OPCODE_ATOMOR:
4089 op = LLVMAtomicRMWBinOpOr;
4090 break;
4091 case TGSI_OPCODE_ATOMXOR:
4092 op = LLVMAtomicRMWBinOpXor;
4093 break;
4094 case TGSI_OPCODE_ATOMUMIN:
4095 op = LLVMAtomicRMWBinOpUMin;
4096 break;
4097 case TGSI_OPCODE_ATOMUMAX:
4098 op = LLVMAtomicRMWBinOpUMax;
4099 break;
4100 case TGSI_OPCODE_ATOMIMIN:
4101 op = LLVMAtomicRMWBinOpMin;
4102 break;
4103 case TGSI_OPCODE_ATOMIMAX:
4104 op = LLVMAtomicRMWBinOpMax;
4105 break;
4106 default:
4107 unreachable("unknown atomic opcode");
4108 }
4109
4110 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4111 LLVMAtomicOrderingSequentiallyConsistent,
4112 false);
4113 }
4114 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4115 }
4116
4117 static void atomic_emit(
4118 const struct lp_build_tgsi_action *action,
4119 struct lp_build_tgsi_context *bld_base,
4120 struct lp_build_emit_data *emit_data)
4121 {
4122 struct si_shader_context *ctx = si_shader_context(bld_base);
4123 struct gallivm_state *gallivm = bld_base->base.gallivm;
4124 LLVMBuilderRef builder = gallivm->builder;
4125 const struct tgsi_full_instruction * inst = emit_data->inst;
4126 char intrinsic_name[40];
4127 LLVMValueRef tmp;
4128
4129 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4130 atomic_emit_memory(ctx, emit_data);
4131 return;
4132 }
4133
4134 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4135 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4136 snprintf(intrinsic_name, sizeof(intrinsic_name),
4137 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4138 } else {
4139 char coords_type[8];
4140
4141 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4142 coords_type, sizeof(coords_type));
4143 snprintf(intrinsic_name, sizeof(intrinsic_name),
4144 "llvm.amdgcn.image.atomic.%s.%s",
4145 action->intr_name, coords_type);
4146 }
4147
4148 tmp = lp_build_intrinsic(
4149 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4150 emit_data->args, emit_data->arg_count, 0);
4151 emit_data->output[emit_data->chan] =
4152 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4153 }
4154
4155 static void resq_fetch_args(
4156 struct lp_build_tgsi_context * bld_base,
4157 struct lp_build_emit_data * emit_data)
4158 {
4159 struct si_shader_context *ctx = si_shader_context(bld_base);
4160 struct gallivm_state *gallivm = bld_base->base.gallivm;
4161 const struct tgsi_full_instruction *inst = emit_data->inst;
4162 const struct tgsi_full_src_register *reg = &inst->Src[0];
4163
4164 emit_data->dst_type = ctx->v4i32;
4165
4166 if (reg->Register.File == TGSI_FILE_BUFFER) {
4167 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4168 emit_data->arg_count = 1;
4169 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4170 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4171 emit_data->arg_count = 1;
4172 } else {
4173 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4174 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4175 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4176 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4177 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4178 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4179 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4180 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4181 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4182 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4183 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4184 emit_data->arg_count = 10;
4185 }
4186 }
4187
4188 static void resq_emit(
4189 const struct lp_build_tgsi_action *action,
4190 struct lp_build_tgsi_context *bld_base,
4191 struct lp_build_emit_data *emit_data)
4192 {
4193 struct gallivm_state *gallivm = bld_base->base.gallivm;
4194 LLVMBuilderRef builder = gallivm->builder;
4195 const struct tgsi_full_instruction *inst = emit_data->inst;
4196 LLVMValueRef out;
4197
4198 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4199 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4200 lp_build_const_int32(gallivm, 2), "");
4201 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4202 out = get_buffer_size(bld_base, emit_data->args[0]);
4203 } else {
4204 out = lp_build_intrinsic(
4205 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4206 emit_data->args, emit_data->arg_count,
4207 LLVMReadNoneAttribute);
4208
4209 /* Divide the number of layers by 6 to get the number of cubes. */
4210 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4211 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4212 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4213
4214 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4215 z = LLVMBuildSDiv(builder, z, imm6, "");
4216 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4217 }
4218 }
4219
4220 emit_data->output[emit_data->chan] = out;
4221 }
4222
4223 static void set_tex_fetch_args(struct si_shader_context *ctx,
4224 struct lp_build_emit_data *emit_data,
4225 unsigned opcode, unsigned target,
4226 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4227 LLVMValueRef *param, unsigned count,
4228 unsigned dmask)
4229 {
4230 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4231 unsigned num_args;
4232 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4233
4234 /* Pad to power of two vector */
4235 while (count < util_next_power_of_two(count))
4236 param[count++] = LLVMGetUndef(ctx->i32);
4237
4238 /* Texture coordinates. */
4239 if (count > 1)
4240 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4241 else
4242 emit_data->args[0] = param[0];
4243
4244 /* Resource. */
4245 emit_data->args[1] = res_ptr;
4246 num_args = 2;
4247
4248 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4249 emit_data->dst_type = ctx->v4i32;
4250 else {
4251 emit_data->dst_type = ctx->v4f32;
4252
4253 emit_data->args[num_args++] = samp_ptr;
4254 }
4255
4256 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4257 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4258 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4259 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4260 tgsi_is_array_sampler(target)); /* da */
4261 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4262 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4263 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4264 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4265
4266 emit_data->arg_count = num_args;
4267 }
4268
4269 static const struct lp_build_tgsi_action tex_action;
4270
4271 enum desc_type {
4272 DESC_IMAGE,
4273 DESC_FMASK,
4274 DESC_SAMPLER
4275 };
4276
4277 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4278 {
4279 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4280 CONST_ADDR_SPACE);
4281 }
4282
4283 /**
4284 * Load an image view, fmask view. or sampler state descriptor.
4285 */
4286 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4287 LLVMValueRef list, LLVMValueRef index,
4288 enum desc_type type)
4289 {
4290 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4291 LLVMBuilderRef builder = gallivm->builder;
4292
4293 switch (type) {
4294 case DESC_IMAGE:
4295 /* The image is at [0:7]. */
4296 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4297 break;
4298 case DESC_FMASK:
4299 /* The FMASK is at [8:15]. */
4300 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4301 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4302 break;
4303 case DESC_SAMPLER:
4304 /* The sampler state is at [12:15]. */
4305 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4306 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4307 list = LLVMBuildPointerCast(builder, list,
4308 const_array(ctx->v4i32, 0), "");
4309 break;
4310 }
4311
4312 return build_indexed_load_const(ctx, list, index);
4313 }
4314
4315 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4316 LLVMValueRef index, enum desc_type type)
4317 {
4318 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4319 SI_PARAM_SAMPLERS);
4320
4321 return get_sampler_desc_custom(ctx, list, index, type);
4322 }
4323
4324 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4325 *
4326 * SI-CI:
4327 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4328 * filtering manually. The driver sets img7 to a mask clearing
4329 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4330 * s_and_b32 samp0, samp0, img7
4331 *
4332 * VI:
4333 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4334 */
4335 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4336 LLVMValueRef res, LLVMValueRef samp)
4337 {
4338 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4339 LLVMValueRef img7, samp0;
4340
4341 if (ctx->screen->b.chip_class >= VI)
4342 return samp;
4343
4344 img7 = LLVMBuildExtractElement(builder, res,
4345 LLVMConstInt(ctx->i32, 7, 0), "");
4346 samp0 = LLVMBuildExtractElement(builder, samp,
4347 LLVMConstInt(ctx->i32, 0, 0), "");
4348 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4349 return LLVMBuildInsertElement(builder, samp, samp0,
4350 LLVMConstInt(ctx->i32, 0, 0), "");
4351 }
4352
4353 static void tex_fetch_ptrs(
4354 struct lp_build_tgsi_context *bld_base,
4355 struct lp_build_emit_data *emit_data,
4356 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4357 {
4358 struct si_shader_context *ctx = si_shader_context(bld_base);
4359 const struct tgsi_full_instruction *inst = emit_data->inst;
4360 unsigned target = inst->Texture.Texture;
4361 unsigned sampler_src;
4362 unsigned sampler_index;
4363
4364 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4365 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4366
4367 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4368 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4369 LLVMValueRef ind_index;
4370
4371 ind_index = get_bounded_indirect_index(ctx,
4372 &reg->Indirect,
4373 reg->Register.Index,
4374 SI_NUM_SAMPLERS);
4375
4376 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4377
4378 if (target == TGSI_TEXTURE_2D_MSAA ||
4379 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4380 if (samp_ptr)
4381 *samp_ptr = NULL;
4382 if (fmask_ptr)
4383 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4384 } else {
4385 if (samp_ptr) {
4386 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4387 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4388 }
4389 if (fmask_ptr)
4390 *fmask_ptr = NULL;
4391 }
4392 } else {
4393 *res_ptr = ctx->sampler_views[sampler_index];
4394 if (samp_ptr)
4395 *samp_ptr = ctx->sampler_states[sampler_index];
4396 if (fmask_ptr)
4397 *fmask_ptr = ctx->fmasks[sampler_index];
4398 }
4399 }
4400
4401 static void txq_fetch_args(
4402 struct lp_build_tgsi_context *bld_base,
4403 struct lp_build_emit_data *emit_data)
4404 {
4405 struct si_shader_context *ctx = si_shader_context(bld_base);
4406 struct gallivm_state *gallivm = bld_base->base.gallivm;
4407 LLVMBuilderRef builder = gallivm->builder;
4408 const struct tgsi_full_instruction *inst = emit_data->inst;
4409 unsigned target = inst->Texture.Texture;
4410 LLVMValueRef res_ptr;
4411 LLVMValueRef address;
4412
4413 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4414
4415 if (target == TGSI_TEXTURE_BUFFER) {
4416 /* Read the size from the buffer descriptor directly. */
4417 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4418 emit_data->args[0] = get_buffer_size(bld_base, res);
4419 return;
4420 }
4421
4422 /* Textures - set the mip level. */
4423 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4424
4425 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4426 NULL, &address, 1, 0xf);
4427 }
4428
4429 static void txq_emit(const struct lp_build_tgsi_action *action,
4430 struct lp_build_tgsi_context *bld_base,
4431 struct lp_build_emit_data *emit_data)
4432 {
4433 struct lp_build_context *base = &bld_base->base;
4434 unsigned target = emit_data->inst->Texture.Texture;
4435
4436 if (target == TGSI_TEXTURE_BUFFER) {
4437 /* Just return the buffer size. */
4438 emit_data->output[emit_data->chan] = emit_data->args[0];
4439 return;
4440 }
4441
4442 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4443 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4444 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4445 LLVMReadNoneAttribute);
4446
4447 /* Divide the number of layers by 6 to get the number of cubes. */
4448 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4449 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4450 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4451 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4452 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4453
4454 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4455 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4456 z = LLVMBuildSDiv(builder, z, six, "");
4457
4458 emit_data->output[emit_data->chan] =
4459 LLVMBuildInsertElement(builder, v4, z, two, "");
4460 }
4461 }
4462
4463 static void tex_fetch_args(
4464 struct lp_build_tgsi_context *bld_base,
4465 struct lp_build_emit_data *emit_data)
4466 {
4467 struct si_shader_context *ctx = si_shader_context(bld_base);
4468 struct gallivm_state *gallivm = bld_base->base.gallivm;
4469 const struct tgsi_full_instruction *inst = emit_data->inst;
4470 unsigned opcode = inst->Instruction.Opcode;
4471 unsigned target = inst->Texture.Texture;
4472 LLVMValueRef coords[5], derivs[6];
4473 LLVMValueRef address[16];
4474 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4475 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4476 unsigned count = 0;
4477 unsigned chan;
4478 unsigned num_deriv_channels = 0;
4479 bool has_offset = inst->Texture.NumOffsets > 0;
4480 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4481 unsigned dmask = 0xf;
4482
4483 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4484
4485 if (target == TGSI_TEXTURE_BUFFER) {
4486 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4487
4488 /* Bitcast and truncate v8i32 to v16i8. */
4489 LLVMValueRef res = res_ptr;
4490 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4491 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4492 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4493
4494 emit_data->dst_type = ctx->v4f32;
4495 emit_data->args[0] = res;
4496 emit_data->args[1] = bld_base->uint_bld.zero;
4497 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4498 emit_data->arg_count = 3;
4499 return;
4500 }
4501
4502 /* Fetch and project texture coordinates */
4503 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4504 for (chan = 0; chan < 3; chan++ ) {
4505 coords[chan] = lp_build_emit_fetch(bld_base,
4506 emit_data->inst, 0,
4507 chan);
4508 if (opcode == TGSI_OPCODE_TXP)
4509 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4510 TGSI_OPCODE_DIV,
4511 coords[chan],
4512 coords[3]);
4513 }
4514
4515 if (opcode == TGSI_OPCODE_TXP)
4516 coords[3] = bld_base->base.one;
4517
4518 /* Pack offsets. */
4519 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4520 /* The offsets are six-bit signed integers packed like this:
4521 * X=[5:0], Y=[13:8], and Z=[21:16].
4522 */
4523 LLVMValueRef offset[3], pack;
4524
4525 assert(inst->Texture.NumOffsets == 1);
4526
4527 for (chan = 0; chan < 3; chan++) {
4528 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4529 emit_data->inst, 0, chan);
4530 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4531 lp_build_const_int32(gallivm, 0x3f), "");
4532 if (chan)
4533 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4534 lp_build_const_int32(gallivm, chan*8), "");
4535 }
4536
4537 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4538 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4539 address[count++] = pack;
4540 }
4541
4542 /* Pack LOD bias value */
4543 if (opcode == TGSI_OPCODE_TXB)
4544 address[count++] = coords[3];
4545 if (opcode == TGSI_OPCODE_TXB2)
4546 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4547
4548 /* Pack depth comparison value */
4549 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4550 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4551 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4552 } else {
4553 assert(ref_pos >= 0);
4554 address[count++] = coords[ref_pos];
4555 }
4556 }
4557
4558 /* Pack user derivatives */
4559 if (opcode == TGSI_OPCODE_TXD) {
4560 int param, num_src_deriv_channels;
4561
4562 switch (target) {
4563 case TGSI_TEXTURE_3D:
4564 num_src_deriv_channels = 3;
4565 num_deriv_channels = 3;
4566 break;
4567 case TGSI_TEXTURE_2D:
4568 case TGSI_TEXTURE_SHADOW2D:
4569 case TGSI_TEXTURE_RECT:
4570 case TGSI_TEXTURE_SHADOWRECT:
4571 case TGSI_TEXTURE_2D_ARRAY:
4572 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4573 num_src_deriv_channels = 2;
4574 num_deriv_channels = 2;
4575 break;
4576 case TGSI_TEXTURE_CUBE:
4577 case TGSI_TEXTURE_SHADOWCUBE:
4578 case TGSI_TEXTURE_CUBE_ARRAY:
4579 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4580 /* Cube derivatives will be converted to 2D. */
4581 num_src_deriv_channels = 3;
4582 num_deriv_channels = 2;
4583 break;
4584 case TGSI_TEXTURE_1D:
4585 case TGSI_TEXTURE_SHADOW1D:
4586 case TGSI_TEXTURE_1D_ARRAY:
4587 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4588 num_src_deriv_channels = 1;
4589 num_deriv_channels = 1;
4590 break;
4591 default:
4592 unreachable("invalid target");
4593 }
4594
4595 for (param = 0; param < 2; param++)
4596 for (chan = 0; chan < num_src_deriv_channels; chan++)
4597 derivs[param * num_src_deriv_channels + chan] =
4598 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4599 }
4600
4601 if (target == TGSI_TEXTURE_CUBE ||
4602 target == TGSI_TEXTURE_CUBE_ARRAY ||
4603 target == TGSI_TEXTURE_SHADOWCUBE ||
4604 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4605 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4606
4607 if (opcode == TGSI_OPCODE_TXD)
4608 for (int i = 0; i < num_deriv_channels * 2; i++)
4609 address[count++] = derivs[i];
4610
4611 /* Pack texture coordinates */
4612 address[count++] = coords[0];
4613 if (num_coords > 1)
4614 address[count++] = coords[1];
4615 if (num_coords > 2)
4616 address[count++] = coords[2];
4617
4618 /* Pack LOD or sample index */
4619 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4620 address[count++] = coords[3];
4621 else if (opcode == TGSI_OPCODE_TXL2)
4622 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4623
4624 if (count > 16) {
4625 assert(!"Cannot handle more than 16 texture address parameters");
4626 count = 16;
4627 }
4628
4629 for (chan = 0; chan < count; chan++ ) {
4630 address[chan] = LLVMBuildBitCast(gallivm->builder,
4631 address[chan], ctx->i32, "");
4632 }
4633
4634 /* Adjust the sample index according to FMASK.
4635 *
4636 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4637 * which is the identity mapping. Each nibble says which physical sample
4638 * should be fetched to get that sample.
4639 *
4640 * For example, 0x11111100 means there are only 2 samples stored and
4641 * the second sample covers 3/4 of the pixel. When reading samples 0
4642 * and 1, return physical sample 0 (determined by the first two 0s
4643 * in FMASK), otherwise return physical sample 1.
4644 *
4645 * The sample index should be adjusted as follows:
4646 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4647 */
4648 if (target == TGSI_TEXTURE_2D_MSAA ||
4649 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4650 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4651 struct lp_build_emit_data txf_emit_data = *emit_data;
4652 LLVMValueRef txf_address[4];
4653 unsigned txf_count = count;
4654 struct tgsi_full_instruction inst = {};
4655
4656 memcpy(txf_address, address, sizeof(txf_address));
4657
4658 if (target == TGSI_TEXTURE_2D_MSAA) {
4659 txf_address[2] = bld_base->uint_bld.zero;
4660 }
4661 txf_address[3] = bld_base->uint_bld.zero;
4662
4663 /* Read FMASK using TXF. */
4664 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4665 inst.Texture.Texture = target;
4666 txf_emit_data.inst = &inst;
4667 txf_emit_data.chan = 0;
4668 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4669 target, fmask_ptr, NULL,
4670 txf_address, txf_count, 0xf);
4671 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4672
4673 /* Initialize some constants. */
4674 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4675 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4676
4677 /* Apply the formula. */
4678 LLVMValueRef fmask =
4679 LLVMBuildExtractElement(gallivm->builder,
4680 txf_emit_data.output[0],
4681 uint_bld->zero, "");
4682
4683 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4684
4685 LLVMValueRef sample_index4 =
4686 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4687
4688 LLVMValueRef shifted_fmask =
4689 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4690
4691 LLVMValueRef final_sample =
4692 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4693
4694 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4695 * resource descriptor is 0 (invalid),
4696 */
4697 LLVMValueRef fmask_desc =
4698 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4699 ctx->v8i32, "");
4700
4701 LLVMValueRef fmask_word1 =
4702 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4703 uint_bld->one, "");
4704
4705 LLVMValueRef word1_is_nonzero =
4706 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4707 fmask_word1, uint_bld->zero, "");
4708
4709 /* Replace the MSAA sample index. */
4710 address[sample_chan] =
4711 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4712 final_sample, address[sample_chan], "");
4713 }
4714
4715 if (opcode == TGSI_OPCODE_TXF) {
4716 /* add tex offsets */
4717 if (inst->Texture.NumOffsets) {
4718 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4719 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4720 const struct tgsi_texture_offset *off = inst->TexOffsets;
4721
4722 assert(inst->Texture.NumOffsets == 1);
4723
4724 switch (target) {
4725 case TGSI_TEXTURE_3D:
4726 address[2] = lp_build_add(uint_bld, address[2],
4727 bld->immediates[off->Index][off->SwizzleZ]);
4728 /* fall through */
4729 case TGSI_TEXTURE_2D:
4730 case TGSI_TEXTURE_SHADOW2D:
4731 case TGSI_TEXTURE_RECT:
4732 case TGSI_TEXTURE_SHADOWRECT:
4733 case TGSI_TEXTURE_2D_ARRAY:
4734 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4735 address[1] =
4736 lp_build_add(uint_bld, address[1],
4737 bld->immediates[off->Index][off->SwizzleY]);
4738 /* fall through */
4739 case TGSI_TEXTURE_1D:
4740 case TGSI_TEXTURE_SHADOW1D:
4741 case TGSI_TEXTURE_1D_ARRAY:
4742 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4743 address[0] =
4744 lp_build_add(uint_bld, address[0],
4745 bld->immediates[off->Index][off->SwizzleX]);
4746 break;
4747 /* texture offsets do not apply to other texture targets */
4748 }
4749 }
4750 }
4751
4752 if (opcode == TGSI_OPCODE_TG4) {
4753 unsigned gather_comp = 0;
4754
4755 /* DMASK was repurposed for GATHER4. 4 components are always
4756 * returned and DMASK works like a swizzle - it selects
4757 * the component to fetch. The only valid DMASK values are
4758 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4759 * (red,red,red,red) etc.) The ISA document doesn't mention
4760 * this.
4761 */
4762
4763 /* Get the component index from src1.x for Gather4. */
4764 if (!tgsi_is_shadow_target(target)) {
4765 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4766 LLVMValueRef comp_imm;
4767 struct tgsi_src_register src1 = inst->Src[1].Register;
4768
4769 assert(src1.File == TGSI_FILE_IMMEDIATE);
4770
4771 comp_imm = imms[src1.Index][src1.SwizzleX];
4772 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4773 gather_comp = CLAMP(gather_comp, 0, 3);
4774 }
4775
4776 dmask = 1 << gather_comp;
4777 }
4778
4779 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4780 samp_ptr, address, count, dmask);
4781 }
4782
4783 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4784 * incorrectly forces nearest filtering if the texture format is integer.
4785 * The only effect it has on Gather4, which always returns 4 texels for
4786 * bilinear filtering, is that the final coordinates are off by 0.5 of
4787 * the texel size.
4788 *
4789 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4790 * or (0.5 / size) from the normalized coordinates.
4791 */
4792 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4793 struct lp_build_emit_data *emit_data,
4794 const char *intr_name,
4795 unsigned coord_vgpr_index)
4796 {
4797 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4798 LLVMValueRef coord = emit_data->args[0];
4799 LLVMValueRef half_texel[2];
4800 int c;
4801
4802 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4803 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4804 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4805 } else {
4806 struct tgsi_full_instruction txq_inst = {};
4807 struct lp_build_emit_data txq_emit_data = {};
4808
4809 /* Query the texture size. */
4810 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4811 txq_emit_data.inst = &txq_inst;
4812 txq_emit_data.dst_type = ctx->v4i32;
4813 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4814 txq_inst.Texture.Texture,
4815 emit_data->args[1], NULL,
4816 &ctx->radeon_bld.soa.bld_base.uint_bld.zero,
4817 1, 0xf);
4818 txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data);
4819
4820 /* Compute -0.5 / size. */
4821 for (c = 0; c < 2; c++) {
4822 half_texel[c] =
4823 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4824 LLVMConstInt(ctx->i32, c, 0), "");
4825 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4826 half_texel[c] =
4827 lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base,
4828 TGSI_OPCODE_RCP, half_texel[c]);
4829 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4830 LLVMConstReal(ctx->f32, -0.5), "");
4831 }
4832 }
4833
4834 for (c = 0; c < 2; c++) {
4835 LLVMValueRef tmp;
4836 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4837
4838 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4839 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4840 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4841 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4842 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4843 }
4844
4845 emit_data->args[0] = coord;
4846 emit_data->output[emit_data->chan] =
4847 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4848 emit_data->args, emit_data->arg_count,
4849 LLVMReadNoneAttribute);
4850 }
4851
4852 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4853 struct lp_build_tgsi_context *bld_base,
4854 struct lp_build_emit_data *emit_data)
4855 {
4856 struct si_shader_context *ctx = si_shader_context(bld_base);
4857 struct lp_build_context *base = &bld_base->base;
4858 const struct tgsi_full_instruction *inst = emit_data->inst;
4859 unsigned opcode = inst->Instruction.Opcode;
4860 unsigned target = inst->Texture.Texture;
4861 char intr_name[127];
4862 bool has_offset = inst->Texture.NumOffsets > 0;
4863 bool is_shadow = tgsi_is_shadow_target(target);
4864 char type[64];
4865 const char *name = "llvm.SI.image.sample";
4866 const char *infix = "";
4867
4868 if (target == TGSI_TEXTURE_BUFFER) {
4869 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4870 base->gallivm->builder,
4871 "llvm.SI.vs.load.input", emit_data->dst_type,
4872 emit_data->args, emit_data->arg_count,
4873 LLVMReadNoneAttribute);
4874 return;
4875 }
4876
4877 switch (opcode) {
4878 case TGSI_OPCODE_TXF:
4879 name = target == TGSI_TEXTURE_2D_MSAA ||
4880 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4881 "llvm.SI.image.load" :
4882 "llvm.SI.image.load.mip";
4883 is_shadow = false;
4884 has_offset = false;
4885 break;
4886 case TGSI_OPCODE_LODQ:
4887 name = "llvm.SI.getlod";
4888 is_shadow = false;
4889 has_offset = false;
4890 break;
4891 case TGSI_OPCODE_TEX:
4892 case TGSI_OPCODE_TEX2:
4893 case TGSI_OPCODE_TXP:
4894 if (ctx->type != PIPE_SHADER_FRAGMENT)
4895 infix = ".lz";
4896 break;
4897 case TGSI_OPCODE_TXB:
4898 case TGSI_OPCODE_TXB2:
4899 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4900 infix = ".b";
4901 break;
4902 case TGSI_OPCODE_TXL:
4903 case TGSI_OPCODE_TXL2:
4904 infix = ".l";
4905 break;
4906 case TGSI_OPCODE_TXD:
4907 infix = ".d";
4908 break;
4909 case TGSI_OPCODE_TG4:
4910 name = "llvm.SI.gather4";
4911 infix = ".lz";
4912 break;
4913 default:
4914 assert(0);
4915 return;
4916 }
4917
4918 /* Add the type and suffixes .c, .o if needed. */
4919 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4920 sprintf(intr_name, "%s%s%s%s.%s",
4921 name, is_shadow ? ".c" : "", infix,
4922 has_offset ? ".o" : "", type);
4923
4924 /* The hardware needs special lowering for Gather4 with integer formats. */
4925 if (opcode == TGSI_OPCODE_TG4) {
4926 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4927 /* This will also work with non-constant indexing because of how
4928 * glsl_to_tgsi works and we intent to preserve that behavior.
4929 */
4930 const unsigned src_idx = 2;
4931 unsigned sampler = inst->Src[src_idx].Register.Index;
4932
4933 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4934
4935 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4936 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4937 /* Texture coordinates start after:
4938 * {offset, bias, z-compare, derivatives}
4939 * Only the offset and z-compare can occur here.
4940 */
4941 si_lower_gather4_integer(ctx, emit_data, intr_name,
4942 (int)has_offset + (int)is_shadow);
4943 return;
4944 }
4945 }
4946
4947 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4948 base->gallivm->builder, intr_name, emit_data->dst_type,
4949 emit_data->args, emit_data->arg_count,
4950 LLVMReadNoneAttribute);
4951 }
4952
4953 static void si_llvm_emit_txqs(
4954 const struct lp_build_tgsi_action *action,
4955 struct lp_build_tgsi_context *bld_base,
4956 struct lp_build_emit_data *emit_data)
4957 {
4958 struct si_shader_context *ctx = si_shader_context(bld_base);
4959 struct gallivm_state *gallivm = bld_base->base.gallivm;
4960 LLVMBuilderRef builder = gallivm->builder;
4961 LLVMValueRef res, samples;
4962 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4963
4964 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4965
4966
4967 /* Read the samples from the descriptor directly. */
4968 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4969 samples = LLVMBuildExtractElement(
4970 builder, res,
4971 lp_build_const_int32(gallivm, 3), "");
4972 samples = LLVMBuildLShr(builder, samples,
4973 lp_build_const_int32(gallivm, 16), "");
4974 samples = LLVMBuildAnd(builder, samples,
4975 lp_build_const_int32(gallivm, 0xf), "");
4976 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4977 samples, "");
4978
4979 emit_data->output[emit_data->chan] = samples;
4980 }
4981
4982 /*
4983 * SI implements derivatives using the local data store (LDS)
4984 * All writes to the LDS happen in all executing threads at
4985 * the same time. TID is the Thread ID for the current
4986 * thread and is a value between 0 and 63, representing
4987 * the thread's position in the wavefront.
4988 *
4989 * For the pixel shader threads are grouped into quads of four pixels.
4990 * The TIDs of the pixels of a quad are:
4991 *
4992 * +------+------+
4993 * |4n + 0|4n + 1|
4994 * +------+------+
4995 * |4n + 2|4n + 3|
4996 * +------+------+
4997 *
4998 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4999 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5000 * the current pixel's column, and masking with 0xfffffffe yields the TID
5001 * of the left pixel of the current pixel's row.
5002 *
5003 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5004 * adding 2 yields the TID of the pixel below the top pixel.
5005 */
5006 /* masks for thread ID. */
5007 #define TID_MASK_TOP_LEFT 0xfffffffc
5008 #define TID_MASK_TOP 0xfffffffd
5009 #define TID_MASK_LEFT 0xfffffffe
5010
5011 static void si_llvm_emit_ddxy(
5012 const struct lp_build_tgsi_action *action,
5013 struct lp_build_tgsi_context *bld_base,
5014 struct lp_build_emit_data *emit_data)
5015 {
5016 struct si_shader_context *ctx = si_shader_context(bld_base);
5017 struct gallivm_state *gallivm = bld_base->base.gallivm;
5018 const struct tgsi_full_instruction *inst = emit_data->inst;
5019 unsigned opcode = inst->Instruction.Opcode;
5020 LLVMValueRef indices[2];
5021 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5022 LLVMValueRef tl, trbl, result[4];
5023 LLVMValueRef tl_tid, trbl_tid;
5024 unsigned swizzle[4];
5025 unsigned c;
5026 int idx;
5027 unsigned mask;
5028
5029 indices[0] = bld_base->uint_bld.zero;
5030 indices[1] = get_thread_id(ctx);
5031 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
5032 indices, 2, "");
5033
5034 if (opcode == TGSI_OPCODE_DDX_FINE)
5035 mask = TID_MASK_LEFT;
5036 else if (opcode == TGSI_OPCODE_DDY_FINE)
5037 mask = TID_MASK_TOP;
5038 else
5039 mask = TID_MASK_TOP_LEFT;
5040
5041 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
5042 lp_build_const_int32(gallivm, mask), "");
5043 indices[1] = tl_tid;
5044 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
5045 indices, 2, "");
5046
5047 /* for DDX we want to next X pixel, DDY next Y pixel. */
5048 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5049 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
5050 lp_build_const_int32(gallivm, idx), "");
5051 indices[1] = trbl_tid;
5052 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
5053 indices, 2, "");
5054
5055 for (c = 0; c < 4; ++c) {
5056 unsigned i;
5057 LLVMValueRef val;
5058 LLVMValueRef args[2];
5059
5060 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
5061 for (i = 0; i < c; ++i) {
5062 if (swizzle[i] == swizzle[c]) {
5063 result[c] = result[i];
5064 break;
5065 }
5066 }
5067 if (i != c)
5068 continue;
5069
5070 val = LLVMBuildBitCast(gallivm->builder,
5071 lp_build_emit_fetch(bld_base, inst, 0, c),
5072 ctx->i32, "");
5073
5074 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
5075
5076 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5077 lp_build_const_int32(gallivm, 4), "");
5078 args[1] = val;
5079 tl = lp_build_intrinsic(gallivm->builder,
5080 "llvm.amdgcn.ds.bpermute", ctx->i32,
5081 args, 2, LLVMReadNoneAttribute);
5082
5083 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5084 lp_build_const_int32(gallivm, 4), "");
5085 trbl = lp_build_intrinsic(gallivm->builder,
5086 "llvm.amdgcn.ds.bpermute", ctx->i32,
5087 args, 2, LLVMReadNoneAttribute);
5088 } else {
5089 LLVMBuildStore(gallivm->builder, val, store_ptr);
5090 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5091 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5092 }
5093 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5094 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5095 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5096 }
5097
5098 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
5099 }
5100
5101 /*
5102 * this takes an I,J coordinate pair,
5103 * and works out the X and Y derivatives.
5104 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5105 */
5106 static LLVMValueRef si_llvm_emit_ddxy_interp(
5107 struct lp_build_tgsi_context *bld_base,
5108 LLVMValueRef interp_ij)
5109 {
5110 struct si_shader_context *ctx = si_shader_context(bld_base);
5111 struct gallivm_state *gallivm = bld_base->base.gallivm;
5112 LLVMValueRef indices[2];
5113 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
5114 LLVMValueRef tl, tr, bl, result[4];
5115 unsigned c;
5116
5117 indices[0] = bld_base->uint_bld.zero;
5118 indices[1] = get_thread_id(ctx);
5119 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
5120 indices, 2, "");
5121
5122 temp = LLVMBuildAnd(gallivm->builder, indices[1],
5123 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
5124
5125 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
5126 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
5127
5128 indices[1] = temp;
5129 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
5130 indices, 2, "");
5131
5132 indices[1] = temp2;
5133 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
5134 indices, 2, "");
5135
5136 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
5137 lp_build_const_int32(gallivm, 1), "");
5138 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
5139 indices, 2, "");
5140
5141 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
5142 lp_build_const_int32(gallivm, 2), "");
5143 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
5144 indices, 2, "");
5145
5146 for (c = 0; c < 2; ++c) {
5147 LLVMValueRef store_val;
5148 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
5149
5150 store_val = LLVMBuildExtractElement(gallivm->builder,
5151 interp_ij, c_ll, "");
5152 LLVMBuildStore(gallivm->builder,
5153 store_val,
5154 store_ptr);
5155
5156 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
5157 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5158
5159 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
5160 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
5161
5162 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
5163
5164 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
5165 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5166
5167 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
5168 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
5169
5170 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
5171 }
5172
5173 return lp_build_gather_values(gallivm, result, 4);
5174 }
5175
5176 static void interp_fetch_args(
5177 struct lp_build_tgsi_context *bld_base,
5178 struct lp_build_emit_data *emit_data)
5179 {
5180 struct si_shader_context *ctx = si_shader_context(bld_base);
5181 struct gallivm_state *gallivm = bld_base->base.gallivm;
5182 const struct tgsi_full_instruction *inst = emit_data->inst;
5183
5184 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5185 /* offset is in second src, first two channels */
5186 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5187 emit_data->inst, 1,
5188 TGSI_CHAN_X);
5189 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5190 emit_data->inst, 1,
5191 TGSI_CHAN_Y);
5192 emit_data->arg_count = 2;
5193 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5194 LLVMValueRef sample_position;
5195 LLVMValueRef sample_id;
5196 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5197
5198 /* fetch sample ID, then fetch its sample position,
5199 * and place into first two channels.
5200 */
5201 sample_id = lp_build_emit_fetch(bld_base,
5202 emit_data->inst, 1, TGSI_CHAN_X);
5203 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5204 ctx->i32, "");
5205 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5206
5207 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5208 sample_position,
5209 lp_build_const_int32(gallivm, 0), "");
5210
5211 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5212 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5213 sample_position,
5214 lp_build_const_int32(gallivm, 1), "");
5215 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5216 emit_data->arg_count = 2;
5217 }
5218 }
5219
5220 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5221 struct lp_build_tgsi_context *bld_base,
5222 struct lp_build_emit_data *emit_data)
5223 {
5224 struct si_shader_context *ctx = si_shader_context(bld_base);
5225 struct si_shader *shader = ctx->shader;
5226 struct gallivm_state *gallivm = bld_base->base.gallivm;
5227 LLVMValueRef interp_param;
5228 const struct tgsi_full_instruction *inst = emit_data->inst;
5229 const char *intr_name;
5230 int input_index = inst->Src[0].Register.Index;
5231 int chan;
5232 int i;
5233 LLVMValueRef attr_number;
5234 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5235 int interp_param_idx;
5236 unsigned interp = shader->selector->info.input_interpolate[input_index];
5237 unsigned location;
5238
5239 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5240
5241 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5242 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5243 location = TGSI_INTERPOLATE_LOC_CENTER;
5244 else
5245 location = TGSI_INTERPOLATE_LOC_CENTROID;
5246
5247 interp_param_idx = lookup_interp_param_index(interp, location);
5248 if (interp_param_idx == -1)
5249 return;
5250 else if (interp_param_idx)
5251 interp_param = get_interp_param(ctx, interp_param_idx);
5252 else
5253 interp_param = NULL;
5254
5255 attr_number = lp_build_const_int32(gallivm, input_index);
5256
5257 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5258 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5259 LLVMValueRef ij_out[2];
5260 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5261
5262 /*
5263 * take the I then J parameters, and the DDX/Y for it, and
5264 * calculate the IJ inputs for the interpolator.
5265 * temp1 = ddx * offset/sample.x + I;
5266 * interp_param.I = ddy * offset/sample.y + temp1;
5267 * temp1 = ddx * offset/sample.x + J;
5268 * interp_param.J = ddy * offset/sample.y + temp1;
5269 */
5270 for (i = 0; i < 2; i++) {
5271 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5272 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5273 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5274 ddxy_out, ix_ll, "");
5275 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5276 ddxy_out, iy_ll, "");
5277 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5278 interp_param, ix_ll, "");
5279 LLVMValueRef temp1, temp2;
5280
5281 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5282 ctx->f32, "");
5283
5284 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5285
5286 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5287
5288 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5289
5290 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5291
5292 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5293 temp2, ctx->i32, "");
5294 }
5295 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5296 }
5297
5298 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5299 for (chan = 0; chan < 2; chan++) {
5300 LLVMValueRef args[4];
5301 LLVMValueRef llvm_chan;
5302 unsigned schan;
5303
5304 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5305 llvm_chan = lp_build_const_int32(gallivm, schan);
5306
5307 args[0] = llvm_chan;
5308 args[1] = attr_number;
5309 args[2] = params;
5310 args[3] = interp_param;
5311
5312 emit_data->output[chan] =
5313 lp_build_intrinsic(gallivm->builder, intr_name,
5314 ctx->f32, args, args[3] ? 4 : 3,
5315 LLVMReadNoneAttribute);
5316 }
5317 }
5318
5319 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5320 struct lp_build_emit_data *emit_data)
5321 {
5322 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5323 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5324 unsigned stream;
5325
5326 assert(src0.File == TGSI_FILE_IMMEDIATE);
5327
5328 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5329 return stream;
5330 }
5331
5332 /* Emit one vertex from the geometry shader */
5333 static void si_llvm_emit_vertex(
5334 const struct lp_build_tgsi_action *action,
5335 struct lp_build_tgsi_context *bld_base,
5336 struct lp_build_emit_data *emit_data)
5337 {
5338 struct si_shader_context *ctx = si_shader_context(bld_base);
5339 struct lp_build_context *uint = &bld_base->uint_bld;
5340 struct si_shader *shader = ctx->shader;
5341 struct tgsi_shader_info *info = &shader->selector->info;
5342 struct gallivm_state *gallivm = bld_base->base.gallivm;
5343 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5344 SI_PARAM_GS2VS_OFFSET);
5345 LLVMValueRef gs_next_vertex;
5346 LLVMValueRef can_emit, kill;
5347 LLVMValueRef args[2];
5348 unsigned chan;
5349 int i;
5350 unsigned stream;
5351
5352 stream = si_llvm_get_stream(bld_base, emit_data);
5353
5354 /* Write vertex attribute values to GSVS ring */
5355 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5356 ctx->gs_next_vertex[stream],
5357 "");
5358
5359 /* If this thread has already emitted the declared maximum number of
5360 * vertices, kill it: excessive vertex emissions are not supposed to
5361 * have any effect, and GS threads have no externally observable
5362 * effects other than emitting vertices.
5363 */
5364 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5365 lp_build_const_int32(gallivm,
5366 shader->selector->gs_max_out_vertices), "");
5367 kill = lp_build_select(&bld_base->base, can_emit,
5368 lp_build_const_float(gallivm, 1.0f),
5369 lp_build_const_float(gallivm, -1.0f));
5370
5371 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5372 ctx->voidt, &kill, 1, 0);
5373
5374 for (i = 0; i < info->num_outputs; i++) {
5375 LLVMValueRef *out_ptr =
5376 ctx->radeon_bld.soa.outputs[i];
5377
5378 for (chan = 0; chan < 4; chan++) {
5379 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5380 LLVMValueRef voffset =
5381 lp_build_const_int32(gallivm, (i * 4 + chan) *
5382 shader->selector->gs_max_out_vertices);
5383
5384 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5385 voffset = lp_build_mul_imm(uint, voffset, 4);
5386
5387 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5388
5389 build_tbuffer_store(ctx,
5390 ctx->gsvs_ring[stream],
5391 out_val, 1,
5392 voffset, soffset, 0,
5393 V_008F0C_BUF_DATA_FORMAT_32,
5394 V_008F0C_BUF_NUM_FORMAT_UINT,
5395 1, 0, 1, 1, 0);
5396 }
5397 }
5398 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5399 lp_build_const_int32(gallivm, 1));
5400
5401 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5402
5403 /* Signal vertex emission */
5404 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5405 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5406 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5407 ctx->voidt, args, 2, 0);
5408 }
5409
5410 /* Cut one primitive from the geometry shader */
5411 static void si_llvm_emit_primitive(
5412 const struct lp_build_tgsi_action *action,
5413 struct lp_build_tgsi_context *bld_base,
5414 struct lp_build_emit_data *emit_data)
5415 {
5416 struct si_shader_context *ctx = si_shader_context(bld_base);
5417 struct gallivm_state *gallivm = bld_base->base.gallivm;
5418 LLVMValueRef args[2];
5419 unsigned stream;
5420
5421 /* Signal primitive cut */
5422 stream = si_llvm_get_stream(bld_base, emit_data);
5423 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5424 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5425 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5426 ctx->voidt, args, 2, 0);
5427 }
5428
5429 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5430 struct lp_build_tgsi_context *bld_base,
5431 struct lp_build_emit_data *emit_data)
5432 {
5433 struct si_shader_context *ctx = si_shader_context(bld_base);
5434 struct gallivm_state *gallivm = bld_base->base.gallivm;
5435
5436 /* The real barrier instruction isn’t needed, because an entire patch
5437 * always fits into a single wave.
5438 */
5439 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5440 emit_optimization_barrier(ctx);
5441 return;
5442 }
5443
5444 lp_build_intrinsic(gallivm->builder,
5445 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5446 : "llvm.AMDGPU.barrier.local",
5447 ctx->voidt, NULL, 0, 0);
5448 }
5449
5450 static const struct lp_build_tgsi_action tex_action = {
5451 .fetch_args = tex_fetch_args,
5452 .emit = build_tex_intrinsic,
5453 };
5454
5455 static const struct lp_build_tgsi_action interp_action = {
5456 .fetch_args = interp_fetch_args,
5457 .emit = build_interp_intrinsic,
5458 };
5459
5460 static void si_create_function(struct si_shader_context *ctx,
5461 LLVMTypeRef *returns, unsigned num_returns,
5462 LLVMTypeRef *params, unsigned num_params,
5463 int last_sgpr)
5464 {
5465 int i;
5466
5467 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5468 params, num_params);
5469 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5470 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5471
5472 for (i = 0; i <= last_sgpr; ++i) {
5473 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5474
5475 /* The combination of:
5476 * - ByVal
5477 * - dereferenceable
5478 * - invariant.load
5479 * allows the optimization passes to move loads and reduces
5480 * SGPR spilling significantly.
5481 */
5482 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5483 LLVMAddAttribute(P, LLVMByValAttribute);
5484 lp_add_attr_dereferenceable(P, UINT64_MAX);
5485 } else
5486 LLVMAddAttribute(P, LLVMInRegAttribute);
5487 }
5488
5489 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5490 /* These were copied from some LLVM test. */
5491 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5492 "less-precise-fpmad",
5493 "true");
5494 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5495 "no-infs-fp-math",
5496 "true");
5497 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5498 "no-nans-fp-math",
5499 "true");
5500 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5501 "unsafe-fp-math",
5502 "true");
5503 }
5504 }
5505
5506 static void create_meta_data(struct si_shader_context *ctx)
5507 {
5508 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5509
5510 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5511 "invariant.load", 14);
5512 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5513 "range", 5);
5514 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5515 "amdgpu.uniform", 14);
5516
5517 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5518 }
5519
5520 static void declare_streamout_params(struct si_shader_context *ctx,
5521 struct pipe_stream_output_info *so,
5522 LLVMTypeRef *params, LLVMTypeRef i32,
5523 unsigned *num_params)
5524 {
5525 int i;
5526
5527 /* Streamout SGPRs. */
5528 if (so->num_outputs) {
5529 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5530 params[ctx->param_streamout_config = (*num_params)++] = i32;
5531 else
5532 ctx->param_streamout_config = ctx->param_tess_offchip;
5533
5534 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5535 }
5536 /* A streamout buffer offset is loaded if the stride is non-zero. */
5537 for (i = 0; i < 4; i++) {
5538 if (!so->stride[i])
5539 continue;
5540
5541 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5542 }
5543 }
5544
5545 static unsigned llvm_get_type_size(LLVMTypeRef type)
5546 {
5547 LLVMTypeKind kind = LLVMGetTypeKind(type);
5548
5549 switch (kind) {
5550 case LLVMIntegerTypeKind:
5551 return LLVMGetIntTypeWidth(type) / 8;
5552 case LLVMFloatTypeKind:
5553 return 4;
5554 case LLVMPointerTypeKind:
5555 return 8;
5556 case LLVMVectorTypeKind:
5557 return LLVMGetVectorSize(type) *
5558 llvm_get_type_size(LLVMGetElementType(type));
5559 default:
5560 assert(0);
5561 return 0;
5562 }
5563 }
5564
5565 static void declare_tess_lds(struct si_shader_context *ctx)
5566 {
5567 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5568 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5569 struct lp_build_context *uint = &bld_base->uint_bld;
5570
5571 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5572 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5573 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5574 "tess_lds");
5575 }
5576
5577 static void create_function(struct si_shader_context *ctx)
5578 {
5579 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5580 struct gallivm_state *gallivm = bld_base->base.gallivm;
5581 struct si_shader *shader = ctx->shader;
5582 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5583 LLVMTypeRef returns[16+32*4];
5584 unsigned i, last_sgpr, num_params, num_return_sgprs;
5585 unsigned num_returns = 0;
5586
5587 v3i32 = LLVMVectorType(ctx->i32, 3);
5588
5589 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5590 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5591 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5592 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5593 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5594
5595 switch (ctx->type) {
5596 case PIPE_SHADER_VERTEX:
5597 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5598 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5599 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5600 params[SI_PARAM_DRAWID] = ctx->i32;
5601 num_params = SI_PARAM_DRAWID+1;
5602
5603 if (shader->key.vs.as_es) {
5604 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5605 } else if (shader->key.vs.as_ls) {
5606 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5607 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5608 } else {
5609 if (ctx->is_gs_copy_shader) {
5610 num_params = SI_PARAM_RW_BUFFERS+1;
5611 } else {
5612 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5613 num_params = SI_PARAM_VS_STATE_BITS+1;
5614 }
5615
5616 /* The locations of the other parameters are assigned dynamically. */
5617 declare_streamout_params(ctx, &shader->selector->so,
5618 params, ctx->i32, &num_params);
5619 }
5620
5621 last_sgpr = num_params-1;
5622
5623 /* VGPRs */
5624 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5625 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5626 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5627 params[ctx->param_instance_id = num_params++] = ctx->i32;
5628
5629 if (!ctx->is_monolithic &&
5630 !ctx->is_gs_copy_shader) {
5631 /* Vertex load indices. */
5632 ctx->param_vertex_index0 = num_params;
5633
5634 for (i = 0; i < shader->selector->info.num_inputs; i++)
5635 params[num_params++] = ctx->i32;
5636
5637 /* PrimitiveID output. */
5638 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5639 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5640 returns[num_returns++] = ctx->f32;
5641 }
5642 break;
5643
5644 case PIPE_SHADER_TESS_CTRL:
5645 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5646 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5647 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5648 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5649 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5650 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5651 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5652
5653 /* VGPRs */
5654 params[SI_PARAM_PATCH_ID] = ctx->i32;
5655 params[SI_PARAM_REL_IDS] = ctx->i32;
5656 num_params = SI_PARAM_REL_IDS+1;
5657
5658 if (!ctx->is_monolithic) {
5659 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5660 * placed after the user SGPRs.
5661 */
5662 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5663 returns[num_returns++] = ctx->i32; /* SGPRs */
5664
5665 for (i = 0; i < 3; i++)
5666 returns[num_returns++] = ctx->f32; /* VGPRs */
5667 }
5668 break;
5669
5670 case PIPE_SHADER_TESS_EVAL:
5671 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5672 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5673
5674 if (shader->key.tes.as_es) {
5675 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5676 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5677 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5678 } else {
5679 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5680 declare_streamout_params(ctx, &shader->selector->so,
5681 params, ctx->i32, &num_params);
5682 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5683 }
5684 last_sgpr = num_params - 1;
5685
5686 /* VGPRs */
5687 params[ctx->param_tes_u = num_params++] = ctx->f32;
5688 params[ctx->param_tes_v = num_params++] = ctx->f32;
5689 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5690 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5691
5692 /* PrimitiveID output. */
5693 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5694 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5695 returns[num_returns++] = ctx->f32;
5696 break;
5697
5698 case PIPE_SHADER_GEOMETRY:
5699 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5700 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5701 last_sgpr = SI_PARAM_GS_WAVE_ID;
5702
5703 /* VGPRs */
5704 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5705 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5706 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5707 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5708 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5709 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5710 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5711 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5712 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5713 break;
5714
5715 case PIPE_SHADER_FRAGMENT:
5716 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5717 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5718 last_sgpr = SI_PARAM_PRIM_MASK;
5719 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5720 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5721 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5722 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5723 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5724 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5725 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5726 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5727 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5728 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5729 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5730 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5731 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5732 params[SI_PARAM_ANCILLARY] = ctx->i32;
5733 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5734 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5735 num_params = SI_PARAM_POS_FIXED_PT+1;
5736
5737 if (!ctx->is_monolithic) {
5738 /* Color inputs from the prolog. */
5739 if (shader->selector->info.colors_read) {
5740 unsigned num_color_elements =
5741 util_bitcount(shader->selector->info.colors_read);
5742
5743 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5744 for (i = 0; i < num_color_elements; i++)
5745 params[num_params++] = ctx->f32;
5746 }
5747
5748 /* Outputs for the epilog. */
5749 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5750 num_returns =
5751 num_return_sgprs +
5752 util_bitcount(shader->selector->info.colors_written) * 4 +
5753 shader->selector->info.writes_z +
5754 shader->selector->info.writes_stencil +
5755 shader->selector->info.writes_samplemask +
5756 1 /* SampleMaskIn */;
5757
5758 num_returns = MAX2(num_returns,
5759 num_return_sgprs +
5760 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5761
5762 for (i = 0; i < num_return_sgprs; i++)
5763 returns[i] = ctx->i32;
5764 for (; i < num_returns; i++)
5765 returns[i] = ctx->f32;
5766 }
5767 break;
5768
5769 case PIPE_SHADER_COMPUTE:
5770 params[SI_PARAM_GRID_SIZE] = v3i32;
5771 params[SI_PARAM_BLOCK_ID] = v3i32;
5772 last_sgpr = SI_PARAM_BLOCK_ID;
5773
5774 params[SI_PARAM_THREAD_ID] = v3i32;
5775 num_params = SI_PARAM_THREAD_ID + 1;
5776 break;
5777 default:
5778 assert(0 && "unimplemented shader");
5779 return;
5780 }
5781
5782 assert(num_params <= ARRAY_SIZE(params));
5783
5784 si_create_function(ctx, returns, num_returns, params,
5785 num_params, last_sgpr);
5786
5787 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5788 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5789 !ctx->is_monolithic) {
5790 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5791 "InitialPSInputAddr",
5792 S_0286D0_PERSP_SAMPLE_ENA(1) |
5793 S_0286D0_PERSP_CENTER_ENA(1) |
5794 S_0286D0_PERSP_CENTROID_ENA(1) |
5795 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5796 S_0286D0_LINEAR_CENTER_ENA(1) |
5797 S_0286D0_LINEAR_CENTROID_ENA(1) |
5798 S_0286D0_FRONT_FACE_ENA(1) |
5799 S_0286D0_POS_FIXED_PT_ENA(1));
5800 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5801 const unsigned *properties = shader->selector->info.properties;
5802 unsigned max_work_group_size =
5803 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5804 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5805 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5806
5807 assert(max_work_group_size);
5808
5809 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5810 "amdgpu-max-work-group-size",
5811 max_work_group_size);
5812 }
5813
5814 shader->info.num_input_sgprs = 0;
5815 shader->info.num_input_vgprs = 0;
5816
5817 for (i = 0; i <= last_sgpr; ++i)
5818 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5819
5820 /* Unused fragment shader inputs are eliminated by the compiler,
5821 * so we don't know yet how many there will be.
5822 */
5823 if (ctx->type != PIPE_SHADER_FRAGMENT)
5824 for (; i < num_params; ++i)
5825 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5826
5827 if (bld_base->info &&
5828 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5829 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5830 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5831 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5832 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5833 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5834 ctx->lds =
5835 LLVMAddGlobalInAddressSpace(gallivm->module,
5836 LLVMArrayType(ctx->i32, 64),
5837 "ddxy_lds",
5838 LOCAL_ADDR_SPACE);
5839
5840 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5841 ctx->type == PIPE_SHADER_TESS_CTRL ||
5842 ctx->type == PIPE_SHADER_TESS_EVAL)
5843 declare_tess_lds(ctx);
5844 }
5845
5846 static void preload_constants(struct si_shader_context *ctx)
5847 {
5848 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5849 struct gallivm_state *gallivm = bld_base->base.gallivm;
5850 const struct tgsi_shader_info *info = bld_base->info;
5851 unsigned buf;
5852 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5853
5854 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5855 if (info->const_file_max[buf] == -1)
5856 continue;
5857
5858 /* Load the resource descriptor */
5859 ctx->const_buffers[buf] =
5860 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5861 }
5862 }
5863
5864 static void preload_shader_buffers(struct si_shader_context *ctx)
5865 {
5866 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5867 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5868 int buf, maxbuf;
5869
5870 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5871 SI_NUM_SHADER_BUFFERS - 1);
5872 for (buf = 0; buf <= maxbuf; ++buf) {
5873 ctx->shader_buffers[buf] =
5874 build_indexed_load_const(
5875 ctx, ptr, lp_build_const_int32(gallivm, buf));
5876 }
5877 }
5878
5879 static void preload_samplers(struct si_shader_context *ctx)
5880 {
5881 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5882 struct gallivm_state *gallivm = bld_base->base.gallivm;
5883 const struct tgsi_shader_info *info = bld_base->info;
5884 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5885 LLVMValueRef offset;
5886
5887 if (num_samplers == 0)
5888 return;
5889
5890 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5891 for (i = 0; i < num_samplers; ++i) {
5892 /* Resource */
5893 offset = lp_build_const_int32(gallivm, i);
5894 ctx->sampler_views[i] =
5895 get_sampler_desc(ctx, offset, DESC_IMAGE);
5896
5897 /* FMASK resource */
5898 if (info->is_msaa_sampler[i])
5899 ctx->fmasks[i] =
5900 get_sampler_desc(ctx, offset, DESC_FMASK);
5901 else {
5902 ctx->sampler_states[i] =
5903 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5904 ctx->sampler_states[i] =
5905 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5906 ctx->sampler_states[i]);
5907 }
5908 }
5909 }
5910
5911 static void preload_images(struct si_shader_context *ctx)
5912 {
5913 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5914 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5915 struct gallivm_state *gallivm = bld_base->base.gallivm;
5916 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5917 LLVMValueRef res_ptr;
5918 unsigned i;
5919
5920 if (num_images == 0)
5921 return;
5922
5923 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5924
5925 for (i = 0; i < num_images; ++i) {
5926 /* Rely on LLVM to shrink the load for buffer resources. */
5927 LLVMValueRef rsrc =
5928 build_indexed_load_const(ctx, res_ptr,
5929 lp_build_const_int32(gallivm, i));
5930
5931 if (info->images_writemask & (1 << i) &&
5932 !(info->images_buffers & (1 << i)))
5933 rsrc = force_dcc_off(ctx, rsrc);
5934
5935 ctx->images[i] = rsrc;
5936 }
5937 }
5938
5939 /**
5940 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5941 * for later use.
5942 */
5943 static void preload_ring_buffers(struct si_shader_context *ctx)
5944 {
5945 struct gallivm_state *gallivm =
5946 ctx->radeon_bld.soa.bld_base.base.gallivm;
5947
5948 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5949 SI_PARAM_RW_BUFFERS);
5950
5951 if ((ctx->type == PIPE_SHADER_VERTEX &&
5952 ctx->shader->key.vs.as_es) ||
5953 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5954 ctx->shader->key.tes.as_es) ||
5955 ctx->type == PIPE_SHADER_GEOMETRY) {
5956 unsigned ring =
5957 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5958 : SI_ES_RING_ESGS;
5959 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5960
5961 ctx->esgs_ring =
5962 build_indexed_load_const(ctx, buf_ptr, offset);
5963 }
5964
5965 if (ctx->is_gs_copy_shader) {
5966 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5967
5968 ctx->gsvs_ring[0] =
5969 build_indexed_load_const(ctx, buf_ptr, offset);
5970 }
5971 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5972 int i;
5973 for (i = 0; i < 4; i++) {
5974 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5975
5976 ctx->gsvs_ring[i] =
5977 build_indexed_load_const(ctx, buf_ptr, offset);
5978 }
5979 }
5980 }
5981
5982 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5983 LLVMValueRef param_rw_buffers,
5984 unsigned param_pos_fixed_pt)
5985 {
5986 struct lp_build_tgsi_context *bld_base =
5987 &ctx->radeon_bld.soa.bld_base;
5988 struct gallivm_state *gallivm = bld_base->base.gallivm;
5989 LLVMBuilderRef builder = gallivm->builder;
5990 LLVMValueRef slot, desc, offset, row, bit, address[2];
5991
5992 /* Use the fixed-point gl_FragCoord input.
5993 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5994 * per coordinate to get the repeating effect.
5995 */
5996 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5997 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5998
5999 /* Load the buffer descriptor. */
6000 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
6001 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
6002
6003 /* The stipple pattern is 32x32, each row has 32 bits. */
6004 offset = LLVMBuildMul(builder, address[1],
6005 LLVMConstInt(ctx->i32, 4, 0), "");
6006 row = buffer_load_const(ctx, desc, offset);
6007 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
6008 bit = LLVMBuildLShr(builder, row, address[0], "");
6009 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
6010
6011 /* The intrinsic kills the thread if arg < 0. */
6012 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
6013 LLVMConstReal(ctx->f32, -1), "");
6014 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
6015 }
6016
6017 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
6018 struct si_shader_config *conf,
6019 unsigned symbol_offset)
6020 {
6021 unsigned i;
6022 const unsigned char *config =
6023 radeon_shader_binary_config_start(binary, symbol_offset);
6024 bool really_needs_scratch = false;
6025
6026 /* LLVM adds SGPR spills to the scratch size.
6027 * Find out if we really need the scratch buffer.
6028 */
6029 for (i = 0; i < binary->reloc_count; i++) {
6030 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
6031
6032 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6033 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6034 really_needs_scratch = true;
6035 break;
6036 }
6037 }
6038
6039 /* XXX: We may be able to emit some of these values directly rather than
6040 * extracting fields to be emitted later.
6041 */
6042
6043 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6044 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6045 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6046 switch (reg) {
6047 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6048 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6049 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6050 case R_00B848_COMPUTE_PGM_RSRC1:
6051 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6052 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6053 conf->float_mode = G_00B028_FLOAT_MODE(value);
6054 conf->rsrc1 = value;
6055 break;
6056 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6057 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6058 break;
6059 case R_00B84C_COMPUTE_PGM_RSRC2:
6060 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6061 conf->rsrc2 = value;
6062 break;
6063 case R_0286CC_SPI_PS_INPUT_ENA:
6064 conf->spi_ps_input_ena = value;
6065 break;
6066 case R_0286D0_SPI_PS_INPUT_ADDR:
6067 conf->spi_ps_input_addr = value;
6068 break;
6069 case R_0286E8_SPI_TMPRING_SIZE:
6070 case R_00B860_COMPUTE_TMPRING_SIZE:
6071 /* WAVESIZE is in units of 256 dwords. */
6072 if (really_needs_scratch)
6073 conf->scratch_bytes_per_wave =
6074 G_00B860_WAVESIZE(value) * 256 * 4;
6075 break;
6076 case 0x4: /* SPILLED_SGPRS */
6077 conf->spilled_sgprs = value;
6078 break;
6079 case 0x8: /* SPILLED_VGPRS */
6080 conf->spilled_vgprs = value;
6081 break;
6082 default:
6083 {
6084 static bool printed;
6085
6086 if (!printed) {
6087 fprintf(stderr, "Warning: LLVM emitted unknown "
6088 "config register: 0x%x\n", reg);
6089 printed = true;
6090 }
6091 }
6092 break;
6093 }
6094 }
6095
6096 if (!conf->spi_ps_input_addr)
6097 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6098 }
6099
6100 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6101 struct si_shader *shader,
6102 struct si_shader_config *config,
6103 uint64_t scratch_va)
6104 {
6105 unsigned i;
6106 uint32_t scratch_rsrc_dword0 = scratch_va;
6107 uint32_t scratch_rsrc_dword1 =
6108 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6109
6110 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6111 * correctly.
6112 */
6113 if (HAVE_LLVM >= 0x0309)
6114 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6115 else
6116 scratch_rsrc_dword1 |=
6117 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6118
6119 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6120 const struct radeon_shader_reloc *reloc =
6121 &shader->binary.relocs[i];
6122 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6123 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6124 &scratch_rsrc_dword0, 4);
6125 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6126 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6127 &scratch_rsrc_dword1, 4);
6128 }
6129 }
6130 }
6131
6132 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6133 {
6134 unsigned size = shader->binary.code_size;
6135
6136 if (shader->prolog)
6137 size += shader->prolog->binary.code_size;
6138 if (shader->epilog)
6139 size += shader->epilog->binary.code_size;
6140 return size;
6141 }
6142
6143 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6144 {
6145 const struct radeon_shader_binary *prolog =
6146 shader->prolog ? &shader->prolog->binary : NULL;
6147 const struct radeon_shader_binary *epilog =
6148 shader->epilog ? &shader->epilog->binary : NULL;
6149 const struct radeon_shader_binary *mainb = &shader->binary;
6150 unsigned bo_size = si_get_shader_binary_size(shader) +
6151 (!epilog ? mainb->rodata_size : 0);
6152 unsigned char *ptr;
6153
6154 assert(!prolog || !prolog->rodata_size);
6155 assert((!prolog && !epilog) || !mainb->rodata_size);
6156 assert(!epilog || !epilog->rodata_size);
6157
6158 r600_resource_reference(&shader->bo, NULL);
6159 shader->bo = si_resource_create_custom(&sscreen->b.b,
6160 PIPE_USAGE_IMMUTABLE,
6161 bo_size);
6162 if (!shader->bo)
6163 return -ENOMEM;
6164
6165 /* Upload. */
6166 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6167 PIPE_TRANSFER_READ_WRITE);
6168
6169 if (prolog) {
6170 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6171 ptr += prolog->code_size;
6172 }
6173
6174 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6175 ptr += mainb->code_size;
6176
6177 if (epilog)
6178 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6179 else if (mainb->rodata_size > 0)
6180 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6181
6182 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6183 return 0;
6184 }
6185
6186 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6187 struct pipe_debug_callback *debug,
6188 const char *name, FILE *file)
6189 {
6190 char *line, *p;
6191 unsigned i, count;
6192
6193 if (binary->disasm_string) {
6194 fprintf(file, "Shader %s disassembly:\n", name);
6195 fprintf(file, "%s", binary->disasm_string);
6196
6197 if (debug && debug->debug_message) {
6198 /* Very long debug messages are cut off, so send the
6199 * disassembly one line at a time. This causes more
6200 * overhead, but on the plus side it simplifies
6201 * parsing of resulting logs.
6202 */
6203 pipe_debug_message(debug, SHADER_INFO,
6204 "Shader Disassembly Begin");
6205
6206 line = binary->disasm_string;
6207 while (*line) {
6208 p = util_strchrnul(line, '\n');
6209 count = p - line;
6210
6211 if (count) {
6212 pipe_debug_message(debug, SHADER_INFO,
6213 "%.*s", count, line);
6214 }
6215
6216 if (!*p)
6217 break;
6218 line = p + 1;
6219 }
6220
6221 pipe_debug_message(debug, SHADER_INFO,
6222 "Shader Disassembly End");
6223 }
6224 } else {
6225 fprintf(file, "Shader %s binary:\n", name);
6226 for (i = 0; i < binary->code_size; i += 4) {
6227 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6228 binary->code[i + 3], binary->code[i + 2],
6229 binary->code[i + 1], binary->code[i]);
6230 }
6231 }
6232 }
6233
6234 static void si_shader_dump_stats(struct si_screen *sscreen,
6235 struct si_shader_config *conf,
6236 unsigned num_inputs,
6237 unsigned code_size,
6238 struct pipe_debug_callback *debug,
6239 unsigned processor,
6240 FILE *file)
6241 {
6242 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6243 unsigned lds_per_wave = 0;
6244 unsigned max_simd_waves = 10;
6245
6246 /* Compute LDS usage for PS. */
6247 if (processor == PIPE_SHADER_FRAGMENT) {
6248 /* The minimum usage per wave is (num_inputs * 48). The maximum
6249 * usage is (num_inputs * 48 * 16).
6250 * We can get anything in between and it varies between waves.
6251 *
6252 * The 48 bytes per input for a single primitive is equal to
6253 * 4 bytes/component * 4 components/input * 3 points.
6254 *
6255 * Other stages don't know the size at compile time or don't
6256 * allocate LDS per wave, but instead they do it per thread group.
6257 */
6258 lds_per_wave = conf->lds_size * lds_increment +
6259 align(num_inputs * 48, lds_increment);
6260 }
6261
6262 /* Compute the per-SIMD wave counts. */
6263 if (conf->num_sgprs) {
6264 if (sscreen->b.chip_class >= VI)
6265 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6266 else
6267 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6268 }
6269
6270 if (conf->num_vgprs)
6271 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6272
6273 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6274 * that PS can use.
6275 */
6276 if (lds_per_wave)
6277 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6278
6279 if (file != stderr ||
6280 r600_can_dump_shader(&sscreen->b, processor)) {
6281 if (processor == PIPE_SHADER_FRAGMENT) {
6282 fprintf(file, "*** SHADER CONFIG ***\n"
6283 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6284 "SPI_PS_INPUT_ENA = 0x%04x\n",
6285 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6286 }
6287
6288 fprintf(file, "*** SHADER STATS ***\n"
6289 "SGPRS: %d\n"
6290 "VGPRS: %d\n"
6291 "Spilled SGPRs: %d\n"
6292 "Spilled VGPRs: %d\n"
6293 "Code Size: %d bytes\n"
6294 "LDS: %d blocks\n"
6295 "Scratch: %d bytes per wave\n"
6296 "Max Waves: %d\n"
6297 "********************\n\n\n",
6298 conf->num_sgprs, conf->num_vgprs,
6299 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
6300 conf->lds_size, conf->scratch_bytes_per_wave,
6301 max_simd_waves);
6302 }
6303
6304 pipe_debug_message(debug, SHADER_INFO,
6305 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6306 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6307 "Spilled VGPRs: %d",
6308 conf->num_sgprs, conf->num_vgprs, code_size,
6309 conf->lds_size, conf->scratch_bytes_per_wave,
6310 max_simd_waves, conf->spilled_sgprs,
6311 conf->spilled_vgprs);
6312 }
6313
6314 static const char *si_get_shader_name(struct si_shader *shader,
6315 unsigned processor)
6316 {
6317 switch (processor) {
6318 case PIPE_SHADER_VERTEX:
6319 if (shader->key.vs.as_es)
6320 return "Vertex Shader as ES";
6321 else if (shader->key.vs.as_ls)
6322 return "Vertex Shader as LS";
6323 else
6324 return "Vertex Shader as VS";
6325 case PIPE_SHADER_TESS_CTRL:
6326 return "Tessellation Control Shader";
6327 case PIPE_SHADER_TESS_EVAL:
6328 if (shader->key.tes.as_es)
6329 return "Tessellation Evaluation Shader as ES";
6330 else
6331 return "Tessellation Evaluation Shader as VS";
6332 case PIPE_SHADER_GEOMETRY:
6333 if (shader->gs_copy_shader == NULL)
6334 return "GS Copy Shader as VS";
6335 else
6336 return "Geometry Shader";
6337 case PIPE_SHADER_FRAGMENT:
6338 return "Pixel Shader";
6339 case PIPE_SHADER_COMPUTE:
6340 return "Compute Shader";
6341 default:
6342 return "Unknown Shader";
6343 }
6344 }
6345
6346 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6347 struct pipe_debug_callback *debug, unsigned processor,
6348 FILE *file)
6349 {
6350 if (file != stderr ||
6351 r600_can_dump_shader(&sscreen->b, processor))
6352 si_dump_shader_key(processor, &shader->key, file);
6353
6354 if (file != stderr && shader->binary.llvm_ir_string) {
6355 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6356 si_get_shader_name(shader, processor));
6357 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6358 }
6359
6360 if (file != stderr ||
6361 (r600_can_dump_shader(&sscreen->b, processor) &&
6362 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6363 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6364
6365 if (shader->prolog)
6366 si_shader_dump_disassembly(&shader->prolog->binary,
6367 debug, "prolog", file);
6368
6369 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6370
6371 if (shader->epilog)
6372 si_shader_dump_disassembly(&shader->epilog->binary,
6373 debug, "epilog", file);
6374 fprintf(file, "\n");
6375 }
6376
6377 si_shader_dump_stats(sscreen, &shader->config,
6378 shader->selector ? shader->selector->info.num_inputs : 0,
6379 si_get_shader_binary_size(shader), debug, processor,
6380 file);
6381 }
6382
6383 int si_compile_llvm(struct si_screen *sscreen,
6384 struct radeon_shader_binary *binary,
6385 struct si_shader_config *conf,
6386 LLVMTargetMachineRef tm,
6387 LLVMModuleRef mod,
6388 struct pipe_debug_callback *debug,
6389 unsigned processor,
6390 const char *name)
6391 {
6392 int r = 0;
6393 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6394
6395 if (r600_can_dump_shader(&sscreen->b, processor)) {
6396 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6397
6398 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6399 fprintf(stderr, "%s LLVM IR:\n\n", name);
6400 LLVMDumpModule(mod);
6401 fprintf(stderr, "\n");
6402 }
6403 }
6404
6405 if (sscreen->record_llvm_ir) {
6406 char *ir = LLVMPrintModuleToString(mod);
6407 binary->llvm_ir_string = strdup(ir);
6408 LLVMDisposeMessage(ir);
6409 }
6410
6411 if (!si_replace_shader(count, binary)) {
6412 r = radeon_llvm_compile(mod, binary, tm, debug);
6413 if (r)
6414 return r;
6415 }
6416
6417 si_shader_binary_read_config(binary, conf, 0);
6418
6419 /* Enable 64-bit and 16-bit denormals, because there is no performance
6420 * cost.
6421 *
6422 * If denormals are enabled, all floating-point output modifiers are
6423 * ignored.
6424 *
6425 * Don't enable denormals for 32-bit floats, because:
6426 * - Floating-point output modifiers would be ignored by the hw.
6427 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6428 * have to stop using those.
6429 * - SI & CI would be very slow.
6430 */
6431 conf->float_mode |= V_00B028_FP_64_DENORMS;
6432
6433 FREE(binary->config);
6434 FREE(binary->global_symbol_offsets);
6435 binary->config = NULL;
6436 binary->global_symbol_offsets = NULL;
6437
6438 /* Some shaders can't have rodata because their binaries can be
6439 * concatenated.
6440 */
6441 if (binary->rodata_size &&
6442 (processor == PIPE_SHADER_VERTEX ||
6443 processor == PIPE_SHADER_TESS_CTRL ||
6444 processor == PIPE_SHADER_TESS_EVAL ||
6445 processor == PIPE_SHADER_FRAGMENT)) {
6446 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6447 return -EINVAL;
6448 }
6449
6450 return r;
6451 }
6452
6453 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6454 {
6455 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6456 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6457 else
6458 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6459 }
6460
6461 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6462 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6463 struct si_shader_context *ctx,
6464 struct si_shader *gs,
6465 struct pipe_debug_callback *debug)
6466 {
6467 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6468 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6469 struct lp_build_context *uint = &bld_base->uint_bld;
6470 struct si_shader_output_values *outputs;
6471 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6472 LLVMValueRef args[9];
6473 int i, r;
6474
6475 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6476
6477 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6478 ctx->type = PIPE_SHADER_VERTEX;
6479 ctx->is_gs_copy_shader = true;
6480
6481 create_meta_data(ctx);
6482 create_function(ctx);
6483 preload_ring_buffers(ctx);
6484
6485 args[0] = ctx->gsvs_ring[0];
6486 args[1] = lp_build_mul_imm(uint,
6487 LLVMGetParam(ctx->radeon_bld.main_fn,
6488 ctx->param_vertex_id),
6489 4);
6490 args[3] = uint->zero;
6491 args[4] = uint->one; /* OFFEN */
6492 args[5] = uint->zero; /* IDXEN */
6493 args[6] = uint->one; /* GLC */
6494 args[7] = uint->one; /* SLC */
6495 args[8] = uint->zero; /* TFE */
6496
6497 /* Fetch vertex data from GSVS ring */
6498 for (i = 0; i < gsinfo->num_outputs; ++i) {
6499 unsigned chan;
6500
6501 outputs[i].name = gsinfo->output_semantic_name[i];
6502 outputs[i].sid = gsinfo->output_semantic_index[i];
6503
6504 for (chan = 0; chan < 4; chan++) {
6505 args[2] = lp_build_const_int32(gallivm,
6506 (i * 4 + chan) *
6507 gs->selector->gs_max_out_vertices * 16 * 4);
6508
6509 outputs[i].values[chan] =
6510 LLVMBuildBitCast(gallivm->builder,
6511 lp_build_intrinsic(gallivm->builder,
6512 "llvm.SI.buffer.load.dword.i32.i32",
6513 ctx->i32, args, 9,
6514 LLVMReadOnlyAttribute),
6515 ctx->f32, "");
6516 }
6517 }
6518
6519 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6520
6521 LLVMBuildRetVoid(gallivm->builder);
6522
6523 /* Dump LLVM IR before any optimization passes */
6524 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6525 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6526 LLVMDumpModule(bld_base->base.gallivm->module);
6527
6528 radeon_llvm_finalize_module(&ctx->radeon_bld);
6529
6530 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6531 &ctx->shader->config, ctx->tm,
6532 bld_base->base.gallivm->module,
6533 debug, PIPE_SHADER_GEOMETRY,
6534 "GS Copy Shader");
6535 if (!r) {
6536 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6537 fprintf(stderr, "GS Copy Shader:\n");
6538 si_shader_dump(sscreen, ctx->shader, debug,
6539 PIPE_SHADER_GEOMETRY, stderr);
6540 r = si_shader_binary_upload(sscreen, ctx->shader);
6541 }
6542
6543 radeon_llvm_dispose(&ctx->radeon_bld);
6544
6545 FREE(outputs);
6546 return r;
6547 }
6548
6549 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
6550 FILE *f)
6551 {
6552 int i;
6553
6554 fprintf(f, "SHADER KEY\n");
6555
6556 switch (shader) {
6557 case PIPE_SHADER_VERTEX:
6558 fprintf(f, " instance_divisors = {");
6559 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6560 fprintf(f, !i ? "%u" : ", %u",
6561 key->vs.prolog.instance_divisors[i]);
6562 fprintf(f, "}\n");
6563 fprintf(f, " as_es = %u\n", key->vs.as_es);
6564 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6565 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6566 break;
6567
6568 case PIPE_SHADER_TESS_CTRL:
6569 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6570 break;
6571
6572 case PIPE_SHADER_TESS_EVAL:
6573 fprintf(f, " as_es = %u\n", key->tes.as_es);
6574 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6575 break;
6576
6577 case PIPE_SHADER_GEOMETRY:
6578 case PIPE_SHADER_COMPUTE:
6579 break;
6580
6581 case PIPE_SHADER_FRAGMENT:
6582 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6583 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6584 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6585 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6586 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6587 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6588 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6589 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6590 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6591 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6592 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6593 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6594 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6595 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6596 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6597 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6598 break;
6599
6600 default:
6601 assert(0);
6602 }
6603 }
6604
6605 static void si_init_shader_ctx(struct si_shader_context *ctx,
6606 struct si_screen *sscreen,
6607 struct si_shader *shader,
6608 LLVMTargetMachineRef tm)
6609 {
6610 struct lp_build_tgsi_context *bld_base;
6611 struct lp_build_tgsi_action tmpl = {};
6612
6613 memset(ctx, 0, sizeof(*ctx));
6614 radeon_llvm_context_init(
6615 &ctx->radeon_bld, "amdgcn--",
6616 (shader && shader->selector) ? &shader->selector->info : NULL,
6617 (shader && shader->selector) ? shader->selector->tokens : NULL);
6618 ctx->tm = tm;
6619 ctx->screen = sscreen;
6620 if (shader && shader->selector)
6621 ctx->type = shader->selector->info.processor;
6622 else
6623 ctx->type = -1;
6624 ctx->shader = shader;
6625
6626 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6627 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6628 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6629 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6630 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6631 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6632 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6633 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6634 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6635 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6636 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6637 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6638
6639 bld_base = &ctx->radeon_bld.soa.bld_base;
6640 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6641
6642 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6643 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6644 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6645
6646 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6647 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6648 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6649 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6650 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6651 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6652 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6653 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6654 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6655 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6656 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6657 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6658 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6659 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6660
6661 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6662 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6663 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6664 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6665 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6666 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6667
6668 tmpl.fetch_args = atomic_fetch_args;
6669 tmpl.emit = atomic_emit;
6670 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6671 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6672 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6673 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6674 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6675 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6676 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6677 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6678 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6679 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6680 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6681 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6682 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6683 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6684 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6685 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6686 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6687 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6688 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6689 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6690
6691 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6692
6693 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6694 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6695 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6696 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6697
6698 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6699 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6700 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6701
6702 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6703 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6704 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6705 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6706 }
6707
6708 int si_compile_tgsi_shader(struct si_screen *sscreen,
6709 LLVMTargetMachineRef tm,
6710 struct si_shader *shader,
6711 bool is_monolithic,
6712 struct pipe_debug_callback *debug)
6713 {
6714 struct si_shader_selector *sel = shader->selector;
6715 struct si_shader_context ctx;
6716 struct lp_build_tgsi_context *bld_base;
6717 LLVMModuleRef mod;
6718 int r = 0;
6719
6720 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6721 * conversion fails. */
6722 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6723 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6724 tgsi_dump(sel->tokens, 0);
6725 si_dump_streamout(&sel->so);
6726 }
6727
6728 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6729 ctx.is_monolithic = is_monolithic;
6730
6731 shader->info.uses_instanceid = sel->info.uses_instanceid;
6732
6733 bld_base = &ctx.radeon_bld.soa.bld_base;
6734 ctx.radeon_bld.load_system_value = declare_system_value;
6735
6736 switch (ctx.type) {
6737 case PIPE_SHADER_VERTEX:
6738 ctx.radeon_bld.load_input = declare_input_vs;
6739 if (shader->key.vs.as_ls)
6740 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6741 else if (shader->key.vs.as_es)
6742 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6743 else
6744 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6745 break;
6746 case PIPE_SHADER_TESS_CTRL:
6747 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6748 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6749 bld_base->emit_store = store_output_tcs;
6750 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6751 break;
6752 case PIPE_SHADER_TESS_EVAL:
6753 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6754 if (shader->key.tes.as_es)
6755 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6756 else
6757 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6758 break;
6759 case PIPE_SHADER_GEOMETRY:
6760 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6761 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6762 break;
6763 case PIPE_SHADER_FRAGMENT:
6764 ctx.radeon_bld.load_input = declare_input_fs;
6765 if (is_monolithic)
6766 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6767 else
6768 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6769 break;
6770 case PIPE_SHADER_COMPUTE:
6771 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6772 break;
6773 default:
6774 assert(!"Unsupported shader type");
6775 return -1;
6776 }
6777
6778 create_meta_data(&ctx);
6779 create_function(&ctx);
6780 preload_constants(&ctx);
6781 preload_shader_buffers(&ctx);
6782 preload_samplers(&ctx);
6783 preload_images(&ctx);
6784 preload_ring_buffers(&ctx);
6785
6786 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6787 shader->key.ps.prolog.poly_stipple) {
6788 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6789 SI_PARAM_RW_BUFFERS);
6790 si_llvm_emit_polygon_stipple(&ctx, list,
6791 SI_PARAM_POS_FIXED_PT);
6792 }
6793
6794 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6795 int i;
6796 for (i = 0; i < 4; i++) {
6797 ctx.gs_next_vertex[i] =
6798 lp_build_alloca(bld_base->base.gallivm,
6799 ctx.i32, "");
6800 }
6801 }
6802
6803 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6804 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6805 goto out;
6806 }
6807
6808 si_llvm_build_ret(&ctx, ctx.return_value);
6809 mod = bld_base->base.gallivm->module;
6810
6811 /* Dump LLVM IR before any optimization passes */
6812 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6813 r600_can_dump_shader(&sscreen->b, ctx.type))
6814 LLVMDumpModule(mod);
6815
6816 radeon_llvm_finalize_module(&ctx.radeon_bld);
6817
6818 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6819 mod, debug, ctx.type, "TGSI shader");
6820 if (r) {
6821 fprintf(stderr, "LLVM failed to compile shader\n");
6822 goto out;
6823 }
6824
6825 radeon_llvm_dispose(&ctx.radeon_bld);
6826
6827 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6828 * LLVM 3.9svn has this bug.
6829 */
6830 if (sel->type == PIPE_SHADER_COMPUTE) {
6831 unsigned *props = sel->info.properties;
6832 unsigned wave_size = 64;
6833 unsigned max_vgprs = 256;
6834 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6835 unsigned max_sgprs_per_wave = 128;
6836 unsigned min_waves_per_cu =
6837 DIV_ROUND_UP(props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
6838 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
6839 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH],
6840 wave_size);
6841 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6842
6843 max_vgprs = max_vgprs / min_waves_per_simd;
6844 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6845
6846 if (shader->config.num_sgprs > max_sgprs ||
6847 shader->config.num_vgprs > max_vgprs) {
6848 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6849 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6850 shader->config.num_sgprs, shader->config.num_vgprs,
6851 max_sgprs, max_vgprs);
6852
6853 /* Just terminate the process, because dependent
6854 * shaders can hang due to bad input data, but use
6855 * the env var to allow shader-db to work.
6856 */
6857 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6858 abort();
6859 }
6860 }
6861
6862 /* Add the scratch offset to input SGPRs. */
6863 if (shader->config.scratch_bytes_per_wave)
6864 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6865
6866 /* Calculate the number of fragment input VGPRs. */
6867 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6868 shader->info.num_input_vgprs = 0;
6869 shader->info.face_vgpr_index = -1;
6870
6871 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6872 shader->info.num_input_vgprs += 2;
6873 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6874 shader->info.num_input_vgprs += 2;
6875 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6876 shader->info.num_input_vgprs += 2;
6877 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6878 shader->info.num_input_vgprs += 3;
6879 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6880 shader->info.num_input_vgprs += 2;
6881 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6882 shader->info.num_input_vgprs += 2;
6883 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6884 shader->info.num_input_vgprs += 2;
6885 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6886 shader->info.num_input_vgprs += 1;
6887 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6888 shader->info.num_input_vgprs += 1;
6889 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6890 shader->info.num_input_vgprs += 1;
6891 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6892 shader->info.num_input_vgprs += 1;
6893 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6894 shader->info.num_input_vgprs += 1;
6895 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6896 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6897 shader->info.num_input_vgprs += 1;
6898 }
6899 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6900 shader->info.num_input_vgprs += 1;
6901 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6902 shader->info.num_input_vgprs += 1;
6903 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6904 shader->info.num_input_vgprs += 1;
6905 }
6906
6907 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6908 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6909 shader->gs_copy_shader->selector = shader->selector;
6910 ctx.shader = shader->gs_copy_shader;
6911 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6912 shader, debug))) {
6913 free(shader->gs_copy_shader);
6914 shader->gs_copy_shader = NULL;
6915 goto out;
6916 }
6917 }
6918
6919 out:
6920 return r;
6921 }
6922
6923 /**
6924 * Create, compile and return a shader part (prolog or epilog).
6925 *
6926 * \param sscreen screen
6927 * \param list list of shader parts of the same category
6928 * \param key shader part key
6929 * \param tm LLVM target machine
6930 * \param debug debug callback
6931 * \param compile the callback responsible for compilation
6932 * \return non-NULL on success
6933 */
6934 static struct si_shader_part *
6935 si_get_shader_part(struct si_screen *sscreen,
6936 struct si_shader_part **list,
6937 union si_shader_part_key *key,
6938 LLVMTargetMachineRef tm,
6939 struct pipe_debug_callback *debug,
6940 bool (*compile)(struct si_screen *,
6941 LLVMTargetMachineRef,
6942 struct pipe_debug_callback *,
6943 struct si_shader_part *))
6944 {
6945 struct si_shader_part *result;
6946
6947 pipe_mutex_lock(sscreen->shader_parts_mutex);
6948
6949 /* Find existing. */
6950 for (result = *list; result; result = result->next) {
6951 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6952 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6953 return result;
6954 }
6955 }
6956
6957 /* Compile a new one. */
6958 result = CALLOC_STRUCT(si_shader_part);
6959 result->key = *key;
6960 if (!compile(sscreen, tm, debug, result)) {
6961 FREE(result);
6962 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6963 return NULL;
6964 }
6965
6966 result->next = *list;
6967 *list = result;
6968 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6969 return result;
6970 }
6971
6972 /**
6973 * Create a vertex shader prolog.
6974 *
6975 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6976 * All inputs are returned unmodified. The vertex load indices are
6977 * stored after them, which will used by the API VS for fetching inputs.
6978 *
6979 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6980 * input_v0,
6981 * input_v1,
6982 * input_v2,
6983 * input_v3,
6984 * (VertexID + BaseVertex),
6985 * (InstanceID + StartInstance),
6986 * (InstanceID / 2 + StartInstance)
6987 */
6988 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6989 LLVMTargetMachineRef tm,
6990 struct pipe_debug_callback *debug,
6991 struct si_shader_part *out)
6992 {
6993 union si_shader_part_key *key = &out->key;
6994 struct si_shader shader = {};
6995 struct si_shader_context ctx;
6996 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6997 LLVMTypeRef *params, *returns;
6998 LLVMValueRef ret, func;
6999 int last_sgpr, num_params, num_returns, i;
7000 bool status = true;
7001
7002 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7003 ctx.type = PIPE_SHADER_VERTEX;
7004 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
7005 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7006
7007 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7008 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7009 sizeof(LLVMTypeRef));
7010 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7011 key->vs_prolog.last_input + 1) *
7012 sizeof(LLVMTypeRef));
7013 num_params = 0;
7014 num_returns = 0;
7015
7016 /* Declare input and output SGPRs. */
7017 num_params = 0;
7018 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7019 params[num_params++] = ctx.i32;
7020 returns[num_returns++] = ctx.i32;
7021 }
7022 last_sgpr = num_params - 1;
7023
7024 /* 4 preloaded VGPRs (outputs must be floats) */
7025 for (i = 0; i < 4; i++) {
7026 params[num_params++] = ctx.i32;
7027 returns[num_returns++] = ctx.f32;
7028 }
7029
7030 /* Vertex load indices. */
7031 for (i = 0; i <= key->vs_prolog.last_input; i++)
7032 returns[num_returns++] = ctx.f32;
7033
7034 /* Create the function. */
7035 si_create_function(&ctx, returns, num_returns, params,
7036 num_params, last_sgpr);
7037 func = ctx.radeon_bld.main_fn;
7038
7039 /* Copy inputs to outputs. This should be no-op, as the registers match,
7040 * but it will prevent the compiler from overwriting them unintentionally.
7041 */
7042 ret = ctx.return_value;
7043 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7044 LLVMValueRef p = LLVMGetParam(func, i);
7045 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7046 }
7047 for (i = num_params - 4; i < num_params; i++) {
7048 LLVMValueRef p = LLVMGetParam(func, i);
7049 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
7050 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7051 }
7052
7053 /* Compute vertex load indices from instance divisors. */
7054 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7055 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7056 LLVMValueRef index;
7057
7058 if (divisor) {
7059 /* InstanceID / Divisor + StartInstance */
7060 index = get_instance_index_for_fetch(&ctx.radeon_bld,
7061 SI_SGPR_START_INSTANCE,
7062 divisor);
7063 } else {
7064 /* VertexID + BaseVertex */
7065 index = LLVMBuildAdd(gallivm->builder,
7066 LLVMGetParam(func, ctx.param_vertex_id),
7067 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7068 }
7069
7070 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
7071 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7072 num_params++, "");
7073 }
7074
7075 /* Compile. */
7076 si_llvm_build_ret(&ctx, ret);
7077 radeon_llvm_finalize_module(&ctx.radeon_bld);
7078
7079 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7080 gallivm->module, debug, ctx.type,
7081 "Vertex Shader Prolog"))
7082 status = false;
7083
7084 radeon_llvm_dispose(&ctx.radeon_bld);
7085 return status;
7086 }
7087
7088 /**
7089 * Compile the vertex shader epilog. This is also used by the tessellation
7090 * evaluation shader compiled as VS.
7091 *
7092 * The input is PrimitiveID.
7093 *
7094 * If PrimitiveID is required by the pixel shader, export it.
7095 * Otherwise, do nothing.
7096 */
7097 static bool si_compile_vs_epilog(struct si_screen *sscreen,
7098 LLVMTargetMachineRef tm,
7099 struct pipe_debug_callback *debug,
7100 struct si_shader_part *out)
7101 {
7102 union si_shader_part_key *key = &out->key;
7103 struct si_shader_context ctx;
7104 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7105 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7106 LLVMTypeRef params[5];
7107 int num_params, i;
7108 bool status = true;
7109
7110 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
7111 ctx.type = PIPE_SHADER_VERTEX;
7112
7113 /* Declare input VGPRs. */
7114 num_params = key->vs_epilog.states.export_prim_id ?
7115 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7116 assert(num_params <= ARRAY_SIZE(params));
7117
7118 for (i = 0; i < num_params; i++)
7119 params[i] = ctx.f32;
7120
7121 /* Create the function. */
7122 si_create_function(&ctx, NULL, 0, params, num_params, -1);
7123
7124 /* Emit exports. */
7125 if (key->vs_epilog.states.export_prim_id) {
7126 struct lp_build_context *base = &bld_base->base;
7127 struct lp_build_context *uint = &bld_base->uint_bld;
7128 LLVMValueRef args[9];
7129
7130 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7131 args[1] = uint->zero; /* whether the EXEC mask is valid */
7132 args[2] = uint->zero; /* DONE bit */
7133 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7134 key->vs_epilog.prim_id_param_offset);
7135 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7136 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
7137 VS_EPILOG_PRIMID_LOC); /* X */
7138 args[6] = uint->undef; /* Y */
7139 args[7] = uint->undef; /* Z */
7140 args[8] = uint->undef; /* W */
7141
7142 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7143 LLVMVoidTypeInContext(base->gallivm->context),
7144 args, 9, 0);
7145 }
7146
7147 /* Compile. */
7148 LLVMBuildRetVoid(gallivm->builder);
7149 radeon_llvm_finalize_module(&ctx.radeon_bld);
7150
7151 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7152 gallivm->module, debug, ctx.type,
7153 "Vertex Shader Epilog"))
7154 status = false;
7155
7156 radeon_llvm_dispose(&ctx.radeon_bld);
7157 return status;
7158 }
7159
7160 /**
7161 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7162 */
7163 static bool si_get_vs_epilog(struct si_screen *sscreen,
7164 LLVMTargetMachineRef tm,
7165 struct si_shader *shader,
7166 struct pipe_debug_callback *debug,
7167 struct si_vs_epilog_bits *states)
7168 {
7169 union si_shader_part_key epilog_key;
7170
7171 memset(&epilog_key, 0, sizeof(epilog_key));
7172 epilog_key.vs_epilog.states = *states;
7173
7174 /* Set up the PrimitiveID output. */
7175 if (shader->key.vs.epilog.export_prim_id) {
7176 unsigned index = shader->selector->info.num_outputs;
7177 unsigned offset = shader->info.nr_param_exports++;
7178
7179 epilog_key.vs_epilog.prim_id_param_offset = offset;
7180 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7181 shader->info.vs_output_param_offset[index] = offset;
7182 }
7183
7184 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7185 &epilog_key, tm, debug,
7186 si_compile_vs_epilog);
7187 return shader->epilog != NULL;
7188 }
7189
7190 /**
7191 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7192 */
7193 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7194 LLVMTargetMachineRef tm,
7195 struct si_shader *shader,
7196 struct pipe_debug_callback *debug)
7197 {
7198 struct tgsi_shader_info *info = &shader->selector->info;
7199 union si_shader_part_key prolog_key;
7200 unsigned i;
7201
7202 /* Get the prolog. */
7203 memset(&prolog_key, 0, sizeof(prolog_key));
7204 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7205 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7206 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7207
7208 /* The prolog is a no-op if there are no inputs. */
7209 if (info->num_inputs) {
7210 shader->prolog =
7211 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7212 &prolog_key, tm, debug,
7213 si_compile_vs_prolog);
7214 if (!shader->prolog)
7215 return false;
7216 }
7217
7218 /* Get the epilog. */
7219 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7220 !si_get_vs_epilog(sscreen, tm, shader, debug,
7221 &shader->key.vs.epilog))
7222 return false;
7223
7224 /* Set the instanceID flag. */
7225 for (i = 0; i < info->num_inputs; i++)
7226 if (prolog_key.vs_prolog.states.instance_divisors[i])
7227 shader->info.uses_instanceid = true;
7228
7229 return true;
7230 }
7231
7232 /**
7233 * Select and compile (or reuse) TES parts (epilog).
7234 */
7235 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7236 LLVMTargetMachineRef tm,
7237 struct si_shader *shader,
7238 struct pipe_debug_callback *debug)
7239 {
7240 if (shader->key.tes.as_es)
7241 return true;
7242
7243 /* TES compiled as VS. */
7244 return si_get_vs_epilog(sscreen, tm, shader, debug,
7245 &shader->key.tes.epilog);
7246 }
7247
7248 /**
7249 * Compile the TCS epilog. This writes tesselation factors to memory based on
7250 * the output primitive type of the tesselator (determined by TES).
7251 */
7252 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7253 LLVMTargetMachineRef tm,
7254 struct pipe_debug_callback *debug,
7255 struct si_shader_part *out)
7256 {
7257 union si_shader_part_key *key = &out->key;
7258 struct si_shader shader = {};
7259 struct si_shader_context ctx;
7260 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7261 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7262 LLVMTypeRef params[16];
7263 LLVMValueRef func;
7264 int last_sgpr, num_params;
7265 bool status = true;
7266
7267 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7268 ctx.type = PIPE_SHADER_TESS_CTRL;
7269 shader.key.tcs.epilog = key->tcs_epilog.states;
7270
7271 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7272 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7273 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7274 params[SI_PARAM_SAMPLERS] = ctx.i64;
7275 params[SI_PARAM_IMAGES] = ctx.i64;
7276 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7277 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7278 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7279 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7280 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7281 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7282 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7283 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7284 num_params = last_sgpr + 1;
7285
7286 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7287 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7288 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7289
7290 /* Create the function. */
7291 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7292 declare_tess_lds(&ctx);
7293 func = ctx.radeon_bld.main_fn;
7294
7295 si_write_tess_factors(bld_base,
7296 LLVMGetParam(func, last_sgpr + 1),
7297 LLVMGetParam(func, last_sgpr + 2),
7298 LLVMGetParam(func, last_sgpr + 3));
7299
7300 /* Compile. */
7301 LLVMBuildRetVoid(gallivm->builder);
7302 radeon_llvm_finalize_module(&ctx.radeon_bld);
7303
7304 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7305 gallivm->module, debug, ctx.type,
7306 "Tessellation Control Shader Epilog"))
7307 status = false;
7308
7309 radeon_llvm_dispose(&ctx.radeon_bld);
7310 return status;
7311 }
7312
7313 /**
7314 * Select and compile (or reuse) TCS parts (epilog).
7315 */
7316 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7317 LLVMTargetMachineRef tm,
7318 struct si_shader *shader,
7319 struct pipe_debug_callback *debug)
7320 {
7321 union si_shader_part_key epilog_key;
7322
7323 /* Get the epilog. */
7324 memset(&epilog_key, 0, sizeof(epilog_key));
7325 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7326
7327 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7328 &epilog_key, tm, debug,
7329 si_compile_tcs_epilog);
7330 return shader->epilog != NULL;
7331 }
7332
7333 /**
7334 * Compile the pixel shader prolog. This handles:
7335 * - two-side color selection and interpolation
7336 * - overriding interpolation parameters for the API PS
7337 * - polygon stippling
7338 *
7339 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7340 * overriden by other states. (e.g. per-sample interpolation)
7341 * Interpolated colors are stored after the preloaded VGPRs.
7342 */
7343 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7344 LLVMTargetMachineRef tm,
7345 struct pipe_debug_callback *debug,
7346 struct si_shader_part *out)
7347 {
7348 union si_shader_part_key *key = &out->key;
7349 struct si_shader shader = {};
7350 struct si_shader_context ctx;
7351 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7352 LLVMTypeRef *params;
7353 LLVMValueRef ret, func;
7354 int last_sgpr, num_params, num_returns, i, num_color_channels;
7355 bool status = true;
7356
7357 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7358 ctx.type = PIPE_SHADER_FRAGMENT;
7359 shader.key.ps.prolog = key->ps_prolog.states;
7360
7361 /* Number of inputs + 8 color elements. */
7362 params = alloca((key->ps_prolog.num_input_sgprs +
7363 key->ps_prolog.num_input_vgprs + 8) *
7364 sizeof(LLVMTypeRef));
7365
7366 /* Declare inputs. */
7367 num_params = 0;
7368 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7369 params[num_params++] = ctx.i32;
7370 last_sgpr = num_params - 1;
7371
7372 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7373 params[num_params++] = ctx.f32;
7374
7375 /* Declare outputs (same as inputs + add colors if needed) */
7376 num_returns = num_params;
7377 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7378 for (i = 0; i < num_color_channels; i++)
7379 params[num_returns++] = ctx.f32;
7380
7381 /* Create the function. */
7382 si_create_function(&ctx, params, num_returns, params,
7383 num_params, last_sgpr);
7384 func = ctx.radeon_bld.main_fn;
7385
7386 /* Copy inputs to outputs. This should be no-op, as the registers match,
7387 * but it will prevent the compiler from overwriting them unintentionally.
7388 */
7389 ret = ctx.return_value;
7390 for (i = 0; i < num_params; i++) {
7391 LLVMValueRef p = LLVMGetParam(func, i);
7392 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7393 }
7394
7395 /* Polygon stippling. */
7396 if (key->ps_prolog.states.poly_stipple) {
7397 /* POS_FIXED_PT is always last. */
7398 unsigned pos = key->ps_prolog.num_input_sgprs +
7399 key->ps_prolog.num_input_vgprs - 1;
7400 LLVMValueRef ptr[2], list;
7401
7402 /* Get the pointer to rw buffers. */
7403 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7404 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7405 list = lp_build_gather_values(gallivm, ptr, 2);
7406 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7407 list = LLVMBuildIntToPtr(gallivm->builder, list,
7408 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7409
7410 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7411 }
7412
7413 if (key->ps_prolog.states.bc_optimize_for_persp ||
7414 key->ps_prolog.states.bc_optimize_for_linear) {
7415 unsigned i, base = key->ps_prolog.num_input_sgprs;
7416 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7417
7418 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7419 * The hw doesn't compute CENTROID if the whole wave only
7420 * contains fully-covered quads.
7421 *
7422 * PRIM_MASK is after user SGPRs.
7423 */
7424 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7425 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7426 LLVMConstInt(ctx.i32, 31, 0), "");
7427 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7428 ctx.i1, "");
7429
7430 if (key->ps_prolog.states.bc_optimize_for_persp) {
7431 /* Read PERSP_CENTER. */
7432 for (i = 0; i < 2; i++)
7433 center[i] = LLVMGetParam(func, base + 2 + i);
7434 /* Read PERSP_CENTROID. */
7435 for (i = 0; i < 2; i++)
7436 centroid[i] = LLVMGetParam(func, base + 4 + i);
7437 /* Select PERSP_CENTROID. */
7438 for (i = 0; i < 2; i++) {
7439 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7440 center[i], centroid[i], "");
7441 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7442 tmp, base + 4 + i, "");
7443 }
7444 }
7445 if (key->ps_prolog.states.bc_optimize_for_linear) {
7446 /* Read LINEAR_CENTER. */
7447 for (i = 0; i < 2; i++)
7448 center[i] = LLVMGetParam(func, base + 8 + i);
7449 /* Read LINEAR_CENTROID. */
7450 for (i = 0; i < 2; i++)
7451 centroid[i] = LLVMGetParam(func, base + 10 + i);
7452 /* Select LINEAR_CENTROID. */
7453 for (i = 0; i < 2; i++) {
7454 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7455 center[i], centroid[i], "");
7456 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7457 tmp, base + 10 + i, "");
7458 }
7459 }
7460 }
7461
7462 /* Interpolate colors. */
7463 for (i = 0; i < 2; i++) {
7464 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7465 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7466 key->ps_prolog.face_vgpr_index;
7467 LLVMValueRef interp[2], color[4];
7468 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7469
7470 if (!writemask)
7471 continue;
7472
7473 /* If the interpolation qualifier is not CONSTANT (-1). */
7474 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7475 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7476 key->ps_prolog.color_interp_vgpr_index[i];
7477
7478 /* Get the (i,j) updated by bc_optimize handling. */
7479 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7480 interp_vgpr, "");
7481 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7482 interp_vgpr + 1, "");
7483 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7484 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7485 ctx.v2i32, "");
7486 }
7487
7488 /* Use the absolute location of the input. */
7489 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7490
7491 if (key->ps_prolog.states.color_two_side) {
7492 face = LLVMGetParam(func, face_vgpr);
7493 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7494 }
7495
7496 interp_fs_input(&ctx,
7497 key->ps_prolog.color_attr_index[i],
7498 TGSI_SEMANTIC_COLOR, i,
7499 key->ps_prolog.num_interp_inputs,
7500 key->ps_prolog.colors_read, interp_ij,
7501 prim_mask, face, color);
7502
7503 while (writemask) {
7504 unsigned chan = u_bit_scan(&writemask);
7505 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7506 num_params++, "");
7507 }
7508 }
7509
7510 /* Force per-sample interpolation. */
7511 if (key->ps_prolog.states.force_persp_sample_interp) {
7512 unsigned i, base = key->ps_prolog.num_input_sgprs;
7513 LLVMValueRef persp_sample[2];
7514
7515 /* Read PERSP_SAMPLE. */
7516 for (i = 0; i < 2; i++)
7517 persp_sample[i] = LLVMGetParam(func, base + i);
7518 /* Overwrite PERSP_CENTER. */
7519 for (i = 0; i < 2; i++)
7520 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7521 persp_sample[i], base + 2 + i, "");
7522 /* Overwrite PERSP_CENTROID. */
7523 for (i = 0; i < 2; i++)
7524 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7525 persp_sample[i], base + 4 + i, "");
7526 }
7527 if (key->ps_prolog.states.force_linear_sample_interp) {
7528 unsigned i, base = key->ps_prolog.num_input_sgprs;
7529 LLVMValueRef linear_sample[2];
7530
7531 /* Read LINEAR_SAMPLE. */
7532 for (i = 0; i < 2; i++)
7533 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7534 /* Overwrite LINEAR_CENTER. */
7535 for (i = 0; i < 2; i++)
7536 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7537 linear_sample[i], base + 8 + i, "");
7538 /* Overwrite LINEAR_CENTROID. */
7539 for (i = 0; i < 2; i++)
7540 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7541 linear_sample[i], base + 10 + i, "");
7542 }
7543
7544 /* Force center interpolation. */
7545 if (key->ps_prolog.states.force_persp_center_interp) {
7546 unsigned i, base = key->ps_prolog.num_input_sgprs;
7547 LLVMValueRef persp_center[2];
7548
7549 /* Read PERSP_CENTER. */
7550 for (i = 0; i < 2; i++)
7551 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7552 /* Overwrite PERSP_SAMPLE. */
7553 for (i = 0; i < 2; i++)
7554 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7555 persp_center[i], base + i, "");
7556 /* Overwrite PERSP_CENTROID. */
7557 for (i = 0; i < 2; i++)
7558 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7559 persp_center[i], base + 4 + i, "");
7560 }
7561 if (key->ps_prolog.states.force_linear_center_interp) {
7562 unsigned i, base = key->ps_prolog.num_input_sgprs;
7563 LLVMValueRef linear_center[2];
7564
7565 /* Read LINEAR_CENTER. */
7566 for (i = 0; i < 2; i++)
7567 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7568 /* Overwrite LINEAR_SAMPLE. */
7569 for (i = 0; i < 2; i++)
7570 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7571 linear_center[i], base + 6 + i, "");
7572 /* Overwrite LINEAR_CENTROID. */
7573 for (i = 0; i < 2; i++)
7574 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7575 linear_center[i], base + 10 + i, "");
7576 }
7577
7578 /* Tell LLVM to insert WQM instruction sequence when needed. */
7579 if (key->ps_prolog.wqm) {
7580 LLVMAddTargetDependentFunctionAttr(func,
7581 "amdgpu-ps-wqm-outputs", "");
7582 }
7583
7584 /* Compile. */
7585 si_llvm_build_ret(&ctx, ret);
7586 radeon_llvm_finalize_module(&ctx.radeon_bld);
7587
7588 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7589 gallivm->module, debug, ctx.type,
7590 "Fragment Shader Prolog"))
7591 status = false;
7592
7593 radeon_llvm_dispose(&ctx.radeon_bld);
7594 return status;
7595 }
7596
7597 /**
7598 * Compile the pixel shader epilog. This handles everything that must be
7599 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7600 */
7601 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7602 LLVMTargetMachineRef tm,
7603 struct pipe_debug_callback *debug,
7604 struct si_shader_part *out)
7605 {
7606 union si_shader_part_key *key = &out->key;
7607 struct si_shader shader = {};
7608 struct si_shader_context ctx;
7609 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7610 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7611 LLVMTypeRef params[16+8*4+3];
7612 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7613 int last_sgpr, num_params, i;
7614 bool status = true;
7615 struct si_ps_exports exp = {};
7616
7617 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7618 ctx.type = PIPE_SHADER_FRAGMENT;
7619 shader.key.ps.epilog = key->ps_epilog.states;
7620
7621 /* Declare input SGPRs. */
7622 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7623 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7624 params[SI_PARAM_SAMPLERS] = ctx.i64;
7625 params[SI_PARAM_IMAGES] = ctx.i64;
7626 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7627 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7628 last_sgpr = SI_PARAM_ALPHA_REF;
7629
7630 /* Declare input VGPRs. */
7631 num_params = (last_sgpr + 1) +
7632 util_bitcount(key->ps_epilog.colors_written) * 4 +
7633 key->ps_epilog.writes_z +
7634 key->ps_epilog.writes_stencil +
7635 key->ps_epilog.writes_samplemask;
7636
7637 num_params = MAX2(num_params,
7638 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7639
7640 assert(num_params <= ARRAY_SIZE(params));
7641
7642 for (i = last_sgpr + 1; i < num_params; i++)
7643 params[i] = ctx.f32;
7644
7645 /* Create the function. */
7646 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7647 /* Disable elimination of unused inputs. */
7648 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7649 "InitialPSInputAddr", 0xffffff);
7650
7651 /* Process colors. */
7652 unsigned vgpr = last_sgpr + 1;
7653 unsigned colors_written = key->ps_epilog.colors_written;
7654 int last_color_export = -1;
7655
7656 /* Find the last color export. */
7657 if (!key->ps_epilog.writes_z &&
7658 !key->ps_epilog.writes_stencil &&
7659 !key->ps_epilog.writes_samplemask) {
7660 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7661
7662 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7663 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7664 /* Just set this if any of the colorbuffers are enabled. */
7665 if (spi_format &
7666 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7667 last_color_export = 0;
7668 } else {
7669 for (i = 0; i < 8; i++)
7670 if (colors_written & (1 << i) &&
7671 (spi_format >> (i * 4)) & 0xf)
7672 last_color_export = i;
7673 }
7674 }
7675
7676 while (colors_written) {
7677 LLVMValueRef color[4];
7678 int mrt = u_bit_scan(&colors_written);
7679
7680 for (i = 0; i < 4; i++)
7681 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7682
7683 si_export_mrt_color(bld_base, color, mrt,
7684 num_params - 1,
7685 mrt == last_color_export, &exp);
7686 }
7687
7688 /* Process depth, stencil, samplemask. */
7689 if (key->ps_epilog.writes_z)
7690 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7691 if (key->ps_epilog.writes_stencil)
7692 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7693 if (key->ps_epilog.writes_samplemask)
7694 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7695
7696 if (depth || stencil || samplemask)
7697 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7698 else if (last_color_export == -1)
7699 si_export_null(bld_base);
7700
7701 if (exp.num)
7702 si_emit_ps_exports(&ctx, &exp);
7703
7704 /* Compile. */
7705 LLVMBuildRetVoid(gallivm->builder);
7706 radeon_llvm_finalize_module(&ctx.radeon_bld);
7707
7708 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7709 gallivm->module, debug, ctx.type,
7710 "Fragment Shader Epilog"))
7711 status = false;
7712
7713 radeon_llvm_dispose(&ctx.radeon_bld);
7714 return status;
7715 }
7716
7717 /**
7718 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7719 */
7720 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7721 LLVMTargetMachineRef tm,
7722 struct si_shader *shader,
7723 struct pipe_debug_callback *debug)
7724 {
7725 struct tgsi_shader_info *info = &shader->selector->info;
7726 union si_shader_part_key prolog_key;
7727 union si_shader_part_key epilog_key;
7728 unsigned i;
7729
7730 /* Get the prolog. */
7731 memset(&prolog_key, 0, sizeof(prolog_key));
7732 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7733 prolog_key.ps_prolog.colors_read = info->colors_read;
7734 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7735 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7736 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7737 (prolog_key.ps_prolog.colors_read ||
7738 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7739 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7740 prolog_key.ps_prolog.states.force_persp_center_interp ||
7741 prolog_key.ps_prolog.states.force_linear_center_interp ||
7742 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7743 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7744
7745 if (info->colors_read) {
7746 unsigned *color = shader->selector->color_attr_index;
7747
7748 if (shader->key.ps.prolog.color_two_side) {
7749 /* BCOLORs are stored after the last input. */
7750 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7751 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7752 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7753 }
7754
7755 for (i = 0; i < 2; i++) {
7756 unsigned interp = info->input_interpolate[color[i]];
7757 unsigned location = info->input_interpolate_loc[color[i]];
7758
7759 if (!(info->colors_read & (0xf << i*4)))
7760 continue;
7761
7762 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7763
7764 if (shader->key.ps.prolog.flatshade_colors &&
7765 interp == TGSI_INTERPOLATE_COLOR)
7766 interp = TGSI_INTERPOLATE_CONSTANT;
7767
7768 switch (interp) {
7769 case TGSI_INTERPOLATE_CONSTANT:
7770 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7771 break;
7772 case TGSI_INTERPOLATE_PERSPECTIVE:
7773 case TGSI_INTERPOLATE_COLOR:
7774 /* Force the interpolation location for colors here. */
7775 if (shader->key.ps.prolog.force_persp_sample_interp)
7776 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7777 if (shader->key.ps.prolog.force_persp_center_interp)
7778 location = TGSI_INTERPOLATE_LOC_CENTER;
7779
7780 switch (location) {
7781 case TGSI_INTERPOLATE_LOC_SAMPLE:
7782 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7783 shader->config.spi_ps_input_ena |=
7784 S_0286CC_PERSP_SAMPLE_ENA(1);
7785 break;
7786 case TGSI_INTERPOLATE_LOC_CENTER:
7787 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7788 shader->config.spi_ps_input_ena |=
7789 S_0286CC_PERSP_CENTER_ENA(1);
7790 break;
7791 case TGSI_INTERPOLATE_LOC_CENTROID:
7792 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7793 shader->config.spi_ps_input_ena |=
7794 S_0286CC_PERSP_CENTROID_ENA(1);
7795 break;
7796 default:
7797 assert(0);
7798 }
7799 break;
7800 case TGSI_INTERPOLATE_LINEAR:
7801 /* Force the interpolation location for colors here. */
7802 if (shader->key.ps.prolog.force_linear_sample_interp)
7803 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7804 if (shader->key.ps.prolog.force_linear_center_interp)
7805 location = TGSI_INTERPOLATE_LOC_CENTER;
7806
7807 switch (location) {
7808 case TGSI_INTERPOLATE_LOC_SAMPLE:
7809 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7810 shader->config.spi_ps_input_ena |=
7811 S_0286CC_LINEAR_SAMPLE_ENA(1);
7812 break;
7813 case TGSI_INTERPOLATE_LOC_CENTER:
7814 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7815 shader->config.spi_ps_input_ena |=
7816 S_0286CC_LINEAR_CENTER_ENA(1);
7817 break;
7818 case TGSI_INTERPOLATE_LOC_CENTROID:
7819 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7820 shader->config.spi_ps_input_ena |=
7821 S_0286CC_LINEAR_CENTROID_ENA(1);
7822 break;
7823 default:
7824 assert(0);
7825 }
7826 break;
7827 default:
7828 assert(0);
7829 }
7830 }
7831 }
7832
7833 /* The prolog is a no-op if these aren't set. */
7834 if (prolog_key.ps_prolog.colors_read ||
7835 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7836 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7837 prolog_key.ps_prolog.states.force_persp_center_interp ||
7838 prolog_key.ps_prolog.states.force_linear_center_interp ||
7839 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7840 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7841 prolog_key.ps_prolog.states.poly_stipple) {
7842 shader->prolog =
7843 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7844 &prolog_key, tm, debug,
7845 si_compile_ps_prolog);
7846 if (!shader->prolog)
7847 return false;
7848 }
7849
7850 /* Get the epilog. */
7851 memset(&epilog_key, 0, sizeof(epilog_key));
7852 epilog_key.ps_epilog.colors_written = info->colors_written;
7853 epilog_key.ps_epilog.writes_z = info->writes_z;
7854 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7855 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7856 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7857
7858 shader->epilog =
7859 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7860 &epilog_key, tm, debug,
7861 si_compile_ps_epilog);
7862 if (!shader->epilog)
7863 return false;
7864
7865 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7866 if (shader->key.ps.prolog.poly_stipple) {
7867 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7868 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7869 }
7870
7871 /* Set up the enable bits for per-sample shading if needed. */
7872 if (shader->key.ps.prolog.force_persp_sample_interp &&
7873 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7874 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7875 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7876 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7877 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7878 }
7879 if (shader->key.ps.prolog.force_linear_sample_interp &&
7880 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7881 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7882 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7883 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7884 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7885 }
7886 if (shader->key.ps.prolog.force_persp_center_interp &&
7887 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7888 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7889 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7890 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7891 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7892 }
7893 if (shader->key.ps.prolog.force_linear_center_interp &&
7894 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7895 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7896 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7897 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7898 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7899 }
7900
7901 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7902 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7903 !(shader->config.spi_ps_input_ena & 0xf)) {
7904 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7905 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7906 }
7907
7908 /* At least one pair of interpolation weights must be enabled. */
7909 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7910 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7911 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7912 }
7913
7914 /* The sample mask input is always enabled, because the API shader always
7915 * passes it through to the epilog. Disable it here if it's unused.
7916 */
7917 if (!shader->key.ps.epilog.poly_line_smoothing &&
7918 !shader->selector->info.reads_samplemask)
7919 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7920
7921 return true;
7922 }
7923
7924 static void si_fix_num_sgprs(struct si_shader *shader)
7925 {
7926 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7927
7928 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7929 }
7930
7931 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7932 struct si_shader *shader,
7933 struct pipe_debug_callback *debug)
7934 {
7935 struct si_shader *mainp = shader->selector->main_shader_part;
7936 int r;
7937
7938 /* LS, ES, VS are compiled on demand if the main part hasn't been
7939 * compiled for that stage.
7940 */
7941 if (!mainp ||
7942 (shader->selector->type == PIPE_SHADER_VERTEX &&
7943 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7944 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7945 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7946 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7947 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7948 shader->key.tcs.epilog.inputs_to_copy) ||
7949 shader->selector->type == PIPE_SHADER_COMPUTE) {
7950 /* Monolithic shader (compiled as a whole, has many variants,
7951 * may take a long time to compile).
7952 */
7953 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7954 if (r)
7955 return r;
7956 } else {
7957 /* The shader consists of 2-3 parts:
7958 *
7959 * - the middle part is the user shader, it has 1 variant only
7960 * and it was compiled during the creation of the shader
7961 * selector
7962 * - the prolog part is inserted at the beginning
7963 * - the epilog part is inserted at the end
7964 *
7965 * The prolog and epilog have many (but simple) variants.
7966 */
7967
7968 /* Copy the compiled TGSI shader data over. */
7969 shader->is_binary_shared = true;
7970 shader->binary = mainp->binary;
7971 shader->config = mainp->config;
7972 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7973 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7974 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7975 memcpy(shader->info.vs_output_param_offset,
7976 mainp->info.vs_output_param_offset,
7977 sizeof(mainp->info.vs_output_param_offset));
7978 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7979 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7980 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7981
7982 /* Select prologs and/or epilogs. */
7983 switch (shader->selector->type) {
7984 case PIPE_SHADER_VERTEX:
7985 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7986 return -1;
7987 break;
7988 case PIPE_SHADER_TESS_CTRL:
7989 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7990 return -1;
7991 break;
7992 case PIPE_SHADER_TESS_EVAL:
7993 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7994 return -1;
7995 break;
7996 case PIPE_SHADER_FRAGMENT:
7997 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7998 return -1;
7999
8000 /* Make sure we have at least as many VGPRs as there
8001 * are allocated inputs.
8002 */
8003 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8004 shader->info.num_input_vgprs);
8005 break;
8006 }
8007
8008 /* Update SGPR and VGPR counts. */
8009 if (shader->prolog) {
8010 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8011 shader->prolog->config.num_sgprs);
8012 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8013 shader->prolog->config.num_vgprs);
8014 }
8015 if (shader->epilog) {
8016 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8017 shader->epilog->config.num_sgprs);
8018 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8019 shader->epilog->config.num_vgprs);
8020 }
8021 }
8022
8023 si_fix_num_sgprs(shader);
8024 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
8025 stderr);
8026
8027 /* Upload. */
8028 r = si_shader_binary_upload(sscreen, shader);
8029 if (r) {
8030 fprintf(stderr, "LLVM failed to upload shader\n");
8031 return r;
8032 }
8033
8034 return 0;
8035 }
8036
8037 void si_shader_destroy(struct si_shader *shader)
8038 {
8039 if (shader->gs_copy_shader) {
8040 si_shader_destroy(shader->gs_copy_shader);
8041 FREE(shader->gs_copy_shader);
8042 }
8043
8044 if (shader->scratch_bo)
8045 r600_resource_reference(&shader->scratch_bo, NULL);
8046
8047 r600_resource_reference(&shader->bo, NULL);
8048
8049 if (!shader->is_binary_shared)
8050 radeon_shader_binary_clean(&shader->binary);
8051
8052 free(shader->shader_log);
8053 }