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radeonsi: Create a helper function for computing the thread id
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94
95 LLVMTargetMachineRef tm;
96
97 LLVMValueRef const_md;
98 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
99 LLVMValueRef lds;
100 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
101 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
102 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
103 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
104 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
105 LLVMValueRef images[SI_NUM_IMAGES];
106 LLVMValueRef so_buffers[4];
107 LLVMValueRef esgs_ring;
108 LLVMValueRef gsvs_ring[4];
109 LLVMValueRef gs_next_vertex[4];
110 LLVMValueRef return_value;
111
112 LLVMTypeRef voidt;
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i32;
116 LLVMTypeRef i64;
117 LLVMTypeRef i128;
118 LLVMTypeRef f32;
119 LLVMTypeRef v16i8;
120 LLVMTypeRef v2i32;
121 LLVMTypeRef v4i32;
122 LLVMTypeRef v4f32;
123 LLVMTypeRef v8i32;
124
125 LLVMValueRef shared_memory;
126 };
127
128 static struct si_shader_context *si_shader_context(
129 struct lp_build_tgsi_context *bld_base)
130 {
131 return (struct si_shader_context *)bld_base;
132 }
133
134 static void si_init_shader_ctx(struct si_shader_context *ctx,
135 struct si_screen *sscreen,
136 struct si_shader *shader,
137 LLVMTargetMachineRef tm);
138
139 /* Ideally pass the sample mask input to the PS epilog as v13, which
140 * is its usual location, so that the shader doesn't have to add v_mov.
141 */
142 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
143
144 /* The VS location of the PrimitiveID input is the same in the epilog,
145 * so that the main shader part doesn't have to move it.
146 */
147 #define VS_EPILOG_PRIMID_LOC 2
148
149 #define PERSPECTIVE_BASE 0
150 #define LINEAR_BASE 9
151
152 #define SAMPLE_OFFSET 0
153 #define CENTER_OFFSET 2
154 #define CENTROID_OFSET 4
155
156 #define USE_SGPR_MAX_SUFFIX_LEN 5
157 #define CONST_ADDR_SPACE 2
158 #define LOCAL_ADDR_SPACE 3
159 #define USER_SGPR_ADDR_SPACE 8
160
161
162 #define SENDMSG_GS 2
163 #define SENDMSG_GS_DONE 3
164
165 #define SENDMSG_GS_OP_NOP (0 << 4)
166 #define SENDMSG_GS_OP_CUT (1 << 4)
167 #define SENDMSG_GS_OP_EMIT (2 << 4)
168 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
169
170 /**
171 * Returns a unique index for a semantic name and index. The index must be
172 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
173 * calculated.
174 */
175 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
176 {
177 switch (semantic_name) {
178 case TGSI_SEMANTIC_POSITION:
179 return 0;
180 case TGSI_SEMANTIC_PSIZE:
181 return 1;
182 case TGSI_SEMANTIC_CLIPDIST:
183 assert(index <= 1);
184 return 2 + index;
185 case TGSI_SEMANTIC_GENERIC:
186 if (index <= 63-4)
187 return 4 + index;
188 else
189 /* same explanation as in the default statement,
190 * the only user hitting this is st/nine.
191 */
192 return 0;
193
194 /* patch indices are completely separate and thus start from 0 */
195 case TGSI_SEMANTIC_TESSOUTER:
196 return 0;
197 case TGSI_SEMANTIC_TESSINNER:
198 return 1;
199 case TGSI_SEMANTIC_PATCH:
200 return 2 + index;
201
202 default:
203 /* Don't fail here. The result of this function is only used
204 * for LS, TCS, TES, and GS, where legacy GL semantics can't
205 * occur, but this function is called for all vertex shaders
206 * before it's known whether LS will be compiled or not.
207 */
208 return 0;
209 }
210 }
211
212 /**
213 * Get the value of a shader input parameter and extract a bitfield.
214 */
215 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
216 unsigned param, unsigned rshift,
217 unsigned bitwidth)
218 {
219 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
220 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
221 param);
222
223 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
224 value = bitcast(&ctx->radeon_bld.soa.bld_base,
225 TGSI_TYPE_UNSIGNED, value);
226
227 if (rshift)
228 value = LLVMBuildLShr(gallivm->builder, value,
229 lp_build_const_int32(gallivm, rshift), "");
230
231 if (rshift + bitwidth < 32) {
232 unsigned mask = (1 << bitwidth) - 1;
233 value = LLVMBuildAnd(gallivm->builder, value,
234 lp_build_const_int32(gallivm, mask), "");
235 }
236
237 return value;
238 }
239
240 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
241 {
242 switch (ctx->type) {
243 case PIPE_SHADER_TESS_CTRL:
244 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
245
246 case PIPE_SHADER_TESS_EVAL:
247 return LLVMGetParam(ctx->radeon_bld.main_fn,
248 ctx->param_tes_rel_patch_id);
249
250 default:
251 assert(0);
252 return NULL;
253 }
254 }
255
256 /* Tessellation shaders pass outputs to the next shader using LDS.
257 *
258 * LS outputs = TCS inputs
259 * TCS outputs = TES inputs
260 *
261 * The LDS layout is:
262 * - TCS inputs for patch 0
263 * - TCS inputs for patch 1
264 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
265 * - ...
266 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
267 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
268 * - TCS outputs for patch 1
269 * - Per-patch TCS outputs for patch 1
270 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
271 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
272 * - ...
273 *
274 * All three shaders VS(LS), TCS, TES share the same LDS space.
275 */
276
277 static LLVMValueRef
278 get_tcs_in_patch_stride(struct si_shader_context *ctx)
279 {
280 if (ctx->type == PIPE_SHADER_VERTEX)
281 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
282 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
283 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
284 else {
285 assert(0);
286 return NULL;
287 }
288 }
289
290 static LLVMValueRef
291 get_tcs_out_patch_stride(struct si_shader_context *ctx)
292 {
293 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
294 }
295
296 static LLVMValueRef
297 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
298 {
299 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
300 unpack_param(ctx,
301 SI_PARAM_TCS_OUT_OFFSETS,
302 0, 16),
303 4);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
308 {
309 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
310 unpack_param(ctx,
311 SI_PARAM_TCS_OUT_OFFSETS,
312 16, 16),
313 4);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
318 {
319 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
320 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
321 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
322
323 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
324 }
325
326 static LLVMValueRef
327 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
328 {
329 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
330 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
331 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
332 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
333
334 return LLVMBuildAdd(gallivm->builder, patch0_offset,
335 LLVMBuildMul(gallivm->builder, patch_stride,
336 rel_patch_id, ""),
337 "");
338 }
339
340 static LLVMValueRef
341 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
342 {
343 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
344 LLVMValueRef patch0_patch_data_offset =
345 get_tcs_out_patch0_patch_data_offset(ctx);
346 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
350 LLVMBuildMul(gallivm->builder, patch_stride,
351 rel_patch_id, ""),
352 "");
353 }
354
355 static void build_indexed_store(struct si_shader_context *ctx,
356 LLVMValueRef base_ptr, LLVMValueRef index,
357 LLVMValueRef value)
358 {
359 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
360 struct gallivm_state *gallivm = bld_base->base.gallivm;
361 LLVMValueRef indices[2], pointer;
362
363 indices[0] = bld_base->uint_bld.zero;
364 indices[1] = index;
365
366 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
367 LLVMBuildStore(gallivm->builder, value, pointer);
368 }
369
370 /**
371 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
372 * It's equivalent to doing a load from &base_ptr[index].
373 *
374 * \param base_ptr Where the array starts.
375 * \param index The element index into the array.
376 */
377 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
378 LLVMValueRef base_ptr, LLVMValueRef index)
379 {
380 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
381 struct gallivm_state *gallivm = bld_base->base.gallivm;
382 LLVMValueRef indices[2], pointer;
383
384 indices[0] = bld_base->uint_bld.zero;
385 indices[1] = index;
386
387 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
388 return LLVMBuildLoad(gallivm->builder, pointer, "");
389 }
390
391 /**
392 * Do a load from &base_ptr[index], but also add a flag that it's loading
393 * a constant.
394 */
395 static LLVMValueRef build_indexed_load_const(
396 struct si_shader_context *ctx,
397 LLVMValueRef base_ptr, LLVMValueRef index)
398 {
399 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
400 LLVMSetMetadata(result, 1, ctx->const_md);
401 return result;
402 }
403
404 static LLVMValueRef get_instance_index_for_fetch(
405 struct radeon_llvm_context *radeon_bld,
406 unsigned param_start_instance, unsigned divisor)
407 {
408 struct si_shader_context *ctx =
409 si_shader_context(&radeon_bld->soa.bld_base);
410 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
411
412 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
413 ctx->param_instance_id);
414
415 /* The division must be done before START_INSTANCE is added. */
416 if (divisor > 1)
417 result = LLVMBuildUDiv(gallivm->builder, result,
418 lp_build_const_int32(gallivm, divisor), "");
419
420 return LLVMBuildAdd(gallivm->builder, result,
421 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
422 }
423
424 static void declare_input_vs(
425 struct radeon_llvm_context *radeon_bld,
426 unsigned input_index,
427 const struct tgsi_full_declaration *decl)
428 {
429 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
430 struct gallivm_state *gallivm = base->gallivm;
431 struct si_shader_context *ctx =
432 si_shader_context(&radeon_bld->soa.bld_base);
433 unsigned divisor =
434 ctx->shader->key.vs.prolog.instance_divisors[input_index];
435
436 unsigned chan;
437
438 LLVMValueRef t_list_ptr;
439 LLVMValueRef t_offset;
440 LLVMValueRef t_list;
441 LLVMValueRef attribute_offset;
442 LLVMValueRef buffer_index;
443 LLVMValueRef args[3];
444 LLVMValueRef input;
445
446 /* Load the T list */
447 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
448
449 t_offset = lp_build_const_int32(gallivm, input_index);
450
451 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
452
453 /* Build the attribute offset */
454 attribute_offset = lp_build_const_int32(gallivm, 0);
455
456 if (!ctx->is_monolithic) {
457 buffer_index = LLVMGetParam(radeon_bld->main_fn,
458 ctx->param_vertex_index0 +
459 input_index);
460 } else if (divisor) {
461 /* Build index from instance ID, start instance and divisor */
462 ctx->shader->info.uses_instanceid = true;
463 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
464 SI_PARAM_START_INSTANCE,
465 divisor);
466 } else {
467 /* Load the buffer index for vertices. */
468 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
469 ctx->param_vertex_id);
470 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
471 SI_PARAM_BASE_VERTEX);
472 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
473 }
474
475 args[0] = t_list;
476 args[1] = attribute_offset;
477 args[2] = buffer_index;
478 input = lp_build_intrinsic(gallivm->builder,
479 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
480 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
481
482 /* Break up the vec4 into individual components */
483 for (chan = 0; chan < 4; chan++) {
484 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
485 /* XXX: Use a helper function for this. There is one in
486 * tgsi_llvm.c. */
487 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
488 LLVMBuildExtractElement(gallivm->builder,
489 input, llvm_chan, "");
490 }
491 }
492
493 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
494 unsigned swizzle)
495 {
496 struct si_shader_context *ctx = si_shader_context(bld_base);
497
498 if (swizzle > 0)
499 return bld_base->uint_bld.zero;
500
501 switch (ctx->type) {
502 case PIPE_SHADER_VERTEX:
503 return LLVMGetParam(ctx->radeon_bld.main_fn,
504 ctx->param_vs_prim_id);
505 case PIPE_SHADER_TESS_CTRL:
506 return LLVMGetParam(ctx->radeon_bld.main_fn,
507 SI_PARAM_PATCH_ID);
508 case PIPE_SHADER_TESS_EVAL:
509 return LLVMGetParam(ctx->radeon_bld.main_fn,
510 ctx->param_tes_patch_id);
511 case PIPE_SHADER_GEOMETRY:
512 return LLVMGetParam(ctx->radeon_bld.main_fn,
513 SI_PARAM_PRIMITIVE_ID);
514 default:
515 assert(0);
516 return bld_base->uint_bld.zero;
517 }
518 }
519
520 /**
521 * Return the value of tgsi_ind_register for indexing.
522 * This is the indirect index with the constant offset added to it.
523 */
524 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index)
527 {
528 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
529 LLVMValueRef result;
530
531 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
532 result = LLVMBuildLoad(gallivm->builder, result, "");
533 result = LLVMBuildAdd(gallivm->builder, result,
534 lp_build_const_int32(gallivm, rel_index), "");
535 return result;
536 }
537
538 /**
539 * Like get_indirect_index, but restricts the return value to a (possibly
540 * undefined) value inside [0..num).
541 */
542 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
543 const struct tgsi_ind_register *ind,
544 int rel_index, unsigned num)
545 {
546 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
547 LLVMBuilderRef builder = gallivm->builder;
548 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
549 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
550 LLVMValueRef cc;
551
552 if (util_is_power_of_two(num)) {
553 result = LLVMBuildAnd(builder, result, c_max, "");
554 } else {
555 /* In theory, this MAX pattern should result in code that is
556 * as good as the bit-wise AND above.
557 *
558 * In practice, LLVM generates worse code (at the time of
559 * writing), because its value tracking is not strong enough.
560 */
561 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
562 result = LLVMBuildSelect(builder, cc, result, c_max, "");
563 }
564
565 return result;
566 }
567
568
569 /**
570 * Calculate a dword address given an input or output register and a stride.
571 */
572 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
573 const struct tgsi_full_dst_register *dst,
574 const struct tgsi_full_src_register *src,
575 LLVMValueRef vertex_dw_stride,
576 LLVMValueRef base_addr)
577 {
578 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
579 struct tgsi_shader_info *info = &ctx->shader->selector->info;
580 ubyte *name, *index, *array_first;
581 int first, param;
582 struct tgsi_full_dst_register reg;
583
584 /* Set the register description. The address computation is the same
585 * for sources and destinations. */
586 if (src) {
587 reg.Register.File = src->Register.File;
588 reg.Register.Index = src->Register.Index;
589 reg.Register.Indirect = src->Register.Indirect;
590 reg.Register.Dimension = src->Register.Dimension;
591 reg.Indirect = src->Indirect;
592 reg.Dimension = src->Dimension;
593 reg.DimIndirect = src->DimIndirect;
594 } else
595 reg = *dst;
596
597 /* If the register is 2-dimensional (e.g. an array of vertices
598 * in a primitive), calculate the base address of the vertex. */
599 if (reg.Register.Dimension) {
600 LLVMValueRef index;
601
602 if (reg.Dimension.Indirect)
603 index = get_indirect_index(ctx, &reg.DimIndirect,
604 reg.Dimension.Index);
605 else
606 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
607
608 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
609 LLVMBuildMul(gallivm->builder, index,
610 vertex_dw_stride, ""), "");
611 }
612
613 /* Get information about the register. */
614 if (reg.Register.File == TGSI_FILE_INPUT) {
615 name = info->input_semantic_name;
616 index = info->input_semantic_index;
617 array_first = info->input_array_first;
618 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
619 name = info->output_semantic_name;
620 index = info->output_semantic_index;
621 array_first = info->output_array_first;
622 } else {
623 assert(0);
624 return NULL;
625 }
626
627 if (reg.Register.Indirect) {
628 /* Add the relative address of the element. */
629 LLVMValueRef ind_index;
630
631 if (reg.Indirect.ArrayID)
632 first = array_first[reg.Indirect.ArrayID];
633 else
634 first = reg.Register.Index;
635
636 ind_index = get_indirect_index(ctx, &reg.Indirect,
637 reg.Register.Index - first);
638
639 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
640 LLVMBuildMul(gallivm->builder, ind_index,
641 lp_build_const_int32(gallivm, 4), ""), "");
642
643 param = si_shader_io_get_unique_index(name[first], index[first]);
644 } else {
645 param = si_shader_io_get_unique_index(name[reg.Register.Index],
646 index[reg.Register.Index]);
647 }
648
649 /* Add the base address of the element. */
650 return LLVMBuildAdd(gallivm->builder, base_addr,
651 lp_build_const_int32(gallivm, param * 4), "");
652 }
653
654 /**
655 * Load from LDS.
656 *
657 * \param type output value type
658 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
659 * \param dw_addr address in dwords
660 */
661 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
662 enum tgsi_opcode_type type, unsigned swizzle,
663 LLVMValueRef dw_addr)
664 {
665 struct si_shader_context *ctx = si_shader_context(bld_base);
666 struct gallivm_state *gallivm = bld_base->base.gallivm;
667 LLVMValueRef value;
668
669 if (swizzle == ~0) {
670 LLVMValueRef values[TGSI_NUM_CHANNELS];
671
672 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
673 values[chan] = lds_load(bld_base, type, chan, dw_addr);
674
675 return lp_build_gather_values(bld_base->base.gallivm, values,
676 TGSI_NUM_CHANNELS);
677 }
678
679 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
680 lp_build_const_int32(gallivm, swizzle));
681
682 value = build_indexed_load(ctx, ctx->lds, dw_addr);
683 if (type == TGSI_TYPE_DOUBLE) {
684 LLVMValueRef value2;
685 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
686 lp_build_const_int32(gallivm, swizzle + 1));
687 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
688 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
689 }
690
691 return LLVMBuildBitCast(gallivm->builder, value,
692 tgsi2llvmtype(bld_base, type), "");
693 }
694
695 /**
696 * Store to LDS.
697 *
698 * \param swizzle offset (typically 0..3)
699 * \param dw_addr address in dwords
700 * \param value value to store
701 */
702 static void lds_store(struct lp_build_tgsi_context *bld_base,
703 unsigned swizzle, LLVMValueRef dw_addr,
704 LLVMValueRef value)
705 {
706 struct si_shader_context *ctx = si_shader_context(bld_base);
707 struct gallivm_state *gallivm = bld_base->base.gallivm;
708
709 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
710 lp_build_const_int32(gallivm, swizzle));
711
712 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
713 build_indexed_store(ctx, ctx->lds,
714 dw_addr, value);
715 }
716
717 static LLVMValueRef fetch_input_tcs(
718 struct lp_build_tgsi_context *bld_base,
719 const struct tgsi_full_src_register *reg,
720 enum tgsi_opcode_type type, unsigned swizzle)
721 {
722 struct si_shader_context *ctx = si_shader_context(bld_base);
723 LLVMValueRef dw_addr, stride;
724
725 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
726 dw_addr = get_tcs_in_current_patch_offset(ctx);
727 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
728
729 return lds_load(bld_base, type, swizzle, dw_addr);
730 }
731
732 static LLVMValueRef fetch_output_tcs(
733 struct lp_build_tgsi_context *bld_base,
734 const struct tgsi_full_src_register *reg,
735 enum tgsi_opcode_type type, unsigned swizzle)
736 {
737 struct si_shader_context *ctx = si_shader_context(bld_base);
738 LLVMValueRef dw_addr, stride;
739
740 if (reg->Register.Dimension) {
741 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
742 dw_addr = get_tcs_out_current_patch_offset(ctx);
743 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
744 } else {
745 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
746 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
747 }
748
749 return lds_load(bld_base, type, swizzle, dw_addr);
750 }
751
752 static LLVMValueRef fetch_input_tes(
753 struct lp_build_tgsi_context *bld_base,
754 const struct tgsi_full_src_register *reg,
755 enum tgsi_opcode_type type, unsigned swizzle)
756 {
757 struct si_shader_context *ctx = si_shader_context(bld_base);
758 LLVMValueRef dw_addr, stride;
759
760 if (reg->Register.Dimension) {
761 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
762 dw_addr = get_tcs_out_current_patch_offset(ctx);
763 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
764 } else {
765 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
766 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
767 }
768
769 return lds_load(bld_base, type, swizzle, dw_addr);
770 }
771
772 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
773 const struct tgsi_full_instruction *inst,
774 const struct tgsi_opcode_info *info,
775 LLVMValueRef dst[4])
776 {
777 struct si_shader_context *ctx = si_shader_context(bld_base);
778 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
779 unsigned chan_index;
780 LLVMValueRef dw_addr, stride;
781
782 /* Only handle per-patch and per-vertex outputs here.
783 * Vectors will be lowered to scalars and this function will be called again.
784 */
785 if (reg->Register.File != TGSI_FILE_OUTPUT ||
786 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
787 radeon_llvm_emit_store(bld_base, inst, info, dst);
788 return;
789 }
790
791 if (reg->Register.Dimension) {
792 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
793 dw_addr = get_tcs_out_current_patch_offset(ctx);
794 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
795 } else {
796 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
797 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
798 }
799
800 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
801 LLVMValueRef value = dst[chan_index];
802
803 if (inst->Instruction.Saturate)
804 value = radeon_llvm_saturate(bld_base, value);
805
806 lds_store(bld_base, chan_index, dw_addr, value);
807 }
808 }
809
810 static LLVMValueRef fetch_input_gs(
811 struct lp_build_tgsi_context *bld_base,
812 const struct tgsi_full_src_register *reg,
813 enum tgsi_opcode_type type,
814 unsigned swizzle)
815 {
816 struct lp_build_context *base = &bld_base->base;
817 struct si_shader_context *ctx = si_shader_context(bld_base);
818 struct si_shader *shader = ctx->shader;
819 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
820 struct gallivm_state *gallivm = base->gallivm;
821 LLVMValueRef vtx_offset;
822 LLVMValueRef args[9];
823 unsigned vtx_offset_param;
824 struct tgsi_shader_info *info = &shader->selector->info;
825 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
826 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
827 unsigned param;
828 LLVMValueRef value;
829
830 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
831 return get_primitive_id(bld_base, swizzle);
832
833 if (!reg->Register.Dimension)
834 return NULL;
835
836 if (swizzle == ~0) {
837 LLVMValueRef values[TGSI_NUM_CHANNELS];
838 unsigned chan;
839 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
840 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
841 }
842 return lp_build_gather_values(bld_base->base.gallivm, values,
843 TGSI_NUM_CHANNELS);
844 }
845
846 /* Get the vertex offset parameter */
847 vtx_offset_param = reg->Dimension.Index;
848 if (vtx_offset_param < 2) {
849 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
850 } else {
851 assert(vtx_offset_param < 6);
852 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
853 }
854 vtx_offset = lp_build_mul_imm(uint,
855 LLVMGetParam(ctx->radeon_bld.main_fn,
856 vtx_offset_param),
857 4);
858
859 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
860 args[0] = ctx->esgs_ring;
861 args[1] = vtx_offset;
862 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
863 args[3] = uint->zero;
864 args[4] = uint->one; /* OFFEN */
865 args[5] = uint->zero; /* IDXEN */
866 args[6] = uint->one; /* GLC */
867 args[7] = uint->zero; /* SLC */
868 args[8] = uint->zero; /* TFE */
869
870 value = lp_build_intrinsic(gallivm->builder,
871 "llvm.SI.buffer.load.dword.i32.i32",
872 ctx->i32, args, 9,
873 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
874 if (type == TGSI_TYPE_DOUBLE) {
875 LLVMValueRef value2;
876 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
877 value2 = lp_build_intrinsic(gallivm->builder,
878 "llvm.SI.buffer.load.dword.i32.i32",
879 ctx->i32, args, 9,
880 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
881 return radeon_llvm_emit_fetch_double(bld_base,
882 value, value2);
883 }
884 return LLVMBuildBitCast(gallivm->builder,
885 value,
886 tgsi2llvmtype(bld_base, type), "");
887 }
888
889 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
890 {
891 switch (interpolate) {
892 case TGSI_INTERPOLATE_CONSTANT:
893 return 0;
894
895 case TGSI_INTERPOLATE_LINEAR:
896 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
897 return SI_PARAM_LINEAR_SAMPLE;
898 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
899 return SI_PARAM_LINEAR_CENTROID;
900 else
901 return SI_PARAM_LINEAR_CENTER;
902 break;
903 case TGSI_INTERPOLATE_COLOR:
904 case TGSI_INTERPOLATE_PERSPECTIVE:
905 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
906 return SI_PARAM_PERSP_SAMPLE;
907 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
908 return SI_PARAM_PERSP_CENTROID;
909 else
910 return SI_PARAM_PERSP_CENTER;
911 break;
912 default:
913 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
914 return -1;
915 }
916 }
917
918 /* This shouldn't be used by explicit INTERP opcodes. */
919 static unsigned select_interp_param(struct si_shader_context *ctx,
920 unsigned param)
921 {
922 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
923 !ctx->is_monolithic)
924 return param;
925
926 /* If the shader doesn't use center/centroid, just return the parameter.
927 *
928 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
929 * switch between center/centroid and sample without shader changes.
930 */
931 switch (param) {
932 case SI_PARAM_PERSP_CENTROID:
933 case SI_PARAM_PERSP_CENTER:
934 return SI_PARAM_PERSP_SAMPLE;
935
936 case SI_PARAM_LINEAR_CENTROID:
937 case SI_PARAM_LINEAR_CENTER:
938 return SI_PARAM_LINEAR_SAMPLE;
939
940 default:
941 return param;
942 }
943 }
944
945 /**
946 * Interpolate a fragment shader input.
947 *
948 * @param ctx context
949 * @param input_index index of the input in hardware
950 * @param semantic_name TGSI_SEMANTIC_*
951 * @param semantic_index semantic index
952 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
953 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
954 * @param interp_param interpolation weights (i,j)
955 * @param prim_mask SI_PARAM_PRIM_MASK
956 * @param face SI_PARAM_FRONT_FACE
957 * @param result the return value (4 components)
958 */
959 static void interp_fs_input(struct si_shader_context *ctx,
960 unsigned input_index,
961 unsigned semantic_name,
962 unsigned semantic_index,
963 unsigned num_interp_inputs,
964 unsigned colors_read_mask,
965 LLVMValueRef interp_param,
966 LLVMValueRef prim_mask,
967 LLVMValueRef face,
968 LLVMValueRef result[4])
969 {
970 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
971 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
972 struct gallivm_state *gallivm = base->gallivm;
973 const char *intr_name;
974 LLVMValueRef attr_number;
975
976 unsigned chan;
977
978 attr_number = lp_build_const_int32(gallivm, input_index);
979
980 /* fs.constant returns the param from the middle vertex, so it's not
981 * really useful for flat shading. It's meant to be used for custom
982 * interpolation (but the intrinsic can't fetch from the other two
983 * vertices).
984 *
985 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
986 * to do the right thing. The only reason we use fs.constant is that
987 * fs.interp cannot be used on integers, because they can be equal
988 * to NaN.
989 */
990 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
991
992 if (semantic_name == TGSI_SEMANTIC_COLOR &&
993 ctx->shader->key.ps.prolog.color_two_side) {
994 LLVMValueRef args[4];
995 LLVMValueRef is_face_positive;
996 LLVMValueRef back_attr_number;
997
998 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
999 * otherwise it's at offset "num_inputs".
1000 */
1001 unsigned back_attr_offset = num_interp_inputs;
1002 if (semantic_index == 1 && colors_read_mask & 0xf)
1003 back_attr_offset += 1;
1004
1005 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1006
1007 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1008 face, uint->zero, "");
1009
1010 args[2] = prim_mask;
1011 args[3] = interp_param;
1012 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1013 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1014 LLVMValueRef front, back;
1015
1016 args[0] = llvm_chan;
1017 args[1] = attr_number;
1018 front = lp_build_intrinsic(gallivm->builder, intr_name,
1019 ctx->f32, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021
1022 args[1] = back_attr_number;
1023 back = lp_build_intrinsic(gallivm->builder, intr_name,
1024 ctx->f32, args, args[3] ? 4 : 3,
1025 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1026
1027 result[chan] = LLVMBuildSelect(gallivm->builder,
1028 is_face_positive,
1029 front,
1030 back,
1031 "");
1032 }
1033 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1034 LLVMValueRef args[4];
1035
1036 args[0] = uint->zero;
1037 args[1] = attr_number;
1038 args[2] = prim_mask;
1039 args[3] = interp_param;
1040 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1041 ctx->f32, args, args[3] ? 4 : 3,
1042 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1043 result[1] =
1044 result[2] = lp_build_const_float(gallivm, 0.0f);
1045 result[3] = lp_build_const_float(gallivm, 1.0f);
1046 } else {
1047 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1048 LLVMValueRef args[4];
1049 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1050
1051 args[0] = llvm_chan;
1052 args[1] = attr_number;
1053 args[2] = prim_mask;
1054 args[3] = interp_param;
1055 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1056 ctx->f32, args, args[3] ? 4 : 3,
1057 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1058 }
1059 }
1060 }
1061
1062 static void declare_input_fs(
1063 struct radeon_llvm_context *radeon_bld,
1064 unsigned input_index,
1065 const struct tgsi_full_declaration *decl)
1066 {
1067 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1068 struct si_shader_context *ctx =
1069 si_shader_context(&radeon_bld->soa.bld_base);
1070 struct si_shader *shader = ctx->shader;
1071 LLVMValueRef main_fn = radeon_bld->main_fn;
1072 LLVMValueRef interp_param = NULL;
1073 int interp_param_idx;
1074
1075 /* Get colors from input VGPRs (set by the prolog). */
1076 if (!ctx->is_monolithic &&
1077 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1078 unsigned i = decl->Semantic.Index;
1079 unsigned colors_read = shader->selector->info.colors_read;
1080 unsigned mask = colors_read >> (i * 4);
1081 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1082 (i ? util_bitcount(colors_read & 0xf) : 0);
1083
1084 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1085 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1086 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1087 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1088 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1089 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1090 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1091 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1092 return;
1093 }
1094
1095 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1096 decl->Interp.Location);
1097 if (interp_param_idx == -1)
1098 return;
1099 else if (interp_param_idx) {
1100 interp_param_idx = select_interp_param(ctx,
1101 interp_param_idx);
1102 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1103 }
1104
1105 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1106 decl->Semantic.Index, shader->selector->info.num_inputs,
1107 shader->selector->info.colors_read, interp_param,
1108 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1109 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1110 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1111 }
1112
1113 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1114 {
1115 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1116 SI_PARAM_ANCILLARY, 8, 4);
1117 }
1118
1119 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1120 {
1121 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1122
1123 return lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
1124 NULL, 0, LLVMReadNoneAttribute);
1125 }
1126
1127 /**
1128 * Load a dword from a constant buffer.
1129 */
1130 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1131 LLVMValueRef offset, LLVMTypeRef return_type)
1132 {
1133 LLVMValueRef args[2] = {resource, offset};
1134
1135 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1136 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1137 }
1138
1139 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1140 {
1141 struct si_shader_context *ctx =
1142 si_shader_context(&radeon_bld->soa.bld_base);
1143 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1144 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1145 LLVMBuilderRef builder = gallivm->builder;
1146 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1147 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1148 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1149
1150 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1151 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1152 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1153
1154 LLVMValueRef pos[4] = {
1155 buffer_load_const(builder, resource, offset0, ctx->f32),
1156 buffer_load_const(builder, resource, offset1, ctx->f32),
1157 lp_build_const_float(gallivm, 0),
1158 lp_build_const_float(gallivm, 0)
1159 };
1160
1161 return lp_build_gather_values(gallivm, pos, 4);
1162 }
1163
1164 static void declare_system_value(
1165 struct radeon_llvm_context *radeon_bld,
1166 unsigned index,
1167 const struct tgsi_full_declaration *decl)
1168 {
1169 struct si_shader_context *ctx =
1170 si_shader_context(&radeon_bld->soa.bld_base);
1171 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1172 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1173 LLVMValueRef value = 0;
1174
1175 switch (decl->Semantic.Name) {
1176 case TGSI_SEMANTIC_INSTANCEID:
1177 value = LLVMGetParam(radeon_bld->main_fn,
1178 ctx->param_instance_id);
1179 break;
1180
1181 case TGSI_SEMANTIC_VERTEXID:
1182 value = LLVMBuildAdd(gallivm->builder,
1183 LLVMGetParam(radeon_bld->main_fn,
1184 ctx->param_vertex_id),
1185 LLVMGetParam(radeon_bld->main_fn,
1186 SI_PARAM_BASE_VERTEX), "");
1187 break;
1188
1189 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1190 value = LLVMGetParam(radeon_bld->main_fn,
1191 ctx->param_vertex_id);
1192 break;
1193
1194 case TGSI_SEMANTIC_BASEVERTEX:
1195 value = LLVMGetParam(radeon_bld->main_fn,
1196 SI_PARAM_BASE_VERTEX);
1197 break;
1198
1199 case TGSI_SEMANTIC_INVOCATIONID:
1200 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1201 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1202 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1203 value = LLVMGetParam(radeon_bld->main_fn,
1204 SI_PARAM_GS_INSTANCE_ID);
1205 else
1206 assert(!"INVOCATIONID not implemented");
1207 break;
1208
1209 case TGSI_SEMANTIC_POSITION:
1210 {
1211 LLVMValueRef pos[4] = {
1212 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1213 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1214 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1215 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1216 LLVMGetParam(radeon_bld->main_fn,
1217 SI_PARAM_POS_W_FLOAT)),
1218 };
1219 value = lp_build_gather_values(gallivm, pos, 4);
1220 break;
1221 }
1222
1223 case TGSI_SEMANTIC_FACE:
1224 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1225 break;
1226
1227 case TGSI_SEMANTIC_SAMPLEID:
1228 value = get_sample_id(radeon_bld);
1229 break;
1230
1231 case TGSI_SEMANTIC_SAMPLEPOS: {
1232 LLVMValueRef pos[4] = {
1233 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1234 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1235 lp_build_const_float(gallivm, 0),
1236 lp_build_const_float(gallivm, 0)
1237 };
1238 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1239 TGSI_OPCODE_FRC, pos[0]);
1240 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1241 TGSI_OPCODE_FRC, pos[1]);
1242 value = lp_build_gather_values(gallivm, pos, 4);
1243 break;
1244 }
1245
1246 case TGSI_SEMANTIC_SAMPLEMASK:
1247 /* This can only occur with the OpenGL Core profile, which
1248 * doesn't support smoothing.
1249 */
1250 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1251 break;
1252
1253 case TGSI_SEMANTIC_TESSCOORD:
1254 {
1255 LLVMValueRef coord[4] = {
1256 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1257 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1258 bld->zero,
1259 bld->zero
1260 };
1261
1262 /* For triangles, the vector should be (u, v, 1-u-v). */
1263 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1264 PIPE_PRIM_TRIANGLES)
1265 coord[2] = lp_build_sub(bld, bld->one,
1266 lp_build_add(bld, coord[0], coord[1]));
1267
1268 value = lp_build_gather_values(gallivm, coord, 4);
1269 break;
1270 }
1271
1272 case TGSI_SEMANTIC_VERTICESIN:
1273 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1274 break;
1275
1276 case TGSI_SEMANTIC_TESSINNER:
1277 case TGSI_SEMANTIC_TESSOUTER:
1278 {
1279 LLVMValueRef dw_addr;
1280 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1281
1282 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1283 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1284 lp_build_const_int32(gallivm, param * 4), "");
1285
1286 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1287 ~0, dw_addr);
1288 break;
1289 }
1290
1291 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1292 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1293 {
1294 LLVMValueRef buf, slot, val[4];
1295 int i, offset;
1296
1297 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1298 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1299 buf = build_indexed_load_const(ctx, buf, slot);
1300 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1301
1302 for (i = 0; i < 4; i++)
1303 val[i] = buffer_load_const(gallivm->builder, buf,
1304 lp_build_const_int32(gallivm, (offset + i) * 4),
1305 ctx->f32);
1306 value = lp_build_gather_values(gallivm, val, 4);
1307 break;
1308 }
1309
1310 case TGSI_SEMANTIC_PRIMID:
1311 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1312 break;
1313
1314 case TGSI_SEMANTIC_GRID_SIZE:
1315 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1316 break;
1317
1318 case TGSI_SEMANTIC_BLOCK_SIZE:
1319 {
1320 LLVMValueRef values[3];
1321 unsigned i;
1322 unsigned *properties = ctx->shader->selector->info.properties;
1323 unsigned sizes[3] = {
1324 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1325 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1326 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1327 };
1328
1329 for (i = 0; i < 3; ++i)
1330 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1331
1332 value = lp_build_gather_values(gallivm, values, 3);
1333 break;
1334 }
1335
1336 case TGSI_SEMANTIC_BLOCK_ID:
1337 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1338 break;
1339
1340 case TGSI_SEMANTIC_THREAD_ID:
1341 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1342 break;
1343
1344 #if HAVE_LLVM >= 0x0309
1345 case TGSI_SEMANTIC_HELPER_INVOCATION:
1346 value = lp_build_intrinsic(gallivm->builder,
1347 "llvm.amdgcn.ps.live",
1348 ctx->i1, NULL, 0,
1349 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1350 value = LLVMBuildNot(gallivm->builder, value, "");
1351 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1352 break;
1353 #endif
1354
1355 default:
1356 assert(!"unknown system value");
1357 return;
1358 }
1359
1360 radeon_bld->system_values[index] = value;
1361 }
1362
1363 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1364 const struct tgsi_full_declaration *decl)
1365 {
1366 struct si_shader_context *ctx =
1367 si_shader_context(&radeon_bld->soa.bld_base);
1368 struct si_shader_selector *sel = ctx->shader->selector;
1369 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1370
1371 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1372 LLVMValueRef var;
1373
1374 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1375 assert(decl->Range.First == decl->Range.Last);
1376 assert(!ctx->shared_memory);
1377
1378 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1379 LLVMArrayType(ctx->i8, sel->local_size),
1380 "compute_lds",
1381 LOCAL_ADDR_SPACE);
1382 LLVMSetAlignment(var, 4);
1383
1384 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1385 }
1386
1387 static LLVMValueRef fetch_constant(
1388 struct lp_build_tgsi_context *bld_base,
1389 const struct tgsi_full_src_register *reg,
1390 enum tgsi_opcode_type type,
1391 unsigned swizzle)
1392 {
1393 struct si_shader_context *ctx = si_shader_context(bld_base);
1394 struct lp_build_context *base = &bld_base->base;
1395 const struct tgsi_ind_register *ireg = &reg->Indirect;
1396 unsigned buf, idx;
1397
1398 LLVMValueRef addr, bufp;
1399 LLVMValueRef result;
1400
1401 if (swizzle == LP_CHAN_ALL) {
1402 unsigned chan;
1403 LLVMValueRef values[4];
1404 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1405 values[chan] = fetch_constant(bld_base, reg, type, chan);
1406
1407 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1408 }
1409
1410 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1411 idx = reg->Register.Index * 4 + swizzle;
1412
1413 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1414 if (type != TGSI_TYPE_DOUBLE)
1415 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1416 else {
1417 return radeon_llvm_emit_fetch_double(bld_base,
1418 ctx->constants[buf][idx],
1419 ctx->constants[buf][idx + 1]);
1420 }
1421 }
1422
1423 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1424 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1425 LLVMValueRef index;
1426 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1427 reg->Dimension.Index,
1428 SI_NUM_CONST_BUFFERS);
1429 bufp = build_indexed_load_const(ctx, ptr, index);
1430 } else
1431 bufp = ctx->const_buffers[buf];
1432
1433 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1434 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1435 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1436 addr = lp_build_add(&bld_base->uint_bld, addr,
1437 lp_build_const_int32(base->gallivm, idx * 4));
1438
1439 result = buffer_load_const(base->gallivm->builder, bufp,
1440 addr, ctx->f32);
1441
1442 if (type != TGSI_TYPE_DOUBLE)
1443 result = bitcast(bld_base, type, result);
1444 else {
1445 LLVMValueRef addr2, result2;
1446 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1447 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1448 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1449 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1450 lp_build_const_int32(base->gallivm, idx * 4));
1451
1452 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1453 addr2, ctx->f32);
1454
1455 result = radeon_llvm_emit_fetch_double(bld_base,
1456 result, result2);
1457 }
1458 return result;
1459 }
1460
1461 /* Upper 16 bits must be zero. */
1462 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1463 LLVMValueRef val[2])
1464 {
1465 return LLVMBuildOr(gallivm->builder, val[0],
1466 LLVMBuildShl(gallivm->builder, val[1],
1467 lp_build_const_int32(gallivm, 16),
1468 ""), "");
1469 }
1470
1471 /* Upper 16 bits are ignored and will be dropped. */
1472 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1473 LLVMValueRef val[2])
1474 {
1475 LLVMValueRef v[2] = {
1476 LLVMBuildAnd(gallivm->builder, val[0],
1477 lp_build_const_int32(gallivm, 0xffff), ""),
1478 val[1],
1479 };
1480 return si_llvm_pack_two_int16(gallivm, v);
1481 }
1482
1483 /* Initialize arguments for the shader export intrinsic */
1484 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1485 LLVMValueRef *values,
1486 unsigned target,
1487 LLVMValueRef *args)
1488 {
1489 struct si_shader_context *ctx = si_shader_context(bld_base);
1490 struct lp_build_context *uint =
1491 &ctx->radeon_bld.soa.bld_base.uint_bld;
1492 struct lp_build_context *base = &bld_base->base;
1493 struct gallivm_state *gallivm = base->gallivm;
1494 LLVMBuilderRef builder = base->gallivm->builder;
1495 LLVMValueRef val[4];
1496 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1497 unsigned chan;
1498 bool is_int8;
1499
1500 /* Default is 0xf. Adjusted below depending on the format. */
1501 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1502
1503 /* Specify whether the EXEC mask represents the valid mask */
1504 args[1] = uint->zero;
1505
1506 /* Specify whether this is the last export */
1507 args[2] = uint->zero;
1508
1509 /* Specify the target we are exporting */
1510 args[3] = lp_build_const_int32(base->gallivm, target);
1511
1512 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1513 const union si_shader_key *key = &ctx->shader->key;
1514 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1515 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1516
1517 assert(cbuf >= 0 && cbuf < 8);
1518 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1519 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1520 }
1521
1522 args[4] = uint->zero; /* COMPR flag */
1523 args[5] = base->undef;
1524 args[6] = base->undef;
1525 args[7] = base->undef;
1526 args[8] = base->undef;
1527
1528 switch (spi_shader_col_format) {
1529 case V_028714_SPI_SHADER_ZERO:
1530 args[0] = uint->zero; /* writemask */
1531 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1532 break;
1533
1534 case V_028714_SPI_SHADER_32_R:
1535 args[0] = uint->one; /* writemask */
1536 args[5] = values[0];
1537 break;
1538
1539 case V_028714_SPI_SHADER_32_GR:
1540 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1541 args[5] = values[0];
1542 args[6] = values[1];
1543 break;
1544
1545 case V_028714_SPI_SHADER_32_AR:
1546 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1547 args[5] = values[0];
1548 args[8] = values[3];
1549 break;
1550
1551 case V_028714_SPI_SHADER_FP16_ABGR:
1552 args[4] = uint->one; /* COMPR flag */
1553
1554 for (chan = 0; chan < 2; chan++) {
1555 LLVMValueRef pack_args[2] = {
1556 values[2 * chan],
1557 values[2 * chan + 1]
1558 };
1559 LLVMValueRef packed;
1560
1561 packed = lp_build_intrinsic(base->gallivm->builder,
1562 "llvm.SI.packf16",
1563 ctx->i32, pack_args, 2,
1564 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1565 args[chan + 5] =
1566 LLVMBuildBitCast(base->gallivm->builder,
1567 packed, ctx->f32, "");
1568 }
1569 break;
1570
1571 case V_028714_SPI_SHADER_UNORM16_ABGR:
1572 for (chan = 0; chan < 4; chan++) {
1573 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1574 val[chan] = LLVMBuildFMul(builder, val[chan],
1575 lp_build_const_float(gallivm, 65535), "");
1576 val[chan] = LLVMBuildFAdd(builder, val[chan],
1577 lp_build_const_float(gallivm, 0.5), "");
1578 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1579 ctx->i32, "");
1580 }
1581
1582 args[4] = uint->one; /* COMPR flag */
1583 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1584 si_llvm_pack_two_int16(gallivm, val));
1585 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1586 si_llvm_pack_two_int16(gallivm, val+2));
1587 break;
1588
1589 case V_028714_SPI_SHADER_SNORM16_ABGR:
1590 for (chan = 0; chan < 4; chan++) {
1591 /* Clamp between [-1, 1]. */
1592 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1593 values[chan],
1594 lp_build_const_float(gallivm, 1));
1595 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1596 val[chan],
1597 lp_build_const_float(gallivm, -1));
1598 /* Convert to a signed integer in [-32767, 32767]. */
1599 val[chan] = LLVMBuildFMul(builder, val[chan],
1600 lp_build_const_float(gallivm, 32767), "");
1601 /* If positive, add 0.5, else add -0.5. */
1602 val[chan] = LLVMBuildFAdd(builder, val[chan],
1603 LLVMBuildSelect(builder,
1604 LLVMBuildFCmp(builder, LLVMRealOGE,
1605 val[chan], base->zero, ""),
1606 lp_build_const_float(gallivm, 0.5),
1607 lp_build_const_float(gallivm, -0.5), ""), "");
1608 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1609 }
1610
1611 args[4] = uint->one; /* COMPR flag */
1612 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1613 si_llvm_pack_two_int32_as_int16(gallivm, val));
1614 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1615 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1616 break;
1617
1618 case V_028714_SPI_SHADER_UINT16_ABGR: {
1619 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1620 255 : 65535);
1621 /* Clamp. */
1622 for (chan = 0; chan < 4; chan++) {
1623 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1624 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1625 val[chan], max);
1626 }
1627
1628 args[4] = uint->one; /* COMPR flag */
1629 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1630 si_llvm_pack_two_int16(gallivm, val));
1631 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1632 si_llvm_pack_two_int16(gallivm, val+2));
1633 break;
1634 }
1635
1636 case V_028714_SPI_SHADER_SINT16_ABGR: {
1637 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1638 127 : 32767);
1639 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1640 -128 : -32768);
1641 /* Clamp. */
1642 for (chan = 0; chan < 4; chan++) {
1643 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1644 val[chan] = lp_build_emit_llvm_binary(bld_base,
1645 TGSI_OPCODE_IMIN,
1646 val[chan], max);
1647 val[chan] = lp_build_emit_llvm_binary(bld_base,
1648 TGSI_OPCODE_IMAX,
1649 val[chan], min);
1650 }
1651
1652 args[4] = uint->one; /* COMPR flag */
1653 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1654 si_llvm_pack_two_int32_as_int16(gallivm, val));
1655 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1656 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1657 break;
1658 }
1659
1660 case V_028714_SPI_SHADER_32_ABGR:
1661 memcpy(&args[5], values, sizeof(values[0]) * 4);
1662 break;
1663 }
1664 }
1665
1666 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1667 LLVMValueRef alpha)
1668 {
1669 struct si_shader_context *ctx = si_shader_context(bld_base);
1670 struct gallivm_state *gallivm = bld_base->base.gallivm;
1671
1672 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1673 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1674 SI_PARAM_ALPHA_REF);
1675
1676 LLVMValueRef alpha_pass =
1677 lp_build_cmp(&bld_base->base,
1678 ctx->shader->key.ps.epilog.alpha_func,
1679 alpha, alpha_ref);
1680 LLVMValueRef arg =
1681 lp_build_select(&bld_base->base,
1682 alpha_pass,
1683 lp_build_const_float(gallivm, 1.0f),
1684 lp_build_const_float(gallivm, -1.0f));
1685
1686 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1687 ctx->voidt, &arg, 1, 0);
1688 } else {
1689 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1690 ctx->voidt, NULL, 0, 0);
1691 }
1692 }
1693
1694 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1695 LLVMValueRef alpha,
1696 unsigned samplemask_param)
1697 {
1698 struct si_shader_context *ctx = si_shader_context(bld_base);
1699 struct gallivm_state *gallivm = bld_base->base.gallivm;
1700 LLVMValueRef coverage;
1701
1702 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1703 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1704 samplemask_param);
1705 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1706
1707 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1708 ctx->i32,
1709 &coverage, 1, LLVMReadNoneAttribute);
1710
1711 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1712 ctx->f32, "");
1713
1714 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1715 lp_build_const_float(gallivm,
1716 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1717
1718 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1719 }
1720
1721 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1722 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1723 {
1724 struct si_shader_context *ctx = si_shader_context(bld_base);
1725 struct lp_build_context *base = &bld_base->base;
1726 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1727 unsigned reg_index;
1728 unsigned chan;
1729 unsigned const_chan;
1730 LLVMValueRef base_elt;
1731 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1732 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
1733 SI_VS_CONST_CLIP_PLANES);
1734 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1735
1736 for (reg_index = 0; reg_index < 2; reg_index ++) {
1737 LLVMValueRef *args = pos[2 + reg_index];
1738
1739 args[5] =
1740 args[6] =
1741 args[7] =
1742 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1743
1744 /* Compute dot products of position and user clip plane vectors */
1745 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1746 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1747 args[1] = lp_build_const_int32(base->gallivm,
1748 ((reg_index * 4 + chan) * 4 +
1749 const_chan) * 4);
1750 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1751 args[1], ctx->f32);
1752 args[5 + chan] =
1753 lp_build_add(base, args[5 + chan],
1754 lp_build_mul(base, base_elt,
1755 out_elts[const_chan]));
1756 }
1757 }
1758
1759 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1760 args[1] = uint->zero;
1761 args[2] = uint->zero;
1762 args[3] = lp_build_const_int32(base->gallivm,
1763 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1764 args[4] = uint->zero;
1765 }
1766 }
1767
1768 static void si_dump_streamout(struct pipe_stream_output_info *so)
1769 {
1770 unsigned i;
1771
1772 if (so->num_outputs)
1773 fprintf(stderr, "STREAMOUT\n");
1774
1775 for (i = 0; i < so->num_outputs; i++) {
1776 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1777 so->output[i].start_component;
1778 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1779 i, so->output[i].output_buffer,
1780 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1781 so->output[i].register_index,
1782 mask & 1 ? "x" : "",
1783 mask & 2 ? "y" : "",
1784 mask & 4 ? "z" : "",
1785 mask & 8 ? "w" : "");
1786 }
1787 }
1788
1789 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1790 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1791 * or v4i32 (num_channels=3,4). */
1792 static void build_tbuffer_store(struct si_shader_context *ctx,
1793 LLVMValueRef rsrc,
1794 LLVMValueRef vdata,
1795 unsigned num_channels,
1796 LLVMValueRef vaddr,
1797 LLVMValueRef soffset,
1798 unsigned inst_offset,
1799 unsigned dfmt,
1800 unsigned nfmt,
1801 unsigned offen,
1802 unsigned idxen,
1803 unsigned glc,
1804 unsigned slc,
1805 unsigned tfe)
1806 {
1807 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1808 LLVMValueRef args[] = {
1809 rsrc,
1810 vdata,
1811 LLVMConstInt(ctx->i32, num_channels, 0),
1812 vaddr,
1813 soffset,
1814 LLVMConstInt(ctx->i32, inst_offset, 0),
1815 LLVMConstInt(ctx->i32, dfmt, 0),
1816 LLVMConstInt(ctx->i32, nfmt, 0),
1817 LLVMConstInt(ctx->i32, offen, 0),
1818 LLVMConstInt(ctx->i32, idxen, 0),
1819 LLVMConstInt(ctx->i32, glc, 0),
1820 LLVMConstInt(ctx->i32, slc, 0),
1821 LLVMConstInt(ctx->i32, tfe, 0)
1822 };
1823
1824 /* The instruction offset field has 12 bits */
1825 assert(offen || inst_offset < (1 << 12));
1826
1827 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1828 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1829 const char *types[] = {"i32", "v2i32", "v4i32"};
1830 char name[256];
1831 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1832
1833 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1834 args, Elements(args), 0);
1835 }
1836
1837 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1838 LLVMValueRef rsrc,
1839 LLVMValueRef vdata,
1840 unsigned num_channels,
1841 LLVMValueRef vaddr,
1842 LLVMValueRef soffset,
1843 unsigned inst_offset)
1844 {
1845 static unsigned dfmt[] = {
1846 V_008F0C_BUF_DATA_FORMAT_32,
1847 V_008F0C_BUF_DATA_FORMAT_32_32,
1848 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1849 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1850 };
1851 assert(num_channels >= 1 && num_channels <= 4);
1852
1853 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1854 inst_offset, dfmt[num_channels-1],
1855 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1856 }
1857
1858 /* On SI, the vertex shader is responsible for writing streamout data
1859 * to buffers. */
1860 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1861 struct si_shader_output_values *outputs,
1862 unsigned noutput)
1863 {
1864 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1865 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1866 LLVMBuilderRef builder = gallivm->builder;
1867 int i, j;
1868 struct lp_build_if_state if_ctx;
1869
1870 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1871 LLVMValueRef so_vtx_count =
1872 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1873
1874 LLVMValueRef tid = get_thread_id(ctx);
1875
1876 /* can_emit = tid < so_vtx_count; */
1877 LLVMValueRef can_emit =
1878 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1879
1880 LLVMValueRef stream_id =
1881 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1882
1883 /* Emit the streamout code conditionally. This actually avoids
1884 * out-of-bounds buffer access. The hw tells us via the SGPR
1885 * (so_vtx_count) which threads are allowed to emit streamout data. */
1886 lp_build_if(&if_ctx, gallivm, can_emit);
1887 {
1888 /* The buffer offset is computed as follows:
1889 * ByteOffset = streamout_offset[buffer_id]*4 +
1890 * (streamout_write_index + thread_id)*stride[buffer_id] +
1891 * attrib_offset
1892 */
1893
1894 LLVMValueRef so_write_index =
1895 LLVMGetParam(ctx->radeon_bld.main_fn,
1896 ctx->param_streamout_write_index);
1897
1898 /* Compute (streamout_write_index + thread_id). */
1899 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1900
1901 /* Compute the write offset for each enabled buffer. */
1902 LLVMValueRef so_write_offset[4] = {};
1903 for (i = 0; i < 4; i++) {
1904 if (!so->stride[i])
1905 continue;
1906
1907 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1908 ctx->param_streamout_offset[i]);
1909 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1910
1911 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1912 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1913 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1914 }
1915
1916 /* Write streamout data. */
1917 for (i = 0; i < so->num_outputs; i++) {
1918 unsigned buf_idx = so->output[i].output_buffer;
1919 unsigned reg = so->output[i].register_index;
1920 unsigned start = so->output[i].start_component;
1921 unsigned num_comps = so->output[i].num_components;
1922 unsigned stream = so->output[i].stream;
1923 LLVMValueRef out[4];
1924 struct lp_build_if_state if_ctx_stream;
1925
1926 assert(num_comps && num_comps <= 4);
1927 if (!num_comps || num_comps > 4)
1928 continue;
1929
1930 if (reg >= noutput)
1931 continue;
1932
1933 /* Load the output as int. */
1934 for (j = 0; j < num_comps; j++) {
1935 out[j] = LLVMBuildBitCast(builder,
1936 outputs[reg].values[start+j],
1937 ctx->i32, "");
1938 }
1939
1940 /* Pack the output. */
1941 LLVMValueRef vdata = NULL;
1942
1943 switch (num_comps) {
1944 case 1: /* as i32 */
1945 vdata = out[0];
1946 break;
1947 case 2: /* as v2i32 */
1948 case 3: /* as v4i32 (aligned to 4) */
1949 case 4: /* as v4i32 */
1950 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1951 for (j = 0; j < num_comps; j++) {
1952 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1953 LLVMConstInt(ctx->i32, j, 0), "");
1954 }
1955 break;
1956 }
1957
1958 LLVMValueRef can_emit_stream =
1959 LLVMBuildICmp(builder, LLVMIntEQ,
1960 stream_id,
1961 lp_build_const_int32(gallivm, stream), "");
1962
1963 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1964 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1965 vdata, num_comps,
1966 so_write_offset[buf_idx],
1967 LLVMConstInt(ctx->i32, 0, 0),
1968 so->output[i].dst_offset*4);
1969 lp_build_endif(&if_ctx_stream);
1970 }
1971 }
1972 lp_build_endif(&if_ctx);
1973 }
1974
1975
1976 /* Generate export instructions for hardware VS shader stage */
1977 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1978 struct si_shader_output_values *outputs,
1979 unsigned noutput)
1980 {
1981 struct si_shader_context *ctx = si_shader_context(bld_base);
1982 struct si_shader *shader = ctx->shader;
1983 struct lp_build_context *base = &bld_base->base;
1984 struct lp_build_context *uint =
1985 &ctx->radeon_bld.soa.bld_base.uint_bld;
1986 LLVMValueRef args[9];
1987 LLVMValueRef pos_args[4][9] = { { 0 } };
1988 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1989 unsigned semantic_name, semantic_index;
1990 unsigned target;
1991 unsigned param_count = 0;
1992 unsigned pos_idx;
1993 int i;
1994
1995 if (outputs && ctx->shader->selector->so.num_outputs) {
1996 si_llvm_emit_streamout(ctx, outputs, noutput);
1997 }
1998
1999 for (i = 0; i < noutput; i++) {
2000 semantic_name = outputs[i].name;
2001 semantic_index = outputs[i].sid;
2002
2003 handle_semantic:
2004 /* Select the correct target */
2005 switch(semantic_name) {
2006 case TGSI_SEMANTIC_PSIZE:
2007 psize_value = outputs[i].values[0];
2008 continue;
2009 case TGSI_SEMANTIC_EDGEFLAG:
2010 edgeflag_value = outputs[i].values[0];
2011 continue;
2012 case TGSI_SEMANTIC_LAYER:
2013 layer_value = outputs[i].values[0];
2014 semantic_name = TGSI_SEMANTIC_GENERIC;
2015 goto handle_semantic;
2016 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2017 viewport_index_value = outputs[i].values[0];
2018 semantic_name = TGSI_SEMANTIC_GENERIC;
2019 goto handle_semantic;
2020 case TGSI_SEMANTIC_POSITION:
2021 target = V_008DFC_SQ_EXP_POS;
2022 break;
2023 case TGSI_SEMANTIC_COLOR:
2024 case TGSI_SEMANTIC_BCOLOR:
2025 target = V_008DFC_SQ_EXP_PARAM + param_count;
2026 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2027 shader->info.vs_output_param_offset[i] = param_count;
2028 param_count++;
2029 break;
2030 case TGSI_SEMANTIC_CLIPDIST:
2031 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2032 break;
2033 case TGSI_SEMANTIC_CLIPVERTEX:
2034 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2035 continue;
2036 case TGSI_SEMANTIC_PRIMID:
2037 case TGSI_SEMANTIC_FOG:
2038 case TGSI_SEMANTIC_TEXCOORD:
2039 case TGSI_SEMANTIC_GENERIC:
2040 target = V_008DFC_SQ_EXP_PARAM + param_count;
2041 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2042 shader->info.vs_output_param_offset[i] = param_count;
2043 param_count++;
2044 break;
2045 default:
2046 target = 0;
2047 fprintf(stderr,
2048 "Warning: SI unhandled vs output type:%d\n",
2049 semantic_name);
2050 }
2051
2052 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2053
2054 if (target >= V_008DFC_SQ_EXP_POS &&
2055 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2056 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2057 args, sizeof(args));
2058 } else {
2059 lp_build_intrinsic(base->gallivm->builder,
2060 "llvm.SI.export", ctx->voidt,
2061 args, 9, 0);
2062 }
2063
2064 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2065 semantic_name = TGSI_SEMANTIC_GENERIC;
2066 goto handle_semantic;
2067 }
2068 }
2069
2070 shader->info.nr_param_exports = param_count;
2071
2072 /* We need to add the position output manually if it's missing. */
2073 if (!pos_args[0][0]) {
2074 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2075 pos_args[0][1] = uint->zero; /* EXEC mask */
2076 pos_args[0][2] = uint->zero; /* last export? */
2077 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2078 pos_args[0][4] = uint->zero; /* COMPR flag */
2079 pos_args[0][5] = base->zero; /* X */
2080 pos_args[0][6] = base->zero; /* Y */
2081 pos_args[0][7] = base->zero; /* Z */
2082 pos_args[0][8] = base->one; /* W */
2083 }
2084
2085 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2086 if (shader->selector->info.writes_psize ||
2087 shader->selector->info.writes_edgeflag ||
2088 shader->selector->info.writes_viewport_index ||
2089 shader->selector->info.writes_layer) {
2090 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2091 shader->selector->info.writes_psize |
2092 (shader->selector->info.writes_edgeflag << 1) |
2093 (shader->selector->info.writes_layer << 2) |
2094 (shader->selector->info.writes_viewport_index << 3));
2095 pos_args[1][1] = uint->zero; /* EXEC mask */
2096 pos_args[1][2] = uint->zero; /* last export? */
2097 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2098 pos_args[1][4] = uint->zero; /* COMPR flag */
2099 pos_args[1][5] = base->zero; /* X */
2100 pos_args[1][6] = base->zero; /* Y */
2101 pos_args[1][7] = base->zero; /* Z */
2102 pos_args[1][8] = base->zero; /* W */
2103
2104 if (shader->selector->info.writes_psize)
2105 pos_args[1][5] = psize_value;
2106
2107 if (shader->selector->info.writes_edgeflag) {
2108 /* The output is a float, but the hw expects an integer
2109 * with the first bit containing the edge flag. */
2110 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2111 edgeflag_value,
2112 ctx->i32, "");
2113 edgeflag_value = lp_build_min(&bld_base->int_bld,
2114 edgeflag_value,
2115 bld_base->int_bld.one);
2116
2117 /* The LLVM intrinsic expects a float. */
2118 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2119 edgeflag_value,
2120 ctx->f32, "");
2121 }
2122
2123 if (shader->selector->info.writes_layer)
2124 pos_args[1][7] = layer_value;
2125
2126 if (shader->selector->info.writes_viewport_index)
2127 pos_args[1][8] = viewport_index_value;
2128 }
2129
2130 for (i = 0; i < 4; i++)
2131 if (pos_args[i][0])
2132 shader->info.nr_pos_exports++;
2133
2134 pos_idx = 0;
2135 for (i = 0; i < 4; i++) {
2136 if (!pos_args[i][0])
2137 continue;
2138
2139 /* Specify the target we are exporting */
2140 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2141
2142 if (pos_idx == shader->info.nr_pos_exports)
2143 /* Specify that this is the last export */
2144 pos_args[i][2] = uint->one;
2145
2146 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2147 ctx->voidt, pos_args[i], 9, 0);
2148 }
2149 }
2150
2151 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2152 LLVMValueRef rel_patch_id,
2153 LLVMValueRef invocation_id,
2154 LLVMValueRef tcs_out_current_patch_data_offset)
2155 {
2156 struct si_shader_context *ctx = si_shader_context(bld_base);
2157 struct gallivm_state *gallivm = bld_base->base.gallivm;
2158 struct si_shader *shader = ctx->shader;
2159 unsigned tess_inner_index, tess_outer_index;
2160 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2161 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2162 unsigned stride, outer_comps, inner_comps, i;
2163 struct lp_build_if_state if_ctx;
2164
2165 /* Do this only for invocation 0, because the tess levels are per-patch,
2166 * not per-vertex.
2167 *
2168 * This can't jump, because invocation 0 executes this. It should
2169 * at least mask out the loads and stores for other invocations.
2170 */
2171 lp_build_if(&if_ctx, gallivm,
2172 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2173 invocation_id, bld_base->uint_bld.zero, ""));
2174
2175 /* Determine the layout of one tess factor element in the buffer. */
2176 switch (shader->key.tcs.epilog.prim_mode) {
2177 case PIPE_PRIM_LINES:
2178 stride = 2; /* 2 dwords, 1 vec2 store */
2179 outer_comps = 2;
2180 inner_comps = 0;
2181 break;
2182 case PIPE_PRIM_TRIANGLES:
2183 stride = 4; /* 4 dwords, 1 vec4 store */
2184 outer_comps = 3;
2185 inner_comps = 1;
2186 break;
2187 case PIPE_PRIM_QUADS:
2188 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2189 outer_comps = 4;
2190 inner_comps = 2;
2191 break;
2192 default:
2193 assert(0);
2194 return;
2195 }
2196
2197 /* Load tess_inner and tess_outer from LDS.
2198 * Any invocation can write them, so we can't get them from a temporary.
2199 */
2200 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2201 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2202
2203 lds_base = tcs_out_current_patch_data_offset;
2204 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2205 lp_build_const_int32(gallivm,
2206 tess_inner_index * 4), "");
2207 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2208 lp_build_const_int32(gallivm,
2209 tess_outer_index * 4), "");
2210
2211 for (i = 0; i < outer_comps; i++)
2212 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2213 for (i = 0; i < inner_comps; i++)
2214 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2215
2216 /* Convert the outputs to vectors for stores. */
2217 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2218 vec1 = NULL;
2219
2220 if (stride > 4)
2221 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2222
2223 /* Get the buffer. */
2224 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2225 SI_PARAM_RW_BUFFERS);
2226 buffer = build_indexed_load_const(ctx, rw_buffers,
2227 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2228
2229 /* Get the offset. */
2230 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2231 SI_PARAM_TESS_FACTOR_OFFSET);
2232 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2233 lp_build_const_int32(gallivm, 4 * stride), "");
2234
2235 /* Store the outputs. */
2236 build_tbuffer_store_dwords(ctx, buffer, vec0,
2237 MIN2(stride, 4), byteoffset, tf_base, 0);
2238 if (vec1)
2239 build_tbuffer_store_dwords(ctx, buffer, vec1,
2240 stride - 4, byteoffset, tf_base, 16);
2241 lp_build_endif(&if_ctx);
2242 }
2243
2244 /* This only writes the tessellation factor levels. */
2245 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2246 {
2247 struct si_shader_context *ctx = si_shader_context(bld_base);
2248 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2249
2250 rel_patch_id = get_rel_patch_id(ctx);
2251 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2252 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2253
2254 if (!ctx->is_monolithic) {
2255 /* Return epilog parameters from this function. */
2256 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2257 LLVMValueRef ret = ctx->return_value;
2258 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2259 unsigned vgpr;
2260
2261 /* RW_BUFFERS pointer */
2262 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2263 SI_PARAM_RW_BUFFERS);
2264 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2265 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2266 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2267 bld_base->uint_bld.zero, "");
2268 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2269 bld_base->uint_bld.one, "");
2270 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2271 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2272
2273 /* Tess factor buffer soffset is after user SGPRs. */
2274 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2275 SI_PARAM_TESS_FACTOR_OFFSET);
2276 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2277 SI_TCS_NUM_USER_SGPR, "");
2278
2279 /* VGPRs */
2280 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2281 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2282 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2283
2284 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2285 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2286 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2287 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2288 ctx->return_value = ret;
2289 return;
2290 }
2291
2292 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2293 }
2294
2295 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2296 {
2297 struct si_shader_context *ctx = si_shader_context(bld_base);
2298 struct si_shader *shader = ctx->shader;
2299 struct tgsi_shader_info *info = &shader->selector->info;
2300 struct gallivm_state *gallivm = bld_base->base.gallivm;
2301 unsigned i, chan;
2302 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2303 ctx->param_rel_auto_id);
2304 LLVMValueRef vertex_dw_stride =
2305 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2306 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2307 vertex_dw_stride, "");
2308
2309 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2310 * its inputs from it. */
2311 for (i = 0; i < info->num_outputs; i++) {
2312 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2313 unsigned name = info->output_semantic_name[i];
2314 unsigned index = info->output_semantic_index[i];
2315 int param = si_shader_io_get_unique_index(name, index);
2316 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2317 lp_build_const_int32(gallivm, param * 4), "");
2318
2319 for (chan = 0; chan < 4; chan++) {
2320 lds_store(bld_base, chan, dw_addr,
2321 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2322 }
2323 }
2324 }
2325
2326 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2327 {
2328 struct si_shader_context *ctx = si_shader_context(bld_base);
2329 struct gallivm_state *gallivm = bld_base->base.gallivm;
2330 struct si_shader *es = ctx->shader;
2331 struct tgsi_shader_info *info = &es->selector->info;
2332 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2333 ctx->param_es2gs_offset);
2334 unsigned chan;
2335 int i;
2336
2337 for (i = 0; i < info->num_outputs; i++) {
2338 LLVMValueRef *out_ptr =
2339 ctx->radeon_bld.soa.outputs[i];
2340 int param_index;
2341
2342 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2343 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2344 continue;
2345
2346 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2347 info->output_semantic_index[i]);
2348
2349 for (chan = 0; chan < 4; chan++) {
2350 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2351 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2352
2353 build_tbuffer_store(ctx,
2354 ctx->esgs_ring,
2355 out_val, 1,
2356 LLVMGetUndef(ctx->i32), soffset,
2357 (4 * param_index + chan) * 4,
2358 V_008F0C_BUF_DATA_FORMAT_32,
2359 V_008F0C_BUF_NUM_FORMAT_UINT,
2360 0, 0, 1, 1, 0);
2361 }
2362 }
2363 }
2364
2365 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2366 {
2367 struct si_shader_context *ctx = si_shader_context(bld_base);
2368 struct gallivm_state *gallivm = bld_base->base.gallivm;
2369 LLVMValueRef args[2];
2370
2371 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2372 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2373 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2374 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2375 }
2376
2377 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2378 {
2379 struct si_shader_context *ctx = si_shader_context(bld_base);
2380 struct gallivm_state *gallivm = bld_base->base.gallivm;
2381 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2382 struct si_shader_output_values *outputs = NULL;
2383 int i,j;
2384
2385 assert(!ctx->is_gs_copy_shader);
2386
2387 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2388
2389 /* Vertex color clamping.
2390 *
2391 * This uses a state constant loaded in a user data SGPR and
2392 * an IF statement is added that clamps all colors if the constant
2393 * is true.
2394 */
2395 if (ctx->type == PIPE_SHADER_VERTEX) {
2396 struct lp_build_if_state if_ctx;
2397 LLVMValueRef cond = NULL;
2398 LLVMValueRef addr, val;
2399
2400 for (i = 0; i < info->num_outputs; i++) {
2401 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2402 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2403 continue;
2404
2405 /* We've found a color. */
2406 if (!cond) {
2407 /* The state is in the first bit of the user SGPR. */
2408 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2409 SI_PARAM_VS_STATE_BITS);
2410 cond = LLVMBuildTrunc(gallivm->builder, cond,
2411 ctx->i1, "");
2412 lp_build_if(&if_ctx, gallivm, cond);
2413 }
2414
2415 for (j = 0; j < 4; j++) {
2416 addr = ctx->radeon_bld.soa.outputs[i][j];
2417 val = LLVMBuildLoad(gallivm->builder, addr, "");
2418 val = radeon_llvm_saturate(bld_base, val);
2419 LLVMBuildStore(gallivm->builder, val, addr);
2420 }
2421 }
2422
2423 if (cond)
2424 lp_build_endif(&if_ctx);
2425 }
2426
2427 for (i = 0; i < info->num_outputs; i++) {
2428 outputs[i].name = info->output_semantic_name[i];
2429 outputs[i].sid = info->output_semantic_index[i];
2430
2431 for (j = 0; j < 4; j++)
2432 outputs[i].values[j] =
2433 LLVMBuildLoad(gallivm->builder,
2434 ctx->radeon_bld.soa.outputs[i][j],
2435 "");
2436 }
2437
2438 if (ctx->is_monolithic) {
2439 /* Export PrimitiveID when PS needs it. */
2440 if (si_vs_exports_prim_id(ctx->shader)) {
2441 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2442 outputs[i].sid = 0;
2443 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2444 get_primitive_id(bld_base, 0));
2445 outputs[i].values[1] = bld_base->base.undef;
2446 outputs[i].values[2] = bld_base->base.undef;
2447 outputs[i].values[3] = bld_base->base.undef;
2448 i++;
2449 }
2450 } else {
2451 /* Return the primitive ID from the LLVM function. */
2452 ctx->return_value =
2453 LLVMBuildInsertValue(gallivm->builder,
2454 ctx->return_value,
2455 bitcast(bld_base, TGSI_TYPE_FLOAT,
2456 get_primitive_id(bld_base, 0)),
2457 VS_EPILOG_PRIMID_LOC, "");
2458 }
2459
2460 si_llvm_export_vs(bld_base, outputs, i);
2461 FREE(outputs);
2462 }
2463
2464 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2465 LLVMValueRef depth, LLVMValueRef stencil,
2466 LLVMValueRef samplemask)
2467 {
2468 struct si_shader_context *ctx = si_shader_context(bld_base);
2469 struct lp_build_context *base = &bld_base->base;
2470 struct lp_build_context *uint = &bld_base->uint_bld;
2471 LLVMValueRef args[9];
2472 unsigned mask = 0;
2473
2474 assert(depth || stencil || samplemask);
2475
2476 args[1] = uint->one; /* whether the EXEC mask is valid */
2477 args[2] = uint->one; /* DONE bit */
2478
2479 /* Specify the target we are exporting */
2480 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2481
2482 args[4] = uint->zero; /* COMP flag */
2483 args[5] = base->undef; /* R, depth */
2484 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2485 args[7] = base->undef; /* B, sample mask */
2486 args[8] = base->undef; /* A, alpha to mask */
2487
2488 if (depth) {
2489 args[5] = depth;
2490 mask |= 0x1;
2491 }
2492
2493 if (stencil) {
2494 args[6] = stencil;
2495 mask |= 0x2;
2496 }
2497
2498 if (samplemask) {
2499 args[7] = samplemask;
2500 mask |= 0x4;
2501 }
2502
2503 /* SI (except OLAND) has a bug that it only looks
2504 * at the X writemask component. */
2505 if (ctx->screen->b.chip_class == SI &&
2506 ctx->screen->b.family != CHIP_OLAND)
2507 mask |= 0x1;
2508
2509 /* Specify which components to enable */
2510 args[0] = lp_build_const_int32(base->gallivm, mask);
2511
2512 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2513 ctx->voidt, args, 9, 0);
2514 }
2515
2516 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2517 LLVMValueRef *color, unsigned index,
2518 unsigned samplemask_param,
2519 bool is_last)
2520 {
2521 struct si_shader_context *ctx = si_shader_context(bld_base);
2522 struct lp_build_context *base = &bld_base->base;
2523 int i;
2524
2525 /* Clamp color */
2526 if (ctx->shader->key.ps.epilog.clamp_color)
2527 for (i = 0; i < 4; i++)
2528 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2529
2530 /* Alpha to one */
2531 if (ctx->shader->key.ps.epilog.alpha_to_one)
2532 color[3] = base->one;
2533
2534 /* Alpha test */
2535 if (index == 0 &&
2536 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2537 si_alpha_test(bld_base, color[3]);
2538
2539 /* Line & polygon smoothing */
2540 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2541 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2542 samplemask_param);
2543
2544 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2545 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2546 LLVMValueRef args[8][9];
2547 int c, last = -1;
2548
2549 /* Get the export arguments, also find out what the last one is. */
2550 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2551 si_llvm_init_export_args(bld_base, color,
2552 V_008DFC_SQ_EXP_MRT + c, args[c]);
2553 if (args[c][0] != bld_base->uint_bld.zero)
2554 last = c;
2555 }
2556
2557 /* Emit all exports. */
2558 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2559 if (is_last && last == c) {
2560 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2561 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2562 } else if (args[c][0] == bld_base->uint_bld.zero)
2563 continue; /* unnecessary NULL export */
2564
2565 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2566 ctx->voidt, args[c], 9, 0);
2567 }
2568 } else {
2569 LLVMValueRef args[9];
2570
2571 /* Export */
2572 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2573 args);
2574 if (is_last) {
2575 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2576 args[2] = bld_base->uint_bld.one; /* DONE bit */
2577 } else if (args[0] == bld_base->uint_bld.zero)
2578 return; /* unnecessary NULL export */
2579
2580 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2581 ctx->voidt, args, 9, 0);
2582 }
2583 }
2584
2585 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2586 {
2587 struct si_shader_context *ctx = si_shader_context(bld_base);
2588 struct lp_build_context *base = &bld_base->base;
2589 struct lp_build_context *uint = &bld_base->uint_bld;
2590 LLVMValueRef args[9];
2591
2592 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2593 args[1] = uint->one; /* whether the EXEC mask is valid */
2594 args[2] = uint->one; /* DONE bit */
2595 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2596 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2597 args[5] = uint->undef; /* R */
2598 args[6] = uint->undef; /* G */
2599 args[7] = uint->undef; /* B */
2600 args[8] = uint->undef; /* A */
2601
2602 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2603 ctx->voidt, args, 9, 0);
2604 }
2605
2606 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2607 {
2608 struct si_shader_context *ctx = si_shader_context(bld_base);
2609 struct si_shader *shader = ctx->shader;
2610 struct lp_build_context *base = &bld_base->base;
2611 struct tgsi_shader_info *info = &shader->selector->info;
2612 LLVMBuilderRef builder = base->gallivm->builder;
2613 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2614 int last_color_export = -1;
2615 int i;
2616
2617 /* Determine the last export. If MRTZ is present, it's always last.
2618 * Otherwise, find the last color export.
2619 */
2620 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2621 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2622
2623 /* Don't export NULL and return if alpha-test is enabled. */
2624 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2625 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2626 (spi_format & 0xf) == 0)
2627 spi_format |= V_028714_SPI_SHADER_32_AR;
2628
2629 for (i = 0; i < info->num_outputs; i++) {
2630 unsigned index = info->output_semantic_index[i];
2631
2632 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2633 continue;
2634
2635 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2636 if (shader->key.ps.epilog.last_cbuf > 0) {
2637 /* Just set this if any of the colorbuffers are enabled. */
2638 if (spi_format &
2639 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2640 last_color_export = i;
2641 continue;
2642 }
2643
2644 if ((spi_format >> (index * 4)) & 0xf)
2645 last_color_export = i;
2646 }
2647
2648 /* If there are no outputs, export NULL. */
2649 if (last_color_export == -1) {
2650 si_export_null(bld_base);
2651 return;
2652 }
2653 }
2654
2655 for (i = 0; i < info->num_outputs; i++) {
2656 unsigned semantic_name = info->output_semantic_name[i];
2657 unsigned semantic_index = info->output_semantic_index[i];
2658 unsigned j;
2659 LLVMValueRef color[4] = {};
2660
2661 /* Select the correct target */
2662 switch (semantic_name) {
2663 case TGSI_SEMANTIC_POSITION:
2664 depth = LLVMBuildLoad(builder,
2665 ctx->radeon_bld.soa.outputs[i][2], "");
2666 break;
2667 case TGSI_SEMANTIC_STENCIL:
2668 stencil = LLVMBuildLoad(builder,
2669 ctx->radeon_bld.soa.outputs[i][1], "");
2670 break;
2671 case TGSI_SEMANTIC_SAMPLEMASK:
2672 samplemask = LLVMBuildLoad(builder,
2673 ctx->radeon_bld.soa.outputs[i][0], "");
2674 break;
2675 case TGSI_SEMANTIC_COLOR:
2676 for (j = 0; j < 4; j++)
2677 color[j] = LLVMBuildLoad(builder,
2678 ctx->radeon_bld.soa.outputs[i][j], "");
2679
2680 si_export_mrt_color(bld_base, color, semantic_index,
2681 SI_PARAM_SAMPLE_COVERAGE,
2682 last_color_export == i);
2683 break;
2684 default:
2685 fprintf(stderr,
2686 "Warning: SI unhandled fs output type:%d\n",
2687 semantic_name);
2688 }
2689 }
2690
2691 if (depth || stencil || samplemask)
2692 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2693 }
2694
2695 /**
2696 * Return PS outputs in this order:
2697 *
2698 * v[0:3] = color0.xyzw
2699 * v[4:7] = color1.xyzw
2700 * ...
2701 * vN+0 = Depth
2702 * vN+1 = Stencil
2703 * vN+2 = SampleMask
2704 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2705 *
2706 * The alpha-ref SGPR is returned via its original location.
2707 */
2708 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2709 {
2710 struct si_shader_context *ctx = si_shader_context(bld_base);
2711 struct si_shader *shader = ctx->shader;
2712 struct lp_build_context *base = &bld_base->base;
2713 struct tgsi_shader_info *info = &shader->selector->info;
2714 LLVMBuilderRef builder = base->gallivm->builder;
2715 unsigned i, j, first_vgpr, vgpr;
2716
2717 LLVMValueRef color[8][4] = {};
2718 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2719 LLVMValueRef ret;
2720
2721 /* Read the output values. */
2722 for (i = 0; i < info->num_outputs; i++) {
2723 unsigned semantic_name = info->output_semantic_name[i];
2724 unsigned semantic_index = info->output_semantic_index[i];
2725
2726 switch (semantic_name) {
2727 case TGSI_SEMANTIC_COLOR:
2728 assert(semantic_index < 8);
2729 for (j = 0; j < 4; j++) {
2730 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2731 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2732 color[semantic_index][j] = result;
2733 }
2734 break;
2735 case TGSI_SEMANTIC_POSITION:
2736 depth = LLVMBuildLoad(builder,
2737 ctx->radeon_bld.soa.outputs[i][2], "");
2738 break;
2739 case TGSI_SEMANTIC_STENCIL:
2740 stencil = LLVMBuildLoad(builder,
2741 ctx->radeon_bld.soa.outputs[i][1], "");
2742 break;
2743 case TGSI_SEMANTIC_SAMPLEMASK:
2744 samplemask = LLVMBuildLoad(builder,
2745 ctx->radeon_bld.soa.outputs[i][0], "");
2746 break;
2747 default:
2748 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2749 semantic_name);
2750 }
2751 }
2752
2753 /* Fill the return structure. */
2754 ret = ctx->return_value;
2755
2756 /* Set SGPRs. */
2757 ret = LLVMBuildInsertValue(builder, ret,
2758 bitcast(bld_base, TGSI_TYPE_SIGNED,
2759 LLVMGetParam(ctx->radeon_bld.main_fn,
2760 SI_PARAM_ALPHA_REF)),
2761 SI_SGPR_ALPHA_REF, "");
2762
2763 /* Set VGPRs */
2764 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2765 for (i = 0; i < ARRAY_SIZE(color); i++) {
2766 if (!color[i][0])
2767 continue;
2768
2769 for (j = 0; j < 4; j++)
2770 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2771 }
2772 if (depth)
2773 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2774 if (stencil)
2775 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2776 if (samplemask)
2777 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2778
2779 /* Add the input sample mask for smoothing at the end. */
2780 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2781 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2782 ret = LLVMBuildInsertValue(builder, ret,
2783 LLVMGetParam(ctx->radeon_bld.main_fn,
2784 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2785
2786 ctx->return_value = ret;
2787 }
2788
2789 /**
2790 * Given a v8i32 resource descriptor for a buffer, extract the size of the
2791 * buffer in number of elements and return it as an i32.
2792 */
2793 static LLVMValueRef get_buffer_size(
2794 struct lp_build_tgsi_context *bld_base,
2795 LLVMValueRef descriptor)
2796 {
2797 struct si_shader_context *ctx = si_shader_context(bld_base);
2798 struct gallivm_state *gallivm = bld_base->base.gallivm;
2799 LLVMBuilderRef builder = gallivm->builder;
2800 LLVMValueRef size =
2801 LLVMBuildExtractElement(builder, descriptor,
2802 lp_build_const_int32(gallivm, 6), "");
2803
2804 if (ctx->screen->b.chip_class >= VI) {
2805 /* On VI, the descriptor contains the size in bytes,
2806 * but TXQ must return the size in elements.
2807 * The stride is always non-zero for resources using TXQ.
2808 */
2809 LLVMValueRef stride =
2810 LLVMBuildExtractElement(builder, descriptor,
2811 lp_build_const_int32(gallivm, 5), "");
2812 stride = LLVMBuildLShr(builder, stride,
2813 lp_build_const_int32(gallivm, 16), "");
2814 stride = LLVMBuildAnd(builder, stride,
2815 lp_build_const_int32(gallivm, 0x3FFF), "");
2816
2817 size = LLVMBuildUDiv(builder, size, stride, "");
2818 }
2819
2820 return size;
2821 }
2822
2823 /**
2824 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2825 * intrinsic names).
2826 */
2827 static void build_int_type_name(
2828 LLVMTypeRef type,
2829 char *buf, unsigned bufsize)
2830 {
2831 assert(bufsize >= 6);
2832
2833 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2834 snprintf(buf, bufsize, "v%ui32",
2835 LLVMGetVectorSize(type));
2836 else
2837 strcpy(buf, "i32");
2838 }
2839
2840 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2841 struct lp_build_tgsi_context *bld_base,
2842 struct lp_build_emit_data *emit_data);
2843
2844 /* Prevent optimizations (at least of memory accesses) across the current
2845 * point in the program by emitting empty inline assembly that is marked as
2846 * having side effects.
2847 */
2848 static void emit_optimization_barrier(struct si_shader_context *ctx)
2849 {
2850 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2851 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
2852 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
2853 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
2854 }
2855
2856 static void membar_emit(
2857 const struct lp_build_tgsi_action *action,
2858 struct lp_build_tgsi_context *bld_base,
2859 struct lp_build_emit_data *emit_data)
2860 {
2861 struct si_shader_context *ctx = si_shader_context(bld_base);
2862
2863 /* Since memoryBarrier only makes guarantees about atomics and
2864 * coherent image accesses (which bypass TC L1), we do not need to emit
2865 * any special cache handling here.
2866 *
2867 * We do have to prevent LLVM from re-ordering loads across
2868 * the barrier though.
2869 */
2870 emit_optimization_barrier(ctx);
2871 }
2872
2873 static LLVMValueRef
2874 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
2875 const struct tgsi_full_src_register *reg)
2876 {
2877 LLVMValueRef ind_index;
2878 LLVMValueRef rsrc_ptr;
2879
2880 if (!reg->Register.Indirect)
2881 return ctx->shader_buffers[reg->Register.Index];
2882
2883 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
2884 reg->Register.Index,
2885 SI_NUM_SHADER_BUFFERS);
2886
2887 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
2888 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2889 }
2890
2891 static bool tgsi_is_array_sampler(unsigned target)
2892 {
2893 return target == TGSI_TEXTURE_1D_ARRAY ||
2894 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2895 target == TGSI_TEXTURE_2D_ARRAY ||
2896 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2897 target == TGSI_TEXTURE_CUBE_ARRAY ||
2898 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2899 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2900 }
2901
2902 static bool tgsi_is_array_image(unsigned target)
2903 {
2904 return target == TGSI_TEXTURE_3D ||
2905 target == TGSI_TEXTURE_CUBE ||
2906 target == TGSI_TEXTURE_1D_ARRAY ||
2907 target == TGSI_TEXTURE_2D_ARRAY ||
2908 target == TGSI_TEXTURE_CUBE_ARRAY ||
2909 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2910 }
2911
2912 /**
2913 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
2914 *
2915 * At least on Tonga, executing image stores on images with DCC enabled and
2916 * non-trivial can eventually lead to lockups. This can occur when an
2917 * application binds an image as read-only but then uses a shader that writes
2918 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
2919 * program termination) in this case, but it doesn't cost much to be a bit
2920 * nicer: disabling DCC in the shader still leads to undefined results but
2921 * avoids the lockup.
2922 */
2923 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
2924 LLVMValueRef rsrc)
2925 {
2926 if (ctx->screen->b.chip_class <= CIK) {
2927 return rsrc;
2928 } else {
2929 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
2930 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
2931 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
2932 LLVMValueRef tmp;
2933
2934 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
2935 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
2936 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
2937 }
2938 }
2939
2940 /**
2941 * Load the resource descriptor for \p image.
2942 */
2943 static void
2944 image_fetch_rsrc(
2945 struct lp_build_tgsi_context *bld_base,
2946 const struct tgsi_full_src_register *image,
2947 bool dcc_off,
2948 LLVMValueRef *rsrc)
2949 {
2950 struct si_shader_context *ctx = si_shader_context(bld_base);
2951
2952 assert(image->Register.File == TGSI_FILE_IMAGE);
2953
2954 if (!image->Register.Indirect) {
2955 /* Fast path: use preloaded resources */
2956 *rsrc = ctx->images[image->Register.Index];
2957 } else {
2958 /* Indexing and manual load */
2959 LLVMValueRef ind_index;
2960 LLVMValueRef rsrc_ptr;
2961 LLVMValueRef tmp;
2962
2963 /* From the GL_ARB_shader_image_load_store extension spec:
2964 *
2965 * If a shader performs an image load, store, or atomic
2966 * operation using an image variable declared as an array,
2967 * and if the index used to select an individual element is
2968 * negative or greater than or equal to the size of the
2969 * array, the results of the operation are undefined but may
2970 * not lead to termination.
2971 */
2972 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
2973 image->Register.Index,
2974 SI_NUM_IMAGES);
2975
2976 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
2977 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2978 if (dcc_off)
2979 tmp = force_dcc_off(ctx, tmp);
2980 *rsrc = tmp;
2981 }
2982 }
2983
2984 static LLVMValueRef image_fetch_coords(
2985 struct lp_build_tgsi_context *bld_base,
2986 const struct tgsi_full_instruction *inst,
2987 unsigned src)
2988 {
2989 struct gallivm_state *gallivm = bld_base->base.gallivm;
2990 LLVMBuilderRef builder = gallivm->builder;
2991 unsigned target = inst->Memory.Texture;
2992 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
2993 LLVMValueRef coords[4];
2994 LLVMValueRef tmp;
2995 int chan;
2996
2997 for (chan = 0; chan < num_coords; ++chan) {
2998 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
2999 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3000 coords[chan] = tmp;
3001 }
3002
3003 if (num_coords == 1)
3004 return coords[0];
3005
3006 if (num_coords == 3) {
3007 /* LLVM has difficulties lowering 3-element vectors. */
3008 coords[3] = bld_base->uint_bld.undef;
3009 num_coords = 4;
3010 }
3011
3012 return lp_build_gather_values(gallivm, coords, num_coords);
3013 }
3014
3015 /**
3016 * Append the extra mode bits that are used by image load and store.
3017 */
3018 static void image_append_args(
3019 struct si_shader_context *ctx,
3020 struct lp_build_emit_data * emit_data,
3021 unsigned target,
3022 bool atomic)
3023 {
3024 const struct tgsi_full_instruction *inst = emit_data->inst;
3025 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3026 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3027
3028 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3029 emit_data->args[emit_data->arg_count++] =
3030 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3031 if (!atomic) {
3032 emit_data->args[emit_data->arg_count++] =
3033 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3034 i1true : i1false; /* glc */
3035 }
3036 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3037 }
3038
3039 /**
3040 * Given a 256 bit resource, extract the top half (which stores the buffer
3041 * resource in the case of textures and images).
3042 */
3043 static LLVMValueRef extract_rsrc_top_half(
3044 struct si_shader_context *ctx,
3045 LLVMValueRef rsrc)
3046 {
3047 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3048 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3049 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3050
3051 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3052 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3053 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3054
3055 return rsrc;
3056 }
3057
3058 /**
3059 * Append the resource and indexing arguments for buffer intrinsics.
3060 *
3061 * \param rsrc the v4i32 buffer resource
3062 * \param index index into the buffer (stride-based)
3063 * \param offset byte offset into the buffer
3064 */
3065 static void buffer_append_args(
3066 struct si_shader_context *ctx,
3067 struct lp_build_emit_data *emit_data,
3068 LLVMValueRef rsrc,
3069 LLVMValueRef index,
3070 LLVMValueRef offset,
3071 bool atomic)
3072 {
3073 const struct tgsi_full_instruction *inst = emit_data->inst;
3074 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3075 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3076
3077 emit_data->args[emit_data->arg_count++] = rsrc;
3078 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3079 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3080 if (!atomic) {
3081 emit_data->args[emit_data->arg_count++] =
3082 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3083 i1true : i1false; /* glc */
3084 }
3085 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3086 }
3087
3088 static void load_fetch_args(
3089 struct lp_build_tgsi_context * bld_base,
3090 struct lp_build_emit_data * emit_data)
3091 {
3092 struct si_shader_context *ctx = si_shader_context(bld_base);
3093 struct gallivm_state *gallivm = bld_base->base.gallivm;
3094 const struct tgsi_full_instruction * inst = emit_data->inst;
3095 unsigned target = inst->Memory.Texture;
3096 LLVMValueRef rsrc;
3097
3098 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3099
3100 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3101 LLVMBuilderRef builder = gallivm->builder;
3102 LLVMValueRef offset;
3103 LLVMValueRef tmp;
3104
3105 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3106
3107 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3108 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3109
3110 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3111 offset, false);
3112 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3113 LLVMValueRef coords;
3114
3115 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3116 coords = image_fetch_coords(bld_base, inst, 1);
3117
3118 if (target == TGSI_TEXTURE_BUFFER) {
3119 rsrc = extract_rsrc_top_half(ctx, rsrc);
3120 buffer_append_args(ctx, emit_data, rsrc, coords,
3121 bld_base->uint_bld.zero, false);
3122 } else {
3123 emit_data->args[0] = coords;
3124 emit_data->args[1] = rsrc;
3125 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3126 emit_data->arg_count = 3;
3127
3128 image_append_args(ctx, emit_data, target, false);
3129 }
3130 }
3131 }
3132
3133 static void load_emit_buffer(struct si_shader_context *ctx,
3134 struct lp_build_emit_data *emit_data)
3135 {
3136 const struct tgsi_full_instruction *inst = emit_data->inst;
3137 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3138 LLVMBuilderRef builder = gallivm->builder;
3139 uint writemask = inst->Dst[0].Register.WriteMask;
3140 uint count = util_last_bit(writemask);
3141 const char *intrinsic_name;
3142 LLVMTypeRef dst_type;
3143
3144 switch (count) {
3145 case 1:
3146 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3147 dst_type = ctx->f32;
3148 break;
3149 case 2:
3150 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3151 dst_type = LLVMVectorType(ctx->f32, 2);
3152 break;
3153 default: // 3 & 4
3154 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3155 dst_type = ctx->v4f32;
3156 count = 4;
3157 }
3158
3159 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3160 builder, intrinsic_name, dst_type,
3161 emit_data->args, emit_data->arg_count,
3162 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3163 }
3164
3165 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3166 const struct tgsi_full_instruction *inst,
3167 LLVMTypeRef type, int arg)
3168 {
3169 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3170 LLVMBuilderRef builder = gallivm->builder;
3171 LLVMValueRef offset, ptr;
3172 int addr_space;
3173
3174 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3175 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3176
3177 ptr = ctx->shared_memory;
3178 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3179 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3180 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3181
3182 return ptr;
3183 }
3184
3185 static void load_emit_memory(
3186 struct si_shader_context *ctx,
3187 struct lp_build_emit_data *emit_data)
3188 {
3189 const struct tgsi_full_instruction *inst = emit_data->inst;
3190 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3191 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3192 LLVMBuilderRef builder = gallivm->builder;
3193 unsigned writemask = inst->Dst[0].Register.WriteMask;
3194 LLVMValueRef channels[4], ptr, derived_ptr, index;
3195 int chan;
3196
3197 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3198
3199 for (chan = 0; chan < 4; ++chan) {
3200 if (!(writemask & (1 << chan))) {
3201 channels[chan] = LLVMGetUndef(base->elem_type);
3202 continue;
3203 }
3204
3205 index = lp_build_const_int32(gallivm, chan);
3206 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3207 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3208 }
3209 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3210 }
3211
3212 static void load_emit(
3213 const struct lp_build_tgsi_action *action,
3214 struct lp_build_tgsi_context *bld_base,
3215 struct lp_build_emit_data *emit_data)
3216 {
3217 struct si_shader_context *ctx = si_shader_context(bld_base);
3218 struct gallivm_state *gallivm = bld_base->base.gallivm;
3219 LLVMBuilderRef builder = gallivm->builder;
3220 const struct tgsi_full_instruction * inst = emit_data->inst;
3221 char intrinsic_name[32];
3222 char coords_type[8];
3223
3224 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3225 load_emit_memory(ctx, emit_data);
3226 return;
3227 }
3228
3229 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3230 emit_optimization_barrier(ctx);
3231
3232 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3233 load_emit_buffer(ctx, emit_data);
3234 return;
3235 }
3236
3237 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3238 emit_data->output[emit_data->chan] =
3239 lp_build_intrinsic(
3240 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3241 emit_data->args, emit_data->arg_count,
3242 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3243 } else {
3244 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3245 coords_type, sizeof(coords_type));
3246
3247 snprintf(intrinsic_name, sizeof(intrinsic_name),
3248 "llvm.amdgcn.image.load.%s", coords_type);
3249
3250 emit_data->output[emit_data->chan] =
3251 lp_build_intrinsic(
3252 builder, intrinsic_name, emit_data->dst_type,
3253 emit_data->args, emit_data->arg_count,
3254 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3255 }
3256 }
3257
3258 static void store_fetch_args(
3259 struct lp_build_tgsi_context * bld_base,
3260 struct lp_build_emit_data * emit_data)
3261 {
3262 struct si_shader_context *ctx = si_shader_context(bld_base);
3263 struct gallivm_state *gallivm = bld_base->base.gallivm;
3264 LLVMBuilderRef builder = gallivm->builder;
3265 const struct tgsi_full_instruction * inst = emit_data->inst;
3266 struct tgsi_full_src_register memory;
3267 LLVMValueRef chans[4];
3268 LLVMValueRef data;
3269 LLVMValueRef rsrc;
3270 unsigned chan;
3271
3272 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3273
3274 for (chan = 0; chan < 4; ++chan) {
3275 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3276 }
3277 data = lp_build_gather_values(gallivm, chans, 4);
3278
3279 emit_data->args[emit_data->arg_count++] = data;
3280
3281 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3282
3283 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3284 LLVMValueRef offset;
3285 LLVMValueRef tmp;
3286
3287 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3288
3289 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3290 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3291
3292 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3293 offset, false);
3294 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3295 unsigned target = inst->Memory.Texture;
3296 LLVMValueRef coords;
3297
3298 coords = image_fetch_coords(bld_base, inst, 0);
3299
3300 if (target == TGSI_TEXTURE_BUFFER) {
3301 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3302
3303 rsrc = extract_rsrc_top_half(ctx, rsrc);
3304 buffer_append_args(ctx, emit_data, rsrc, coords,
3305 bld_base->uint_bld.zero, false);
3306 } else {
3307 emit_data->args[1] = coords;
3308 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3309 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3310 emit_data->arg_count = 4;
3311
3312 image_append_args(ctx, emit_data, target, false);
3313 }
3314 }
3315 }
3316
3317 static void store_emit_buffer(
3318 struct si_shader_context *ctx,
3319 struct lp_build_emit_data *emit_data)
3320 {
3321 const struct tgsi_full_instruction *inst = emit_data->inst;
3322 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3323 LLVMBuilderRef builder = gallivm->builder;
3324 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3325 LLVMValueRef base_data = emit_data->args[0];
3326 LLVMValueRef base_offset = emit_data->args[3];
3327 unsigned writemask = inst->Dst[0].Register.WriteMask;
3328
3329 while (writemask) {
3330 int start, count;
3331 const char *intrinsic_name;
3332 LLVMValueRef data;
3333 LLVMValueRef offset;
3334 LLVMValueRef tmp;
3335
3336 u_bit_scan_consecutive_range(&writemask, &start, &count);
3337
3338 /* Due to an LLVM limitation, split 3-element writes
3339 * into a 2-element and a 1-element write. */
3340 if (count == 3) {
3341 writemask |= 1 << (start + 2);
3342 count = 2;
3343 }
3344
3345 if (count == 4) {
3346 data = base_data;
3347 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3348 } else if (count == 2) {
3349 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3350
3351 tmp = LLVMBuildExtractElement(
3352 builder, base_data,
3353 lp_build_const_int32(gallivm, start), "");
3354 data = LLVMBuildInsertElement(
3355 builder, LLVMGetUndef(v2f32), tmp,
3356 uint_bld->zero, "");
3357
3358 tmp = LLVMBuildExtractElement(
3359 builder, base_data,
3360 lp_build_const_int32(gallivm, start + 1), "");
3361 data = LLVMBuildInsertElement(
3362 builder, data, tmp, uint_bld->one, "");
3363
3364 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3365 } else {
3366 assert(count == 1);
3367 data = LLVMBuildExtractElement(
3368 builder, base_data,
3369 lp_build_const_int32(gallivm, start), "");
3370 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3371 }
3372
3373 offset = base_offset;
3374 if (start != 0) {
3375 offset = LLVMBuildAdd(
3376 builder, offset,
3377 lp_build_const_int32(gallivm, start * 4), "");
3378 }
3379
3380 emit_data->args[0] = data;
3381 emit_data->args[3] = offset;
3382
3383 lp_build_intrinsic(
3384 builder, intrinsic_name, emit_data->dst_type,
3385 emit_data->args, emit_data->arg_count,
3386 LLVMNoUnwindAttribute);
3387 }
3388 }
3389
3390 static void store_emit_memory(
3391 struct si_shader_context *ctx,
3392 struct lp_build_emit_data *emit_data)
3393 {
3394 const struct tgsi_full_instruction *inst = emit_data->inst;
3395 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3396 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3397 LLVMBuilderRef builder = gallivm->builder;
3398 unsigned writemask = inst->Dst[0].Register.WriteMask;
3399 LLVMValueRef ptr, derived_ptr, data, index;
3400 int chan;
3401
3402 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3403
3404 for (chan = 0; chan < 4; ++chan) {
3405 if (!(writemask & (1 << chan))) {
3406 continue;
3407 }
3408 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3409 index = lp_build_const_int32(gallivm, chan);
3410 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3411 LLVMBuildStore(builder, data, derived_ptr);
3412 }
3413 }
3414
3415 static void store_emit(
3416 const struct lp_build_tgsi_action *action,
3417 struct lp_build_tgsi_context *bld_base,
3418 struct lp_build_emit_data *emit_data)
3419 {
3420 struct gallivm_state *gallivm = bld_base->base.gallivm;
3421 LLVMBuilderRef builder = gallivm->builder;
3422 const struct tgsi_full_instruction * inst = emit_data->inst;
3423 unsigned target = inst->Memory.Texture;
3424 char intrinsic_name[32];
3425 char coords_type[8];
3426
3427 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3428 store_emit_buffer(si_shader_context(bld_base), emit_data);
3429 return;
3430 } else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3431 store_emit_memory(si_shader_context(bld_base), emit_data);
3432 return;
3433 }
3434
3435 if (target == TGSI_TEXTURE_BUFFER) {
3436 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3437 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3438 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3439 LLVMNoUnwindAttribute);
3440 } else {
3441 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3442 coords_type, sizeof(coords_type));
3443 snprintf(intrinsic_name, sizeof(intrinsic_name),
3444 "llvm.amdgcn.image.store.%s", coords_type);
3445
3446 emit_data->output[emit_data->chan] =
3447 lp_build_intrinsic(
3448 builder, intrinsic_name, emit_data->dst_type,
3449 emit_data->args, emit_data->arg_count,
3450 LLVMNoUnwindAttribute);
3451 }
3452 }
3453
3454 static void atomic_fetch_args(
3455 struct lp_build_tgsi_context * bld_base,
3456 struct lp_build_emit_data * emit_data)
3457 {
3458 struct si_shader_context *ctx = si_shader_context(bld_base);
3459 struct gallivm_state *gallivm = bld_base->base.gallivm;
3460 LLVMBuilderRef builder = gallivm->builder;
3461 const struct tgsi_full_instruction * inst = emit_data->inst;
3462 LLVMValueRef data1, data2;
3463 LLVMValueRef rsrc;
3464 LLVMValueRef tmp;
3465
3466 emit_data->dst_type = bld_base->base.elem_type;
3467
3468 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3469 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3470
3471 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3472 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3473 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3474 }
3475
3476 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3477 * of arguments, which is reversed relative to TGSI (and GLSL)
3478 */
3479 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3480 emit_data->args[emit_data->arg_count++] = data2;
3481 emit_data->args[emit_data->arg_count++] = data1;
3482
3483 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3484 LLVMValueRef offset;
3485
3486 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3487
3488 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3489 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3490
3491 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3492 offset, true);
3493 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3494 unsigned target = inst->Memory.Texture;
3495 LLVMValueRef coords;
3496
3497 image_fetch_rsrc(bld_base, &inst->Src[0],
3498 target != TGSI_TEXTURE_BUFFER, &rsrc);
3499 coords = image_fetch_coords(bld_base, inst, 1);
3500
3501 if (target == TGSI_TEXTURE_BUFFER) {
3502 rsrc = extract_rsrc_top_half(ctx, rsrc);
3503 buffer_append_args(ctx, emit_data, rsrc, coords,
3504 bld_base->uint_bld.zero, true);
3505 } else {
3506 emit_data->args[emit_data->arg_count++] = coords;
3507 emit_data->args[emit_data->arg_count++] = rsrc;
3508
3509 image_append_args(ctx, emit_data, target, true);
3510 }
3511 }
3512 }
3513
3514 static void atomic_emit_memory(struct si_shader_context *ctx,
3515 struct lp_build_emit_data *emit_data) {
3516 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3517 LLVMBuilderRef builder = gallivm->builder;
3518 const struct tgsi_full_instruction * inst = emit_data->inst;
3519 LLVMValueRef ptr, result, arg;
3520
3521 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3522
3523 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3524 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3525
3526 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3527 LLVMValueRef new_data;
3528 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3529 inst, 3, 0);
3530
3531 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3532
3533 #if HAVE_LLVM >= 0x309
3534 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3535 LLVMAtomicOrderingSequentiallyConsistent,
3536 LLVMAtomicOrderingSequentiallyConsistent,
3537 false);
3538 #endif
3539
3540 result = LLVMBuildExtractValue(builder, result, 0, "");
3541 } else {
3542 LLVMAtomicRMWBinOp op;
3543
3544 switch(inst->Instruction.Opcode) {
3545 case TGSI_OPCODE_ATOMUADD:
3546 op = LLVMAtomicRMWBinOpAdd;
3547 break;
3548 case TGSI_OPCODE_ATOMXCHG:
3549 op = LLVMAtomicRMWBinOpXchg;
3550 break;
3551 case TGSI_OPCODE_ATOMAND:
3552 op = LLVMAtomicRMWBinOpAnd;
3553 break;
3554 case TGSI_OPCODE_ATOMOR:
3555 op = LLVMAtomicRMWBinOpOr;
3556 break;
3557 case TGSI_OPCODE_ATOMXOR:
3558 op = LLVMAtomicRMWBinOpXor;
3559 break;
3560 case TGSI_OPCODE_ATOMUMIN:
3561 op = LLVMAtomicRMWBinOpUMin;
3562 break;
3563 case TGSI_OPCODE_ATOMUMAX:
3564 op = LLVMAtomicRMWBinOpUMax;
3565 break;
3566 case TGSI_OPCODE_ATOMIMIN:
3567 op = LLVMAtomicRMWBinOpMin;
3568 break;
3569 case TGSI_OPCODE_ATOMIMAX:
3570 op = LLVMAtomicRMWBinOpMax;
3571 break;
3572 default:
3573 unreachable("unknown atomic opcode");
3574 }
3575
3576 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3577 LLVMAtomicOrderingSequentiallyConsistent,
3578 false);
3579 }
3580 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3581 }
3582
3583 static void atomic_emit(
3584 const struct lp_build_tgsi_action *action,
3585 struct lp_build_tgsi_context *bld_base,
3586 struct lp_build_emit_data *emit_data)
3587 {
3588 struct si_shader_context *ctx = si_shader_context(bld_base);
3589 struct gallivm_state *gallivm = bld_base->base.gallivm;
3590 LLVMBuilderRef builder = gallivm->builder;
3591 const struct tgsi_full_instruction * inst = emit_data->inst;
3592 char intrinsic_name[40];
3593 LLVMValueRef tmp;
3594
3595 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3596 atomic_emit_memory(ctx, emit_data);
3597 return;
3598 }
3599
3600 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3601 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3602 snprintf(intrinsic_name, sizeof(intrinsic_name),
3603 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3604 } else {
3605 char coords_type[8];
3606
3607 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3608 coords_type, sizeof(coords_type));
3609 snprintf(intrinsic_name, sizeof(intrinsic_name),
3610 "llvm.amdgcn.image.atomic.%s.%s",
3611 action->intr_name, coords_type);
3612 }
3613
3614 tmp = lp_build_intrinsic(
3615 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3616 emit_data->args, emit_data->arg_count,
3617 LLVMNoUnwindAttribute);
3618 emit_data->output[emit_data->chan] =
3619 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3620 }
3621
3622 static void resq_fetch_args(
3623 struct lp_build_tgsi_context * bld_base,
3624 struct lp_build_emit_data * emit_data)
3625 {
3626 struct si_shader_context *ctx = si_shader_context(bld_base);
3627 struct gallivm_state *gallivm = bld_base->base.gallivm;
3628 const struct tgsi_full_instruction *inst = emit_data->inst;
3629 const struct tgsi_full_src_register *reg = &inst->Src[0];
3630
3631 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3632
3633 if (reg->Register.File == TGSI_FILE_BUFFER) {
3634 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
3635 emit_data->arg_count = 1;
3636 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3637 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
3638 emit_data->arg_count = 1;
3639 } else {
3640 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3641 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
3642 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3643 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3644 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3645 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
3646 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3647 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3648 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3649 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3650 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3651 emit_data->arg_count = 10;
3652 }
3653 }
3654
3655 static void resq_emit(
3656 const struct lp_build_tgsi_action *action,
3657 struct lp_build_tgsi_context *bld_base,
3658 struct lp_build_emit_data *emit_data)
3659 {
3660 struct gallivm_state *gallivm = bld_base->base.gallivm;
3661 LLVMBuilderRef builder = gallivm->builder;
3662 const struct tgsi_full_instruction *inst = emit_data->inst;
3663 LLVMValueRef out;
3664
3665 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3666 out = LLVMBuildExtractElement(builder, emit_data->args[0],
3667 lp_build_const_int32(gallivm, 2), "");
3668 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3669 out = get_buffer_size(bld_base, emit_data->args[0]);
3670 } else {
3671 out = lp_build_intrinsic(
3672 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
3673 emit_data->args, emit_data->arg_count,
3674 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3675
3676 /* Divide the number of layers by 6 to get the number of cubes. */
3677 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
3678 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
3679 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
3680
3681 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
3682 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
3683 z = LLVMBuildSDiv(builder, z, imm6, "");
3684 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
3685 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
3686 }
3687 }
3688
3689 emit_data->output[emit_data->chan] = out;
3690 }
3691
3692 static void set_tex_fetch_args(struct si_shader_context *ctx,
3693 struct lp_build_emit_data *emit_data,
3694 unsigned opcode, unsigned target,
3695 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3696 LLVMValueRef *param, unsigned count,
3697 unsigned dmask)
3698 {
3699 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3700 unsigned num_args;
3701 unsigned is_rect = target == TGSI_TEXTURE_RECT;
3702
3703 /* Pad to power of two vector */
3704 while (count < util_next_power_of_two(count))
3705 param[count++] = LLVMGetUndef(ctx->i32);
3706
3707 /* Texture coordinates. */
3708 if (count > 1)
3709 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
3710 else
3711 emit_data->args[0] = param[0];
3712
3713 /* Resource. */
3714 emit_data->args[1] = res_ptr;
3715 num_args = 2;
3716
3717 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
3718 emit_data->dst_type = ctx->v4i32;
3719 else {
3720 emit_data->dst_type = ctx->v4f32;
3721
3722 emit_data->args[num_args++] = samp_ptr;
3723 }
3724
3725 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
3726 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
3727 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
3728 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
3729 tgsi_is_array_sampler(target)); /* da */
3730 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
3731 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
3732 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
3733 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
3734
3735 emit_data->arg_count = num_args;
3736 }
3737
3738 static const struct lp_build_tgsi_action tex_action;
3739
3740 enum desc_type {
3741 DESC_IMAGE,
3742 DESC_FMASK,
3743 DESC_SAMPLER
3744 };
3745
3746 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3747 {
3748 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3749 CONST_ADDR_SPACE);
3750 }
3751
3752 /**
3753 * Load an image view, fmask view. or sampler state descriptor.
3754 */
3755 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
3756 LLVMValueRef list, LLVMValueRef index,
3757 enum desc_type type)
3758 {
3759 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3760 LLVMBuilderRef builder = gallivm->builder;
3761
3762 switch (type) {
3763 case DESC_IMAGE:
3764 /* The image is at [0:7]. */
3765 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3766 break;
3767 case DESC_FMASK:
3768 /* The FMASK is at [8:15]. */
3769 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3770 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
3771 break;
3772 case DESC_SAMPLER:
3773 /* The sampler state is at [12:15]. */
3774 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
3775 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
3776 list = LLVMBuildPointerCast(builder, list,
3777 const_array(ctx->v4i32, 0), "");
3778 break;
3779 }
3780
3781 return build_indexed_load_const(ctx, list, index);
3782 }
3783
3784 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
3785 LLVMValueRef index, enum desc_type type)
3786 {
3787 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
3788 SI_PARAM_SAMPLERS);
3789
3790 return get_sampler_desc_custom(ctx, list, index, type);
3791 }
3792
3793 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3794 *
3795 * SI-CI:
3796 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3797 * filtering manually. The driver sets img7 to a mask clearing
3798 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3799 * s_and_b32 samp0, samp0, img7
3800 *
3801 * VI:
3802 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3803 */
3804 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
3805 LLVMValueRef res, LLVMValueRef samp)
3806 {
3807 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3808 LLVMValueRef img7, samp0;
3809
3810 if (ctx->screen->b.chip_class >= VI)
3811 return samp;
3812
3813 img7 = LLVMBuildExtractElement(builder, res,
3814 LLVMConstInt(ctx->i32, 7, 0), "");
3815 samp0 = LLVMBuildExtractElement(builder, samp,
3816 LLVMConstInt(ctx->i32, 0, 0), "");
3817 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3818 return LLVMBuildInsertElement(builder, samp, samp0,
3819 LLVMConstInt(ctx->i32, 0, 0), "");
3820 }
3821
3822 static void tex_fetch_ptrs(
3823 struct lp_build_tgsi_context *bld_base,
3824 struct lp_build_emit_data *emit_data,
3825 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
3826 {
3827 struct si_shader_context *ctx = si_shader_context(bld_base);
3828 const struct tgsi_full_instruction *inst = emit_data->inst;
3829 unsigned target = inst->Texture.Texture;
3830 unsigned sampler_src;
3831 unsigned sampler_index;
3832
3833 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
3834 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
3835
3836 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
3837 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
3838 LLVMValueRef ind_index;
3839
3840 ind_index = get_bounded_indirect_index(ctx,
3841 &reg->Indirect,
3842 reg->Register.Index,
3843 SI_NUM_SAMPLERS);
3844
3845 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
3846
3847 if (target == TGSI_TEXTURE_2D_MSAA ||
3848 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3849 *samp_ptr = NULL;
3850 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
3851 } else {
3852 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
3853 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3854 *fmask_ptr = NULL;
3855 }
3856 } else {
3857 *res_ptr = ctx->sampler_views[sampler_index];
3858 *samp_ptr = ctx->sampler_states[sampler_index];
3859 *fmask_ptr = ctx->fmasks[sampler_index];
3860 }
3861 }
3862
3863 static void tex_fetch_args(
3864 struct lp_build_tgsi_context *bld_base,
3865 struct lp_build_emit_data *emit_data)
3866 {
3867 struct si_shader_context *ctx = si_shader_context(bld_base);
3868 struct gallivm_state *gallivm = bld_base->base.gallivm;
3869 LLVMBuilderRef builder = gallivm->builder;
3870 const struct tgsi_full_instruction *inst = emit_data->inst;
3871 unsigned opcode = inst->Instruction.Opcode;
3872 unsigned target = inst->Texture.Texture;
3873 LLVMValueRef coords[5], derivs[6];
3874 LLVMValueRef address[16];
3875 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3876 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
3877 unsigned count = 0;
3878 unsigned chan;
3879 unsigned num_deriv_channels = 0;
3880 bool has_offset = inst->Texture.NumOffsets > 0;
3881 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3882 unsigned dmask = 0xf;
3883
3884 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3885
3886 if (opcode == TGSI_OPCODE_TXQ) {
3887 if (target == TGSI_TEXTURE_BUFFER) {
3888 /* Read the size from the buffer descriptor directly. */
3889 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3890 emit_data->args[0] = get_buffer_size(bld_base, res);
3891 return;
3892 }
3893
3894 /* Textures - set the mip level. */
3895 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
3896
3897 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3898 NULL, address, count, 0xf);
3899 return;
3900 }
3901
3902 if (target == TGSI_TEXTURE_BUFFER) {
3903 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3904
3905 /* Bitcast and truncate v8i32 to v16i8. */
3906 LLVMValueRef res = res_ptr;
3907 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
3908 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
3909 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
3910
3911 emit_data->dst_type = ctx->v4f32;
3912 emit_data->args[0] = res;
3913 emit_data->args[1] = bld_base->uint_bld.zero;
3914 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3915 emit_data->arg_count = 3;
3916 return;
3917 }
3918
3919 /* Fetch and project texture coordinates */
3920 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
3921 for (chan = 0; chan < 3; chan++ ) {
3922 coords[chan] = lp_build_emit_fetch(bld_base,
3923 emit_data->inst, 0,
3924 chan);
3925 if (opcode == TGSI_OPCODE_TXP)
3926 coords[chan] = lp_build_emit_llvm_binary(bld_base,
3927 TGSI_OPCODE_DIV,
3928 coords[chan],
3929 coords[3]);
3930 }
3931
3932 if (opcode == TGSI_OPCODE_TXP)
3933 coords[3] = bld_base->base.one;
3934
3935 /* Pack offsets. */
3936 if (has_offset && opcode != TGSI_OPCODE_TXF) {
3937 /* The offsets are six-bit signed integers packed like this:
3938 * X=[5:0], Y=[13:8], and Z=[21:16].
3939 */
3940 LLVMValueRef offset[3], pack;
3941
3942 assert(inst->Texture.NumOffsets == 1);
3943
3944 for (chan = 0; chan < 3; chan++) {
3945 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
3946 emit_data->inst, 0, chan);
3947 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
3948 lp_build_const_int32(gallivm, 0x3f), "");
3949 if (chan)
3950 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
3951 lp_build_const_int32(gallivm, chan*8), "");
3952 }
3953
3954 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
3955 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
3956 address[count++] = pack;
3957 }
3958
3959 /* Pack LOD bias value */
3960 if (opcode == TGSI_OPCODE_TXB)
3961 address[count++] = coords[3];
3962 if (opcode == TGSI_OPCODE_TXB2)
3963 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3964
3965 /* Pack depth comparison value */
3966 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
3967 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
3968 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3969 } else {
3970 assert(ref_pos >= 0);
3971 address[count++] = coords[ref_pos];
3972 }
3973 }
3974
3975 /* Pack user derivatives */
3976 if (opcode == TGSI_OPCODE_TXD) {
3977 int param, num_src_deriv_channels;
3978
3979 switch (target) {
3980 case TGSI_TEXTURE_3D:
3981 num_src_deriv_channels = 3;
3982 num_deriv_channels = 3;
3983 break;
3984 case TGSI_TEXTURE_2D:
3985 case TGSI_TEXTURE_SHADOW2D:
3986 case TGSI_TEXTURE_RECT:
3987 case TGSI_TEXTURE_SHADOWRECT:
3988 case TGSI_TEXTURE_2D_ARRAY:
3989 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3990 num_src_deriv_channels = 2;
3991 num_deriv_channels = 2;
3992 break;
3993 case TGSI_TEXTURE_CUBE:
3994 case TGSI_TEXTURE_SHADOWCUBE:
3995 case TGSI_TEXTURE_CUBE_ARRAY:
3996 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
3997 /* Cube derivatives will be converted to 2D. */
3998 num_src_deriv_channels = 3;
3999 num_deriv_channels = 2;
4000 break;
4001 case TGSI_TEXTURE_1D:
4002 case TGSI_TEXTURE_SHADOW1D:
4003 case TGSI_TEXTURE_1D_ARRAY:
4004 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4005 num_src_deriv_channels = 1;
4006 num_deriv_channels = 1;
4007 break;
4008 default:
4009 unreachable("invalid target");
4010 }
4011
4012 for (param = 0; param < 2; param++)
4013 for (chan = 0; chan < num_src_deriv_channels; chan++)
4014 derivs[param * num_src_deriv_channels + chan] =
4015 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4016 }
4017
4018 if (target == TGSI_TEXTURE_CUBE ||
4019 target == TGSI_TEXTURE_CUBE_ARRAY ||
4020 target == TGSI_TEXTURE_SHADOWCUBE ||
4021 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4022 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4023
4024 if (opcode == TGSI_OPCODE_TXD)
4025 for (int i = 0; i < num_deriv_channels * 2; i++)
4026 address[count++] = derivs[i];
4027
4028 /* Pack texture coordinates */
4029 address[count++] = coords[0];
4030 if (num_coords > 1)
4031 address[count++] = coords[1];
4032 if (num_coords > 2)
4033 address[count++] = coords[2];
4034
4035 /* Pack LOD or sample index */
4036 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4037 address[count++] = coords[3];
4038 else if (opcode == TGSI_OPCODE_TXL2)
4039 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4040
4041 if (count > 16) {
4042 assert(!"Cannot handle more than 16 texture address parameters");
4043 count = 16;
4044 }
4045
4046 for (chan = 0; chan < count; chan++ ) {
4047 address[chan] = LLVMBuildBitCast(gallivm->builder,
4048 address[chan], ctx->i32, "");
4049 }
4050
4051 /* Adjust the sample index according to FMASK.
4052 *
4053 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4054 * which is the identity mapping. Each nibble says which physical sample
4055 * should be fetched to get that sample.
4056 *
4057 * For example, 0x11111100 means there are only 2 samples stored and
4058 * the second sample covers 3/4 of the pixel. When reading samples 0
4059 * and 1, return physical sample 0 (determined by the first two 0s
4060 * in FMASK), otherwise return physical sample 1.
4061 *
4062 * The sample index should be adjusted as follows:
4063 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4064 */
4065 if (target == TGSI_TEXTURE_2D_MSAA ||
4066 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4067 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4068 struct lp_build_emit_data txf_emit_data = *emit_data;
4069 LLVMValueRef txf_address[4];
4070 unsigned txf_count = count;
4071 struct tgsi_full_instruction inst = {};
4072
4073 memcpy(txf_address, address, sizeof(txf_address));
4074
4075 if (target == TGSI_TEXTURE_2D_MSAA) {
4076 txf_address[2] = bld_base->uint_bld.zero;
4077 }
4078 txf_address[3] = bld_base->uint_bld.zero;
4079
4080 /* Read FMASK using TXF. */
4081 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4082 inst.Texture.Texture = target;
4083 txf_emit_data.inst = &inst;
4084 txf_emit_data.chan = 0;
4085 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4086 target, fmask_ptr, NULL,
4087 txf_address, txf_count, 0xf);
4088 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4089
4090 /* Initialize some constants. */
4091 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4092 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4093
4094 /* Apply the formula. */
4095 LLVMValueRef fmask =
4096 LLVMBuildExtractElement(gallivm->builder,
4097 txf_emit_data.output[0],
4098 uint_bld->zero, "");
4099
4100 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4101
4102 LLVMValueRef sample_index4 =
4103 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4104
4105 LLVMValueRef shifted_fmask =
4106 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4107
4108 LLVMValueRef final_sample =
4109 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4110
4111 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4112 * resource descriptor is 0 (invalid),
4113 */
4114 LLVMValueRef fmask_desc =
4115 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4116 ctx->v8i32, "");
4117
4118 LLVMValueRef fmask_word1 =
4119 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4120 uint_bld->one, "");
4121
4122 LLVMValueRef word1_is_nonzero =
4123 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4124 fmask_word1, uint_bld->zero, "");
4125
4126 /* Replace the MSAA sample index. */
4127 address[sample_chan] =
4128 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4129 final_sample, address[sample_chan], "");
4130 }
4131
4132 if (opcode == TGSI_OPCODE_TXF) {
4133 /* add tex offsets */
4134 if (inst->Texture.NumOffsets) {
4135 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4136 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4137 const struct tgsi_texture_offset *off = inst->TexOffsets;
4138
4139 assert(inst->Texture.NumOffsets == 1);
4140
4141 switch (target) {
4142 case TGSI_TEXTURE_3D:
4143 address[2] = lp_build_add(uint_bld, address[2],
4144 bld->immediates[off->Index][off->SwizzleZ]);
4145 /* fall through */
4146 case TGSI_TEXTURE_2D:
4147 case TGSI_TEXTURE_SHADOW2D:
4148 case TGSI_TEXTURE_RECT:
4149 case TGSI_TEXTURE_SHADOWRECT:
4150 case TGSI_TEXTURE_2D_ARRAY:
4151 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4152 address[1] =
4153 lp_build_add(uint_bld, address[1],
4154 bld->immediates[off->Index][off->SwizzleY]);
4155 /* fall through */
4156 case TGSI_TEXTURE_1D:
4157 case TGSI_TEXTURE_SHADOW1D:
4158 case TGSI_TEXTURE_1D_ARRAY:
4159 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4160 address[0] =
4161 lp_build_add(uint_bld, address[0],
4162 bld->immediates[off->Index][off->SwizzleX]);
4163 break;
4164 /* texture offsets do not apply to other texture targets */
4165 }
4166 }
4167 }
4168
4169 if (opcode == TGSI_OPCODE_TG4) {
4170 unsigned gather_comp = 0;
4171
4172 /* DMASK was repurposed for GATHER4. 4 components are always
4173 * returned and DMASK works like a swizzle - it selects
4174 * the component to fetch. The only valid DMASK values are
4175 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4176 * (red,red,red,red) etc.) The ISA document doesn't mention
4177 * this.
4178 */
4179
4180 /* Get the component index from src1.x for Gather4. */
4181 if (!tgsi_is_shadow_target(target)) {
4182 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4183 LLVMValueRef comp_imm;
4184 struct tgsi_src_register src1 = inst->Src[1].Register;
4185
4186 assert(src1.File == TGSI_FILE_IMMEDIATE);
4187
4188 comp_imm = imms[src1.Index][src1.SwizzleX];
4189 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4190 gather_comp = CLAMP(gather_comp, 0, 3);
4191 }
4192
4193 dmask = 1 << gather_comp;
4194 }
4195
4196 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4197 samp_ptr, address, count, dmask);
4198 }
4199
4200 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4201 struct lp_build_tgsi_context *bld_base,
4202 struct lp_build_emit_data *emit_data)
4203 {
4204 struct lp_build_context *base = &bld_base->base;
4205 unsigned opcode = emit_data->inst->Instruction.Opcode;
4206 unsigned target = emit_data->inst->Texture.Texture;
4207 char intr_name[127];
4208 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4209 bool is_shadow = tgsi_is_shadow_target(target);
4210 char type[64];
4211 const char *name = "llvm.SI.image.sample";
4212 const char *infix = "";
4213
4214 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
4215 /* Just return the buffer size. */
4216 emit_data->output[emit_data->chan] = emit_data->args[0];
4217 return;
4218 }
4219
4220 if (target == TGSI_TEXTURE_BUFFER) {
4221 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4222 base->gallivm->builder,
4223 "llvm.SI.vs.load.input", emit_data->dst_type,
4224 emit_data->args, emit_data->arg_count,
4225 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4226 return;
4227 }
4228
4229 switch (opcode) {
4230 case TGSI_OPCODE_TXF:
4231 name = target == TGSI_TEXTURE_2D_MSAA ||
4232 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4233 "llvm.SI.image.load" :
4234 "llvm.SI.image.load.mip";
4235 is_shadow = false;
4236 has_offset = false;
4237 break;
4238 case TGSI_OPCODE_TXQ:
4239 name = "llvm.SI.getresinfo";
4240 is_shadow = false;
4241 has_offset = false;
4242 break;
4243 case TGSI_OPCODE_LODQ:
4244 name = "llvm.SI.getlod";
4245 is_shadow = false;
4246 has_offset = false;
4247 break;
4248 case TGSI_OPCODE_TEX:
4249 case TGSI_OPCODE_TEX2:
4250 case TGSI_OPCODE_TXP:
4251 break;
4252 case TGSI_OPCODE_TXB:
4253 case TGSI_OPCODE_TXB2:
4254 infix = ".b";
4255 break;
4256 case TGSI_OPCODE_TXL:
4257 case TGSI_OPCODE_TXL2:
4258 infix = ".l";
4259 break;
4260 case TGSI_OPCODE_TXD:
4261 infix = ".d";
4262 break;
4263 case TGSI_OPCODE_TG4:
4264 name = "llvm.SI.gather4";
4265 break;
4266 default:
4267 assert(0);
4268 return;
4269 }
4270
4271 /* Add the type and suffixes .c, .o if needed. */
4272 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4273 sprintf(intr_name, "%s%s%s%s.%s",
4274 name, is_shadow ? ".c" : "", infix,
4275 has_offset ? ".o" : "", type);
4276
4277 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4278 base->gallivm->builder, intr_name, emit_data->dst_type,
4279 emit_data->args, emit_data->arg_count,
4280 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4281
4282 /* Divide the number of layers by 6 to get the number of cubes. */
4283 if (opcode == TGSI_OPCODE_TXQ &&
4284 (target == TGSI_TEXTURE_CUBE_ARRAY ||
4285 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
4286 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4287 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4288 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4289
4290 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4291 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4292 z = LLVMBuildSDiv(builder, z, six, "");
4293
4294 emit_data->output[emit_data->chan] =
4295 LLVMBuildInsertElement(builder, v4, z, two, "");
4296 }
4297 }
4298
4299 static void si_llvm_emit_txqs(
4300 const struct lp_build_tgsi_action *action,
4301 struct lp_build_tgsi_context *bld_base,
4302 struct lp_build_emit_data *emit_data)
4303 {
4304 struct si_shader_context *ctx = si_shader_context(bld_base);
4305 struct gallivm_state *gallivm = bld_base->base.gallivm;
4306 LLVMBuilderRef builder = gallivm->builder;
4307 LLVMValueRef res, samples;
4308 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4309
4310 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4311
4312
4313 /* Read the samples from the descriptor directly. */
4314 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4315 samples = LLVMBuildExtractElement(
4316 builder, res,
4317 lp_build_const_int32(gallivm, 3), "");
4318 samples = LLVMBuildLShr(builder, samples,
4319 lp_build_const_int32(gallivm, 16), "");
4320 samples = LLVMBuildAnd(builder, samples,
4321 lp_build_const_int32(gallivm, 0xf), "");
4322 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4323 samples, "");
4324
4325 emit_data->output[emit_data->chan] = samples;
4326 }
4327
4328 /*
4329 * SI implements derivatives using the local data store (LDS)
4330 * All writes to the LDS happen in all executing threads at
4331 * the same time. TID is the Thread ID for the current
4332 * thread and is a value between 0 and 63, representing
4333 * the thread's position in the wavefront.
4334 *
4335 * For the pixel shader threads are grouped into quads of four pixels.
4336 * The TIDs of the pixels of a quad are:
4337 *
4338 * +------+------+
4339 * |4n + 0|4n + 1|
4340 * +------+------+
4341 * |4n + 2|4n + 3|
4342 * +------+------+
4343 *
4344 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4345 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4346 * the current pixel's column, and masking with 0xfffffffe yields the TID
4347 * of the left pixel of the current pixel's row.
4348 *
4349 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4350 * adding 2 yields the TID of the pixel below the top pixel.
4351 */
4352 /* masks for thread ID. */
4353 #define TID_MASK_TOP_LEFT 0xfffffffc
4354 #define TID_MASK_TOP 0xfffffffd
4355 #define TID_MASK_LEFT 0xfffffffe
4356
4357 static void si_llvm_emit_ddxy(
4358 const struct lp_build_tgsi_action *action,
4359 struct lp_build_tgsi_context *bld_base,
4360 struct lp_build_emit_data *emit_data)
4361 {
4362 struct si_shader_context *ctx = si_shader_context(bld_base);
4363 struct gallivm_state *gallivm = bld_base->base.gallivm;
4364 const struct tgsi_full_instruction *inst = emit_data->inst;
4365 unsigned opcode = inst->Instruction.Opcode;
4366 LLVMValueRef indices[2];
4367 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4368 LLVMValueRef tl, trbl, result[4];
4369 unsigned swizzle[4];
4370 unsigned c;
4371 int idx;
4372 unsigned mask;
4373
4374 indices[0] = bld_base->uint_bld.zero;
4375 indices[1] = get_thread_id(ctx);
4376 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4377 indices, 2, "");
4378
4379 if (opcode == TGSI_OPCODE_DDX_FINE)
4380 mask = TID_MASK_LEFT;
4381 else if (opcode == TGSI_OPCODE_DDY_FINE)
4382 mask = TID_MASK_TOP;
4383 else
4384 mask = TID_MASK_TOP_LEFT;
4385
4386 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
4387 lp_build_const_int32(gallivm, mask), "");
4388 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4389 indices, 2, "");
4390
4391 /* for DDX we want to next X pixel, DDY next Y pixel. */
4392 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4393 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
4394 lp_build_const_int32(gallivm, idx), "");
4395 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4396 indices, 2, "");
4397
4398 for (c = 0; c < 4; ++c) {
4399 unsigned i;
4400
4401 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4402 for (i = 0; i < c; ++i) {
4403 if (swizzle[i] == swizzle[c]) {
4404 result[c] = result[i];
4405 break;
4406 }
4407 }
4408 if (i != c)
4409 continue;
4410
4411 LLVMBuildStore(gallivm->builder,
4412 LLVMBuildBitCast(gallivm->builder,
4413 lp_build_emit_fetch(bld_base, inst, 0, c),
4414 ctx->i32, ""),
4415 store_ptr);
4416
4417 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4418 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4419
4420 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4421 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4422
4423 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4424 }
4425
4426 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4427 }
4428
4429 /*
4430 * this takes an I,J coordinate pair,
4431 * and works out the X and Y derivatives.
4432 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4433 */
4434 static LLVMValueRef si_llvm_emit_ddxy_interp(
4435 struct lp_build_tgsi_context *bld_base,
4436 LLVMValueRef interp_ij)
4437 {
4438 struct si_shader_context *ctx = si_shader_context(bld_base);
4439 struct gallivm_state *gallivm = bld_base->base.gallivm;
4440 LLVMValueRef indices[2];
4441 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4442 LLVMValueRef tl, tr, bl, result[4];
4443 unsigned c;
4444
4445 indices[0] = bld_base->uint_bld.zero;
4446 indices[1] = get_thread_id(ctx);
4447 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4448 indices, 2, "");
4449
4450 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4451 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4452
4453 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4454 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4455
4456 indices[1] = temp;
4457 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4458 indices, 2, "");
4459
4460 indices[1] = temp2;
4461 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4462 indices, 2, "");
4463
4464 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4465 lp_build_const_int32(gallivm, 1), "");
4466 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4467 indices, 2, "");
4468
4469 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4470 lp_build_const_int32(gallivm, 2), "");
4471 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4472 indices, 2, "");
4473
4474 for (c = 0; c < 2; ++c) {
4475 LLVMValueRef store_val;
4476 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4477
4478 store_val = LLVMBuildExtractElement(gallivm->builder,
4479 interp_ij, c_ll, "");
4480 LLVMBuildStore(gallivm->builder,
4481 store_val,
4482 store_ptr);
4483
4484 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4485 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4486
4487 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
4488 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
4489
4490 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
4491
4492 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
4493 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4494
4495 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
4496 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
4497
4498 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
4499 }
4500
4501 return lp_build_gather_values(gallivm, result, 4);
4502 }
4503
4504 static void interp_fetch_args(
4505 struct lp_build_tgsi_context *bld_base,
4506 struct lp_build_emit_data *emit_data)
4507 {
4508 struct si_shader_context *ctx = si_shader_context(bld_base);
4509 struct gallivm_state *gallivm = bld_base->base.gallivm;
4510 const struct tgsi_full_instruction *inst = emit_data->inst;
4511
4512 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4513 /* offset is in second src, first two channels */
4514 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4515 emit_data->inst, 1,
4516 TGSI_CHAN_X);
4517 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4518 emit_data->inst, 1,
4519 TGSI_CHAN_Y);
4520 emit_data->arg_count = 2;
4521 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4522 LLVMValueRef sample_position;
4523 LLVMValueRef sample_id;
4524 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4525
4526 /* fetch sample ID, then fetch its sample position,
4527 * and place into first two channels.
4528 */
4529 sample_id = lp_build_emit_fetch(bld_base,
4530 emit_data->inst, 1, TGSI_CHAN_X);
4531 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4532 ctx->i32, "");
4533 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4534
4535 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4536 sample_position,
4537 lp_build_const_int32(gallivm, 0), "");
4538
4539 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4540 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4541 sample_position,
4542 lp_build_const_int32(gallivm, 1), "");
4543 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4544 emit_data->arg_count = 2;
4545 }
4546 }
4547
4548 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4549 struct lp_build_tgsi_context *bld_base,
4550 struct lp_build_emit_data *emit_data)
4551 {
4552 struct si_shader_context *ctx = si_shader_context(bld_base);
4553 struct si_shader *shader = ctx->shader;
4554 struct gallivm_state *gallivm = bld_base->base.gallivm;
4555 LLVMValueRef interp_param;
4556 const struct tgsi_full_instruction *inst = emit_data->inst;
4557 const char *intr_name;
4558 int input_index = inst->Src[0].Register.Index;
4559 int chan;
4560 int i;
4561 LLVMValueRef attr_number;
4562 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
4563 int interp_param_idx;
4564 unsigned interp = shader->selector->info.input_interpolate[input_index];
4565 unsigned location;
4566
4567 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4568
4569 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4570 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4571 location = TGSI_INTERPOLATE_LOC_CENTER;
4572 else
4573 location = TGSI_INTERPOLATE_LOC_CENTROID;
4574
4575 interp_param_idx = lookup_interp_param_index(interp, location);
4576 if (interp_param_idx == -1)
4577 return;
4578 else if (interp_param_idx)
4579 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
4580 else
4581 interp_param = NULL;
4582
4583 attr_number = lp_build_const_int32(gallivm, input_index);
4584
4585 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4586 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4587 LLVMValueRef ij_out[2];
4588 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4589
4590 /*
4591 * take the I then J parameters, and the DDX/Y for it, and
4592 * calculate the IJ inputs for the interpolator.
4593 * temp1 = ddx * offset/sample.x + I;
4594 * interp_param.I = ddy * offset/sample.y + temp1;
4595 * temp1 = ddx * offset/sample.x + J;
4596 * interp_param.J = ddy * offset/sample.y + temp1;
4597 */
4598 for (i = 0; i < 2; i++) {
4599 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
4600 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4601 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4602 ddxy_out, ix_ll, "");
4603 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4604 ddxy_out, iy_ll, "");
4605 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4606 interp_param, ix_ll, "");
4607 LLVMValueRef temp1, temp2;
4608
4609 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4610 ctx->f32, "");
4611
4612 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4613
4614 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4615
4616 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4617
4618 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4619
4620 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
4621 temp2, ctx->i32, "");
4622 }
4623 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4624 }
4625
4626 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4627 for (chan = 0; chan < 2; chan++) {
4628 LLVMValueRef args[4];
4629 LLVMValueRef llvm_chan;
4630 unsigned schan;
4631
4632 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4633 llvm_chan = lp_build_const_int32(gallivm, schan);
4634
4635 args[0] = llvm_chan;
4636 args[1] = attr_number;
4637 args[2] = params;
4638 args[3] = interp_param;
4639
4640 emit_data->output[chan] =
4641 lp_build_intrinsic(gallivm->builder, intr_name,
4642 ctx->f32, args, args[3] ? 4 : 3,
4643 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4644 }
4645 }
4646
4647 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4648 struct lp_build_emit_data *emit_data)
4649 {
4650 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4651 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4652 unsigned stream;
4653
4654 assert(src0.File == TGSI_FILE_IMMEDIATE);
4655
4656 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
4657 return stream;
4658 }
4659
4660 /* Emit one vertex from the geometry shader */
4661 static void si_llvm_emit_vertex(
4662 const struct lp_build_tgsi_action *action,
4663 struct lp_build_tgsi_context *bld_base,
4664 struct lp_build_emit_data *emit_data)
4665 {
4666 struct si_shader_context *ctx = si_shader_context(bld_base);
4667 struct lp_build_context *uint = &bld_base->uint_bld;
4668 struct si_shader *shader = ctx->shader;
4669 struct tgsi_shader_info *info = &shader->selector->info;
4670 struct gallivm_state *gallivm = bld_base->base.gallivm;
4671 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
4672 SI_PARAM_GS2VS_OFFSET);
4673 LLVMValueRef gs_next_vertex;
4674 LLVMValueRef can_emit, kill;
4675 LLVMValueRef args[2];
4676 unsigned chan;
4677 int i;
4678 unsigned stream;
4679
4680 stream = si_llvm_get_stream(bld_base, emit_data);
4681
4682 /* Write vertex attribute values to GSVS ring */
4683 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
4684 ctx->gs_next_vertex[stream],
4685 "");
4686
4687 /* If this thread has already emitted the declared maximum number of
4688 * vertices, kill it: excessive vertex emissions are not supposed to
4689 * have any effect, and GS threads have no externally observable
4690 * effects other than emitting vertices.
4691 */
4692 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
4693 lp_build_const_int32(gallivm,
4694 shader->selector->gs_max_out_vertices), "");
4695 kill = lp_build_select(&bld_base->base, can_emit,
4696 lp_build_const_float(gallivm, 1.0f),
4697 lp_build_const_float(gallivm, -1.0f));
4698
4699 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4700 ctx->voidt, &kill, 1, 0);
4701
4702 for (i = 0; i < info->num_outputs; i++) {
4703 LLVMValueRef *out_ptr =
4704 ctx->radeon_bld.soa.outputs[i];
4705
4706 for (chan = 0; chan < 4; chan++) {
4707 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
4708 LLVMValueRef voffset =
4709 lp_build_const_int32(gallivm, (i * 4 + chan) *
4710 shader->selector->gs_max_out_vertices);
4711
4712 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4713 voffset = lp_build_mul_imm(uint, voffset, 4);
4714
4715 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
4716
4717 build_tbuffer_store(ctx,
4718 ctx->gsvs_ring[stream],
4719 out_val, 1,
4720 voffset, soffset, 0,
4721 V_008F0C_BUF_DATA_FORMAT_32,
4722 V_008F0C_BUF_NUM_FORMAT_UINT,
4723 1, 0, 1, 1, 0);
4724 }
4725 }
4726 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4727 lp_build_const_int32(gallivm, 1));
4728
4729 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4730
4731 /* Signal vertex emission */
4732 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
4733 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4734 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4735 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4736 }
4737
4738 /* Cut one primitive from the geometry shader */
4739 static void si_llvm_emit_primitive(
4740 const struct lp_build_tgsi_action *action,
4741 struct lp_build_tgsi_context *bld_base,
4742 struct lp_build_emit_data *emit_data)
4743 {
4744 struct si_shader_context *ctx = si_shader_context(bld_base);
4745 struct gallivm_state *gallivm = bld_base->base.gallivm;
4746 LLVMValueRef args[2];
4747 unsigned stream;
4748
4749 /* Signal primitive cut */
4750 stream = si_llvm_get_stream(bld_base, emit_data);
4751 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
4752 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4753 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4754 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4755 }
4756
4757 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4758 struct lp_build_tgsi_context *bld_base,
4759 struct lp_build_emit_data *emit_data)
4760 {
4761 struct si_shader_context *ctx = si_shader_context(bld_base);
4762 struct gallivm_state *gallivm = bld_base->base.gallivm;
4763
4764 /* The real barrier instruction isn’t needed, because an entire patch
4765 * always fits into a single wave.
4766 */
4767 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4768 emit_optimization_barrier(ctx);
4769 return;
4770 }
4771
4772 lp_build_intrinsic(gallivm->builder,
4773 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
4774 : "llvm.AMDGPU.barrier.local",
4775 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
4776 }
4777
4778 static const struct lp_build_tgsi_action tex_action = {
4779 .fetch_args = tex_fetch_args,
4780 .emit = build_tex_intrinsic,
4781 };
4782
4783 static const struct lp_build_tgsi_action interp_action = {
4784 .fetch_args = interp_fetch_args,
4785 .emit = build_interp_intrinsic,
4786 };
4787
4788 static void si_create_function(struct si_shader_context *ctx,
4789 LLVMTypeRef *returns, unsigned num_returns,
4790 LLVMTypeRef *params, unsigned num_params,
4791 int last_array_pointer, int last_sgpr)
4792 {
4793 int i;
4794
4795 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
4796 params, num_params);
4797 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
4798 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
4799
4800 for (i = 0; i <= last_sgpr; ++i) {
4801 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
4802
4803 /* We tell llvm that array inputs are passed by value to allow Sinking pass
4804 * to move load. Inputs are constant so this is fine. */
4805 if (i <= last_array_pointer)
4806 LLVMAddAttribute(P, LLVMByValAttribute);
4807 else
4808 LLVMAddAttribute(P, LLVMInRegAttribute);
4809 }
4810 }
4811
4812 static void create_meta_data(struct si_shader_context *ctx)
4813 {
4814 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
4815 LLVMValueRef args[3];
4816
4817 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
4818 args[1] = 0;
4819 args[2] = lp_build_const_int32(gallivm, 1);
4820
4821 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
4822 }
4823
4824 static void declare_streamout_params(struct si_shader_context *ctx,
4825 struct pipe_stream_output_info *so,
4826 LLVMTypeRef *params, LLVMTypeRef i32,
4827 unsigned *num_params)
4828 {
4829 int i;
4830
4831 /* Streamout SGPRs. */
4832 if (so->num_outputs) {
4833 params[ctx->param_streamout_config = (*num_params)++] = i32;
4834 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
4835 }
4836 /* A streamout buffer offset is loaded if the stride is non-zero. */
4837 for (i = 0; i < 4; i++) {
4838 if (!so->stride[i])
4839 continue;
4840
4841 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
4842 }
4843 }
4844
4845 static unsigned llvm_get_type_size(LLVMTypeRef type)
4846 {
4847 LLVMTypeKind kind = LLVMGetTypeKind(type);
4848
4849 switch (kind) {
4850 case LLVMIntegerTypeKind:
4851 return LLVMGetIntTypeWidth(type) / 8;
4852 case LLVMFloatTypeKind:
4853 return 4;
4854 case LLVMPointerTypeKind:
4855 return 8;
4856 case LLVMVectorTypeKind:
4857 return LLVMGetVectorSize(type) *
4858 llvm_get_type_size(LLVMGetElementType(type));
4859 default:
4860 assert(0);
4861 return 0;
4862 }
4863 }
4864
4865 static void declare_tess_lds(struct si_shader_context *ctx)
4866 {
4867 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4868 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
4869
4870 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
4871 unsigned vertex_data_dw_size = 32*32*4;
4872 unsigned patch_data_dw_size = 32*4;
4873 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
4874 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
4875 unsigned lds_dwords = patch_dw_size;
4876
4877 /* The actual size is computed outside of the shader to reduce
4878 * the number of shader variants. */
4879 ctx->lds =
4880 LLVMAddGlobalInAddressSpace(gallivm->module,
4881 LLVMArrayType(i32, lds_dwords),
4882 "tess_lds",
4883 LOCAL_ADDR_SPACE);
4884 }
4885
4886 static void create_function(struct si_shader_context *ctx)
4887 {
4888 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4889 struct gallivm_state *gallivm = bld_base->base.gallivm;
4890 struct si_shader *shader = ctx->shader;
4891 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
4892 LLVMTypeRef returns[16+32*4];
4893 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
4894 unsigned num_returns = 0;
4895
4896 v3i32 = LLVMVectorType(ctx->i32, 3);
4897
4898 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
4899 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
4900 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
4901 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
4902 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
4903 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
4904
4905 switch (ctx->type) {
4906 case PIPE_SHADER_VERTEX:
4907 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
4908 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
4909 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
4910 params[SI_PARAM_START_INSTANCE] = ctx->i32;
4911 num_params = SI_PARAM_START_INSTANCE+1;
4912
4913 if (shader->key.vs.as_es) {
4914 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4915 } else if (shader->key.vs.as_ls) {
4916 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
4917 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
4918 } else {
4919 if (ctx->is_gs_copy_shader) {
4920 last_array_pointer = SI_PARAM_RW_BUFFERS;
4921 num_params = SI_PARAM_RW_BUFFERS+1;
4922 } else {
4923 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
4924 num_params = SI_PARAM_VS_STATE_BITS+1;
4925 }
4926
4927 /* The locations of the other parameters are assigned dynamically. */
4928 declare_streamout_params(ctx, &shader->selector->so,
4929 params, ctx->i32, &num_params);
4930 }
4931
4932 last_sgpr = num_params-1;
4933
4934 /* VGPRs */
4935 params[ctx->param_vertex_id = num_params++] = ctx->i32;
4936 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
4937 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
4938 params[ctx->param_instance_id = num_params++] = ctx->i32;
4939
4940 if (!ctx->is_monolithic &&
4941 !ctx->is_gs_copy_shader) {
4942 /* Vertex load indices. */
4943 ctx->param_vertex_index0 = num_params;
4944
4945 for (i = 0; i < shader->selector->info.num_inputs; i++)
4946 params[num_params++] = ctx->i32;
4947
4948 /* PrimitiveID output. */
4949 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
4950 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4951 returns[num_returns++] = ctx->f32;
4952 }
4953 break;
4954
4955 case PIPE_SHADER_TESS_CTRL:
4956 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4957 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4958 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
4959 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
4960 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
4961
4962 /* VGPRs */
4963 params[SI_PARAM_PATCH_ID] = ctx->i32;
4964 params[SI_PARAM_REL_IDS] = ctx->i32;
4965 num_params = SI_PARAM_REL_IDS+1;
4966
4967 if (!ctx->is_monolithic) {
4968 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
4969 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
4970 returns[num_returns++] = ctx->i32; /* SGPRs */
4971
4972 for (i = 0; i < 3; i++)
4973 returns[num_returns++] = ctx->f32; /* VGPRs */
4974 }
4975 break;
4976
4977 case PIPE_SHADER_TESS_EVAL:
4978 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4979 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4980 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
4981
4982 if (shader->key.tes.as_es) {
4983 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4984 } else {
4985 declare_streamout_params(ctx, &shader->selector->so,
4986 params, ctx->i32, &num_params);
4987 }
4988 last_sgpr = num_params - 1;
4989
4990 /* VGPRs */
4991 params[ctx->param_tes_u = num_params++] = ctx->f32;
4992 params[ctx->param_tes_v = num_params++] = ctx->f32;
4993 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
4994 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
4995
4996 /* PrimitiveID output. */
4997 if (!ctx->is_monolithic && !shader->key.tes.as_es)
4998 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4999 returns[num_returns++] = ctx->f32;
5000 break;
5001
5002 case PIPE_SHADER_GEOMETRY:
5003 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5004 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5005 last_sgpr = SI_PARAM_GS_WAVE_ID;
5006
5007 /* VGPRs */
5008 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5009 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5010 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5011 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5012 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5013 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5014 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5015 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5016 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5017 break;
5018
5019 case PIPE_SHADER_FRAGMENT:
5020 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5021 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5022 last_sgpr = SI_PARAM_PRIM_MASK;
5023 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5024 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5025 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5026 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5027 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5028 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5029 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5030 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5031 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5032 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5033 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5034 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5035 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5036 params[SI_PARAM_ANCILLARY] = ctx->i32;
5037 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5038 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5039 num_params = SI_PARAM_POS_FIXED_PT+1;
5040
5041 if (!ctx->is_monolithic) {
5042 /* Color inputs from the prolog. */
5043 if (shader->selector->info.colors_read) {
5044 unsigned num_color_elements =
5045 util_bitcount(shader->selector->info.colors_read);
5046
5047 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5048 for (i = 0; i < num_color_elements; i++)
5049 params[num_params++] = ctx->f32;
5050 }
5051
5052 /* Outputs for the epilog. */
5053 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5054 num_returns =
5055 num_return_sgprs +
5056 util_bitcount(shader->selector->info.colors_written) * 4 +
5057 shader->selector->info.writes_z +
5058 shader->selector->info.writes_stencil +
5059 shader->selector->info.writes_samplemask +
5060 1 /* SampleMaskIn */;
5061
5062 num_returns = MAX2(num_returns,
5063 num_return_sgprs +
5064 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5065
5066 for (i = 0; i < num_return_sgprs; i++)
5067 returns[i] = ctx->i32;
5068 for (; i < num_returns; i++)
5069 returns[i] = ctx->f32;
5070 }
5071 break;
5072
5073 case PIPE_SHADER_COMPUTE:
5074 params[SI_PARAM_GRID_SIZE] = v3i32;
5075 params[SI_PARAM_BLOCK_ID] = v3i32;
5076 last_sgpr = SI_PARAM_BLOCK_ID;
5077
5078 params[SI_PARAM_THREAD_ID] = v3i32;
5079 num_params = SI_PARAM_THREAD_ID + 1;
5080 break;
5081 default:
5082 assert(0 && "unimplemented shader");
5083 return;
5084 }
5085
5086 assert(num_params <= Elements(params));
5087
5088 si_create_function(ctx, returns, num_returns, params,
5089 num_params, last_array_pointer, last_sgpr);
5090
5091 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5092 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5093 !ctx->is_monolithic) {
5094 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5095 "InitialPSInputAddr",
5096 S_0286D0_PERSP_SAMPLE_ENA(1) |
5097 S_0286D0_PERSP_CENTER_ENA(1) |
5098 S_0286D0_PERSP_CENTROID_ENA(1) |
5099 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5100 S_0286D0_LINEAR_CENTER_ENA(1) |
5101 S_0286D0_LINEAR_CENTROID_ENA(1) |
5102 S_0286D0_FRONT_FACE_ENA(1) |
5103 S_0286D0_POS_FIXED_PT_ENA(1));
5104 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5105 const unsigned *properties = shader->selector->info.properties;
5106 unsigned max_work_group_size =
5107 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5108 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5109 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5110
5111 assert(max_work_group_size);
5112
5113 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5114 "amdgpu-max-work-group-size",
5115 max_work_group_size);
5116 }
5117
5118 shader->info.num_input_sgprs = 0;
5119 shader->info.num_input_vgprs = 0;
5120
5121 for (i = 0; i <= last_sgpr; ++i)
5122 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5123
5124 /* Unused fragment shader inputs are eliminated by the compiler,
5125 * so we don't know yet how many there will be.
5126 */
5127 if (ctx->type != PIPE_SHADER_FRAGMENT)
5128 for (; i < num_params; ++i)
5129 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5130
5131 if (bld_base->info &&
5132 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5133 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5134 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5135 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5136 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5137 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5138 ctx->lds =
5139 LLVMAddGlobalInAddressSpace(gallivm->module,
5140 LLVMArrayType(ctx->i32, 64),
5141 "ddxy_lds",
5142 LOCAL_ADDR_SPACE);
5143
5144 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5145 ctx->type == PIPE_SHADER_TESS_CTRL ||
5146 ctx->type == PIPE_SHADER_TESS_EVAL)
5147 declare_tess_lds(ctx);
5148 }
5149
5150 static void preload_constants(struct si_shader_context *ctx)
5151 {
5152 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5153 struct gallivm_state *gallivm = bld_base->base.gallivm;
5154 const struct tgsi_shader_info *info = bld_base->info;
5155 unsigned buf;
5156 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5157
5158 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5159 unsigned i, num_const = info->const_file_max[buf] + 1;
5160
5161 if (num_const == 0)
5162 continue;
5163
5164 /* Allocate space for the constant values */
5165 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5166
5167 /* Load the resource descriptor */
5168 ctx->const_buffers[buf] =
5169 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5170
5171 /* Load the constants, we rely on the code sinking to do the rest */
5172 for (i = 0; i < num_const * 4; ++i) {
5173 ctx->constants[buf][i] =
5174 buffer_load_const(gallivm->builder,
5175 ctx->const_buffers[buf],
5176 lp_build_const_int32(gallivm, i * 4),
5177 ctx->f32);
5178 }
5179 }
5180 }
5181
5182 static void preload_shader_buffers(struct si_shader_context *ctx)
5183 {
5184 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5185 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5186 int buf, maxbuf;
5187
5188 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5189 SI_NUM_SHADER_BUFFERS - 1);
5190 for (buf = 0; buf <= maxbuf; ++buf) {
5191 ctx->shader_buffers[buf] =
5192 build_indexed_load_const(
5193 ctx, ptr, lp_build_const_int32(gallivm, buf));
5194 }
5195 }
5196
5197 static void preload_samplers(struct si_shader_context *ctx)
5198 {
5199 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5200 struct gallivm_state *gallivm = bld_base->base.gallivm;
5201 const struct tgsi_shader_info *info = bld_base->info;
5202 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5203 LLVMValueRef offset;
5204
5205 if (num_samplers == 0)
5206 return;
5207
5208 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5209 for (i = 0; i < num_samplers; ++i) {
5210 /* Resource */
5211 offset = lp_build_const_int32(gallivm, i);
5212 ctx->sampler_views[i] =
5213 get_sampler_desc(ctx, offset, DESC_IMAGE);
5214
5215 /* FMASK resource */
5216 if (info->is_msaa_sampler[i])
5217 ctx->fmasks[i] =
5218 get_sampler_desc(ctx, offset, DESC_FMASK);
5219 else {
5220 ctx->sampler_states[i] =
5221 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5222 ctx->sampler_states[i] =
5223 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5224 ctx->sampler_states[i]);
5225 }
5226 }
5227 }
5228
5229 static void preload_images(struct si_shader_context *ctx)
5230 {
5231 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5232 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5233 struct gallivm_state *gallivm = bld_base->base.gallivm;
5234 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5235 LLVMValueRef res_ptr;
5236 unsigned i;
5237
5238 if (num_images == 0)
5239 return;
5240
5241 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5242
5243 for (i = 0; i < num_images; ++i) {
5244 /* Rely on LLVM to shrink the load for buffer resources. */
5245 LLVMValueRef rsrc =
5246 build_indexed_load_const(ctx, res_ptr,
5247 lp_build_const_int32(gallivm, i));
5248
5249 if (info->images_writemask & (1 << i) &&
5250 !(info->images_buffers & (1 << i)))
5251 rsrc = force_dcc_off(ctx, rsrc);
5252
5253 ctx->images[i] = rsrc;
5254 }
5255 }
5256
5257 static void preload_streamout_buffers(struct si_shader_context *ctx)
5258 {
5259 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5260 struct gallivm_state *gallivm = bld_base->base.gallivm;
5261 unsigned i;
5262
5263 /* Streamout can only be used if the shader is compiled as VS. */
5264 if (!ctx->shader->selector->so.num_outputs ||
5265 (ctx->type == PIPE_SHADER_VERTEX &&
5266 (ctx->shader->key.vs.as_es ||
5267 ctx->shader->key.vs.as_ls)) ||
5268 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5269 ctx->shader->key.tes.as_es))
5270 return;
5271
5272 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5273 SI_PARAM_RW_BUFFERS);
5274
5275 /* Load the resources, we rely on the code sinking to do the rest */
5276 for (i = 0; i < 4; ++i) {
5277 if (ctx->shader->selector->so.stride[i]) {
5278 LLVMValueRef offset = lp_build_const_int32(gallivm,
5279 SI_VS_STREAMOUT_BUF0 + i);
5280
5281 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5282 }
5283 }
5284 }
5285
5286 /**
5287 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5288 * for later use.
5289 */
5290 static void preload_ring_buffers(struct si_shader_context *ctx)
5291 {
5292 struct gallivm_state *gallivm =
5293 ctx->radeon_bld.soa.bld_base.base.gallivm;
5294
5295 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5296 SI_PARAM_RW_BUFFERS);
5297
5298 if ((ctx->type == PIPE_SHADER_VERTEX &&
5299 ctx->shader->key.vs.as_es) ||
5300 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5301 ctx->shader->key.tes.as_es) ||
5302 ctx->type == PIPE_SHADER_GEOMETRY) {
5303 unsigned ring =
5304 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5305 : SI_ES_RING_ESGS;
5306 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5307
5308 ctx->esgs_ring =
5309 build_indexed_load_const(ctx, buf_ptr, offset);
5310 }
5311
5312 if (ctx->is_gs_copy_shader) {
5313 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5314
5315 ctx->gsvs_ring[0] =
5316 build_indexed_load_const(ctx, buf_ptr, offset);
5317 }
5318 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5319 int i;
5320 for (i = 0; i < 4; i++) {
5321 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5322
5323 ctx->gsvs_ring[i] =
5324 build_indexed_load_const(ctx, buf_ptr, offset);
5325 }
5326 }
5327 }
5328
5329 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5330 LLVMValueRef param_rw_buffers,
5331 unsigned param_pos_fixed_pt)
5332 {
5333 struct lp_build_tgsi_context *bld_base =
5334 &ctx->radeon_bld.soa.bld_base;
5335 struct gallivm_state *gallivm = bld_base->base.gallivm;
5336 LLVMBuilderRef builder = gallivm->builder;
5337 LLVMValueRef slot, desc, offset, row, bit, address[2];
5338
5339 /* Use the fixed-point gl_FragCoord input.
5340 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5341 * per coordinate to get the repeating effect.
5342 */
5343 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5344 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5345
5346 /* Load the buffer descriptor. */
5347 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5348 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5349
5350 /* The stipple pattern is 32x32, each row has 32 bits. */
5351 offset = LLVMBuildMul(builder, address[1],
5352 LLVMConstInt(ctx->i32, 4, 0), "");
5353 row = buffer_load_const(builder, desc, offset, ctx->i32);
5354 bit = LLVMBuildLShr(builder, row, address[0], "");
5355 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5356
5357 /* The intrinsic kills the thread if arg < 0. */
5358 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5359 LLVMConstReal(ctx->f32, -1), "");
5360 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5361 }
5362
5363 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5364 struct si_shader_config *conf,
5365 unsigned symbol_offset)
5366 {
5367 unsigned i;
5368 const unsigned char *config =
5369 radeon_shader_binary_config_start(binary, symbol_offset);
5370
5371 /* XXX: We may be able to emit some of these values directly rather than
5372 * extracting fields to be emitted later.
5373 */
5374
5375 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5376 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5377 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5378 switch (reg) {
5379 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5380 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5381 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5382 case R_00B848_COMPUTE_PGM_RSRC1:
5383 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5384 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5385 conf->float_mode = G_00B028_FLOAT_MODE(value);
5386 conf->rsrc1 = value;
5387 break;
5388 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5389 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5390 break;
5391 case R_00B84C_COMPUTE_PGM_RSRC2:
5392 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5393 conf->rsrc2 = value;
5394 break;
5395 case R_0286CC_SPI_PS_INPUT_ENA:
5396 conf->spi_ps_input_ena = value;
5397 break;
5398 case R_0286D0_SPI_PS_INPUT_ADDR:
5399 conf->spi_ps_input_addr = value;
5400 break;
5401 case R_0286E8_SPI_TMPRING_SIZE:
5402 case R_00B860_COMPUTE_TMPRING_SIZE:
5403 /* WAVESIZE is in units of 256 dwords. */
5404 conf->scratch_bytes_per_wave =
5405 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
5406 break;
5407 default:
5408 {
5409 static bool printed;
5410
5411 if (!printed) {
5412 fprintf(stderr, "Warning: LLVM emitted unknown "
5413 "config register: 0x%x\n", reg);
5414 printed = true;
5415 }
5416 }
5417 break;
5418 }
5419
5420 if (!conf->spi_ps_input_addr)
5421 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5422 }
5423 }
5424
5425 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5426 struct si_shader *shader,
5427 struct si_shader_config *config,
5428 uint64_t scratch_va)
5429 {
5430 unsigned i;
5431 uint32_t scratch_rsrc_dword0 = scratch_va;
5432 uint32_t scratch_rsrc_dword1 =
5433 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
5434 | S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5435
5436 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5437 const struct radeon_shader_reloc *reloc =
5438 &shader->binary.relocs[i];
5439 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5440 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5441 &scratch_rsrc_dword0, 4);
5442 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5443 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5444 &scratch_rsrc_dword1, 4);
5445 }
5446 }
5447 }
5448
5449 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5450 {
5451 unsigned size = shader->binary.code_size;
5452
5453 if (shader->prolog)
5454 size += shader->prolog->binary.code_size;
5455 if (shader->epilog)
5456 size += shader->epilog->binary.code_size;
5457 return size;
5458 }
5459
5460 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5461 {
5462 const struct radeon_shader_binary *prolog =
5463 shader->prolog ? &shader->prolog->binary : NULL;
5464 const struct radeon_shader_binary *epilog =
5465 shader->epilog ? &shader->epilog->binary : NULL;
5466 const struct radeon_shader_binary *mainb = &shader->binary;
5467 unsigned bo_size = si_get_shader_binary_size(shader) +
5468 (!epilog ? mainb->rodata_size : 0);
5469 unsigned char *ptr;
5470
5471 assert(!prolog || !prolog->rodata_size);
5472 assert((!prolog && !epilog) || !mainb->rodata_size);
5473 assert(!epilog || !epilog->rodata_size);
5474
5475 r600_resource_reference(&shader->bo, NULL);
5476 shader->bo = si_resource_create_custom(&sscreen->b.b,
5477 PIPE_USAGE_IMMUTABLE,
5478 bo_size);
5479 if (!shader->bo)
5480 return -ENOMEM;
5481
5482 /* Upload. */
5483 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5484 PIPE_TRANSFER_READ_WRITE);
5485
5486 if (prolog) {
5487 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5488 ptr += prolog->code_size;
5489 }
5490
5491 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5492 ptr += mainb->code_size;
5493
5494 if (epilog)
5495 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5496 else if (mainb->rodata_size > 0)
5497 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5498
5499 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5500 return 0;
5501 }
5502
5503 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5504 struct pipe_debug_callback *debug,
5505 const char *name, FILE *file)
5506 {
5507 char *line, *p;
5508 unsigned i, count;
5509
5510 if (binary->disasm_string) {
5511 fprintf(file, "Shader %s disassembly:\n", name);
5512 fprintf(file, "%s", binary->disasm_string);
5513
5514 if (debug && debug->debug_message) {
5515 /* Very long debug messages are cut off, so send the
5516 * disassembly one line at a time. This causes more
5517 * overhead, but on the plus side it simplifies
5518 * parsing of resulting logs.
5519 */
5520 pipe_debug_message(debug, SHADER_INFO,
5521 "Shader Disassembly Begin");
5522
5523 line = binary->disasm_string;
5524 while (*line) {
5525 p = util_strchrnul(line, '\n');
5526 count = p - line;
5527
5528 if (count) {
5529 pipe_debug_message(debug, SHADER_INFO,
5530 "%.*s", count, line);
5531 }
5532
5533 if (!*p)
5534 break;
5535 line = p + 1;
5536 }
5537
5538 pipe_debug_message(debug, SHADER_INFO,
5539 "Shader Disassembly End");
5540 }
5541 } else {
5542 fprintf(file, "Shader %s binary:\n", name);
5543 for (i = 0; i < binary->code_size; i += 4) {
5544 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5545 binary->code[i + 3], binary->code[i + 2],
5546 binary->code[i + 1], binary->code[i]);
5547 }
5548 }
5549 }
5550
5551 static void si_shader_dump_stats(struct si_screen *sscreen,
5552 struct si_shader_config *conf,
5553 unsigned num_inputs,
5554 unsigned code_size,
5555 struct pipe_debug_callback *debug,
5556 unsigned processor,
5557 FILE *file)
5558 {
5559 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5560 unsigned lds_per_wave = 0;
5561 unsigned max_simd_waves = 10;
5562
5563 /* Compute LDS usage for PS. */
5564 if (processor == PIPE_SHADER_FRAGMENT) {
5565 /* The minimum usage per wave is (num_inputs * 36). The maximum
5566 * usage is (num_inputs * 36 * 16).
5567 * We can get anything in between and it varies between waves.
5568 *
5569 * Other stages don't know the size at compile time or don't
5570 * allocate LDS per wave, but instead they do it per thread group.
5571 */
5572 lds_per_wave = conf->lds_size * lds_increment +
5573 align(num_inputs * 36, lds_increment);
5574 }
5575
5576 /* Compute the per-SIMD wave counts. */
5577 if (conf->num_sgprs) {
5578 if (sscreen->b.chip_class >= VI)
5579 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5580 else
5581 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5582 }
5583
5584 if (conf->num_vgprs)
5585 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5586
5587 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5588 * that PS can use.
5589 */
5590 if (lds_per_wave)
5591 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5592
5593 if (file != stderr ||
5594 r600_can_dump_shader(&sscreen->b, processor)) {
5595 if (processor == PIPE_SHADER_FRAGMENT) {
5596 fprintf(file, "*** SHADER CONFIG ***\n"
5597 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5598 "SPI_PS_INPUT_ENA = 0x%04x\n",
5599 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5600 }
5601
5602 fprintf(file, "*** SHADER STATS ***\n"
5603 "SGPRS: %d\n"
5604 "VGPRS: %d\n"
5605 "Code Size: %d bytes\n"
5606 "LDS: %d blocks\n"
5607 "Scratch: %d bytes per wave\n"
5608 "Max Waves: %d\n"
5609 "********************\n",
5610 conf->num_sgprs, conf->num_vgprs, code_size,
5611 conf->lds_size, conf->scratch_bytes_per_wave,
5612 max_simd_waves);
5613 }
5614
5615 pipe_debug_message(debug, SHADER_INFO,
5616 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5617 "LDS: %d Scratch: %d Max Waves: %d",
5618 conf->num_sgprs, conf->num_vgprs, code_size,
5619 conf->lds_size, conf->scratch_bytes_per_wave,
5620 max_simd_waves);
5621 }
5622
5623 static const char *si_get_shader_name(struct si_shader *shader,
5624 unsigned processor)
5625 {
5626 switch (processor) {
5627 case PIPE_SHADER_VERTEX:
5628 if (shader->key.vs.as_es)
5629 return "Vertex Shader as ES";
5630 else if (shader->key.vs.as_ls)
5631 return "Vertex Shader as LS";
5632 else
5633 return "Vertex Shader as VS";
5634 case PIPE_SHADER_TESS_CTRL:
5635 return "Tessellation Control Shader";
5636 case PIPE_SHADER_TESS_EVAL:
5637 if (shader->key.tes.as_es)
5638 return "Tessellation Evaluation Shader as ES";
5639 else
5640 return "Tessellation Evaluation Shader as VS";
5641 case PIPE_SHADER_GEOMETRY:
5642 if (shader->gs_copy_shader == NULL)
5643 return "GS Copy Shader as VS";
5644 else
5645 return "Geometry Shader";
5646 case PIPE_SHADER_FRAGMENT:
5647 return "Pixel Shader";
5648 case PIPE_SHADER_COMPUTE:
5649 return "Compute Shader";
5650 default:
5651 return "Unknown Shader";
5652 }
5653 }
5654
5655 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5656 struct pipe_debug_callback *debug, unsigned processor,
5657 FILE *file)
5658 {
5659 if (file != stderr ||
5660 (r600_can_dump_shader(&sscreen->b, processor) &&
5661 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5662 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5663
5664 if (shader->prolog)
5665 si_shader_dump_disassembly(&shader->prolog->binary,
5666 debug, "prolog", file);
5667
5668 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5669
5670 if (shader->epilog)
5671 si_shader_dump_disassembly(&shader->epilog->binary,
5672 debug, "epilog", file);
5673 fprintf(file, "\n");
5674 }
5675
5676 si_shader_dump_stats(sscreen, &shader->config,
5677 shader->selector ? shader->selector->info.num_inputs : 0,
5678 si_get_shader_binary_size(shader), debug, processor,
5679 file);
5680 }
5681
5682 int si_compile_llvm(struct si_screen *sscreen,
5683 struct radeon_shader_binary *binary,
5684 struct si_shader_config *conf,
5685 LLVMTargetMachineRef tm,
5686 LLVMModuleRef mod,
5687 struct pipe_debug_callback *debug,
5688 unsigned processor,
5689 const char *name)
5690 {
5691 int r = 0;
5692 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5693
5694 if (r600_can_dump_shader(&sscreen->b, processor)) {
5695 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5696
5697 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5698 fprintf(stderr, "%s LLVM IR:\n\n", name);
5699 LLVMDumpModule(mod);
5700 fprintf(stderr, "\n");
5701 }
5702 }
5703
5704 if (!si_replace_shader(count, binary)) {
5705 r = radeon_llvm_compile(mod, binary,
5706 r600_get_llvm_processor_name(sscreen->b.family), tm,
5707 debug);
5708 if (r)
5709 return r;
5710 }
5711
5712 si_shader_binary_read_config(binary, conf, 0);
5713
5714 /* Enable 64-bit and 16-bit denormals, because there is no performance
5715 * cost.
5716 *
5717 * If denormals are enabled, all floating-point output modifiers are
5718 * ignored.
5719 *
5720 * Don't enable denormals for 32-bit floats, because:
5721 * - Floating-point output modifiers would be ignored by the hw.
5722 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5723 * have to stop using those.
5724 * - SI & CI would be very slow.
5725 */
5726 conf->float_mode |= V_00B028_FP_64_DENORMS;
5727
5728 FREE(binary->config);
5729 FREE(binary->global_symbol_offsets);
5730 binary->config = NULL;
5731 binary->global_symbol_offsets = NULL;
5732
5733 /* Some shaders can't have rodata because their binaries can be
5734 * concatenated.
5735 */
5736 if (binary->rodata_size &&
5737 (processor == PIPE_SHADER_VERTEX ||
5738 processor == PIPE_SHADER_TESS_CTRL ||
5739 processor == PIPE_SHADER_TESS_EVAL ||
5740 processor == PIPE_SHADER_FRAGMENT)) {
5741 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5742 return -EINVAL;
5743 }
5744
5745 return r;
5746 }
5747
5748 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5749 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
5750 struct si_shader_context *ctx,
5751 struct si_shader *gs,
5752 struct pipe_debug_callback *debug)
5753 {
5754 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5755 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5756 struct lp_build_context *uint = &bld_base->uint_bld;
5757 struct si_shader_output_values *outputs;
5758 struct tgsi_shader_info *gsinfo = &gs->selector->info;
5759 LLVMValueRef args[9];
5760 int i, r;
5761
5762 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5763
5764 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
5765 ctx->type = PIPE_SHADER_VERTEX;
5766 ctx->is_gs_copy_shader = true;
5767
5768 create_meta_data(ctx);
5769 create_function(ctx);
5770 preload_streamout_buffers(ctx);
5771 preload_ring_buffers(ctx);
5772
5773 args[0] = ctx->gsvs_ring[0];
5774 args[1] = lp_build_mul_imm(uint,
5775 LLVMGetParam(ctx->radeon_bld.main_fn,
5776 ctx->param_vertex_id),
5777 4);
5778 args[3] = uint->zero;
5779 args[4] = uint->one; /* OFFEN */
5780 args[5] = uint->zero; /* IDXEN */
5781 args[6] = uint->one; /* GLC */
5782 args[7] = uint->one; /* SLC */
5783 args[8] = uint->zero; /* TFE */
5784
5785 /* Fetch vertex data from GSVS ring */
5786 for (i = 0; i < gsinfo->num_outputs; ++i) {
5787 unsigned chan;
5788
5789 outputs[i].name = gsinfo->output_semantic_name[i];
5790 outputs[i].sid = gsinfo->output_semantic_index[i];
5791
5792 for (chan = 0; chan < 4; chan++) {
5793 args[2] = lp_build_const_int32(gallivm,
5794 (i * 4 + chan) *
5795 gs->selector->gs_max_out_vertices * 16 * 4);
5796
5797 outputs[i].values[chan] =
5798 LLVMBuildBitCast(gallivm->builder,
5799 lp_build_intrinsic(gallivm->builder,
5800 "llvm.SI.buffer.load.dword.i32.i32",
5801 ctx->i32, args, 9,
5802 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
5803 ctx->f32, "");
5804 }
5805 }
5806
5807 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5808
5809 LLVMBuildRet(gallivm->builder, ctx->return_value);
5810
5811 /* Dump LLVM IR before any optimization passes */
5812 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5813 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5814 LLVMDumpModule(bld_base->base.gallivm->module);
5815
5816 radeon_llvm_finalize_module(&ctx->radeon_bld);
5817
5818 r = si_compile_llvm(sscreen, &ctx->shader->binary,
5819 &ctx->shader->config, ctx->tm,
5820 bld_base->base.gallivm->module,
5821 debug, PIPE_SHADER_GEOMETRY,
5822 "GS Copy Shader");
5823 if (!r) {
5824 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5825 fprintf(stderr, "GS Copy Shader:\n");
5826 si_shader_dump(sscreen, ctx->shader, debug,
5827 PIPE_SHADER_GEOMETRY, stderr);
5828 r = si_shader_binary_upload(sscreen, ctx->shader);
5829 }
5830
5831 radeon_llvm_dispose(&ctx->radeon_bld);
5832
5833 FREE(outputs);
5834 return r;
5835 }
5836
5837 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
5838 {
5839 int i;
5840
5841 fprintf(f, "SHADER KEY\n");
5842
5843 switch (shader) {
5844 case PIPE_SHADER_VERTEX:
5845 fprintf(f, " instance_divisors = {");
5846 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
5847 fprintf(f, !i ? "%u" : ", %u",
5848 key->vs.prolog.instance_divisors[i]);
5849 fprintf(f, "}\n");
5850 fprintf(f, " as_es = %u\n", key->vs.as_es);
5851 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
5852 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
5853 break;
5854
5855 case PIPE_SHADER_TESS_CTRL:
5856 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
5857 break;
5858
5859 case PIPE_SHADER_TESS_EVAL:
5860 fprintf(f, " as_es = %u\n", key->tes.as_es);
5861 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
5862 break;
5863
5864 case PIPE_SHADER_GEOMETRY:
5865 case PIPE_SHADER_COMPUTE:
5866 break;
5867
5868 case PIPE_SHADER_FRAGMENT:
5869 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
5870 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
5871 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
5872 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
5873 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
5874 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
5875 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
5876 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
5877 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
5878 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
5879 break;
5880
5881 default:
5882 assert(0);
5883 }
5884 }
5885
5886 static void si_init_shader_ctx(struct si_shader_context *ctx,
5887 struct si_screen *sscreen,
5888 struct si_shader *shader,
5889 LLVMTargetMachineRef tm)
5890 {
5891 struct lp_build_tgsi_context *bld_base;
5892 struct lp_build_tgsi_action tmpl = {};
5893
5894 memset(ctx, 0, sizeof(*ctx));
5895 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
5896 ctx->tm = tm;
5897 ctx->screen = sscreen;
5898 if (shader && shader->selector)
5899 ctx->type = shader->selector->info.processor;
5900 else
5901 ctx->type = -1;
5902 ctx->shader = shader;
5903
5904 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
5905 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
5906 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
5907 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
5908 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
5909 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
5910 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
5911 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
5912 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
5913 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
5914 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
5915 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
5916
5917 bld_base = &ctx->radeon_bld.soa.bld_base;
5918 if (shader && shader->selector)
5919 bld_base->info = &shader->selector->info;
5920 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5921
5922 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5923 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5924 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5925
5926 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
5927 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
5928 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
5929 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
5930 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
5931 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
5932 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
5933 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
5934 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
5935 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
5936 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
5937 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
5938 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
5939
5940 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
5941 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
5942 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
5943 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
5944 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
5945 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
5946
5947 tmpl.fetch_args = atomic_fetch_args;
5948 tmpl.emit = atomic_emit;
5949 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5950 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
5951 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
5952 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
5953 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
5954 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
5955 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
5956 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
5957 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
5958 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
5959 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
5960 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
5961 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
5962 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
5963 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
5964 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
5965 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
5966 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
5967 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
5968 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
5969
5970 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5971
5972 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5973 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5974 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5975 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5976
5977 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5978 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5979 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5980
5981 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
5982 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
5983 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
5984 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
5985 }
5986
5987 int si_compile_tgsi_shader(struct si_screen *sscreen,
5988 LLVMTargetMachineRef tm,
5989 struct si_shader *shader,
5990 bool is_monolithic,
5991 struct pipe_debug_callback *debug)
5992 {
5993 struct si_shader_selector *sel = shader->selector;
5994 struct si_shader_context ctx;
5995 struct lp_build_tgsi_context *bld_base;
5996 LLVMModuleRef mod;
5997 int r = 0;
5998
5999 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6000 * conversion fails. */
6001 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6002 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6003 si_dump_shader_key(sel->type, &shader->key, stderr);
6004 tgsi_dump(sel->tokens, 0);
6005 si_dump_streamout(&sel->so);
6006 }
6007
6008 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6009 ctx.is_monolithic = is_monolithic;
6010
6011 shader->info.uses_instanceid = sel->info.uses_instanceid;
6012
6013 bld_base = &ctx.radeon_bld.soa.bld_base;
6014 ctx.radeon_bld.load_system_value = declare_system_value;
6015
6016 switch (ctx.type) {
6017 case PIPE_SHADER_VERTEX:
6018 ctx.radeon_bld.load_input = declare_input_vs;
6019 if (shader->key.vs.as_ls)
6020 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6021 else if (shader->key.vs.as_es)
6022 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6023 else
6024 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6025 break;
6026 case PIPE_SHADER_TESS_CTRL:
6027 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6028 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6029 bld_base->emit_store = store_output_tcs;
6030 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6031 break;
6032 case PIPE_SHADER_TESS_EVAL:
6033 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6034 if (shader->key.tes.as_es)
6035 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6036 else
6037 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6038 break;
6039 case PIPE_SHADER_GEOMETRY:
6040 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6041 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6042 break;
6043 case PIPE_SHADER_FRAGMENT:
6044 ctx.radeon_bld.load_input = declare_input_fs;
6045 if (is_monolithic)
6046 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6047 else
6048 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6049 break;
6050 case PIPE_SHADER_COMPUTE:
6051 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6052 break;
6053 default:
6054 assert(!"Unsupported shader type");
6055 return -1;
6056 }
6057
6058 create_meta_data(&ctx);
6059 create_function(&ctx);
6060 preload_constants(&ctx);
6061 preload_shader_buffers(&ctx);
6062 preload_samplers(&ctx);
6063 preload_images(&ctx);
6064 preload_streamout_buffers(&ctx);
6065 preload_ring_buffers(&ctx);
6066
6067 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6068 shader->key.ps.prolog.poly_stipple) {
6069 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6070 SI_PARAM_RW_BUFFERS);
6071 si_llvm_emit_polygon_stipple(&ctx, list,
6072 SI_PARAM_POS_FIXED_PT);
6073 }
6074
6075 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6076 int i;
6077 for (i = 0; i < 4; i++) {
6078 ctx.gs_next_vertex[i] =
6079 lp_build_alloca(bld_base->base.gallivm,
6080 ctx.i32, "");
6081 }
6082 }
6083
6084 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6085 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6086 goto out;
6087 }
6088
6089 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
6090 mod = bld_base->base.gallivm->module;
6091
6092 /* Dump LLVM IR before any optimization passes */
6093 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6094 r600_can_dump_shader(&sscreen->b, ctx.type))
6095 LLVMDumpModule(mod);
6096
6097 radeon_llvm_finalize_module(&ctx.radeon_bld);
6098
6099 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6100 mod, debug, ctx.type, "TGSI shader");
6101 if (r) {
6102 fprintf(stderr, "LLVM failed to compile shader\n");
6103 goto out;
6104 }
6105
6106 radeon_llvm_dispose(&ctx.radeon_bld);
6107
6108 /* Add the scratch offset to input SGPRs. */
6109 if (shader->config.scratch_bytes_per_wave)
6110 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6111
6112 /* Calculate the number of fragment input VGPRs. */
6113 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6114 shader->info.num_input_vgprs = 0;
6115 shader->info.face_vgpr_index = -1;
6116
6117 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6118 shader->info.num_input_vgprs += 2;
6119 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6120 shader->info.num_input_vgprs += 2;
6121 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6122 shader->info.num_input_vgprs += 2;
6123 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6124 shader->info.num_input_vgprs += 3;
6125 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6126 shader->info.num_input_vgprs += 2;
6127 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6128 shader->info.num_input_vgprs += 2;
6129 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6130 shader->info.num_input_vgprs += 2;
6131 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6132 shader->info.num_input_vgprs += 1;
6133 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6134 shader->info.num_input_vgprs += 1;
6135 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6136 shader->info.num_input_vgprs += 1;
6137 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6138 shader->info.num_input_vgprs += 1;
6139 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6140 shader->info.num_input_vgprs += 1;
6141 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6142 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6143 shader->info.num_input_vgprs += 1;
6144 }
6145 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6146 shader->info.num_input_vgprs += 1;
6147 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6148 shader->info.num_input_vgprs += 1;
6149 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6150 shader->info.num_input_vgprs += 1;
6151 }
6152
6153 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6154 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6155 shader->gs_copy_shader->selector = shader->selector;
6156 ctx.shader = shader->gs_copy_shader;
6157 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6158 shader, debug))) {
6159 free(shader->gs_copy_shader);
6160 shader->gs_copy_shader = NULL;
6161 goto out;
6162 }
6163 }
6164
6165 out:
6166 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6167 FREE(ctx.constants[i]);
6168 return r;
6169 }
6170
6171 /**
6172 * Create, compile and return a shader part (prolog or epilog).
6173 *
6174 * \param sscreen screen
6175 * \param list list of shader parts of the same category
6176 * \param key shader part key
6177 * \param tm LLVM target machine
6178 * \param debug debug callback
6179 * \param compile the callback responsible for compilation
6180 * \return non-NULL on success
6181 */
6182 static struct si_shader_part *
6183 si_get_shader_part(struct si_screen *sscreen,
6184 struct si_shader_part **list,
6185 union si_shader_part_key *key,
6186 LLVMTargetMachineRef tm,
6187 struct pipe_debug_callback *debug,
6188 bool (*compile)(struct si_screen *,
6189 LLVMTargetMachineRef,
6190 struct pipe_debug_callback *,
6191 struct si_shader_part *))
6192 {
6193 struct si_shader_part *result;
6194
6195 pipe_mutex_lock(sscreen->shader_parts_mutex);
6196
6197 /* Find existing. */
6198 for (result = *list; result; result = result->next) {
6199 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6200 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6201 return result;
6202 }
6203 }
6204
6205 /* Compile a new one. */
6206 result = CALLOC_STRUCT(si_shader_part);
6207 result->key = *key;
6208 if (!compile(sscreen, tm, debug, result)) {
6209 FREE(result);
6210 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6211 return NULL;
6212 }
6213
6214 result->next = *list;
6215 *list = result;
6216 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6217 return result;
6218 }
6219
6220 /**
6221 * Create a vertex shader prolog.
6222 *
6223 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6224 * All inputs are returned unmodified. The vertex load indices are
6225 * stored after them, which will used by the API VS for fetching inputs.
6226 *
6227 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6228 * input_v0,
6229 * input_v1,
6230 * input_v2,
6231 * input_v3,
6232 * (VertexID + BaseVertex),
6233 * (InstanceID + StartInstance),
6234 * (InstanceID / 2 + StartInstance)
6235 */
6236 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6237 LLVMTargetMachineRef tm,
6238 struct pipe_debug_callback *debug,
6239 struct si_shader_part *out)
6240 {
6241 union si_shader_part_key *key = &out->key;
6242 struct si_shader shader = {};
6243 struct si_shader_context ctx;
6244 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6245 LLVMTypeRef *params, *returns;
6246 LLVMValueRef ret, func;
6247 int last_sgpr, num_params, num_returns, i;
6248 bool status = true;
6249
6250 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6251 ctx.type = PIPE_SHADER_VERTEX;
6252 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6253 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6254
6255 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6256 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6257 sizeof(LLVMTypeRef));
6258 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6259 key->vs_prolog.last_input + 1) *
6260 sizeof(LLVMTypeRef));
6261 num_params = 0;
6262 num_returns = 0;
6263
6264 /* Declare input and output SGPRs. */
6265 num_params = 0;
6266 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6267 params[num_params++] = ctx.i32;
6268 returns[num_returns++] = ctx.i32;
6269 }
6270 last_sgpr = num_params - 1;
6271
6272 /* 4 preloaded VGPRs (outputs must be floats) */
6273 for (i = 0; i < 4; i++) {
6274 params[num_params++] = ctx.i32;
6275 returns[num_returns++] = ctx.f32;
6276 }
6277
6278 /* Vertex load indices. */
6279 for (i = 0; i <= key->vs_prolog.last_input; i++)
6280 returns[num_returns++] = ctx.f32;
6281
6282 /* Create the function. */
6283 si_create_function(&ctx, returns, num_returns, params,
6284 num_params, -1, last_sgpr);
6285 func = ctx.radeon_bld.main_fn;
6286
6287 /* Copy inputs to outputs. This should be no-op, as the registers match,
6288 * but it will prevent the compiler from overwriting them unintentionally.
6289 */
6290 ret = ctx.return_value;
6291 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6292 LLVMValueRef p = LLVMGetParam(func, i);
6293 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6294 }
6295 for (i = num_params - 4; i < num_params; i++) {
6296 LLVMValueRef p = LLVMGetParam(func, i);
6297 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6298 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6299 }
6300
6301 /* Compute vertex load indices from instance divisors. */
6302 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6303 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6304 LLVMValueRef index;
6305
6306 if (divisor) {
6307 /* InstanceID / Divisor + StartInstance */
6308 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6309 SI_SGPR_START_INSTANCE,
6310 divisor);
6311 } else {
6312 /* VertexID + BaseVertex */
6313 index = LLVMBuildAdd(gallivm->builder,
6314 LLVMGetParam(func, ctx.param_vertex_id),
6315 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6316 }
6317
6318 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6319 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6320 num_params++, "");
6321 }
6322
6323 /* Compile. */
6324 LLVMBuildRet(gallivm->builder, ret);
6325 radeon_llvm_finalize_module(&ctx.radeon_bld);
6326
6327 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6328 gallivm->module, debug, ctx.type,
6329 "Vertex Shader Prolog"))
6330 status = false;
6331
6332 radeon_llvm_dispose(&ctx.radeon_bld);
6333 return status;
6334 }
6335
6336 /**
6337 * Compile the vertex shader epilog. This is also used by the tessellation
6338 * evaluation shader compiled as VS.
6339 *
6340 * The input is PrimitiveID.
6341 *
6342 * If PrimitiveID is required by the pixel shader, export it.
6343 * Otherwise, do nothing.
6344 */
6345 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6346 LLVMTargetMachineRef tm,
6347 struct pipe_debug_callback *debug,
6348 struct si_shader_part *out)
6349 {
6350 union si_shader_part_key *key = &out->key;
6351 struct si_shader_context ctx;
6352 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6353 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6354 LLVMTypeRef params[5];
6355 int num_params, i;
6356 bool status = true;
6357
6358 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6359 ctx.type = PIPE_SHADER_VERTEX;
6360
6361 /* Declare input VGPRs. */
6362 num_params = key->vs_epilog.states.export_prim_id ?
6363 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6364 assert(num_params <= ARRAY_SIZE(params));
6365
6366 for (i = 0; i < num_params; i++)
6367 params[i] = ctx.f32;
6368
6369 /* Create the function. */
6370 si_create_function(&ctx, NULL, 0, params, num_params,
6371 -1, -1);
6372
6373 /* Emit exports. */
6374 if (key->vs_epilog.states.export_prim_id) {
6375 struct lp_build_context *base = &bld_base->base;
6376 struct lp_build_context *uint = &bld_base->uint_bld;
6377 LLVMValueRef args[9];
6378
6379 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6380 args[1] = uint->zero; /* whether the EXEC mask is valid */
6381 args[2] = uint->zero; /* DONE bit */
6382 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6383 key->vs_epilog.prim_id_param_offset);
6384 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6385 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6386 VS_EPILOG_PRIMID_LOC); /* X */
6387 args[6] = uint->undef; /* Y */
6388 args[7] = uint->undef; /* Z */
6389 args[8] = uint->undef; /* W */
6390
6391 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6392 LLVMVoidTypeInContext(base->gallivm->context),
6393 args, 9, 0);
6394 }
6395
6396 /* Compile. */
6397 LLVMBuildRet(gallivm->builder, ctx.return_value);
6398 radeon_llvm_finalize_module(&ctx.radeon_bld);
6399
6400 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6401 gallivm->module, debug, ctx.type,
6402 "Vertex Shader Epilog"))
6403 status = false;
6404
6405 radeon_llvm_dispose(&ctx.radeon_bld);
6406 return status;
6407 }
6408
6409 /**
6410 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6411 */
6412 static bool si_get_vs_epilog(struct si_screen *sscreen,
6413 LLVMTargetMachineRef tm,
6414 struct si_shader *shader,
6415 struct pipe_debug_callback *debug,
6416 struct si_vs_epilog_bits *states)
6417 {
6418 union si_shader_part_key epilog_key;
6419
6420 memset(&epilog_key, 0, sizeof(epilog_key));
6421 epilog_key.vs_epilog.states = *states;
6422
6423 /* Set up the PrimitiveID output. */
6424 if (shader->key.vs.epilog.export_prim_id) {
6425 unsigned index = shader->selector->info.num_outputs;
6426 unsigned offset = shader->info.nr_param_exports++;
6427
6428 epilog_key.vs_epilog.prim_id_param_offset = offset;
6429 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6430 shader->info.vs_output_param_offset[index] = offset;
6431 }
6432
6433 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
6434 &epilog_key, tm, debug,
6435 si_compile_vs_epilog);
6436 return shader->epilog != NULL;
6437 }
6438
6439 /**
6440 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6441 */
6442 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6443 LLVMTargetMachineRef tm,
6444 struct si_shader *shader,
6445 struct pipe_debug_callback *debug)
6446 {
6447 struct tgsi_shader_info *info = &shader->selector->info;
6448 union si_shader_part_key prolog_key;
6449 unsigned i;
6450
6451 /* Get the prolog. */
6452 memset(&prolog_key, 0, sizeof(prolog_key));
6453 prolog_key.vs_prolog.states = shader->key.vs.prolog;
6454 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6455 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6456
6457 /* The prolog is a no-op if there are no inputs. */
6458 if (info->num_inputs) {
6459 shader->prolog =
6460 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6461 &prolog_key, tm, debug,
6462 si_compile_vs_prolog);
6463 if (!shader->prolog)
6464 return false;
6465 }
6466
6467 /* Get the epilog. */
6468 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
6469 !si_get_vs_epilog(sscreen, tm, shader, debug,
6470 &shader->key.vs.epilog))
6471 return false;
6472
6473 /* Set the instanceID flag. */
6474 for (i = 0; i < info->num_inputs; i++)
6475 if (prolog_key.vs_prolog.states.instance_divisors[i])
6476 shader->info.uses_instanceid = true;
6477
6478 return true;
6479 }
6480
6481 /**
6482 * Select and compile (or reuse) TES parts (epilog).
6483 */
6484 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
6485 LLVMTargetMachineRef tm,
6486 struct si_shader *shader,
6487 struct pipe_debug_callback *debug)
6488 {
6489 if (shader->key.tes.as_es)
6490 return true;
6491
6492 /* TES compiled as VS. */
6493 return si_get_vs_epilog(sscreen, tm, shader, debug,
6494 &shader->key.tes.epilog);
6495 }
6496
6497 /**
6498 * Compile the TCS epilog. This writes tesselation factors to memory based on
6499 * the output primitive type of the tesselator (determined by TES).
6500 */
6501 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
6502 LLVMTargetMachineRef tm,
6503 struct pipe_debug_callback *debug,
6504 struct si_shader_part *out)
6505 {
6506 union si_shader_part_key *key = &out->key;
6507 struct si_shader shader = {};
6508 struct si_shader_context ctx;
6509 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6510 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6511 LLVMTypeRef params[16];
6512 LLVMValueRef func;
6513 int last_array_pointer, last_sgpr, num_params;
6514 bool status = true;
6515
6516 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6517 ctx.type = PIPE_SHADER_TESS_CTRL;
6518 shader.key.tcs.epilog = key->tcs_epilog.states;
6519
6520 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
6521 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
6522 last_array_pointer = SI_PARAM_RW_BUFFERS;
6523 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6524 params[SI_PARAM_SAMPLERS] = ctx.i64;
6525 params[SI_PARAM_IMAGES] = ctx.i64;
6526 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6527 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
6528 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
6529 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
6530 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
6531 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
6532 num_params = last_sgpr + 1;
6533
6534 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
6535 params[num_params++] = ctx.i32; /* invocation ID within the patch */
6536 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
6537
6538 /* Create the function. */
6539 si_create_function(&ctx, NULL, 0, params, num_params,
6540 last_array_pointer, last_sgpr);
6541 declare_tess_lds(&ctx);
6542 func = ctx.radeon_bld.main_fn;
6543
6544 si_write_tess_factors(bld_base,
6545 LLVMGetParam(func, last_sgpr + 1),
6546 LLVMGetParam(func, last_sgpr + 2),
6547 LLVMGetParam(func, last_sgpr + 3));
6548
6549 /* Compile. */
6550 LLVMBuildRet(gallivm->builder, ctx.return_value);
6551 radeon_llvm_finalize_module(&ctx.radeon_bld);
6552
6553 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6554 gallivm->module, debug, ctx.type,
6555 "Tessellation Control Shader Epilog"))
6556 status = false;
6557
6558 radeon_llvm_dispose(&ctx.radeon_bld);
6559 return status;
6560 }
6561
6562 /**
6563 * Select and compile (or reuse) TCS parts (epilog).
6564 */
6565 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6566 LLVMTargetMachineRef tm,
6567 struct si_shader *shader,
6568 struct pipe_debug_callback *debug)
6569 {
6570 union si_shader_part_key epilog_key;
6571
6572 /* Get the epilog. */
6573 memset(&epilog_key, 0, sizeof(epilog_key));
6574 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
6575
6576 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6577 &epilog_key, tm, debug,
6578 si_compile_tcs_epilog);
6579 return shader->epilog != NULL;
6580 }
6581
6582 /**
6583 * Compile the pixel shader prolog. This handles:
6584 * - two-side color selection and interpolation
6585 * - overriding interpolation parameters for the API PS
6586 * - polygon stippling
6587 *
6588 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6589 * overriden by other states. (e.g. per-sample interpolation)
6590 * Interpolated colors are stored after the preloaded VGPRs.
6591 */
6592 static bool si_compile_ps_prolog(struct si_screen *sscreen,
6593 LLVMTargetMachineRef tm,
6594 struct pipe_debug_callback *debug,
6595 struct si_shader_part *out)
6596 {
6597 union si_shader_part_key *key = &out->key;
6598 struct si_shader shader = {};
6599 struct si_shader_context ctx;
6600 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6601 LLVMTypeRef *params;
6602 LLVMValueRef ret, func;
6603 int last_sgpr, num_params, num_returns, i, num_color_channels;
6604 bool status = true;
6605
6606 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6607 ctx.type = PIPE_SHADER_FRAGMENT;
6608 shader.key.ps.prolog = key->ps_prolog.states;
6609
6610 /* Number of inputs + 8 color elements. */
6611 params = alloca((key->ps_prolog.num_input_sgprs +
6612 key->ps_prolog.num_input_vgprs + 8) *
6613 sizeof(LLVMTypeRef));
6614
6615 /* Declare inputs. */
6616 num_params = 0;
6617 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
6618 params[num_params++] = ctx.i32;
6619 last_sgpr = num_params - 1;
6620
6621 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
6622 params[num_params++] = ctx.f32;
6623
6624 /* Declare outputs (same as inputs + add colors if needed) */
6625 num_returns = num_params;
6626 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6627 for (i = 0; i < num_color_channels; i++)
6628 params[num_returns++] = ctx.f32;
6629
6630 /* Create the function. */
6631 si_create_function(&ctx, params, num_returns, params,
6632 num_params, -1, last_sgpr);
6633 func = ctx.radeon_bld.main_fn;
6634
6635 /* Copy inputs to outputs. This should be no-op, as the registers match,
6636 * but it will prevent the compiler from overwriting them unintentionally.
6637 */
6638 ret = ctx.return_value;
6639 for (i = 0; i < num_params; i++) {
6640 LLVMValueRef p = LLVMGetParam(func, i);
6641 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6642 }
6643
6644 /* Polygon stippling. */
6645 if (key->ps_prolog.states.poly_stipple) {
6646 /* POS_FIXED_PT is always last. */
6647 unsigned pos = key->ps_prolog.num_input_sgprs +
6648 key->ps_prolog.num_input_vgprs - 1;
6649 LLVMValueRef ptr[2], list;
6650
6651 /* Get the pointer to rw buffers. */
6652 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
6653 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
6654 list = lp_build_gather_values(gallivm, ptr, 2);
6655 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
6656 list = LLVMBuildIntToPtr(gallivm->builder, list,
6657 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
6658
6659 si_llvm_emit_polygon_stipple(&ctx, list, pos);
6660 }
6661
6662 /* Interpolate colors. */
6663 for (i = 0; i < 2; i++) {
6664 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6665 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6666 key->ps_prolog.face_vgpr_index;
6667 LLVMValueRef interp[2], color[4];
6668 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6669
6670 if (!writemask)
6671 continue;
6672
6673 /* If the interpolation qualifier is not CONSTANT (-1). */
6674 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6675 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6676 key->ps_prolog.color_interp_vgpr_index[i];
6677
6678 interp[0] = LLVMGetParam(func, interp_vgpr);
6679 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
6680 interp_ij = lp_build_gather_values(gallivm, interp, 2);
6681 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
6682 ctx.v2i32, "");
6683 }
6684
6685 /* Use the absolute location of the input. */
6686 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6687
6688 if (key->ps_prolog.states.color_two_side) {
6689 face = LLVMGetParam(func, face_vgpr);
6690 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
6691 }
6692
6693 interp_fs_input(&ctx,
6694 key->ps_prolog.color_attr_index[i],
6695 TGSI_SEMANTIC_COLOR, i,
6696 key->ps_prolog.num_interp_inputs,
6697 key->ps_prolog.colors_read, interp_ij,
6698 prim_mask, face, color);
6699
6700 while (writemask) {
6701 unsigned chan = u_bit_scan(&writemask);
6702 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
6703 num_params++, "");
6704 }
6705 }
6706
6707 /* Force per-sample interpolation. */
6708 if (key->ps_prolog.states.force_persample_interp) {
6709 unsigned i, base = key->ps_prolog.num_input_sgprs;
6710 LLVMValueRef persp_sample[2], linear_sample[2];
6711
6712 /* Read PERSP_SAMPLE. */
6713 for (i = 0; i < 2; i++)
6714 persp_sample[i] = LLVMGetParam(func, base + i);
6715 /* Overwrite PERSP_CENTER. */
6716 for (i = 0; i < 2; i++)
6717 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6718 persp_sample[i], base + 2 + i, "");
6719 /* Overwrite PERSP_CENTROID. */
6720 for (i = 0; i < 2; i++)
6721 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6722 persp_sample[i], base + 4 + i, "");
6723 /* Read LINEAR_SAMPLE. */
6724 for (i = 0; i < 2; i++)
6725 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6726 /* Overwrite LINEAR_CENTER. */
6727 for (i = 0; i < 2; i++)
6728 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6729 linear_sample[i], base + 8 + i, "");
6730 /* Overwrite LINEAR_CENTROID. */
6731 for (i = 0; i < 2; i++)
6732 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6733 linear_sample[i], base + 10 + i, "");
6734 }
6735
6736 /* Compile. */
6737 LLVMBuildRet(gallivm->builder, ret);
6738 radeon_llvm_finalize_module(&ctx.radeon_bld);
6739
6740 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6741 gallivm->module, debug, ctx.type,
6742 "Fragment Shader Prolog"))
6743 status = false;
6744
6745 radeon_llvm_dispose(&ctx.radeon_bld);
6746 return status;
6747 }
6748
6749 /**
6750 * Compile the pixel shader epilog. This handles everything that must be
6751 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6752 */
6753 static bool si_compile_ps_epilog(struct si_screen *sscreen,
6754 LLVMTargetMachineRef tm,
6755 struct pipe_debug_callback *debug,
6756 struct si_shader_part *out)
6757 {
6758 union si_shader_part_key *key = &out->key;
6759 struct si_shader shader = {};
6760 struct si_shader_context ctx;
6761 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6762 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6763 LLVMTypeRef params[16+8*4+3];
6764 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6765 int last_array_pointer, last_sgpr, num_params, i;
6766 bool status = true;
6767
6768 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6769 ctx.type = PIPE_SHADER_FRAGMENT;
6770 shader.key.ps.epilog = key->ps_epilog.states;
6771
6772 /* Declare input SGPRs. */
6773 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
6774 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6775 params[SI_PARAM_SAMPLERS] = ctx.i64;
6776 params[SI_PARAM_IMAGES] = ctx.i64;
6777 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6778 params[SI_PARAM_ALPHA_REF] = ctx.f32;
6779 last_array_pointer = -1;
6780 last_sgpr = SI_PARAM_ALPHA_REF;
6781
6782 /* Declare input VGPRs. */
6783 num_params = (last_sgpr + 1) +
6784 util_bitcount(key->ps_epilog.colors_written) * 4 +
6785 key->ps_epilog.writes_z +
6786 key->ps_epilog.writes_stencil +
6787 key->ps_epilog.writes_samplemask;
6788
6789 num_params = MAX2(num_params,
6790 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6791
6792 assert(num_params <= ARRAY_SIZE(params));
6793
6794 for (i = last_sgpr + 1; i < num_params; i++)
6795 params[i] = ctx.f32;
6796
6797 /* Create the function. */
6798 si_create_function(&ctx, NULL, 0, params, num_params,
6799 last_array_pointer, last_sgpr);
6800 /* Disable elimination of unused inputs. */
6801 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
6802 "InitialPSInputAddr", 0xffffff);
6803
6804 /* Process colors. */
6805 unsigned vgpr = last_sgpr + 1;
6806 unsigned colors_written = key->ps_epilog.colors_written;
6807 int last_color_export = -1;
6808
6809 /* Find the last color export. */
6810 if (!key->ps_epilog.writes_z &&
6811 !key->ps_epilog.writes_stencil &&
6812 !key->ps_epilog.writes_samplemask) {
6813 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6814
6815 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6816 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6817 /* Just set this if any of the colorbuffers are enabled. */
6818 if (spi_format &
6819 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6820 last_color_export = 0;
6821 } else {
6822 for (i = 0; i < 8; i++)
6823 if (colors_written & (1 << i) &&
6824 (spi_format >> (i * 4)) & 0xf)
6825 last_color_export = i;
6826 }
6827 }
6828
6829 while (colors_written) {
6830 LLVMValueRef color[4];
6831 int mrt = u_bit_scan(&colors_written);
6832
6833 for (i = 0; i < 4; i++)
6834 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6835
6836 si_export_mrt_color(bld_base, color, mrt,
6837 num_params - 1,
6838 mrt == last_color_export);
6839 }
6840
6841 /* Process depth, stencil, samplemask. */
6842 if (key->ps_epilog.writes_z)
6843 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6844 if (key->ps_epilog.writes_stencil)
6845 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6846 if (key->ps_epilog.writes_samplemask)
6847 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6848
6849 if (depth || stencil || samplemask)
6850 si_export_mrt_z(bld_base, depth, stencil, samplemask);
6851 else if (last_color_export == -1)
6852 si_export_null(bld_base);
6853
6854 /* Compile. */
6855 LLVMBuildRetVoid(gallivm->builder);
6856 radeon_llvm_finalize_module(&ctx.radeon_bld);
6857
6858 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6859 gallivm->module, debug, ctx.type,
6860 "Fragment Shader Epilog"))
6861 status = false;
6862
6863 radeon_llvm_dispose(&ctx.radeon_bld);
6864 return status;
6865 }
6866
6867 /**
6868 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6869 */
6870 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6871 LLVMTargetMachineRef tm,
6872 struct si_shader *shader,
6873 struct pipe_debug_callback *debug)
6874 {
6875 struct tgsi_shader_info *info = &shader->selector->info;
6876 union si_shader_part_key prolog_key;
6877 union si_shader_part_key epilog_key;
6878 unsigned i;
6879
6880 /* Get the prolog. */
6881 memset(&prolog_key, 0, sizeof(prolog_key));
6882 prolog_key.ps_prolog.states = shader->key.ps.prolog;
6883 prolog_key.ps_prolog.colors_read = info->colors_read;
6884 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6885 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6886
6887 if (info->colors_read) {
6888 unsigned *color = shader->selector->color_attr_index;
6889
6890 if (shader->key.ps.prolog.color_two_side) {
6891 /* BCOLORs are stored after the last input. */
6892 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
6893 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6894 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6895 }
6896
6897 for (i = 0; i < 2; i++) {
6898 unsigned location = info->input_interpolate_loc[color[i]];
6899
6900 if (!(info->colors_read & (0xf << i*4)))
6901 continue;
6902
6903 prolog_key.ps_prolog.color_attr_index[i] = color[i];
6904
6905 /* Force per-sample interpolation for the colors here. */
6906 if (shader->key.ps.prolog.force_persample_interp)
6907 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6908
6909 switch (info->input_interpolate[color[i]]) {
6910 case TGSI_INTERPOLATE_CONSTANT:
6911 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
6912 break;
6913 case TGSI_INTERPOLATE_PERSPECTIVE:
6914 case TGSI_INTERPOLATE_COLOR:
6915 switch (location) {
6916 case TGSI_INTERPOLATE_LOC_SAMPLE:
6917 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
6918 shader->config.spi_ps_input_ena |=
6919 S_0286CC_PERSP_SAMPLE_ENA(1);
6920 break;
6921 case TGSI_INTERPOLATE_LOC_CENTER:
6922 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
6923 shader->config.spi_ps_input_ena |=
6924 S_0286CC_PERSP_CENTER_ENA(1);
6925 break;
6926 case TGSI_INTERPOLATE_LOC_CENTROID:
6927 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
6928 shader->config.spi_ps_input_ena |=
6929 S_0286CC_PERSP_CENTROID_ENA(1);
6930 break;
6931 default:
6932 assert(0);
6933 }
6934 break;
6935 case TGSI_INTERPOLATE_LINEAR:
6936 switch (location) {
6937 case TGSI_INTERPOLATE_LOC_SAMPLE:
6938 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
6939 shader->config.spi_ps_input_ena |=
6940 S_0286CC_LINEAR_SAMPLE_ENA(1);
6941 break;
6942 case TGSI_INTERPOLATE_LOC_CENTER:
6943 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
6944 shader->config.spi_ps_input_ena |=
6945 S_0286CC_LINEAR_CENTER_ENA(1);
6946 break;
6947 case TGSI_INTERPOLATE_LOC_CENTROID:
6948 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
6949 shader->config.spi_ps_input_ena |=
6950 S_0286CC_LINEAR_CENTROID_ENA(1);
6951 break;
6952 default:
6953 assert(0);
6954 }
6955 break;
6956 default:
6957 assert(0);
6958 }
6959 }
6960 }
6961
6962 /* The prolog is a no-op if these aren't set. */
6963 if (prolog_key.ps_prolog.colors_read ||
6964 prolog_key.ps_prolog.states.force_persample_interp ||
6965 prolog_key.ps_prolog.states.poly_stipple) {
6966 shader->prolog =
6967 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6968 &prolog_key, tm, debug,
6969 si_compile_ps_prolog);
6970 if (!shader->prolog)
6971 return false;
6972 }
6973
6974 /* Get the epilog. */
6975 memset(&epilog_key, 0, sizeof(epilog_key));
6976 epilog_key.ps_epilog.colors_written = info->colors_written;
6977 epilog_key.ps_epilog.writes_z = info->writes_z;
6978 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
6979 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
6980 epilog_key.ps_epilog.states = shader->key.ps.epilog;
6981
6982 shader->epilog =
6983 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6984 &epilog_key, tm, debug,
6985 si_compile_ps_epilog);
6986 if (!shader->epilog)
6987 return false;
6988
6989 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6990 if (shader->key.ps.prolog.poly_stipple) {
6991 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6992 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6993 }
6994
6995 /* Set up the enable bits for per-sample shading if needed. */
6996 if (shader->key.ps.prolog.force_persample_interp) {
6997 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6998 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6999 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7000 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7001 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7002 }
7003 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7004 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
7005 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7006 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7007 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7008 }
7009 }
7010
7011 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7012 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7013 !(shader->config.spi_ps_input_ena & 0xf)) {
7014 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7015 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7016 }
7017
7018 /* At least one pair of interpolation weights must be enabled. */
7019 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7020 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7021 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7022 }
7023
7024 /* The sample mask input is always enabled, because the API shader always
7025 * passes it through to the epilog. Disable it here if it's unused.
7026 */
7027 if (!shader->key.ps.epilog.poly_line_smoothing &&
7028 !shader->selector->info.reads_samplemask)
7029 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7030
7031 return true;
7032 }
7033
7034 static void si_fix_num_sgprs(struct si_shader *shader)
7035 {
7036 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7037
7038 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7039 }
7040
7041 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7042 struct si_shader *shader,
7043 struct pipe_debug_callback *debug)
7044 {
7045 struct si_shader *mainp = shader->selector->main_shader_part;
7046 int r;
7047
7048 /* LS, ES, VS are compiled on demand if the main part hasn't been
7049 * compiled for that stage.
7050 */
7051 if (!mainp ||
7052 (shader->selector->type == PIPE_SHADER_VERTEX &&
7053 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7054 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7055 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7056 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7057 shader->selector->type == PIPE_SHADER_COMPUTE) {
7058 /* Monolithic shader (compiled as a whole, has many variants,
7059 * may take a long time to compile).
7060 */
7061 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7062 if (r)
7063 return r;
7064 } else {
7065 /* The shader consists of 2-3 parts:
7066 *
7067 * - the middle part is the user shader, it has 1 variant only
7068 * and it was compiled during the creation of the shader
7069 * selector
7070 * - the prolog part is inserted at the beginning
7071 * - the epilog part is inserted at the end
7072 *
7073 * The prolog and epilog have many (but simple) variants.
7074 */
7075
7076 /* Copy the compiled TGSI shader data over. */
7077 shader->is_binary_shared = true;
7078 shader->binary = mainp->binary;
7079 shader->config = mainp->config;
7080 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7081 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7082 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7083 memcpy(shader->info.vs_output_param_offset,
7084 mainp->info.vs_output_param_offset,
7085 sizeof(mainp->info.vs_output_param_offset));
7086 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7087 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7088 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7089
7090 /* Select prologs and/or epilogs. */
7091 switch (shader->selector->type) {
7092 case PIPE_SHADER_VERTEX:
7093 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7094 return -1;
7095 break;
7096 case PIPE_SHADER_TESS_CTRL:
7097 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7098 return -1;
7099 break;
7100 case PIPE_SHADER_TESS_EVAL:
7101 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7102 return -1;
7103 break;
7104 case PIPE_SHADER_FRAGMENT:
7105 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7106 return -1;
7107
7108 /* Make sure we have at least as many VGPRs as there
7109 * are allocated inputs.
7110 */
7111 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7112 shader->info.num_input_vgprs);
7113 break;
7114 }
7115
7116 /* Update SGPR and VGPR counts. */
7117 if (shader->prolog) {
7118 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7119 shader->prolog->config.num_sgprs);
7120 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7121 shader->prolog->config.num_vgprs);
7122 }
7123 if (shader->epilog) {
7124 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7125 shader->epilog->config.num_sgprs);
7126 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7127 shader->epilog->config.num_vgprs);
7128 }
7129 }
7130
7131 si_fix_num_sgprs(shader);
7132 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7133 stderr);
7134
7135 /* Upload. */
7136 r = si_shader_binary_upload(sscreen, shader);
7137 if (r) {
7138 fprintf(stderr, "LLVM failed to upload shader\n");
7139 return r;
7140 }
7141
7142 return 0;
7143 }
7144
7145 void si_shader_destroy(struct si_shader *shader)
7146 {
7147 if (shader->gs_copy_shader) {
7148 si_shader_destroy(shader->gs_copy_shader);
7149 FREE(shader->gs_copy_shader);
7150 }
7151
7152 if (shader->scratch_bo)
7153 r600_resource_reference(&shader->scratch_bo, NULL);
7154
7155 r600_resource_reference(&shader->bo, NULL);
7156
7157 if (!shader->is_binary_shared)
7158 radeon_shader_binary_clean(&shader->binary);
7159 }