projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: do force_persample_interp in shaders for non-trivial cases
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Given a semantic name and index of a parameter and a mask of used parameters
168 * (inputs or outputs), return the index of the parameter in the list of all
169 * used parameters.
170 *
171 * For example, assume this list of parameters:
172 * POSITION, PSIZE, GENERIC0, GENERIC2
173 * which has the mask:
174 * 11000000000101
175 * Then:
176 * querying POSITION returns 0,
177 * querying PSIZE returns 1,
178 * querying GENERIC0 returns 2,
179 * querying GENERIC2 returns 3.
180 *
181 * Which can be used as an offset to a parameter buffer in units of vec4s.
182 */
183 static int get_param_index(unsigned semantic_name, unsigned index,
184 uint64_t mask)
185 {
186 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
187 int i, param_index = 0;
188
189 /* If not present... */
190 if (!((1llu << unique_index) & mask))
191 return -1;
192
193 for (i = 0; mask; i++) {
194 uint64_t bit = 1llu << i;
195
196 if (bit & mask) {
197 if (i == unique_index)
198 return param_index;
199
200 mask &= ~bit;
201 param_index++;
202 }
203 }
204
205 assert(!"unreachable");
206 return -1;
207 }
208
209 /**
210 * Get the value of a shader input parameter and extract a bitfield.
211 */
212 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
213 unsigned param, unsigned rshift,
214 unsigned bitwidth)
215 {
216 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
217 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
218 param);
219
220 if (rshift)
221 value = LLVMBuildLShr(gallivm->builder, value,
222 lp_build_const_int32(gallivm, rshift), "");
223
224 if (rshift + bitwidth < 32) {
225 unsigned mask = (1 << bitwidth) - 1;
226 value = LLVMBuildAnd(gallivm->builder, value,
227 lp_build_const_int32(gallivm, mask), "");
228 }
229
230 return value;
231 }
232
233 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
234 {
235 switch (si_shader_ctx->type) {
236 case TGSI_PROCESSOR_TESS_CTRL:
237 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
238
239 case TGSI_PROCESSOR_TESS_EVAL:
240 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
241 si_shader_ctx->param_tes_rel_patch_id);
242
243 default:
244 assert(0);
245 return NULL;
246 }
247 }
248
249 /* Tessellation shaders pass outputs to the next shader using LDS.
250 *
251 * LS outputs = TCS inputs
252 * TCS outputs = TES inputs
253 *
254 * The LDS layout is:
255 * - TCS inputs for patch 0
256 * - TCS inputs for patch 1
257 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
258 * - ...
259 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
260 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
261 * - TCS outputs for patch 1
262 * - Per-patch TCS outputs for patch 1
263 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
264 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
265 * - ...
266 *
267 * All three shaders VS(LS), TCS, TES share the same LDS space.
268 */
269
270 static LLVMValueRef
271 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
272 {
273 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
274 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
275 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
276 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
277 else {
278 assert(0);
279 return NULL;
280 }
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
285 {
286 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
287 }
288
289 static LLVMValueRef
290 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
291 {
292 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
293 unpack_param(si_shader_ctx,
294 SI_PARAM_TCS_OUT_OFFSETS,
295 0, 16),
296 4);
297 }
298
299 static LLVMValueRef
300 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
301 {
302 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
303 unpack_param(si_shader_ctx,
304 SI_PARAM_TCS_OUT_OFFSETS,
305 16, 16),
306 4);
307 }
308
309 static LLVMValueRef
310 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
311 {
312 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
313 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
315
316 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
321 {
322 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
323 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
326
327 return LLVMBuildAdd(gallivm->builder, patch0_offset,
328 LLVMBuildMul(gallivm->builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 static LLVMValueRef
334 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
335 {
336 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
337 LLVMValueRef patch0_patch_data_offset =
338 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index,
350 LLVMValueRef value)
351 {
352 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
353 struct gallivm_state *gallivm = bld_base->base.gallivm;
354 LLVMValueRef indices[2], pointer;
355
356 indices[0] = bld_base->uint_bld.zero;
357 indices[1] = index;
358
359 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
360 LLVMBuildStore(gallivm->builder, value, pointer);
361 }
362
363 /**
364 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
365 * It's equivalent to doing a load from &base_ptr[index].
366 *
367 * \param base_ptr Where the array starts.
368 * \param index The element index into the array.
369 */
370 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
374 struct gallivm_state *gallivm = bld_base->base.gallivm;
375 LLVMValueRef indices[2], pointer;
376
377 indices[0] = bld_base->uint_bld.zero;
378 indices[1] = index;
379
380 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
381 return LLVMBuildLoad(gallivm->builder, pointer, "");
382 }
383
384 /**
385 * Do a load from &base_ptr[index], but also add a flag that it's loading
386 * a constant.
387 */
388 static LLVMValueRef build_indexed_load_const(
389 struct si_shader_context * si_shader_ctx,
390 LLVMValueRef base_ptr, LLVMValueRef index)
391 {
392 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
393 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
394 return result;
395 }
396
397 static LLVMValueRef get_instance_index_for_fetch(
398 struct radeon_llvm_context * radeon_bld,
399 unsigned divisor)
400 {
401 struct si_shader_context *si_shader_ctx =
402 si_shader_context(&radeon_bld->soa.bld_base);
403 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
404
405 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
406 si_shader_ctx->param_instance_id);
407
408 /* The division must be done before START_INSTANCE is added. */
409 if (divisor > 1)
410 result = LLVMBuildUDiv(gallivm->builder, result,
411 lp_build_const_int32(gallivm, divisor), "");
412
413 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
414 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
415 }
416
417 static void declare_input_vs(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned input_index,
420 const struct tgsi_full_declaration *decl)
421 {
422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
423 struct gallivm_state *gallivm = base->gallivm;
424 struct si_shader_context *si_shader_ctx =
425 si_shader_context(&radeon_bld->soa.bld_base);
426 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
427
428 unsigned chan;
429
430 LLVMValueRef t_list_ptr;
431 LLVMValueRef t_offset;
432 LLVMValueRef t_list;
433 LLVMValueRef attribute_offset;
434 LLVMValueRef buffer_index;
435 LLVMValueRef args[3];
436 LLVMTypeRef vec4_type;
437 LLVMValueRef input;
438
439 /* Load the T list */
440 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
441
442 t_offset = lp_build_const_int32(gallivm, input_index);
443
444 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
445
446 /* Build the attribute offset */
447 attribute_offset = lp_build_const_int32(gallivm, 0);
448
449 if (divisor) {
450 /* Build index from instance ID, start instance and divisor */
451 si_shader_ctx->shader->uses_instanceid = true;
452 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
453 } else {
454 /* Load the buffer index for vertices. */
455 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_vertex_id);
457 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
458 SI_PARAM_BASE_VERTEX);
459 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
460 }
461
462 vec4_type = LLVMVectorType(base->elem_type, 4);
463 args[0] = t_list;
464 args[1] = attribute_offset;
465 args[2] = buffer_index;
466 input = lp_build_intrinsic(gallivm->builder,
467 "llvm.SI.vs.load.input", vec4_type, args, 3,
468 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
469
470 /* Break up the vec4 into individual components */
471 for (chan = 0; chan < 4; chan++) {
472 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
473 /* XXX: Use a helper function for this. There is one in
474 * tgsi_llvm.c. */
475 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
476 LLVMBuildExtractElement(gallivm->builder,
477 input, llvm_chan, "");
478 }
479 }
480
481 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
482 unsigned swizzle)
483 {
484 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
485
486 if (swizzle > 0)
487 return bld_base->uint_bld.zero;
488
489 switch (si_shader_ctx->type) {
490 case TGSI_PROCESSOR_VERTEX:
491 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
492 si_shader_ctx->param_vs_prim_id);
493 case TGSI_PROCESSOR_TESS_CTRL:
494 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
495 SI_PARAM_PATCH_ID);
496 case TGSI_PROCESSOR_TESS_EVAL:
497 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
498 si_shader_ctx->param_tes_patch_id);
499 case TGSI_PROCESSOR_GEOMETRY:
500 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
501 SI_PARAM_PRIMITIVE_ID);
502 default:
503 assert(0);
504 return bld_base->uint_bld.zero;
505 }
506 }
507
508 /**
509 * Return the value of tgsi_ind_register for indexing.
510 * This is the indirect index with the constant offset added to it.
511 */
512 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
513 const struct tgsi_ind_register *ind,
514 int rel_index)
515 {
516 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
517 LLVMValueRef result;
518
519 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
520 result = LLVMBuildLoad(gallivm->builder, result, "");
521 result = LLVMBuildAdd(gallivm->builder, result,
522 lp_build_const_int32(gallivm, rel_index), "");
523 return result;
524 }
525
526 /**
527 * Calculate a dword address given an input or output register and a stride.
528 */
529 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
530 const struct tgsi_full_dst_register *dst,
531 const struct tgsi_full_src_register *src,
532 LLVMValueRef vertex_dw_stride,
533 LLVMValueRef base_addr)
534 {
535 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
536 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
537 ubyte *name, *index, *array_first;
538 int first, param;
539 struct tgsi_full_dst_register reg;
540
541 /* Set the register description. The address computation is the same
542 * for sources and destinations. */
543 if (src) {
544 reg.Register.File = src->Register.File;
545 reg.Register.Index = src->Register.Index;
546 reg.Register.Indirect = src->Register.Indirect;
547 reg.Register.Dimension = src->Register.Dimension;
548 reg.Indirect = src->Indirect;
549 reg.Dimension = src->Dimension;
550 reg.DimIndirect = src->DimIndirect;
551 } else
552 reg = *dst;
553
554 /* If the register is 2-dimensional (e.g. an array of vertices
555 * in a primitive), calculate the base address of the vertex. */
556 if (reg.Register.Dimension) {
557 LLVMValueRef index;
558
559 if (reg.Dimension.Indirect)
560 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
561 reg.Dimension.Index);
562 else
563 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
564
565 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
566 LLVMBuildMul(gallivm->builder, index,
567 vertex_dw_stride, ""), "");
568 }
569
570 /* Get information about the register. */
571 if (reg.Register.File == TGSI_FILE_INPUT) {
572 name = info->input_semantic_name;
573 index = info->input_semantic_index;
574 array_first = info->input_array_first;
575 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
576 name = info->output_semantic_name;
577 index = info->output_semantic_index;
578 array_first = info->output_array_first;
579 } else {
580 assert(0);
581 return NULL;
582 }
583
584 if (reg.Register.Indirect) {
585 /* Add the relative address of the element. */
586 LLVMValueRef ind_index;
587
588 if (reg.Indirect.ArrayID)
589 first = array_first[reg.Indirect.ArrayID];
590 else
591 first = reg.Register.Index;
592
593 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
594 reg.Register.Index - first);
595
596 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
597 LLVMBuildMul(gallivm->builder, ind_index,
598 lp_build_const_int32(gallivm, 4), ""), "");
599
600 param = si_shader_io_get_unique_index(name[first], index[first]);
601 } else {
602 param = si_shader_io_get_unique_index(name[reg.Register.Index],
603 index[reg.Register.Index]);
604 }
605
606 /* Add the base address of the element. */
607 return LLVMBuildAdd(gallivm->builder, base_addr,
608 lp_build_const_int32(gallivm, param * 4), "");
609 }
610
611 /**
612 * Load from LDS.
613 *
614 * \param type output value type
615 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
616 * \param dw_addr address in dwords
617 */
618 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
619 enum tgsi_opcode_type type, unsigned swizzle,
620 LLVMValueRef dw_addr)
621 {
622 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
623 struct gallivm_state *gallivm = bld_base->base.gallivm;
624 LLVMValueRef value;
625
626 if (swizzle == ~0) {
627 LLVMValueRef values[TGSI_NUM_CHANNELS];
628
629 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
630 values[chan] = lds_load(bld_base, type, chan, dw_addr);
631
632 return lp_build_gather_values(bld_base->base.gallivm, values,
633 TGSI_NUM_CHANNELS);
634 }
635
636 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
637 lp_build_const_int32(gallivm, swizzle));
638
639 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
640 return LLVMBuildBitCast(gallivm->builder, value,
641 tgsi2llvmtype(bld_base, type), "");
642 }
643
644 /**
645 * Store to LDS.
646 *
647 * \param swizzle offset (typically 0..3)
648 * \param dw_addr address in dwords
649 * \param value value to store
650 */
651 static void lds_store(struct lp_build_tgsi_context * bld_base,
652 unsigned swizzle, LLVMValueRef dw_addr,
653 LLVMValueRef value)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct gallivm_state *gallivm = bld_base->base.gallivm;
657
658 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
659 lp_build_const_int32(gallivm, swizzle));
660
661 value = LLVMBuildBitCast(gallivm->builder, value,
662 LLVMInt32TypeInContext(gallivm->context), "");
663 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
664 dw_addr, value);
665 }
666
667 static LLVMValueRef fetch_input_tcs(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
676 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
677 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
678
679 return lds_load(bld_base, type, swizzle, dw_addr);
680 }
681
682 static LLVMValueRef fetch_output_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 if (reg->Register.Dimension) {
691 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
692 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
693 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
694 } else {
695 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
696 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
697 }
698
699 return lds_load(bld_base, type, swizzle, dw_addr);
700 }
701
702 static LLVMValueRef fetch_input_tes(
703 struct lp_build_tgsi_context *bld_base,
704 const struct tgsi_full_src_register *reg,
705 enum tgsi_opcode_type type, unsigned swizzle)
706 {
707 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
708 LLVMValueRef dw_addr, stride;
709
710 if (reg->Register.Dimension) {
711 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
712 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
714 } else {
715 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
716 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
717 }
718
719 return lds_load(bld_base, type, swizzle, dw_addr);
720 }
721
722 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
723 const struct tgsi_full_instruction * inst,
724 const struct tgsi_opcode_info * info,
725 LLVMValueRef dst[4])
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
729 unsigned chan_index;
730 LLVMValueRef dw_addr, stride;
731
732 /* Only handle per-patch and per-vertex outputs here.
733 * Vectors will be lowered to scalars and this function will be called again.
734 */
735 if (reg->Register.File != TGSI_FILE_OUTPUT ||
736 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
737 radeon_llvm_emit_store(bld_base, inst, info, dst);
738 return;
739 }
740
741 if (reg->Register.Dimension) {
742 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
743 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
744 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
745 } else {
746 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
747 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
748 }
749
750 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
751 LLVMValueRef value = dst[chan_index];
752
753 if (inst->Instruction.Saturate)
754 value = radeon_llvm_saturate(bld_base, value);
755
756 lds_store(bld_base, chan_index, dw_addr, value);
757 }
758 }
759
760 static LLVMValueRef fetch_input_gs(
761 struct lp_build_tgsi_context *bld_base,
762 const struct tgsi_full_src_register *reg,
763 enum tgsi_opcode_type type,
764 unsigned swizzle)
765 {
766 struct lp_build_context *base = &bld_base->base;
767 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
768 struct si_shader *shader = si_shader_ctx->shader;
769 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
770 struct gallivm_state *gallivm = base->gallivm;
771 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
772 LLVMValueRef vtx_offset;
773 LLVMValueRef args[9];
774 unsigned vtx_offset_param;
775 struct tgsi_shader_info *info = &shader->selector->info;
776 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
777 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
778
779 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
780 return get_primitive_id(bld_base, swizzle);
781
782 if (!reg->Register.Dimension)
783 return NULL;
784
785 if (swizzle == ~0) {
786 LLVMValueRef values[TGSI_NUM_CHANNELS];
787 unsigned chan;
788 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
789 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
790 }
791 return lp_build_gather_values(bld_base->base.gallivm, values,
792 TGSI_NUM_CHANNELS);
793 }
794
795 /* Get the vertex offset parameter */
796 vtx_offset_param = reg->Dimension.Index;
797 if (vtx_offset_param < 2) {
798 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
799 } else {
800 assert(vtx_offset_param < 6);
801 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
802 }
803 vtx_offset = lp_build_mul_imm(uint,
804 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
805 vtx_offset_param),
806 4);
807
808 args[0] = si_shader_ctx->esgs_ring;
809 args[1] = vtx_offset;
810 args[2] = lp_build_const_int32(gallivm,
811 (get_param_index(semantic_name, semantic_index,
812 shader->selector->inputs_read) * 4 +
813 swizzle) * 256);
814 args[3] = uint->zero;
815 args[4] = uint->one; /* OFFEN */
816 args[5] = uint->zero; /* IDXEN */
817 args[6] = uint->one; /* GLC */
818 args[7] = uint->zero; /* SLC */
819 args[8] = uint->zero; /* TFE */
820
821 return LLVMBuildBitCast(gallivm->builder,
822 lp_build_intrinsic(gallivm->builder,
823 "llvm.SI.buffer.load.dword.i32.i32",
824 i32, args, 9,
825 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
826 tgsi2llvmtype(bld_base, type), "");
827 }
828
829 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
830 {
831 switch (interpolate) {
832 case TGSI_INTERPOLATE_CONSTANT:
833 return 0;
834
835 case TGSI_INTERPOLATE_LINEAR:
836 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
837 return SI_PARAM_LINEAR_SAMPLE;
838 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
839 return SI_PARAM_LINEAR_CENTROID;
840 else
841 return SI_PARAM_LINEAR_CENTER;
842 break;
843 case TGSI_INTERPOLATE_COLOR:
844 case TGSI_INTERPOLATE_PERSPECTIVE:
845 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
846 return SI_PARAM_PERSP_SAMPLE;
847 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
848 return SI_PARAM_PERSP_CENTROID;
849 else
850 return SI_PARAM_PERSP_CENTER;
851 break;
852 default:
853 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
854 return -1;
855 }
856 }
857
858 /* This shouldn't be used by explicit INTERP opcodes. */
859 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
860 unsigned param)
861 {
862 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
863 unsigned sample_param = 0;
864 LLVMValueRef default_ij, sample_ij, force_sample;
865
866 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
867
868 /* If the shader doesn't use center/centroid, just return the parameter.
869 *
870 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
871 * switch between center/centroid and sample without shader changes.
872 */
873 switch (param) {
874 case SI_PARAM_PERSP_CENTROID:
875 case SI_PARAM_PERSP_CENTER:
876 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
877 return default_ij;
878
879 sample_param = SI_PARAM_PERSP_SAMPLE;
880 break;
881
882 case SI_PARAM_LINEAR_CENTROID:
883 case SI_PARAM_LINEAR_CENTER:
884 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
885 return default_ij;
886
887 sample_param = SI_PARAM_LINEAR_SAMPLE;
888 break;
889
890 default:
891 return default_ij;
892 }
893
894 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
895 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
896
897 /* TODO: this can be done more efficiently by switching between
898 * 2 prologs.
899 */
900 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
901 SI_PARAM_PS_STATE_BITS);
902 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
903 LLVMInt1TypeInContext(gallivm->context), "");
904 return LLVMBuildSelect(gallivm->builder, force_sample,
905 sample_ij, default_ij, "");
906 }
907
908 static void declare_input_fs(
909 struct radeon_llvm_context *radeon_bld,
910 unsigned input_index,
911 const struct tgsi_full_declaration *decl)
912 {
913 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
914 struct si_shader_context *si_shader_ctx =
915 si_shader_context(&radeon_bld->soa.bld_base);
916 struct si_shader *shader = si_shader_ctx->shader;
917 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
918 struct gallivm_state *gallivm = base->gallivm;
919 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
920 LLVMValueRef main_fn = radeon_bld->main_fn;
921
922 LLVMValueRef interp_param = NULL;
923 int interp_param_idx;
924 const char * intr_name;
925
926 /* This value is:
927 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
928 * quad begins a new primitive. Bit 0 always needs
929 * to be unset)
930 * [32:16] ParamOffset
931 *
932 */
933 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
934 LLVMValueRef attr_number;
935
936 unsigned chan;
937
938 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
939 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
940 unsigned soa_index =
941 radeon_llvm_reg_index_soa(input_index, chan);
942 radeon_bld->inputs[soa_index] =
943 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
944
945 if (chan == 3)
946 /* RCP for fragcoord.w */
947 radeon_bld->inputs[soa_index] =
948 LLVMBuildFDiv(gallivm->builder,
949 lp_build_const_float(gallivm, 1.0f),
950 radeon_bld->inputs[soa_index],
951 "");
952 }
953 return;
954 }
955
956 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
957 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
958 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
959 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
960 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
961 lp_build_const_float(gallivm, 0.0f);
962 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
963 lp_build_const_float(gallivm, 1.0f);
964
965 return;
966 }
967
968 shader->ps_input_param_offset[input_index] = shader->nparam++;
969 attr_number = lp_build_const_int32(gallivm,
970 shader->ps_input_param_offset[input_index]);
971
972 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
973 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
974 decl->Interp.Location);
975 if (interp_param_idx == -1)
976 return;
977 else if (interp_param_idx)
978 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
979
980 /* fs.constant returns the param from the middle vertex, so it's not
981 * really useful for flat shading. It's meant to be used for custom
982 * interpolation (but the intrinsic can't fetch from the other two
983 * vertices).
984 *
985 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
986 * to do the right thing. The only reason we use fs.constant is that
987 * fs.interp cannot be used on integers, because they can be equal
988 * to NaN.
989 */
990 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
991
992 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
993 si_shader_ctx->shader->key.ps.color_two_side) {
994 LLVMValueRef args[4];
995 LLVMValueRef face, is_face_positive;
996 LLVMValueRef back_attr_number =
997 lp_build_const_int32(gallivm,
998 shader->ps_input_param_offset[input_index] + 1);
999
1000 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
1001
1002 is_face_positive = LLVMBuildFCmp(gallivm->builder,
1003 LLVMRealOGT, face,
1004 lp_build_const_float(gallivm, 0.0f),
1005 "");
1006
1007 args[2] = params;
1008 args[3] = interp_param;
1009 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1010 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1011 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1012 LLVMValueRef front, back;
1013
1014 args[0] = llvm_chan;
1015 args[1] = attr_number;
1016 front = lp_build_intrinsic(gallivm->builder, intr_name,
1017 input_type, args, args[3] ? 4 : 3,
1018 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1019
1020 args[1] = back_attr_number;
1021 back = lp_build_intrinsic(gallivm->builder, intr_name,
1022 input_type, args, args[3] ? 4 : 3,
1023 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1024
1025 radeon_bld->inputs[soa_index] =
1026 LLVMBuildSelect(gallivm->builder,
1027 is_face_positive,
1028 front,
1029 back,
1030 "");
1031 }
1032
1033 shader->nparam++;
1034 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1035 LLVMValueRef args[4];
1036
1037 args[0] = uint->zero;
1038 args[1] = attr_number;
1039 args[2] = params;
1040 args[3] = interp_param;
1041 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1042 lp_build_intrinsic(gallivm->builder, intr_name,
1043 input_type, args, args[3] ? 4 : 3,
1044 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1045 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1046 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1047 lp_build_const_float(gallivm, 0.0f);
1048 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1049 lp_build_const_float(gallivm, 1.0f);
1050 } else {
1051 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1052 LLVMValueRef args[4];
1053 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1054 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1055 args[0] = llvm_chan;
1056 args[1] = attr_number;
1057 args[2] = params;
1058 args[3] = interp_param;
1059 radeon_bld->inputs[soa_index] =
1060 lp_build_intrinsic(gallivm->builder, intr_name,
1061 input_type, args, args[3] ? 4 : 3,
1062 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1063 }
1064 }
1065 }
1066
1067 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1068 {
1069 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1070 SI_PARAM_ANCILLARY, 8, 4);
1071 }
1072
1073 /**
1074 * Load a dword from a constant buffer.
1075 */
1076 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1077 LLVMValueRef offset, LLVMTypeRef return_type)
1078 {
1079 LLVMValueRef args[2] = {resource, offset};
1080
1081 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1082 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1083 }
1084
1085 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1086 {
1087 struct si_shader_context *si_shader_ctx =
1088 si_shader_context(&radeon_bld->soa.bld_base);
1089 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1090 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1091 LLVMBuilderRef builder = gallivm->builder;
1092 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1093 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1094 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1095
1096 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1097 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1098 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1099
1100 LLVMValueRef pos[4] = {
1101 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1102 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1103 lp_build_const_float(gallivm, 0),
1104 lp_build_const_float(gallivm, 0)
1105 };
1106
1107 return lp_build_gather_values(gallivm, pos, 4);
1108 }
1109
1110 static void declare_system_value(
1111 struct radeon_llvm_context * radeon_bld,
1112 unsigned index,
1113 const struct tgsi_full_declaration *decl)
1114 {
1115 struct si_shader_context *si_shader_ctx =
1116 si_shader_context(&radeon_bld->soa.bld_base);
1117 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1118 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1119 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1120 LLVMValueRef value = 0;
1121
1122 switch (decl->Semantic.Name) {
1123 case TGSI_SEMANTIC_INSTANCEID:
1124 value = LLVMGetParam(radeon_bld->main_fn,
1125 si_shader_ctx->param_instance_id);
1126 break;
1127
1128 case TGSI_SEMANTIC_VERTEXID:
1129 value = LLVMBuildAdd(gallivm->builder,
1130 LLVMGetParam(radeon_bld->main_fn,
1131 si_shader_ctx->param_vertex_id),
1132 LLVMGetParam(radeon_bld->main_fn,
1133 SI_PARAM_BASE_VERTEX), "");
1134 break;
1135
1136 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1137 value = LLVMGetParam(radeon_bld->main_fn,
1138 si_shader_ctx->param_vertex_id);
1139 break;
1140
1141 case TGSI_SEMANTIC_BASEVERTEX:
1142 value = LLVMGetParam(radeon_bld->main_fn,
1143 SI_PARAM_BASE_VERTEX);
1144 break;
1145
1146 case TGSI_SEMANTIC_INVOCATIONID:
1147 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1148 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1149 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1150 value = LLVMGetParam(radeon_bld->main_fn,
1151 SI_PARAM_GS_INSTANCE_ID);
1152 else
1153 assert(!"INVOCATIONID not implemented");
1154 break;
1155
1156 case TGSI_SEMANTIC_SAMPLEID:
1157 value = get_sample_id(radeon_bld);
1158 break;
1159
1160 case TGSI_SEMANTIC_SAMPLEPOS:
1161 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1162 break;
1163
1164 case TGSI_SEMANTIC_SAMPLEMASK:
1165 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1166 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1167 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1168 value = uint_bld->one;
1169 else
1170 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1171 break;
1172
1173 case TGSI_SEMANTIC_TESSCOORD:
1174 {
1175 LLVMValueRef coord[4] = {
1176 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1177 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1178 bld->zero,
1179 bld->zero
1180 };
1181
1182 /* For triangles, the vector should be (u, v, 1-u-v). */
1183 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1184 PIPE_PRIM_TRIANGLES)
1185 coord[2] = lp_build_sub(bld, bld->one,
1186 lp_build_add(bld, coord[0], coord[1]));
1187
1188 value = lp_build_gather_values(gallivm, coord, 4);
1189 break;
1190 }
1191
1192 case TGSI_SEMANTIC_VERTICESIN:
1193 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1194 break;
1195
1196 case TGSI_SEMANTIC_TESSINNER:
1197 case TGSI_SEMANTIC_TESSOUTER:
1198 {
1199 LLVMValueRef dw_addr;
1200 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1201
1202 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1203 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1204 lp_build_const_int32(gallivm, param * 4), "");
1205
1206 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1207 ~0, dw_addr);
1208 break;
1209 }
1210
1211 case TGSI_SEMANTIC_PRIMID:
1212 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1213 break;
1214
1215 default:
1216 assert(!"unknown system value");
1217 return;
1218 }
1219
1220 radeon_bld->system_values[index] = value;
1221 }
1222
1223 static LLVMValueRef fetch_constant(
1224 struct lp_build_tgsi_context * bld_base,
1225 const struct tgsi_full_src_register *reg,
1226 enum tgsi_opcode_type type,
1227 unsigned swizzle)
1228 {
1229 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1230 struct lp_build_context * base = &bld_base->base;
1231 const struct tgsi_ind_register *ireg = &reg->Indirect;
1232 unsigned buf, idx;
1233
1234 LLVMValueRef addr, bufp;
1235 LLVMValueRef result;
1236
1237 if (swizzle == LP_CHAN_ALL) {
1238 unsigned chan;
1239 LLVMValueRef values[4];
1240 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1241 values[chan] = fetch_constant(bld_base, reg, type, chan);
1242
1243 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1244 }
1245
1246 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1247 idx = reg->Register.Index * 4 + swizzle;
1248
1249 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1250 if (type != TGSI_TYPE_DOUBLE)
1251 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1252 else {
1253 return radeon_llvm_emit_fetch_double(bld_base,
1254 si_shader_ctx->constants[buf][idx],
1255 si_shader_ctx->constants[buf][idx + 1]);
1256 }
1257 }
1258
1259 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1260 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1261 LLVMValueRef index;
1262 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1263 reg->Dimension.Index);
1264 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1265 } else
1266 bufp = si_shader_ctx->const_resource[buf];
1267
1268 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1269 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1270 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1271 addr = lp_build_add(&bld_base->uint_bld, addr,
1272 lp_build_const_int32(base->gallivm, idx * 4));
1273
1274 result = buffer_load_const(base->gallivm->builder, bufp,
1275 addr, bld_base->base.elem_type);
1276
1277 if (type != TGSI_TYPE_DOUBLE)
1278 result = bitcast(bld_base, type, result);
1279 else {
1280 LLVMValueRef addr2, result2;
1281 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1282 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1283 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1284 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1285 lp_build_const_int32(base->gallivm, idx * 4));
1286
1287 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1288 addr2, bld_base->base.elem_type);
1289
1290 result = radeon_llvm_emit_fetch_double(bld_base,
1291 result, result2);
1292 }
1293 return result;
1294 }
1295
1296 /* Initialize arguments for the shader export intrinsic */
1297 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1298 LLVMValueRef *values,
1299 unsigned target,
1300 LLVMValueRef *args)
1301 {
1302 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1303 struct lp_build_context *uint =
1304 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1305 struct lp_build_context *base = &bld_base->base;
1306 unsigned compressed = 0;
1307 unsigned chan;
1308
1309 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1310 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1311
1312 if (cbuf >= 0 && cbuf < 8) {
1313 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1314
1315 if (compressed)
1316 si_shader_ctx->shader->spi_shader_col_format |=
1317 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1318 else
1319 si_shader_ctx->shader->spi_shader_col_format |=
1320 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1321
1322 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1323 }
1324 }
1325
1326 if (compressed) {
1327 /* Pixel shader needs to pack output values before export */
1328 for (chan = 0; chan < 2; chan++ ) {
1329 args[0] = values[2 * chan];
1330 args[1] = values[2 * chan + 1];
1331 args[chan + 5] =
1332 lp_build_intrinsic(base->gallivm->builder,
1333 "llvm.SI.packf16",
1334 LLVMInt32TypeInContext(base->gallivm->context),
1335 args, 2,
1336 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1337 args[chan + 7] = args[chan + 5] =
1338 LLVMBuildBitCast(base->gallivm->builder,
1339 args[chan + 5],
1340 LLVMFloatTypeInContext(base->gallivm->context),
1341 "");
1342 }
1343
1344 /* Set COMPR flag */
1345 args[4] = uint->one;
1346 } else {
1347 for (chan = 0; chan < 4; chan++ )
1348 /* +5 because the first output value will be
1349 * the 6th argument to the intrinsic. */
1350 args[chan + 5] = values[chan];
1351
1352 /* Clear COMPR flag */
1353 args[4] = uint->zero;
1354 }
1355
1356 /* XXX: This controls which components of the output
1357 * registers actually get exported. (e.g bit 0 means export
1358 * X component, bit 1 means export Y component, etc.) I'm
1359 * hard coding this to 0xf for now. In the future, we might
1360 * want to do something else. */
1361 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1362
1363 /* Specify whether the EXEC mask represents the valid mask */
1364 args[1] = uint->zero;
1365
1366 /* Specify whether this is the last export */
1367 args[2] = uint->zero;
1368
1369 /* Specify the target we are exporting */
1370 args[3] = lp_build_const_int32(base->gallivm, target);
1371
1372 /* XXX: We probably need to keep track of the output
1373 * values, so we know what we are passing to the next
1374 * stage. */
1375 }
1376
1377 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1378 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1379 LLVMValueRef *out_ptr,
1380 unsigned target,
1381 LLVMValueRef *args)
1382 {
1383 struct gallivm_state *gallivm = bld_base->base.gallivm;
1384 LLVMValueRef values[4];
1385 int i;
1386
1387 for (i = 0; i < 4; i++)
1388 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1389
1390 si_llvm_init_export_args(bld_base, values, target, args);
1391 }
1392
1393 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1394 LLVMValueRef alpha_ptr)
1395 {
1396 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1397 struct gallivm_state *gallivm = bld_base->base.gallivm;
1398
1399 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1400 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1401 SI_PARAM_ALPHA_REF);
1402
1403 LLVMValueRef alpha_pass =
1404 lp_build_cmp(&bld_base->base,
1405 si_shader_ctx->shader->key.ps.alpha_func,
1406 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1407 alpha_ref);
1408 LLVMValueRef arg =
1409 lp_build_select(&bld_base->base,
1410 alpha_pass,
1411 lp_build_const_float(gallivm, 1.0f),
1412 lp_build_const_float(gallivm, -1.0f));
1413
1414 lp_build_intrinsic(gallivm->builder,
1415 "llvm.AMDGPU.kill",
1416 LLVMVoidTypeInContext(gallivm->context),
1417 &arg, 1, 0);
1418 } else {
1419 lp_build_intrinsic(gallivm->builder,
1420 "llvm.AMDGPU.kilp",
1421 LLVMVoidTypeInContext(gallivm->context),
1422 NULL, 0, 0);
1423 }
1424
1425 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1426 }
1427
1428 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1429 LLVMValueRef alpha_ptr)
1430 {
1431 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1432 struct gallivm_state *gallivm = bld_base->base.gallivm;
1433 LLVMValueRef coverage, alpha;
1434
1435 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1436 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1437 SI_PARAM_SAMPLE_COVERAGE);
1438 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1439
1440 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1441 bld_base->int_bld.elem_type,
1442 &coverage, 1, LLVMReadNoneAttribute);
1443
1444 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1445 bld_base->base.elem_type, "");
1446
1447 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1448 lp_build_const_float(gallivm,
1449 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1450
1451 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1452 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1453 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1454 }
1455
1456 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1457 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1458 {
1459 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1460 struct lp_build_context *base = &bld_base->base;
1461 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1462 unsigned reg_index;
1463 unsigned chan;
1464 unsigned const_chan;
1465 LLVMValueRef base_elt;
1466 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1467 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1468 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1469
1470 for (reg_index = 0; reg_index < 2; reg_index ++) {
1471 LLVMValueRef *args = pos[2 + reg_index];
1472
1473 args[5] =
1474 args[6] =
1475 args[7] =
1476 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1477
1478 /* Compute dot products of position and user clip plane vectors */
1479 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1480 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1481 args[1] = lp_build_const_int32(base->gallivm,
1482 ((reg_index * 4 + chan) * 4 +
1483 const_chan) * 4);
1484 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1485 args[1], base->elem_type);
1486 args[5 + chan] =
1487 lp_build_add(base, args[5 + chan],
1488 lp_build_mul(base, base_elt,
1489 out_elts[const_chan]));
1490 }
1491 }
1492
1493 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1494 args[1] = uint->zero;
1495 args[2] = uint->zero;
1496 args[3] = lp_build_const_int32(base->gallivm,
1497 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1498 args[4] = uint->zero;
1499 }
1500 }
1501
1502 static void si_dump_streamout(struct pipe_stream_output_info *so)
1503 {
1504 unsigned i;
1505
1506 if (so->num_outputs)
1507 fprintf(stderr, "STREAMOUT\n");
1508
1509 for (i = 0; i < so->num_outputs; i++) {
1510 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1511 so->output[i].start_component;
1512 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1513 i, so->output[i].output_buffer,
1514 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1515 so->output[i].register_index,
1516 mask & 1 ? "x" : "",
1517 mask & 2 ? "y" : "",
1518 mask & 4 ? "z" : "",
1519 mask & 8 ? "w" : "");
1520 }
1521 }
1522
1523 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1524 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1525 * or v4i32 (num_channels=3,4). */
1526 static void build_tbuffer_store(struct si_shader_context *shader,
1527 LLVMValueRef rsrc,
1528 LLVMValueRef vdata,
1529 unsigned num_channels,
1530 LLVMValueRef vaddr,
1531 LLVMValueRef soffset,
1532 unsigned inst_offset,
1533 unsigned dfmt,
1534 unsigned nfmt,
1535 unsigned offen,
1536 unsigned idxen,
1537 unsigned glc,
1538 unsigned slc,
1539 unsigned tfe)
1540 {
1541 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1542 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1543 LLVMValueRef args[] = {
1544 rsrc,
1545 vdata,
1546 LLVMConstInt(i32, num_channels, 0),
1547 vaddr,
1548 soffset,
1549 LLVMConstInt(i32, inst_offset, 0),
1550 LLVMConstInt(i32, dfmt, 0),
1551 LLVMConstInt(i32, nfmt, 0),
1552 LLVMConstInt(i32, offen, 0),
1553 LLVMConstInt(i32, idxen, 0),
1554 LLVMConstInt(i32, glc, 0),
1555 LLVMConstInt(i32, slc, 0),
1556 LLVMConstInt(i32, tfe, 0)
1557 };
1558
1559 /* The instruction offset field has 12 bits */
1560 assert(offen || inst_offset < (1 << 12));
1561
1562 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1563 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1564 const char *types[] = {"i32", "v2i32", "v4i32"};
1565 char name[256];
1566 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1567
1568 lp_build_intrinsic(gallivm->builder, name,
1569 LLVMVoidTypeInContext(gallivm->context),
1570 args, Elements(args), 0);
1571 }
1572
1573 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1574 LLVMValueRef rsrc,
1575 LLVMValueRef vdata,
1576 unsigned num_channels,
1577 LLVMValueRef vaddr,
1578 LLVMValueRef soffset,
1579 unsigned inst_offset)
1580 {
1581 static unsigned dfmt[] = {
1582 V_008F0C_BUF_DATA_FORMAT_32,
1583 V_008F0C_BUF_DATA_FORMAT_32_32,
1584 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1585 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1586 };
1587 assert(num_channels >= 1 && num_channels <= 4);
1588
1589 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1590 inst_offset, dfmt[num_channels-1],
1591 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1592 }
1593
1594 /* On SI, the vertex shader is responsible for writing streamout data
1595 * to buffers. */
1596 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1597 struct si_shader_output_values *outputs,
1598 unsigned noutput)
1599 {
1600 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1601 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1602 LLVMBuilderRef builder = gallivm->builder;
1603 int i, j;
1604 struct lp_build_if_state if_ctx;
1605
1606 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1607
1608 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1609 LLVMValueRef so_vtx_count =
1610 unpack_param(shader, shader->param_streamout_config, 16, 7);
1611
1612 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1613 NULL, 0, LLVMReadNoneAttribute);
1614
1615 /* can_emit = tid < so_vtx_count; */
1616 LLVMValueRef can_emit =
1617 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1618
1619 LLVMValueRef stream_id =
1620 unpack_param(shader, shader->param_streamout_config, 24, 2);
1621
1622 /* Emit the streamout code conditionally. This actually avoids
1623 * out-of-bounds buffer access. The hw tells us via the SGPR
1624 * (so_vtx_count) which threads are allowed to emit streamout data. */
1625 lp_build_if(&if_ctx, gallivm, can_emit);
1626 {
1627 /* The buffer offset is computed as follows:
1628 * ByteOffset = streamout_offset[buffer_id]*4 +
1629 * (streamout_write_index + thread_id)*stride[buffer_id] +
1630 * attrib_offset
1631 */
1632
1633 LLVMValueRef so_write_index =
1634 LLVMGetParam(shader->radeon_bld.main_fn,
1635 shader->param_streamout_write_index);
1636
1637 /* Compute (streamout_write_index + thread_id). */
1638 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1639
1640 /* Compute the write offset for each enabled buffer. */
1641 LLVMValueRef so_write_offset[4] = {};
1642 for (i = 0; i < 4; i++) {
1643 if (!so->stride[i])
1644 continue;
1645
1646 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1647 shader->param_streamout_offset[i]);
1648 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1649
1650 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1651 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1652 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1653 }
1654
1655 /* Write streamout data. */
1656 for (i = 0; i < so->num_outputs; i++) {
1657 unsigned buf_idx = so->output[i].output_buffer;
1658 unsigned reg = so->output[i].register_index;
1659 unsigned start = so->output[i].start_component;
1660 unsigned num_comps = so->output[i].num_components;
1661 unsigned stream = so->output[i].stream;
1662 LLVMValueRef out[4];
1663 struct lp_build_if_state if_ctx_stream;
1664
1665 assert(num_comps && num_comps <= 4);
1666 if (!num_comps || num_comps > 4)
1667 continue;
1668
1669 if (reg >= noutput)
1670 continue;
1671
1672 /* Load the output as int. */
1673 for (j = 0; j < num_comps; j++) {
1674 out[j] = LLVMBuildBitCast(builder,
1675 outputs[reg].values[start+j],
1676 i32, "");
1677 }
1678
1679 /* Pack the output. */
1680 LLVMValueRef vdata = NULL;
1681
1682 switch (num_comps) {
1683 case 1: /* as i32 */
1684 vdata = out[0];
1685 break;
1686 case 2: /* as v2i32 */
1687 case 3: /* as v4i32 (aligned to 4) */
1688 case 4: /* as v4i32 */
1689 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1690 for (j = 0; j < num_comps; j++) {
1691 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1692 LLVMConstInt(i32, j, 0), "");
1693 }
1694 break;
1695 }
1696
1697 LLVMValueRef can_emit_stream =
1698 LLVMBuildICmp(builder, LLVMIntEQ,
1699 stream_id,
1700 lp_build_const_int32(gallivm, stream), "");
1701
1702 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1703 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1704 vdata, num_comps,
1705 so_write_offset[buf_idx],
1706 LLVMConstInt(i32, 0, 0),
1707 so->output[i].dst_offset*4);
1708 lp_build_endif(&if_ctx_stream);
1709 }
1710 }
1711 lp_build_endif(&if_ctx);
1712 }
1713
1714
1715 /* Generate export instructions for hardware VS shader stage */
1716 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1717 struct si_shader_output_values *outputs,
1718 unsigned noutput)
1719 {
1720 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1721 struct si_shader * shader = si_shader_ctx->shader;
1722 struct lp_build_context * base = &bld_base->base;
1723 struct lp_build_context * uint =
1724 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1725 LLVMValueRef args[9];
1726 LLVMValueRef pos_args[4][9] = { { 0 } };
1727 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1728 unsigned semantic_name, semantic_index;
1729 unsigned target;
1730 unsigned param_count = 0;
1731 unsigned pos_idx;
1732 int i;
1733
1734 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1735 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1736 }
1737
1738 for (i = 0; i < noutput; i++) {
1739 semantic_name = outputs[i].name;
1740 semantic_index = outputs[i].sid;
1741
1742 handle_semantic:
1743 /* Select the correct target */
1744 switch(semantic_name) {
1745 case TGSI_SEMANTIC_PSIZE:
1746 psize_value = outputs[i].values[0];
1747 continue;
1748 case TGSI_SEMANTIC_EDGEFLAG:
1749 edgeflag_value = outputs[i].values[0];
1750 continue;
1751 case TGSI_SEMANTIC_LAYER:
1752 layer_value = outputs[i].values[0];
1753 semantic_name = TGSI_SEMANTIC_GENERIC;
1754 goto handle_semantic;
1755 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1756 viewport_index_value = outputs[i].values[0];
1757 semantic_name = TGSI_SEMANTIC_GENERIC;
1758 goto handle_semantic;
1759 case TGSI_SEMANTIC_POSITION:
1760 target = V_008DFC_SQ_EXP_POS;
1761 break;
1762 case TGSI_SEMANTIC_COLOR:
1763 case TGSI_SEMANTIC_BCOLOR:
1764 target = V_008DFC_SQ_EXP_PARAM + param_count;
1765 shader->vs_output_param_offset[i] = param_count;
1766 param_count++;
1767 break;
1768 case TGSI_SEMANTIC_CLIPDIST:
1769 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1770 break;
1771 case TGSI_SEMANTIC_CLIPVERTEX:
1772 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1773 continue;
1774 case TGSI_SEMANTIC_PRIMID:
1775 case TGSI_SEMANTIC_FOG:
1776 case TGSI_SEMANTIC_TEXCOORD:
1777 case TGSI_SEMANTIC_GENERIC:
1778 target = V_008DFC_SQ_EXP_PARAM + param_count;
1779 shader->vs_output_param_offset[i] = param_count;
1780 param_count++;
1781 break;
1782 default:
1783 target = 0;
1784 fprintf(stderr,
1785 "Warning: SI unhandled vs output type:%d\n",
1786 semantic_name);
1787 }
1788
1789 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1790
1791 if (target >= V_008DFC_SQ_EXP_POS &&
1792 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1793 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1794 args, sizeof(args));
1795 } else {
1796 lp_build_intrinsic(base->gallivm->builder,
1797 "llvm.SI.export",
1798 LLVMVoidTypeInContext(base->gallivm->context),
1799 args, 9, 0);
1800 }
1801
1802 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1803 semantic_name = TGSI_SEMANTIC_GENERIC;
1804 goto handle_semantic;
1805 }
1806 }
1807
1808 shader->nr_param_exports = param_count;
1809
1810 /* We need to add the position output manually if it's missing. */
1811 if (!pos_args[0][0]) {
1812 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1813 pos_args[0][1] = uint->zero; /* EXEC mask */
1814 pos_args[0][2] = uint->zero; /* last export? */
1815 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1816 pos_args[0][4] = uint->zero; /* COMPR flag */
1817 pos_args[0][5] = base->zero; /* X */
1818 pos_args[0][6] = base->zero; /* Y */
1819 pos_args[0][7] = base->zero; /* Z */
1820 pos_args[0][8] = base->one; /* W */
1821 }
1822
1823 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1824 if (shader->selector->info.writes_psize ||
1825 shader->selector->info.writes_edgeflag ||
1826 shader->selector->info.writes_viewport_index ||
1827 shader->selector->info.writes_layer) {
1828 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1829 shader->selector->info.writes_psize |
1830 (shader->selector->info.writes_edgeflag << 1) |
1831 (shader->selector->info.writes_layer << 2) |
1832 (shader->selector->info.writes_viewport_index << 3));
1833 pos_args[1][1] = uint->zero; /* EXEC mask */
1834 pos_args[1][2] = uint->zero; /* last export? */
1835 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1836 pos_args[1][4] = uint->zero; /* COMPR flag */
1837 pos_args[1][5] = base->zero; /* X */
1838 pos_args[1][6] = base->zero; /* Y */
1839 pos_args[1][7] = base->zero; /* Z */
1840 pos_args[1][8] = base->zero; /* W */
1841
1842 if (shader->selector->info.writes_psize)
1843 pos_args[1][5] = psize_value;
1844
1845 if (shader->selector->info.writes_edgeflag) {
1846 /* The output is a float, but the hw expects an integer
1847 * with the first bit containing the edge flag. */
1848 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1849 edgeflag_value,
1850 bld_base->uint_bld.elem_type, "");
1851 edgeflag_value = lp_build_min(&bld_base->int_bld,
1852 edgeflag_value,
1853 bld_base->int_bld.one);
1854
1855 /* The LLVM intrinsic expects a float. */
1856 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1857 edgeflag_value,
1858 base->elem_type, "");
1859 }
1860
1861 if (shader->selector->info.writes_layer)
1862 pos_args[1][7] = layer_value;
1863
1864 if (shader->selector->info.writes_viewport_index)
1865 pos_args[1][8] = viewport_index_value;
1866 }
1867
1868 for (i = 0; i < 4; i++)
1869 if (pos_args[i][0])
1870 shader->nr_pos_exports++;
1871
1872 pos_idx = 0;
1873 for (i = 0; i < 4; i++) {
1874 if (!pos_args[i][0])
1875 continue;
1876
1877 /* Specify the target we are exporting */
1878 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1879
1880 if (pos_idx == shader->nr_pos_exports)
1881 /* Specify that this is the last export */
1882 pos_args[i][2] = uint->one;
1883
1884 lp_build_intrinsic(base->gallivm->builder,
1885 "llvm.SI.export",
1886 LLVMVoidTypeInContext(base->gallivm->context),
1887 pos_args[i], 9, 0);
1888 }
1889 }
1890
1891 /* This only writes the tessellation factor levels. */
1892 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1893 {
1894 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1895 struct gallivm_state *gallivm = bld_base->base.gallivm;
1896 struct si_shader *shader = si_shader_ctx->shader;
1897 unsigned tess_inner_index, tess_outer_index;
1898 LLVMValueRef lds_base, lds_inner, lds_outer;
1899 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1900 LLVMValueRef out[6], vec0, vec1, invocation_id;
1901 unsigned stride, outer_comps, inner_comps, i;
1902 struct lp_build_if_state if_ctx;
1903
1904 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1905
1906 /* Do this only for invocation 0, because the tess levels are per-patch,
1907 * not per-vertex.
1908 *
1909 * This can't jump, because invocation 0 executes this. It should
1910 * at least mask out the loads and stores for other invocations.
1911 */
1912 lp_build_if(&if_ctx, gallivm,
1913 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1914 invocation_id, bld_base->uint_bld.zero, ""));
1915
1916 /* Determine the layout of one tess factor element in the buffer. */
1917 switch (shader->key.tcs.prim_mode) {
1918 case PIPE_PRIM_LINES:
1919 stride = 2; /* 2 dwords, 1 vec2 store */
1920 outer_comps = 2;
1921 inner_comps = 0;
1922 break;
1923 case PIPE_PRIM_TRIANGLES:
1924 stride = 4; /* 4 dwords, 1 vec4 store */
1925 outer_comps = 3;
1926 inner_comps = 1;
1927 break;
1928 case PIPE_PRIM_QUADS:
1929 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1930 outer_comps = 4;
1931 inner_comps = 2;
1932 break;
1933 default:
1934 assert(0);
1935 return;
1936 }
1937
1938 /* Load tess_inner and tess_outer from LDS.
1939 * Any invocation can write them, so we can't get them from a temporary.
1940 */
1941 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1942 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1943
1944 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1945 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1946 lp_build_const_int32(gallivm,
1947 tess_inner_index * 4), "");
1948 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1949 lp_build_const_int32(gallivm,
1950 tess_outer_index * 4), "");
1951
1952 for (i = 0; i < outer_comps; i++)
1953 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1954 for (i = 0; i < inner_comps; i++)
1955 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1956
1957 /* Convert the outputs to vectors for stores. */
1958 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1959 vec1 = NULL;
1960
1961 if (stride > 4)
1962 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1963
1964 /* Get the buffer. */
1965 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1966 SI_PARAM_RW_BUFFERS);
1967 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1968 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1969
1970 /* Get the offset. */
1971 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1972 SI_PARAM_TESS_FACTOR_OFFSET);
1973 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1974 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1975 lp_build_const_int32(gallivm, 4 * stride), "");
1976
1977 /* Store the outputs. */
1978 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1979 MIN2(stride, 4), byteoffset, tf_base, 0);
1980 if (vec1)
1981 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1982 stride - 4, byteoffset, tf_base, 16);
1983 lp_build_endif(&if_ctx);
1984 }
1985
1986 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1987 {
1988 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1989 struct si_shader *shader = si_shader_ctx->shader;
1990 struct tgsi_shader_info *info = &shader->selector->info;
1991 struct gallivm_state *gallivm = bld_base->base.gallivm;
1992 unsigned i, chan;
1993 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1994 si_shader_ctx->param_rel_auto_id);
1995 LLVMValueRef vertex_dw_stride =
1996 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1997 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1998 vertex_dw_stride, "");
1999
2000 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2001 * its inputs from it. */
2002 for (i = 0; i < info->num_outputs; i++) {
2003 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2004 unsigned name = info->output_semantic_name[i];
2005 unsigned index = info->output_semantic_index[i];
2006 int param = si_shader_io_get_unique_index(name, index);
2007 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2008 lp_build_const_int32(gallivm, param * 4), "");
2009
2010 for (chan = 0; chan < 4; chan++) {
2011 lds_store(bld_base, chan, dw_addr,
2012 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2013 }
2014 }
2015 }
2016
2017 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2018 {
2019 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2020 struct gallivm_state *gallivm = bld_base->base.gallivm;
2021 struct si_shader *es = si_shader_ctx->shader;
2022 struct tgsi_shader_info *info = &es->selector->info;
2023 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2024 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2025 si_shader_ctx->param_es2gs_offset);
2026 uint64_t enabled_outputs = si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL ?
2027 es->key.tes.es_enabled_outputs :
2028 es->key.vs.es_enabled_outputs;
2029 unsigned chan;
2030 int i;
2031
2032 for (i = 0; i < info->num_outputs; i++) {
2033 LLVMValueRef *out_ptr =
2034 si_shader_ctx->radeon_bld.soa.outputs[i];
2035 int param_index;
2036
2037 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2038 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2039 continue;
2040
2041 param_index = get_param_index(info->output_semantic_name[i],
2042 info->output_semantic_index[i],
2043 enabled_outputs);
2044 if (param_index < 0)
2045 continue;
2046
2047 for (chan = 0; chan < 4; chan++) {
2048 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2049 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2050
2051 build_tbuffer_store(si_shader_ctx,
2052 si_shader_ctx->esgs_ring,
2053 out_val, 1,
2054 LLVMGetUndef(i32), soffset,
2055 (4 * param_index + chan) * 4,
2056 V_008F0C_BUF_DATA_FORMAT_32,
2057 V_008F0C_BUF_NUM_FORMAT_UINT,
2058 0, 0, 1, 1, 0);
2059 }
2060 }
2061 }
2062
2063 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2064 {
2065 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2066 struct gallivm_state *gallivm = bld_base->base.gallivm;
2067 LLVMValueRef args[2];
2068
2069 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2070 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2071 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2072 LLVMVoidTypeInContext(gallivm->context), args, 2,
2073 LLVMNoUnwindAttribute);
2074 }
2075
2076 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2077 {
2078 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2079 struct gallivm_state *gallivm = bld_base->base.gallivm;
2080 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2081 struct si_shader_output_values *outputs = NULL;
2082 int i,j;
2083
2084 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2085
2086 for (i = 0; i < info->num_outputs; i++) {
2087 outputs[i].name = info->output_semantic_name[i];
2088 outputs[i].sid = info->output_semantic_index[i];
2089
2090 for (j = 0; j < 4; j++)
2091 outputs[i].values[j] =
2092 LLVMBuildLoad(gallivm->builder,
2093 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2094 "");
2095 }
2096
2097 /* Export PrimitiveID when PS needs it. */
2098 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2099 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2100 outputs[i].sid = 0;
2101 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 get_primitive_id(bld_base, 0));
2103 outputs[i].values[1] = bld_base->base.undef;
2104 outputs[i].values[2] = bld_base->base.undef;
2105 outputs[i].values[3] = bld_base->base.undef;
2106 i++;
2107 }
2108
2109 si_llvm_export_vs(bld_base, outputs, i);
2110 FREE(outputs);
2111 }
2112
2113 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2114 {
2115 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2116 struct si_shader * shader = si_shader_ctx->shader;
2117 struct lp_build_context * base = &bld_base->base;
2118 struct lp_build_context * uint = &bld_base->uint_bld;
2119 struct tgsi_shader_info *info = &shader->selector->info;
2120 LLVMValueRef args[9];
2121 LLVMValueRef last_args[9] = { 0 };
2122 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2123 int i;
2124
2125 for (i = 0; i < info->num_outputs; i++) {
2126 unsigned semantic_name = info->output_semantic_name[i];
2127 unsigned semantic_index = info->output_semantic_index[i];
2128 unsigned target;
2129 LLVMValueRef alpha_ptr;
2130
2131 /* Select the correct target */
2132 switch (semantic_name) {
2133 case TGSI_SEMANTIC_POSITION:
2134 depth_index = i;
2135 continue;
2136 case TGSI_SEMANTIC_STENCIL:
2137 stencil_index = i;
2138 continue;
2139 case TGSI_SEMANTIC_SAMPLEMASK:
2140 samplemask_index = i;
2141 continue;
2142 case TGSI_SEMANTIC_COLOR:
2143 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2144 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2145
2146 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2147 LLVMBuildStore(base->gallivm->builder,
2148 base->one, alpha_ptr);
2149
2150 if (semantic_index == 0 &&
2151 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2152 si_alpha_test(bld_base, alpha_ptr);
2153
2154 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2155 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2156 break;
2157 default:
2158 target = 0;
2159 fprintf(stderr,
2160 "Warning: SI unhandled fs output type:%d\n",
2161 semantic_name);
2162 }
2163
2164 si_llvm_init_export_args_load(bld_base,
2165 si_shader_ctx->radeon_bld.soa.outputs[i],
2166 target, args);
2167
2168 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2169 /* If there is an export instruction waiting to be emitted, do so now. */
2170 if (last_args[0]) {
2171 lp_build_intrinsic(base->gallivm->builder,
2172 "llvm.SI.export",
2173 LLVMVoidTypeInContext(base->gallivm->context),
2174 last_args, 9, 0);
2175 }
2176
2177 /* This instruction will be emitted at the end of the shader. */
2178 memcpy(last_args, args, sizeof(args));
2179
2180 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2181 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2182 semantic_index == 0 &&
2183 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2184 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2185 si_llvm_init_export_args_load(bld_base,
2186 si_shader_ctx->radeon_bld.soa.outputs[i],
2187 V_008DFC_SQ_EXP_MRT + c, args);
2188 lp_build_intrinsic(base->gallivm->builder,
2189 "llvm.SI.export",
2190 LLVMVoidTypeInContext(base->gallivm->context),
2191 args, 9, 0);
2192 }
2193 }
2194 } else {
2195 lp_build_intrinsic(base->gallivm->builder,
2196 "llvm.SI.export",
2197 LLVMVoidTypeInContext(base->gallivm->context),
2198 args, 9, 0);
2199 }
2200 }
2201
2202 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2203 LLVMValueRef out_ptr;
2204 unsigned mask = 0;
2205
2206 /* Specify the target we are exporting */
2207 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2208
2209 args[5] = base->zero; /* R, depth */
2210 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2211 args[7] = base->zero; /* B, sample mask */
2212 args[8] = base->zero; /* A, alpha to mask */
2213
2214 if (depth_index >= 0) {
2215 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2216 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2217 mask |= 0x1;
2218 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2219 }
2220
2221 if (stencil_index >= 0) {
2222 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2223 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2224 mask |= 0x2;
2225 si_shader_ctx->shader->db_shader_control |=
2226 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2227 }
2228
2229 if (samplemask_index >= 0) {
2230 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2231 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2232 mask |= 0x4;
2233 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2234 }
2235
2236 /* SI (except OLAND) has a bug that it only looks
2237 * at the X writemask component. */
2238 if (si_shader_ctx->screen->b.chip_class == SI &&
2239 si_shader_ctx->screen->b.family != CHIP_OLAND)
2240 mask |= 0x1;
2241
2242 if (samplemask_index >= 0)
2243 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2244 else if (stencil_index >= 0)
2245 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2246 else
2247 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2248
2249 /* Specify which components to enable */
2250 args[0] = lp_build_const_int32(base->gallivm, mask);
2251
2252 args[1] =
2253 args[2] =
2254 args[4] = uint->zero;
2255
2256 if (last_args[0])
2257 lp_build_intrinsic(base->gallivm->builder,
2258 "llvm.SI.export",
2259 LLVMVoidTypeInContext(base->gallivm->context),
2260 args, 9, 0);
2261 else
2262 memcpy(last_args, args, sizeof(args));
2263 }
2264
2265 if (!last_args[0]) {
2266 /* Specify which components to enable */
2267 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2268
2269 /* Specify the target we are exporting */
2270 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2271
2272 /* Set COMPR flag to zero to export data as 32-bit */
2273 last_args[4] = uint->zero;
2274
2275 /* dummy bits */
2276 last_args[5]= uint->zero;
2277 last_args[6]= uint->zero;
2278 last_args[7]= uint->zero;
2279 last_args[8]= uint->zero;
2280 }
2281
2282 /* Specify whether the EXEC mask represents the valid mask */
2283 last_args[1] = uint->one;
2284
2285 /* Specify that this is the last export */
2286 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2287
2288 lp_build_intrinsic(base->gallivm->builder,
2289 "llvm.SI.export",
2290 LLVMVoidTypeInContext(base->gallivm->context),
2291 last_args, 9, 0);
2292 }
2293
2294 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2295 struct lp_build_tgsi_context * bld_base,
2296 struct lp_build_emit_data * emit_data);
2297
2298 static bool tgsi_is_array_sampler(unsigned target)
2299 {
2300 return target == TGSI_TEXTURE_1D_ARRAY ||
2301 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2302 target == TGSI_TEXTURE_2D_ARRAY ||
2303 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2304 target == TGSI_TEXTURE_CUBE_ARRAY ||
2305 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2306 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2307 }
2308
2309 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2310 struct lp_build_emit_data *emit_data,
2311 unsigned opcode, unsigned target,
2312 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2313 LLVMValueRef *param, unsigned count,
2314 unsigned dmask)
2315 {
2316 unsigned num_args;
2317 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2318 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2319
2320 /* Pad to power of two vector */
2321 while (count < util_next_power_of_two(count))
2322 param[count++] = LLVMGetUndef(i32);
2323
2324 /* Texture coordinates. */
2325 if (count > 1)
2326 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2327 else
2328 emit_data->args[0] = param[0];
2329
2330 /* Resource. */
2331 emit_data->args[1] = res_ptr;
2332 num_args = 2;
2333
2334 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2335 emit_data->dst_type = LLVMVectorType(i32, 4);
2336 else {
2337 emit_data->dst_type = LLVMVectorType(
2338 LLVMFloatTypeInContext(gallivm->context), 4);
2339
2340 emit_data->args[num_args++] = samp_ptr;
2341 }
2342
2343 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2344 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2345 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2346 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2347 tgsi_is_array_sampler(target)); /* da */
2348 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2349 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2350 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2351 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2352
2353 emit_data->arg_count = num_args;
2354 }
2355
2356 static const struct lp_build_tgsi_action tex_action;
2357
2358 static void tex_fetch_ptrs(
2359 struct lp_build_tgsi_context * bld_base,
2360 struct lp_build_emit_data * emit_data,
2361 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2362 {
2363 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2364 struct gallivm_state *gallivm = bld_base->base.gallivm;
2365 const struct tgsi_full_instruction * inst = emit_data->inst;
2366 unsigned target = inst->Texture.Texture;
2367 unsigned sampler_src;
2368 unsigned sampler_index;
2369
2370 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2371 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2372
2373 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2374 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2375 LLVMValueRef ind_index;
2376
2377 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2378
2379 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2380 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2381
2382 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2383 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2384
2385 if (target == TGSI_TEXTURE_2D_MSAA ||
2386 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2387 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2388 lp_build_const_int32(gallivm,
2389 SI_FMASK_TEX_OFFSET), "");
2390 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2391 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2392 }
2393 } else {
2394 *res_ptr = si_shader_ctx->resources[sampler_index];
2395 *samp_ptr = si_shader_ctx->samplers[sampler_index];
2396 *fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2397 }
2398 }
2399
2400 static void tex_fetch_args(
2401 struct lp_build_tgsi_context * bld_base,
2402 struct lp_build_emit_data * emit_data)
2403 {
2404 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2405 struct gallivm_state *gallivm = bld_base->base.gallivm;
2406 LLVMBuilderRef builder = gallivm->builder;
2407 const struct tgsi_full_instruction * inst = emit_data->inst;
2408 unsigned opcode = inst->Instruction.Opcode;
2409 unsigned target = inst->Texture.Texture;
2410 LLVMValueRef coords[5], derivs[6];
2411 LLVMValueRef address[16];
2412 int ref_pos;
2413 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2414 unsigned count = 0;
2415 unsigned chan;
2416 unsigned num_deriv_channels = 0;
2417 bool has_offset = inst->Texture.NumOffsets > 0;
2418 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2419 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2420 unsigned dmask = 0xf;
2421
2422 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2423
2424 if (opcode == TGSI_OPCODE_TXQ) {
2425 if (target == TGSI_TEXTURE_BUFFER) {
2426 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2427
2428 /* Read the size from the buffer descriptor directly. */
2429 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2430 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2431 lp_build_const_int32(gallivm, 6), "");
2432
2433 if (si_shader_ctx->screen->b.chip_class >= VI) {
2434 /* On VI, the descriptor contains the size in bytes,
2435 * but TXQ must return the size in elements.
2436 * The stride is always non-zero for resources using TXQ.
2437 */
2438 LLVMValueRef stride =
2439 LLVMBuildExtractElement(builder, res,
2440 lp_build_const_int32(gallivm, 5), "");
2441 stride = LLVMBuildLShr(builder, stride,
2442 lp_build_const_int32(gallivm, 16), "");
2443 stride = LLVMBuildAnd(builder, stride,
2444 lp_build_const_int32(gallivm, 0x3FFF), "");
2445
2446 size = LLVMBuildUDiv(builder, size, stride, "");
2447 }
2448
2449 emit_data->args[0] = size;
2450 return;
2451 }
2452
2453 /* Textures - set the mip level. */
2454 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2455
2456 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2457 NULL, address, count, 0xf);
2458 return;
2459 }
2460
2461 if (target == TGSI_TEXTURE_BUFFER) {
2462 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2463 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2464 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2465 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2466
2467 /* Bitcast and truncate v8i32 to v16i8. */
2468 LLVMValueRef res = res_ptr;
2469 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2470 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2471 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2472
2473 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2474 emit_data->args[0] = res;
2475 emit_data->args[1] = bld_base->uint_bld.zero;
2476 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2477 emit_data->arg_count = 3;
2478 return;
2479 }
2480
2481 /* Fetch and project texture coordinates */
2482 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2483 for (chan = 0; chan < 3; chan++ ) {
2484 coords[chan] = lp_build_emit_fetch(bld_base,
2485 emit_data->inst, 0,
2486 chan);
2487 if (opcode == TGSI_OPCODE_TXP)
2488 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2489 TGSI_OPCODE_DIV,
2490 coords[chan],
2491 coords[3]);
2492 }
2493
2494 if (opcode == TGSI_OPCODE_TXP)
2495 coords[3] = bld_base->base.one;
2496
2497 /* Pack offsets. */
2498 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2499 /* The offsets are six-bit signed integers packed like this:
2500 * X=[5:0], Y=[13:8], and Z=[21:16].
2501 */
2502 LLVMValueRef offset[3], pack;
2503
2504 assert(inst->Texture.NumOffsets == 1);
2505
2506 for (chan = 0; chan < 3; chan++) {
2507 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2508 emit_data->inst, 0, chan);
2509 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2510 lp_build_const_int32(gallivm, 0x3f), "");
2511 if (chan)
2512 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2513 lp_build_const_int32(gallivm, chan*8), "");
2514 }
2515
2516 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2517 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2518 address[count++] = pack;
2519 }
2520
2521 /* Pack LOD bias value */
2522 if (opcode == TGSI_OPCODE_TXB)
2523 address[count++] = coords[3];
2524 if (opcode == TGSI_OPCODE_TXB2)
2525 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2526
2527 /* Pack depth comparison value */
2528 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2529 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2530 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2531 } else {
2532 assert(ref_pos >= 0);
2533 address[count++] = coords[ref_pos];
2534 }
2535 }
2536
2537 /* Pack user derivatives */
2538 if (opcode == TGSI_OPCODE_TXD) {
2539 int param, num_src_deriv_channels;
2540
2541 switch (target) {
2542 case TGSI_TEXTURE_3D:
2543 num_src_deriv_channels = 3;
2544 num_deriv_channels = 3;
2545 break;
2546 case TGSI_TEXTURE_2D:
2547 case TGSI_TEXTURE_SHADOW2D:
2548 case TGSI_TEXTURE_RECT:
2549 case TGSI_TEXTURE_SHADOWRECT:
2550 case TGSI_TEXTURE_2D_ARRAY:
2551 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2552 num_src_deriv_channels = 2;
2553 num_deriv_channels = 2;
2554 break;
2555 case TGSI_TEXTURE_CUBE:
2556 case TGSI_TEXTURE_SHADOWCUBE:
2557 case TGSI_TEXTURE_CUBE_ARRAY:
2558 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2559 /* Cube derivatives will be converted to 2D. */
2560 num_src_deriv_channels = 3;
2561 num_deriv_channels = 2;
2562 break;
2563 case TGSI_TEXTURE_1D:
2564 case TGSI_TEXTURE_SHADOW1D:
2565 case TGSI_TEXTURE_1D_ARRAY:
2566 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2567 num_src_deriv_channels = 1;
2568 num_deriv_channels = 1;
2569 break;
2570 default:
2571 unreachable("invalid target");
2572 }
2573
2574 for (param = 0; param < 2; param++)
2575 for (chan = 0; chan < num_src_deriv_channels; chan++)
2576 derivs[param * num_src_deriv_channels + chan] =
2577 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2578 }
2579
2580 if (target == TGSI_TEXTURE_CUBE ||
2581 target == TGSI_TEXTURE_CUBE_ARRAY ||
2582 target == TGSI_TEXTURE_SHADOWCUBE ||
2583 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2584 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2585
2586 if (opcode == TGSI_OPCODE_TXD)
2587 for (int i = 0; i < num_deriv_channels * 2; i++)
2588 address[count++] = derivs[i];
2589
2590 /* Pack texture coordinates */
2591 address[count++] = coords[0];
2592 if (num_coords > 1)
2593 address[count++] = coords[1];
2594 if (num_coords > 2)
2595 address[count++] = coords[2];
2596
2597 /* Pack LOD or sample index */
2598 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2599 address[count++] = coords[3];
2600 else if (opcode == TGSI_OPCODE_TXL2)
2601 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2602
2603 if (count > 16) {
2604 assert(!"Cannot handle more than 16 texture address parameters");
2605 count = 16;
2606 }
2607
2608 for (chan = 0; chan < count; chan++ ) {
2609 address[chan] = LLVMBuildBitCast(gallivm->builder,
2610 address[chan], i32, "");
2611 }
2612
2613 /* Adjust the sample index according to FMASK.
2614 *
2615 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2616 * which is the identity mapping. Each nibble says which physical sample
2617 * should be fetched to get that sample.
2618 *
2619 * For example, 0x11111100 means there are only 2 samples stored and
2620 * the second sample covers 3/4 of the pixel. When reading samples 0
2621 * and 1, return physical sample 0 (determined by the first two 0s
2622 * in FMASK), otherwise return physical sample 1.
2623 *
2624 * The sample index should be adjusted as follows:
2625 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2626 */
2627 if (target == TGSI_TEXTURE_2D_MSAA ||
2628 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2629 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2630 struct lp_build_emit_data txf_emit_data = *emit_data;
2631 LLVMValueRef txf_address[4];
2632 unsigned txf_count = count;
2633 struct tgsi_full_instruction inst = {};
2634
2635 memcpy(txf_address, address, sizeof(txf_address));
2636
2637 if (target == TGSI_TEXTURE_2D_MSAA) {
2638 txf_address[2] = bld_base->uint_bld.zero;
2639 }
2640 txf_address[3] = bld_base->uint_bld.zero;
2641
2642 /* Read FMASK using TXF. */
2643 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2644 inst.Texture.Texture = target;
2645 txf_emit_data.inst = &inst;
2646 txf_emit_data.chan = 0;
2647 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2648 target, fmask_ptr, NULL,
2649 txf_address, txf_count, 0xf);
2650 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2651
2652 /* Initialize some constants. */
2653 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2654 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2655
2656 /* Apply the formula. */
2657 LLVMValueRef fmask =
2658 LLVMBuildExtractElement(gallivm->builder,
2659 txf_emit_data.output[0],
2660 uint_bld->zero, "");
2661
2662 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2663
2664 LLVMValueRef sample_index4 =
2665 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2666
2667 LLVMValueRef shifted_fmask =
2668 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2669
2670 LLVMValueRef final_sample =
2671 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2672
2673 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2674 * resource descriptor is 0 (invalid),
2675 */
2676 LLVMValueRef fmask_desc =
2677 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2678 LLVMVectorType(uint_bld->elem_type, 8), "");
2679
2680 LLVMValueRef fmask_word1 =
2681 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2682 uint_bld->one, "");
2683
2684 LLVMValueRef word1_is_nonzero =
2685 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2686 fmask_word1, uint_bld->zero, "");
2687
2688 /* Replace the MSAA sample index. */
2689 address[sample_chan] =
2690 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2691 final_sample, address[sample_chan], "");
2692 }
2693
2694 if (opcode == TGSI_OPCODE_TXF) {
2695 /* add tex offsets */
2696 if (inst->Texture.NumOffsets) {
2697 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2698 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2699 const struct tgsi_texture_offset * off = inst->TexOffsets;
2700
2701 assert(inst->Texture.NumOffsets == 1);
2702
2703 switch (target) {
2704 case TGSI_TEXTURE_3D:
2705 address[2] = lp_build_add(uint_bld, address[2],
2706 bld->immediates[off->Index][off->SwizzleZ]);
2707 /* fall through */
2708 case TGSI_TEXTURE_2D:
2709 case TGSI_TEXTURE_SHADOW2D:
2710 case TGSI_TEXTURE_RECT:
2711 case TGSI_TEXTURE_SHADOWRECT:
2712 case TGSI_TEXTURE_2D_ARRAY:
2713 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2714 address[1] =
2715 lp_build_add(uint_bld, address[1],
2716 bld->immediates[off->Index][off->SwizzleY]);
2717 /* fall through */
2718 case TGSI_TEXTURE_1D:
2719 case TGSI_TEXTURE_SHADOW1D:
2720 case TGSI_TEXTURE_1D_ARRAY:
2721 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2722 address[0] =
2723 lp_build_add(uint_bld, address[0],
2724 bld->immediates[off->Index][off->SwizzleX]);
2725 break;
2726 /* texture offsets do not apply to other texture targets */
2727 }
2728 }
2729 }
2730
2731 if (opcode == TGSI_OPCODE_TG4) {
2732 unsigned gather_comp = 0;
2733
2734 /* DMASK was repurposed for GATHER4. 4 components are always
2735 * returned and DMASK works like a swizzle - it selects
2736 * the component to fetch. The only valid DMASK values are
2737 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2738 * (red,red,red,red) etc.) The ISA document doesn't mention
2739 * this.
2740 */
2741
2742 /* Get the component index from src1.x for Gather4. */
2743 if (!tgsi_is_shadow_target(target)) {
2744 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2745 LLVMValueRef comp_imm;
2746 struct tgsi_src_register src1 = inst->Src[1].Register;
2747
2748 assert(src1.File == TGSI_FILE_IMMEDIATE);
2749
2750 comp_imm = imms[src1.Index][src1.SwizzleX];
2751 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2752 gather_comp = CLAMP(gather_comp, 0, 3);
2753 }
2754
2755 dmask = 1 << gather_comp;
2756 }
2757
2758 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2759 samp_ptr, address, count, dmask);
2760 }
2761
2762 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2763 struct lp_build_tgsi_context * bld_base,
2764 struct lp_build_emit_data * emit_data)
2765 {
2766 struct lp_build_context * base = &bld_base->base;
2767 unsigned opcode = emit_data->inst->Instruction.Opcode;
2768 unsigned target = emit_data->inst->Texture.Texture;
2769 char intr_name[127];
2770 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2771 bool is_shadow = tgsi_is_shadow_target(target);
2772 char type[64];
2773 const char *name = "llvm.SI.image.sample";
2774 const char *infix = "";
2775
2776 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2777 /* Just return the buffer size. */
2778 emit_data->output[emit_data->chan] = emit_data->args[0];
2779 return;
2780 }
2781
2782 if (target == TGSI_TEXTURE_BUFFER) {
2783 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2784 base->gallivm->builder,
2785 "llvm.SI.vs.load.input", emit_data->dst_type,
2786 emit_data->args, emit_data->arg_count,
2787 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2788 return;
2789 }
2790
2791 switch (opcode) {
2792 case TGSI_OPCODE_TXF:
2793 name = target == TGSI_TEXTURE_2D_MSAA ||
2794 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2795 "llvm.SI.image.load" :
2796 "llvm.SI.image.load.mip";
2797 is_shadow = false;
2798 has_offset = false;
2799 break;
2800 case TGSI_OPCODE_TXQ:
2801 name = "llvm.SI.getresinfo";
2802 is_shadow = false;
2803 has_offset = false;
2804 break;
2805 case TGSI_OPCODE_LODQ:
2806 name = "llvm.SI.getlod";
2807 is_shadow = false;
2808 has_offset = false;
2809 break;
2810 case TGSI_OPCODE_TEX:
2811 case TGSI_OPCODE_TEX2:
2812 case TGSI_OPCODE_TXP:
2813 break;
2814 case TGSI_OPCODE_TXB:
2815 case TGSI_OPCODE_TXB2:
2816 infix = ".b";
2817 break;
2818 case TGSI_OPCODE_TXL:
2819 case TGSI_OPCODE_TXL2:
2820 infix = ".l";
2821 break;
2822 case TGSI_OPCODE_TXD:
2823 infix = ".d";
2824 break;
2825 case TGSI_OPCODE_TG4:
2826 name = "llvm.SI.gather4";
2827 break;
2828 default:
2829 assert(0);
2830 return;
2831 }
2832
2833 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2834 sprintf(type, ".v%ui32",
2835 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2836 else
2837 strcpy(type, ".i32");
2838
2839 /* Add the type and suffixes .c, .o if needed. */
2840 sprintf(intr_name, "%s%s%s%s%s",
2841 name, is_shadow ? ".c" : "", infix,
2842 has_offset ? ".o" : "", type);
2843
2844 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2845 base->gallivm->builder, intr_name, emit_data->dst_type,
2846 emit_data->args, emit_data->arg_count,
2847 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2848
2849 /* Divide the number of layers by 6 to get the number of cubes. */
2850 if (opcode == TGSI_OPCODE_TXQ &&
2851 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2852 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2853 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2854 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2855 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2856
2857 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2858 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2859 z = LLVMBuildSDiv(builder, z, six, "");
2860
2861 emit_data->output[emit_data->chan] =
2862 LLVMBuildInsertElement(builder, v4, z, two, "");
2863 }
2864 }
2865
2866 static void si_llvm_emit_txqs(
2867 const struct lp_build_tgsi_action * action,
2868 struct lp_build_tgsi_context * bld_base,
2869 struct lp_build_emit_data * emit_data)
2870 {
2871 struct gallivm_state *gallivm = bld_base->base.gallivm;
2872 LLVMBuilderRef builder = gallivm->builder;
2873 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2874 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2875 LLVMValueRef res, samples;
2876 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2877
2878 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2879
2880
2881 /* Read the samples from the descriptor directly. */
2882 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2883 samples = LLVMBuildExtractElement(
2884 builder, res,
2885 lp_build_const_int32(gallivm, 3), "");
2886 samples = LLVMBuildLShr(builder, samples,
2887 lp_build_const_int32(gallivm, 16), "");
2888 samples = LLVMBuildAnd(builder, samples,
2889 lp_build_const_int32(gallivm, 0xf), "");
2890 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2891 samples, "");
2892
2893 emit_data->output[emit_data->chan] = samples;
2894 }
2895
2896 /*
2897 * SI implements derivatives using the local data store (LDS)
2898 * All writes to the LDS happen in all executing threads at
2899 * the same time. TID is the Thread ID for the current
2900 * thread and is a value between 0 and 63, representing
2901 * the thread's position in the wavefront.
2902 *
2903 * For the pixel shader threads are grouped into quads of four pixels.
2904 * The TIDs of the pixels of a quad are:
2905 *
2906 * +------+------+
2907 * |4n + 0|4n + 1|
2908 * +------+------+
2909 * |4n + 2|4n + 3|
2910 * +------+------+
2911 *
2912 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2913 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2914 * the current pixel's column, and masking with 0xfffffffe yields the TID
2915 * of the left pixel of the current pixel's row.
2916 *
2917 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2918 * adding 2 yields the TID of the pixel below the top pixel.
2919 */
2920 /* masks for thread ID. */
2921 #define TID_MASK_TOP_LEFT 0xfffffffc
2922 #define TID_MASK_TOP 0xfffffffd
2923 #define TID_MASK_LEFT 0xfffffffe
2924
2925 static void si_llvm_emit_ddxy(
2926 const struct lp_build_tgsi_action * action,
2927 struct lp_build_tgsi_context * bld_base,
2928 struct lp_build_emit_data * emit_data)
2929 {
2930 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2931 struct gallivm_state *gallivm = bld_base->base.gallivm;
2932 struct lp_build_context * base = &bld_base->base;
2933 const struct tgsi_full_instruction *inst = emit_data->inst;
2934 unsigned opcode = inst->Instruction.Opcode;
2935 LLVMValueRef indices[2];
2936 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2937 LLVMValueRef tl, trbl, result[4];
2938 LLVMTypeRef i32;
2939 unsigned swizzle[4];
2940 unsigned c;
2941 int idx;
2942 unsigned mask;
2943
2944 i32 = LLVMInt32TypeInContext(gallivm->context);
2945
2946 indices[0] = bld_base->uint_bld.zero;
2947 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2948 NULL, 0, LLVMReadNoneAttribute);
2949 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2950 indices, 2, "");
2951
2952 if (opcode == TGSI_OPCODE_DDX_FINE)
2953 mask = TID_MASK_LEFT;
2954 else if (opcode == TGSI_OPCODE_DDY_FINE)
2955 mask = TID_MASK_TOP;
2956 else
2957 mask = TID_MASK_TOP_LEFT;
2958
2959 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2960 lp_build_const_int32(gallivm, mask), "");
2961 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2962 indices, 2, "");
2963
2964 /* for DDX we want to next X pixel, DDY next Y pixel. */
2965 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2966 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2967 lp_build_const_int32(gallivm, idx), "");
2968 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2969 indices, 2, "");
2970
2971 for (c = 0; c < 4; ++c) {
2972 unsigned i;
2973
2974 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2975 for (i = 0; i < c; ++i) {
2976 if (swizzle[i] == swizzle[c]) {
2977 result[c] = result[i];
2978 break;
2979 }
2980 }
2981 if (i != c)
2982 continue;
2983
2984 LLVMBuildStore(gallivm->builder,
2985 LLVMBuildBitCast(gallivm->builder,
2986 lp_build_emit_fetch(bld_base, inst, 0, c),
2987 i32, ""),
2988 store_ptr);
2989
2990 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2991 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2992
2993 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2994 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2995
2996 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2997 }
2998
2999 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3000 }
3001
3002 /*
3003 * this takes an I,J coordinate pair,
3004 * and works out the X and Y derivatives.
3005 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3006 */
3007 static LLVMValueRef si_llvm_emit_ddxy_interp(
3008 struct lp_build_tgsi_context *bld_base,
3009 LLVMValueRef interp_ij)
3010 {
3011 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3012 struct gallivm_state *gallivm = bld_base->base.gallivm;
3013 struct lp_build_context *base = &bld_base->base;
3014 LLVMValueRef indices[2];
3015 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3016 LLVMValueRef tl, tr, bl, result[4];
3017 LLVMTypeRef i32;
3018 unsigned c;
3019
3020 i32 = LLVMInt32TypeInContext(gallivm->context);
3021
3022 indices[0] = bld_base->uint_bld.zero;
3023 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3024 NULL, 0, LLVMReadNoneAttribute);
3025 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3026 indices, 2, "");
3027
3028 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3029 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3030
3031 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3032 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3033
3034 indices[1] = temp;
3035 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3036 indices, 2, "");
3037
3038 indices[1] = temp2;
3039 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3040 indices, 2, "");
3041
3042 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3043 lp_build_const_int32(gallivm, 1), "");
3044 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3045 indices, 2, "");
3046
3047 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3048 lp_build_const_int32(gallivm, 2), "");
3049 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3050 indices, 2, "");
3051
3052 for (c = 0; c < 2; ++c) {
3053 LLVMValueRef store_val;
3054 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3055
3056 store_val = LLVMBuildExtractElement(gallivm->builder,
3057 interp_ij, c_ll, "");
3058 LLVMBuildStore(gallivm->builder,
3059 store_val,
3060 store_ptr);
3061
3062 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3063 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3064
3065 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3066 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3067
3068 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3069
3070 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3071 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3072
3073 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3074 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3075
3076 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3077 }
3078
3079 return lp_build_gather_values(gallivm, result, 4);
3080 }
3081
3082 static void interp_fetch_args(
3083 struct lp_build_tgsi_context *bld_base,
3084 struct lp_build_emit_data *emit_data)
3085 {
3086 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3087 struct gallivm_state *gallivm = bld_base->base.gallivm;
3088 const struct tgsi_full_instruction *inst = emit_data->inst;
3089
3090 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3091 /* offset is in second src, first two channels */
3092 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3093 emit_data->inst, 1,
3094 0);
3095 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3096 emit_data->inst, 1,
3097 1);
3098 emit_data->arg_count = 2;
3099 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3100 LLVMValueRef sample_position;
3101 LLVMValueRef sample_id;
3102 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3103
3104 /* fetch sample ID, then fetch its sample position,
3105 * and place into first two channels.
3106 */
3107 sample_id = lp_build_emit_fetch(bld_base,
3108 emit_data->inst, 1, 0);
3109 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3110 LLVMInt32TypeInContext(gallivm->context),
3111 "");
3112 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3113
3114 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3115 sample_position,
3116 lp_build_const_int32(gallivm, 0), "");
3117
3118 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3119 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3120 sample_position,
3121 lp_build_const_int32(gallivm, 1), "");
3122 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3123 emit_data->arg_count = 2;
3124 }
3125 }
3126
3127 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3128 struct lp_build_tgsi_context *bld_base,
3129 struct lp_build_emit_data *emit_data)
3130 {
3131 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3132 struct si_shader *shader = si_shader_ctx->shader;
3133 struct gallivm_state *gallivm = bld_base->base.gallivm;
3134 LLVMValueRef interp_param;
3135 const struct tgsi_full_instruction *inst = emit_data->inst;
3136 const char *intr_name;
3137 int input_index;
3138 int chan;
3139 int i;
3140 LLVMValueRef attr_number;
3141 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3142 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3143 int interp_param_idx;
3144 unsigned location;
3145
3146 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3147 input_index = inst->Src[0].Register.Index;
3148
3149 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3150 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3151 location = TGSI_INTERPOLATE_LOC_CENTER;
3152 else
3153 location = TGSI_INTERPOLATE_LOC_CENTROID;
3154
3155 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3156 location);
3157 if (interp_param_idx == -1)
3158 return;
3159 else if (interp_param_idx)
3160 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3161 else
3162 interp_param = NULL;
3163
3164 attr_number = lp_build_const_int32(gallivm,
3165 shader->ps_input_param_offset[input_index]);
3166
3167 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3168 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3169 LLVMValueRef ij_out[2];
3170 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3171
3172 /*
3173 * take the I then J parameters, and the DDX/Y for it, and
3174 * calculate the IJ inputs for the interpolator.
3175 * temp1 = ddx * offset/sample.x + I;
3176 * interp_param.I = ddy * offset/sample.y + temp1;
3177 * temp1 = ddx * offset/sample.x + J;
3178 * interp_param.J = ddy * offset/sample.y + temp1;
3179 */
3180 for (i = 0; i < 2; i++) {
3181 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3182 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3183 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3184 ddxy_out, ix_ll, "");
3185 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3186 ddxy_out, iy_ll, "");
3187 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3188 interp_param, ix_ll, "");
3189 LLVMValueRef temp1, temp2;
3190
3191 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3192 LLVMFloatTypeInContext(gallivm->context), "");
3193
3194 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3195
3196 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3197
3198 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3199
3200 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3201
3202 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3203 temp2,
3204 LLVMIntTypeInContext(gallivm->context, 32), "");
3205 }
3206 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3207 }
3208
3209 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3210 for (chan = 0; chan < 2; chan++) {
3211 LLVMValueRef args[4];
3212 LLVMValueRef llvm_chan;
3213 unsigned schan;
3214
3215 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3216 llvm_chan = lp_build_const_int32(gallivm, schan);
3217
3218 args[0] = llvm_chan;
3219 args[1] = attr_number;
3220 args[2] = params;
3221 args[3] = interp_param;
3222
3223 emit_data->output[chan] =
3224 lp_build_intrinsic(gallivm->builder, intr_name,
3225 input_type, args, args[3] ? 4 : 3,
3226 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3227 }
3228 }
3229
3230 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3231 struct lp_build_emit_data *emit_data)
3232 {
3233 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3234 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3235 unsigned stream;
3236
3237 assert(src0.File == TGSI_FILE_IMMEDIATE);
3238
3239 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3240 return stream;
3241 }
3242
3243 /* Emit one vertex from the geometry shader */
3244 static void si_llvm_emit_vertex(
3245 const struct lp_build_tgsi_action *action,
3246 struct lp_build_tgsi_context *bld_base,
3247 struct lp_build_emit_data *emit_data)
3248 {
3249 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3250 struct lp_build_context *uint = &bld_base->uint_bld;
3251 struct si_shader *shader = si_shader_ctx->shader;
3252 struct tgsi_shader_info *info = &shader->selector->info;
3253 struct gallivm_state *gallivm = bld_base->base.gallivm;
3254 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3255 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3256 SI_PARAM_GS2VS_OFFSET);
3257 LLVMValueRef gs_next_vertex;
3258 LLVMValueRef can_emit, kill;
3259 LLVMValueRef args[2];
3260 unsigned chan;
3261 int i;
3262 unsigned stream;
3263
3264 stream = si_llvm_get_stream(bld_base, emit_data);
3265
3266 /* Write vertex attribute values to GSVS ring */
3267 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3268 si_shader_ctx->gs_next_vertex[stream],
3269 "");
3270
3271 /* If this thread has already emitted the declared maximum number of
3272 * vertices, kill it: excessive vertex emissions are not supposed to
3273 * have any effect, and GS threads have no externally observable
3274 * effects other than emitting vertices.
3275 */
3276 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3277 lp_build_const_int32(gallivm,
3278 shader->selector->gs_max_out_vertices), "");
3279 kill = lp_build_select(&bld_base->base, can_emit,
3280 lp_build_const_float(gallivm, 1.0f),
3281 lp_build_const_float(gallivm, -1.0f));
3282
3283 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3284 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3285
3286 for (i = 0; i < info->num_outputs; i++) {
3287 LLVMValueRef *out_ptr =
3288 si_shader_ctx->radeon_bld.soa.outputs[i];
3289
3290 for (chan = 0; chan < 4; chan++) {
3291 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3292 LLVMValueRef voffset =
3293 lp_build_const_int32(gallivm, (i * 4 + chan) *
3294 shader->selector->gs_max_out_vertices);
3295
3296 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3297 voffset = lp_build_mul_imm(uint, voffset, 4);
3298
3299 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3300
3301 build_tbuffer_store(si_shader_ctx,
3302 si_shader_ctx->gsvs_ring[stream],
3303 out_val, 1,
3304 voffset, soffset, 0,
3305 V_008F0C_BUF_DATA_FORMAT_32,
3306 V_008F0C_BUF_NUM_FORMAT_UINT,
3307 1, 0, 1, 1, 0);
3308 }
3309 }
3310 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3311 lp_build_const_int32(gallivm, 1));
3312
3313 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3314
3315 /* Signal vertex emission */
3316 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3317 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3318 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3319 LLVMVoidTypeInContext(gallivm->context), args, 2,
3320 LLVMNoUnwindAttribute);
3321 }
3322
3323 /* Cut one primitive from the geometry shader */
3324 static void si_llvm_emit_primitive(
3325 const struct lp_build_tgsi_action *action,
3326 struct lp_build_tgsi_context *bld_base,
3327 struct lp_build_emit_data *emit_data)
3328 {
3329 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3330 struct gallivm_state *gallivm = bld_base->base.gallivm;
3331 LLVMValueRef args[2];
3332 unsigned stream;
3333
3334 /* Signal primitive cut */
3335 stream = si_llvm_get_stream(bld_base, emit_data);
3336 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3337 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3338 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3339 LLVMVoidTypeInContext(gallivm->context), args, 2,
3340 LLVMNoUnwindAttribute);
3341 }
3342
3343 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3344 struct lp_build_tgsi_context *bld_base,
3345 struct lp_build_emit_data *emit_data)
3346 {
3347 struct gallivm_state *gallivm = bld_base->base.gallivm;
3348
3349 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3350 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3351 LLVMNoUnwindAttribute);
3352 }
3353
3354 static const struct lp_build_tgsi_action tex_action = {
3355 .fetch_args = tex_fetch_args,
3356 .emit = build_tex_intrinsic,
3357 };
3358
3359 static const struct lp_build_tgsi_action interp_action = {
3360 .fetch_args = interp_fetch_args,
3361 .emit = build_interp_intrinsic,
3362 };
3363
3364 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3365 {
3366 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3367 LLVMValueRef args[3];
3368
3369 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3370 args[1] = 0;
3371 args[2] = lp_build_const_int32(gallivm, 1);
3372
3373 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3374 }
3375
3376 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3377 {
3378 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3379 CONST_ADDR_SPACE);
3380 }
3381
3382 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3383 struct pipe_stream_output_info *so,
3384 LLVMTypeRef *params, LLVMTypeRef i32,
3385 unsigned *num_params)
3386 {
3387 int i;
3388
3389 /* Streamout SGPRs. */
3390 if (so->num_outputs) {
3391 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3392 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3393 }
3394 /* A streamout buffer offset is loaded if the stride is non-zero. */
3395 for (i = 0; i < 4; i++) {
3396 if (!so->stride[i])
3397 continue;
3398
3399 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3400 }
3401 }
3402
3403 static void create_function(struct si_shader_context *si_shader_ctx)
3404 {
3405 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3406 struct gallivm_state *gallivm = bld_base->base.gallivm;
3407 struct si_shader *shader = si_shader_ctx->shader;
3408 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3409 unsigned i, last_array_pointer, last_sgpr, num_params;
3410
3411 i8 = LLVMInt8TypeInContext(gallivm->context);
3412 i32 = LLVMInt32TypeInContext(gallivm->context);
3413 f32 = LLVMFloatTypeInContext(gallivm->context);
3414 v2i32 = LLVMVectorType(i32, 2);
3415 v3i32 = LLVMVectorType(i32, 3);
3416 v4i32 = LLVMVectorType(i32, 4);
3417 v8i32 = LLVMVectorType(i32, 8);
3418 v16i8 = LLVMVectorType(i8, 16);
3419
3420 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3421 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3422 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3423 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3424 last_array_pointer = SI_PARAM_RESOURCE;
3425
3426 switch (si_shader_ctx->type) {
3427 case TGSI_PROCESSOR_VERTEX:
3428 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3429 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3430 params[SI_PARAM_BASE_VERTEX] = i32;
3431 params[SI_PARAM_START_INSTANCE] = i32;
3432 num_params = SI_PARAM_START_INSTANCE+1;
3433
3434 if (shader->key.vs.as_es) {
3435 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3436 } else if (shader->key.vs.as_ls) {
3437 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3438 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3439 } else {
3440 if (shader->is_gs_copy_shader) {
3441 last_array_pointer = SI_PARAM_CONST;
3442 num_params = SI_PARAM_CONST+1;
3443 }
3444
3445 /* The locations of the other parameters are assigned dynamically. */
3446 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3447 params, i32, &num_params);
3448 }
3449
3450 last_sgpr = num_params-1;
3451
3452 /* VGPRs */
3453 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3454 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3455 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3456 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3457 break;
3458
3459 case TGSI_PROCESSOR_TESS_CTRL:
3460 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3461 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3462 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3463 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3464 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3465
3466 /* VGPRs */
3467 params[SI_PARAM_PATCH_ID] = i32;
3468 params[SI_PARAM_REL_IDS] = i32;
3469 num_params = SI_PARAM_REL_IDS+1;
3470 break;
3471
3472 case TGSI_PROCESSOR_TESS_EVAL:
3473 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3474 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3475 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3476
3477 if (shader->key.tes.as_es) {
3478 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3479 } else {
3480 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3481 params, i32, &num_params);
3482 }
3483 last_sgpr = num_params - 1;
3484
3485 /* VGPRs */
3486 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3487 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3488 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3489 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3490 break;
3491
3492 case TGSI_PROCESSOR_GEOMETRY:
3493 params[SI_PARAM_GS2VS_OFFSET] = i32;
3494 params[SI_PARAM_GS_WAVE_ID] = i32;
3495 last_sgpr = SI_PARAM_GS_WAVE_ID;
3496
3497 /* VGPRs */
3498 params[SI_PARAM_VTX0_OFFSET] = i32;
3499 params[SI_PARAM_VTX1_OFFSET] = i32;
3500 params[SI_PARAM_PRIMITIVE_ID] = i32;
3501 params[SI_PARAM_VTX2_OFFSET] = i32;
3502 params[SI_PARAM_VTX3_OFFSET] = i32;
3503 params[SI_PARAM_VTX4_OFFSET] = i32;
3504 params[SI_PARAM_VTX5_OFFSET] = i32;
3505 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3506 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3507 break;
3508
3509 case TGSI_PROCESSOR_FRAGMENT:
3510 params[SI_PARAM_ALPHA_REF] = f32;
3511 params[SI_PARAM_PS_STATE_BITS] = i32;
3512 params[SI_PARAM_PRIM_MASK] = i32;
3513 last_sgpr = SI_PARAM_PRIM_MASK;
3514 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3515 params[SI_PARAM_PERSP_CENTER] = v2i32;
3516 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3517 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3518 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3519 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3520 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3521 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3522 params[SI_PARAM_POS_X_FLOAT] = f32;
3523 params[SI_PARAM_POS_Y_FLOAT] = f32;
3524 params[SI_PARAM_POS_Z_FLOAT] = f32;
3525 params[SI_PARAM_POS_W_FLOAT] = f32;
3526 params[SI_PARAM_FRONT_FACE] = f32;
3527 params[SI_PARAM_ANCILLARY] = i32;
3528 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3529 params[SI_PARAM_POS_FIXED_PT] = f32;
3530 num_params = SI_PARAM_POS_FIXED_PT+1;
3531 break;
3532
3533 default:
3534 assert(0 && "unimplemented shader");
3535 return;
3536 }
3537
3538 assert(num_params <= Elements(params));
3539 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3540 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3541
3542 if (shader->dx10_clamp_mode)
3543 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3544 "enable-no-nans-fp-math", "true");
3545
3546 for (i = 0; i <= last_sgpr; ++i) {
3547 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3548
3549 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3550 * to move load. Inputs are constant so this is fine. */
3551 if (i <= last_array_pointer)
3552 LLVMAddAttribute(P, LLVMByValAttribute);
3553 else
3554 LLVMAddAttribute(P, LLVMInRegAttribute);
3555 }
3556
3557 if (bld_base->info &&
3558 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3559 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3560 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3561 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3562 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3563 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3564 si_shader_ctx->lds =
3565 LLVMAddGlobalInAddressSpace(gallivm->module,
3566 LLVMArrayType(i32, 64),
3567 "ddxy_lds",
3568 LOCAL_ADDR_SPACE);
3569
3570 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3571 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3572 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3573 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3574 unsigned vertex_data_dw_size = 32*32*4;
3575 unsigned patch_data_dw_size = 32*4;
3576 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3577 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3578 unsigned lds_dwords = patch_dw_size;
3579
3580 /* The actual size is computed outside of the shader to reduce
3581 * the number of shader variants. */
3582 si_shader_ctx->lds =
3583 LLVMAddGlobalInAddressSpace(gallivm->module,
3584 LLVMArrayType(i32, lds_dwords),
3585 "tess_lds",
3586 LOCAL_ADDR_SPACE);
3587 }
3588 }
3589
3590 static void preload_constants(struct si_shader_context *si_shader_ctx)
3591 {
3592 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3593 struct gallivm_state * gallivm = bld_base->base.gallivm;
3594 const struct tgsi_shader_info * info = bld_base->info;
3595 unsigned buf;
3596 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3597
3598 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3599 unsigned i, num_const = info->const_file_max[buf] + 1;
3600
3601 if (num_const == 0)
3602 continue;
3603
3604 /* Allocate space for the constant values */
3605 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3606
3607 /* Load the resource descriptor */
3608 si_shader_ctx->const_resource[buf] =
3609 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3610
3611 /* Load the constants, we rely on the code sinking to do the rest */
3612 for (i = 0; i < num_const * 4; ++i) {
3613 si_shader_ctx->constants[buf][i] =
3614 buffer_load_const(gallivm->builder,
3615 si_shader_ctx->const_resource[buf],
3616 lp_build_const_int32(gallivm, i * 4),
3617 bld_base->base.elem_type);
3618 }
3619 }
3620 }
3621
3622 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3623 {
3624 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3625 struct gallivm_state * gallivm = bld_base->base.gallivm;
3626 const struct tgsi_shader_info * info = bld_base->info;
3627
3628 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3629
3630 LLVMValueRef res_ptr, samp_ptr;
3631 LLVMValueRef offset;
3632
3633 if (num_samplers == 0)
3634 return;
3635
3636 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3637 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3638
3639 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3640 for (i = 0; i < num_samplers; ++i) {
3641 /* Resource */
3642 offset = lp_build_const_int32(gallivm, i);
3643 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3644
3645 /* Sampler */
3646 offset = lp_build_const_int32(gallivm, i);
3647 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3648
3649 /* FMASK resource */
3650 if (info->is_msaa_sampler[i]) {
3651 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3652 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3653 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3654 }
3655 }
3656 }
3657
3658 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3659 {
3660 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3661 struct gallivm_state * gallivm = bld_base->base.gallivm;
3662 unsigned i;
3663
3664 /* Streamout can only be used if the shader is compiled as VS. */
3665 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3666 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3667 (si_shader_ctx->shader->key.vs.as_es ||
3668 si_shader_ctx->shader->key.vs.as_ls)) ||
3669 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3670 si_shader_ctx->shader->key.tes.as_es))
3671 return;
3672
3673 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3674 SI_PARAM_RW_BUFFERS);
3675
3676 /* Load the resources, we rely on the code sinking to do the rest */
3677 for (i = 0; i < 4; ++i) {
3678 if (si_shader_ctx->shader->selector->so.stride[i]) {
3679 LLVMValueRef offset = lp_build_const_int32(gallivm,
3680 SI_SO_BUF_OFFSET + i);
3681
3682 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3683 }
3684 }
3685 }
3686
3687 /**
3688 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3689 * for later use.
3690 */
3691 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3692 {
3693 struct gallivm_state *gallivm =
3694 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3695
3696 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3697 SI_PARAM_RW_BUFFERS);
3698
3699 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3700 si_shader_ctx->shader->key.vs.as_es) ||
3701 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3702 si_shader_ctx->shader->key.tes.as_es) ||
3703 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3704 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3705
3706 si_shader_ctx->esgs_ring =
3707 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3708 }
3709
3710 if (si_shader_ctx->shader->is_gs_copy_shader) {
3711 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3712
3713 si_shader_ctx->gsvs_ring[0] =
3714 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3715 }
3716 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3717 int i;
3718 for (i = 0; i < 4; i++) {
3719 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3720
3721 si_shader_ctx->gsvs_ring[i] =
3722 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3723 }
3724 }
3725 }
3726
3727 void si_shader_binary_read_config(const struct si_screen *sscreen,
3728 struct si_shader *shader,
3729 unsigned symbol_offset)
3730 {
3731 unsigned i;
3732 const unsigned char *config =
3733 radeon_shader_binary_config_start(&shader->binary,
3734 symbol_offset);
3735
3736 /* XXX: We may be able to emit some of these values directly rather than
3737 * extracting fields to be emitted later.
3738 */
3739
3740 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3741 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3742 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3743 switch (reg) {
3744 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3745 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3746 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3747 case R_00B848_COMPUTE_PGM_RSRC1:
3748 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3749 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3750 shader->float_mode = G_00B028_FLOAT_MODE(value);
3751 break;
3752 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3753 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3754 break;
3755 case R_00B84C_COMPUTE_PGM_RSRC2:
3756 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3757 break;
3758 case R_0286CC_SPI_PS_INPUT_ENA:
3759 shader->spi_ps_input_ena = value;
3760 break;
3761 case R_0286E8_SPI_TMPRING_SIZE:
3762 case R_00B860_COMPUTE_TMPRING_SIZE:
3763 /* WAVESIZE is in units of 256 dwords. */
3764 shader->scratch_bytes_per_wave =
3765 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3766 break;
3767 default:
3768 fprintf(stderr, "Warning: Compiler emitted unknown "
3769 "config register: 0x%x\n", reg);
3770 break;
3771 }
3772 }
3773 }
3774
3775 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3776 struct si_shader *shader,
3777 uint64_t scratch_va)
3778 {
3779 unsigned i;
3780 uint32_t scratch_rsrc_dword0 = scratch_va;
3781 uint32_t scratch_rsrc_dword1 =
3782 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3783 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3784
3785 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3786 const struct radeon_shader_reloc *reloc =
3787 &shader->binary.relocs[i];
3788 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3789 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3790 &scratch_rsrc_dword0, 4);
3791 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3792 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3793 &scratch_rsrc_dword1, 4);
3794 }
3795 }
3796 }
3797
3798 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3799 {
3800 const struct radeon_shader_binary *binary = &shader->binary;
3801 unsigned code_size = binary->code_size + binary->rodata_size;
3802 unsigned char *ptr;
3803
3804 r600_resource_reference(&shader->bo, NULL);
3805 shader->bo = si_resource_create_custom(&sscreen->b.b,
3806 PIPE_USAGE_IMMUTABLE,
3807 code_size);
3808 if (!shader->bo)
3809 return -ENOMEM;
3810
3811 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3812 PIPE_TRANSFER_READ_WRITE);
3813 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3814 if (binary->rodata_size > 0) {
3815 ptr += binary->code_size;
3816 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3817 binary->rodata_size);
3818 }
3819
3820 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3821 return 0;
3822 }
3823
3824 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3825 {
3826 const struct radeon_shader_binary *binary = &shader->binary;
3827 unsigned i;
3828 int r;
3829 bool dump = r600_can_dump_shader(&sscreen->b,
3830 shader->selector ? shader->selector->tokens : NULL);
3831
3832 si_shader_binary_read_config(sscreen, shader, 0);
3833 r = si_shader_binary_upload(sscreen, shader);
3834 if (r)
3835 return r;
3836
3837 if (dump) {
3838 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3839 if (binary->disasm_string) {
3840 fprintf(stderr, "\nShader Disassembly:\n\n");
3841 fprintf(stderr, "%s\n", binary->disasm_string);
3842 } else {
3843 fprintf(stderr, "SI CODE:\n");
3844 for (i = 0; i < binary->code_size; i+=4 ) {
3845 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3846 binary->code[i + 2], binary->code[i + 1],
3847 binary->code[i]);
3848 }
3849 }
3850 }
3851
3852 fprintf(stderr, "*** SHADER STATS ***\n"
3853 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3854 "Scratch: %d bytes per wave\n********************\n",
3855 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3856 shader->lds_size, shader->scratch_bytes_per_wave);
3857 }
3858 return 0;
3859 }
3860
3861 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3862 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3863 {
3864 int r = 0;
3865 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3866 shader->selector ? shader->selector->tokens : NULL);
3867 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3868
3869 r = radeon_llvm_compile(mod, &shader->binary,
3870 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3871 if (r)
3872 return r;
3873
3874 r = si_shader_binary_read(sscreen, shader);
3875
3876 FREE(shader->binary.config);
3877 FREE(shader->binary.rodata);
3878 FREE(shader->binary.global_symbol_offsets);
3879 if (shader->scratch_bytes_per_wave == 0) {
3880 FREE(shader->binary.code);
3881 FREE(shader->binary.relocs);
3882 memset(&shader->binary, 0,
3883 offsetof(struct radeon_shader_binary, disasm_string));
3884 }
3885 return r;
3886 }
3887
3888 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3889 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3890 struct si_shader_context *si_shader_ctx,
3891 struct si_shader *gs, bool dump)
3892 {
3893 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3894 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3895 struct lp_build_context *base = &bld_base->base;
3896 struct lp_build_context *uint = &bld_base->uint_bld;
3897 struct si_shader *shader = si_shader_ctx->shader;
3898 struct si_shader_output_values *outputs;
3899 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3900 LLVMValueRef args[9];
3901 int i, r;
3902
3903 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3904
3905 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3906 shader->is_gs_copy_shader = true;
3907
3908 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3909
3910 create_meta_data(si_shader_ctx);
3911 create_function(si_shader_ctx);
3912 preload_streamout_buffers(si_shader_ctx);
3913 preload_ring_buffers(si_shader_ctx);
3914
3915 args[0] = si_shader_ctx->gsvs_ring[0];
3916 args[1] = lp_build_mul_imm(uint,
3917 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3918 si_shader_ctx->param_vertex_id),
3919 4);
3920 args[3] = uint->zero;
3921 args[4] = uint->one; /* OFFEN */
3922 args[5] = uint->zero; /* IDXEN */
3923 args[6] = uint->one; /* GLC */
3924 args[7] = uint->one; /* SLC */
3925 args[8] = uint->zero; /* TFE */
3926
3927 /* Fetch vertex data from GSVS ring */
3928 for (i = 0; i < gsinfo->num_outputs; ++i) {
3929 unsigned chan;
3930
3931 outputs[i].name = gsinfo->output_semantic_name[i];
3932 outputs[i].sid = gsinfo->output_semantic_index[i];
3933
3934 for (chan = 0; chan < 4; chan++) {
3935 args[2] = lp_build_const_int32(gallivm,
3936 (i * 4 + chan) *
3937 gs->selector->gs_max_out_vertices * 16 * 4);
3938
3939 outputs[i].values[chan] =
3940 LLVMBuildBitCast(gallivm->builder,
3941 lp_build_intrinsic(gallivm->builder,
3942 "llvm.SI.buffer.load.dword.i32.i32",
3943 LLVMInt32TypeInContext(gallivm->context),
3944 args, 9,
3945 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3946 base->elem_type, "");
3947 }
3948 }
3949
3950 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3951
3952 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3953
3954 if (dump)
3955 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3956
3957 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3958 si_shader_ctx->tm, bld_base->base.gallivm->module);
3959
3960 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
3961
3962 FREE(outputs);
3963 return r;
3964 }
3965
3966 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
3967 {
3968 int i;
3969
3970 fprintf(f, "SHADER KEY\n");
3971
3972 switch (shader) {
3973 case PIPE_SHADER_VERTEX:
3974 fprintf(f, " instance_divisors = {");
3975 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
3976 fprintf(f, !i ? "%u" : ", %u",
3977 key->vs.instance_divisors[i]);
3978 fprintf(f, "}\n");
3979
3980 if (key->vs.as_es)
3981 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3982 key->vs.es_enabled_outputs);
3983 fprintf(f, " as_es = %u\n", key->vs.as_es);
3984 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
3985 break;
3986
3987 case PIPE_SHADER_TESS_CTRL:
3988 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
3989 break;
3990
3991 case PIPE_SHADER_TESS_EVAL:
3992 if (key->tes.as_es)
3993 fprintf(f, " es_enabled_outputs = 0x%"PRIx64"\n",
3994 key->tes.es_enabled_outputs);
3995 fprintf(f, " as_es = %u\n", key->tes.as_es);
3996 break;
3997
3998 case PIPE_SHADER_GEOMETRY:
3999 break;
4000
4001 case PIPE_SHADER_FRAGMENT:
4002 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4003 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4004 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4005 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4006 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4007 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4008 break;
4009
4010 default:
4011 assert(0);
4012 }
4013 }
4014
4015 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4016 struct si_shader *shader)
4017 {
4018 struct si_shader_selector *sel = shader->selector;
4019 struct tgsi_token *tokens = sel->tokens;
4020 struct si_shader_context si_shader_ctx;
4021 struct lp_build_tgsi_context * bld_base;
4022 struct tgsi_shader_info stipple_shader_info;
4023 LLVMModuleRef mod;
4024 int r = 0;
4025 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4026 shader->key.ps.poly_stipple;
4027 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
4028
4029 if (poly_stipple) {
4030 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4031 SI_POLY_STIPPLE_SAMPLER);
4032 tgsi_scan_shader(tokens, &stipple_shader_info);
4033 }
4034
4035 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4036 * conversion fails. */
4037 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4038 si_dump_shader_key(sel->type, &shader->key, stderr);
4039 tgsi_dump(tokens, 0);
4040 si_dump_streamout(&sel->so);
4041 }
4042
4043 assert(shader->nparam == 0);
4044
4045 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4046 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4047 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4048
4049 if (sel->type != PIPE_SHADER_COMPUTE)
4050 shader->dx10_clamp_mode = true;
4051
4052 if (sel->info.uses_kill)
4053 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4054
4055 shader->uses_instanceid = sel->info.uses_instanceid;
4056 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4057 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4058
4059 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4060 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4061 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4062
4063 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4064 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4065 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4066 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4067 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4068 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4069 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4070 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4071 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4072 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4073 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4074 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4075 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4076
4077 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4078 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4079 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4080 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4081
4082 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4083 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4084 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4085
4086 if (HAVE_LLVM >= 0x0306) {
4087 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4088 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4089 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4090 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4091 }
4092
4093 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4094 si_shader_ctx.shader = shader;
4095 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4096 si_shader_ctx.screen = sscreen;
4097 si_shader_ctx.tm = tm;
4098
4099 switch (si_shader_ctx.type) {
4100 case TGSI_PROCESSOR_VERTEX:
4101 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4102 if (shader->key.vs.as_ls)
4103 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4104 else if (shader->key.vs.as_es)
4105 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4106 else
4107 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4108 break;
4109 case TGSI_PROCESSOR_TESS_CTRL:
4110 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4111 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4112 bld_base->emit_store = store_output_tcs;
4113 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4114 break;
4115 case TGSI_PROCESSOR_TESS_EVAL:
4116 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4117 if (shader->key.tes.as_es)
4118 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4119 else
4120 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4121 break;
4122 case TGSI_PROCESSOR_GEOMETRY:
4123 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4124 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4125 break;
4126 case TGSI_PROCESSOR_FRAGMENT:
4127 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4128 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4129
4130 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4131 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4132 shader->db_shader_control |=
4133 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4134 break;
4135 case TGSI_FS_DEPTH_LAYOUT_LESS:
4136 shader->db_shader_control |=
4137 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4138 break;
4139 }
4140 break;
4141 default:
4142 assert(!"Unsupported shader type");
4143 return -1;
4144 }
4145
4146 create_meta_data(&si_shader_ctx);
4147 create_function(&si_shader_ctx);
4148 preload_constants(&si_shader_ctx);
4149 preload_samplers(&si_shader_ctx);
4150 preload_streamout_buffers(&si_shader_ctx);
4151 preload_ring_buffers(&si_shader_ctx);
4152
4153 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4154 int i;
4155 for (i = 0; i < 4; i++) {
4156 si_shader_ctx.gs_next_vertex[i] =
4157 lp_build_alloca(bld_base->base.gallivm,
4158 bld_base->uint_bld.elem_type, "");
4159 }
4160 }
4161
4162 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4163 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4164 goto out;
4165 }
4166
4167 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4168
4169 mod = bld_base->base.gallivm->module;
4170 r = si_compile_llvm(sscreen, shader, tm, mod);
4171 if (r) {
4172 fprintf(stderr, "LLVM failed to compile shader\n");
4173 goto out;
4174 }
4175
4176 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4177
4178 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4179 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4180 shader->gs_copy_shader->selector = shader->selector;
4181 shader->gs_copy_shader->key = shader->key;
4182 si_shader_ctx.shader = shader->gs_copy_shader;
4183 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4184 shader, dump))) {
4185 free(shader->gs_copy_shader);
4186 shader->gs_copy_shader = NULL;
4187 goto out;
4188 }
4189 }
4190
4191 out:
4192 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4193 FREE(si_shader_ctx.constants[i]);
4194 if (poly_stipple)
4195 tgsi_free_tokens(tokens);
4196 return r;
4197 }
4198
4199 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
4200 {
4201 if (shader->gs_copy_shader)
4202 si_shader_destroy(ctx, shader->gs_copy_shader);
4203
4204 if (shader->scratch_bo)
4205 r600_resource_reference(&shader->scratch_bo, NULL);
4206
4207 r600_resource_reference(&shader->bo, NULL);
4208
4209 FREE(shader->binary.code);
4210 FREE(shader->binary.relocs);
4211 FREE(shader->binary.disasm_string);
4212 }